drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *match_clock,
  87                     intel_clock_t *best_clock);
  88 static bool
  89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  90                         int target, int refclk, intel_clock_t *match_clock,
  91                         intel_clock_t *best_clock);
  92
  93 static bool
  94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                       int target, int refclk, intel_clock_t *match_clock,
  96                       intel_clock_t *best_clock);
  97 static bool
  98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  99                            int target, int refclk, intel_clock_t *match_clock,
 100                            intel_clock_t *best_clock);
 101
 102 static inline u32 /* units of 100MHz */
 103 intel_fdi_link_freq(struct drm_device *dev)
 104 {
 105         if (IS_GEN5(dev)) {
 106                 struct drm_i915_private *dev_priv = dev->dev_private;
 107                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 108         } else
 109                 return 27;
 110 }
 111
 112 static const intel_limit_t intel_limits_i8xx_dvo = {
 113         .dot = { .min = 25000, .max = 350000 },
 114         .vco = { .min = 930000, .max = 1400000 },
 115         .n = { .min = 3, .max = 16 },
 116         .m = { .min = 96, .max = 140 },
 117         .m1 = { .min = 18, .max = 26 },
 118         .m2 = { .min = 6, .max = 16 },
 119         .p = { .min = 4, .max = 128 },
 120         .p1 = { .min = 2, .max = 33 },
 121         .p2 = { .dot_limit = 165000,
 122                 .p2_slow = 4, .p2_fast = 2 },
 123         .find_pll = intel_find_best_PLL,
 124 };
 125
 126 static const intel_limit_t intel_limits_i8xx_lvds = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 1, .max = 6 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i9xx_sdvo = {
 141         .dot = { .min = 20000, .max = 400000 },
 142         .vco = { .min = 1400000, .max = 2800000 },
 143         .n = { .min = 1, .max = 6 },
 144         .m = { .min = 70, .max = 120 },
 145         .m1 = { .min = 10, .max = 22 },
 146         .m2 = { .min = 5, .max = 9 },
 147         .p = { .min = 5, .max = 80 },
 148         .p1 = { .min = 1, .max = 8 },
 149         .p2 = { .dot_limit = 200000,
 150                 .p2_slow = 10, .p2_fast = 5 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_lvds = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 7, .max = 98 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 112000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168
 169 static const intel_limit_t intel_limits_g4x_sdvo = {
 170         .dot = { .min = 25000, .max = 270000 },
 171         .vco = { .min = 1750000, .max = 3500000},
 172         .n = { .min = 1, .max = 4 },
 173         .m = { .min = 104, .max = 138 },
 174         .m1 = { .min = 17, .max = 23 },
 175         .m2 = { .min = 5, .max = 11 },
 176         .p = { .min = 10, .max = 30 },
 177         .p1 = { .min = 1, .max = 3},
 178         .p2 = { .dot_limit = 270000,
 179                 .p2_slow = 10,
 180                 .p2_fast = 10
 181         },
 182         .find_pll = intel_g4x_find_best_PLL,
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_hdmi = {
 186         .dot = { .min = 22000, .max = 400000 },
 187         .vco = { .min = 1750000, .max = 3500000},
 188         .n = { .min = 1, .max = 4 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 16, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 5, .max = 80 },
 193         .p1 = { .min = 1, .max = 8},
 194         .p2 = { .dot_limit = 165000,
 195                 .p2_slow = 10, .p2_fast = 5 },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 200         .dot = { .min = 20000, .max = 115000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 28, .max = 112 },
 207         .p1 = { .min = 2, .max = 8 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 14, .p2_fast = 14
 210         },
 211         .find_pll = intel_g4x_find_best_PLL,
 212 };
 213
 214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 215         .dot = { .min = 80000, .max = 224000 },
 216         .vco = { .min = 1750000, .max = 3500000 },
 217         .n = { .min = 1, .max = 3 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 14, .max = 42 },
 222         .p1 = { .min = 2, .max = 6 },
 223         .p2 = { .dot_limit = 0,
 224                 .p2_slow = 7, .p2_fast = 7
 225         },
 226         .find_pll = intel_g4x_find_best_PLL,
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_display_port = {
 230         .dot = { .min = 161670, .max = 227000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 2 },
 233         .m = { .min = 97, .max = 108 },
 234         .m1 = { .min = 0x10, .max = 0x12 },
 235         .m2 = { .min = 0x05, .max = 0x06 },
 236         .p = { .min = 10, .max = 20 },
 237         .p1 = { .min = 1, .max = 2},
 238         .p2 = { .dot_limit = 0,
 239                 .p2_slow = 10, .p2_fast = 10 },
 240         .find_pll = intel_find_pll_g4x_dp,
 241 };
 242
 243 static const intel_limit_t intel_limits_pineview_sdvo = {
 244         .dot = { .min = 20000, .max = 400000},
 245         .vco = { .min = 1700000, .max = 3500000 },
 246         /* Pineview's Ncounter is a ring counter */
 247         .n = { .min = 3, .max = 6 },
 248         .m = { .min = 2, .max = 256 },
 249         /* Pineview only has one combined m divider, which we treat as m2. */
 250         .m1 = { .min = 0, .max = 0 },
 251         .m2 = { .min = 0, .max = 254 },
 252         .p = { .min = 5, .max = 80 },
 253         .p1 = { .min = 1, .max = 8 },
 254         .p2 = { .dot_limit = 200000,
 255                 .p2_slow = 10, .p2_fast = 5 },
 256         .find_pll = intel_find_best_PLL,
 257 };
 258
 259 static const intel_limit_t intel_limits_pineview_lvds = {
 260         .dot = { .min = 20000, .max = 400000 },
 261         .vco = { .min = 1700000, .max = 3500000 },
 262         .n = { .min = 3, .max = 6 },
 263         .m = { .min = 2, .max = 256 },
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 7, .max = 112 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 112000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 /* Ironlake / Sandybridge
 274  *
 275  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 276  * the range value for them is (actual_value - 2).
 277  */
 278 static const intel_limit_t intel_limits_ironlake_dac = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 5 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 5, .max = 80 },
 286         .p1 = { .min = 1, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 10, .p2_fast = 5 },
 289         .find_pll = intel_g4x_find_best_PLL,
 290 };
 291
 292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 3 },
 296         .m = { .min = 79, .max = 118 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 14, .max = 56 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 7, .p2_fast = 7 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 /* LVDS 100mhz refclk limits. */
 321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 322         .dot = { .min = 25000, .max = 350000 },
 323         .vco = { .min = 1760000, .max = 3510000 },
 324         .n = { .min = 1, .max = 2 },
 325         .m = { .min = 79, .max = 126 },
 326         .m1 = { .min = 12, .max = 22 },
 327         .m2 = { .min = 5, .max = 9 },
 328         .p = { .min = 28, .max = 112 },
 329         .p1 = { .min = 2, .max = 8 },
 330         .p2 = { .dot_limit = 225000,
 331                 .p2_slow = 14, .p2_fast = 14 },
 332         .find_pll = intel_g4x_find_best_PLL,
 333 };
 334
 335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 3 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 14, .max = 42 },
 343         .p1 = { .min = 2, .max = 6 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 7, .p2_fast = 7 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_display_port = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000},
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 81, .max = 90 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 10, .max = 20 },
 357         .p1 = { .min = 1, .max = 2},
 358         .p2 = { .dot_limit = 0,
 359                 .p2_slow = 10, .p2_fast = 10 },
 360         .find_pll = intel_find_pll_ironlake_dp,
 361 };
 362
 363 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 364                               unsigned int reg)
 365 {
 366         unsigned int val;
 367
 368         /* use the module option value if specified */
 369         if (i915_lvds_channel_mode > 0)
 370                 return i915_lvds_channel_mode == 2;
 371
 372         if (dev_priv->lvds_val)
 373                 val = dev_priv->lvds_val;
 374         else {
 375                 /* BIOS should set the proper LVDS register value at boot, but
 376                  * in reality, it doesn't set the value when the lid is closed;
 377                  * we need to check "the value to be set" in VBT when LVDS
 378                  * register is uninitialized.
 379                  */
 380                 val = I915_READ(reg);
 381                 if (!(val & ~LVDS_DETECTED))
 382                         val = dev_priv->bios_lvds_val;
 383                 dev_priv->lvds_val = val;
 384         }
 385         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 386 }
 387
 388 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 389                                                 int refclk)
 390 {
 391         struct drm_device *dev = crtc->dev;
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         const intel_limit_t *limit;
 394
 395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 396                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 397                         /* LVDS dual channel */
 398                         if (refclk == 100000)
 399                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 400                         else
 401                                 limit = &intel_limits_ironlake_dual_lvds;
 402                 } else {
 403                         if (refclk == 100000)
 404                                 limit = &intel_limits_ironlake_single_lvds_100m;
 405                         else
 406                                 limit = &intel_limits_ironlake_single_lvds;
 407                 }
 408         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 409                         HAS_eDP)
 410                 limit = &intel_limits_ironlake_display_port;
 411         else
 412                 limit = &intel_limits_ironlake_dac;
 413
 414         return limit;
 415 }
 416
 417 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 418 {
 419         struct drm_device *dev = crtc->dev;
 420         struct drm_i915_private *dev_priv = dev->dev_private;
 421         const intel_limit_t *limit;
 422
 423         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 424                 if (is_dual_link_lvds(dev_priv, LVDS))
 425                         /* LVDS with dual channel */
 426                         limit = &intel_limits_g4x_dual_channel_lvds;
 427                 else
 428                         /* LVDS with dual channel */
 429                         limit = &intel_limits_g4x_single_channel_lvds;
 430         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 431                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 432                 limit = &intel_limits_g4x_hdmi;
 433         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 434                 limit = &intel_limits_g4x_sdvo;
 435         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 436                 limit = &intel_limits_g4x_display_port;
 437         } else /* The option is for other outputs */
 438                 limit = &intel_limits_i9xx_sdvo;
 439
 440         return limit;
 441 }
 442
 443 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 444 {
 445         struct drm_device *dev = crtc->dev;
 446         const intel_limit_t *limit;
 447
 448         if (HAS_PCH_SPLIT(dev))
 449                 limit = intel_ironlake_limit(crtc, refclk);
 450         else if (IS_G4X(dev)) {
 451                 limit = intel_g4x_limit(crtc);
 452         } else if (IS_PINEVIEW(dev)) {
 453                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 454                         limit = &intel_limits_pineview_lvds;
 455                 else
 456                         limit = &intel_limits_pineview_sdvo;
 457         } else if (!IS_GEN2(dev)) {
 458                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 459                         limit = &intel_limits_i9xx_lvds;
 460                 else
 461                         limit = &intel_limits_i9xx_sdvo;
 462         } else {
 463                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 464                         limit = &intel_limits_i8xx_lvds;
 465                 else
 466                         limit = &intel_limits_i8xx_dvo;
 467         }
 468         return limit;
 469 }
 470
 471 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 472 static void pineview_clock(int refclk, intel_clock_t *clock)
 473 {
 474         clock->m = clock->m2 + 2;
 475         clock->p = clock->p1 * clock->p2;
 476         clock->vco = refclk * clock->m / clock->n;
 477         clock->dot = clock->vco / clock->p;
 478 }
 479
 480 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 481 {
 482         if (IS_PINEVIEW(dev)) {
 483                 pineview_clock(refclk, clock);
 484                 return;
 485         }
 486         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 487         clock->p = clock->p1 * clock->p2;
 488         clock->vco = refclk * clock->m / (clock->n + 2);
 489         clock->dot = clock->vco / clock->p;
 490 }
 491
 492 /**
 493  * Returns whether any output on the specified pipe is of the specified type
 494  */
 495 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 496 {
 497         struct drm_device *dev = crtc->dev;
 498         struct drm_mode_config *mode_config = &dev->mode_config;
 499         struct intel_encoder *encoder;
 500
 501         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 502                 if (encoder->base.crtc == crtc && encoder->type == type)
 503                         return true;
 504
 505         return false;
 506 }
 507
 508 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 509 /**
 510  * Returns whether the given set of divisors are valid for a given refclk with
 511  * the given connectors.
 512  */
 513
 514 static bool intel_PLL_is_valid(struct drm_device *dev,
 515                                const intel_limit_t *limit,
 516                                const intel_clock_t *clock)
 517 {
 518         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 519                 INTELPllInvalid("p1 out of range\n");
 520         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 521                 INTELPllInvalid("p out of range\n");
 522         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 523                 INTELPllInvalid("m2 out of range\n");
 524         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 525                 INTELPllInvalid("m1 out of range\n");
 526         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 527                 INTELPllInvalid("m1 <= m2\n");
 528         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 529                 INTELPllInvalid("m out of range\n");
 530         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 531                 INTELPllInvalid("n out of range\n");
 532         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 533                 INTELPllInvalid("vco out of range\n");
 534         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 535          * connector, etc., rather than just a single range.
 536          */
 537         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 538                 INTELPllInvalid("dot out of range\n");
 539
 540         return true;
 541 }
 542
 543 static bool
 544 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 545                     int target, int refclk, intel_clock_t *match_clock,
 546                     intel_clock_t *best_clock)
 547
 548 {
 549         struct drm_device *dev = crtc->dev;
 550         struct drm_i915_private *dev_priv = dev->dev_private;
 551         intel_clock_t clock;
 552         int err = target;
 553
 554         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 555             (I915_READ(LVDS)) != 0) {
 556                 /*
 557                  * For LVDS, if the panel is on, just rely on its current
 558                  * settings for dual-channel.  We haven't figured out how to
 559                  * reliably set up different single/dual channel state, if we
 560                  * even can.
 561                  */
 562                 if (is_dual_link_lvds(dev_priv, LVDS))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         /* m1 is always 0 in Pineview */
 580                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 581                                 break;
 582                         for (clock.n = limit->n.min;
 583                              clock.n <= limit->n.max; clock.n++) {
 584                                 for (clock.p1 = limit->p1.min;
 585                                         clock.p1 <= limit->p1.max; clock.p1++) {
 586                                         int this_err;
 587
 588                                         intel_clock(dev, refclk, &clock);
 589                                         if (!intel_PLL_is_valid(dev, limit,
 590                                                                 &clock))
 591                                                 continue;
 592                                         if (match_clock &&
 593                                             clock.p != match_clock->p)
 594                                                 continue;
 595
 596                                         this_err = abs(clock.dot - target);
 597                                         if (this_err < err) {
 598                                                 *best_clock = clock;
 599                                                 err = this_err;
 600                                         }
 601                                 }
 602                         }
 603                 }
 604         }
 605
 606         return (err != target);
 607 }
 608
 609 static bool
 610 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 611                         int target, int refclk, intel_clock_t *match_clock,
 612                         intel_clock_t *best_clock)
 613 {
 614         struct drm_device *dev = crtc->dev;
 615         struct drm_i915_private *dev_priv = dev->dev_private;
 616         intel_clock_t clock;
 617         int max_n;
 618         bool found;
 619         /* approximately equals target * 0.00585 */
 620         int err_most = (target >> 8) + (target >> 9);
 621         found = false;
 622
 623         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 624                 int lvds_reg;
 625
 626                 if (HAS_PCH_SPLIT(dev))
 627                         lvds_reg = PCH_LVDS;
 628                 else
 629                         lvds_reg = LVDS;
 630                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 631                     LVDS_CLKB_POWER_UP)
 632                         clock.p2 = limit->p2.p2_fast;
 633                 else
 634                         clock.p2 = limit->p2.p2_slow;
 635         } else {
 636                 if (target < limit->p2.dot_limit)
 637                         clock.p2 = limit->p2.p2_slow;
 638                 else
 639                         clock.p2 = limit->p2.p2_fast;
 640         }
 641
 642         memset(best_clock, 0, sizeof(*best_clock));
 643         max_n = limit->n.max;
 644         /* based on hardware requirement, prefer smaller n to precision */
 645         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 646                 /* based on hardware requirement, prefere larger m1,m2 */
 647                 for (clock.m1 = limit->m1.max;
 648                      clock.m1 >= limit->m1.min; clock.m1--) {
 649                         for (clock.m2 = limit->m2.max;
 650                              clock.m2 >= limit->m2.min; clock.m2--) {
 651                                 for (clock.p1 = limit->p1.max;
 652                                      clock.p1 >= limit->p1.min; clock.p1--) {
 653                                         int this_err;
 654
 655                                         intel_clock(dev, refclk, &clock);
 656                                         if (!intel_PLL_is_valid(dev, limit,
 657                                                                 &clock))
 658                                                 continue;
 659                                         if (match_clock &&
 660                                             clock.p != match_clock->p)
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err_most) {
 665                                                 *best_clock = clock;
 666                                                 err_most = this_err;
 667                                                 max_n = clock.n;
 668                                                 found = true;
 669                                         }
 670                                 }
 671                         }
 672                 }
 673         }
 674         return found;
 675 }
 676
 677 static bool
 678 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                            int target, int refclk, intel_clock_t *match_clock,
 680                            intel_clock_t *best_clock)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         intel_clock_t clock;
 684
 685         if (target < 200000) {
 686                 clock.n = 1;
 687                 clock.p1 = 2;
 688                 clock.p2 = 10;
 689                 clock.m1 = 12;
 690                 clock.m2 = 9;
 691         } else {
 692                 clock.n = 2;
 693                 clock.p1 = 1;
 694                 clock.p2 = 10;
 695                 clock.m1 = 14;
 696                 clock.m2 = 8;
 697         }
 698         intel_clock(dev, refclk, &clock);
 699         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 700         return true;
 701 }
 702
 703 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 704 static bool
 705 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 706                       int target, int refclk, intel_clock_t *match_clock,
 707                       intel_clock_t *best_clock)
 708 {
 709         intel_clock_t clock;
 710         if (target < 200000) {
 711                 clock.p1 = 2;
 712                 clock.p2 = 10;
 713                 clock.n = 2;
 714                 clock.m1 = 23;
 715                 clock.m2 = 8;
 716         } else {
 717                 clock.p1 = 1;
 718                 clock.p2 = 10;
 719                 clock.n = 1;
 720                 clock.m1 = 14;
 721                 clock.m2 = 2;
 722         }
 723         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 724         clock.p = (clock.p1 * clock.p2);
 725         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 726         clock.vco = 0;
 727         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 728         return true;
 729 }
 730
 731 /**
 732  * intel_wait_for_vblank - wait for vblank on a given pipe
 733  * @dev: drm device
 734  * @pipe: pipe to wait for
 735  *
 736  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 737  * mode setting code.
 738  */
 739 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 740 {
 741         struct drm_i915_private *dev_priv = dev->dev_private;
 742         int pipestat_reg = PIPESTAT(pipe);
 743
 744         /* Clear existing vblank status. Note this will clear any other
 745          * sticky status fields as well.
 746          *
 747          * This races with i915_driver_irq_handler() with the result
 748          * that either function could miss a vblank event.  Here it is not
 749          * fatal, as we will either wait upon the next vblank interrupt or
 750          * timeout.  Generally speaking intel_wait_for_vblank() is only
 751          * called during modeset at which time the GPU should be idle and
 752          * should *not* be performing page flips and thus not waiting on
 753          * vblanks...
 754          * Currently, the result of us stealing a vblank from the irq
 755          * handler is that a single frame will be skipped during swapbuffers.
 756          */
 757         I915_WRITE(pipestat_reg,
 758                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 759
 760         /* Wait for vblank interrupt bit to set */
 761         if (wait_for(I915_READ(pipestat_reg) &
 762                      PIPE_VBLANK_INTERRUPT_STATUS,
 763                      50))
 764                 DRM_DEBUG_KMS("vblank wait timed out\n");
 765 }
 766
 767 /*
 768  * intel_wait_for_pipe_off - wait for pipe to turn off
 769  * @dev: drm device
 770  * @pipe: pipe to wait for
 771  *
 772  * After disabling a pipe, we can't wait for vblank in the usual way,
 773  * spinning on the vblank interrupt status bit, since we won't actually
 774  * see an interrupt when the pipe is disabled.
 775  *
 776  * On Gen4 and above:
 777  *   wait for the pipe register state bit to turn off
 778  *
 779  * Otherwise:
 780  *   wait for the display line value to settle (it usually
 781  *   ends up stopping at the start of the next frame).
 782  *
 783  */
 784 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 785 {
 786         struct drm_i915_private *dev_priv = dev->dev_private;
 787
 788         if (INTEL_INFO(dev)->gen >= 4) {
 789                 int reg = PIPECONF(pipe);
 790
 791                 /* Wait for the Pipe State to go off */
 792                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 793                              100))
 794                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 795         } else {
 796                 u32 last_line;
 797                 int reg = PIPEDSL(pipe);
 798                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 799
 800                 /* Wait for the display line to settle */
 801                 do {
 802                         last_line = I915_READ(reg) & DSL_LINEMASK;
 803                         mdelay(5);
 804                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 805                          time_after(timeout, jiffies));
 806                 if (time_after(jiffies, timeout))
 807                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 808         }
 809 }
 810
 811 static const char *state_string(bool enabled)
 812 {
 813         return enabled ? "on" : "off";
 814 }
 815
 816 /* Only for pre-ILK configs */
 817 static void assert_pll(struct drm_i915_private *dev_priv,
 818                        enum pipe pipe, bool state)
 819 {
 820         int reg;
 821         u32 val;
 822         bool cur_state;
 823
 824         reg = DPLL(pipe);
 825         val = I915_READ(reg);
 826         cur_state = !!(val & DPLL_VCO_ENABLE);
 827         WARN(cur_state != state,
 828              "PLL state assertion failure (expected %s, current %s)\n",
 829              state_string(state), state_string(cur_state));
 830 }
 831 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 832 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 833
 834 /* For ILK+ */
 835 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 836                            enum pipe pipe, bool state)
 837 {
 838         int reg;
 839         u32 val;
 840         bool cur_state;
 841
 842         if (HAS_PCH_CPT(dev_priv->dev)) {
 843                 u32 pch_dpll;
 844
 845                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 846
 847                 /* Make sure the selected PLL is enabled to the transcoder */
 848                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 849                      "transcoder %d PLL not enabled\n", pipe);
 850
 851                 /* Convert the transcoder pipe number to a pll pipe number */
 852                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 853         }
 854
 855         reg = PCH_DPLL(pipe);
 856         val = I915_READ(reg);
 857         cur_state = !!(val & DPLL_VCO_ENABLE);
 858         WARN(cur_state != state,
 859              "PCH PLL state assertion failure (expected %s, current %s)\n",
 860              state_string(state), state_string(cur_state));
 861 }
 862 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 863 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 864
 865 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 866                           enum pipe pipe, bool state)
 867 {
 868         int reg;
 869         u32 val;
 870         bool cur_state;
 871
 872         reg = FDI_TX_CTL(pipe);
 873         val = I915_READ(reg);
 874         cur_state = !!(val & FDI_TX_ENABLE);
 875         WARN(cur_state != state,
 876              "FDI TX state assertion failure (expected %s, current %s)\n",
 877              state_string(state), state_string(cur_state));
 878 }
 879 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 880 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 881
 882 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 883                           enum pipe pipe, bool state)
 884 {
 885         int reg;
 886         u32 val;
 887         bool cur_state;
 888
 889         reg = FDI_RX_CTL(pipe);
 890         val = I915_READ(reg);
 891         cur_state = !!(val & FDI_RX_ENABLE);
 892         WARN(cur_state != state,
 893              "FDI RX state assertion failure (expected %s, current %s)\n",
 894              state_string(state), state_string(cur_state));
 895 }
 896 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 897 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 898
 899 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 900                                       enum pipe pipe)
 901 {
 902         int reg;
 903         u32 val;
 904
 905         /* ILK FDI PLL is always enabled */
 906         if (dev_priv->info->gen == 5)
 907                 return;
 908
 909         reg = FDI_TX_CTL(pipe);
 910         val = I915_READ(reg);
 911         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 912 }
 913
 914 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 915                                       enum pipe pipe)
 916 {
 917         int reg;
 918         u32 val;
 919
 920         reg = FDI_RX_CTL(pipe);
 921         val = I915_READ(reg);
 922         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 923 }
 924
 925 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 926                                   enum pipe pipe)
 927 {
 928         int pp_reg, lvds_reg;
 929         u32 val;
 930         enum pipe panel_pipe = PIPE_A;
 931         bool locked = true;
 932
 933         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 934                 pp_reg = PCH_PP_CONTROL;
 935                 lvds_reg = PCH_LVDS;
 936         } else {
 937                 pp_reg = PP_CONTROL;
 938                 lvds_reg = LVDS;
 939         }
 940
 941         val = I915_READ(pp_reg);
 942         if (!(val & PANEL_POWER_ON) ||
 943             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 944                 locked = false;
 945
 946         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 947                 panel_pipe = PIPE_B;
 948
 949         WARN(panel_pipe == pipe && locked,
 950              "panel assertion failure, pipe %c regs locked\n",
 951              pipe_name(pipe));
 952 }
 953
 954 void assert_pipe(struct drm_i915_private *dev_priv,
 955                  enum pipe pipe, bool state)
 956 {
 957         int reg;
 958         u32 val;
 959         bool cur_state;
 960
 961         /* if we need the pipe A quirk it must be always on */
 962         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
 963                 state = true;
 964
 965         reg = PIPECONF(pipe);
 966         val = I915_READ(reg);
 967         cur_state = !!(val & PIPECONF_ENABLE);
 968         WARN(cur_state != state,
 969              "pipe %c assertion failure (expected %s, current %s)\n",
 970              pipe_name(pipe), state_string(state), state_string(cur_state));
 971 }
 972
 973 static void assert_plane(struct drm_i915_private *dev_priv,
 974                          enum plane plane, bool state)
 975 {
 976         int reg;
 977         u32 val;
 978         bool cur_state;
 979
 980         reg = DSPCNTR(plane);
 981         val = I915_READ(reg);
 982         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
 983         WARN(cur_state != state,
 984              "plane %c assertion failure (expected %s, current %s)\n",
 985              plane_name(plane), state_string(state), state_string(cur_state));
 986 }
 987
 988 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
 989 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
 990
 991 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 992                                    enum pipe pipe)
 993 {
 994         int reg, i;
 995         u32 val;
 996         int cur_pipe;
 997
 998         /* Planes are fixed to pipes on ILK+ */
 999         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1000                 reg = DSPCNTR(pipe);
1001                 val = I915_READ(reg);
1002                 WARN((val & DISPLAY_PLANE_ENABLE),
1003                      "plane %c assertion failure, should be disabled but not\n",
1004                      plane_name(pipe));
1005                 return;
1006         }
1007
1008         /* Need to check both planes against the pipe */
1009         for (i = 0; i < 2; i++) {
1010                 reg = DSPCNTR(i);
1011                 val = I915_READ(reg);
1012                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1013                         DISPPLANE_SEL_PIPE_SHIFT;
1014                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1015                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1016                      plane_name(i), pipe_name(pipe));
1017         }
1018 }
1019
1020 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1021 {
1022         u32 val;
1023         bool enabled;
1024
1025         val = I915_READ(PCH_DREF_CONTROL);
1026         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1027                             DREF_SUPERSPREAD_SOURCE_MASK));
1028         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1029 }
1030
1031 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1032                                        enum pipe pipe)
1033 {
1034         int reg;
1035         u32 val;
1036         bool enabled;
1037
1038         reg = TRANSCONF(pipe);
1039         val = I915_READ(reg);
1040         enabled = !!(val & TRANS_ENABLE);
1041         WARN(enabled,
1042              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1043              pipe_name(pipe));
1044 }
1045
1046 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1047                             enum pipe pipe, u32 port_sel, u32 val)
1048 {
1049         if ((val & DP_PORT_EN) == 0)
1050                 return false;
1051
1052         if (HAS_PCH_CPT(dev_priv->dev)) {
1053                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1054                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1055                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1056                         return false;
1057         } else {
1058                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1059                         return false;
1060         }
1061         return true;
1062 }
1063
1064 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1065                               enum pipe pipe, u32 val)
1066 {
1067         if ((val & PORT_ENABLE) == 0)
1068                 return false;
1069
1070         if (HAS_PCH_CPT(dev_priv->dev)) {
1071                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1072                         return false;
1073         } else {
1074                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1075                         return false;
1076         }
1077         return true;
1078 }
1079
1080 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1081                               enum pipe pipe, u32 val)
1082 {
1083         if ((val & LVDS_PORT_EN) == 0)
1084                 return false;
1085
1086         if (HAS_PCH_CPT(dev_priv->dev)) {
1087                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1088                         return false;
1089         } else {
1090                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1091                         return false;
1092         }
1093         return true;
1094 }
1095
1096 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1097                               enum pipe pipe, u32 val)
1098 {
1099         if ((val & ADPA_DAC_ENABLE) == 0)
1100                 return false;
1101         if (HAS_PCH_CPT(dev_priv->dev)) {
1102                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1103                         return false;
1104         } else {
1105                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1106                         return false;
1107         }
1108         return true;
1109 }
1110
1111 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1112                                    enum pipe pipe, int reg, u32 port_sel)
1113 {
1114         u32 val = I915_READ(reg);
1115         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1116              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1117              reg, pipe_name(pipe));
1118 }
1119
1120 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1121                                      enum pipe pipe, int reg)
1122 {
1123         u32 val = I915_READ(reg);
1124         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1125              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1126              reg, pipe_name(pipe));
1127 }
1128
1129 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1130                                       enum pipe pipe)
1131 {
1132         int reg;
1133         u32 val;
1134
1135         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1136         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1137         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1138
1139         reg = PCH_ADPA;
1140         val = I915_READ(reg);
1141         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1142              "PCH VGA enabled on transcoder %c, should be disabled\n",
1143              pipe_name(pipe));
1144
1145         reg = PCH_LVDS;
1146         val = I915_READ(reg);
1147         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1148              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1149              pipe_name(pipe));
1150
1151         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1152         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1153         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1154 }
1155
1156 /**
1157  * intel_enable_pll - enable a PLL
1158  * @dev_priv: i915 private structure
1159  * @pipe: pipe PLL to enable
1160  *
1161  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1162  * make sure the PLL reg is writable first though, since the panel write
1163  * protect mechanism may be enabled.
1164  *
1165  * Note!  This is for pre-ILK only.
1166  */
1167 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1168 {
1169         int reg;
1170         u32 val;
1171
1172         /* No really, not for ILK+ */
1173         BUG_ON(dev_priv->info->gen >= 5);
1174
1175         /* PLL is protected by panel, make sure we can write it */
1176         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1177                 assert_panel_unlocked(dev_priv, pipe);
1178
1179         reg = DPLL(pipe);
1180         val = I915_READ(reg);
1181         val |= DPLL_VCO_ENABLE;
1182
1183         /* We do this three times for luck */
1184         I915_WRITE(reg, val);
1185         POSTING_READ(reg);
1186         udelay(150); /* wait for warmup */
1187         I915_WRITE(reg, val);
1188         POSTING_READ(reg);
1189         udelay(150); /* wait for warmup */
1190         I915_WRITE(reg, val);
1191         POSTING_READ(reg);
1192         udelay(150); /* wait for warmup */
1193 }
1194
1195 /**
1196  * intel_disable_pll - disable a PLL
1197  * @dev_priv: i915 private structure
1198  * @pipe: pipe PLL to disable
1199  *
1200  * Disable the PLL for @pipe, making sure the pipe is off first.
1201  *
1202  * Note!  This is for pre-ILK only.
1203  */
1204 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1205 {
1206         int reg;
1207         u32 val;
1208
1209         /* Don't disable pipe A or pipe A PLLs if needed */
1210         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1211                 return;
1212
1213         /* Make sure the pipe isn't still relying on us */
1214         assert_pipe_disabled(dev_priv, pipe);
1215
1216         reg = DPLL(pipe);
1217         val = I915_READ(reg);
1218         val &= ~DPLL_VCO_ENABLE;
1219         I915_WRITE(reg, val);
1220         POSTING_READ(reg);
1221 }
1222
1223 /**
1224  * intel_enable_pch_pll - enable PCH PLL
1225  * @dev_priv: i915 private structure
1226  * @pipe: pipe PLL to enable
1227  *
1228  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1229  * drives the transcoder clock.
1230  */
1231 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1232                                  enum pipe pipe)
1233 {
1234         int reg;
1235         u32 val;
1236
1237         if (pipe > 1)
1238                 return;
1239
1240         /* PCH only available on ILK+ */
1241         BUG_ON(dev_priv->info->gen < 5);
1242
1243         /* PCH refclock must be enabled first */
1244         assert_pch_refclk_enabled(dev_priv);
1245
1246         reg = PCH_DPLL(pipe);
1247         val = I915_READ(reg);
1248         val |= DPLL_VCO_ENABLE;
1249         I915_WRITE(reg, val);
1250         POSTING_READ(reg);
1251         udelay(200);
1252 }
1253
1254 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1255                                   enum pipe pipe)
1256 {
1257         int reg;
1258         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1259                 pll_sel = TRANSC_DPLL_ENABLE;
1260
1261         if (pipe > 1)
1262                 return;
1263
1264         /* PCH only available on ILK+ */
1265         BUG_ON(dev_priv->info->gen < 5);
1266
1267         /* Make sure transcoder isn't still depending on us */
1268         assert_transcoder_disabled(dev_priv, pipe);
1269
1270         if (pipe == 0)
1271                 pll_sel |= TRANSC_DPLLA_SEL;
1272         else if (pipe == 1)
1273                 pll_sel |= TRANSC_DPLLB_SEL;
1274
1275
1276         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1277                 return;
1278
1279         reg = PCH_DPLL(pipe);
1280         val = I915_READ(reg);
1281         val &= ~DPLL_VCO_ENABLE;
1282         I915_WRITE(reg, val);
1283         POSTING_READ(reg);
1284         udelay(200);
1285 }
1286
1287 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1288                                     enum pipe pipe)
1289 {
1290         int reg;
1291         u32 val, pipeconf_val;
1292         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1293
1294         /* PCH only available on ILK+ */
1295         BUG_ON(dev_priv->info->gen < 5);
1296
1297         /* Make sure PCH DPLL is enabled */
1298         assert_pch_pll_enabled(dev_priv, pipe);
1299
1300         /* FDI must be feeding us bits for PCH ports */
1301         assert_fdi_tx_enabled(dev_priv, pipe);
1302         assert_fdi_rx_enabled(dev_priv, pipe);
1303
1304         reg = TRANSCONF(pipe);
1305         val = I915_READ(reg);
1306         pipeconf_val = I915_READ(PIPECONF(pipe));
1307
1308         if (HAS_PCH_IBX(dev_priv->dev)) {
1309                 /*
1310                  * make the BPC in transcoder be consistent with
1311                  * that in pipeconf reg.
1312                  */
1313                 val &= ~PIPE_BPC_MASK;
1314                 val |= pipeconf_val & PIPE_BPC_MASK;
1315         }
1316
1317         val &= ~TRANS_INTERLACE_MASK;
1318         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1319                 if (HAS_PCH_IBX(dev_priv->dev) &&
1320                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1321                         val |= TRANS_LEGACY_INTERLACED_ILK;
1322                 else
1323                         val |= TRANS_INTERLACED;
1324         else
1325                 val |= TRANS_PROGRESSIVE;
1326
1327         I915_WRITE(reg, val | TRANS_ENABLE);
1328         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1329                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1330 }
1331
1332 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1333                                      enum pipe pipe)
1334 {
1335         int reg;
1336         u32 val;
1337
1338         /* FDI relies on the transcoder */
1339         assert_fdi_tx_disabled(dev_priv, pipe);
1340         assert_fdi_rx_disabled(dev_priv, pipe);
1341
1342         /* Ports must be off as well */
1343         assert_pch_ports_disabled(dev_priv, pipe);
1344
1345         reg = TRANSCONF(pipe);
1346         val = I915_READ(reg);
1347         val &= ~TRANS_ENABLE;
1348         I915_WRITE(reg, val);
1349         /* wait for PCH transcoder off, transcoder state */
1350         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1351                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1352 }
1353
1354 /**
1355  * intel_enable_pipe - enable a pipe, asserting requirements
1356  * @dev_priv: i915 private structure
1357  * @pipe: pipe to enable
1358  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1359  *
1360  * Enable @pipe, making sure that various hardware specific requirements
1361  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1362  *
1363  * @pipe should be %PIPE_A or %PIPE_B.
1364  *
1365  * Will wait until the pipe is actually running (i.e. first vblank) before
1366  * returning.
1367  */
1368 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1369                               bool pch_port)
1370 {
1371         int reg;
1372         u32 val;
1373
1374         /*
1375          * A pipe without a PLL won't actually be able to drive bits from
1376          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1377          * need the check.
1378          */
1379         if (!HAS_PCH_SPLIT(dev_priv->dev))
1380                 assert_pll_enabled(dev_priv, pipe);
1381         else {
1382                 if (pch_port) {
1383                         /* if driving the PCH, we need FDI enabled */
1384                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1385                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1386                 }
1387                 /* FIXME: assert CPU port conditions for SNB+ */
1388         }
1389
1390         reg = PIPECONF(pipe);
1391         val = I915_READ(reg);
1392         if (val & PIPECONF_ENABLE)
1393                 return;
1394
1395         I915_WRITE(reg, val | PIPECONF_ENABLE);
1396         intel_wait_for_vblank(dev_priv->dev, pipe);
1397 }
1398
1399 /**
1400  * intel_disable_pipe - disable a pipe, asserting requirements
1401  * @dev_priv: i915 private structure
1402  * @pipe: pipe to disable
1403  *
1404  * Disable @pipe, making sure that various hardware specific requirements
1405  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1406  *
1407  * @pipe should be %PIPE_A or %PIPE_B.
1408  *
1409  * Will wait until the pipe has shut down before returning.
1410  */
1411 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1412                                enum pipe pipe)
1413 {
1414         int reg;
1415         u32 val;
1416
1417         /*
1418          * Make sure planes won't keep trying to pump pixels to us,
1419          * or we might hang the display.
1420          */
1421         assert_planes_disabled(dev_priv, pipe);
1422
1423         /* Don't disable pipe A or pipe A PLLs if needed */
1424         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1425                 return;
1426
1427         reg = PIPECONF(pipe);
1428         val = I915_READ(reg);
1429         if ((val & PIPECONF_ENABLE) == 0)
1430                 return;
1431
1432         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1433         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1434 }
1435
1436 /*
1437  * Plane regs are double buffered, going from enabled->disabled needs a
1438  * trigger in order to latch.  The display address reg provides this.
1439  */
1440 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1441                                       enum plane plane)
1442 {
1443         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1444         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1445 }
1446
1447 /**
1448  * intel_enable_plane - enable a display plane on a given pipe
1449  * @dev_priv: i915 private structure
1450  * @plane: plane to enable
1451  * @pipe: pipe being fed
1452  *
1453  * Enable @plane on @pipe, making sure that @pipe is running first.
1454  */
1455 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1456                                enum plane plane, enum pipe pipe)
1457 {
1458         int reg;
1459         u32 val;
1460
1461         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1462         assert_pipe_enabled(dev_priv, pipe);
1463
1464         reg = DSPCNTR(plane);
1465         val = I915_READ(reg);
1466         if (val & DISPLAY_PLANE_ENABLE)
1467                 return;
1468
1469         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1470         intel_flush_display_plane(dev_priv, plane);
1471         intel_wait_for_vblank(dev_priv->dev, pipe);
1472 }
1473
1474 /**
1475  * intel_disable_plane - disable a display plane
1476  * @dev_priv: i915 private structure
1477  * @plane: plane to disable
1478  * @pipe: pipe consuming the data
1479  *
1480  * Disable @plane; should be an independent operation.
1481  */
1482 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1483                                 enum plane plane, enum pipe pipe)
1484 {
1485         int reg;
1486         u32 val;
1487
1488         reg = DSPCNTR(plane);
1489         val = I915_READ(reg);
1490         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1491                 return;
1492
1493         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1494         intel_flush_display_plane(dev_priv, plane);
1495         intel_wait_for_vblank(dev_priv->dev, pipe);
1496 }
1497
1498 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1499                            enum pipe pipe, int reg, u32 port_sel)
1500 {
1501         u32 val = I915_READ(reg);
1502         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1503                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1504                 I915_WRITE(reg, val & ~DP_PORT_EN);
1505         }
1506 }
1507
1508 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1509                              enum pipe pipe, int reg)
1510 {
1511         u32 val = I915_READ(reg);
1512         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1513                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1514                               reg, pipe);
1515                 I915_WRITE(reg, val & ~PORT_ENABLE);
1516         }
1517 }
1518
1519 /* Disable any ports connected to this transcoder */
1520 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1521                                     enum pipe pipe)
1522 {
1523         u32 reg, val;
1524
1525         val = I915_READ(PCH_PP_CONTROL);
1526         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1527
1528         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1529         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1530         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1531
1532         reg = PCH_ADPA;
1533         val = I915_READ(reg);
1534         if (adpa_pipe_enabled(dev_priv, val, pipe))
1535                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1536
1537         reg = PCH_LVDS;
1538         val = I915_READ(reg);
1539         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1540                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1541                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1542                 POSTING_READ(reg);
1543                 udelay(100);
1544         }
1545
1546         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1547         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1548         disable_pch_hdmi(dev_priv, pipe, HDMID);
1549 }
1550
1551 static void i8xx_disable_fbc(struct drm_device *dev)
1552 {
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         u32 fbc_ctl;
1555
1556         /* Disable compression */
1557         fbc_ctl = I915_READ(FBC_CONTROL);
1558         if ((fbc_ctl & FBC_CTL_EN) == 0)
1559                 return;
1560
1561         fbc_ctl &= ~FBC_CTL_EN;
1562         I915_WRITE(FBC_CONTROL, fbc_ctl);
1563
1564         /* Wait for compressing bit to clear */
1565         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1566                 DRM_DEBUG_KMS("FBC idle timed out\n");
1567                 return;
1568         }
1569
1570         DRM_DEBUG_KMS("disabled FBC\n");
1571 }
1572
1573 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1574 {
1575         struct drm_device *dev = crtc->dev;
1576         struct drm_i915_private *dev_priv = dev->dev_private;
1577         struct drm_framebuffer *fb = crtc->fb;
1578         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1579         struct drm_i915_gem_object *obj = intel_fb->obj;
1580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1581         int cfb_pitch;
1582         int plane, i;
1583         u32 fbc_ctl, fbc_ctl2;
1584
1585         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1586         if (fb->pitches[0] < cfb_pitch)
1587                 cfb_pitch = fb->pitches[0];
1588
1589         /* FBC_CTL wants 64B units */
1590         cfb_pitch = (cfb_pitch / 64) - 1;
1591         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1592
1593         /* Clear old tags */
1594         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1595                 I915_WRITE(FBC_TAG + (i * 4), 0);
1596
1597         /* Set it up... */
1598         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1599         fbc_ctl2 |= plane;
1600         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1601         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1602
1603         /* enable it... */
1604         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1605         if (IS_I945GM(dev))
1606                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1607         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1608         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1609         fbc_ctl |= obj->fence_reg;
1610         I915_WRITE(FBC_CONTROL, fbc_ctl);
1611
1612         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1613                       cfb_pitch, crtc->y, intel_crtc->plane);
1614 }
1615
1616 static bool i8xx_fbc_enabled(struct drm_device *dev)
1617 {
1618         struct drm_i915_private *dev_priv = dev->dev_private;
1619
1620         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1621 }
1622
1623 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1624 {
1625         struct drm_device *dev = crtc->dev;
1626         struct drm_i915_private *dev_priv = dev->dev_private;
1627         struct drm_framebuffer *fb = crtc->fb;
1628         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1629         struct drm_i915_gem_object *obj = intel_fb->obj;
1630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1631         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1632         unsigned long stall_watermark = 200;
1633         u32 dpfc_ctl;
1634
1635         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1636         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1637         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1638
1639         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1640                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1641                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1642         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1643
1644         /* enable it... */
1645         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1646
1647         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1648 }
1649
1650 static void g4x_disable_fbc(struct drm_device *dev)
1651 {
1652         struct drm_i915_private *dev_priv = dev->dev_private;
1653         u32 dpfc_ctl;
1654
1655         /* Disable compression */
1656         dpfc_ctl = I915_READ(DPFC_CONTROL);
1657         if (dpfc_ctl & DPFC_CTL_EN) {
1658                 dpfc_ctl &= ~DPFC_CTL_EN;
1659                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1660
1661                 DRM_DEBUG_KMS("disabled FBC\n");
1662         }
1663 }
1664
1665 static bool g4x_fbc_enabled(struct drm_device *dev)
1666 {
1667         struct drm_i915_private *dev_priv = dev->dev_private;
1668
1669         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1670 }
1671
1672 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1673 {
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675         u32 blt_ecoskpd;
1676
1677         /* Make sure blitter notifies FBC of writes */
1678         gen6_gt_force_wake_get(dev_priv);
1679         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1680         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1681                 GEN6_BLITTER_LOCK_SHIFT;
1682         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1683         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1684         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1685         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1686                          GEN6_BLITTER_LOCK_SHIFT);
1687         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1688         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1689         gen6_gt_force_wake_put(dev_priv);
1690 }
1691
1692 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1693 {
1694         struct drm_device *dev = crtc->dev;
1695         struct drm_i915_private *dev_priv = dev->dev_private;
1696         struct drm_framebuffer *fb = crtc->fb;
1697         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1698         struct drm_i915_gem_object *obj = intel_fb->obj;
1699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1700         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1701         unsigned long stall_watermark = 200;
1702         u32 dpfc_ctl;
1703
1704         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1705         dpfc_ctl &= DPFC_RESERVED;
1706         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1707         /* Set persistent mode for front-buffer rendering, ala X. */
1708         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1709         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1710         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1711
1712         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1713                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1714                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1715         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1716         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1717         /* enable it... */
1718         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1719
1720         if (IS_GEN6(dev)) {
1721                 I915_WRITE(SNB_DPFC_CTL_SA,
1722                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1723                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1724                 sandybridge_blit_fbc_update(dev);
1725         }
1726
1727         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1728 }
1729
1730 static void ironlake_disable_fbc(struct drm_device *dev)
1731 {
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733         u32 dpfc_ctl;
1734
1735         /* Disable compression */
1736         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1737         if (dpfc_ctl & DPFC_CTL_EN) {
1738                 dpfc_ctl &= ~DPFC_CTL_EN;
1739                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1740
1741                 DRM_DEBUG_KMS("disabled FBC\n");
1742         }
1743 }
1744
1745 static bool ironlake_fbc_enabled(struct drm_device *dev)
1746 {
1747         struct drm_i915_private *dev_priv = dev->dev_private;
1748
1749         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1750 }
1751
1752 bool intel_fbc_enabled(struct drm_device *dev)
1753 {
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755
1756         if (!dev_priv->display.fbc_enabled)
1757                 return false;
1758
1759         return dev_priv->display.fbc_enabled(dev);
1760 }
1761
1762 static void intel_fbc_work_fn(struct work_struct *__work)
1763 {
1764         struct intel_fbc_work *work =
1765                 container_of(to_delayed_work(__work),
1766                              struct intel_fbc_work, work);
1767         struct drm_device *dev = work->crtc->dev;
1768         struct drm_i915_private *dev_priv = dev->dev_private;
1769
1770         mutex_lock(&dev->struct_mutex);
1771         if (work == dev_priv->fbc_work) {
1772                 /* Double check that we haven't switched fb without cancelling
1773                  * the prior work.
1774                  */
1775                 if (work->crtc->fb == work->fb) {
1776                         dev_priv->display.enable_fbc(work->crtc,
1777                                                      work->interval);
1778
1779                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1780                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1781                         dev_priv->cfb_y = work->crtc->y;
1782                 }
1783
1784                 dev_priv->fbc_work = NULL;
1785         }
1786         mutex_unlock(&dev->struct_mutex);
1787
1788         kfree(work);
1789 }
1790
1791 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1792 {
1793         if (dev_priv->fbc_work == NULL)
1794                 return;
1795
1796         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1797
1798         /* Synchronisation is provided by struct_mutex and checking of
1799          * dev_priv->fbc_work, so we can perform the cancellation
1800          * entirely asynchronously.
1801          */
1802         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1803                 /* tasklet was killed before being run, clean up */
1804                 kfree(dev_priv->fbc_work);
1805
1806         /* Mark the work as no longer wanted so that if it does
1807          * wake-up (because the work was already running and waiting
1808          * for our mutex), it will discover that is no longer
1809          * necessary to run.
1810          */
1811         dev_priv->fbc_work = NULL;
1812 }
1813
1814 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1815 {
1816         struct intel_fbc_work *work;
1817         struct drm_device *dev = crtc->dev;
1818         struct drm_i915_private *dev_priv = dev->dev_private;
1819
1820         if (!dev_priv->display.enable_fbc)
1821                 return;
1822
1823         intel_cancel_fbc_work(dev_priv);
1824
1825         work = kzalloc(sizeof *work, GFP_KERNEL);
1826         if (work == NULL) {
1827                 dev_priv->display.enable_fbc(crtc, interval);
1828                 return;
1829         }
1830
1831         work->crtc = crtc;
1832         work->fb = crtc->fb;
1833         work->interval = interval;
1834         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1835
1836         dev_priv->fbc_work = work;
1837
1838         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1839
1840         /* Delay the actual enabling to let pageflipping cease and the
1841          * display to settle before starting the compression. Note that
1842          * this delay also serves a second purpose: it allows for a
1843          * vblank to pass after disabling the FBC before we attempt
1844          * to modify the control registers.
1845          *
1846          * A more complicated solution would involve tracking vblanks
1847          * following the termination of the page-flipping sequence
1848          * and indeed performing the enable as a co-routine and not
1849          * waiting synchronously upon the vblank.
1850          */
1851         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1852 }
1853
1854 void intel_disable_fbc(struct drm_device *dev)
1855 {
1856         struct drm_i915_private *dev_priv = dev->dev_private;
1857
1858         intel_cancel_fbc_work(dev_priv);
1859
1860         if (!dev_priv->display.disable_fbc)
1861                 return;
1862
1863         dev_priv->display.disable_fbc(dev);
1864         dev_priv->cfb_plane = -1;
1865 }
1866
1867 /**
1868  * intel_update_fbc - enable/disable FBC as needed
1869  * @dev: the drm_device
1870  *
1871  * Set up the framebuffer compression hardware at mode set time.  We
1872  * enable it if possible:
1873  *   - plane A only (on pre-965)
1874  *   - no pixel mulitply/line duplication
1875  *   - no alpha buffer discard
1876  *   - no dual wide
1877  *   - framebuffer <= 2048 in width, 1536 in height
1878  *
1879  * We can't assume that any compression will take place (worst case),
1880  * so the compressed buffer has to be the same size as the uncompressed
1881  * one.  It also must reside (along with the line length buffer) in
1882  * stolen memory.
1883  *
1884  * We need to enable/disable FBC on a global basis.
1885  */
1886 static void intel_update_fbc(struct drm_device *dev)
1887 {
1888         struct drm_i915_private *dev_priv = dev->dev_private;
1889         struct drm_crtc *crtc = NULL, *tmp_crtc;
1890         struct intel_crtc *intel_crtc;
1891         struct drm_framebuffer *fb;
1892         struct intel_framebuffer *intel_fb;
1893         struct drm_i915_gem_object *obj;
1894         int enable_fbc;
1895
1896         DRM_DEBUG_KMS("\n");
1897
1898         if (!i915_powersave)
1899                 return;
1900
1901         if (!I915_HAS_FBC(dev))
1902                 return;
1903
1904         /*
1905          * If FBC is already on, we just have to verify that we can
1906          * keep it that way...
1907          * Need to disable if:
1908          *   - more than one pipe is active
1909          *   - changing FBC params (stride, fence, mode)
1910          *   - new fb is too large to fit in compressed buffer
1911          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1912          */
1913         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1914                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1915                         if (crtc) {
1916                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1917                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1918                                 goto out_disable;
1919                         }
1920                         crtc = tmp_crtc;
1921                 }
1922         }
1923
1924         if (!crtc || crtc->fb == NULL) {
1925                 DRM_DEBUG_KMS("no output, disabling\n");
1926                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1927                 goto out_disable;
1928         }
1929
1930         intel_crtc = to_intel_crtc(crtc);
1931         fb = crtc->fb;
1932         intel_fb = to_intel_framebuffer(fb);
1933         obj = intel_fb->obj;
1934
1935         enable_fbc = i915_enable_fbc;
1936         if (enable_fbc < 0) {
1937                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1938                 enable_fbc = 1;
1939                 if (INTEL_INFO(dev)->gen <= 6)
1940                         enable_fbc = 0;
1941         }
1942         if (!enable_fbc) {
1943                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1944                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1945                 goto out_disable;
1946         }
1947         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1948                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1949                               "compression\n");
1950                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1951                 goto out_disable;
1952         }
1953         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1954             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1955                 DRM_DEBUG_KMS("mode incompatible with compression, "
1956                               "disabling\n");
1957                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1958                 goto out_disable;
1959         }
1960         if ((crtc->mode.hdisplay > 2048) ||
1961             (crtc->mode.vdisplay > 1536)) {
1962                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1963                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1964                 goto out_disable;
1965         }
1966         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1967                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1968                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1969                 goto out_disable;
1970         }
1971
1972         /* The use of a CPU fence is mandatory in order to detect writes
1973          * by the CPU to the scanout and trigger updates to the FBC.
1974          */
1975         if (obj->tiling_mode != I915_TILING_X ||
1976             obj->fence_reg == I915_FENCE_REG_NONE) {
1977                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1978                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1979                 goto out_disable;
1980         }
1981
1982         /* If the kernel debugger is active, always disable compression */
1983         if (in_dbg_master())
1984                 goto out_disable;
1985
1986         /* If the scanout has not changed, don't modify the FBC settings.
1987          * Note that we make the fundamental assumption that the fb->obj
1988          * cannot be unpinned (and have its GTT offset and fence revoked)
1989          * without first being decoupled from the scanout and FBC disabled.
1990          */
1991         if (dev_priv->cfb_plane == intel_crtc->plane &&
1992             dev_priv->cfb_fb == fb->base.id &&
1993             dev_priv->cfb_y == crtc->y)
1994                 return;
1995
1996         if (intel_fbc_enabled(dev)) {
1997                 /* We update FBC along two paths, after changing fb/crtc
1998                  * configuration (modeswitching) and after page-flipping
1999                  * finishes. For the latter, we know that not only did
2000                  * we disable the FBC at the start of the page-flip
2001                  * sequence, but also more than one vblank has passed.
2002                  *
2003                  * For the former case of modeswitching, it is possible
2004                  * to switch between two FBC valid configurations
2005                  * instantaneously so we do need to disable the FBC
2006                  * before we can modify its control registers. We also
2007                  * have to wait for the next vblank for that to take
2008                  * effect. However, since we delay enabling FBC we can
2009                  * assume that a vblank has passed since disabling and
2010                  * that we can safely alter the registers in the deferred
2011                  * callback.
2012                  *
2013                  * In the scenario that we go from a valid to invalid
2014                  * and then back to valid FBC configuration we have
2015                  * no strict enforcement that a vblank occurred since
2016                  * disabling the FBC. However, along all current pipe
2017                  * disabling paths we do need to wait for a vblank at
2018                  * some point. And we wait before enabling FBC anyway.
2019                  */
2020                 DRM_DEBUG_KMS("disabling active FBC for update\n");
2021                 intel_disable_fbc(dev);
2022         }
2023
2024         intel_enable_fbc(crtc, 500);
2025         return;
2026
2027 out_disable:
2028         /* Multiple disables should be harmless */
2029         if (intel_fbc_enabled(dev)) {
2030                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2031                 intel_disable_fbc(dev);
2032         }
2033 }
2034
2035 int
2036 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2037                            struct drm_i915_gem_object *obj,
2038                            struct intel_ring_buffer *pipelined)
2039 {
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041         u32 alignment;
2042         int ret;
2043
2044         switch (obj->tiling_mode) {
2045         case I915_TILING_NONE:
2046                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2047                         alignment = 128 * 1024;
2048                 else if (INTEL_INFO(dev)->gen >= 4)
2049                         alignment = 4 * 1024;
2050                 else
2051                         alignment = 64 * 1024;
2052                 break;
2053         case I915_TILING_X:
2054                 /* pin() will align the object as required by fence */
2055                 alignment = 0;
2056                 break;
2057         case I915_TILING_Y:
2058                 /* FIXME: Is this true? */
2059                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2060                 return -EINVAL;
2061         default:
2062                 BUG();
2063         }
2064
2065         dev_priv->mm.interruptible = false;
2066         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2067         if (ret)
2068                 goto err_interruptible;
2069
2070         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2071          * fence, whereas 965+ only requires a fence if using
2072          * framebuffer compression.  For simplicity, we always install
2073          * a fence as the cost is not that onerous.
2074          */
2075         if (obj->tiling_mode != I915_TILING_NONE) {
2076                 ret = i915_gem_object_get_fence(obj, pipelined);
2077                 if (ret)
2078                         goto err_unpin;
2079
2080                 i915_gem_object_pin_fence(obj);
2081         }
2082
2083         dev_priv->mm.interruptible = true;
2084         return 0;
2085
2086 err_unpin:
2087         i915_gem_object_unpin(obj);
2088 err_interruptible:
2089         dev_priv->mm.interruptible = true;
2090         return ret;
2091 }
2092
2093 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2094 {
2095         i915_gem_object_unpin_fence(obj);
2096         i915_gem_object_unpin(obj);
2097 }
2098
2099 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2100                              int x, int y)
2101 {
2102         struct drm_device *dev = crtc->dev;
2103         struct drm_i915_private *dev_priv = dev->dev_private;
2104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2105         struct intel_framebuffer *intel_fb;
2106         struct drm_i915_gem_object *obj;
2107         int plane = intel_crtc->plane;
2108         unsigned long Start, Offset;
2109         u32 dspcntr;
2110         u32 reg;
2111
2112         switch (plane) {
2113         case 0:
2114         case 1:
2115                 break;
2116         default:
2117                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2118                 return -EINVAL;
2119         }
2120
2121         intel_fb = to_intel_framebuffer(fb);
2122         obj = intel_fb->obj;
2123
2124         reg = DSPCNTR(plane);
2125         dspcntr = I915_READ(reg);
2126         /* Mask out pixel format bits in case we change it */
2127         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2128         switch (fb->bits_per_pixel) {
2129         case 8:
2130                 dspcntr |= DISPPLANE_8BPP;
2131                 break;
2132         case 16:
2133                 if (fb->depth == 15)
2134                         dspcntr |= DISPPLANE_15_16BPP;
2135                 else
2136                         dspcntr |= DISPPLANE_16BPP;
2137                 break;
2138         case 24:
2139         case 32:
2140                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2141                 break;
2142         default:
2143                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2144                 return -EINVAL;
2145         }
2146         if (INTEL_INFO(dev)->gen >= 4) {
2147                 if (obj->tiling_mode != I915_TILING_NONE)
2148                         dspcntr |= DISPPLANE_TILED;
2149                 else
2150                         dspcntr &= ~DISPPLANE_TILED;
2151         }
2152
2153         I915_WRITE(reg, dspcntr);
2154
2155         Start = obj->gtt_offset;
2156         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2157
2158         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2159                       Start, Offset, x, y, fb->pitches[0]);
2160         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2161         if (INTEL_INFO(dev)->gen >= 4) {
2162                 I915_WRITE(DSPSURF(plane), Start);
2163                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164                 I915_WRITE(DSPADDR(plane), Offset);
2165         } else
2166                 I915_WRITE(DSPADDR(plane), Start + Offset);
2167         POSTING_READ(reg);
2168
2169         return 0;
2170 }
2171
2172 static int ironlake_update_plane(struct drm_crtc *crtc,
2173                                  struct drm_framebuffer *fb, int x, int y)
2174 {
2175         struct drm_device *dev = crtc->dev;
2176         struct drm_i915_private *dev_priv = dev->dev_private;
2177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2178         struct intel_framebuffer *intel_fb;
2179         struct drm_i915_gem_object *obj;
2180         int plane = intel_crtc->plane;
2181         unsigned long Start, Offset;
2182         u32 dspcntr;
2183         u32 reg;
2184
2185         switch (plane) {
2186         case 0:
2187         case 1:
2188         case 2:
2189                 break;
2190         default:
2191                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2192                 return -EINVAL;
2193         }
2194
2195         intel_fb = to_intel_framebuffer(fb);
2196         obj = intel_fb->obj;
2197
2198         reg = DSPCNTR(plane);
2199         dspcntr = I915_READ(reg);
2200         /* Mask out pixel format bits in case we change it */
2201         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2202         switch (fb->bits_per_pixel) {
2203         case 8:
2204                 dspcntr |= DISPPLANE_8BPP;
2205                 break;
2206         case 16:
2207                 if (fb->depth != 16)
2208                         return -EINVAL;
2209
2210                 dspcntr |= DISPPLANE_16BPP;
2211                 break;
2212         case 24:
2213         case 32:
2214                 if (fb->depth == 24)
2215                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2216                 else if (fb->depth == 30)
2217                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2218                 else
2219                         return -EINVAL;
2220                 break;
2221         default:
2222                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2223                 return -EINVAL;
2224         }
2225
2226         if (obj->tiling_mode != I915_TILING_NONE)
2227                 dspcntr |= DISPPLANE_TILED;
2228         else
2229                 dspcntr &= ~DISPPLANE_TILED;
2230
2231         /* must disable */
2232         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2233
2234         I915_WRITE(reg, dspcntr);
2235
2236         Start = obj->gtt_offset;
2237         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2238
2239         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2240                       Start, Offset, x, y, fb->pitches[0]);
2241         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2242         I915_WRITE(DSPSURF(plane), Start);
2243         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2244         I915_WRITE(DSPADDR(plane), Offset);
2245         POSTING_READ(reg);
2246
2247         return 0;
2248 }
2249
2250 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2251 static int
2252 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2253                            int x, int y, enum mode_set_atomic state)
2254 {
2255         struct drm_device *dev = crtc->dev;
2256         struct drm_i915_private *dev_priv = dev->dev_private;
2257         int ret;
2258
2259         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2260         if (ret)
2261                 return ret;
2262
2263         intel_update_fbc(dev);
2264         intel_increase_pllclock(crtc);
2265
2266         return 0;
2267 }
2268
2269 static int
2270 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2271                     struct drm_framebuffer *old_fb)
2272 {
2273         struct drm_device *dev = crtc->dev;
2274         struct drm_i915_master_private *master_priv;
2275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2276         int ret;
2277
2278         /* no fb bound */
2279         if (!crtc->fb) {
2280                 DRM_ERROR("No FB bound\n");
2281                 return 0;
2282         }
2283
2284         switch (intel_crtc->plane) {
2285         case 0:
2286         case 1:
2287                 break;
2288         case 2:
2289                 if (IS_IVYBRIDGE(dev))
2290                         break;
2291                 /* fall through otherwise */
2292         default:
2293                 DRM_ERROR("no plane for crtc\n");
2294                 return -EINVAL;
2295         }
2296
2297         mutex_lock(&dev->struct_mutex);
2298         ret = intel_pin_and_fence_fb_obj(dev,
2299                                          to_intel_framebuffer(crtc->fb)->obj,
2300                                          NULL);
2301         if (ret != 0) {
2302                 mutex_unlock(&dev->struct_mutex);
2303                 DRM_ERROR("pin & fence failed\n");
2304                 return ret;
2305         }
2306
2307         if (old_fb) {
2308                 struct drm_i915_private *dev_priv = dev->dev_private;
2309                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2310
2311                 wait_event(dev_priv->pending_flip_queue,
2312                            atomic_read(&dev_priv->mm.wedged) ||
2313                            atomic_read(&obj->pending_flip) == 0);
2314
2315                 /* Big Hammer, we also need to ensure that any pending
2316                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2317                  * current scanout is retired before unpinning the old
2318                  * framebuffer.
2319                  *
2320                  * This should only fail upon a hung GPU, in which case we
2321                  * can safely continue.
2322                  */
2323                 ret = i915_gem_object_finish_gpu(obj);
2324                 (void) ret;
2325         }
2326
2327         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2328                                          LEAVE_ATOMIC_MODE_SET);
2329         if (ret) {
2330                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2331                 mutex_unlock(&dev->struct_mutex);
2332                 DRM_ERROR("failed to update base address\n");
2333                 return ret;
2334         }
2335
2336         if (old_fb) {
2337                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2338                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2339         }
2340
2341         mutex_unlock(&dev->struct_mutex);
2342
2343         if (!dev->primary->master)
2344                 return 0;
2345
2346         master_priv = dev->primary->master->driver_priv;
2347         if (!master_priv->sarea_priv)
2348                 return 0;
2349
2350         if (intel_crtc->pipe) {
2351                 master_priv->sarea_priv->pipeB_x = x;
2352                 master_priv->sarea_priv->pipeB_y = y;
2353         } else {
2354                 master_priv->sarea_priv->pipeA_x = x;
2355                 master_priv->sarea_priv->pipeA_y = y;
2356         }
2357
2358         return 0;
2359 }
2360
2361 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2362 {
2363         struct drm_device *dev = crtc->dev;
2364         struct drm_i915_private *dev_priv = dev->dev_private;
2365         u32 dpa_ctl;
2366
2367         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2368         dpa_ctl = I915_READ(DP_A);
2369         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2370
2371         if (clock < 200000) {
2372                 u32 temp;
2373                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2374                 /* workaround for 160Mhz:
2375                    1) program 0x4600c bits 15:0 = 0x8124
2376                    2) program 0x46010 bit 0 = 1
2377                    3) program 0x46034 bit 24 = 1
2378                    4) program 0x64000 bit 14 = 1
2379                    */
2380                 temp = I915_READ(0x4600c);
2381                 temp &= 0xffff0000;
2382                 I915_WRITE(0x4600c, temp | 0x8124);
2383
2384                 temp = I915_READ(0x46010);
2385                 I915_WRITE(0x46010, temp | 1);
2386
2387                 temp = I915_READ(0x46034);
2388                 I915_WRITE(0x46034, temp | (1 << 24));
2389         } else {
2390                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2391         }
2392         I915_WRITE(DP_A, dpa_ctl);
2393
2394         POSTING_READ(DP_A);
2395         udelay(500);
2396 }
2397
2398 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2399 {
2400         struct drm_device *dev = crtc->dev;
2401         struct drm_i915_private *dev_priv = dev->dev_private;
2402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403         int pipe = intel_crtc->pipe;
2404         u32 reg, temp;
2405
2406         /* enable normal train */
2407         reg = FDI_TX_CTL(pipe);
2408         temp = I915_READ(reg);
2409         if (IS_IVYBRIDGE(dev)) {
2410                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2411                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2412         } else {
2413                 temp &= ~FDI_LINK_TRAIN_NONE;
2414                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2415         }
2416         I915_WRITE(reg, temp);
2417
2418         reg = FDI_RX_CTL(pipe);
2419         temp = I915_READ(reg);
2420         if (HAS_PCH_CPT(dev)) {
2421                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2422                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2423         } else {
2424                 temp &= ~FDI_LINK_TRAIN_NONE;
2425                 temp |= FDI_LINK_TRAIN_NONE;
2426         }
2427         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2428
2429         /* wait one idle pattern time */
2430         POSTING_READ(reg);
2431         udelay(1000);
2432
2433         /* IVB wants error correction enabled */
2434         if (IS_IVYBRIDGE(dev))
2435                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2436                            FDI_FE_ERRC_ENABLE);
2437 }
2438
2439 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2440 {
2441         struct drm_i915_private *dev_priv = dev->dev_private;
2442         u32 flags = I915_READ(SOUTH_CHICKEN1);
2443
2444         flags |= FDI_PHASE_SYNC_OVR(pipe);
2445         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2446         flags |= FDI_PHASE_SYNC_EN(pipe);
2447         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2448         POSTING_READ(SOUTH_CHICKEN1);
2449 }
2450
2451 /* The FDI link training functions for ILK/Ibexpeak. */
2452 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2453 {
2454         struct drm_device *dev = crtc->dev;
2455         struct drm_i915_private *dev_priv = dev->dev_private;
2456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2457         int pipe = intel_crtc->pipe;
2458         int plane = intel_crtc->plane;
2459         u32 reg, temp, tries;
2460
2461         /* FDI needs bits from pipe & plane first */
2462         assert_pipe_enabled(dev_priv, pipe);
2463         assert_plane_enabled(dev_priv, plane);
2464
2465         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2466            for train result */
2467         reg = FDI_RX_IMR(pipe);
2468         temp = I915_READ(reg);
2469         temp &= ~FDI_RX_SYMBOL_LOCK;
2470         temp &= ~FDI_RX_BIT_LOCK;
2471         I915_WRITE(reg, temp);
2472         I915_READ(reg);
2473         udelay(150);
2474
2475         /* enable CPU FDI TX and PCH FDI RX */
2476         reg = FDI_TX_CTL(pipe);
2477         temp = I915_READ(reg);
2478         temp &= ~(7 << 19);
2479         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2480         temp &= ~FDI_LINK_TRAIN_NONE;
2481         temp |= FDI_LINK_TRAIN_PATTERN_1;
2482         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2483
2484         reg = FDI_RX_CTL(pipe);
2485         temp = I915_READ(reg);
2486         temp &= ~FDI_LINK_TRAIN_NONE;
2487         temp |= FDI_LINK_TRAIN_PATTERN_1;
2488         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2489
2490         POSTING_READ(reg);
2491         udelay(150);
2492
2493         /* Ironlake workaround, enable clock pointer after FDI enable*/
2494         if (HAS_PCH_IBX(dev)) {
2495                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2496                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2497                            FDI_RX_PHASE_SYNC_POINTER_EN);
2498         }
2499
2500         reg = FDI_RX_IIR(pipe);
2501         for (tries = 0; tries < 5; tries++) {
2502                 temp = I915_READ(reg);
2503                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2504
2505                 if ((temp & FDI_RX_BIT_LOCK)) {
2506                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2507                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2508                         break;
2509                 }
2510         }
2511         if (tries == 5)
2512                 DRM_ERROR("FDI train 1 fail!\n");
2513
2514         /* Train 2 */
2515         reg = FDI_TX_CTL(pipe);
2516         temp = I915_READ(reg);
2517         temp &= ~FDI_LINK_TRAIN_NONE;
2518         temp |= FDI_LINK_TRAIN_PATTERN_2;
2519         I915_WRITE(reg, temp);
2520
2521         reg = FDI_RX_CTL(pipe);
2522         temp = I915_READ(reg);
2523         temp &= ~FDI_LINK_TRAIN_NONE;
2524         temp |= FDI_LINK_TRAIN_PATTERN_2;
2525         I915_WRITE(reg, temp);
2526
2527         POSTING_READ(reg);
2528         udelay(150);
2529
2530         reg = FDI_RX_IIR(pipe);
2531         for (tries = 0; tries < 5; tries++) {
2532                 temp = I915_READ(reg);
2533                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2534
2535                 if (temp & FDI_RX_SYMBOL_LOCK) {
2536                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2537                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2538                         break;
2539                 }
2540         }
2541         if (tries == 5)
2542                 DRM_ERROR("FDI train 2 fail!\n");
2543
2544         DRM_DEBUG_KMS("FDI train done\n");
2545
2546 }
2547
2548 static const int snb_b_fdi_train_param[] = {
2549         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2550         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2551         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2552         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2553 };
2554
2555 /* The FDI link training functions for SNB/Cougarpoint. */
2556 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2557 {
2558         struct drm_device *dev = crtc->dev;
2559         struct drm_i915_private *dev_priv = dev->dev_private;
2560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2561         int pipe = intel_crtc->pipe;
2562         u32 reg, temp, i, retry;
2563
2564         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2565            for train result */
2566         reg = FDI_RX_IMR(pipe);
2567         temp = I915_READ(reg);
2568         temp &= ~FDI_RX_SYMBOL_LOCK;
2569         temp &= ~FDI_RX_BIT_LOCK;
2570         I915_WRITE(reg, temp);
2571
2572         POSTING_READ(reg);
2573         udelay(150);
2574
2575         /* enable CPU FDI TX and PCH FDI RX */
2576         reg = FDI_TX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         temp &= ~(7 << 19);
2579         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2580         temp &= ~FDI_LINK_TRAIN_NONE;
2581         temp |= FDI_LINK_TRAIN_PATTERN_1;
2582         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583         /* SNB-B */
2584         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2585         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586
2587         reg = FDI_RX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         if (HAS_PCH_CPT(dev)) {
2590                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2592         } else {
2593                 temp &= ~FDI_LINK_TRAIN_NONE;
2594                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2595         }
2596         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2597
2598         POSTING_READ(reg);
2599         udelay(150);
2600
2601         if (HAS_PCH_CPT(dev))
2602                 cpt_phase_pointer_enable(dev, pipe);
2603
2604         for (i = 0; i < 4; i++) {
2605                 reg = FDI_TX_CTL(pipe);
2606                 temp = I915_READ(reg);
2607                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2608                 temp |= snb_b_fdi_train_param[i];
2609                 I915_WRITE(reg, temp);
2610
2611                 POSTING_READ(reg);
2612                 udelay(500);
2613
2614                 for (retry = 0; retry < 5; retry++) {
2615                         reg = FDI_RX_IIR(pipe);
2616                         temp = I915_READ(reg);
2617                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2618                         if (temp & FDI_RX_BIT_LOCK) {
2619                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2620                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2621                                 break;
2622                         }
2623                         udelay(50);
2624                 }
2625                 if (retry < 5)
2626                         break;
2627         }
2628         if (i == 4)
2629                 DRM_ERROR("FDI train 1 fail!\n");
2630
2631         /* Train 2 */
2632         reg = FDI_TX_CTL(pipe);
2633         temp = I915_READ(reg);
2634         temp &= ~FDI_LINK_TRAIN_NONE;
2635         temp |= FDI_LINK_TRAIN_PATTERN_2;
2636         if (IS_GEN6(dev)) {
2637                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2638                 /* SNB-B */
2639                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2640         }
2641         I915_WRITE(reg, temp);
2642
2643         reg = FDI_RX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         if (HAS_PCH_CPT(dev)) {
2646                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2647                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2648         } else {
2649                 temp &= ~FDI_LINK_TRAIN_NONE;
2650                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2651         }
2652         I915_WRITE(reg, temp);
2653
2654         POSTING_READ(reg);
2655         udelay(150);
2656
2657         for (i = 0; i < 4; i++) {
2658                 reg = FDI_TX_CTL(pipe);
2659                 temp = I915_READ(reg);
2660                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2661                 temp |= snb_b_fdi_train_param[i];
2662                 I915_WRITE(reg, temp);
2663
2664                 POSTING_READ(reg);
2665                 udelay(500);
2666
2667                 for (retry = 0; retry < 5; retry++) {
2668                         reg = FDI_RX_IIR(pipe);
2669                         temp = I915_READ(reg);
2670                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2671                         if (temp & FDI_RX_SYMBOL_LOCK) {
2672                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2673                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2674                                 break;
2675                         }
2676                         udelay(50);
2677                 }
2678                 if (retry < 5)
2679                         break;
2680         }
2681         if (i == 4)
2682                 DRM_ERROR("FDI train 2 fail!\n");
2683
2684         DRM_DEBUG_KMS("FDI train done.\n");
2685 }
2686
2687 /* Manual link training for Ivy Bridge A0 parts */
2688 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2689 {
2690         struct drm_device *dev = crtc->dev;
2691         struct drm_i915_private *dev_priv = dev->dev_private;
2692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2693         int pipe = intel_crtc->pipe;
2694         u32 reg, temp, i;
2695
2696         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2697            for train result */
2698         reg = FDI_RX_IMR(pipe);
2699         temp = I915_READ(reg);
2700         temp &= ~FDI_RX_SYMBOL_LOCK;
2701         temp &= ~FDI_RX_BIT_LOCK;
2702         I915_WRITE(reg, temp);
2703
2704         POSTING_READ(reg);
2705         udelay(150);
2706
2707         /* enable CPU FDI TX and PCH FDI RX */
2708         reg = FDI_TX_CTL(pipe);
2709         temp = I915_READ(reg);
2710         temp &= ~(7 << 19);
2711         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2712         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2713         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2714         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2715         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2716         temp |= FDI_COMPOSITE_SYNC;
2717         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2718
2719         reg = FDI_RX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         temp &= ~FDI_LINK_TRAIN_AUTO;
2722         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2723         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2724         temp |= FDI_COMPOSITE_SYNC;
2725         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2726
2727         POSTING_READ(reg);
2728         udelay(150);
2729
2730         if (HAS_PCH_CPT(dev))
2731                 cpt_phase_pointer_enable(dev, pipe);
2732
2733         for (i = 0; i < 4; i++) {
2734                 reg = FDI_TX_CTL(pipe);
2735                 temp = I915_READ(reg);
2736                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2737                 temp |= snb_b_fdi_train_param[i];
2738                 I915_WRITE(reg, temp);
2739
2740                 POSTING_READ(reg);
2741                 udelay(500);
2742
2743                 reg = FDI_RX_IIR(pipe);
2744                 temp = I915_READ(reg);
2745                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2746
2747                 if (temp & FDI_RX_BIT_LOCK ||
2748                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2749                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2750                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2751                         break;
2752                 }
2753         }
2754         if (i == 4)
2755                 DRM_ERROR("FDI train 1 fail!\n");
2756
2757         /* Train 2 */
2758         reg = FDI_TX_CTL(pipe);
2759         temp = I915_READ(reg);
2760         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2761         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2762         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2763         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2764         I915_WRITE(reg, temp);
2765
2766         reg = FDI_RX_CTL(pipe);
2767         temp = I915_READ(reg);
2768         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2769         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2770         I915_WRITE(reg, temp);
2771
2772         POSTING_READ(reg);
2773         udelay(150);
2774
2775         for (i = 0; i < 4; i++) {
2776                 reg = FDI_TX_CTL(pipe);
2777                 temp = I915_READ(reg);
2778                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779                 temp |= snb_b_fdi_train_param[i];
2780                 I915_WRITE(reg, temp);
2781
2782                 POSTING_READ(reg);
2783                 udelay(500);
2784
2785                 reg = FDI_RX_IIR(pipe);
2786                 temp = I915_READ(reg);
2787                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2788
2789                 if (temp & FDI_RX_SYMBOL_LOCK) {
2790                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2791                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2792                         break;
2793                 }
2794         }
2795         if (i == 4)
2796                 DRM_ERROR("FDI train 2 fail!\n");
2797
2798         DRM_DEBUG_KMS("FDI train done.\n");
2799 }
2800
2801 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2802 {
2803         struct drm_device *dev = crtc->dev;
2804         struct drm_i915_private *dev_priv = dev->dev_private;
2805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2806         int pipe = intel_crtc->pipe;
2807         u32 reg, temp;
2808
2809         /* Write the TU size bits so error detection works */
2810         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2811                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2812
2813         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~((0x7 << 19) | (0x7 << 16));
2817         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2818         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821         POSTING_READ(reg);
2822         udelay(200);
2823
2824         /* Switch from Rawclk to PCDclk */
2825         temp = I915_READ(reg);
2826         I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828         POSTING_READ(reg);
2829         udelay(200);
2830
2831         /* Enable CPU FDI TX PLL, always on for Ironlake */
2832         reg = FDI_TX_CTL(pipe);
2833         temp = I915_READ(reg);
2834         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2835                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2836
2837                 POSTING_READ(reg);
2838                 udelay(100);
2839         }
2840 }
2841
2842 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2843 {
2844         struct drm_i915_private *dev_priv = dev->dev_private;
2845         u32 flags = I915_READ(SOUTH_CHICKEN1);
2846
2847         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2848         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2849         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2850         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2851         POSTING_READ(SOUTH_CHICKEN1);
2852 }
2853 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2854 {
2855         struct drm_device *dev = crtc->dev;
2856         struct drm_i915_private *dev_priv = dev->dev_private;
2857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2858         int pipe = intel_crtc->pipe;
2859         u32 reg, temp;
2860
2861         /* disable CPU FDI tx and PCH FDI rx */
2862         reg = FDI_TX_CTL(pipe);
2863         temp = I915_READ(reg);
2864         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2865         POSTING_READ(reg);
2866
2867         reg = FDI_RX_CTL(pipe);
2868         temp = I915_READ(reg);
2869         temp &= ~(0x7 << 16);
2870         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2871         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2872
2873         POSTING_READ(reg);
2874         udelay(100);
2875
2876         /* Ironlake workaround, disable clock pointer after downing FDI */
2877         if (HAS_PCH_IBX(dev)) {
2878                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2879                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2880                            I915_READ(FDI_RX_CHICKEN(pipe) &
2881                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2882         } else if (HAS_PCH_CPT(dev)) {
2883                 cpt_phase_pointer_disable(dev, pipe);
2884         }
2885
2886         /* still set train pattern 1 */
2887         reg = FDI_TX_CTL(pipe);
2888         temp = I915_READ(reg);
2889         temp &= ~FDI_LINK_TRAIN_NONE;
2890         temp |= FDI_LINK_TRAIN_PATTERN_1;
2891         I915_WRITE(reg, temp);
2892
2893         reg = FDI_RX_CTL(pipe);
2894         temp = I915_READ(reg);
2895         if (HAS_PCH_CPT(dev)) {
2896                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2897                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2898         } else {
2899                 temp &= ~FDI_LINK_TRAIN_NONE;
2900                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2901         }
2902         /* BPC in FDI rx is consistent with that in PIPECONF */
2903         temp &= ~(0x07 << 16);
2904         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2905         I915_WRITE(reg, temp);
2906
2907         POSTING_READ(reg);
2908         udelay(100);
2909 }
2910
2911 /*
2912  * When we disable a pipe, we need to clear any pending scanline wait events
2913  * to avoid hanging the ring, which we assume we are waiting on.
2914  */
2915 static void intel_clear_scanline_wait(struct drm_device *dev)
2916 {
2917         struct drm_i915_private *dev_priv = dev->dev_private;
2918         struct intel_ring_buffer *ring;
2919         u32 tmp;
2920
2921         if (IS_GEN2(dev))
2922                 /* Can't break the hang on i8xx */
2923                 return;
2924
2925         ring = LP_RING(dev_priv);
2926         tmp = I915_READ_CTL(ring);
2927         if (tmp & RING_WAIT)
2928                 I915_WRITE_CTL(ring, tmp);
2929 }
2930
2931 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2932 {
2933         struct drm_i915_gem_object *obj;
2934         struct drm_i915_private *dev_priv;
2935
2936         if (crtc->fb == NULL)
2937                 return;
2938
2939         obj = to_intel_framebuffer(crtc->fb)->obj;
2940         dev_priv = crtc->dev->dev_private;
2941         wait_event(dev_priv->pending_flip_queue,
2942                    atomic_read(&obj->pending_flip) == 0);
2943 }
2944
2945 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2946 {
2947         struct drm_device *dev = crtc->dev;
2948         struct drm_mode_config *mode_config = &dev->mode_config;
2949         struct intel_encoder *encoder;
2950
2951         /*
2952          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2953          * must be driven by its own crtc; no sharing is possible.
2954          */
2955         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2956                 if (encoder->base.crtc != crtc)
2957                         continue;
2958
2959                 switch (encoder->type) {
2960                 case INTEL_OUTPUT_EDP:
2961                         if (!intel_encoder_is_pch_edp(&encoder->base))
2962                                 return false;
2963                         continue;
2964                 }
2965         }
2966
2967         return true;
2968 }
2969
2970 /*
2971  * Enable PCH resources required for PCH ports:
2972  *   - PCH PLLs
2973  *   - FDI training & RX/TX
2974  *   - update transcoder timings
2975  *   - DP transcoding bits
2976  *   - transcoder
2977  */
2978 static void ironlake_pch_enable(struct drm_crtc *crtc)
2979 {
2980         struct drm_device *dev = crtc->dev;
2981         struct drm_i915_private *dev_priv = dev->dev_private;
2982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2983         int pipe = intel_crtc->pipe;
2984         u32 reg, temp, transc_sel;
2985
2986         /* For PCH output, training FDI link */
2987         dev_priv->display.fdi_link_train(crtc);
2988
2989         intel_enable_pch_pll(dev_priv, pipe);
2990
2991         if (HAS_PCH_CPT(dev)) {
2992                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2993                         TRANSC_DPLLB_SEL;
2994
2995                 /* Be sure PCH DPLL SEL is set */
2996                 temp = I915_READ(PCH_DPLL_SEL);
2997                 if (pipe == 0) {
2998                         temp &= ~(TRANSA_DPLLB_SEL);
2999                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3000                 } else if (pipe == 1) {
3001                         temp &= ~(TRANSB_DPLLB_SEL);
3002                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3003                 } else if (pipe == 2) {
3004                         temp &= ~(TRANSC_DPLLB_SEL);
3005                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
3006                 }
3007                 I915_WRITE(PCH_DPLL_SEL, temp);
3008         }
3009
3010         /* set transcoder timing, panel must allow it */
3011         assert_panel_unlocked(dev_priv, pipe);
3012         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3013         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3014         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3015
3016         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3017         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3018         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3019         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3020
3021         intel_fdi_normal_train(crtc);
3022
3023         /* For PCH DP, enable TRANS_DP_CTL */
3024         if (HAS_PCH_CPT(dev) &&
3025             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3026              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3027                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3028                 reg = TRANS_DP_CTL(pipe);
3029                 temp = I915_READ(reg);
3030                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3031                           TRANS_DP_SYNC_MASK |
3032                           TRANS_DP_BPC_MASK);
3033                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3034                          TRANS_DP_ENH_FRAMING);
3035                 temp |= bpc << 9; /* same format but at 11:9 */
3036
3037                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3038                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3039                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3040                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3041
3042                 switch (intel_trans_dp_port_sel(crtc)) {
3043                 case PCH_DP_B:
3044                         temp |= TRANS_DP_PORT_SEL_B;
3045                         break;
3046                 case PCH_DP_C:
3047                         temp |= TRANS_DP_PORT_SEL_C;
3048                         break;
3049                 case PCH_DP_D:
3050                         temp |= TRANS_DP_PORT_SEL_D;
3051                         break;
3052                 default:
3053                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3054                         temp |= TRANS_DP_PORT_SEL_B;
3055                         break;
3056                 }
3057
3058                 I915_WRITE(reg, temp);
3059         }
3060
3061         intel_enable_transcoder(dev_priv, pipe);
3062 }
3063
3064 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3065 {
3066         struct drm_i915_private *dev_priv = dev->dev_private;
3067         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3068         u32 temp;
3069
3070         temp = I915_READ(dslreg);
3071         udelay(500);
3072         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3073                 /* Without this, mode sets may fail silently on FDI */
3074                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3075                 udelay(250);
3076                 I915_WRITE(tc2reg, 0);
3077                 if (wait_for(I915_READ(dslreg) != temp, 5))
3078                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3079         }
3080 }
3081
3082 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3083 {
3084         struct drm_device *dev = crtc->dev;
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087         int pipe = intel_crtc->pipe;
3088         int plane = intel_crtc->plane;
3089         u32 temp;
3090         bool is_pch_port;
3091
3092         if (intel_crtc->active)
3093                 return;
3094
3095         intel_crtc->active = true;
3096         intel_update_watermarks(dev);
3097
3098         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3099                 temp = I915_READ(PCH_LVDS);
3100                 if ((temp & LVDS_PORT_EN) == 0)
3101                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3102         }
3103
3104         is_pch_port = intel_crtc_driving_pch(crtc);
3105
3106         if (is_pch_port)
3107                 ironlake_fdi_pll_enable(crtc);
3108         else
3109                 ironlake_fdi_disable(crtc);
3110
3111         /* Enable panel fitting for LVDS */
3112         if (dev_priv->pch_pf_size &&
3113             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3114                 /* Force use of hard-coded filter coefficients
3115                  * as some pre-programmed values are broken,
3116                  * e.g. x201.
3117                  */
3118                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3119                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3120                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3121         }
3122
3123         /*
3124          * On ILK+ LUT must be loaded before the pipe is running but with
3125          * clocks enabled
3126          */
3127         intel_crtc_load_lut(crtc);
3128
3129         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3130         intel_enable_plane(dev_priv, plane, pipe);
3131
3132         if (is_pch_port)
3133                 ironlake_pch_enable(crtc);
3134
3135         mutex_lock(&dev->struct_mutex);
3136         intel_update_fbc(dev);
3137         mutex_unlock(&dev->struct_mutex);
3138
3139         intel_crtc_update_cursor(crtc, true);
3140 }
3141
3142 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3143 {
3144         struct drm_device *dev = crtc->dev;
3145         struct drm_i915_private *dev_priv = dev->dev_private;
3146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3147         int pipe = intel_crtc->pipe;
3148         int plane = intel_crtc->plane;
3149         u32 reg, temp;
3150
3151         if (!intel_crtc->active)
3152                 return;
3153
3154         intel_crtc_wait_for_pending_flips(crtc);
3155         drm_vblank_off(dev, pipe);
3156         intel_crtc_update_cursor(crtc, false);
3157
3158         intel_disable_plane(dev_priv, plane, pipe);
3159
3160         if (dev_priv->cfb_plane == plane)
3161                 intel_disable_fbc(dev);
3162
3163         intel_disable_pipe(dev_priv, pipe);
3164
3165         /* Disable PF */
3166         I915_WRITE(PF_CTL(pipe), 0);
3167         I915_WRITE(PF_WIN_SZ(pipe), 0);
3168
3169         ironlake_fdi_disable(crtc);
3170
3171         /* This is a horrible layering violation; we should be doing this in
3172          * the connector/encoder ->prepare instead, but we don't always have
3173          * enough information there about the config to know whether it will
3174          * actually be necessary or just cause undesired flicker.
3175          */
3176         intel_disable_pch_ports(dev_priv, pipe);
3177
3178         intel_disable_transcoder(dev_priv, pipe);
3179
3180         if (HAS_PCH_CPT(dev)) {
3181                 /* disable TRANS_DP_CTL */
3182                 reg = TRANS_DP_CTL(pipe);
3183                 temp = I915_READ(reg);
3184                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3185                 temp |= TRANS_DP_PORT_SEL_NONE;
3186                 I915_WRITE(reg, temp);
3187
3188                 /* disable DPLL_SEL */
3189                 temp = I915_READ(PCH_DPLL_SEL);
3190                 switch (pipe) {
3191                 case 0:
3192                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3193                         break;
3194                 case 1:
3195                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3196                         break;
3197                 case 2:
3198                         /* C shares PLL A or B */
3199                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3200                         break;
3201                 default:
3202                         BUG(); /* wtf */
3203                 }
3204                 I915_WRITE(PCH_DPLL_SEL, temp);
3205         }
3206
3207         /* disable PCH DPLL */
3208         if (!intel_crtc->no_pll)
3209                 intel_disable_pch_pll(dev_priv, pipe);
3210
3211         /* Switch from PCDclk to Rawclk */
3212         reg = FDI_RX_CTL(pipe);
3213         temp = I915_READ(reg);
3214         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3215
3216         /* Disable CPU FDI TX PLL */
3217         reg = FDI_TX_CTL(pipe);
3218         temp = I915_READ(reg);
3219         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3220
3221         POSTING_READ(reg);
3222         udelay(100);
3223
3224         reg = FDI_RX_CTL(pipe);
3225         temp = I915_READ(reg);
3226         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3227
3228         /* Wait for the clocks to turn off. */
3229         POSTING_READ(reg);
3230         udelay(100);
3231
3232         intel_crtc->active = false;
3233         intel_update_watermarks(dev);
3234
3235         mutex_lock(&dev->struct_mutex);
3236         intel_update_fbc(dev);
3237         intel_clear_scanline_wait(dev);
3238         mutex_unlock(&dev->struct_mutex);
3239 }
3240
3241 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3242 {
3243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3244         int pipe = intel_crtc->pipe;
3245         int plane = intel_crtc->plane;
3246
3247         /* XXX: When our outputs are all unaware of DPMS modes other than off
3248          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3249          */
3250         switch (mode) {
3251         case DRM_MODE_DPMS_ON:
3252         case DRM_MODE_DPMS_STANDBY:
3253         case DRM_MODE_DPMS_SUSPEND:
3254                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3255                 ironlake_crtc_enable(crtc);
3256                 break;
3257
3258         case DRM_MODE_DPMS_OFF:
3259                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3260                 ironlake_crtc_disable(crtc);
3261                 break;
3262         }
3263 }
3264
3265 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3266 {
3267         if (!enable && intel_crtc->overlay) {
3268                 struct drm_device *dev = intel_crtc->base.dev;
3269                 struct drm_i915_private *dev_priv = dev->dev_private;
3270
3271                 mutex_lock(&dev->struct_mutex);
3272                 dev_priv->mm.interruptible = false;
3273                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3274                 dev_priv->mm.interruptible = true;
3275                 mutex_unlock(&dev->struct_mutex);
3276         }
3277
3278         /* Let userspace switch the overlay on again. In most cases userspace
3279          * has to recompute where to put it anyway.
3280          */
3281 }
3282
3283 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3284 {
3285         struct drm_device *dev = crtc->dev;
3286         struct drm_i915_private *dev_priv = dev->dev_private;
3287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3288         int pipe = intel_crtc->pipe;
3289         int plane = intel_crtc->plane;
3290
3291         if (intel_crtc->active)
3292                 return;
3293
3294         intel_crtc->active = true;
3295         intel_update_watermarks(dev);
3296
3297         intel_enable_pll(dev_priv, pipe);
3298         intel_enable_pipe(dev_priv, pipe, false);
3299         intel_enable_plane(dev_priv, plane, pipe);
3300
3301         intel_crtc_load_lut(crtc);
3302         intel_update_fbc(dev);
3303
3304         /* Give the overlay scaler a chance to enable if it's on this pipe */
3305         intel_crtc_dpms_overlay(intel_crtc, true);
3306         intel_crtc_update_cursor(crtc, true);
3307 }
3308
3309 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3310 {
3311         struct drm_device *dev = crtc->dev;
3312         struct drm_i915_private *dev_priv = dev->dev_private;
3313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3314         int pipe = intel_crtc->pipe;
3315         int plane = intel_crtc->plane;
3316
3317         if (!intel_crtc->active)
3318                 return;
3319
3320         /* Give the overlay scaler a chance to disable if it's on this pipe */
3321         intel_crtc_wait_for_pending_flips(crtc);
3322         drm_vblank_off(dev, pipe);
3323         intel_crtc_dpms_overlay(intel_crtc, false);
3324         intel_crtc_update_cursor(crtc, false);
3325
3326         if (dev_priv->cfb_plane == plane)
3327                 intel_disable_fbc(dev);
3328
3329         intel_disable_plane(dev_priv, plane, pipe);
3330         intel_disable_pipe(dev_priv, pipe);
3331         intel_disable_pll(dev_priv, pipe);
3332
3333         intel_crtc->active = false;
3334         intel_update_fbc(dev);
3335         intel_update_watermarks(dev);
3336         intel_clear_scanline_wait(dev);
3337 }
3338
3339 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3340 {
3341         /* XXX: When our outputs are all unaware of DPMS modes other than off
3342          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3343          */
3344         switch (mode) {
3345         case DRM_MODE_DPMS_ON:
3346         case DRM_MODE_DPMS_STANDBY:
3347         case DRM_MODE_DPMS_SUSPEND:
3348                 i9xx_crtc_enable(crtc);
3349                 break;
3350         case DRM_MODE_DPMS_OFF:
3351                 i9xx_crtc_disable(crtc);
3352                 break;
3353         }
3354 }
3355
3356 /**
3357  * Sets the power management mode of the pipe and plane.
3358  */
3359 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3360 {
3361         struct drm_device *dev = crtc->dev;
3362         struct drm_i915_private *dev_priv = dev->dev_private;
3363         struct drm_i915_master_private *master_priv;
3364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365         int pipe = intel_crtc->pipe;
3366         bool enabled;
3367
3368         if (intel_crtc->dpms_mode == mode)
3369                 return;
3370
3371         intel_crtc->dpms_mode = mode;
3372
3373         dev_priv->display.dpms(crtc, mode);
3374
3375         if (!dev->primary->master)
3376                 return;
3377
3378         master_priv = dev->primary->master->driver_priv;
3379         if (!master_priv->sarea_priv)
3380                 return;
3381
3382         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3383
3384         switch (pipe) {
3385         case 0:
3386                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3387                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3388                 break;
3389         case 1:
3390                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3391                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3392                 break;
3393         default:
3394                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3395                 break;
3396         }
3397 }
3398
3399 static void intel_crtc_disable(struct drm_crtc *crtc)
3400 {
3401         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3402         struct drm_device *dev = crtc->dev;
3403
3404         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3405         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3406         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3407
3408         if (crtc->fb) {
3409                 mutex_lock(&dev->struct_mutex);
3410                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3411                 mutex_unlock(&dev->struct_mutex);
3412         }
3413 }
3414
3415 /* Prepare for a mode set.
3416  *
3417  * Note we could be a lot smarter here.  We need to figure out which outputs
3418  * will be enabled, which disabled (in short, how the config will changes)
3419  * and perform the minimum necessary steps to accomplish that, e.g. updating
3420  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3421  * panel fitting is in the proper state, etc.
3422  */
3423 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3424 {
3425         i9xx_crtc_disable(crtc);
3426 }
3427
3428 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3429 {
3430         i9xx_crtc_enable(crtc);
3431 }
3432
3433 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3434 {
3435         ironlake_crtc_disable(crtc);
3436 }
3437
3438 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3439 {
3440         ironlake_crtc_enable(crtc);
3441 }
3442
3443 void intel_encoder_prepare(struct drm_encoder *encoder)
3444 {
3445         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3446         /* lvds has its own version of prepare see intel_lvds_prepare */
3447         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3448 }
3449
3450 void intel_encoder_commit(struct drm_encoder *encoder)
3451 {
3452         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3453         struct drm_device *dev = encoder->dev;
3454         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3455         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3456
3457         /* lvds has its own version of commit see intel_lvds_commit */
3458         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3459
3460         if (HAS_PCH_CPT(dev))
3461                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3462 }
3463
3464 void intel_encoder_destroy(struct drm_encoder *encoder)
3465 {
3466         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3467
3468         drm_encoder_cleanup(encoder);
3469         kfree(intel_encoder);
3470 }
3471
3472 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3473                                   struct drm_display_mode *mode,
3474                                   struct drm_display_mode *adjusted_mode)
3475 {
3476         struct drm_device *dev = crtc->dev;
3477
3478         if (HAS_PCH_SPLIT(dev)) {
3479                 /* FDI link clock is fixed at 2.7G */
3480                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3481                         return false;
3482         }
3483
3484         /* All interlaced capable intel hw wants timings in frames. */
3485         drm_mode_set_crtcinfo(adjusted_mode, 0);
3486
3487         return true;
3488 }
3489
3490 static int i945_get_display_clock_speed(struct drm_device *dev)
3491 {
3492         return 400000;
3493 }
3494
3495 static int i915_get_display_clock_speed(struct drm_device *dev)
3496 {
3497         return 333000;
3498 }
3499
3500 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3501 {
3502         return 200000;
3503 }
3504
3505 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3506 {
3507         u16 gcfgc = 0;
3508
3509         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3510
3511         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3512                 return 133000;
3513         else {
3514                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3515                 case GC_DISPLAY_CLOCK_333_MHZ:
3516                         return 333000;
3517                 default:
3518                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3519                         return 190000;
3520                 }
3521         }
3522 }
3523
3524 static int i865_get_display_clock_speed(struct drm_device *dev)
3525 {
3526         return 266000;
3527 }
3528
3529 static int i855_get_display_clock_speed(struct drm_device *dev)
3530 {
3531         u16 hpllcc = 0;
3532         /* Assume that the hardware is in the high speed state.  This
3533          * should be the default.
3534          */
3535         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3536         case GC_CLOCK_133_200:
3537         case GC_CLOCK_100_200:
3538                 return 200000;
3539         case GC_CLOCK_166_250:
3540                 return 250000;
3541         case GC_CLOCK_100_133:
3542                 return 133000;
3543         }
3544
3545         /* Shouldn't happen */
3546         return 0;
3547 }
3548
3549 static int i830_get_display_clock_speed(struct drm_device *dev)
3550 {
3551         return 133000;
3552 }
3553
3554 struct fdi_m_n {
3555         u32        tu;
3556         u32        gmch_m;
3557         u32        gmch_n;
3558         u32        link_m;
3559         u32        link_n;
3560 };
3561
3562 static void
3563 fdi_reduce_ratio(u32 *num, u32 *den)
3564 {
3565         while (*num > 0xffffff || *den > 0xffffff) {
3566                 *num >>= 1;
3567                 *den >>= 1;
3568         }
3569 }
3570
3571 static void
3572 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3573                      int link_clock, struct fdi_m_n *m_n)
3574 {
3575         m_n->tu = 64; /* default size */
3576
3577         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3578         m_n->gmch_m = bits_per_pixel * pixel_clock;
3579         m_n->gmch_n = link_clock * nlanes * 8;
3580         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3581
3582         m_n->link_m = pixel_clock;
3583         m_n->link_n = link_clock;
3584         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3585 }
3586
3587
3588 struct intel_watermark_params {
3589         unsigned long fifo_size;
3590         unsigned long max_wm;
3591         unsigned long default_wm;
3592         unsigned long guard_size;
3593         unsigned long cacheline_size;
3594 };
3595
3596 /* Pineview has different values for various configs */
3597 static const struct intel_watermark_params pineview_display_wm = {
3598         PINEVIEW_DISPLAY_FIFO,
3599         PINEVIEW_MAX_WM,
3600         PINEVIEW_DFT_WM,
3601         PINEVIEW_GUARD_WM,
3602         PINEVIEW_FIFO_LINE_SIZE
3603 };
3604 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3605         PINEVIEW_DISPLAY_FIFO,
3606         PINEVIEW_MAX_WM,
3607         PINEVIEW_DFT_HPLLOFF_WM,
3608         PINEVIEW_GUARD_WM,
3609         PINEVIEW_FIFO_LINE_SIZE
3610 };
3611 static const struct intel_watermark_params pineview_cursor_wm = {
3612         PINEVIEW_CURSOR_FIFO,
3613         PINEVIEW_CURSOR_MAX_WM,
3614         PINEVIEW_CURSOR_DFT_WM,
3615         PINEVIEW_CURSOR_GUARD_WM,
3616         PINEVIEW_FIFO_LINE_SIZE,
3617 };
3618 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3619         PINEVIEW_CURSOR_FIFO,
3620         PINEVIEW_CURSOR_MAX_WM,
3621         PINEVIEW_CURSOR_DFT_WM,
3622         PINEVIEW_CURSOR_GUARD_WM,
3623         PINEVIEW_FIFO_LINE_SIZE
3624 };
3625 static const struct intel_watermark_params g4x_wm_info = {
3626         G4X_FIFO_SIZE,
3627         G4X_MAX_WM,
3628         G4X_MAX_WM,
3629         2,
3630         G4X_FIFO_LINE_SIZE,
3631 };
3632 static const struct intel_watermark_params g4x_cursor_wm_info = {
3633         I965_CURSOR_FIFO,
3634         I965_CURSOR_MAX_WM,
3635         I965_CURSOR_DFT_WM,
3636         2,
3637         G4X_FIFO_LINE_SIZE,
3638 };
3639 static const struct intel_watermark_params i965_cursor_wm_info = {
3640         I965_CURSOR_FIFO,
3641         I965_CURSOR_MAX_WM,
3642         I965_CURSOR_DFT_WM,
3643         2,
3644         I915_FIFO_LINE_SIZE,
3645 };
3646 static const struct intel_watermark_params i945_wm_info = {
3647         I945_FIFO_SIZE,
3648         I915_MAX_WM,
3649         1,
3650         2,
3651         I915_FIFO_LINE_SIZE
3652 };
3653 static const struct intel_watermark_params i915_wm_info = {
3654         I915_FIFO_SIZE,
3655         I915_MAX_WM,
3656         1,
3657         2,
3658         I915_FIFO_LINE_SIZE
3659 };
3660 static const struct intel_watermark_params i855_wm_info = {
3661         I855GM_FIFO_SIZE,
3662         I915_MAX_WM,
3663         1,
3664         2,
3665         I830_FIFO_LINE_SIZE
3666 };
3667 static const struct intel_watermark_params i830_wm_info = {
3668         I830_FIFO_SIZE,
3669         I915_MAX_WM,
3670         1,
3671         2,
3672         I830_FIFO_LINE_SIZE
3673 };
3674
3675 static const struct intel_watermark_params ironlake_display_wm_info = {
3676         ILK_DISPLAY_FIFO,
3677         ILK_DISPLAY_MAXWM,
3678         ILK_DISPLAY_DFTWM,
3679         2,
3680         ILK_FIFO_LINE_SIZE
3681 };
3682 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3683         ILK_CURSOR_FIFO,
3684         ILK_CURSOR_MAXWM,
3685         ILK_CURSOR_DFTWM,
3686         2,
3687         ILK_FIFO_LINE_SIZE
3688 };
3689 static const struct intel_watermark_params ironlake_display_srwm_info = {
3690         ILK_DISPLAY_SR_FIFO,
3691         ILK_DISPLAY_MAX_SRWM,
3692         ILK_DISPLAY_DFT_SRWM,
3693         2,
3694         ILK_FIFO_LINE_SIZE
3695 };
3696 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3697         ILK_CURSOR_SR_FIFO,
3698         ILK_CURSOR_MAX_SRWM,
3699         ILK_CURSOR_DFT_SRWM,
3700         2,
3701         ILK_FIFO_LINE_SIZE
3702 };
3703
3704 static const struct intel_watermark_params sandybridge_display_wm_info = {
3705         SNB_DISPLAY_FIFO,
3706         SNB_DISPLAY_MAXWM,
3707         SNB_DISPLAY_DFTWM,
3708         2,
3709         SNB_FIFO_LINE_SIZE
3710 };
3711 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3712         SNB_CURSOR_FIFO,
3713         SNB_CURSOR_MAXWM,
3714         SNB_CURSOR_DFTWM,
3715         2,
3716         SNB_FIFO_LINE_SIZE
3717 };
3718 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3719         SNB_DISPLAY_SR_FIFO,
3720         SNB_DISPLAY_MAX_SRWM,
3721         SNB_DISPLAY_DFT_SRWM,
3722         2,
3723         SNB_FIFO_LINE_SIZE
3724 };
3725 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3726         SNB_CURSOR_SR_FIFO,
3727         SNB_CURSOR_MAX_SRWM,
3728         SNB_CURSOR_DFT_SRWM,
3729         2,
3730         SNB_FIFO_LINE_SIZE
3731 };
3732
3733
3734 /**
3735  * intel_calculate_wm - calculate watermark level
3736  * @clock_in_khz: pixel clock
3737  * @wm: chip FIFO params
3738  * @pixel_size: display pixel size
3739  * @latency_ns: memory latency for the platform
3740  *
3741  * Calculate the watermark level (the level at which the display plane will
3742  * start fetching from memory again).  Each chip has a different display
3743  * FIFO size and allocation, so the caller needs to figure that out and pass
3744  * in the correct intel_watermark_params structure.
3745  *
3746  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3747  * on the pixel size.  When it reaches the watermark level, it'll start
3748  * fetching FIFO line sized based chunks from memory until the FIFO fills
3749  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3750  * will occur, and a display engine hang could result.
3751  */
3752 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3753                                         const struct intel_watermark_params *wm,
3754                                         int fifo_size,
3755                                         int pixel_size,
3756                                         unsigned long latency_ns)
3757 {
3758         long entries_required, wm_size;
3759
3760         /*
3761          * Note: we need to make sure we don't overflow for various clock &
3762          * latency values.
3763          * clocks go from a few thousand to several hundred thousand.
3764          * latency is usually a few thousand
3765          */
3766         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3767                 1000;
3768         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3769
3770         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3771
3772         wm_size = fifo_size - (entries_required + wm->guard_size);
3773
3774         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3775
3776         /* Don't promote wm_size to unsigned... */
3777         if (wm_size > (long)wm->max_wm)
3778                 wm_size = wm->max_wm;
3779         if (wm_size <= 0)
3780                 wm_size = wm->default_wm;
3781         return wm_size;
3782 }
3783
3784 struct cxsr_latency {
3785         int is_desktop;
3786         int is_ddr3;
3787         unsigned long fsb_freq;
3788         unsigned long mem_freq;
3789         unsigned long display_sr;
3790         unsigned long display_hpll_disable;
3791         unsigned long cursor_sr;
3792         unsigned long cursor_hpll_disable;
3793 };
3794
3795 static const struct cxsr_latency cxsr_latency_table[] = {
3796         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3797         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3798         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3799         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3800         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3801
3802         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3803         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3804         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3805         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3806         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3807
3808         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3809         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3810         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3811         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3812         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3813
3814         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3815         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3816         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3817         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3818         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3819
3820         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3821         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3822         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3823         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3824         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3825
3826         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3827         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3828         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3829         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3830         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3831 };
3832
3833 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3834                                                          int is_ddr3,
3835                                                          int fsb,
3836                                                          int mem)
3837 {
3838         const struct cxsr_latency *latency;
3839         int i;
3840
3841         if (fsb == 0 || mem == 0)
3842                 return NULL;
3843
3844         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3845                 latency = &cxsr_latency_table[i];
3846                 if (is_desktop == latency->is_desktop &&
3847                     is_ddr3 == latency->is_ddr3 &&
3848                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3849                         return latency;
3850         }
3851
3852         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3853
3854         return NULL;
3855 }
3856
3857 static void pineview_disable_cxsr(struct drm_device *dev)
3858 {
3859         struct drm_i915_private *dev_priv = dev->dev_private;
3860
3861         /* deactivate cxsr */
3862         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3863 }
3864
3865 /*
3866  * Latency for FIFO fetches is dependent on several factors:
3867  *   - memory configuration (speed, channels)
3868  *   - chipset
3869  *   - current MCH state
3870  * It can be fairly high in some situations, so here we assume a fairly
3871  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3872  * set this value too high, the FIFO will fetch frequently to stay full)
3873  * and power consumption (set it too low to save power and we might see
3874  * FIFO underruns and display "flicker").
3875  *
3876  * A value of 5us seems to be a good balance; safe for very low end
3877  * platforms but not overly aggressive on lower latency configs.
3878  */
3879 static const int latency_ns = 5000;
3880
3881 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3882 {
3883         struct drm_i915_private *dev_priv = dev->dev_private;
3884         uint32_t dsparb = I915_READ(DSPARB);
3885         int size;
3886
3887         size = dsparb & 0x7f;
3888         if (plane)
3889                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3890
3891         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3892                       plane ? "B" : "A", size);
3893
3894         return size;
3895 }
3896
3897 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3898 {
3899         struct drm_i915_private *dev_priv = dev->dev_private;
3900         uint32_t dsparb = I915_READ(DSPARB);
3901         int size;
3902
3903         size = dsparb & 0x1ff;
3904         if (plane)
3905                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3906         size >>= 1; /* Convert to cachelines */
3907
3908         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3909                       plane ? "B" : "A", size);
3910
3911         return size;
3912 }
3913
3914 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3915 {
3916         struct drm_i915_private *dev_priv = dev->dev_private;
3917         uint32_t dsparb = I915_READ(DSPARB);
3918         int size;
3919
3920         size = dsparb & 0x7f;
3921         size >>= 2; /* Convert to cachelines */
3922
3923         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3924                       plane ? "B" : "A",
3925                       size);
3926
3927         return size;
3928 }
3929
3930 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3931 {
3932         struct drm_i915_private *dev_priv = dev->dev_private;
3933         uint32_t dsparb = I915_READ(DSPARB);
3934         int size;
3935
3936         size = dsparb & 0x7f;
3937         size >>= 1; /* Convert to cachelines */
3938
3939         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3940                       plane ? "B" : "A", size);
3941
3942         return size;
3943 }
3944
3945 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3946 {
3947         struct drm_crtc *crtc, *enabled = NULL;
3948
3949         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3950                 if (crtc->enabled && crtc->fb) {
3951                         if (enabled)
3952                                 return NULL;
3953                         enabled = crtc;
3954                 }
3955         }
3956
3957         return enabled;
3958 }
3959
3960 static void pineview_update_wm(struct drm_device *dev)
3961 {
3962         struct drm_i915_private *dev_priv = dev->dev_private;
3963         struct drm_crtc *crtc;
3964         const struct cxsr_latency *latency;
3965         u32 reg;
3966         unsigned long wm;
3967
3968         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3969                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3970         if (!latency) {
3971                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3972                 pineview_disable_cxsr(dev);
3973                 return;
3974         }
3975
3976         crtc = single_enabled_crtc(dev);
3977         if (crtc) {
3978                 int clock = crtc->mode.clock;
3979                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3980
3981                 /* Display SR */
3982                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3983                                         pineview_display_wm.fifo_size,
3984                                         pixel_size, latency->display_sr);
3985                 reg = I915_READ(DSPFW1);
3986                 reg &= ~DSPFW_SR_MASK;
3987                 reg |= wm << DSPFW_SR_SHIFT;
3988                 I915_WRITE(DSPFW1, reg);
3989                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3990
3991                 /* cursor SR */
3992                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3993                                         pineview_display_wm.fifo_size,
3994                                         pixel_size, latency->cursor_sr);
3995                 reg = I915_READ(DSPFW3);
3996                 reg &= ~DSPFW_CURSOR_SR_MASK;
3997                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3998                 I915_WRITE(DSPFW3, reg);
3999
4000                 /* Display HPLL off SR */
4001                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4002                                         pineview_display_hplloff_wm.fifo_size,
4003                                         pixel_size, latency->display_hpll_disable);
4004                 reg = I915_READ(DSPFW3);
4005                 reg &= ~DSPFW_HPLL_SR_MASK;
4006                 reg |= wm & DSPFW_HPLL_SR_MASK;
4007                 I915_WRITE(DSPFW3, reg);
4008
4009                 /* cursor HPLL off SR */
4010                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4011                                         pineview_display_hplloff_wm.fifo_size,
4012                                         pixel_size, latency->cursor_hpll_disable);
4013                 reg = I915_READ(DSPFW3);
4014                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4015                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4016                 I915_WRITE(DSPFW3, reg);
4017                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4018
4019                 /* activate cxsr */
4020                 I915_WRITE(DSPFW3,
4021                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4022                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4023         } else {
4024                 pineview_disable_cxsr(dev);
4025                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4026         }
4027 }
4028
4029 static bool g4x_compute_wm0(struct drm_device *dev,
4030                             int plane,
4031                             const struct intel_watermark_params *display,
4032                             int display_latency_ns,
4033                             const struct intel_watermark_params *cursor,
4034                             int cursor_latency_ns,
4035                             int *plane_wm,
4036                             int *cursor_wm)
4037 {
4038         struct drm_crtc *crtc;
4039         int htotal, hdisplay, clock, pixel_size;
4040         int line_time_us, line_count;
4041         int entries, tlb_miss;
4042
4043         crtc = intel_get_crtc_for_plane(dev, plane);
4044         if (crtc->fb == NULL || !crtc->enabled) {
4045                 *cursor_wm = cursor->guard_size;
4046                 *plane_wm = display->guard_size;
4047                 return false;
4048         }
4049
4050         htotal = crtc->mode.htotal;
4051         hdisplay = crtc->mode.hdisplay;
4052         clock = crtc->mode.clock;
4053         pixel_size = crtc->fb->bits_per_pixel / 8;
4054
4055         /* Use the small buffer method to calculate plane watermark */
4056         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4057         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4058         if (tlb_miss > 0)
4059                 entries += tlb_miss;
4060         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4061         *plane_wm = entries + display->guard_size;
4062         if (*plane_wm > (int)display->max_wm)
4063                 *plane_wm = display->max_wm;
4064
4065         /* Use the large buffer method to calculate cursor watermark */
4066         line_time_us = ((htotal * 1000) / clock);
4067         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4068         entries = line_count * 64 * pixel_size;
4069         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4070         if (tlb_miss > 0)
4071                 entries += tlb_miss;
4072         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4073         *cursor_wm = entries + cursor->guard_size;
4074         if (*cursor_wm > (int)cursor->max_wm)
4075                 *cursor_wm = (int)cursor->max_wm;
4076
4077         return true;
4078 }
4079
4080 /*
4081  * Check the wm result.
4082  *
4083  * If any calculated watermark values is larger than the maximum value that
4084  * can be programmed into the associated watermark register, that watermark
4085  * must be disabled.
4086  */
4087 static bool g4x_check_srwm(struct drm_device *dev,
4088                            int display_wm, int cursor_wm,
4089                            const struct intel_watermark_params *display,
4090                            const struct intel_watermark_params *cursor)
4091 {
4092         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4093                       display_wm, cursor_wm);
4094
4095         if (display_wm > display->max_wm) {
4096                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4097                               display_wm, display->max_wm);
4098                 return false;
4099         }
4100
4101         if (cursor_wm > cursor->max_wm) {
4102                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4103                               cursor_wm, cursor->max_wm);
4104                 return false;
4105         }
4106
4107         if (!(display_wm || cursor_wm)) {
4108                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4109                 return false;
4110         }
4111
4112         return true;
4113 }
4114
4115 static bool g4x_compute_srwm(struct drm_device *dev,
4116                              int plane,
4117                              int latency_ns,
4118                              const struct intel_watermark_params *display,
4119                              const struct intel_watermark_params *cursor,
4120                              int *display_wm, int *cursor_wm)
4121 {
4122         struct drm_crtc *crtc;
4123         int hdisplay, htotal, pixel_size, clock;
4124         unsigned long line_time_us;
4125         int line_count, line_size;
4126         int small, large;
4127         int entries;
4128
4129         if (!latency_ns) {
4130                 *display_wm = *cursor_wm = 0;
4131                 return false;
4132         }
4133
4134         crtc = intel_get_crtc_for_plane(dev, plane);
4135         hdisplay = crtc->mode.hdisplay;
4136         htotal = crtc->mode.htotal;
4137         clock = crtc->mode.clock;
4138         pixel_size = crtc->fb->bits_per_pixel / 8;
4139
4140         line_time_us = (htotal * 1000) / clock;
4141         line_count = (latency_ns / line_time_us + 1000) / 1000;
4142         line_size = hdisplay * pixel_size;
4143
4144         /* Use the minimum of the small and large buffer method for primary */
4145         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4146         large = line_count * line_size;
4147
4148         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4149         *display_wm = entries + display->guard_size;
4150
4151         /* calculate the self-refresh watermark for display cursor */
4152         entries = line_count * pixel_size * 64;
4153         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4154         *cursor_wm = entries + cursor->guard_size;
4155
4156         return g4x_check_srwm(dev,
4157                               *display_wm, *cursor_wm,
4158                               display, cursor);
4159 }
4160
4161 #define single_plane_enabled(mask) is_power_of_2(mask)
4162
4163 static void g4x_update_wm(struct drm_device *dev)
4164 {
4165         static const int sr_latency_ns = 12000;
4166         struct drm_i915_private *dev_priv = dev->dev_private;
4167         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4168         int plane_sr, cursor_sr;
4169         unsigned int enabled = 0;
4170
4171         if (g4x_compute_wm0(dev, 0,
4172                             &g4x_wm_info, latency_ns,
4173                             &g4x_cursor_wm_info, latency_ns,
4174                             &planea_wm, &cursora_wm))
4175                 enabled |= 1;
4176
4177         if (g4x_compute_wm0(dev, 1,
4178                             &g4x_wm_info, latency_ns,
4179                             &g4x_cursor_wm_info, latency_ns,
4180                             &planeb_wm, &cursorb_wm))
4181                 enabled |= 2;
4182
4183         plane_sr = cursor_sr = 0;
4184         if (single_plane_enabled(enabled) &&
4185             g4x_compute_srwm(dev, ffs(enabled) - 1,
4186                              sr_latency_ns,
4187                              &g4x_wm_info,
4188                              &g4x_cursor_wm_info,
4189                              &plane_sr, &cursor_sr))
4190                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4191         else
4192                 I915_WRITE(FW_BLC_SELF,
4193                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4194
4195         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4196                       planea_wm, cursora_wm,
4197                       planeb_wm, cursorb_wm,
4198                       plane_sr, cursor_sr);
4199
4200         I915_WRITE(DSPFW1,
4201                    (plane_sr << DSPFW_SR_SHIFT) |
4202                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4203                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4204                    planea_wm);
4205         I915_WRITE(DSPFW2,
4206                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4207                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4208         /* HPLL off in SR has some issues on G4x... disable it */
4209         I915_WRITE(DSPFW3,
4210                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4211                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4212 }
4213
4214 static void i965_update_wm(struct drm_device *dev)
4215 {
4216         struct drm_i915_private *dev_priv = dev->dev_private;
4217         struct drm_crtc *crtc;
4218         int srwm = 1;
4219         int cursor_sr = 16;
4220
4221         /* Calc sr entries for one plane configs */
4222         crtc = single_enabled_crtc(dev);
4223         if (crtc) {
4224                 /* self-refresh has much higher latency */
4225                 static const int sr_latency_ns = 12000;
4226                 int clock = crtc->mode.clock;
4227                 int htotal = crtc->mode.htotal;
4228                 int hdisplay = crtc->mode.hdisplay;
4229                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4230                 unsigned long line_time_us;
4231                 int entries;
4232
4233                 line_time_us = ((htotal * 1000) / clock);
4234
4235                 /* Use ns/us then divide to preserve precision */
4236                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4237                         pixel_size * hdisplay;
4238                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4239                 srwm = I965_FIFO_SIZE - entries;
4240                 if (srwm < 0)
4241                         srwm = 1;
4242                 srwm &= 0x1ff;
4243                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4244                               entries, srwm);
4245
4246                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4247                         pixel_size * 64;
4248                 entries = DIV_ROUND_UP(entries,
4249                                           i965_cursor_wm_info.cacheline_size);
4250                 cursor_sr = i965_cursor_wm_info.fifo_size -
4251                         (entries + i965_cursor_wm_info.guard_size);
4252
4253                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4254                         cursor_sr = i965_cursor_wm_info.max_wm;
4255
4256                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4257                               "cursor %d\n", srwm, cursor_sr);
4258
4259                 if (IS_CRESTLINE(dev))
4260                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4261         } else {
4262                 /* Turn off self refresh if both pipes are enabled */
4263                 if (IS_CRESTLINE(dev))
4264                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4265                                    & ~FW_BLC_SELF_EN);
4266         }
4267
4268         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4269                       srwm);
4270
4271         /* 965 has limitations... */
4272         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4273                    (8 << 16) | (8 << 8) | (8 << 0));
4274         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4275         /* update cursor SR watermark */
4276         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4277 }
4278
4279 static void i9xx_update_wm(struct drm_device *dev)
4280 {
4281         struct drm_i915_private *dev_priv = dev->dev_private;
4282         const struct intel_watermark_params *wm_info;
4283         uint32_t fwater_lo;
4284         uint32_t fwater_hi;
4285         int cwm, srwm = 1;
4286         int fifo_size;
4287         int planea_wm, planeb_wm;
4288         struct drm_crtc *crtc, *enabled = NULL;
4289
4290         if (IS_I945GM(dev))
4291                 wm_info = &i945_wm_info;
4292         else if (!IS_GEN2(dev))
4293                 wm_info = &i915_wm_info;
4294         else
4295                 wm_info = &i855_wm_info;
4296
4297         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4298         crtc = intel_get_crtc_for_plane(dev, 0);
4299         if (crtc->enabled && crtc->fb) {
4300                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4301                                                wm_info, fifo_size,
4302                                                crtc->fb->bits_per_pixel / 8,
4303                                                latency_ns);
4304                 enabled = crtc;
4305         } else
4306                 planea_wm = fifo_size - wm_info->guard_size;
4307
4308         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4309         crtc = intel_get_crtc_for_plane(dev, 1);
4310         if (crtc->enabled && crtc->fb) {
4311                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4312                                                wm_info, fifo_size,
4313                                                crtc->fb->bits_per_pixel / 8,
4314                                                latency_ns);
4315                 if (enabled == NULL)
4316                         enabled = crtc;
4317                 else
4318                         enabled = NULL;
4319         } else
4320                 planeb_wm = fifo_size - wm_info->guard_size;
4321
4322         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4323
4324         /*
4325          * Overlay gets an aggressive default since video jitter is bad.
4326          */
4327         cwm = 2;
4328
4329         /* Play safe and disable self-refresh before adjusting watermarks. */
4330         if (IS_I945G(dev) || IS_I945GM(dev))
4331                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4332         else if (IS_I915GM(dev))
4333                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4334
4335         /* Calc sr entries for one plane configs */
4336         if (HAS_FW_BLC(dev) && enabled) {
4337                 /* self-refresh has much higher latency */
4338                 static const int sr_latency_ns = 6000;
4339                 int clock = enabled->mode.clock;
4340                 int htotal = enabled->mode.htotal;
4341                 int hdisplay = enabled->mode.hdisplay;
4342                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4343                 unsigned long line_time_us;
4344                 int entries;
4345
4346                 line_time_us = (htotal * 1000) / clock;
4347
4348                 /* Use ns/us then divide to preserve precision */
4349                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4350                         pixel_size * hdisplay;
4351                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4352                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4353                 srwm = wm_info->fifo_size - entries;
4354                 if (srwm < 0)
4355                         srwm = 1;
4356
4357                 if (IS_I945G(dev) || IS_I945GM(dev))
4358                         I915_WRITE(FW_BLC_SELF,
4359                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4360                 else if (IS_I915GM(dev))
4361                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4362         }
4363
4364         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4365                       planea_wm, planeb_wm, cwm, srwm);
4366
4367         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4368         fwater_hi = (cwm & 0x1f);
4369
4370         /* Set request length to 8 cachelines per fetch */
4371         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4372         fwater_hi = fwater_hi | (1 << 8);
4373
4374         I915_WRITE(FW_BLC, fwater_lo);
4375         I915_WRITE(FW_BLC2, fwater_hi);
4376
4377         if (HAS_FW_BLC(dev)) {
4378                 if (enabled) {
4379                         if (IS_I945G(dev) || IS_I945GM(dev))
4380                                 I915_WRITE(FW_BLC_SELF,
4381                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4382                         else if (IS_I915GM(dev))
4383                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4384                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4385                 } else
4386                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4387         }
4388 }
4389
4390 static void i830_update_wm(struct drm_device *dev)
4391 {
4392         struct drm_i915_private *dev_priv = dev->dev_private;
4393         struct drm_crtc *crtc;
4394         uint32_t fwater_lo;
4395         int planea_wm;
4396
4397         crtc = single_enabled_crtc(dev);
4398         if (crtc == NULL)
4399                 return;
4400
4401         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4402                                        dev_priv->display.get_fifo_size(dev, 0),
4403                                        crtc->fb->bits_per_pixel / 8,
4404                                        latency_ns);
4405         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4406         fwater_lo |= (3<<8) | planea_wm;
4407
4408         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4409
4410         I915_WRITE(FW_BLC, fwater_lo);
4411 }
4412
4413 #define ILK_LP0_PLANE_LATENCY           700
4414 #define ILK_LP0_CURSOR_LATENCY          1300
4415
4416 /*
4417  * Check the wm result.
4418  *
4419  * If any calculated watermark values is larger than the maximum value that
4420  * can be programmed into the associated watermark register, that watermark
4421  * must be disabled.
4422  */
4423 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4424                                 int fbc_wm, int display_wm, int cursor_wm,
4425                                 const struct intel_watermark_params *display,
4426                                 const struct intel_watermark_params *cursor)
4427 {
4428         struct drm_i915_private *dev_priv = dev->dev_private;
4429
4430         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4431                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4432
4433         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4434                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4435                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4436
4437                 /* fbc has it's own way to disable FBC WM */
4438                 I915_WRITE(DISP_ARB_CTL,
4439                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4440                 return false;
4441         }
4442
4443         if (display_wm > display->max_wm) {
4444                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4445                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4446                 return false;
4447         }
4448
4449         if (cursor_wm > cursor->max_wm) {
4450                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4451                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4452                 return false;
4453         }
4454
4455         if (!(fbc_wm || display_wm || cursor_wm)) {
4456                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4457                 return false;
4458         }
4459
4460         return true;
4461 }
4462
4463 /*
4464  * Compute watermark values of WM[1-3],
4465  */
4466 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4467                                   int latency_ns,
4468                                   const struct intel_watermark_params *display,
4469                                   const struct intel_watermark_params *cursor,
4470                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4471 {
4472         struct drm_crtc *crtc;
4473         unsigned long line_time_us;
4474         int hdisplay, htotal, pixel_size, clock;
4475         int line_count, line_size;
4476         int small, large;
4477         int entries;
4478
4479         if (!latency_ns) {
4480                 *fbc_wm = *display_wm = *cursor_wm = 0;
4481                 return false;
4482         }
4483
4484         crtc = intel_get_crtc_for_plane(dev, plane);
4485         hdisplay = crtc->mode.hdisplay;
4486         htotal = crtc->mode.htotal;
4487         clock = crtc->mode.clock;
4488         pixel_size = crtc->fb->bits_per_pixel / 8;
4489
4490         line_time_us = (htotal * 1000) / clock;
4491         line_count = (latency_ns / line_time_us + 1000) / 1000;
4492         line_size = hdisplay * pixel_size;
4493
4494         /* Use the minimum of the small and large buffer method for primary */
4495         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4496         large = line_count * line_size;
4497
4498         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4499         *display_wm = entries + display->guard_size;
4500
4501         /*
4502          * Spec says:
4503          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4504          */
4505         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4506
4507         /* calculate the self-refresh watermark for display cursor */
4508         entries = line_count * pixel_size * 64;
4509         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4510         *cursor_wm = entries + cursor->guard_size;
4511
4512         return ironlake_check_srwm(dev, level,
4513                                    *fbc_wm, *display_wm, *cursor_wm,
4514                                    display, cursor);
4515 }
4516
4517 static void ironlake_update_wm(struct drm_device *dev)
4518 {
4519         struct drm_i915_private *dev_priv = dev->dev_private;
4520         int fbc_wm, plane_wm, cursor_wm;
4521         unsigned int enabled;
4522
4523         enabled = 0;
4524         if (g4x_compute_wm0(dev, 0,
4525                             &ironlake_display_wm_info,
4526                             ILK_LP0_PLANE_LATENCY,
4527                             &ironlake_cursor_wm_info,
4528                             ILK_LP0_CURSOR_LATENCY,
4529                             &plane_wm, &cursor_wm)) {
4530                 I915_WRITE(WM0_PIPEA_ILK,
4531                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4532                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4533                               " plane %d, " "cursor: %d\n",
4534                               plane_wm, cursor_wm);
4535                 enabled |= 1;
4536         }
4537
4538         if (g4x_compute_wm0(dev, 1,
4539                             &ironlake_display_wm_info,
4540                             ILK_LP0_PLANE_LATENCY,
4541                             &ironlake_cursor_wm_info,
4542                             ILK_LP0_CURSOR_LATENCY,
4543                             &plane_wm, &cursor_wm)) {
4544                 I915_WRITE(WM0_PIPEB_ILK,
4545                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4546                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4547                               " plane %d, cursor: %d\n",
4548                               plane_wm, cursor_wm);
4549                 enabled |= 2;
4550         }
4551
4552         /*
4553          * Calculate and update the self-refresh watermark only when one
4554          * display plane is used.
4555          */
4556         I915_WRITE(WM3_LP_ILK, 0);
4557         I915_WRITE(WM2_LP_ILK, 0);
4558         I915_WRITE(WM1_LP_ILK, 0);
4559
4560         if (!single_plane_enabled(enabled))
4561                 return;
4562         enabled = ffs(enabled) - 1;
4563
4564         /* WM1 */
4565         if (!ironlake_compute_srwm(dev, 1, enabled,
4566                                    ILK_READ_WM1_LATENCY() * 500,
4567                                    &ironlake_display_srwm_info,
4568                                    &ironlake_cursor_srwm_info,
4569                                    &fbc_wm, &plane_wm, &cursor_wm))
4570                 return;
4571
4572         I915_WRITE(WM1_LP_ILK,
4573                    WM1_LP_SR_EN |
4574                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4575                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4576                    (plane_wm << WM1_LP_SR_SHIFT) |
4577                    cursor_wm);
4578
4579         /* WM2 */
4580         if (!ironlake_compute_srwm(dev, 2, enabled,
4581                                    ILK_READ_WM2_LATENCY() * 500,
4582                                    &ironlake_display_srwm_info,
4583                                    &ironlake_cursor_srwm_info,
4584                                    &fbc_wm, &plane_wm, &cursor_wm))
4585                 return;
4586
4587         I915_WRITE(WM2_LP_ILK,
4588                    WM2_LP_EN |
4589                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4590                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4591                    (plane_wm << WM1_LP_SR_SHIFT) |
4592                    cursor_wm);
4593
4594         /*
4595          * WM3 is unsupported on ILK, probably because we don't have latency
4596          * data for that power state
4597          */
4598 }
4599
4600 void sandybridge_update_wm(struct drm_device *dev)
4601 {
4602         struct drm_i915_private *dev_priv = dev->dev_private;
4603         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4604         u32 val;
4605         int fbc_wm, plane_wm, cursor_wm;
4606         unsigned int enabled;
4607
4608         enabled = 0;
4609         if (g4x_compute_wm0(dev, 0,
4610                             &sandybridge_display_wm_info, latency,
4611                             &sandybridge_cursor_wm_info, latency,
4612                             &plane_wm, &cursor_wm)) {
4613                 val = I915_READ(WM0_PIPEA_ILK);
4614                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4615                 I915_WRITE(WM0_PIPEA_ILK, val |
4616                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4617                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4618                               " plane %d, " "cursor: %d\n",
4619                               plane_wm, cursor_wm);
4620                 enabled |= 1;
4621         }
4622
4623         if (g4x_compute_wm0(dev, 1,
4624                             &sandybridge_display_wm_info, latency,
4625                             &sandybridge_cursor_wm_info, latency,
4626                             &plane_wm, &cursor_wm)) {
4627                 val = I915_READ(WM0_PIPEB_ILK);
4628                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4629                 I915_WRITE(WM0_PIPEB_ILK, val |
4630                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4631                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4632                               " plane %d, cursor: %d\n",
4633                               plane_wm, cursor_wm);
4634                 enabled |= 2;
4635         }
4636
4637         /* IVB has 3 pipes */
4638         if (IS_IVYBRIDGE(dev) &&
4639             g4x_compute_wm0(dev, 2,
4640                             &sandybridge_display_wm_info, latency,
4641                             &sandybridge_cursor_wm_info, latency,
4642                             &plane_wm, &cursor_wm)) {
4643                 val = I915_READ(WM0_PIPEC_IVB);
4644                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4645                 I915_WRITE(WM0_PIPEC_IVB, val |
4646                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4647                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4648                               " plane %d, cursor: %d\n",
4649                               plane_wm, cursor_wm);
4650                 enabled |= 3;
4651         }
4652
4653         /*
4654          * Calculate and update the self-refresh watermark only when one
4655          * display plane is used.
4656          *
4657          * SNB support 3 levels of watermark.
4658          *
4659          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4660          * and disabled in the descending order
4661          *
4662          */
4663         I915_WRITE(WM3_LP_ILK, 0);
4664         I915_WRITE(WM2_LP_ILK, 0);
4665         I915_WRITE(WM1_LP_ILK, 0);
4666
4667         if (!single_plane_enabled(enabled) ||
4668             dev_priv->sprite_scaling_enabled)
4669                 return;
4670         enabled = ffs(enabled) - 1;
4671
4672         /* WM1 */
4673         if (!ironlake_compute_srwm(dev, 1, enabled,
4674                                    SNB_READ_WM1_LATENCY() * 500,
4675                                    &sandybridge_display_srwm_info,
4676                                    &sandybridge_cursor_srwm_info,
4677                                    &fbc_wm, &plane_wm, &cursor_wm))
4678                 return;
4679
4680         I915_WRITE(WM1_LP_ILK,
4681                    WM1_LP_SR_EN |
4682                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4683                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4684                    (plane_wm << WM1_LP_SR_SHIFT) |
4685                    cursor_wm);
4686
4687         /* WM2 */
4688         if (!ironlake_compute_srwm(dev, 2, enabled,
4689                                    SNB_READ_WM2_LATENCY() * 500,
4690                                    &sandybridge_display_srwm_info,
4691                                    &sandybridge_cursor_srwm_info,
4692                                    &fbc_wm, &plane_wm, &cursor_wm))
4693                 return;
4694
4695         I915_WRITE(WM2_LP_ILK,
4696                    WM2_LP_EN |
4697                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4698                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4699                    (plane_wm << WM1_LP_SR_SHIFT) |
4700                    cursor_wm);
4701
4702         /* WM3 */
4703         if (!ironlake_compute_srwm(dev, 3, enabled,
4704                                    SNB_READ_WM3_LATENCY() * 500,
4705                                    &sandybridge_display_srwm_info,
4706                                    &sandybridge_cursor_srwm_info,
4707                                    &fbc_wm, &plane_wm, &cursor_wm))
4708                 return;
4709
4710         I915_WRITE(WM3_LP_ILK,
4711                    WM3_LP_EN |
4712                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4713                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4714                    (plane_wm << WM1_LP_SR_SHIFT) |
4715                    cursor_wm);
4716 }
4717
4718 static bool
4719 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4720                               uint32_t sprite_width, int pixel_size,
4721                               const struct intel_watermark_params *display,
4722                               int display_latency_ns, int *sprite_wm)
4723 {
4724         struct drm_crtc *crtc;
4725         int clock;
4726         int entries, tlb_miss;
4727
4728         crtc = intel_get_crtc_for_plane(dev, plane);
4729         if (crtc->fb == NULL || !crtc->enabled) {
4730                 *sprite_wm = display->guard_size;
4731                 return false;
4732         }
4733
4734         clock = crtc->mode.clock;
4735
4736         /* Use the small buffer method to calculate the sprite watermark */
4737         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4738         tlb_miss = display->fifo_size*display->cacheline_size -
4739                 sprite_width * 8;
4740         if (tlb_miss > 0)
4741                 entries += tlb_miss;
4742         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4743         *sprite_wm = entries + display->guard_size;
4744         if (*sprite_wm > (int)display->max_wm)
4745                 *sprite_wm = display->max_wm;
4746
4747         return true;
4748 }
4749
4750 static bool
4751 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4752                                 uint32_t sprite_width, int pixel_size,
4753                                 const struct intel_watermark_params *display,
4754                                 int latency_ns, int *sprite_wm)
4755 {
4756         struct drm_crtc *crtc;
4757         unsigned long line_time_us;
4758         int clock;
4759         int line_count, line_size;
4760         int small, large;
4761         int entries;
4762
4763         if (!latency_ns) {
4764                 *sprite_wm = 0;
4765                 return false;
4766         }
4767
4768         crtc = intel_get_crtc_for_plane(dev, plane);
4769         clock = crtc->mode.clock;
4770
4771         line_time_us = (sprite_width * 1000) / clock;
4772         line_count = (latency_ns / line_time_us + 1000) / 1000;
4773         line_size = sprite_width * pixel_size;
4774
4775         /* Use the minimum of the small and large buffer method for primary */
4776         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4777         large = line_count * line_size;
4778
4779         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4780         *sprite_wm = entries + display->guard_size;
4781
4782         return *sprite_wm > 0x3ff ? false : true;
4783 }
4784
4785 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4786                                          uint32_t sprite_width, int pixel_size)
4787 {
4788         struct drm_i915_private *dev_priv = dev->dev_private;
4789         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4790         u32 val;
4791         int sprite_wm, reg;
4792         int ret;
4793
4794         switch (pipe) {
4795         case 0:
4796                 reg = WM0_PIPEA_ILK;
4797                 break;
4798         case 1:
4799                 reg = WM0_PIPEB_ILK;
4800                 break;
4801         case 2:
4802                 reg = WM0_PIPEC_IVB;
4803                 break;
4804         default:
4805                 return; /* bad pipe */
4806         }
4807
4808         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4809                                             &sandybridge_display_wm_info,
4810                                             latency, &sprite_wm);
4811         if (!ret) {
4812                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4813                               pipe);
4814                 return;
4815         }
4816
4817         val = I915_READ(reg);
4818         val &= ~WM0_PIPE_SPRITE_MASK;
4819         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4820         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4821
4822
4823         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4824                                               pixel_size,
4825                                               &sandybridge_display_srwm_info,
4826                                               SNB_READ_WM1_LATENCY() * 500,
4827                                               &sprite_wm);
4828         if (!ret) {
4829                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4830                               pipe);
4831                 return;
4832         }
4833         I915_WRITE(WM1S_LP_ILK, sprite_wm);
4834
4835         /* Only IVB has two more LP watermarks for sprite */
4836         if (!IS_IVYBRIDGE(dev))
4837                 return;
4838
4839         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4840                                               pixel_size,
4841                                               &sandybridge_display_srwm_info,
4842                                               SNB_READ_WM2_LATENCY() * 500,
4843                                               &sprite_wm);
4844         if (!ret) {
4845                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4846                               pipe);
4847                 return;
4848         }
4849         I915_WRITE(WM2S_LP_IVB, sprite_wm);
4850
4851         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4852                                               pixel_size,
4853                                               &sandybridge_display_srwm_info,
4854                                               SNB_READ_WM3_LATENCY() * 500,
4855                                               &sprite_wm);
4856         if (!ret) {
4857                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4858                               pipe);
4859                 return;
4860         }
4861         I915_WRITE(WM3S_LP_IVB, sprite_wm);
4862 }
4863
4864 /**
4865  * intel_update_watermarks - update FIFO watermark values based on current modes
4866  *
4867  * Calculate watermark values for the various WM regs based on current mode
4868  * and plane configuration.
4869  *
4870  * There are several cases to deal with here:
4871  *   - normal (i.e. non-self-refresh)
4872  *   - self-refresh (SR) mode
4873  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4874  *   - lines are small relative to FIFO size (buffer can hold more than 2
4875  *     lines), so need to account for TLB latency
4876  *
4877  *   The normal calculation is:
4878  *     watermark = dotclock * bytes per pixel * latency
4879  *   where latency is platform & configuration dependent (we assume pessimal
4880  *   values here).
4881  *
4882  *   The SR calculation is:
4883  *     watermark = (trunc(latency/line time)+1) * surface width *
4884  *       bytes per pixel
4885  *   where
4886  *     line time = htotal / dotclock
4887  *     surface width = hdisplay for normal plane and 64 for cursor
4888  *   and latency is assumed to be high, as above.
4889  *
4890  * The final value programmed to the register should always be rounded up,
4891  * and include an extra 2 entries to account for clock crossings.
4892  *
4893  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4894  * to set the non-SR watermarks to 8.
4895  */
4896 static void intel_update_watermarks(struct drm_device *dev)
4897 {
4898         struct drm_i915_private *dev_priv = dev->dev_private;
4899
4900         if (dev_priv->display.update_wm)
4901                 dev_priv->display.update_wm(dev);
4902 }
4903
4904 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4905                                     uint32_t sprite_width, int pixel_size)
4906 {
4907         struct drm_i915_private *dev_priv = dev->dev_private;
4908
4909         if (dev_priv->display.update_sprite_wm)
4910                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4911                                                    pixel_size);
4912 }
4913
4914 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4915 {
4916         if (i915_panel_use_ssc >= 0)
4917                 return i915_panel_use_ssc != 0;
4918         return dev_priv->lvds_use_ssc
4919                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4920 }
4921
4922 /**
4923  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4924  * @crtc: CRTC structure
4925  * @mode: requested mode
4926  *
4927  * A pipe may be connected to one or more outputs.  Based on the depth of the
4928  * attached framebuffer, choose a good color depth to use on the pipe.
4929  *
4930  * If possible, match the pipe depth to the fb depth.  In some cases, this
4931  * isn't ideal, because the connected output supports a lesser or restricted
4932  * set of depths.  Resolve that here:
4933  *    LVDS typically supports only 6bpc, so clamp down in that case
4934  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4935  *    Displays may support a restricted set as well, check EDID and clamp as
4936  *      appropriate.
4937  *    DP may want to dither down to 6bpc to fit larger modes
4938  *
4939  * RETURNS:
4940  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4941  * true if they don't match).
4942  */
4943 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4944                                          unsigned int *pipe_bpp,
4945                                          struct drm_display_mode *mode)
4946 {
4947         struct drm_device *dev = crtc->dev;
4948         struct drm_i915_private *dev_priv = dev->dev_private;
4949         struct drm_encoder *encoder;
4950         struct drm_connector *connector;
4951         unsigned int display_bpc = UINT_MAX, bpc;
4952
4953         /* Walk the encoders & connectors on this crtc, get min bpc */
4954         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4955                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4956
4957                 if (encoder->crtc != crtc)
4958                         continue;
4959
4960                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4961                         unsigned int lvds_bpc;
4962
4963                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4964                             LVDS_A3_POWER_UP)
4965                                 lvds_bpc = 8;
4966                         else
4967                                 lvds_bpc = 6;
4968
4969                         if (lvds_bpc < display_bpc) {
4970                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4971                                 display_bpc = lvds_bpc;
4972                         }
4973                         continue;
4974                 }
4975
4976                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4977                         /* Use VBT settings if we have an eDP panel */
4978                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4979
4980                         if (edp_bpc < display_bpc) {
4981                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4982                                 display_bpc = edp_bpc;
4983                         }
4984                         continue;
4985                 }
4986
4987                 /* Not one of the known troublemakers, check the EDID */
4988                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4989                                     head) {
4990                         if (connector->encoder != encoder)
4991                                 continue;
4992
4993                         /* Don't use an invalid EDID bpc value */
4994                         if (connector->display_info.bpc &&
4995                             connector->display_info.bpc < display_bpc) {
4996                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4997                                 display_bpc = connector->display_info.bpc;
4998                         }
4999                 }
5000
5001                 /*
5002                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5003                  * through, clamp it down.  (Note: >12bpc will be caught below.)
5004                  */
5005                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5006                         if (display_bpc > 8 && display_bpc < 12) {
5007                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5008                                 display_bpc = 12;
5009                         } else {
5010                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5011                                 display_bpc = 8;
5012                         }
5013                 }
5014         }
5015
5016         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5017                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5018                 display_bpc = 6;
5019         }
5020
5021         /*
5022          * We could just drive the pipe at the highest bpc all the time and
5023          * enable dithering as needed, but that costs bandwidth.  So choose
5024          * the minimum value that expresses the full color range of the fb but
5025          * also stays within the max display bpc discovered above.
5026          */
5027
5028         switch (crtc->fb->depth) {
5029         case 8:
5030                 bpc = 8; /* since we go through a colormap */
5031                 break;
5032         case 15:
5033         case 16:
5034                 bpc = 6; /* min is 18bpp */
5035                 break;
5036         case 24:
5037                 bpc = 8;
5038                 break;
5039         case 30:
5040                 bpc = 10;
5041                 break;
5042         case 48:
5043                 bpc = 12;
5044                 break;
5045         default:
5046                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5047                 bpc = min((unsigned int)8, display_bpc);
5048                 break;
5049         }
5050
5051         display_bpc = min(display_bpc, bpc);
5052
5053         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5054                       bpc, display_bpc);
5055
5056         *pipe_bpp = display_bpc * 3;
5057
5058         return display_bpc != bpc;
5059 }
5060
5061 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5062 {
5063         struct drm_device *dev = crtc->dev;
5064         struct drm_i915_private *dev_priv = dev->dev_private;
5065         int refclk;
5066
5067         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5068             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5069                 refclk = dev_priv->lvds_ssc_freq * 1000;
5070                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5071                               refclk / 1000);
5072         } else if (!IS_GEN2(dev)) {
5073                 refclk = 96000;
5074         } else {
5075                 refclk = 48000;
5076         }
5077
5078         return refclk;
5079 }
5080
5081 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5082                                       intel_clock_t *clock)
5083 {
5084         /* SDVO TV has fixed PLL values depend on its clock range,
5085            this mirrors vbios setting. */
5086         if (adjusted_mode->clock >= 100000
5087             && adjusted_mode->clock < 140500) {
5088                 clock->p1 = 2;
5089                 clock->p2 = 10;
5090                 clock->n = 3;
5091                 clock->m1 = 16;
5092                 clock->m2 = 8;
5093         } else if (adjusted_mode->clock >= 140500
5094                    && adjusted_mode->clock <= 200000) {
5095                 clock->p1 = 1;
5096                 clock->p2 = 10;
5097                 clock->n = 6;
5098                 clock->m1 = 12;
5099                 clock->m2 = 8;
5100         }
5101 }
5102
5103 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5104                                      intel_clock_t *clock,
5105                                      intel_clock_t *reduced_clock)
5106 {
5107         struct drm_device *dev = crtc->dev;
5108         struct drm_i915_private *dev_priv = dev->dev_private;
5109         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5110         int pipe = intel_crtc->pipe;
5111         u32 fp, fp2 = 0;
5112
5113         if (IS_PINEVIEW(dev)) {
5114                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5115                 if (reduced_clock)
5116                         fp2 = (1 << reduced_clock->n) << 16 |
5117                                 reduced_clock->m1 << 8 | reduced_clock->m2;
5118         } else {
5119                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5120                 if (reduced_clock)
5121                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5122                                 reduced_clock->m2;
5123         }
5124
5125         I915_WRITE(FP0(pipe), fp);
5126
5127         intel_crtc->lowfreq_avail = false;
5128         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5129             reduced_clock && i915_powersave) {
5130                 I915_WRITE(FP1(pipe), fp2);
5131                 intel_crtc->lowfreq_avail = true;
5132         } else {
5133                 I915_WRITE(FP1(pipe), fp);
5134         }
5135 }
5136
5137 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
5138                               struct drm_display_mode *adjusted_mode)
5139 {
5140         struct drm_device *dev = crtc->dev;
5141         struct drm_i915_private *dev_priv = dev->dev_private;
5142         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5143         int pipe = intel_crtc->pipe;
5144         u32 temp, lvds_sync = 0;
5145
5146         temp = I915_READ(LVDS);
5147         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5148         if (pipe == 1) {
5149                 temp |= LVDS_PIPEB_SELECT;
5150         } else {
5151                 temp &= ~LVDS_PIPEB_SELECT;
5152         }
5153         /* set the corresponsding LVDS_BORDER bit */
5154         temp |= dev_priv->lvds_border_bits;
5155         /* Set the B0-B3 data pairs corresponding to whether we're going to
5156          * set the DPLLs for dual-channel mode or not.
5157          */
5158         if (clock->p2 == 7)
5159                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5160         else
5161                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5162
5163         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5164          * appropriately here, but we need to look more thoroughly into how
5165          * panels behave in the two modes.
5166          */
5167         /* set the dithering flag on LVDS as needed */
5168         if (INTEL_INFO(dev)->gen >= 4) {
5169                 if (dev_priv->lvds_dither)
5170                         temp |= LVDS_ENABLE_DITHER;
5171                 else
5172                         temp &= ~LVDS_ENABLE_DITHER;
5173         }
5174         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5175                 lvds_sync |= LVDS_HSYNC_POLARITY;
5176         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5177                 lvds_sync |= LVDS_VSYNC_POLARITY;
5178         if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5179             != lvds_sync) {
5180                 char flags[2] = "-+";
5181                 DRM_INFO("Changing LVDS panel from "
5182                          "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5183                          flags[!(temp & LVDS_HSYNC_POLARITY)],
5184                          flags[!(temp & LVDS_VSYNC_POLARITY)],
5185                          flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5186                          flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5187                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5188                 temp |= lvds_sync;
5189         }
5190         I915_WRITE(LVDS, temp);
5191 }
5192
5193 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5194                               struct drm_display_mode *mode,
5195                               struct drm_display_mode *adjusted_mode,
5196                               int x, int y,
5197                               struct drm_framebuffer *old_fb)
5198 {
5199         struct drm_device *dev = crtc->dev;
5200         struct drm_i915_private *dev_priv = dev->dev_private;
5201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5202         int pipe = intel_crtc->pipe;
5203         int plane = intel_crtc->plane;
5204         int refclk, num_connectors = 0;
5205         intel_clock_t clock, reduced_clock;
5206         u32 dpll, dspcntr, pipeconf, vsyncshift;
5207         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5208         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5209         struct drm_mode_config *mode_config = &dev->mode_config;
5210         struct intel_encoder *encoder;
5211         const intel_limit_t *limit;
5212         int ret;
5213         u32 temp;
5214
5215         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5216                 if (encoder->base.crtc != crtc)
5217                         continue;
5218
5219                 switch (encoder->type) {
5220                 case INTEL_OUTPUT_LVDS:
5221                         is_lvds = true;
5222                         break;
5223                 case INTEL_OUTPUT_SDVO:
5224                 case INTEL_OUTPUT_HDMI:
5225                         is_sdvo = true;
5226                         if (encoder->needs_tv_clock)
5227                                 is_tv = true;
5228                         break;
5229                 case INTEL_OUTPUT_DVO:
5230                         is_dvo = true;
5231                         break;
5232                 case INTEL_OUTPUT_TVOUT:
5233                         is_tv = true;
5234                         break;
5235                 case INTEL_OUTPUT_ANALOG:
5236                         is_crt = true;
5237                         break;
5238                 case INTEL_OUTPUT_DISPLAYPORT:
5239                         is_dp = true;
5240                         break;
5241                 }
5242
5243                 num_connectors++;
5244         }
5245
5246         refclk = i9xx_get_refclk(crtc, num_connectors);
5247
5248         /*
5249          * Returns a set of divisors for the desired target clock with the given
5250          * refclk, or FALSE.  The returned values represent the clock equation:
5251          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5252          */
5253         limit = intel_limit(crtc, refclk);
5254         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5255                              &clock);
5256         if (!ok) {
5257                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5258                 return -EINVAL;
5259         }
5260
5261         /* Ensure that the cursor is valid for the new mode before changing... */
5262         intel_crtc_update_cursor(crtc, true);
5263
5264         if (is_lvds && dev_priv->lvds_downclock_avail) {
5265                 /*
5266                  * Ensure we match the reduced clock's P to the target clock.
5267                  * If the clocks don't match, we can't switch the display clock
5268                  * by using the FP0/FP1. In such case we will disable the LVDS
5269                  * downclock feature.
5270                 */
5271                 has_reduced_clock = limit->find_pll(limit, crtc,
5272                                                     dev_priv->lvds_downclock,
5273                                                     refclk,
5274                                                     &clock,
5275                                                     &reduced_clock);
5276         }
5277
5278         if (is_sdvo && is_tv)
5279                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5280
5281         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5282                                  &reduced_clock : NULL);
5283
5284         dpll = DPLL_VGA_MODE_DIS;
5285
5286         if (!IS_GEN2(dev)) {
5287                 if (is_lvds)
5288                         dpll |= DPLLB_MODE_LVDS;
5289                 else
5290                         dpll |= DPLLB_MODE_DAC_SERIAL;
5291                 if (is_sdvo) {
5292                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5293                         if (pixel_multiplier > 1) {
5294                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5295                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5296                         }
5297                         dpll |= DPLL_DVO_HIGH_SPEED;
5298                 }
5299                 if (is_dp)
5300                         dpll |= DPLL_DVO_HIGH_SPEED;
5301
5302                 /* compute bitmask from p1 value */
5303                 if (IS_PINEVIEW(dev))
5304                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5305                 else {
5306                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5307                         if (IS_G4X(dev) && has_reduced_clock)
5308                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5309                 }
5310                 switch (clock.p2) {
5311                 case 5:
5312                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5313                         break;
5314                 case 7:
5315                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5316                         break;
5317                 case 10:
5318                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5319                         break;
5320                 case 14:
5321                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5322                         break;
5323                 }
5324                 if (INTEL_INFO(dev)->gen >= 4)
5325                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5326         } else {
5327                 if (is_lvds) {
5328                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5329                 } else {
5330                         if (clock.p1 == 2)
5331                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5332                         else
5333                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5334                         if (clock.p2 == 4)
5335                                 dpll |= PLL_P2_DIVIDE_BY_4;
5336                 }
5337         }
5338
5339         if (is_sdvo && is_tv)
5340                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5341         else if (is_tv)
5342                 /* XXX: just matching BIOS for now */
5343                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5344                 dpll |= 3;
5345         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5346                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5347         else
5348                 dpll |= PLL_REF_INPUT_DREFCLK;
5349
5350         /* setup pipeconf */
5351         pipeconf = I915_READ(PIPECONF(pipe));
5352
5353         /* Set up the display plane register */
5354         dspcntr = DISPPLANE_GAMMA_ENABLE;
5355
5356         if (pipe == 0)
5357                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5358         else
5359                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5360
5361         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5362                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5363                  * core speed.
5364                  *
5365                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5366                  * pipe == 0 check?
5367                  */
5368                 if (mode->clock >
5369                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5370                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5371                 else
5372                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5373         }
5374
5375         /* default to 8bpc */
5376         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5377         if (is_dp) {
5378                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5379                         pipeconf |= PIPECONF_BPP_6 |
5380                                     PIPECONF_DITHER_EN |
5381                                     PIPECONF_DITHER_TYPE_SP;
5382                 }
5383         }
5384
5385         dpll |= DPLL_VCO_ENABLE;
5386
5387         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5388         drm_mode_debug_printmodeline(mode);
5389
5390         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5391
5392         POSTING_READ(DPLL(pipe));
5393         udelay(150);
5394
5395         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5396          * This is an exception to the general rule that mode_set doesn't turn
5397          * things on.
5398          */
5399         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5400                 intel_update_lvds(crtc, &clock, adjusted_mode);
5401
5402         if (is_dp) {
5403                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5404         }
5405
5406         I915_WRITE(DPLL(pipe), dpll);
5407
5408         /* Wait for the clocks to stabilize. */
5409         POSTING_READ(DPLL(pipe));
5410         udelay(150);
5411
5412         if (INTEL_INFO(dev)->gen >= 4) {
5413                 temp = 0;
5414                 if (is_sdvo) {
5415                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5416                         if (temp > 1)
5417                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5418                         else
5419                                 temp = 0;
5420                 }
5421                 I915_WRITE(DPLL_MD(pipe), temp);
5422         } else {
5423                 /* The pixel multiplier can only be updated once the
5424                  * DPLL is enabled and the clocks are stable.
5425                  *
5426                  * So write it again.
5427                  */
5428                 I915_WRITE(DPLL(pipe), dpll);
5429         }
5430
5431         if (HAS_PIPE_CXSR(dev)) {
5432                 if (intel_crtc->lowfreq_avail) {
5433                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5434                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5435                 } else {
5436                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5437                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5438                 }
5439         }
5440
5441         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5442         if (!IS_GEN2(dev) &&
5443             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5444                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5445                 /* the chip adds 2 halflines automatically */
5446                 adjusted_mode->crtc_vtotal -= 1;
5447                 adjusted_mode->crtc_vblank_end -= 1;
5448                 vsyncshift = adjusted_mode->crtc_hsync_start
5449                              - adjusted_mode->crtc_htotal/2;
5450         } else {
5451                 pipeconf |= PIPECONF_PROGRESSIVE;
5452                 vsyncshift = 0;
5453         }
5454
5455         if (!IS_GEN3(dev))
5456                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5457
5458         I915_WRITE(HTOTAL(pipe),
5459                    (adjusted_mode->crtc_hdisplay - 1) |
5460                    ((adjusted_mode->crtc_htotal - 1) << 16));
5461         I915_WRITE(HBLANK(pipe),
5462                    (adjusted_mode->crtc_hblank_start - 1) |
5463                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5464         I915_WRITE(HSYNC(pipe),
5465                    (adjusted_mode->crtc_hsync_start - 1) |
5466                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5467
5468         I915_WRITE(VTOTAL(pipe),
5469                    (adjusted_mode->crtc_vdisplay - 1) |
5470                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5471         I915_WRITE(VBLANK(pipe),
5472                    (adjusted_mode->crtc_vblank_start - 1) |
5473                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5474         I915_WRITE(VSYNC(pipe),
5475                    (adjusted_mode->crtc_vsync_start - 1) |
5476                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5477
5478         /* pipesrc and dspsize control the size that is scaled from,
5479          * which should always be the user's requested size.
5480          */
5481         I915_WRITE(DSPSIZE(plane),
5482                    ((mode->vdisplay - 1) << 16) |
5483                    (mode->hdisplay - 1));
5484         I915_WRITE(DSPPOS(plane), 0);
5485         I915_WRITE(PIPESRC(pipe),
5486                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5487
5488         I915_WRITE(PIPECONF(pipe), pipeconf);
5489         POSTING_READ(PIPECONF(pipe));
5490         intel_enable_pipe(dev_priv, pipe, false);
5491
5492         intel_wait_for_vblank(dev, pipe);
5493
5494         I915_WRITE(DSPCNTR(plane), dspcntr);
5495         POSTING_READ(DSPCNTR(plane));
5496         intel_enable_plane(dev_priv, plane, pipe);
5497
5498         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5499
5500         intel_update_watermarks(dev);
5501
5502         return ret;
5503 }
5504
5505 /*
5506  * Initialize reference clocks when the driver loads
5507  */
5508 void ironlake_init_pch_refclk(struct drm_device *dev)
5509 {
5510         struct drm_i915_private *dev_priv = dev->dev_private;
5511         struct drm_mode_config *mode_config = &dev->mode_config;
5512         struct intel_encoder *encoder;
5513         u32 temp;
5514         bool has_lvds = false;
5515         bool has_cpu_edp = false;
5516         bool has_pch_edp = false;
5517         bool has_panel = false;
5518         bool has_ck505 = false;
5519         bool can_ssc = false;
5520
5521         /* We need to take the global config into account */
5522         list_for_each_entry(encoder, &mode_config->encoder_list,
5523                             base.head) {
5524                 switch (encoder->type) {
5525                 case INTEL_OUTPUT_LVDS:
5526                         has_panel = true;
5527                         has_lvds = true;
5528                         break;
5529                 case INTEL_OUTPUT_EDP:
5530                         has_panel = true;
5531                         if (intel_encoder_is_pch_edp(&encoder->base))
5532                                 has_pch_edp = true;
5533                         else
5534                                 has_cpu_edp = true;
5535                         break;
5536                 }
5537         }
5538
5539         if (HAS_PCH_IBX(dev)) {
5540                 has_ck505 = dev_priv->display_clock_mode;
5541                 can_ssc = has_ck505;
5542         } else {
5543                 has_ck505 = false;
5544                 can_ssc = true;
5545         }
5546
5547         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5548                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5549                       has_ck505);
5550
5551         /* Ironlake: try to setup display ref clock before DPLL
5552          * enabling. This is only under driver's control after
5553          * PCH B stepping, previous chipset stepping should be
5554          * ignoring this setting.
5555          */
5556         temp = I915_READ(PCH_DREF_CONTROL);
5557         /* Always enable nonspread source */
5558         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5559
5560         if (has_ck505)
5561                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5562         else
5563                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5564
5565         if (has_panel) {
5566                 temp &= ~DREF_SSC_SOURCE_MASK;
5567                 temp |= DREF_SSC_SOURCE_ENABLE;
5568
5569                 /* SSC must be turned on before enabling the CPU output  */
5570                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5571                         DRM_DEBUG_KMS("Using SSC on panel\n");
5572                         temp |= DREF_SSC1_ENABLE;
5573                 }
5574
5575                 /* Get SSC going before enabling the outputs */
5576                 I915_WRITE(PCH_DREF_CONTROL, temp);
5577                 POSTING_READ(PCH_DREF_CONTROL);
5578                 udelay(200);
5579
5580                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5581
5582                 /* Enable CPU source on CPU attached eDP */
5583                 if (has_cpu_edp) {
5584                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5585                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5586                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5587                         }
5588                         else
5589                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5590                 } else
5591                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5592
5593                 I915_WRITE(PCH_DREF_CONTROL, temp);
5594                 POSTING_READ(PCH_DREF_CONTROL);
5595                 udelay(200);
5596         } else {
5597                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5598
5599                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5600
5601                 /* Turn off CPU output */
5602                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5603
5604                 I915_WRITE(PCH_DREF_CONTROL, temp);
5605                 POSTING_READ(PCH_DREF_CONTROL);
5606                 udelay(200);
5607
5608                 /* Turn off the SSC source */
5609                 temp &= ~DREF_SSC_SOURCE_MASK;
5610                 temp |= DREF_SSC_SOURCE_DISABLE;
5611
5612                 /* Turn off SSC1 */
5613                 temp &= ~ DREF_SSC1_ENABLE;
5614
5615                 I915_WRITE(PCH_DREF_CONTROL, temp);
5616                 POSTING_READ(PCH_DREF_CONTROL);
5617                 udelay(200);
5618         }
5619 }
5620
5621 static int ironlake_get_refclk(struct drm_crtc *crtc)
5622 {
5623         struct drm_device *dev = crtc->dev;
5624         struct drm_i915_private *dev_priv = dev->dev_private;
5625         struct intel_encoder *encoder;
5626         struct drm_mode_config *mode_config = &dev->mode_config;
5627         struct intel_encoder *edp_encoder = NULL;
5628         int num_connectors = 0;
5629         bool is_lvds = false;
5630
5631         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5632                 if (encoder->base.crtc != crtc)
5633                         continue;
5634
5635                 switch (encoder->type) {
5636                 case INTEL_OUTPUT_LVDS:
5637                         is_lvds = true;
5638                         break;
5639                 case INTEL_OUTPUT_EDP:
5640                         edp_encoder = encoder;
5641                         break;
5642                 }
5643                 num_connectors++;
5644         }
5645
5646         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5647                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5648                               dev_priv->lvds_ssc_freq);
5649                 return dev_priv->lvds_ssc_freq * 1000;
5650         }
5651
5652         return 120000;
5653 }
5654
5655 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5656                                   struct drm_display_mode *mode,
5657                                   struct drm_display_mode *adjusted_mode,
5658                                   int x, int y,
5659                                   struct drm_framebuffer *old_fb)
5660 {
5661         struct drm_device *dev = crtc->dev;
5662         struct drm_i915_private *dev_priv = dev->dev_private;
5663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5664         int pipe = intel_crtc->pipe;
5665         int plane = intel_crtc->plane;
5666         int refclk, num_connectors = 0;
5667         intel_clock_t clock, reduced_clock;
5668         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5669         bool ok, has_reduced_clock = false, is_sdvo = false;
5670         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5671         struct intel_encoder *has_edp_encoder = NULL;
5672         struct drm_mode_config *mode_config = &dev->mode_config;
5673         struct intel_encoder *encoder;
5674         const intel_limit_t *limit;
5675         int ret;
5676         struct fdi_m_n m_n = {0};
5677         u32 temp;
5678         u32 lvds_sync = 0;
5679         int target_clock, pixel_multiplier, lane, link_bw, factor;
5680         unsigned int pipe_bpp;
5681         bool dither;
5682
5683         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5684                 if (encoder->base.crtc != crtc)
5685                         continue;
5686
5687                 switch (encoder->type) {
5688                 case INTEL_OUTPUT_LVDS:
5689                         is_lvds = true;
5690                         break;
5691                 case INTEL_OUTPUT_SDVO:
5692                 case INTEL_OUTPUT_HDMI:
5693                         is_sdvo = true;
5694                         if (encoder->needs_tv_clock)
5695                                 is_tv = true;
5696                         break;
5697                 case INTEL_OUTPUT_TVOUT:
5698                         is_tv = true;
5699                         break;
5700                 case INTEL_OUTPUT_ANALOG:
5701                         is_crt = true;
5702                         break;
5703                 case INTEL_OUTPUT_DISPLAYPORT:
5704                         is_dp = true;
5705                         break;
5706                 case INTEL_OUTPUT_EDP:
5707                         has_edp_encoder = encoder;
5708                         break;
5709                 }
5710
5711                 num_connectors++;
5712         }
5713
5714         refclk = ironlake_get_refclk(crtc);
5715
5716         /*
5717          * Returns a set of divisors for the desired target clock with the given
5718          * refclk, or FALSE.  The returned values represent the clock equation:
5719          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5720          */
5721         limit = intel_limit(crtc, refclk);
5722         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5723                              &clock);
5724         if (!ok) {
5725                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5726                 return -EINVAL;
5727         }
5728
5729         /* Ensure that the cursor is valid for the new mode before changing... */
5730         intel_crtc_update_cursor(crtc, true);
5731
5732         if (is_lvds && dev_priv->lvds_downclock_avail) {
5733                 /*
5734                  * Ensure we match the reduced clock's P to the target clock.
5735                  * If the clocks don't match, we can't switch the display clock
5736                  * by using the FP0/FP1. In such case we will disable the LVDS
5737                  * downclock feature.
5738                 */
5739                 has_reduced_clock = limit->find_pll(limit, crtc,
5740                                                     dev_priv->lvds_downclock,
5741                                                     refclk,
5742                                                     &clock,
5743                                                     &reduced_clock);
5744         }
5745         /* SDVO TV has fixed PLL values depend on its clock range,
5746            this mirrors vbios setting. */
5747         if (is_sdvo && is_tv) {
5748                 if (adjusted_mode->clock >= 100000
5749                     && adjusted_mode->clock < 140500) {
5750                         clock.p1 = 2;
5751                         clock.p2 = 10;
5752                         clock.n = 3;
5753                         clock.m1 = 16;
5754                         clock.m2 = 8;
5755                 } else if (adjusted_mode->clock >= 140500
5756                            && adjusted_mode->clock <= 200000) {
5757                         clock.p1 = 1;
5758                         clock.p2 = 10;
5759                         clock.n = 6;
5760                         clock.m1 = 12;
5761                         clock.m2 = 8;
5762                 }
5763         }
5764
5765         /* FDI link */
5766         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5767         lane = 0;
5768         /* CPU eDP doesn't require FDI link, so just set DP M/N
5769            according to current link config */
5770         if (has_edp_encoder &&
5771             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5772                 target_clock = mode->clock;
5773                 intel_edp_link_config(has_edp_encoder,
5774                                       &lane, &link_bw);
5775         } else {
5776                 /* [e]DP over FDI requires target mode clock
5777                    instead of link clock */
5778                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5779                         target_clock = mode->clock;
5780                 else
5781                         target_clock = adjusted_mode->clock;
5782
5783                 /* FDI is a binary signal running at ~2.7GHz, encoding
5784                  * each output octet as 10 bits. The actual frequency
5785                  * is stored as a divider into a 100MHz clock, and the
5786                  * mode pixel clock is stored in units of 1KHz.
5787                  * Hence the bw of each lane in terms of the mode signal
5788                  * is:
5789                  */
5790                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5791         }
5792
5793         /* determine panel color depth */
5794         temp = I915_READ(PIPECONF(pipe));
5795         temp &= ~PIPE_BPC_MASK;
5796         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5797         switch (pipe_bpp) {
5798         case 18:
5799                 temp |= PIPE_6BPC;
5800                 break;
5801         case 24:
5802                 temp |= PIPE_8BPC;
5803                 break;
5804         case 30:
5805                 temp |= PIPE_10BPC;
5806                 break;
5807         case 36:
5808                 temp |= PIPE_12BPC;
5809                 break;
5810         default:
5811                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5812                         pipe_bpp);
5813                 temp |= PIPE_8BPC;
5814                 pipe_bpp = 24;
5815                 break;
5816         }
5817
5818         intel_crtc->bpp = pipe_bpp;
5819         I915_WRITE(PIPECONF(pipe), temp);
5820
5821         if (!lane) {
5822                 /*
5823                  * Account for spread spectrum to avoid
5824                  * oversubscribing the link. Max center spread
5825                  * is 2.5%; use 5% for safety's sake.
5826                  */
5827                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5828                 lane = bps / (link_bw * 8) + 1;
5829         }
5830
5831         intel_crtc->fdi_lanes = lane;
5832
5833         if (pixel_multiplier > 1)
5834                 link_bw *= pixel_multiplier;
5835         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5836                              &m_n);
5837
5838         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5839         if (has_reduced_clock)
5840                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5841                         reduced_clock.m2;
5842
5843         /* Enable autotuning of the PLL clock (if permissible) */
5844         factor = 21;
5845         if (is_lvds) {
5846                 if ((intel_panel_use_ssc(dev_priv) &&
5847                      dev_priv->lvds_ssc_freq == 100) ||
5848                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5849                         factor = 25;
5850         } else if (is_sdvo && is_tv)
5851                 factor = 20;
5852
5853         if (clock.m < factor * clock.n)
5854                 fp |= FP_CB_TUNE;
5855
5856         dpll = 0;
5857
5858         if (is_lvds)
5859                 dpll |= DPLLB_MODE_LVDS;
5860         else
5861                 dpll |= DPLLB_MODE_DAC_SERIAL;
5862         if (is_sdvo) {
5863                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5864                 if (pixel_multiplier > 1) {
5865                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5866                 }
5867                 dpll |= DPLL_DVO_HIGH_SPEED;
5868         }
5869         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5870                 dpll |= DPLL_DVO_HIGH_SPEED;
5871
5872         /* compute bitmask from p1 value */
5873         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5874         /* also FPA1 */
5875         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5876
5877         switch (clock.p2) {
5878         case 5:
5879                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5880                 break;
5881         case 7:
5882                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5883                 break;
5884         case 10:
5885                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5886                 break;
5887         case 14:
5888                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5889                 break;
5890         }
5891
5892         if (is_sdvo && is_tv)
5893                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5894         else if (is_tv)
5895                 /* XXX: just matching BIOS for now */
5896                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5897                 dpll |= 3;
5898         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5899                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5900         else
5901                 dpll |= PLL_REF_INPUT_DREFCLK;
5902
5903         /* setup pipeconf */
5904         pipeconf = I915_READ(PIPECONF(pipe));
5905
5906         /* Set up the display plane register */
5907         dspcntr = DISPPLANE_GAMMA_ENABLE;
5908
5909         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5910         drm_mode_debug_printmodeline(mode);
5911
5912         /* PCH eDP needs FDI, but CPU eDP does not */
5913         if (!intel_crtc->no_pll) {
5914                 if (!has_edp_encoder ||
5915                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5916                         I915_WRITE(PCH_FP0(pipe), fp);
5917                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5918
5919                         POSTING_READ(PCH_DPLL(pipe));
5920                         udelay(150);
5921                 }
5922         } else {
5923                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5924                     fp == I915_READ(PCH_FP0(0))) {
5925                         intel_crtc->use_pll_a = true;
5926                         DRM_DEBUG_KMS("using pipe a dpll\n");
5927                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5928                            fp == I915_READ(PCH_FP0(1))) {
5929                         intel_crtc->use_pll_a = false;
5930                         DRM_DEBUG_KMS("using pipe b dpll\n");
5931                 } else {
5932                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5933                         return -EINVAL;
5934                 }
5935         }
5936
5937         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5938          * This is an exception to the general rule that mode_set doesn't turn
5939          * things on.
5940          */
5941         if (is_lvds) {
5942                 temp = I915_READ(PCH_LVDS);
5943                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5944                 if (HAS_PCH_CPT(dev)) {
5945                         temp &= ~PORT_TRANS_SEL_MASK;
5946                         temp |= PORT_TRANS_SEL_CPT(pipe);
5947                 } else {
5948                         if (pipe == 1)
5949                                 temp |= LVDS_PIPEB_SELECT;
5950                         else
5951                                 temp &= ~LVDS_PIPEB_SELECT;
5952                 }
5953
5954                 /* set the corresponsding LVDS_BORDER bit */
5955                 temp |= dev_priv->lvds_border_bits;
5956                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5957                  * set the DPLLs for dual-channel mode or not.
5958                  */
5959                 if (clock.p2 == 7)
5960                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5961                 else
5962                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5963
5964                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5965                  * appropriately here, but we need to look more thoroughly into how
5966                  * panels behave in the two modes.
5967                  */
5968                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5969                         lvds_sync |= LVDS_HSYNC_POLARITY;
5970                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5971                         lvds_sync |= LVDS_VSYNC_POLARITY;
5972                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5973                     != lvds_sync) {
5974                         char flags[2] = "-+";
5975                         DRM_INFO("Changing LVDS panel from "
5976                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5977                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5978                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5979                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5980                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5981                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5982                         temp |= lvds_sync;
5983                 }
5984                 I915_WRITE(PCH_LVDS, temp);
5985         }
5986
5987         pipeconf &= ~PIPECONF_DITHER_EN;
5988         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5989         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5990                 pipeconf |= PIPECONF_DITHER_EN;
5991                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5992         }
5993         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5994                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5995         } else {
5996                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5997                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5998                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5999                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
6000                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
6001         }
6002
6003         if (!intel_crtc->no_pll &&
6004             (!has_edp_encoder ||
6005              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
6006                 I915_WRITE(PCH_DPLL(pipe), dpll);
6007
6008                 /* Wait for the clocks to stabilize. */
6009                 POSTING_READ(PCH_DPLL(pipe));
6010                 udelay(150);
6011
6012                 /* The pixel multiplier can only be updated once the
6013                  * DPLL is enabled and the clocks are stable.
6014                  *
6015                  * So write it again.
6016                  */
6017                 I915_WRITE(PCH_DPLL(pipe), dpll);
6018         }
6019
6020         intel_crtc->lowfreq_avail = false;
6021         if (!intel_crtc->no_pll) {
6022                 if (is_lvds && has_reduced_clock && i915_powersave) {
6023                         I915_WRITE(PCH_FP1(pipe), fp2);
6024                         intel_crtc->lowfreq_avail = true;
6025                         if (HAS_PIPE_CXSR(dev)) {
6026                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6027                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6028                         }
6029                 } else {
6030                         I915_WRITE(PCH_FP1(pipe), fp);
6031                         if (HAS_PIPE_CXSR(dev)) {
6032                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6033                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6034                         }
6035                 }
6036         }
6037
6038         pipeconf &= ~PIPECONF_INTERLACE_MASK;
6039         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6040                 pipeconf |= PIPECONF_INTERLACED_ILK;
6041                 /* the chip adds 2 halflines automatically */
6042                 adjusted_mode->crtc_vtotal -= 1;
6043                 adjusted_mode->crtc_vblank_end -= 1;
6044                 I915_WRITE(VSYNCSHIFT(pipe),
6045                            adjusted_mode->crtc_hsync_start
6046                            - adjusted_mode->crtc_htotal/2);
6047         } else {
6048                 pipeconf |= PIPECONF_PROGRESSIVE;
6049                 I915_WRITE(VSYNCSHIFT(pipe), 0);
6050         }
6051
6052         I915_WRITE(HTOTAL(pipe),
6053                    (adjusted_mode->crtc_hdisplay - 1) |
6054                    ((adjusted_mode->crtc_htotal - 1) << 16));
6055         I915_WRITE(HBLANK(pipe),
6056                    (adjusted_mode->crtc_hblank_start - 1) |
6057                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6058         I915_WRITE(HSYNC(pipe),
6059                    (adjusted_mode->crtc_hsync_start - 1) |
6060                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6061
6062         I915_WRITE(VTOTAL(pipe),
6063                    (adjusted_mode->crtc_vdisplay - 1) |
6064                    ((adjusted_mode->crtc_vtotal - 1) << 16));
6065         I915_WRITE(VBLANK(pipe),
6066                    (adjusted_mode->crtc_vblank_start - 1) |
6067                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
6068         I915_WRITE(VSYNC(pipe),
6069                    (adjusted_mode->crtc_vsync_start - 1) |
6070                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6071
6072         /* pipesrc controls the size that is scaled from, which should
6073          * always be the user's requested size.
6074          */
6075         I915_WRITE(PIPESRC(pipe),
6076                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6077
6078         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6079         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6080         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6081         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6082
6083         if (has_edp_encoder &&
6084             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6085                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6086         }
6087
6088         I915_WRITE(PIPECONF(pipe), pipeconf);
6089         POSTING_READ(PIPECONF(pipe));
6090
6091         intel_wait_for_vblank(dev, pipe);
6092
6093         I915_WRITE(DSPCNTR(plane), dspcntr);
6094         POSTING_READ(DSPCNTR(plane));
6095
6096         ret = intel_pipe_set_base(crtc, x, y, old_fb);
6097
6098         intel_update_watermarks(dev);
6099
6100         return ret;
6101 }
6102
6103 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6104                                struct drm_display_mode *mode,
6105                                struct drm_display_mode *adjusted_mode,
6106                                int x, int y,
6107                                struct drm_framebuffer *old_fb)
6108 {
6109         struct drm_device *dev = crtc->dev;
6110         struct drm_i915_private *dev_priv = dev->dev_private;
6111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6112         int pipe = intel_crtc->pipe;
6113         int ret;
6114
6115         drm_vblank_pre_modeset(dev, pipe);
6116
6117         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6118                                               x, y, old_fb);
6119         drm_vblank_post_modeset(dev, pipe);
6120
6121         if (ret)
6122                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6123         else
6124                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6125
6126         return ret;
6127 }
6128
6129 static bool intel_eld_uptodate(struct drm_connector *connector,
6130                                int reg_eldv, uint32_t bits_eldv,
6131                                int reg_elda, uint32_t bits_elda,
6132                                int reg_edid)
6133 {
6134         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6135         uint8_t *eld = connector->eld;
6136         uint32_t i;
6137
6138         i = I915_READ(reg_eldv);
6139         i &= bits_eldv;
6140
6141         if (!eld[0])
6142                 return !i;
6143
6144         if (!i)
6145                 return false;
6146
6147         i = I915_READ(reg_elda);
6148         i &= ~bits_elda;
6149         I915_WRITE(reg_elda, i);
6150
6151         for (i = 0; i < eld[2]; i++)
6152                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6153                         return false;
6154
6155         return true;
6156 }
6157
6158 static void g4x_write_eld(struct drm_connector *connector,
6159                           struct drm_crtc *crtc)
6160 {
6161         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6162         uint8_t *eld = connector->eld;
6163         uint32_t eldv;
6164         uint32_t len;
6165         uint32_t i;
6166
6167         i = I915_READ(G4X_AUD_VID_DID);
6168
6169         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6170                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6171         else
6172                 eldv = G4X_ELDV_DEVCTG;
6173
6174         if (intel_eld_uptodate(connector,
6175                                G4X_AUD_CNTL_ST, eldv,
6176                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6177                                G4X_HDMIW_HDMIEDID))
6178                 return;
6179
6180         i = I915_READ(G4X_AUD_CNTL_ST);
6181         i &= ~(eldv | G4X_ELD_ADDR);
6182         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6183         I915_WRITE(G4X_AUD_CNTL_ST, i);
6184
6185         if (!eld[0])
6186                 return;
6187
6188         len = min_t(uint8_t, eld[2], len);
6189         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6190         for (i = 0; i < len; i++)
6191                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6192
6193         i = I915_READ(G4X_AUD_CNTL_ST);
6194         i |= eldv;
6195         I915_WRITE(G4X_AUD_CNTL_ST, i);
6196 }
6197
6198 static void ironlake_write_eld(struct drm_connector *connector,
6199                                      struct drm_crtc *crtc)
6200 {
6201         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6202         uint8_t *eld = connector->eld;
6203         uint32_t eldv;
6204         uint32_t i;
6205         int len;
6206         int hdmiw_hdmiedid;
6207         int aud_config;
6208         int aud_cntl_st;
6209         int aud_cntrl_st2;
6210
6211         if (HAS_PCH_IBX(connector->dev)) {
6212                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6213                 aud_config = IBX_AUD_CONFIG_A;
6214                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6215                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6216         } else {
6217                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6218                 aud_config = CPT_AUD_CONFIG_A;
6219                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6220                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6221         }
6222
6223         i = to_intel_crtc(crtc)->pipe;
6224         hdmiw_hdmiedid += i * 0x100;
6225         aud_cntl_st += i * 0x100;
6226         aud_config += i * 0x100;
6227
6228         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6229
6230         i = I915_READ(aud_cntl_st);
6231         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
6232         if (!i) {
6233                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6234                 /* operate blindly on all ports */
6235                 eldv = IBX_ELD_VALIDB;
6236                 eldv |= IBX_ELD_VALIDB << 4;
6237                 eldv |= IBX_ELD_VALIDB << 8;
6238         } else {
6239                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6240                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6241         }
6242
6243         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6244                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6245                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6246                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6247         } else
6248                 I915_WRITE(aud_config, 0);
6249
6250         if (intel_eld_uptodate(connector,
6251                                aud_cntrl_st2, eldv,
6252                                aud_cntl_st, IBX_ELD_ADDRESS,
6253                                hdmiw_hdmiedid))
6254                 return;
6255
6256         i = I915_READ(aud_cntrl_st2);
6257         i &= ~eldv;
6258         I915_WRITE(aud_cntrl_st2, i);
6259
6260         if (!eld[0])
6261                 return;
6262
6263         i = I915_READ(aud_cntl_st);
6264         i &= ~IBX_ELD_ADDRESS;
6265         I915_WRITE(aud_cntl_st, i);
6266
6267         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6268         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6269         for (i = 0; i < len; i++)
6270                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6271
6272         i = I915_READ(aud_cntrl_st2);
6273         i |= eldv;
6274         I915_WRITE(aud_cntrl_st2, i);
6275 }
6276
6277 void intel_write_eld(struct drm_encoder *encoder,
6278                      struct drm_display_mode *mode)
6279 {
6280         struct drm_crtc *crtc = encoder->crtc;
6281         struct drm_connector *connector;
6282         struct drm_device *dev = encoder->dev;
6283         struct drm_i915_private *dev_priv = dev->dev_private;
6284
6285         connector = drm_select_eld(encoder, mode);
6286         if (!connector)
6287                 return;
6288
6289         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6290                          connector->base.id,
6291                          drm_get_connector_name(connector),
6292                          connector->encoder->base.id,
6293                          drm_get_encoder_name(connector->encoder));
6294
6295         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6296
6297         if (dev_priv->display.write_eld)
6298                 dev_priv->display.write_eld(connector, crtc);
6299 }
6300
6301 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6302 void intel_crtc_load_lut(struct drm_crtc *crtc)
6303 {
6304         struct drm_device *dev = crtc->dev;
6305         struct drm_i915_private *dev_priv = dev->dev_private;
6306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6307         int palreg = PALETTE(intel_crtc->pipe);
6308         int i;
6309
6310         /* The clocks have to be on to load the palette. */
6311         if (!crtc->enabled)
6312                 return;
6313
6314         /* use legacy palette for Ironlake */
6315         if (HAS_PCH_SPLIT(dev))
6316                 palreg = LGC_PALETTE(intel_crtc->pipe);
6317
6318         for (i = 0; i < 256; i++) {
6319                 I915_WRITE(palreg + 4 * i,
6320                            (intel_crtc->lut_r[i] << 16) |
6321                            (intel_crtc->lut_g[i] << 8) |
6322                            intel_crtc->lut_b[i]);
6323         }
6324 }
6325
6326 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6327 {
6328         struct drm_device *dev = crtc->dev;
6329         struct drm_i915_private *dev_priv = dev->dev_private;
6330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6331         bool visible = base != 0;
6332         u32 cntl;
6333
6334         if (intel_crtc->cursor_visible == visible)
6335                 return;
6336
6337         cntl = I915_READ(_CURACNTR);
6338         if (visible) {
6339                 /* On these chipsets we can only modify the base whilst
6340                  * the cursor is disabled.
6341                  */
6342                 I915_WRITE(_CURABASE, base);
6343
6344                 cntl &= ~(CURSOR_FORMAT_MASK);
6345                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6346                 cntl |= CURSOR_ENABLE |
6347                         CURSOR_GAMMA_ENABLE |
6348                         CURSOR_FORMAT_ARGB;
6349         } else
6350                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6351         I915_WRITE(_CURACNTR, cntl);
6352
6353         intel_crtc->cursor_visible = visible;
6354 }
6355
6356 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6357 {
6358         struct drm_device *dev = crtc->dev;
6359         struct drm_i915_private *dev_priv = dev->dev_private;
6360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361         int pipe = intel_crtc->pipe;
6362         bool visible = base != 0;
6363
6364         if (intel_crtc->cursor_visible != visible) {
6365                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6366                 if (base) {
6367                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6368                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6369                         cntl |= pipe << 28; /* Connect to correct pipe */
6370                 } else {
6371                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6372                         cntl |= CURSOR_MODE_DISABLE;
6373                 }
6374                 I915_WRITE(CURCNTR(pipe), cntl);
6375
6376                 intel_crtc->cursor_visible = visible;
6377         }
6378         /* and commit changes on next vblank */
6379         I915_WRITE(CURBASE(pipe), base);
6380 }
6381
6382 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6383 {
6384         struct drm_device *dev = crtc->dev;
6385         struct drm_i915_private *dev_priv = dev->dev_private;
6386         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6387         int pipe = intel_crtc->pipe;
6388         bool visible = base != 0;
6389
6390         if (intel_crtc->cursor_visible != visible) {
6391                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6392                 if (base) {
6393                         cntl &= ~CURSOR_MODE;
6394                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6395                 } else {
6396                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6397                         cntl |= CURSOR_MODE_DISABLE;
6398                 }
6399                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6400
6401                 intel_crtc->cursor_visible = visible;
6402         }
6403         /* and commit changes on next vblank */
6404         I915_WRITE(CURBASE_IVB(pipe), base);
6405 }
6406
6407 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6408 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6409                                      bool on)
6410 {
6411         struct drm_device *dev = crtc->dev;
6412         struct drm_i915_private *dev_priv = dev->dev_private;
6413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6414         int pipe = intel_crtc->pipe;
6415         int x = intel_crtc->cursor_x;
6416         int y = intel_crtc->cursor_y;
6417         u32 base, pos;
6418         bool visible;
6419
6420         pos = 0;
6421
6422         if (on && crtc->enabled && crtc->fb) {
6423                 base = intel_crtc->cursor_addr;
6424                 if (x > (int) crtc->fb->width)
6425                         base = 0;
6426
6427                 if (y > (int) crtc->fb->height)
6428                         base = 0;
6429         } else
6430                 base = 0;
6431
6432         if (x < 0) {
6433                 if (x + intel_crtc->cursor_width < 0)
6434                         base = 0;
6435
6436                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6437                 x = -x;
6438         }
6439         pos |= x << CURSOR_X_SHIFT;
6440
6441         if (y < 0) {
6442                 if (y + intel_crtc->cursor_height < 0)
6443                         base = 0;
6444
6445                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6446                 y = -y;
6447         }
6448         pos |= y << CURSOR_Y_SHIFT;
6449
6450         visible = base != 0;
6451         if (!visible && !intel_crtc->cursor_visible)
6452                 return;
6453
6454         if (IS_IVYBRIDGE(dev)) {
6455                 I915_WRITE(CURPOS_IVB(pipe), pos);
6456                 ivb_update_cursor(crtc, base);
6457         } else {
6458                 I915_WRITE(CURPOS(pipe), pos);
6459                 if (IS_845G(dev) || IS_I865G(dev))
6460                         i845_update_cursor(crtc, base);
6461                 else
6462                         i9xx_update_cursor(crtc, base);
6463         }
6464
6465         if (visible)
6466                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6467 }
6468
6469 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6470                                  struct drm_file *file,
6471                                  uint32_t handle,
6472                                  uint32_t width, uint32_t height)
6473 {
6474         struct drm_device *dev = crtc->dev;
6475         struct drm_i915_private *dev_priv = dev->dev_private;
6476         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6477         struct drm_i915_gem_object *obj;
6478         uint32_t addr;
6479         int ret;
6480
6481         DRM_DEBUG_KMS("\n");
6482
6483         /* if we want to turn off the cursor ignore width and height */
6484         if (!handle) {
6485                 DRM_DEBUG_KMS("cursor off\n");
6486                 addr = 0;
6487                 obj = NULL;
6488                 mutex_lock(&dev->struct_mutex);
6489                 goto finish;
6490         }
6491
6492         /* Currently we only support 64x64 cursors */
6493         if (width != 64 || height != 64) {
6494                 DRM_ERROR("we currently only support 64x64 cursors\n");
6495                 return -EINVAL;
6496         }
6497
6498         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6499         if (&obj->base == NULL)
6500                 return -ENOENT;
6501
6502         if (obj->base.size < width * height * 4) {
6503                 DRM_ERROR("buffer is to small\n");
6504                 ret = -ENOMEM;
6505                 goto fail;
6506         }
6507
6508         /* we only need to pin inside GTT if cursor is non-phy */
6509         mutex_lock(&dev->struct_mutex);
6510         if (!dev_priv->info->cursor_needs_physical) {
6511                 if (obj->tiling_mode) {
6512                         DRM_ERROR("cursor cannot be tiled\n");
6513                         ret = -EINVAL;
6514                         goto fail_locked;
6515                 }
6516
6517                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6518                 if (ret) {
6519                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6520                         goto fail_locked;
6521                 }
6522
6523                 ret = i915_gem_object_put_fence(obj);
6524                 if (ret) {
6525                         DRM_ERROR("failed to release fence for cursor");
6526                         goto fail_unpin;
6527                 }
6528
6529                 addr = obj->gtt_offset;
6530         } else {
6531                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6532                 ret = i915_gem_attach_phys_object(dev, obj,
6533                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6534                                                   align);
6535                 if (ret) {
6536                         DRM_ERROR("failed to attach phys object\n");
6537                         goto fail_locked;
6538                 }
6539                 addr = obj->phys_obj->handle->busaddr;
6540         }
6541
6542         if (IS_GEN2(dev))
6543                 I915_WRITE(CURSIZE, (height << 12) | width);
6544
6545  finish:
6546         if (intel_crtc->cursor_bo) {
6547                 if (dev_priv->info->cursor_needs_physical) {
6548                         if (intel_crtc->cursor_bo != obj)
6549                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6550                 } else
6551                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6552                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6553         }
6554
6555         mutex_unlock(&dev->struct_mutex);
6556
6557         intel_crtc->cursor_addr = addr;
6558         intel_crtc->cursor_bo = obj;
6559         intel_crtc->cursor_width = width;
6560         intel_crtc->cursor_height = height;
6561
6562         intel_crtc_update_cursor(crtc, true);
6563
6564         return 0;
6565 fail_unpin:
6566         i915_gem_object_unpin(obj);
6567 fail_locked:
6568         mutex_unlock(&dev->struct_mutex);
6569 fail:
6570         drm_gem_object_unreference_unlocked(&obj->base);
6571         return ret;
6572 }
6573
6574 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6575 {
6576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6577
6578         intel_crtc->cursor_x = x;
6579         intel_crtc->cursor_y = y;
6580
6581         intel_crtc_update_cursor(crtc, true);
6582
6583         return 0;
6584 }
6585
6586 /** Sets the color ramps on behalf of RandR */
6587 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6588                                  u16 blue, int regno)
6589 {
6590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6591
6592         intel_crtc->lut_r[regno] = red >> 8;
6593         intel_crtc->lut_g[regno] = green >> 8;
6594         intel_crtc->lut_b[regno] = blue >> 8;
6595 }
6596
6597 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6598                              u16 *blue, int regno)
6599 {
6600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6601
6602         *red = intel_crtc->lut_r[regno] << 8;
6603         *green = intel_crtc->lut_g[regno] << 8;
6604         *blue = intel_crtc->lut_b[regno] << 8;
6605 }
6606
6607 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6608                                  u16 *blue, uint32_t start, uint32_t size)
6609 {
6610         int end = (start + size > 256) ? 256 : start + size, i;
6611         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6612
6613         for (i = start; i < end; i++) {
6614                 intel_crtc->lut_r[i] = red[i] >> 8;
6615                 intel_crtc->lut_g[i] = green[i] >> 8;
6616                 intel_crtc->lut_b[i] = blue[i] >> 8;
6617         }
6618
6619         intel_crtc_load_lut(crtc);
6620 }
6621
6622 /**
6623  * Get a pipe with a simple mode set on it for doing load-based monitor
6624  * detection.
6625  *
6626  * It will be up to the load-detect code to adjust the pipe as appropriate for
6627  * its requirements.  The pipe will be connected to no other encoders.
6628  *
6629  * Currently this code will only succeed if there is a pipe with no encoders
6630  * configured for it.  In the future, it could choose to temporarily disable
6631  * some outputs to free up a pipe for its use.
6632  *
6633  * \return crtc, or NULL if no pipes are available.
6634  */
6635
6636 /* VESA 640x480x72Hz mode to set on the pipe */
6637 static struct drm_display_mode load_detect_mode = {
6638         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6639                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6640 };
6641
6642 static struct drm_framebuffer *
6643 intel_framebuffer_create(struct drm_device *dev,
6644                          struct drm_mode_fb_cmd2 *mode_cmd,
6645                          struct drm_i915_gem_object *obj)
6646 {
6647         struct intel_framebuffer *intel_fb;
6648         int ret;
6649
6650         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6651         if (!intel_fb) {
6652                 drm_gem_object_unreference_unlocked(&obj->base);
6653                 return ERR_PTR(-ENOMEM);
6654         }
6655
6656         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6657         if (ret) {
6658                 drm_gem_object_unreference_unlocked(&obj->base);
6659                 kfree(intel_fb);
6660                 return ERR_PTR(ret);
6661         }
6662
6663         return &intel_fb->base;
6664 }
6665
6666 static u32
6667 intel_framebuffer_pitch_for_width(int width, int bpp)
6668 {
6669         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6670         return ALIGN(pitch, 64);
6671 }
6672
6673 static u32
6674 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6675 {
6676         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6677         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6678 }
6679
6680 static struct drm_framebuffer *
6681 intel_framebuffer_create_for_mode(struct drm_device *dev,
6682                                   struct drm_display_mode *mode,
6683                                   int depth, int bpp)
6684 {
6685         struct drm_i915_gem_object *obj;
6686         struct drm_mode_fb_cmd2 mode_cmd;
6687
6688         obj = i915_gem_alloc_object(dev,
6689                                     intel_framebuffer_size_for_mode(mode, bpp));
6690         if (obj == NULL)
6691                 return ERR_PTR(-ENOMEM);
6692
6693         mode_cmd.width = mode->hdisplay;
6694         mode_cmd.height = mode->vdisplay;
6695         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6696                                                                 bpp);
6697         mode_cmd.pixel_format = 0;
6698
6699         return intel_framebuffer_create(dev, &mode_cmd, obj);
6700 }
6701
6702 static struct drm_framebuffer *
6703 mode_fits_in_fbdev(struct drm_device *dev,
6704                    struct drm_display_mode *mode)
6705 {
6706         struct drm_i915_private *dev_priv = dev->dev_private;
6707         struct drm_i915_gem_object *obj;
6708         struct drm_framebuffer *fb;
6709
6710         if (dev_priv->fbdev == NULL)
6711                 return NULL;
6712
6713         obj = dev_priv->fbdev->ifb.obj;
6714         if (obj == NULL)
6715                 return NULL;
6716
6717         fb = &dev_priv->fbdev->ifb.base;
6718         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6719                                                                fb->bits_per_pixel))
6720                 return NULL;
6721
6722         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6723                 return NULL;
6724
6725         return fb;
6726 }
6727
6728 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6729                                 struct drm_connector *connector,
6730                                 struct drm_display_mode *mode,
6731                                 struct intel_load_detect_pipe *old)
6732 {
6733         struct intel_crtc *intel_crtc;
6734         struct drm_crtc *possible_crtc;
6735         struct drm_encoder *encoder = &intel_encoder->base;
6736         struct drm_crtc *crtc = NULL;
6737         struct drm_device *dev = encoder->dev;
6738         struct drm_framebuffer *old_fb;
6739         int i = -1;
6740
6741         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6742                       connector->base.id, drm_get_connector_name(connector),
6743                       encoder->base.id, drm_get_encoder_name(encoder));
6744
6745         /*
6746          * Algorithm gets a little messy:
6747          *
6748          *   - if the connector already has an assigned crtc, use it (but make
6749          *     sure it's on first)
6750          *
6751          *   - try to find the first unused crtc that can drive this connector,
6752          *     and use that if we find one
6753          */
6754
6755         /* See if we already have a CRTC for this connector */
6756         if (encoder->crtc) {
6757                 crtc = encoder->crtc;
6758
6759                 intel_crtc = to_intel_crtc(crtc);
6760                 old->dpms_mode = intel_crtc->dpms_mode;
6761                 old->load_detect_temp = false;
6762
6763                 /* Make sure the crtc and connector are running */
6764                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6765                         struct drm_encoder_helper_funcs *encoder_funcs;
6766                         struct drm_crtc_helper_funcs *crtc_funcs;
6767
6768                         crtc_funcs = crtc->helper_private;
6769                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6770
6771                         encoder_funcs = encoder->helper_private;
6772                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6773                 }
6774
6775                 return true;
6776         }
6777
6778         /* Find an unused one (if possible) */
6779         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6780                 i++;
6781                 if (!(encoder->possible_crtcs & (1 << i)))
6782                         continue;
6783                 if (!possible_crtc->enabled) {
6784                         crtc = possible_crtc;
6785                         break;
6786                 }
6787         }
6788
6789         /*
6790          * If we didn't find an unused CRTC, don't use any.
6791          */
6792         if (!crtc) {
6793                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6794                 return false;
6795         }
6796
6797         encoder->crtc = crtc;
6798         connector->encoder = encoder;
6799
6800         intel_crtc = to_intel_crtc(crtc);
6801         old->dpms_mode = intel_crtc->dpms_mode;
6802         old->load_detect_temp = true;
6803         old->release_fb = NULL;
6804
6805         if (!mode)
6806                 mode = &load_detect_mode;
6807
6808         old_fb = crtc->fb;
6809
6810         /* We need a framebuffer large enough to accommodate all accesses
6811          * that the plane may generate whilst we perform load detection.
6812          * We can not rely on the fbcon either being present (we get called
6813          * during its initialisation to detect all boot displays, or it may
6814          * not even exist) or that it is large enough to satisfy the
6815          * requested mode.
6816          */
6817         crtc->fb = mode_fits_in_fbdev(dev, mode);
6818         if (crtc->fb == NULL) {
6819                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6820                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6821                 old->release_fb = crtc->fb;
6822         } else
6823                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6824         if (IS_ERR(crtc->fb)) {
6825                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6826                 crtc->fb = old_fb;
6827                 return false;
6828         }
6829
6830         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6831                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6832                 if (old->release_fb)
6833                         old->release_fb->funcs->destroy(old->release_fb);
6834                 crtc->fb = old_fb;
6835                 return false;
6836         }
6837
6838         /* let the connector get through one full cycle before testing */
6839         intel_wait_for_vblank(dev, intel_crtc->pipe);
6840
6841         return true;
6842 }
6843
6844 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6845                                     struct drm_connector *connector,
6846                                     struct intel_load_detect_pipe *old)
6847 {
6848         struct drm_encoder *encoder = &intel_encoder->base;
6849         struct drm_device *dev = encoder->dev;
6850         struct drm_crtc *crtc = encoder->crtc;
6851         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6852         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6853
6854         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6855                       connector->base.id, drm_get_connector_name(connector),
6856                       encoder->base.id, drm_get_encoder_name(encoder));
6857
6858         if (old->load_detect_temp) {
6859                 connector->encoder = NULL;
6860                 drm_helper_disable_unused_functions(dev);
6861
6862                 if (old->release_fb)
6863                         old->release_fb->funcs->destroy(old->release_fb);
6864
6865                 return;
6866         }
6867
6868         /* Switch crtc and encoder back off if necessary */
6869         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6870                 encoder_funcs->dpms(encoder, old->dpms_mode);
6871                 crtc_funcs->dpms(crtc, old->dpms_mode);
6872         }
6873 }
6874
6875 /* Returns the clock of the currently programmed mode of the given pipe. */
6876 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6877 {
6878         struct drm_i915_private *dev_priv = dev->dev_private;
6879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6880         int pipe = intel_crtc->pipe;
6881         u32 dpll = I915_READ(DPLL(pipe));
6882         u32 fp;
6883         intel_clock_t clock;
6884
6885         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6886                 fp = I915_READ(FP0(pipe));
6887         else
6888                 fp = I915_READ(FP1(pipe));
6889
6890         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6891         if (IS_PINEVIEW(dev)) {
6892                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6893                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6894         } else {
6895                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6896                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6897         }
6898
6899         if (!IS_GEN2(dev)) {
6900                 if (IS_PINEVIEW(dev))
6901                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6902                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6903                 else
6904                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6905                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6906
6907                 switch (dpll & DPLL_MODE_MASK) {
6908                 case DPLLB_MODE_DAC_SERIAL:
6909                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6910                                 5 : 10;
6911                         break;
6912                 case DPLLB_MODE_LVDS:
6913                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6914                                 7 : 14;
6915                         break;
6916                 default:
6917                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6918                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6919                         return 0;
6920                 }
6921
6922                 /* XXX: Handle the 100Mhz refclk */
6923                 intel_clock(dev, 96000, &clock);
6924         } else {
6925                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6926
6927                 if (is_lvds) {
6928                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6929                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6930                         clock.p2 = 14;
6931
6932                         if ((dpll & PLL_REF_INPUT_MASK) ==
6933                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6934                                 /* XXX: might not be 66MHz */
6935                                 intel_clock(dev, 66000, &clock);
6936                         } else
6937                                 intel_clock(dev, 48000, &clock);
6938                 } else {
6939                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6940                                 clock.p1 = 2;
6941                         else {
6942                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6943                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6944                         }
6945                         if (dpll & PLL_P2_DIVIDE_BY_4)
6946                                 clock.p2 = 4;
6947                         else
6948                                 clock.p2 = 2;
6949
6950                         intel_clock(dev, 48000, &clock);
6951                 }
6952         }
6953
6954         /* XXX: It would be nice to validate the clocks, but we can't reuse
6955          * i830PllIsValid() because it relies on the xf86_config connector
6956          * configuration being accurate, which it isn't necessarily.
6957          */
6958
6959         return clock.dot;
6960 }
6961
6962 /** Returns the currently programmed mode of the given pipe. */
6963 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6964                                              struct drm_crtc *crtc)
6965 {
6966         struct drm_i915_private *dev_priv = dev->dev_private;
6967         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6968         int pipe = intel_crtc->pipe;
6969         struct drm_display_mode *mode;
6970         int htot = I915_READ(HTOTAL(pipe));
6971         int hsync = I915_READ(HSYNC(pipe));
6972         int vtot = I915_READ(VTOTAL(pipe));
6973         int vsync = I915_READ(VSYNC(pipe));
6974
6975         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6976         if (!mode)
6977                 return NULL;
6978
6979         mode->clock = intel_crtc_clock_get(dev, crtc);
6980         mode->hdisplay = (htot & 0xffff) + 1;
6981         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6982         mode->hsync_start = (hsync & 0xffff) + 1;
6983         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6984         mode->vdisplay = (vtot & 0xffff) + 1;
6985         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6986         mode->vsync_start = (vsync & 0xffff) + 1;
6987         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6988
6989         drm_mode_set_name(mode);
6990         drm_mode_set_crtcinfo(mode, 0);
6991
6992         return mode;
6993 }
6994
6995 #define GPU_IDLE_TIMEOUT 500 /* ms */
6996
6997 /* When this timer fires, we've been idle for awhile */
6998 static void intel_gpu_idle_timer(unsigned long arg)
6999 {
7000         struct drm_device *dev = (struct drm_device *)arg;
7001         drm_i915_private_t *dev_priv = dev->dev_private;
7002
7003         if (!list_empty(&dev_priv->mm.active_list)) {
7004                 /* Still processing requests, so just re-arm the timer. */
7005                 mod_timer(&dev_priv->idle_timer, jiffies +
7006                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7007                 return;
7008         }
7009
7010         dev_priv->busy = false;
7011         queue_work(dev_priv->wq, &dev_priv->idle_work);
7012 }
7013
7014 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
7015
7016 static void intel_crtc_idle_timer(unsigned long arg)
7017 {
7018         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
7019         struct drm_crtc *crtc = &intel_crtc->base;
7020         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
7021         struct intel_framebuffer *intel_fb;
7022
7023         intel_fb = to_intel_framebuffer(crtc->fb);
7024         if (intel_fb && intel_fb->obj->active) {
7025                 /* The framebuffer is still being accessed by the GPU. */
7026                 mod_timer(&intel_crtc->idle_timer, jiffies +
7027                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7028                 return;
7029         }
7030
7031         intel_crtc->busy = false;
7032         queue_work(dev_priv->wq, &dev_priv->idle_work);
7033 }
7034
7035 static void intel_increase_pllclock(struct drm_crtc *crtc)
7036 {
7037         struct drm_device *dev = crtc->dev;
7038         drm_i915_private_t *dev_priv = dev->dev_private;
7039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7040         int pipe = intel_crtc->pipe;
7041         int dpll_reg = DPLL(pipe);
7042         int dpll;
7043
7044         if (HAS_PCH_SPLIT(dev))
7045                 return;
7046
7047         if (!dev_priv->lvds_downclock_avail)
7048                 return;
7049
7050         dpll = I915_READ(dpll_reg);
7051         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7052                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7053
7054                 assert_panel_unlocked(dev_priv, pipe);
7055
7056                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7057                 I915_WRITE(dpll_reg, dpll);
7058                 intel_wait_for_vblank(dev, pipe);
7059
7060                 dpll = I915_READ(dpll_reg);
7061                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7062                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7063         }
7064
7065         /* Schedule downclock */
7066         mod_timer(&intel_crtc->idle_timer, jiffies +
7067                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7068 }
7069
7070 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7071 {
7072         struct drm_device *dev = crtc->dev;
7073         drm_i915_private_t *dev_priv = dev->dev_private;
7074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7075         int pipe = intel_crtc->pipe;
7076         int dpll_reg = DPLL(pipe);
7077         int dpll = I915_READ(dpll_reg);
7078
7079         if (HAS_PCH_SPLIT(dev))
7080                 return;
7081
7082         if (!dev_priv->lvds_downclock_avail)
7083                 return;
7084
7085         /*
7086          * Since this is called by a timer, we should never get here in
7087          * the manual case.
7088          */
7089         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7090                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7091
7092                 assert_panel_unlocked(dev_priv, pipe);
7093
7094                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7095                 I915_WRITE(dpll_reg, dpll);
7096                 intel_wait_for_vblank(dev, pipe);
7097                 dpll = I915_READ(dpll_reg);
7098                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7099                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7100         }
7101
7102 }
7103
7104 /**
7105  * intel_idle_update - adjust clocks for idleness
7106  * @work: work struct
7107  *
7108  * Either the GPU or display (or both) went idle.  Check the busy status
7109  * here and adjust the CRTC and GPU clocks as necessary.
7110  */
7111 static void intel_idle_update(struct work_struct *work)
7112 {
7113         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7114                                                     idle_work);
7115         struct drm_device *dev = dev_priv->dev;
7116         struct drm_crtc *crtc;
7117         struct intel_crtc *intel_crtc;
7118
7119         if (!i915_powersave)
7120                 return;
7121
7122         mutex_lock(&dev->struct_mutex);
7123
7124         i915_update_gfx_val(dev_priv);
7125
7126         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7127                 /* Skip inactive CRTCs */
7128                 if (!crtc->fb)
7129                         continue;
7130
7131                 intel_crtc = to_intel_crtc(crtc);
7132                 if (!intel_crtc->busy)
7133                         intel_decrease_pllclock(crtc);
7134         }
7135
7136
7137         mutex_unlock(&dev->struct_mutex);
7138 }
7139
7140 /**
7141  * intel_mark_busy - mark the GPU and possibly the display busy
7142  * @dev: drm device
7143  * @obj: object we're operating on
7144  *
7145  * Callers can use this function to indicate that the GPU is busy processing
7146  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
7147  * buffer), we'll also mark the display as busy, so we know to increase its
7148  * clock frequency.
7149  */
7150 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7151 {
7152         drm_i915_private_t *dev_priv = dev->dev_private;
7153         struct drm_crtc *crtc = NULL;
7154         struct intel_framebuffer *intel_fb;
7155         struct intel_crtc *intel_crtc;
7156
7157         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7158                 return;
7159
7160         if (!dev_priv->busy)
7161                 dev_priv->busy = true;
7162         else
7163                 mod_timer(&dev_priv->idle_timer, jiffies +
7164                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7165
7166         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7167                 if (!crtc->fb)
7168                         continue;
7169
7170                 intel_crtc = to_intel_crtc(crtc);
7171                 intel_fb = to_intel_framebuffer(crtc->fb);
7172                 if (intel_fb->obj == obj) {
7173                         if (!intel_crtc->busy) {
7174                                 /* Non-busy -> busy, upclock */
7175                                 intel_increase_pllclock(crtc);
7176                                 intel_crtc->busy = true;
7177                         } else {
7178                                 /* Busy -> busy, put off timer */
7179                                 mod_timer(&intel_crtc->idle_timer, jiffies +
7180                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7181                         }
7182                 }
7183         }
7184 }
7185
7186 static void intel_crtc_destroy(struct drm_crtc *crtc)
7187 {
7188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7189         struct drm_device *dev = crtc->dev;
7190         struct intel_unpin_work *work;
7191         unsigned long flags;
7192
7193         spin_lock_irqsave(&dev->event_lock, flags);
7194         work = intel_crtc->unpin_work;
7195         intel_crtc->unpin_work = NULL;
7196         spin_unlock_irqrestore(&dev->event_lock, flags);
7197
7198         if (work) {
7199                 cancel_work_sync(&work->work);
7200                 kfree(work);
7201         }
7202
7203         drm_crtc_cleanup(crtc);
7204
7205         kfree(intel_crtc);
7206 }
7207
7208 static void intel_unpin_work_fn(struct work_struct *__work)
7209 {
7210         struct intel_unpin_work *work =
7211                 container_of(__work, struct intel_unpin_work, work);
7212
7213         mutex_lock(&work->dev->struct_mutex);
7214         intel_unpin_fb_obj(work->old_fb_obj);
7215         drm_gem_object_unreference(&work->pending_flip_obj->base);
7216         drm_gem_object_unreference(&work->old_fb_obj->base);
7217
7218         intel_update_fbc(work->dev);
7219         mutex_unlock(&work->dev->struct_mutex);
7220         kfree(work);
7221 }
7222
7223 static void do_intel_finish_page_flip(struct drm_device *dev,
7224                                       struct drm_crtc *crtc)
7225 {
7226         drm_i915_private_t *dev_priv = dev->dev_private;
7227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7228         struct intel_unpin_work *work;
7229         struct drm_i915_gem_object *obj;
7230         struct drm_pending_vblank_event *e;
7231         struct timeval tnow, tvbl;
7232         unsigned long flags;
7233
7234         /* Ignore early vblank irqs */
7235         if (intel_crtc == NULL)
7236                 return;
7237
7238         do_gettimeofday(&tnow);
7239
7240         spin_lock_irqsave(&dev->event_lock, flags);
7241         work = intel_crtc->unpin_work;
7242         if (work == NULL || !work->pending) {
7243                 spin_unlock_irqrestore(&dev->event_lock, flags);
7244                 return;
7245         }
7246
7247         intel_crtc->unpin_work = NULL;
7248
7249         if (work->event) {
7250                 e = work->event;
7251                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7252
7253                 /* Called before vblank count and timestamps have
7254                  * been updated for the vblank interval of flip
7255                  * completion? Need to increment vblank count and
7256                  * add one videorefresh duration to returned timestamp
7257                  * to account for this. We assume this happened if we
7258                  * get called over 0.9 frame durations after the last
7259                  * timestamped vblank.
7260                  *
7261                  * This calculation can not be used with vrefresh rates
7262                  * below 5Hz (10Hz to be on the safe side) without
7263                  * promoting to 64 integers.
7264                  */
7265                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7266                     9 * crtc->framedur_ns) {
7267                         e->event.sequence++;
7268                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7269                                              crtc->framedur_ns);
7270                 }
7271
7272                 e->event.tv_sec = tvbl.tv_sec;
7273                 e->event.tv_usec = tvbl.tv_usec;
7274
7275                 list_add_tail(&e->base.link,
7276                               &e->base.file_priv->event_list);
7277                 wake_up_interruptible(&e->base.file_priv->event_wait);
7278         }
7279
7280         drm_vblank_put(dev, intel_crtc->pipe);
7281
7282         spin_unlock_irqrestore(&dev->event_lock, flags);
7283
7284         obj = work->old_fb_obj;
7285
7286         atomic_clear_mask(1 << intel_crtc->plane,
7287                           &obj->pending_flip.counter);
7288         if (atomic_read(&obj->pending_flip) == 0)
7289                 wake_up(&dev_priv->pending_flip_queue);
7290
7291         schedule_work(&work->work);
7292
7293         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7294 }
7295
7296 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7297 {
7298         drm_i915_private_t *dev_priv = dev->dev_private;
7299         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7300
7301         do_intel_finish_page_flip(dev, crtc);
7302 }
7303
7304 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7305 {
7306         drm_i915_private_t *dev_priv = dev->dev_private;
7307         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7308
7309         do_intel_finish_page_flip(dev, crtc);
7310 }
7311
7312 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7313 {
7314         drm_i915_private_t *dev_priv = dev->dev_private;
7315         struct intel_crtc *intel_crtc =
7316                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7317         unsigned long flags;
7318
7319         spin_lock_irqsave(&dev->event_lock, flags);
7320         if (intel_crtc->unpin_work) {
7321                 if ((++intel_crtc->unpin_work->pending) > 1)
7322                         DRM_ERROR("Prepared flip multiple times\n");
7323         } else {
7324                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7325         }
7326         spin_unlock_irqrestore(&dev->event_lock, flags);
7327 }
7328
7329 static int intel_gen2_queue_flip(struct drm_device *dev,
7330                                  struct drm_crtc *crtc,
7331                                  struct drm_framebuffer *fb,
7332                                  struct drm_i915_gem_object *obj)
7333 {
7334         struct drm_i915_private *dev_priv = dev->dev_private;
7335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7336         unsigned long offset;
7337         u32 flip_mask;
7338         int ret;
7339
7340         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7341         if (ret)
7342                 goto out;
7343
7344         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7345         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7346
7347         ret = BEGIN_LP_RING(6);
7348         if (ret)
7349                 goto out;
7350
7351         /* Can't queue multiple flips, so wait for the previous
7352          * one to finish before executing the next.
7353          */
7354         if (intel_crtc->plane)
7355                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7356         else
7357                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7358         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7359         OUT_RING(MI_NOOP);
7360         OUT_RING(MI_DISPLAY_FLIP |
7361                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7362         OUT_RING(fb->pitches[0]);
7363         OUT_RING(obj->gtt_offset + offset);
7364         OUT_RING(0); /* aux display base address, unused */
7365         ADVANCE_LP_RING();
7366 out:
7367         return ret;
7368 }
7369
7370 static int intel_gen3_queue_flip(struct drm_device *dev,
7371                                  struct drm_crtc *crtc,
7372                                  struct drm_framebuffer *fb,
7373                                  struct drm_i915_gem_object *obj)
7374 {
7375         struct drm_i915_private *dev_priv = dev->dev_private;
7376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7377         unsigned long offset;
7378         u32 flip_mask;
7379         int ret;
7380
7381         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7382         if (ret)
7383                 goto out;
7384
7385         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7386         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7387
7388         ret = BEGIN_LP_RING(6);
7389         if (ret)
7390                 goto out;
7391
7392         if (intel_crtc->plane)
7393                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7394         else
7395                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7396         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7397         OUT_RING(MI_NOOP);
7398         OUT_RING(MI_DISPLAY_FLIP_I915 |
7399                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7400         OUT_RING(fb->pitches[0]);
7401         OUT_RING(obj->gtt_offset + offset);
7402         OUT_RING(MI_NOOP);
7403
7404         ADVANCE_LP_RING();
7405 out:
7406         return ret;
7407 }
7408
7409 static int intel_gen4_queue_flip(struct drm_device *dev,
7410                                  struct drm_crtc *crtc,
7411                                  struct drm_framebuffer *fb,
7412                                  struct drm_i915_gem_object *obj)
7413 {
7414         struct drm_i915_private *dev_priv = dev->dev_private;
7415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7416         uint32_t pf, pipesrc;
7417         int ret;
7418
7419         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7420         if (ret)
7421                 goto out;
7422
7423         ret = BEGIN_LP_RING(4);
7424         if (ret)
7425                 goto out;
7426
7427         /* i965+ uses the linear or tiled offsets from the
7428          * Display Registers (which do not change across a page-flip)
7429          * so we need only reprogram the base address.
7430          */
7431         OUT_RING(MI_DISPLAY_FLIP |
7432                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7433         OUT_RING(fb->pitches[0]);
7434         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7435
7436         /* XXX Enabling the panel-fitter across page-flip is so far
7437          * untested on non-native modes, so ignore it for now.
7438          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7439          */
7440         pf = 0;
7441         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7442         OUT_RING(pf | pipesrc);
7443         ADVANCE_LP_RING();
7444 out:
7445         return ret;
7446 }
7447
7448 static int intel_gen6_queue_flip(struct drm_device *dev,
7449                                  struct drm_crtc *crtc,
7450                                  struct drm_framebuffer *fb,
7451                                  struct drm_i915_gem_object *obj)
7452 {
7453         struct drm_i915_private *dev_priv = dev->dev_private;
7454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7455         uint32_t pf, pipesrc;
7456         int ret;
7457
7458         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7459         if (ret)
7460                 goto out;
7461
7462         ret = BEGIN_LP_RING(4);
7463         if (ret)
7464                 goto out;
7465
7466         OUT_RING(MI_DISPLAY_FLIP |
7467                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7468         OUT_RING(fb->pitches[0] | obj->tiling_mode);
7469         OUT_RING(obj->gtt_offset);
7470
7471         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7472         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7473         OUT_RING(pf | pipesrc);
7474         ADVANCE_LP_RING();
7475 out:
7476         return ret;
7477 }
7478
7479 /*
7480  * On gen7 we currently use the blit ring because (in early silicon at least)
7481  * the render ring doesn't give us interrpts for page flip completion, which
7482  * means clients will hang after the first flip is queued.  Fortunately the
7483  * blit ring generates interrupts properly, so use it instead.
7484  */
7485 static int intel_gen7_queue_flip(struct drm_device *dev,
7486                                  struct drm_crtc *crtc,
7487                                  struct drm_framebuffer *fb,
7488                                  struct drm_i915_gem_object *obj)
7489 {
7490         struct drm_i915_private *dev_priv = dev->dev_private;
7491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7492         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7493         int ret;
7494
7495         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7496         if (ret)
7497                 goto out;
7498
7499         ret = intel_ring_begin(ring, 4);
7500         if (ret)
7501                 goto out;
7502
7503         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7504         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7505         intel_ring_emit(ring, (obj->gtt_offset));
7506         intel_ring_emit(ring, (MI_NOOP));
7507         intel_ring_advance(ring);
7508 out:
7509         return ret;
7510 }
7511
7512 static int intel_default_queue_flip(struct drm_device *dev,
7513                                     struct drm_crtc *crtc,
7514                                     struct drm_framebuffer *fb,
7515                                     struct drm_i915_gem_object *obj)
7516 {
7517         return -ENODEV;
7518 }
7519
7520 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7521                                 struct drm_framebuffer *fb,
7522                                 struct drm_pending_vblank_event *event)
7523 {
7524         struct drm_device *dev = crtc->dev;
7525         struct drm_i915_private *dev_priv = dev->dev_private;
7526         struct intel_framebuffer *intel_fb;
7527         struct drm_i915_gem_object *obj;
7528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7529         struct intel_unpin_work *work;
7530         unsigned long flags;
7531         int ret;
7532
7533         work = kzalloc(sizeof *work, GFP_KERNEL);
7534         if (work == NULL)
7535                 return -ENOMEM;
7536
7537         work->event = event;
7538         work->dev = crtc->dev;
7539         intel_fb = to_intel_framebuffer(crtc->fb);
7540         work->old_fb_obj = intel_fb->obj;
7541         INIT_WORK(&work->work, intel_unpin_work_fn);
7542
7543         ret = drm_vblank_get(dev, intel_crtc->pipe);
7544         if (ret)
7545                 goto free_work;
7546
7547         /* We borrow the event spin lock for protecting unpin_work */
7548         spin_lock_irqsave(&dev->event_lock, flags);
7549         if (intel_crtc->unpin_work) {
7550                 spin_unlock_irqrestore(&dev->event_lock, flags);
7551                 kfree(work);
7552                 drm_vblank_put(dev, intel_crtc->pipe);
7553
7554                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7555                 return -EBUSY;
7556         }
7557         intel_crtc->unpin_work = work;
7558         spin_unlock_irqrestore(&dev->event_lock, flags);
7559
7560         intel_fb = to_intel_framebuffer(fb);
7561         obj = intel_fb->obj;
7562
7563         mutex_lock(&dev->struct_mutex);
7564
7565         /* Reference the objects for the scheduled work. */
7566         drm_gem_object_reference(&work->old_fb_obj->base);
7567         drm_gem_object_reference(&obj->base);
7568
7569         crtc->fb = fb;
7570
7571         work->pending_flip_obj = obj;
7572
7573         work->enable_stall_check = true;
7574
7575         /* Block clients from rendering to the new back buffer until
7576          * the flip occurs and the object is no longer visible.
7577          */
7578         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7579
7580         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7581         if (ret)
7582                 goto cleanup_pending;
7583
7584         intel_disable_fbc(dev);
7585         mutex_unlock(&dev->struct_mutex);
7586
7587         trace_i915_flip_request(intel_crtc->plane, obj);
7588
7589         return 0;
7590
7591 cleanup_pending:
7592         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7593         drm_gem_object_unreference(&work->old_fb_obj->base);
7594         drm_gem_object_unreference(&obj->base);
7595         mutex_unlock(&dev->struct_mutex);
7596
7597         spin_lock_irqsave(&dev->event_lock, flags);
7598         intel_crtc->unpin_work = NULL;
7599         spin_unlock_irqrestore(&dev->event_lock, flags);
7600
7601         drm_vblank_put(dev, intel_crtc->pipe);
7602 free_work:
7603         kfree(work);
7604
7605         return ret;
7606 }
7607
7608 static void intel_sanitize_modesetting(struct drm_device *dev,
7609                                        int pipe, int plane)
7610 {
7611         struct drm_i915_private *dev_priv = dev->dev_private;
7612         u32 reg, val;
7613
7614         if (HAS_PCH_SPLIT(dev))
7615                 return;
7616
7617         /* Who knows what state these registers were left in by the BIOS or
7618          * grub?
7619          *
7620          * If we leave the registers in a conflicting state (e.g. with the
7621          * display plane reading from the other pipe than the one we intend
7622          * to use) then when we attempt to teardown the active mode, we will
7623          * not disable the pipes and planes in the correct order -- leaving
7624          * a plane reading from a disabled pipe and possibly leading to
7625          * undefined behaviour.
7626          */
7627
7628         reg = DSPCNTR(plane);
7629         val = I915_READ(reg);
7630
7631         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7632                 return;
7633         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7634                 return;
7635
7636         /* This display plane is active and attached to the other CPU pipe. */
7637         pipe = !pipe;
7638
7639         /* Disable the plane and wait for it to stop reading from the pipe. */
7640         intel_disable_plane(dev_priv, plane, pipe);
7641         intel_disable_pipe(dev_priv, pipe);
7642 }
7643
7644 static void intel_crtc_reset(struct drm_crtc *crtc)
7645 {
7646         struct drm_device *dev = crtc->dev;
7647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7648
7649         /* Reset flags back to the 'unknown' status so that they
7650          * will be correctly set on the initial modeset.
7651          */
7652         intel_crtc->dpms_mode = -1;
7653
7654         /* We need to fix up any BIOS configuration that conflicts with
7655          * our expectations.
7656          */
7657         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7658 }
7659
7660 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7661         .dpms = intel_crtc_dpms,
7662         .mode_fixup = intel_crtc_mode_fixup,
7663         .mode_set = intel_crtc_mode_set,
7664         .mode_set_base = intel_pipe_set_base,
7665         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7666         .load_lut = intel_crtc_load_lut,
7667         .disable = intel_crtc_disable,
7668 };
7669
7670 static const struct drm_crtc_funcs intel_crtc_funcs = {
7671         .reset = intel_crtc_reset,
7672         .cursor_set = intel_crtc_cursor_set,
7673         .cursor_move = intel_crtc_cursor_move,
7674         .gamma_set = intel_crtc_gamma_set,
7675         .set_config = drm_crtc_helper_set_config,
7676         .destroy = intel_crtc_destroy,
7677         .page_flip = intel_crtc_page_flip,
7678 };
7679
7680 static void intel_crtc_init(struct drm_device *dev, int pipe)
7681 {
7682         drm_i915_private_t *dev_priv = dev->dev_private;
7683         struct intel_crtc *intel_crtc;
7684         int i;
7685
7686         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7687         if (intel_crtc == NULL)
7688                 return;
7689
7690         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7691
7692         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7693         for (i = 0; i < 256; i++) {
7694                 intel_crtc->lut_r[i] = i;
7695                 intel_crtc->lut_g[i] = i;
7696                 intel_crtc->lut_b[i] = i;
7697         }
7698
7699         /* Swap pipes & planes for FBC on pre-965 */
7700         intel_crtc->pipe = pipe;
7701         intel_crtc->plane = pipe;
7702         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7703                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7704                 intel_crtc->plane = !pipe;
7705         }
7706
7707         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7708                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7709         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7710         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7711
7712         intel_crtc_reset(&intel_crtc->base);
7713         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7714         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7715
7716         if (HAS_PCH_SPLIT(dev)) {
7717                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7718                         intel_crtc->no_pll = true;
7719                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7720                 intel_helper_funcs.commit = ironlake_crtc_commit;
7721         } else {
7722                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7723                 intel_helper_funcs.commit = i9xx_crtc_commit;
7724         }
7725
7726         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7727
7728         intel_crtc->busy = false;
7729
7730         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7731                     (unsigned long)intel_crtc);
7732 }
7733
7734 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7735                                 struct drm_file *file)
7736 {
7737         drm_i915_private_t *dev_priv = dev->dev_private;
7738         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7739         struct drm_mode_object *drmmode_obj;
7740         struct intel_crtc *crtc;
7741
7742         if (!dev_priv) {
7743                 DRM_ERROR("called with no initialization\n");
7744                 return -EINVAL;
7745         }
7746
7747         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7748                         DRM_MODE_OBJECT_CRTC);
7749
7750         if (!drmmode_obj) {
7751                 DRM_ERROR("no such CRTC id\n");
7752                 return -EINVAL;
7753         }
7754
7755         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7756         pipe_from_crtc_id->pipe = crtc->pipe;
7757
7758         return 0;
7759 }
7760
7761 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7762 {
7763         struct intel_encoder *encoder;
7764         int index_mask = 0;
7765         int entry = 0;
7766
7767         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7768                 if (type_mask & encoder->clone_mask)
7769                         index_mask |= (1 << entry);
7770                 entry++;
7771         }
7772
7773         return index_mask;
7774 }
7775
7776 static bool has_edp_a(struct drm_device *dev)
7777 {
7778         struct drm_i915_private *dev_priv = dev->dev_private;
7779
7780         if (!IS_MOBILE(dev))
7781                 return false;
7782
7783         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7784                 return false;
7785
7786         if (IS_GEN5(dev) &&
7787             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7788                 return false;
7789
7790         return true;
7791 }
7792
7793 static void intel_setup_outputs(struct drm_device *dev)
7794 {
7795         struct drm_i915_private *dev_priv = dev->dev_private;
7796         struct intel_encoder *encoder;
7797         bool dpd_is_edp = false;
7798         bool has_lvds;
7799
7800         has_lvds = intel_lvds_init(dev);
7801         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7802                 /* disable the panel fitter on everything but LVDS */
7803                 I915_WRITE(PFIT_CONTROL, 0);
7804         }
7805
7806         if (HAS_PCH_SPLIT(dev)) {
7807                 dpd_is_edp = intel_dpd_is_edp(dev);
7808
7809                 if (has_edp_a(dev))
7810                         intel_dp_init(dev, DP_A);
7811
7812                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7813                         intel_dp_init(dev, PCH_DP_D);
7814         }
7815
7816         intel_crt_init(dev);
7817
7818         if (HAS_PCH_SPLIT(dev)) {
7819                 int found;
7820
7821                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7822                         /* PCH SDVOB multiplex with HDMIB */
7823                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
7824                         if (!found)
7825                                 intel_hdmi_init(dev, HDMIB);
7826                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7827                                 intel_dp_init(dev, PCH_DP_B);
7828                 }
7829
7830                 if (I915_READ(HDMIC) & PORT_DETECTED)
7831                         intel_hdmi_init(dev, HDMIC);
7832
7833                 if (I915_READ(HDMID) & PORT_DETECTED)
7834                         intel_hdmi_init(dev, HDMID);
7835
7836                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7837                         intel_dp_init(dev, PCH_DP_C);
7838
7839                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7840                         intel_dp_init(dev, PCH_DP_D);
7841
7842         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7843                 bool found = false;
7844
7845                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7846                         DRM_DEBUG_KMS("probing SDVOB\n");
7847                         found = intel_sdvo_init(dev, SDVOB, true);
7848                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7849                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7850                                 intel_hdmi_init(dev, SDVOB);
7851                         }
7852
7853                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7854                                 DRM_DEBUG_KMS("probing DP_B\n");
7855                                 intel_dp_init(dev, DP_B);
7856                         }
7857                 }
7858
7859                 /* Before G4X SDVOC doesn't have its own detect register */
7860
7861                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7862                         DRM_DEBUG_KMS("probing SDVOC\n");
7863                         found = intel_sdvo_init(dev, SDVOC, false);
7864                 }
7865
7866                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7867
7868                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7869                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7870                                 intel_hdmi_init(dev, SDVOC);
7871                         }
7872                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7873                                 DRM_DEBUG_KMS("probing DP_C\n");
7874                                 intel_dp_init(dev, DP_C);
7875                         }
7876                 }
7877
7878                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7879                     (I915_READ(DP_D) & DP_DETECTED)) {
7880                         DRM_DEBUG_KMS("probing DP_D\n");
7881                         intel_dp_init(dev, DP_D);
7882                 }
7883         } else if (IS_GEN2(dev))
7884                 intel_dvo_init(dev);
7885
7886         if (SUPPORTS_TV(dev))
7887                 intel_tv_init(dev);
7888
7889         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7890                 encoder->base.possible_crtcs = encoder->crtc_mask;
7891                 encoder->base.possible_clones =
7892                         intel_encoder_clones(dev, encoder->clone_mask);
7893         }
7894
7895         /* disable all the possible outputs/crtcs before entering KMS mode */
7896         drm_helper_disable_unused_functions(dev);
7897
7898         if (HAS_PCH_SPLIT(dev))
7899                 ironlake_init_pch_refclk(dev);
7900 }
7901
7902 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7903 {
7904         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7905
7906         drm_framebuffer_cleanup(fb);
7907         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7908
7909         kfree(intel_fb);
7910 }
7911
7912 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7913                                                 struct drm_file *file,
7914                                                 unsigned int *handle)
7915 {
7916         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7917         struct drm_i915_gem_object *obj = intel_fb->obj;
7918
7919         return drm_gem_handle_create(file, &obj->base, handle);
7920 }
7921
7922 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7923         .destroy = intel_user_framebuffer_destroy,
7924         .create_handle = intel_user_framebuffer_create_handle,
7925 };
7926
7927 int intel_framebuffer_init(struct drm_device *dev,
7928                            struct intel_framebuffer *intel_fb,
7929                            struct drm_mode_fb_cmd2 *mode_cmd,
7930                            struct drm_i915_gem_object *obj)
7931 {
7932         int ret;
7933
7934         if (obj->tiling_mode == I915_TILING_Y)
7935                 return -EINVAL;
7936
7937         if (mode_cmd->pitches[0] & 63)
7938                 return -EINVAL;
7939
7940         switch (mode_cmd->pixel_format) {
7941         case DRM_FORMAT_RGB332:
7942         case DRM_FORMAT_RGB565:
7943         case DRM_FORMAT_XRGB8888:
7944         case DRM_FORMAT_ARGB8888:
7945         case DRM_FORMAT_XRGB2101010:
7946         case DRM_FORMAT_ARGB2101010:
7947                 /* RGB formats are common across chipsets */
7948                 break;
7949         case DRM_FORMAT_YUYV:
7950         case DRM_FORMAT_UYVY:
7951         case DRM_FORMAT_YVYU:
7952         case DRM_FORMAT_VYUY:
7953                 break;
7954         default:
7955                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7956                                 mode_cmd->pixel_format);
7957                 return -EINVAL;
7958         }
7959
7960         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7961         if (ret) {
7962                 DRM_ERROR("framebuffer init failed %d\n", ret);
7963                 return ret;
7964         }
7965
7966         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7967         intel_fb->obj = obj;
7968         return 0;
7969 }
7970
7971 static struct drm_framebuffer *
7972 intel_user_framebuffer_create(struct drm_device *dev,
7973                               struct drm_file *filp,
7974                               struct drm_mode_fb_cmd2 *mode_cmd)
7975 {
7976         struct drm_i915_gem_object *obj;
7977
7978         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7979                                                 mode_cmd->handles[0]));
7980         if (&obj->base == NULL)
7981                 return ERR_PTR(-ENOENT);
7982
7983         return intel_framebuffer_create(dev, mode_cmd, obj);
7984 }
7985
7986 static const struct drm_mode_config_funcs intel_mode_funcs = {
7987         .fb_create = intel_user_framebuffer_create,
7988         .output_poll_changed = intel_fb_output_poll_changed,
7989 };
7990
7991 static struct drm_i915_gem_object *
7992 intel_alloc_context_page(struct drm_device *dev)
7993 {
7994         struct drm_i915_gem_object *ctx;
7995         int ret;
7996
7997         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7998
7999         ctx = i915_gem_alloc_object(dev, 4096);
8000         if (!ctx) {
8001                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8002                 return NULL;
8003         }
8004
8005         ret = i915_gem_object_pin(ctx, 4096, true);
8006         if (ret) {
8007                 DRM_ERROR("failed to pin power context: %d\n", ret);
8008                 goto err_unref;
8009         }
8010
8011         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
8012         if (ret) {
8013                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8014                 goto err_unpin;
8015         }
8016
8017         return ctx;
8018
8019 err_unpin:
8020         i915_gem_object_unpin(ctx);
8021 err_unref:
8022         drm_gem_object_unreference(&ctx->base);
8023         mutex_unlock(&dev->struct_mutex);
8024         return NULL;
8025 }
8026
8027 bool ironlake_set_drps(struct drm_device *dev, u8 val)
8028 {
8029         struct drm_i915_private *dev_priv = dev->dev_private;
8030         u16 rgvswctl;
8031
8032         rgvswctl = I915_READ16(MEMSWCTL);
8033         if (rgvswctl & MEMCTL_CMD_STS) {
8034                 DRM_DEBUG("gpu busy, RCS change rejected\n");
8035                 return false; /* still busy with another command */
8036         }
8037
8038         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8039                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8040         I915_WRITE16(MEMSWCTL, rgvswctl);
8041         POSTING_READ16(MEMSWCTL);
8042
8043         rgvswctl |= MEMCTL_CMD_STS;
8044         I915_WRITE16(MEMSWCTL, rgvswctl);
8045
8046         return true;
8047 }
8048
8049 void ironlake_enable_drps(struct drm_device *dev)
8050 {
8051         struct drm_i915_private *dev_priv = dev->dev_private;
8052         u32 rgvmodectl = I915_READ(MEMMODECTL);
8053         u8 fmax, fmin, fstart, vstart;
8054
8055         /* Enable temp reporting */
8056         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8057         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8058
8059         /* 100ms RC evaluation intervals */
8060         I915_WRITE(RCUPEI, 100000);
8061         I915_WRITE(RCDNEI, 100000);
8062
8063         /* Set max/min thresholds to 90ms and 80ms respectively */
8064         I915_WRITE(RCBMAXAVG, 90000);
8065         I915_WRITE(RCBMINAVG, 80000);
8066
8067         I915_WRITE(MEMIHYST, 1);
8068
8069         /* Set up min, max, and cur for interrupt handling */
8070         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8071         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8072         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8073                 MEMMODE_FSTART_SHIFT;
8074
8075         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8076                 PXVFREQ_PX_SHIFT;
8077
8078         dev_priv->fmax = fmax; /* IPS callback will increase this */
8079         dev_priv->fstart = fstart;
8080
8081         dev_priv->max_delay = fstart;
8082         dev_priv->min_delay = fmin;
8083         dev_priv->cur_delay = fstart;
8084
8085         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8086                          fmax, fmin, fstart);
8087
8088         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8089
8090         /*
8091          * Interrupts will be enabled in ironlake_irq_postinstall
8092          */
8093
8094         I915_WRITE(VIDSTART, vstart);
8095         POSTING_READ(VIDSTART);
8096
8097         rgvmodectl |= MEMMODE_SWMODE_EN;
8098         I915_WRITE(MEMMODECTL, rgvmodectl);
8099
8100         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8101                 DRM_ERROR("stuck trying to change perf mode\n");
8102         msleep(1);
8103
8104         ironlake_set_drps(dev, fstart);
8105
8106         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8107                 I915_READ(0x112e0);
8108         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8109         dev_priv->last_count2 = I915_READ(0x112f4);
8110         getrawmonotonic(&dev_priv->last_time2);
8111 }
8112
8113 void ironlake_disable_drps(struct drm_device *dev)
8114 {
8115         struct drm_i915_private *dev_priv = dev->dev_private;
8116         u16 rgvswctl = I915_READ16(MEMSWCTL);
8117
8118         /* Ack interrupts, disable EFC interrupt */
8119         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8120         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8121         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8122         I915_WRITE(DEIIR, DE_PCU_EVENT);
8123         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8124
8125         /* Go back to the starting frequency */
8126         ironlake_set_drps(dev, dev_priv->fstart);
8127         msleep(1);
8128         rgvswctl |= MEMCTL_CMD_STS;
8129         I915_WRITE(MEMSWCTL, rgvswctl);
8130         msleep(1);
8131
8132 }
8133
8134 void gen6_set_rps(struct drm_device *dev, u8 val)
8135 {
8136         struct drm_i915_private *dev_priv = dev->dev_private;
8137         u32 swreq;
8138
8139         swreq = (val & 0x3ff) << 25;
8140         I915_WRITE(GEN6_RPNSWREQ, swreq);
8141 }
8142
8143 void gen6_disable_rps(struct drm_device *dev)
8144 {
8145         struct drm_i915_private *dev_priv = dev->dev_private;
8146
8147         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8148         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8149         I915_WRITE(GEN6_PMIER, 0);
8150         /* Complete PM interrupt masking here doesn't race with the rps work
8151          * item again unmasking PM interrupts because that is using a different
8152          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8153          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8154
8155         spin_lock_irq(&dev_priv->rps_lock);
8156         dev_priv->pm_iir = 0;
8157         spin_unlock_irq(&dev_priv->rps_lock);
8158
8159         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8160 }
8161
8162 static unsigned long intel_pxfreq(u32 vidfreq)
8163 {
8164         unsigned long freq;
8165         int div = (vidfreq & 0x3f0000) >> 16;
8166         int post = (vidfreq & 0x3000) >> 12;
8167         int pre = (vidfreq & 0x7);
8168
8169         if (!pre)
8170                 return 0;
8171
8172         freq = ((div * 133333) / ((1<<post) * pre));
8173
8174         return freq;
8175 }
8176
8177 void intel_init_emon(struct drm_device *dev)
8178 {
8179         struct drm_i915_private *dev_priv = dev->dev_private;
8180         u32 lcfuse;
8181         u8 pxw[16];
8182         int i;
8183
8184         /* Disable to program */
8185         I915_WRITE(ECR, 0);
8186         POSTING_READ(ECR);
8187
8188         /* Program energy weights for various events */
8189         I915_WRITE(SDEW, 0x15040d00);
8190         I915_WRITE(CSIEW0, 0x007f0000);
8191         I915_WRITE(CSIEW1, 0x1e220004);
8192         I915_WRITE(CSIEW2, 0x04000004);
8193
8194         for (i = 0; i < 5; i++)
8195                 I915_WRITE(PEW + (i * 4), 0);
8196         for (i = 0; i < 3; i++)
8197                 I915_WRITE(DEW + (i * 4), 0);
8198
8199         /* Program P-state weights to account for frequency power adjustment */
8200         for (i = 0; i < 16; i++) {
8201                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8202                 unsigned long freq = intel_pxfreq(pxvidfreq);
8203                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8204                         PXVFREQ_PX_SHIFT;
8205                 unsigned long val;
8206
8207                 val = vid * vid;
8208                 val *= (freq / 1000);
8209                 val *= 255;
8210                 val /= (127*127*900);
8211                 if (val > 0xff)
8212                         DRM_ERROR("bad pxval: %ld\n", val);
8213                 pxw[i] = val;
8214         }
8215         /* Render standby states get 0 weight */
8216         pxw[14] = 0;
8217         pxw[15] = 0;
8218
8219         for (i = 0; i < 4; i++) {
8220                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8221                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8222                 I915_WRITE(PXW + (i * 4), val);
8223         }
8224
8225         /* Adjust magic regs to magic values (more experimental results) */
8226         I915_WRITE(OGW0, 0);
8227         I915_WRITE(OGW1, 0);
8228         I915_WRITE(EG0, 0x00007f00);
8229         I915_WRITE(EG1, 0x0000000e);
8230         I915_WRITE(EG2, 0x000e0000);
8231         I915_WRITE(EG3, 0x68000300);
8232         I915_WRITE(EG4, 0x42000000);
8233         I915_WRITE(EG5, 0x00140031);
8234         I915_WRITE(EG6, 0);
8235         I915_WRITE(EG7, 0);
8236
8237         for (i = 0; i < 8; i++)
8238                 I915_WRITE(PXWL + (i * 4), 0);
8239
8240         /* Enable PMON + select events */
8241         I915_WRITE(ECR, 0x80000019);
8242
8243         lcfuse = I915_READ(LCFUSE02);
8244
8245         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8246 }
8247
8248 static bool intel_enable_rc6(struct drm_device *dev)
8249 {
8250         /*
8251          * Respect the kernel parameter if it is set
8252          */
8253         if (i915_enable_rc6 >= 0)
8254                 return i915_enable_rc6;
8255
8256         /*
8257          * Disable RC6 on Ironlake
8258          */
8259         if (INTEL_INFO(dev)->gen == 5)
8260                 return 0;
8261
8262         /*
8263          * Disable rc6 on Sandybridge
8264          */
8265         if (INTEL_INFO(dev)->gen == 6) {
8266                 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8267                 return 0;
8268         }
8269         DRM_DEBUG_DRIVER("RC6 enabled\n");
8270         return 1;
8271 }
8272
8273 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8274 {
8275         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8276         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8277         u32 pcu_mbox, rc6_mask = 0;
8278         u32 gtfifodbg;
8279         int cur_freq, min_freq, max_freq;
8280         int i;
8281
8282         /* Here begins a magic sequence of register writes to enable
8283          * auto-downclocking.
8284          *
8285          * Perhaps there might be some value in exposing these to
8286          * userspace...
8287          */
8288         I915_WRITE(GEN6_RC_STATE, 0);
8289         mutex_lock(&dev_priv->dev->struct_mutex);
8290
8291         /* Clear the DBG now so we don't confuse earlier errors */
8292         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8293                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8294                 I915_WRITE(GTFIFODBG, gtfifodbg);
8295         }
8296
8297         gen6_gt_force_wake_get(dev_priv);
8298
8299         /* disable the counters and set deterministic thresholds */
8300         I915_WRITE(GEN6_RC_CONTROL, 0);
8301
8302         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8303         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8304         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8305         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8306         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8307
8308         for (i = 0; i < I915_NUM_RINGS; i++)
8309                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8310
8311         I915_WRITE(GEN6_RC_SLEEP, 0);
8312         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8313         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8314         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8315         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8316
8317         if (intel_enable_rc6(dev_priv->dev))
8318                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8319                         GEN6_RC_CTL_RC6_ENABLE;
8320
8321         I915_WRITE(GEN6_RC_CONTROL,
8322                    rc6_mask |
8323                    GEN6_RC_CTL_EI_MODE(1) |
8324                    GEN6_RC_CTL_HW_ENABLE);
8325
8326         I915_WRITE(GEN6_RPNSWREQ,
8327                    GEN6_FREQUENCY(10) |
8328                    GEN6_OFFSET(0) |
8329                    GEN6_AGGRESSIVE_TURBO);
8330         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8331                    GEN6_FREQUENCY(12));
8332
8333         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8334         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8335                    18 << 24 |
8336                    6 << 16);
8337         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8338         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8339         I915_WRITE(GEN6_RP_UP_EI, 100000);
8340         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8341         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8342         I915_WRITE(GEN6_RP_CONTROL,
8343                    GEN6_RP_MEDIA_TURBO |
8344                    GEN6_RP_MEDIA_HW_MODE |
8345                    GEN6_RP_MEDIA_IS_GFX |
8346                    GEN6_RP_ENABLE |
8347                    GEN6_RP_UP_BUSY_AVG |
8348                    GEN6_RP_DOWN_IDLE_CONT);
8349
8350         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8351                      500))
8352                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8353
8354         I915_WRITE(GEN6_PCODE_DATA, 0);
8355         I915_WRITE(GEN6_PCODE_MAILBOX,
8356                    GEN6_PCODE_READY |
8357                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8358         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8359                      500))
8360                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8361
8362         min_freq = (rp_state_cap & 0xff0000) >> 16;
8363         max_freq = rp_state_cap & 0xff;
8364         cur_freq = (gt_perf_status & 0xff00) >> 8;
8365
8366         /* Check for overclock support */
8367         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8368                      500))
8369                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8370         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8371         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8372         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8373                      500))
8374                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8375         if (pcu_mbox & (1<<31)) { /* OC supported */
8376                 max_freq = pcu_mbox & 0xff;
8377                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8378         }
8379
8380         /* In units of 100MHz */
8381         dev_priv->max_delay = max_freq;
8382         dev_priv->min_delay = min_freq;
8383         dev_priv->cur_delay = cur_freq;
8384
8385         /* requires MSI enabled */
8386         I915_WRITE(GEN6_PMIER,
8387                    GEN6_PM_MBOX_EVENT |
8388                    GEN6_PM_THERMAL_EVENT |
8389                    GEN6_PM_RP_DOWN_TIMEOUT |
8390                    GEN6_PM_RP_UP_THRESHOLD |
8391                    GEN6_PM_RP_DOWN_THRESHOLD |
8392                    GEN6_PM_RP_UP_EI_EXPIRED |
8393                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8394         spin_lock_irq(&dev_priv->rps_lock);
8395         WARN_ON(dev_priv->pm_iir != 0);
8396         I915_WRITE(GEN6_PMIMR, 0);
8397         spin_unlock_irq(&dev_priv->rps_lock);
8398         /* enable all PM interrupts */
8399         I915_WRITE(GEN6_PMINTRMSK, 0);
8400
8401         gen6_gt_force_wake_put(dev_priv);
8402         mutex_unlock(&dev_priv->dev->struct_mutex);
8403 }
8404
8405 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8406 {
8407         int min_freq = 15;
8408         int gpu_freq, ia_freq, max_ia_freq;
8409         int scaling_factor = 180;
8410
8411         max_ia_freq = cpufreq_quick_get_max(0);
8412         /*
8413          * Default to measured freq if none found, PCU will ensure we don't go
8414          * over
8415          */
8416         if (!max_ia_freq)
8417                 max_ia_freq = tsc_khz;
8418
8419         /* Convert from kHz to MHz */
8420         max_ia_freq /= 1000;
8421
8422         mutex_lock(&dev_priv->dev->struct_mutex);
8423
8424         /*
8425          * For each potential GPU frequency, load a ring frequency we'd like
8426          * to use for memory access.  We do this by specifying the IA frequency
8427          * the PCU should use as a reference to determine the ring frequency.
8428          */
8429         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8430              gpu_freq--) {
8431                 int diff = dev_priv->max_delay - gpu_freq;
8432
8433                 /*
8434                  * For GPU frequencies less than 750MHz, just use the lowest
8435                  * ring freq.
8436                  */
8437                 if (gpu_freq < min_freq)
8438                         ia_freq = 800;
8439                 else
8440                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8441                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8442
8443                 I915_WRITE(GEN6_PCODE_DATA,
8444                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8445                            gpu_freq);
8446                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8447                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8448                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8449                               GEN6_PCODE_READY) == 0, 10)) {
8450                         DRM_ERROR("pcode write of freq table timed out\n");
8451                         continue;
8452                 }
8453         }
8454
8455         mutex_unlock(&dev_priv->dev->struct_mutex);
8456 }
8457
8458 static void ironlake_init_clock_gating(struct drm_device *dev)
8459 {
8460         struct drm_i915_private *dev_priv = dev->dev_private;
8461         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8462
8463         /* Required for FBC */
8464         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8465                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8466                 DPFDUNIT_CLOCK_GATE_DISABLE;
8467         /* Required for CxSR */
8468         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8469
8470         I915_WRITE(PCH_3DCGDIS0,
8471                    MARIUNIT_CLOCK_GATE_DISABLE |
8472                    SVSMUNIT_CLOCK_GATE_DISABLE);
8473         I915_WRITE(PCH_3DCGDIS1,
8474                    VFMUNIT_CLOCK_GATE_DISABLE);
8475
8476         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8477
8478         /*
8479          * According to the spec the following bits should be set in
8480          * order to enable memory self-refresh
8481          * The bit 22/21 of 0x42004
8482          * The bit 5 of 0x42020
8483          * The bit 15 of 0x45000
8484          */
8485         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8486                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8487                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8488         I915_WRITE(ILK_DSPCLK_GATE,
8489                    (I915_READ(ILK_DSPCLK_GATE) |
8490                     ILK_DPARB_CLK_GATE));
8491         I915_WRITE(DISP_ARB_CTL,
8492                    (I915_READ(DISP_ARB_CTL) |
8493                     DISP_FBC_WM_DIS));
8494         I915_WRITE(WM3_LP_ILK, 0);
8495         I915_WRITE(WM2_LP_ILK, 0);
8496         I915_WRITE(WM1_LP_ILK, 0);
8497
8498         /*
8499          * Based on the document from hardware guys the following bits
8500          * should be set unconditionally in order to enable FBC.
8501          * The bit 22 of 0x42000
8502          * The bit 22 of 0x42004
8503          * The bit 7,8,9 of 0x42020.
8504          */
8505         if (IS_IRONLAKE_M(dev)) {
8506                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8507                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8508                            ILK_FBCQ_DIS);
8509                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8510                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8511                            ILK_DPARB_GATE);
8512                 I915_WRITE(ILK_DSPCLK_GATE,
8513                            I915_READ(ILK_DSPCLK_GATE) |
8514                            ILK_DPFC_DIS1 |
8515                            ILK_DPFC_DIS2 |
8516                            ILK_CLK_FBC);
8517         }
8518
8519         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8520                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8521                    ILK_ELPIN_409_SELECT);
8522         I915_WRITE(_3D_CHICKEN2,
8523                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8524                    _3D_CHICKEN2_WM_READ_PIPELINED);
8525 }
8526
8527 static void gen6_init_clock_gating(struct drm_device *dev)
8528 {
8529         struct drm_i915_private *dev_priv = dev->dev_private;
8530         int pipe;
8531         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8532
8533         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8534
8535         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8536                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8537                    ILK_ELPIN_409_SELECT);
8538
8539         I915_WRITE(WM3_LP_ILK, 0);
8540         I915_WRITE(WM2_LP_ILK, 0);
8541         I915_WRITE(WM1_LP_ILK, 0);
8542
8543         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8544          * gating disable must be set.  Failure to set it results in
8545          * flickering pixels due to Z write ordering failures after
8546          * some amount of runtime in the Mesa "fire" demo, and Unigine
8547          * Sanctuary and Tropics, and apparently anything else with
8548          * alpha test or pixel discard.
8549          *
8550          * According to the spec, bit 11 (RCCUNIT) must also be set,
8551          * but we didn't debug actual testcases to find it out.
8552          */
8553         I915_WRITE(GEN6_UCGCTL2,
8554                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8555                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8556
8557         /*
8558          * According to the spec the following bits should be
8559          * set in order to enable memory self-refresh and fbc:
8560          * The bit21 and bit22 of 0x42000
8561          * The bit21 and bit22 of 0x42004
8562          * The bit5 and bit7 of 0x42020
8563          * The bit14 of 0x70180
8564          * The bit14 of 0x71180
8565          */
8566         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8567                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8568                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8569         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8570                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8571                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8572         I915_WRITE(ILK_DSPCLK_GATE,
8573                    I915_READ(ILK_DSPCLK_GATE) |
8574                    ILK_DPARB_CLK_GATE  |
8575                    ILK_DPFD_CLK_GATE);
8576
8577         for_each_pipe(pipe) {
8578                 I915_WRITE(DSPCNTR(pipe),
8579                            I915_READ(DSPCNTR(pipe)) |
8580                            DISPPLANE_TRICKLE_FEED_DISABLE);
8581                 intel_flush_display_plane(dev_priv, pipe);
8582         }
8583 }
8584
8585 static void ivybridge_init_clock_gating(struct drm_device *dev)
8586 {
8587         struct drm_i915_private *dev_priv = dev->dev_private;
8588         int pipe;
8589         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8590
8591         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8592
8593         I915_WRITE(WM3_LP_ILK, 0);
8594         I915_WRITE(WM2_LP_ILK, 0);
8595         I915_WRITE(WM1_LP_ILK, 0);
8596
8597         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8598
8599         I915_WRITE(IVB_CHICKEN3,
8600                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8601                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8602
8603         for_each_pipe(pipe) {
8604                 I915_WRITE(DSPCNTR(pipe),
8605                            I915_READ(DSPCNTR(pipe)) |
8606                            DISPPLANE_TRICKLE_FEED_DISABLE);
8607                 intel_flush_display_plane(dev_priv, pipe);
8608         }
8609 }
8610
8611 static void g4x_init_clock_gating(struct drm_device *dev)
8612 {
8613         struct drm_i915_private *dev_priv = dev->dev_private;
8614         uint32_t dspclk_gate;
8615
8616         I915_WRITE(RENCLK_GATE_D1, 0);
8617         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8618                    GS_UNIT_CLOCK_GATE_DISABLE |
8619                    CL_UNIT_CLOCK_GATE_DISABLE);
8620         I915_WRITE(RAMCLK_GATE_D, 0);
8621         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8622                 OVRUNIT_CLOCK_GATE_DISABLE |
8623                 OVCUNIT_CLOCK_GATE_DISABLE;
8624         if (IS_GM45(dev))
8625                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8626         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8627 }
8628
8629 static void crestline_init_clock_gating(struct drm_device *dev)
8630 {
8631         struct drm_i915_private *dev_priv = dev->dev_private;
8632
8633         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8634         I915_WRITE(RENCLK_GATE_D2, 0);
8635         I915_WRITE(DSPCLK_GATE_D, 0);
8636         I915_WRITE(RAMCLK_GATE_D, 0);
8637         I915_WRITE16(DEUC, 0);
8638 }
8639
8640 static void broadwater_init_clock_gating(struct drm_device *dev)
8641 {
8642         struct drm_i915_private *dev_priv = dev->dev_private;
8643
8644         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8645                    I965_RCC_CLOCK_GATE_DISABLE |
8646                    I965_RCPB_CLOCK_GATE_DISABLE |
8647                    I965_ISC_CLOCK_GATE_DISABLE |
8648                    I965_FBC_CLOCK_GATE_DISABLE);
8649         I915_WRITE(RENCLK_GATE_D2, 0);
8650 }
8651
8652 static void gen3_init_clock_gating(struct drm_device *dev)
8653 {
8654         struct drm_i915_private *dev_priv = dev->dev_private;
8655         u32 dstate = I915_READ(D_STATE);
8656
8657         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8658                 DSTATE_DOT_CLOCK_GATING;
8659         I915_WRITE(D_STATE, dstate);
8660 }
8661
8662 static void i85x_init_clock_gating(struct drm_device *dev)
8663 {
8664         struct drm_i915_private *dev_priv = dev->dev_private;
8665
8666         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8667 }
8668
8669 static void i830_init_clock_gating(struct drm_device *dev)
8670 {
8671         struct drm_i915_private *dev_priv = dev->dev_private;
8672
8673         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8674 }
8675
8676 static void ibx_init_clock_gating(struct drm_device *dev)
8677 {
8678         struct drm_i915_private *dev_priv = dev->dev_private;
8679
8680         /*
8681          * On Ibex Peak and Cougar Point, we need to disable clock
8682          * gating for the panel power sequencer or it will fail to
8683          * start up when no ports are active.
8684          */
8685         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8686 }
8687
8688 static void cpt_init_clock_gating(struct drm_device *dev)
8689 {
8690         struct drm_i915_private *dev_priv = dev->dev_private;
8691         int pipe;
8692
8693         /*
8694          * On Ibex Peak and Cougar Point, we need to disable clock
8695          * gating for the panel power sequencer or it will fail to
8696          * start up when no ports are active.
8697          */
8698         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8699         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8700                    DPLS_EDP_PPS_FIX_DIS);
8701         /* Without this, mode sets may fail silently on FDI */
8702         for_each_pipe(pipe)
8703                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8704 }
8705
8706 static void ironlake_teardown_rc6(struct drm_device *dev)
8707 {
8708         struct drm_i915_private *dev_priv = dev->dev_private;
8709
8710         if (dev_priv->renderctx) {
8711                 i915_gem_object_unpin(dev_priv->renderctx);
8712                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8713                 dev_priv->renderctx = NULL;
8714         }
8715
8716         if (dev_priv->pwrctx) {
8717                 i915_gem_object_unpin(dev_priv->pwrctx);
8718                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8719                 dev_priv->pwrctx = NULL;
8720         }
8721 }
8722
8723 static void ironlake_disable_rc6(struct drm_device *dev)
8724 {
8725         struct drm_i915_private *dev_priv = dev->dev_private;
8726
8727         if (I915_READ(PWRCTXA)) {
8728                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8729                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8730                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8731                          50);
8732
8733                 I915_WRITE(PWRCTXA, 0);
8734                 POSTING_READ(PWRCTXA);
8735
8736                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8737                 POSTING_READ(RSTDBYCTL);
8738         }
8739
8740         ironlake_teardown_rc6(dev);
8741 }
8742
8743 static int ironlake_setup_rc6(struct drm_device *dev)
8744 {
8745         struct drm_i915_private *dev_priv = dev->dev_private;
8746
8747         if (dev_priv->renderctx == NULL)
8748                 dev_priv->renderctx = intel_alloc_context_page(dev);
8749         if (!dev_priv->renderctx)
8750                 return -ENOMEM;
8751
8752         if (dev_priv->pwrctx == NULL)
8753                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8754         if (!dev_priv->pwrctx) {
8755                 ironlake_teardown_rc6(dev);
8756                 return -ENOMEM;
8757         }
8758
8759         return 0;
8760 }
8761
8762 void ironlake_enable_rc6(struct drm_device *dev)
8763 {
8764         struct drm_i915_private *dev_priv = dev->dev_private;
8765         int ret;
8766
8767         /* rc6 disabled by default due to repeated reports of hanging during
8768          * boot and resume.
8769          */
8770         if (!intel_enable_rc6(dev))
8771                 return;
8772
8773         mutex_lock(&dev->struct_mutex);
8774         ret = ironlake_setup_rc6(dev);
8775         if (ret) {
8776                 mutex_unlock(&dev->struct_mutex);
8777                 return;
8778         }
8779
8780         /*
8781          * GPU can automatically power down the render unit if given a page
8782          * to save state.
8783          */
8784         ret = BEGIN_LP_RING(6);
8785         if (ret) {
8786                 ironlake_teardown_rc6(dev);
8787                 mutex_unlock(&dev->struct_mutex);
8788                 return;
8789         }
8790
8791         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8792         OUT_RING(MI_SET_CONTEXT);
8793         OUT_RING(dev_priv->renderctx->gtt_offset |
8794                  MI_MM_SPACE_GTT |
8795                  MI_SAVE_EXT_STATE_EN |
8796                  MI_RESTORE_EXT_STATE_EN |
8797                  MI_RESTORE_INHIBIT);
8798         OUT_RING(MI_SUSPEND_FLUSH);
8799         OUT_RING(MI_NOOP);
8800         OUT_RING(MI_FLUSH);
8801         ADVANCE_LP_RING();
8802
8803         /*
8804          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8805          * does an implicit flush, combined with MI_FLUSH above, it should be
8806          * safe to assume that renderctx is valid
8807          */
8808         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8809         if (ret) {
8810                 DRM_ERROR("failed to enable ironlake power power savings\n");
8811                 ironlake_teardown_rc6(dev);
8812                 mutex_unlock(&dev->struct_mutex);
8813                 return;
8814         }
8815
8816         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8817         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8818         mutex_unlock(&dev->struct_mutex);
8819 }
8820
8821 void intel_init_clock_gating(struct drm_device *dev)
8822 {
8823         struct drm_i915_private *dev_priv = dev->dev_private;
8824
8825         dev_priv->display.init_clock_gating(dev);
8826
8827         if (dev_priv->display.init_pch_clock_gating)
8828                 dev_priv->display.init_pch_clock_gating(dev);
8829 }
8830
8831 /* Set up chip specific display functions */
8832 static void intel_init_display(struct drm_device *dev)
8833 {
8834         struct drm_i915_private *dev_priv = dev->dev_private;
8835
8836         /* We always want a DPMS function */
8837         if (HAS_PCH_SPLIT(dev)) {
8838                 dev_priv->display.dpms = ironlake_crtc_dpms;
8839                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8840                 dev_priv->display.update_plane = ironlake_update_plane;
8841         } else {
8842                 dev_priv->display.dpms = i9xx_crtc_dpms;
8843                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8844                 dev_priv->display.update_plane = i9xx_update_plane;
8845         }
8846
8847         if (I915_HAS_FBC(dev)) {
8848                 if (HAS_PCH_SPLIT(dev)) {
8849                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8850                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8851                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8852                 } else if (IS_GM45(dev)) {
8853                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8854                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8855                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8856                 } else if (IS_CRESTLINE(dev)) {
8857                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8858                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8859                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8860                 }
8861                 /* 855GM needs testing */
8862         }
8863
8864         /* Returns the core display clock speed */
8865         if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8866                 dev_priv->display.get_display_clock_speed =
8867                         i945_get_display_clock_speed;
8868         else if (IS_I915G(dev))
8869                 dev_priv->display.get_display_clock_speed =
8870                         i915_get_display_clock_speed;
8871         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8872                 dev_priv->display.get_display_clock_speed =
8873                         i9xx_misc_get_display_clock_speed;
8874         else if (IS_I915GM(dev))
8875                 dev_priv->display.get_display_clock_speed =
8876                         i915gm_get_display_clock_speed;
8877         else if (IS_I865G(dev))
8878                 dev_priv->display.get_display_clock_speed =
8879                         i865_get_display_clock_speed;
8880         else if (IS_I85X(dev))
8881                 dev_priv->display.get_display_clock_speed =
8882                         i855_get_display_clock_speed;
8883         else /* 852, 830 */
8884                 dev_priv->display.get_display_clock_speed =
8885                         i830_get_display_clock_speed;
8886
8887         /* For FIFO watermark updates */
8888         if (HAS_PCH_SPLIT(dev)) {
8889                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8890                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8891
8892                 /* IVB configs may use multi-threaded forcewake */
8893                 if (IS_IVYBRIDGE(dev)) {
8894                         u32     ecobus;
8895
8896                         /* A small trick here - if the bios hasn't configured MT forcewake,
8897                          * and if the device is in RC6, then force_wake_mt_get will not wake
8898                          * the device and the ECOBUS read will return zero. Which will be
8899                          * (correctly) interpreted by the test below as MT forcewake being
8900                          * disabled.
8901                          */
8902                         mutex_lock(&dev->struct_mutex);
8903                         __gen6_gt_force_wake_mt_get(dev_priv);
8904                         ecobus = I915_READ_NOTRACE(ECOBUS);
8905                         __gen6_gt_force_wake_mt_put(dev_priv);
8906                         mutex_unlock(&dev->struct_mutex);
8907
8908                         if (ecobus & FORCEWAKE_MT_ENABLE) {
8909                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8910                                 dev_priv->display.force_wake_get =
8911                                         __gen6_gt_force_wake_mt_get;
8912                                 dev_priv->display.force_wake_put =
8913                                         __gen6_gt_force_wake_mt_put;
8914                         }
8915                 }
8916
8917                 if (HAS_PCH_IBX(dev))
8918                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8919                 else if (HAS_PCH_CPT(dev))
8920                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8921
8922                 if (IS_GEN5(dev)) {
8923                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8924                                 dev_priv->display.update_wm = ironlake_update_wm;
8925                         else {
8926                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8927                                               "Disable CxSR\n");
8928                                 dev_priv->display.update_wm = NULL;
8929                         }
8930                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8931                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8932                         dev_priv->display.write_eld = ironlake_write_eld;
8933                 } else if (IS_GEN6(dev)) {
8934                         if (SNB_READ_WM0_LATENCY()) {
8935                                 dev_priv->display.update_wm = sandybridge_update_wm;
8936                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8937                         } else {
8938                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8939                                               "Disable CxSR\n");
8940                                 dev_priv->display.update_wm = NULL;
8941                         }
8942                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8943                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8944                         dev_priv->display.write_eld = ironlake_write_eld;
8945                 } else if (IS_IVYBRIDGE(dev)) {
8946                         /* FIXME: detect B0+ stepping and use auto training */
8947                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8948                         if (SNB_READ_WM0_LATENCY()) {
8949                                 dev_priv->display.update_wm = sandybridge_update_wm;
8950                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8951                         } else {
8952                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8953                                               "Disable CxSR\n");
8954                                 dev_priv->display.update_wm = NULL;
8955                         }
8956                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8957                         dev_priv->display.write_eld = ironlake_write_eld;
8958                 } else
8959                         dev_priv->display.update_wm = NULL;
8960         } else if (IS_PINEVIEW(dev)) {
8961                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8962                                             dev_priv->is_ddr3,
8963                                             dev_priv->fsb_freq,
8964                                             dev_priv->mem_freq)) {
8965                         DRM_INFO("failed to find known CxSR latency "
8966                                  "(found ddr%s fsb freq %d, mem freq %d), "
8967                                  "disabling CxSR\n",
8968                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8969                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8970                         /* Disable CxSR and never update its watermark again */
8971                         pineview_disable_cxsr(dev);
8972                         dev_priv->display.update_wm = NULL;
8973                 } else
8974                         dev_priv->display.update_wm = pineview_update_wm;
8975                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8976         } else if (IS_G4X(dev)) {
8977                 dev_priv->display.write_eld = g4x_write_eld;
8978                 dev_priv->display.update_wm = g4x_update_wm;
8979                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8980         } else if (IS_GEN4(dev)) {
8981                 dev_priv->display.update_wm = i965_update_wm;
8982                 if (IS_CRESTLINE(dev))
8983                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8984                 else if (IS_BROADWATER(dev))
8985                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8986         } else if (IS_GEN3(dev)) {
8987                 dev_priv->display.update_wm = i9xx_update_wm;
8988                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8989                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8990         } else if (IS_I865G(dev)) {
8991                 dev_priv->display.update_wm = i830_update_wm;
8992                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8993                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8994         } else if (IS_I85X(dev)) {
8995                 dev_priv->display.update_wm = i9xx_update_wm;
8996                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8997                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8998         } else {
8999                 dev_priv->display.update_wm = i830_update_wm;
9000                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9001                 if (IS_845G(dev))
9002                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
9003                 else
9004                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
9005         }
9006
9007         /* Default just returns -ENODEV to indicate unsupported */
9008         dev_priv->display.queue_flip = intel_default_queue_flip;
9009
9010         switch (INTEL_INFO(dev)->gen) {
9011         case 2:
9012                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9013                 break;
9014
9015         case 3:
9016                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9017                 break;
9018
9019         case 4:
9020         case 5:
9021                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9022                 break;
9023
9024         case 6:
9025                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9026                 break;
9027         case 7:
9028                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9029                 break;
9030         }
9031 }
9032
9033 /*
9034  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9035  * resume, or other times.  This quirk makes sure that's the case for
9036  * affected systems.
9037  */
9038 static void quirk_pipea_force(struct drm_device *dev)
9039 {
9040         struct drm_i915_private *dev_priv = dev->dev_private;
9041
9042         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9043         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9044 }
9045
9046 /*
9047  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9048  */
9049 static void quirk_ssc_force_disable(struct drm_device *dev)
9050 {
9051         struct drm_i915_private *dev_priv = dev->dev_private;
9052         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9053 }
9054
9055 /*
9056  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9057  * brightness value
9058  */
9059 static void quirk_invert_brightness(struct drm_device *dev)
9060 {
9061         struct drm_i915_private *dev_priv = dev->dev_private;
9062         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9063 }
9064
9065 struct intel_quirk {
9066         int device;
9067         int subsystem_vendor;
9068         int subsystem_device;
9069         void (*hook)(struct drm_device *dev);
9070 };
9071
9072 struct intel_quirk intel_quirks[] = {
9073         /* HP Mini needs pipe A force quirk (LP: #322104) */
9074         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9075
9076         /* Thinkpad R31 needs pipe A force quirk */
9077         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9078         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9079         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9080
9081         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9082         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
9083         /* ThinkPad X40 needs pipe A force quirk */
9084
9085         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9086         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9087
9088         /* 855 & before need to leave pipe A & dpll A up */
9089         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9090         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9091
9092         /* Lenovo U160 cannot use SSC on LVDS */
9093         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9094
9095         /* Sony Vaio Y cannot use SSC on LVDS */
9096         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9097
9098         /* Acer Aspire 5734Z must invert backlight brightness */
9099         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9100 };
9101
9102 static void intel_init_quirks(struct drm_device *dev)
9103 {
9104         struct pci_dev *d = dev->pdev;
9105         int i;
9106
9107         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9108                 struct intel_quirk *q = &intel_quirks[i];
9109
9110                 if (d->device == q->device &&
9111                     (d->subsystem_vendor == q->subsystem_vendor ||
9112                      q->subsystem_vendor == PCI_ANY_ID) &&
9113                     (d->subsystem_device == q->subsystem_device ||
9114                      q->subsystem_device == PCI_ANY_ID))
9115                         q->hook(dev);
9116         }
9117 }
9118
9119 /* Disable the VGA plane that we never use */
9120 static void i915_disable_vga(struct drm_device *dev)
9121 {
9122         struct drm_i915_private *dev_priv = dev->dev_private;
9123         u8 sr1;
9124         u32 vga_reg;
9125
9126         if (HAS_PCH_SPLIT(dev))
9127                 vga_reg = CPU_VGACNTRL;
9128         else
9129                 vga_reg = VGACNTRL;
9130
9131         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9132         outb(1, VGA_SR_INDEX);
9133         sr1 = inb(VGA_SR_DATA);
9134         outb(sr1 | 1<<5, VGA_SR_DATA);
9135         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9136         udelay(300);
9137
9138         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9139         POSTING_READ(vga_reg);
9140 }
9141
9142 void intel_modeset_init(struct drm_device *dev)
9143 {
9144         struct drm_i915_private *dev_priv = dev->dev_private;
9145         int i, ret;
9146
9147         drm_mode_config_init(dev);
9148
9149         dev->mode_config.min_width = 0;
9150         dev->mode_config.min_height = 0;
9151
9152         dev->mode_config.preferred_depth = 24;
9153         dev->mode_config.prefer_shadow = 1;
9154
9155         dev->mode_config.funcs = (void *)&intel_mode_funcs;
9156
9157         intel_init_quirks(dev);
9158
9159         intel_init_display(dev);
9160
9161         if (IS_GEN2(dev)) {
9162                 dev->mode_config.max_width = 2048;
9163                 dev->mode_config.max_height = 2048;
9164         } else if (IS_GEN3(dev)) {
9165                 dev->mode_config.max_width = 4096;
9166                 dev->mode_config.max_height = 4096;
9167         } else {
9168                 dev->mode_config.max_width = 8192;
9169                 dev->mode_config.max_height = 8192;
9170         }
9171         dev->mode_config.fb_base = dev->agp->base;
9172
9173         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9174                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9175
9176         for (i = 0; i < dev_priv->num_pipe; i++) {
9177                 intel_crtc_init(dev, i);
9178                 ret = intel_plane_init(dev, i);
9179                 if (ret)
9180                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9181         }
9182
9183         /* Just disable it once at startup */
9184         i915_disable_vga(dev);
9185         intel_setup_outputs(dev);
9186
9187         intel_init_clock_gating(dev);
9188
9189         if (IS_IRONLAKE_M(dev)) {
9190                 ironlake_enable_drps(dev);
9191                 intel_init_emon(dev);
9192         }
9193
9194         if (IS_GEN6(dev) || IS_GEN7(dev)) {
9195                 gen6_enable_rps(dev_priv);
9196                 gen6_update_ring_freq(dev_priv);
9197         }
9198
9199         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9200         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9201                     (unsigned long)dev);
9202 }
9203
9204 void intel_modeset_gem_init(struct drm_device *dev)
9205 {
9206         if (IS_IRONLAKE_M(dev))
9207                 ironlake_enable_rc6(dev);
9208
9209         intel_setup_overlay(dev);
9210 }
9211
9212 void intel_modeset_cleanup(struct drm_device *dev)
9213 {
9214         struct drm_i915_private *dev_priv = dev->dev_private;
9215         struct drm_crtc *crtc;
9216         struct intel_crtc *intel_crtc;
9217
9218         drm_kms_helper_poll_fini(dev);
9219         mutex_lock(&dev->struct_mutex);
9220
9221         intel_unregister_dsm_handler();
9222
9223
9224         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9225                 /* Skip inactive CRTCs */
9226                 if (!crtc->fb)
9227                         continue;
9228
9229                 intel_crtc = to_intel_crtc(crtc);
9230                 intel_increase_pllclock(crtc);
9231         }
9232
9233         intel_disable_fbc(dev);
9234
9235         if (IS_IRONLAKE_M(dev))
9236                 ironlake_disable_drps(dev);
9237         if (IS_GEN6(dev) || IS_GEN7(dev))
9238                 gen6_disable_rps(dev);
9239
9240         if (IS_IRONLAKE_M(dev))
9241                 ironlake_disable_rc6(dev);
9242
9243         mutex_unlock(&dev->struct_mutex);
9244
9245         /* Disable the irq before mode object teardown, for the irq might
9246          * enqueue unpin/hotplug work. */
9247         drm_irq_uninstall(dev);
9248         cancel_work_sync(&dev_priv->hotplug_work);
9249         cancel_work_sync(&dev_priv->rps_work);
9250
9251         /* flush any delayed tasks or pending work */
9252         flush_scheduled_work();
9253
9254         /* Shut off idle work before the crtcs get freed. */
9255         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9256                 intel_crtc = to_intel_crtc(crtc);
9257                 del_timer_sync(&intel_crtc->idle_timer);
9258         }
9259         del_timer_sync(&dev_priv->idle_timer);
9260         cancel_work_sync(&dev_priv->idle_work);
9261
9262         drm_mode_config_cleanup(dev);
9263 }
9264
9265 /*
9266  * Return which encoder is currently attached for connector.
9267  */
9268 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9269 {
9270         return &intel_attached_encoder(connector)->base;
9271 }
9272
9273 void intel_connector_attach_encoder(struct intel_connector *connector,
9274                                     struct intel_encoder *encoder)
9275 {
9276         connector->encoder = encoder;
9277         drm_mode_connector_attach_encoder(&connector->base,
9278                                           &encoder->base);
9279 }
9280
9281 /*
9282  * set vga decode state - true == enable VGA decode
9283  */
9284 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9285 {
9286         struct drm_i915_private *dev_priv = dev->dev_private;
9287         u16 gmch_ctrl;
9288
9289         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9290         if (state)
9291                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9292         else
9293                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9294         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9295         return 0;
9296 }
9297
9298 #ifdef CONFIG_DEBUG_FS
9299 #include <linux/seq_file.h>
9300
9301 struct intel_display_error_state {
9302         struct intel_cursor_error_state {
9303                 u32 control;
9304                 u32 position;
9305                 u32 base;
9306                 u32 size;
9307         } cursor[2];
9308
9309         struct intel_pipe_error_state {
9310                 u32 conf;
9311                 u32 source;
9312
9313                 u32 htotal;
9314                 u32 hblank;
9315                 u32 hsync;
9316                 u32 vtotal;
9317                 u32 vblank;
9318                 u32 vsync;
9319         } pipe[2];
9320
9321         struct intel_plane_error_state {
9322                 u32 control;
9323                 u32 stride;
9324                 u32 size;
9325                 u32 pos;
9326                 u32 addr;
9327                 u32 surface;
9328                 u32 tile_offset;
9329         } plane[2];
9330 };
9331
9332 struct intel_display_error_state *
9333 intel_display_capture_error_state(struct drm_device *dev)
9334 {
9335         drm_i915_private_t *dev_priv = dev->dev_private;
9336         struct intel_display_error_state *error;
9337         int i;
9338
9339         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9340         if (error == NULL)
9341                 return NULL;
9342
9343         for (i = 0; i < 2; i++) {
9344                 error->cursor[i].control = I915_READ(CURCNTR(i));
9345                 error->cursor[i].position = I915_READ(CURPOS(i));
9346                 error->cursor[i].base = I915_READ(CURBASE(i));
9347
9348                 error->plane[i].control = I915_READ(DSPCNTR(i));
9349                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9350                 error->plane[i].size = I915_READ(DSPSIZE(i));
9351                 error->plane[i].pos = I915_READ(DSPPOS(i));
9352                 error->plane[i].addr = I915_READ(DSPADDR(i));
9353                 if (INTEL_INFO(dev)->gen >= 4) {
9354                         error->plane[i].surface = I915_READ(DSPSURF(i));
9355                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9356                 }
9357
9358                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9359                 error->pipe[i].source = I915_READ(PIPESRC(i));
9360                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9361                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9362                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9363                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9364                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9365                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9366         }
9367
9368         return error;
9369 }
9370
9371 void
9372 intel_display_print_error_state(struct seq_file *m,
9373                                 struct drm_device *dev,
9374                                 struct intel_display_error_state *error)
9375 {
9376         int i;
9377
9378         for (i = 0; i < 2; i++) {
9379                 seq_printf(m, "Pipe [%d]:\n", i);
9380                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9381                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9382                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9383                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9384                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9385                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9386                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9387                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9388
9389                 seq_printf(m, "Plane [%d]:\n", i);
9390                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9391                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9392                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9393                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9394                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9395                 if (INTEL_INFO(dev)->gen >= 4) {
9396                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9397                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9398                 }
9399
9400                 seq_printf(m, "Cursor [%d]:\n", i);
9401                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9402                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9403                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9404         }
9405 }
9406 #endif