2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
51 DRM_FORMAT_XRGB8888, \
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
73 static const uint32_t intel_cursor_formats[] = {
77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86 static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
98 static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100 static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
107 if (!connector->mst_port)
108 return connector->encoder;
110 return &connector->mst_port->mst_encoders[pipe]->base;
119 int p2_slow, p2_fast;
122 typedef struct intel_limit intel_limit_t;
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
129 intel_pch_rawclk(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
133 WARN_ON(!HAS_PCH_SPLIT(dev));
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
369 static const intel_limit_t intel_limits_vlv = {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv = {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401 static void vlv_clock(int refclk, intel_clock_t *clock)
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
412 * Returns whether any output on the specified pipe is of the specified type
414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
455 limit = &intel_limits_ironlake_dual_lvds;
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
460 limit = &intel_limits_ironlake_single_lvds;
463 limit = &intel_limits_ironlake_dac;
468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
511 limit = &intel_limits_i9xx_sdvo;
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
518 limit = &intel_limits_i8xx_dac;
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk, intel_clock_t *clock)
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
539 static void i9xx_clock(int refclk, intel_clock_t *clock)
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
549 static void chv_clock(int refclk, intel_clock_t *clock)
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
566 static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
606 struct drm_device *dev = crtc->base.dev;
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
619 clock.p2 = limit->p2.p2_slow;
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
624 clock.p2 = limit->p2.p2_fast;
627 memset(best_clock, 0, sizeof(*best_clock));
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
646 clock.p != match_clock->p)
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
659 return (err != target);
663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
667 struct drm_device *dev = crtc->base.dev;
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
680 clock.p2 = limit->p2.p2_slow;
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
685 clock.p2 = limit->p2.p2_fast;
688 memset(best_clock, 0, sizeof(*best_clock));
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
705 clock.p != match_clock->p)
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
718 return (err != target);
722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
726 struct drm_device *dev = crtc->base.dev;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
738 clock.p2 = limit->p2.p2_slow;
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
743 clock.p2 = limit->p2.p2_fast;
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
783 struct drm_device *dev = crtc->base.dev;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
790 target *= 5; /* fast clock */
792 memset(best_clock, 0, sizeof(*best_clock));
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
807 vlv_clock(refclk, &clock);
809 if (!intel_PLL_is_valid(dev, limit,
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
816 if (ppm < 100 && clock.p > best_clock->p) {
822 if (bestppm >= 10 && ppm < bestppm - 10) {
836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
840 struct drm_device *dev = crtc->base.dev;
845 memset(best_clock, 0, sizeof(*best_clock));
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
860 clock.p = clock.p1 * clock.p2;
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
865 if (m2 > INT_MAX/clock.m1)
870 chv_clock(refclk, &clock);
872 if (!intel_PLL_is_valid(dev, limit, &clock))
875 /* based on hardware requirement, prefer bigger p
877 if (clock.p > best_clock->p) {
887 bool intel_crtc_active(struct drm_crtc *crtc)
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
900 return intel_crtc->active && crtc->primary->fb &&
901 intel_crtc->config->base.adjusted_mode.crtc_clock;
904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
910 return intel_crtc->config->cpu_transcoder;
913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 u32 reg = PIPEDSL(pipe);
921 line_mask = DSL_LINEMASK_GEN2;
923 line_mask = DSL_LINEMASK_GEN3;
925 line1 = I915_READ(reg) & line_mask;
927 line2 = I915_READ(reg) & line_mask;
929 return line1 == line2;
933 * intel_wait_for_pipe_off - wait for pipe to turn off
934 * @crtc: crtc whose pipe to wait for
936 * After disabling a pipe, we can't wait for vblank in the usual way,
937 * spinning on the vblank interrupt status bit, since we won't actually
938 * see an interrupt when the pipe is disabled.
941 * wait for the pipe register state bit to turn off
944 * wait for the display line value to settle (it usually
945 * ends up stopping at the start of the next frame).
948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
950 struct drm_device *dev = crtc->base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
953 enum pipe pipe = crtc->pipe;
955 if (INTEL_INFO(dev)->gen >= 4) {
956 int reg = PIPECONF(cpu_transcoder);
958 /* Wait for the Pipe State to go off */
959 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
961 WARN(1, "pipe_off wait timed out\n");
963 /* Wait for the display line to settle */
964 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
965 WARN(1, "pipe_off wait timed out\n");
970 * ibx_digital_port_connected - is the specified port connected?
971 * @dev_priv: i915 private structure
972 * @port: the port to test
974 * Returns true if @port is connected, false otherwise.
976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
977 struct intel_digital_port *port)
981 if (HAS_PCH_IBX(dev_priv->dev)) {
982 switch (port->port) {
984 bit = SDE_PORTB_HOTPLUG;
987 bit = SDE_PORTC_HOTPLUG;
990 bit = SDE_PORTD_HOTPLUG;
996 switch (port->port) {
998 bit = SDE_PORTB_HOTPLUG_CPT;
1001 bit = SDE_PORTC_HOTPLUG_CPT;
1004 bit = SDE_PORTD_HOTPLUG_CPT;
1011 return I915_READ(SDEISR) & bit;
1014 static const char *state_string(bool enabled)
1016 return enabled ? "on" : "off";
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, bool state)
1028 val = I915_READ(reg);
1029 cur_state = !!(val & DPLL_VCO_ENABLE);
1030 I915_STATE_WARN(cur_state != state,
1031 "PLL state assertion failure (expected %s, current %s)\n",
1032 state_string(state), state_string(cur_state));
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1041 mutex_lock(&dev_priv->dpio_lock);
1042 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043 mutex_unlock(&dev_priv->dpio_lock);
1045 cur_state = val & DSI_PLL_VCO_EN;
1046 I915_STATE_WARN(cur_state != state,
1047 "DSI PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state), state_string(cur_state));
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1056 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1058 if (crtc->config->shared_dpll < 0)
1061 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066 struct intel_shared_dpll *pll,
1070 struct intel_dpll_hw_state hw_state;
1073 "asserting DPLL %s with no DPLL\n", state_string(state)))
1076 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077 I915_STATE_WARN(cur_state != state,
1078 "%s assertion failure (expected %s, current %s)\n",
1079 pll->name, state_string(state), state_string(cur_state));
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083 enum pipe pipe, bool state)
1088 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1091 if (HAS_DDI(dev_priv->dev)) {
1092 /* DDI does not have a specific FDI_TX register */
1093 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094 val = I915_READ(reg);
1095 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1097 reg = FDI_TX_CTL(pipe);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & FDI_TX_ENABLE);
1101 I915_STATE_WARN(cur_state != state,
1102 "FDI TX state assertion failure (expected %s, current %s)\n",
1103 state_string(state), state_string(cur_state));
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109 enum pipe pipe, bool state)
1115 reg = FDI_RX_CTL(pipe);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 state_string(state), state_string(cur_state));
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1131 /* ILK FDI PLL is always enabled */
1132 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1135 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136 if (HAS_DDI(dev_priv->dev))
1139 reg = FDI_TX_CTL(pipe);
1140 val = I915_READ(reg);
1141 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154 I915_STATE_WARN(cur_state != state,
1155 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1162 struct drm_device *dev = dev_priv->dev;
1165 enum pipe panel_pipe = PIPE_A;
1168 if (WARN_ON(HAS_DDI(dev)))
1171 if (HAS_PCH_SPLIT(dev)) {
1174 pp_reg = PCH_PP_CONTROL;
1175 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1177 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179 panel_pipe = PIPE_B;
1180 /* XXX: else fix for eDP */
1181 } else if (IS_VALLEYVIEW(dev)) {
1182 /* presumably write lock depends on pipe, not port select */
1183 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1186 pp_reg = PP_CONTROL;
1187 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188 panel_pipe = PIPE_B;
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1196 I915_STATE_WARN(panel_pipe == pipe && locked,
1197 "panel assertion failure, pipe %c regs locked\n",
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state)
1204 struct drm_device *dev = dev_priv->dev;
1207 if (IS_845G(dev) || IS_I865G(dev))
1208 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1210 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1212 I915_STATE_WARN(cur_state != state,
1213 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214 pipe_name(pipe), state_string(state), state_string(cur_state));
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228 /* if we need the pipe quirk it must be always on */
1229 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1233 if (!intel_display_power_is_enabled(dev_priv,
1234 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1237 reg = PIPECONF(cpu_transcoder);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & PIPECONF_ENABLE);
1242 I915_STATE_WARN(cur_state != state,
1243 "pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe), state_string(state), state_string(cur_state));
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248 enum plane plane, bool state)
1254 reg = DSPCNTR(plane);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "plane %c assertion failure (expected %s, current %s)\n",
1259 plane_name(plane), state_string(state), state_string(cur_state));
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1268 struct drm_device *dev = dev_priv->dev;
1273 /* Primary planes are fixed to pipes on gen4+ */
1274 if (INTEL_INFO(dev)->gen >= 4) {
1275 reg = DSPCNTR(pipe);
1276 val = I915_READ(reg);
1277 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278 "plane %c assertion failure, should be disabled but not\n",
1283 /* Need to check both planes against the pipe */
1284 for_each_pipe(dev_priv, i) {
1286 val = I915_READ(reg);
1287 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288 DISPPLANE_SEL_PIPE_SHIFT;
1289 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(i), pipe_name(pipe));
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1298 struct drm_device *dev = dev_priv->dev;
1302 if (INTEL_INFO(dev)->gen >= 9) {
1303 for_each_sprite(pipe, sprite) {
1304 val = I915_READ(PLANE_CTL(pipe, sprite));
1305 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307 sprite, pipe_name(pipe));
1309 } else if (IS_VALLEYVIEW(dev)) {
1310 for_each_sprite(pipe, sprite) {
1311 reg = SPCNTR(pipe, sprite);
1312 val = I915_READ(reg);
1313 I915_STATE_WARN(val & SP_ENABLE,
1314 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315 sprite_name(pipe, sprite), pipe_name(pipe));
1317 } else if (INTEL_INFO(dev)->gen >= 7) {
1319 val = I915_READ(reg);
1320 I915_STATE_WARN(val & SPRITE_ENABLE,
1321 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322 plane_name(pipe), pipe_name(pipe));
1323 } else if (INTEL_INFO(dev)->gen >= 5) {
1324 reg = DVSCNTR(pipe);
1325 val = I915_READ(reg);
1326 I915_STATE_WARN(val & DVS_ENABLE,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 plane_name(pipe), pipe_name(pipe));
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1334 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335 drm_crtc_vblank_put(crtc);
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1343 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1345 val = I915_READ(PCH_DREF_CONTROL);
1346 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347 DREF_SUPERSPREAD_SOURCE_MASK));
1348 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1358 reg = PCH_TRANSCONF(pipe);
1359 val = I915_READ(reg);
1360 enabled = !!(val & TRANS_ENABLE);
1361 I915_STATE_WARN(enabled,
1362 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367 enum pipe pipe, u32 port_sel, u32 val)
1369 if ((val & DP_PORT_EN) == 0)
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1377 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1390 if ((val & SDVO_ENABLE) == 0)
1393 if (HAS_PCH_CPT(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1396 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1409 if ((val & LVDS_PORT_EN) == 0)
1412 if (HAS_PCH_CPT(dev_priv->dev)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1427 if (HAS_PCH_CPT(dev_priv->dev)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, int reg, u32 port_sel)
1440 u32 val = I915_READ(reg);
1441 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443 reg, pipe_name(pipe));
1445 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446 && (val & DP_PIPEB_SELECT),
1447 "IBX PCH dp port still using transcoder B\n");
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, int reg)
1453 u32 val = I915_READ(reg);
1454 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456 reg, pipe_name(pipe));
1458 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459 && (val & SDVO_PIPE_B_SELECT),
1460 "IBX PCH hdmi port still using transcoder B\n");
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1474 val = I915_READ(reg);
1475 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476 "PCH VGA enabled on transcoder %c, should be disabled\n",
1480 val = I915_READ(reg);
1481 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1490 static void intel_init_dpio(struct drm_device *dev)
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1494 if (!IS_VALLEYVIEW(dev))
1498 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499 * CHV x1 PHY (DP/HDMI D)
1500 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1502 if (IS_CHERRYVIEW(dev)) {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511 const struct intel_crtc_state *pipe_config)
1513 struct drm_device *dev = crtc->base.dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 int reg = DPLL(crtc->pipe);
1516 u32 dpll = pipe_config->dpll_hw_state.dpll;
1518 assert_pipe_disabled(dev_priv, crtc->pipe);
1520 /* No really, not for ILK+ */
1521 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1523 /* PLL is protected by panel, make sure we can write it */
1524 if (IS_MOBILE(dev_priv->dev))
1525 assert_panel_unlocked(dev_priv, crtc->pipe);
1527 I915_WRITE(reg, dpll);
1531 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1534 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535 POSTING_READ(DPLL_MD(crtc->pipe));
1537 /* We do this three times for luck */
1538 I915_WRITE(reg, dpll);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1543 udelay(150); /* wait for warmup */
1544 I915_WRITE(reg, dpll);
1546 udelay(150); /* wait for warmup */
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550 const struct intel_crtc_state *pipe_config)
1552 struct drm_device *dev = crtc->base.dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 int pipe = crtc->pipe;
1555 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1558 assert_pipe_disabled(dev_priv, crtc->pipe);
1560 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1562 mutex_lock(&dev_priv->dpio_lock);
1564 /* Enable back the 10bit clock to display controller */
1565 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566 tmp |= DPIO_DCLKP_EN;
1567 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1570 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1575 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1577 /* Check PLL is locked */
1578 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579 DRM_ERROR("PLL %d failed to lock\n", pipe);
1581 /* not sure when this should be written */
1582 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583 POSTING_READ(DPLL_MD(pipe));
1585 mutex_unlock(&dev_priv->dpio_lock);
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1590 struct intel_crtc *crtc;
1593 for_each_intel_crtc(dev, crtc)
1594 count += crtc->active &&
1595 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1602 struct drm_device *dev = crtc->base.dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 int reg = DPLL(crtc->pipe);
1605 u32 dpll = crtc->config->dpll_hw_state.dpll;
1607 assert_pipe_disabled(dev_priv, crtc->pipe);
1609 /* No really, not for ILK+ */
1610 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1612 /* PLL is protected by panel, make sure we can write it */
1613 if (IS_MOBILE(dev) && !IS_I830(dev))
1614 assert_panel_unlocked(dev_priv, crtc->pipe);
1616 /* Enable DVO 2x clock on both PLLs if necessary */
1617 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1619 * It appears to be important that we don't enable this
1620 * for the current pipe before otherwise configuring the
1621 * PLL. No idea how this should be handled if multiple
1622 * DVO outputs are enabled simultaneosly.
1624 dpll |= DPLL_DVO_2X_MODE;
1625 I915_WRITE(DPLL(!crtc->pipe),
1626 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1629 /* Wait for the clocks to stabilize. */
1633 if (INTEL_INFO(dev)->gen >= 4) {
1634 I915_WRITE(DPLL_MD(crtc->pipe),
1635 crtc->config->dpll_hw_state.dpll_md);
1637 /* The pixel multiplier can only be updated once the
1638 * DPLL is enabled and the clocks are stable.
1640 * So write it again.
1642 I915_WRITE(reg, dpll);
1645 /* We do this three times for luck */
1646 I915_WRITE(reg, dpll);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1651 udelay(150); /* wait for warmup */
1652 I915_WRITE(reg, dpll);
1654 udelay(150); /* wait for warmup */
1658 * i9xx_disable_pll - disable a PLL
1659 * @dev_priv: i915 private structure
1660 * @pipe: pipe PLL to disable
1662 * Disable the PLL for @pipe, making sure the pipe is off first.
1664 * Note! This is for pre-ILK only.
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1668 struct drm_device *dev = crtc->base.dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 enum pipe pipe = crtc->pipe;
1672 /* Disable DVO 2x clock on both PLLs if necessary */
1674 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675 intel_num_dvo_pipes(dev) == 1) {
1676 I915_WRITE(DPLL(PIPE_B),
1677 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678 I915_WRITE(DPLL(PIPE_A),
1679 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1682 /* Don't disable pipe or pipe PLLs if needed */
1683 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1687 /* Make sure the pipe isn't still relying on us */
1688 assert_pipe_disabled(dev_priv, pipe);
1690 I915_WRITE(DPLL(pipe), 0);
1691 POSTING_READ(DPLL(pipe));
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1702 * Leave integrated clock source and reference clock enabled for pipe B.
1703 * The latter is needed for VGA hotplug / manual detection.
1706 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1714 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv, pipe);
1720 /* Set PLL en = 0 */
1721 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1723 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1727 mutex_lock(&dev_priv->dpio_lock);
1729 /* Disable 10bit clock to display controller */
1730 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731 val &= ~DPIO_DCLKP_EN;
1732 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1734 /* disable left/right clock distribution */
1735 if (pipe != PIPE_B) {
1736 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1745 mutex_unlock(&dev_priv->dpio_lock);
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749 struct intel_digital_port *dport)
1754 switch (dport->port) {
1756 port_mask = DPLL_PORTB_READY_MASK;
1760 port_mask = DPLL_PORTC_READY_MASK;
1764 port_mask = DPLL_PORTD_READY_MASK;
1765 dpll_reg = DPIO_PHY_STATUS;
1771 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773 port_name(dport->port), I915_READ(dpll_reg));
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1782 if (WARN_ON(pll == NULL))
1785 WARN_ON(!pll->config.crtc_mask);
1786 if (pll->active == 0) {
1787 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1789 assert_shared_dpll_disabled(dev_priv, pll);
1791 pll->mode_set(dev_priv, pll);
1796 * intel_enable_shared_dpll - enable PCH PLL
1797 * @dev_priv: i915 private structure
1798 * @pipe: pipe PLL to enable
1800 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801 * drives the transcoder clock.
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1809 if (WARN_ON(pll == NULL))
1812 if (WARN_ON(pll->config.crtc_mask == 0))
1815 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816 pll->name, pll->active, pll->on,
1817 crtc->base.base.id);
1819 if (pll->active++) {
1821 assert_shared_dpll_enabled(dev_priv, pll);
1826 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1828 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829 pll->enable(dev_priv, pll);
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1835 struct drm_device *dev = crtc->base.dev;
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1837 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev)->gen < 5);
1841 if (WARN_ON(pll == NULL))
1844 if (WARN_ON(pll->config.crtc_mask == 0))
1847 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848 pll->name, pll->active, pll->on,
1849 crtc->base.base.id);
1851 if (WARN_ON(pll->active == 0)) {
1852 assert_shared_dpll_disabled(dev_priv, pll);
1856 assert_shared_dpll_enabled(dev_priv, pll);
1861 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862 pll->disable(dev_priv, pll);
1865 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1871 struct drm_device *dev = dev_priv->dev;
1872 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874 uint32_t reg, val, pipeconf_val;
1876 /* PCH only available on ILK+ */
1877 BUG_ON(!HAS_PCH_SPLIT(dev));
1879 /* Make sure PCH DPLL is enabled */
1880 assert_shared_dpll_enabled(dev_priv,
1881 intel_crtc_to_shared_dpll(intel_crtc));
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, pipe);
1885 assert_fdi_rx_enabled(dev_priv, pipe);
1887 if (HAS_PCH_CPT(dev)) {
1888 /* Workaround: Set the timing override bit before enabling the
1889 * pch transcoder. */
1890 reg = TRANS_CHICKEN2(pipe);
1891 val = I915_READ(reg);
1892 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893 I915_WRITE(reg, val);
1896 reg = PCH_TRANSCONF(pipe);
1897 val = I915_READ(reg);
1898 pipeconf_val = I915_READ(PIPECONF(pipe));
1900 if (HAS_PCH_IBX(dev_priv->dev)) {
1902 * make the BPC in transcoder be consistent with
1903 * that in pipeconf reg.
1905 val &= ~PIPECONF_BPC_MASK;
1906 val |= pipeconf_val & PIPECONF_BPC_MASK;
1909 val &= ~TRANS_INTERLACE_MASK;
1910 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911 if (HAS_PCH_IBX(dev_priv->dev) &&
1912 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913 val |= TRANS_LEGACY_INTERLACED_ILK;
1915 val |= TRANS_INTERLACED;
1917 val |= TRANS_PROGRESSIVE;
1919 I915_WRITE(reg, val | TRANS_ENABLE);
1920 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925 enum transcoder cpu_transcoder)
1927 u32 val, pipeconf_val;
1929 /* PCH only available on ILK+ */
1930 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1932 /* FDI must be feeding us bits for PCH ports */
1933 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1936 /* Workaround: set timing override bit. */
1937 val = I915_READ(_TRANSA_CHICKEN2);
1938 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939 I915_WRITE(_TRANSA_CHICKEN2, val);
1942 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1944 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945 PIPECONF_INTERLACED_ILK)
1946 val |= TRANS_INTERLACED;
1948 val |= TRANS_PROGRESSIVE;
1950 I915_WRITE(LPT_TRANSCONF, val);
1951 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952 DRM_ERROR("Failed to enable PCH transcoder\n");
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1958 struct drm_device *dev = dev_priv->dev;
1961 /* FDI relies on the transcoder */
1962 assert_fdi_tx_disabled(dev_priv, pipe);
1963 assert_fdi_rx_disabled(dev_priv, pipe);
1965 /* Ports must be off as well */
1966 assert_pch_ports_disabled(dev_priv, pipe);
1968 reg = PCH_TRANSCONF(pipe);
1969 val = I915_READ(reg);
1970 val &= ~TRANS_ENABLE;
1971 I915_WRITE(reg, val);
1972 /* wait for PCH transcoder off, transcoder state */
1973 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1976 if (!HAS_PCH_IBX(dev)) {
1977 /* Workaround: Clear the timing override chicken bit again. */
1978 reg = TRANS_CHICKEN2(pipe);
1979 val = I915_READ(reg);
1980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981 I915_WRITE(reg, val);
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1989 val = I915_READ(LPT_TRANSCONF);
1990 val &= ~TRANS_ENABLE;
1991 I915_WRITE(LPT_TRANSCONF, val);
1992 /* wait for PCH transcoder off, transcoder state */
1993 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994 DRM_ERROR("Failed to disable PCH transcoder\n");
1996 /* Workaround: clear timing override bit. */
1997 val = I915_READ(_TRANSA_CHICKEN2);
1998 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999 I915_WRITE(_TRANSA_CHICKEN2, val);
2003 * intel_enable_pipe - enable a pipe, asserting requirements
2004 * @crtc: crtc responsible for the pipe
2006 * Enable @crtc's pipe, making sure that various hardware specific requirements
2007 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2011 struct drm_device *dev = crtc->base.dev;
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2013 enum pipe pipe = crtc->pipe;
2014 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2016 enum pipe pch_transcoder;
2020 assert_planes_disabled(dev_priv, pipe);
2021 assert_cursor_disabled(dev_priv, pipe);
2022 assert_sprites_disabled(dev_priv, pipe);
2024 if (HAS_PCH_LPT(dev_priv->dev))
2025 pch_transcoder = TRANSCODER_A;
2027 pch_transcoder = pipe;
2030 * A pipe without a PLL won't actually be able to drive bits from
2031 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2034 if (!HAS_PCH_SPLIT(dev_priv->dev))
2035 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036 assert_dsi_pll_enabled(dev_priv);
2038 assert_pll_enabled(dev_priv, pipe);
2040 if (crtc->config->has_pch_encoder) {
2041 /* if driving the PCH, we need FDI enabled */
2042 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043 assert_fdi_tx_pll_enabled(dev_priv,
2044 (enum pipe) cpu_transcoder);
2046 /* FIXME: assert CPU port conditions for SNB+ */
2049 reg = PIPECONF(cpu_transcoder);
2050 val = I915_READ(reg);
2051 if (val & PIPECONF_ENABLE) {
2052 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2057 I915_WRITE(reg, val | PIPECONF_ENABLE);
2062 * intel_disable_pipe - disable a pipe, asserting requirements
2063 * @crtc: crtc whose pipes is to be disabled
2065 * Disable the pipe of @crtc, making sure that various hardware
2066 * specific requirements are met, if applicable, e.g. plane
2067 * disabled, panel fitter off, etc.
2069 * Will wait until the pipe has shut down before returning.
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2073 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075 enum pipe pipe = crtc->pipe;
2080 * Make sure planes won't keep trying to pump pixels to us,
2081 * or we might hang the display.
2083 assert_planes_disabled(dev_priv, pipe);
2084 assert_cursor_disabled(dev_priv, pipe);
2085 assert_sprites_disabled(dev_priv, pipe);
2087 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0)
2093 * Double wide has implications for planes
2094 * so best keep it disabled when not needed.
2096 if (crtc->config->double_wide)
2097 val &= ~PIPECONF_DOUBLE_WIDE;
2099 /* Don't disable pipe or pipe PLLs if needed */
2100 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102 val &= ~PIPECONF_ENABLE;
2104 I915_WRITE(reg, val);
2105 if ((val & PIPECONF_ENABLE) == 0)
2106 intel_wait_for_pipe_off(crtc);
2110 * Plane regs are double buffered, going from enabled->disabled needs a
2111 * trigger in order to latch. The display address reg provides this.
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2116 struct drm_device *dev = dev_priv->dev;
2117 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2119 I915_WRITE(reg, I915_READ(reg));
2124 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125 * @plane: plane to be enabled
2126 * @crtc: crtc for the plane
2128 * Enable @plane on @crtc, making sure that the pipe is running first.
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131 struct drm_crtc *crtc)
2133 struct drm_device *dev = plane->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2137 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2140 if (intel_crtc->primary_enabled)
2143 intel_crtc->primary_enabled = true;
2145 dev_priv->display.update_primary_plane(crtc, plane->fb,
2149 * BDW signals flip done immediately if the plane
2150 * is disabled, even if the plane enable is already
2151 * armed to occur at the next vblank :(
2153 if (IS_BROADWELL(dev))
2154 intel_wait_for_vblank(dev, intel_crtc->pipe);
2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
2159 * @plane: plane to be disabled
2160 * @crtc: crtc for the plane
2162 * Disable @plane on @crtc, making sure that the pipe is running first.
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165 struct drm_crtc *crtc)
2167 struct drm_device *dev = plane->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2171 if (WARN_ON(!intel_crtc->active))
2174 if (!intel_crtc->primary_enabled)
2177 intel_crtc->primary_enabled = false;
2179 dev_priv->display.update_primary_plane(crtc, plane->fb,
2183 static bool need_vtd_wa(struct drm_device *dev)
2185 #ifdef CONFIG_INTEL_IOMMU
2186 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2193 intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
2197 tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
2198 return ALIGN(height, tile_height);
2202 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2203 struct drm_framebuffer *fb,
2204 struct intel_engine_cs *pipelined)
2206 struct drm_device *dev = fb->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2212 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2214 switch (obj->tiling_mode) {
2215 case I915_TILING_NONE:
2216 if (INTEL_INFO(dev)->gen >= 9)
2217 alignment = 256 * 1024;
2218 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2219 alignment = 128 * 1024;
2220 else if (INTEL_INFO(dev)->gen >= 4)
2221 alignment = 4 * 1024;
2223 alignment = 64 * 1024;
2226 if (INTEL_INFO(dev)->gen >= 9)
2227 alignment = 256 * 1024;
2229 /* pin() will align the object as required by fence */
2234 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2240 /* Note that the w/a also requires 64 PTE of padding following the
2241 * bo. We currently fill all unused PTE with the shadow page and so
2242 * we should always have valid PTE following the scanout preventing
2245 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2246 alignment = 256 * 1024;
2249 * Global gtt pte registers are special registers which actually forward
2250 * writes to a chunk of system memory. Which means that there is no risk
2251 * that the register values disappear as soon as we call
2252 * intel_runtime_pm_put(), so it is correct to wrap only the
2253 * pin/unpin/fence and not more.
2255 intel_runtime_pm_get(dev_priv);
2257 dev_priv->mm.interruptible = false;
2258 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2260 goto err_interruptible;
2262 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2263 * fence, whereas 965+ only requires a fence if using
2264 * framebuffer compression. For simplicity, we always install
2265 * a fence as the cost is not that onerous.
2267 ret = i915_gem_object_get_fence(obj);
2271 i915_gem_object_pin_fence(obj);
2273 dev_priv->mm.interruptible = true;
2274 intel_runtime_pm_put(dev_priv);
2278 i915_gem_object_unpin_from_display_plane(obj);
2280 dev_priv->mm.interruptible = true;
2281 intel_runtime_pm_put(dev_priv);
2285 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2287 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2289 i915_gem_object_unpin_fence(obj);
2290 i915_gem_object_unpin_from_display_plane(obj);
2293 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2294 * is assumed to be a power-of-two. */
2295 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2296 unsigned int tiling_mode,
2300 if (tiling_mode != I915_TILING_NONE) {
2301 unsigned int tile_rows, tiles;
2306 tiles = *x / (512/cpp);
2309 return tile_rows * pitch * 8 + tiles * 4096;
2311 unsigned int offset;
2313 offset = *y * pitch + *x * cpp;
2315 *x = (offset & 4095) / cpp;
2316 return offset & -4096;
2320 static int i9xx_format_to_fourcc(int format)
2323 case DISPPLANE_8BPP:
2324 return DRM_FORMAT_C8;
2325 case DISPPLANE_BGRX555:
2326 return DRM_FORMAT_XRGB1555;
2327 case DISPPLANE_BGRX565:
2328 return DRM_FORMAT_RGB565;
2330 case DISPPLANE_BGRX888:
2331 return DRM_FORMAT_XRGB8888;
2332 case DISPPLANE_RGBX888:
2333 return DRM_FORMAT_XBGR8888;
2334 case DISPPLANE_BGRX101010:
2335 return DRM_FORMAT_XRGB2101010;
2336 case DISPPLANE_RGBX101010:
2337 return DRM_FORMAT_XBGR2101010;
2341 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2344 case PLANE_CTL_FORMAT_RGB_565:
2345 return DRM_FORMAT_RGB565;
2347 case PLANE_CTL_FORMAT_XRGB_8888:
2350 return DRM_FORMAT_ABGR8888;
2352 return DRM_FORMAT_XBGR8888;
2355 return DRM_FORMAT_ARGB8888;
2357 return DRM_FORMAT_XRGB8888;
2359 case PLANE_CTL_FORMAT_XRGB_2101010:
2361 return DRM_FORMAT_XBGR2101010;
2363 return DRM_FORMAT_XRGB2101010;
2368 intel_alloc_plane_obj(struct intel_crtc *crtc,
2369 struct intel_initial_plane_config *plane_config)
2371 struct drm_device *dev = crtc->base.dev;
2372 struct drm_i915_gem_object *obj = NULL;
2373 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2374 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2375 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2378 size_aligned -= base_aligned;
2380 if (plane_config->size == 0)
2383 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2390 obj->tiling_mode = plane_config->tiling;
2391 if (obj->tiling_mode == I915_TILING_X)
2392 obj->stride = crtc->base.primary->fb->pitches[0];
2394 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2395 mode_cmd.width = crtc->base.primary->fb->width;
2396 mode_cmd.height = crtc->base.primary->fb->height;
2397 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2399 mutex_lock(&dev->struct_mutex);
2401 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2403 DRM_DEBUG_KMS("intel fb init failed\n");
2407 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2408 mutex_unlock(&dev->struct_mutex);
2410 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2414 drm_gem_object_unreference(&obj->base);
2415 mutex_unlock(&dev->struct_mutex);
2420 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2421 struct intel_initial_plane_config *plane_config)
2423 struct drm_device *dev = intel_crtc->base.dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2426 struct intel_crtc *i;
2427 struct drm_i915_gem_object *obj;
2429 if (!intel_crtc->base.primary->fb)
2432 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2435 kfree(intel_crtc->base.primary->fb);
2436 intel_crtc->base.primary->fb = NULL;
2439 * Failed to alloc the obj, check to see if we should share
2440 * an fb with another CRTC instead
2442 for_each_crtc(dev, c) {
2443 i = to_intel_crtc(c);
2445 if (c == &intel_crtc->base)
2451 obj = intel_fb_obj(c->primary->fb);
2455 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2456 if (obj->tiling_mode != I915_TILING_NONE)
2457 dev_priv->preserve_bios_swizzle = true;
2459 drm_framebuffer_reference(c->primary->fb);
2460 intel_crtc->base.primary->fb = c->primary->fb;
2461 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2467 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2468 struct drm_framebuffer *fb,
2471 struct drm_device *dev = crtc->dev;
2472 struct drm_i915_private *dev_priv = dev->dev_private;
2473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2474 struct drm_i915_gem_object *obj;
2475 int plane = intel_crtc->plane;
2476 unsigned long linear_offset;
2478 u32 reg = DSPCNTR(plane);
2481 if (!intel_crtc->primary_enabled) {
2483 if (INTEL_INFO(dev)->gen >= 4)
2484 I915_WRITE(DSPSURF(plane), 0);
2486 I915_WRITE(DSPADDR(plane), 0);
2491 obj = intel_fb_obj(fb);
2492 if (WARN_ON(obj == NULL))
2495 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2497 dspcntr = DISPPLANE_GAMMA_ENABLE;
2499 dspcntr |= DISPLAY_PLANE_ENABLE;
2501 if (INTEL_INFO(dev)->gen < 4) {
2502 if (intel_crtc->pipe == PIPE_B)
2503 dspcntr |= DISPPLANE_SEL_PIPE_B;
2505 /* pipesrc and dspsize control the size that is scaled from,
2506 * which should always be the user's requested size.
2508 I915_WRITE(DSPSIZE(plane),
2509 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2510 (intel_crtc->config->pipe_src_w - 1));
2511 I915_WRITE(DSPPOS(plane), 0);
2512 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2513 I915_WRITE(PRIMSIZE(plane),
2514 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2515 (intel_crtc->config->pipe_src_w - 1));
2516 I915_WRITE(PRIMPOS(plane), 0);
2517 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2520 switch (fb->pixel_format) {
2522 dspcntr |= DISPPLANE_8BPP;
2524 case DRM_FORMAT_XRGB1555:
2525 case DRM_FORMAT_ARGB1555:
2526 dspcntr |= DISPPLANE_BGRX555;
2528 case DRM_FORMAT_RGB565:
2529 dspcntr |= DISPPLANE_BGRX565;
2531 case DRM_FORMAT_XRGB8888:
2532 case DRM_FORMAT_ARGB8888:
2533 dspcntr |= DISPPLANE_BGRX888;
2535 case DRM_FORMAT_XBGR8888:
2536 case DRM_FORMAT_ABGR8888:
2537 dspcntr |= DISPPLANE_RGBX888;
2539 case DRM_FORMAT_XRGB2101010:
2540 case DRM_FORMAT_ARGB2101010:
2541 dspcntr |= DISPPLANE_BGRX101010;
2543 case DRM_FORMAT_XBGR2101010:
2544 case DRM_FORMAT_ABGR2101010:
2545 dspcntr |= DISPPLANE_RGBX101010;
2551 if (INTEL_INFO(dev)->gen >= 4 &&
2552 obj->tiling_mode != I915_TILING_NONE)
2553 dspcntr |= DISPPLANE_TILED;
2556 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2558 linear_offset = y * fb->pitches[0] + x * pixel_size;
2560 if (INTEL_INFO(dev)->gen >= 4) {
2561 intel_crtc->dspaddr_offset =
2562 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2565 linear_offset -= intel_crtc->dspaddr_offset;
2567 intel_crtc->dspaddr_offset = linear_offset;
2570 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2571 dspcntr |= DISPPLANE_ROTATE_180;
2573 x += (intel_crtc->config->pipe_src_w - 1);
2574 y += (intel_crtc->config->pipe_src_h - 1);
2576 /* Finding the last pixel of the last line of the display
2577 data and adding to linear_offset*/
2579 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2580 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2583 I915_WRITE(reg, dspcntr);
2585 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2586 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2588 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2589 if (INTEL_INFO(dev)->gen >= 4) {
2590 I915_WRITE(DSPSURF(plane),
2591 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2592 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2593 I915_WRITE(DSPLINOFF(plane), linear_offset);
2595 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2599 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2600 struct drm_framebuffer *fb,
2603 struct drm_device *dev = crtc->dev;
2604 struct drm_i915_private *dev_priv = dev->dev_private;
2605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2606 struct drm_i915_gem_object *obj;
2607 int plane = intel_crtc->plane;
2608 unsigned long linear_offset;
2610 u32 reg = DSPCNTR(plane);
2613 if (!intel_crtc->primary_enabled) {
2615 I915_WRITE(DSPSURF(plane), 0);
2620 obj = intel_fb_obj(fb);
2621 if (WARN_ON(obj == NULL))
2624 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2626 dspcntr = DISPPLANE_GAMMA_ENABLE;
2628 dspcntr |= DISPLAY_PLANE_ENABLE;
2630 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2631 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2633 switch (fb->pixel_format) {
2635 dspcntr |= DISPPLANE_8BPP;
2637 case DRM_FORMAT_RGB565:
2638 dspcntr |= DISPPLANE_BGRX565;
2640 case DRM_FORMAT_XRGB8888:
2641 case DRM_FORMAT_ARGB8888:
2642 dspcntr |= DISPPLANE_BGRX888;
2644 case DRM_FORMAT_XBGR8888:
2645 case DRM_FORMAT_ABGR8888:
2646 dspcntr |= DISPPLANE_RGBX888;
2648 case DRM_FORMAT_XRGB2101010:
2649 case DRM_FORMAT_ARGB2101010:
2650 dspcntr |= DISPPLANE_BGRX101010;
2652 case DRM_FORMAT_XBGR2101010:
2653 case DRM_FORMAT_ABGR2101010:
2654 dspcntr |= DISPPLANE_RGBX101010;
2660 if (obj->tiling_mode != I915_TILING_NONE)
2661 dspcntr |= DISPPLANE_TILED;
2663 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2664 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2666 linear_offset = y * fb->pitches[0] + x * pixel_size;
2667 intel_crtc->dspaddr_offset =
2668 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2671 linear_offset -= intel_crtc->dspaddr_offset;
2672 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2673 dspcntr |= DISPPLANE_ROTATE_180;
2675 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2676 x += (intel_crtc->config->pipe_src_w - 1);
2677 y += (intel_crtc->config->pipe_src_h - 1);
2679 /* Finding the last pixel of the last line of the display
2680 data and adding to linear_offset*/
2682 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2683 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2687 I915_WRITE(reg, dspcntr);
2689 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2690 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2692 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2693 I915_WRITE(DSPSURF(plane),
2694 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2695 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2696 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2698 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2699 I915_WRITE(DSPLINOFF(plane), linear_offset);
2704 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2705 struct drm_framebuffer *fb,
2708 struct drm_device *dev = crtc->dev;
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2711 struct intel_framebuffer *intel_fb;
2712 struct drm_i915_gem_object *obj;
2713 int pipe = intel_crtc->pipe;
2714 u32 plane_ctl, stride;
2716 if (!intel_crtc->primary_enabled) {
2717 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2718 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2719 POSTING_READ(PLANE_CTL(pipe, 0));
2723 plane_ctl = PLANE_CTL_ENABLE |
2724 PLANE_CTL_PIPE_GAMMA_ENABLE |
2725 PLANE_CTL_PIPE_CSC_ENABLE;
2727 switch (fb->pixel_format) {
2728 case DRM_FORMAT_RGB565:
2729 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2731 case DRM_FORMAT_XRGB8888:
2732 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2734 case DRM_FORMAT_ARGB8888:
2735 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2736 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2738 case DRM_FORMAT_XBGR8888:
2739 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2740 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2742 case DRM_FORMAT_ABGR8888:
2743 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2744 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2745 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2747 case DRM_FORMAT_XRGB2101010:
2748 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2750 case DRM_FORMAT_XBGR2101010:
2751 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2752 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2758 intel_fb = to_intel_framebuffer(fb);
2759 obj = intel_fb->obj;
2762 * The stride is either expressed as a multiple of 64 bytes chunks for
2763 * linear buffers or in number of tiles for tiled buffers.
2765 switch (obj->tiling_mode) {
2766 case I915_TILING_NONE:
2767 stride = fb->pitches[0] >> 6;
2770 plane_ctl |= PLANE_CTL_TILED_X;
2771 stride = fb->pitches[0] >> 9;
2777 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2778 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2779 plane_ctl |= PLANE_CTL_ROTATE_180;
2781 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2783 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2784 i915_gem_obj_ggtt_offset(obj),
2785 x, y, fb->width, fb->height,
2788 I915_WRITE(PLANE_POS(pipe, 0), 0);
2789 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2790 I915_WRITE(PLANE_SIZE(pipe, 0),
2791 (intel_crtc->config->pipe_src_h - 1) << 16 |
2792 (intel_crtc->config->pipe_src_w - 1));
2793 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2794 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2796 POSTING_READ(PLANE_SURF(pipe, 0));
2799 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2801 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2802 int x, int y, enum mode_set_atomic state)
2804 struct drm_device *dev = crtc->dev;
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2807 if (dev_priv->display.disable_fbc)
2808 dev_priv->display.disable_fbc(dev);
2810 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2815 static void intel_complete_page_flips(struct drm_device *dev)
2817 struct drm_crtc *crtc;
2819 for_each_crtc(dev, crtc) {
2820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2821 enum plane plane = intel_crtc->plane;
2823 intel_prepare_page_flip(dev, plane);
2824 intel_finish_page_flip_plane(dev, plane);
2828 static void intel_update_primary_planes(struct drm_device *dev)
2830 struct drm_i915_private *dev_priv = dev->dev_private;
2831 struct drm_crtc *crtc;
2833 for_each_crtc(dev, crtc) {
2834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2836 drm_modeset_lock(&crtc->mutex, NULL);
2838 * FIXME: Once we have proper support for primary planes (and
2839 * disabling them without disabling the entire crtc) allow again
2840 * a NULL crtc->primary->fb.
2842 if (intel_crtc->active && crtc->primary->fb)
2843 dev_priv->display.update_primary_plane(crtc,
2847 drm_modeset_unlock(&crtc->mutex);
2851 void intel_prepare_reset(struct drm_device *dev)
2853 struct drm_i915_private *dev_priv = to_i915(dev);
2854 struct intel_crtc *crtc;
2856 /* no reset support for gen2 */
2860 /* reset doesn't touch the display */
2861 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2864 drm_modeset_lock_all(dev);
2867 * Disabling the crtcs gracefully seems nicer. Also the
2868 * g33 docs say we should at least disable all the planes.
2870 for_each_intel_crtc(dev, crtc) {
2872 dev_priv->display.crtc_disable(&crtc->base);
2876 void intel_finish_reset(struct drm_device *dev)
2878 struct drm_i915_private *dev_priv = to_i915(dev);
2881 * Flips in the rings will be nuked by the reset,
2882 * so complete all pending flips so that user space
2883 * will get its events and not get stuck.
2885 intel_complete_page_flips(dev);
2887 /* no reset support for gen2 */
2891 /* reset doesn't touch the display */
2892 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2894 * Flips in the rings have been nuked by the reset,
2895 * so update the base address of all primary
2896 * planes to the the last fb to make sure we're
2897 * showing the correct fb after a reset.
2899 intel_update_primary_planes(dev);
2904 * The display has been reset as well,
2905 * so need a full re-initialization.
2907 intel_runtime_pm_disable_interrupts(dev_priv);
2908 intel_runtime_pm_enable_interrupts(dev_priv);
2910 intel_modeset_init_hw(dev);
2912 spin_lock_irq(&dev_priv->irq_lock);
2913 if (dev_priv->display.hpd_irq_setup)
2914 dev_priv->display.hpd_irq_setup(dev);
2915 spin_unlock_irq(&dev_priv->irq_lock);
2917 intel_modeset_setup_hw_state(dev, true);
2919 intel_hpd_init(dev_priv);
2921 drm_modeset_unlock_all(dev);
2925 intel_finish_fb(struct drm_framebuffer *old_fb)
2927 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2928 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2929 bool was_interruptible = dev_priv->mm.interruptible;
2932 /* Big Hammer, we also need to ensure that any pending
2933 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2934 * current scanout is retired before unpinning the old
2937 * This should only fail upon a hung GPU, in which case we
2938 * can safely continue.
2940 dev_priv->mm.interruptible = false;
2941 ret = i915_gem_object_finish_gpu(obj);
2942 dev_priv->mm.interruptible = was_interruptible;
2947 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2949 struct drm_device *dev = crtc->dev;
2950 struct drm_i915_private *dev_priv = dev->dev_private;
2951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2954 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2955 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2958 spin_lock_irq(&dev->event_lock);
2959 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2960 spin_unlock_irq(&dev->event_lock);
2965 static void intel_update_pipe_size(struct intel_crtc *crtc)
2967 struct drm_device *dev = crtc->base.dev;
2968 struct drm_i915_private *dev_priv = dev->dev_private;
2969 const struct drm_display_mode *adjusted_mode;
2975 * Update pipe size and adjust fitter if needed: the reason for this is
2976 * that in compute_mode_changes we check the native mode (not the pfit
2977 * mode) to see if we can flip rather than do a full mode set. In the
2978 * fastboot case, we'll flip, but if we don't update the pipesrc and
2979 * pfit state, we'll end up with a big fb scanned out into the wrong
2982 * To fix this properly, we need to hoist the checks up into
2983 * compute_mode_changes (or above), check the actual pfit state and
2984 * whether the platform allows pfit disable with pipe active, and only
2985 * then update the pipesrc and pfit state, even on the flip path.
2988 adjusted_mode = &crtc->config->base.adjusted_mode;
2990 I915_WRITE(PIPESRC(crtc->pipe),
2991 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2992 (adjusted_mode->crtc_vdisplay - 1));
2993 if (!crtc->config->pch_pfit.enabled &&
2994 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2995 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2996 I915_WRITE(PF_CTL(crtc->pipe), 0);
2997 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2998 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3000 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3001 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3004 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3006 struct drm_device *dev = crtc->dev;
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3009 int pipe = intel_crtc->pipe;
3012 /* enable normal train */
3013 reg = FDI_TX_CTL(pipe);
3014 temp = I915_READ(reg);
3015 if (IS_IVYBRIDGE(dev)) {
3016 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3017 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3019 temp &= ~FDI_LINK_TRAIN_NONE;
3020 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3022 I915_WRITE(reg, temp);
3024 reg = FDI_RX_CTL(pipe);
3025 temp = I915_READ(reg);
3026 if (HAS_PCH_CPT(dev)) {
3027 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3028 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3030 temp &= ~FDI_LINK_TRAIN_NONE;
3031 temp |= FDI_LINK_TRAIN_NONE;
3033 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3035 /* wait one idle pattern time */
3039 /* IVB wants error correction enabled */
3040 if (IS_IVYBRIDGE(dev))
3041 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3042 FDI_FE_ERRC_ENABLE);
3045 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3047 return crtc->base.enabled && crtc->active &&
3048 crtc->config->has_pch_encoder;
3051 static void ivb_modeset_global_resources(struct drm_device *dev)
3053 struct drm_i915_private *dev_priv = dev->dev_private;
3054 struct intel_crtc *pipe_B_crtc =
3055 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3056 struct intel_crtc *pipe_C_crtc =
3057 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3061 * When everything is off disable fdi C so that we could enable fdi B
3062 * with all lanes. Note that we don't care about enabled pipes without
3063 * an enabled pch encoder.
3065 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3066 !pipe_has_enabled_pch(pipe_C_crtc)) {
3067 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3068 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3070 temp = I915_READ(SOUTH_CHICKEN1);
3071 temp &= ~FDI_BC_BIFURCATION_SELECT;
3072 DRM_DEBUG_KMS("disabling fdi C rx\n");
3073 I915_WRITE(SOUTH_CHICKEN1, temp);
3077 /* The FDI link training functions for ILK/Ibexpeak. */
3078 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3080 struct drm_device *dev = crtc->dev;
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3083 int pipe = intel_crtc->pipe;
3084 u32 reg, temp, tries;
3086 /* FDI needs bits from pipe first */
3087 assert_pipe_enabled(dev_priv, pipe);
3089 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3091 reg = FDI_RX_IMR(pipe);
3092 temp = I915_READ(reg);
3093 temp &= ~FDI_RX_SYMBOL_LOCK;
3094 temp &= ~FDI_RX_BIT_LOCK;
3095 I915_WRITE(reg, temp);
3099 /* enable CPU FDI TX and PCH FDI RX */
3100 reg = FDI_TX_CTL(pipe);
3101 temp = I915_READ(reg);
3102 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3103 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3104 temp &= ~FDI_LINK_TRAIN_NONE;
3105 temp |= FDI_LINK_TRAIN_PATTERN_1;
3106 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3108 reg = FDI_RX_CTL(pipe);
3109 temp = I915_READ(reg);
3110 temp &= ~FDI_LINK_TRAIN_NONE;
3111 temp |= FDI_LINK_TRAIN_PATTERN_1;
3112 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3117 /* Ironlake workaround, enable clock pointer after FDI enable*/
3118 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3119 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3120 FDI_RX_PHASE_SYNC_POINTER_EN);
3122 reg = FDI_RX_IIR(pipe);
3123 for (tries = 0; tries < 5; tries++) {
3124 temp = I915_READ(reg);
3125 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3127 if ((temp & FDI_RX_BIT_LOCK)) {
3128 DRM_DEBUG_KMS("FDI train 1 done.\n");
3129 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3134 DRM_ERROR("FDI train 1 fail!\n");
3137 reg = FDI_TX_CTL(pipe);
3138 temp = I915_READ(reg);
3139 temp &= ~FDI_LINK_TRAIN_NONE;
3140 temp |= FDI_LINK_TRAIN_PATTERN_2;
3141 I915_WRITE(reg, temp);
3143 reg = FDI_RX_CTL(pipe);
3144 temp = I915_READ(reg);
3145 temp &= ~FDI_LINK_TRAIN_NONE;
3146 temp |= FDI_LINK_TRAIN_PATTERN_2;
3147 I915_WRITE(reg, temp);
3152 reg = FDI_RX_IIR(pipe);
3153 for (tries = 0; tries < 5; tries++) {
3154 temp = I915_READ(reg);
3155 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3157 if (temp & FDI_RX_SYMBOL_LOCK) {
3158 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3159 DRM_DEBUG_KMS("FDI train 2 done.\n");
3164 DRM_ERROR("FDI train 2 fail!\n");
3166 DRM_DEBUG_KMS("FDI train done\n");
3170 static const int snb_b_fdi_train_param[] = {
3171 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3172 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3173 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3174 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3177 /* The FDI link training functions for SNB/Cougarpoint. */
3178 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3180 struct drm_device *dev = crtc->dev;
3181 struct drm_i915_private *dev_priv = dev->dev_private;
3182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3183 int pipe = intel_crtc->pipe;
3184 u32 reg, temp, i, retry;
3186 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3188 reg = FDI_RX_IMR(pipe);
3189 temp = I915_READ(reg);
3190 temp &= ~FDI_RX_SYMBOL_LOCK;
3191 temp &= ~FDI_RX_BIT_LOCK;
3192 I915_WRITE(reg, temp);
3197 /* enable CPU FDI TX and PCH FDI RX */
3198 reg = FDI_TX_CTL(pipe);
3199 temp = I915_READ(reg);
3200 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3201 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3202 temp &= ~FDI_LINK_TRAIN_NONE;
3203 temp |= FDI_LINK_TRAIN_PATTERN_1;
3204 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3206 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3207 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3209 I915_WRITE(FDI_RX_MISC(pipe),
3210 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3212 reg = FDI_RX_CTL(pipe);
3213 temp = I915_READ(reg);
3214 if (HAS_PCH_CPT(dev)) {
3215 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3216 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3218 temp &= ~FDI_LINK_TRAIN_NONE;
3219 temp |= FDI_LINK_TRAIN_PATTERN_1;
3221 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3226 for (i = 0; i < 4; i++) {
3227 reg = FDI_TX_CTL(pipe);
3228 temp = I915_READ(reg);
3229 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3230 temp |= snb_b_fdi_train_param[i];
3231 I915_WRITE(reg, temp);
3236 for (retry = 0; retry < 5; retry++) {
3237 reg = FDI_RX_IIR(pipe);
3238 temp = I915_READ(reg);
3239 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3240 if (temp & FDI_RX_BIT_LOCK) {
3241 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3242 DRM_DEBUG_KMS("FDI train 1 done.\n");
3251 DRM_ERROR("FDI train 1 fail!\n");
3254 reg = FDI_TX_CTL(pipe);
3255 temp = I915_READ(reg);
3256 temp &= ~FDI_LINK_TRAIN_NONE;
3257 temp |= FDI_LINK_TRAIN_PATTERN_2;
3259 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3261 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3263 I915_WRITE(reg, temp);
3265 reg = FDI_RX_CTL(pipe);
3266 temp = I915_READ(reg);
3267 if (HAS_PCH_CPT(dev)) {
3268 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3269 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3271 temp &= ~FDI_LINK_TRAIN_NONE;
3272 temp |= FDI_LINK_TRAIN_PATTERN_2;
3274 I915_WRITE(reg, temp);
3279 for (i = 0; i < 4; i++) {
3280 reg = FDI_TX_CTL(pipe);
3281 temp = I915_READ(reg);
3282 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3283 temp |= snb_b_fdi_train_param[i];
3284 I915_WRITE(reg, temp);
3289 for (retry = 0; retry < 5; retry++) {
3290 reg = FDI_RX_IIR(pipe);
3291 temp = I915_READ(reg);
3292 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3293 if (temp & FDI_RX_SYMBOL_LOCK) {
3294 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3295 DRM_DEBUG_KMS("FDI train 2 done.\n");
3304 DRM_ERROR("FDI train 2 fail!\n");
3306 DRM_DEBUG_KMS("FDI train done.\n");
3309 /* Manual link training for Ivy Bridge A0 parts */
3310 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3312 struct drm_device *dev = crtc->dev;
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3315 int pipe = intel_crtc->pipe;
3316 u32 reg, temp, i, j;
3318 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3320 reg = FDI_RX_IMR(pipe);
3321 temp = I915_READ(reg);
3322 temp &= ~FDI_RX_SYMBOL_LOCK;
3323 temp &= ~FDI_RX_BIT_LOCK;
3324 I915_WRITE(reg, temp);
3329 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3330 I915_READ(FDI_RX_IIR(pipe)));
3332 /* Try each vswing and preemphasis setting twice before moving on */
3333 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3334 /* disable first in case we need to retry */
3335 reg = FDI_TX_CTL(pipe);
3336 temp = I915_READ(reg);
3337 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3338 temp &= ~FDI_TX_ENABLE;
3339 I915_WRITE(reg, temp);
3341 reg = FDI_RX_CTL(pipe);
3342 temp = I915_READ(reg);
3343 temp &= ~FDI_LINK_TRAIN_AUTO;
3344 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3345 temp &= ~FDI_RX_ENABLE;
3346 I915_WRITE(reg, temp);
3348 /* enable CPU FDI TX and PCH FDI RX */
3349 reg = FDI_TX_CTL(pipe);
3350 temp = I915_READ(reg);
3351 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3352 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3353 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3354 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3355 temp |= snb_b_fdi_train_param[j/2];
3356 temp |= FDI_COMPOSITE_SYNC;
3357 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3359 I915_WRITE(FDI_RX_MISC(pipe),
3360 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3362 reg = FDI_RX_CTL(pipe);
3363 temp = I915_READ(reg);
3364 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3365 temp |= FDI_COMPOSITE_SYNC;
3366 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3369 udelay(1); /* should be 0.5us */
3371 for (i = 0; i < 4; i++) {
3372 reg = FDI_RX_IIR(pipe);
3373 temp = I915_READ(reg);
3374 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3376 if (temp & FDI_RX_BIT_LOCK ||
3377 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3378 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3379 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3383 udelay(1); /* should be 0.5us */
3386 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3391 reg = FDI_TX_CTL(pipe);
3392 temp = I915_READ(reg);
3393 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3394 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3395 I915_WRITE(reg, temp);
3397 reg = FDI_RX_CTL(pipe);
3398 temp = I915_READ(reg);
3399 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3400 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3401 I915_WRITE(reg, temp);
3404 udelay(2); /* should be 1.5us */
3406 for (i = 0; i < 4; i++) {
3407 reg = FDI_RX_IIR(pipe);
3408 temp = I915_READ(reg);
3409 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3411 if (temp & FDI_RX_SYMBOL_LOCK ||
3412 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3413 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3414 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3418 udelay(2); /* should be 1.5us */
3421 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3425 DRM_DEBUG_KMS("FDI train done.\n");
3428 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3430 struct drm_device *dev = intel_crtc->base.dev;
3431 struct drm_i915_private *dev_priv = dev->dev_private;
3432 int pipe = intel_crtc->pipe;
3436 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3437 reg = FDI_RX_CTL(pipe);
3438 temp = I915_READ(reg);
3439 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3440 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3441 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3442 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3447 /* Switch from Rawclk to PCDclk */
3448 temp = I915_READ(reg);
3449 I915_WRITE(reg, temp | FDI_PCDCLK);
3454 /* Enable CPU FDI TX PLL, always on for Ironlake */
3455 reg = FDI_TX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3458 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3465 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3467 struct drm_device *dev = intel_crtc->base.dev;
3468 struct drm_i915_private *dev_priv = dev->dev_private;
3469 int pipe = intel_crtc->pipe;
3472 /* Switch from PCDclk to Rawclk */
3473 reg = FDI_RX_CTL(pipe);
3474 temp = I915_READ(reg);
3475 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3477 /* Disable CPU FDI TX PLL */
3478 reg = FDI_TX_CTL(pipe);
3479 temp = I915_READ(reg);
3480 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3485 reg = FDI_RX_CTL(pipe);
3486 temp = I915_READ(reg);
3487 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3489 /* Wait for the clocks to turn off. */
3494 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3496 struct drm_device *dev = crtc->dev;
3497 struct drm_i915_private *dev_priv = dev->dev_private;
3498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499 int pipe = intel_crtc->pipe;
3502 /* disable CPU FDI tx and PCH FDI rx */
3503 reg = FDI_TX_CTL(pipe);
3504 temp = I915_READ(reg);
3505 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3508 reg = FDI_RX_CTL(pipe);
3509 temp = I915_READ(reg);
3510 temp &= ~(0x7 << 16);
3511 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3512 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3517 /* Ironlake workaround, disable clock pointer after downing FDI */
3518 if (HAS_PCH_IBX(dev))
3519 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3521 /* still set train pattern 1 */
3522 reg = FDI_TX_CTL(pipe);
3523 temp = I915_READ(reg);
3524 temp &= ~FDI_LINK_TRAIN_NONE;
3525 temp |= FDI_LINK_TRAIN_PATTERN_1;
3526 I915_WRITE(reg, temp);
3528 reg = FDI_RX_CTL(pipe);
3529 temp = I915_READ(reg);
3530 if (HAS_PCH_CPT(dev)) {
3531 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3532 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3534 temp &= ~FDI_LINK_TRAIN_NONE;
3535 temp |= FDI_LINK_TRAIN_PATTERN_1;
3537 /* BPC in FDI rx is consistent with that in PIPECONF */
3538 temp &= ~(0x07 << 16);
3539 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3540 I915_WRITE(reg, temp);
3546 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3548 struct intel_crtc *crtc;
3550 /* Note that we don't need to be called with mode_config.lock here
3551 * as our list of CRTC objects is static for the lifetime of the
3552 * device and so cannot disappear as we iterate. Similarly, we can
3553 * happily treat the predicates as racy, atomic checks as userspace
3554 * cannot claim and pin a new fb without at least acquring the
3555 * struct_mutex and so serialising with us.
3557 for_each_intel_crtc(dev, crtc) {
3558 if (atomic_read(&crtc->unpin_work_count) == 0)
3561 if (crtc->unpin_work)
3562 intel_wait_for_vblank(dev, crtc->pipe);
3570 static void page_flip_completed(struct intel_crtc *intel_crtc)
3572 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3573 struct intel_unpin_work *work = intel_crtc->unpin_work;
3575 /* ensure that the unpin work is consistent wrt ->pending. */
3577 intel_crtc->unpin_work = NULL;
3580 drm_send_vblank_event(intel_crtc->base.dev,
3584 drm_crtc_vblank_put(&intel_crtc->base);
3586 wake_up_all(&dev_priv->pending_flip_queue);
3587 queue_work(dev_priv->wq, &work->work);
3589 trace_i915_flip_complete(intel_crtc->plane,
3590 work->pending_flip_obj);
3593 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3595 struct drm_device *dev = crtc->dev;
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3598 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3599 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3600 !intel_crtc_has_pending_flip(crtc),
3602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3604 spin_lock_irq(&dev->event_lock);
3605 if (intel_crtc->unpin_work) {
3606 WARN_ONCE(1, "Removing stuck page flip\n");
3607 page_flip_completed(intel_crtc);
3609 spin_unlock_irq(&dev->event_lock);
3612 if (crtc->primary->fb) {
3613 mutex_lock(&dev->struct_mutex);
3614 intel_finish_fb(crtc->primary->fb);
3615 mutex_unlock(&dev->struct_mutex);
3619 /* Program iCLKIP clock to the desired frequency */
3620 static void lpt_program_iclkip(struct drm_crtc *crtc)
3622 struct drm_device *dev = crtc->dev;
3623 struct drm_i915_private *dev_priv = dev->dev_private;
3624 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3625 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3628 mutex_lock(&dev_priv->dpio_lock);
3630 /* It is necessary to ungate the pixclk gate prior to programming
3631 * the divisors, and gate it back when it is done.
3633 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3635 /* Disable SSCCTL */
3636 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3637 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3641 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3642 if (clock == 20000) {
3647 /* The iCLK virtual clock root frequency is in MHz,
3648 * but the adjusted_mode->crtc_clock in in KHz. To get the
3649 * divisors, it is necessary to divide one by another, so we
3650 * convert the virtual clock precision to KHz here for higher
3653 u32 iclk_virtual_root_freq = 172800 * 1000;
3654 u32 iclk_pi_range = 64;
3655 u32 desired_divisor, msb_divisor_value, pi_value;
3657 desired_divisor = (iclk_virtual_root_freq / clock);
3658 msb_divisor_value = desired_divisor / iclk_pi_range;
3659 pi_value = desired_divisor % iclk_pi_range;
3662 divsel = msb_divisor_value - 2;
3663 phaseinc = pi_value;
3666 /* This should not happen with any sane values */
3667 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3668 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3669 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3670 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3672 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3679 /* Program SSCDIVINTPHASE6 */
3680 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3681 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3682 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3683 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3684 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3685 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3686 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3687 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3689 /* Program SSCAUXDIV */
3690 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3691 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3692 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3693 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3695 /* Enable modulator and associated divider */
3696 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3697 temp &= ~SBI_SSCCTL_DISABLE;
3698 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3700 /* Wait for initialization time */
3703 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3705 mutex_unlock(&dev_priv->dpio_lock);
3708 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3709 enum pipe pch_transcoder)
3711 struct drm_device *dev = crtc->base.dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3715 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3716 I915_READ(HTOTAL(cpu_transcoder)));
3717 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3718 I915_READ(HBLANK(cpu_transcoder)));
3719 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3720 I915_READ(HSYNC(cpu_transcoder)));
3722 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3723 I915_READ(VTOTAL(cpu_transcoder)));
3724 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3725 I915_READ(VBLANK(cpu_transcoder)));
3726 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3727 I915_READ(VSYNC(cpu_transcoder)));
3728 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3729 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3732 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3734 struct drm_i915_private *dev_priv = dev->dev_private;
3737 temp = I915_READ(SOUTH_CHICKEN1);
3738 if (temp & FDI_BC_BIFURCATION_SELECT)
3741 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3742 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3744 temp |= FDI_BC_BIFURCATION_SELECT;
3745 DRM_DEBUG_KMS("enabling fdi C rx\n");
3746 I915_WRITE(SOUTH_CHICKEN1, temp);
3747 POSTING_READ(SOUTH_CHICKEN1);
3750 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3752 struct drm_device *dev = intel_crtc->base.dev;
3753 struct drm_i915_private *dev_priv = dev->dev_private;
3755 switch (intel_crtc->pipe) {
3759 if (intel_crtc->config->fdi_lanes > 2)
3760 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3762 cpt_enable_fdi_bc_bifurcation(dev);
3766 cpt_enable_fdi_bc_bifurcation(dev);
3775 * Enable PCH resources required for PCH ports:
3777 * - FDI training & RX/TX
3778 * - update transcoder timings
3779 * - DP transcoding bits
3782 static void ironlake_pch_enable(struct drm_crtc *crtc)
3784 struct drm_device *dev = crtc->dev;
3785 struct drm_i915_private *dev_priv = dev->dev_private;
3786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3787 int pipe = intel_crtc->pipe;
3790 assert_pch_transcoder_disabled(dev_priv, pipe);
3792 if (IS_IVYBRIDGE(dev))
3793 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3795 /* Write the TU size bits before fdi link training, so that error
3796 * detection works. */
3797 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3798 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3800 /* For PCH output, training FDI link */
3801 dev_priv->display.fdi_link_train(crtc);
3803 /* We need to program the right clock selection before writing the pixel
3804 * mutliplier into the DPLL. */
3805 if (HAS_PCH_CPT(dev)) {
3808 temp = I915_READ(PCH_DPLL_SEL);
3809 temp |= TRANS_DPLL_ENABLE(pipe);
3810 sel = TRANS_DPLLB_SEL(pipe);
3811 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3815 I915_WRITE(PCH_DPLL_SEL, temp);
3818 /* XXX: pch pll's can be enabled any time before we enable the PCH
3819 * transcoder, and we actually should do this to not upset any PCH
3820 * transcoder that already use the clock when we share it.
3822 * Note that enable_shared_dpll tries to do the right thing, but
3823 * get_shared_dpll unconditionally resets the pll - we need that to have
3824 * the right LVDS enable sequence. */
3825 intel_enable_shared_dpll(intel_crtc);
3827 /* set transcoder timing, panel must allow it */
3828 assert_panel_unlocked(dev_priv, pipe);
3829 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3831 intel_fdi_normal_train(crtc);
3833 /* For PCH DP, enable TRANS_DP_CTL */
3834 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3835 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3836 reg = TRANS_DP_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3839 TRANS_DP_SYNC_MASK |
3841 temp |= (TRANS_DP_OUTPUT_ENABLE |
3842 TRANS_DP_ENH_FRAMING);
3843 temp |= bpc << 9; /* same format but at 11:9 */
3845 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3846 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3847 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3848 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3850 switch (intel_trans_dp_port_sel(crtc)) {
3852 temp |= TRANS_DP_PORT_SEL_B;
3855 temp |= TRANS_DP_PORT_SEL_C;
3858 temp |= TRANS_DP_PORT_SEL_D;
3864 I915_WRITE(reg, temp);
3867 ironlake_enable_pch_transcoder(dev_priv, pipe);
3870 static void lpt_pch_enable(struct drm_crtc *crtc)
3872 struct drm_device *dev = crtc->dev;
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3875 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3877 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3879 lpt_program_iclkip(crtc);
3881 /* Set transcoder timing. */
3882 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3884 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3887 void intel_put_shared_dpll(struct intel_crtc *crtc)
3889 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3894 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3895 WARN(1, "bad %s crtc mask\n", pll->name);
3899 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3900 if (pll->config.crtc_mask == 0) {
3902 WARN_ON(pll->active);
3905 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3908 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3909 struct intel_crtc_state *crtc_state)
3911 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3912 struct intel_shared_dpll *pll;
3913 enum intel_dpll_id i;
3915 if (HAS_PCH_IBX(dev_priv->dev)) {
3916 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3917 i = (enum intel_dpll_id) crtc->pipe;
3918 pll = &dev_priv->shared_dplls[i];
3920 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3921 crtc->base.base.id, pll->name);
3923 WARN_ON(pll->new_config->crtc_mask);
3928 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3929 pll = &dev_priv->shared_dplls[i];
3931 /* Only want to check enabled timings first */
3932 if (pll->new_config->crtc_mask == 0)
3935 if (memcmp(&crtc_state->dpll_hw_state,
3936 &pll->new_config->hw_state,
3937 sizeof(pll->new_config->hw_state)) == 0) {
3938 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3939 crtc->base.base.id, pll->name,
3940 pll->new_config->crtc_mask,
3946 /* Ok no matching timings, maybe there's a free one? */
3947 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3948 pll = &dev_priv->shared_dplls[i];
3949 if (pll->new_config->crtc_mask == 0) {
3950 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3951 crtc->base.base.id, pll->name);
3959 if (pll->new_config->crtc_mask == 0)
3960 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3962 crtc_state->shared_dpll = i;
3963 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3964 pipe_name(crtc->pipe));
3966 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3972 * intel_shared_dpll_start_config - start a new PLL staged config
3973 * @dev_priv: DRM device
3974 * @clear_pipes: mask of pipes that will have their PLLs freed
3976 * Starts a new PLL staged config, copying the current config but
3977 * releasing the references of pipes specified in clear_pipes.
3979 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3980 unsigned clear_pipes)
3982 struct intel_shared_dpll *pll;
3983 enum intel_dpll_id i;
3985 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3986 pll = &dev_priv->shared_dplls[i];
3988 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3990 if (!pll->new_config)
3993 pll->new_config->crtc_mask &= ~clear_pipes;
4000 pll = &dev_priv->shared_dplls[i];
4001 kfree(pll->new_config);
4002 pll->new_config = NULL;
4008 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4010 struct intel_shared_dpll *pll;
4011 enum intel_dpll_id i;
4013 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4014 pll = &dev_priv->shared_dplls[i];
4016 WARN_ON(pll->new_config == &pll->config);
4018 pll->config = *pll->new_config;
4019 kfree(pll->new_config);
4020 pll->new_config = NULL;
4024 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4026 struct intel_shared_dpll *pll;
4027 enum intel_dpll_id i;
4029 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4030 pll = &dev_priv->shared_dplls[i];
4032 WARN_ON(pll->new_config == &pll->config);
4034 kfree(pll->new_config);
4035 pll->new_config = NULL;
4039 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4041 struct drm_i915_private *dev_priv = dev->dev_private;
4042 int dslreg = PIPEDSL(pipe);
4045 temp = I915_READ(dslreg);
4047 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4048 if (wait_for(I915_READ(dslreg) != temp, 5))
4049 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4053 static void skylake_pfit_enable(struct intel_crtc *crtc)
4055 struct drm_device *dev = crtc->base.dev;
4056 struct drm_i915_private *dev_priv = dev->dev_private;
4057 int pipe = crtc->pipe;
4059 if (crtc->config->pch_pfit.enabled) {
4060 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4061 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4062 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4066 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4068 struct drm_device *dev = crtc->base.dev;
4069 struct drm_i915_private *dev_priv = dev->dev_private;
4070 int pipe = crtc->pipe;
4072 if (crtc->config->pch_pfit.enabled) {
4073 /* Force use of hard-coded filter coefficients
4074 * as some pre-programmed values are broken,
4077 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4078 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4079 PF_PIPE_SEL_IVB(pipe));
4081 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4082 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4083 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4087 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4089 struct drm_device *dev = crtc->dev;
4090 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4091 struct drm_plane *plane;
4092 struct intel_plane *intel_plane;
4094 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4095 intel_plane = to_intel_plane(plane);
4096 if (intel_plane->pipe == pipe)
4097 intel_plane_restore(&intel_plane->base);
4101 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4103 struct drm_device *dev = crtc->dev;
4104 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4105 struct drm_plane *plane;
4106 struct intel_plane *intel_plane;
4108 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4109 intel_plane = to_intel_plane(plane);
4110 if (intel_plane->pipe == pipe)
4111 plane->funcs->disable_plane(plane);
4115 void hsw_enable_ips(struct intel_crtc *crtc)
4117 struct drm_device *dev = crtc->base.dev;
4118 struct drm_i915_private *dev_priv = dev->dev_private;
4120 if (!crtc->config->ips_enabled)
4123 /* We can only enable IPS after we enable a plane and wait for a vblank */
4124 intel_wait_for_vblank(dev, crtc->pipe);
4126 assert_plane_enabled(dev_priv, crtc->plane);
4127 if (IS_BROADWELL(dev)) {
4128 mutex_lock(&dev_priv->rps.hw_lock);
4129 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4130 mutex_unlock(&dev_priv->rps.hw_lock);
4131 /* Quoting Art Runyan: "its not safe to expect any particular
4132 * value in IPS_CTL bit 31 after enabling IPS through the
4133 * mailbox." Moreover, the mailbox may return a bogus state,
4134 * so we need to just enable it and continue on.
4137 I915_WRITE(IPS_CTL, IPS_ENABLE);
4138 /* The bit only becomes 1 in the next vblank, so this wait here
4139 * is essentially intel_wait_for_vblank. If we don't have this
4140 * and don't wait for vblanks until the end of crtc_enable, then
4141 * the HW state readout code will complain that the expected
4142 * IPS_CTL value is not the one we read. */
4143 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4144 DRM_ERROR("Timed out waiting for IPS enable\n");
4148 void hsw_disable_ips(struct intel_crtc *crtc)
4150 struct drm_device *dev = crtc->base.dev;
4151 struct drm_i915_private *dev_priv = dev->dev_private;
4153 if (!crtc->config->ips_enabled)
4156 assert_plane_enabled(dev_priv, crtc->plane);
4157 if (IS_BROADWELL(dev)) {
4158 mutex_lock(&dev_priv->rps.hw_lock);
4159 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4160 mutex_unlock(&dev_priv->rps.hw_lock);
4161 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4162 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4163 DRM_ERROR("Timed out waiting for IPS disable\n");
4165 I915_WRITE(IPS_CTL, 0);
4166 POSTING_READ(IPS_CTL);
4169 /* We need to wait for a vblank before we can disable the plane. */
4170 intel_wait_for_vblank(dev, crtc->pipe);
4173 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4174 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4176 struct drm_device *dev = crtc->dev;
4177 struct drm_i915_private *dev_priv = dev->dev_private;
4178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179 enum pipe pipe = intel_crtc->pipe;
4180 int palreg = PALETTE(pipe);
4182 bool reenable_ips = false;
4184 /* The clocks have to be on to load the palette. */
4185 if (!crtc->enabled || !intel_crtc->active)
4188 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4189 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4190 assert_dsi_pll_enabled(dev_priv);
4192 assert_pll_enabled(dev_priv, pipe);
4195 /* use legacy palette for Ironlake */
4196 if (!HAS_GMCH_DISPLAY(dev))
4197 palreg = LGC_PALETTE(pipe);
4199 /* Workaround : Do not read or write the pipe palette/gamma data while
4200 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4202 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4203 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4204 GAMMA_MODE_MODE_SPLIT)) {
4205 hsw_disable_ips(intel_crtc);
4206 reenable_ips = true;
4209 for (i = 0; i < 256; i++) {
4210 I915_WRITE(palreg + 4 * i,
4211 (intel_crtc->lut_r[i] << 16) |
4212 (intel_crtc->lut_g[i] << 8) |
4213 intel_crtc->lut_b[i]);
4217 hsw_enable_ips(intel_crtc);
4220 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4222 if (!enable && intel_crtc->overlay) {
4223 struct drm_device *dev = intel_crtc->base.dev;
4224 struct drm_i915_private *dev_priv = dev->dev_private;
4226 mutex_lock(&dev->struct_mutex);
4227 dev_priv->mm.interruptible = false;
4228 (void) intel_overlay_switch_off(intel_crtc->overlay);
4229 dev_priv->mm.interruptible = true;
4230 mutex_unlock(&dev->struct_mutex);
4233 /* Let userspace switch the overlay on again. In most cases userspace
4234 * has to recompute where to put it anyway.
4238 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4240 struct drm_device *dev = crtc->dev;
4241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4242 int pipe = intel_crtc->pipe;
4244 intel_enable_primary_hw_plane(crtc->primary, crtc);
4245 intel_enable_sprite_planes(crtc);
4246 intel_crtc_update_cursor(crtc, true);
4247 intel_crtc_dpms_overlay(intel_crtc, true);
4249 hsw_enable_ips(intel_crtc);
4251 mutex_lock(&dev->struct_mutex);
4252 intel_fbc_update(dev);
4253 mutex_unlock(&dev->struct_mutex);
4256 * FIXME: Once we grow proper nuclear flip support out of this we need
4257 * to compute the mask of flip planes precisely. For the time being
4258 * consider this a flip from a NULL plane.
4260 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4263 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4265 struct drm_device *dev = crtc->dev;
4266 struct drm_i915_private *dev_priv = dev->dev_private;
4267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4268 int pipe = intel_crtc->pipe;
4269 int plane = intel_crtc->plane;
4271 intel_crtc_wait_for_pending_flips(crtc);
4273 if (dev_priv->fbc.plane == plane)
4274 intel_fbc_disable(dev);
4276 hsw_disable_ips(intel_crtc);
4278 intel_crtc_dpms_overlay(intel_crtc, false);
4279 intel_crtc_update_cursor(crtc, false);
4280 intel_disable_sprite_planes(crtc);
4281 intel_disable_primary_hw_plane(crtc->primary, crtc);
4284 * FIXME: Once we grow proper nuclear flip support out of this we need
4285 * to compute the mask of flip planes precisely. For the time being
4286 * consider this a flip to a NULL plane.
4288 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4291 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4293 struct drm_device *dev = crtc->dev;
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4296 struct intel_encoder *encoder;
4297 int pipe = intel_crtc->pipe;
4299 WARN_ON(!crtc->enabled);
4301 if (intel_crtc->active)
4304 if (intel_crtc->config->has_pch_encoder)
4305 intel_prepare_shared_dpll(intel_crtc);
4307 if (intel_crtc->config->has_dp_encoder)
4308 intel_dp_set_m_n(intel_crtc);
4310 intel_set_pipe_timings(intel_crtc);
4312 if (intel_crtc->config->has_pch_encoder) {
4313 intel_cpu_transcoder_set_m_n(intel_crtc,
4314 &intel_crtc->config->fdi_m_n, NULL);
4317 ironlake_set_pipeconf(crtc);
4319 intel_crtc->active = true;
4321 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4322 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4324 for_each_encoder_on_crtc(dev, crtc, encoder)
4325 if (encoder->pre_enable)
4326 encoder->pre_enable(encoder);
4328 if (intel_crtc->config->has_pch_encoder) {
4329 /* Note: FDI PLL enabling _must_ be done before we enable the
4330 * cpu pipes, hence this is separate from all the other fdi/pch
4332 ironlake_fdi_pll_enable(intel_crtc);
4334 assert_fdi_tx_disabled(dev_priv, pipe);
4335 assert_fdi_rx_disabled(dev_priv, pipe);
4338 ironlake_pfit_enable(intel_crtc);
4341 * On ILK+ LUT must be loaded before the pipe is running but with
4344 intel_crtc_load_lut(crtc);
4346 intel_update_watermarks(crtc);
4347 intel_enable_pipe(intel_crtc);
4349 if (intel_crtc->config->has_pch_encoder)
4350 ironlake_pch_enable(crtc);
4352 assert_vblank_disabled(crtc);
4353 drm_crtc_vblank_on(crtc);
4355 for_each_encoder_on_crtc(dev, crtc, encoder)
4356 encoder->enable(encoder);
4358 if (HAS_PCH_CPT(dev))
4359 cpt_verify_modeset(dev, intel_crtc->pipe);
4361 intel_crtc_enable_planes(crtc);
4364 /* IPS only exists on ULT machines and is tied to pipe A. */
4365 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4367 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4371 * This implements the workaround described in the "notes" section of the mode
4372 * set sequence documentation. When going from no pipes or single pipe to
4373 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4374 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4376 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4378 struct drm_device *dev = crtc->base.dev;
4379 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4381 /* We want to get the other_active_crtc only if there's only 1 other
4383 for_each_intel_crtc(dev, crtc_it) {
4384 if (!crtc_it->active || crtc_it == crtc)
4387 if (other_active_crtc)
4390 other_active_crtc = crtc_it;
4392 if (!other_active_crtc)
4395 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4396 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4399 static void haswell_crtc_enable(struct drm_crtc *crtc)
4401 struct drm_device *dev = crtc->dev;
4402 struct drm_i915_private *dev_priv = dev->dev_private;
4403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4404 struct intel_encoder *encoder;
4405 int pipe = intel_crtc->pipe;
4407 WARN_ON(!crtc->enabled);
4409 if (intel_crtc->active)
4412 if (intel_crtc_to_shared_dpll(intel_crtc))
4413 intel_enable_shared_dpll(intel_crtc);
4415 if (intel_crtc->config->has_dp_encoder)
4416 intel_dp_set_m_n(intel_crtc);
4418 intel_set_pipe_timings(intel_crtc);
4420 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4421 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4422 intel_crtc->config->pixel_multiplier - 1);
4425 if (intel_crtc->config->has_pch_encoder) {
4426 intel_cpu_transcoder_set_m_n(intel_crtc,
4427 &intel_crtc->config->fdi_m_n, NULL);
4430 haswell_set_pipeconf(crtc);
4432 intel_set_pipe_csc(crtc);
4434 intel_crtc->active = true;
4436 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4437 for_each_encoder_on_crtc(dev, crtc, encoder)
4438 if (encoder->pre_enable)
4439 encoder->pre_enable(encoder);
4441 if (intel_crtc->config->has_pch_encoder) {
4442 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4444 dev_priv->display.fdi_link_train(crtc);
4447 intel_ddi_enable_pipe_clock(intel_crtc);
4449 if (IS_SKYLAKE(dev))
4450 skylake_pfit_enable(intel_crtc);
4452 ironlake_pfit_enable(intel_crtc);
4455 * On ILK+ LUT must be loaded before the pipe is running but with
4458 intel_crtc_load_lut(crtc);
4460 intel_ddi_set_pipe_settings(crtc);
4461 intel_ddi_enable_transcoder_func(crtc);
4463 intel_update_watermarks(crtc);
4464 intel_enable_pipe(intel_crtc);
4466 if (intel_crtc->config->has_pch_encoder)
4467 lpt_pch_enable(crtc);
4469 if (intel_crtc->config->dp_encoder_is_mst)
4470 intel_ddi_set_vc_payload_alloc(crtc, true);
4472 assert_vblank_disabled(crtc);
4473 drm_crtc_vblank_on(crtc);
4475 for_each_encoder_on_crtc(dev, crtc, encoder) {
4476 encoder->enable(encoder);
4477 intel_opregion_notify_encoder(encoder, true);
4480 /* If we change the relative order between pipe/planes enabling, we need
4481 * to change the workaround. */
4482 haswell_mode_set_planes_workaround(intel_crtc);
4483 intel_crtc_enable_planes(crtc);
4486 static void skylake_pfit_disable(struct intel_crtc *crtc)
4488 struct drm_device *dev = crtc->base.dev;
4489 struct drm_i915_private *dev_priv = dev->dev_private;
4490 int pipe = crtc->pipe;
4492 /* To avoid upsetting the power well on haswell only disable the pfit if
4493 * it's in use. The hw state code will make sure we get this right. */
4494 if (crtc->config->pch_pfit.enabled) {
4495 I915_WRITE(PS_CTL(pipe), 0);
4496 I915_WRITE(PS_WIN_POS(pipe), 0);
4497 I915_WRITE(PS_WIN_SZ(pipe), 0);
4501 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4503 struct drm_device *dev = crtc->base.dev;
4504 struct drm_i915_private *dev_priv = dev->dev_private;
4505 int pipe = crtc->pipe;
4507 /* To avoid upsetting the power well on haswell only disable the pfit if
4508 * it's in use. The hw state code will make sure we get this right. */
4509 if (crtc->config->pch_pfit.enabled) {
4510 I915_WRITE(PF_CTL(pipe), 0);
4511 I915_WRITE(PF_WIN_POS(pipe), 0);
4512 I915_WRITE(PF_WIN_SZ(pipe), 0);
4516 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4518 struct drm_device *dev = crtc->dev;
4519 struct drm_i915_private *dev_priv = dev->dev_private;
4520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4521 struct intel_encoder *encoder;
4522 int pipe = intel_crtc->pipe;
4525 if (!intel_crtc->active)
4528 intel_crtc_disable_planes(crtc);
4530 for_each_encoder_on_crtc(dev, crtc, encoder)
4531 encoder->disable(encoder);
4533 drm_crtc_vblank_off(crtc);
4534 assert_vblank_disabled(crtc);
4536 if (intel_crtc->config->has_pch_encoder)
4537 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4539 intel_disable_pipe(intel_crtc);
4541 ironlake_pfit_disable(intel_crtc);
4543 for_each_encoder_on_crtc(dev, crtc, encoder)
4544 if (encoder->post_disable)
4545 encoder->post_disable(encoder);
4547 if (intel_crtc->config->has_pch_encoder) {
4548 ironlake_fdi_disable(crtc);
4550 ironlake_disable_pch_transcoder(dev_priv, pipe);
4552 if (HAS_PCH_CPT(dev)) {
4553 /* disable TRANS_DP_CTL */
4554 reg = TRANS_DP_CTL(pipe);
4555 temp = I915_READ(reg);
4556 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4557 TRANS_DP_PORT_SEL_MASK);
4558 temp |= TRANS_DP_PORT_SEL_NONE;
4559 I915_WRITE(reg, temp);
4561 /* disable DPLL_SEL */
4562 temp = I915_READ(PCH_DPLL_SEL);
4563 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4564 I915_WRITE(PCH_DPLL_SEL, temp);
4567 /* disable PCH DPLL */
4568 intel_disable_shared_dpll(intel_crtc);
4570 ironlake_fdi_pll_disable(intel_crtc);
4573 intel_crtc->active = false;
4574 intel_update_watermarks(crtc);
4576 mutex_lock(&dev->struct_mutex);
4577 intel_fbc_update(dev);
4578 mutex_unlock(&dev->struct_mutex);
4581 static void haswell_crtc_disable(struct drm_crtc *crtc)
4583 struct drm_device *dev = crtc->dev;
4584 struct drm_i915_private *dev_priv = dev->dev_private;
4585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4586 struct intel_encoder *encoder;
4587 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4589 if (!intel_crtc->active)
4592 intel_crtc_disable_planes(crtc);
4594 for_each_encoder_on_crtc(dev, crtc, encoder) {
4595 intel_opregion_notify_encoder(encoder, false);
4596 encoder->disable(encoder);
4599 drm_crtc_vblank_off(crtc);
4600 assert_vblank_disabled(crtc);
4602 if (intel_crtc->config->has_pch_encoder)
4603 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4605 intel_disable_pipe(intel_crtc);
4607 if (intel_crtc->config->dp_encoder_is_mst)
4608 intel_ddi_set_vc_payload_alloc(crtc, false);
4610 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4612 if (IS_SKYLAKE(dev))
4613 skylake_pfit_disable(intel_crtc);
4615 ironlake_pfit_disable(intel_crtc);
4617 intel_ddi_disable_pipe_clock(intel_crtc);
4619 if (intel_crtc->config->has_pch_encoder) {
4620 lpt_disable_pch_transcoder(dev_priv);
4621 intel_ddi_fdi_disable(crtc);
4624 for_each_encoder_on_crtc(dev, crtc, encoder)
4625 if (encoder->post_disable)
4626 encoder->post_disable(encoder);
4628 intel_crtc->active = false;
4629 intel_update_watermarks(crtc);
4631 mutex_lock(&dev->struct_mutex);
4632 intel_fbc_update(dev);
4633 mutex_unlock(&dev->struct_mutex);
4635 if (intel_crtc_to_shared_dpll(intel_crtc))
4636 intel_disable_shared_dpll(intel_crtc);
4639 static void ironlake_crtc_off(struct drm_crtc *crtc)
4641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4642 intel_put_shared_dpll(intel_crtc);
4646 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4648 struct drm_device *dev = crtc->base.dev;
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4650 struct intel_crtc_state *pipe_config = crtc->config;
4652 if (!pipe_config->gmch_pfit.control)
4656 * The panel fitter should only be adjusted whilst the pipe is disabled,
4657 * according to register description and PRM.
4659 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4660 assert_pipe_disabled(dev_priv, crtc->pipe);
4662 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4663 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4665 /* Border color in case we don't scale up to the full screen. Black by
4666 * default, change to something else for debugging. */
4667 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4670 static enum intel_display_power_domain port_to_power_domain(enum port port)
4674 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4676 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4678 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4680 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4683 return POWER_DOMAIN_PORT_OTHER;
4687 #define for_each_power_domain(domain, mask) \
4688 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4689 if ((1 << (domain)) & (mask))
4691 enum intel_display_power_domain
4692 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4694 struct drm_device *dev = intel_encoder->base.dev;
4695 struct intel_digital_port *intel_dig_port;
4697 switch (intel_encoder->type) {
4698 case INTEL_OUTPUT_UNKNOWN:
4699 /* Only DDI platforms should ever use this output type */
4700 WARN_ON_ONCE(!HAS_DDI(dev));
4701 case INTEL_OUTPUT_DISPLAYPORT:
4702 case INTEL_OUTPUT_HDMI:
4703 case INTEL_OUTPUT_EDP:
4704 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4705 return port_to_power_domain(intel_dig_port->port);
4706 case INTEL_OUTPUT_DP_MST:
4707 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4708 return port_to_power_domain(intel_dig_port->port);
4709 case INTEL_OUTPUT_ANALOG:
4710 return POWER_DOMAIN_PORT_CRT;
4711 case INTEL_OUTPUT_DSI:
4712 return POWER_DOMAIN_PORT_DSI;
4714 return POWER_DOMAIN_PORT_OTHER;
4718 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4720 struct drm_device *dev = crtc->dev;
4721 struct intel_encoder *intel_encoder;
4722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4723 enum pipe pipe = intel_crtc->pipe;
4725 enum transcoder transcoder;
4727 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4729 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4730 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4731 if (intel_crtc->config->pch_pfit.enabled ||
4732 intel_crtc->config->pch_pfit.force_thru)
4733 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4735 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4736 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4741 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4743 struct drm_i915_private *dev_priv = dev->dev_private;
4744 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4745 struct intel_crtc *crtc;
4748 * First get all needed power domains, then put all unneeded, to avoid
4749 * any unnecessary toggling of the power wells.
4751 for_each_intel_crtc(dev, crtc) {
4752 enum intel_display_power_domain domain;
4754 if (!crtc->base.enabled)
4757 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4759 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4760 intel_display_power_get(dev_priv, domain);
4763 if (dev_priv->display.modeset_global_resources)
4764 dev_priv->display.modeset_global_resources(dev);
4766 for_each_intel_crtc(dev, crtc) {
4767 enum intel_display_power_domain domain;
4769 for_each_power_domain(domain, crtc->enabled_power_domains)
4770 intel_display_power_put(dev_priv, domain);
4772 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4775 intel_display_set_init_power(dev_priv, false);
4778 /* returns HPLL frequency in kHz */
4779 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4781 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4783 /* Obtain SKU information */
4784 mutex_lock(&dev_priv->dpio_lock);
4785 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4786 CCK_FUSE_HPLL_FREQ_MASK;
4787 mutex_unlock(&dev_priv->dpio_lock);
4789 return vco_freq[hpll_freq] * 1000;
4792 static void vlv_update_cdclk(struct drm_device *dev)
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4796 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4797 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4798 dev_priv->vlv_cdclk_freq);
4801 * Program the gmbus_freq based on the cdclk frequency.
4802 * BSpec erroneously claims we should aim for 4MHz, but
4803 * in fact 1MHz is the correct frequency.
4805 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4808 /* Adjust CDclk dividers to allow high res or save power if possible */
4809 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4811 struct drm_i915_private *dev_priv = dev->dev_private;
4814 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4816 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4818 else if (cdclk == 266667)
4823 mutex_lock(&dev_priv->rps.hw_lock);
4824 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4825 val &= ~DSPFREQGUAR_MASK;
4826 val |= (cmd << DSPFREQGUAR_SHIFT);
4827 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4828 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4829 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4831 DRM_ERROR("timed out waiting for CDclk change\n");
4833 mutex_unlock(&dev_priv->rps.hw_lock);
4835 if (cdclk == 400000) {
4838 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4840 mutex_lock(&dev_priv->dpio_lock);
4841 /* adjust cdclk divider */
4842 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4843 val &= ~DISPLAY_FREQUENCY_VALUES;
4845 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4847 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4848 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4850 DRM_ERROR("timed out waiting for CDclk change\n");
4851 mutex_unlock(&dev_priv->dpio_lock);
4854 mutex_lock(&dev_priv->dpio_lock);
4855 /* adjust self-refresh exit latency value */
4856 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4860 * For high bandwidth configs, we set a higher latency in the bunit
4861 * so that the core display fetch happens in time to avoid underruns.
4863 if (cdclk == 400000)
4864 val |= 4500 / 250; /* 4.5 usec */
4866 val |= 3000 / 250; /* 3.0 usec */
4867 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4868 mutex_unlock(&dev_priv->dpio_lock);
4870 vlv_update_cdclk(dev);
4873 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4875 struct drm_i915_private *dev_priv = dev->dev_private;
4878 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4895 MISSING_CASE(cdclk);
4899 mutex_lock(&dev_priv->rps.hw_lock);
4900 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4901 val &= ~DSPFREQGUAR_MASK_CHV;
4902 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4903 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4904 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4905 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4907 DRM_ERROR("timed out waiting for CDclk change\n");
4909 mutex_unlock(&dev_priv->rps.hw_lock);
4911 vlv_update_cdclk(dev);
4914 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4917 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4919 /* FIXME: Punit isn't quite ready yet */
4920 if (IS_CHERRYVIEW(dev_priv->dev))
4924 * Really only a few cases to deal with, as only 4 CDclks are supported:
4927 * 320/333MHz (depends on HPLL freq)
4929 * So we check to see whether we're above 90% of the lower bin and
4932 * We seem to get an unstable or solid color picture at 200MHz.
4933 * Not sure what's wrong. For now use 200MHz only when all pipes
4936 if (max_pixclk > freq_320*9/10)
4938 else if (max_pixclk > 266667*9/10)
4940 else if (max_pixclk > 0)
4946 /* compute the max pixel clock for new configuration */
4947 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4949 struct drm_device *dev = dev_priv->dev;
4950 struct intel_crtc *intel_crtc;
4953 for_each_intel_crtc(dev, intel_crtc) {
4954 if (intel_crtc->new_enabled)
4955 max_pixclk = max(max_pixclk,
4956 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4962 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4963 unsigned *prepare_pipes)
4965 struct drm_i915_private *dev_priv = dev->dev_private;
4966 struct intel_crtc *intel_crtc;
4967 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4969 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4970 dev_priv->vlv_cdclk_freq)
4973 /* disable/enable all currently active pipes while we change cdclk */
4974 for_each_intel_crtc(dev, intel_crtc)
4975 if (intel_crtc->base.enabled)
4976 *prepare_pipes |= (1 << intel_crtc->pipe);
4979 static void valleyview_modeset_global_resources(struct drm_device *dev)
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4983 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4985 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4987 * FIXME: We can end up here with all power domains off, yet
4988 * with a CDCLK frequency other than the minimum. To account
4989 * for this take the PIPE-A power domain, which covers the HW
4990 * blocks needed for the following programming. This can be
4991 * removed once it's guaranteed that we get here either with
4992 * the minimum CDCLK set, or the required power domains
4995 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
4997 if (IS_CHERRYVIEW(dev))
4998 cherryview_set_cdclk(dev, req_cdclk);
5000 valleyview_set_cdclk(dev, req_cdclk);
5002 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5006 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5008 struct drm_device *dev = crtc->dev;
5009 struct drm_i915_private *dev_priv = to_i915(dev);
5010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5011 struct intel_encoder *encoder;
5012 int pipe = intel_crtc->pipe;
5015 WARN_ON(!crtc->enabled);
5017 if (intel_crtc->active)
5020 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5023 if (IS_CHERRYVIEW(dev))
5024 chv_prepare_pll(intel_crtc, intel_crtc->config);
5026 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5029 if (intel_crtc->config->has_dp_encoder)
5030 intel_dp_set_m_n(intel_crtc);
5032 intel_set_pipe_timings(intel_crtc);
5034 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5035 struct drm_i915_private *dev_priv = dev->dev_private;
5037 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5038 I915_WRITE(CHV_CANVAS(pipe), 0);
5041 i9xx_set_pipeconf(intel_crtc);
5043 intel_crtc->active = true;
5045 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5047 for_each_encoder_on_crtc(dev, crtc, encoder)
5048 if (encoder->pre_pll_enable)
5049 encoder->pre_pll_enable(encoder);
5052 if (IS_CHERRYVIEW(dev))
5053 chv_enable_pll(intel_crtc, intel_crtc->config);
5055 vlv_enable_pll(intel_crtc, intel_crtc->config);
5058 for_each_encoder_on_crtc(dev, crtc, encoder)
5059 if (encoder->pre_enable)
5060 encoder->pre_enable(encoder);
5062 i9xx_pfit_enable(intel_crtc);
5064 intel_crtc_load_lut(crtc);
5066 intel_update_watermarks(crtc);
5067 intel_enable_pipe(intel_crtc);
5069 assert_vblank_disabled(crtc);
5070 drm_crtc_vblank_on(crtc);
5072 for_each_encoder_on_crtc(dev, crtc, encoder)
5073 encoder->enable(encoder);
5075 intel_crtc_enable_planes(crtc);
5077 /* Underruns don't raise interrupts, so check manually. */
5078 i9xx_check_fifo_underruns(dev_priv);
5081 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5083 struct drm_device *dev = crtc->base.dev;
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5086 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5087 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5090 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5092 struct drm_device *dev = crtc->dev;
5093 struct drm_i915_private *dev_priv = to_i915(dev);
5094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5095 struct intel_encoder *encoder;
5096 int pipe = intel_crtc->pipe;
5098 WARN_ON(!crtc->enabled);
5100 if (intel_crtc->active)
5103 i9xx_set_pll_dividers(intel_crtc);
5105 if (intel_crtc->config->has_dp_encoder)
5106 intel_dp_set_m_n(intel_crtc);
5108 intel_set_pipe_timings(intel_crtc);
5110 i9xx_set_pipeconf(intel_crtc);
5112 intel_crtc->active = true;
5115 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5117 for_each_encoder_on_crtc(dev, crtc, encoder)
5118 if (encoder->pre_enable)
5119 encoder->pre_enable(encoder);
5121 i9xx_enable_pll(intel_crtc);
5123 i9xx_pfit_enable(intel_crtc);
5125 intel_crtc_load_lut(crtc);
5127 intel_update_watermarks(crtc);
5128 intel_enable_pipe(intel_crtc);
5130 assert_vblank_disabled(crtc);
5131 drm_crtc_vblank_on(crtc);
5133 for_each_encoder_on_crtc(dev, crtc, encoder)
5134 encoder->enable(encoder);
5136 intel_crtc_enable_planes(crtc);
5139 * Gen2 reports pipe underruns whenever all planes are disabled.
5140 * So don't enable underrun reporting before at least some planes
5142 * FIXME: Need to fix the logic to work when we turn off all planes
5143 * but leave the pipe running.
5146 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5148 /* Underruns don't raise interrupts, so check manually. */
5149 i9xx_check_fifo_underruns(dev_priv);
5152 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5154 struct drm_device *dev = crtc->base.dev;
5155 struct drm_i915_private *dev_priv = dev->dev_private;
5157 if (!crtc->config->gmch_pfit.control)
5160 assert_pipe_disabled(dev_priv, crtc->pipe);
5162 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5163 I915_READ(PFIT_CONTROL));
5164 I915_WRITE(PFIT_CONTROL, 0);
5167 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5169 struct drm_device *dev = crtc->dev;
5170 struct drm_i915_private *dev_priv = dev->dev_private;
5171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5172 struct intel_encoder *encoder;
5173 int pipe = intel_crtc->pipe;
5175 if (!intel_crtc->active)
5179 * Gen2 reports pipe underruns whenever all planes are disabled.
5180 * So diasble underrun reporting before all the planes get disabled.
5181 * FIXME: Need to fix the logic to work when we turn off all planes
5182 * but leave the pipe running.
5185 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5188 * Vblank time updates from the shadow to live plane control register
5189 * are blocked if the memory self-refresh mode is active at that
5190 * moment. So to make sure the plane gets truly disabled, disable
5191 * first the self-refresh mode. The self-refresh enable bit in turn
5192 * will be checked/applied by the HW only at the next frame start
5193 * event which is after the vblank start event, so we need to have a
5194 * wait-for-vblank between disabling the plane and the pipe.
5196 intel_set_memory_cxsr(dev_priv, false);
5197 intel_crtc_disable_planes(crtc);
5200 * On gen2 planes are double buffered but the pipe isn't, so we must
5201 * wait for planes to fully turn off before disabling the pipe.
5202 * We also need to wait on all gmch platforms because of the
5203 * self-refresh mode constraint explained above.
5205 intel_wait_for_vblank(dev, pipe);
5207 for_each_encoder_on_crtc(dev, crtc, encoder)
5208 encoder->disable(encoder);
5210 drm_crtc_vblank_off(crtc);
5211 assert_vblank_disabled(crtc);
5213 intel_disable_pipe(intel_crtc);
5215 i9xx_pfit_disable(intel_crtc);
5217 for_each_encoder_on_crtc(dev, crtc, encoder)
5218 if (encoder->post_disable)
5219 encoder->post_disable(encoder);
5221 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5222 if (IS_CHERRYVIEW(dev))
5223 chv_disable_pll(dev_priv, pipe);
5224 else if (IS_VALLEYVIEW(dev))
5225 vlv_disable_pll(dev_priv, pipe);
5227 i9xx_disable_pll(intel_crtc);
5231 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5233 intel_crtc->active = false;
5234 intel_update_watermarks(crtc);
5236 mutex_lock(&dev->struct_mutex);
5237 intel_fbc_update(dev);
5238 mutex_unlock(&dev->struct_mutex);
5241 static void i9xx_crtc_off(struct drm_crtc *crtc)
5245 /* Master function to enable/disable CRTC and corresponding power wells */
5246 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5248 struct drm_device *dev = crtc->dev;
5249 struct drm_i915_private *dev_priv = dev->dev_private;
5250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5251 enum intel_display_power_domain domain;
5252 unsigned long domains;
5255 if (!intel_crtc->active) {
5256 domains = get_crtc_power_domains(crtc);
5257 for_each_power_domain(domain, domains)
5258 intel_display_power_get(dev_priv, domain);
5259 intel_crtc->enabled_power_domains = domains;
5261 dev_priv->display.crtc_enable(crtc);
5264 if (intel_crtc->active) {
5265 dev_priv->display.crtc_disable(crtc);
5267 domains = intel_crtc->enabled_power_domains;
5268 for_each_power_domain(domain, domains)
5269 intel_display_power_put(dev_priv, domain);
5270 intel_crtc->enabled_power_domains = 0;
5276 * Sets the power management mode of the pipe and plane.
5278 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5280 struct drm_device *dev = crtc->dev;
5281 struct intel_encoder *intel_encoder;
5282 bool enable = false;
5284 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5285 enable |= intel_encoder->connectors_active;
5287 intel_crtc_control(crtc, enable);
5290 static void intel_crtc_disable(struct drm_crtc *crtc)
5292 struct drm_device *dev = crtc->dev;
5293 struct drm_connector *connector;
5294 struct drm_i915_private *dev_priv = dev->dev_private;
5296 /* crtc should still be enabled when we disable it. */
5297 WARN_ON(!crtc->enabled);
5299 dev_priv->display.crtc_disable(crtc);
5300 dev_priv->display.off(crtc);
5302 crtc->primary->funcs->disable_plane(crtc->primary);
5304 /* Update computed state. */
5305 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5306 if (!connector->encoder || !connector->encoder->crtc)
5309 if (connector->encoder->crtc != crtc)
5312 connector->dpms = DRM_MODE_DPMS_OFF;
5313 to_intel_encoder(connector->encoder)->connectors_active = false;
5317 void intel_encoder_destroy(struct drm_encoder *encoder)
5319 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5321 drm_encoder_cleanup(encoder);
5322 kfree(intel_encoder);
5325 /* Simple dpms helper for encoders with just one connector, no cloning and only
5326 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5327 * state of the entire output pipe. */
5328 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5330 if (mode == DRM_MODE_DPMS_ON) {
5331 encoder->connectors_active = true;
5333 intel_crtc_update_dpms(encoder->base.crtc);
5335 encoder->connectors_active = false;
5337 intel_crtc_update_dpms(encoder->base.crtc);
5341 /* Cross check the actual hw state with our own modeset state tracking (and it's
5342 * internal consistency). */
5343 static void intel_connector_check_state(struct intel_connector *connector)
5345 if (connector->get_hw_state(connector)) {
5346 struct intel_encoder *encoder = connector->encoder;
5347 struct drm_crtc *crtc;
5348 bool encoder_enabled;
5351 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5352 connector->base.base.id,
5353 connector->base.name);
5355 /* there is no real hw state for MST connectors */
5356 if (connector->mst_port)
5359 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5360 "wrong connector dpms state\n");
5361 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5362 "active connector not linked to encoder\n");
5365 I915_STATE_WARN(!encoder->connectors_active,
5366 "encoder->connectors_active not set\n");
5368 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5369 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5370 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5373 crtc = encoder->base.crtc;
5375 I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5376 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5377 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5378 "encoder active on the wrong pipe\n");
5383 /* Even simpler default implementation, if there's really no special case to
5385 void intel_connector_dpms(struct drm_connector *connector, int mode)
5387 /* All the simple cases only support two dpms states. */
5388 if (mode != DRM_MODE_DPMS_ON)
5389 mode = DRM_MODE_DPMS_OFF;
5391 if (mode == connector->dpms)
5394 connector->dpms = mode;
5396 /* Only need to change hw state when actually enabled */
5397 if (connector->encoder)
5398 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5400 intel_modeset_check_state(connector->dev);
5403 /* Simple connector->get_hw_state implementation for encoders that support only
5404 * one connector and no cloning and hence the encoder state determines the state
5405 * of the connector. */
5406 bool intel_connector_get_hw_state(struct intel_connector *connector)
5409 struct intel_encoder *encoder = connector->encoder;
5411 return encoder->get_hw_state(encoder, &pipe);
5414 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5415 struct intel_crtc_state *pipe_config)
5417 struct drm_i915_private *dev_priv = dev->dev_private;
5418 struct intel_crtc *pipe_B_crtc =
5419 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5421 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5422 pipe_name(pipe), pipe_config->fdi_lanes);
5423 if (pipe_config->fdi_lanes > 4) {
5424 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5425 pipe_name(pipe), pipe_config->fdi_lanes);
5429 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5430 if (pipe_config->fdi_lanes > 2) {
5431 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5432 pipe_config->fdi_lanes);
5439 if (INTEL_INFO(dev)->num_pipes == 2)
5442 /* Ivybridge 3 pipe is really complicated */
5447 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5448 pipe_config->fdi_lanes > 2) {
5449 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5450 pipe_name(pipe), pipe_config->fdi_lanes);
5455 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5456 pipe_B_crtc->config->fdi_lanes <= 2) {
5457 if (pipe_config->fdi_lanes > 2) {
5458 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5459 pipe_name(pipe), pipe_config->fdi_lanes);
5463 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5473 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5474 struct intel_crtc_state *pipe_config)
5476 struct drm_device *dev = intel_crtc->base.dev;
5477 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5478 int lane, link_bw, fdi_dotclock;
5479 bool setup_ok, needs_recompute = false;
5482 /* FDI is a binary signal running at ~2.7GHz, encoding
5483 * each output octet as 10 bits. The actual frequency
5484 * is stored as a divider into a 100MHz clock, and the
5485 * mode pixel clock is stored in units of 1KHz.
5486 * Hence the bw of each lane in terms of the mode signal
5489 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5491 fdi_dotclock = adjusted_mode->crtc_clock;
5493 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5494 pipe_config->pipe_bpp);
5496 pipe_config->fdi_lanes = lane;
5498 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5499 link_bw, &pipe_config->fdi_m_n);
5501 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5502 intel_crtc->pipe, pipe_config);
5503 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5504 pipe_config->pipe_bpp -= 2*3;
5505 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5506 pipe_config->pipe_bpp);
5507 needs_recompute = true;
5508 pipe_config->bw_constrained = true;
5513 if (needs_recompute)
5516 return setup_ok ? 0 : -EINVAL;
5519 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5520 struct intel_crtc_state *pipe_config)
5522 pipe_config->ips_enabled = i915.enable_ips &&
5523 hsw_crtc_supports_ips(crtc) &&
5524 pipe_config->pipe_bpp <= 24;
5527 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5528 struct intel_crtc_state *pipe_config)
5530 struct drm_device *dev = crtc->base.dev;
5531 struct drm_i915_private *dev_priv = dev->dev_private;
5532 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5534 /* FIXME should check pixel clock limits on all platforms */
5535 if (INTEL_INFO(dev)->gen < 4) {
5537 dev_priv->display.get_display_clock_speed(dev);
5540 * Enable pixel doubling when the dot clock
5541 * is > 90% of the (display) core speed.
5543 * GDG double wide on either pipe,
5544 * otherwise pipe A only.
5546 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5547 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5549 pipe_config->double_wide = true;
5552 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5557 * Pipe horizontal size must be even in:
5559 * - LVDS dual channel mode
5560 * - Double wide pipe
5562 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5563 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5564 pipe_config->pipe_src_w &= ~1;
5566 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5567 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5569 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5570 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5573 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5574 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5575 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5576 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5578 pipe_config->pipe_bpp = 8*3;
5582 hsw_compute_ips_config(crtc, pipe_config);
5584 if (pipe_config->has_pch_encoder)
5585 return ironlake_fdi_compute_config(crtc, pipe_config);
5590 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5592 struct drm_i915_private *dev_priv = dev->dev_private;
5596 /* FIXME: Punit isn't quite ready yet */
5597 if (IS_CHERRYVIEW(dev))
5600 if (dev_priv->hpll_freq == 0)
5601 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5603 mutex_lock(&dev_priv->dpio_lock);
5604 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5605 mutex_unlock(&dev_priv->dpio_lock);
5607 divider = val & DISPLAY_FREQUENCY_VALUES;
5609 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5610 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5611 "cdclk change in progress\n");
5613 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5616 static int i945_get_display_clock_speed(struct drm_device *dev)
5621 static int i915_get_display_clock_speed(struct drm_device *dev)
5626 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5631 static int pnv_get_display_clock_speed(struct drm_device *dev)
5635 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5637 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5638 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5640 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5642 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5644 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5647 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5648 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5650 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5655 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5659 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5661 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5664 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5665 case GC_DISPLAY_CLOCK_333_MHZ:
5668 case GC_DISPLAY_CLOCK_190_200_MHZ:
5674 static int i865_get_display_clock_speed(struct drm_device *dev)
5679 static int i855_get_display_clock_speed(struct drm_device *dev)
5682 /* Assume that the hardware is in the high speed state. This
5683 * should be the default.
5685 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5686 case GC_CLOCK_133_200:
5687 case GC_CLOCK_100_200:
5689 case GC_CLOCK_166_250:
5691 case GC_CLOCK_100_133:
5695 /* Shouldn't happen */
5699 static int i830_get_display_clock_speed(struct drm_device *dev)
5705 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5707 while (*num > DATA_LINK_M_N_MASK ||
5708 *den > DATA_LINK_M_N_MASK) {
5714 static void compute_m_n(unsigned int m, unsigned int n,
5715 uint32_t *ret_m, uint32_t *ret_n)
5717 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5718 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5719 intel_reduce_m_n_ratio(ret_m, ret_n);
5723 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5724 int pixel_clock, int link_clock,
5725 struct intel_link_m_n *m_n)
5729 compute_m_n(bits_per_pixel * pixel_clock,
5730 link_clock * nlanes * 8,
5731 &m_n->gmch_m, &m_n->gmch_n);
5733 compute_m_n(pixel_clock, link_clock,
5734 &m_n->link_m, &m_n->link_n);
5737 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5739 if (i915.panel_use_ssc >= 0)
5740 return i915.panel_use_ssc != 0;
5741 return dev_priv->vbt.lvds_use_ssc
5742 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5745 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5747 struct drm_device *dev = crtc->base.dev;
5748 struct drm_i915_private *dev_priv = dev->dev_private;
5751 if (IS_VALLEYVIEW(dev)) {
5753 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5754 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5755 refclk = dev_priv->vbt.lvds_ssc_freq;
5756 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5757 } else if (!IS_GEN2(dev)) {
5766 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5768 return (1 << dpll->n) << 16 | dpll->m2;
5771 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5773 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5776 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5777 struct intel_crtc_state *crtc_state,
5778 intel_clock_t *reduced_clock)
5780 struct drm_device *dev = crtc->base.dev;
5783 if (IS_PINEVIEW(dev)) {
5784 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5786 fp2 = pnv_dpll_compute_fp(reduced_clock);
5788 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5790 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5793 crtc_state->dpll_hw_state.fp0 = fp;
5795 crtc->lowfreq_avail = false;
5796 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5797 reduced_clock && i915.powersave) {
5798 crtc_state->dpll_hw_state.fp1 = fp2;
5799 crtc->lowfreq_avail = true;
5801 crtc_state->dpll_hw_state.fp1 = fp;
5805 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5811 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5812 * and set it to a reasonable value instead.
5814 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5815 reg_val &= 0xffffff00;
5816 reg_val |= 0x00000030;
5817 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5819 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5820 reg_val &= 0x8cffffff;
5821 reg_val = 0x8c000000;
5822 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5824 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5825 reg_val &= 0xffffff00;
5826 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5828 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5829 reg_val &= 0x00ffffff;
5830 reg_val |= 0xb0000000;
5831 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5834 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5835 struct intel_link_m_n *m_n)
5837 struct drm_device *dev = crtc->base.dev;
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5839 int pipe = crtc->pipe;
5841 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5842 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5843 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5844 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5847 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5848 struct intel_link_m_n *m_n,
5849 struct intel_link_m_n *m2_n2)
5851 struct drm_device *dev = crtc->base.dev;
5852 struct drm_i915_private *dev_priv = dev->dev_private;
5853 int pipe = crtc->pipe;
5854 enum transcoder transcoder = crtc->config->cpu_transcoder;
5856 if (INTEL_INFO(dev)->gen >= 5) {
5857 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5858 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5859 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5860 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5861 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5862 * for gen < 8) and if DRRS is supported (to make sure the
5863 * registers are not unnecessarily accessed).
5865 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5866 crtc->config->has_drrs) {
5867 I915_WRITE(PIPE_DATA_M2(transcoder),
5868 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5869 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5870 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5871 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5874 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5875 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5876 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5877 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5881 void intel_dp_set_m_n(struct intel_crtc *crtc)
5883 if (crtc->config->has_pch_encoder)
5884 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5886 intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
5887 &crtc->config->dp_m2_n2);
5890 static void vlv_update_pll(struct intel_crtc *crtc,
5891 struct intel_crtc_state *pipe_config)
5896 * Enable DPIO clock input. We should never disable the reference
5897 * clock for pipe B, since VGA hotplug / manual detection depends
5900 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5901 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5902 /* We should never disable this, set it here for state tracking */
5903 if (crtc->pipe == PIPE_B)
5904 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5905 dpll |= DPLL_VCO_ENABLE;
5906 pipe_config->dpll_hw_state.dpll = dpll;
5908 dpll_md = (pipe_config->pixel_multiplier - 1)
5909 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5910 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5913 static void vlv_prepare_pll(struct intel_crtc *crtc,
5914 const struct intel_crtc_state *pipe_config)
5916 struct drm_device *dev = crtc->base.dev;
5917 struct drm_i915_private *dev_priv = dev->dev_private;
5918 int pipe = crtc->pipe;
5920 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5921 u32 coreclk, reg_val;
5923 mutex_lock(&dev_priv->dpio_lock);
5925 bestn = pipe_config->dpll.n;
5926 bestm1 = pipe_config->dpll.m1;
5927 bestm2 = pipe_config->dpll.m2;
5928 bestp1 = pipe_config->dpll.p1;
5929 bestp2 = pipe_config->dpll.p2;
5931 /* See eDP HDMI DPIO driver vbios notes doc */
5933 /* PLL B needs special handling */
5935 vlv_pllb_recal_opamp(dev_priv, pipe);
5937 /* Set up Tx target for periodic Rcomp update */
5938 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5940 /* Disable target IRef on PLL */
5941 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5942 reg_val &= 0x00ffffff;
5943 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5945 /* Disable fast lock */
5946 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5948 /* Set idtafcrecal before PLL is enabled */
5949 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5950 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5951 mdiv |= ((bestn << DPIO_N_SHIFT));
5952 mdiv |= (1 << DPIO_K_SHIFT);
5955 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5956 * but we don't support that).
5957 * Note: don't use the DAC post divider as it seems unstable.
5959 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5960 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5962 mdiv |= DPIO_ENABLE_CALIBRATION;
5963 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5965 /* Set HBR and RBR LPF coefficients */
5966 if (pipe_config->port_clock == 162000 ||
5967 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5968 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5969 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5972 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5975 if (pipe_config->has_dp_encoder) {
5976 /* Use SSC source */
5978 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5981 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5983 } else { /* HDMI or VGA */
5984 /* Use bend source */
5986 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5989 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5993 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5994 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5995 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5996 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5997 coreclk |= 0x01000000;
5998 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6000 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6001 mutex_unlock(&dev_priv->dpio_lock);
6004 static void chv_update_pll(struct intel_crtc *crtc,
6005 struct intel_crtc_state *pipe_config)
6007 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6008 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6010 if (crtc->pipe != PIPE_A)
6011 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6013 pipe_config->dpll_hw_state.dpll_md =
6014 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6017 static void chv_prepare_pll(struct intel_crtc *crtc,
6018 const struct intel_crtc_state *pipe_config)
6020 struct drm_device *dev = crtc->base.dev;
6021 struct drm_i915_private *dev_priv = dev->dev_private;
6022 int pipe = crtc->pipe;
6023 int dpll_reg = DPLL(crtc->pipe);
6024 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6025 u32 loopfilter, intcoeff;
6026 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6029 bestn = pipe_config->dpll.n;
6030 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6031 bestm1 = pipe_config->dpll.m1;
6032 bestm2 = pipe_config->dpll.m2 >> 22;
6033 bestp1 = pipe_config->dpll.p1;
6034 bestp2 = pipe_config->dpll.p2;
6037 * Enable Refclk and SSC
6039 I915_WRITE(dpll_reg,
6040 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6042 mutex_lock(&dev_priv->dpio_lock);
6044 /* p1 and p2 divider */
6045 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6046 5 << DPIO_CHV_S1_DIV_SHIFT |
6047 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6048 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6049 1 << DPIO_CHV_K_DIV_SHIFT);
6051 /* Feedback post-divider - m2 */
6052 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6054 /* Feedback refclk divider - n and m1 */
6055 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6056 DPIO_CHV_M1_DIV_BY_2 |
6057 1 << DPIO_CHV_N_DIV_SHIFT);
6059 /* M2 fraction division */
6060 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6062 /* M2 fraction division enable */
6063 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6064 DPIO_CHV_FRAC_DIV_EN |
6065 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6068 refclk = i9xx_get_refclk(crtc, 0);
6069 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6070 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6071 if (refclk == 100000)
6073 else if (refclk == 38400)
6077 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6078 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6081 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6082 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6085 mutex_unlock(&dev_priv->dpio_lock);
6089 * vlv_force_pll_on - forcibly enable just the PLL
6090 * @dev_priv: i915 private structure
6091 * @pipe: pipe PLL to enable
6092 * @dpll: PLL configuration
6094 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6095 * in cases where we need the PLL enabled even when @pipe is not going to
6098 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6099 const struct dpll *dpll)
6101 struct intel_crtc *crtc =
6102 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6103 struct intel_crtc_state pipe_config = {
6104 .pixel_multiplier = 1,
6108 if (IS_CHERRYVIEW(dev)) {
6109 chv_update_pll(crtc, &pipe_config);
6110 chv_prepare_pll(crtc, &pipe_config);
6111 chv_enable_pll(crtc, &pipe_config);
6113 vlv_update_pll(crtc, &pipe_config);
6114 vlv_prepare_pll(crtc, &pipe_config);
6115 vlv_enable_pll(crtc, &pipe_config);
6120 * vlv_force_pll_off - forcibly disable just the PLL
6121 * @dev_priv: i915 private structure
6122 * @pipe: pipe PLL to disable
6124 * Disable the PLL for @pipe. To be used in cases where we need
6125 * the PLL enabled even when @pipe is not going to be enabled.
6127 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6129 if (IS_CHERRYVIEW(dev))
6130 chv_disable_pll(to_i915(dev), pipe);
6132 vlv_disable_pll(to_i915(dev), pipe);
6135 static void i9xx_update_pll(struct intel_crtc *crtc,
6136 struct intel_crtc_state *crtc_state,
6137 intel_clock_t *reduced_clock,
6140 struct drm_device *dev = crtc->base.dev;
6141 struct drm_i915_private *dev_priv = dev->dev_private;
6144 struct dpll *clock = &crtc_state->dpll;
6146 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6148 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6149 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6151 dpll = DPLL_VGA_MODE_DIS;
6153 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6154 dpll |= DPLLB_MODE_LVDS;
6156 dpll |= DPLLB_MODE_DAC_SERIAL;
6158 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6159 dpll |= (crtc_state->pixel_multiplier - 1)
6160 << SDVO_MULTIPLIER_SHIFT_HIRES;
6164 dpll |= DPLL_SDVO_HIGH_SPEED;
6166 if (crtc_state->has_dp_encoder)
6167 dpll |= DPLL_SDVO_HIGH_SPEED;
6169 /* compute bitmask from p1 value */
6170 if (IS_PINEVIEW(dev))
6171 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6173 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6174 if (IS_G4X(dev) && reduced_clock)
6175 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6177 switch (clock->p2) {
6179 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6182 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6185 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6188 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6191 if (INTEL_INFO(dev)->gen >= 4)
6192 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6194 if (crtc_state->sdvo_tv_clock)
6195 dpll |= PLL_REF_INPUT_TVCLKINBC;
6196 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6197 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6198 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6200 dpll |= PLL_REF_INPUT_DREFCLK;
6202 dpll |= DPLL_VCO_ENABLE;
6203 crtc_state->dpll_hw_state.dpll = dpll;
6205 if (INTEL_INFO(dev)->gen >= 4) {
6206 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6207 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6208 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6212 static void i8xx_update_pll(struct intel_crtc *crtc,
6213 struct intel_crtc_state *crtc_state,
6214 intel_clock_t *reduced_clock,
6217 struct drm_device *dev = crtc->base.dev;
6218 struct drm_i915_private *dev_priv = dev->dev_private;
6220 struct dpll *clock = &crtc_state->dpll;
6222 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6224 dpll = DPLL_VGA_MODE_DIS;
6226 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6227 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6230 dpll |= PLL_P1_DIVIDE_BY_TWO;
6232 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6234 dpll |= PLL_P2_DIVIDE_BY_4;
6237 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6238 dpll |= DPLL_DVO_2X_MODE;
6240 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6241 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6242 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6244 dpll |= PLL_REF_INPUT_DREFCLK;
6246 dpll |= DPLL_VCO_ENABLE;
6247 crtc_state->dpll_hw_state.dpll = dpll;
6250 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6252 struct drm_device *dev = intel_crtc->base.dev;
6253 struct drm_i915_private *dev_priv = dev->dev_private;
6254 enum pipe pipe = intel_crtc->pipe;
6255 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6256 struct drm_display_mode *adjusted_mode =
6257 &intel_crtc->config->base.adjusted_mode;
6258 uint32_t crtc_vtotal, crtc_vblank_end;
6261 /* We need to be careful not to changed the adjusted mode, for otherwise
6262 * the hw state checker will get angry at the mismatch. */
6263 crtc_vtotal = adjusted_mode->crtc_vtotal;
6264 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6266 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6267 /* the chip adds 2 halflines automatically */
6269 crtc_vblank_end -= 1;
6271 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6272 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6274 vsyncshift = adjusted_mode->crtc_hsync_start -
6275 adjusted_mode->crtc_htotal / 2;
6277 vsyncshift += adjusted_mode->crtc_htotal;
6280 if (INTEL_INFO(dev)->gen > 3)
6281 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6283 I915_WRITE(HTOTAL(cpu_transcoder),
6284 (adjusted_mode->crtc_hdisplay - 1) |
6285 ((adjusted_mode->crtc_htotal - 1) << 16));
6286 I915_WRITE(HBLANK(cpu_transcoder),
6287 (adjusted_mode->crtc_hblank_start - 1) |
6288 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6289 I915_WRITE(HSYNC(cpu_transcoder),
6290 (adjusted_mode->crtc_hsync_start - 1) |
6291 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6293 I915_WRITE(VTOTAL(cpu_transcoder),
6294 (adjusted_mode->crtc_vdisplay - 1) |
6295 ((crtc_vtotal - 1) << 16));
6296 I915_WRITE(VBLANK(cpu_transcoder),
6297 (adjusted_mode->crtc_vblank_start - 1) |
6298 ((crtc_vblank_end - 1) << 16));
6299 I915_WRITE(VSYNC(cpu_transcoder),
6300 (adjusted_mode->crtc_vsync_start - 1) |
6301 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6303 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6304 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6305 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6307 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6308 (pipe == PIPE_B || pipe == PIPE_C))
6309 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6311 /* pipesrc controls the size that is scaled from, which should
6312 * always be the user's requested size.
6314 I915_WRITE(PIPESRC(pipe),
6315 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6316 (intel_crtc->config->pipe_src_h - 1));
6319 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6320 struct intel_crtc_state *pipe_config)
6322 struct drm_device *dev = crtc->base.dev;
6323 struct drm_i915_private *dev_priv = dev->dev_private;
6324 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6327 tmp = I915_READ(HTOTAL(cpu_transcoder));
6328 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6329 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6330 tmp = I915_READ(HBLANK(cpu_transcoder));
6331 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6332 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6333 tmp = I915_READ(HSYNC(cpu_transcoder));
6334 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6335 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6337 tmp = I915_READ(VTOTAL(cpu_transcoder));
6338 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6339 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6340 tmp = I915_READ(VBLANK(cpu_transcoder));
6341 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6342 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6343 tmp = I915_READ(VSYNC(cpu_transcoder));
6344 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6345 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6347 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6348 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6349 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6350 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6353 tmp = I915_READ(PIPESRC(crtc->pipe));
6354 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6355 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6357 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6358 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6361 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6362 struct intel_crtc_state *pipe_config)
6364 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6365 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6366 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6367 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6369 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6370 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6371 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6372 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6374 mode->flags = pipe_config->base.adjusted_mode.flags;
6376 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6377 mode->flags |= pipe_config->base.adjusted_mode.flags;
6380 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6382 struct drm_device *dev = intel_crtc->base.dev;
6383 struct drm_i915_private *dev_priv = dev->dev_private;
6388 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6389 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6390 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6392 if (intel_crtc->config->double_wide)
6393 pipeconf |= PIPECONF_DOUBLE_WIDE;
6395 /* only g4x and later have fancy bpc/dither controls */
6396 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6397 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6398 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6399 pipeconf |= PIPECONF_DITHER_EN |
6400 PIPECONF_DITHER_TYPE_SP;
6402 switch (intel_crtc->config->pipe_bpp) {
6404 pipeconf |= PIPECONF_6BPC;
6407 pipeconf |= PIPECONF_8BPC;
6410 pipeconf |= PIPECONF_10BPC;
6413 /* Case prevented by intel_choose_pipe_bpp_dither. */
6418 if (HAS_PIPE_CXSR(dev)) {
6419 if (intel_crtc->lowfreq_avail) {
6420 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6421 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6423 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6427 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6428 if (INTEL_INFO(dev)->gen < 4 ||
6429 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6430 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6432 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6434 pipeconf |= PIPECONF_PROGRESSIVE;
6436 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6437 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6439 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6440 POSTING_READ(PIPECONF(intel_crtc->pipe));
6443 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6444 struct intel_crtc_state *crtc_state)
6446 struct drm_device *dev = crtc->base.dev;
6447 struct drm_i915_private *dev_priv = dev->dev_private;
6448 int refclk, num_connectors = 0;
6449 intel_clock_t clock, reduced_clock;
6450 bool ok, has_reduced_clock = false;
6451 bool is_lvds = false, is_dsi = false;
6452 struct intel_encoder *encoder;
6453 const intel_limit_t *limit;
6455 for_each_intel_encoder(dev, encoder) {
6456 if (encoder->new_crtc != crtc)
6459 switch (encoder->type) {
6460 case INTEL_OUTPUT_LVDS:
6463 case INTEL_OUTPUT_DSI:
6476 if (!crtc_state->clock_set) {
6477 refclk = i9xx_get_refclk(crtc, num_connectors);
6480 * Returns a set of divisors for the desired target clock with
6481 * the given refclk, or FALSE. The returned values represent
6482 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6485 limit = intel_limit(crtc, refclk);
6486 ok = dev_priv->display.find_dpll(limit, crtc,
6487 crtc_state->port_clock,
6488 refclk, NULL, &clock);
6490 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6494 if (is_lvds && dev_priv->lvds_downclock_avail) {
6496 * Ensure we match the reduced clock's P to the target
6497 * clock. If the clocks don't match, we can't switch
6498 * the display clock by using the FP0/FP1. In such case
6499 * we will disable the LVDS downclock feature.
6502 dev_priv->display.find_dpll(limit, crtc,
6503 dev_priv->lvds_downclock,
6507 /* Compat-code for transition, will disappear. */
6508 crtc_state->dpll.n = clock.n;
6509 crtc_state->dpll.m1 = clock.m1;
6510 crtc_state->dpll.m2 = clock.m2;
6511 crtc_state->dpll.p1 = clock.p1;
6512 crtc_state->dpll.p2 = clock.p2;
6516 i8xx_update_pll(crtc, crtc_state,
6517 has_reduced_clock ? &reduced_clock : NULL,
6519 } else if (IS_CHERRYVIEW(dev)) {
6520 chv_update_pll(crtc, crtc_state);
6521 } else if (IS_VALLEYVIEW(dev)) {
6522 vlv_update_pll(crtc, crtc_state);
6524 i9xx_update_pll(crtc, crtc_state,
6525 has_reduced_clock ? &reduced_clock : NULL,
6532 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6533 struct intel_crtc_state *pipe_config)
6535 struct drm_device *dev = crtc->base.dev;
6536 struct drm_i915_private *dev_priv = dev->dev_private;
6539 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6542 tmp = I915_READ(PFIT_CONTROL);
6543 if (!(tmp & PFIT_ENABLE))
6546 /* Check whether the pfit is attached to our pipe. */
6547 if (INTEL_INFO(dev)->gen < 4) {
6548 if (crtc->pipe != PIPE_B)
6551 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6555 pipe_config->gmch_pfit.control = tmp;
6556 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6557 if (INTEL_INFO(dev)->gen < 5)
6558 pipe_config->gmch_pfit.lvds_border_bits =
6559 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6562 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6563 struct intel_crtc_state *pipe_config)
6565 struct drm_device *dev = crtc->base.dev;
6566 struct drm_i915_private *dev_priv = dev->dev_private;
6567 int pipe = pipe_config->cpu_transcoder;
6568 intel_clock_t clock;
6570 int refclk = 100000;
6572 /* In case of MIPI DPLL will not even be used */
6573 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6576 mutex_lock(&dev_priv->dpio_lock);
6577 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6578 mutex_unlock(&dev_priv->dpio_lock);
6580 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6581 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6582 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6583 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6584 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6586 vlv_clock(refclk, &clock);
6588 /* clock.dot is the fast clock */
6589 pipe_config->port_clock = clock.dot / 5;
6593 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6594 struct intel_initial_plane_config *plane_config)
6596 struct drm_device *dev = crtc->base.dev;
6597 struct drm_i915_private *dev_priv = dev->dev_private;
6598 u32 val, base, offset;
6599 int pipe = crtc->pipe, plane = crtc->plane;
6600 int fourcc, pixel_format;
6602 struct drm_framebuffer *fb;
6603 struct intel_framebuffer *intel_fb;
6605 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6607 DRM_DEBUG_KMS("failed to alloc fb\n");
6611 fb = &intel_fb->base;
6613 val = I915_READ(DSPCNTR(plane));
6615 if (INTEL_INFO(dev)->gen >= 4)
6616 if (val & DISPPLANE_TILED)
6617 plane_config->tiling = I915_TILING_X;
6619 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6620 fourcc = i9xx_format_to_fourcc(pixel_format);
6621 fb->pixel_format = fourcc;
6622 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6624 if (INTEL_INFO(dev)->gen >= 4) {
6625 if (plane_config->tiling)
6626 offset = I915_READ(DSPTILEOFF(plane));
6628 offset = I915_READ(DSPLINOFF(plane));
6629 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6631 base = I915_READ(DSPADDR(plane));
6633 plane_config->base = base;
6635 val = I915_READ(PIPESRC(pipe));
6636 fb->width = ((val >> 16) & 0xfff) + 1;
6637 fb->height = ((val >> 0) & 0xfff) + 1;
6639 val = I915_READ(DSPSTRIDE(pipe));
6640 fb->pitches[0] = val & 0xffffffc0;
6642 aligned_height = intel_fb_align_height(dev, fb->height,
6643 plane_config->tiling);
6645 plane_config->size = fb->pitches[0] * aligned_height;
6647 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6648 pipe_name(pipe), plane, fb->width, fb->height,
6649 fb->bits_per_pixel, base, fb->pitches[0],
6650 plane_config->size);
6652 crtc->base.primary->fb = fb;
6655 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6656 struct intel_crtc_state *pipe_config)
6658 struct drm_device *dev = crtc->base.dev;
6659 struct drm_i915_private *dev_priv = dev->dev_private;
6660 int pipe = pipe_config->cpu_transcoder;
6661 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6662 intel_clock_t clock;
6663 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6664 int refclk = 100000;
6666 mutex_lock(&dev_priv->dpio_lock);
6667 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6668 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6669 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6670 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6671 mutex_unlock(&dev_priv->dpio_lock);
6673 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6674 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6675 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6676 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6677 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6679 chv_clock(refclk, &clock);
6681 /* clock.dot is the fast clock */
6682 pipe_config->port_clock = clock.dot / 5;
6685 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6686 struct intel_crtc_state *pipe_config)
6688 struct drm_device *dev = crtc->base.dev;
6689 struct drm_i915_private *dev_priv = dev->dev_private;
6692 if (!intel_display_power_is_enabled(dev_priv,
6693 POWER_DOMAIN_PIPE(crtc->pipe)))
6696 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6697 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6699 tmp = I915_READ(PIPECONF(crtc->pipe));
6700 if (!(tmp & PIPECONF_ENABLE))
6703 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6704 switch (tmp & PIPECONF_BPC_MASK) {
6706 pipe_config->pipe_bpp = 18;
6709 pipe_config->pipe_bpp = 24;
6711 case PIPECONF_10BPC:
6712 pipe_config->pipe_bpp = 30;
6719 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6720 pipe_config->limited_color_range = true;
6722 if (INTEL_INFO(dev)->gen < 4)
6723 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6725 intel_get_pipe_timings(crtc, pipe_config);
6727 i9xx_get_pfit_config(crtc, pipe_config);
6729 if (INTEL_INFO(dev)->gen >= 4) {
6730 tmp = I915_READ(DPLL_MD(crtc->pipe));
6731 pipe_config->pixel_multiplier =
6732 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6733 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6734 pipe_config->dpll_hw_state.dpll_md = tmp;
6735 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6736 tmp = I915_READ(DPLL(crtc->pipe));
6737 pipe_config->pixel_multiplier =
6738 ((tmp & SDVO_MULTIPLIER_MASK)
6739 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6741 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6742 * port and will be fixed up in the encoder->get_config
6744 pipe_config->pixel_multiplier = 1;
6746 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6747 if (!IS_VALLEYVIEW(dev)) {
6749 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6750 * on 830. Filter it out here so that we don't
6751 * report errors due to that.
6754 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6756 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6757 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6759 /* Mask out read-only status bits. */
6760 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6761 DPLL_PORTC_READY_MASK |
6762 DPLL_PORTB_READY_MASK);
6765 if (IS_CHERRYVIEW(dev))
6766 chv_crtc_clock_get(crtc, pipe_config);
6767 else if (IS_VALLEYVIEW(dev))
6768 vlv_crtc_clock_get(crtc, pipe_config);
6770 i9xx_crtc_clock_get(crtc, pipe_config);
6775 static void ironlake_init_pch_refclk(struct drm_device *dev)
6777 struct drm_i915_private *dev_priv = dev->dev_private;
6778 struct intel_encoder *encoder;
6780 bool has_lvds = false;
6781 bool has_cpu_edp = false;
6782 bool has_panel = false;
6783 bool has_ck505 = false;
6784 bool can_ssc = false;
6786 /* We need to take the global config into account */
6787 for_each_intel_encoder(dev, encoder) {
6788 switch (encoder->type) {
6789 case INTEL_OUTPUT_LVDS:
6793 case INTEL_OUTPUT_EDP:
6795 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6803 if (HAS_PCH_IBX(dev)) {
6804 has_ck505 = dev_priv->vbt.display_clock_mode;
6805 can_ssc = has_ck505;
6811 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6812 has_panel, has_lvds, has_ck505);
6814 /* Ironlake: try to setup display ref clock before DPLL
6815 * enabling. This is only under driver's control after
6816 * PCH B stepping, previous chipset stepping should be
6817 * ignoring this setting.
6819 val = I915_READ(PCH_DREF_CONTROL);
6821 /* As we must carefully and slowly disable/enable each source in turn,
6822 * compute the final state we want first and check if we need to
6823 * make any changes at all.
6826 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6828 final |= DREF_NONSPREAD_CK505_ENABLE;
6830 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6832 final &= ~DREF_SSC_SOURCE_MASK;
6833 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6834 final &= ~DREF_SSC1_ENABLE;
6837 final |= DREF_SSC_SOURCE_ENABLE;
6839 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6840 final |= DREF_SSC1_ENABLE;
6843 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6844 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6846 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6848 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6850 final |= DREF_SSC_SOURCE_DISABLE;
6851 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6857 /* Always enable nonspread source */
6858 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6861 val |= DREF_NONSPREAD_CK505_ENABLE;
6863 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6866 val &= ~DREF_SSC_SOURCE_MASK;
6867 val |= DREF_SSC_SOURCE_ENABLE;
6869 /* SSC must be turned on before enabling the CPU output */
6870 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6871 DRM_DEBUG_KMS("Using SSC on panel\n");
6872 val |= DREF_SSC1_ENABLE;
6874 val &= ~DREF_SSC1_ENABLE;
6876 /* Get SSC going before enabling the outputs */
6877 I915_WRITE(PCH_DREF_CONTROL, val);
6878 POSTING_READ(PCH_DREF_CONTROL);
6881 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6883 /* Enable CPU source on CPU attached eDP */
6885 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6886 DRM_DEBUG_KMS("Using SSC on eDP\n");
6887 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6889 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6891 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6893 I915_WRITE(PCH_DREF_CONTROL, val);
6894 POSTING_READ(PCH_DREF_CONTROL);
6897 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6899 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6901 /* Turn off CPU output */
6902 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6904 I915_WRITE(PCH_DREF_CONTROL, val);
6905 POSTING_READ(PCH_DREF_CONTROL);
6908 /* Turn off the SSC source */
6909 val &= ~DREF_SSC_SOURCE_MASK;
6910 val |= DREF_SSC_SOURCE_DISABLE;
6913 val &= ~DREF_SSC1_ENABLE;
6915 I915_WRITE(PCH_DREF_CONTROL, val);
6916 POSTING_READ(PCH_DREF_CONTROL);
6920 BUG_ON(val != final);
6923 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6927 tmp = I915_READ(SOUTH_CHICKEN2);
6928 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6929 I915_WRITE(SOUTH_CHICKEN2, tmp);
6931 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6932 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6933 DRM_ERROR("FDI mPHY reset assert timeout\n");
6935 tmp = I915_READ(SOUTH_CHICKEN2);
6936 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6937 I915_WRITE(SOUTH_CHICKEN2, tmp);
6939 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6940 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6941 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6944 /* WaMPhyProgramming:hsw */
6945 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6949 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6950 tmp &= ~(0xFF << 24);
6951 tmp |= (0x12 << 24);
6952 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6954 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6956 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6958 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6960 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6962 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6963 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6964 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6966 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6967 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6968 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6970 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6973 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6975 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6978 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6980 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6983 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6985 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6988 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6990 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6991 tmp &= ~(0xFF << 16);
6992 tmp |= (0x1C << 16);
6993 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6995 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6996 tmp &= ~(0xFF << 16);
6997 tmp |= (0x1C << 16);
6998 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7000 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7002 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7004 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7006 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7008 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7009 tmp &= ~(0xF << 28);
7011 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7013 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7014 tmp &= ~(0xF << 28);
7016 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7019 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7020 * Programming" based on the parameters passed:
7021 * - Sequence to enable CLKOUT_DP
7022 * - Sequence to enable CLKOUT_DP without spread
7023 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7025 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7028 struct drm_i915_private *dev_priv = dev->dev_private;
7031 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7033 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7034 with_fdi, "LP PCH doesn't have FDI\n"))
7037 mutex_lock(&dev_priv->dpio_lock);
7039 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7040 tmp &= ~SBI_SSCCTL_DISABLE;
7041 tmp |= SBI_SSCCTL_PATHALT;
7042 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7047 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7048 tmp &= ~SBI_SSCCTL_PATHALT;
7049 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7052 lpt_reset_fdi_mphy(dev_priv);
7053 lpt_program_fdi_mphy(dev_priv);
7057 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7058 SBI_GEN0 : SBI_DBUFF0;
7059 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7060 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7061 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7063 mutex_unlock(&dev_priv->dpio_lock);
7066 /* Sequence to disable CLKOUT_DP */
7067 static void lpt_disable_clkout_dp(struct drm_device *dev)
7069 struct drm_i915_private *dev_priv = dev->dev_private;
7072 mutex_lock(&dev_priv->dpio_lock);
7074 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7075 SBI_GEN0 : SBI_DBUFF0;
7076 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7077 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7078 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7080 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7081 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7082 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7083 tmp |= SBI_SSCCTL_PATHALT;
7084 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7087 tmp |= SBI_SSCCTL_DISABLE;
7088 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7091 mutex_unlock(&dev_priv->dpio_lock);
7094 static void lpt_init_pch_refclk(struct drm_device *dev)
7096 struct intel_encoder *encoder;
7097 bool has_vga = false;
7099 for_each_intel_encoder(dev, encoder) {
7100 switch (encoder->type) {
7101 case INTEL_OUTPUT_ANALOG:
7110 lpt_enable_clkout_dp(dev, true, true);
7112 lpt_disable_clkout_dp(dev);
7116 * Initialize reference clocks when the driver loads
7118 void intel_init_pch_refclk(struct drm_device *dev)
7120 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7121 ironlake_init_pch_refclk(dev);
7122 else if (HAS_PCH_LPT(dev))
7123 lpt_init_pch_refclk(dev);
7126 static int ironlake_get_refclk(struct drm_crtc *crtc)
7128 struct drm_device *dev = crtc->dev;
7129 struct drm_i915_private *dev_priv = dev->dev_private;
7130 struct intel_encoder *encoder;
7131 int num_connectors = 0;
7132 bool is_lvds = false;
7134 for_each_intel_encoder(dev, encoder) {
7135 if (encoder->new_crtc != to_intel_crtc(crtc))
7138 switch (encoder->type) {
7139 case INTEL_OUTPUT_LVDS:
7148 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7149 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7150 dev_priv->vbt.lvds_ssc_freq);
7151 return dev_priv->vbt.lvds_ssc_freq;
7157 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7159 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7161 int pipe = intel_crtc->pipe;
7166 switch (intel_crtc->config->pipe_bpp) {
7168 val |= PIPECONF_6BPC;
7171 val |= PIPECONF_8BPC;
7174 val |= PIPECONF_10BPC;
7177 val |= PIPECONF_12BPC;
7180 /* Case prevented by intel_choose_pipe_bpp_dither. */
7184 if (intel_crtc->config->dither)
7185 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7187 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7188 val |= PIPECONF_INTERLACED_ILK;
7190 val |= PIPECONF_PROGRESSIVE;
7192 if (intel_crtc->config->limited_color_range)
7193 val |= PIPECONF_COLOR_RANGE_SELECT;
7195 I915_WRITE(PIPECONF(pipe), val);
7196 POSTING_READ(PIPECONF(pipe));
7200 * Set up the pipe CSC unit.
7202 * Currently only full range RGB to limited range RGB conversion
7203 * is supported, but eventually this should handle various
7204 * RGB<->YCbCr scenarios as well.
7206 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7208 struct drm_device *dev = crtc->dev;
7209 struct drm_i915_private *dev_priv = dev->dev_private;
7210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7211 int pipe = intel_crtc->pipe;
7212 uint16_t coeff = 0x7800; /* 1.0 */
7215 * TODO: Check what kind of values actually come out of the pipe
7216 * with these coeff/postoff values and adjust to get the best
7217 * accuracy. Perhaps we even need to take the bpc value into
7221 if (intel_crtc->config->limited_color_range)
7222 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7225 * GY/GU and RY/RU should be the other way around according
7226 * to BSpec, but reality doesn't agree. Just set them up in
7227 * a way that results in the correct picture.
7229 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7230 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7232 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7233 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7235 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7236 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7238 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7239 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7240 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7242 if (INTEL_INFO(dev)->gen > 6) {
7243 uint16_t postoff = 0;
7245 if (intel_crtc->config->limited_color_range)
7246 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7248 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7249 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7250 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7252 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7254 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7256 if (intel_crtc->config->limited_color_range)
7257 mode |= CSC_BLACK_SCREEN_OFFSET;
7259 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7263 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7265 struct drm_device *dev = crtc->dev;
7266 struct drm_i915_private *dev_priv = dev->dev_private;
7267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7268 enum pipe pipe = intel_crtc->pipe;
7269 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7274 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7275 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7277 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7278 val |= PIPECONF_INTERLACED_ILK;
7280 val |= PIPECONF_PROGRESSIVE;
7282 I915_WRITE(PIPECONF(cpu_transcoder), val);
7283 POSTING_READ(PIPECONF(cpu_transcoder));
7285 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7286 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7288 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7291 switch (intel_crtc->config->pipe_bpp) {
7293 val |= PIPEMISC_DITHER_6_BPC;
7296 val |= PIPEMISC_DITHER_8_BPC;
7299 val |= PIPEMISC_DITHER_10_BPC;
7302 val |= PIPEMISC_DITHER_12_BPC;
7305 /* Case prevented by pipe_config_set_bpp. */
7309 if (intel_crtc->config->dither)
7310 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7312 I915_WRITE(PIPEMISC(pipe), val);
7316 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7317 struct intel_crtc_state *crtc_state,
7318 intel_clock_t *clock,
7319 bool *has_reduced_clock,
7320 intel_clock_t *reduced_clock)
7322 struct drm_device *dev = crtc->dev;
7323 struct drm_i915_private *dev_priv = dev->dev_private;
7324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7326 const intel_limit_t *limit;
7327 bool ret, is_lvds = false;
7329 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7331 refclk = ironlake_get_refclk(crtc);
7334 * Returns a set of divisors for the desired target clock with the given
7335 * refclk, or FALSE. The returned values represent the clock equation:
7336 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7338 limit = intel_limit(intel_crtc, refclk);
7339 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7340 crtc_state->port_clock,
7341 refclk, NULL, clock);
7345 if (is_lvds && dev_priv->lvds_downclock_avail) {
7347 * Ensure we match the reduced clock's P to the target clock.
7348 * If the clocks don't match, we can't switch the display clock
7349 * by using the FP0/FP1. In such case we will disable the LVDS
7350 * downclock feature.
7352 *has_reduced_clock =
7353 dev_priv->display.find_dpll(limit, intel_crtc,
7354 dev_priv->lvds_downclock,
7362 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7365 * Account for spread spectrum to avoid
7366 * oversubscribing the link. Max center spread
7367 * is 2.5%; use 5% for safety's sake.
7369 u32 bps = target_clock * bpp * 21 / 20;
7370 return DIV_ROUND_UP(bps, link_bw * 8);
7373 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7375 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7378 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7379 struct intel_crtc_state *crtc_state,
7381 intel_clock_t *reduced_clock, u32 *fp2)
7383 struct drm_crtc *crtc = &intel_crtc->base;
7384 struct drm_device *dev = crtc->dev;
7385 struct drm_i915_private *dev_priv = dev->dev_private;
7386 struct intel_encoder *intel_encoder;
7388 int factor, num_connectors = 0;
7389 bool is_lvds = false, is_sdvo = false;
7391 for_each_intel_encoder(dev, intel_encoder) {
7392 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7395 switch (intel_encoder->type) {
7396 case INTEL_OUTPUT_LVDS:
7399 case INTEL_OUTPUT_SDVO:
7400 case INTEL_OUTPUT_HDMI:
7410 /* Enable autotuning of the PLL clock (if permissible) */
7413 if ((intel_panel_use_ssc(dev_priv) &&
7414 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7415 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7417 } else if (crtc_state->sdvo_tv_clock)
7420 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7423 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7429 dpll |= DPLLB_MODE_LVDS;
7431 dpll |= DPLLB_MODE_DAC_SERIAL;
7433 dpll |= (crtc_state->pixel_multiplier - 1)
7434 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7437 dpll |= DPLL_SDVO_HIGH_SPEED;
7438 if (crtc_state->has_dp_encoder)
7439 dpll |= DPLL_SDVO_HIGH_SPEED;
7441 /* compute bitmask from p1 value */
7442 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7444 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7446 switch (crtc_state->dpll.p2) {
7448 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7451 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7454 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7457 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7461 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7462 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7464 dpll |= PLL_REF_INPUT_DREFCLK;
7466 return dpll | DPLL_VCO_ENABLE;
7469 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7470 struct intel_crtc_state *crtc_state)
7472 struct drm_device *dev = crtc->base.dev;
7473 intel_clock_t clock, reduced_clock;
7474 u32 dpll = 0, fp = 0, fp2 = 0;
7475 bool ok, has_reduced_clock = false;
7476 bool is_lvds = false;
7477 struct intel_shared_dpll *pll;
7479 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7481 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7482 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7484 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7485 &has_reduced_clock, &reduced_clock);
7486 if (!ok && !crtc_state->clock_set) {
7487 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7490 /* Compat-code for transition, will disappear. */
7491 if (!crtc_state->clock_set) {
7492 crtc_state->dpll.n = clock.n;
7493 crtc_state->dpll.m1 = clock.m1;
7494 crtc_state->dpll.m2 = clock.m2;
7495 crtc_state->dpll.p1 = clock.p1;
7496 crtc_state->dpll.p2 = clock.p2;
7499 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7500 if (crtc_state->has_pch_encoder) {
7501 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7502 if (has_reduced_clock)
7503 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7505 dpll = ironlake_compute_dpll(crtc, crtc_state,
7506 &fp, &reduced_clock,
7507 has_reduced_clock ? &fp2 : NULL);
7509 crtc_state->dpll_hw_state.dpll = dpll;
7510 crtc_state->dpll_hw_state.fp0 = fp;
7511 if (has_reduced_clock)
7512 crtc_state->dpll_hw_state.fp1 = fp2;
7514 crtc_state->dpll_hw_state.fp1 = fp;
7516 pll = intel_get_shared_dpll(crtc, crtc_state);
7518 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7519 pipe_name(crtc->pipe));
7524 if (is_lvds && has_reduced_clock && i915.powersave)
7525 crtc->lowfreq_avail = true;
7527 crtc->lowfreq_avail = false;
7532 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7533 struct intel_link_m_n *m_n)
7535 struct drm_device *dev = crtc->base.dev;
7536 struct drm_i915_private *dev_priv = dev->dev_private;
7537 enum pipe pipe = crtc->pipe;
7539 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7540 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7541 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7543 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7544 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7545 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7548 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7549 enum transcoder transcoder,
7550 struct intel_link_m_n *m_n,
7551 struct intel_link_m_n *m2_n2)
7553 struct drm_device *dev = crtc->base.dev;
7554 struct drm_i915_private *dev_priv = dev->dev_private;
7555 enum pipe pipe = crtc->pipe;
7557 if (INTEL_INFO(dev)->gen >= 5) {
7558 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7559 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7560 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7562 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7563 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7564 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7565 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7566 * gen < 8) and if DRRS is supported (to make sure the
7567 * registers are not unnecessarily read).
7569 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7570 crtc->config->has_drrs) {
7571 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7572 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7573 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7575 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7576 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7577 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7580 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7581 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7582 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7584 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7585 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7586 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7590 void intel_dp_get_m_n(struct intel_crtc *crtc,
7591 struct intel_crtc_state *pipe_config)
7593 if (pipe_config->has_pch_encoder)
7594 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7596 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7597 &pipe_config->dp_m_n,
7598 &pipe_config->dp_m2_n2);
7601 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7602 struct intel_crtc_state *pipe_config)
7604 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7605 &pipe_config->fdi_m_n, NULL);
7608 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7609 struct intel_crtc_state *pipe_config)
7611 struct drm_device *dev = crtc->base.dev;
7612 struct drm_i915_private *dev_priv = dev->dev_private;
7615 tmp = I915_READ(PS_CTL(crtc->pipe));
7617 if (tmp & PS_ENABLE) {
7618 pipe_config->pch_pfit.enabled = true;
7619 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7620 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7625 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7626 struct intel_initial_plane_config *plane_config)
7628 struct drm_device *dev = crtc->base.dev;
7629 struct drm_i915_private *dev_priv = dev->dev_private;
7630 u32 val, base, offset, stride_mult;
7631 int pipe = crtc->pipe;
7632 int fourcc, pixel_format;
7634 struct drm_framebuffer *fb;
7635 struct intel_framebuffer *intel_fb;
7637 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7639 DRM_DEBUG_KMS("failed to alloc fb\n");
7643 fb = &intel_fb->base;
7645 val = I915_READ(PLANE_CTL(pipe, 0));
7646 if (val & PLANE_CTL_TILED_MASK)
7647 plane_config->tiling = I915_TILING_X;
7649 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7650 fourcc = skl_format_to_fourcc(pixel_format,
7651 val & PLANE_CTL_ORDER_RGBX,
7652 val & PLANE_CTL_ALPHA_MASK);
7653 fb->pixel_format = fourcc;
7654 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7656 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7657 plane_config->base = base;
7659 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7661 val = I915_READ(PLANE_SIZE(pipe, 0));
7662 fb->height = ((val >> 16) & 0xfff) + 1;
7663 fb->width = ((val >> 0) & 0x1fff) + 1;
7665 val = I915_READ(PLANE_STRIDE(pipe, 0));
7666 switch (plane_config->tiling) {
7667 case I915_TILING_NONE:
7674 MISSING_CASE(plane_config->tiling);
7677 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7679 aligned_height = intel_fb_align_height(dev, fb->height,
7680 plane_config->tiling);
7682 plane_config->size = fb->pitches[0] * aligned_height;
7684 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7685 pipe_name(pipe), fb->width, fb->height,
7686 fb->bits_per_pixel, base, fb->pitches[0],
7687 plane_config->size);
7689 crtc->base.primary->fb = fb;
7696 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7697 struct intel_crtc_state *pipe_config)
7699 struct drm_device *dev = crtc->base.dev;
7700 struct drm_i915_private *dev_priv = dev->dev_private;
7703 tmp = I915_READ(PF_CTL(crtc->pipe));
7705 if (tmp & PF_ENABLE) {
7706 pipe_config->pch_pfit.enabled = true;
7707 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7708 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7710 /* We currently do not free assignements of panel fitters on
7711 * ivb/hsw (since we don't use the higher upscaling modes which
7712 * differentiates them) so just WARN about this case for now. */
7714 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7715 PF_PIPE_SEL_IVB(crtc->pipe));
7721 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7722 struct intel_initial_plane_config *plane_config)
7724 struct drm_device *dev = crtc->base.dev;
7725 struct drm_i915_private *dev_priv = dev->dev_private;
7726 u32 val, base, offset;
7727 int pipe = crtc->pipe;
7728 int fourcc, pixel_format;
7730 struct drm_framebuffer *fb;
7731 struct intel_framebuffer *intel_fb;
7733 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7735 DRM_DEBUG_KMS("failed to alloc fb\n");
7739 fb = &intel_fb->base;
7741 val = I915_READ(DSPCNTR(pipe));
7743 if (INTEL_INFO(dev)->gen >= 4)
7744 if (val & DISPPLANE_TILED)
7745 plane_config->tiling = I915_TILING_X;
7747 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7748 fourcc = i9xx_format_to_fourcc(pixel_format);
7749 fb->pixel_format = fourcc;
7750 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7752 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7753 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7754 offset = I915_READ(DSPOFFSET(pipe));
7756 if (plane_config->tiling)
7757 offset = I915_READ(DSPTILEOFF(pipe));
7759 offset = I915_READ(DSPLINOFF(pipe));
7761 plane_config->base = base;
7763 val = I915_READ(PIPESRC(pipe));
7764 fb->width = ((val >> 16) & 0xfff) + 1;
7765 fb->height = ((val >> 0) & 0xfff) + 1;
7767 val = I915_READ(DSPSTRIDE(pipe));
7768 fb->pitches[0] = val & 0xffffffc0;
7770 aligned_height = intel_fb_align_height(dev, fb->height,
7771 plane_config->tiling);
7773 plane_config->size = fb->pitches[0] * aligned_height;
7775 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7776 pipe_name(pipe), fb->width, fb->height,
7777 fb->bits_per_pixel, base, fb->pitches[0],
7778 plane_config->size);
7780 crtc->base.primary->fb = fb;
7783 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7784 struct intel_crtc_state *pipe_config)
7786 struct drm_device *dev = crtc->base.dev;
7787 struct drm_i915_private *dev_priv = dev->dev_private;
7790 if (!intel_display_power_is_enabled(dev_priv,
7791 POWER_DOMAIN_PIPE(crtc->pipe)))
7794 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7795 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7797 tmp = I915_READ(PIPECONF(crtc->pipe));
7798 if (!(tmp & PIPECONF_ENABLE))
7801 switch (tmp & PIPECONF_BPC_MASK) {
7803 pipe_config->pipe_bpp = 18;
7806 pipe_config->pipe_bpp = 24;
7808 case PIPECONF_10BPC:
7809 pipe_config->pipe_bpp = 30;
7811 case PIPECONF_12BPC:
7812 pipe_config->pipe_bpp = 36;
7818 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7819 pipe_config->limited_color_range = true;
7821 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7822 struct intel_shared_dpll *pll;
7824 pipe_config->has_pch_encoder = true;
7826 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7827 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7828 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7830 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7832 if (HAS_PCH_IBX(dev_priv->dev)) {
7833 pipe_config->shared_dpll =
7834 (enum intel_dpll_id) crtc->pipe;
7836 tmp = I915_READ(PCH_DPLL_SEL);
7837 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7838 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7840 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7843 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7845 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7846 &pipe_config->dpll_hw_state));
7848 tmp = pipe_config->dpll_hw_state.dpll;
7849 pipe_config->pixel_multiplier =
7850 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7851 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7853 ironlake_pch_clock_get(crtc, pipe_config);
7855 pipe_config->pixel_multiplier = 1;
7858 intel_get_pipe_timings(crtc, pipe_config);
7860 ironlake_get_pfit_config(crtc, pipe_config);
7865 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7867 struct drm_device *dev = dev_priv->dev;
7868 struct intel_crtc *crtc;
7870 for_each_intel_crtc(dev, crtc)
7871 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7872 pipe_name(crtc->pipe));
7874 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7875 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7876 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7877 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7878 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7879 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7880 "CPU PWM1 enabled\n");
7881 if (IS_HASWELL(dev))
7882 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7883 "CPU PWM2 enabled\n");
7884 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7885 "PCH PWM1 enabled\n");
7886 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7887 "Utility pin enabled\n");
7888 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7891 * In theory we can still leave IRQs enabled, as long as only the HPD
7892 * interrupts remain enabled. We used to check for that, but since it's
7893 * gen-specific and since we only disable LCPLL after we fully disable
7894 * the interrupts, the check below should be enough.
7896 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7899 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7901 struct drm_device *dev = dev_priv->dev;
7903 if (IS_HASWELL(dev))
7904 return I915_READ(D_COMP_HSW);
7906 return I915_READ(D_COMP_BDW);
7909 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7911 struct drm_device *dev = dev_priv->dev;
7913 if (IS_HASWELL(dev)) {
7914 mutex_lock(&dev_priv->rps.hw_lock);
7915 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7917 DRM_ERROR("Failed to write to D_COMP\n");
7918 mutex_unlock(&dev_priv->rps.hw_lock);
7920 I915_WRITE(D_COMP_BDW, val);
7921 POSTING_READ(D_COMP_BDW);
7926 * This function implements pieces of two sequences from BSpec:
7927 * - Sequence for display software to disable LCPLL
7928 * - Sequence for display software to allow package C8+
7929 * The steps implemented here are just the steps that actually touch the LCPLL
7930 * register. Callers should take care of disabling all the display engine
7931 * functions, doing the mode unset, fixing interrupts, etc.
7933 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7934 bool switch_to_fclk, bool allow_power_down)
7938 assert_can_disable_lcpll(dev_priv);
7940 val = I915_READ(LCPLL_CTL);
7942 if (switch_to_fclk) {
7943 val |= LCPLL_CD_SOURCE_FCLK;
7944 I915_WRITE(LCPLL_CTL, val);
7946 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7947 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7948 DRM_ERROR("Switching to FCLK failed\n");
7950 val = I915_READ(LCPLL_CTL);
7953 val |= LCPLL_PLL_DISABLE;
7954 I915_WRITE(LCPLL_CTL, val);
7955 POSTING_READ(LCPLL_CTL);
7957 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7958 DRM_ERROR("LCPLL still locked\n");
7960 val = hsw_read_dcomp(dev_priv);
7961 val |= D_COMP_COMP_DISABLE;
7962 hsw_write_dcomp(dev_priv, val);
7965 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7967 DRM_ERROR("D_COMP RCOMP still in progress\n");
7969 if (allow_power_down) {
7970 val = I915_READ(LCPLL_CTL);
7971 val |= LCPLL_POWER_DOWN_ALLOW;
7972 I915_WRITE(LCPLL_CTL, val);
7973 POSTING_READ(LCPLL_CTL);
7978 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7981 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7985 val = I915_READ(LCPLL_CTL);
7987 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7988 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7992 * Make sure we're not on PC8 state before disabling PC8, otherwise
7993 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7995 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7997 if (val & LCPLL_POWER_DOWN_ALLOW) {
7998 val &= ~LCPLL_POWER_DOWN_ALLOW;
7999 I915_WRITE(LCPLL_CTL, val);
8000 POSTING_READ(LCPLL_CTL);
8003 val = hsw_read_dcomp(dev_priv);
8004 val |= D_COMP_COMP_FORCE;
8005 val &= ~D_COMP_COMP_DISABLE;
8006 hsw_write_dcomp(dev_priv, val);
8008 val = I915_READ(LCPLL_CTL);
8009 val &= ~LCPLL_PLL_DISABLE;
8010 I915_WRITE(LCPLL_CTL, val);
8012 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8013 DRM_ERROR("LCPLL not locked yet\n");
8015 if (val & LCPLL_CD_SOURCE_FCLK) {
8016 val = I915_READ(LCPLL_CTL);
8017 val &= ~LCPLL_CD_SOURCE_FCLK;
8018 I915_WRITE(LCPLL_CTL, val);
8020 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8021 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8022 DRM_ERROR("Switching back to LCPLL failed\n");
8025 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8029 * Package states C8 and deeper are really deep PC states that can only be
8030 * reached when all the devices on the system allow it, so even if the graphics
8031 * device allows PC8+, it doesn't mean the system will actually get to these
8032 * states. Our driver only allows PC8+ when going into runtime PM.
8034 * The requirements for PC8+ are that all the outputs are disabled, the power
8035 * well is disabled and most interrupts are disabled, and these are also
8036 * requirements for runtime PM. When these conditions are met, we manually do
8037 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8038 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8041 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8042 * the state of some registers, so when we come back from PC8+ we need to
8043 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8044 * need to take care of the registers kept by RC6. Notice that this happens even
8045 * if we don't put the device in PCI D3 state (which is what currently happens
8046 * because of the runtime PM support).
8048 * For more, read "Display Sequences for Package C8" on the hardware
8051 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8053 struct drm_device *dev = dev_priv->dev;
8056 DRM_DEBUG_KMS("Enabling package C8+\n");
8058 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8059 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8060 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8061 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8064 lpt_disable_clkout_dp(dev);
8065 hsw_disable_lcpll(dev_priv, true, true);
8068 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8070 struct drm_device *dev = dev_priv->dev;
8073 DRM_DEBUG_KMS("Disabling package C8+\n");
8075 hsw_restore_lcpll(dev_priv);
8076 lpt_init_pch_refclk(dev);
8078 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8079 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8080 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8081 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8084 intel_prepare_ddi(dev);
8087 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8088 struct intel_crtc_state *crtc_state)
8090 if (!intel_ddi_pll_select(crtc, crtc_state))
8093 crtc->lowfreq_avail = false;
8098 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8100 struct intel_crtc_state *pipe_config)
8102 u32 temp, dpll_ctl1;
8104 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8105 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8107 switch (pipe_config->ddi_pll_sel) {
8110 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8111 * of the shared DPLL framework and thus needs to be read out
8114 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8115 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8118 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8121 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8124 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8129 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8131 struct intel_crtc_state *pipe_config)
8133 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8135 switch (pipe_config->ddi_pll_sel) {
8136 case PORT_CLK_SEL_WRPLL1:
8137 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8139 case PORT_CLK_SEL_WRPLL2:
8140 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8145 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8146 struct intel_crtc_state *pipe_config)
8148 struct drm_device *dev = crtc->base.dev;
8149 struct drm_i915_private *dev_priv = dev->dev_private;
8150 struct intel_shared_dpll *pll;
8154 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8156 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8158 if (IS_SKYLAKE(dev))
8159 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8161 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8163 if (pipe_config->shared_dpll >= 0) {
8164 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8166 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8167 &pipe_config->dpll_hw_state));
8171 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8172 * DDI E. So just check whether this pipe is wired to DDI E and whether
8173 * the PCH transcoder is on.
8175 if (INTEL_INFO(dev)->gen < 9 &&
8176 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8177 pipe_config->has_pch_encoder = true;
8179 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8180 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8181 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8183 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8187 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8188 struct intel_crtc_state *pipe_config)
8190 struct drm_device *dev = crtc->base.dev;
8191 struct drm_i915_private *dev_priv = dev->dev_private;
8192 enum intel_display_power_domain pfit_domain;
8195 if (!intel_display_power_is_enabled(dev_priv,
8196 POWER_DOMAIN_PIPE(crtc->pipe)))
8199 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8200 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8202 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8203 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8204 enum pipe trans_edp_pipe;
8205 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8207 WARN(1, "unknown pipe linked to edp transcoder\n");
8208 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8209 case TRANS_DDI_EDP_INPUT_A_ON:
8210 trans_edp_pipe = PIPE_A;
8212 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8213 trans_edp_pipe = PIPE_B;
8215 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8216 trans_edp_pipe = PIPE_C;
8220 if (trans_edp_pipe == crtc->pipe)
8221 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8224 if (!intel_display_power_is_enabled(dev_priv,
8225 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8228 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8229 if (!(tmp & PIPECONF_ENABLE))
8232 haswell_get_ddi_port_state(crtc, pipe_config);
8234 intel_get_pipe_timings(crtc, pipe_config);
8236 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8237 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8238 if (IS_SKYLAKE(dev))
8239 skylake_get_pfit_config(crtc, pipe_config);
8241 ironlake_get_pfit_config(crtc, pipe_config);
8244 if (IS_HASWELL(dev))
8245 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8246 (I915_READ(IPS_CTL) & IPS_ENABLE);
8248 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8249 pipe_config->pixel_multiplier =
8250 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8252 pipe_config->pixel_multiplier = 1;
8258 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8260 struct drm_device *dev = crtc->dev;
8261 struct drm_i915_private *dev_priv = dev->dev_private;
8262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8263 uint32_t cntl = 0, size = 0;
8266 unsigned int width = intel_crtc->cursor_width;
8267 unsigned int height = intel_crtc->cursor_height;
8268 unsigned int stride = roundup_pow_of_two(width) * 4;
8272 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8283 cntl |= CURSOR_ENABLE |
8284 CURSOR_GAMMA_ENABLE |
8285 CURSOR_FORMAT_ARGB |
8286 CURSOR_STRIDE(stride);
8288 size = (height << 12) | width;
8291 if (intel_crtc->cursor_cntl != 0 &&
8292 (intel_crtc->cursor_base != base ||
8293 intel_crtc->cursor_size != size ||
8294 intel_crtc->cursor_cntl != cntl)) {
8295 /* On these chipsets we can only modify the base/size/stride
8296 * whilst the cursor is disabled.
8298 I915_WRITE(_CURACNTR, 0);
8299 POSTING_READ(_CURACNTR);
8300 intel_crtc->cursor_cntl = 0;
8303 if (intel_crtc->cursor_base != base) {
8304 I915_WRITE(_CURABASE, base);
8305 intel_crtc->cursor_base = base;
8308 if (intel_crtc->cursor_size != size) {
8309 I915_WRITE(CURSIZE, size);
8310 intel_crtc->cursor_size = size;
8313 if (intel_crtc->cursor_cntl != cntl) {
8314 I915_WRITE(_CURACNTR, cntl);
8315 POSTING_READ(_CURACNTR);
8316 intel_crtc->cursor_cntl = cntl;
8320 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8322 struct drm_device *dev = crtc->dev;
8323 struct drm_i915_private *dev_priv = dev->dev_private;
8324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8325 int pipe = intel_crtc->pipe;
8330 cntl = MCURSOR_GAMMA_ENABLE;
8331 switch (intel_crtc->cursor_width) {
8333 cntl |= CURSOR_MODE_64_ARGB_AX;
8336 cntl |= CURSOR_MODE_128_ARGB_AX;
8339 cntl |= CURSOR_MODE_256_ARGB_AX;
8342 MISSING_CASE(intel_crtc->cursor_width);
8345 cntl |= pipe << 28; /* Connect to correct pipe */
8347 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8348 cntl |= CURSOR_PIPE_CSC_ENABLE;
8351 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8352 cntl |= CURSOR_ROTATE_180;
8354 if (intel_crtc->cursor_cntl != cntl) {
8355 I915_WRITE(CURCNTR(pipe), cntl);
8356 POSTING_READ(CURCNTR(pipe));
8357 intel_crtc->cursor_cntl = cntl;
8360 /* and commit changes on next vblank */
8361 I915_WRITE(CURBASE(pipe), base);
8362 POSTING_READ(CURBASE(pipe));
8364 intel_crtc->cursor_base = base;
8367 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8368 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8371 struct drm_device *dev = crtc->dev;
8372 struct drm_i915_private *dev_priv = dev->dev_private;
8373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8374 int pipe = intel_crtc->pipe;
8375 int x = crtc->cursor_x;
8376 int y = crtc->cursor_y;
8377 u32 base = 0, pos = 0;
8380 base = intel_crtc->cursor_addr;
8382 if (x >= intel_crtc->config->pipe_src_w)
8385 if (y >= intel_crtc->config->pipe_src_h)
8389 if (x + intel_crtc->cursor_width <= 0)
8392 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8395 pos |= x << CURSOR_X_SHIFT;
8398 if (y + intel_crtc->cursor_height <= 0)
8401 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8404 pos |= y << CURSOR_Y_SHIFT;
8406 if (base == 0 && intel_crtc->cursor_base == 0)
8409 I915_WRITE(CURPOS(pipe), pos);
8411 /* ILK+ do this automagically */
8412 if (HAS_GMCH_DISPLAY(dev) &&
8413 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8414 base += (intel_crtc->cursor_height *
8415 intel_crtc->cursor_width - 1) * 4;
8418 if (IS_845G(dev) || IS_I865G(dev))
8419 i845_update_cursor(crtc, base);
8421 i9xx_update_cursor(crtc, base);
8424 static bool cursor_size_ok(struct drm_device *dev,
8425 uint32_t width, uint32_t height)
8427 if (width == 0 || height == 0)
8431 * 845g/865g are special in that they are only limited by
8432 * the width of their cursors, the height is arbitrary up to
8433 * the precision of the register. Everything else requires
8434 * square cursors, limited to a few power-of-two sizes.
8436 if (IS_845G(dev) || IS_I865G(dev)) {
8437 if ((width & 63) != 0)
8440 if (width > (IS_845G(dev) ? 64 : 512))
8446 switch (width | height) {
8461 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8462 u16 *blue, uint32_t start, uint32_t size)
8464 int end = (start + size > 256) ? 256 : start + size, i;
8465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8467 for (i = start; i < end; i++) {
8468 intel_crtc->lut_r[i] = red[i] >> 8;
8469 intel_crtc->lut_g[i] = green[i] >> 8;
8470 intel_crtc->lut_b[i] = blue[i] >> 8;
8473 intel_crtc_load_lut(crtc);
8476 /* VESA 640x480x72Hz mode to set on the pipe */
8477 static struct drm_display_mode load_detect_mode = {
8478 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8479 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8482 struct drm_framebuffer *
8483 __intel_framebuffer_create(struct drm_device *dev,
8484 struct drm_mode_fb_cmd2 *mode_cmd,
8485 struct drm_i915_gem_object *obj)
8487 struct intel_framebuffer *intel_fb;
8490 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8492 drm_gem_object_unreference(&obj->base);
8493 return ERR_PTR(-ENOMEM);
8496 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8500 return &intel_fb->base;
8502 drm_gem_object_unreference(&obj->base);
8505 return ERR_PTR(ret);
8508 static struct drm_framebuffer *
8509 intel_framebuffer_create(struct drm_device *dev,
8510 struct drm_mode_fb_cmd2 *mode_cmd,
8511 struct drm_i915_gem_object *obj)
8513 struct drm_framebuffer *fb;
8516 ret = i915_mutex_lock_interruptible(dev);
8518 return ERR_PTR(ret);
8519 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8520 mutex_unlock(&dev->struct_mutex);
8526 intel_framebuffer_pitch_for_width(int width, int bpp)
8528 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8529 return ALIGN(pitch, 64);
8533 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8535 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8536 return PAGE_ALIGN(pitch * mode->vdisplay);
8539 static struct drm_framebuffer *
8540 intel_framebuffer_create_for_mode(struct drm_device *dev,
8541 struct drm_display_mode *mode,
8544 struct drm_i915_gem_object *obj;
8545 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8547 obj = i915_gem_alloc_object(dev,
8548 intel_framebuffer_size_for_mode(mode, bpp));
8550 return ERR_PTR(-ENOMEM);
8552 mode_cmd.width = mode->hdisplay;
8553 mode_cmd.height = mode->vdisplay;
8554 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8556 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8558 return intel_framebuffer_create(dev, &mode_cmd, obj);
8561 static struct drm_framebuffer *
8562 mode_fits_in_fbdev(struct drm_device *dev,
8563 struct drm_display_mode *mode)
8565 #ifdef CONFIG_DRM_I915_FBDEV
8566 struct drm_i915_private *dev_priv = dev->dev_private;
8567 struct drm_i915_gem_object *obj;
8568 struct drm_framebuffer *fb;
8570 if (!dev_priv->fbdev)
8573 if (!dev_priv->fbdev->fb)
8576 obj = dev_priv->fbdev->fb->obj;
8579 fb = &dev_priv->fbdev->fb->base;
8580 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8581 fb->bits_per_pixel))
8584 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8593 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8594 struct drm_display_mode *mode,
8595 struct intel_load_detect_pipe *old,
8596 struct drm_modeset_acquire_ctx *ctx)
8598 struct intel_crtc *intel_crtc;
8599 struct intel_encoder *intel_encoder =
8600 intel_attached_encoder(connector);
8601 struct drm_crtc *possible_crtc;
8602 struct drm_encoder *encoder = &intel_encoder->base;
8603 struct drm_crtc *crtc = NULL;
8604 struct drm_device *dev = encoder->dev;
8605 struct drm_framebuffer *fb;
8606 struct drm_mode_config *config = &dev->mode_config;
8609 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8610 connector->base.id, connector->name,
8611 encoder->base.id, encoder->name);
8614 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8619 * Algorithm gets a little messy:
8621 * - if the connector already has an assigned crtc, use it (but make
8622 * sure it's on first)
8624 * - try to find the first unused crtc that can drive this connector,
8625 * and use that if we find one
8628 /* See if we already have a CRTC for this connector */
8629 if (encoder->crtc) {
8630 crtc = encoder->crtc;
8632 ret = drm_modeset_lock(&crtc->mutex, ctx);
8635 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8639 old->dpms_mode = connector->dpms;
8640 old->load_detect_temp = false;
8642 /* Make sure the crtc and connector are running */
8643 if (connector->dpms != DRM_MODE_DPMS_ON)
8644 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8649 /* Find an unused one (if possible) */
8650 for_each_crtc(dev, possible_crtc) {
8652 if (!(encoder->possible_crtcs & (1 << i)))
8654 if (possible_crtc->enabled)
8656 /* This can occur when applying the pipe A quirk on resume. */
8657 if (to_intel_crtc(possible_crtc)->new_enabled)
8660 crtc = possible_crtc;
8665 * If we didn't find an unused CRTC, don't use any.
8668 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8672 ret = drm_modeset_lock(&crtc->mutex, ctx);
8675 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8678 intel_encoder->new_crtc = to_intel_crtc(crtc);
8679 to_intel_connector(connector)->new_encoder = intel_encoder;
8681 intel_crtc = to_intel_crtc(crtc);
8682 intel_crtc->new_enabled = true;
8683 intel_crtc->new_config = intel_crtc->config;
8684 old->dpms_mode = connector->dpms;
8685 old->load_detect_temp = true;
8686 old->release_fb = NULL;
8689 mode = &load_detect_mode;
8691 /* We need a framebuffer large enough to accommodate all accesses
8692 * that the plane may generate whilst we perform load detection.
8693 * We can not rely on the fbcon either being present (we get called
8694 * during its initialisation to detect all boot displays, or it may
8695 * not even exist) or that it is large enough to satisfy the
8698 fb = mode_fits_in_fbdev(dev, mode);
8700 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8701 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8702 old->release_fb = fb;
8704 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8706 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8710 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8711 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8712 if (old->release_fb)
8713 old->release_fb->funcs->destroy(old->release_fb);
8716 crtc->primary->crtc = crtc;
8718 /* let the connector get through one full cycle before testing */
8719 intel_wait_for_vblank(dev, intel_crtc->pipe);
8723 intel_crtc->new_enabled = crtc->enabled;
8724 if (intel_crtc->new_enabled)
8725 intel_crtc->new_config = intel_crtc->config;
8727 intel_crtc->new_config = NULL;
8729 if (ret == -EDEADLK) {
8730 drm_modeset_backoff(ctx);
8737 void intel_release_load_detect_pipe(struct drm_connector *connector,
8738 struct intel_load_detect_pipe *old)
8740 struct intel_encoder *intel_encoder =
8741 intel_attached_encoder(connector);
8742 struct drm_encoder *encoder = &intel_encoder->base;
8743 struct drm_crtc *crtc = encoder->crtc;
8744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8746 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8747 connector->base.id, connector->name,
8748 encoder->base.id, encoder->name);
8750 if (old->load_detect_temp) {
8751 to_intel_connector(connector)->new_encoder = NULL;
8752 intel_encoder->new_crtc = NULL;
8753 intel_crtc->new_enabled = false;
8754 intel_crtc->new_config = NULL;
8755 intel_set_mode(crtc, NULL, 0, 0, NULL);
8757 if (old->release_fb) {
8758 drm_framebuffer_unregister_private(old->release_fb);
8759 drm_framebuffer_unreference(old->release_fb);
8765 /* Switch crtc and encoder back off if necessary */
8766 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8767 connector->funcs->dpms(connector, old->dpms_mode);
8770 static int i9xx_pll_refclk(struct drm_device *dev,
8771 const struct intel_crtc_state *pipe_config)
8773 struct drm_i915_private *dev_priv = dev->dev_private;
8774 u32 dpll = pipe_config->dpll_hw_state.dpll;
8776 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8777 return dev_priv->vbt.lvds_ssc_freq;
8778 else if (HAS_PCH_SPLIT(dev))
8780 else if (!IS_GEN2(dev))
8786 /* Returns the clock of the currently programmed mode of the given pipe. */
8787 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8788 struct intel_crtc_state *pipe_config)
8790 struct drm_device *dev = crtc->base.dev;
8791 struct drm_i915_private *dev_priv = dev->dev_private;
8792 int pipe = pipe_config->cpu_transcoder;
8793 u32 dpll = pipe_config->dpll_hw_state.dpll;
8795 intel_clock_t clock;
8796 int refclk = i9xx_pll_refclk(dev, pipe_config);
8798 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8799 fp = pipe_config->dpll_hw_state.fp0;
8801 fp = pipe_config->dpll_hw_state.fp1;
8803 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8804 if (IS_PINEVIEW(dev)) {
8805 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8806 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8808 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8809 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8812 if (!IS_GEN2(dev)) {
8813 if (IS_PINEVIEW(dev))
8814 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8815 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8817 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8818 DPLL_FPA01_P1_POST_DIV_SHIFT);
8820 switch (dpll & DPLL_MODE_MASK) {
8821 case DPLLB_MODE_DAC_SERIAL:
8822 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8825 case DPLLB_MODE_LVDS:
8826 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8830 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8831 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8835 if (IS_PINEVIEW(dev))
8836 pineview_clock(refclk, &clock);
8838 i9xx_clock(refclk, &clock);
8840 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8841 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8844 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8845 DPLL_FPA01_P1_POST_DIV_SHIFT);
8847 if (lvds & LVDS_CLKB_POWER_UP)
8852 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8855 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8856 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8858 if (dpll & PLL_P2_DIVIDE_BY_4)
8864 i9xx_clock(refclk, &clock);
8868 * This value includes pixel_multiplier. We will use
8869 * port_clock to compute adjusted_mode.crtc_clock in the
8870 * encoder's get_config() function.
8872 pipe_config->port_clock = clock.dot;
8875 int intel_dotclock_calculate(int link_freq,
8876 const struct intel_link_m_n *m_n)
8879 * The calculation for the data clock is:
8880 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8881 * But we want to avoid losing precison if possible, so:
8882 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8884 * and the link clock is simpler:
8885 * link_clock = (m * link_clock) / n
8891 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8894 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8895 struct intel_crtc_state *pipe_config)
8897 struct drm_device *dev = crtc->base.dev;
8899 /* read out port_clock from the DPLL */
8900 i9xx_crtc_clock_get(crtc, pipe_config);
8903 * This value does not include pixel_multiplier.
8904 * We will check that port_clock and adjusted_mode.crtc_clock
8905 * agree once we know their relationship in the encoder's
8906 * get_config() function.
8908 pipe_config->base.adjusted_mode.crtc_clock =
8909 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8910 &pipe_config->fdi_m_n);
8913 /** Returns the currently programmed mode of the given pipe. */
8914 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8915 struct drm_crtc *crtc)
8917 struct drm_i915_private *dev_priv = dev->dev_private;
8918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8919 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8920 struct drm_display_mode *mode;
8921 struct intel_crtc_state pipe_config;
8922 int htot = I915_READ(HTOTAL(cpu_transcoder));
8923 int hsync = I915_READ(HSYNC(cpu_transcoder));
8924 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8925 int vsync = I915_READ(VSYNC(cpu_transcoder));
8926 enum pipe pipe = intel_crtc->pipe;
8928 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8933 * Construct a pipe_config sufficient for getting the clock info
8934 * back out of crtc_clock_get.
8936 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8937 * to use a real value here instead.
8939 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8940 pipe_config.pixel_multiplier = 1;
8941 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8942 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8943 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8944 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8946 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8947 mode->hdisplay = (htot & 0xffff) + 1;
8948 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8949 mode->hsync_start = (hsync & 0xffff) + 1;
8950 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8951 mode->vdisplay = (vtot & 0xffff) + 1;
8952 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8953 mode->vsync_start = (vsync & 0xffff) + 1;
8954 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8956 drm_mode_set_name(mode);
8961 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8963 struct drm_device *dev = crtc->dev;
8964 struct drm_i915_private *dev_priv = dev->dev_private;
8965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8967 if (!HAS_GMCH_DISPLAY(dev))
8970 if (!dev_priv->lvds_downclock_avail)
8974 * Since this is called by a timer, we should never get here in
8977 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8978 int pipe = intel_crtc->pipe;
8979 int dpll_reg = DPLL(pipe);
8982 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8984 assert_panel_unlocked(dev_priv, pipe);
8986 dpll = I915_READ(dpll_reg);
8987 dpll |= DISPLAY_RATE_SELECT_FPA1;
8988 I915_WRITE(dpll_reg, dpll);
8989 intel_wait_for_vblank(dev, pipe);
8990 dpll = I915_READ(dpll_reg);
8991 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8992 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8997 void intel_mark_busy(struct drm_device *dev)
8999 struct drm_i915_private *dev_priv = dev->dev_private;
9001 if (dev_priv->mm.busy)
9004 intel_runtime_pm_get(dev_priv);
9005 i915_update_gfx_val(dev_priv);
9006 dev_priv->mm.busy = true;
9009 void intel_mark_idle(struct drm_device *dev)
9011 struct drm_i915_private *dev_priv = dev->dev_private;
9012 struct drm_crtc *crtc;
9014 if (!dev_priv->mm.busy)
9017 dev_priv->mm.busy = false;
9019 if (!i915.powersave)
9022 for_each_crtc(dev, crtc) {
9023 if (!crtc->primary->fb)
9026 intel_decrease_pllclock(crtc);
9029 if (INTEL_INFO(dev)->gen >= 6)
9030 gen6_rps_idle(dev->dev_private);
9033 intel_runtime_pm_put(dev_priv);
9036 static void intel_crtc_set_state(struct intel_crtc *crtc,
9037 struct intel_crtc_state *crtc_state)
9039 kfree(crtc->config);
9040 crtc->config = crtc_state;
9041 crtc->base.state = &crtc_state->base;
9044 static void intel_crtc_destroy(struct drm_crtc *crtc)
9046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9047 struct drm_device *dev = crtc->dev;
9048 struct intel_unpin_work *work;
9050 spin_lock_irq(&dev->event_lock);
9051 work = intel_crtc->unpin_work;
9052 intel_crtc->unpin_work = NULL;
9053 spin_unlock_irq(&dev->event_lock);
9056 cancel_work_sync(&work->work);
9060 intel_crtc_set_state(intel_crtc, NULL);
9061 drm_crtc_cleanup(crtc);
9066 static void intel_unpin_work_fn(struct work_struct *__work)
9068 struct intel_unpin_work *work =
9069 container_of(__work, struct intel_unpin_work, work);
9070 struct drm_device *dev = work->crtc->dev;
9071 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9073 mutex_lock(&dev->struct_mutex);
9074 intel_unpin_fb_obj(work->old_fb_obj);
9075 drm_gem_object_unreference(&work->pending_flip_obj->base);
9076 drm_gem_object_unreference(&work->old_fb_obj->base);
9078 intel_fbc_update(dev);
9080 if (work->flip_queued_req)
9081 i915_gem_request_assign(&work->flip_queued_req, NULL);
9082 mutex_unlock(&dev->struct_mutex);
9084 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9086 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9087 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9092 static void do_intel_finish_page_flip(struct drm_device *dev,
9093 struct drm_crtc *crtc)
9095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9096 struct intel_unpin_work *work;
9097 unsigned long flags;
9099 /* Ignore early vblank irqs */
9100 if (intel_crtc == NULL)
9104 * This is called both by irq handlers and the reset code (to complete
9105 * lost pageflips) so needs the full irqsave spinlocks.
9107 spin_lock_irqsave(&dev->event_lock, flags);
9108 work = intel_crtc->unpin_work;
9110 /* Ensure we don't miss a work->pending update ... */
9113 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9114 spin_unlock_irqrestore(&dev->event_lock, flags);
9118 page_flip_completed(intel_crtc);
9120 spin_unlock_irqrestore(&dev->event_lock, flags);
9123 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9125 struct drm_i915_private *dev_priv = dev->dev_private;
9126 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9128 do_intel_finish_page_flip(dev, crtc);
9131 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9133 struct drm_i915_private *dev_priv = dev->dev_private;
9134 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9136 do_intel_finish_page_flip(dev, crtc);
9139 /* Is 'a' after or equal to 'b'? */
9140 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9142 return !((a - b) & 0x80000000);
9145 static bool page_flip_finished(struct intel_crtc *crtc)
9147 struct drm_device *dev = crtc->base.dev;
9148 struct drm_i915_private *dev_priv = dev->dev_private;
9150 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9151 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9155 * The relevant registers doen't exist on pre-ctg.
9156 * As the flip done interrupt doesn't trigger for mmio
9157 * flips on gmch platforms, a flip count check isn't
9158 * really needed there. But since ctg has the registers,
9159 * include it in the check anyway.
9161 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9165 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9166 * used the same base address. In that case the mmio flip might
9167 * have completed, but the CS hasn't even executed the flip yet.
9169 * A flip count check isn't enough as the CS might have updated
9170 * the base address just after start of vblank, but before we
9171 * managed to process the interrupt. This means we'd complete the
9174 * Combining both checks should get us a good enough result. It may
9175 * still happen that the CS flip has been executed, but has not
9176 * yet actually completed. But in case the base address is the same
9177 * anyway, we don't really care.
9179 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9180 crtc->unpin_work->gtt_offset &&
9181 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9182 crtc->unpin_work->flip_count);
9185 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9187 struct drm_i915_private *dev_priv = dev->dev_private;
9188 struct intel_crtc *intel_crtc =
9189 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9190 unsigned long flags;
9194 * This is called both by irq handlers and the reset code (to complete
9195 * lost pageflips) so needs the full irqsave spinlocks.
9197 * NB: An MMIO update of the plane base pointer will also
9198 * generate a page-flip completion irq, i.e. every modeset
9199 * is also accompanied by a spurious intel_prepare_page_flip().
9201 spin_lock_irqsave(&dev->event_lock, flags);
9202 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9203 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9204 spin_unlock_irqrestore(&dev->event_lock, flags);
9207 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9209 /* Ensure that the work item is consistent when activating it ... */
9211 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9212 /* and that it is marked active as soon as the irq could fire. */
9216 static int intel_gen2_queue_flip(struct drm_device *dev,
9217 struct drm_crtc *crtc,
9218 struct drm_framebuffer *fb,
9219 struct drm_i915_gem_object *obj,
9220 struct intel_engine_cs *ring,
9223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9227 ret = intel_ring_begin(ring, 6);
9231 /* Can't queue multiple flips, so wait for the previous
9232 * one to finish before executing the next.
9234 if (intel_crtc->plane)
9235 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9237 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9238 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9239 intel_ring_emit(ring, MI_NOOP);
9240 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9241 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9242 intel_ring_emit(ring, fb->pitches[0]);
9243 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9244 intel_ring_emit(ring, 0); /* aux display base address, unused */
9246 intel_mark_page_flip_active(intel_crtc);
9247 __intel_ring_advance(ring);
9251 static int intel_gen3_queue_flip(struct drm_device *dev,
9252 struct drm_crtc *crtc,
9253 struct drm_framebuffer *fb,
9254 struct drm_i915_gem_object *obj,
9255 struct intel_engine_cs *ring,
9258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9262 ret = intel_ring_begin(ring, 6);
9266 if (intel_crtc->plane)
9267 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9269 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9270 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9271 intel_ring_emit(ring, MI_NOOP);
9272 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9273 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9274 intel_ring_emit(ring, fb->pitches[0]);
9275 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9276 intel_ring_emit(ring, MI_NOOP);
9278 intel_mark_page_flip_active(intel_crtc);
9279 __intel_ring_advance(ring);
9283 static int intel_gen4_queue_flip(struct drm_device *dev,
9284 struct drm_crtc *crtc,
9285 struct drm_framebuffer *fb,
9286 struct drm_i915_gem_object *obj,
9287 struct intel_engine_cs *ring,
9290 struct drm_i915_private *dev_priv = dev->dev_private;
9291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9292 uint32_t pf, pipesrc;
9295 ret = intel_ring_begin(ring, 4);
9299 /* i965+ uses the linear or tiled offsets from the
9300 * Display Registers (which do not change across a page-flip)
9301 * so we need only reprogram the base address.
9303 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9304 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9305 intel_ring_emit(ring, fb->pitches[0]);
9306 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9309 /* XXX Enabling the panel-fitter across page-flip is so far
9310 * untested on non-native modes, so ignore it for now.
9311 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9314 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9315 intel_ring_emit(ring, pf | pipesrc);
9317 intel_mark_page_flip_active(intel_crtc);
9318 __intel_ring_advance(ring);
9322 static int intel_gen6_queue_flip(struct drm_device *dev,
9323 struct drm_crtc *crtc,
9324 struct drm_framebuffer *fb,
9325 struct drm_i915_gem_object *obj,
9326 struct intel_engine_cs *ring,
9329 struct drm_i915_private *dev_priv = dev->dev_private;
9330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9331 uint32_t pf, pipesrc;
9334 ret = intel_ring_begin(ring, 4);
9338 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9339 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9340 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9341 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9343 /* Contrary to the suggestions in the documentation,
9344 * "Enable Panel Fitter" does not seem to be required when page
9345 * flipping with a non-native mode, and worse causes a normal
9347 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9350 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9351 intel_ring_emit(ring, pf | pipesrc);
9353 intel_mark_page_flip_active(intel_crtc);
9354 __intel_ring_advance(ring);
9358 static int intel_gen7_queue_flip(struct drm_device *dev,
9359 struct drm_crtc *crtc,
9360 struct drm_framebuffer *fb,
9361 struct drm_i915_gem_object *obj,
9362 struct intel_engine_cs *ring,
9365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9366 uint32_t plane_bit = 0;
9369 switch (intel_crtc->plane) {
9371 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9374 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9377 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9380 WARN_ONCE(1, "unknown plane in flip command\n");
9385 if (ring->id == RCS) {
9388 * On Gen 8, SRM is now taking an extra dword to accommodate
9389 * 48bits addresses, and we need a NOOP for the batch size to
9397 * BSpec MI_DISPLAY_FLIP for IVB:
9398 * "The full packet must be contained within the same cache line."
9400 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9401 * cacheline, if we ever start emitting more commands before
9402 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9403 * then do the cacheline alignment, and finally emit the
9406 ret = intel_ring_cacheline_align(ring);
9410 ret = intel_ring_begin(ring, len);
9414 /* Unmask the flip-done completion message. Note that the bspec says that
9415 * we should do this for both the BCS and RCS, and that we must not unmask
9416 * more than one flip event at any time (or ensure that one flip message
9417 * can be sent by waiting for flip-done prior to queueing new flips).
9418 * Experimentation says that BCS works despite DERRMR masking all
9419 * flip-done completion events and that unmasking all planes at once
9420 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9421 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9423 if (ring->id == RCS) {
9424 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9425 intel_ring_emit(ring, DERRMR);
9426 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9427 DERRMR_PIPEB_PRI_FLIP_DONE |
9428 DERRMR_PIPEC_PRI_FLIP_DONE));
9430 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9431 MI_SRM_LRM_GLOBAL_GTT);
9433 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9434 MI_SRM_LRM_GLOBAL_GTT);
9435 intel_ring_emit(ring, DERRMR);
9436 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9438 intel_ring_emit(ring, 0);
9439 intel_ring_emit(ring, MI_NOOP);
9443 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9444 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9445 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9446 intel_ring_emit(ring, (MI_NOOP));
9448 intel_mark_page_flip_active(intel_crtc);
9449 __intel_ring_advance(ring);
9453 static bool use_mmio_flip(struct intel_engine_cs *ring,
9454 struct drm_i915_gem_object *obj)
9457 * This is not being used for older platforms, because
9458 * non-availability of flip done interrupt forces us to use
9459 * CS flips. Older platforms derive flip done using some clever
9460 * tricks involving the flip_pending status bits and vblank irqs.
9461 * So using MMIO flips there would disrupt this mechanism.
9467 if (INTEL_INFO(ring->dev)->gen < 5)
9470 if (i915.use_mmio_flip < 0)
9472 else if (i915.use_mmio_flip > 0)
9474 else if (i915.enable_execlists)
9477 return ring != i915_gem_request_get_ring(obj->last_read_req);
9480 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9482 struct drm_device *dev = intel_crtc->base.dev;
9483 struct drm_i915_private *dev_priv = dev->dev_private;
9484 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9485 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9486 struct drm_i915_gem_object *obj = intel_fb->obj;
9487 const enum pipe pipe = intel_crtc->pipe;
9490 ctl = I915_READ(PLANE_CTL(pipe, 0));
9491 ctl &= ~PLANE_CTL_TILED_MASK;
9492 if (obj->tiling_mode == I915_TILING_X)
9493 ctl |= PLANE_CTL_TILED_X;
9496 * The stride is either expressed as a multiple of 64 bytes chunks for
9497 * linear buffers or in number of tiles for tiled buffers.
9499 stride = fb->pitches[0] >> 6;
9500 if (obj->tiling_mode == I915_TILING_X)
9501 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9504 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9505 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9507 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9508 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9510 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9511 POSTING_READ(PLANE_SURF(pipe, 0));
9514 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9516 struct drm_device *dev = intel_crtc->base.dev;
9517 struct drm_i915_private *dev_priv = dev->dev_private;
9518 struct intel_framebuffer *intel_fb =
9519 to_intel_framebuffer(intel_crtc->base.primary->fb);
9520 struct drm_i915_gem_object *obj = intel_fb->obj;
9524 reg = DSPCNTR(intel_crtc->plane);
9525 dspcntr = I915_READ(reg);
9527 if (obj->tiling_mode != I915_TILING_NONE)
9528 dspcntr |= DISPPLANE_TILED;
9530 dspcntr &= ~DISPPLANE_TILED;
9532 I915_WRITE(reg, dspcntr);
9534 I915_WRITE(DSPSURF(intel_crtc->plane),
9535 intel_crtc->unpin_work->gtt_offset);
9536 POSTING_READ(DSPSURF(intel_crtc->plane));
9541 * XXX: This is the temporary way to update the plane registers until we get
9542 * around to using the usual plane update functions for MMIO flips
9544 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9546 struct drm_device *dev = intel_crtc->base.dev;
9548 u32 start_vbl_count;
9550 intel_mark_page_flip_active(intel_crtc);
9552 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9554 if (INTEL_INFO(dev)->gen >= 9)
9555 skl_do_mmio_flip(intel_crtc);
9557 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9558 ilk_do_mmio_flip(intel_crtc);
9561 intel_pipe_update_end(intel_crtc, start_vbl_count);
9564 static void intel_mmio_flip_work_func(struct work_struct *work)
9566 struct intel_crtc *crtc =
9567 container_of(work, struct intel_crtc, mmio_flip.work);
9568 struct intel_mmio_flip *mmio_flip;
9570 mmio_flip = &crtc->mmio_flip;
9572 WARN_ON(__i915_wait_request(mmio_flip->req,
9573 crtc->reset_counter,
9574 false, NULL, NULL) != 0);
9576 intel_do_mmio_flip(crtc);
9577 if (mmio_flip->req) {
9578 mutex_lock(&crtc->base.dev->struct_mutex);
9579 i915_gem_request_assign(&mmio_flip->req, NULL);
9580 mutex_unlock(&crtc->base.dev->struct_mutex);
9584 static int intel_queue_mmio_flip(struct drm_device *dev,
9585 struct drm_crtc *crtc,
9586 struct drm_framebuffer *fb,
9587 struct drm_i915_gem_object *obj,
9588 struct intel_engine_cs *ring,
9591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9593 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9594 obj->last_write_req);
9596 schedule_work(&intel_crtc->mmio_flip.work);
9601 static int intel_gen9_queue_flip(struct drm_device *dev,
9602 struct drm_crtc *crtc,
9603 struct drm_framebuffer *fb,
9604 struct drm_i915_gem_object *obj,
9605 struct intel_engine_cs *ring,
9608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9609 uint32_t plane = 0, stride;
9612 switch(intel_crtc->pipe) {
9614 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9617 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9620 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9623 WARN_ONCE(1, "unknown plane in flip command\n");
9627 switch (obj->tiling_mode) {
9628 case I915_TILING_NONE:
9629 stride = fb->pitches[0] >> 6;
9632 stride = fb->pitches[0] >> 9;
9635 WARN_ONCE(1, "unknown tiling in flip command\n");
9639 ret = intel_ring_begin(ring, 10);
9643 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9644 intel_ring_emit(ring, DERRMR);
9645 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9646 DERRMR_PIPEB_PRI_FLIP_DONE |
9647 DERRMR_PIPEC_PRI_FLIP_DONE));
9648 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9649 MI_SRM_LRM_GLOBAL_GTT);
9650 intel_ring_emit(ring, DERRMR);
9651 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9652 intel_ring_emit(ring, 0);
9654 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9655 intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9656 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9658 intel_mark_page_flip_active(intel_crtc);
9659 __intel_ring_advance(ring);
9664 static int intel_default_queue_flip(struct drm_device *dev,
9665 struct drm_crtc *crtc,
9666 struct drm_framebuffer *fb,
9667 struct drm_i915_gem_object *obj,
9668 struct intel_engine_cs *ring,
9674 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9675 struct drm_crtc *crtc)
9677 struct drm_i915_private *dev_priv = dev->dev_private;
9678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9679 struct intel_unpin_work *work = intel_crtc->unpin_work;
9682 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9685 if (!work->enable_stall_check)
9688 if (work->flip_ready_vblank == 0) {
9689 if (work->flip_queued_req &&
9690 !i915_gem_request_completed(work->flip_queued_req, true))
9693 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9696 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9699 /* Potential stall - if we see that the flip has happened,
9700 * assume a missed interrupt. */
9701 if (INTEL_INFO(dev)->gen >= 4)
9702 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9704 addr = I915_READ(DSPADDR(intel_crtc->plane));
9706 /* There is a potential issue here with a false positive after a flip
9707 * to the same address. We could address this by checking for a
9708 * non-incrementing frame counter.
9710 return addr == work->gtt_offset;
9713 void intel_check_page_flip(struct drm_device *dev, int pipe)
9715 struct drm_i915_private *dev_priv = dev->dev_private;
9716 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9724 spin_lock(&dev->event_lock);
9725 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9726 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9727 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9728 page_flip_completed(intel_crtc);
9730 spin_unlock(&dev->event_lock);
9733 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9734 struct drm_framebuffer *fb,
9735 struct drm_pending_vblank_event *event,
9736 uint32_t page_flip_flags)
9738 struct drm_device *dev = crtc->dev;
9739 struct drm_i915_private *dev_priv = dev->dev_private;
9740 struct drm_framebuffer *old_fb = crtc->primary->fb;
9741 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9743 struct drm_plane *primary = crtc->primary;
9744 enum pipe pipe = intel_crtc->pipe;
9745 struct intel_unpin_work *work;
9746 struct intel_engine_cs *ring;
9750 * drm_mode_page_flip_ioctl() should already catch this, but double
9751 * check to be safe. In the future we may enable pageflipping from
9752 * a disabled primary plane.
9754 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9757 /* Can't change pixel format via MI display flips. */
9758 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9762 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9763 * Note that pitch changes could also affect these register.
9765 if (INTEL_INFO(dev)->gen > 3 &&
9766 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9767 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9770 if (i915_terminally_wedged(&dev_priv->gpu_error))
9773 work = kzalloc(sizeof(*work), GFP_KERNEL);
9777 work->event = event;
9779 work->old_fb_obj = intel_fb_obj(old_fb);
9780 INIT_WORK(&work->work, intel_unpin_work_fn);
9782 ret = drm_crtc_vblank_get(crtc);
9786 /* We borrow the event spin lock for protecting unpin_work */
9787 spin_lock_irq(&dev->event_lock);
9788 if (intel_crtc->unpin_work) {
9789 /* Before declaring the flip queue wedged, check if
9790 * the hardware completed the operation behind our backs.
9792 if (__intel_pageflip_stall_check(dev, crtc)) {
9793 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9794 page_flip_completed(intel_crtc);
9796 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9797 spin_unlock_irq(&dev->event_lock);
9799 drm_crtc_vblank_put(crtc);
9804 intel_crtc->unpin_work = work;
9805 spin_unlock_irq(&dev->event_lock);
9807 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9808 flush_workqueue(dev_priv->wq);
9810 ret = i915_mutex_lock_interruptible(dev);
9814 /* Reference the objects for the scheduled work. */
9815 drm_gem_object_reference(&work->old_fb_obj->base);
9816 drm_gem_object_reference(&obj->base);
9818 crtc->primary->fb = fb;
9820 work->pending_flip_obj = obj;
9822 atomic_inc(&intel_crtc->unpin_work_count);
9823 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9825 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9826 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9828 if (IS_VALLEYVIEW(dev)) {
9829 ring = &dev_priv->ring[BCS];
9830 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9831 /* vlv: DISPLAY_FLIP fails to change tiling */
9833 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9834 ring = &dev_priv->ring[BCS];
9835 } else if (INTEL_INFO(dev)->gen >= 7) {
9836 ring = i915_gem_request_get_ring(obj->last_read_req);
9837 if (ring == NULL || ring->id != RCS)
9838 ring = &dev_priv->ring[BCS];
9840 ring = &dev_priv->ring[RCS];
9843 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9845 goto cleanup_pending;
9848 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9850 if (use_mmio_flip(ring, obj)) {
9851 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9856 i915_gem_request_assign(&work->flip_queued_req,
9857 obj->last_write_req);
9859 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9864 i915_gem_request_assign(&work->flip_queued_req,
9865 intel_ring_get_request(ring));
9868 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9869 work->enable_stall_check = true;
9871 i915_gem_track_fb(work->old_fb_obj, obj,
9872 INTEL_FRONTBUFFER_PRIMARY(pipe));
9874 intel_fbc_disable(dev);
9875 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9876 mutex_unlock(&dev->struct_mutex);
9878 trace_i915_flip_request(intel_crtc->plane, obj);
9883 intel_unpin_fb_obj(obj);
9885 atomic_dec(&intel_crtc->unpin_work_count);
9886 crtc->primary->fb = old_fb;
9887 drm_gem_object_unreference(&work->old_fb_obj->base);
9888 drm_gem_object_unreference(&obj->base);
9889 mutex_unlock(&dev->struct_mutex);
9892 spin_lock_irq(&dev->event_lock);
9893 intel_crtc->unpin_work = NULL;
9894 spin_unlock_irq(&dev->event_lock);
9896 drm_crtc_vblank_put(crtc);
9902 ret = intel_plane_restore(primary);
9903 if (ret == 0 && event) {
9904 spin_lock_irq(&dev->event_lock);
9905 drm_send_vblank_event(dev, pipe, event);
9906 spin_unlock_irq(&dev->event_lock);
9912 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9913 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9914 .load_lut = intel_crtc_load_lut,
9915 .atomic_begin = intel_begin_crtc_commit,
9916 .atomic_flush = intel_finish_crtc_commit,
9920 * intel_modeset_update_staged_output_state
9922 * Updates the staged output configuration state, e.g. after we've read out the
9925 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9927 struct intel_crtc *crtc;
9928 struct intel_encoder *encoder;
9929 struct intel_connector *connector;
9931 list_for_each_entry(connector, &dev->mode_config.connector_list,
9933 connector->new_encoder =
9934 to_intel_encoder(connector->base.encoder);
9937 for_each_intel_encoder(dev, encoder) {
9939 to_intel_crtc(encoder->base.crtc);
9942 for_each_intel_crtc(dev, crtc) {
9943 crtc->new_enabled = crtc->base.enabled;
9945 if (crtc->new_enabled)
9946 crtc->new_config = crtc->config;
9948 crtc->new_config = NULL;
9953 * intel_modeset_commit_output_state
9955 * This function copies the stage display pipe configuration to the real one.
9957 static void intel_modeset_commit_output_state(struct drm_device *dev)
9959 struct intel_crtc *crtc;
9960 struct intel_encoder *encoder;
9961 struct intel_connector *connector;
9963 list_for_each_entry(connector, &dev->mode_config.connector_list,
9965 connector->base.encoder = &connector->new_encoder->base;
9968 for_each_intel_encoder(dev, encoder) {
9969 encoder->base.crtc = &encoder->new_crtc->base;
9972 for_each_intel_crtc(dev, crtc) {
9973 crtc->base.enabled = crtc->new_enabled;
9978 connected_sink_compute_bpp(struct intel_connector *connector,
9979 struct intel_crtc_state *pipe_config)
9981 int bpp = pipe_config->pipe_bpp;
9983 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9984 connector->base.base.id,
9985 connector->base.name);
9987 /* Don't use an invalid EDID bpc value */
9988 if (connector->base.display_info.bpc &&
9989 connector->base.display_info.bpc * 3 < bpp) {
9990 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9991 bpp, connector->base.display_info.bpc*3);
9992 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9995 /* Clamp bpp to 8 on screens without EDID 1.4 */
9996 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9997 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9999 pipe_config->pipe_bpp = 24;
10004 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10005 struct drm_framebuffer *fb,
10006 struct intel_crtc_state *pipe_config)
10008 struct drm_device *dev = crtc->base.dev;
10009 struct intel_connector *connector;
10012 switch (fb->pixel_format) {
10013 case DRM_FORMAT_C8:
10014 bpp = 8*3; /* since we go through a colormap */
10016 case DRM_FORMAT_XRGB1555:
10017 case DRM_FORMAT_ARGB1555:
10018 /* checked in intel_framebuffer_init already */
10019 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10021 case DRM_FORMAT_RGB565:
10022 bpp = 6*3; /* min is 18bpp */
10024 case DRM_FORMAT_XBGR8888:
10025 case DRM_FORMAT_ABGR8888:
10026 /* checked in intel_framebuffer_init already */
10027 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10029 case DRM_FORMAT_XRGB8888:
10030 case DRM_FORMAT_ARGB8888:
10033 case DRM_FORMAT_XRGB2101010:
10034 case DRM_FORMAT_ARGB2101010:
10035 case DRM_FORMAT_XBGR2101010:
10036 case DRM_FORMAT_ABGR2101010:
10037 /* checked in intel_framebuffer_init already */
10038 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10042 /* TODO: gen4+ supports 16 bpc floating point, too. */
10044 DRM_DEBUG_KMS("unsupported depth\n");
10048 pipe_config->pipe_bpp = bpp;
10050 /* Clamp display bpp to EDID value */
10051 list_for_each_entry(connector, &dev->mode_config.connector_list,
10053 if (!connector->new_encoder ||
10054 connector->new_encoder->new_crtc != crtc)
10057 connected_sink_compute_bpp(connector, pipe_config);
10063 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10065 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10066 "type: 0x%x flags: 0x%x\n",
10068 mode->crtc_hdisplay, mode->crtc_hsync_start,
10069 mode->crtc_hsync_end, mode->crtc_htotal,
10070 mode->crtc_vdisplay, mode->crtc_vsync_start,
10071 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10074 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10075 struct intel_crtc_state *pipe_config,
10076 const char *context)
10078 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10079 context, pipe_name(crtc->pipe));
10081 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10082 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10083 pipe_config->pipe_bpp, pipe_config->dither);
10084 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10085 pipe_config->has_pch_encoder,
10086 pipe_config->fdi_lanes,
10087 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10088 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10089 pipe_config->fdi_m_n.tu);
10090 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10091 pipe_config->has_dp_encoder,
10092 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10093 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10094 pipe_config->dp_m_n.tu);
10096 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10097 pipe_config->has_dp_encoder,
10098 pipe_config->dp_m2_n2.gmch_m,
10099 pipe_config->dp_m2_n2.gmch_n,
10100 pipe_config->dp_m2_n2.link_m,
10101 pipe_config->dp_m2_n2.link_n,
10102 pipe_config->dp_m2_n2.tu);
10104 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10105 pipe_config->has_audio,
10106 pipe_config->has_infoframe);
10108 DRM_DEBUG_KMS("requested mode:\n");
10109 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10110 DRM_DEBUG_KMS("adjusted mode:\n");
10111 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10112 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10113 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10114 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10115 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10116 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10117 pipe_config->gmch_pfit.control,
10118 pipe_config->gmch_pfit.pgm_ratios,
10119 pipe_config->gmch_pfit.lvds_border_bits);
10120 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10121 pipe_config->pch_pfit.pos,
10122 pipe_config->pch_pfit.size,
10123 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10124 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10125 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10128 static bool encoders_cloneable(const struct intel_encoder *a,
10129 const struct intel_encoder *b)
10131 /* masks could be asymmetric, so check both ways */
10132 return a == b || (a->cloneable & (1 << b->type) &&
10133 b->cloneable & (1 << a->type));
10136 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10137 struct intel_encoder *encoder)
10139 struct drm_device *dev = crtc->base.dev;
10140 struct intel_encoder *source_encoder;
10142 for_each_intel_encoder(dev, source_encoder) {
10143 if (source_encoder->new_crtc != crtc)
10146 if (!encoders_cloneable(encoder, source_encoder))
10153 static bool check_encoder_cloning(struct intel_crtc *crtc)
10155 struct drm_device *dev = crtc->base.dev;
10156 struct intel_encoder *encoder;
10158 for_each_intel_encoder(dev, encoder) {
10159 if (encoder->new_crtc != crtc)
10162 if (!check_single_encoder_cloning(crtc, encoder))
10169 static bool check_digital_port_conflicts(struct drm_device *dev)
10171 struct intel_connector *connector;
10172 unsigned int used_ports = 0;
10175 * Walk the connector list instead of the encoder
10176 * list to detect the problem on ddi platforms
10177 * where there's just one encoder per digital port.
10179 list_for_each_entry(connector,
10180 &dev->mode_config.connector_list, base.head) {
10181 struct intel_encoder *encoder = connector->new_encoder;
10186 WARN_ON(!encoder->new_crtc);
10188 switch (encoder->type) {
10189 unsigned int port_mask;
10190 case INTEL_OUTPUT_UNKNOWN:
10191 if (WARN_ON(!HAS_DDI(dev)))
10193 case INTEL_OUTPUT_DISPLAYPORT:
10194 case INTEL_OUTPUT_HDMI:
10195 case INTEL_OUTPUT_EDP:
10196 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10198 /* the same port mustn't appear more than once */
10199 if (used_ports & port_mask)
10202 used_ports |= port_mask;
10211 static struct intel_crtc_state *
10212 intel_modeset_pipe_config(struct drm_crtc *crtc,
10213 struct drm_framebuffer *fb,
10214 struct drm_display_mode *mode)
10216 struct drm_device *dev = crtc->dev;
10217 struct intel_encoder *encoder;
10218 struct intel_crtc_state *pipe_config;
10219 int plane_bpp, ret = -EINVAL;
10222 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10223 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10224 return ERR_PTR(-EINVAL);
10227 if (!check_digital_port_conflicts(dev)) {
10228 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10229 return ERR_PTR(-EINVAL);
10232 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10234 return ERR_PTR(-ENOMEM);
10236 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10237 drm_mode_copy(&pipe_config->base.mode, mode);
10239 pipe_config->cpu_transcoder =
10240 (enum transcoder) to_intel_crtc(crtc)->pipe;
10241 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10244 * Sanitize sync polarity flags based on requested ones. If neither
10245 * positive or negative polarity is requested, treat this as meaning
10246 * negative polarity.
10248 if (!(pipe_config->base.adjusted_mode.flags &
10249 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10250 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10252 if (!(pipe_config->base.adjusted_mode.flags &
10253 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10254 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10256 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10257 * plane pixel format and any sink constraints into account. Returns the
10258 * source plane bpp so that dithering can be selected on mismatches
10259 * after encoders and crtc also have had their say. */
10260 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10266 * Determine the real pipe dimensions. Note that stereo modes can
10267 * increase the actual pipe size due to the frame doubling and
10268 * insertion of additional space for blanks between the frame. This
10269 * is stored in the crtc timings. We use the requested mode to do this
10270 * computation to clearly distinguish it from the adjusted mode, which
10271 * can be changed by the connectors in the below retry loop.
10273 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10274 &pipe_config->pipe_src_w,
10275 &pipe_config->pipe_src_h);
10278 /* Ensure the port clock defaults are reset when retrying. */
10279 pipe_config->port_clock = 0;
10280 pipe_config->pixel_multiplier = 1;
10282 /* Fill in default crtc timings, allow encoders to overwrite them. */
10283 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10284 CRTC_STEREO_DOUBLE);
10286 /* Pass our mode to the connectors and the CRTC to give them a chance to
10287 * adjust it according to limitations or connector properties, and also
10288 * a chance to reject the mode entirely.
10290 for_each_intel_encoder(dev, encoder) {
10292 if (&encoder->new_crtc->base != crtc)
10295 if (!(encoder->compute_config(encoder, pipe_config))) {
10296 DRM_DEBUG_KMS("Encoder config failure\n");
10301 /* Set default port clock if not overwritten by the encoder. Needs to be
10302 * done afterwards in case the encoder adjusts the mode. */
10303 if (!pipe_config->port_clock)
10304 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10305 * pipe_config->pixel_multiplier;
10307 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10309 DRM_DEBUG_KMS("CRTC fixup failed\n");
10313 if (ret == RETRY) {
10314 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10319 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10321 goto encoder_retry;
10324 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10325 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10326 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10328 return pipe_config;
10330 kfree(pipe_config);
10331 return ERR_PTR(ret);
10334 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10335 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10337 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10338 unsigned *prepare_pipes, unsigned *disable_pipes)
10340 struct intel_crtc *intel_crtc;
10341 struct drm_device *dev = crtc->dev;
10342 struct intel_encoder *encoder;
10343 struct intel_connector *connector;
10344 struct drm_crtc *tmp_crtc;
10346 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10348 /* Check which crtcs have changed outputs connected to them, these need
10349 * to be part of the prepare_pipes mask. We don't (yet) support global
10350 * modeset across multiple crtcs, so modeset_pipes will only have one
10351 * bit set at most. */
10352 list_for_each_entry(connector, &dev->mode_config.connector_list,
10354 if (connector->base.encoder == &connector->new_encoder->base)
10357 if (connector->base.encoder) {
10358 tmp_crtc = connector->base.encoder->crtc;
10360 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10363 if (connector->new_encoder)
10365 1 << connector->new_encoder->new_crtc->pipe;
10368 for_each_intel_encoder(dev, encoder) {
10369 if (encoder->base.crtc == &encoder->new_crtc->base)
10372 if (encoder->base.crtc) {
10373 tmp_crtc = encoder->base.crtc;
10375 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10378 if (encoder->new_crtc)
10379 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10382 /* Check for pipes that will be enabled/disabled ... */
10383 for_each_intel_crtc(dev, intel_crtc) {
10384 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10387 if (!intel_crtc->new_enabled)
10388 *disable_pipes |= 1 << intel_crtc->pipe;
10390 *prepare_pipes |= 1 << intel_crtc->pipe;
10394 /* set_mode is also used to update properties on life display pipes. */
10395 intel_crtc = to_intel_crtc(crtc);
10396 if (intel_crtc->new_enabled)
10397 *prepare_pipes |= 1 << intel_crtc->pipe;
10400 * For simplicity do a full modeset on any pipe where the output routing
10401 * changed. We could be more clever, but that would require us to be
10402 * more careful with calling the relevant encoder->mode_set functions.
10404 if (*prepare_pipes)
10405 *modeset_pipes = *prepare_pipes;
10407 /* ... and mask these out. */
10408 *modeset_pipes &= ~(*disable_pipes);
10409 *prepare_pipes &= ~(*disable_pipes);
10412 * HACK: We don't (yet) fully support global modesets. intel_set_config
10413 * obies this rule, but the modeset restore mode of
10414 * intel_modeset_setup_hw_state does not.
10416 *modeset_pipes &= 1 << intel_crtc->pipe;
10417 *prepare_pipes &= 1 << intel_crtc->pipe;
10419 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10420 *modeset_pipes, *prepare_pipes, *disable_pipes);
10423 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10425 struct drm_encoder *encoder;
10426 struct drm_device *dev = crtc->dev;
10428 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10429 if (encoder->crtc == crtc)
10436 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10438 struct drm_i915_private *dev_priv = dev->dev_private;
10439 struct intel_encoder *intel_encoder;
10440 struct intel_crtc *intel_crtc;
10441 struct drm_connector *connector;
10443 intel_shared_dpll_commit(dev_priv);
10445 for_each_intel_encoder(dev, intel_encoder) {
10446 if (!intel_encoder->base.crtc)
10449 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10451 if (prepare_pipes & (1 << intel_crtc->pipe))
10452 intel_encoder->connectors_active = false;
10455 intel_modeset_commit_output_state(dev);
10457 /* Double check state. */
10458 for_each_intel_crtc(dev, intel_crtc) {
10459 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10460 WARN_ON(intel_crtc->new_config &&
10461 intel_crtc->new_config != intel_crtc->config);
10462 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10465 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10466 if (!connector->encoder || !connector->encoder->crtc)
10469 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10471 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10472 struct drm_property *dpms_property =
10473 dev->mode_config.dpms_property;
10475 connector->dpms = DRM_MODE_DPMS_ON;
10476 drm_object_property_set_value(&connector->base,
10480 intel_encoder = to_intel_encoder(connector->encoder);
10481 intel_encoder->connectors_active = true;
10487 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10491 if (clock1 == clock2)
10494 if (!clock1 || !clock2)
10497 diff = abs(clock1 - clock2);
10499 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10505 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10506 list_for_each_entry((intel_crtc), \
10507 &(dev)->mode_config.crtc_list, \
10509 if (mask & (1 <<(intel_crtc)->pipe))
10512 intel_pipe_config_compare(struct drm_device *dev,
10513 struct intel_crtc_state *current_config,
10514 struct intel_crtc_state *pipe_config)
10516 #define PIPE_CONF_CHECK_X(name) \
10517 if (current_config->name != pipe_config->name) { \
10518 DRM_ERROR("mismatch in " #name " " \
10519 "(expected 0x%08x, found 0x%08x)\n", \
10520 current_config->name, \
10521 pipe_config->name); \
10525 #define PIPE_CONF_CHECK_I(name) \
10526 if (current_config->name != pipe_config->name) { \
10527 DRM_ERROR("mismatch in " #name " " \
10528 "(expected %i, found %i)\n", \
10529 current_config->name, \
10530 pipe_config->name); \
10534 /* This is required for BDW+ where there is only one set of registers for
10535 * switching between high and low RR.
10536 * This macro can be used whenever a comparison has to be made between one
10537 * hw state and multiple sw state variables.
10539 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10540 if ((current_config->name != pipe_config->name) && \
10541 (current_config->alt_name != pipe_config->name)) { \
10542 DRM_ERROR("mismatch in " #name " " \
10543 "(expected %i or %i, found %i)\n", \
10544 current_config->name, \
10545 current_config->alt_name, \
10546 pipe_config->name); \
10550 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10551 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10552 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10553 "(expected %i, found %i)\n", \
10554 current_config->name & (mask), \
10555 pipe_config->name & (mask)); \
10559 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10560 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10561 DRM_ERROR("mismatch in " #name " " \
10562 "(expected %i, found %i)\n", \
10563 current_config->name, \
10564 pipe_config->name); \
10568 #define PIPE_CONF_QUIRK(quirk) \
10569 ((current_config->quirks | pipe_config->quirks) & (quirk))
10571 PIPE_CONF_CHECK_I(cpu_transcoder);
10573 PIPE_CONF_CHECK_I(has_pch_encoder);
10574 PIPE_CONF_CHECK_I(fdi_lanes);
10575 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10576 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10577 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10578 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10579 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10581 PIPE_CONF_CHECK_I(has_dp_encoder);
10583 if (INTEL_INFO(dev)->gen < 8) {
10584 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10585 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10586 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10587 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10588 PIPE_CONF_CHECK_I(dp_m_n.tu);
10590 if (current_config->has_drrs) {
10591 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10592 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10593 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10594 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10595 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10598 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10599 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10600 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10601 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10602 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10605 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10606 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10607 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10608 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10609 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10610 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10612 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10613 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10614 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10615 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10616 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10617 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10619 PIPE_CONF_CHECK_I(pixel_multiplier);
10620 PIPE_CONF_CHECK_I(has_hdmi_sink);
10621 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10622 IS_VALLEYVIEW(dev))
10623 PIPE_CONF_CHECK_I(limited_color_range);
10624 PIPE_CONF_CHECK_I(has_infoframe);
10626 PIPE_CONF_CHECK_I(has_audio);
10628 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10629 DRM_MODE_FLAG_INTERLACE);
10631 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10632 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10633 DRM_MODE_FLAG_PHSYNC);
10634 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10635 DRM_MODE_FLAG_NHSYNC);
10636 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10637 DRM_MODE_FLAG_PVSYNC);
10638 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10639 DRM_MODE_FLAG_NVSYNC);
10642 PIPE_CONF_CHECK_I(pipe_src_w);
10643 PIPE_CONF_CHECK_I(pipe_src_h);
10646 * FIXME: BIOS likes to set up a cloned config with lvds+external
10647 * screen. Since we don't yet re-compute the pipe config when moving
10648 * just the lvds port away to another pipe the sw tracking won't match.
10650 * Proper atomic modesets with recomputed global state will fix this.
10651 * Until then just don't check gmch state for inherited modes.
10653 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10654 PIPE_CONF_CHECK_I(gmch_pfit.control);
10655 /* pfit ratios are autocomputed by the hw on gen4+ */
10656 if (INTEL_INFO(dev)->gen < 4)
10657 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10658 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10661 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10662 if (current_config->pch_pfit.enabled) {
10663 PIPE_CONF_CHECK_I(pch_pfit.pos);
10664 PIPE_CONF_CHECK_I(pch_pfit.size);
10667 /* BDW+ don't expose a synchronous way to read the state */
10668 if (IS_HASWELL(dev))
10669 PIPE_CONF_CHECK_I(ips_enabled);
10671 PIPE_CONF_CHECK_I(double_wide);
10673 PIPE_CONF_CHECK_X(ddi_pll_sel);
10675 PIPE_CONF_CHECK_I(shared_dpll);
10676 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10677 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10678 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10679 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10680 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10681 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10682 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10683 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10685 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10686 PIPE_CONF_CHECK_I(pipe_bpp);
10688 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10689 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10691 #undef PIPE_CONF_CHECK_X
10692 #undef PIPE_CONF_CHECK_I
10693 #undef PIPE_CONF_CHECK_I_ALT
10694 #undef PIPE_CONF_CHECK_FLAGS
10695 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10696 #undef PIPE_CONF_QUIRK
10701 static void check_wm_state(struct drm_device *dev)
10703 struct drm_i915_private *dev_priv = dev->dev_private;
10704 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10705 struct intel_crtc *intel_crtc;
10708 if (INTEL_INFO(dev)->gen < 9)
10711 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10712 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10714 for_each_intel_crtc(dev, intel_crtc) {
10715 struct skl_ddb_entry *hw_entry, *sw_entry;
10716 const enum pipe pipe = intel_crtc->pipe;
10718 if (!intel_crtc->active)
10722 for_each_plane(pipe, plane) {
10723 hw_entry = &hw_ddb.plane[pipe][plane];
10724 sw_entry = &sw_ddb->plane[pipe][plane];
10726 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10729 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10730 "(expected (%u,%u), found (%u,%u))\n",
10731 pipe_name(pipe), plane + 1,
10732 sw_entry->start, sw_entry->end,
10733 hw_entry->start, hw_entry->end);
10737 hw_entry = &hw_ddb.cursor[pipe];
10738 sw_entry = &sw_ddb->cursor[pipe];
10740 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10743 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10744 "(expected (%u,%u), found (%u,%u))\n",
10746 sw_entry->start, sw_entry->end,
10747 hw_entry->start, hw_entry->end);
10752 check_connector_state(struct drm_device *dev)
10754 struct intel_connector *connector;
10756 list_for_each_entry(connector, &dev->mode_config.connector_list,
10758 /* This also checks the encoder/connector hw state with the
10759 * ->get_hw_state callbacks. */
10760 intel_connector_check_state(connector);
10762 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10763 "connector's staged encoder doesn't match current encoder\n");
10768 check_encoder_state(struct drm_device *dev)
10770 struct intel_encoder *encoder;
10771 struct intel_connector *connector;
10773 for_each_intel_encoder(dev, encoder) {
10774 bool enabled = false;
10775 bool active = false;
10776 enum pipe pipe, tracked_pipe;
10778 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10779 encoder->base.base.id,
10780 encoder->base.name);
10782 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10783 "encoder's stage crtc doesn't match current crtc\n");
10784 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10785 "encoder's active_connectors set, but no crtc\n");
10787 list_for_each_entry(connector, &dev->mode_config.connector_list,
10789 if (connector->base.encoder != &encoder->base)
10792 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10796 * for MST connectors if we unplug the connector is gone
10797 * away but the encoder is still connected to a crtc
10798 * until a modeset happens in response to the hotplug.
10800 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10803 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10804 "encoder's enabled state mismatch "
10805 "(expected %i, found %i)\n",
10806 !!encoder->base.crtc, enabled);
10807 I915_STATE_WARN(active && !encoder->base.crtc,
10808 "active encoder with no crtc\n");
10810 I915_STATE_WARN(encoder->connectors_active != active,
10811 "encoder's computed active state doesn't match tracked active state "
10812 "(expected %i, found %i)\n", active, encoder->connectors_active);
10814 active = encoder->get_hw_state(encoder, &pipe);
10815 I915_STATE_WARN(active != encoder->connectors_active,
10816 "encoder's hw state doesn't match sw tracking "
10817 "(expected %i, found %i)\n",
10818 encoder->connectors_active, active);
10820 if (!encoder->base.crtc)
10823 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10824 I915_STATE_WARN(active && pipe != tracked_pipe,
10825 "active encoder's pipe doesn't match"
10826 "(expected %i, found %i)\n",
10827 tracked_pipe, pipe);
10833 check_crtc_state(struct drm_device *dev)
10835 struct drm_i915_private *dev_priv = dev->dev_private;
10836 struct intel_crtc *crtc;
10837 struct intel_encoder *encoder;
10838 struct intel_crtc_state pipe_config;
10840 for_each_intel_crtc(dev, crtc) {
10841 bool enabled = false;
10842 bool active = false;
10844 memset(&pipe_config, 0, sizeof(pipe_config));
10846 DRM_DEBUG_KMS("[CRTC:%d]\n",
10847 crtc->base.base.id);
10849 I915_STATE_WARN(crtc->active && !crtc->base.enabled,
10850 "active crtc, but not enabled in sw tracking\n");
10852 for_each_intel_encoder(dev, encoder) {
10853 if (encoder->base.crtc != &crtc->base)
10856 if (encoder->connectors_active)
10860 I915_STATE_WARN(active != crtc->active,
10861 "crtc's computed active state doesn't match tracked active state "
10862 "(expected %i, found %i)\n", active, crtc->active);
10863 I915_STATE_WARN(enabled != crtc->base.enabled,
10864 "crtc's computed enabled state doesn't match tracked enabled state "
10865 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10867 active = dev_priv->display.get_pipe_config(crtc,
10870 /* hw state is inconsistent with the pipe quirk */
10871 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10872 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10873 active = crtc->active;
10875 for_each_intel_encoder(dev, encoder) {
10877 if (encoder->base.crtc != &crtc->base)
10879 if (encoder->get_hw_state(encoder, &pipe))
10880 encoder->get_config(encoder, &pipe_config);
10883 I915_STATE_WARN(crtc->active != active,
10884 "crtc active state doesn't match with hw state "
10885 "(expected %i, found %i)\n", crtc->active, active);
10888 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10889 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10890 intel_dump_pipe_config(crtc, &pipe_config,
10892 intel_dump_pipe_config(crtc, crtc->config,
10899 check_shared_dpll_state(struct drm_device *dev)
10901 struct drm_i915_private *dev_priv = dev->dev_private;
10902 struct intel_crtc *crtc;
10903 struct intel_dpll_hw_state dpll_hw_state;
10906 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10907 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10908 int enabled_crtcs = 0, active_crtcs = 0;
10911 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10913 DRM_DEBUG_KMS("%s\n", pll->name);
10915 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10917 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10918 "more active pll users than references: %i vs %i\n",
10919 pll->active, hweight32(pll->config.crtc_mask));
10920 I915_STATE_WARN(pll->active && !pll->on,
10921 "pll in active use but not on in sw tracking\n");
10922 I915_STATE_WARN(pll->on && !pll->active,
10923 "pll in on but not on in use in sw tracking\n");
10924 I915_STATE_WARN(pll->on != active,
10925 "pll on state mismatch (expected %i, found %i)\n",
10928 for_each_intel_crtc(dev, crtc) {
10929 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10931 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10934 I915_STATE_WARN(pll->active != active_crtcs,
10935 "pll active crtcs mismatch (expected %i, found %i)\n",
10936 pll->active, active_crtcs);
10937 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10938 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10939 hweight32(pll->config.crtc_mask), enabled_crtcs);
10941 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10942 sizeof(dpll_hw_state)),
10943 "pll hw state mismatch\n");
10948 intel_modeset_check_state(struct drm_device *dev)
10950 check_wm_state(dev);
10951 check_connector_state(dev);
10952 check_encoder_state(dev);
10953 check_crtc_state(dev);
10954 check_shared_dpll_state(dev);
10957 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10961 * FDI already provided one idea for the dotclock.
10962 * Yell if the encoder disagrees.
10964 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10965 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10966 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10969 static void update_scanline_offset(struct intel_crtc *crtc)
10971 struct drm_device *dev = crtc->base.dev;
10974 * The scanline counter increments at the leading edge of hsync.
10976 * On most platforms it starts counting from vtotal-1 on the
10977 * first active line. That means the scanline counter value is
10978 * always one less than what we would expect. Ie. just after
10979 * start of vblank, which also occurs at start of hsync (on the
10980 * last active line), the scanline counter will read vblank_start-1.
10982 * On gen2 the scanline counter starts counting from 1 instead
10983 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10984 * to keep the value positive), instead of adding one.
10986 * On HSW+ the behaviour of the scanline counter depends on the output
10987 * type. For DP ports it behaves like most other platforms, but on HDMI
10988 * there's an extra 1 line difference. So we need to add two instead of
10989 * one to the value.
10991 if (IS_GEN2(dev)) {
10992 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
10995 vtotal = mode->crtc_vtotal;
10996 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10999 crtc->scanline_offset = vtotal - 1;
11000 } else if (HAS_DDI(dev) &&
11001 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11002 crtc->scanline_offset = 2;
11004 crtc->scanline_offset = 1;
11007 static struct intel_crtc_state *
11008 intel_modeset_compute_config(struct drm_crtc *crtc,
11009 struct drm_display_mode *mode,
11010 struct drm_framebuffer *fb,
11011 unsigned *modeset_pipes,
11012 unsigned *prepare_pipes,
11013 unsigned *disable_pipes)
11015 struct intel_crtc_state *pipe_config = NULL;
11017 intel_modeset_affected_pipes(crtc, modeset_pipes,
11018 prepare_pipes, disable_pipes);
11020 if ((*modeset_pipes) == 0)
11024 * Note this needs changes when we start tracking multiple modes
11025 * and crtcs. At that point we'll need to compute the whole config
11026 * (i.e. one pipe_config for each crtc) rather than just the one
11029 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11030 if (IS_ERR(pipe_config)) {
11033 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11037 return pipe_config;
11040 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11041 unsigned modeset_pipes,
11042 unsigned disable_pipes)
11044 struct drm_i915_private *dev_priv = to_i915(dev);
11045 unsigned clear_pipes = modeset_pipes | disable_pipes;
11046 struct intel_crtc *intel_crtc;
11049 if (!dev_priv->display.crtc_compute_clock)
11052 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11056 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11057 struct intel_crtc_state *state = intel_crtc->new_config;
11058 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11061 intel_shared_dpll_abort_config(dev_priv);
11070 static int __intel_set_mode(struct drm_crtc *crtc,
11071 struct drm_display_mode *mode,
11072 int x, int y, struct drm_framebuffer *fb,
11073 struct intel_crtc_state *pipe_config,
11074 unsigned modeset_pipes,
11075 unsigned prepare_pipes,
11076 unsigned disable_pipes)
11078 struct drm_device *dev = crtc->dev;
11079 struct drm_i915_private *dev_priv = dev->dev_private;
11080 struct drm_display_mode *saved_mode;
11081 struct intel_crtc *intel_crtc;
11084 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11088 *saved_mode = crtc->mode;
11091 to_intel_crtc(crtc)->new_config = pipe_config;
11094 * See if the config requires any additional preparation, e.g.
11095 * to adjust global state with pipes off. We need to do this
11096 * here so we can get the modeset_pipe updated config for the new
11097 * mode set on this crtc. For other crtcs we need to use the
11098 * adjusted_mode bits in the crtc directly.
11100 if (IS_VALLEYVIEW(dev)) {
11101 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11103 /* may have added more to prepare_pipes than we should */
11104 prepare_pipes &= ~disable_pipes;
11107 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11111 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11112 intel_crtc_disable(&intel_crtc->base);
11114 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11115 if (intel_crtc->base.enabled)
11116 dev_priv->display.crtc_disable(&intel_crtc->base);
11119 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11120 * to set it here already despite that we pass it down the callchain.
11122 * Note we'll need to fix this up when we start tracking multiple
11123 * pipes; here we assume a single modeset_pipe and only track the
11124 * single crtc and mode.
11126 if (modeset_pipes) {
11127 crtc->mode = *mode;
11128 /* mode_set/enable/disable functions rely on a correct pipe
11130 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11133 * Calculate and store various constants which
11134 * are later needed by vblank and swap-completion
11135 * timestamping. They are derived from true hwmode.
11137 drm_calc_timestamping_constants(crtc,
11138 &pipe_config->base.adjusted_mode);
11141 /* Only after disabling all output pipelines that will be changed can we
11142 * update the the output configuration. */
11143 intel_modeset_update_state(dev, prepare_pipes);
11145 modeset_update_crtc_power_domains(dev);
11147 /* Set up the DPLL and any encoders state that needs to adjust or depend
11150 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11151 struct drm_plane *primary = intel_crtc->base.primary;
11152 int vdisplay, hdisplay;
11154 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11155 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11157 hdisplay, vdisplay,
11159 hdisplay << 16, vdisplay << 16);
11162 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11163 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11164 update_scanline_offset(intel_crtc);
11166 dev_priv->display.crtc_enable(&intel_crtc->base);
11169 /* FIXME: add subpixel order */
11171 if (ret && crtc->enabled)
11172 crtc->mode = *saved_mode;
11178 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11179 struct drm_display_mode *mode,
11180 int x, int y, struct drm_framebuffer *fb,
11181 struct intel_crtc_state *pipe_config,
11182 unsigned modeset_pipes,
11183 unsigned prepare_pipes,
11184 unsigned disable_pipes)
11188 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11189 prepare_pipes, disable_pipes);
11192 intel_modeset_check_state(crtc->dev);
11197 static int intel_set_mode(struct drm_crtc *crtc,
11198 struct drm_display_mode *mode,
11199 int x, int y, struct drm_framebuffer *fb)
11201 struct intel_crtc_state *pipe_config;
11202 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11204 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11209 if (IS_ERR(pipe_config))
11210 return PTR_ERR(pipe_config);
11212 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11213 modeset_pipes, prepare_pipes,
11217 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11219 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11222 #undef for_each_intel_crtc_masked
11224 static void intel_set_config_free(struct intel_set_config *config)
11229 kfree(config->save_connector_encoders);
11230 kfree(config->save_encoder_crtcs);
11231 kfree(config->save_crtc_enabled);
11235 static int intel_set_config_save_state(struct drm_device *dev,
11236 struct intel_set_config *config)
11238 struct drm_crtc *crtc;
11239 struct drm_encoder *encoder;
11240 struct drm_connector *connector;
11243 config->save_crtc_enabled =
11244 kcalloc(dev->mode_config.num_crtc,
11245 sizeof(bool), GFP_KERNEL);
11246 if (!config->save_crtc_enabled)
11249 config->save_encoder_crtcs =
11250 kcalloc(dev->mode_config.num_encoder,
11251 sizeof(struct drm_crtc *), GFP_KERNEL);
11252 if (!config->save_encoder_crtcs)
11255 config->save_connector_encoders =
11256 kcalloc(dev->mode_config.num_connector,
11257 sizeof(struct drm_encoder *), GFP_KERNEL);
11258 if (!config->save_connector_encoders)
11261 /* Copy data. Note that driver private data is not affected.
11262 * Should anything bad happen only the expected state is
11263 * restored, not the drivers personal bookkeeping.
11266 for_each_crtc(dev, crtc) {
11267 config->save_crtc_enabled[count++] = crtc->enabled;
11271 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11272 config->save_encoder_crtcs[count++] = encoder->crtc;
11276 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11277 config->save_connector_encoders[count++] = connector->encoder;
11283 static void intel_set_config_restore_state(struct drm_device *dev,
11284 struct intel_set_config *config)
11286 struct intel_crtc *crtc;
11287 struct intel_encoder *encoder;
11288 struct intel_connector *connector;
11292 for_each_intel_crtc(dev, crtc) {
11293 crtc->new_enabled = config->save_crtc_enabled[count++];
11295 if (crtc->new_enabled)
11296 crtc->new_config = crtc->config;
11298 crtc->new_config = NULL;
11302 for_each_intel_encoder(dev, encoder) {
11303 encoder->new_crtc =
11304 to_intel_crtc(config->save_encoder_crtcs[count++]);
11308 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11309 connector->new_encoder =
11310 to_intel_encoder(config->save_connector_encoders[count++]);
11315 is_crtc_connector_off(struct drm_mode_set *set)
11319 if (set->num_connectors == 0)
11322 if (WARN_ON(set->connectors == NULL))
11325 for (i = 0; i < set->num_connectors; i++)
11326 if (set->connectors[i]->encoder &&
11327 set->connectors[i]->encoder->crtc == set->crtc &&
11328 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11335 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11336 struct intel_set_config *config)
11339 /* We should be able to check here if the fb has the same properties
11340 * and then just flip_or_move it */
11341 if (is_crtc_connector_off(set)) {
11342 config->mode_changed = true;
11343 } else if (set->crtc->primary->fb != set->fb) {
11345 * If we have no fb, we can only flip as long as the crtc is
11346 * active, otherwise we need a full mode set. The crtc may
11347 * be active if we've only disabled the primary plane, or
11348 * in fastboot situations.
11350 if (set->crtc->primary->fb == NULL) {
11351 struct intel_crtc *intel_crtc =
11352 to_intel_crtc(set->crtc);
11354 if (intel_crtc->active) {
11355 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11356 config->fb_changed = true;
11358 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11359 config->mode_changed = true;
11361 } else if (set->fb == NULL) {
11362 config->mode_changed = true;
11363 } else if (set->fb->pixel_format !=
11364 set->crtc->primary->fb->pixel_format) {
11365 config->mode_changed = true;
11367 config->fb_changed = true;
11371 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11372 config->fb_changed = true;
11374 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11375 DRM_DEBUG_KMS("modes are different, full mode set\n");
11376 drm_mode_debug_printmodeline(&set->crtc->mode);
11377 drm_mode_debug_printmodeline(set->mode);
11378 config->mode_changed = true;
11381 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11382 set->crtc->base.id, config->mode_changed, config->fb_changed);
11386 intel_modeset_stage_output_state(struct drm_device *dev,
11387 struct drm_mode_set *set,
11388 struct intel_set_config *config)
11390 struct intel_connector *connector;
11391 struct intel_encoder *encoder;
11392 struct intel_crtc *crtc;
11395 /* The upper layers ensure that we either disable a crtc or have a list
11396 * of connectors. For paranoia, double-check this. */
11397 WARN_ON(!set->fb && (set->num_connectors != 0));
11398 WARN_ON(set->fb && (set->num_connectors == 0));
11400 list_for_each_entry(connector, &dev->mode_config.connector_list,
11402 /* Otherwise traverse passed in connector list and get encoders
11404 for (ro = 0; ro < set->num_connectors; ro++) {
11405 if (set->connectors[ro] == &connector->base) {
11406 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11411 /* If we disable the crtc, disable all its connectors. Also, if
11412 * the connector is on the changing crtc but not on the new
11413 * connector list, disable it. */
11414 if ((!set->fb || ro == set->num_connectors) &&
11415 connector->base.encoder &&
11416 connector->base.encoder->crtc == set->crtc) {
11417 connector->new_encoder = NULL;
11419 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11420 connector->base.base.id,
11421 connector->base.name);
11425 if (&connector->new_encoder->base != connector->base.encoder) {
11426 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11427 config->mode_changed = true;
11430 /* connector->new_encoder is now updated for all connectors. */
11432 /* Update crtc of enabled connectors. */
11433 list_for_each_entry(connector, &dev->mode_config.connector_list,
11435 struct drm_crtc *new_crtc;
11437 if (!connector->new_encoder)
11440 new_crtc = connector->new_encoder->base.crtc;
11442 for (ro = 0; ro < set->num_connectors; ro++) {
11443 if (set->connectors[ro] == &connector->base)
11444 new_crtc = set->crtc;
11447 /* Make sure the new CRTC will work with the encoder */
11448 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11452 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11454 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11455 connector->base.base.id,
11456 connector->base.name,
11457 new_crtc->base.id);
11460 /* Check for any encoders that needs to be disabled. */
11461 for_each_intel_encoder(dev, encoder) {
11462 int num_connectors = 0;
11463 list_for_each_entry(connector,
11464 &dev->mode_config.connector_list,
11466 if (connector->new_encoder == encoder) {
11467 WARN_ON(!connector->new_encoder->new_crtc);
11472 if (num_connectors == 0)
11473 encoder->new_crtc = NULL;
11474 else if (num_connectors > 1)
11477 /* Only now check for crtc changes so we don't miss encoders
11478 * that will be disabled. */
11479 if (&encoder->new_crtc->base != encoder->base.crtc) {
11480 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11481 config->mode_changed = true;
11484 /* Now we've also updated encoder->new_crtc for all encoders. */
11485 list_for_each_entry(connector, &dev->mode_config.connector_list,
11487 if (connector->new_encoder)
11488 if (connector->new_encoder != connector->encoder)
11489 connector->encoder = connector->new_encoder;
11491 for_each_intel_crtc(dev, crtc) {
11492 crtc->new_enabled = false;
11494 for_each_intel_encoder(dev, encoder) {
11495 if (encoder->new_crtc == crtc) {
11496 crtc->new_enabled = true;
11501 if (crtc->new_enabled != crtc->base.enabled) {
11502 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11503 crtc->new_enabled ? "en" : "dis");
11504 config->mode_changed = true;
11507 if (crtc->new_enabled)
11508 crtc->new_config = crtc->config;
11510 crtc->new_config = NULL;
11516 static void disable_crtc_nofb(struct intel_crtc *crtc)
11518 struct drm_device *dev = crtc->base.dev;
11519 struct intel_encoder *encoder;
11520 struct intel_connector *connector;
11522 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11523 pipe_name(crtc->pipe));
11525 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11526 if (connector->new_encoder &&
11527 connector->new_encoder->new_crtc == crtc)
11528 connector->new_encoder = NULL;
11531 for_each_intel_encoder(dev, encoder) {
11532 if (encoder->new_crtc == crtc)
11533 encoder->new_crtc = NULL;
11536 crtc->new_enabled = false;
11537 crtc->new_config = NULL;
11540 static int intel_crtc_set_config(struct drm_mode_set *set)
11542 struct drm_device *dev;
11543 struct drm_mode_set save_set;
11544 struct intel_set_config *config;
11545 struct intel_crtc_state *pipe_config;
11546 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11550 BUG_ON(!set->crtc);
11551 BUG_ON(!set->crtc->helper_private);
11553 /* Enforce sane interface api - has been abused by the fb helper. */
11554 BUG_ON(!set->mode && set->fb);
11555 BUG_ON(set->fb && set->num_connectors == 0);
11558 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11559 set->crtc->base.id, set->fb->base.id,
11560 (int)set->num_connectors, set->x, set->y);
11562 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11565 dev = set->crtc->dev;
11568 config = kzalloc(sizeof(*config), GFP_KERNEL);
11572 ret = intel_set_config_save_state(dev, config);
11576 save_set.crtc = set->crtc;
11577 save_set.mode = &set->crtc->mode;
11578 save_set.x = set->crtc->x;
11579 save_set.y = set->crtc->y;
11580 save_set.fb = set->crtc->primary->fb;
11582 /* Compute whether we need a full modeset, only an fb base update or no
11583 * change at all. In the future we might also check whether only the
11584 * mode changed, e.g. for LVDS where we only change the panel fitter in
11586 intel_set_config_compute_mode_changes(set, config);
11588 ret = intel_modeset_stage_output_state(dev, set, config);
11592 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11597 if (IS_ERR(pipe_config)) {
11598 ret = PTR_ERR(pipe_config);
11600 } else if (pipe_config) {
11601 if (pipe_config->has_audio !=
11602 to_intel_crtc(set->crtc)->config->has_audio)
11603 config->mode_changed = true;
11606 * Note we have an issue here with infoframes: current code
11607 * only updates them on the full mode set path per hw
11608 * requirements. So here we should be checking for any
11609 * required changes and forcing a mode set.
11613 /* set_mode will free it in the mode_changed case */
11614 if (!config->mode_changed)
11615 kfree(pipe_config);
11617 intel_update_pipe_size(to_intel_crtc(set->crtc));
11619 if (config->mode_changed) {
11620 ret = intel_set_mode_pipes(set->crtc, set->mode,
11621 set->x, set->y, set->fb, pipe_config,
11622 modeset_pipes, prepare_pipes,
11624 } else if (config->fb_changed) {
11625 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11626 struct drm_plane *primary = set->crtc->primary;
11627 int vdisplay, hdisplay;
11629 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11630 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11631 0, 0, hdisplay, vdisplay,
11632 set->x << 16, set->y << 16,
11633 hdisplay << 16, vdisplay << 16);
11636 * We need to make sure the primary plane is re-enabled if it
11637 * has previously been turned off.
11639 if (!intel_crtc->primary_enabled && ret == 0) {
11640 WARN_ON(!intel_crtc->active);
11641 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11645 * In the fastboot case this may be our only check of the
11646 * state after boot. It would be better to only do it on
11647 * the first update, but we don't have a nice way of doing that
11648 * (and really, set_config isn't used much for high freq page
11649 * flipping, so increasing its cost here shouldn't be a big
11652 if (i915.fastboot && ret == 0)
11653 intel_modeset_check_state(set->crtc->dev);
11657 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11658 set->crtc->base.id, ret);
11660 intel_set_config_restore_state(dev, config);
11663 * HACK: if the pipe was on, but we didn't have a framebuffer,
11664 * force the pipe off to avoid oopsing in the modeset code
11665 * due to fb==NULL. This should only happen during boot since
11666 * we don't yet reconstruct the FB from the hardware state.
11668 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11669 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11671 /* Try to restore the config */
11672 if (config->mode_changed &&
11673 intel_set_mode(save_set.crtc, save_set.mode,
11674 save_set.x, save_set.y, save_set.fb))
11675 DRM_ERROR("failed to restore config after modeset failure\n");
11679 intel_set_config_free(config);
11683 static const struct drm_crtc_funcs intel_crtc_funcs = {
11684 .gamma_set = intel_crtc_gamma_set,
11685 .set_config = intel_crtc_set_config,
11686 .destroy = intel_crtc_destroy,
11687 .page_flip = intel_crtc_page_flip,
11688 .atomic_duplicate_state = intel_crtc_duplicate_state,
11689 .atomic_destroy_state = intel_crtc_destroy_state,
11692 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11693 struct intel_shared_dpll *pll,
11694 struct intel_dpll_hw_state *hw_state)
11698 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11701 val = I915_READ(PCH_DPLL(pll->id));
11702 hw_state->dpll = val;
11703 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11704 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11706 return val & DPLL_VCO_ENABLE;
11709 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11710 struct intel_shared_dpll *pll)
11712 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11713 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11716 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11717 struct intel_shared_dpll *pll)
11719 /* PCH refclock must be enabled first */
11720 ibx_assert_pch_refclk_enabled(dev_priv);
11722 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11724 /* Wait for the clocks to stabilize. */
11725 POSTING_READ(PCH_DPLL(pll->id));
11728 /* The pixel multiplier can only be updated once the
11729 * DPLL is enabled and the clocks are stable.
11731 * So write it again.
11733 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11734 POSTING_READ(PCH_DPLL(pll->id));
11738 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11739 struct intel_shared_dpll *pll)
11741 struct drm_device *dev = dev_priv->dev;
11742 struct intel_crtc *crtc;
11744 /* Make sure no transcoder isn't still depending on us. */
11745 for_each_intel_crtc(dev, crtc) {
11746 if (intel_crtc_to_shared_dpll(crtc) == pll)
11747 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11750 I915_WRITE(PCH_DPLL(pll->id), 0);
11751 POSTING_READ(PCH_DPLL(pll->id));
11755 static char *ibx_pch_dpll_names[] = {
11760 static void ibx_pch_dpll_init(struct drm_device *dev)
11762 struct drm_i915_private *dev_priv = dev->dev_private;
11765 dev_priv->num_shared_dpll = 2;
11767 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11768 dev_priv->shared_dplls[i].id = i;
11769 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11770 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11771 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11772 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11773 dev_priv->shared_dplls[i].get_hw_state =
11774 ibx_pch_dpll_get_hw_state;
11778 static void intel_shared_dpll_init(struct drm_device *dev)
11780 struct drm_i915_private *dev_priv = dev->dev_private;
11783 intel_ddi_pll_init(dev);
11784 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11785 ibx_pch_dpll_init(dev);
11787 dev_priv->num_shared_dpll = 0;
11789 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11793 * intel_prepare_plane_fb - Prepare fb for usage on plane
11794 * @plane: drm plane to prepare for
11795 * @fb: framebuffer to prepare for presentation
11797 * Prepares a framebuffer for usage on a display plane. Generally this
11798 * involves pinning the underlying object and updating the frontbuffer tracking
11799 * bits. Some older platforms need special physical address handling for
11802 * Returns 0 on success, negative error code on failure.
11805 intel_prepare_plane_fb(struct drm_plane *plane,
11806 struct drm_framebuffer *fb)
11808 struct drm_device *dev = plane->dev;
11809 struct intel_plane *intel_plane = to_intel_plane(plane);
11810 enum pipe pipe = intel_plane->pipe;
11811 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11812 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11813 unsigned frontbuffer_bits = 0;
11819 switch (plane->type) {
11820 case DRM_PLANE_TYPE_PRIMARY:
11821 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11823 case DRM_PLANE_TYPE_CURSOR:
11824 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11826 case DRM_PLANE_TYPE_OVERLAY:
11827 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11831 mutex_lock(&dev->struct_mutex);
11833 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11834 INTEL_INFO(dev)->cursor_needs_physical) {
11835 int align = IS_I830(dev) ? 16 * 1024 : 256;
11836 ret = i915_gem_object_attach_phys(obj, align);
11838 DRM_DEBUG_KMS("failed to attach phys object\n");
11840 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11844 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11846 mutex_unlock(&dev->struct_mutex);
11852 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11853 * @plane: drm plane to clean up for
11854 * @fb: old framebuffer that was on plane
11856 * Cleans up a framebuffer that has just been removed from a plane.
11859 intel_cleanup_plane_fb(struct drm_plane *plane,
11860 struct drm_framebuffer *fb)
11862 struct drm_device *dev = plane->dev;
11863 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11868 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11869 !INTEL_INFO(dev)->cursor_needs_physical) {
11870 mutex_lock(&dev->struct_mutex);
11871 intel_unpin_fb_obj(obj);
11872 mutex_unlock(&dev->struct_mutex);
11877 intel_check_primary_plane(struct drm_plane *plane,
11878 struct intel_plane_state *state)
11880 struct drm_device *dev = plane->dev;
11881 struct drm_i915_private *dev_priv = dev->dev_private;
11882 struct drm_crtc *crtc = state->base.crtc;
11883 struct intel_crtc *intel_crtc;
11884 struct drm_framebuffer *fb = state->base.fb;
11885 struct drm_rect *dest = &state->dst;
11886 struct drm_rect *src = &state->src;
11887 const struct drm_rect *clip = &state->clip;
11890 crtc = crtc ? crtc : plane->crtc;
11891 intel_crtc = to_intel_crtc(crtc);
11893 ret = drm_plane_helper_check_update(plane, crtc, fb,
11895 DRM_PLANE_HELPER_NO_SCALING,
11896 DRM_PLANE_HELPER_NO_SCALING,
11897 false, true, &state->visible);
11901 if (intel_crtc->active) {
11902 intel_crtc->atomic.wait_for_flips = true;
11905 * FBC does not work on some platforms for rotated
11906 * planes, so disable it when rotation is not 0 and
11907 * update it when rotation is set back to 0.
11909 * FIXME: This is redundant with the fbc update done in
11910 * the primary plane enable function except that that
11911 * one is done too late. We eventually need to unify
11914 if (intel_crtc->primary_enabled &&
11915 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11916 dev_priv->fbc.plane == intel_crtc->plane &&
11917 state->base.rotation != BIT(DRM_ROTATE_0)) {
11918 intel_crtc->atomic.disable_fbc = true;
11921 if (state->visible) {
11923 * BDW signals flip done immediately if the plane
11924 * is disabled, even if the plane enable is already
11925 * armed to occur at the next vblank :(
11927 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11928 intel_crtc->atomic.wait_vblank = true;
11931 intel_crtc->atomic.fb_bits |=
11932 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11934 intel_crtc->atomic.update_fbc = true;
11941 intel_commit_primary_plane(struct drm_plane *plane,
11942 struct intel_plane_state *state)
11944 struct drm_crtc *crtc = state->base.crtc;
11945 struct drm_framebuffer *fb = state->base.fb;
11946 struct drm_device *dev = plane->dev;
11947 struct drm_i915_private *dev_priv = dev->dev_private;
11948 struct intel_crtc *intel_crtc;
11949 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11950 struct intel_plane *intel_plane = to_intel_plane(plane);
11951 struct drm_rect *src = &state->src;
11953 crtc = crtc ? crtc : plane->crtc;
11954 intel_crtc = to_intel_crtc(crtc);
11957 crtc->x = src->x1 >> 16;
11958 crtc->y = src->y1 >> 16;
11960 intel_plane->obj = obj;
11962 if (intel_crtc->active) {
11963 if (state->visible) {
11964 /* FIXME: kill this fastboot hack */
11965 intel_update_pipe_size(intel_crtc);
11967 intel_crtc->primary_enabled = true;
11969 dev_priv->display.update_primary_plane(crtc, plane->fb,
11973 * If clipping results in a non-visible primary plane,
11974 * we'll disable the primary plane. Note that this is
11975 * a bit different than what happens if userspace
11976 * explicitly disables the plane by passing fb=0
11977 * because plane->fb still gets set and pinned.
11979 intel_disable_primary_hw_plane(plane, crtc);
11984 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
11986 struct drm_device *dev = crtc->dev;
11987 struct drm_i915_private *dev_priv = dev->dev_private;
11988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11989 struct intel_plane *intel_plane;
11990 struct drm_plane *p;
11991 unsigned fb_bits = 0;
11993 /* Track fb's for any planes being disabled */
11994 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
11995 intel_plane = to_intel_plane(p);
11997 if (intel_crtc->atomic.disabled_planes &
11998 (1 << drm_plane_index(p))) {
12000 case DRM_PLANE_TYPE_PRIMARY:
12001 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12003 case DRM_PLANE_TYPE_CURSOR:
12004 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12006 case DRM_PLANE_TYPE_OVERLAY:
12007 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12011 mutex_lock(&dev->struct_mutex);
12012 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12013 mutex_unlock(&dev->struct_mutex);
12017 if (intel_crtc->atomic.wait_for_flips)
12018 intel_crtc_wait_for_pending_flips(crtc);
12020 if (intel_crtc->atomic.disable_fbc)
12021 intel_fbc_disable(dev);
12023 if (intel_crtc->atomic.pre_disable_primary)
12024 intel_pre_disable_primary(crtc);
12026 if (intel_crtc->atomic.update_wm)
12027 intel_update_watermarks(crtc);
12029 intel_runtime_pm_get(dev_priv);
12031 /* Perform vblank evasion around commit operation */
12032 if (intel_crtc->active)
12033 intel_crtc->atomic.evade =
12034 intel_pipe_update_start(intel_crtc,
12035 &intel_crtc->atomic.start_vbl_count);
12038 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12040 struct drm_device *dev = crtc->dev;
12041 struct drm_i915_private *dev_priv = dev->dev_private;
12042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12043 struct drm_plane *p;
12045 if (intel_crtc->atomic.evade)
12046 intel_pipe_update_end(intel_crtc,
12047 intel_crtc->atomic.start_vbl_count);
12049 intel_runtime_pm_put(dev_priv);
12051 if (intel_crtc->atomic.wait_vblank)
12052 intel_wait_for_vblank(dev, intel_crtc->pipe);
12054 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12056 if (intel_crtc->atomic.update_fbc) {
12057 mutex_lock(&dev->struct_mutex);
12058 intel_fbc_update(dev);
12059 mutex_unlock(&dev->struct_mutex);
12062 if (intel_crtc->atomic.post_enable_primary)
12063 intel_post_enable_primary(crtc);
12065 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12066 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12067 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12070 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12074 * intel_plane_destroy - destroy a plane
12075 * @plane: plane to destroy
12077 * Common destruction function for all types of planes (primary, cursor,
12080 void intel_plane_destroy(struct drm_plane *plane)
12082 struct intel_plane *intel_plane = to_intel_plane(plane);
12083 drm_plane_cleanup(plane);
12084 kfree(intel_plane);
12087 const struct drm_plane_funcs intel_plane_funcs = {
12088 .update_plane = drm_plane_helper_update,
12089 .disable_plane = drm_plane_helper_disable,
12090 .destroy = intel_plane_destroy,
12091 .set_property = drm_atomic_helper_plane_set_property,
12092 .atomic_get_property = intel_plane_atomic_get_property,
12093 .atomic_set_property = intel_plane_atomic_set_property,
12094 .atomic_duplicate_state = intel_plane_duplicate_state,
12095 .atomic_destroy_state = intel_plane_destroy_state,
12099 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12102 struct intel_plane *primary;
12103 struct intel_plane_state *state;
12104 const uint32_t *intel_primary_formats;
12107 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12108 if (primary == NULL)
12111 state = intel_create_plane_state(&primary->base);
12116 primary->base.state = &state->base;
12118 primary->can_scale = false;
12119 primary->max_downscale = 1;
12120 primary->pipe = pipe;
12121 primary->plane = pipe;
12122 primary->check_plane = intel_check_primary_plane;
12123 primary->commit_plane = intel_commit_primary_plane;
12124 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12125 primary->plane = !pipe;
12127 if (INTEL_INFO(dev)->gen <= 3) {
12128 intel_primary_formats = intel_primary_formats_gen2;
12129 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12131 intel_primary_formats = intel_primary_formats_gen4;
12132 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12135 drm_universal_plane_init(dev, &primary->base, 0,
12136 &intel_plane_funcs,
12137 intel_primary_formats, num_formats,
12138 DRM_PLANE_TYPE_PRIMARY);
12140 if (INTEL_INFO(dev)->gen >= 4) {
12141 if (!dev->mode_config.rotation_property)
12142 dev->mode_config.rotation_property =
12143 drm_mode_create_rotation_property(dev,
12144 BIT(DRM_ROTATE_0) |
12145 BIT(DRM_ROTATE_180));
12146 if (dev->mode_config.rotation_property)
12147 drm_object_attach_property(&primary->base.base,
12148 dev->mode_config.rotation_property,
12149 state->base.rotation);
12152 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12154 return &primary->base;
12158 intel_check_cursor_plane(struct drm_plane *plane,
12159 struct intel_plane_state *state)
12161 struct drm_crtc *crtc = state->base.crtc;
12162 struct drm_device *dev = plane->dev;
12163 struct drm_framebuffer *fb = state->base.fb;
12164 struct drm_rect *dest = &state->dst;
12165 struct drm_rect *src = &state->src;
12166 const struct drm_rect *clip = &state->clip;
12167 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12168 struct intel_crtc *intel_crtc;
12172 crtc = crtc ? crtc : plane->crtc;
12173 intel_crtc = to_intel_crtc(crtc);
12175 ret = drm_plane_helper_check_update(plane, crtc, fb,
12177 DRM_PLANE_HELPER_NO_SCALING,
12178 DRM_PLANE_HELPER_NO_SCALING,
12179 true, true, &state->visible);
12184 /* if we want to turn off the cursor ignore width and height */
12188 /* Check for which cursor types we support */
12189 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12190 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12191 state->base.crtc_w, state->base.crtc_h);
12195 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12196 if (obj->base.size < stride * state->base.crtc_h) {
12197 DRM_DEBUG_KMS("buffer is too small\n");
12201 /* we only need to pin inside GTT if cursor is non-phy */
12202 mutex_lock(&dev->struct_mutex);
12203 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12204 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12207 mutex_unlock(&dev->struct_mutex);
12210 if (intel_crtc->active) {
12211 if (intel_crtc->cursor_width != state->base.crtc_w)
12212 intel_crtc->atomic.update_wm = true;
12214 intel_crtc->atomic.fb_bits |=
12215 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12222 intel_commit_cursor_plane(struct drm_plane *plane,
12223 struct intel_plane_state *state)
12225 struct drm_crtc *crtc = state->base.crtc;
12226 struct drm_device *dev = plane->dev;
12227 struct intel_crtc *intel_crtc;
12228 struct intel_plane *intel_plane = to_intel_plane(plane);
12229 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12232 crtc = crtc ? crtc : plane->crtc;
12233 intel_crtc = to_intel_crtc(crtc);
12235 plane->fb = state->base.fb;
12236 crtc->cursor_x = state->base.crtc_x;
12237 crtc->cursor_y = state->base.crtc_y;
12239 intel_plane->obj = obj;
12241 if (intel_crtc->cursor_bo == obj)
12246 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12247 addr = i915_gem_obj_ggtt_offset(obj);
12249 addr = obj->phys_handle->busaddr;
12251 intel_crtc->cursor_addr = addr;
12252 intel_crtc->cursor_bo = obj;
12254 intel_crtc->cursor_width = state->base.crtc_w;
12255 intel_crtc->cursor_height = state->base.crtc_h;
12257 if (intel_crtc->active)
12258 intel_crtc_update_cursor(crtc, state->visible);
12261 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12264 struct intel_plane *cursor;
12265 struct intel_plane_state *state;
12267 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12268 if (cursor == NULL)
12271 state = intel_create_plane_state(&cursor->base);
12276 cursor->base.state = &state->base;
12278 cursor->can_scale = false;
12279 cursor->max_downscale = 1;
12280 cursor->pipe = pipe;
12281 cursor->plane = pipe;
12282 cursor->check_plane = intel_check_cursor_plane;
12283 cursor->commit_plane = intel_commit_cursor_plane;
12285 drm_universal_plane_init(dev, &cursor->base, 0,
12286 &intel_plane_funcs,
12287 intel_cursor_formats,
12288 ARRAY_SIZE(intel_cursor_formats),
12289 DRM_PLANE_TYPE_CURSOR);
12291 if (INTEL_INFO(dev)->gen >= 4) {
12292 if (!dev->mode_config.rotation_property)
12293 dev->mode_config.rotation_property =
12294 drm_mode_create_rotation_property(dev,
12295 BIT(DRM_ROTATE_0) |
12296 BIT(DRM_ROTATE_180));
12297 if (dev->mode_config.rotation_property)
12298 drm_object_attach_property(&cursor->base.base,
12299 dev->mode_config.rotation_property,
12300 state->base.rotation);
12303 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12305 return &cursor->base;
12308 static void intel_crtc_init(struct drm_device *dev, int pipe)
12310 struct drm_i915_private *dev_priv = dev->dev_private;
12311 struct intel_crtc *intel_crtc;
12312 struct intel_crtc_state *crtc_state = NULL;
12313 struct drm_plane *primary = NULL;
12314 struct drm_plane *cursor = NULL;
12317 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12318 if (intel_crtc == NULL)
12321 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12324 intel_crtc_set_state(intel_crtc, crtc_state);
12326 primary = intel_primary_plane_create(dev, pipe);
12330 cursor = intel_cursor_plane_create(dev, pipe);
12334 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12335 cursor, &intel_crtc_funcs);
12339 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12340 for (i = 0; i < 256; i++) {
12341 intel_crtc->lut_r[i] = i;
12342 intel_crtc->lut_g[i] = i;
12343 intel_crtc->lut_b[i] = i;
12347 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12348 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12350 intel_crtc->pipe = pipe;
12351 intel_crtc->plane = pipe;
12352 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12353 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12354 intel_crtc->plane = !pipe;
12357 intel_crtc->cursor_base = ~0;
12358 intel_crtc->cursor_cntl = ~0;
12359 intel_crtc->cursor_size = ~0;
12361 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12362 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12363 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12364 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12366 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12368 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12370 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12375 drm_plane_cleanup(primary);
12377 drm_plane_cleanup(cursor);
12382 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12384 struct drm_encoder *encoder = connector->base.encoder;
12385 struct drm_device *dev = connector->base.dev;
12387 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12389 if (!encoder || WARN_ON(!encoder->crtc))
12390 return INVALID_PIPE;
12392 return to_intel_crtc(encoder->crtc)->pipe;
12395 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12396 struct drm_file *file)
12398 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12399 struct drm_crtc *drmmode_crtc;
12400 struct intel_crtc *crtc;
12402 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12405 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12407 if (!drmmode_crtc) {
12408 DRM_ERROR("no such CRTC id\n");
12412 crtc = to_intel_crtc(drmmode_crtc);
12413 pipe_from_crtc_id->pipe = crtc->pipe;
12418 static int intel_encoder_clones(struct intel_encoder *encoder)
12420 struct drm_device *dev = encoder->base.dev;
12421 struct intel_encoder *source_encoder;
12422 int index_mask = 0;
12425 for_each_intel_encoder(dev, source_encoder) {
12426 if (encoders_cloneable(encoder, source_encoder))
12427 index_mask |= (1 << entry);
12435 static bool has_edp_a(struct drm_device *dev)
12437 struct drm_i915_private *dev_priv = dev->dev_private;
12439 if (!IS_MOBILE(dev))
12442 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12445 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12451 static bool intel_crt_present(struct drm_device *dev)
12453 struct drm_i915_private *dev_priv = dev->dev_private;
12455 if (INTEL_INFO(dev)->gen >= 9)
12458 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12461 if (IS_CHERRYVIEW(dev))
12464 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12470 static void intel_setup_outputs(struct drm_device *dev)
12472 struct drm_i915_private *dev_priv = dev->dev_private;
12473 struct intel_encoder *encoder;
12474 struct drm_connector *connector;
12475 bool dpd_is_edp = false;
12477 intel_lvds_init(dev);
12479 if (intel_crt_present(dev))
12480 intel_crt_init(dev);
12482 if (HAS_DDI(dev)) {
12485 /* Haswell uses DDI functions to detect digital outputs */
12486 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12487 /* DDI A only supports eDP */
12489 intel_ddi_init(dev, PORT_A);
12491 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12493 found = I915_READ(SFUSE_STRAP);
12495 if (found & SFUSE_STRAP_DDIB_DETECTED)
12496 intel_ddi_init(dev, PORT_B);
12497 if (found & SFUSE_STRAP_DDIC_DETECTED)
12498 intel_ddi_init(dev, PORT_C);
12499 if (found & SFUSE_STRAP_DDID_DETECTED)
12500 intel_ddi_init(dev, PORT_D);
12501 } else if (HAS_PCH_SPLIT(dev)) {
12503 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12505 if (has_edp_a(dev))
12506 intel_dp_init(dev, DP_A, PORT_A);
12508 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12509 /* PCH SDVOB multiplex with HDMIB */
12510 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12512 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12513 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12514 intel_dp_init(dev, PCH_DP_B, PORT_B);
12517 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12518 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12520 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12521 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12523 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12524 intel_dp_init(dev, PCH_DP_C, PORT_C);
12526 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12527 intel_dp_init(dev, PCH_DP_D, PORT_D);
12528 } else if (IS_VALLEYVIEW(dev)) {
12530 * The DP_DETECTED bit is the latched state of the DDC
12531 * SDA pin at boot. However since eDP doesn't require DDC
12532 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12533 * eDP ports may have been muxed to an alternate function.
12534 * Thus we can't rely on the DP_DETECTED bit alone to detect
12535 * eDP ports. Consult the VBT as well as DP_DETECTED to
12536 * detect eDP ports.
12538 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12539 !intel_dp_is_edp(dev, PORT_B))
12540 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12542 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12543 intel_dp_is_edp(dev, PORT_B))
12544 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12546 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12547 !intel_dp_is_edp(dev, PORT_C))
12548 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12550 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12551 intel_dp_is_edp(dev, PORT_C))
12552 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12554 if (IS_CHERRYVIEW(dev)) {
12555 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12556 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12558 /* eDP not supported on port D, so don't check VBT */
12559 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12560 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12563 intel_dsi_init(dev);
12564 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12565 bool found = false;
12567 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12568 DRM_DEBUG_KMS("probing SDVOB\n");
12569 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12570 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12571 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12572 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12575 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12576 intel_dp_init(dev, DP_B, PORT_B);
12579 /* Before G4X SDVOC doesn't have its own detect register */
12581 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12582 DRM_DEBUG_KMS("probing SDVOC\n");
12583 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12586 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12588 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12589 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12590 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12592 if (SUPPORTS_INTEGRATED_DP(dev))
12593 intel_dp_init(dev, DP_C, PORT_C);
12596 if (SUPPORTS_INTEGRATED_DP(dev) &&
12597 (I915_READ(DP_D) & DP_DETECTED))
12598 intel_dp_init(dev, DP_D, PORT_D);
12599 } else if (IS_GEN2(dev))
12600 intel_dvo_init(dev);
12602 if (SUPPORTS_TV(dev))
12603 intel_tv_init(dev);
12606 * FIXME: We don't have full atomic support yet, but we want to be
12607 * able to enable/test plane updates via the atomic interface in the
12608 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12609 * will take some atomic codepaths to lookup properties during
12610 * drmModeGetConnector() that unconditionally dereference
12611 * connector->state.
12613 * We create a dummy connector state here for each connector to ensure
12614 * the DRM core doesn't try to dereference a NULL connector->state.
12615 * The actual connector properties will never be updated or contain
12616 * useful information, but since we're doing this specifically for
12617 * testing/debug of the plane operations (and only when a specific
12618 * kernel module option is given), that shouldn't really matter.
12620 * Once atomic support for crtc's + connectors lands, this loop should
12621 * be removed since we'll be setting up real connector state, which
12622 * will contain Intel-specific properties.
12624 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12625 list_for_each_entry(connector,
12626 &dev->mode_config.connector_list,
12628 if (!WARN_ON(connector->state)) {
12630 kzalloc(sizeof(*connector->state),
12636 intel_psr_init(dev);
12638 for_each_intel_encoder(dev, encoder) {
12639 encoder->base.possible_crtcs = encoder->crtc_mask;
12640 encoder->base.possible_clones =
12641 intel_encoder_clones(encoder);
12644 intel_init_pch_refclk(dev);
12646 drm_helper_move_panel_connectors_to_head(dev);
12649 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12651 struct drm_device *dev = fb->dev;
12652 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12654 drm_framebuffer_cleanup(fb);
12655 mutex_lock(&dev->struct_mutex);
12656 WARN_ON(!intel_fb->obj->framebuffer_references--);
12657 drm_gem_object_unreference(&intel_fb->obj->base);
12658 mutex_unlock(&dev->struct_mutex);
12662 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12663 struct drm_file *file,
12664 unsigned int *handle)
12666 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12667 struct drm_i915_gem_object *obj = intel_fb->obj;
12669 return drm_gem_handle_create(file, &obj->base, handle);
12672 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12673 .destroy = intel_user_framebuffer_destroy,
12674 .create_handle = intel_user_framebuffer_create_handle,
12677 static int intel_framebuffer_init(struct drm_device *dev,
12678 struct intel_framebuffer *intel_fb,
12679 struct drm_mode_fb_cmd2 *mode_cmd,
12680 struct drm_i915_gem_object *obj)
12682 int aligned_height;
12686 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12688 if (obj->tiling_mode == I915_TILING_Y) {
12689 DRM_DEBUG("hardware does not support tiling Y\n");
12693 if (mode_cmd->pitches[0] & 63) {
12694 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12695 mode_cmd->pitches[0]);
12699 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12700 pitch_limit = 32*1024;
12701 } else if (INTEL_INFO(dev)->gen >= 4) {
12702 if (obj->tiling_mode)
12703 pitch_limit = 16*1024;
12705 pitch_limit = 32*1024;
12706 } else if (INTEL_INFO(dev)->gen >= 3) {
12707 if (obj->tiling_mode)
12708 pitch_limit = 8*1024;
12710 pitch_limit = 16*1024;
12712 /* XXX DSPC is limited to 4k tiled */
12713 pitch_limit = 8*1024;
12715 if (mode_cmd->pitches[0] > pitch_limit) {
12716 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12717 obj->tiling_mode ? "tiled" : "linear",
12718 mode_cmd->pitches[0], pitch_limit);
12722 if (obj->tiling_mode != I915_TILING_NONE &&
12723 mode_cmd->pitches[0] != obj->stride) {
12724 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12725 mode_cmd->pitches[0], obj->stride);
12729 /* Reject formats not supported by any plane early. */
12730 switch (mode_cmd->pixel_format) {
12731 case DRM_FORMAT_C8:
12732 case DRM_FORMAT_RGB565:
12733 case DRM_FORMAT_XRGB8888:
12734 case DRM_FORMAT_ARGB8888:
12736 case DRM_FORMAT_XRGB1555:
12737 case DRM_FORMAT_ARGB1555:
12738 if (INTEL_INFO(dev)->gen > 3) {
12739 DRM_DEBUG("unsupported pixel format: %s\n",
12740 drm_get_format_name(mode_cmd->pixel_format));
12744 case DRM_FORMAT_XBGR8888:
12745 case DRM_FORMAT_ABGR8888:
12746 case DRM_FORMAT_XRGB2101010:
12747 case DRM_FORMAT_ARGB2101010:
12748 case DRM_FORMAT_XBGR2101010:
12749 case DRM_FORMAT_ABGR2101010:
12750 if (INTEL_INFO(dev)->gen < 4) {
12751 DRM_DEBUG("unsupported pixel format: %s\n",
12752 drm_get_format_name(mode_cmd->pixel_format));
12756 case DRM_FORMAT_YUYV:
12757 case DRM_FORMAT_UYVY:
12758 case DRM_FORMAT_YVYU:
12759 case DRM_FORMAT_VYUY:
12760 if (INTEL_INFO(dev)->gen < 5) {
12761 DRM_DEBUG("unsupported pixel format: %s\n",
12762 drm_get_format_name(mode_cmd->pixel_format));
12767 DRM_DEBUG("unsupported pixel format: %s\n",
12768 drm_get_format_name(mode_cmd->pixel_format));
12772 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12773 if (mode_cmd->offsets[0] != 0)
12776 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12778 /* FIXME drm helper for size checks (especially planar formats)? */
12779 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12782 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12783 intel_fb->obj = obj;
12784 intel_fb->obj->framebuffer_references++;
12786 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12788 DRM_ERROR("framebuffer init failed %d\n", ret);
12795 static struct drm_framebuffer *
12796 intel_user_framebuffer_create(struct drm_device *dev,
12797 struct drm_file *filp,
12798 struct drm_mode_fb_cmd2 *mode_cmd)
12800 struct drm_i915_gem_object *obj;
12802 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12803 mode_cmd->handles[0]));
12804 if (&obj->base == NULL)
12805 return ERR_PTR(-ENOENT);
12807 return intel_framebuffer_create(dev, mode_cmd, obj);
12810 #ifndef CONFIG_DRM_I915_FBDEV
12811 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12816 static const struct drm_mode_config_funcs intel_mode_funcs = {
12817 .fb_create = intel_user_framebuffer_create,
12818 .output_poll_changed = intel_fbdev_output_poll_changed,
12819 .atomic_check = intel_atomic_check,
12820 .atomic_commit = intel_atomic_commit,
12823 /* Set up chip specific display functions */
12824 static void intel_init_display(struct drm_device *dev)
12826 struct drm_i915_private *dev_priv = dev->dev_private;
12828 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12829 dev_priv->display.find_dpll = g4x_find_best_dpll;
12830 else if (IS_CHERRYVIEW(dev))
12831 dev_priv->display.find_dpll = chv_find_best_dpll;
12832 else if (IS_VALLEYVIEW(dev))
12833 dev_priv->display.find_dpll = vlv_find_best_dpll;
12834 else if (IS_PINEVIEW(dev))
12835 dev_priv->display.find_dpll = pnv_find_best_dpll;
12837 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12839 if (INTEL_INFO(dev)->gen >= 9) {
12840 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12841 dev_priv->display.get_initial_plane_config =
12842 skylake_get_initial_plane_config;
12843 dev_priv->display.crtc_compute_clock =
12844 haswell_crtc_compute_clock;
12845 dev_priv->display.crtc_enable = haswell_crtc_enable;
12846 dev_priv->display.crtc_disable = haswell_crtc_disable;
12847 dev_priv->display.off = ironlake_crtc_off;
12848 dev_priv->display.update_primary_plane =
12849 skylake_update_primary_plane;
12850 } else if (HAS_DDI(dev)) {
12851 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12852 dev_priv->display.get_initial_plane_config =
12853 ironlake_get_initial_plane_config;
12854 dev_priv->display.crtc_compute_clock =
12855 haswell_crtc_compute_clock;
12856 dev_priv->display.crtc_enable = haswell_crtc_enable;
12857 dev_priv->display.crtc_disable = haswell_crtc_disable;
12858 dev_priv->display.off = ironlake_crtc_off;
12859 dev_priv->display.update_primary_plane =
12860 ironlake_update_primary_plane;
12861 } else if (HAS_PCH_SPLIT(dev)) {
12862 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12863 dev_priv->display.get_initial_plane_config =
12864 ironlake_get_initial_plane_config;
12865 dev_priv->display.crtc_compute_clock =
12866 ironlake_crtc_compute_clock;
12867 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12868 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12869 dev_priv->display.off = ironlake_crtc_off;
12870 dev_priv->display.update_primary_plane =
12871 ironlake_update_primary_plane;
12872 } else if (IS_VALLEYVIEW(dev)) {
12873 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12874 dev_priv->display.get_initial_plane_config =
12875 i9xx_get_initial_plane_config;
12876 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12877 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12878 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12879 dev_priv->display.off = i9xx_crtc_off;
12880 dev_priv->display.update_primary_plane =
12881 i9xx_update_primary_plane;
12883 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12884 dev_priv->display.get_initial_plane_config =
12885 i9xx_get_initial_plane_config;
12886 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12887 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12888 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12889 dev_priv->display.off = i9xx_crtc_off;
12890 dev_priv->display.update_primary_plane =
12891 i9xx_update_primary_plane;
12894 /* Returns the core display clock speed */
12895 if (IS_VALLEYVIEW(dev))
12896 dev_priv->display.get_display_clock_speed =
12897 valleyview_get_display_clock_speed;
12898 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12899 dev_priv->display.get_display_clock_speed =
12900 i945_get_display_clock_speed;
12901 else if (IS_I915G(dev))
12902 dev_priv->display.get_display_clock_speed =
12903 i915_get_display_clock_speed;
12904 else if (IS_I945GM(dev) || IS_845G(dev))
12905 dev_priv->display.get_display_clock_speed =
12906 i9xx_misc_get_display_clock_speed;
12907 else if (IS_PINEVIEW(dev))
12908 dev_priv->display.get_display_clock_speed =
12909 pnv_get_display_clock_speed;
12910 else if (IS_I915GM(dev))
12911 dev_priv->display.get_display_clock_speed =
12912 i915gm_get_display_clock_speed;
12913 else if (IS_I865G(dev))
12914 dev_priv->display.get_display_clock_speed =
12915 i865_get_display_clock_speed;
12916 else if (IS_I85X(dev))
12917 dev_priv->display.get_display_clock_speed =
12918 i855_get_display_clock_speed;
12919 else /* 852, 830 */
12920 dev_priv->display.get_display_clock_speed =
12921 i830_get_display_clock_speed;
12923 if (IS_GEN5(dev)) {
12924 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12925 } else if (IS_GEN6(dev)) {
12926 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12927 } else if (IS_IVYBRIDGE(dev)) {
12928 /* FIXME: detect B0+ stepping and use auto training */
12929 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12930 dev_priv->display.modeset_global_resources =
12931 ivb_modeset_global_resources;
12932 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12933 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12934 } else if (IS_VALLEYVIEW(dev)) {
12935 dev_priv->display.modeset_global_resources =
12936 valleyview_modeset_global_resources;
12939 /* Default just returns -ENODEV to indicate unsupported */
12940 dev_priv->display.queue_flip = intel_default_queue_flip;
12942 switch (INTEL_INFO(dev)->gen) {
12944 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12948 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12953 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12957 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12960 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12961 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12964 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12968 intel_panel_init_backlight_funcs(dev);
12970 mutex_init(&dev_priv->pps_mutex);
12974 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12975 * resume, or other times. This quirk makes sure that's the case for
12976 * affected systems.
12978 static void quirk_pipea_force(struct drm_device *dev)
12980 struct drm_i915_private *dev_priv = dev->dev_private;
12982 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12983 DRM_INFO("applying pipe a force quirk\n");
12986 static void quirk_pipeb_force(struct drm_device *dev)
12988 struct drm_i915_private *dev_priv = dev->dev_private;
12990 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12991 DRM_INFO("applying pipe b force quirk\n");
12995 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12997 static void quirk_ssc_force_disable(struct drm_device *dev)
12999 struct drm_i915_private *dev_priv = dev->dev_private;
13000 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13001 DRM_INFO("applying lvds SSC disable quirk\n");
13005 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13008 static void quirk_invert_brightness(struct drm_device *dev)
13010 struct drm_i915_private *dev_priv = dev->dev_private;
13011 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13012 DRM_INFO("applying inverted panel brightness quirk\n");
13015 /* Some VBT's incorrectly indicate no backlight is present */
13016 static void quirk_backlight_present(struct drm_device *dev)
13018 struct drm_i915_private *dev_priv = dev->dev_private;
13019 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13020 DRM_INFO("applying backlight present quirk\n");
13023 struct intel_quirk {
13025 int subsystem_vendor;
13026 int subsystem_device;
13027 void (*hook)(struct drm_device *dev);
13030 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13031 struct intel_dmi_quirk {
13032 void (*hook)(struct drm_device *dev);
13033 const struct dmi_system_id (*dmi_id_list)[];
13036 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13038 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13042 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13044 .dmi_id_list = &(const struct dmi_system_id[]) {
13046 .callback = intel_dmi_reverse_brightness,
13047 .ident = "NCR Corporation",
13048 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13049 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13052 { } /* terminating entry */
13054 .hook = quirk_invert_brightness,
13058 static struct intel_quirk intel_quirks[] = {
13059 /* HP Mini needs pipe A force quirk (LP: #322104) */
13060 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13062 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13063 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13065 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13066 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13068 /* 830 needs to leave pipe A & dpll A up */
13069 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13071 /* 830 needs to leave pipe B & dpll B up */
13072 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13074 /* Lenovo U160 cannot use SSC on LVDS */
13075 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13077 /* Sony Vaio Y cannot use SSC on LVDS */
13078 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13080 /* Acer Aspire 5734Z must invert backlight brightness */
13081 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13083 /* Acer/eMachines G725 */
13084 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13086 /* Acer/eMachines e725 */
13087 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13089 /* Acer/Packard Bell NCL20 */
13090 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13092 /* Acer Aspire 4736Z */
13093 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13095 /* Acer Aspire 5336 */
13096 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13098 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13099 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13101 /* Acer C720 Chromebook (Core i3 4005U) */
13102 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13104 /* Apple Macbook 2,1 (Core 2 T7400) */
13105 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13107 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13108 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13110 /* HP Chromebook 14 (Celeron 2955U) */
13111 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13113 /* Dell Chromebook 11 */
13114 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13117 static void intel_init_quirks(struct drm_device *dev)
13119 struct pci_dev *d = dev->pdev;
13122 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13123 struct intel_quirk *q = &intel_quirks[i];
13125 if (d->device == q->device &&
13126 (d->subsystem_vendor == q->subsystem_vendor ||
13127 q->subsystem_vendor == PCI_ANY_ID) &&
13128 (d->subsystem_device == q->subsystem_device ||
13129 q->subsystem_device == PCI_ANY_ID))
13132 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13133 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13134 intel_dmi_quirks[i].hook(dev);
13138 /* Disable the VGA plane that we never use */
13139 static void i915_disable_vga(struct drm_device *dev)
13141 struct drm_i915_private *dev_priv = dev->dev_private;
13143 u32 vga_reg = i915_vgacntrl_reg(dev);
13145 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13146 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13147 outb(SR01, VGA_SR_INDEX);
13148 sr1 = inb(VGA_SR_DATA);
13149 outb(sr1 | 1<<5, VGA_SR_DATA);
13150 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13153 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13154 POSTING_READ(vga_reg);
13157 void intel_modeset_init_hw(struct drm_device *dev)
13159 intel_prepare_ddi(dev);
13161 if (IS_VALLEYVIEW(dev))
13162 vlv_update_cdclk(dev);
13164 intel_init_clock_gating(dev);
13166 intel_enable_gt_powersave(dev);
13169 void intel_modeset_init(struct drm_device *dev)
13171 struct drm_i915_private *dev_priv = dev->dev_private;
13174 struct intel_crtc *crtc;
13176 drm_mode_config_init(dev);
13178 dev->mode_config.min_width = 0;
13179 dev->mode_config.min_height = 0;
13181 dev->mode_config.preferred_depth = 24;
13182 dev->mode_config.prefer_shadow = 1;
13184 dev->mode_config.funcs = &intel_mode_funcs;
13186 intel_init_quirks(dev);
13188 intel_init_pm(dev);
13190 if (INTEL_INFO(dev)->num_pipes == 0)
13193 intel_init_display(dev);
13194 intel_init_audio(dev);
13196 if (IS_GEN2(dev)) {
13197 dev->mode_config.max_width = 2048;
13198 dev->mode_config.max_height = 2048;
13199 } else if (IS_GEN3(dev)) {
13200 dev->mode_config.max_width = 4096;
13201 dev->mode_config.max_height = 4096;
13203 dev->mode_config.max_width = 8192;
13204 dev->mode_config.max_height = 8192;
13207 if (IS_845G(dev) || IS_I865G(dev)) {
13208 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13209 dev->mode_config.cursor_height = 1023;
13210 } else if (IS_GEN2(dev)) {
13211 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13212 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13214 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13215 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13218 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13220 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13221 INTEL_INFO(dev)->num_pipes,
13222 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13224 for_each_pipe(dev_priv, pipe) {
13225 intel_crtc_init(dev, pipe);
13226 for_each_sprite(pipe, sprite) {
13227 ret = intel_plane_init(dev, pipe, sprite);
13229 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13230 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13234 intel_init_dpio(dev);
13236 intel_shared_dpll_init(dev);
13238 /* Just disable it once at startup */
13239 i915_disable_vga(dev);
13240 intel_setup_outputs(dev);
13242 /* Just in case the BIOS is doing something questionable. */
13243 intel_fbc_disable(dev);
13245 drm_modeset_lock_all(dev);
13246 intel_modeset_setup_hw_state(dev, false);
13247 drm_modeset_unlock_all(dev);
13249 for_each_intel_crtc(dev, crtc) {
13254 * Note that reserving the BIOS fb up front prevents us
13255 * from stuffing other stolen allocations like the ring
13256 * on top. This prevents some ugliness at boot time, and
13257 * can even allow for smooth boot transitions if the BIOS
13258 * fb is large enough for the active pipe configuration.
13260 if (dev_priv->display.get_initial_plane_config) {
13261 dev_priv->display.get_initial_plane_config(crtc,
13262 &crtc->plane_config);
13264 * If the fb is shared between multiple heads, we'll
13265 * just get the first one.
13267 intel_find_plane_obj(crtc, &crtc->plane_config);
13272 static void intel_enable_pipe_a(struct drm_device *dev)
13274 struct intel_connector *connector;
13275 struct drm_connector *crt = NULL;
13276 struct intel_load_detect_pipe load_detect_temp;
13277 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13279 /* We can't just switch on the pipe A, we need to set things up with a
13280 * proper mode and output configuration. As a gross hack, enable pipe A
13281 * by enabling the load detect pipe once. */
13282 list_for_each_entry(connector,
13283 &dev->mode_config.connector_list,
13285 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13286 crt = &connector->base;
13294 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13295 intel_release_load_detect_pipe(crt, &load_detect_temp);
13299 intel_check_plane_mapping(struct intel_crtc *crtc)
13301 struct drm_device *dev = crtc->base.dev;
13302 struct drm_i915_private *dev_priv = dev->dev_private;
13305 if (INTEL_INFO(dev)->num_pipes == 1)
13308 reg = DSPCNTR(!crtc->plane);
13309 val = I915_READ(reg);
13311 if ((val & DISPLAY_PLANE_ENABLE) &&
13312 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13318 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13320 struct drm_device *dev = crtc->base.dev;
13321 struct drm_i915_private *dev_priv = dev->dev_private;
13324 /* Clear any frame start delays used for debugging left by the BIOS */
13325 reg = PIPECONF(crtc->config->cpu_transcoder);
13326 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13328 /* restore vblank interrupts to correct state */
13329 if (crtc->active) {
13330 update_scanline_offset(crtc);
13331 drm_vblank_on(dev, crtc->pipe);
13333 drm_vblank_off(dev, crtc->pipe);
13335 /* We need to sanitize the plane -> pipe mapping first because this will
13336 * disable the crtc (and hence change the state) if it is wrong. Note
13337 * that gen4+ has a fixed plane -> pipe mapping. */
13338 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13339 struct intel_connector *connector;
13342 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13343 crtc->base.base.id);
13345 /* Pipe has the wrong plane attached and the plane is active.
13346 * Temporarily change the plane mapping and disable everything
13348 plane = crtc->plane;
13349 crtc->plane = !plane;
13350 crtc->primary_enabled = true;
13351 dev_priv->display.crtc_disable(&crtc->base);
13352 crtc->plane = plane;
13354 /* ... and break all links. */
13355 list_for_each_entry(connector, &dev->mode_config.connector_list,
13357 if (connector->encoder->base.crtc != &crtc->base)
13360 connector->base.dpms = DRM_MODE_DPMS_OFF;
13361 connector->base.encoder = NULL;
13363 /* multiple connectors may have the same encoder:
13364 * handle them and break crtc link separately */
13365 list_for_each_entry(connector, &dev->mode_config.connector_list,
13367 if (connector->encoder->base.crtc == &crtc->base) {
13368 connector->encoder->base.crtc = NULL;
13369 connector->encoder->connectors_active = false;
13372 WARN_ON(crtc->active);
13373 crtc->base.enabled = false;
13376 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13377 crtc->pipe == PIPE_A && !crtc->active) {
13378 /* BIOS forgot to enable pipe A, this mostly happens after
13379 * resume. Force-enable the pipe to fix this, the update_dpms
13380 * call below we restore the pipe to the right state, but leave
13381 * the required bits on. */
13382 intel_enable_pipe_a(dev);
13385 /* Adjust the state of the output pipe according to whether we
13386 * have active connectors/encoders. */
13387 intel_crtc_update_dpms(&crtc->base);
13389 if (crtc->active != crtc->base.enabled) {
13390 struct intel_encoder *encoder;
13392 /* This can happen either due to bugs in the get_hw_state
13393 * functions or because the pipe is force-enabled due to the
13395 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13396 crtc->base.base.id,
13397 crtc->base.enabled ? "enabled" : "disabled",
13398 crtc->active ? "enabled" : "disabled");
13400 crtc->base.enabled = crtc->active;
13402 /* Because we only establish the connector -> encoder ->
13403 * crtc links if something is active, this means the
13404 * crtc is now deactivated. Break the links. connector
13405 * -> encoder links are only establish when things are
13406 * actually up, hence no need to break them. */
13407 WARN_ON(crtc->active);
13409 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13410 WARN_ON(encoder->connectors_active);
13411 encoder->base.crtc = NULL;
13415 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13417 * We start out with underrun reporting disabled to avoid races.
13418 * For correct bookkeeping mark this on active crtcs.
13420 * Also on gmch platforms we dont have any hardware bits to
13421 * disable the underrun reporting. Which means we need to start
13422 * out with underrun reporting disabled also on inactive pipes,
13423 * since otherwise we'll complain about the garbage we read when
13424 * e.g. coming up after runtime pm.
13426 * No protection against concurrent access is required - at
13427 * worst a fifo underrun happens which also sets this to false.
13429 crtc->cpu_fifo_underrun_disabled = true;
13430 crtc->pch_fifo_underrun_disabled = true;
13434 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13436 struct intel_connector *connector;
13437 struct drm_device *dev = encoder->base.dev;
13439 /* We need to check both for a crtc link (meaning that the
13440 * encoder is active and trying to read from a pipe) and the
13441 * pipe itself being active. */
13442 bool has_active_crtc = encoder->base.crtc &&
13443 to_intel_crtc(encoder->base.crtc)->active;
13445 if (encoder->connectors_active && !has_active_crtc) {
13446 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13447 encoder->base.base.id,
13448 encoder->base.name);
13450 /* Connector is active, but has no active pipe. This is
13451 * fallout from our resume register restoring. Disable
13452 * the encoder manually again. */
13453 if (encoder->base.crtc) {
13454 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13455 encoder->base.base.id,
13456 encoder->base.name);
13457 encoder->disable(encoder);
13458 if (encoder->post_disable)
13459 encoder->post_disable(encoder);
13461 encoder->base.crtc = NULL;
13462 encoder->connectors_active = false;
13464 /* Inconsistent output/port/pipe state happens presumably due to
13465 * a bug in one of the get_hw_state functions. Or someplace else
13466 * in our code, like the register restore mess on resume. Clamp
13467 * things to off as a safer default. */
13468 list_for_each_entry(connector,
13469 &dev->mode_config.connector_list,
13471 if (connector->encoder != encoder)
13473 connector->base.dpms = DRM_MODE_DPMS_OFF;
13474 connector->base.encoder = NULL;
13477 /* Enabled encoders without active connectors will be fixed in
13478 * the crtc fixup. */
13481 void i915_redisable_vga_power_on(struct drm_device *dev)
13483 struct drm_i915_private *dev_priv = dev->dev_private;
13484 u32 vga_reg = i915_vgacntrl_reg(dev);
13486 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13487 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13488 i915_disable_vga(dev);
13492 void i915_redisable_vga(struct drm_device *dev)
13494 struct drm_i915_private *dev_priv = dev->dev_private;
13496 /* This function can be called both from intel_modeset_setup_hw_state or
13497 * at a very early point in our resume sequence, where the power well
13498 * structures are not yet restored. Since this function is at a very
13499 * paranoid "someone might have enabled VGA while we were not looking"
13500 * level, just check if the power well is enabled instead of trying to
13501 * follow the "don't touch the power well if we don't need it" policy
13502 * the rest of the driver uses. */
13503 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13506 i915_redisable_vga_power_on(dev);
13509 static bool primary_get_hw_state(struct intel_crtc *crtc)
13511 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13516 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13519 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13521 struct drm_i915_private *dev_priv = dev->dev_private;
13523 struct intel_crtc *crtc;
13524 struct intel_encoder *encoder;
13525 struct intel_connector *connector;
13528 for_each_intel_crtc(dev, crtc) {
13529 memset(crtc->config, 0, sizeof(*crtc->config));
13531 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13533 crtc->active = dev_priv->display.get_pipe_config(crtc,
13536 crtc->base.enabled = crtc->active;
13537 crtc->primary_enabled = primary_get_hw_state(crtc);
13539 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13540 crtc->base.base.id,
13541 crtc->active ? "enabled" : "disabled");
13544 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13545 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13547 pll->on = pll->get_hw_state(dev_priv, pll,
13548 &pll->config.hw_state);
13550 pll->config.crtc_mask = 0;
13551 for_each_intel_crtc(dev, crtc) {
13552 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13554 pll->config.crtc_mask |= 1 << crtc->pipe;
13558 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13559 pll->name, pll->config.crtc_mask, pll->on);
13561 if (pll->config.crtc_mask)
13562 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13565 for_each_intel_encoder(dev, encoder) {
13568 if (encoder->get_hw_state(encoder, &pipe)) {
13569 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13570 encoder->base.crtc = &crtc->base;
13571 encoder->get_config(encoder, crtc->config);
13573 encoder->base.crtc = NULL;
13576 encoder->connectors_active = false;
13577 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13578 encoder->base.base.id,
13579 encoder->base.name,
13580 encoder->base.crtc ? "enabled" : "disabled",
13584 list_for_each_entry(connector, &dev->mode_config.connector_list,
13586 if (connector->get_hw_state(connector)) {
13587 connector->base.dpms = DRM_MODE_DPMS_ON;
13588 connector->encoder->connectors_active = true;
13589 connector->base.encoder = &connector->encoder->base;
13591 connector->base.dpms = DRM_MODE_DPMS_OFF;
13592 connector->base.encoder = NULL;
13594 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13595 connector->base.base.id,
13596 connector->base.name,
13597 connector->base.encoder ? "enabled" : "disabled");
13601 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13602 * and i915 state tracking structures. */
13603 void intel_modeset_setup_hw_state(struct drm_device *dev,
13604 bool force_restore)
13606 struct drm_i915_private *dev_priv = dev->dev_private;
13608 struct intel_crtc *crtc;
13609 struct intel_encoder *encoder;
13612 intel_modeset_readout_hw_state(dev);
13615 * Now that we have the config, copy it to each CRTC struct
13616 * Note that this could go away if we move to using crtc_config
13617 * checking everywhere.
13619 for_each_intel_crtc(dev, crtc) {
13620 if (crtc->active && i915.fastboot) {
13621 intel_mode_from_pipe_config(&crtc->base.mode,
13623 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13624 crtc->base.base.id);
13625 drm_mode_debug_printmodeline(&crtc->base.mode);
13629 /* HW state is read out, now we need to sanitize this mess. */
13630 for_each_intel_encoder(dev, encoder) {
13631 intel_sanitize_encoder(encoder);
13634 for_each_pipe(dev_priv, pipe) {
13635 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13636 intel_sanitize_crtc(crtc);
13637 intel_dump_pipe_config(crtc, crtc->config,
13638 "[setup_hw_state]");
13641 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13642 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13644 if (!pll->on || pll->active)
13647 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13649 pll->disable(dev_priv, pll);
13654 skl_wm_get_hw_state(dev);
13655 else if (HAS_PCH_SPLIT(dev))
13656 ilk_wm_get_hw_state(dev);
13658 if (force_restore) {
13659 i915_redisable_vga(dev);
13662 * We need to use raw interfaces for restoring state to avoid
13663 * checking (bogus) intermediate states.
13665 for_each_pipe(dev_priv, pipe) {
13666 struct drm_crtc *crtc =
13667 dev_priv->pipe_to_crtc_mapping[pipe];
13669 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13670 crtc->primary->fb);
13673 intel_modeset_update_staged_output_state(dev);
13676 intel_modeset_check_state(dev);
13679 void intel_modeset_gem_init(struct drm_device *dev)
13681 struct drm_i915_private *dev_priv = dev->dev_private;
13682 struct drm_crtc *c;
13683 struct drm_i915_gem_object *obj;
13685 mutex_lock(&dev->struct_mutex);
13686 intel_init_gt_powersave(dev);
13687 mutex_unlock(&dev->struct_mutex);
13690 * There may be no VBT; and if the BIOS enabled SSC we can
13691 * just keep using it to avoid unnecessary flicker. Whereas if the
13692 * BIOS isn't using it, don't assume it will work even if the VBT
13693 * indicates as much.
13695 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13696 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13699 intel_modeset_init_hw(dev);
13701 intel_setup_overlay(dev);
13704 * Make sure any fbs we allocated at startup are properly
13705 * pinned & fenced. When we do the allocation it's too early
13708 mutex_lock(&dev->struct_mutex);
13709 for_each_crtc(dev, c) {
13710 obj = intel_fb_obj(c->primary->fb);
13714 if (intel_pin_and_fence_fb_obj(c->primary,
13717 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13718 to_intel_crtc(c)->pipe);
13719 drm_framebuffer_unreference(c->primary->fb);
13720 c->primary->fb = NULL;
13723 mutex_unlock(&dev->struct_mutex);
13725 intel_backlight_register(dev);
13728 void intel_connector_unregister(struct intel_connector *intel_connector)
13730 struct drm_connector *connector = &intel_connector->base;
13732 intel_panel_destroy_backlight(connector);
13733 drm_connector_unregister(connector);
13736 void intel_modeset_cleanup(struct drm_device *dev)
13738 struct drm_i915_private *dev_priv = dev->dev_private;
13739 struct drm_connector *connector;
13741 intel_disable_gt_powersave(dev);
13743 intel_backlight_unregister(dev);
13746 * Interrupts and polling as the first thing to avoid creating havoc.
13747 * Too much stuff here (turning of connectors, ...) would
13748 * experience fancy races otherwise.
13750 intel_irq_uninstall(dev_priv);
13753 * Due to the hpd irq storm handling the hotplug work can re-arm the
13754 * poll handlers. Hence disable polling after hpd handling is shut down.
13756 drm_kms_helper_poll_fini(dev);
13758 mutex_lock(&dev->struct_mutex);
13760 intel_unregister_dsm_handler();
13762 intel_fbc_disable(dev);
13764 ironlake_teardown_rc6(dev);
13766 mutex_unlock(&dev->struct_mutex);
13768 /* flush any delayed tasks or pending work */
13769 flush_scheduled_work();
13771 /* destroy the backlight and sysfs files before encoders/connectors */
13772 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13773 struct intel_connector *intel_connector;
13775 intel_connector = to_intel_connector(connector);
13776 intel_connector->unregister(intel_connector);
13779 drm_mode_config_cleanup(dev);
13781 intel_cleanup_overlay(dev);
13783 mutex_lock(&dev->struct_mutex);
13784 intel_cleanup_gt_powersave(dev);
13785 mutex_unlock(&dev->struct_mutex);
13789 * Return which encoder is currently attached for connector.
13791 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13793 return &intel_attached_encoder(connector)->base;
13796 void intel_connector_attach_encoder(struct intel_connector *connector,
13797 struct intel_encoder *encoder)
13799 connector->encoder = encoder;
13800 drm_mode_connector_attach_encoder(&connector->base,
13805 * set vga decode state - true == enable VGA decode
13807 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13809 struct drm_i915_private *dev_priv = dev->dev_private;
13810 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13813 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13814 DRM_ERROR("failed to read control word\n");
13818 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13822 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13824 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13826 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13827 DRM_ERROR("failed to write control word\n");
13834 struct intel_display_error_state {
13836 u32 power_well_driver;
13838 int num_transcoders;
13840 struct intel_cursor_error_state {
13845 } cursor[I915_MAX_PIPES];
13847 struct intel_pipe_error_state {
13848 bool power_domain_on;
13851 } pipe[I915_MAX_PIPES];
13853 struct intel_plane_error_state {
13861 } plane[I915_MAX_PIPES];
13863 struct intel_transcoder_error_state {
13864 bool power_domain_on;
13865 enum transcoder cpu_transcoder;
13878 struct intel_display_error_state *
13879 intel_display_capture_error_state(struct drm_device *dev)
13881 struct drm_i915_private *dev_priv = dev->dev_private;
13882 struct intel_display_error_state *error;
13883 int transcoders[] = {
13891 if (INTEL_INFO(dev)->num_pipes == 0)
13894 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13898 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13899 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13901 for_each_pipe(dev_priv, i) {
13902 error->pipe[i].power_domain_on =
13903 __intel_display_power_is_enabled(dev_priv,
13904 POWER_DOMAIN_PIPE(i));
13905 if (!error->pipe[i].power_domain_on)
13908 error->cursor[i].control = I915_READ(CURCNTR(i));
13909 error->cursor[i].position = I915_READ(CURPOS(i));
13910 error->cursor[i].base = I915_READ(CURBASE(i));
13912 error->plane[i].control = I915_READ(DSPCNTR(i));
13913 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13914 if (INTEL_INFO(dev)->gen <= 3) {
13915 error->plane[i].size = I915_READ(DSPSIZE(i));
13916 error->plane[i].pos = I915_READ(DSPPOS(i));
13918 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13919 error->plane[i].addr = I915_READ(DSPADDR(i));
13920 if (INTEL_INFO(dev)->gen >= 4) {
13921 error->plane[i].surface = I915_READ(DSPSURF(i));
13922 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13925 error->pipe[i].source = I915_READ(PIPESRC(i));
13927 if (HAS_GMCH_DISPLAY(dev))
13928 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13931 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13932 if (HAS_DDI(dev_priv->dev))
13933 error->num_transcoders++; /* Account for eDP. */
13935 for (i = 0; i < error->num_transcoders; i++) {
13936 enum transcoder cpu_transcoder = transcoders[i];
13938 error->transcoder[i].power_domain_on =
13939 __intel_display_power_is_enabled(dev_priv,
13940 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13941 if (!error->transcoder[i].power_domain_on)
13944 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13946 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13947 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13948 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13949 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13950 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13951 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13952 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13958 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13961 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13962 struct drm_device *dev,
13963 struct intel_display_error_state *error)
13965 struct drm_i915_private *dev_priv = dev->dev_private;
13971 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13972 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13973 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13974 error->power_well_driver);
13975 for_each_pipe(dev_priv, i) {
13976 err_printf(m, "Pipe [%d]:\n", i);
13977 err_printf(m, " Power: %s\n",
13978 error->pipe[i].power_domain_on ? "on" : "off");
13979 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13980 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13982 err_printf(m, "Plane [%d]:\n", i);
13983 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13984 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13985 if (INTEL_INFO(dev)->gen <= 3) {
13986 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13987 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13989 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13990 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13991 if (INTEL_INFO(dev)->gen >= 4) {
13992 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13993 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13996 err_printf(m, "Cursor [%d]:\n", i);
13997 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13998 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13999 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14002 for (i = 0; i < error->num_transcoders; i++) {
14003 err_printf(m, "CPU transcoder: %c\n",
14004 transcoder_name(error->transcoder[i].cpu_transcoder));
14005 err_printf(m, " Power: %s\n",
14006 error->transcoder[i].power_domain_on ? "on" : "off");
14007 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14008 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14009 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14010 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14011 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14012 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14013 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14017 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14019 struct intel_crtc *crtc;
14021 for_each_intel_crtc(dev, crtc) {
14022 struct intel_unpin_work *work;
14024 spin_lock_irq(&dev->event_lock);
14026 work = crtc->unpin_work;
14028 if (work && work->event &&
14029 work->event->base.file_priv == file) {
14030 kfree(work->event);
14031 work->event = NULL;
14034 spin_unlock_irq(&dev->event_lock);