drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         /**
  75          * find_pll() - Find the best values for the PLL
  76          * @limit: limits for the PLL
  77          * @crtc: current CRTC
  78          * @target: target frequency in kHz
  79          * @refclk: reference clock frequency in kHz
  80          * @match_clock: if provided, @best_clock P divider must
  81          *               match the P divider from @match_clock
  82          *               used for LVDS downclocking
  83          * @best_clock: best PLL values found
  84          *
  85          * Returns true on success, false on failure.
  86          */
  87         bool (*find_pll)(const intel_limit_t *limit,
  88                          struct drm_crtc *crtc,
  89                          int target, int refclk,
  90                          intel_clock_t *match_clock,
  91                          intel_clock_t *best_clock);
  92 };
  93
  94 /* FDI */
  95 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  96
  97 int
  98 intel_pch_rawclk(struct drm_device *dev)
  99 {
 100         struct drm_i915_private *dev_priv = dev->dev_private;
 101
 102         WARN_ON(!HAS_PCH_SPLIT(dev));
 103
 104         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 105 }
 106
 107 static bool
 108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 109                     int target, int refclk, intel_clock_t *match_clock,
 110                     intel_clock_t *best_clock);
 111 static bool
 112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static bool
 117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 118                       int target, int refclk, intel_clock_t *match_clock,
 119                       intel_clock_t *best_clock);
 120 static bool
 121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 122                            int target, int refclk, intel_clock_t *match_clock,
 123                            intel_clock_t *best_clock);
 124
 125 static bool
 126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 127                         int target, int refclk, intel_clock_t *match_clock,
 128                         intel_clock_t *best_clock);
 129
 130 static inline u32 /* units of 100MHz */
 131 intel_fdi_link_freq(struct drm_device *dev)
 132 {
 133         if (IS_GEN5(dev)) {
 134                 struct drm_i915_private *dev_priv = dev->dev_private;
 135                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 136         } else
 137                 return 27;
 138 }
 139
 140 static const intel_limit_t intel_limits_i8xx_dvo = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 2, .max = 33 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 4, .p2_fast = 2 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i8xx_lvds = {
 155         .dot = { .min = 25000, .max = 350000 },
 156         .vco = { .min = 930000, .max = 1400000 },
 157         .n = { .min = 3, .max = 16 },
 158         .m = { .min = 96, .max = 140 },
 159         .m1 = { .min = 18, .max = 26 },
 160         .m2 = { .min = 6, .max = 16 },
 161         .p = { .min = 4, .max = 128 },
 162         .p1 = { .min = 1, .max = 6 },
 163         .p2 = { .dot_limit = 165000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_sdvo = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 8, .max = 18 },
 174         .m2 = { .min = 3, .max = 7 },
 175         .p = { .min = 5, .max = 80 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 200000,
 178                 .p2_slow = 10, .p2_fast = 5 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182 static const intel_limit_t intel_limits_i9xx_lvds = {
 183         .dot = { .min = 20000, .max = 400000 },
 184         .vco = { .min = 1400000, .max = 2800000 },
 185         .n = { .min = 1, .max = 6 },
 186         .m = { .min = 70, .max = 120 },
 187         .m1 = { .min = 8, .max = 18 },
 188         .m2 = { .min = 3, .max = 7 },
 189         .p = { .min = 7, .max = 98 },
 190         .p1 = { .min = 1, .max = 8 },
 191         .p2 = { .dot_limit = 112000,
 192                 .p2_slow = 14, .p2_fast = 7 },
 193         .find_pll = intel_find_best_PLL,
 194 };
 195
 196
 197 static const intel_limit_t intel_limits_g4x_sdvo = {
 198         .dot = { .min = 25000, .max = 270000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 17, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 10, .max = 30 },
 205         .p1 = { .min = 1, .max = 3},
 206         .p2 = { .dot_limit = 270000,
 207                 .p2_slow = 10,
 208                 .p2_fast = 10
 209         },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_hdmi = {
 214         .dot = { .min = 22000, .max = 400000 },
 215         .vco = { .min = 1750000, .max = 3500000},
 216         .n = { .min = 1, .max = 4 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 16, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 5, .max = 80 },
 221         .p1 = { .min = 1, .max = 8},
 222         .p2 = { .dot_limit = 165000,
 223                 .p2_slow = 10, .p2_fast = 5 },
 224         .find_pll = intel_g4x_find_best_PLL,
 225 };
 226
 227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 228         .dot = { .min = 20000, .max = 115000 },
 229         .vco = { .min = 1750000, .max = 3500000 },
 230         .n = { .min = 1, .max = 3 },
 231         .m = { .min = 104, .max = 138 },
 232         .m1 = { .min = 17, .max = 23 },
 233         .m2 = { .min = 5, .max = 11 },
 234         .p = { .min = 28, .max = 112 },
 235         .p1 = { .min = 2, .max = 8 },
 236         .p2 = { .dot_limit = 0,
 237                 .p2_slow = 14, .p2_fast = 14
 238         },
 239         .find_pll = intel_g4x_find_best_PLL,
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 243         .dot = { .min = 80000, .max = 224000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 14, .max = 42 },
 250         .p1 = { .min = 2, .max = 6 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 7, .p2_fast = 7
 253         },
 254         .find_pll = intel_g4x_find_best_PLL,
 255 };
 256
 257 static const intel_limit_t intel_limits_g4x_display_port = {
 258         .dot = { .min = 161670, .max = 227000 },
 259         .vco = { .min = 1750000, .max = 3500000},
 260         .n = { .min = 1, .max = 2 },
 261         .m = { .min = 97, .max = 108 },
 262         .m1 = { .min = 0x10, .max = 0x12 },
 263         .m2 = { .min = 0x05, .max = 0x06 },
 264         .p = { .min = 10, .max = 20 },
 265         .p1 = { .min = 1, .max = 2},
 266         .p2 = { .dot_limit = 0,
 267                 .p2_slow = 10, .p2_fast = 10 },
 268         .find_pll = intel_find_pll_g4x_dp,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_sdvo = {
 272         .dot = { .min = 20000, .max = 400000},
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         /* Pineview's Ncounter is a ring counter */
 275         .n = { .min = 3, .max = 6 },
 276         .m = { .min = 2, .max = 256 },
 277         /* Pineview only has one combined m divider, which we treat as m2. */
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 200000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_pineview_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1700000, .max = 3500000 },
 290         .n = { .min = 3, .max = 6 },
 291         .m = { .min = 2, .max = 256 },
 292         .m1 = { .min = 0, .max = 0 },
 293         .m2 = { .min = 0, .max = 254 },
 294         .p = { .min = 7, .max = 112 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_find_best_PLL,
 299 };
 300
 301 /* Ironlake / Sandybridge
 302  *
 303  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 304  * the range value for them is (actual_value - 2).
 305  */
 306 static const intel_limit_t intel_limits_ironlake_dac = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 5 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 5, .max = 80 },
 314         .p1 = { .min = 1, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 10, .p2_fast = 5 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 118 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 14, .p2_fast = 14 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 335         .dot = { .min = 25000, .max = 350000 },
 336         .vco = { .min = 1760000, .max = 3510000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 79, .max = 127 },
 339         .m1 = { .min = 12, .max = 22 },
 340         .m2 = { .min = 5, .max = 9 },
 341         .p = { .min = 14, .max = 56 },
 342         .p1 = { .min = 2, .max = 8 },
 343         .p2 = { .dot_limit = 225000,
 344                 .p2_slow = 7, .p2_fast = 7 },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 /* LVDS 100mhz refclk limits. */
 349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 28, .max = 112 },
 357         .p1 = { .min = 2, .max = 8 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 14, .p2_fast = 14 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000 },
 366         .n = { .min = 1, .max = 3 },
 367         .m = { .min = 79, .max = 126 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 14, .max = 42 },
 371         .p1 = { .min = 2, .max = 6 },
 372         .p2 = { .dot_limit = 225000,
 373                 .p2_slow = 7, .p2_fast = 7 },
 374         .find_pll = intel_g4x_find_best_PLL,
 375 };
 376
 377 static const intel_limit_t intel_limits_ironlake_display_port = {
 378         .dot = { .min = 25000, .max = 350000 },
 379         .vco = { .min = 1760000, .max = 3510000},
 380         .n = { .min = 1, .max = 2 },
 381         .m = { .min = 81, .max = 90 },
 382         .m1 = { .min = 12, .max = 22 },
 383         .m2 = { .min = 5, .max = 9 },
 384         .p = { .min = 10, .max = 20 },
 385         .p1 = { .min = 1, .max = 2},
 386         .p2 = { .dot_limit = 0,
 387                 .p2_slow = 10, .p2_fast = 10 },
 388         .find_pll = intel_find_pll_ironlake_dp,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_dac = {
 392         .dot = { .min = 25000, .max = 270000 },
 393         .vco = { .min = 4000000, .max = 6000000 },
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 22, .max = 450 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_hdmi = {
 406         .dot = { .min = 20000, .max = 165000 },
 407         .vco = { .min = 4000000, .max = 5994000},
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 60, .max = 300 }, /* guess */
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 static const intel_limit_t intel_limits_vlv_dp = {
 420         .dot = { .min = 25000, .max = 270000 },
 421         .vco = { .min = 4000000, .max = 6000000 },
 422         .n = { .min = 1, .max = 7 },
 423         .m = { .min = 22, .max = 450 },
 424         .m1 = { .min = 2, .max = 3 },
 425         .m2 = { .min = 11, .max = 156 },
 426         .p = { .min = 10, .max = 30 },
 427         .p1 = { .min = 2, .max = 3 },
 428         .p2 = { .dot_limit = 270000,
 429                 .p2_slow = 2, .p2_fast = 20 },
 430         .find_pll = intel_vlv_find_best_pll,
 431 };
 432
 433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 434 {
 435         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 436
 437         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 438                 DRM_ERROR("DPIO idle wait timed out\n");
 439                 return 0;
 440         }
 441
 442         I915_WRITE(DPIO_REG, reg);
 443         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 444                    DPIO_BYTE);
 445         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 446                 DRM_ERROR("DPIO read wait timed out\n");
 447                 return 0;
 448         }
 449
 450         return I915_READ(DPIO_DATA);
 451 }
 452
 453 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 454                              u32 val)
 455 {
 456         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 457
 458         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 459                 DRM_ERROR("DPIO idle wait timed out\n");
 460                 return;
 461         }
 462
 463         I915_WRITE(DPIO_DATA, val);
 464         I915_WRITE(DPIO_REG, reg);
 465         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 466                    DPIO_BYTE);
 467         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 468                 DRM_ERROR("DPIO write wait timed out\n");
 469 }
 470
 471 static void vlv_init_dpio(struct drm_device *dev)
 472 {
 473         struct drm_i915_private *dev_priv = dev->dev_private;
 474
 475         /* Reset the DPIO config */
 476         I915_WRITE(DPIO_CTL, 0);
 477         POSTING_READ(DPIO_CTL);
 478         I915_WRITE(DPIO_CTL, 1);
 479         POSTING_READ(DPIO_CTL);
 480 }
 481
 482 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 483                                                 int refclk)
 484 {
 485         struct drm_device *dev = crtc->dev;
 486         const intel_limit_t *limit;
 487
 488         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 489                 if (intel_is_dual_link_lvds(dev)) {
 490                         if (refclk == 100000)
 491                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 492                         else
 493                                 limit = &intel_limits_ironlake_dual_lvds;
 494                 } else {
 495                         if (refclk == 100000)
 496                                 limit = &intel_limits_ironlake_single_lvds_100m;
 497                         else
 498                                 limit = &intel_limits_ironlake_single_lvds;
 499                 }
 500         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 501                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 502                 limit = &intel_limits_ironlake_display_port;
 503         else
 504                 limit = &intel_limits_ironlake_dac;
 505
 506         return limit;
 507 }
 508
 509 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 510 {
 511         struct drm_device *dev = crtc->dev;
 512         const intel_limit_t *limit;
 513
 514         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 515                 if (intel_is_dual_link_lvds(dev))
 516                         limit = &intel_limits_g4x_dual_channel_lvds;
 517                 else
 518                         limit = &intel_limits_g4x_single_channel_lvds;
 519         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 520                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 521                 limit = &intel_limits_g4x_hdmi;
 522         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 523                 limit = &intel_limits_g4x_sdvo;
 524         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 525                 limit = &intel_limits_g4x_display_port;
 526         } else /* The option is for other outputs */
 527                 limit = &intel_limits_i9xx_sdvo;
 528
 529         return limit;
 530 }
 531
 532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 533 {
 534         struct drm_device *dev = crtc->dev;
 535         const intel_limit_t *limit;
 536
 537         if (HAS_PCH_SPLIT(dev))
 538                 limit = intel_ironlake_limit(crtc, refclk);
 539         else if (IS_G4X(dev)) {
 540                 limit = intel_g4x_limit(crtc);
 541         } else if (IS_PINEVIEW(dev)) {
 542                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 543                         limit = &intel_limits_pineview_lvds;
 544                 else
 545                         limit = &intel_limits_pineview_sdvo;
 546         } else if (IS_VALLEYVIEW(dev)) {
 547                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 548                         limit = &intel_limits_vlv_dac;
 549                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 550                         limit = &intel_limits_vlv_hdmi;
 551                 else
 552                         limit = &intel_limits_vlv_dp;
 553         } else if (!IS_GEN2(dev)) {
 554                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 555                         limit = &intel_limits_i9xx_lvds;
 556                 else
 557                         limit = &intel_limits_i9xx_sdvo;
 558         } else {
 559                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 560                         limit = &intel_limits_i8xx_lvds;
 561                 else
 562                         limit = &intel_limits_i8xx_dvo;
 563         }
 564         return limit;
 565 }
 566
 567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 568 static void pineview_clock(int refclk, intel_clock_t *clock)
 569 {
 570         clock->m = clock->m2 + 2;
 571         clock->p = clock->p1 * clock->p2;
 572         clock->vco = refclk * clock->m / clock->n;
 573         clock->dot = clock->vco / clock->p;
 574 }
 575
 576 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 577 {
 578         if (IS_PINEVIEW(dev)) {
 579                 pineview_clock(refclk, clock);
 580                 return;
 581         }
 582         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 583         clock->p = clock->p1 * clock->p2;
 584         clock->vco = refclk * clock->m / (clock->n + 2);
 585         clock->dot = clock->vco / clock->p;
 586 }
 587
 588 /**
 589  * Returns whether any output on the specified pipe is of the specified type
 590  */
 591 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 592 {
 593         struct drm_device *dev = crtc->dev;
 594         struct intel_encoder *encoder;
 595
 596         for_each_encoder_on_crtc(dev, crtc, encoder)
 597                 if (encoder->type == type)
 598                         return true;
 599
 600         return false;
 601 }
 602
 603 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 604 /**
 605  * Returns whether the given set of divisors are valid for a given refclk with
 606  * the given connectors.
 607  */
 608
 609 static bool intel_PLL_is_valid(struct drm_device *dev,
 610                                const intel_limit_t *limit,
 611                                const intel_clock_t *clock)
 612 {
 613         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 614                 INTELPllInvalid("p1 out of range\n");
 615         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 616                 INTELPllInvalid("p out of range\n");
 617         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 618                 INTELPllInvalid("m2 out of range\n");
 619         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 620                 INTELPllInvalid("m1 out of range\n");
 621         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 622                 INTELPllInvalid("m1 <= m2\n");
 623         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 624                 INTELPllInvalid("m out of range\n");
 625         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 626                 INTELPllInvalid("n out of range\n");
 627         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 628                 INTELPllInvalid("vco out of range\n");
 629         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 630          * connector, etc., rather than just a single range.
 631          */
 632         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 633                 INTELPllInvalid("dot out of range\n");
 634
 635         return true;
 636 }
 637
 638 static bool
 639 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 640                     int target, int refclk, intel_clock_t *match_clock,
 641                     intel_clock_t *best_clock)
 642
 643 {
 644         struct drm_device *dev = crtc->dev;
 645         intel_clock_t clock;
 646         int err = target;
 647
 648         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 649                 /*
 650                  * For LVDS just rely on its current settings for dual-channel.
 651                  * We haven't figured out how to reliably set up different
 652                  * single/dual channel state, if we even can.
 653                  */
 654                 if (intel_is_dual_link_lvds(dev))
 655                         clock.p2 = limit->p2.p2_fast;
 656                 else
 657                         clock.p2 = limit->p2.p2_slow;
 658         } else {
 659                 if (target < limit->p2.dot_limit)
 660                         clock.p2 = limit->p2.p2_slow;
 661                 else
 662                         clock.p2 = limit->p2.p2_fast;
 663         }
 664
 665         memset(best_clock, 0, sizeof(*best_clock));
 666
 667         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 668              clock.m1++) {
 669                 for (clock.m2 = limit->m2.min;
 670                      clock.m2 <= limit->m2.max; clock.m2++) {
 671                         /* m1 is always 0 in Pineview */
 672                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 673                                 break;
 674                         for (clock.n = limit->n.min;
 675                              clock.n <= limit->n.max; clock.n++) {
 676                                 for (clock.p1 = limit->p1.min;
 677                                         clock.p1 <= limit->p1.max; clock.p1++) {
 678                                         int this_err;
 679
 680                                         intel_clock(dev, refclk, &clock);
 681                                         if (!intel_PLL_is_valid(dev, limit,
 682                                                                 &clock))
 683                                                 continue;
 684                                         if (match_clock &&
 685                                             clock.p != match_clock->p)
 686                                                 continue;
 687
 688                                         this_err = abs(clock.dot - target);
 689                                         if (this_err < err) {
 690                                                 *best_clock = clock;
 691                                                 err = this_err;
 692                                         }
 693                                 }
 694                         }
 695                 }
 696         }
 697
 698         return (err != target);
 699 }
 700
 701 static bool
 702 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 703                         int target, int refclk, intel_clock_t *match_clock,
 704                         intel_clock_t *best_clock)
 705 {
 706         struct drm_device *dev = crtc->dev;
 707         intel_clock_t clock;
 708         int max_n;
 709         bool found;
 710         /* approximately equals target * 0.00585 */
 711         int err_most = (target >> 8) + (target >> 9);
 712         found = false;
 713
 714         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 715                 int lvds_reg;
 716
 717                 if (HAS_PCH_SPLIT(dev))
 718                         lvds_reg = PCH_LVDS;
 719                 else
 720                         lvds_reg = LVDS;
 721                 if (intel_is_dual_link_lvds(dev))
 722                         clock.p2 = limit->p2.p2_fast;
 723                 else
 724                         clock.p2 = limit->p2.p2_slow;
 725         } else {
 726                 if (target < limit->p2.dot_limit)
 727                         clock.p2 = limit->p2.p2_slow;
 728                 else
 729                         clock.p2 = limit->p2.p2_fast;
 730         }
 731
 732         memset(best_clock, 0, sizeof(*best_clock));
 733         max_n = limit->n.max;
 734         /* based on hardware requirement, prefer smaller n to precision */
 735         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 736                 /* based on hardware requirement, prefere larger m1,m2 */
 737                 for (clock.m1 = limit->m1.max;
 738                      clock.m1 >= limit->m1.min; clock.m1--) {
 739                         for (clock.m2 = limit->m2.max;
 740                              clock.m2 >= limit->m2.min; clock.m2--) {
 741                                 for (clock.p1 = limit->p1.max;
 742                                      clock.p1 >= limit->p1.min; clock.p1--) {
 743                                         int this_err;
 744
 745                                         intel_clock(dev, refclk, &clock);
 746                                         if (!intel_PLL_is_valid(dev, limit,
 747                                                                 &clock))
 748                                                 continue;
 749                                         if (match_clock &&
 750                                             clock.p != match_clock->p)
 751                                                 continue;
 752
 753                                         this_err = abs(clock.dot - target);
 754                                         if (this_err < err_most) {
 755                                                 *best_clock = clock;
 756                                                 err_most = this_err;
 757                                                 max_n = clock.n;
 758                                                 found = true;
 759                                         }
 760                                 }
 761                         }
 762                 }
 763         }
 764         return found;
 765 }
 766
 767 static bool
 768 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 769                            int target, int refclk, intel_clock_t *match_clock,
 770                            intel_clock_t *best_clock)
 771 {
 772         struct drm_device *dev = crtc->dev;
 773         intel_clock_t clock;
 774
 775         if (target < 200000) {
 776                 clock.n = 1;
 777                 clock.p1 = 2;
 778                 clock.p2 = 10;
 779                 clock.m1 = 12;
 780                 clock.m2 = 9;
 781         } else {
 782                 clock.n = 2;
 783                 clock.p1 = 1;
 784                 clock.p2 = 10;
 785                 clock.m1 = 14;
 786                 clock.m2 = 8;
 787         }
 788         intel_clock(dev, refclk, &clock);
 789         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 790         return true;
 791 }
 792
 793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 794 static bool
 795 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 796                       int target, int refclk, intel_clock_t *match_clock,
 797                       intel_clock_t *best_clock)
 798 {
 799         intel_clock_t clock;
 800         if (target < 200000) {
 801                 clock.p1 = 2;
 802                 clock.p2 = 10;
 803                 clock.n = 2;
 804                 clock.m1 = 23;
 805                 clock.m2 = 8;
 806         } else {
 807                 clock.p1 = 1;
 808                 clock.p2 = 10;
 809                 clock.n = 1;
 810                 clock.m1 = 14;
 811                 clock.m2 = 2;
 812         }
 813         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 814         clock.p = (clock.p1 * clock.p2);
 815         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 816         clock.vco = 0;
 817         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 818         return true;
 819 }
 820 static bool
 821 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 822                         int target, int refclk, intel_clock_t *match_clock,
 823                         intel_clock_t *best_clock)
 824 {
 825         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 826         u32 m, n, fastclk;
 827         u32 updrate, minupdate, fracbits, p;
 828         unsigned long bestppm, ppm, absppm;
 829         int dotclk, flag;
 830
 831         flag = 0;
 832         dotclk = target * 1000;
 833         bestppm = 1000000;
 834         ppm = absppm = 0;
 835         fastclk = dotclk / (2*100);
 836         updrate = 0;
 837         minupdate = 19200;
 838         fracbits = 1;
 839         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 840         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 841
 842         /* based on hardware requirement, prefer smaller n to precision */
 843         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 844                 updrate = refclk / n;
 845                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 846                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 847                                 if (p2 > 10)
 848                                         p2 = p2 - 1;
 849                                 p = p1 * p2;
 850                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 851                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 852                                         m2 = (((2*(fastclk * p * n / m1 )) +
 853                                                refclk) / (2*refclk));
 854                                         m = m1 * m2;
 855                                         vco = updrate * m;
 856                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 857                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 858                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 859                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 860                                                         bestppm = 0;
 861                                                         flag = 1;
 862                                                 }
 863                                                 if (absppm < bestppm - 10) {
 864                                                         bestppm = absppm;
 865                                                         flag = 1;
 866                                                 }
 867                                                 if (flag) {
 868                                                         bestn = n;
 869                                                         bestm1 = m1;
 870                                                         bestm2 = m2;
 871                                                         bestp1 = p1;
 872                                                         bestp2 = p2;
 873                                                         flag = 0;
 874                                                 }
 875                                         }
 876                                 }
 877                         }
 878                 }
 879         }
 880         best_clock->n = bestn;
 881         best_clock->m1 = bestm1;
 882         best_clock->m2 = bestm2;
 883         best_clock->p1 = bestp1;
 884         best_clock->p2 = bestp2;
 885
 886         return true;
 887 }
 888
 889 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 890                                              enum pipe pipe)
 891 {
 892         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 894
 895         return intel_crtc->cpu_transcoder;
 896 }
 897
 898 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 899 {
 900         struct drm_i915_private *dev_priv = dev->dev_private;
 901         u32 frame, frame_reg = PIPEFRAME(pipe);
 902
 903         frame = I915_READ(frame_reg);
 904
 905         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 906                 DRM_DEBUG_KMS("vblank wait timed out\n");
 907 }
 908
 909 /**
 910  * intel_wait_for_vblank - wait for vblank on a given pipe
 911  * @dev: drm device
 912  * @pipe: pipe to wait for
 913  *
 914  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 915  * mode setting code.
 916  */
 917 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 918 {
 919         struct drm_i915_private *dev_priv = dev->dev_private;
 920         int pipestat_reg = PIPESTAT(pipe);
 921
 922         if (INTEL_INFO(dev)->gen >= 5) {
 923                 ironlake_wait_for_vblank(dev, pipe);
 924                 return;
 925         }
 926
 927         /* Clear existing vblank status. Note this will clear any other
 928          * sticky status fields as well.
 929          *
 930          * This races with i915_driver_irq_handler() with the result
 931          * that either function could miss a vblank event.  Here it is not
 932          * fatal, as we will either wait upon the next vblank interrupt or
 933          * timeout.  Generally speaking intel_wait_for_vblank() is only
 934          * called during modeset at which time the GPU should be idle and
 935          * should *not* be performing page flips and thus not waiting on
 936          * vblanks...
 937          * Currently, the result of us stealing a vblank from the irq
 938          * handler is that a single frame will be skipped during swapbuffers.
 939          */
 940         I915_WRITE(pipestat_reg,
 941                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 942
 943         /* Wait for vblank interrupt bit to set */
 944         if (wait_for(I915_READ(pipestat_reg) &
 945                      PIPE_VBLANK_INTERRUPT_STATUS,
 946                      50))
 947                 DRM_DEBUG_KMS("vblank wait timed out\n");
 948 }
 949
 950 /*
 951  * intel_wait_for_pipe_off - wait for pipe to turn off
 952  * @dev: drm device
 953  * @pipe: pipe to wait for
 954  *
 955  * After disabling a pipe, we can't wait for vblank in the usual way,
 956  * spinning on the vblank interrupt status bit, since we won't actually
 957  * see an interrupt when the pipe is disabled.
 958  *
 959  * On Gen4 and above:
 960  *   wait for the pipe register state bit to turn off
 961  *
 962  * Otherwise:
 963  *   wait for the display line value to settle (it usually
 964  *   ends up stopping at the start of the next frame).
 965  *
 966  */
 967 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 968 {
 969         struct drm_i915_private *dev_priv = dev->dev_private;
 970         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 971                                                                       pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 4) {
 974                 int reg = PIPECONF(cpu_transcoder);
 975
 976                 /* Wait for the Pipe State to go off */
 977                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 978                              100))
 979                         WARN(1, "pipe_off wait timed out\n");
 980         } else {
 981                 u32 last_line, line_mask;
 982                 int reg = PIPEDSL(pipe);
 983                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 984
 985                 if (IS_GEN2(dev))
 986                         line_mask = DSL_LINEMASK_GEN2;
 987                 else
 988                         line_mask = DSL_LINEMASK_GEN3;
 989
 990                 /* Wait for the display line to settle */
 991                 do {
 992                         last_line = I915_READ(reg) & line_mask;
 993                         mdelay(5);
 994                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 995                          time_after(timeout, jiffies));
 996                 if (time_after(jiffies, timeout))
 997                         WARN(1, "pipe_off wait timed out\n");
 998         }
 999 }
1000
1001 /*
1002  * ibx_digital_port_connected - is the specified port connected?
1003  * @dev_priv: i915 private structure
1004  * @port: the port to test
1005  *
1006  * Returns true if @port is connected, false otherwise.
1007  */
1008 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009                                 struct intel_digital_port *port)
1010 {
1011         u32 bit;
1012
1013         if (HAS_PCH_IBX(dev_priv->dev)) {
1014                 switch(port->port) {
1015                 case PORT_B:
1016                         bit = SDE_PORTB_HOTPLUG;
1017                         break;
1018                 case PORT_C:
1019                         bit = SDE_PORTC_HOTPLUG;
1020                         break;
1021                 case PORT_D:
1022                         bit = SDE_PORTD_HOTPLUG;
1023                         break;
1024                 default:
1025                         return true;
1026                 }
1027         } else {
1028                 switch(port->port) {
1029                 case PORT_B:
1030                         bit = SDE_PORTB_HOTPLUG_CPT;
1031                         break;
1032                 case PORT_C:
1033                         bit = SDE_PORTC_HOTPLUG_CPT;
1034                         break;
1035                 case PORT_D:
1036                         bit = SDE_PORTD_HOTPLUG_CPT;
1037                         break;
1038                 default:
1039                         return true;
1040                 }
1041         }
1042
1043         return I915_READ(SDEISR) & bit;
1044 }
1045
1046 static const char *state_string(bool enabled)
1047 {
1048         return enabled ? "on" : "off";
1049 }
1050
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private *dev_priv,
1053                        enum pipe pipe, bool state)
1054 {
1055         int reg;
1056         u32 val;
1057         bool cur_state;
1058
1059         reg = DPLL(pipe);
1060         val = I915_READ(reg);
1061         cur_state = !!(val & DPLL_VCO_ENABLE);
1062         WARN(cur_state != state,
1063              "PLL state assertion failure (expected %s, current %s)\n",
1064              state_string(state), state_string(cur_state));
1065 }
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
1069 /* For ILK+ */
1070 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1071                            struct intel_pch_pll *pll,
1072                            struct intel_crtc *crtc,
1073                            bool state)
1074 {
1075         u32 val;
1076         bool cur_state;
1077
1078         if (HAS_PCH_LPT(dev_priv->dev)) {
1079                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080                 return;
1081         }
1082
1083         if (WARN (!pll,
1084                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1085                 return;
1086
1087         val = I915_READ(pll->pll_reg);
1088         cur_state = !!(val & DPLL_VCO_ENABLE);
1089         WARN(cur_state != state,
1090              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091              pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093         /* Make sure the selected PLL is correctly attached to the transcoder */
1094         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1095                 u32 pch_dpll;
1096
1097                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1098                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1101                           cur_state, crtc->pipe, pch_dpll)) {
1102                         cur_state = !!(val >> (4*crtc->pipe + 3));
1103                         WARN(cur_state != state,
1104                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1105                              pll->pll_reg == _PCH_DPLL_B,
1106                              state_string(state),
1107                              crtc->pipe,
1108                              val);
1109                 }
1110         }
1111 }
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1114
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116                           enum pipe pipe, bool state)
1117 {
1118         int reg;
1119         u32 val;
1120         bool cur_state;
1121         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122                                                                       pipe);
1123
1124         if (HAS_DDI(dev_priv->dev)) {
1125                 /* DDI does not have a specific FDI_TX register */
1126                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129         } else {
1130                 reg = FDI_TX_CTL(pipe);
1131                 val = I915_READ(reg);
1132                 cur_state = !!(val & FDI_TX_ENABLE);
1133         }
1134         WARN(cur_state != state,
1135              "FDI TX state assertion failure (expected %s, current %s)\n",
1136              state_string(state), state_string(cur_state));
1137 }
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142                           enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX state assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159                                       enum pipe pipe)
1160 {
1161         int reg;
1162         u32 val;
1163
1164         /* ILK FDI PLL is always enabled */
1165         if (dev_priv->info->gen == 5)
1166                 return;
1167
1168         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169         if (HAS_DDI(dev_priv->dev))
1170                 return;
1171
1172         reg = FDI_TX_CTL(pipe);
1173         val = I915_READ(reg);
1174         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178                                       enum pipe pipe)
1179 {
1180         int reg;
1181         u32 val;
1182
1183         reg = FDI_RX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189                                   enum pipe pipe)
1190 {
1191         int pp_reg, lvds_reg;
1192         u32 val;
1193         enum pipe panel_pipe = PIPE_A;
1194         bool locked = true;
1195
1196         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197                 pp_reg = PCH_PP_CONTROL;
1198                 lvds_reg = PCH_LVDS;
1199         } else {
1200                 pp_reg = PP_CONTROL;
1201                 lvds_reg = LVDS;
1202         }
1203
1204         val = I915_READ(pp_reg);
1205         if (!(val & PANEL_POWER_ON) ||
1206             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207                 locked = false;
1208
1209         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210                 panel_pipe = PIPE_B;
1211
1212         WARN(panel_pipe == pipe && locked,
1213              "panel assertion failure, pipe %c regs locked\n",
1214              pipe_name(pipe));
1215 }
1216
1217 void assert_pipe(struct drm_i915_private *dev_priv,
1218                  enum pipe pipe, bool state)
1219 {
1220         int reg;
1221         u32 val;
1222         bool cur_state;
1223         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224                                                                       pipe);
1225
1226         /* if we need the pipe A quirk it must be always on */
1227         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228                 state = true;
1229
1230         if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231             !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         int reg, i;
1266         u32 val;
1267         int cur_pipe;
1268
1269         /* Planes are fixed to pipes on ILK+ */
1270         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1271                 reg = DSPCNTR(pipe);
1272                 val = I915_READ(reg);
1273                 WARN((val & DISPLAY_PLANE_ENABLE),
1274                      "plane %c assertion failure, should be disabled but not\n",
1275                      plane_name(pipe));
1276                 return;
1277         }
1278
1279         /* Need to check both planes against the pipe */
1280         for (i = 0; i < 2; i++) {
1281                 reg = DSPCNTR(i);
1282                 val = I915_READ(reg);
1283                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284                         DISPPLANE_SEL_PIPE_SHIFT;
1285                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1286                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287                      plane_name(i), pipe_name(pipe));
1288         }
1289 }
1290
1291 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292                                     enum pipe pipe)
1293 {
1294         int reg, i;
1295         u32 val;
1296
1297         if (!IS_VALLEYVIEW(dev_priv->dev))
1298                 return;
1299
1300         /* Need to check both planes against the pipe */
1301         for (i = 0; i < dev_priv->num_plane; i++) {
1302                 reg = SPCNTR(pipe, i);
1303                 val = I915_READ(reg);
1304                 WARN((val & SP_ENABLE),
1305                      "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306                      pipe * 2 + i, pipe_name(pipe));
1307         }
1308 }
1309
1310 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311 {
1312         u32 val;
1313         bool enabled;
1314
1315         if (HAS_PCH_LPT(dev_priv->dev)) {
1316                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1317                 return;
1318         }
1319
1320         val = I915_READ(PCH_DREF_CONTROL);
1321         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322                             DREF_SUPERSPREAD_SOURCE_MASK));
1323         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324 }
1325
1326 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1327                                        enum pipe pipe)
1328 {
1329         int reg;
1330         u32 val;
1331         bool enabled;
1332
1333         reg = TRANSCONF(pipe);
1334         val = I915_READ(reg);
1335         enabled = !!(val & TRANS_ENABLE);
1336         WARN(enabled,
1337              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338              pipe_name(pipe));
1339 }
1340
1341 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342                             enum pipe pipe, u32 port_sel, u32 val)
1343 {
1344         if ((val & DP_PORT_EN) == 0)
1345                 return false;
1346
1347         if (HAS_PCH_CPT(dev_priv->dev)) {
1348                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351                         return false;
1352         } else {
1353                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354                         return false;
1355         }
1356         return true;
1357 }
1358
1359 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360                               enum pipe pipe, u32 val)
1361 {
1362         if ((val & SDVO_ENABLE) == 0)
1363                 return false;
1364
1365         if (HAS_PCH_CPT(dev_priv->dev)) {
1366                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1367                         return false;
1368         } else {
1369                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1370                         return false;
1371         }
1372         return true;
1373 }
1374
1375 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376                               enum pipe pipe, u32 val)
1377 {
1378         if ((val & LVDS_PORT_EN) == 0)
1379                 return false;
1380
1381         if (HAS_PCH_CPT(dev_priv->dev)) {
1382                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1383                         return false;
1384         } else {
1385                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1386                         return false;
1387         }
1388         return true;
1389 }
1390
1391 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392                               enum pipe pipe, u32 val)
1393 {
1394         if ((val & ADPA_DAC_ENABLE) == 0)
1395                 return false;
1396         if (HAS_PCH_CPT(dev_priv->dev)) {
1397                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405
1406 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1407                                    enum pipe pipe, int reg, u32 port_sel)
1408 {
1409         u32 val = I915_READ(reg);
1410         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1411              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1412              reg, pipe_name(pipe));
1413
1414         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415              && (val & DP_PIPEB_SELECT),
1416              "IBX PCH dp port still using transcoder B\n");
1417 }
1418
1419 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420                                      enum pipe pipe, int reg)
1421 {
1422         u32 val = I915_READ(reg);
1423         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1424              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1425              reg, pipe_name(pipe));
1426
1427         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1428              && (val & SDVO_PIPE_B_SELECT),
1429              "IBX PCH hdmi port still using transcoder B\n");
1430 }
1431
1432 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1433                                       enum pipe pipe)
1434 {
1435         int reg;
1436         u32 val;
1437
1438         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1441
1442         reg = PCH_ADPA;
1443         val = I915_READ(reg);
1444         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1445              "PCH VGA enabled on transcoder %c, should be disabled\n",
1446              pipe_name(pipe));
1447
1448         reg = PCH_LVDS;
1449         val = I915_READ(reg);
1450         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1451              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1452              pipe_name(pipe));
1453
1454         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1457 }
1458
1459 /**
1460  * intel_enable_pll - enable a PLL
1461  * @dev_priv: i915 private structure
1462  * @pipe: pipe PLL to enable
1463  *
1464  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1465  * make sure the PLL reg is writable first though, since the panel write
1466  * protect mechanism may be enabled.
1467  *
1468  * Note!  This is for pre-ILK only.
1469  *
1470  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1471  */
1472 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474         int reg;
1475         u32 val;
1476
1477         /* No really, not for ILK+ */
1478         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1479
1480         /* PLL is protected by panel, make sure we can write it */
1481         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1482                 assert_panel_unlocked(dev_priv, pipe);
1483
1484         reg = DPLL(pipe);
1485         val = I915_READ(reg);
1486         val |= DPLL_VCO_ENABLE;
1487
1488         /* We do this three times for luck */
1489         I915_WRITE(reg, val);
1490         POSTING_READ(reg);
1491         udelay(150); /* wait for warmup */
1492         I915_WRITE(reg, val);
1493         POSTING_READ(reg);
1494         udelay(150); /* wait for warmup */
1495         I915_WRITE(reg, val);
1496         POSTING_READ(reg);
1497         udelay(150); /* wait for warmup */
1498 }
1499
1500 /**
1501  * intel_disable_pll - disable a PLL
1502  * @dev_priv: i915 private structure
1503  * @pipe: pipe PLL to disable
1504  *
1505  * Disable the PLL for @pipe, making sure the pipe is off first.
1506  *
1507  * Note!  This is for pre-ILK only.
1508  */
1509 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1510 {
1511         int reg;
1512         u32 val;
1513
1514         /* Don't disable pipe A or pipe A PLLs if needed */
1515         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1516                 return;
1517
1518         /* Make sure the pipe isn't still relying on us */
1519         assert_pipe_disabled(dev_priv, pipe);
1520
1521         reg = DPLL(pipe);
1522         val = I915_READ(reg);
1523         val &= ~DPLL_VCO_ENABLE;
1524         I915_WRITE(reg, val);
1525         POSTING_READ(reg);
1526 }
1527
1528 /* SBI access */
1529 static void
1530 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1531                 enum intel_sbi_destination destination)
1532 {
1533         u32 tmp;
1534
1535         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1536
1537         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1538                                 100)) {
1539                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1540                 return;
1541         }
1542
1543         I915_WRITE(SBI_ADDR, (reg << 16));
1544         I915_WRITE(SBI_DATA, value);
1545
1546         if (destination == SBI_ICLK)
1547                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1548         else
1549                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1550         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1551
1552         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1553                                 100)) {
1554                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1555                 return;
1556         }
1557 }
1558
1559 static u32
1560 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1561                enum intel_sbi_destination destination)
1562 {
1563         u32 value = 0;
1564         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1565
1566         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1567                                 100)) {
1568                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1569                 return 0;
1570         }
1571
1572         I915_WRITE(SBI_ADDR, (reg << 16));
1573
1574         if (destination == SBI_ICLK)
1575                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1576         else
1577                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1578         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1579
1580         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1581                                 100)) {
1582                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1583                 return 0;
1584         }
1585
1586         return I915_READ(SBI_DATA);
1587 }
1588
1589 /**
1590  * ironlake_enable_pch_pll - enable PCH PLL
1591  * @dev_priv: i915 private structure
1592  * @pipe: pipe PLL to enable
1593  *
1594  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595  * drives the transcoder clock.
1596  */
1597 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1598 {
1599         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1600         struct intel_pch_pll *pll;
1601         int reg;
1602         u32 val;
1603
1604         /* PCH PLLs only available on ILK, SNB and IVB */
1605         BUG_ON(dev_priv->info->gen < 5);
1606         pll = intel_crtc->pch_pll;
1607         if (pll == NULL)
1608                 return;
1609
1610         if (WARN_ON(pll->refcount == 0))
1611                 return;
1612
1613         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614                       pll->pll_reg, pll->active, pll->on,
1615                       intel_crtc->base.base.id);
1616
1617         /* PCH refclock must be enabled first */
1618         assert_pch_refclk_enabled(dev_priv);
1619
1620         if (pll->active++ && pll->on) {
1621                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1622                 return;
1623         }
1624
1625         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1626
1627         reg = pll->pll_reg;
1628         val = I915_READ(reg);
1629         val |= DPLL_VCO_ENABLE;
1630         I915_WRITE(reg, val);
1631         POSTING_READ(reg);
1632         udelay(200);
1633
1634         pll->on = true;
1635 }
1636
1637 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1638 {
1639         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1640         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1641         int reg;
1642         u32 val;
1643
1644         /* PCH only available on ILK+ */
1645         BUG_ON(dev_priv->info->gen < 5);
1646         if (pll == NULL)
1647                return;
1648
1649         if (WARN_ON(pll->refcount == 0))
1650                 return;
1651
1652         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653                       pll->pll_reg, pll->active, pll->on,
1654                       intel_crtc->base.base.id);
1655
1656         if (WARN_ON(pll->active == 0)) {
1657                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1658                 return;
1659         }
1660
1661         if (--pll->active) {
1662                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1663                 return;
1664         }
1665
1666         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1667
1668         /* Make sure transcoder isn't still depending on us */
1669         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1670
1671         reg = pll->pll_reg;
1672         val = I915_READ(reg);
1673         val &= ~DPLL_VCO_ENABLE;
1674         I915_WRITE(reg, val);
1675         POSTING_READ(reg);
1676         udelay(200);
1677
1678         pll->on = false;
1679 }
1680
1681 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682                                            enum pipe pipe)
1683 {
1684         struct drm_device *dev = dev_priv->dev;
1685         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1686         uint32_t reg, val, pipeconf_val;
1687
1688         /* PCH only available on ILK+ */
1689         BUG_ON(dev_priv->info->gen < 5);
1690
1691         /* Make sure PCH DPLL is enabled */
1692         assert_pch_pll_enabled(dev_priv,
1693                                to_intel_crtc(crtc)->pch_pll,
1694                                to_intel_crtc(crtc));
1695
1696         /* FDI must be feeding us bits for PCH ports */
1697         assert_fdi_tx_enabled(dev_priv, pipe);
1698         assert_fdi_rx_enabled(dev_priv, pipe);
1699
1700         if (HAS_PCH_CPT(dev)) {
1701                 /* Workaround: Set the timing override bit before enabling the
1702                  * pch transcoder. */
1703                 reg = TRANS_CHICKEN2(pipe);
1704                 val = I915_READ(reg);
1705                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1706                 I915_WRITE(reg, val);
1707         }
1708
1709         reg = TRANSCONF(pipe);
1710         val = I915_READ(reg);
1711         pipeconf_val = I915_READ(PIPECONF(pipe));
1712
1713         if (HAS_PCH_IBX(dev_priv->dev)) {
1714                 /*
1715                  * make the BPC in transcoder be consistent with
1716                  * that in pipeconf reg.
1717                  */
1718                 val &= ~PIPECONF_BPC_MASK;
1719                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1720         }
1721
1722         val &= ~TRANS_INTERLACE_MASK;
1723         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1724                 if (HAS_PCH_IBX(dev_priv->dev) &&
1725                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1726                         val |= TRANS_LEGACY_INTERLACED_ILK;
1727                 else
1728                         val |= TRANS_INTERLACED;
1729         else
1730                 val |= TRANS_PROGRESSIVE;
1731
1732         I915_WRITE(reg, val | TRANS_ENABLE);
1733         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1734                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1735 }
1736
1737 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1738                                       enum transcoder cpu_transcoder)
1739 {
1740         u32 val, pipeconf_val;
1741
1742         /* PCH only available on ILK+ */
1743         BUG_ON(dev_priv->info->gen < 5);
1744
1745         /* FDI must be feeding us bits for PCH ports */
1746         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1747         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1748
1749         /* Workaround: set timing override bit. */
1750         val = I915_READ(_TRANSA_CHICKEN2);
1751         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1752         I915_WRITE(_TRANSA_CHICKEN2, val);
1753
1754         val = TRANS_ENABLE;
1755         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1756
1757         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1758             PIPECONF_INTERLACED_ILK)
1759                 val |= TRANS_INTERLACED;
1760         else
1761                 val |= TRANS_PROGRESSIVE;
1762
1763         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1764         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1765                 DRM_ERROR("Failed to enable PCH transcoder\n");
1766 }
1767
1768 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769                                             enum pipe pipe)
1770 {
1771         struct drm_device *dev = dev_priv->dev;
1772         uint32_t reg, val;
1773
1774         /* FDI relies on the transcoder */
1775         assert_fdi_tx_disabled(dev_priv, pipe);
1776         assert_fdi_rx_disabled(dev_priv, pipe);
1777
1778         /* Ports must be off as well */
1779         assert_pch_ports_disabled(dev_priv, pipe);
1780
1781         reg = TRANSCONF(pipe);
1782         val = I915_READ(reg);
1783         val &= ~TRANS_ENABLE;
1784         I915_WRITE(reg, val);
1785         /* wait for PCH transcoder off, transcoder state */
1786         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1787                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1788
1789         if (!HAS_PCH_IBX(dev)) {
1790                 /* Workaround: Clear the timing override chicken bit again. */
1791                 reg = TRANS_CHICKEN2(pipe);
1792                 val = I915_READ(reg);
1793                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1794                 I915_WRITE(reg, val);
1795         }
1796 }
1797
1798 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1799 {
1800         u32 val;
1801
1802         val = I915_READ(_TRANSACONF);
1803         val &= ~TRANS_ENABLE;
1804         I915_WRITE(_TRANSACONF, val);
1805         /* wait for PCH transcoder off, transcoder state */
1806         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1807                 DRM_ERROR("Failed to disable PCH transcoder\n");
1808
1809         /* Workaround: clear timing override bit. */
1810         val = I915_READ(_TRANSA_CHICKEN2);
1811         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1812         I915_WRITE(_TRANSA_CHICKEN2, val);
1813 }
1814
1815 /**
1816  * intel_enable_pipe - enable a pipe, asserting requirements
1817  * @dev_priv: i915 private structure
1818  * @pipe: pipe to enable
1819  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1820  *
1821  * Enable @pipe, making sure that various hardware specific requirements
1822  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1823  *
1824  * @pipe should be %PIPE_A or %PIPE_B.
1825  *
1826  * Will wait until the pipe is actually running (i.e. first vblank) before
1827  * returning.
1828  */
1829 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1830                               bool pch_port)
1831 {
1832         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1833                                                                       pipe);
1834         enum pipe pch_transcoder;
1835         int reg;
1836         u32 val;
1837
1838         if (HAS_PCH_LPT(dev_priv->dev))
1839                 pch_transcoder = TRANSCODER_A;
1840         else
1841                 pch_transcoder = pipe;
1842
1843         /*
1844          * A pipe without a PLL won't actually be able to drive bits from
1845          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1846          * need the check.
1847          */
1848         if (!HAS_PCH_SPLIT(dev_priv->dev))
1849                 assert_pll_enabled(dev_priv, pipe);
1850         else {
1851                 if (pch_port) {
1852                         /* if driving the PCH, we need FDI enabled */
1853                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1854                         assert_fdi_tx_pll_enabled(dev_priv,
1855                                                   (enum pipe) cpu_transcoder);
1856                 }
1857                 /* FIXME: assert CPU port conditions for SNB+ */
1858         }
1859
1860         reg = PIPECONF(cpu_transcoder);
1861         val = I915_READ(reg);
1862         if (val & PIPECONF_ENABLE)
1863                 return;
1864
1865         I915_WRITE(reg, val | PIPECONF_ENABLE);
1866         intel_wait_for_vblank(dev_priv->dev, pipe);
1867 }
1868
1869 /**
1870  * intel_disable_pipe - disable a pipe, asserting requirements
1871  * @dev_priv: i915 private structure
1872  * @pipe: pipe to disable
1873  *
1874  * Disable @pipe, making sure that various hardware specific requirements
1875  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1876  *
1877  * @pipe should be %PIPE_A or %PIPE_B.
1878  *
1879  * Will wait until the pipe has shut down before returning.
1880  */
1881 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1882                                enum pipe pipe)
1883 {
1884         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1885                                                                       pipe);
1886         int reg;
1887         u32 val;
1888
1889         /*
1890          * Make sure planes won't keep trying to pump pixels to us,
1891          * or we might hang the display.
1892          */
1893         assert_planes_disabled(dev_priv, pipe);
1894         assert_sprites_disabled(dev_priv, pipe);
1895
1896         /* Don't disable pipe A or pipe A PLLs if needed */
1897         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1898                 return;
1899
1900         reg = PIPECONF(cpu_transcoder);
1901         val = I915_READ(reg);
1902         if ((val & PIPECONF_ENABLE) == 0)
1903                 return;
1904
1905         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1906         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1907 }
1908
1909 /*
1910  * Plane regs are double buffered, going from enabled->disabled needs a
1911  * trigger in order to latch.  The display address reg provides this.
1912  */
1913 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1914                                       enum plane plane)
1915 {
1916         if (dev_priv->info->gen >= 4)
1917                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1918         else
1919                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1920 }
1921
1922 /**
1923  * intel_enable_plane - enable a display plane on a given pipe
1924  * @dev_priv: i915 private structure
1925  * @plane: plane to enable
1926  * @pipe: pipe being fed
1927  *
1928  * Enable @plane on @pipe, making sure that @pipe is running first.
1929  */
1930 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1931                                enum plane plane, enum pipe pipe)
1932 {
1933         int reg;
1934         u32 val;
1935
1936         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937         assert_pipe_enabled(dev_priv, pipe);
1938
1939         reg = DSPCNTR(plane);
1940         val = I915_READ(reg);
1941         if (val & DISPLAY_PLANE_ENABLE)
1942                 return;
1943
1944         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1945         intel_flush_display_plane(dev_priv, plane);
1946         intel_wait_for_vblank(dev_priv->dev, pipe);
1947 }
1948
1949 /**
1950  * intel_disable_plane - disable a display plane
1951  * @dev_priv: i915 private structure
1952  * @plane: plane to disable
1953  * @pipe: pipe consuming the data
1954  *
1955  * Disable @plane; should be an independent operation.
1956  */
1957 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1958                                 enum plane plane, enum pipe pipe)
1959 {
1960         int reg;
1961         u32 val;
1962
1963         reg = DSPCNTR(plane);
1964         val = I915_READ(reg);
1965         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1966                 return;
1967
1968         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1969         intel_flush_display_plane(dev_priv, plane);
1970         intel_wait_for_vblank(dev_priv->dev, pipe);
1971 }
1972
1973 static bool need_vtd_wa(struct drm_device *dev)
1974 {
1975 #ifdef CONFIG_INTEL_IOMMU
1976         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977                 return true;
1978 #endif
1979         return false;
1980 }
1981
1982 int
1983 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1984                            struct drm_i915_gem_object *obj,
1985                            struct intel_ring_buffer *pipelined)
1986 {
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         u32 alignment;
1989         int ret;
1990
1991         switch (obj->tiling_mode) {
1992         case I915_TILING_NONE:
1993                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994                         alignment = 128 * 1024;
1995                 else if (INTEL_INFO(dev)->gen >= 4)
1996                         alignment = 4 * 1024;
1997                 else
1998                         alignment = 64 * 1024;
1999                 break;
2000         case I915_TILING_X:
2001                 /* pin() will align the object as required by fence */
2002                 alignment = 0;
2003                 break;
2004         case I915_TILING_Y:
2005                 /* FIXME: Is this true? */
2006                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2007                 return -EINVAL;
2008         default:
2009                 BUG();
2010         }
2011
2012         /* Note that the w/a also requires 64 PTE of padding following the
2013          * bo. We currently fill all unused PTE with the shadow page and so
2014          * we should always have valid PTE following the scanout preventing
2015          * the VT-d warning.
2016          */
2017         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2018                 alignment = 256 * 1024;
2019
2020         dev_priv->mm.interruptible = false;
2021         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2022         if (ret)
2023                 goto err_interruptible;
2024
2025         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2026          * fence, whereas 965+ only requires a fence if using
2027          * framebuffer compression.  For simplicity, we always install
2028          * a fence as the cost is not that onerous.
2029          */
2030         ret = i915_gem_object_get_fence(obj);
2031         if (ret)
2032                 goto err_unpin;
2033
2034         i915_gem_object_pin_fence(obj);
2035
2036         dev_priv->mm.interruptible = true;
2037         return 0;
2038
2039 err_unpin:
2040         i915_gem_object_unpin(obj);
2041 err_interruptible:
2042         dev_priv->mm.interruptible = true;
2043         return ret;
2044 }
2045
2046 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2047 {
2048         i915_gem_object_unpin_fence(obj);
2049         i915_gem_object_unpin(obj);
2050 }
2051
2052 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2053  * is assumed to be a power-of-two. */
2054 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2055                                              unsigned int tiling_mode,
2056                                              unsigned int cpp,
2057                                              unsigned int pitch)
2058 {
2059         if (tiling_mode != I915_TILING_NONE) {
2060                 unsigned int tile_rows, tiles;
2061
2062                 tile_rows = *y / 8;
2063                 *y %= 8;
2064
2065                 tiles = *x / (512/cpp);
2066                 *x %= 512/cpp;
2067
2068                 return tile_rows * pitch * 8 + tiles * 4096;
2069         } else {
2070                 unsigned int offset;
2071
2072                 offset = *y * pitch + *x * cpp;
2073                 *y = 0;
2074                 *x = (offset & 4095) / cpp;
2075                 return offset & -4096;
2076         }
2077 }
2078
2079 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2080                              int x, int y)
2081 {
2082         struct drm_device *dev = crtc->dev;
2083         struct drm_i915_private *dev_priv = dev->dev_private;
2084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085         struct intel_framebuffer *intel_fb;
2086         struct drm_i915_gem_object *obj;
2087         int plane = intel_crtc->plane;
2088         unsigned long linear_offset;
2089         u32 dspcntr;
2090         u32 reg;
2091
2092         switch (plane) {
2093         case 0:
2094         case 1:
2095                 break;
2096         default:
2097                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2098                 return -EINVAL;
2099         }
2100
2101         intel_fb = to_intel_framebuffer(fb);
2102         obj = intel_fb->obj;
2103
2104         reg = DSPCNTR(plane);
2105         dspcntr = I915_READ(reg);
2106         /* Mask out pixel format bits in case we change it */
2107         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2108         switch (fb->pixel_format) {
2109         case DRM_FORMAT_C8:
2110                 dspcntr |= DISPPLANE_8BPP;
2111                 break;
2112         case DRM_FORMAT_XRGB1555:
2113         case DRM_FORMAT_ARGB1555:
2114                 dspcntr |= DISPPLANE_BGRX555;
2115                 break;
2116         case DRM_FORMAT_RGB565:
2117                 dspcntr |= DISPPLANE_BGRX565;
2118                 break;
2119         case DRM_FORMAT_XRGB8888:
2120         case DRM_FORMAT_ARGB8888:
2121                 dspcntr |= DISPPLANE_BGRX888;
2122                 break;
2123         case DRM_FORMAT_XBGR8888:
2124         case DRM_FORMAT_ABGR8888:
2125                 dspcntr |= DISPPLANE_RGBX888;
2126                 break;
2127         case DRM_FORMAT_XRGB2101010:
2128         case DRM_FORMAT_ARGB2101010:
2129                 dspcntr |= DISPPLANE_BGRX101010;
2130                 break;
2131         case DRM_FORMAT_XBGR2101010:
2132         case DRM_FORMAT_ABGR2101010:
2133                 dspcntr |= DISPPLANE_RGBX101010;
2134                 break;
2135         default:
2136                 BUG();
2137         }
2138
2139         if (INTEL_INFO(dev)->gen >= 4) {
2140                 if (obj->tiling_mode != I915_TILING_NONE)
2141                         dspcntr |= DISPPLANE_TILED;
2142                 else
2143                         dspcntr &= ~DISPPLANE_TILED;
2144         }
2145
2146         I915_WRITE(reg, dspcntr);
2147
2148         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2149
2150         if (INTEL_INFO(dev)->gen >= 4) {
2151                 intel_crtc->dspaddr_offset =
2152                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2153                                                        fb->bits_per_pixel / 8,
2154                                                        fb->pitches[0]);
2155                 linear_offset -= intel_crtc->dspaddr_offset;
2156         } else {
2157                 intel_crtc->dspaddr_offset = linear_offset;
2158         }
2159
2160         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2161                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2162         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2163         if (INTEL_INFO(dev)->gen >= 4) {
2164                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2165                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2166                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2167                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2168         } else
2169                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2170         POSTING_READ(reg);
2171
2172         return 0;
2173 }
2174
2175 static int ironlake_update_plane(struct drm_crtc *crtc,
2176                                  struct drm_framebuffer *fb, int x, int y)
2177 {
2178         struct drm_device *dev = crtc->dev;
2179         struct drm_i915_private *dev_priv = dev->dev_private;
2180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181         struct intel_framebuffer *intel_fb;
2182         struct drm_i915_gem_object *obj;
2183         int plane = intel_crtc->plane;
2184         unsigned long linear_offset;
2185         u32 dspcntr;
2186         u32 reg;
2187
2188         switch (plane) {
2189         case 0:
2190         case 1:
2191         case 2:
2192                 break;
2193         default:
2194                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2195                 return -EINVAL;
2196         }
2197
2198         intel_fb = to_intel_framebuffer(fb);
2199         obj = intel_fb->obj;
2200
2201         reg = DSPCNTR(plane);
2202         dspcntr = I915_READ(reg);
2203         /* Mask out pixel format bits in case we change it */
2204         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2205         switch (fb->pixel_format) {
2206         case DRM_FORMAT_C8:
2207                 dspcntr |= DISPPLANE_8BPP;
2208                 break;
2209         case DRM_FORMAT_RGB565:
2210                 dspcntr |= DISPPLANE_BGRX565;
2211                 break;
2212         case DRM_FORMAT_XRGB8888:
2213         case DRM_FORMAT_ARGB8888:
2214                 dspcntr |= DISPPLANE_BGRX888;
2215                 break;
2216         case DRM_FORMAT_XBGR8888:
2217         case DRM_FORMAT_ABGR8888:
2218                 dspcntr |= DISPPLANE_RGBX888;
2219                 break;
2220         case DRM_FORMAT_XRGB2101010:
2221         case DRM_FORMAT_ARGB2101010:
2222                 dspcntr |= DISPPLANE_BGRX101010;
2223                 break;
2224         case DRM_FORMAT_XBGR2101010:
2225         case DRM_FORMAT_ABGR2101010:
2226                 dspcntr |= DISPPLANE_RGBX101010;
2227                 break;
2228         default:
2229                 BUG();
2230         }
2231
2232         if (obj->tiling_mode != I915_TILING_NONE)
2233                 dspcntr |= DISPPLANE_TILED;
2234         else
2235                 dspcntr &= ~DISPPLANE_TILED;
2236
2237         /* must disable */
2238         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2239
2240         I915_WRITE(reg, dspcntr);
2241
2242         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2243         intel_crtc->dspaddr_offset =
2244                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2245                                                fb->bits_per_pixel / 8,
2246                                                fb->pitches[0]);
2247         linear_offset -= intel_crtc->dspaddr_offset;
2248
2249         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2250                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2251         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2252         I915_MODIFY_DISPBASE(DSPSURF(plane),
2253                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2254         if (IS_HASWELL(dev)) {
2255                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2256         } else {
2257                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2258                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2259         }
2260         POSTING_READ(reg);
2261
2262         return 0;
2263 }
2264
2265 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2266 static int
2267 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2268                            int x, int y, enum mode_set_atomic state)
2269 {
2270         struct drm_device *dev = crtc->dev;
2271         struct drm_i915_private *dev_priv = dev->dev_private;
2272
2273         if (dev_priv->display.disable_fbc)
2274                 dev_priv->display.disable_fbc(dev);
2275         intel_increase_pllclock(crtc);
2276
2277         return dev_priv->display.update_plane(crtc, fb, x, y);
2278 }
2279
2280 void intel_display_handle_reset(struct drm_device *dev)
2281 {
2282         struct drm_i915_private *dev_priv = dev->dev_private;
2283         struct drm_crtc *crtc;
2284
2285         /*
2286          * Flips in the rings have been nuked by the reset,
2287          * so complete all pending flips so that user space
2288          * will get its events and not get stuck.
2289          *
2290          * Also update the base address of all primary
2291          * planes to the the last fb to make sure we're
2292          * showing the correct fb after a reset.
2293          *
2294          * Need to make two loops over the crtcs so that we
2295          * don't try to grab a crtc mutex before the
2296          * pending_flip_queue really got woken up.
2297          */
2298
2299         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2300                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2301                 enum plane plane = intel_crtc->plane;
2302
2303                 intel_prepare_page_flip(dev, plane);
2304                 intel_finish_page_flip_plane(dev, plane);
2305         }
2306
2307         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2308                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309
2310                 mutex_lock(&crtc->mutex);
2311                 if (intel_crtc->active)
2312                         dev_priv->display.update_plane(crtc, crtc->fb,
2313                                                        crtc->x, crtc->y);
2314                 mutex_unlock(&crtc->mutex);
2315         }
2316 }
2317
2318 static int
2319 intel_finish_fb(struct drm_framebuffer *old_fb)
2320 {
2321         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2322         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2323         bool was_interruptible = dev_priv->mm.interruptible;
2324         int ret;
2325
2326         /* Big Hammer, we also need to ensure that any pending
2327          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2328          * current scanout is retired before unpinning the old
2329          * framebuffer.
2330          *
2331          * This should only fail upon a hung GPU, in which case we
2332          * can safely continue.
2333          */
2334         dev_priv->mm.interruptible = false;
2335         ret = i915_gem_object_finish_gpu(obj);
2336         dev_priv->mm.interruptible = was_interruptible;
2337
2338         return ret;
2339 }
2340
2341 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2342 {
2343         struct drm_device *dev = crtc->dev;
2344         struct drm_i915_master_private *master_priv;
2345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2346
2347         if (!dev->primary->master)
2348                 return;
2349
2350         master_priv = dev->primary->master->driver_priv;
2351         if (!master_priv->sarea_priv)
2352                 return;
2353
2354         switch (intel_crtc->pipe) {
2355         case 0:
2356                 master_priv->sarea_priv->pipeA_x = x;
2357                 master_priv->sarea_priv->pipeA_y = y;
2358                 break;
2359         case 1:
2360                 master_priv->sarea_priv->pipeB_x = x;
2361                 master_priv->sarea_priv->pipeB_y = y;
2362                 break;
2363         default:
2364                 break;
2365         }
2366 }
2367
2368 static int
2369 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2370                     struct drm_framebuffer *fb)
2371 {
2372         struct drm_device *dev = crtc->dev;
2373         struct drm_i915_private *dev_priv = dev->dev_private;
2374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2375         struct drm_framebuffer *old_fb;
2376         int ret;
2377
2378         /* no fb bound */
2379         if (!fb) {
2380                 DRM_ERROR("No FB bound\n");
2381                 return 0;
2382         }
2383
2384         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2385                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2386                                 intel_crtc->plane,
2387                                 INTEL_INFO(dev)->num_pipes);
2388                 return -EINVAL;
2389         }
2390
2391         mutex_lock(&dev->struct_mutex);
2392         ret = intel_pin_and_fence_fb_obj(dev,
2393                                          to_intel_framebuffer(fb)->obj,
2394                                          NULL);
2395         if (ret != 0) {
2396                 mutex_unlock(&dev->struct_mutex);
2397                 DRM_ERROR("pin & fence failed\n");
2398                 return ret;
2399         }
2400
2401         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2402         if (ret) {
2403                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2404                 mutex_unlock(&dev->struct_mutex);
2405                 DRM_ERROR("failed to update base address\n");
2406                 return ret;
2407         }
2408
2409         old_fb = crtc->fb;
2410         crtc->fb = fb;
2411         crtc->x = x;
2412         crtc->y = y;
2413
2414         if (old_fb) {
2415                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2416                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2417         }
2418
2419         intel_update_fbc(dev);
2420         mutex_unlock(&dev->struct_mutex);
2421
2422         intel_crtc_update_sarea_pos(crtc, x, y);
2423
2424         return 0;
2425 }
2426
2427 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2428 {
2429         struct drm_device *dev = crtc->dev;
2430         struct drm_i915_private *dev_priv = dev->dev_private;
2431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432         int pipe = intel_crtc->pipe;
2433         u32 reg, temp;
2434
2435         /* enable normal train */
2436         reg = FDI_TX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         if (IS_IVYBRIDGE(dev)) {
2439                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2440                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2441         } else {
2442                 temp &= ~FDI_LINK_TRAIN_NONE;
2443                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2444         }
2445         I915_WRITE(reg, temp);
2446
2447         reg = FDI_RX_CTL(pipe);
2448         temp = I915_READ(reg);
2449         if (HAS_PCH_CPT(dev)) {
2450                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2451                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2452         } else {
2453                 temp &= ~FDI_LINK_TRAIN_NONE;
2454                 temp |= FDI_LINK_TRAIN_NONE;
2455         }
2456         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2457
2458         /* wait one idle pattern time */
2459         POSTING_READ(reg);
2460         udelay(1000);
2461
2462         /* IVB wants error correction enabled */
2463         if (IS_IVYBRIDGE(dev))
2464                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2465                            FDI_FE_ERRC_ENABLE);
2466 }
2467
2468 static void ivb_modeset_global_resources(struct drm_device *dev)
2469 {
2470         struct drm_i915_private *dev_priv = dev->dev_private;
2471         struct intel_crtc *pipe_B_crtc =
2472                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2473         struct intel_crtc *pipe_C_crtc =
2474                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2475         uint32_t temp;
2476
2477         /* When everything is off disable fdi C so that we could enable fdi B
2478          * with all lanes. XXX: This misses the case where a pipe is not using
2479          * any pch resources and so doesn't need any fdi lanes. */
2480         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2481                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2482                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2483
2484                 temp = I915_READ(SOUTH_CHICKEN1);
2485                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2486                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2487                 I915_WRITE(SOUTH_CHICKEN1, temp);
2488         }
2489 }
2490
2491 /* The FDI link training functions for ILK/Ibexpeak. */
2492 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2493 {
2494         struct drm_device *dev = crtc->dev;
2495         struct drm_i915_private *dev_priv = dev->dev_private;
2496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2497         int pipe = intel_crtc->pipe;
2498         int plane = intel_crtc->plane;
2499         u32 reg, temp, tries;
2500
2501         /* FDI needs bits from pipe & plane first */
2502         assert_pipe_enabled(dev_priv, pipe);
2503         assert_plane_enabled(dev_priv, plane);
2504
2505         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2506            for train result */
2507         reg = FDI_RX_IMR(pipe);
2508         temp = I915_READ(reg);
2509         temp &= ~FDI_RX_SYMBOL_LOCK;
2510         temp &= ~FDI_RX_BIT_LOCK;
2511         I915_WRITE(reg, temp);
2512         I915_READ(reg);
2513         udelay(150);
2514
2515         /* enable CPU FDI TX and PCH FDI RX */
2516         reg = FDI_TX_CTL(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~(7 << 19);
2519         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2520         temp &= ~FDI_LINK_TRAIN_NONE;
2521         temp |= FDI_LINK_TRAIN_PATTERN_1;
2522         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2523
2524         reg = FDI_RX_CTL(pipe);
2525         temp = I915_READ(reg);
2526         temp &= ~FDI_LINK_TRAIN_NONE;
2527         temp |= FDI_LINK_TRAIN_PATTERN_1;
2528         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2529
2530         POSTING_READ(reg);
2531         udelay(150);
2532
2533         /* Ironlake workaround, enable clock pointer after FDI enable*/
2534         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2535         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2536                    FDI_RX_PHASE_SYNC_POINTER_EN);
2537
2538         reg = FDI_RX_IIR(pipe);
2539         for (tries = 0; tries < 5; tries++) {
2540                 temp = I915_READ(reg);
2541                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2542
2543                 if ((temp & FDI_RX_BIT_LOCK)) {
2544                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2545                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2546                         break;
2547                 }
2548         }
2549         if (tries == 5)
2550                 DRM_ERROR("FDI train 1 fail!\n");
2551
2552         /* Train 2 */
2553         reg = FDI_TX_CTL(pipe);
2554         temp = I915_READ(reg);
2555         temp &= ~FDI_LINK_TRAIN_NONE;
2556         temp |= FDI_LINK_TRAIN_PATTERN_2;
2557         I915_WRITE(reg, temp);
2558
2559         reg = FDI_RX_CTL(pipe);
2560         temp = I915_READ(reg);
2561         temp &= ~FDI_LINK_TRAIN_NONE;
2562         temp |= FDI_LINK_TRAIN_PATTERN_2;
2563         I915_WRITE(reg, temp);
2564
2565         POSTING_READ(reg);
2566         udelay(150);
2567
2568         reg = FDI_RX_IIR(pipe);
2569         for (tries = 0; tries < 5; tries++) {
2570                 temp = I915_READ(reg);
2571                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2572
2573                 if (temp & FDI_RX_SYMBOL_LOCK) {
2574                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2575                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2576                         break;
2577                 }
2578         }
2579         if (tries == 5)
2580                 DRM_ERROR("FDI train 2 fail!\n");
2581
2582         DRM_DEBUG_KMS("FDI train done\n");
2583
2584 }
2585
2586 static const int snb_b_fdi_train_param[] = {
2587         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2588         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2589         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2590         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2591 };
2592
2593 /* The FDI link training functions for SNB/Cougarpoint. */
2594 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2595 {
2596         struct drm_device *dev = crtc->dev;
2597         struct drm_i915_private *dev_priv = dev->dev_private;
2598         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599         int pipe = intel_crtc->pipe;
2600         u32 reg, temp, i, retry;
2601
2602         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2603            for train result */
2604         reg = FDI_RX_IMR(pipe);
2605         temp = I915_READ(reg);
2606         temp &= ~FDI_RX_SYMBOL_LOCK;
2607         temp &= ~FDI_RX_BIT_LOCK;
2608         I915_WRITE(reg, temp);
2609
2610         POSTING_READ(reg);
2611         udelay(150);
2612
2613         /* enable CPU FDI TX and PCH FDI RX */
2614         reg = FDI_TX_CTL(pipe);
2615         temp = I915_READ(reg);
2616         temp &= ~(7 << 19);
2617         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2618         temp &= ~FDI_LINK_TRAIN_NONE;
2619         temp |= FDI_LINK_TRAIN_PATTERN_1;
2620         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2621         /* SNB-B */
2622         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2623         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2624
2625         I915_WRITE(FDI_RX_MISC(pipe),
2626                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2627
2628         reg = FDI_RX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         if (HAS_PCH_CPT(dev)) {
2631                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2633         } else {
2634                 temp &= ~FDI_LINK_TRAIN_NONE;
2635                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2636         }
2637         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639         POSTING_READ(reg);
2640         udelay(150);
2641
2642         for (i = 0; i < 4; i++) {
2643                 reg = FDI_TX_CTL(pipe);
2644                 temp = I915_READ(reg);
2645                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646                 temp |= snb_b_fdi_train_param[i];
2647                 I915_WRITE(reg, temp);
2648
2649                 POSTING_READ(reg);
2650                 udelay(500);
2651
2652                 for (retry = 0; retry < 5; retry++) {
2653                         reg = FDI_RX_IIR(pipe);
2654                         temp = I915_READ(reg);
2655                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656                         if (temp & FDI_RX_BIT_LOCK) {
2657                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2658                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2659                                 break;
2660                         }
2661                         udelay(50);
2662                 }
2663                 if (retry < 5)
2664                         break;
2665         }
2666         if (i == 4)
2667                 DRM_ERROR("FDI train 1 fail!\n");
2668
2669         /* Train 2 */
2670         reg = FDI_TX_CTL(pipe);
2671         temp = I915_READ(reg);
2672         temp &= ~FDI_LINK_TRAIN_NONE;
2673         temp |= FDI_LINK_TRAIN_PATTERN_2;
2674         if (IS_GEN6(dev)) {
2675                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676                 /* SNB-B */
2677                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2678         }
2679         I915_WRITE(reg, temp);
2680
2681         reg = FDI_RX_CTL(pipe);
2682         temp = I915_READ(reg);
2683         if (HAS_PCH_CPT(dev)) {
2684                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2685                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2686         } else {
2687                 temp &= ~FDI_LINK_TRAIN_NONE;
2688                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2689         }
2690         I915_WRITE(reg, temp);
2691
2692         POSTING_READ(reg);
2693         udelay(150);
2694
2695         for (i = 0; i < 4; i++) {
2696                 reg = FDI_TX_CTL(pipe);
2697                 temp = I915_READ(reg);
2698                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699                 temp |= snb_b_fdi_train_param[i];
2700                 I915_WRITE(reg, temp);
2701
2702                 POSTING_READ(reg);
2703                 udelay(500);
2704
2705                 for (retry = 0; retry < 5; retry++) {
2706                         reg = FDI_RX_IIR(pipe);
2707                         temp = I915_READ(reg);
2708                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709                         if (temp & FDI_RX_SYMBOL_LOCK) {
2710                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2712                                 break;
2713                         }
2714                         udelay(50);
2715                 }
2716                 if (retry < 5)
2717                         break;
2718         }
2719         if (i == 4)
2720                 DRM_ERROR("FDI train 2 fail!\n");
2721
2722         DRM_DEBUG_KMS("FDI train done.\n");
2723 }
2724
2725 /* Manual link training for Ivy Bridge A0 parts */
2726 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2727 {
2728         struct drm_device *dev = crtc->dev;
2729         struct drm_i915_private *dev_priv = dev->dev_private;
2730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731         int pipe = intel_crtc->pipe;
2732         u32 reg, temp, i;
2733
2734         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2735            for train result */
2736         reg = FDI_RX_IMR(pipe);
2737         temp = I915_READ(reg);
2738         temp &= ~FDI_RX_SYMBOL_LOCK;
2739         temp &= ~FDI_RX_BIT_LOCK;
2740         I915_WRITE(reg, temp);
2741
2742         POSTING_READ(reg);
2743         udelay(150);
2744
2745         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2746                       I915_READ(FDI_RX_IIR(pipe)));
2747
2748         /* enable CPU FDI TX and PCH FDI RX */
2749         reg = FDI_TX_CTL(pipe);
2750         temp = I915_READ(reg);
2751         temp &= ~(7 << 19);
2752         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2753         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2754         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2755         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2756         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2757         temp |= FDI_COMPOSITE_SYNC;
2758         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2759
2760         I915_WRITE(FDI_RX_MISC(pipe),
2761                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2762
2763         reg = FDI_RX_CTL(pipe);
2764         temp = I915_READ(reg);
2765         temp &= ~FDI_LINK_TRAIN_AUTO;
2766         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2767         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2768         temp |= FDI_COMPOSITE_SYNC;
2769         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2770
2771         POSTING_READ(reg);
2772         udelay(150);
2773
2774         for (i = 0; i < 4; i++) {
2775                 reg = FDI_TX_CTL(pipe);
2776                 temp = I915_READ(reg);
2777                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2778                 temp |= snb_b_fdi_train_param[i];
2779                 I915_WRITE(reg, temp);
2780
2781                 POSTING_READ(reg);
2782                 udelay(500);
2783
2784                 reg = FDI_RX_IIR(pipe);
2785                 temp = I915_READ(reg);
2786                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2787
2788                 if (temp & FDI_RX_BIT_LOCK ||
2789                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2790                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2791                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2792                         break;
2793                 }
2794         }
2795         if (i == 4)
2796                 DRM_ERROR("FDI train 1 fail!\n");
2797
2798         /* Train 2 */
2799         reg = FDI_TX_CTL(pipe);
2800         temp = I915_READ(reg);
2801         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2802         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2803         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2804         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2805         I915_WRITE(reg, temp);
2806
2807         reg = FDI_RX_CTL(pipe);
2808         temp = I915_READ(reg);
2809         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2810         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2811         I915_WRITE(reg, temp);
2812
2813         POSTING_READ(reg);
2814         udelay(150);
2815
2816         for (i = 0; i < 4; i++) {
2817                 reg = FDI_TX_CTL(pipe);
2818                 temp = I915_READ(reg);
2819                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2820                 temp |= snb_b_fdi_train_param[i];
2821                 I915_WRITE(reg, temp);
2822
2823                 POSTING_READ(reg);
2824                 udelay(500);
2825
2826                 reg = FDI_RX_IIR(pipe);
2827                 temp = I915_READ(reg);
2828                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2829
2830                 if (temp & FDI_RX_SYMBOL_LOCK) {
2831                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2832                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2833                         break;
2834                 }
2835         }
2836         if (i == 4)
2837                 DRM_ERROR("FDI train 2 fail!\n");
2838
2839         DRM_DEBUG_KMS("FDI train done.\n");
2840 }
2841
2842 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2843 {
2844         struct drm_device *dev = intel_crtc->base.dev;
2845         struct drm_i915_private *dev_priv = dev->dev_private;
2846         int pipe = intel_crtc->pipe;
2847         u32 reg, temp;
2848
2849
2850         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2851         reg = FDI_RX_CTL(pipe);
2852         temp = I915_READ(reg);
2853         temp &= ~((0x7 << 19) | (0x7 << 16));
2854         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2855         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2856         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2857
2858         POSTING_READ(reg);
2859         udelay(200);
2860
2861         /* Switch from Rawclk to PCDclk */
2862         temp = I915_READ(reg);
2863         I915_WRITE(reg, temp | FDI_PCDCLK);
2864
2865         POSTING_READ(reg);
2866         udelay(200);
2867
2868         /* Enable CPU FDI TX PLL, always on for Ironlake */
2869         reg = FDI_TX_CTL(pipe);
2870         temp = I915_READ(reg);
2871         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2872                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2873
2874                 POSTING_READ(reg);
2875                 udelay(100);
2876         }
2877 }
2878
2879 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2880 {
2881         struct drm_device *dev = intel_crtc->base.dev;
2882         struct drm_i915_private *dev_priv = dev->dev_private;
2883         int pipe = intel_crtc->pipe;
2884         u32 reg, temp;
2885
2886         /* Switch from PCDclk to Rawclk */
2887         reg = FDI_RX_CTL(pipe);
2888         temp = I915_READ(reg);
2889         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2890
2891         /* Disable CPU FDI TX PLL */
2892         reg = FDI_TX_CTL(pipe);
2893         temp = I915_READ(reg);
2894         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2895
2896         POSTING_READ(reg);
2897         udelay(100);
2898
2899         reg = FDI_RX_CTL(pipe);
2900         temp = I915_READ(reg);
2901         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2902
2903         /* Wait for the clocks to turn off. */
2904         POSTING_READ(reg);
2905         udelay(100);
2906 }
2907
2908 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2909 {
2910         struct drm_device *dev = crtc->dev;
2911         struct drm_i915_private *dev_priv = dev->dev_private;
2912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2913         int pipe = intel_crtc->pipe;
2914         u32 reg, temp;
2915
2916         /* disable CPU FDI tx and PCH FDI rx */
2917         reg = FDI_TX_CTL(pipe);
2918         temp = I915_READ(reg);
2919         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2920         POSTING_READ(reg);
2921
2922         reg = FDI_RX_CTL(pipe);
2923         temp = I915_READ(reg);
2924         temp &= ~(0x7 << 16);
2925         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2926         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2927
2928         POSTING_READ(reg);
2929         udelay(100);
2930
2931         /* Ironlake workaround, disable clock pointer after downing FDI */
2932         if (HAS_PCH_IBX(dev)) {
2933                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2934         }
2935
2936         /* still set train pattern 1 */
2937         reg = FDI_TX_CTL(pipe);
2938         temp = I915_READ(reg);
2939         temp &= ~FDI_LINK_TRAIN_NONE;
2940         temp |= FDI_LINK_TRAIN_PATTERN_1;
2941         I915_WRITE(reg, temp);
2942
2943         reg = FDI_RX_CTL(pipe);
2944         temp = I915_READ(reg);
2945         if (HAS_PCH_CPT(dev)) {
2946                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2947                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2948         } else {
2949                 temp &= ~FDI_LINK_TRAIN_NONE;
2950                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2951         }
2952         /* BPC in FDI rx is consistent with that in PIPECONF */
2953         temp &= ~(0x07 << 16);
2954         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2955         I915_WRITE(reg, temp);
2956
2957         POSTING_READ(reg);
2958         udelay(100);
2959 }
2960
2961 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2962 {
2963         struct drm_device *dev = crtc->dev;
2964         struct drm_i915_private *dev_priv = dev->dev_private;
2965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2966         unsigned long flags;
2967         bool pending;
2968
2969         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2970             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2971                 return false;
2972
2973         spin_lock_irqsave(&dev->event_lock, flags);
2974         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2975         spin_unlock_irqrestore(&dev->event_lock, flags);
2976
2977         return pending;
2978 }
2979
2980 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2981 {
2982         struct drm_device *dev = crtc->dev;
2983         struct drm_i915_private *dev_priv = dev->dev_private;
2984
2985         if (crtc->fb == NULL)
2986                 return;
2987
2988         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2989
2990         wait_event(dev_priv->pending_flip_queue,
2991                    !intel_crtc_has_pending_flip(crtc));
2992
2993         mutex_lock(&dev->struct_mutex);
2994         intel_finish_fb(crtc->fb);
2995         mutex_unlock(&dev->struct_mutex);
2996 }
2997
2998 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2999 {
3000         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3001 }
3002
3003 /* Program iCLKIP clock to the desired frequency */
3004 static void lpt_program_iclkip(struct drm_crtc *crtc)
3005 {
3006         struct drm_device *dev = crtc->dev;
3007         struct drm_i915_private *dev_priv = dev->dev_private;
3008         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3009         u32 temp;
3010
3011         mutex_lock(&dev_priv->dpio_lock);
3012
3013         /* It is necessary to ungate the pixclk gate prior to programming
3014          * the divisors, and gate it back when it is done.
3015          */
3016         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3017
3018         /* Disable SSCCTL */
3019         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3020                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3021                                 SBI_SSCCTL_DISABLE,
3022                         SBI_ICLK);
3023
3024         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3025         if (crtc->mode.clock == 20000) {
3026                 auxdiv = 1;
3027                 divsel = 0x41;
3028                 phaseinc = 0x20;
3029         } else {
3030                 /* The iCLK virtual clock root frequency is in MHz,
3031                  * but the crtc->mode.clock in in KHz. To get the divisors,
3032                  * it is necessary to divide one by another, so we
3033                  * convert the virtual clock precision to KHz here for higher
3034                  * precision.
3035                  */
3036                 u32 iclk_virtual_root_freq = 172800 * 1000;
3037                 u32 iclk_pi_range = 64;
3038                 u32 desired_divisor, msb_divisor_value, pi_value;
3039
3040                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3041                 msb_divisor_value = desired_divisor / iclk_pi_range;
3042                 pi_value = desired_divisor % iclk_pi_range;
3043
3044                 auxdiv = 0;
3045                 divsel = msb_divisor_value - 2;
3046                 phaseinc = pi_value;
3047         }
3048
3049         /* This should not happen with any sane values */
3050         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3051                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3052         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3053                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3054
3055         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3056                         crtc->mode.clock,
3057                         auxdiv,
3058                         divsel,
3059                         phasedir,
3060                         phaseinc);
3061
3062         /* Program SSCDIVINTPHASE6 */
3063         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3064         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3065         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3066         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3067         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3068         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3069         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3070         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3071
3072         /* Program SSCAUXDIV */
3073         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3074         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3075         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3076         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3077
3078         /* Enable modulator and associated divider */
3079         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3080         temp &= ~SBI_SSCCTL_DISABLE;
3081         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3082
3083         /* Wait for initialization time */
3084         udelay(24);
3085
3086         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3087
3088         mutex_unlock(&dev_priv->dpio_lock);
3089 }
3090
3091 /*
3092  * Enable PCH resources required for PCH ports:
3093  *   - PCH PLLs
3094  *   - FDI training & RX/TX
3095  *   - update transcoder timings
3096  *   - DP transcoding bits
3097  *   - transcoder
3098  */
3099 static void ironlake_pch_enable(struct drm_crtc *crtc)
3100 {
3101         struct drm_device *dev = crtc->dev;
3102         struct drm_i915_private *dev_priv = dev->dev_private;
3103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3104         int pipe = intel_crtc->pipe;
3105         u32 reg, temp;
3106
3107         assert_transcoder_disabled(dev_priv, pipe);
3108
3109         /* Write the TU size bits before fdi link training, so that error
3110          * detection works. */
3111         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3112                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3113
3114         /* For PCH output, training FDI link */
3115         dev_priv->display.fdi_link_train(crtc);
3116
3117         /* XXX: pch pll's can be enabled any time before we enable the PCH
3118          * transcoder, and we actually should do this to not upset any PCH
3119          * transcoder that already use the clock when we share it.
3120          *
3121          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3122          * unconditionally resets the pll - we need that to have the right LVDS
3123          * enable sequence. */
3124         ironlake_enable_pch_pll(intel_crtc);
3125
3126         if (HAS_PCH_CPT(dev)) {
3127                 u32 sel;
3128
3129                 temp = I915_READ(PCH_DPLL_SEL);
3130                 switch (pipe) {
3131                 default:
3132                 case 0:
3133                         temp |= TRANSA_DPLL_ENABLE;
3134                         sel = TRANSA_DPLLB_SEL;
3135                         break;
3136                 case 1:
3137                         temp |= TRANSB_DPLL_ENABLE;
3138                         sel = TRANSB_DPLLB_SEL;
3139                         break;
3140                 case 2:
3141                         temp |= TRANSC_DPLL_ENABLE;
3142                         sel = TRANSC_DPLLB_SEL;
3143                         break;
3144                 }
3145                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3146                         temp |= sel;
3147                 else
3148                         temp &= ~sel;
3149                 I915_WRITE(PCH_DPLL_SEL, temp);
3150         }
3151
3152         /* set transcoder timing, panel must allow it */
3153         assert_panel_unlocked(dev_priv, pipe);
3154         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3155         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3156         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3157
3158         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3159         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3160         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3161         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3162
3163         intel_fdi_normal_train(crtc);
3164
3165         /* For PCH DP, enable TRANS_DP_CTL */
3166         if (HAS_PCH_CPT(dev) &&
3167             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3168              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3169                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3170                 reg = TRANS_DP_CTL(pipe);
3171                 temp = I915_READ(reg);
3172                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3173                           TRANS_DP_SYNC_MASK |
3174                           TRANS_DP_BPC_MASK);
3175                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3176                          TRANS_DP_ENH_FRAMING);
3177                 temp |= bpc << 9; /* same format but at 11:9 */
3178
3179                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3180                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3181                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3182                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3183
3184                 switch (intel_trans_dp_port_sel(crtc)) {
3185                 case PCH_DP_B:
3186                         temp |= TRANS_DP_PORT_SEL_B;
3187                         break;
3188                 case PCH_DP_C:
3189                         temp |= TRANS_DP_PORT_SEL_C;
3190                         break;
3191                 case PCH_DP_D:
3192                         temp |= TRANS_DP_PORT_SEL_D;
3193                         break;
3194                 default:
3195                         BUG();
3196                 }
3197
3198                 I915_WRITE(reg, temp);
3199         }
3200
3201         ironlake_enable_pch_transcoder(dev_priv, pipe);
3202 }
3203
3204 static void lpt_pch_enable(struct drm_crtc *crtc)
3205 {
3206         struct drm_device *dev = crtc->dev;
3207         struct drm_i915_private *dev_priv = dev->dev_private;
3208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3209         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3210
3211         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3212
3213         lpt_program_iclkip(crtc);
3214
3215         /* Set transcoder timing. */
3216         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3217         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3218         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3219
3220         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3221         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3222         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3223         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3224
3225         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3226 }
3227
3228 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3229 {
3230         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3231
3232         if (pll == NULL)
3233                 return;
3234
3235         if (pll->refcount == 0) {
3236                 WARN(1, "bad PCH PLL refcount\n");
3237                 return;
3238         }
3239
3240         --pll->refcount;
3241         intel_crtc->pch_pll = NULL;
3242 }
3243
3244 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3245 {
3246         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3247         struct intel_pch_pll *pll;
3248         int i;
3249
3250         pll = intel_crtc->pch_pll;
3251         if (pll) {
3252                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3253                               intel_crtc->base.base.id, pll->pll_reg);
3254                 goto prepare;
3255         }
3256
3257         if (HAS_PCH_IBX(dev_priv->dev)) {
3258                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3259                 i = intel_crtc->pipe;
3260                 pll = &dev_priv->pch_plls[i];
3261
3262                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3263                               intel_crtc->base.base.id, pll->pll_reg);
3264
3265                 goto found;
3266         }
3267
3268         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3269                 pll = &dev_priv->pch_plls[i];
3270
3271                 /* Only want to check enabled timings first */
3272                 if (pll->refcount == 0)
3273                         continue;
3274
3275                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3276                     fp == I915_READ(pll->fp0_reg)) {
3277                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3278                                       intel_crtc->base.base.id,
3279                                       pll->pll_reg, pll->refcount, pll->active);
3280
3281                         goto found;
3282                 }
3283         }
3284
3285         /* Ok no matching timings, maybe there's a free one? */
3286         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3287                 pll = &dev_priv->pch_plls[i];
3288                 if (pll->refcount == 0) {
3289                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3290                                       intel_crtc->base.base.id, pll->pll_reg);
3291                         goto found;
3292                 }
3293         }
3294
3295         return NULL;
3296
3297 found:
3298         intel_crtc->pch_pll = pll;
3299         pll->refcount++;
3300         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3301 prepare: /* separate function? */
3302         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3303
3304         /* Wait for the clocks to stabilize before rewriting the regs */
3305         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3306         POSTING_READ(pll->pll_reg);
3307         udelay(150);
3308
3309         I915_WRITE(pll->fp0_reg, fp);
3310         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3311         pll->on = false;
3312         return pll;
3313 }
3314
3315 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3316 {
3317         struct drm_i915_private *dev_priv = dev->dev_private;
3318         int dslreg = PIPEDSL(pipe);
3319         u32 temp;
3320
3321         temp = I915_READ(dslreg);
3322         udelay(500);
3323         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3324                 if (wait_for(I915_READ(dslreg) != temp, 5))
3325                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3326         }
3327 }
3328
3329 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3330 {
3331         struct drm_device *dev = crtc->dev;
3332         struct drm_i915_private *dev_priv = dev->dev_private;
3333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3334         struct intel_encoder *encoder;
3335         int pipe = intel_crtc->pipe;
3336         int plane = intel_crtc->plane;
3337         u32 temp;
3338
3339         WARN_ON(!crtc->enabled);
3340
3341         if (intel_crtc->active)
3342                 return;
3343
3344         intel_crtc->active = true;
3345         intel_update_watermarks(dev);
3346
3347         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3348                 temp = I915_READ(PCH_LVDS);
3349                 if ((temp & LVDS_PORT_EN) == 0)
3350                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3351         }
3352
3353
3354         if (intel_crtc->config.has_pch_encoder) {
3355                 /* Note: FDI PLL enabling _must_ be done before we enable the
3356                  * cpu pipes, hence this is separate from all the other fdi/pch
3357                  * enabling. */
3358                 ironlake_fdi_pll_enable(intel_crtc);
3359         } else {
3360                 assert_fdi_tx_disabled(dev_priv, pipe);
3361                 assert_fdi_rx_disabled(dev_priv, pipe);
3362         }
3363
3364         for_each_encoder_on_crtc(dev, crtc, encoder)
3365                 if (encoder->pre_enable)
3366                         encoder->pre_enable(encoder);
3367
3368         /* Enable panel fitting for LVDS */
3369         if (dev_priv->pch_pf_size &&
3370             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3371              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3372                 /* Force use of hard-coded filter coefficients
3373                  * as some pre-programmed values are broken,
3374                  * e.g. x201.
3375                  */
3376                 if (IS_IVYBRIDGE(dev))
3377                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3378                                                  PF_PIPE_SEL_IVB(pipe));
3379                 else
3380                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3381                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3382                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3383         }
3384
3385         /*
3386          * On ILK+ LUT must be loaded before the pipe is running but with
3387          * clocks enabled
3388          */
3389         intel_crtc_load_lut(crtc);
3390
3391         intel_enable_pipe(dev_priv, pipe,
3392                           intel_crtc->config.has_pch_encoder);
3393         intel_enable_plane(dev_priv, plane, pipe);
3394
3395         if (intel_crtc->config.has_pch_encoder)
3396                 ironlake_pch_enable(crtc);
3397
3398         mutex_lock(&dev->struct_mutex);
3399         intel_update_fbc(dev);
3400         mutex_unlock(&dev->struct_mutex);
3401
3402         intel_crtc_update_cursor(crtc, true);
3403
3404         for_each_encoder_on_crtc(dev, crtc, encoder)
3405                 encoder->enable(encoder);
3406
3407         if (HAS_PCH_CPT(dev))
3408                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3409
3410         /*
3411          * There seems to be a race in PCH platform hw (at least on some
3412          * outputs) where an enabled pipe still completes any pageflip right
3413          * away (as if the pipe is off) instead of waiting for vblank. As soon
3414          * as the first vblank happend, everything works as expected. Hence just
3415          * wait for one vblank before returning to avoid strange things
3416          * happening.
3417          */
3418         intel_wait_for_vblank(dev, intel_crtc->pipe);
3419 }
3420
3421 static void haswell_crtc_enable(struct drm_crtc *crtc)
3422 {
3423         struct drm_device *dev = crtc->dev;
3424         struct drm_i915_private *dev_priv = dev->dev_private;
3425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3426         struct intel_encoder *encoder;
3427         int pipe = intel_crtc->pipe;
3428         int plane = intel_crtc->plane;
3429
3430         WARN_ON(!crtc->enabled);
3431
3432         if (intel_crtc->active)
3433                 return;
3434
3435         intel_crtc->active = true;
3436         intel_update_watermarks(dev);
3437
3438         if (intel_crtc->config.has_pch_encoder)
3439                 dev_priv->display.fdi_link_train(crtc);
3440
3441         for_each_encoder_on_crtc(dev, crtc, encoder)
3442                 if (encoder->pre_enable)
3443                         encoder->pre_enable(encoder);
3444
3445         intel_ddi_enable_pipe_clock(intel_crtc);
3446
3447         /* Enable panel fitting for eDP */
3448         if (dev_priv->pch_pf_size &&
3449             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3450                 /* Force use of hard-coded filter coefficients
3451                  * as some pre-programmed values are broken,
3452                  * e.g. x201.
3453                  */
3454                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3455                                          PF_PIPE_SEL_IVB(pipe));
3456                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3457                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3458         }
3459
3460         /*
3461          * On ILK+ LUT must be loaded before the pipe is running but with
3462          * clocks enabled
3463          */
3464         intel_crtc_load_lut(crtc);
3465
3466         intel_ddi_set_pipe_settings(crtc);
3467         intel_ddi_enable_transcoder_func(crtc);
3468
3469         intel_enable_pipe(dev_priv, pipe,
3470                           intel_crtc->config.has_pch_encoder);
3471         intel_enable_plane(dev_priv, plane, pipe);
3472
3473         if (intel_crtc->config.has_pch_encoder)
3474                 lpt_pch_enable(crtc);
3475
3476         mutex_lock(&dev->struct_mutex);
3477         intel_update_fbc(dev);
3478         mutex_unlock(&dev->struct_mutex);
3479
3480         intel_crtc_update_cursor(crtc, true);
3481
3482         for_each_encoder_on_crtc(dev, crtc, encoder)
3483                 encoder->enable(encoder);
3484
3485         /*
3486          * There seems to be a race in PCH platform hw (at least on some
3487          * outputs) where an enabled pipe still completes any pageflip right
3488          * away (as if the pipe is off) instead of waiting for vblank. As soon
3489          * as the first vblank happend, everything works as expected. Hence just
3490          * wait for one vblank before returning to avoid strange things
3491          * happening.
3492          */
3493         intel_wait_for_vblank(dev, intel_crtc->pipe);
3494 }
3495
3496 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3497 {
3498         struct drm_device *dev = crtc->dev;
3499         struct drm_i915_private *dev_priv = dev->dev_private;
3500         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3501         struct intel_encoder *encoder;
3502         int pipe = intel_crtc->pipe;
3503         int plane = intel_crtc->plane;
3504         u32 reg, temp;
3505
3506
3507         if (!intel_crtc->active)
3508                 return;
3509
3510         for_each_encoder_on_crtc(dev, crtc, encoder)
3511                 encoder->disable(encoder);
3512
3513         intel_crtc_wait_for_pending_flips(crtc);
3514         drm_vblank_off(dev, pipe);
3515         intel_crtc_update_cursor(crtc, false);
3516
3517         intel_disable_plane(dev_priv, plane, pipe);
3518
3519         if (dev_priv->cfb_plane == plane)
3520                 intel_disable_fbc(dev);
3521
3522         intel_disable_pipe(dev_priv, pipe);
3523
3524         /* Disable PF */
3525         I915_WRITE(PF_CTL(pipe), 0);
3526         I915_WRITE(PF_WIN_SZ(pipe), 0);
3527
3528         for_each_encoder_on_crtc(dev, crtc, encoder)
3529                 if (encoder->post_disable)
3530                         encoder->post_disable(encoder);
3531
3532         ironlake_fdi_disable(crtc);
3533
3534         ironlake_disable_pch_transcoder(dev_priv, pipe);
3535
3536         if (HAS_PCH_CPT(dev)) {
3537                 /* disable TRANS_DP_CTL */
3538                 reg = TRANS_DP_CTL(pipe);
3539                 temp = I915_READ(reg);
3540                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3541                 temp |= TRANS_DP_PORT_SEL_NONE;
3542                 I915_WRITE(reg, temp);
3543
3544                 /* disable DPLL_SEL */
3545                 temp = I915_READ(PCH_DPLL_SEL);
3546                 switch (pipe) {
3547                 case 0:
3548                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3549                         break;
3550                 case 1:
3551                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3552                         break;
3553                 case 2:
3554                         /* C shares PLL A or B */
3555                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3556                         break;
3557                 default:
3558                         BUG(); /* wtf */
3559                 }
3560                 I915_WRITE(PCH_DPLL_SEL, temp);
3561         }
3562
3563         /* disable PCH DPLL */
3564         intel_disable_pch_pll(intel_crtc);
3565
3566         ironlake_fdi_pll_disable(intel_crtc);
3567
3568         intel_crtc->active = false;
3569         intel_update_watermarks(dev);
3570
3571         mutex_lock(&dev->struct_mutex);
3572         intel_update_fbc(dev);
3573         mutex_unlock(&dev->struct_mutex);
3574 }
3575
3576 static void haswell_crtc_disable(struct drm_crtc *crtc)
3577 {
3578         struct drm_device *dev = crtc->dev;
3579         struct drm_i915_private *dev_priv = dev->dev_private;
3580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581         struct intel_encoder *encoder;
3582         int pipe = intel_crtc->pipe;
3583         int plane = intel_crtc->plane;
3584         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3585         bool is_pch_port;
3586
3587         if (!intel_crtc->active)
3588                 return;
3589
3590         is_pch_port = haswell_crtc_driving_pch(crtc);
3591
3592         for_each_encoder_on_crtc(dev, crtc, encoder)
3593                 encoder->disable(encoder);
3594
3595         intel_crtc_wait_for_pending_flips(crtc);
3596         drm_vblank_off(dev, pipe);
3597         intel_crtc_update_cursor(crtc, false);
3598
3599         intel_disable_plane(dev_priv, plane, pipe);
3600
3601         if (dev_priv->cfb_plane == plane)
3602                 intel_disable_fbc(dev);
3603
3604         intel_disable_pipe(dev_priv, pipe);
3605
3606         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3607
3608         /* Disable PF */
3609         I915_WRITE(PF_CTL(pipe), 0);
3610         I915_WRITE(PF_WIN_SZ(pipe), 0);
3611
3612         intel_ddi_disable_pipe_clock(intel_crtc);
3613
3614         for_each_encoder_on_crtc(dev, crtc, encoder)
3615                 if (encoder->post_disable)
3616                         encoder->post_disable(encoder);
3617
3618         if (is_pch_port) {
3619                 lpt_disable_pch_transcoder(dev_priv);
3620                 intel_ddi_fdi_disable(crtc);
3621         }
3622
3623         intel_crtc->active = false;
3624         intel_update_watermarks(dev);
3625
3626         mutex_lock(&dev->struct_mutex);
3627         intel_update_fbc(dev);
3628         mutex_unlock(&dev->struct_mutex);
3629 }
3630
3631 static void ironlake_crtc_off(struct drm_crtc *crtc)
3632 {
3633         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634         intel_put_pch_pll(intel_crtc);
3635 }
3636
3637 static void haswell_crtc_off(struct drm_crtc *crtc)
3638 {
3639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3640
3641         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3642          * start using it. */
3643         intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3644
3645         intel_ddi_put_crtc_pll(crtc);
3646 }
3647
3648 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3649 {
3650         if (!enable && intel_crtc->overlay) {
3651                 struct drm_device *dev = intel_crtc->base.dev;
3652                 struct drm_i915_private *dev_priv = dev->dev_private;
3653
3654                 mutex_lock(&dev->struct_mutex);
3655                 dev_priv->mm.interruptible = false;
3656                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3657                 dev_priv->mm.interruptible = true;
3658                 mutex_unlock(&dev->struct_mutex);
3659         }
3660
3661         /* Let userspace switch the overlay on again. In most cases userspace
3662          * has to recompute where to put it anyway.
3663          */
3664 }
3665
3666 /**
3667  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3668  * cursor plane briefly if not already running after enabling the display
3669  * plane.
3670  * This workaround avoids occasional blank screens when self refresh is
3671  * enabled.
3672  */
3673 static void
3674 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3675 {
3676         u32 cntl = I915_READ(CURCNTR(pipe));
3677
3678         if ((cntl & CURSOR_MODE) == 0) {
3679                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3680
3681                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3682                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3683                 intel_wait_for_vblank(dev_priv->dev, pipe);
3684                 I915_WRITE(CURCNTR(pipe), cntl);
3685                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3686                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3687         }
3688 }
3689
3690 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3691 {
3692         struct drm_device *dev = crtc->dev;
3693         struct drm_i915_private *dev_priv = dev->dev_private;
3694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695         struct intel_encoder *encoder;
3696         int pipe = intel_crtc->pipe;
3697         int plane = intel_crtc->plane;
3698
3699         WARN_ON(!crtc->enabled);
3700
3701         if (intel_crtc->active)
3702                 return;
3703
3704         intel_crtc->active = true;
3705         intel_update_watermarks(dev);
3706
3707         intel_enable_pll(dev_priv, pipe);
3708
3709         for_each_encoder_on_crtc(dev, crtc, encoder)
3710                 if (encoder->pre_enable)
3711                         encoder->pre_enable(encoder);
3712
3713         intel_enable_pipe(dev_priv, pipe, false);
3714         intel_enable_plane(dev_priv, plane, pipe);
3715         if (IS_G4X(dev))
3716                 g4x_fixup_plane(dev_priv, pipe);
3717
3718         intel_crtc_load_lut(crtc);
3719         intel_update_fbc(dev);
3720
3721         /* Give the overlay scaler a chance to enable if it's on this pipe */
3722         intel_crtc_dpms_overlay(intel_crtc, true);
3723         intel_crtc_update_cursor(crtc, true);
3724
3725         for_each_encoder_on_crtc(dev, crtc, encoder)
3726                 encoder->enable(encoder);
3727 }
3728
3729 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3730 {
3731         struct drm_device *dev = crtc->dev;
3732         struct drm_i915_private *dev_priv = dev->dev_private;
3733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3734         struct intel_encoder *encoder;
3735         int pipe = intel_crtc->pipe;
3736         int plane = intel_crtc->plane;
3737         u32 pctl;
3738
3739
3740         if (!intel_crtc->active)
3741                 return;
3742
3743         for_each_encoder_on_crtc(dev, crtc, encoder)
3744                 encoder->disable(encoder);
3745
3746         /* Give the overlay scaler a chance to disable if it's on this pipe */
3747         intel_crtc_wait_for_pending_flips(crtc);
3748         drm_vblank_off(dev, pipe);
3749         intel_crtc_dpms_overlay(intel_crtc, false);
3750         intel_crtc_update_cursor(crtc, false);
3751
3752         if (dev_priv->cfb_plane == plane)
3753                 intel_disable_fbc(dev);
3754
3755         intel_disable_plane(dev_priv, plane, pipe);
3756         intel_disable_pipe(dev_priv, pipe);
3757
3758         /* Disable pannel fitter if it is on this pipe. */
3759         pctl = I915_READ(PFIT_CONTROL);
3760         if ((pctl & PFIT_ENABLE) &&
3761             ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3762                 I915_WRITE(PFIT_CONTROL, 0);
3763
3764         intel_disable_pll(dev_priv, pipe);
3765
3766         intel_crtc->active = false;
3767         intel_update_fbc(dev);
3768         intel_update_watermarks(dev);
3769 }
3770
3771 static void i9xx_crtc_off(struct drm_crtc *crtc)
3772 {
3773 }
3774
3775 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3776                                     bool enabled)
3777 {
3778         struct drm_device *dev = crtc->dev;
3779         struct drm_i915_master_private *master_priv;
3780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3781         int pipe = intel_crtc->pipe;
3782
3783         if (!dev->primary->master)
3784                 return;
3785
3786         master_priv = dev->primary->master->driver_priv;
3787         if (!master_priv->sarea_priv)
3788                 return;
3789
3790         switch (pipe) {
3791         case 0:
3792                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3793                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3794                 break;
3795         case 1:
3796                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3797                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3798                 break;
3799         default:
3800                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3801                 break;
3802         }
3803 }
3804
3805 /**
3806  * Sets the power management mode of the pipe and plane.
3807  */
3808 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3809 {
3810         struct drm_device *dev = crtc->dev;
3811         struct drm_i915_private *dev_priv = dev->dev_private;
3812         struct intel_encoder *intel_encoder;
3813         bool enable = false;
3814
3815         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3816                 enable |= intel_encoder->connectors_active;
3817
3818         if (enable)
3819                 dev_priv->display.crtc_enable(crtc);
3820         else
3821                 dev_priv->display.crtc_disable(crtc);
3822
3823         intel_crtc_update_sarea(crtc, enable);
3824 }
3825
3826 static void intel_crtc_disable(struct drm_crtc *crtc)
3827 {
3828         struct drm_device *dev = crtc->dev;
3829         struct drm_connector *connector;
3830         struct drm_i915_private *dev_priv = dev->dev_private;
3831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3832
3833         /* crtc should still be enabled when we disable it. */
3834         WARN_ON(!crtc->enabled);
3835
3836         intel_crtc->eld_vld = false;
3837         dev_priv->display.crtc_disable(crtc);
3838         intel_crtc_update_sarea(crtc, false);
3839         dev_priv->display.off(crtc);
3840
3841         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3842         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3843
3844         if (crtc->fb) {
3845                 mutex_lock(&dev->struct_mutex);
3846                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3847                 mutex_unlock(&dev->struct_mutex);
3848                 crtc->fb = NULL;
3849         }
3850
3851         /* Update computed state. */
3852         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3853                 if (!connector->encoder || !connector->encoder->crtc)
3854                         continue;
3855
3856                 if (connector->encoder->crtc != crtc)
3857                         continue;
3858
3859                 connector->dpms = DRM_MODE_DPMS_OFF;
3860                 to_intel_encoder(connector->encoder)->connectors_active = false;
3861         }
3862 }
3863
3864 void intel_modeset_disable(struct drm_device *dev)
3865 {
3866         struct drm_crtc *crtc;
3867
3868         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3869                 if (crtc->enabled)
3870                         intel_crtc_disable(crtc);
3871         }
3872 }
3873
3874 void intel_encoder_destroy(struct drm_encoder *encoder)
3875 {
3876         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3877
3878         drm_encoder_cleanup(encoder);
3879         kfree(intel_encoder);
3880 }
3881
3882 /* Simple dpms helper for encodres with just one connector, no cloning and only
3883  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3884  * state of the entire output pipe. */
3885 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3886 {
3887         if (mode == DRM_MODE_DPMS_ON) {
3888                 encoder->connectors_active = true;
3889
3890                 intel_crtc_update_dpms(encoder->base.crtc);
3891         } else {
3892                 encoder->connectors_active = false;
3893
3894                 intel_crtc_update_dpms(encoder->base.crtc);
3895         }
3896 }
3897
3898 /* Cross check the actual hw state with our own modeset state tracking (and it's
3899  * internal consistency). */
3900 static void intel_connector_check_state(struct intel_connector *connector)
3901 {
3902         if (connector->get_hw_state(connector)) {
3903                 struct intel_encoder *encoder = connector->encoder;
3904                 struct drm_crtc *crtc;
3905                 bool encoder_enabled;
3906                 enum pipe pipe;
3907
3908                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3909                               connector->base.base.id,
3910                               drm_get_connector_name(&connector->base));
3911
3912                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3913                      "wrong connector dpms state\n");
3914                 WARN(connector->base.encoder != &encoder->base,
3915                      "active connector not linked to encoder\n");
3916                 WARN(!encoder->connectors_active,
3917                      "encoder->connectors_active not set\n");
3918
3919                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3920                 WARN(!encoder_enabled, "encoder not enabled\n");
3921                 if (WARN_ON(!encoder->base.crtc))
3922                         return;
3923
3924                 crtc = encoder->base.crtc;
3925
3926                 WARN(!crtc->enabled, "crtc not enabled\n");
3927                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3928                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3929                      "encoder active on the wrong pipe\n");
3930         }
3931 }
3932
3933 /* Even simpler default implementation, if there's really no special case to
3934  * consider. */
3935 void intel_connector_dpms(struct drm_connector *connector, int mode)
3936 {
3937         struct intel_encoder *encoder = intel_attached_encoder(connector);
3938
3939         /* All the simple cases only support two dpms states. */
3940         if (mode != DRM_MODE_DPMS_ON)
3941                 mode = DRM_MODE_DPMS_OFF;
3942
3943         if (mode == connector->dpms)
3944                 return;
3945
3946         connector->dpms = mode;
3947
3948         /* Only need to change hw state when actually enabled */
3949         if (encoder->base.crtc)
3950                 intel_encoder_dpms(encoder, mode);
3951         else
3952                 WARN_ON(encoder->connectors_active != false);
3953
3954         intel_modeset_check_state(connector->dev);
3955 }
3956
3957 /* Simple connector->get_hw_state implementation for encoders that support only
3958  * one connector and no cloning and hence the encoder state determines the state
3959  * of the connector. */
3960 bool intel_connector_get_hw_state(struct intel_connector *connector)
3961 {
3962         enum pipe pipe = 0;
3963         struct intel_encoder *encoder = connector->encoder;
3964
3965         return encoder->get_hw_state(encoder, &pipe);
3966 }
3967
3968 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3969                                       struct intel_crtc_config *pipe_config)
3970 {
3971         struct drm_device *dev = crtc->dev;
3972         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3973
3974         if (HAS_PCH_SPLIT(dev)) {
3975                 /* FDI link clock is fixed at 2.7G */
3976                 if (pipe_config->requested_mode.clock * 3
3977                     > IRONLAKE_FDI_FREQ * 4)
3978                         return false;
3979         }
3980
3981         /* All interlaced capable intel hw wants timings in frames. Note though
3982          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3983          * timings, so we need to be careful not to clobber these.*/
3984         if (!pipe_config->timings_set)
3985                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3986
3987         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3988          * with a hsync front porch of 0.
3989          */
3990         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3991                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3992                 return false;
3993
3994         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3995                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3996         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3997                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3998                  * for lvds. */
3999                 pipe_config->pipe_bpp = 8*3;
4000         }
4001
4002         return true;
4003 }
4004
4005 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4006 {
4007         return 400000; /* FIXME */
4008 }
4009
4010 static int i945_get_display_clock_speed(struct drm_device *dev)
4011 {
4012         return 400000;
4013 }
4014
4015 static int i915_get_display_clock_speed(struct drm_device *dev)
4016 {
4017         return 333000;
4018 }
4019
4020 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4021 {
4022         return 200000;
4023 }
4024
4025 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4026 {
4027         u16 gcfgc = 0;
4028
4029         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4030
4031         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4032                 return 133000;
4033         else {
4034                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4035                 case GC_DISPLAY_CLOCK_333_MHZ:
4036                         return 333000;
4037                 default:
4038                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4039                         return 190000;
4040                 }
4041         }
4042 }
4043
4044 static int i865_get_display_clock_speed(struct drm_device *dev)
4045 {
4046         return 266000;
4047 }
4048
4049 static int i855_get_display_clock_speed(struct drm_device *dev)
4050 {
4051         u16 hpllcc = 0;
4052         /* Assume that the hardware is in the high speed state.  This
4053          * should be the default.
4054          */
4055         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4056         case GC_CLOCK_133_200:
4057         case GC_CLOCK_100_200:
4058                 return 200000;
4059         case GC_CLOCK_166_250:
4060                 return 250000;
4061         case GC_CLOCK_100_133:
4062                 return 133000;
4063         }
4064
4065         /* Shouldn't happen */
4066         return 0;
4067 }
4068
4069 static int i830_get_display_clock_speed(struct drm_device *dev)
4070 {
4071         return 133000;
4072 }
4073
4074 static void
4075 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4076 {
4077         while (*num > 0xffffff || *den > 0xffffff) {
4078                 *num >>= 1;
4079                 *den >>= 1;
4080         }
4081 }
4082
4083 void
4084 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4085                        int pixel_clock, int link_clock,
4086                        struct intel_link_m_n *m_n)
4087 {
4088         m_n->tu = 64;
4089         m_n->gmch_m = bits_per_pixel * pixel_clock;
4090         m_n->gmch_n = link_clock * nlanes * 8;
4091         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4092         m_n->link_m = pixel_clock;
4093         m_n->link_n = link_clock;
4094         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4095 }
4096
4097 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4098 {
4099         if (i915_panel_use_ssc >= 0)
4100                 return i915_panel_use_ssc != 0;
4101         return dev_priv->lvds_use_ssc
4102                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4103 }
4104
4105 static int vlv_get_refclk(struct drm_crtc *crtc)
4106 {
4107         struct drm_device *dev = crtc->dev;
4108         struct drm_i915_private *dev_priv = dev->dev_private;
4109         int refclk = 27000; /* for DP & HDMI */
4110
4111         return 100000; /* only one validated so far */
4112
4113         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4114                 refclk = 96000;
4115         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4116                 if (intel_panel_use_ssc(dev_priv))
4117                         refclk = 100000;
4118                 else
4119                         refclk = 96000;
4120         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4121                 refclk = 100000;
4122         }
4123
4124         return refclk;
4125 }
4126
4127 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4128 {
4129         struct drm_device *dev = crtc->dev;
4130         struct drm_i915_private *dev_priv = dev->dev_private;
4131         int refclk;
4132
4133         if (IS_VALLEYVIEW(dev)) {
4134                 refclk = vlv_get_refclk(crtc);
4135         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4136             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4137                 refclk = dev_priv->lvds_ssc_freq * 1000;
4138                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4139                               refclk / 1000);
4140         } else if (!IS_GEN2(dev)) {
4141                 refclk = 96000;
4142         } else {
4143                 refclk = 48000;
4144         }
4145
4146         return refclk;
4147 }
4148
4149 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4150                                       intel_clock_t *clock)
4151 {
4152         /* SDVO TV has fixed PLL values depend on its clock range,
4153            this mirrors vbios setting. */
4154         if (adjusted_mode->clock >= 100000
4155             && adjusted_mode->clock < 140500) {
4156                 clock->p1 = 2;
4157                 clock->p2 = 10;
4158                 clock->n = 3;
4159                 clock->m1 = 16;
4160                 clock->m2 = 8;
4161         } else if (adjusted_mode->clock >= 140500
4162                    && adjusted_mode->clock <= 200000) {
4163                 clock->p1 = 1;
4164                 clock->p2 = 10;
4165                 clock->n = 6;
4166                 clock->m1 = 12;
4167                 clock->m2 = 8;
4168         }
4169 }
4170
4171 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4172                                      intel_clock_t *clock,
4173                                      intel_clock_t *reduced_clock)
4174 {
4175         struct drm_device *dev = crtc->dev;
4176         struct drm_i915_private *dev_priv = dev->dev_private;
4177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178         int pipe = intel_crtc->pipe;
4179         u32 fp, fp2 = 0;
4180
4181         if (IS_PINEVIEW(dev)) {
4182                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4183                 if (reduced_clock)
4184                         fp2 = (1 << reduced_clock->n) << 16 |
4185                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4186         } else {
4187                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4188                 if (reduced_clock)
4189                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4190                                 reduced_clock->m2;
4191         }
4192
4193         I915_WRITE(FP0(pipe), fp);
4194
4195         intel_crtc->lowfreq_avail = false;
4196         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4197             reduced_clock && i915_powersave) {
4198                 I915_WRITE(FP1(pipe), fp2);
4199                 intel_crtc->lowfreq_avail = true;
4200         } else {
4201                 I915_WRITE(FP1(pipe), fp);
4202         }
4203 }
4204
4205 static void vlv_update_pll(struct drm_crtc *crtc,
4206                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4207                            int num_connectors)
4208 {
4209         struct drm_device *dev = crtc->dev;
4210         struct drm_i915_private *dev_priv = dev->dev_private;
4211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4212         struct drm_display_mode *adjusted_mode =
4213                 &intel_crtc->config.adjusted_mode;
4214         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4215         int pipe = intel_crtc->pipe;
4216         u32 dpll, mdiv, pdiv;
4217         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4218         bool is_sdvo;
4219         u32 temp;
4220
4221         mutex_lock(&dev_priv->dpio_lock);
4222
4223         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4224                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4225
4226         dpll = DPLL_VGA_MODE_DIS;
4227         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4228         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4229         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4230
4231         I915_WRITE(DPLL(pipe), dpll);
4232         POSTING_READ(DPLL(pipe));
4233
4234         bestn = clock->n;
4235         bestm1 = clock->m1;
4236         bestm2 = clock->m2;
4237         bestp1 = clock->p1;
4238         bestp2 = clock->p2;
4239
4240         /*
4241          * In Valleyview PLL and program lane counter registers are exposed
4242          * through DPIO interface
4243          */
4244         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4245         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4246         mdiv |= ((bestn << DPIO_N_SHIFT));
4247         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4248         mdiv |= (1 << DPIO_K_SHIFT);
4249         mdiv |= DPIO_ENABLE_CALIBRATION;
4250         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4251
4252         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4253
4254         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4255                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4256                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4257                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4258         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4259
4260         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4261
4262         dpll |= DPLL_VCO_ENABLE;
4263         I915_WRITE(DPLL(pipe), dpll);
4264         POSTING_READ(DPLL(pipe));
4265         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4266                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4267
4268         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4269
4270         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4271                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4272
4273         I915_WRITE(DPLL(pipe), dpll);
4274
4275         /* Wait for the clocks to stabilize. */
4276         POSTING_READ(DPLL(pipe));
4277         udelay(150);
4278
4279         temp = 0;
4280         if (is_sdvo) {
4281                 temp = 0;
4282                 if (intel_crtc->config.pixel_multiplier > 1) {
4283                         temp = (intel_crtc->config.pixel_multiplier - 1)
4284                                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4285                 }
4286         }
4287         I915_WRITE(DPLL_MD(pipe), temp);
4288         POSTING_READ(DPLL_MD(pipe));
4289
4290         /* Now program lane control registers */
4291         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4292                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4293         {
4294                 temp = 0x1000C4;
4295                 if(pipe == 1)
4296                         temp |= (1 << 21);
4297                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4298         }
4299         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4300         {
4301                 temp = 0x1000C4;
4302                 if(pipe == 1)
4303                         temp |= (1 << 21);
4304                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4305         }
4306
4307         mutex_unlock(&dev_priv->dpio_lock);
4308 }
4309
4310 static void i9xx_update_pll(struct drm_crtc *crtc,
4311                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4312                             int num_connectors)
4313 {
4314         struct drm_device *dev = crtc->dev;
4315         struct drm_i915_private *dev_priv = dev->dev_private;
4316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4317         struct drm_display_mode *adjusted_mode =
4318                 &intel_crtc->config.adjusted_mode;
4319         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4320         struct intel_encoder *encoder;
4321         int pipe = intel_crtc->pipe;
4322         u32 dpll;
4323         bool is_sdvo;
4324
4325         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4326
4327         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4328                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4329
4330         dpll = DPLL_VGA_MODE_DIS;
4331
4332         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4333                 dpll |= DPLLB_MODE_LVDS;
4334         else
4335                 dpll |= DPLLB_MODE_DAC_SERIAL;
4336
4337         if (is_sdvo) {
4338                 if ((intel_crtc->config.pixel_multiplier > 1) &&
4339                     (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4340                         dpll |= (intel_crtc->config.pixel_multiplier - 1)
4341                                 << SDVO_MULTIPLIER_SHIFT_HIRES;
4342                 }
4343                 dpll |= DPLL_DVO_HIGH_SPEED;
4344         }
4345         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4346                 dpll |= DPLL_DVO_HIGH_SPEED;
4347
4348         /* compute bitmask from p1 value */
4349         if (IS_PINEVIEW(dev))
4350                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4351         else {
4352                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4353                 if (IS_G4X(dev) && reduced_clock)
4354                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4355         }
4356         switch (clock->p2) {
4357         case 5:
4358                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4359                 break;
4360         case 7:
4361                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4362                 break;
4363         case 10:
4364                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4365                 break;
4366         case 14:
4367                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4368                 break;
4369         }
4370         if (INTEL_INFO(dev)->gen >= 4)
4371                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4372
4373         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4374                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4375         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4376                 /* XXX: just matching BIOS for now */
4377                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4378                 dpll |= 3;
4379         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4380                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4381                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4382         else
4383                 dpll |= PLL_REF_INPUT_DREFCLK;
4384
4385         dpll |= DPLL_VCO_ENABLE;
4386         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4387         POSTING_READ(DPLL(pipe));
4388         udelay(150);
4389
4390         for_each_encoder_on_crtc(dev, crtc, encoder)
4391                 if (encoder->pre_pll_enable)
4392                         encoder->pre_pll_enable(encoder);
4393
4394         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4395                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4396
4397         I915_WRITE(DPLL(pipe), dpll);
4398
4399         /* Wait for the clocks to stabilize. */
4400         POSTING_READ(DPLL(pipe));
4401         udelay(150);
4402
4403         if (INTEL_INFO(dev)->gen >= 4) {
4404                 u32 temp = 0;
4405                 if (is_sdvo) {
4406                         temp = 0;
4407                         if (intel_crtc->config.pixel_multiplier > 1) {
4408                                 temp = (intel_crtc->config.pixel_multiplier - 1)
4409                                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4410                         }
4411                 }
4412                 I915_WRITE(DPLL_MD(pipe), temp);
4413         } else {
4414                 /* The pixel multiplier can only be updated once the
4415                  * DPLL is enabled and the clocks are stable.
4416                  *
4417                  * So write it again.
4418                  */
4419                 I915_WRITE(DPLL(pipe), dpll);
4420         }
4421 }
4422
4423 static void i8xx_update_pll(struct drm_crtc *crtc,
4424                             struct drm_display_mode *adjusted_mode,
4425                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4426                             int num_connectors)
4427 {
4428         struct drm_device *dev = crtc->dev;
4429         struct drm_i915_private *dev_priv = dev->dev_private;
4430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4431         struct intel_encoder *encoder;
4432         int pipe = intel_crtc->pipe;
4433         u32 dpll;
4434
4435         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4436
4437         dpll = DPLL_VGA_MODE_DIS;
4438
4439         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4440                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4441         } else {
4442                 if (clock->p1 == 2)
4443                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4444                 else
4445                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4446                 if (clock->p2 == 4)
4447                         dpll |= PLL_P2_DIVIDE_BY_4;
4448         }
4449
4450         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4451                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4452                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4453         else
4454                 dpll |= PLL_REF_INPUT_DREFCLK;
4455
4456         dpll |= DPLL_VCO_ENABLE;
4457         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4458         POSTING_READ(DPLL(pipe));
4459         udelay(150);
4460
4461         for_each_encoder_on_crtc(dev, crtc, encoder)
4462                 if (encoder->pre_pll_enable)
4463                         encoder->pre_pll_enable(encoder);
4464
4465         I915_WRITE(DPLL(pipe), dpll);
4466
4467         /* Wait for the clocks to stabilize. */
4468         POSTING_READ(DPLL(pipe));
4469         udelay(150);
4470
4471         /* The pixel multiplier can only be updated once the
4472          * DPLL is enabled and the clocks are stable.
4473          *
4474          * So write it again.
4475          */
4476         I915_WRITE(DPLL(pipe), dpll);
4477 }
4478
4479 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4480                                    struct drm_display_mode *mode,
4481                                    struct drm_display_mode *adjusted_mode)
4482 {
4483         struct drm_device *dev = intel_crtc->base.dev;
4484         struct drm_i915_private *dev_priv = dev->dev_private;
4485         enum pipe pipe = intel_crtc->pipe;
4486         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4487         uint32_t vsyncshift;
4488
4489         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4490                 /* the chip adds 2 halflines automatically */
4491                 adjusted_mode->crtc_vtotal -= 1;
4492                 adjusted_mode->crtc_vblank_end -= 1;
4493                 vsyncshift = adjusted_mode->crtc_hsync_start
4494                              - adjusted_mode->crtc_htotal / 2;
4495         } else {
4496                 vsyncshift = 0;
4497         }
4498
4499         if (INTEL_INFO(dev)->gen > 3)
4500                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4501
4502         I915_WRITE(HTOTAL(cpu_transcoder),
4503                    (adjusted_mode->crtc_hdisplay - 1) |
4504                    ((adjusted_mode->crtc_htotal - 1) << 16));
4505         I915_WRITE(HBLANK(cpu_transcoder),
4506                    (adjusted_mode->crtc_hblank_start - 1) |
4507                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4508         I915_WRITE(HSYNC(cpu_transcoder),
4509                    (adjusted_mode->crtc_hsync_start - 1) |
4510                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4511
4512         I915_WRITE(VTOTAL(cpu_transcoder),
4513                    (adjusted_mode->crtc_vdisplay - 1) |
4514                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4515         I915_WRITE(VBLANK(cpu_transcoder),
4516                    (adjusted_mode->crtc_vblank_start - 1) |
4517                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4518         I915_WRITE(VSYNC(cpu_transcoder),
4519                    (adjusted_mode->crtc_vsync_start - 1) |
4520                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4521
4522         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4523          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4524          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4525          * bits. */
4526         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4527             (pipe == PIPE_B || pipe == PIPE_C))
4528                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4529
4530         /* pipesrc controls the size that is scaled from, which should
4531          * always be the user's requested size.
4532          */
4533         I915_WRITE(PIPESRC(pipe),
4534                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4535 }
4536
4537 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4538                               int x, int y,
4539                               struct drm_framebuffer *fb)
4540 {
4541         struct drm_device *dev = crtc->dev;
4542         struct drm_i915_private *dev_priv = dev->dev_private;
4543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4544         struct drm_display_mode *adjusted_mode =
4545                 &intel_crtc->config.adjusted_mode;
4546         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4547         int pipe = intel_crtc->pipe;
4548         int plane = intel_crtc->plane;
4549         int refclk, num_connectors = 0;
4550         intel_clock_t clock, reduced_clock;
4551         u32 dspcntr, pipeconf;
4552         bool ok, has_reduced_clock = false, is_sdvo = false;
4553         bool is_lvds = false, is_tv = false, is_dp = false;
4554         struct intel_encoder *encoder;
4555         const intel_limit_t *limit;
4556         int ret;
4557
4558         for_each_encoder_on_crtc(dev, crtc, encoder) {
4559                 switch (encoder->type) {
4560                 case INTEL_OUTPUT_LVDS:
4561                         is_lvds = true;
4562                         break;
4563                 case INTEL_OUTPUT_SDVO:
4564                 case INTEL_OUTPUT_HDMI:
4565                         is_sdvo = true;
4566                         if (encoder->needs_tv_clock)
4567                                 is_tv = true;
4568                         break;
4569                 case INTEL_OUTPUT_TVOUT:
4570                         is_tv = true;
4571                         break;
4572                 case INTEL_OUTPUT_DISPLAYPORT:
4573                         is_dp = true;
4574                         break;
4575                 }
4576
4577                 num_connectors++;
4578         }
4579
4580         refclk = i9xx_get_refclk(crtc, num_connectors);
4581
4582         /*
4583          * Returns a set of divisors for the desired target clock with the given
4584          * refclk, or FALSE.  The returned values represent the clock equation:
4585          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4586          */
4587         limit = intel_limit(crtc, refclk);
4588         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4589                              &clock);
4590         if (!ok) {
4591                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4592                 return -EINVAL;
4593         }
4594
4595         /* Ensure that the cursor is valid for the new mode before changing... */
4596         intel_crtc_update_cursor(crtc, true);
4597
4598         if (is_lvds && dev_priv->lvds_downclock_avail) {
4599                 /*
4600                  * Ensure we match the reduced clock's P to the target clock.
4601                  * If the clocks don't match, we can't switch the display clock
4602                  * by using the FP0/FP1. In such case we will disable the LVDS
4603                  * downclock feature.
4604                 */
4605                 has_reduced_clock = limit->find_pll(limit, crtc,
4606                                                     dev_priv->lvds_downclock,
4607                                                     refclk,
4608                                                     &clock,
4609                                                     &reduced_clock);
4610         }
4611
4612         if (is_sdvo && is_tv)
4613                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4614
4615         if (IS_GEN2(dev))
4616                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4617                                 has_reduced_clock ? &reduced_clock : NULL,
4618                                 num_connectors);
4619         else if (IS_VALLEYVIEW(dev))
4620                 vlv_update_pll(crtc, &clock,
4621                                 has_reduced_clock ? &reduced_clock : NULL,
4622                                 num_connectors);
4623         else
4624                 i9xx_update_pll(crtc, &clock,
4625                                 has_reduced_clock ? &reduced_clock : NULL,
4626                                 num_connectors);
4627
4628         /* setup pipeconf */
4629         pipeconf = I915_READ(PIPECONF(pipe));
4630
4631         /* Set up the display plane register */
4632         dspcntr = DISPPLANE_GAMMA_ENABLE;
4633
4634         if (!IS_VALLEYVIEW(dev)) {
4635                 if (pipe == 0)
4636                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4637                 else
4638                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4639         }
4640
4641         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4642                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4643                  * core speed.
4644                  *
4645                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4646                  * pipe == 0 check?
4647                  */
4648                 if (mode->clock >
4649                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4650                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4651                 else
4652                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4653         }
4654
4655         /* default to 8bpc */
4656         pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4657         if (is_dp) {
4658                 if (intel_crtc->config.dither) {
4659                         pipeconf |= PIPECONF_6BPC |
4660                                     PIPECONF_DITHER_EN |
4661                                     PIPECONF_DITHER_TYPE_SP;
4662                 }
4663         }
4664
4665         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4666                 if (intel_crtc->config.dither) {
4667                         pipeconf |= PIPECONF_6BPC |
4668                                         PIPECONF_ENABLE |
4669                                         I965_PIPECONF_ACTIVE;
4670                 }
4671         }
4672
4673         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4674         drm_mode_debug_printmodeline(mode);
4675
4676         if (HAS_PIPE_CXSR(dev)) {
4677                 if (intel_crtc->lowfreq_avail) {
4678                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4679                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4680                 } else {
4681                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4682                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4683                 }
4684         }
4685
4686         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4687         if (!IS_GEN2(dev) &&
4688             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4689                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4690         else
4691                 pipeconf |= PIPECONF_PROGRESSIVE;
4692
4693         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4694
4695         /* pipesrc and dspsize control the size that is scaled from,
4696          * which should always be the user's requested size.
4697          */
4698         I915_WRITE(DSPSIZE(plane),
4699                    ((mode->vdisplay - 1) << 16) |
4700                    (mode->hdisplay - 1));
4701         I915_WRITE(DSPPOS(plane), 0);
4702
4703         I915_WRITE(PIPECONF(pipe), pipeconf);
4704         POSTING_READ(PIPECONF(pipe));
4705         intel_enable_pipe(dev_priv, pipe, false);
4706
4707         intel_wait_for_vblank(dev, pipe);
4708
4709         I915_WRITE(DSPCNTR(plane), dspcntr);
4710         POSTING_READ(DSPCNTR(plane));
4711
4712         ret = intel_pipe_set_base(crtc, x, y, fb);
4713
4714         intel_update_watermarks(dev);
4715
4716         return ret;
4717 }
4718
4719 static void ironlake_init_pch_refclk(struct drm_device *dev)
4720 {
4721         struct drm_i915_private *dev_priv = dev->dev_private;
4722         struct drm_mode_config *mode_config = &dev->mode_config;
4723         struct intel_encoder *encoder;
4724         u32 val, final;
4725         bool has_lvds = false;
4726         bool has_cpu_edp = false;
4727         bool has_pch_edp = false;
4728         bool has_panel = false;
4729         bool has_ck505 = false;
4730         bool can_ssc = false;
4731
4732         /* We need to take the global config into account */
4733         list_for_each_entry(encoder, &mode_config->encoder_list,
4734                             base.head) {
4735                 switch (encoder->type) {
4736                 case INTEL_OUTPUT_LVDS:
4737                         has_panel = true;
4738                         has_lvds = true;
4739                         break;
4740                 case INTEL_OUTPUT_EDP:
4741                         has_panel = true;
4742                         if (intel_encoder_is_pch_edp(&encoder->base))
4743                                 has_pch_edp = true;
4744                         else
4745                                 has_cpu_edp = true;
4746                         break;
4747                 }
4748         }
4749
4750         if (HAS_PCH_IBX(dev)) {
4751                 has_ck505 = dev_priv->display_clock_mode;
4752                 can_ssc = has_ck505;
4753         } else {
4754                 has_ck505 = false;
4755                 can_ssc = true;
4756         }
4757
4758         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4759                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4760                       has_ck505);
4761
4762         /* Ironlake: try to setup display ref clock before DPLL
4763          * enabling. This is only under driver's control after
4764          * PCH B stepping, previous chipset stepping should be
4765          * ignoring this setting.
4766          */
4767         val = I915_READ(PCH_DREF_CONTROL);
4768
4769         /* As we must carefully and slowly disable/enable each source in turn,
4770          * compute the final state we want first and check if we need to
4771          * make any changes at all.
4772          */
4773         final = val;
4774         final &= ~DREF_NONSPREAD_SOURCE_MASK;
4775         if (has_ck505)
4776                 final |= DREF_NONSPREAD_CK505_ENABLE;
4777         else
4778                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4779
4780         final &= ~DREF_SSC_SOURCE_MASK;
4781         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4782         final &= ~DREF_SSC1_ENABLE;
4783
4784         if (has_panel) {
4785                 final |= DREF_SSC_SOURCE_ENABLE;
4786
4787                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4788                         final |= DREF_SSC1_ENABLE;
4789
4790                 if (has_cpu_edp) {
4791                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
4792                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4793                         else
4794                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4795                 } else
4796                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4797         } else {
4798                 final |= DREF_SSC_SOURCE_DISABLE;
4799                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4800         }
4801
4802         if (final == val)
4803                 return;
4804
4805         /* Always enable nonspread source */
4806         val &= ~DREF_NONSPREAD_SOURCE_MASK;
4807
4808         if (has_ck505)
4809                 val |= DREF_NONSPREAD_CK505_ENABLE;
4810         else
4811                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4812
4813         if (has_panel) {
4814                 val &= ~DREF_SSC_SOURCE_MASK;
4815                 val |= DREF_SSC_SOURCE_ENABLE;
4816
4817                 /* SSC must be turned on before enabling the CPU output  */
4818                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4819                         DRM_DEBUG_KMS("Using SSC on panel\n");
4820                         val |= DREF_SSC1_ENABLE;
4821                 } else
4822                         val &= ~DREF_SSC1_ENABLE;
4823
4824                 /* Get SSC going before enabling the outputs */
4825                 I915_WRITE(PCH_DREF_CONTROL, val);
4826                 POSTING_READ(PCH_DREF_CONTROL);
4827                 udelay(200);
4828
4829                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4830
4831                 /* Enable CPU source on CPU attached eDP */
4832                 if (has_cpu_edp) {
4833                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4834                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4835                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4836                         }
4837                         else
4838                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4839                 } else
4840                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4841
4842                 I915_WRITE(PCH_DREF_CONTROL, val);
4843                 POSTING_READ(PCH_DREF_CONTROL);
4844                 udelay(200);
4845         } else {
4846                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4847
4848                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4849
4850                 /* Turn off CPU output */
4851                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4852
4853                 I915_WRITE(PCH_DREF_CONTROL, val);
4854                 POSTING_READ(PCH_DREF_CONTROL);
4855                 udelay(200);
4856
4857                 /* Turn off the SSC source */
4858                 val &= ~DREF_SSC_SOURCE_MASK;
4859                 val |= DREF_SSC_SOURCE_DISABLE;
4860
4861                 /* Turn off SSC1 */
4862                 val &= ~DREF_SSC1_ENABLE;
4863
4864                 I915_WRITE(PCH_DREF_CONTROL, val);
4865                 POSTING_READ(PCH_DREF_CONTROL);
4866                 udelay(200);
4867         }
4868
4869         BUG_ON(val != final);
4870 }
4871
4872 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4873 static void lpt_init_pch_refclk(struct drm_device *dev)
4874 {
4875         struct drm_i915_private *dev_priv = dev->dev_private;
4876         struct drm_mode_config *mode_config = &dev->mode_config;
4877         struct intel_encoder *encoder;
4878         bool has_vga = false;
4879         bool is_sdv = false;
4880         u32 tmp;
4881
4882         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4883                 switch (encoder->type) {
4884                 case INTEL_OUTPUT_ANALOG:
4885                         has_vga = true;
4886                         break;
4887                 }
4888         }
4889
4890         if (!has_vga)
4891                 return;
4892
4893         mutex_lock(&dev_priv->dpio_lock);
4894
4895         /* XXX: Rip out SDV support once Haswell ships for real. */
4896         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4897                 is_sdv = true;
4898
4899         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4900         tmp &= ~SBI_SSCCTL_DISABLE;
4901         tmp |= SBI_SSCCTL_PATHALT;
4902         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4903
4904         udelay(24);
4905
4906         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4907         tmp &= ~SBI_SSCCTL_PATHALT;
4908         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4909
4910         if (!is_sdv) {
4911                 tmp = I915_READ(SOUTH_CHICKEN2);
4912                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4913                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4914
4915                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4916                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4917                         DRM_ERROR("FDI mPHY reset assert timeout\n");
4918
4919                 tmp = I915_READ(SOUTH_CHICKEN2);
4920                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4921                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4922
4923                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4924                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4925                                        100))
4926                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4927         }
4928
4929         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4930         tmp &= ~(0xFF << 24);
4931         tmp |= (0x12 << 24);
4932         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4933
4934         if (!is_sdv) {
4935                 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4936                 tmp &= ~(0x3 << 6);
4937                 tmp |= (1 << 6) | (1 << 0);
4938                 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4939         }
4940
4941         if (is_sdv) {
4942                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4943                 tmp |= 0x7FFF;
4944                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4945         }
4946
4947         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4948         tmp |= (1 << 11);
4949         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4950
4951         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4952         tmp |= (1 << 11);
4953         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4954
4955         if (is_sdv) {
4956                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4957                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4958                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4959
4960                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4961                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4962                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4963
4964                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4965                 tmp |= (0x3F << 8);
4966                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4967
4968                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4969                 tmp |= (0x3F << 8);
4970                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4971         }
4972
4973         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4974         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4975         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4976
4977         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4978         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4979         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4980
4981         if (!is_sdv) {
4982                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4983                 tmp &= ~(7 << 13);
4984                 tmp |= (5 << 13);
4985                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4986
4987                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4988                 tmp &= ~(7 << 13);
4989                 tmp |= (5 << 13);
4990                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4991         }
4992
4993         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4994         tmp &= ~0xFF;
4995         tmp |= 0x1C;
4996         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4997
4998         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4999         tmp &= ~0xFF;
5000         tmp |= 0x1C;
5001         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5002
5003         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5004         tmp &= ~(0xFF << 16);
5005         tmp |= (0x1C << 16);
5006         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5007
5008         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5009         tmp &= ~(0xFF << 16);
5010         tmp |= (0x1C << 16);
5011         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5012
5013         if (!is_sdv) {
5014                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5015                 tmp |= (1 << 27);
5016                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5017
5018                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5019                 tmp |= (1 << 27);
5020                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5021
5022                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5023                 tmp &= ~(0xF << 28);
5024                 tmp |= (4 << 28);
5025                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5026
5027                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5028                 tmp &= ~(0xF << 28);
5029                 tmp |= (4 << 28);
5030                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5031         }
5032
5033         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5034         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5035         tmp |= SBI_DBUFF0_ENABLE;
5036         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5037
5038         mutex_unlock(&dev_priv->dpio_lock);
5039 }
5040
5041 /*
5042  * Initialize reference clocks when the driver loads
5043  */
5044 void intel_init_pch_refclk(struct drm_device *dev)
5045 {
5046         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5047                 ironlake_init_pch_refclk(dev);
5048         else if (HAS_PCH_LPT(dev))
5049                 lpt_init_pch_refclk(dev);
5050 }
5051
5052 static int ironlake_get_refclk(struct drm_crtc *crtc)
5053 {
5054         struct drm_device *dev = crtc->dev;
5055         struct drm_i915_private *dev_priv = dev->dev_private;
5056         struct intel_encoder *encoder;
5057         struct intel_encoder *edp_encoder = NULL;
5058         int num_connectors = 0;
5059         bool is_lvds = false;
5060
5061         for_each_encoder_on_crtc(dev, crtc, encoder) {
5062                 switch (encoder->type) {
5063                 case INTEL_OUTPUT_LVDS:
5064                         is_lvds = true;
5065                         break;
5066                 case INTEL_OUTPUT_EDP:
5067                         edp_encoder = encoder;
5068                         break;
5069                 }
5070                 num_connectors++;
5071         }
5072
5073         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5074                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5075                               dev_priv->lvds_ssc_freq);
5076                 return dev_priv->lvds_ssc_freq * 1000;
5077         }
5078
5079         return 120000;
5080 }
5081
5082 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5083                                   struct drm_display_mode *adjusted_mode,
5084                                   bool dither)
5085 {
5086         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5088         int pipe = intel_crtc->pipe;
5089         uint32_t val;
5090
5091         val = I915_READ(PIPECONF(pipe));
5092
5093         val &= ~PIPECONF_BPC_MASK;
5094         switch (intel_crtc->config.pipe_bpp) {
5095         case 18:
5096                 val |= PIPECONF_6BPC;
5097                 break;
5098         case 24:
5099                 val |= PIPECONF_8BPC;
5100                 break;
5101         case 30:
5102                 val |= PIPECONF_10BPC;
5103                 break;
5104         case 36:
5105                 val |= PIPECONF_12BPC;
5106                 break;
5107         default:
5108                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5109                 BUG();
5110         }
5111
5112         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5113         if (dither)
5114                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5115
5116         val &= ~PIPECONF_INTERLACE_MASK;
5117         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5118                 val |= PIPECONF_INTERLACED_ILK;
5119         else
5120                 val |= PIPECONF_PROGRESSIVE;
5121
5122         if (intel_crtc->config.limited_color_range)
5123                 val |= PIPECONF_COLOR_RANGE_SELECT;
5124         else
5125                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5126
5127         I915_WRITE(PIPECONF(pipe), val);
5128         POSTING_READ(PIPECONF(pipe));
5129 }
5130
5131 /*
5132  * Set up the pipe CSC unit.
5133  *
5134  * Currently only full range RGB to limited range RGB conversion
5135  * is supported, but eventually this should handle various
5136  * RGB<->YCbCr scenarios as well.
5137  */
5138 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5139 {
5140         struct drm_device *dev = crtc->dev;
5141         struct drm_i915_private *dev_priv = dev->dev_private;
5142         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5143         int pipe = intel_crtc->pipe;
5144         uint16_t coeff = 0x7800; /* 1.0 */
5145
5146         /*
5147          * TODO: Check what kind of values actually come out of the pipe
5148          * with these coeff/postoff values and adjust to get the best
5149          * accuracy. Perhaps we even need to take the bpc value into
5150          * consideration.
5151          */
5152
5153         if (intel_crtc->config.limited_color_range)
5154                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5155
5156         /*
5157          * GY/GU and RY/RU should be the other way around according
5158          * to BSpec, but reality doesn't agree. Just set them up in
5159          * a way that results in the correct picture.
5160          */
5161         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5162         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5163
5164         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5165         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5166
5167         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5168         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5169
5170         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5171         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5172         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5173
5174         if (INTEL_INFO(dev)->gen > 6) {
5175                 uint16_t postoff = 0;
5176
5177                 if (intel_crtc->config.limited_color_range)
5178                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5179
5180                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5181                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5182                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5183
5184                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5185         } else {
5186                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5187
5188                 if (intel_crtc->config.limited_color_range)
5189                         mode |= CSC_BLACK_SCREEN_OFFSET;
5190
5191                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5192         }
5193 }
5194
5195 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5196                                  struct drm_display_mode *adjusted_mode,
5197                                  bool dither)
5198 {
5199         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5201         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5202         uint32_t val;
5203
5204         val = I915_READ(PIPECONF(cpu_transcoder));
5205
5206         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5207         if (dither)
5208                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5209
5210         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5211         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5212                 val |= PIPECONF_INTERLACED_ILK;
5213         else
5214                 val |= PIPECONF_PROGRESSIVE;
5215
5216         I915_WRITE(PIPECONF(cpu_transcoder), val);
5217         POSTING_READ(PIPECONF(cpu_transcoder));
5218 }
5219
5220 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5221                                     struct drm_display_mode *adjusted_mode,
5222                                     intel_clock_t *clock,
5223                                     bool *has_reduced_clock,
5224                                     intel_clock_t *reduced_clock)
5225 {
5226         struct drm_device *dev = crtc->dev;
5227         struct drm_i915_private *dev_priv = dev->dev_private;
5228         struct intel_encoder *intel_encoder;
5229         int refclk;
5230         const intel_limit_t *limit;
5231         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5232
5233         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5234                 switch (intel_encoder->type) {
5235                 case INTEL_OUTPUT_LVDS:
5236                         is_lvds = true;
5237                         break;
5238                 case INTEL_OUTPUT_SDVO:
5239                 case INTEL_OUTPUT_HDMI:
5240                         is_sdvo = true;
5241                         if (intel_encoder->needs_tv_clock)
5242                                 is_tv = true;
5243                         break;
5244                 case INTEL_OUTPUT_TVOUT:
5245                         is_tv = true;
5246                         break;
5247                 }
5248         }
5249
5250         refclk = ironlake_get_refclk(crtc);
5251
5252         /*
5253          * Returns a set of divisors for the desired target clock with the given
5254          * refclk, or FALSE.  The returned values represent the clock equation:
5255          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5256          */
5257         limit = intel_limit(crtc, refclk);
5258         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5259                               clock);
5260         if (!ret)
5261                 return false;
5262
5263         if (is_lvds && dev_priv->lvds_downclock_avail) {
5264                 /*
5265                  * Ensure we match the reduced clock's P to the target clock.
5266                  * If the clocks don't match, we can't switch the display clock
5267                  * by using the FP0/FP1. In such case we will disable the LVDS
5268                  * downclock feature.
5269                 */
5270                 *has_reduced_clock = limit->find_pll(limit, crtc,
5271                                                      dev_priv->lvds_downclock,
5272                                                      refclk,
5273                                                      clock,
5274                                                      reduced_clock);
5275         }
5276
5277         if (is_sdvo && is_tv)
5278                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5279
5280         return true;
5281 }
5282
5283 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5284 {
5285         struct drm_i915_private *dev_priv = dev->dev_private;
5286         uint32_t temp;
5287
5288         temp = I915_READ(SOUTH_CHICKEN1);
5289         if (temp & FDI_BC_BIFURCATION_SELECT)
5290                 return;
5291
5292         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5293         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5294
5295         temp |= FDI_BC_BIFURCATION_SELECT;
5296         DRM_DEBUG_KMS("enabling fdi C rx\n");
5297         I915_WRITE(SOUTH_CHICKEN1, temp);
5298         POSTING_READ(SOUTH_CHICKEN1);
5299 }
5300
5301 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5302 {
5303         struct drm_device *dev = intel_crtc->base.dev;
5304         struct drm_i915_private *dev_priv = dev->dev_private;
5305         struct intel_crtc *pipe_B_crtc =
5306                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5307
5308         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5309                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5310         if (intel_crtc->fdi_lanes > 4) {
5311                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5312                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5313                 /* Clamp lanes to avoid programming the hw with bogus values. */
5314                 intel_crtc->fdi_lanes = 4;
5315
5316                 return false;
5317         }
5318
5319         if (INTEL_INFO(dev)->num_pipes == 2)
5320                 return true;
5321
5322         switch (intel_crtc->pipe) {
5323         case PIPE_A:
5324                 return true;
5325         case PIPE_B:
5326                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5327                     intel_crtc->fdi_lanes > 2) {
5328                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5329                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5330                         /* Clamp lanes to avoid programming the hw with bogus values. */
5331                         intel_crtc->fdi_lanes = 2;
5332
5333                         return false;
5334                 }
5335
5336                 if (intel_crtc->fdi_lanes > 2)
5337                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5338                 else
5339                         cpt_enable_fdi_bc_bifurcation(dev);
5340
5341                 return true;
5342         case PIPE_C:
5343                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5344                         if (intel_crtc->fdi_lanes > 2) {
5345                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5346                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5347                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5348                                 intel_crtc->fdi_lanes = 2;
5349
5350                                 return false;
5351                         }
5352                 } else {
5353                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5354                         return false;
5355                 }
5356
5357                 cpt_enable_fdi_bc_bifurcation(dev);
5358
5359                 return true;
5360         default:
5361                 BUG();
5362         }
5363 }
5364
5365 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5366 {
5367         /*
5368          * Account for spread spectrum to avoid
5369          * oversubscribing the link. Max center spread
5370          * is 2.5%; use 5% for safety's sake.
5371          */
5372         u32 bps = target_clock * bpp * 21 / 20;
5373         return bps / (link_bw * 8) + 1;
5374 }
5375
5376 void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5377                                   struct intel_link_m_n *m_n)
5378 {
5379         struct drm_device *dev = crtc->base.dev;
5380         struct drm_i915_private *dev_priv = dev->dev_private;
5381         int pipe = crtc->pipe;
5382
5383         I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5384         I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5385         I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5386         I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5387 }
5388
5389 void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5390                                   struct intel_link_m_n *m_n)
5391 {
5392         struct drm_device *dev = crtc->base.dev;
5393         struct drm_i915_private *dev_priv = dev->dev_private;
5394         int pipe = crtc->pipe;
5395         enum transcoder transcoder = crtc->cpu_transcoder;
5396
5397         if (INTEL_INFO(dev)->gen >= 5) {
5398                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5399                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5400                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5401                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5402         } else {
5403                 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5404                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5405                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5406                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5407         }
5408 }
5409
5410 static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5411 {
5412         struct drm_device *dev = crtc->dev;
5413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5414         struct drm_display_mode *adjusted_mode =
5415                 &intel_crtc->config.adjusted_mode;
5416         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5417         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5418         struct intel_link_m_n m_n = {0};
5419         int target_clock, lane, link_bw;
5420         bool is_dp = false, is_cpu_edp = false;
5421
5422         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5423                 switch (intel_encoder->type) {
5424                 case INTEL_OUTPUT_DISPLAYPORT:
5425                         is_dp = true;
5426                         break;
5427                 case INTEL_OUTPUT_EDP:
5428                         is_dp = true;
5429                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5430                                 is_cpu_edp = true;
5431                         edp_encoder = intel_encoder;
5432                         break;
5433                 }
5434         }
5435
5436         /* FDI is a binary signal running at ~2.7GHz, encoding
5437          * each output octet as 10 bits. The actual frequency
5438          * is stored as a divider into a 100MHz clock, and the
5439          * mode pixel clock is stored in units of 1KHz.
5440          * Hence the bw of each lane in terms of the mode signal
5441          * is:
5442          */
5443         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5444
5445         /* [e]DP over FDI requires target mode clock instead of link clock. */
5446         if (edp_encoder)
5447                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5448         else if (is_dp)
5449                 target_clock = mode->clock;
5450         else
5451                 target_clock = adjusted_mode->clock;
5452
5453         lane = ironlake_get_lanes_required(target_clock, link_bw,
5454                                            intel_crtc->config.pipe_bpp);
5455
5456         intel_crtc->fdi_lanes = lane;
5457
5458         if (intel_crtc->config.pixel_multiplier > 1)
5459                 link_bw *= intel_crtc->config.pixel_multiplier;
5460         intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5461                                link_bw, &m_n);
5462
5463         intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
5464 }
5465
5466 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5467                                       intel_clock_t *clock, u32 fp)
5468 {
5469         struct drm_crtc *crtc = &intel_crtc->base;
5470         struct drm_device *dev = crtc->dev;
5471         struct drm_i915_private *dev_priv = dev->dev_private;
5472         struct intel_encoder *intel_encoder;
5473         uint32_t dpll;
5474         int factor, num_connectors = 0;
5475         bool is_lvds = false, is_sdvo = false, is_tv = false;
5476         bool is_dp = false, is_cpu_edp = false;
5477
5478         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5479                 switch (intel_encoder->type) {
5480                 case INTEL_OUTPUT_LVDS:
5481                         is_lvds = true;
5482                         break;
5483                 case INTEL_OUTPUT_SDVO:
5484                 case INTEL_OUTPUT_HDMI:
5485                         is_sdvo = true;
5486                         if (intel_encoder->needs_tv_clock)
5487                                 is_tv = true;
5488                         break;
5489                 case INTEL_OUTPUT_TVOUT:
5490                         is_tv = true;
5491                         break;
5492                 case INTEL_OUTPUT_DISPLAYPORT:
5493                         is_dp = true;
5494                         break;
5495                 case INTEL_OUTPUT_EDP:
5496                         is_dp = true;
5497                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5498                                 is_cpu_edp = true;
5499                         break;
5500                 }
5501
5502                 num_connectors++;
5503         }
5504
5505         /* Enable autotuning of the PLL clock (if permissible) */
5506         factor = 21;
5507         if (is_lvds) {
5508                 if ((intel_panel_use_ssc(dev_priv) &&
5509                      dev_priv->lvds_ssc_freq == 100) ||
5510                     intel_is_dual_link_lvds(dev))
5511                         factor = 25;
5512         } else if (is_sdvo && is_tv)
5513                 factor = 20;
5514
5515         if (clock->m < factor * clock->n)
5516                 fp |= FP_CB_TUNE;
5517
5518         dpll = 0;
5519
5520         if (is_lvds)
5521                 dpll |= DPLLB_MODE_LVDS;
5522         else
5523                 dpll |= DPLLB_MODE_DAC_SERIAL;
5524         if (is_sdvo) {
5525                 if (intel_crtc->config.pixel_multiplier > 1) {
5526                         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5527                                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5528                 }
5529                 dpll |= DPLL_DVO_HIGH_SPEED;
5530         }
5531         if (is_dp && !is_cpu_edp)
5532                 dpll |= DPLL_DVO_HIGH_SPEED;
5533
5534         /* compute bitmask from p1 value */
5535         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5536         /* also FPA1 */
5537         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5538
5539         switch (clock->p2) {
5540         case 5:
5541                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5542                 break;
5543         case 7:
5544                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5545                 break;
5546         case 10:
5547                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5548                 break;
5549         case 14:
5550                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5551                 break;
5552         }
5553
5554         if (is_sdvo && is_tv)
5555                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5556         else if (is_tv)
5557                 /* XXX: just matching BIOS for now */
5558                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5559                 dpll |= 3;
5560         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5561                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5562         else
5563                 dpll |= PLL_REF_INPUT_DREFCLK;
5564
5565         return dpll;
5566 }
5567
5568 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5569                                   int x, int y,
5570                                   struct drm_framebuffer *fb)
5571 {
5572         struct drm_device *dev = crtc->dev;
5573         struct drm_i915_private *dev_priv = dev->dev_private;
5574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5575         struct drm_display_mode *adjusted_mode =
5576                 &intel_crtc->config.adjusted_mode;
5577         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5578         int pipe = intel_crtc->pipe;
5579         int plane = intel_crtc->plane;
5580         int num_connectors = 0;
5581         intel_clock_t clock, reduced_clock;
5582         u32 dpll, fp = 0, fp2 = 0;
5583         bool ok, has_reduced_clock = false;
5584         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5585         struct intel_encoder *encoder;
5586         int ret;
5587         bool dither, fdi_config_ok;
5588
5589         for_each_encoder_on_crtc(dev, crtc, encoder) {
5590                 switch (encoder->type) {
5591                 case INTEL_OUTPUT_LVDS:
5592                         is_lvds = true;
5593                         break;
5594                 case INTEL_OUTPUT_DISPLAYPORT:
5595                         is_dp = true;
5596                         break;
5597                 case INTEL_OUTPUT_EDP:
5598                         is_dp = true;
5599                         if (!intel_encoder_is_pch_edp(&encoder->base))
5600                                 is_cpu_edp = true;
5601                         break;
5602                 }
5603
5604                 num_connectors++;
5605         }
5606
5607         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5608              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5609
5610         intel_crtc->cpu_transcoder = pipe;
5611
5612         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5613                                      &has_reduced_clock, &reduced_clock);
5614         if (!ok) {
5615                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5616                 return -EINVAL;
5617         }
5618
5619         /* Ensure that the cursor is valid for the new mode before changing... */
5620         intel_crtc_update_cursor(crtc, true);
5621
5622         /* determine panel color depth */
5623         dither = intel_crtc->config.dither;
5624         if (is_lvds && dev_priv->lvds_dither)
5625                 dither = true;
5626
5627         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5628         if (has_reduced_clock)
5629                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5630                         reduced_clock.m2;
5631
5632         dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
5633
5634         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5635         drm_mode_debug_printmodeline(mode);
5636
5637         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5638         if (!is_cpu_edp) {
5639                 struct intel_pch_pll *pll;
5640
5641                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5642                 if (pll == NULL) {
5643                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5644                                          pipe);
5645                         return -EINVAL;
5646                 }
5647         } else
5648                 intel_put_pch_pll(intel_crtc);
5649
5650         if (is_dp)
5651                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5652
5653         for_each_encoder_on_crtc(dev, crtc, encoder)
5654                 if (encoder->pre_pll_enable)
5655                         encoder->pre_pll_enable(encoder);
5656
5657         if (intel_crtc->pch_pll) {
5658                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5659
5660                 /* Wait for the clocks to stabilize. */
5661                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5662                 udelay(150);
5663
5664                 /* The pixel multiplier can only be updated once the
5665                  * DPLL is enabled and the clocks are stable.
5666                  *
5667                  * So write it again.
5668                  */
5669                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5670         }
5671
5672         intel_crtc->lowfreq_avail = false;
5673         if (intel_crtc->pch_pll) {
5674                 if (is_lvds && has_reduced_clock && i915_powersave) {
5675                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5676                         intel_crtc->lowfreq_avail = true;
5677                 } else {
5678                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5679                 }
5680         }
5681
5682         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5683
5684         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5685          * ironlake_check_fdi_lanes. */
5686         intel_crtc->fdi_lanes = 0;
5687         if (intel_crtc->config.has_pch_encoder)
5688                 ironlake_fdi_set_m_n(crtc);
5689
5690         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5691
5692         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5693
5694         intel_wait_for_vblank(dev, pipe);
5695
5696         /* Set up the display plane register */
5697         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5698         POSTING_READ(DSPCNTR(plane));
5699
5700         ret = intel_pipe_set_base(crtc, x, y, fb);
5701
5702         intel_update_watermarks(dev);
5703
5704         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5705
5706         return fdi_config_ok ? ret : -EINVAL;
5707 }
5708
5709 static void haswell_modeset_global_resources(struct drm_device *dev)
5710 {
5711         struct drm_i915_private *dev_priv = dev->dev_private;
5712         bool enable = false;
5713         struct intel_crtc *crtc;
5714         struct intel_encoder *encoder;
5715
5716         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5717                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5718                         enable = true;
5719                 /* XXX: Should check for edp transcoder here, but thanks to init
5720                  * sequence that's not yet available. Just in case desktop eDP
5721                  * on PORT D is possible on haswell, too. */
5722         }
5723
5724         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5725                             base.head) {
5726                 if (encoder->type != INTEL_OUTPUT_EDP &&
5727                     encoder->connectors_active)
5728                         enable = true;
5729         }
5730
5731         /* Even the eDP panel fitter is outside the always-on well. */
5732         if (dev_priv->pch_pf_size)
5733                 enable = true;
5734
5735         intel_set_power_well(dev, enable);
5736 }
5737
5738 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5739                                  int x, int y,
5740                                  struct drm_framebuffer *fb)
5741 {
5742         struct drm_device *dev = crtc->dev;
5743         struct drm_i915_private *dev_priv = dev->dev_private;
5744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5745         struct drm_display_mode *adjusted_mode =
5746                 &intel_crtc->config.adjusted_mode;
5747         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5748         int pipe = intel_crtc->pipe;
5749         int plane = intel_crtc->plane;
5750         int num_connectors = 0;
5751         bool is_dp = false, is_cpu_edp = false;
5752         struct intel_encoder *encoder;
5753         int ret;
5754         bool dither;
5755
5756         for_each_encoder_on_crtc(dev, crtc, encoder) {
5757                 switch (encoder->type) {
5758                 case INTEL_OUTPUT_DISPLAYPORT:
5759                         is_dp = true;
5760                         break;
5761                 case INTEL_OUTPUT_EDP:
5762                         is_dp = true;
5763                         if (!intel_encoder_is_pch_edp(&encoder->base))
5764                                 is_cpu_edp = true;
5765                         break;
5766                 }
5767
5768                 num_connectors++;
5769         }
5770
5771         if (is_cpu_edp)
5772                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5773         else
5774                 intel_crtc->cpu_transcoder = pipe;
5775
5776         /* We are not sure yet this won't happen. */
5777         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5778              INTEL_PCH_TYPE(dev));
5779
5780         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5781              num_connectors, pipe_name(pipe));
5782
5783         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5784                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5785
5786         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5787
5788         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5789                 return -EINVAL;
5790
5791         /* Ensure that the cursor is valid for the new mode before changing... */
5792         intel_crtc_update_cursor(crtc, true);
5793
5794         /* determine panel color depth */
5795         dither = intel_crtc->config.dither;
5796
5797         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5798         drm_mode_debug_printmodeline(mode);
5799
5800         if (is_dp)
5801                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5802
5803         intel_crtc->lowfreq_avail = false;
5804
5805         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5806
5807         if (intel_crtc->config.has_pch_encoder)
5808                 ironlake_fdi_set_m_n(crtc);
5809
5810         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5811
5812         intel_set_pipe_csc(crtc);
5813
5814         /* Set up the display plane register */
5815         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5816         POSTING_READ(DSPCNTR(plane));
5817
5818         ret = intel_pipe_set_base(crtc, x, y, fb);
5819
5820         intel_update_watermarks(dev);
5821
5822         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5823
5824         return ret;
5825 }
5826
5827 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5828                                int x, int y,
5829                                struct drm_framebuffer *fb)
5830 {
5831         struct drm_device *dev = crtc->dev;
5832         struct drm_i915_private *dev_priv = dev->dev_private;
5833         struct drm_encoder_helper_funcs *encoder_funcs;
5834         struct intel_encoder *encoder;
5835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5836         struct drm_display_mode *adjusted_mode =
5837                 &intel_crtc->config.adjusted_mode;
5838         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5839         int pipe = intel_crtc->pipe;
5840         int ret;
5841
5842         drm_vblank_pre_modeset(dev, pipe);
5843
5844         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5845
5846         drm_vblank_post_modeset(dev, pipe);
5847
5848         if (ret != 0)
5849                 return ret;
5850
5851         for_each_encoder_on_crtc(dev, crtc, encoder) {
5852                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5853                         encoder->base.base.id,
5854                         drm_get_encoder_name(&encoder->base),
5855                         mode->base.id, mode->name);
5856                 if (encoder->mode_set) {
5857                         encoder->mode_set(encoder);
5858                 } else {
5859                         encoder_funcs = encoder->base.helper_private;
5860                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5861                 }
5862         }
5863
5864         return 0;
5865 }
5866
5867 static bool intel_eld_uptodate(struct drm_connector *connector,
5868                                int reg_eldv, uint32_t bits_eldv,
5869                                int reg_elda, uint32_t bits_elda,
5870                                int reg_edid)
5871 {
5872         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5873         uint8_t *eld = connector->eld;
5874         uint32_t i;
5875
5876         i = I915_READ(reg_eldv);
5877         i &= bits_eldv;
5878
5879         if (!eld[0])
5880                 return !i;
5881
5882         if (!i)
5883                 return false;
5884
5885         i = I915_READ(reg_elda);
5886         i &= ~bits_elda;
5887         I915_WRITE(reg_elda, i);
5888
5889         for (i = 0; i < eld[2]; i++)
5890                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5891                         return false;
5892
5893         return true;
5894 }
5895
5896 static void g4x_write_eld(struct drm_connector *connector,
5897                           struct drm_crtc *crtc)
5898 {
5899         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5900         uint8_t *eld = connector->eld;
5901         uint32_t eldv;
5902         uint32_t len;
5903         uint32_t i;
5904
5905         i = I915_READ(G4X_AUD_VID_DID);
5906
5907         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5908                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5909         else
5910                 eldv = G4X_ELDV_DEVCTG;
5911
5912         if (intel_eld_uptodate(connector,
5913                                G4X_AUD_CNTL_ST, eldv,
5914                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5915                                G4X_HDMIW_HDMIEDID))
5916                 return;
5917
5918         i = I915_READ(G4X_AUD_CNTL_ST);
5919         i &= ~(eldv | G4X_ELD_ADDR);
5920         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5921         I915_WRITE(G4X_AUD_CNTL_ST, i);
5922
5923         if (!eld[0])
5924                 return;
5925
5926         len = min_t(uint8_t, eld[2], len);
5927         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5928         for (i = 0; i < len; i++)
5929                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5930
5931         i = I915_READ(G4X_AUD_CNTL_ST);
5932         i |= eldv;
5933         I915_WRITE(G4X_AUD_CNTL_ST, i);
5934 }
5935
5936 static void haswell_write_eld(struct drm_connector *connector,
5937                                      struct drm_crtc *crtc)
5938 {
5939         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5940         uint8_t *eld = connector->eld;
5941         struct drm_device *dev = crtc->dev;
5942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5943         uint32_t eldv;
5944         uint32_t i;
5945         int len;
5946         int pipe = to_intel_crtc(crtc)->pipe;
5947         int tmp;
5948
5949         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5950         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5951         int aud_config = HSW_AUD_CFG(pipe);
5952         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5953
5954
5955         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5956
5957         /* Audio output enable */
5958         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5959         tmp = I915_READ(aud_cntrl_st2);
5960         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5961         I915_WRITE(aud_cntrl_st2, tmp);
5962
5963         /* Wait for 1 vertical blank */
5964         intel_wait_for_vblank(dev, pipe);
5965
5966         /* Set ELD valid state */
5967         tmp = I915_READ(aud_cntrl_st2);
5968         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5969         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5970         I915_WRITE(aud_cntrl_st2, tmp);
5971         tmp = I915_READ(aud_cntrl_st2);
5972         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5973
5974         /* Enable HDMI mode */
5975         tmp = I915_READ(aud_config);
5976         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5977         /* clear N_programing_enable and N_value_index */
5978         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5979         I915_WRITE(aud_config, tmp);
5980
5981         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5982
5983         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5984         intel_crtc->eld_vld = true;
5985
5986         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5987                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5988                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5989                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5990         } else
5991                 I915_WRITE(aud_config, 0);
5992
5993         if (intel_eld_uptodate(connector,
5994                                aud_cntrl_st2, eldv,
5995                                aud_cntl_st, IBX_ELD_ADDRESS,
5996                                hdmiw_hdmiedid))
5997                 return;
5998
5999         i = I915_READ(aud_cntrl_st2);
6000         i &= ~eldv;
6001         I915_WRITE(aud_cntrl_st2, i);
6002
6003         if (!eld[0])
6004                 return;
6005
6006         i = I915_READ(aud_cntl_st);
6007         i &= ~IBX_ELD_ADDRESS;
6008         I915_WRITE(aud_cntl_st, i);
6009         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6010         DRM_DEBUG_DRIVER("port num:%d\n", i);
6011
6012         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6013         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6014         for (i = 0; i < len; i++)
6015                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6016
6017         i = I915_READ(aud_cntrl_st2);
6018         i |= eldv;
6019         I915_WRITE(aud_cntrl_st2, i);
6020
6021 }
6022
6023 static void ironlake_write_eld(struct drm_connector *connector,
6024                                      struct drm_crtc *crtc)
6025 {
6026         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6027         uint8_t *eld = connector->eld;
6028         uint32_t eldv;
6029         uint32_t i;
6030         int len;
6031         int hdmiw_hdmiedid;
6032         int aud_config;
6033         int aud_cntl_st;
6034         int aud_cntrl_st2;
6035         int pipe = to_intel_crtc(crtc)->pipe;
6036
6037         if (HAS_PCH_IBX(connector->dev)) {
6038                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6039                 aud_config = IBX_AUD_CFG(pipe);
6040                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6041                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6042         } else {
6043                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6044                 aud_config = CPT_AUD_CFG(pipe);
6045                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6046                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6047         }
6048
6049         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6050
6051         i = I915_READ(aud_cntl_st);
6052         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6053         if (!i) {
6054                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6055                 /* operate blindly on all ports */
6056                 eldv = IBX_ELD_VALIDB;
6057                 eldv |= IBX_ELD_VALIDB << 4;
6058                 eldv |= IBX_ELD_VALIDB << 8;
6059         } else {
6060                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6061                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6062         }
6063
6064         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6065                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6066                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6067                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6068         } else
6069                 I915_WRITE(aud_config, 0);
6070
6071         if (intel_eld_uptodate(connector,
6072                                aud_cntrl_st2, eldv,
6073                                aud_cntl_st, IBX_ELD_ADDRESS,
6074                                hdmiw_hdmiedid))
6075                 return;
6076
6077         i = I915_READ(aud_cntrl_st2);
6078         i &= ~eldv;
6079         I915_WRITE(aud_cntrl_st2, i);
6080
6081         if (!eld[0])
6082                 return;
6083
6084         i = I915_READ(aud_cntl_st);
6085         i &= ~IBX_ELD_ADDRESS;
6086         I915_WRITE(aud_cntl_st, i);
6087
6088         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6089         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6090         for (i = 0; i < len; i++)
6091                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6092
6093         i = I915_READ(aud_cntrl_st2);
6094         i |= eldv;
6095         I915_WRITE(aud_cntrl_st2, i);
6096 }
6097
6098 void intel_write_eld(struct drm_encoder *encoder,
6099                      struct drm_display_mode *mode)
6100 {
6101         struct drm_crtc *crtc = encoder->crtc;
6102         struct drm_connector *connector;
6103         struct drm_device *dev = encoder->dev;
6104         struct drm_i915_private *dev_priv = dev->dev_private;
6105
6106         connector = drm_select_eld(encoder, mode);
6107         if (!connector)
6108                 return;
6109
6110         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6111                          connector->base.id,
6112                          drm_get_connector_name(connector),
6113                          connector->encoder->base.id,
6114                          drm_get_encoder_name(connector->encoder));
6115
6116         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6117
6118         if (dev_priv->display.write_eld)
6119                 dev_priv->display.write_eld(connector, crtc);
6120 }
6121
6122 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6123 void intel_crtc_load_lut(struct drm_crtc *crtc)
6124 {
6125         struct drm_device *dev = crtc->dev;
6126         struct drm_i915_private *dev_priv = dev->dev_private;
6127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6128         int palreg = PALETTE(intel_crtc->pipe);
6129         int i;
6130
6131         /* The clocks have to be on to load the palette. */
6132         if (!crtc->enabled || !intel_crtc->active)
6133                 return;
6134
6135         /* use legacy palette for Ironlake */
6136         if (HAS_PCH_SPLIT(dev))
6137                 palreg = LGC_PALETTE(intel_crtc->pipe);
6138
6139         for (i = 0; i < 256; i++) {
6140                 I915_WRITE(palreg + 4 * i,
6141                            (intel_crtc->lut_r[i] << 16) |
6142                            (intel_crtc->lut_g[i] << 8) |
6143                            intel_crtc->lut_b[i]);
6144         }
6145 }
6146
6147 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6148 {
6149         struct drm_device *dev = crtc->dev;
6150         struct drm_i915_private *dev_priv = dev->dev_private;
6151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152         bool visible = base != 0;
6153         u32 cntl;
6154
6155         if (intel_crtc->cursor_visible == visible)
6156                 return;
6157
6158         cntl = I915_READ(_CURACNTR);
6159         if (visible) {
6160                 /* On these chipsets we can only modify the base whilst
6161                  * the cursor is disabled.
6162                  */
6163                 I915_WRITE(_CURABASE, base);
6164
6165                 cntl &= ~(CURSOR_FORMAT_MASK);
6166                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6167                 cntl |= CURSOR_ENABLE |
6168                         CURSOR_GAMMA_ENABLE |
6169                         CURSOR_FORMAT_ARGB;
6170         } else
6171                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6172         I915_WRITE(_CURACNTR, cntl);
6173
6174         intel_crtc->cursor_visible = visible;
6175 }
6176
6177 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6178 {
6179         struct drm_device *dev = crtc->dev;
6180         struct drm_i915_private *dev_priv = dev->dev_private;
6181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6182         int pipe = intel_crtc->pipe;
6183         bool visible = base != 0;
6184
6185         if (intel_crtc->cursor_visible != visible) {
6186                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6187                 if (base) {
6188                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6189                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6190                         cntl |= pipe << 28; /* Connect to correct pipe */
6191                 } else {
6192                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6193                         cntl |= CURSOR_MODE_DISABLE;
6194                 }
6195                 I915_WRITE(CURCNTR(pipe), cntl);
6196
6197                 intel_crtc->cursor_visible = visible;
6198         }
6199         /* and commit changes on next vblank */
6200         I915_WRITE(CURBASE(pipe), base);
6201 }
6202
6203 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6204 {
6205         struct drm_device *dev = crtc->dev;
6206         struct drm_i915_private *dev_priv = dev->dev_private;
6207         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6208         int pipe = intel_crtc->pipe;
6209         bool visible = base != 0;
6210
6211         if (intel_crtc->cursor_visible != visible) {
6212                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6213                 if (base) {
6214                         cntl &= ~CURSOR_MODE;
6215                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6216                 } else {
6217                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6218                         cntl |= CURSOR_MODE_DISABLE;
6219                 }
6220                 if (IS_HASWELL(dev))
6221                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6222                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6223
6224                 intel_crtc->cursor_visible = visible;
6225         }
6226         /* and commit changes on next vblank */
6227         I915_WRITE(CURBASE_IVB(pipe), base);
6228 }
6229
6230 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6231 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6232                                      bool on)
6233 {
6234         struct drm_device *dev = crtc->dev;
6235         struct drm_i915_private *dev_priv = dev->dev_private;
6236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6237         int pipe = intel_crtc->pipe;
6238         int x = intel_crtc->cursor_x;
6239         int y = intel_crtc->cursor_y;
6240         u32 base, pos;
6241         bool visible;
6242
6243         pos = 0;
6244
6245         if (on && crtc->enabled && crtc->fb) {
6246                 base = intel_crtc->cursor_addr;
6247                 if (x > (int) crtc->fb->width)
6248                         base = 0;
6249
6250                 if (y > (int) crtc->fb->height)
6251                         base = 0;
6252         } else
6253                 base = 0;
6254
6255         if (x < 0) {
6256                 if (x + intel_crtc->cursor_width < 0)
6257                         base = 0;
6258
6259                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6260                 x = -x;
6261         }
6262         pos |= x << CURSOR_X_SHIFT;
6263
6264         if (y < 0) {
6265                 if (y + intel_crtc->cursor_height < 0)
6266                         base = 0;
6267
6268                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6269                 y = -y;
6270         }
6271         pos |= y << CURSOR_Y_SHIFT;
6272
6273         visible = base != 0;
6274         if (!visible && !intel_crtc->cursor_visible)
6275                 return;
6276
6277         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6278                 I915_WRITE(CURPOS_IVB(pipe), pos);
6279                 ivb_update_cursor(crtc, base);
6280         } else {
6281                 I915_WRITE(CURPOS(pipe), pos);
6282                 if (IS_845G(dev) || IS_I865G(dev))
6283                         i845_update_cursor(crtc, base);
6284                 else
6285                         i9xx_update_cursor(crtc, base);
6286         }
6287 }
6288
6289 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6290                                  struct drm_file *file,
6291                                  uint32_t handle,
6292                                  uint32_t width, uint32_t height)
6293 {
6294         struct drm_device *dev = crtc->dev;
6295         struct drm_i915_private *dev_priv = dev->dev_private;
6296         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6297         struct drm_i915_gem_object *obj;
6298         uint32_t addr;
6299         int ret;
6300
6301         /* if we want to turn off the cursor ignore width and height */
6302         if (!handle) {
6303                 DRM_DEBUG_KMS("cursor off\n");
6304                 addr = 0;
6305                 obj = NULL;
6306                 mutex_lock(&dev->struct_mutex);
6307                 goto finish;
6308         }
6309
6310         /* Currently we only support 64x64 cursors */
6311         if (width != 64 || height != 64) {
6312                 DRM_ERROR("we currently only support 64x64 cursors\n");
6313                 return -EINVAL;
6314         }
6315
6316         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6317         if (&obj->base == NULL)
6318                 return -ENOENT;
6319
6320         if (obj->base.size < width * height * 4) {
6321                 DRM_ERROR("buffer is to small\n");
6322                 ret = -ENOMEM;
6323                 goto fail;
6324         }
6325
6326         /* we only need to pin inside GTT if cursor is non-phy */
6327         mutex_lock(&dev->struct_mutex);
6328         if (!dev_priv->info->cursor_needs_physical) {
6329                 unsigned alignment;
6330
6331                 if (obj->tiling_mode) {
6332                         DRM_ERROR("cursor cannot be tiled\n");
6333                         ret = -EINVAL;
6334                         goto fail_locked;
6335                 }
6336
6337                 /* Note that the w/a also requires 2 PTE of padding following
6338                  * the bo. We currently fill all unused PTE with the shadow
6339                  * page and so we should always have valid PTE following the
6340                  * cursor preventing the VT-d warning.
6341                  */
6342                 alignment = 0;
6343                 if (need_vtd_wa(dev))
6344                         alignment = 64*1024;
6345
6346                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6347                 if (ret) {
6348                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6349                         goto fail_locked;
6350                 }
6351
6352                 ret = i915_gem_object_put_fence(obj);
6353                 if (ret) {
6354                         DRM_ERROR("failed to release fence for cursor");
6355                         goto fail_unpin;
6356                 }
6357
6358                 addr = obj->gtt_offset;
6359         } else {
6360                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6361                 ret = i915_gem_attach_phys_object(dev, obj,
6362                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6363                                                   align);
6364                 if (ret) {
6365                         DRM_ERROR("failed to attach phys object\n");
6366                         goto fail_locked;
6367                 }
6368                 addr = obj->phys_obj->handle->busaddr;
6369         }
6370
6371         if (IS_GEN2(dev))
6372                 I915_WRITE(CURSIZE, (height << 12) | width);
6373
6374  finish:
6375         if (intel_crtc->cursor_bo) {
6376                 if (dev_priv->info->cursor_needs_physical) {
6377                         if (intel_crtc->cursor_bo != obj)
6378                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6379                 } else
6380                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6381                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6382         }
6383
6384         mutex_unlock(&dev->struct_mutex);
6385
6386         intel_crtc->cursor_addr = addr;
6387         intel_crtc->cursor_bo = obj;
6388         intel_crtc->cursor_width = width;
6389         intel_crtc->cursor_height = height;
6390
6391         intel_crtc_update_cursor(crtc, true);
6392
6393         return 0;
6394 fail_unpin:
6395         i915_gem_object_unpin(obj);
6396 fail_locked:
6397         mutex_unlock(&dev->struct_mutex);
6398 fail:
6399         drm_gem_object_unreference_unlocked(&obj->base);
6400         return ret;
6401 }
6402
6403 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6404 {
6405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406
6407         intel_crtc->cursor_x = x;
6408         intel_crtc->cursor_y = y;
6409
6410         intel_crtc_update_cursor(crtc, true);
6411
6412         return 0;
6413 }
6414
6415 /** Sets the color ramps on behalf of RandR */
6416 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6417                                  u16 blue, int regno)
6418 {
6419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6420
6421         intel_crtc->lut_r[regno] = red >> 8;
6422         intel_crtc->lut_g[regno] = green >> 8;
6423         intel_crtc->lut_b[regno] = blue >> 8;
6424 }
6425
6426 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6427                              u16 *blue, int regno)
6428 {
6429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6430
6431         *red = intel_crtc->lut_r[regno] << 8;
6432         *green = intel_crtc->lut_g[regno] << 8;
6433         *blue = intel_crtc->lut_b[regno] << 8;
6434 }
6435
6436 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6437                                  u16 *blue, uint32_t start, uint32_t size)
6438 {
6439         int end = (start + size > 256) ? 256 : start + size, i;
6440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6441
6442         for (i = start; i < end; i++) {
6443                 intel_crtc->lut_r[i] = red[i] >> 8;
6444                 intel_crtc->lut_g[i] = green[i] >> 8;
6445                 intel_crtc->lut_b[i] = blue[i] >> 8;
6446         }
6447
6448         intel_crtc_load_lut(crtc);
6449 }
6450
6451 /* VESA 640x480x72Hz mode to set on the pipe */
6452 static struct drm_display_mode load_detect_mode = {
6453         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6454                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6455 };
6456
6457 static struct drm_framebuffer *
6458 intel_framebuffer_create(struct drm_device *dev,
6459                          struct drm_mode_fb_cmd2 *mode_cmd,
6460                          struct drm_i915_gem_object *obj)
6461 {
6462         struct intel_framebuffer *intel_fb;
6463         int ret;
6464
6465         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6466         if (!intel_fb) {
6467                 drm_gem_object_unreference_unlocked(&obj->base);
6468                 return ERR_PTR(-ENOMEM);
6469         }
6470
6471         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6472         if (ret) {
6473                 drm_gem_object_unreference_unlocked(&obj->base);
6474                 kfree(intel_fb);
6475                 return ERR_PTR(ret);
6476         }
6477
6478         return &intel_fb->base;
6479 }
6480
6481 static u32
6482 intel_framebuffer_pitch_for_width(int width, int bpp)
6483 {
6484         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6485         return ALIGN(pitch, 64);
6486 }
6487
6488 static u32
6489 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6490 {
6491         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6492         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6493 }
6494
6495 static struct drm_framebuffer *
6496 intel_framebuffer_create_for_mode(struct drm_device *dev,
6497                                   struct drm_display_mode *mode,
6498                                   int depth, int bpp)
6499 {
6500         struct drm_i915_gem_object *obj;
6501         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6502
6503         obj = i915_gem_alloc_object(dev,
6504                                     intel_framebuffer_size_for_mode(mode, bpp));
6505         if (obj == NULL)
6506                 return ERR_PTR(-ENOMEM);
6507
6508         mode_cmd.width = mode->hdisplay;
6509         mode_cmd.height = mode->vdisplay;
6510         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6511                                                                 bpp);
6512         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6513
6514         return intel_framebuffer_create(dev, &mode_cmd, obj);
6515 }
6516
6517 static struct drm_framebuffer *
6518 mode_fits_in_fbdev(struct drm_device *dev,
6519                    struct drm_display_mode *mode)
6520 {
6521         struct drm_i915_private *dev_priv = dev->dev_private;
6522         struct drm_i915_gem_object *obj;
6523         struct drm_framebuffer *fb;
6524
6525         if (dev_priv->fbdev == NULL)
6526                 return NULL;
6527
6528         obj = dev_priv->fbdev->ifb.obj;
6529         if (obj == NULL)
6530                 return NULL;
6531
6532         fb = &dev_priv->fbdev->ifb.base;
6533         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6534                                                                fb->bits_per_pixel))
6535                 return NULL;
6536
6537         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6538                 return NULL;
6539
6540         return fb;
6541 }
6542
6543 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6544                                 struct drm_display_mode *mode,
6545                                 struct intel_load_detect_pipe *old)
6546 {
6547         struct intel_crtc *intel_crtc;
6548         struct intel_encoder *intel_encoder =
6549                 intel_attached_encoder(connector);
6550         struct drm_crtc *possible_crtc;
6551         struct drm_encoder *encoder = &intel_encoder->base;
6552         struct drm_crtc *crtc = NULL;
6553         struct drm_device *dev = encoder->dev;
6554         struct drm_framebuffer *fb;
6555         int i = -1;
6556
6557         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6558                       connector->base.id, drm_get_connector_name(connector),
6559                       encoder->base.id, drm_get_encoder_name(encoder));
6560
6561         /*
6562          * Algorithm gets a little messy:
6563          *
6564          *   - if the connector already has an assigned crtc, use it (but make
6565          *     sure it's on first)
6566          *
6567          *   - try to find the first unused crtc that can drive this connector,
6568          *     and use that if we find one
6569          */
6570
6571         /* See if we already have a CRTC for this connector */
6572         if (encoder->crtc) {
6573                 crtc = encoder->crtc;
6574
6575                 mutex_lock(&crtc->mutex);
6576
6577                 old->dpms_mode = connector->dpms;
6578                 old->load_detect_temp = false;
6579
6580                 /* Make sure the crtc and connector are running */
6581                 if (connector->dpms != DRM_MODE_DPMS_ON)
6582                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6583
6584                 return true;
6585         }
6586
6587         /* Find an unused one (if possible) */
6588         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6589                 i++;
6590                 if (!(encoder->possible_crtcs & (1 << i)))
6591                         continue;
6592                 if (!possible_crtc->enabled) {
6593                         crtc = possible_crtc;
6594                         break;
6595                 }
6596         }
6597
6598         /*
6599          * If we didn't find an unused CRTC, don't use any.
6600          */
6601         if (!crtc) {
6602                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6603                 return false;
6604         }
6605
6606         mutex_lock(&crtc->mutex);
6607         intel_encoder->new_crtc = to_intel_crtc(crtc);
6608         to_intel_connector(connector)->new_encoder = intel_encoder;
6609
6610         intel_crtc = to_intel_crtc(crtc);
6611         old->dpms_mode = connector->dpms;
6612         old->load_detect_temp = true;
6613         old->release_fb = NULL;
6614
6615         if (!mode)
6616                 mode = &load_detect_mode;
6617
6618         /* We need a framebuffer large enough to accommodate all accesses
6619          * that the plane may generate whilst we perform load detection.
6620          * We can not rely on the fbcon either being present (we get called
6621          * during its initialisation to detect all boot displays, or it may
6622          * not even exist) or that it is large enough to satisfy the
6623          * requested mode.
6624          */
6625         fb = mode_fits_in_fbdev(dev, mode);
6626         if (fb == NULL) {
6627                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6628                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6629                 old->release_fb = fb;
6630         } else
6631                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6632         if (IS_ERR(fb)) {
6633                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6634                 mutex_unlock(&crtc->mutex);
6635                 return false;
6636         }
6637
6638         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6639                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6640                 if (old->release_fb)
6641                         old->release_fb->funcs->destroy(old->release_fb);
6642                 mutex_unlock(&crtc->mutex);
6643                 return false;
6644         }
6645
6646         /* let the connector get through one full cycle before testing */
6647         intel_wait_for_vblank(dev, intel_crtc->pipe);
6648         return true;
6649 }
6650
6651 void intel_release_load_detect_pipe(struct drm_connector *connector,
6652                                     struct intel_load_detect_pipe *old)
6653 {
6654         struct intel_encoder *intel_encoder =
6655                 intel_attached_encoder(connector);
6656         struct drm_encoder *encoder = &intel_encoder->base;
6657         struct drm_crtc *crtc = encoder->crtc;
6658
6659         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6660                       connector->base.id, drm_get_connector_name(connector),
6661                       encoder->base.id, drm_get_encoder_name(encoder));
6662
6663         if (old->load_detect_temp) {
6664                 to_intel_connector(connector)->new_encoder = NULL;
6665                 intel_encoder->new_crtc = NULL;
6666                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6667
6668                 if (old->release_fb) {
6669                         drm_framebuffer_unregister_private(old->release_fb);
6670                         drm_framebuffer_unreference(old->release_fb);
6671                 }
6672
6673                 mutex_unlock(&crtc->mutex);
6674                 return;
6675         }
6676
6677         /* Switch crtc and encoder back off if necessary */
6678         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6679                 connector->funcs->dpms(connector, old->dpms_mode);
6680
6681         mutex_unlock(&crtc->mutex);
6682 }
6683
6684 /* Returns the clock of the currently programmed mode of the given pipe. */
6685 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6686 {
6687         struct drm_i915_private *dev_priv = dev->dev_private;
6688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6689         int pipe = intel_crtc->pipe;
6690         u32 dpll = I915_READ(DPLL(pipe));
6691         u32 fp;
6692         intel_clock_t clock;
6693
6694         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6695                 fp = I915_READ(FP0(pipe));
6696         else
6697                 fp = I915_READ(FP1(pipe));
6698
6699         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6700         if (IS_PINEVIEW(dev)) {
6701                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6702                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6703         } else {
6704                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6705                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6706         }
6707
6708         if (!IS_GEN2(dev)) {
6709                 if (IS_PINEVIEW(dev))
6710                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6711                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6712                 else
6713                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6714                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6715
6716                 switch (dpll & DPLL_MODE_MASK) {
6717                 case DPLLB_MODE_DAC_SERIAL:
6718                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6719                                 5 : 10;
6720                         break;
6721                 case DPLLB_MODE_LVDS:
6722                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6723                                 7 : 14;
6724                         break;
6725                 default:
6726                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6727                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6728                         return 0;
6729                 }
6730
6731                 /* XXX: Handle the 100Mhz refclk */
6732                 intel_clock(dev, 96000, &clock);
6733         } else {
6734                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6735
6736                 if (is_lvds) {
6737                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6738                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6739                         clock.p2 = 14;
6740
6741                         if ((dpll & PLL_REF_INPUT_MASK) ==
6742                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6743                                 /* XXX: might not be 66MHz */
6744                                 intel_clock(dev, 66000, &clock);
6745                         } else
6746                                 intel_clock(dev, 48000, &clock);
6747                 } else {
6748                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6749                                 clock.p1 = 2;
6750                         else {
6751                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6752                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6753                         }
6754                         if (dpll & PLL_P2_DIVIDE_BY_4)
6755                                 clock.p2 = 4;
6756                         else
6757                                 clock.p2 = 2;
6758
6759                         intel_clock(dev, 48000, &clock);
6760                 }
6761         }
6762
6763         /* XXX: It would be nice to validate the clocks, but we can't reuse
6764          * i830PllIsValid() because it relies on the xf86_config connector
6765          * configuration being accurate, which it isn't necessarily.
6766          */
6767
6768         return clock.dot;
6769 }
6770
6771 /** Returns the currently programmed mode of the given pipe. */
6772 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6773                                              struct drm_crtc *crtc)
6774 {
6775         struct drm_i915_private *dev_priv = dev->dev_private;
6776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6777         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6778         struct drm_display_mode *mode;
6779         int htot = I915_READ(HTOTAL(cpu_transcoder));
6780         int hsync = I915_READ(HSYNC(cpu_transcoder));
6781         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6782         int vsync = I915_READ(VSYNC(cpu_transcoder));
6783
6784         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6785         if (!mode)
6786                 return NULL;
6787
6788         mode->clock = intel_crtc_clock_get(dev, crtc);
6789         mode->hdisplay = (htot & 0xffff) + 1;
6790         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6791         mode->hsync_start = (hsync & 0xffff) + 1;
6792         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6793         mode->vdisplay = (vtot & 0xffff) + 1;
6794         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6795         mode->vsync_start = (vsync & 0xffff) + 1;
6796         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6797
6798         drm_mode_set_name(mode);
6799
6800         return mode;
6801 }
6802
6803 static void intel_increase_pllclock(struct drm_crtc *crtc)
6804 {
6805         struct drm_device *dev = crtc->dev;
6806         drm_i915_private_t *dev_priv = dev->dev_private;
6807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6808         int pipe = intel_crtc->pipe;
6809         int dpll_reg = DPLL(pipe);
6810         int dpll;
6811
6812         if (HAS_PCH_SPLIT(dev))
6813                 return;
6814
6815         if (!dev_priv->lvds_downclock_avail)
6816                 return;
6817
6818         dpll = I915_READ(dpll_reg);
6819         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6820                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6821
6822                 assert_panel_unlocked(dev_priv, pipe);
6823
6824                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6825                 I915_WRITE(dpll_reg, dpll);
6826                 intel_wait_for_vblank(dev, pipe);
6827
6828                 dpll = I915_READ(dpll_reg);
6829                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6830                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6831         }
6832 }
6833
6834 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6835 {
6836         struct drm_device *dev = crtc->dev;
6837         drm_i915_private_t *dev_priv = dev->dev_private;
6838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6839
6840         if (HAS_PCH_SPLIT(dev))
6841                 return;
6842
6843         if (!dev_priv->lvds_downclock_avail)
6844                 return;
6845
6846         /*
6847          * Since this is called by a timer, we should never get here in
6848          * the manual case.
6849          */
6850         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6851                 int pipe = intel_crtc->pipe;
6852                 int dpll_reg = DPLL(pipe);
6853                 int dpll;
6854
6855                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6856
6857                 assert_panel_unlocked(dev_priv, pipe);
6858
6859                 dpll = I915_READ(dpll_reg);
6860                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6861                 I915_WRITE(dpll_reg, dpll);
6862                 intel_wait_for_vblank(dev, pipe);
6863                 dpll = I915_READ(dpll_reg);
6864                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6865                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6866         }
6867
6868 }
6869
6870 void intel_mark_busy(struct drm_device *dev)
6871 {
6872         i915_update_gfx_val(dev->dev_private);
6873 }
6874
6875 void intel_mark_idle(struct drm_device *dev)
6876 {
6877         struct drm_crtc *crtc;
6878
6879         if (!i915_powersave)
6880                 return;
6881
6882         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6883                 if (!crtc->fb)
6884                         continue;
6885
6886                 intel_decrease_pllclock(crtc);
6887         }
6888 }
6889
6890 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6891 {
6892         struct drm_device *dev = obj->base.dev;
6893         struct drm_crtc *crtc;
6894
6895         if (!i915_powersave)
6896                 return;
6897
6898         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6899                 if (!crtc->fb)
6900                         continue;
6901
6902                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6903                         intel_increase_pllclock(crtc);
6904         }
6905 }
6906
6907 static void intel_crtc_destroy(struct drm_crtc *crtc)
6908 {
6909         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6910         struct drm_device *dev = crtc->dev;
6911         struct intel_unpin_work *work;
6912         unsigned long flags;
6913
6914         spin_lock_irqsave(&dev->event_lock, flags);
6915         work = intel_crtc->unpin_work;
6916         intel_crtc->unpin_work = NULL;
6917         spin_unlock_irqrestore(&dev->event_lock, flags);
6918
6919         if (work) {
6920                 cancel_work_sync(&work->work);
6921                 kfree(work);
6922         }
6923
6924         drm_crtc_cleanup(crtc);
6925
6926         kfree(intel_crtc);
6927 }
6928
6929 static void intel_unpin_work_fn(struct work_struct *__work)
6930 {
6931         struct intel_unpin_work *work =
6932                 container_of(__work, struct intel_unpin_work, work);
6933         struct drm_device *dev = work->crtc->dev;
6934
6935         mutex_lock(&dev->struct_mutex);
6936         intel_unpin_fb_obj(work->old_fb_obj);
6937         drm_gem_object_unreference(&work->pending_flip_obj->base);
6938         drm_gem_object_unreference(&work->old_fb_obj->base);
6939
6940         intel_update_fbc(dev);
6941         mutex_unlock(&dev->struct_mutex);
6942
6943         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6944         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6945
6946         kfree(work);
6947 }
6948
6949 static void do_intel_finish_page_flip(struct drm_device *dev,
6950                                       struct drm_crtc *crtc)
6951 {
6952         drm_i915_private_t *dev_priv = dev->dev_private;
6953         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6954         struct intel_unpin_work *work;
6955         unsigned long flags;
6956
6957         /* Ignore early vblank irqs */
6958         if (intel_crtc == NULL)
6959                 return;
6960
6961         spin_lock_irqsave(&dev->event_lock, flags);
6962         work = intel_crtc->unpin_work;
6963
6964         /* Ensure we don't miss a work->pending update ... */
6965         smp_rmb();
6966
6967         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6968                 spin_unlock_irqrestore(&dev->event_lock, flags);
6969                 return;
6970         }
6971
6972         /* and that the unpin work is consistent wrt ->pending. */
6973         smp_rmb();
6974
6975         intel_crtc->unpin_work = NULL;
6976
6977         if (work->event)
6978                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6979
6980         drm_vblank_put(dev, intel_crtc->pipe);
6981
6982         spin_unlock_irqrestore(&dev->event_lock, flags);
6983
6984         wake_up_all(&dev_priv->pending_flip_queue);
6985
6986         queue_work(dev_priv->wq, &work->work);
6987
6988         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6989 }
6990
6991 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6992 {
6993         drm_i915_private_t *dev_priv = dev->dev_private;
6994         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6995
6996         do_intel_finish_page_flip(dev, crtc);
6997 }
6998
6999 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7000 {
7001         drm_i915_private_t *dev_priv = dev->dev_private;
7002         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7003
7004         do_intel_finish_page_flip(dev, crtc);
7005 }
7006
7007 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7008 {
7009         drm_i915_private_t *dev_priv = dev->dev_private;
7010         struct intel_crtc *intel_crtc =
7011                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7012         unsigned long flags;
7013
7014         /* NB: An MMIO update of the plane base pointer will also
7015          * generate a page-flip completion irq, i.e. every modeset
7016          * is also accompanied by a spurious intel_prepare_page_flip().
7017          */
7018         spin_lock_irqsave(&dev->event_lock, flags);
7019         if (intel_crtc->unpin_work)
7020                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7021         spin_unlock_irqrestore(&dev->event_lock, flags);
7022 }
7023
7024 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7025 {
7026         /* Ensure that the work item is consistent when activating it ... */
7027         smp_wmb();
7028         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7029         /* and that it is marked active as soon as the irq could fire. */
7030         smp_wmb();
7031 }
7032
7033 static int intel_gen2_queue_flip(struct drm_device *dev,
7034                                  struct drm_crtc *crtc,
7035                                  struct drm_framebuffer *fb,
7036                                  struct drm_i915_gem_object *obj)
7037 {
7038         struct drm_i915_private *dev_priv = dev->dev_private;
7039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7040         u32 flip_mask;
7041         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7042         int ret;
7043
7044         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7045         if (ret)
7046                 goto err;
7047
7048         ret = intel_ring_begin(ring, 6);
7049         if (ret)
7050                 goto err_unpin;
7051
7052         /* Can't queue multiple flips, so wait for the previous
7053          * one to finish before executing the next.
7054          */
7055         if (intel_crtc->plane)
7056                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7057         else
7058                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7059         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7060         intel_ring_emit(ring, MI_NOOP);
7061         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7062                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7063         intel_ring_emit(ring, fb->pitches[0]);
7064         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7065         intel_ring_emit(ring, 0); /* aux display base address, unused */
7066
7067         intel_mark_page_flip_active(intel_crtc);
7068         intel_ring_advance(ring);
7069         return 0;
7070
7071 err_unpin:
7072         intel_unpin_fb_obj(obj);
7073 err:
7074         return ret;
7075 }
7076
7077 static int intel_gen3_queue_flip(struct drm_device *dev,
7078                                  struct drm_crtc *crtc,
7079                                  struct drm_framebuffer *fb,
7080                                  struct drm_i915_gem_object *obj)
7081 {
7082         struct drm_i915_private *dev_priv = dev->dev_private;
7083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7084         u32 flip_mask;
7085         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7086         int ret;
7087
7088         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7089         if (ret)
7090                 goto err;
7091
7092         ret = intel_ring_begin(ring, 6);
7093         if (ret)
7094                 goto err_unpin;
7095
7096         if (intel_crtc->plane)
7097                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7098         else
7099                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7100         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7101         intel_ring_emit(ring, MI_NOOP);
7102         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7103                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7104         intel_ring_emit(ring, fb->pitches[0]);
7105         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7106         intel_ring_emit(ring, MI_NOOP);
7107
7108         intel_mark_page_flip_active(intel_crtc);
7109         intel_ring_advance(ring);
7110         return 0;
7111
7112 err_unpin:
7113         intel_unpin_fb_obj(obj);
7114 err:
7115         return ret;
7116 }
7117
7118 static int intel_gen4_queue_flip(struct drm_device *dev,
7119                                  struct drm_crtc *crtc,
7120                                  struct drm_framebuffer *fb,
7121                                  struct drm_i915_gem_object *obj)
7122 {
7123         struct drm_i915_private *dev_priv = dev->dev_private;
7124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7125         uint32_t pf, pipesrc;
7126         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7127         int ret;
7128
7129         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7130         if (ret)
7131                 goto err;
7132
7133         ret = intel_ring_begin(ring, 4);
7134         if (ret)
7135                 goto err_unpin;
7136
7137         /* i965+ uses the linear or tiled offsets from the
7138          * Display Registers (which do not change across a page-flip)
7139          * so we need only reprogram the base address.
7140          */
7141         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7142                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7143         intel_ring_emit(ring, fb->pitches[0]);
7144         intel_ring_emit(ring,
7145                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7146                         obj->tiling_mode);
7147
7148         /* XXX Enabling the panel-fitter across page-flip is so far
7149          * untested on non-native modes, so ignore it for now.
7150          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7151          */
7152         pf = 0;
7153         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7154         intel_ring_emit(ring, pf | pipesrc);
7155
7156         intel_mark_page_flip_active(intel_crtc);
7157         intel_ring_advance(ring);
7158         return 0;
7159
7160 err_unpin:
7161         intel_unpin_fb_obj(obj);
7162 err:
7163         return ret;
7164 }
7165
7166 static int intel_gen6_queue_flip(struct drm_device *dev,
7167                                  struct drm_crtc *crtc,
7168                                  struct drm_framebuffer *fb,
7169                                  struct drm_i915_gem_object *obj)
7170 {
7171         struct drm_i915_private *dev_priv = dev->dev_private;
7172         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7173         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7174         uint32_t pf, pipesrc;
7175         int ret;
7176
7177         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7178         if (ret)
7179                 goto err;
7180
7181         ret = intel_ring_begin(ring, 4);
7182         if (ret)
7183                 goto err_unpin;
7184
7185         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7186                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7187         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7188         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7189
7190         /* Contrary to the suggestions in the documentation,
7191          * "Enable Panel Fitter" does not seem to be required when page
7192          * flipping with a non-native mode, and worse causes a normal
7193          * modeset to fail.
7194          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7195          */
7196         pf = 0;
7197         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7198         intel_ring_emit(ring, pf | pipesrc);
7199
7200         intel_mark_page_flip_active(intel_crtc);
7201         intel_ring_advance(ring);
7202         return 0;
7203
7204 err_unpin:
7205         intel_unpin_fb_obj(obj);
7206 err:
7207         return ret;
7208 }
7209
7210 /*
7211  * On gen7 we currently use the blit ring because (in early silicon at least)
7212  * the render ring doesn't give us interrpts for page flip completion, which
7213  * means clients will hang after the first flip is queued.  Fortunately the
7214  * blit ring generates interrupts properly, so use it instead.
7215  */
7216 static int intel_gen7_queue_flip(struct drm_device *dev,
7217                                  struct drm_crtc *crtc,
7218                                  struct drm_framebuffer *fb,
7219                                  struct drm_i915_gem_object *obj)
7220 {
7221         struct drm_i915_private *dev_priv = dev->dev_private;
7222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7223         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7224         uint32_t plane_bit = 0;
7225         int ret;
7226
7227         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7228         if (ret)
7229                 goto err;
7230
7231         switch(intel_crtc->plane) {
7232         case PLANE_A:
7233                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7234                 break;
7235         case PLANE_B:
7236                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7237                 break;
7238         case PLANE_C:
7239                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7240                 break;
7241         default:
7242                 WARN_ONCE(1, "unknown plane in flip command\n");
7243                 ret = -ENODEV;
7244                 goto err_unpin;
7245         }
7246
7247         ret = intel_ring_begin(ring, 4);
7248         if (ret)
7249                 goto err_unpin;
7250
7251         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7252         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7253         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7254         intel_ring_emit(ring, (MI_NOOP));
7255
7256         intel_mark_page_flip_active(intel_crtc);
7257         intel_ring_advance(ring);
7258         return 0;
7259
7260 err_unpin:
7261         intel_unpin_fb_obj(obj);
7262 err:
7263         return ret;
7264 }
7265
7266 static int intel_default_queue_flip(struct drm_device *dev,
7267                                     struct drm_crtc *crtc,
7268                                     struct drm_framebuffer *fb,
7269                                     struct drm_i915_gem_object *obj)
7270 {
7271         return -ENODEV;
7272 }
7273
7274 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7275                                 struct drm_framebuffer *fb,
7276                                 struct drm_pending_vblank_event *event)
7277 {
7278         struct drm_device *dev = crtc->dev;
7279         struct drm_i915_private *dev_priv = dev->dev_private;
7280         struct drm_framebuffer *old_fb = crtc->fb;
7281         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7283         struct intel_unpin_work *work;
7284         unsigned long flags;
7285         int ret;
7286
7287         /* Can't change pixel format via MI display flips. */
7288         if (fb->pixel_format != crtc->fb->pixel_format)
7289                 return -EINVAL;
7290
7291         /*
7292          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7293          * Note that pitch changes could also affect these register.
7294          */
7295         if (INTEL_INFO(dev)->gen > 3 &&
7296             (fb->offsets[0] != crtc->fb->offsets[0] ||
7297              fb->pitches[0] != crtc->fb->pitches[0]))
7298                 return -EINVAL;
7299
7300         work = kzalloc(sizeof *work, GFP_KERNEL);
7301         if (work == NULL)
7302                 return -ENOMEM;
7303
7304         work->event = event;
7305         work->crtc = crtc;
7306         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7307         INIT_WORK(&work->work, intel_unpin_work_fn);
7308
7309         ret = drm_vblank_get(dev, intel_crtc->pipe);
7310         if (ret)
7311                 goto free_work;
7312
7313         /* We borrow the event spin lock for protecting unpin_work */
7314         spin_lock_irqsave(&dev->event_lock, flags);
7315         if (intel_crtc->unpin_work) {
7316                 spin_unlock_irqrestore(&dev->event_lock, flags);
7317                 kfree(work);
7318                 drm_vblank_put(dev, intel_crtc->pipe);
7319
7320                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7321                 return -EBUSY;
7322         }
7323         intel_crtc->unpin_work = work;
7324         spin_unlock_irqrestore(&dev->event_lock, flags);
7325
7326         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7327                 flush_workqueue(dev_priv->wq);
7328
7329         ret = i915_mutex_lock_interruptible(dev);
7330         if (ret)
7331                 goto cleanup;
7332
7333         /* Reference the objects for the scheduled work. */
7334         drm_gem_object_reference(&work->old_fb_obj->base);
7335         drm_gem_object_reference(&obj->base);
7336
7337         crtc->fb = fb;
7338
7339         work->pending_flip_obj = obj;
7340
7341         work->enable_stall_check = true;
7342
7343         atomic_inc(&intel_crtc->unpin_work_count);
7344         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7345
7346         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7347         if (ret)
7348                 goto cleanup_pending;
7349
7350         intel_disable_fbc(dev);
7351         intel_mark_fb_busy(obj);
7352         mutex_unlock(&dev->struct_mutex);
7353
7354         trace_i915_flip_request(intel_crtc->plane, obj);
7355
7356         return 0;
7357
7358 cleanup_pending:
7359         atomic_dec(&intel_crtc->unpin_work_count);
7360         crtc->fb = old_fb;
7361         drm_gem_object_unreference(&work->old_fb_obj->base);
7362         drm_gem_object_unreference(&obj->base);
7363         mutex_unlock(&dev->struct_mutex);
7364
7365 cleanup:
7366         spin_lock_irqsave(&dev->event_lock, flags);
7367         intel_crtc->unpin_work = NULL;
7368         spin_unlock_irqrestore(&dev->event_lock, flags);
7369
7370         drm_vblank_put(dev, intel_crtc->pipe);
7371 free_work:
7372         kfree(work);
7373
7374         return ret;
7375 }
7376
7377 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7378         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7379         .load_lut = intel_crtc_load_lut,
7380 };
7381
7382 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7383 {
7384         struct intel_encoder *other_encoder;
7385         struct drm_crtc *crtc = &encoder->new_crtc->base;
7386
7387         if (WARN_ON(!crtc))
7388                 return false;
7389
7390         list_for_each_entry(other_encoder,
7391                             &crtc->dev->mode_config.encoder_list,
7392                             base.head) {
7393
7394                 if (&other_encoder->new_crtc->base != crtc ||
7395                     encoder == other_encoder)
7396                         continue;
7397                 else
7398                         return true;
7399         }
7400
7401         return false;
7402 }
7403
7404 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7405                                   struct drm_crtc *crtc)
7406 {
7407         struct drm_device *dev;
7408         struct drm_crtc *tmp;
7409         int crtc_mask = 1;
7410
7411         WARN(!crtc, "checking null crtc?\n");
7412
7413         dev = crtc->dev;
7414
7415         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7416                 if (tmp == crtc)
7417                         break;
7418                 crtc_mask <<= 1;
7419         }
7420
7421         if (encoder->possible_crtcs & crtc_mask)
7422                 return true;
7423         return false;
7424 }
7425
7426 /**
7427  * intel_modeset_update_staged_output_state
7428  *
7429  * Updates the staged output configuration state, e.g. after we've read out the
7430  * current hw state.
7431  */
7432 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7433 {
7434         struct intel_encoder *encoder;
7435         struct intel_connector *connector;
7436
7437         list_for_each_entry(connector, &dev->mode_config.connector_list,
7438                             base.head) {
7439                 connector->new_encoder =
7440                         to_intel_encoder(connector->base.encoder);
7441         }
7442
7443         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7444                             base.head) {
7445                 encoder->new_crtc =
7446                         to_intel_crtc(encoder->base.crtc);
7447         }
7448 }
7449
7450 /**
7451  * intel_modeset_commit_output_state
7452  *
7453  * This function copies the stage display pipe configuration to the real one.
7454  */
7455 static void intel_modeset_commit_output_state(struct drm_device *dev)
7456 {
7457         struct intel_encoder *encoder;
7458         struct intel_connector *connector;
7459
7460         list_for_each_entry(connector, &dev->mode_config.connector_list,
7461                             base.head) {
7462                 connector->base.encoder = &connector->new_encoder->base;
7463         }
7464
7465         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7466                             base.head) {
7467                 encoder->base.crtc = &encoder->new_crtc->base;
7468         }
7469 }
7470
7471 static int
7472 pipe_config_set_bpp(struct drm_crtc *crtc,
7473                     struct drm_framebuffer *fb,
7474                     struct intel_crtc_config *pipe_config)
7475 {
7476         struct drm_device *dev = crtc->dev;
7477         struct drm_connector *connector;
7478         int bpp;
7479
7480         switch (fb->pixel_format) {
7481         case DRM_FORMAT_C8:
7482                 bpp = 8*3; /* since we go through a colormap */
7483                 break;
7484         case DRM_FORMAT_XRGB1555:
7485         case DRM_FORMAT_ARGB1555:
7486                 /* checked in intel_framebuffer_init already */
7487                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7488                         return -EINVAL;
7489         case DRM_FORMAT_RGB565:
7490                 bpp = 6*3; /* min is 18bpp */
7491                 break;
7492         case DRM_FORMAT_XBGR8888:
7493         case DRM_FORMAT_ABGR8888:
7494                 /* checked in intel_framebuffer_init already */
7495                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7496                         return -EINVAL;
7497         case DRM_FORMAT_XRGB8888:
7498         case DRM_FORMAT_ARGB8888:
7499                 bpp = 8*3;
7500                 break;
7501         case DRM_FORMAT_XRGB2101010:
7502         case DRM_FORMAT_ARGB2101010:
7503         case DRM_FORMAT_XBGR2101010:
7504         case DRM_FORMAT_ABGR2101010:
7505                 /* checked in intel_framebuffer_init already */
7506                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7507                         return -EINVAL;
7508                 bpp = 10*3;
7509                 break;
7510         /* TODO: gen4+ supports 16 bpc floating point, too. */
7511         default:
7512                 DRM_DEBUG_KMS("unsupported depth\n");
7513                 return -EINVAL;
7514         }
7515
7516         pipe_config->pipe_bpp = bpp;
7517
7518         /* Clamp display bpp to EDID value */
7519         list_for_each_entry(connector, &dev->mode_config.connector_list,
7520                             head) {
7521                 if (connector->encoder && connector->encoder->crtc != crtc)
7522                         continue;
7523
7524                 /* Don't use an invalid EDID bpc value */
7525                 if (connector->display_info.bpc &&
7526                     connector->display_info.bpc * 3 < bpp) {
7527                         DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7528                                       bpp, connector->display_info.bpc*3);
7529                         pipe_config->pipe_bpp = connector->display_info.bpc*3;
7530                 }
7531         }
7532
7533         return bpp;
7534 }
7535
7536 static struct intel_crtc_config *
7537 intel_modeset_pipe_config(struct drm_crtc *crtc,
7538                           struct drm_framebuffer *fb,
7539                           struct drm_display_mode *mode)
7540 {
7541         struct drm_device *dev = crtc->dev;
7542         struct drm_encoder_helper_funcs *encoder_funcs;
7543         struct intel_encoder *encoder;
7544         struct intel_crtc_config *pipe_config;
7545         int plane_bpp;
7546
7547         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7548         if (!pipe_config)
7549                 return ERR_PTR(-ENOMEM);
7550
7551         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7552         drm_mode_copy(&pipe_config->requested_mode, mode);
7553
7554         plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7555         if (plane_bpp < 0)
7556                 goto fail;
7557
7558         /* Pass our mode to the connectors and the CRTC to give them a chance to
7559          * adjust it according to limitations or connector properties, and also
7560          * a chance to reject the mode entirely.
7561          */
7562         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7563                             base.head) {
7564
7565                 if (&encoder->new_crtc->base != crtc)
7566                         continue;
7567
7568                 if (encoder->compute_config) {
7569                         if (!(encoder->compute_config(encoder, pipe_config))) {
7570                                 DRM_DEBUG_KMS("Encoder config failure\n");
7571                                 goto fail;
7572                         }
7573
7574                         continue;
7575                 }
7576
7577                 encoder_funcs = encoder->base.helper_private;
7578                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7579                                                 &pipe_config->requested_mode,
7580                                                 &pipe_config->adjusted_mode))) {
7581                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7582                         goto fail;
7583                 }
7584         }
7585
7586         if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7587                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7588                 goto fail;
7589         }
7590         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7591
7592         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7593         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7594                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7595
7596         return pipe_config;
7597 fail:
7598         kfree(pipe_config);
7599         return ERR_PTR(-EINVAL);
7600 }
7601
7602 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7603  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7604 static void
7605 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7606                              unsigned *prepare_pipes, unsigned *disable_pipes)
7607 {
7608         struct intel_crtc *intel_crtc;
7609         struct drm_device *dev = crtc->dev;
7610         struct intel_encoder *encoder;
7611         struct intel_connector *connector;
7612         struct drm_crtc *tmp_crtc;
7613
7614         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7615
7616         /* Check which crtcs have changed outputs connected to them, these need
7617          * to be part of the prepare_pipes mask. We don't (yet) support global
7618          * modeset across multiple crtcs, so modeset_pipes will only have one
7619          * bit set at most. */
7620         list_for_each_entry(connector, &dev->mode_config.connector_list,
7621                             base.head) {
7622                 if (connector->base.encoder == &connector->new_encoder->base)
7623                         continue;
7624
7625                 if (connector->base.encoder) {
7626                         tmp_crtc = connector->base.encoder->crtc;
7627
7628                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7629                 }
7630
7631                 if (connector->new_encoder)
7632                         *prepare_pipes |=
7633                                 1 << connector->new_encoder->new_crtc->pipe;
7634         }
7635
7636         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7637                             base.head) {
7638                 if (encoder->base.crtc == &encoder->new_crtc->base)
7639                         continue;
7640
7641                 if (encoder->base.crtc) {
7642                         tmp_crtc = encoder->base.crtc;
7643
7644                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7645                 }
7646
7647                 if (encoder->new_crtc)
7648                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7649         }
7650
7651         /* Check for any pipes that will be fully disabled ... */
7652         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7653                             base.head) {
7654                 bool used = false;
7655
7656                 /* Don't try to disable disabled crtcs. */
7657                 if (!intel_crtc->base.enabled)
7658                         continue;
7659
7660                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7661                                     base.head) {
7662                         if (encoder->new_crtc == intel_crtc)
7663                                 used = true;
7664                 }
7665
7666                 if (!used)
7667                         *disable_pipes |= 1 << intel_crtc->pipe;
7668         }
7669
7670
7671         /* set_mode is also used to update properties on life display pipes. */
7672         intel_crtc = to_intel_crtc(crtc);
7673         if (crtc->enabled)
7674                 *prepare_pipes |= 1 << intel_crtc->pipe;
7675
7676         /* We only support modeset on one single crtc, hence we need to do that
7677          * only for the passed in crtc iff we change anything else than just
7678          * disable crtcs.
7679          *
7680          * This is actually not true, to be fully compatible with the old crtc
7681          * helper we automatically disable _any_ output (i.e. doesn't need to be
7682          * connected to the crtc we're modesetting on) if it's disconnected.
7683          * Which is a rather nutty api (since changed the output configuration
7684          * without userspace's explicit request can lead to confusion), but
7685          * alas. Hence we currently need to modeset on all pipes we prepare. */
7686         if (*prepare_pipes)
7687                 *modeset_pipes = *prepare_pipes;
7688
7689         /* ... and mask these out. */
7690         *modeset_pipes &= ~(*disable_pipes);
7691         *prepare_pipes &= ~(*disable_pipes);
7692 }
7693
7694 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7695 {
7696         struct drm_encoder *encoder;
7697         struct drm_device *dev = crtc->dev;
7698
7699         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7700                 if (encoder->crtc == crtc)
7701                         return true;
7702
7703         return false;
7704 }
7705
7706 static void
7707 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7708 {
7709         struct intel_encoder *intel_encoder;
7710         struct intel_crtc *intel_crtc;
7711         struct drm_connector *connector;
7712
7713         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7714                             base.head) {
7715                 if (!intel_encoder->base.crtc)
7716                         continue;
7717
7718                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7719
7720                 if (prepare_pipes & (1 << intel_crtc->pipe))
7721                         intel_encoder->connectors_active = false;
7722         }
7723
7724         intel_modeset_commit_output_state(dev);
7725
7726         /* Update computed state. */
7727         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7728                             base.head) {
7729                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7730         }
7731
7732         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7733                 if (!connector->encoder || !connector->encoder->crtc)
7734                         continue;
7735
7736                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7737
7738                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7739                         struct drm_property *dpms_property =
7740                                 dev->mode_config.dpms_property;
7741
7742                         connector->dpms = DRM_MODE_DPMS_ON;
7743                         drm_object_property_set_value(&connector->base,
7744                                                          dpms_property,
7745                                                          DRM_MODE_DPMS_ON);
7746
7747                         intel_encoder = to_intel_encoder(connector->encoder);
7748                         intel_encoder->connectors_active = true;
7749                 }
7750         }
7751
7752 }
7753
7754 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7755         list_for_each_entry((intel_crtc), \
7756                             &(dev)->mode_config.crtc_list, \
7757                             base.head) \
7758                 if (mask & (1 <<(intel_crtc)->pipe)) \
7759
7760 void
7761 intel_modeset_check_state(struct drm_device *dev)
7762 {
7763         struct intel_crtc *crtc;
7764         struct intel_encoder *encoder;
7765         struct intel_connector *connector;
7766
7767         list_for_each_entry(connector, &dev->mode_config.connector_list,
7768                             base.head) {
7769                 /* This also checks the encoder/connector hw state with the
7770                  * ->get_hw_state callbacks. */
7771                 intel_connector_check_state(connector);
7772
7773                 WARN(&connector->new_encoder->base != connector->base.encoder,
7774                      "connector's staged encoder doesn't match current encoder\n");
7775         }
7776
7777         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7778                             base.head) {
7779                 bool enabled = false;
7780                 bool active = false;
7781                 enum pipe pipe, tracked_pipe;
7782
7783                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7784                               encoder->base.base.id,
7785                               drm_get_encoder_name(&encoder->base));
7786
7787                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7788                      "encoder's stage crtc doesn't match current crtc\n");
7789                 WARN(encoder->connectors_active && !encoder->base.crtc,
7790                      "encoder's active_connectors set, but no crtc\n");
7791
7792                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7793                                     base.head) {
7794                         if (connector->base.encoder != &encoder->base)
7795                                 continue;
7796                         enabled = true;
7797                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7798                                 active = true;
7799                 }
7800                 WARN(!!encoder->base.crtc != enabled,
7801                      "encoder's enabled state mismatch "
7802                      "(expected %i, found %i)\n",
7803                      !!encoder->base.crtc, enabled);
7804                 WARN(active && !encoder->base.crtc,
7805                      "active encoder with no crtc\n");
7806
7807                 WARN(encoder->connectors_active != active,
7808                      "encoder's computed active state doesn't match tracked active state "
7809                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7810
7811                 active = encoder->get_hw_state(encoder, &pipe);
7812                 WARN(active != encoder->connectors_active,
7813                      "encoder's hw state doesn't match sw tracking "
7814                      "(expected %i, found %i)\n",
7815                      encoder->connectors_active, active);
7816
7817                 if (!encoder->base.crtc)
7818                         continue;
7819
7820                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7821                 WARN(active && pipe != tracked_pipe,
7822                      "active encoder's pipe doesn't match"
7823                      "(expected %i, found %i)\n",
7824                      tracked_pipe, pipe);
7825
7826         }
7827
7828         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7829                             base.head) {
7830                 bool enabled = false;
7831                 bool active = false;
7832
7833                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7834                               crtc->base.base.id);
7835
7836                 WARN(crtc->active && !crtc->base.enabled,
7837                      "active crtc, but not enabled in sw tracking\n");
7838
7839                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7840                                     base.head) {
7841                         if (encoder->base.crtc != &crtc->base)
7842                                 continue;
7843                         enabled = true;
7844                         if (encoder->connectors_active)
7845                                 active = true;
7846                 }
7847                 WARN(active != crtc->active,
7848                      "crtc's computed active state doesn't match tracked active state "
7849                      "(expected %i, found %i)\n", active, crtc->active);
7850                 WARN(enabled != crtc->base.enabled,
7851                      "crtc's computed enabled state doesn't match tracked enabled state "
7852                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7853
7854                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7855         }
7856 }
7857
7858 int intel_set_mode(struct drm_crtc *crtc,
7859                    struct drm_display_mode *mode,
7860                    int x, int y, struct drm_framebuffer *fb)
7861 {
7862         struct drm_device *dev = crtc->dev;
7863         drm_i915_private_t *dev_priv = dev->dev_private;
7864         struct drm_display_mode *saved_mode, *saved_hwmode;
7865         struct intel_crtc_config *pipe_config = NULL;
7866         struct intel_crtc *intel_crtc;
7867         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7868         int ret = 0;
7869
7870         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7871         if (!saved_mode)
7872                 return -ENOMEM;
7873         saved_hwmode = saved_mode + 1;
7874
7875         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7876                                      &prepare_pipes, &disable_pipes);
7877
7878         *saved_hwmode = crtc->hwmode;
7879         *saved_mode = crtc->mode;
7880
7881         /* Hack: Because we don't (yet) support global modeset on multiple
7882          * crtcs, we don't keep track of the new mode for more than one crtc.
7883          * Hence simply check whether any bit is set in modeset_pipes in all the
7884          * pieces of code that are not yet converted to deal with mutliple crtcs
7885          * changing their mode at the same time. */
7886         if (modeset_pipes) {
7887                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
7888                 if (IS_ERR(pipe_config)) {
7889                         ret = PTR_ERR(pipe_config);
7890                         pipe_config = NULL;
7891
7892                         goto out;
7893                 }
7894         }
7895
7896         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7897                       modeset_pipes, prepare_pipes, disable_pipes);
7898
7899         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7900                 intel_crtc_disable(&intel_crtc->base);
7901
7902         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7903                 if (intel_crtc->base.enabled)
7904                         dev_priv->display.crtc_disable(&intel_crtc->base);
7905         }
7906
7907         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7908          * to set it here already despite that we pass it down the callchain.
7909          */
7910         if (modeset_pipes) {
7911                 crtc->mode = *mode;
7912                 /* mode_set/enable/disable functions rely on a correct pipe
7913                  * config. */
7914                 to_intel_crtc(crtc)->config = *pipe_config;
7915         }
7916
7917         /* Only after disabling all output pipelines that will be changed can we
7918          * update the the output configuration. */
7919         intel_modeset_update_state(dev, prepare_pipes);
7920
7921         if (dev_priv->display.modeset_global_resources)
7922                 dev_priv->display.modeset_global_resources(dev);
7923
7924         /* Set up the DPLL and any encoders state that needs to adjust or depend
7925          * on the DPLL.
7926          */
7927         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7928                 ret = intel_crtc_mode_set(&intel_crtc->base,
7929                                           x, y, fb);
7930                 if (ret)
7931                         goto done;
7932         }
7933
7934         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7935         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7936                 dev_priv->display.crtc_enable(&intel_crtc->base);
7937
7938         if (modeset_pipes) {
7939                 /* Store real post-adjustment hardware mode. */
7940                 crtc->hwmode = pipe_config->adjusted_mode;
7941
7942                 /* Calculate and store various constants which
7943                  * are later needed by vblank and swap-completion
7944                  * timestamping. They are derived from true hwmode.
7945                  */
7946                 drm_calc_timestamping_constants(crtc);
7947         }
7948
7949         /* FIXME: add subpixel order */
7950 done:
7951         if (ret && crtc->enabled) {
7952                 crtc->hwmode = *saved_hwmode;
7953                 crtc->mode = *saved_mode;
7954         } else {
7955                 intel_modeset_check_state(dev);
7956         }
7957
7958 out:
7959         kfree(pipe_config);
7960         kfree(saved_mode);
7961         return ret;
7962 }
7963
7964 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7965 {
7966         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7967 }
7968
7969 #undef for_each_intel_crtc_masked
7970
7971 static void intel_set_config_free(struct intel_set_config *config)
7972 {
7973         if (!config)
7974                 return;
7975
7976         kfree(config->save_connector_encoders);
7977         kfree(config->save_encoder_crtcs);
7978         kfree(config);
7979 }
7980
7981 static int intel_set_config_save_state(struct drm_device *dev,
7982                                        struct intel_set_config *config)
7983 {
7984         struct drm_encoder *encoder;
7985         struct drm_connector *connector;
7986         int count;
7987
7988         config->save_encoder_crtcs =
7989                 kcalloc(dev->mode_config.num_encoder,
7990                         sizeof(struct drm_crtc *), GFP_KERNEL);
7991         if (!config->save_encoder_crtcs)
7992                 return -ENOMEM;
7993
7994         config->save_connector_encoders =
7995                 kcalloc(dev->mode_config.num_connector,
7996                         sizeof(struct drm_encoder *), GFP_KERNEL);
7997         if (!config->save_connector_encoders)
7998                 return -ENOMEM;
7999
8000         /* Copy data. Note that driver private data is not affected.
8001          * Should anything bad happen only the expected state is
8002          * restored, not the drivers personal bookkeeping.
8003          */
8004         count = 0;
8005         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8006                 config->save_encoder_crtcs[count++] = encoder->crtc;
8007         }
8008
8009         count = 0;
8010         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8011                 config->save_connector_encoders[count++] = connector->encoder;
8012         }
8013
8014         return 0;
8015 }
8016
8017 static void intel_set_config_restore_state(struct drm_device *dev,
8018                                            struct intel_set_config *config)
8019 {
8020         struct intel_encoder *encoder;
8021         struct intel_connector *connector;
8022         int count;
8023
8024         count = 0;
8025         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8026                 encoder->new_crtc =
8027                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8028         }
8029
8030         count = 0;
8031         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8032                 connector->new_encoder =
8033                         to_intel_encoder(config->save_connector_encoders[count++]);
8034         }
8035 }
8036
8037 static void
8038 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8039                                       struct intel_set_config *config)
8040 {
8041
8042         /* We should be able to check here if the fb has the same properties
8043          * and then just flip_or_move it */
8044         if (set->crtc->fb != set->fb) {
8045                 /* If we have no fb then treat it as a full mode set */
8046                 if (set->crtc->fb == NULL) {
8047                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8048                         config->mode_changed = true;
8049                 } else if (set->fb == NULL) {
8050                         config->mode_changed = true;
8051                 } else if (set->fb->pixel_format !=
8052                            set->crtc->fb->pixel_format) {
8053                         config->mode_changed = true;
8054                 } else
8055                         config->fb_changed = true;
8056         }
8057
8058         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8059                 config->fb_changed = true;
8060
8061         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8062                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8063                 drm_mode_debug_printmodeline(&set->crtc->mode);
8064                 drm_mode_debug_printmodeline(set->mode);
8065                 config->mode_changed = true;
8066         }
8067 }
8068
8069 static int
8070 intel_modeset_stage_output_state(struct drm_device *dev,
8071                                  struct drm_mode_set *set,
8072                                  struct intel_set_config *config)
8073 {
8074         struct drm_crtc *new_crtc;
8075         struct intel_connector *connector;
8076         struct intel_encoder *encoder;
8077         int count, ro;
8078
8079         /* The upper layers ensure that we either disable a crtc or have a list
8080          * of connectors. For paranoia, double-check this. */
8081         WARN_ON(!set->fb && (set->num_connectors != 0));
8082         WARN_ON(set->fb && (set->num_connectors == 0));
8083
8084         count = 0;
8085         list_for_each_entry(connector, &dev->mode_config.connector_list,
8086                             base.head) {
8087                 /* Otherwise traverse passed in connector list and get encoders
8088                  * for them. */
8089                 for (ro = 0; ro < set->num_connectors; ro++) {
8090                         if (set->connectors[ro] == &connector->base) {
8091                                 connector->new_encoder = connector->encoder;
8092                                 break;
8093                         }
8094                 }
8095
8096                 /* If we disable the crtc, disable all its connectors. Also, if
8097                  * the connector is on the changing crtc but not on the new
8098                  * connector list, disable it. */
8099                 if ((!set->fb || ro == set->num_connectors) &&
8100                     connector->base.encoder &&
8101                     connector->base.encoder->crtc == set->crtc) {
8102                         connector->new_encoder = NULL;
8103
8104                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8105                                 connector->base.base.id,
8106                                 drm_get_connector_name(&connector->base));
8107                 }
8108
8109
8110                 if (&connector->new_encoder->base != connector->base.encoder) {
8111                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8112                         config->mode_changed = true;
8113                 }
8114         }
8115         /* connector->new_encoder is now updated for all connectors. */
8116
8117         /* Update crtc of enabled connectors. */
8118         count = 0;
8119         list_for_each_entry(connector, &dev->mode_config.connector_list,
8120                             base.head) {
8121                 if (!connector->new_encoder)
8122                         continue;
8123
8124                 new_crtc = connector->new_encoder->base.crtc;
8125
8126                 for (ro = 0; ro < set->num_connectors; ro++) {
8127                         if (set->connectors[ro] == &connector->base)
8128                                 new_crtc = set->crtc;
8129                 }
8130
8131                 /* Make sure the new CRTC will work with the encoder */
8132                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8133                                            new_crtc)) {
8134                         return -EINVAL;
8135                 }
8136                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8137
8138                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8139                         connector->base.base.id,
8140                         drm_get_connector_name(&connector->base),
8141                         new_crtc->base.id);
8142         }
8143
8144         /* Check for any encoders that needs to be disabled. */
8145         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8146                             base.head) {
8147                 list_for_each_entry(connector,
8148                                     &dev->mode_config.connector_list,
8149                                     base.head) {
8150                         if (connector->new_encoder == encoder) {
8151                                 WARN_ON(!connector->new_encoder->new_crtc);
8152
8153                                 goto next_encoder;
8154                         }
8155                 }
8156                 encoder->new_crtc = NULL;
8157 next_encoder:
8158                 /* Only now check for crtc changes so we don't miss encoders
8159                  * that will be disabled. */
8160                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8161                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8162                         config->mode_changed = true;
8163                 }
8164         }
8165         /* Now we've also updated encoder->new_crtc for all encoders. */
8166
8167         return 0;
8168 }
8169
8170 static int intel_crtc_set_config(struct drm_mode_set *set)
8171 {
8172         struct drm_device *dev;
8173         struct drm_mode_set save_set;
8174         struct intel_set_config *config;
8175         int ret;
8176
8177         BUG_ON(!set);
8178         BUG_ON(!set->crtc);
8179         BUG_ON(!set->crtc->helper_private);
8180
8181         /* Enforce sane interface api - has been abused by the fb helper. */
8182         BUG_ON(!set->mode && set->fb);
8183         BUG_ON(set->fb && set->num_connectors == 0);
8184
8185         if (set->fb) {
8186                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8187                                 set->crtc->base.id, set->fb->base.id,
8188                                 (int)set->num_connectors, set->x, set->y);
8189         } else {
8190                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8191         }
8192
8193         dev = set->crtc->dev;
8194
8195         ret = -ENOMEM;
8196         config = kzalloc(sizeof(*config), GFP_KERNEL);
8197         if (!config)
8198                 goto out_config;
8199
8200         ret = intel_set_config_save_state(dev, config);
8201         if (ret)
8202                 goto out_config;
8203
8204         save_set.crtc = set->crtc;
8205         save_set.mode = &set->crtc->mode;
8206         save_set.x = set->crtc->x;
8207         save_set.y = set->crtc->y;
8208         save_set.fb = set->crtc->fb;
8209
8210         /* Compute whether we need a full modeset, only an fb base update or no
8211          * change at all. In the future we might also check whether only the
8212          * mode changed, e.g. for LVDS where we only change the panel fitter in
8213          * such cases. */
8214         intel_set_config_compute_mode_changes(set, config);
8215
8216         ret = intel_modeset_stage_output_state(dev, set, config);
8217         if (ret)
8218                 goto fail;
8219
8220         if (config->mode_changed) {
8221                 if (set->mode) {
8222                         DRM_DEBUG_KMS("attempting to set mode from"
8223                                         " userspace\n");
8224                         drm_mode_debug_printmodeline(set->mode);
8225                 }
8226
8227                 ret = intel_set_mode(set->crtc, set->mode,
8228                                      set->x, set->y, set->fb);
8229                 if (ret) {
8230                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8231                                   set->crtc->base.id, ret);
8232                         goto fail;
8233                 }
8234         } else if (config->fb_changed) {
8235                 intel_crtc_wait_for_pending_flips(set->crtc);
8236
8237                 ret = intel_pipe_set_base(set->crtc,
8238                                           set->x, set->y, set->fb);
8239         }
8240
8241         intel_set_config_free(config);
8242
8243         return 0;
8244
8245 fail:
8246         intel_set_config_restore_state(dev, config);
8247
8248         /* Try to restore the config */
8249         if (config->mode_changed &&
8250             intel_set_mode(save_set.crtc, save_set.mode,
8251                            save_set.x, save_set.y, save_set.fb))
8252                 DRM_ERROR("failed to restore config after modeset failure\n");
8253
8254 out_config:
8255         intel_set_config_free(config);
8256         return ret;
8257 }
8258
8259 static const struct drm_crtc_funcs intel_crtc_funcs = {
8260         .cursor_set = intel_crtc_cursor_set,
8261         .cursor_move = intel_crtc_cursor_move,
8262         .gamma_set = intel_crtc_gamma_set,
8263         .set_config = intel_crtc_set_config,
8264         .destroy = intel_crtc_destroy,
8265         .page_flip = intel_crtc_page_flip,
8266 };
8267
8268 static void intel_cpu_pll_init(struct drm_device *dev)
8269 {
8270         if (HAS_DDI(dev))
8271                 intel_ddi_pll_init(dev);
8272 }
8273
8274 static void intel_pch_pll_init(struct drm_device *dev)
8275 {
8276         drm_i915_private_t *dev_priv = dev->dev_private;
8277         int i;
8278
8279         if (dev_priv->num_pch_pll == 0) {
8280                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8281                 return;
8282         }
8283
8284         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8285                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8286                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8287                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8288         }
8289 }
8290
8291 static void intel_crtc_init(struct drm_device *dev, int pipe)
8292 {
8293         drm_i915_private_t *dev_priv = dev->dev_private;
8294         struct intel_crtc *intel_crtc;
8295         int i;
8296
8297         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8298         if (intel_crtc == NULL)
8299                 return;
8300
8301         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8302
8303         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8304         for (i = 0; i < 256; i++) {
8305                 intel_crtc->lut_r[i] = i;
8306                 intel_crtc->lut_g[i] = i;
8307                 intel_crtc->lut_b[i] = i;
8308         }
8309
8310         /* Swap pipes & planes for FBC on pre-965 */
8311         intel_crtc->pipe = pipe;
8312         intel_crtc->plane = pipe;
8313         intel_crtc->cpu_transcoder = pipe;
8314         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8315                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8316                 intel_crtc->plane = !pipe;
8317         }
8318
8319         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8320                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8321         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8322         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8323
8324         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8325 }
8326
8327 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8328                                 struct drm_file *file)
8329 {
8330         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8331         struct drm_mode_object *drmmode_obj;
8332         struct intel_crtc *crtc;
8333
8334         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8335                 return -ENODEV;
8336
8337         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8338                         DRM_MODE_OBJECT_CRTC);
8339
8340         if (!drmmode_obj) {
8341                 DRM_ERROR("no such CRTC id\n");
8342                 return -EINVAL;
8343         }
8344
8345         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8346         pipe_from_crtc_id->pipe = crtc->pipe;
8347
8348         return 0;
8349 }
8350
8351 static int intel_encoder_clones(struct intel_encoder *encoder)
8352 {
8353         struct drm_device *dev = encoder->base.dev;
8354         struct intel_encoder *source_encoder;
8355         int index_mask = 0;
8356         int entry = 0;
8357
8358         list_for_each_entry(source_encoder,
8359                             &dev->mode_config.encoder_list, base.head) {
8360
8361                 if (encoder == source_encoder)
8362                         index_mask |= (1 << entry);
8363
8364                 /* Intel hw has only one MUX where enocoders could be cloned. */
8365                 if (encoder->cloneable && source_encoder->cloneable)
8366                         index_mask |= (1 << entry);
8367
8368                 entry++;
8369         }
8370
8371         return index_mask;
8372 }
8373
8374 static bool has_edp_a(struct drm_device *dev)
8375 {
8376         struct drm_i915_private *dev_priv = dev->dev_private;
8377
8378         if (!IS_MOBILE(dev))
8379                 return false;
8380
8381         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8382                 return false;
8383
8384         if (IS_GEN5(dev) &&
8385             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8386                 return false;
8387
8388         return true;
8389 }
8390
8391 static void intel_setup_outputs(struct drm_device *dev)
8392 {
8393         struct drm_i915_private *dev_priv = dev->dev_private;
8394         struct intel_encoder *encoder;
8395         bool dpd_is_edp = false;
8396         bool has_lvds;
8397
8398         has_lvds = intel_lvds_init(dev);
8399         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8400                 /* disable the panel fitter on everything but LVDS */
8401                 I915_WRITE(PFIT_CONTROL, 0);
8402         }
8403
8404         if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8405                 intel_crt_init(dev);
8406
8407         if (HAS_DDI(dev)) {
8408                 int found;
8409
8410                 /* Haswell uses DDI functions to detect digital outputs */
8411                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8412                 /* DDI A only supports eDP */
8413                 if (found)
8414                         intel_ddi_init(dev, PORT_A);
8415
8416                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8417                  * register */
8418                 found = I915_READ(SFUSE_STRAP);
8419
8420                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8421                         intel_ddi_init(dev, PORT_B);
8422                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8423                         intel_ddi_init(dev, PORT_C);
8424                 if (found & SFUSE_STRAP_DDID_DETECTED)
8425                         intel_ddi_init(dev, PORT_D);
8426         } else if (HAS_PCH_SPLIT(dev)) {
8427                 int found;
8428                 dpd_is_edp = intel_dpd_is_edp(dev);
8429
8430                 if (has_edp_a(dev))
8431                         intel_dp_init(dev, DP_A, PORT_A);
8432
8433                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8434                         /* PCH SDVOB multiplex with HDMIB */
8435                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8436                         if (!found)
8437                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8438                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8439                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8440                 }
8441
8442                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8443                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8444
8445                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8446                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8447
8448                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8449                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8450
8451                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8452                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8453         } else if (IS_VALLEYVIEW(dev)) {
8454                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8455                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8456                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8457
8458                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8459                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8460                                         PORT_B);
8461                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8462                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8463                 }
8464         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8465                 bool found = false;
8466
8467                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8468                         DRM_DEBUG_KMS("probing SDVOB\n");
8469                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8470                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8471                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8472                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8473                         }
8474
8475                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8476                                 DRM_DEBUG_KMS("probing DP_B\n");
8477                                 intel_dp_init(dev, DP_B, PORT_B);
8478                         }
8479                 }
8480
8481                 /* Before G4X SDVOC doesn't have its own detect register */
8482
8483                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8484                         DRM_DEBUG_KMS("probing SDVOC\n");
8485                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8486                 }
8487
8488                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8489
8490                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8491                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8492                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8493                         }
8494                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8495                                 DRM_DEBUG_KMS("probing DP_C\n");
8496                                 intel_dp_init(dev, DP_C, PORT_C);
8497                         }
8498                 }
8499
8500                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8501                     (I915_READ(DP_D) & DP_DETECTED)) {
8502                         DRM_DEBUG_KMS("probing DP_D\n");
8503                         intel_dp_init(dev, DP_D, PORT_D);
8504                 }
8505         } else if (IS_GEN2(dev))
8506                 intel_dvo_init(dev);
8507
8508         if (SUPPORTS_TV(dev))
8509                 intel_tv_init(dev);
8510
8511         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8512                 encoder->base.possible_crtcs = encoder->crtc_mask;
8513                 encoder->base.possible_clones =
8514                         intel_encoder_clones(encoder);
8515         }
8516
8517         intel_init_pch_refclk(dev);
8518
8519         drm_helper_move_panel_connectors_to_head(dev);
8520 }
8521
8522 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8523 {
8524         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8525
8526         drm_framebuffer_cleanup(fb);
8527         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8528
8529         kfree(intel_fb);
8530 }
8531
8532 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8533                                                 struct drm_file *file,
8534                                                 unsigned int *handle)
8535 {
8536         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8537         struct drm_i915_gem_object *obj = intel_fb->obj;
8538
8539         return drm_gem_handle_create(file, &obj->base, handle);
8540 }
8541
8542 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8543         .destroy = intel_user_framebuffer_destroy,
8544         .create_handle = intel_user_framebuffer_create_handle,
8545 };
8546
8547 int intel_framebuffer_init(struct drm_device *dev,
8548                            struct intel_framebuffer *intel_fb,
8549                            struct drm_mode_fb_cmd2 *mode_cmd,
8550                            struct drm_i915_gem_object *obj)
8551 {
8552         int ret;
8553
8554         if (obj->tiling_mode == I915_TILING_Y) {
8555                 DRM_DEBUG("hardware does not support tiling Y\n");
8556                 return -EINVAL;
8557         }
8558
8559         if (mode_cmd->pitches[0] & 63) {
8560                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8561                           mode_cmd->pitches[0]);
8562                 return -EINVAL;
8563         }
8564
8565         /* FIXME <= Gen4 stride limits are bit unclear */
8566         if (mode_cmd->pitches[0] > 32768) {
8567                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8568                           mode_cmd->pitches[0]);
8569                 return -EINVAL;
8570         }
8571
8572         if (obj->tiling_mode != I915_TILING_NONE &&
8573             mode_cmd->pitches[0] != obj->stride) {
8574                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8575                           mode_cmd->pitches[0], obj->stride);
8576                 return -EINVAL;
8577         }
8578
8579         /* Reject formats not supported by any plane early. */
8580         switch (mode_cmd->pixel_format) {
8581         case DRM_FORMAT_C8:
8582         case DRM_FORMAT_RGB565:
8583         case DRM_FORMAT_XRGB8888:
8584         case DRM_FORMAT_ARGB8888:
8585                 break;
8586         case DRM_FORMAT_XRGB1555:
8587         case DRM_FORMAT_ARGB1555:
8588                 if (INTEL_INFO(dev)->gen > 3) {
8589                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8590                         return -EINVAL;
8591                 }
8592                 break;
8593         case DRM_FORMAT_XBGR8888:
8594         case DRM_FORMAT_ABGR8888:
8595         case DRM_FORMAT_XRGB2101010:
8596         case DRM_FORMAT_ARGB2101010:
8597         case DRM_FORMAT_XBGR2101010:
8598         case DRM_FORMAT_ABGR2101010:
8599                 if (INTEL_INFO(dev)->gen < 4) {
8600                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8601                         return -EINVAL;
8602                 }
8603                 break;
8604         case DRM_FORMAT_YUYV:
8605         case DRM_FORMAT_UYVY:
8606         case DRM_FORMAT_YVYU:
8607         case DRM_FORMAT_VYUY:
8608                 if (INTEL_INFO(dev)->gen < 5) {
8609                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8610                         return -EINVAL;
8611                 }
8612                 break;
8613         default:
8614                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8615                 return -EINVAL;
8616         }
8617
8618         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8619         if (mode_cmd->offsets[0] != 0)
8620                 return -EINVAL;
8621
8622         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8623         intel_fb->obj = obj;
8624
8625         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8626         if (ret) {
8627                 DRM_ERROR("framebuffer init failed %d\n", ret);
8628                 return ret;
8629         }
8630
8631         return 0;
8632 }
8633
8634 static struct drm_framebuffer *
8635 intel_user_framebuffer_create(struct drm_device *dev,
8636                               struct drm_file *filp,
8637                               struct drm_mode_fb_cmd2 *mode_cmd)
8638 {
8639         struct drm_i915_gem_object *obj;
8640
8641         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8642                                                 mode_cmd->handles[0]));
8643         if (&obj->base == NULL)
8644                 return ERR_PTR(-ENOENT);
8645
8646         return intel_framebuffer_create(dev, mode_cmd, obj);
8647 }
8648
8649 static const struct drm_mode_config_funcs intel_mode_funcs = {
8650         .fb_create = intel_user_framebuffer_create,
8651         .output_poll_changed = intel_fb_output_poll_changed,
8652 };
8653
8654 /* Set up chip specific display functions */
8655 static void intel_init_display(struct drm_device *dev)
8656 {
8657         struct drm_i915_private *dev_priv = dev->dev_private;
8658
8659         if (HAS_DDI(dev)) {
8660                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8661                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8662                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8663                 dev_priv->display.off = haswell_crtc_off;
8664                 dev_priv->display.update_plane = ironlake_update_plane;
8665         } else if (HAS_PCH_SPLIT(dev)) {
8666                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8667                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8668                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8669                 dev_priv->display.off = ironlake_crtc_off;
8670                 dev_priv->display.update_plane = ironlake_update_plane;
8671         } else {
8672                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8673                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8674                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8675                 dev_priv->display.off = i9xx_crtc_off;
8676                 dev_priv->display.update_plane = i9xx_update_plane;
8677         }
8678
8679         /* Returns the core display clock speed */
8680         if (IS_VALLEYVIEW(dev))
8681                 dev_priv->display.get_display_clock_speed =
8682                         valleyview_get_display_clock_speed;
8683         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8684                 dev_priv->display.get_display_clock_speed =
8685                         i945_get_display_clock_speed;
8686         else if (IS_I915G(dev))
8687                 dev_priv->display.get_display_clock_speed =
8688                         i915_get_display_clock_speed;
8689         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8690                 dev_priv->display.get_display_clock_speed =
8691                         i9xx_misc_get_display_clock_speed;
8692         else if (IS_I915GM(dev))
8693                 dev_priv->display.get_display_clock_speed =
8694                         i915gm_get_display_clock_speed;
8695         else if (IS_I865G(dev))
8696                 dev_priv->display.get_display_clock_speed =
8697                         i865_get_display_clock_speed;
8698         else if (IS_I85X(dev))
8699                 dev_priv->display.get_display_clock_speed =
8700                         i855_get_display_clock_speed;
8701         else /* 852, 830 */
8702                 dev_priv->display.get_display_clock_speed =
8703                         i830_get_display_clock_speed;
8704
8705         if (HAS_PCH_SPLIT(dev)) {
8706                 if (IS_GEN5(dev)) {
8707                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8708                         dev_priv->display.write_eld = ironlake_write_eld;
8709                 } else if (IS_GEN6(dev)) {
8710                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8711                         dev_priv->display.write_eld = ironlake_write_eld;
8712                 } else if (IS_IVYBRIDGE(dev)) {
8713                         /* FIXME: detect B0+ stepping and use auto training */
8714                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8715                         dev_priv->display.write_eld = ironlake_write_eld;
8716                         dev_priv->display.modeset_global_resources =
8717                                 ivb_modeset_global_resources;
8718                 } else if (IS_HASWELL(dev)) {
8719                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8720                         dev_priv->display.write_eld = haswell_write_eld;
8721                         dev_priv->display.modeset_global_resources =
8722                                 haswell_modeset_global_resources;
8723                 }
8724         } else if (IS_G4X(dev)) {
8725                 dev_priv->display.write_eld = g4x_write_eld;
8726         }
8727
8728         /* Default just returns -ENODEV to indicate unsupported */
8729         dev_priv->display.queue_flip = intel_default_queue_flip;
8730
8731         switch (INTEL_INFO(dev)->gen) {
8732         case 2:
8733                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8734                 break;
8735
8736         case 3:
8737                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8738                 break;
8739
8740         case 4:
8741         case 5:
8742                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8743                 break;
8744
8745         case 6:
8746                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8747                 break;
8748         case 7:
8749                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8750                 break;
8751         }
8752 }
8753
8754 /*
8755  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8756  * resume, or other times.  This quirk makes sure that's the case for
8757  * affected systems.
8758  */
8759 static void quirk_pipea_force(struct drm_device *dev)
8760 {
8761         struct drm_i915_private *dev_priv = dev->dev_private;
8762
8763         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8764         DRM_INFO("applying pipe a force quirk\n");
8765 }
8766
8767 /*
8768  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8769  */
8770 static void quirk_ssc_force_disable(struct drm_device *dev)
8771 {
8772         struct drm_i915_private *dev_priv = dev->dev_private;
8773         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8774         DRM_INFO("applying lvds SSC disable quirk\n");
8775 }
8776
8777 /*
8778  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8779  * brightness value
8780  */
8781 static void quirk_invert_brightness(struct drm_device *dev)
8782 {
8783         struct drm_i915_private *dev_priv = dev->dev_private;
8784         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8785         DRM_INFO("applying inverted panel brightness quirk\n");
8786 }
8787
8788 struct intel_quirk {
8789         int device;
8790         int subsystem_vendor;
8791         int subsystem_device;
8792         void (*hook)(struct drm_device *dev);
8793 };
8794
8795 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8796 struct intel_dmi_quirk {
8797         void (*hook)(struct drm_device *dev);
8798         const struct dmi_system_id (*dmi_id_list)[];
8799 };
8800
8801 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8802 {
8803         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8804         return 1;
8805 }
8806
8807 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8808         {
8809                 .dmi_id_list = &(const struct dmi_system_id[]) {
8810                         {
8811                                 .callback = intel_dmi_reverse_brightness,
8812                                 .ident = "NCR Corporation",
8813                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8814                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8815                                 },
8816                         },
8817                         { }  /* terminating entry */
8818                 },
8819                 .hook = quirk_invert_brightness,
8820         },
8821 };
8822
8823 static struct intel_quirk intel_quirks[] = {
8824         /* HP Mini needs pipe A force quirk (LP: #322104) */
8825         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8826
8827         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8828         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8829
8830         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8831         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8832
8833         /* 830/845 need to leave pipe A & dpll A up */
8834         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8835         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8836
8837         /* Lenovo U160 cannot use SSC on LVDS */
8838         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8839
8840         /* Sony Vaio Y cannot use SSC on LVDS */
8841         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8842
8843         /* Acer Aspire 5734Z must invert backlight brightness */
8844         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8845
8846         /* Acer/eMachines G725 */
8847         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8848
8849         /* Acer/eMachines e725 */
8850         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8851
8852         /* Acer/Packard Bell NCL20 */
8853         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8854
8855         /* Acer Aspire 4736Z */
8856         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8857 };
8858
8859 static void intel_init_quirks(struct drm_device *dev)
8860 {
8861         struct pci_dev *d = dev->pdev;
8862         int i;
8863
8864         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8865                 struct intel_quirk *q = &intel_quirks[i];
8866
8867                 if (d->device == q->device &&
8868                     (d->subsystem_vendor == q->subsystem_vendor ||
8869                      q->subsystem_vendor == PCI_ANY_ID) &&
8870                     (d->subsystem_device == q->subsystem_device ||
8871                      q->subsystem_device == PCI_ANY_ID))
8872                         q->hook(dev);
8873         }
8874         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8875                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8876                         intel_dmi_quirks[i].hook(dev);
8877         }
8878 }
8879
8880 /* Disable the VGA plane that we never use */
8881 static void i915_disable_vga(struct drm_device *dev)
8882 {
8883         struct drm_i915_private *dev_priv = dev->dev_private;
8884         u8 sr1;
8885         u32 vga_reg = i915_vgacntrl_reg(dev);
8886
8887         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8888         outb(SR01, VGA_SR_INDEX);
8889         sr1 = inb(VGA_SR_DATA);
8890         outb(sr1 | 1<<5, VGA_SR_DATA);
8891         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8892         udelay(300);
8893
8894         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8895         POSTING_READ(vga_reg);
8896 }
8897
8898 void intel_modeset_init_hw(struct drm_device *dev)
8899 {
8900         intel_init_power_well(dev);
8901
8902         intel_prepare_ddi(dev);
8903
8904         intel_init_clock_gating(dev);
8905
8906         mutex_lock(&dev->struct_mutex);
8907         intel_enable_gt_powersave(dev);
8908         mutex_unlock(&dev->struct_mutex);
8909 }
8910
8911 void intel_modeset_init(struct drm_device *dev)
8912 {
8913         struct drm_i915_private *dev_priv = dev->dev_private;
8914         int i, j, ret;
8915
8916         drm_mode_config_init(dev);
8917
8918         dev->mode_config.min_width = 0;
8919         dev->mode_config.min_height = 0;
8920
8921         dev->mode_config.preferred_depth = 24;
8922         dev->mode_config.prefer_shadow = 1;
8923
8924         dev->mode_config.funcs = &intel_mode_funcs;
8925
8926         intel_init_quirks(dev);
8927
8928         intel_init_pm(dev);
8929
8930         intel_init_display(dev);
8931
8932         if (IS_GEN2(dev)) {
8933                 dev->mode_config.max_width = 2048;
8934                 dev->mode_config.max_height = 2048;
8935         } else if (IS_GEN3(dev)) {
8936                 dev->mode_config.max_width = 4096;
8937                 dev->mode_config.max_height = 4096;
8938         } else {
8939                 dev->mode_config.max_width = 8192;
8940                 dev->mode_config.max_height = 8192;
8941         }
8942         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8943
8944         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8945                       INTEL_INFO(dev)->num_pipes,
8946                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
8947
8948         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
8949                 intel_crtc_init(dev, i);
8950                 for (j = 0; j < dev_priv->num_plane; j++) {
8951                         ret = intel_plane_init(dev, i, j);
8952                         if (ret)
8953                                 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
8954                                               i, j, ret);
8955                 }
8956         }
8957
8958         intel_cpu_pll_init(dev);
8959         intel_pch_pll_init(dev);
8960
8961         /* Just disable it once at startup */
8962         i915_disable_vga(dev);
8963         intel_setup_outputs(dev);
8964
8965         /* Just in case the BIOS is doing something questionable. */
8966         intel_disable_fbc(dev);
8967 }
8968
8969 static void
8970 intel_connector_break_all_links(struct intel_connector *connector)
8971 {
8972         connector->base.dpms = DRM_MODE_DPMS_OFF;
8973         connector->base.encoder = NULL;
8974         connector->encoder->connectors_active = false;
8975         connector->encoder->base.crtc = NULL;
8976 }
8977
8978 static void intel_enable_pipe_a(struct drm_device *dev)
8979 {
8980         struct intel_connector *connector;
8981         struct drm_connector *crt = NULL;
8982         struct intel_load_detect_pipe load_detect_temp;
8983
8984         /* We can't just switch on the pipe A, we need to set things up with a
8985          * proper mode and output configuration. As a gross hack, enable pipe A
8986          * by enabling the load detect pipe once. */
8987         list_for_each_entry(connector,
8988                             &dev->mode_config.connector_list,
8989                             base.head) {
8990                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8991                         crt = &connector->base;
8992                         break;
8993                 }
8994         }
8995
8996         if (!crt)
8997                 return;
8998
8999         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9000                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9001
9002
9003 }
9004
9005 static bool
9006 intel_check_plane_mapping(struct intel_crtc *crtc)
9007 {
9008         struct drm_device *dev = crtc->base.dev;
9009         struct drm_i915_private *dev_priv = dev->dev_private;
9010         u32 reg, val;
9011
9012         if (INTEL_INFO(dev)->num_pipes == 1)
9013                 return true;
9014
9015         reg = DSPCNTR(!crtc->plane);
9016         val = I915_READ(reg);
9017
9018         if ((val & DISPLAY_PLANE_ENABLE) &&
9019             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9020                 return false;
9021
9022         return true;
9023 }
9024
9025 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9026 {
9027         struct drm_device *dev = crtc->base.dev;
9028         struct drm_i915_private *dev_priv = dev->dev_private;
9029         u32 reg;
9030
9031         /* Clear any frame start delays used for debugging left by the BIOS */
9032         reg = PIPECONF(crtc->cpu_transcoder);
9033         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9034
9035         /* We need to sanitize the plane -> pipe mapping first because this will
9036          * disable the crtc (and hence change the state) if it is wrong. Note
9037          * that gen4+ has a fixed plane -> pipe mapping.  */
9038         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9039                 struct intel_connector *connector;
9040                 bool plane;
9041
9042                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9043                               crtc->base.base.id);
9044
9045                 /* Pipe has the wrong plane attached and the plane is active.
9046                  * Temporarily change the plane mapping and disable everything
9047                  * ...  */
9048                 plane = crtc->plane;
9049                 crtc->plane = !plane;
9050                 dev_priv->display.crtc_disable(&crtc->base);
9051                 crtc->plane = plane;
9052
9053                 /* ... and break all links. */
9054                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9055                                     base.head) {
9056                         if (connector->encoder->base.crtc != &crtc->base)
9057                                 continue;
9058
9059                         intel_connector_break_all_links(connector);
9060                 }
9061
9062                 WARN_ON(crtc->active);
9063                 crtc->base.enabled = false;
9064         }
9065
9066         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9067             crtc->pipe == PIPE_A && !crtc->active) {
9068                 /* BIOS forgot to enable pipe A, this mostly happens after
9069                  * resume. Force-enable the pipe to fix this, the update_dpms
9070                  * call below we restore the pipe to the right state, but leave
9071                  * the required bits on. */
9072                 intel_enable_pipe_a(dev);
9073         }
9074
9075         /* Adjust the state of the output pipe according to whether we
9076          * have active connectors/encoders. */
9077         intel_crtc_update_dpms(&crtc->base);
9078
9079         if (crtc->active != crtc->base.enabled) {
9080                 struct intel_encoder *encoder;
9081
9082                 /* This can happen either due to bugs in the get_hw_state
9083                  * functions or because the pipe is force-enabled due to the
9084                  * pipe A quirk. */
9085                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9086                               crtc->base.base.id,
9087                               crtc->base.enabled ? "enabled" : "disabled",
9088                               crtc->active ? "enabled" : "disabled");
9089
9090                 crtc->base.enabled = crtc->active;
9091
9092                 /* Because we only establish the connector -> encoder ->
9093                  * crtc links if something is active, this means the
9094                  * crtc is now deactivated. Break the links. connector
9095                  * -> encoder links are only establish when things are
9096                  *  actually up, hence no need to break them. */
9097                 WARN_ON(crtc->active);
9098
9099                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9100                         WARN_ON(encoder->connectors_active);
9101                         encoder->base.crtc = NULL;
9102                 }
9103         }
9104 }
9105
9106 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9107 {
9108         struct intel_connector *connector;
9109         struct drm_device *dev = encoder->base.dev;
9110
9111         /* We need to check both for a crtc link (meaning that the
9112          * encoder is active and trying to read from a pipe) and the
9113          * pipe itself being active. */
9114         bool has_active_crtc = encoder->base.crtc &&
9115                 to_intel_crtc(encoder->base.crtc)->active;
9116
9117         if (encoder->connectors_active && !has_active_crtc) {
9118                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9119                               encoder->base.base.id,
9120                               drm_get_encoder_name(&encoder->base));
9121
9122                 /* Connector is active, but has no active pipe. This is
9123                  * fallout from our resume register restoring. Disable
9124                  * the encoder manually again. */
9125                 if (encoder->base.crtc) {
9126                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9127                                       encoder->base.base.id,
9128                                       drm_get_encoder_name(&encoder->base));
9129                         encoder->disable(encoder);
9130                 }
9131
9132                 /* Inconsistent output/port/pipe state happens presumably due to
9133                  * a bug in one of the get_hw_state functions. Or someplace else
9134                  * in our code, like the register restore mess on resume. Clamp
9135                  * things to off as a safer default. */
9136                 list_for_each_entry(connector,
9137                                     &dev->mode_config.connector_list,
9138                                     base.head) {
9139                         if (connector->encoder != encoder)
9140                                 continue;
9141
9142                         intel_connector_break_all_links(connector);
9143                 }
9144         }
9145         /* Enabled encoders without active connectors will be fixed in
9146          * the crtc fixup. */
9147 }
9148
9149 void i915_redisable_vga(struct drm_device *dev)
9150 {
9151         struct drm_i915_private *dev_priv = dev->dev_private;
9152         u32 vga_reg = i915_vgacntrl_reg(dev);
9153
9154         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9155                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9156                 i915_disable_vga(dev);
9157         }
9158 }
9159
9160 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9161  * and i915 state tracking structures. */
9162 void intel_modeset_setup_hw_state(struct drm_device *dev,
9163                                   bool force_restore)
9164 {
9165         struct drm_i915_private *dev_priv = dev->dev_private;
9166         enum pipe pipe;
9167         u32 tmp;
9168         struct drm_plane *plane;
9169         struct intel_crtc *crtc;
9170         struct intel_encoder *encoder;
9171         struct intel_connector *connector;
9172
9173         if (HAS_DDI(dev)) {
9174                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9175
9176                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9177                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9178                         case TRANS_DDI_EDP_INPUT_A_ON:
9179                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9180                                 pipe = PIPE_A;
9181                                 break;
9182                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9183                                 pipe = PIPE_B;
9184                                 break;
9185                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9186                                 pipe = PIPE_C;
9187                                 break;
9188                         default:
9189                                 /* A bogus value has been programmed, disable
9190                                  * the transcoder */
9191                                 WARN(1, "Bogus eDP source %08x\n", tmp);
9192                                 intel_ddi_disable_transcoder_func(dev_priv,
9193                                                 TRANSCODER_EDP);
9194                                 goto setup_pipes;
9195                         }
9196
9197                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9198                         crtc->cpu_transcoder = TRANSCODER_EDP;
9199
9200                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9201                                       pipe_name(pipe));
9202                 }
9203         }
9204
9205 setup_pipes:
9206         for_each_pipe(pipe) {
9207                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9208
9209                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9210                 if (tmp & PIPECONF_ENABLE)
9211                         crtc->active = true;
9212                 else
9213                         crtc->active = false;
9214
9215                 crtc->base.enabled = crtc->active;
9216
9217                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9218                               crtc->base.base.id,
9219                               crtc->active ? "enabled" : "disabled");
9220         }
9221
9222         if (HAS_DDI(dev))
9223                 intel_ddi_setup_hw_pll_state(dev);
9224
9225         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9226                             base.head) {
9227                 pipe = 0;
9228
9229                 if (encoder->get_hw_state(encoder, &pipe)) {
9230                         encoder->base.crtc =
9231                                 dev_priv->pipe_to_crtc_mapping[pipe];
9232                 } else {
9233                         encoder->base.crtc = NULL;
9234                 }
9235
9236                 encoder->connectors_active = false;
9237                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9238                               encoder->base.base.id,
9239                               drm_get_encoder_name(&encoder->base),
9240                               encoder->base.crtc ? "enabled" : "disabled",
9241                               pipe);
9242         }
9243
9244         list_for_each_entry(connector, &dev->mode_config.connector_list,
9245                             base.head) {
9246                 if (connector->get_hw_state(connector)) {
9247                         connector->base.dpms = DRM_MODE_DPMS_ON;
9248                         connector->encoder->connectors_active = true;
9249                         connector->base.encoder = &connector->encoder->base;
9250                 } else {
9251                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9252                         connector->base.encoder = NULL;
9253                 }
9254                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9255                               connector->base.base.id,
9256                               drm_get_connector_name(&connector->base),
9257                               connector->base.encoder ? "enabled" : "disabled");
9258         }
9259
9260         /* HW state is read out, now we need to sanitize this mess. */
9261         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9262                             base.head) {
9263                 intel_sanitize_encoder(encoder);
9264         }
9265
9266         for_each_pipe(pipe) {
9267                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9268                 intel_sanitize_crtc(crtc);
9269         }
9270
9271         if (force_restore) {
9272                 for_each_pipe(pipe) {
9273                         struct drm_crtc *crtc =
9274                                 dev_priv->pipe_to_crtc_mapping[pipe];
9275                         intel_crtc_restore_mode(crtc);
9276                 }
9277                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9278                         intel_plane_restore(plane);
9279
9280                 i915_redisable_vga(dev);
9281         } else {
9282                 intel_modeset_update_staged_output_state(dev);
9283         }
9284
9285         intel_modeset_check_state(dev);
9286
9287         drm_mode_config_reset(dev);
9288 }
9289
9290 void intel_modeset_gem_init(struct drm_device *dev)
9291 {
9292         intel_modeset_init_hw(dev);
9293
9294         intel_setup_overlay(dev);
9295
9296         intel_modeset_setup_hw_state(dev, false);
9297 }
9298
9299 void intel_modeset_cleanup(struct drm_device *dev)
9300 {
9301         struct drm_i915_private *dev_priv = dev->dev_private;
9302         struct drm_crtc *crtc;
9303         struct intel_crtc *intel_crtc;
9304
9305         drm_kms_helper_poll_fini(dev);
9306         mutex_lock(&dev->struct_mutex);
9307
9308         intel_unregister_dsm_handler();
9309
9310
9311         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9312                 /* Skip inactive CRTCs */
9313                 if (!crtc->fb)
9314                         continue;
9315
9316                 intel_crtc = to_intel_crtc(crtc);
9317                 intel_increase_pllclock(crtc);
9318         }
9319
9320         intel_disable_fbc(dev);
9321
9322         intel_disable_gt_powersave(dev);
9323
9324         ironlake_teardown_rc6(dev);
9325
9326         if (IS_VALLEYVIEW(dev))
9327                 vlv_init_dpio(dev);
9328
9329         mutex_unlock(&dev->struct_mutex);
9330
9331         /* Disable the irq before mode object teardown, for the irq might
9332          * enqueue unpin/hotplug work. */
9333         drm_irq_uninstall(dev);
9334         cancel_work_sync(&dev_priv->hotplug_work);
9335         cancel_work_sync(&dev_priv->rps.work);
9336
9337         /* flush any delayed tasks or pending work */
9338         flush_scheduled_work();
9339
9340         drm_mode_config_cleanup(dev);
9341
9342         intel_cleanup_overlay(dev);
9343 }
9344
9345 /*
9346  * Return which encoder is currently attached for connector.
9347  */
9348 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9349 {
9350         return &intel_attached_encoder(connector)->base;
9351 }
9352
9353 void intel_connector_attach_encoder(struct intel_connector *connector,
9354                                     struct intel_encoder *encoder)
9355 {
9356         connector->encoder = encoder;
9357         drm_mode_connector_attach_encoder(&connector->base,
9358                                           &encoder->base);
9359 }
9360
9361 /*
9362  * set vga decode state - true == enable VGA decode
9363  */
9364 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9365 {
9366         struct drm_i915_private *dev_priv = dev->dev_private;
9367         u16 gmch_ctrl;
9368
9369         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9370         if (state)
9371                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9372         else
9373                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9374         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9375         return 0;
9376 }
9377
9378 #ifdef CONFIG_DEBUG_FS
9379 #include <linux/seq_file.h>
9380
9381 struct intel_display_error_state {
9382         struct intel_cursor_error_state {
9383                 u32 control;
9384                 u32 position;
9385                 u32 base;
9386                 u32 size;
9387         } cursor[I915_MAX_PIPES];
9388
9389         struct intel_pipe_error_state {
9390                 u32 conf;
9391                 u32 source;
9392
9393                 u32 htotal;
9394                 u32 hblank;
9395                 u32 hsync;
9396                 u32 vtotal;
9397                 u32 vblank;
9398                 u32 vsync;
9399         } pipe[I915_MAX_PIPES];
9400
9401         struct intel_plane_error_state {
9402                 u32 control;
9403                 u32 stride;
9404                 u32 size;
9405                 u32 pos;
9406                 u32 addr;
9407                 u32 surface;
9408                 u32 tile_offset;
9409         } plane[I915_MAX_PIPES];
9410 };
9411
9412 struct intel_display_error_state *
9413 intel_display_capture_error_state(struct drm_device *dev)
9414 {
9415         drm_i915_private_t *dev_priv = dev->dev_private;
9416         struct intel_display_error_state *error;
9417         enum transcoder cpu_transcoder;
9418         int i;
9419
9420         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9421         if (error == NULL)
9422                 return NULL;
9423
9424         for_each_pipe(i) {
9425                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9426
9427                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9428                         error->cursor[i].control = I915_READ(CURCNTR(i));
9429                         error->cursor[i].position = I915_READ(CURPOS(i));
9430                         error->cursor[i].base = I915_READ(CURBASE(i));
9431                 } else {
9432                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9433                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9434                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9435                 }
9436
9437                 error->plane[i].control = I915_READ(DSPCNTR(i));
9438                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9439                 if (INTEL_INFO(dev)->gen <= 3) {
9440                         error->plane[i].size = I915_READ(DSPSIZE(i));
9441                         error->plane[i].pos = I915_READ(DSPPOS(i));
9442                 }
9443                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9444                         error->plane[i].addr = I915_READ(DSPADDR(i));
9445                 if (INTEL_INFO(dev)->gen >= 4) {
9446                         error->plane[i].surface = I915_READ(DSPSURF(i));
9447                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9448                 }
9449
9450                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9451                 error->pipe[i].source = I915_READ(PIPESRC(i));
9452                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9453                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9454                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9455                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9456                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9457                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9458         }
9459
9460         return error;
9461 }
9462
9463 void
9464 intel_display_print_error_state(struct seq_file *m,
9465                                 struct drm_device *dev,
9466                                 struct intel_display_error_state *error)
9467 {
9468         int i;
9469
9470         seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9471         for_each_pipe(i) {
9472                 seq_printf(m, "Pipe [%d]:\n", i);
9473                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9474                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9475                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9476                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9477                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9478                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9479                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9480                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9481
9482                 seq_printf(m, "Plane [%d]:\n", i);
9483                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9484                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9485                 if (INTEL_INFO(dev)->gen <= 3) {
9486                         seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9487                         seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9488                 }
9489                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9490                         seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9491                 if (INTEL_INFO(dev)->gen >= 4) {
9492                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9493                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9494                 }
9495
9496                 seq_printf(m, "Cursor [%d]:\n", i);
9497                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9498                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9499                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9500         }
9501 }
9502 #endif