2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
72 static const uint32_t intel_cursor_formats[] = {
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
79 static void intel_increase_pllclock(struct drm_device *dev,
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void intel_dp_set_m_n(struct intel_crtc *crtc);
95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
104 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 if (!connector->mst_port)
107 return connector->encoder;
109 return &connector->mst_port->mst_encoders[pipe]->base;
118 int p2_slow, p2_fast;
121 typedef struct intel_limit intel_limit_t;
123 intel_range_t dot, vco, n, m, m1, m2, p, p1;
128 intel_pch_rawclk(struct drm_device *dev)
130 struct drm_i915_private *dev_priv = dev->dev_private;
132 WARN_ON(!HAS_PCH_SPLIT(dev));
134 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
137 static inline u32 /* units of 100MHz */
138 intel_fdi_link_freq(struct drm_device *dev)
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
147 static const intel_limit_t intel_limits_i8xx_dac = {
148 .dot = { .min = 25000, .max = 350000 },
149 .vco = { .min = 908000, .max = 1512000 },
150 .n = { .min = 2, .max = 16 },
151 .m = { .min = 96, .max = 140 },
152 .m1 = { .min = 18, .max = 26 },
153 .m2 = { .min = 6, .max = 16 },
154 .p = { .min = 4, .max = 128 },
155 .p1 = { .min = 2, .max = 33 },
156 .p2 = { .dot_limit = 165000,
157 .p2_slow = 4, .p2_fast = 2 },
160 static const intel_limit_t intel_limits_i8xx_dvo = {
161 .dot = { .min = 25000, .max = 350000 },
162 .vco = { .min = 908000, .max = 1512000 },
163 .n = { .min = 2, .max = 16 },
164 .m = { .min = 96, .max = 140 },
165 .m1 = { .min = 18, .max = 26 },
166 .m2 = { .min = 6, .max = 16 },
167 .p = { .min = 4, .max = 128 },
168 .p1 = { .min = 2, .max = 33 },
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 4, .p2_fast = 4 },
173 static const intel_limit_t intel_limits_i8xx_lvds = {
174 .dot = { .min = 25000, .max = 350000 },
175 .vco = { .min = 908000, .max = 1512000 },
176 .n = { .min = 2, .max = 16 },
177 .m = { .min = 96, .max = 140 },
178 .m1 = { .min = 18, .max = 26 },
179 .m2 = { .min = 6, .max = 16 },
180 .p = { .min = 4, .max = 128 },
181 .p1 = { .min = 1, .max = 6 },
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 14, .p2_fast = 7 },
186 static const intel_limit_t intel_limits_i9xx_sdvo = {
187 .dot = { .min = 20000, .max = 400000 },
188 .vco = { .min = 1400000, .max = 2800000 },
189 .n = { .min = 1, .max = 6 },
190 .m = { .min = 70, .max = 120 },
191 .m1 = { .min = 8, .max = 18 },
192 .m2 = { .min = 3, .max = 7 },
193 .p = { .min = 5, .max = 80 },
194 .p1 = { .min = 1, .max = 8 },
195 .p2 = { .dot_limit = 200000,
196 .p2_slow = 10, .p2_fast = 5 },
199 static const intel_limit_t intel_limits_i9xx_lvds = {
200 .dot = { .min = 20000, .max = 400000 },
201 .vco = { .min = 1400000, .max = 2800000 },
202 .n = { .min = 1, .max = 6 },
203 .m = { .min = 70, .max = 120 },
204 .m1 = { .min = 8, .max = 18 },
205 .m2 = { .min = 3, .max = 7 },
206 .p = { .min = 7, .max = 98 },
207 .p1 = { .min = 1, .max = 8 },
208 .p2 = { .dot_limit = 112000,
209 .p2_slow = 14, .p2_fast = 7 },
213 static const intel_limit_t intel_limits_g4x_sdvo = {
214 .dot = { .min = 25000, .max = 270000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 10, .max = 30 },
221 .p1 = { .min = 1, .max = 3},
222 .p2 = { .dot_limit = 270000,
228 static const intel_limit_t intel_limits_g4x_hdmi = {
229 .dot = { .min = 22000, .max = 400000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 4 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 16, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 5, .max = 80 },
236 .p1 = { .min = 1, .max = 8},
237 .p2 = { .dot_limit = 165000,
238 .p2_slow = 10, .p2_fast = 5 },
241 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
242 .dot = { .min = 20000, .max = 115000 },
243 .vco = { .min = 1750000, .max = 3500000 },
244 .n = { .min = 1, .max = 3 },
245 .m = { .min = 104, .max = 138 },
246 .m1 = { .min = 17, .max = 23 },
247 .m2 = { .min = 5, .max = 11 },
248 .p = { .min = 28, .max = 112 },
249 .p1 = { .min = 2, .max = 8 },
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 14, .p2_fast = 14
255 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
256 .dot = { .min = 80000, .max = 224000 },
257 .vco = { .min = 1750000, .max = 3500000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 104, .max = 138 },
260 .m1 = { .min = 17, .max = 23 },
261 .m2 = { .min = 5, .max = 11 },
262 .p = { .min = 14, .max = 42 },
263 .p1 = { .min = 2, .max = 6 },
264 .p2 = { .dot_limit = 0,
265 .p2_slow = 7, .p2_fast = 7
269 static const intel_limit_t intel_limits_pineview_sdvo = {
270 .dot = { .min = 20000, .max = 400000},
271 .vco = { .min = 1700000, .max = 3500000 },
272 /* Pineview's Ncounter is a ring counter */
273 .n = { .min = 3, .max = 6 },
274 .m = { .min = 2, .max = 256 },
275 /* Pineview only has one combined m divider, which we treat as m2. */
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 200000,
281 .p2_slow = 10, .p2_fast = 5 },
284 static const intel_limit_t intel_limits_pineview_lvds = {
285 .dot = { .min = 20000, .max = 400000 },
286 .vco = { .min = 1700000, .max = 3500000 },
287 .n = { .min = 3, .max = 6 },
288 .m = { .min = 2, .max = 256 },
289 .m1 = { .min = 0, .max = 0 },
290 .m2 = { .min = 0, .max = 254 },
291 .p = { .min = 7, .max = 112 },
292 .p1 = { .min = 1, .max = 8 },
293 .p2 = { .dot_limit = 112000,
294 .p2_slow = 14, .p2_fast = 14 },
297 /* Ironlake / Sandybridge
299 * We calculate clock using (register_value + 2) for N/M1/M2, so here
300 * the range value for them is (actual_value - 2).
302 static const intel_limit_t intel_limits_ironlake_dac = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 5 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 10, .p2_fast = 5 },
315 static const intel_limit_t intel_limits_ironlake_single_lvds = {
316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 3 },
319 .m = { .min = 79, .max = 118 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2, .max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
328 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 127 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 56 },
336 .p1 = { .min = 2, .max = 8 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
341 /* LVDS 100mhz refclk limits. */
342 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
343 .dot = { .min = 25000, .max = 350000 },
344 .vco = { .min = 1760000, .max = 3510000 },
345 .n = { .min = 1, .max = 2 },
346 .m = { .min = 79, .max = 126 },
347 .m1 = { .min = 12, .max = 22 },
348 .m2 = { .min = 5, .max = 9 },
349 .p = { .min = 28, .max = 112 },
350 .p1 = { .min = 2, .max = 8 },
351 .p2 = { .dot_limit = 225000,
352 .p2_slow = 14, .p2_fast = 14 },
355 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
356 .dot = { .min = 25000, .max = 350000 },
357 .vco = { .min = 1760000, .max = 3510000 },
358 .n = { .min = 1, .max = 3 },
359 .m = { .min = 79, .max = 126 },
360 .m1 = { .min = 12, .max = 22 },
361 .m2 = { .min = 5, .max = 9 },
362 .p = { .min = 14, .max = 42 },
363 .p1 = { .min = 2, .max = 6 },
364 .p2 = { .dot_limit = 225000,
365 .p2_slow = 7, .p2_fast = 7 },
368 static const intel_limit_t intel_limits_vlv = {
370 * These are the data rate limits (measured in fast clocks)
371 * since those are the strictest limits we have. The fast
372 * clock and actual rate limits are more relaxed, so checking
373 * them would make no difference.
375 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
376 .vco = { .min = 4000000, .max = 6000000 },
377 .n = { .min = 1, .max = 7 },
378 .m1 = { .min = 2, .max = 3 },
379 .m2 = { .min = 11, .max = 156 },
380 .p1 = { .min = 2, .max = 3 },
381 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
384 static const intel_limit_t intel_limits_chv = {
386 * These are the data rate limits (measured in fast clocks)
387 * since those are the strictest limits we have. The fast
388 * clock and actual rate limits are more relaxed, so checking
389 * them would make no difference.
391 .dot = { .min = 25000 * 5, .max = 540000 * 5},
392 .vco = { .min = 4860000, .max = 6700000 },
393 .n = { .min = 1, .max = 1 },
394 .m1 = { .min = 2, .max = 2 },
395 .m2 = { .min = 24 << 22, .max = 175 << 22 },
396 .p1 = { .min = 2, .max = 4 },
397 .p2 = { .p2_slow = 1, .p2_fast = 14 },
400 static void vlv_clock(int refclk, intel_clock_t *clock)
402 clock->m = clock->m1 * clock->m2;
403 clock->p = clock->p1 * clock->p2;
404 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
407 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
411 * Returns whether any output on the specified pipe is of the specified type
413 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 struct drm_device *dev = crtc->dev;
416 struct intel_encoder *encoder;
418 for_each_encoder_on_crtc(dev, crtc, encoder)
419 if (encoder->type == type)
425 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
428 struct drm_device *dev = crtc->dev;
429 const intel_limit_t *limit;
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
432 if (intel_is_dual_link_lvds(dev)) {
433 if (refclk == 100000)
434 limit = &intel_limits_ironlake_dual_lvds_100m;
436 limit = &intel_limits_ironlake_dual_lvds;
438 if (refclk == 100000)
439 limit = &intel_limits_ironlake_single_lvds_100m;
441 limit = &intel_limits_ironlake_single_lvds;
444 limit = &intel_limits_ironlake_dac;
449 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 struct drm_device *dev = crtc->dev;
452 const intel_limit_t *limit;
454 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
455 if (intel_is_dual_link_lvds(dev))
456 limit = &intel_limits_g4x_dual_channel_lvds;
458 limit = &intel_limits_g4x_single_channel_lvds;
459 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
460 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
461 limit = &intel_limits_g4x_hdmi;
462 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
463 limit = &intel_limits_g4x_sdvo;
464 } else /* The option is for other outputs */
465 limit = &intel_limits_i9xx_sdvo;
470 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 struct drm_device *dev = crtc->dev;
473 const intel_limit_t *limit;
475 if (HAS_PCH_SPLIT(dev))
476 limit = intel_ironlake_limit(crtc, refclk);
477 else if (IS_G4X(dev)) {
478 limit = intel_g4x_limit(crtc);
479 } else if (IS_PINEVIEW(dev)) {
480 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
481 limit = &intel_limits_pineview_lvds;
483 limit = &intel_limits_pineview_sdvo;
484 } else if (IS_CHERRYVIEW(dev)) {
485 limit = &intel_limits_chv;
486 } else if (IS_VALLEYVIEW(dev)) {
487 limit = &intel_limits_vlv;
488 } else if (!IS_GEN2(dev)) {
489 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
490 limit = &intel_limits_i9xx_lvds;
492 limit = &intel_limits_i9xx_sdvo;
494 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
495 limit = &intel_limits_i8xx_lvds;
496 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
497 limit = &intel_limits_i8xx_dvo;
499 limit = &intel_limits_i8xx_dac;
504 /* m1 is reserved as 0 in Pineview, n is a ring counter */
505 static void pineview_clock(int refclk, intel_clock_t *clock)
507 clock->m = clock->m2 + 2;
508 clock->p = clock->p1 * clock->p2;
509 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
512 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
515 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
520 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 clock->m = i9xx_dpll_compute_m(clock);
523 clock->p = clock->p1 * clock->p2;
524 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
527 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
530 static void chv_clock(int refclk, intel_clock_t *clock)
532 clock->m = clock->m1 * clock->m2;
533 clock->p = clock->p1 * clock->p2;
534 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
541 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 * Returns whether the given set of divisors are valid for a given refclk with
544 * the given connectors.
547 static bool intel_PLL_is_valid(struct drm_device *dev,
548 const intel_limit_t *limit,
549 const intel_clock_t *clock)
551 if (clock->n < limit->n.min || limit->n.max < clock->n)
552 INTELPllInvalid("n out of range\n");
553 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
554 INTELPllInvalid("p1 out of range\n");
555 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
556 INTELPllInvalid("m2 out of range\n");
557 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
558 INTELPllInvalid("m1 out of range\n");
560 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
561 if (clock->m1 <= clock->m2)
562 INTELPllInvalid("m1 <= m2\n");
564 if (!IS_VALLEYVIEW(dev)) {
565 if (clock->p < limit->p.min || limit->p.max < clock->p)
566 INTELPllInvalid("p out of range\n");
567 if (clock->m < limit->m.min || limit->m.max < clock->m)
568 INTELPllInvalid("m out of range\n");
571 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
572 INTELPllInvalid("vco out of range\n");
573 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
574 * connector, etc., rather than just a single range.
576 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
577 INTELPllInvalid("dot out of range\n");
583 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
584 int target, int refclk, intel_clock_t *match_clock,
585 intel_clock_t *best_clock)
587 struct drm_device *dev = crtc->dev;
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 * For LVDS just rely on its current settings for dual-channel.
594 * We haven't figured out how to reliably set up different
595 * single/dual channel state, if we even can.
597 if (intel_is_dual_link_lvds(dev))
598 clock.p2 = limit->p2.p2_fast;
600 clock.p2 = limit->p2.p2_slow;
602 if (target < limit->p2.dot_limit)
603 clock.p2 = limit->p2.p2_slow;
605 clock.p2 = limit->p2.p2_fast;
608 memset(best_clock, 0, sizeof(*best_clock));
610 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 for (clock.m2 = limit->m2.min;
613 clock.m2 <= limit->m2.max; clock.m2++) {
614 if (clock.m2 >= clock.m1)
616 for (clock.n = limit->n.min;
617 clock.n <= limit->n.max; clock.n++) {
618 for (clock.p1 = limit->p1.min;
619 clock.p1 <= limit->p1.max; clock.p1++) {
622 i9xx_clock(refclk, &clock);
623 if (!intel_PLL_is_valid(dev, limit,
627 clock.p != match_clock->p)
630 this_err = abs(clock.dot - target);
631 if (this_err < err) {
640 return (err != target);
644 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *match_clock,
646 intel_clock_t *best_clock)
648 struct drm_device *dev = crtc->dev;
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
658 if (intel_is_dual_link_lvds(dev))
659 clock.p2 = limit->p2.p2_fast;
661 clock.p2 = limit->p2.p2_slow;
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
666 clock.p2 = limit->p2.p2_fast;
669 memset(best_clock, 0, sizeof(*best_clock));
671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
675 for (clock.n = limit->n.min;
676 clock.n <= limit->n.max; clock.n++) {
677 for (clock.p1 = limit->p1.min;
678 clock.p1 <= limit->p1.max; clock.p1++) {
681 pineview_clock(refclk, &clock);
682 if (!intel_PLL_is_valid(dev, limit,
686 clock.p != match_clock->p)
689 this_err = abs(clock.dot - target);
690 if (this_err < err) {
699 return (err != target);
703 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
704 int target, int refclk, intel_clock_t *match_clock,
705 intel_clock_t *best_clock)
707 struct drm_device *dev = crtc->dev;
711 /* approximately equals target * 0.00585 */
712 int err_most = (target >> 8) + (target >> 9);
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
716 if (intel_is_dual_link_lvds(dev))
717 clock.p2 = limit->p2.p2_fast;
719 clock.p2 = limit->p2.p2_slow;
721 if (target < limit->p2.dot_limit)
722 clock.p2 = limit->p2.p2_slow;
724 clock.p2 = limit->p2.p2_fast;
727 memset(best_clock, 0, sizeof(*best_clock));
728 max_n = limit->n.max;
729 /* based on hardware requirement, prefer smaller n to precision */
730 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
731 /* based on hardware requirement, prefere larger m1,m2 */
732 for (clock.m1 = limit->m1.max;
733 clock.m1 >= limit->m1.min; clock.m1--) {
734 for (clock.m2 = limit->m2.max;
735 clock.m2 >= limit->m2.min; clock.m2--) {
736 for (clock.p1 = limit->p1.max;
737 clock.p1 >= limit->p1.min; clock.p1--) {
740 i9xx_clock(refclk, &clock);
741 if (!intel_PLL_is_valid(dev, limit,
745 this_err = abs(clock.dot - target);
746 if (this_err < err_most) {
760 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
761 int target, int refclk, intel_clock_t *match_clock,
762 intel_clock_t *best_clock)
764 struct drm_device *dev = crtc->dev;
766 unsigned int bestppm = 1000000;
767 /* min update 19.2 MHz */
768 int max_n = min(limit->n.max, refclk / 19200);
771 target *= 5; /* fast clock */
773 memset(best_clock, 0, sizeof(*best_clock));
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
778 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
779 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
780 clock.p = clock.p1 * clock.p2;
781 /* based on hardware requirement, prefer bigger m1,m2 values */
782 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
783 unsigned int ppm, diff;
785 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
788 vlv_clock(refclk, &clock);
790 if (!intel_PLL_is_valid(dev, limit,
794 diff = abs(clock.dot - target);
795 ppm = div_u64(1000000ULL * diff, target);
797 if (ppm < 100 && clock.p > best_clock->p) {
803 if (bestppm >= 10 && ppm < bestppm - 10) {
817 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
821 struct drm_device *dev = crtc->dev;
826 memset(best_clock, 0, sizeof(*best_clock));
829 * Based on hardware doc, the n always set to 1, and m1 always
830 * set to 2. If requires to support 200Mhz refclk, we need to
831 * revisit this because n may not 1 anymore.
833 clock.n = 1, clock.m1 = 2;
834 target *= 5; /* fast clock */
836 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
837 for (clock.p2 = limit->p2.p2_fast;
838 clock.p2 >= limit->p2.p2_slow;
839 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841 clock.p = clock.p1 * clock.p2;
843 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
844 clock.n) << 22, refclk * clock.m1);
846 if (m2 > INT_MAX/clock.m1)
851 chv_clock(refclk, &clock);
853 if (!intel_PLL_is_valid(dev, limit, &clock))
856 /* based on hardware requirement, prefer bigger p
858 if (clock.p > best_clock->p) {
868 bool intel_crtc_active(struct drm_crtc *crtc)
870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872 /* Be paranoid as we can arrive here with only partial
873 * state retrieved from the hardware during setup.
875 * We can ditch the adjusted_mode.crtc_clock check as soon
876 * as Haswell has gained clock readout/fastboot support.
878 * We can ditch the crtc->primary->fb check as soon as we can
879 * properly reconstruct framebuffers.
881 return intel_crtc->active && crtc->primary->fb &&
882 intel_crtc->config.adjusted_mode.crtc_clock;
885 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
888 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891 return intel_crtc->config.cpu_transcoder;
894 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
896 struct drm_i915_private *dev_priv = dev->dev_private;
897 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
899 frame = I915_READ(frame_reg);
901 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
902 WARN(1, "vblank wait timed out\n");
906 * intel_wait_for_vblank - wait for vblank on a given pipe
908 * @pipe: pipe to wait for
910 * Wait for vblank to occur on a given pipe. Needed for various bits of
913 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 int pipestat_reg = PIPESTAT(pipe);
918 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
919 g4x_wait_for_vblank(dev, pipe);
923 /* Clear existing vblank status. Note this will clear any other
924 * sticky status fields as well.
926 * This races with i915_driver_irq_handler() with the result
927 * that either function could miss a vblank event. Here it is not
928 * fatal, as we will either wait upon the next vblank interrupt or
929 * timeout. Generally speaking intel_wait_for_vblank() is only
930 * called during modeset at which time the GPU should be idle and
931 * should *not* be performing page flips and thus not waiting on
933 * Currently, the result of us stealing a vblank from the irq
934 * handler is that a single frame will be skipped during swapbuffers.
936 I915_WRITE(pipestat_reg,
937 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
939 /* Wait for vblank interrupt bit to set */
940 if (wait_for(I915_READ(pipestat_reg) &
941 PIPE_VBLANK_INTERRUPT_STATUS,
943 DRM_DEBUG_KMS("vblank wait timed out\n");
946 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 u32 reg = PIPEDSL(pipe);
954 line_mask = DSL_LINEMASK_GEN2;
956 line_mask = DSL_LINEMASK_GEN3;
958 line1 = I915_READ(reg) & line_mask;
960 line2 = I915_READ(reg) & line_mask;
962 return line1 == line2;
966 * intel_wait_for_pipe_off - wait for pipe to turn off
968 * @pipe: pipe to wait for
970 * After disabling a pipe, we can't wait for vblank in the usual way,
971 * spinning on the vblank interrupt status bit, since we won't actually
972 * see an interrupt when the pipe is disabled.
975 * wait for the pipe register state bit to turn off
978 * wait for the display line value to settle (it usually
979 * ends up stopping at the start of the next frame).
982 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
988 if (INTEL_INFO(dev)->gen >= 4) {
989 int reg = PIPECONF(cpu_transcoder);
991 /* Wait for the Pipe State to go off */
992 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
994 WARN(1, "pipe_off wait timed out\n");
996 /* Wait for the display line to settle */
997 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
998 WARN(1, "pipe_off wait timed out\n");
1003 * ibx_digital_port_connected - is the specified port connected?
1004 * @dev_priv: i915 private structure
1005 * @port: the port to test
1007 * Returns true if @port is connected, false otherwise.
1009 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1010 struct intel_digital_port *port)
1014 if (HAS_PCH_IBX(dev_priv->dev)) {
1015 switch (port->port) {
1017 bit = SDE_PORTB_HOTPLUG;
1020 bit = SDE_PORTC_HOTPLUG;
1023 bit = SDE_PORTD_HOTPLUG;
1029 switch (port->port) {
1031 bit = SDE_PORTB_HOTPLUG_CPT;
1034 bit = SDE_PORTC_HOTPLUG_CPT;
1037 bit = SDE_PORTD_HOTPLUG_CPT;
1044 return I915_READ(SDEISR) & bit;
1047 static const char *state_string(bool enabled)
1049 return enabled ? "on" : "off";
1052 /* Only for pre-ILK configs */
1053 void assert_pll(struct drm_i915_private *dev_priv,
1054 enum pipe pipe, bool state)
1061 val = I915_READ(reg);
1062 cur_state = !!(val & DPLL_VCO_ENABLE);
1063 WARN(cur_state != state,
1064 "PLL state assertion failure (expected %s, current %s)\n",
1065 state_string(state), state_string(cur_state));
1068 /* XXX: the dsi pll is shared between MIPI DSI ports */
1069 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1074 mutex_lock(&dev_priv->dpio_lock);
1075 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1076 mutex_unlock(&dev_priv->dpio_lock);
1078 cur_state = val & DSI_PLL_VCO_EN;
1079 WARN(cur_state != state,
1080 "DSI PLL state assertion failure (expected %s, current %s)\n",
1081 state_string(state), state_string(cur_state));
1083 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1084 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1086 struct intel_shared_dpll *
1087 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1089 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1091 if (crtc->config.shared_dpll < 0)
1094 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1098 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1099 struct intel_shared_dpll *pll,
1103 struct intel_dpll_hw_state hw_state;
1106 "asserting DPLL %s with no DPLL\n", state_string(state)))
1109 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1110 WARN(cur_state != state,
1111 "%s assertion failure (expected %s, current %s)\n",
1112 pll->name, state_string(state), state_string(cur_state));
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1164 /* ILK FDI PLL is always enabled */
1165 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv->dev))
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1184 reg = FDI_RX_CTL(pipe);
1185 val = I915_READ(reg);
1186 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1187 WARN(cur_state != state,
1188 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1189 state_string(state), state_string(cur_state));
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1195 int pp_reg, lvds_reg;
1197 enum pipe panel_pipe = PIPE_A;
1200 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201 pp_reg = PCH_PP_CONTROL;
1202 lvds_reg = PCH_LVDS;
1204 pp_reg = PP_CONTROL;
1208 val = I915_READ(pp_reg);
1209 if (!(val & PANEL_POWER_ON) ||
1210 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1213 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214 panel_pipe = PIPE_B;
1216 WARN(panel_pipe == pipe && locked,
1217 "panel assertion failure, pipe %c regs locked\n",
1221 static void assert_cursor(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1224 struct drm_device *dev = dev_priv->dev;
1227 if (IS_845G(dev) || IS_I865G(dev))
1228 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1230 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1232 WARN(cur_state != state,
1233 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1234 pipe_name(pipe), state_string(state), state_string(cur_state));
1236 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1237 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1239 void assert_pipe(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1245 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1248 /* if we need the pipe A quirk it must be always on */
1249 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1252 if (!intel_display_power_enabled(dev_priv,
1253 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1256 reg = PIPECONF(cpu_transcoder);
1257 val = I915_READ(reg);
1258 cur_state = !!(val & PIPECONF_ENABLE);
1261 WARN(cur_state != state,
1262 "pipe %c assertion failure (expected %s, current %s)\n",
1263 pipe_name(pipe), state_string(state), state_string(cur_state));
1266 static void assert_plane(struct drm_i915_private *dev_priv,
1267 enum plane plane, bool state)
1273 reg = DSPCNTR(plane);
1274 val = I915_READ(reg);
1275 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1276 WARN(cur_state != state,
1277 "plane %c assertion failure (expected %s, current %s)\n",
1278 plane_name(plane), state_string(state), state_string(cur_state));
1281 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1282 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1284 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1287 struct drm_device *dev = dev_priv->dev;
1292 /* Primary planes are fixed to pipes on gen4+ */
1293 if (INTEL_INFO(dev)->gen >= 4) {
1294 reg = DSPCNTR(pipe);
1295 val = I915_READ(reg);
1296 WARN(val & DISPLAY_PLANE_ENABLE,
1297 "plane %c assertion failure, should be disabled but not\n",
1302 /* Need to check both planes against the pipe */
1305 val = I915_READ(reg);
1306 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1307 DISPPLANE_SEL_PIPE_SHIFT;
1308 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1309 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1310 plane_name(i), pipe_name(pipe));
1314 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1317 struct drm_device *dev = dev_priv->dev;
1321 if (IS_VALLEYVIEW(dev)) {
1322 for_each_sprite(pipe, sprite) {
1323 reg = SPCNTR(pipe, sprite);
1324 val = I915_READ(reg);
1325 WARN(val & SP_ENABLE,
1326 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327 sprite_name(pipe, sprite), pipe_name(pipe));
1329 } else if (INTEL_INFO(dev)->gen >= 7) {
1331 val = I915_READ(reg);
1332 WARN(val & SPRITE_ENABLE,
1333 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1334 plane_name(pipe), pipe_name(pipe));
1335 } else if (INTEL_INFO(dev)->gen >= 5) {
1336 reg = DVSCNTR(pipe);
1337 val = I915_READ(reg);
1338 WARN(val & DVS_ENABLE,
1339 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1340 plane_name(pipe), pipe_name(pipe));
1344 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1349 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1351 val = I915_READ(PCH_DREF_CONTROL);
1352 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1353 DREF_SUPERSPREAD_SOURCE_MASK));
1354 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1357 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1364 reg = PCH_TRANSCONF(pipe);
1365 val = I915_READ(reg);
1366 enabled = !!(val & TRANS_ENABLE);
1368 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 port_sel, u32 val)
1375 if ((val & DP_PORT_EN) == 0)
1378 if (HAS_PCH_CPT(dev_priv->dev)) {
1379 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1380 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1381 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1383 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1384 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1387 if ((val & DP_PIPE_MASK) != (pipe << 30))
1393 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe, u32 val)
1396 if ((val & SDVO_ENABLE) == 0)
1399 if (HAS_PCH_CPT(dev_priv->dev)) {
1400 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1402 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1403 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1406 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1412 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1413 enum pipe pipe, u32 val)
1415 if ((val & LVDS_PORT_EN) == 0)
1418 if (HAS_PCH_CPT(dev_priv->dev)) {
1419 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1422 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1428 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1429 enum pipe pipe, u32 val)
1431 if ((val & ADPA_DAC_ENABLE) == 0)
1433 if (HAS_PCH_CPT(dev_priv->dev)) {
1434 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1437 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1443 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1444 enum pipe pipe, int reg, u32 port_sel)
1446 u32 val = I915_READ(reg);
1447 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449 reg, pipe_name(pipe));
1451 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1452 && (val & DP_PIPEB_SELECT),
1453 "IBX PCH dp port still using transcoder B\n");
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, int reg)
1459 u32 val = I915_READ(reg);
1460 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462 reg, pipe_name(pipe));
1464 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1465 && (val & SDVO_PIPE_B_SELECT),
1466 "IBX PCH hdmi port still using transcoder B\n");
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1477 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1480 val = I915_READ(reg);
1481 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1482 "PCH VGA enabled on transcoder %c, should be disabled\n",
1486 val = I915_READ(reg);
1487 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1488 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1491 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1492 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1493 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1496 static void intel_init_dpio(struct drm_device *dev)
1498 struct drm_i915_private *dev_priv = dev->dev_private;
1500 if (!IS_VALLEYVIEW(dev))
1504 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1505 * CHV x1 PHY (DP/HDMI D)
1506 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1508 if (IS_CHERRYVIEW(dev)) {
1509 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1510 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1512 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1516 static void intel_reset_dpio(struct drm_device *dev)
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1520 if (IS_CHERRYVIEW(dev)) {
1524 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1525 /* Poll for phypwrgood signal */
1526 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1527 PHY_POWERGOOD(phy), 1))
1528 DRM_ERROR("Display PHY %d is not power up\n", phy);
1531 * Deassert common lane reset for PHY.
1533 * This should only be done on init and resume from S3
1534 * with both PLLs disabled, or we risk losing DPIO and
1535 * PLL synchronization.
1537 val = I915_READ(DISPLAY_PHY_CONTROL);
1538 I915_WRITE(DISPLAY_PHY_CONTROL,
1539 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1544 static void vlv_enable_pll(struct intel_crtc *crtc)
1546 struct drm_device *dev = crtc->base.dev;
1547 struct drm_i915_private *dev_priv = dev->dev_private;
1548 int reg = DPLL(crtc->pipe);
1549 u32 dpll = crtc->config.dpll_hw_state.dpll;
1551 assert_pipe_disabled(dev_priv, crtc->pipe);
1553 /* No really, not for ILK+ */
1554 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1556 /* PLL is protected by panel, make sure we can write it */
1557 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1558 assert_panel_unlocked(dev_priv, crtc->pipe);
1560 I915_WRITE(reg, dpll);
1564 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1565 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1567 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1568 POSTING_READ(DPLL_MD(crtc->pipe));
1570 /* We do this three times for luck */
1571 I915_WRITE(reg, dpll);
1573 udelay(150); /* wait for warmup */
1574 I915_WRITE(reg, dpll);
1576 udelay(150); /* wait for warmup */
1577 I915_WRITE(reg, dpll);
1579 udelay(150); /* wait for warmup */
1582 static void chv_enable_pll(struct intel_crtc *crtc)
1584 struct drm_device *dev = crtc->base.dev;
1585 struct drm_i915_private *dev_priv = dev->dev_private;
1586 int pipe = crtc->pipe;
1587 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1590 assert_pipe_disabled(dev_priv, crtc->pipe);
1592 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1594 mutex_lock(&dev_priv->dpio_lock);
1596 /* Enable back the 10bit clock to display controller */
1597 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1598 tmp |= DPIO_DCLKP_EN;
1599 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1602 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1607 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1609 /* Check PLL is locked */
1610 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1611 DRM_ERROR("PLL %d failed to lock\n", pipe);
1613 /* not sure when this should be written */
1614 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1615 POSTING_READ(DPLL_MD(pipe));
1617 mutex_unlock(&dev_priv->dpio_lock);
1620 static void i9xx_enable_pll(struct intel_crtc *crtc)
1622 struct drm_device *dev = crtc->base.dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 int reg = DPLL(crtc->pipe);
1625 u32 dpll = crtc->config.dpll_hw_state.dpll;
1627 assert_pipe_disabled(dev_priv, crtc->pipe);
1629 /* No really, not for ILK+ */
1630 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1632 /* PLL is protected by panel, make sure we can write it */
1633 if (IS_MOBILE(dev) && !IS_I830(dev))
1634 assert_panel_unlocked(dev_priv, crtc->pipe);
1636 I915_WRITE(reg, dpll);
1638 /* Wait for the clocks to stabilize. */
1642 if (INTEL_INFO(dev)->gen >= 4) {
1643 I915_WRITE(DPLL_MD(crtc->pipe),
1644 crtc->config.dpll_hw_state.dpll_md);
1646 /* The pixel multiplier can only be updated once the
1647 * DPLL is enabled and the clocks are stable.
1649 * So write it again.
1651 I915_WRITE(reg, dpll);
1654 /* We do this three times for luck */
1655 I915_WRITE(reg, dpll);
1657 udelay(150); /* wait for warmup */
1658 I915_WRITE(reg, dpll);
1660 udelay(150); /* wait for warmup */
1661 I915_WRITE(reg, dpll);
1663 udelay(150); /* wait for warmup */
1667 * i9xx_disable_pll - disable a PLL
1668 * @dev_priv: i915 private structure
1669 * @pipe: pipe PLL to disable
1671 * Disable the PLL for @pipe, making sure the pipe is off first.
1673 * Note! This is for pre-ILK only.
1675 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1677 /* Don't disable pipe A or pipe A PLLs if needed */
1678 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1681 /* Make sure the pipe isn't still relying on us */
1682 assert_pipe_disabled(dev_priv, pipe);
1684 I915_WRITE(DPLL(pipe), 0);
1685 POSTING_READ(DPLL(pipe));
1688 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 /* Make sure the pipe isn't still relying on us */
1693 assert_pipe_disabled(dev_priv, pipe);
1696 * Leave integrated clock source and reference clock enabled for pipe B.
1697 * The latter is needed for VGA hotplug / manual detection.
1700 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1701 I915_WRITE(DPLL(pipe), val);
1702 POSTING_READ(DPLL(pipe));
1706 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1708 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1711 /* Make sure the pipe isn't still relying on us */
1712 assert_pipe_disabled(dev_priv, pipe);
1714 /* Set PLL en = 0 */
1715 val = DPLL_SSC_REF_CLOCK_CHV;
1717 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1718 I915_WRITE(DPLL(pipe), val);
1719 POSTING_READ(DPLL(pipe));
1721 mutex_lock(&dev_priv->dpio_lock);
1723 /* Disable 10bit clock to display controller */
1724 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1725 val &= ~DPIO_DCLKP_EN;
1726 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1728 /* disable left/right clock distribution */
1729 if (pipe != PIPE_B) {
1730 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1731 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1732 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1734 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1735 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1736 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1739 mutex_unlock(&dev_priv->dpio_lock);
1742 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1743 struct intel_digital_port *dport)
1748 switch (dport->port) {
1750 port_mask = DPLL_PORTB_READY_MASK;
1754 port_mask = DPLL_PORTC_READY_MASK;
1758 port_mask = DPLL_PORTD_READY_MASK;
1759 dpll_reg = DPIO_PHY_STATUS;
1765 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1766 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1767 port_name(dport->port), I915_READ(dpll_reg));
1770 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1772 struct drm_device *dev = crtc->base.dev;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1776 if (WARN_ON(pll == NULL))
1779 WARN_ON(!pll->refcount);
1780 if (pll->active == 0) {
1781 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1783 assert_shared_dpll_disabled(dev_priv, pll);
1785 pll->mode_set(dev_priv, pll);
1790 * intel_enable_shared_dpll - enable PCH PLL
1791 * @dev_priv: i915 private structure
1792 * @pipe: pipe PLL to enable
1794 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1795 * drives the transcoder clock.
1797 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1799 struct drm_device *dev = crtc->base.dev;
1800 struct drm_i915_private *dev_priv = dev->dev_private;
1801 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1803 if (WARN_ON(pll == NULL))
1806 if (WARN_ON(pll->refcount == 0))
1809 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1810 pll->name, pll->active, pll->on,
1811 crtc->base.base.id);
1813 if (pll->active++) {
1815 assert_shared_dpll_enabled(dev_priv, pll);
1820 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1822 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1823 pll->enable(dev_priv, pll);
1827 void intel_disable_shared_dpll(struct intel_crtc *crtc)
1829 struct drm_device *dev = crtc->base.dev;
1830 struct drm_i915_private *dev_priv = dev->dev_private;
1831 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1833 /* PCH only available on ILK+ */
1834 BUG_ON(INTEL_INFO(dev)->gen < 5);
1835 if (WARN_ON(pll == NULL))
1838 if (WARN_ON(pll->refcount == 0))
1841 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1842 pll->name, pll->active, pll->on,
1843 crtc->base.base.id);
1845 if (WARN_ON(pll->active == 0)) {
1846 assert_shared_dpll_disabled(dev_priv, pll);
1850 assert_shared_dpll_enabled(dev_priv, pll);
1855 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1856 pll->disable(dev_priv, pll);
1859 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1862 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1865 struct drm_device *dev = dev_priv->dev;
1866 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1868 uint32_t reg, val, pipeconf_val;
1870 /* PCH only available on ILK+ */
1871 BUG_ON(INTEL_INFO(dev)->gen < 5);
1873 /* Make sure PCH DPLL is enabled */
1874 assert_shared_dpll_enabled(dev_priv,
1875 intel_crtc_to_shared_dpll(intel_crtc));
1877 /* FDI must be feeding us bits for PCH ports */
1878 assert_fdi_tx_enabled(dev_priv, pipe);
1879 assert_fdi_rx_enabled(dev_priv, pipe);
1881 if (HAS_PCH_CPT(dev)) {
1882 /* Workaround: Set the timing override bit before enabling the
1883 * pch transcoder. */
1884 reg = TRANS_CHICKEN2(pipe);
1885 val = I915_READ(reg);
1886 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1887 I915_WRITE(reg, val);
1890 reg = PCH_TRANSCONF(pipe);
1891 val = I915_READ(reg);
1892 pipeconf_val = I915_READ(PIPECONF(pipe));
1894 if (HAS_PCH_IBX(dev_priv->dev)) {
1896 * make the BPC in transcoder be consistent with
1897 * that in pipeconf reg.
1899 val &= ~PIPECONF_BPC_MASK;
1900 val |= pipeconf_val & PIPECONF_BPC_MASK;
1903 val &= ~TRANS_INTERLACE_MASK;
1904 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1905 if (HAS_PCH_IBX(dev_priv->dev) &&
1906 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1907 val |= TRANS_LEGACY_INTERLACED_ILK;
1909 val |= TRANS_INTERLACED;
1911 val |= TRANS_PROGRESSIVE;
1913 I915_WRITE(reg, val | TRANS_ENABLE);
1914 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1915 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1918 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1919 enum transcoder cpu_transcoder)
1921 u32 val, pipeconf_val;
1923 /* PCH only available on ILK+ */
1924 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1926 /* FDI must be feeding us bits for PCH ports */
1927 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1928 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1930 /* Workaround: set timing override bit. */
1931 val = I915_READ(_TRANSA_CHICKEN2);
1932 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1933 I915_WRITE(_TRANSA_CHICKEN2, val);
1936 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1938 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1939 PIPECONF_INTERLACED_ILK)
1940 val |= TRANS_INTERLACED;
1942 val |= TRANS_PROGRESSIVE;
1944 I915_WRITE(LPT_TRANSCONF, val);
1945 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1946 DRM_ERROR("Failed to enable PCH transcoder\n");
1949 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1952 struct drm_device *dev = dev_priv->dev;
1955 /* FDI relies on the transcoder */
1956 assert_fdi_tx_disabled(dev_priv, pipe);
1957 assert_fdi_rx_disabled(dev_priv, pipe);
1959 /* Ports must be off as well */
1960 assert_pch_ports_disabled(dev_priv, pipe);
1962 reg = PCH_TRANSCONF(pipe);
1963 val = I915_READ(reg);
1964 val &= ~TRANS_ENABLE;
1965 I915_WRITE(reg, val);
1966 /* wait for PCH transcoder off, transcoder state */
1967 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1968 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1970 if (!HAS_PCH_IBX(dev)) {
1971 /* Workaround: Clear the timing override chicken bit again. */
1972 reg = TRANS_CHICKEN2(pipe);
1973 val = I915_READ(reg);
1974 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1975 I915_WRITE(reg, val);
1979 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 val = I915_READ(LPT_TRANSCONF);
1984 val &= ~TRANS_ENABLE;
1985 I915_WRITE(LPT_TRANSCONF, val);
1986 /* wait for PCH transcoder off, transcoder state */
1987 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1988 DRM_ERROR("Failed to disable PCH transcoder\n");
1990 /* Workaround: clear timing override bit. */
1991 val = I915_READ(_TRANSA_CHICKEN2);
1992 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1993 I915_WRITE(_TRANSA_CHICKEN2, val);
1997 * intel_enable_pipe - enable a pipe, asserting requirements
1998 * @crtc: crtc responsible for the pipe
2000 * Enable @crtc's pipe, making sure that various hardware specific requirements
2001 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2003 static void intel_enable_pipe(struct intel_crtc *crtc)
2005 struct drm_device *dev = crtc->base.dev;
2006 struct drm_i915_private *dev_priv = dev->dev_private;
2007 enum pipe pipe = crtc->pipe;
2008 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2010 enum pipe pch_transcoder;
2014 assert_planes_disabled(dev_priv, pipe);
2015 assert_cursor_disabled(dev_priv, pipe);
2016 assert_sprites_disabled(dev_priv, pipe);
2018 if (HAS_PCH_LPT(dev_priv->dev))
2019 pch_transcoder = TRANSCODER_A;
2021 pch_transcoder = pipe;
2024 * A pipe without a PLL won't actually be able to drive bits from
2025 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2028 if (!HAS_PCH_SPLIT(dev_priv->dev))
2029 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2030 assert_dsi_pll_enabled(dev_priv);
2032 assert_pll_enabled(dev_priv, pipe);
2034 if (crtc->config.has_pch_encoder) {
2035 /* if driving the PCH, we need FDI enabled */
2036 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2037 assert_fdi_tx_pll_enabled(dev_priv,
2038 (enum pipe) cpu_transcoder);
2040 /* FIXME: assert CPU port conditions for SNB+ */
2043 reg = PIPECONF(cpu_transcoder);
2044 val = I915_READ(reg);
2045 if (val & PIPECONF_ENABLE) {
2046 WARN_ON(!(pipe == PIPE_A &&
2047 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2051 I915_WRITE(reg, val | PIPECONF_ENABLE);
2056 * intel_disable_pipe - disable a pipe, asserting requirements
2057 * @dev_priv: i915 private structure
2058 * @pipe: pipe to disable
2060 * Disable @pipe, making sure that various hardware specific requirements
2061 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2063 * @pipe should be %PIPE_A or %PIPE_B.
2065 * Will wait until the pipe has shut down before returning.
2067 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2070 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2076 * Make sure planes won't keep trying to pump pixels to us,
2077 * or we might hang the display.
2079 assert_planes_disabled(dev_priv, pipe);
2080 assert_cursor_disabled(dev_priv, pipe);
2081 assert_sprites_disabled(dev_priv, pipe);
2083 /* Don't disable pipe A or pipe A PLLs if needed */
2084 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2087 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0)
2092 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2093 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2097 * Plane regs are double buffered, going from enabled->disabled needs a
2098 * trigger in order to latch. The display address reg provides this.
2100 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2103 struct drm_device *dev = dev_priv->dev;
2104 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2106 I915_WRITE(reg, I915_READ(reg));
2111 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2112 * @dev_priv: i915 private structure
2113 * @plane: plane to enable
2114 * @pipe: pipe being fed
2116 * Enable @plane on @pipe, making sure that @pipe is running first.
2118 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2119 enum plane plane, enum pipe pipe)
2121 struct drm_device *dev = dev_priv->dev;
2122 struct intel_crtc *intel_crtc =
2123 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2127 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2128 assert_pipe_enabled(dev_priv, pipe);
2130 if (intel_crtc->primary_enabled)
2133 intel_crtc->primary_enabled = true;
2135 reg = DSPCNTR(plane);
2136 val = I915_READ(reg);
2137 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2139 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2140 intel_flush_primary_plane(dev_priv, plane);
2143 * BDW signals flip done immediately if the plane
2144 * is disabled, even if the plane enable is already
2145 * armed to occur at the next vblank :(
2147 if (IS_BROADWELL(dev))
2148 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 * intel_disable_primary_hw_plane - disable the primary hardware plane
2153 * @dev_priv: i915 private structure
2154 * @plane: plane to disable
2155 * @pipe: pipe consuming the data
2157 * Disable @plane; should be an independent operation.
2159 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2160 enum plane plane, enum pipe pipe)
2162 struct intel_crtc *intel_crtc =
2163 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2167 if (!intel_crtc->primary_enabled)
2170 intel_crtc->primary_enabled = false;
2172 reg = DSPCNTR(plane);
2173 val = I915_READ(reg);
2174 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2176 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2177 intel_flush_primary_plane(dev_priv, plane);
2180 static bool need_vtd_wa(struct drm_device *dev)
2182 #ifdef CONFIG_INTEL_IOMMU
2183 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2189 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2193 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2194 return ALIGN(height, tile_height);
2198 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2199 struct drm_i915_gem_object *obj,
2200 struct intel_engine_cs *pipelined)
2202 struct drm_i915_private *dev_priv = dev->dev_private;
2206 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208 switch (obj->tiling_mode) {
2209 case I915_TILING_NONE:
2210 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2211 alignment = 128 * 1024;
2212 else if (INTEL_INFO(dev)->gen >= 4)
2213 alignment = 4 * 1024;
2215 alignment = 64 * 1024;
2218 /* pin() will align the object as required by fence */
2222 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2228 /* Note that the w/a also requires 64 PTE of padding following the
2229 * bo. We currently fill all unused PTE with the shadow page and so
2230 * we should always have valid PTE following the scanout preventing
2233 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2234 alignment = 256 * 1024;
2236 dev_priv->mm.interruptible = false;
2237 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2239 goto err_interruptible;
2241 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2242 * fence, whereas 965+ only requires a fence if using
2243 * framebuffer compression. For simplicity, we always install
2244 * a fence as the cost is not that onerous.
2246 ret = i915_gem_object_get_fence(obj);
2250 i915_gem_object_pin_fence(obj);
2252 dev_priv->mm.interruptible = true;
2256 i915_gem_object_unpin_from_display_plane(obj);
2258 dev_priv->mm.interruptible = true;
2262 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2264 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2266 i915_gem_object_unpin_fence(obj);
2267 i915_gem_object_unpin_from_display_plane(obj);
2270 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2271 * is assumed to be a power-of-two. */
2272 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2273 unsigned int tiling_mode,
2277 if (tiling_mode != I915_TILING_NONE) {
2278 unsigned int tile_rows, tiles;
2283 tiles = *x / (512/cpp);
2286 return tile_rows * pitch * 8 + tiles * 4096;
2288 unsigned int offset;
2290 offset = *y * pitch + *x * cpp;
2292 *x = (offset & 4095) / cpp;
2293 return offset & -4096;
2297 int intel_format_to_fourcc(int format)
2300 case DISPPLANE_8BPP:
2301 return DRM_FORMAT_C8;
2302 case DISPPLANE_BGRX555:
2303 return DRM_FORMAT_XRGB1555;
2304 case DISPPLANE_BGRX565:
2305 return DRM_FORMAT_RGB565;
2307 case DISPPLANE_BGRX888:
2308 return DRM_FORMAT_XRGB8888;
2309 case DISPPLANE_RGBX888:
2310 return DRM_FORMAT_XBGR8888;
2311 case DISPPLANE_BGRX101010:
2312 return DRM_FORMAT_XRGB2101010;
2313 case DISPPLANE_RGBX101010:
2314 return DRM_FORMAT_XBGR2101010;
2318 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2319 struct intel_plane_config *plane_config)
2321 struct drm_device *dev = crtc->base.dev;
2322 struct drm_i915_gem_object *obj = NULL;
2323 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2324 u32 base = plane_config->base;
2326 if (plane_config->size == 0)
2329 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2330 plane_config->size);
2334 if (plane_config->tiled) {
2335 obj->tiling_mode = I915_TILING_X;
2336 obj->stride = crtc->base.primary->fb->pitches[0];
2339 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2340 mode_cmd.width = crtc->base.primary->fb->width;
2341 mode_cmd.height = crtc->base.primary->fb->height;
2342 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2344 mutex_lock(&dev->struct_mutex);
2346 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2348 DRM_DEBUG_KMS("intel fb init failed\n");
2352 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2353 mutex_unlock(&dev->struct_mutex);
2355 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2359 drm_gem_object_unreference(&obj->base);
2360 mutex_unlock(&dev->struct_mutex);
2364 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2365 struct intel_plane_config *plane_config)
2367 struct drm_device *dev = intel_crtc->base.dev;
2369 struct intel_crtc *i;
2370 struct drm_i915_gem_object *obj;
2372 if (!intel_crtc->base.primary->fb)
2375 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2378 kfree(intel_crtc->base.primary->fb);
2379 intel_crtc->base.primary->fb = NULL;
2382 * Failed to alloc the obj, check to see if we should share
2383 * an fb with another CRTC instead
2385 for_each_crtc(dev, c) {
2386 i = to_intel_crtc(c);
2388 if (c == &intel_crtc->base)
2394 obj = intel_fb_obj(c->primary->fb);
2398 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2399 drm_framebuffer_reference(c->primary->fb);
2400 intel_crtc->base.primary->fb = c->primary->fb;
2401 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2407 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2408 struct drm_framebuffer *fb,
2411 struct drm_device *dev = crtc->dev;
2412 struct drm_i915_private *dev_priv = dev->dev_private;
2413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2415 int plane = intel_crtc->plane;
2416 unsigned long linear_offset;
2420 reg = DSPCNTR(plane);
2421 dspcntr = I915_READ(reg);
2422 /* Mask out pixel format bits in case we change it */
2423 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2424 switch (fb->pixel_format) {
2426 dspcntr |= DISPPLANE_8BPP;
2428 case DRM_FORMAT_XRGB1555:
2429 case DRM_FORMAT_ARGB1555:
2430 dspcntr |= DISPPLANE_BGRX555;
2432 case DRM_FORMAT_RGB565:
2433 dspcntr |= DISPPLANE_BGRX565;
2435 case DRM_FORMAT_XRGB8888:
2436 case DRM_FORMAT_ARGB8888:
2437 dspcntr |= DISPPLANE_BGRX888;
2439 case DRM_FORMAT_XBGR8888:
2440 case DRM_FORMAT_ABGR8888:
2441 dspcntr |= DISPPLANE_RGBX888;
2443 case DRM_FORMAT_XRGB2101010:
2444 case DRM_FORMAT_ARGB2101010:
2445 dspcntr |= DISPPLANE_BGRX101010;
2447 case DRM_FORMAT_XBGR2101010:
2448 case DRM_FORMAT_ABGR2101010:
2449 dspcntr |= DISPPLANE_RGBX101010;
2455 if (INTEL_INFO(dev)->gen >= 4) {
2456 if (obj->tiling_mode != I915_TILING_NONE)
2457 dspcntr |= DISPPLANE_TILED;
2459 dspcntr &= ~DISPPLANE_TILED;
2463 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2465 I915_WRITE(reg, dspcntr);
2467 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2469 if (INTEL_INFO(dev)->gen >= 4) {
2470 intel_crtc->dspaddr_offset =
2471 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2472 fb->bits_per_pixel / 8,
2474 linear_offset -= intel_crtc->dspaddr_offset;
2476 intel_crtc->dspaddr_offset = linear_offset;
2479 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2480 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2482 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2483 if (INTEL_INFO(dev)->gen >= 4) {
2484 I915_WRITE(DSPSURF(plane),
2485 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2486 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2487 I915_WRITE(DSPLINOFF(plane), linear_offset);
2489 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2493 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2494 struct drm_framebuffer *fb,
2497 struct drm_device *dev = crtc->dev;
2498 struct drm_i915_private *dev_priv = dev->dev_private;
2499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2500 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2501 int plane = intel_crtc->plane;
2502 unsigned long linear_offset;
2506 reg = DSPCNTR(plane);
2507 dspcntr = I915_READ(reg);
2508 /* Mask out pixel format bits in case we change it */
2509 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2510 switch (fb->pixel_format) {
2512 dspcntr |= DISPPLANE_8BPP;
2514 case DRM_FORMAT_RGB565:
2515 dspcntr |= DISPPLANE_BGRX565;
2517 case DRM_FORMAT_XRGB8888:
2518 case DRM_FORMAT_ARGB8888:
2519 dspcntr |= DISPPLANE_BGRX888;
2521 case DRM_FORMAT_XBGR8888:
2522 case DRM_FORMAT_ABGR8888:
2523 dspcntr |= DISPPLANE_RGBX888;
2525 case DRM_FORMAT_XRGB2101010:
2526 case DRM_FORMAT_ARGB2101010:
2527 dspcntr |= DISPPLANE_BGRX101010;
2529 case DRM_FORMAT_XBGR2101010:
2530 case DRM_FORMAT_ABGR2101010:
2531 dspcntr |= DISPPLANE_RGBX101010;
2537 if (obj->tiling_mode != I915_TILING_NONE)
2538 dspcntr |= DISPPLANE_TILED;
2540 dspcntr &= ~DISPPLANE_TILED;
2542 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2543 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2545 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2547 I915_WRITE(reg, dspcntr);
2549 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2550 intel_crtc->dspaddr_offset =
2551 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2552 fb->bits_per_pixel / 8,
2554 linear_offset -= intel_crtc->dspaddr_offset;
2556 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2557 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2559 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2560 I915_WRITE(DSPSURF(plane),
2561 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2562 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2563 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2565 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2566 I915_WRITE(DSPLINOFF(plane), linear_offset);
2571 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2573 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2574 int x, int y, enum mode_set_atomic state)
2576 struct drm_device *dev = crtc->dev;
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2579 if (dev_priv->display.disable_fbc)
2580 dev_priv->display.disable_fbc(dev);
2581 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2583 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2588 void intel_display_handle_reset(struct drm_device *dev)
2590 struct drm_i915_private *dev_priv = dev->dev_private;
2591 struct drm_crtc *crtc;
2594 * Flips in the rings have been nuked by the reset,
2595 * so complete all pending flips so that user space
2596 * will get its events and not get stuck.
2598 * Also update the base address of all primary
2599 * planes to the the last fb to make sure we're
2600 * showing the correct fb after a reset.
2602 * Need to make two loops over the crtcs so that we
2603 * don't try to grab a crtc mutex before the
2604 * pending_flip_queue really got woken up.
2607 for_each_crtc(dev, crtc) {
2608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2609 enum plane plane = intel_crtc->plane;
2611 intel_prepare_page_flip(dev, plane);
2612 intel_finish_page_flip_plane(dev, plane);
2615 for_each_crtc(dev, crtc) {
2616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2618 drm_modeset_lock(&crtc->mutex, NULL);
2620 * FIXME: Once we have proper support for primary planes (and
2621 * disabling them without disabling the entire crtc) allow again
2622 * a NULL crtc->primary->fb.
2624 if (intel_crtc->active && crtc->primary->fb)
2625 dev_priv->display.update_primary_plane(crtc,
2629 drm_modeset_unlock(&crtc->mutex);
2634 intel_finish_fb(struct drm_framebuffer *old_fb)
2636 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2637 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2638 bool was_interruptible = dev_priv->mm.interruptible;
2641 /* Big Hammer, we also need to ensure that any pending
2642 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2643 * current scanout is retired before unpinning the old
2646 * This should only fail upon a hung GPU, in which case we
2647 * can safely continue.
2649 dev_priv->mm.interruptible = false;
2650 ret = i915_gem_object_finish_gpu(obj);
2651 dev_priv->mm.interruptible = was_interruptible;
2656 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2658 struct drm_device *dev = crtc->dev;
2659 struct drm_i915_private *dev_priv = dev->dev_private;
2660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2661 unsigned long flags;
2664 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2665 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2668 spin_lock_irqsave(&dev->event_lock, flags);
2669 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2670 spin_unlock_irqrestore(&dev->event_lock, flags);
2676 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2677 struct drm_framebuffer *fb)
2679 struct drm_device *dev = crtc->dev;
2680 struct drm_i915_private *dev_priv = dev->dev_private;
2681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2682 enum pipe pipe = intel_crtc->pipe;
2683 struct drm_framebuffer *old_fb = crtc->primary->fb;
2684 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2685 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2688 if (intel_crtc_has_pending_flip(crtc)) {
2689 DRM_ERROR("pipe is still busy with an old pageflip\n");
2695 DRM_ERROR("No FB bound\n");
2699 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2700 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2701 plane_name(intel_crtc->plane),
2702 INTEL_INFO(dev)->num_pipes);
2706 mutex_lock(&dev->struct_mutex);
2707 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2709 i915_gem_track_fb(old_obj, obj,
2710 INTEL_FRONTBUFFER_PRIMARY(pipe));
2711 mutex_unlock(&dev->struct_mutex);
2713 DRM_ERROR("pin & fence failed\n");
2718 * Update pipe size and adjust fitter if needed: the reason for this is
2719 * that in compute_mode_changes we check the native mode (not the pfit
2720 * mode) to see if we can flip rather than do a full mode set. In the
2721 * fastboot case, we'll flip, but if we don't update the pipesrc and
2722 * pfit state, we'll end up with a big fb scanned out into the wrong
2725 * To fix this properly, we need to hoist the checks up into
2726 * compute_mode_changes (or above), check the actual pfit state and
2727 * whether the platform allows pfit disable with pipe active, and only
2728 * then update the pipesrc and pfit state, even on the flip path.
2730 if (i915.fastboot) {
2731 const struct drm_display_mode *adjusted_mode =
2732 &intel_crtc->config.adjusted_mode;
2734 I915_WRITE(PIPESRC(intel_crtc->pipe),
2735 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2736 (adjusted_mode->crtc_vdisplay - 1));
2737 if (!intel_crtc->config.pch_pfit.enabled &&
2738 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2739 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2740 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2741 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2742 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2744 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2745 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2748 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2750 if (intel_crtc->active)
2751 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2753 crtc->primary->fb = fb;
2758 if (intel_crtc->active && old_fb != fb)
2759 intel_wait_for_vblank(dev, intel_crtc->pipe);
2760 mutex_lock(&dev->struct_mutex);
2761 intel_unpin_fb_obj(old_obj);
2762 mutex_unlock(&dev->struct_mutex);
2765 mutex_lock(&dev->struct_mutex);
2766 intel_update_fbc(dev);
2767 mutex_unlock(&dev->struct_mutex);
2772 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2774 struct drm_device *dev = crtc->dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777 int pipe = intel_crtc->pipe;
2780 /* enable normal train */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 if (IS_IVYBRIDGE(dev)) {
2784 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2785 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2790 I915_WRITE(reg, temp);
2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 if (HAS_PCH_CPT(dev)) {
2795 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2796 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2798 temp &= ~FDI_LINK_TRAIN_NONE;
2799 temp |= FDI_LINK_TRAIN_NONE;
2801 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2803 /* wait one idle pattern time */
2807 /* IVB wants error correction enabled */
2808 if (IS_IVYBRIDGE(dev))
2809 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2810 FDI_FE_ERRC_ENABLE);
2813 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2815 return crtc->base.enabled && crtc->active &&
2816 crtc->config.has_pch_encoder;
2819 static void ivb_modeset_global_resources(struct drm_device *dev)
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822 struct intel_crtc *pipe_B_crtc =
2823 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2824 struct intel_crtc *pipe_C_crtc =
2825 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2829 * When everything is off disable fdi C so that we could enable fdi B
2830 * with all lanes. Note that we don't care about enabled pipes without
2831 * an enabled pch encoder.
2833 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2834 !pipe_has_enabled_pch(pipe_C_crtc)) {
2835 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2836 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2838 temp = I915_READ(SOUTH_CHICKEN1);
2839 temp &= ~FDI_BC_BIFURCATION_SELECT;
2840 DRM_DEBUG_KMS("disabling fdi C rx\n");
2841 I915_WRITE(SOUTH_CHICKEN1, temp);
2845 /* The FDI link training functions for ILK/Ibexpeak. */
2846 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2848 struct drm_device *dev = crtc->dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2851 int pipe = intel_crtc->pipe;
2852 u32 reg, temp, tries;
2854 /* FDI needs bits from pipe first */
2855 assert_pipe_enabled(dev_priv, pipe);
2857 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2859 reg = FDI_RX_IMR(pipe);
2860 temp = I915_READ(reg);
2861 temp &= ~FDI_RX_SYMBOL_LOCK;
2862 temp &= ~FDI_RX_BIT_LOCK;
2863 I915_WRITE(reg, temp);
2867 /* enable CPU FDI TX and PCH FDI RX */
2868 reg = FDI_TX_CTL(pipe);
2869 temp = I915_READ(reg);
2870 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2871 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2872 temp &= ~FDI_LINK_TRAIN_NONE;
2873 temp |= FDI_LINK_TRAIN_PATTERN_1;
2874 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2876 reg = FDI_RX_CTL(pipe);
2877 temp = I915_READ(reg);
2878 temp &= ~FDI_LINK_TRAIN_NONE;
2879 temp |= FDI_LINK_TRAIN_PATTERN_1;
2880 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2885 /* Ironlake workaround, enable clock pointer after FDI enable*/
2886 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2887 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2888 FDI_RX_PHASE_SYNC_POINTER_EN);
2890 reg = FDI_RX_IIR(pipe);
2891 for (tries = 0; tries < 5; tries++) {
2892 temp = I915_READ(reg);
2893 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2895 if ((temp & FDI_RX_BIT_LOCK)) {
2896 DRM_DEBUG_KMS("FDI train 1 done.\n");
2897 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2902 DRM_ERROR("FDI train 1 fail!\n");
2905 reg = FDI_TX_CTL(pipe);
2906 temp = I915_READ(reg);
2907 temp &= ~FDI_LINK_TRAIN_NONE;
2908 temp |= FDI_LINK_TRAIN_PATTERN_2;
2909 I915_WRITE(reg, temp);
2911 reg = FDI_RX_CTL(pipe);
2912 temp = I915_READ(reg);
2913 temp &= ~FDI_LINK_TRAIN_NONE;
2914 temp |= FDI_LINK_TRAIN_PATTERN_2;
2915 I915_WRITE(reg, temp);
2920 reg = FDI_RX_IIR(pipe);
2921 for (tries = 0; tries < 5; tries++) {
2922 temp = I915_READ(reg);
2923 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2925 if (temp & FDI_RX_SYMBOL_LOCK) {
2926 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2927 DRM_DEBUG_KMS("FDI train 2 done.\n");
2932 DRM_ERROR("FDI train 2 fail!\n");
2934 DRM_DEBUG_KMS("FDI train done\n");
2938 static const int snb_b_fdi_train_param[] = {
2939 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2940 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2941 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2942 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2945 /* The FDI link training functions for SNB/Cougarpoint. */
2946 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2948 struct drm_device *dev = crtc->dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2951 int pipe = intel_crtc->pipe;
2952 u32 reg, temp, i, retry;
2954 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2956 reg = FDI_RX_IMR(pipe);
2957 temp = I915_READ(reg);
2958 temp &= ~FDI_RX_SYMBOL_LOCK;
2959 temp &= ~FDI_RX_BIT_LOCK;
2960 I915_WRITE(reg, temp);
2965 /* enable CPU FDI TX and PCH FDI RX */
2966 reg = FDI_TX_CTL(pipe);
2967 temp = I915_READ(reg);
2968 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2969 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2970 temp &= ~FDI_LINK_TRAIN_NONE;
2971 temp |= FDI_LINK_TRAIN_PATTERN_1;
2972 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2974 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2975 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2977 I915_WRITE(FDI_RX_MISC(pipe),
2978 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2980 reg = FDI_RX_CTL(pipe);
2981 temp = I915_READ(reg);
2982 if (HAS_PCH_CPT(dev)) {
2983 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2984 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2986 temp &= ~FDI_LINK_TRAIN_NONE;
2987 temp |= FDI_LINK_TRAIN_PATTERN_1;
2989 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2994 for (i = 0; i < 4; i++) {
2995 reg = FDI_TX_CTL(pipe);
2996 temp = I915_READ(reg);
2997 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2998 temp |= snb_b_fdi_train_param[i];
2999 I915_WRITE(reg, temp);
3004 for (retry = 0; retry < 5; retry++) {
3005 reg = FDI_RX_IIR(pipe);
3006 temp = I915_READ(reg);
3007 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3008 if (temp & FDI_RX_BIT_LOCK) {
3009 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3010 DRM_DEBUG_KMS("FDI train 1 done.\n");
3019 DRM_ERROR("FDI train 1 fail!\n");
3022 reg = FDI_TX_CTL(pipe);
3023 temp = I915_READ(reg);
3024 temp &= ~FDI_LINK_TRAIN_NONE;
3025 temp |= FDI_LINK_TRAIN_PATTERN_2;
3027 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3029 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3031 I915_WRITE(reg, temp);
3033 reg = FDI_RX_CTL(pipe);
3034 temp = I915_READ(reg);
3035 if (HAS_PCH_CPT(dev)) {
3036 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3037 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3039 temp &= ~FDI_LINK_TRAIN_NONE;
3040 temp |= FDI_LINK_TRAIN_PATTERN_2;
3042 I915_WRITE(reg, temp);
3047 for (i = 0; i < 4; i++) {
3048 reg = FDI_TX_CTL(pipe);
3049 temp = I915_READ(reg);
3050 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3051 temp |= snb_b_fdi_train_param[i];
3052 I915_WRITE(reg, temp);
3057 for (retry = 0; retry < 5; retry++) {
3058 reg = FDI_RX_IIR(pipe);
3059 temp = I915_READ(reg);
3060 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3061 if (temp & FDI_RX_SYMBOL_LOCK) {
3062 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3063 DRM_DEBUG_KMS("FDI train 2 done.\n");
3072 DRM_ERROR("FDI train 2 fail!\n");
3074 DRM_DEBUG_KMS("FDI train done.\n");
3077 /* Manual link training for Ivy Bridge A0 parts */
3078 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3080 struct drm_device *dev = crtc->dev;
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3083 int pipe = intel_crtc->pipe;
3084 u32 reg, temp, i, j;
3086 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3088 reg = FDI_RX_IMR(pipe);
3089 temp = I915_READ(reg);
3090 temp &= ~FDI_RX_SYMBOL_LOCK;
3091 temp &= ~FDI_RX_BIT_LOCK;
3092 I915_WRITE(reg, temp);
3097 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3098 I915_READ(FDI_RX_IIR(pipe)));
3100 /* Try each vswing and preemphasis setting twice before moving on */
3101 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3102 /* disable first in case we need to retry */
3103 reg = FDI_TX_CTL(pipe);
3104 temp = I915_READ(reg);
3105 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3106 temp &= ~FDI_TX_ENABLE;
3107 I915_WRITE(reg, temp);
3109 reg = FDI_RX_CTL(pipe);
3110 temp = I915_READ(reg);
3111 temp &= ~FDI_LINK_TRAIN_AUTO;
3112 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3113 temp &= ~FDI_RX_ENABLE;
3114 I915_WRITE(reg, temp);
3116 /* enable CPU FDI TX and PCH FDI RX */
3117 reg = FDI_TX_CTL(pipe);
3118 temp = I915_READ(reg);
3119 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3120 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3121 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3122 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3123 temp |= snb_b_fdi_train_param[j/2];
3124 temp |= FDI_COMPOSITE_SYNC;
3125 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3127 I915_WRITE(FDI_RX_MISC(pipe),
3128 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3130 reg = FDI_RX_CTL(pipe);
3131 temp = I915_READ(reg);
3132 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3133 temp |= FDI_COMPOSITE_SYNC;
3134 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3137 udelay(1); /* should be 0.5us */
3139 for (i = 0; i < 4; i++) {
3140 reg = FDI_RX_IIR(pipe);
3141 temp = I915_READ(reg);
3142 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3144 if (temp & FDI_RX_BIT_LOCK ||
3145 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3146 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3147 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3151 udelay(1); /* should be 0.5us */
3154 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3159 reg = FDI_TX_CTL(pipe);
3160 temp = I915_READ(reg);
3161 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3162 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3163 I915_WRITE(reg, temp);
3165 reg = FDI_RX_CTL(pipe);
3166 temp = I915_READ(reg);
3167 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3168 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3169 I915_WRITE(reg, temp);
3172 udelay(2); /* should be 1.5us */
3174 for (i = 0; i < 4; i++) {
3175 reg = FDI_RX_IIR(pipe);
3176 temp = I915_READ(reg);
3177 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3179 if (temp & FDI_RX_SYMBOL_LOCK ||
3180 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3181 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3182 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3186 udelay(2); /* should be 1.5us */
3189 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3193 DRM_DEBUG_KMS("FDI train done.\n");
3196 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3198 struct drm_device *dev = intel_crtc->base.dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 int pipe = intel_crtc->pipe;
3204 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3205 reg = FDI_RX_CTL(pipe);
3206 temp = I915_READ(reg);
3207 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3208 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3209 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3210 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3215 /* Switch from Rawclk to PCDclk */
3216 temp = I915_READ(reg);
3217 I915_WRITE(reg, temp | FDI_PCDCLK);
3222 /* Enable CPU FDI TX PLL, always on for Ironlake */
3223 reg = FDI_TX_CTL(pipe);
3224 temp = I915_READ(reg);
3225 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3226 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3233 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3235 struct drm_device *dev = intel_crtc->base.dev;
3236 struct drm_i915_private *dev_priv = dev->dev_private;
3237 int pipe = intel_crtc->pipe;
3240 /* Switch from PCDclk to Rawclk */
3241 reg = FDI_RX_CTL(pipe);
3242 temp = I915_READ(reg);
3243 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3245 /* Disable CPU FDI TX PLL */
3246 reg = FDI_TX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3253 reg = FDI_RX_CTL(pipe);
3254 temp = I915_READ(reg);
3255 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3257 /* Wait for the clocks to turn off. */
3262 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3264 struct drm_device *dev = crtc->dev;
3265 struct drm_i915_private *dev_priv = dev->dev_private;
3266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3267 int pipe = intel_crtc->pipe;
3270 /* disable CPU FDI tx and PCH FDI rx */
3271 reg = FDI_TX_CTL(pipe);
3272 temp = I915_READ(reg);
3273 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3276 reg = FDI_RX_CTL(pipe);
3277 temp = I915_READ(reg);
3278 temp &= ~(0x7 << 16);
3279 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3280 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3285 /* Ironlake workaround, disable clock pointer after downing FDI */
3286 if (HAS_PCH_IBX(dev))
3287 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3289 /* still set train pattern 1 */
3290 reg = FDI_TX_CTL(pipe);
3291 temp = I915_READ(reg);
3292 temp &= ~FDI_LINK_TRAIN_NONE;
3293 temp |= FDI_LINK_TRAIN_PATTERN_1;
3294 I915_WRITE(reg, temp);
3296 reg = FDI_RX_CTL(pipe);
3297 temp = I915_READ(reg);
3298 if (HAS_PCH_CPT(dev)) {
3299 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3302 temp &= ~FDI_LINK_TRAIN_NONE;
3303 temp |= FDI_LINK_TRAIN_PATTERN_1;
3305 /* BPC in FDI rx is consistent with that in PIPECONF */
3306 temp &= ~(0x07 << 16);
3307 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3308 I915_WRITE(reg, temp);
3314 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3316 struct intel_crtc *crtc;
3318 /* Note that we don't need to be called with mode_config.lock here
3319 * as our list of CRTC objects is static for the lifetime of the
3320 * device and so cannot disappear as we iterate. Similarly, we can
3321 * happily treat the predicates as racy, atomic checks as userspace
3322 * cannot claim and pin a new fb without at least acquring the
3323 * struct_mutex and so serialising with us.
3325 for_each_intel_crtc(dev, crtc) {
3326 if (atomic_read(&crtc->unpin_work_count) == 0)
3329 if (crtc->unpin_work)
3330 intel_wait_for_vblank(dev, crtc->pipe);
3338 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3340 struct drm_device *dev = crtc->dev;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3343 if (crtc->primary->fb == NULL)
3346 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3348 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3349 !intel_crtc_has_pending_flip(crtc),
3352 mutex_lock(&dev->struct_mutex);
3353 intel_finish_fb(crtc->primary->fb);
3354 mutex_unlock(&dev->struct_mutex);
3357 /* Program iCLKIP clock to the desired frequency */
3358 static void lpt_program_iclkip(struct drm_crtc *crtc)
3360 struct drm_device *dev = crtc->dev;
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3363 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3366 mutex_lock(&dev_priv->dpio_lock);
3368 /* It is necessary to ungate the pixclk gate prior to programming
3369 * the divisors, and gate it back when it is done.
3371 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3373 /* Disable SSCCTL */
3374 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3375 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3379 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3380 if (clock == 20000) {
3385 /* The iCLK virtual clock root frequency is in MHz,
3386 * but the adjusted_mode->crtc_clock in in KHz. To get the
3387 * divisors, it is necessary to divide one by another, so we
3388 * convert the virtual clock precision to KHz here for higher
3391 u32 iclk_virtual_root_freq = 172800 * 1000;
3392 u32 iclk_pi_range = 64;
3393 u32 desired_divisor, msb_divisor_value, pi_value;
3395 desired_divisor = (iclk_virtual_root_freq / clock);
3396 msb_divisor_value = desired_divisor / iclk_pi_range;
3397 pi_value = desired_divisor % iclk_pi_range;
3400 divsel = msb_divisor_value - 2;
3401 phaseinc = pi_value;
3404 /* This should not happen with any sane values */
3405 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3406 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3407 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3408 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3410 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3417 /* Program SSCDIVINTPHASE6 */
3418 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3419 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3420 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3421 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3422 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3423 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3424 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3425 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3427 /* Program SSCAUXDIV */
3428 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3429 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3430 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3431 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3433 /* Enable modulator and associated divider */
3434 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3435 temp &= ~SBI_SSCCTL_DISABLE;
3436 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3438 /* Wait for initialization time */
3441 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3443 mutex_unlock(&dev_priv->dpio_lock);
3446 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3447 enum pipe pch_transcoder)
3449 struct drm_device *dev = crtc->base.dev;
3450 struct drm_i915_private *dev_priv = dev->dev_private;
3451 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3453 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3454 I915_READ(HTOTAL(cpu_transcoder)));
3455 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3456 I915_READ(HBLANK(cpu_transcoder)));
3457 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3458 I915_READ(HSYNC(cpu_transcoder)));
3460 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3461 I915_READ(VTOTAL(cpu_transcoder)));
3462 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3463 I915_READ(VBLANK(cpu_transcoder)));
3464 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3465 I915_READ(VSYNC(cpu_transcoder)));
3466 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3467 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3470 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3472 struct drm_i915_private *dev_priv = dev->dev_private;
3475 temp = I915_READ(SOUTH_CHICKEN1);
3476 if (temp & FDI_BC_BIFURCATION_SELECT)
3479 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3480 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3482 temp |= FDI_BC_BIFURCATION_SELECT;
3483 DRM_DEBUG_KMS("enabling fdi C rx\n");
3484 I915_WRITE(SOUTH_CHICKEN1, temp);
3485 POSTING_READ(SOUTH_CHICKEN1);
3488 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3490 struct drm_device *dev = intel_crtc->base.dev;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3493 switch (intel_crtc->pipe) {
3497 if (intel_crtc->config.fdi_lanes > 2)
3498 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3500 cpt_enable_fdi_bc_bifurcation(dev);
3504 cpt_enable_fdi_bc_bifurcation(dev);
3513 * Enable PCH resources required for PCH ports:
3515 * - FDI training & RX/TX
3516 * - update transcoder timings
3517 * - DP transcoding bits
3520 static void ironlake_pch_enable(struct drm_crtc *crtc)
3522 struct drm_device *dev = crtc->dev;
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3525 int pipe = intel_crtc->pipe;
3528 assert_pch_transcoder_disabled(dev_priv, pipe);
3530 if (IS_IVYBRIDGE(dev))
3531 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3533 /* Write the TU size bits before fdi link training, so that error
3534 * detection works. */
3535 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3536 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3538 /* For PCH output, training FDI link */
3539 dev_priv->display.fdi_link_train(crtc);
3541 /* We need to program the right clock selection before writing the pixel
3542 * mutliplier into the DPLL. */
3543 if (HAS_PCH_CPT(dev)) {
3546 temp = I915_READ(PCH_DPLL_SEL);
3547 temp |= TRANS_DPLL_ENABLE(pipe);
3548 sel = TRANS_DPLLB_SEL(pipe);
3549 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3553 I915_WRITE(PCH_DPLL_SEL, temp);
3556 /* XXX: pch pll's can be enabled any time before we enable the PCH
3557 * transcoder, and we actually should do this to not upset any PCH
3558 * transcoder that already use the clock when we share it.
3560 * Note that enable_shared_dpll tries to do the right thing, but
3561 * get_shared_dpll unconditionally resets the pll - we need that to have
3562 * the right LVDS enable sequence. */
3563 intel_enable_shared_dpll(intel_crtc);
3565 /* set transcoder timing, panel must allow it */
3566 assert_panel_unlocked(dev_priv, pipe);
3567 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3569 intel_fdi_normal_train(crtc);
3571 /* For PCH DP, enable TRANS_DP_CTL */
3572 if (HAS_PCH_CPT(dev) &&
3573 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3574 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3575 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3576 reg = TRANS_DP_CTL(pipe);
3577 temp = I915_READ(reg);
3578 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3579 TRANS_DP_SYNC_MASK |
3581 temp |= (TRANS_DP_OUTPUT_ENABLE |
3582 TRANS_DP_ENH_FRAMING);
3583 temp |= bpc << 9; /* same format but at 11:9 */
3585 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3586 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3587 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3588 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3590 switch (intel_trans_dp_port_sel(crtc)) {
3592 temp |= TRANS_DP_PORT_SEL_B;
3595 temp |= TRANS_DP_PORT_SEL_C;
3598 temp |= TRANS_DP_PORT_SEL_D;
3604 I915_WRITE(reg, temp);
3607 ironlake_enable_pch_transcoder(dev_priv, pipe);
3610 static void lpt_pch_enable(struct drm_crtc *crtc)
3612 struct drm_device *dev = crtc->dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3617 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3619 lpt_program_iclkip(crtc);
3621 /* Set transcoder timing. */
3622 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3624 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3627 void intel_put_shared_dpll(struct intel_crtc *crtc)
3629 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3634 if (pll->refcount == 0) {
3635 WARN(1, "bad %s refcount\n", pll->name);
3639 if (--pll->refcount == 0) {
3641 WARN_ON(pll->active);
3644 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3647 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3649 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3650 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3651 enum intel_dpll_id i;
3654 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3655 crtc->base.base.id, pll->name);
3656 intel_put_shared_dpll(crtc);
3659 if (HAS_PCH_IBX(dev_priv->dev)) {
3660 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3661 i = (enum intel_dpll_id) crtc->pipe;
3662 pll = &dev_priv->shared_dplls[i];
3664 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3665 crtc->base.base.id, pll->name);
3667 WARN_ON(pll->refcount);
3672 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3673 pll = &dev_priv->shared_dplls[i];
3675 /* Only want to check enabled timings first */
3676 if (pll->refcount == 0)
3679 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3680 sizeof(pll->hw_state)) == 0) {
3681 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3683 pll->name, pll->refcount, pll->active);
3689 /* Ok no matching timings, maybe there's a free one? */
3690 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3691 pll = &dev_priv->shared_dplls[i];
3692 if (pll->refcount == 0) {
3693 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3694 crtc->base.base.id, pll->name);
3702 if (pll->refcount == 0)
3703 pll->hw_state = crtc->config.dpll_hw_state;
3705 crtc->config.shared_dpll = i;
3706 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3707 pipe_name(crtc->pipe));
3714 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 int dslreg = PIPEDSL(pipe);
3720 temp = I915_READ(dslreg);
3722 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3723 if (wait_for(I915_READ(dslreg) != temp, 5))
3724 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3728 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3730 struct drm_device *dev = crtc->base.dev;
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 int pipe = crtc->pipe;
3734 if (crtc->config.pch_pfit.enabled) {
3735 /* Force use of hard-coded filter coefficients
3736 * as some pre-programmed values are broken,
3739 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3740 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3741 PF_PIPE_SEL_IVB(pipe));
3743 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3744 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3745 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3749 static void intel_enable_planes(struct drm_crtc *crtc)
3751 struct drm_device *dev = crtc->dev;
3752 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3753 struct drm_plane *plane;
3754 struct intel_plane *intel_plane;
3756 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3757 intel_plane = to_intel_plane(plane);
3758 if (intel_plane->pipe == pipe)
3759 intel_plane_restore(&intel_plane->base);
3763 static void intel_disable_planes(struct drm_crtc *crtc)
3765 struct drm_device *dev = crtc->dev;
3766 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3767 struct drm_plane *plane;
3768 struct intel_plane *intel_plane;
3770 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3771 intel_plane = to_intel_plane(plane);
3772 if (intel_plane->pipe == pipe)
3773 intel_plane_disable(&intel_plane->base);
3777 void hsw_enable_ips(struct intel_crtc *crtc)
3779 struct drm_device *dev = crtc->base.dev;
3780 struct drm_i915_private *dev_priv = dev->dev_private;
3782 if (!crtc->config.ips_enabled)
3785 /* We can only enable IPS after we enable a plane and wait for a vblank */
3786 intel_wait_for_vblank(dev, crtc->pipe);
3788 assert_plane_enabled(dev_priv, crtc->plane);
3789 if (IS_BROADWELL(dev)) {
3790 mutex_lock(&dev_priv->rps.hw_lock);
3791 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3792 mutex_unlock(&dev_priv->rps.hw_lock);
3793 /* Quoting Art Runyan: "its not safe to expect any particular
3794 * value in IPS_CTL bit 31 after enabling IPS through the
3795 * mailbox." Moreover, the mailbox may return a bogus state,
3796 * so we need to just enable it and continue on.
3799 I915_WRITE(IPS_CTL, IPS_ENABLE);
3800 /* The bit only becomes 1 in the next vblank, so this wait here
3801 * is essentially intel_wait_for_vblank. If we don't have this
3802 * and don't wait for vblanks until the end of crtc_enable, then
3803 * the HW state readout code will complain that the expected
3804 * IPS_CTL value is not the one we read. */
3805 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3806 DRM_ERROR("Timed out waiting for IPS enable\n");
3810 void hsw_disable_ips(struct intel_crtc *crtc)
3812 struct drm_device *dev = crtc->base.dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3815 if (!crtc->config.ips_enabled)
3818 assert_plane_enabled(dev_priv, crtc->plane);
3819 if (IS_BROADWELL(dev)) {
3820 mutex_lock(&dev_priv->rps.hw_lock);
3821 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3822 mutex_unlock(&dev_priv->rps.hw_lock);
3823 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3824 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3825 DRM_ERROR("Timed out waiting for IPS disable\n");
3827 I915_WRITE(IPS_CTL, 0);
3828 POSTING_READ(IPS_CTL);
3831 /* We need to wait for a vblank before we can disable the plane. */
3832 intel_wait_for_vblank(dev, crtc->pipe);
3835 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3836 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3838 struct drm_device *dev = crtc->dev;
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3841 enum pipe pipe = intel_crtc->pipe;
3842 int palreg = PALETTE(pipe);
3844 bool reenable_ips = false;
3846 /* The clocks have to be on to load the palette. */
3847 if (!crtc->enabled || !intel_crtc->active)
3850 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3851 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3852 assert_dsi_pll_enabled(dev_priv);
3854 assert_pll_enabled(dev_priv, pipe);
3857 /* use legacy palette for Ironlake */
3858 if (!HAS_GMCH_DISPLAY(dev))
3859 palreg = LGC_PALETTE(pipe);
3861 /* Workaround : Do not read or write the pipe palette/gamma data while
3862 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3864 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3865 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3866 GAMMA_MODE_MODE_SPLIT)) {
3867 hsw_disable_ips(intel_crtc);
3868 reenable_ips = true;
3871 for (i = 0; i < 256; i++) {
3872 I915_WRITE(palreg + 4 * i,
3873 (intel_crtc->lut_r[i] << 16) |
3874 (intel_crtc->lut_g[i] << 8) |
3875 intel_crtc->lut_b[i]);
3879 hsw_enable_ips(intel_crtc);
3882 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3884 if (!enable && intel_crtc->overlay) {
3885 struct drm_device *dev = intel_crtc->base.dev;
3886 struct drm_i915_private *dev_priv = dev->dev_private;
3888 mutex_lock(&dev->struct_mutex);
3889 dev_priv->mm.interruptible = false;
3890 (void) intel_overlay_switch_off(intel_crtc->overlay);
3891 dev_priv->mm.interruptible = true;
3892 mutex_unlock(&dev->struct_mutex);
3895 /* Let userspace switch the overlay on again. In most cases userspace
3896 * has to recompute where to put it anyway.
3900 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3902 struct drm_device *dev = crtc->dev;
3903 struct drm_i915_private *dev_priv = dev->dev_private;
3904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3905 int pipe = intel_crtc->pipe;
3906 int plane = intel_crtc->plane;
3908 drm_vblank_on(dev, pipe);
3910 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3911 intel_enable_planes(crtc);
3912 intel_crtc_update_cursor(crtc, true);
3913 intel_crtc_dpms_overlay(intel_crtc, true);
3915 hsw_enable_ips(intel_crtc);
3917 mutex_lock(&dev->struct_mutex);
3918 intel_update_fbc(dev);
3919 mutex_unlock(&dev->struct_mutex);
3922 * FIXME: Once we grow proper nuclear flip support out of this we need
3923 * to compute the mask of flip planes precisely. For the time being
3924 * consider this a flip from a NULL plane.
3926 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3929 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3931 struct drm_device *dev = crtc->dev;
3932 struct drm_i915_private *dev_priv = dev->dev_private;
3933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3934 int pipe = intel_crtc->pipe;
3935 int plane = intel_crtc->plane;
3937 intel_crtc_wait_for_pending_flips(crtc);
3939 if (dev_priv->fbc.plane == plane)
3940 intel_disable_fbc(dev);
3942 hsw_disable_ips(intel_crtc);
3944 intel_crtc_dpms_overlay(intel_crtc, false);
3945 intel_crtc_update_cursor(crtc, false);
3946 intel_disable_planes(crtc);
3947 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3950 * FIXME: Once we grow proper nuclear flip support out of this we need
3951 * to compute the mask of flip planes precisely. For the time being
3952 * consider this a flip to a NULL plane.
3954 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3956 drm_vblank_off(dev, pipe);
3959 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3961 struct drm_device *dev = crtc->dev;
3962 struct drm_i915_private *dev_priv = dev->dev_private;
3963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3964 struct intel_encoder *encoder;
3965 int pipe = intel_crtc->pipe;
3966 enum plane plane = intel_crtc->plane;
3968 WARN_ON(!crtc->enabled);
3970 if (intel_crtc->active)
3973 if (intel_crtc->config.has_pch_encoder)
3974 intel_prepare_shared_dpll(intel_crtc);
3976 if (intel_crtc->config.has_dp_encoder)
3977 intel_dp_set_m_n(intel_crtc);
3979 intel_set_pipe_timings(intel_crtc);
3981 if (intel_crtc->config.has_pch_encoder) {
3982 intel_cpu_transcoder_set_m_n(intel_crtc,
3983 &intel_crtc->config.fdi_m_n);
3986 ironlake_set_pipeconf(crtc);
3988 /* Set up the display plane register */
3989 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3990 POSTING_READ(DSPCNTR(plane));
3992 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3995 intel_crtc->active = true;
3997 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3998 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4000 for_each_encoder_on_crtc(dev, crtc, encoder)
4001 if (encoder->pre_enable)
4002 encoder->pre_enable(encoder);
4004 if (intel_crtc->config.has_pch_encoder) {
4005 /* Note: FDI PLL enabling _must_ be done before we enable the
4006 * cpu pipes, hence this is separate from all the other fdi/pch
4008 ironlake_fdi_pll_enable(intel_crtc);
4010 assert_fdi_tx_disabled(dev_priv, pipe);
4011 assert_fdi_rx_disabled(dev_priv, pipe);
4014 ironlake_pfit_enable(intel_crtc);
4017 * On ILK+ LUT must be loaded before the pipe is running but with
4020 intel_crtc_load_lut(crtc);
4022 intel_update_watermarks(crtc);
4023 intel_enable_pipe(intel_crtc);
4025 if (intel_crtc->config.has_pch_encoder)
4026 ironlake_pch_enable(crtc);
4028 for_each_encoder_on_crtc(dev, crtc, encoder)
4029 encoder->enable(encoder);
4031 if (HAS_PCH_CPT(dev))
4032 cpt_verify_modeset(dev, intel_crtc->pipe);
4034 intel_crtc_enable_planes(crtc);
4037 /* IPS only exists on ULT machines and is tied to pipe A. */
4038 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4040 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4044 * This implements the workaround described in the "notes" section of the mode
4045 * set sequence documentation. When going from no pipes or single pipe to
4046 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4047 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4049 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4051 struct drm_device *dev = crtc->base.dev;
4052 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4054 /* We want to get the other_active_crtc only if there's only 1 other
4056 for_each_intel_crtc(dev, crtc_it) {
4057 if (!crtc_it->active || crtc_it == crtc)
4060 if (other_active_crtc)
4063 other_active_crtc = crtc_it;
4065 if (!other_active_crtc)
4068 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4069 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4072 static void haswell_crtc_enable(struct drm_crtc *crtc)
4074 struct drm_device *dev = crtc->dev;
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4077 struct intel_encoder *encoder;
4078 int pipe = intel_crtc->pipe;
4079 enum plane plane = intel_crtc->plane;
4081 WARN_ON(!crtc->enabled);
4083 if (intel_crtc->active)
4086 if (intel_crtc_to_shared_dpll(intel_crtc))
4087 intel_enable_shared_dpll(intel_crtc);
4089 if (intel_crtc->config.has_dp_encoder)
4090 intel_dp_set_m_n(intel_crtc);
4092 intel_set_pipe_timings(intel_crtc);
4094 if (intel_crtc->config.has_pch_encoder) {
4095 intel_cpu_transcoder_set_m_n(intel_crtc,
4096 &intel_crtc->config.fdi_m_n);
4099 haswell_set_pipeconf(crtc);
4101 intel_set_pipe_csc(crtc);
4103 /* Set up the display plane register */
4104 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4105 POSTING_READ(DSPCNTR(plane));
4107 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4110 intel_crtc->active = true;
4112 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4113 for_each_encoder_on_crtc(dev, crtc, encoder)
4114 if (encoder->pre_enable)
4115 encoder->pre_enable(encoder);
4117 if (intel_crtc->config.has_pch_encoder) {
4118 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4119 dev_priv->display.fdi_link_train(crtc);
4122 intel_ddi_enable_pipe_clock(intel_crtc);
4124 ironlake_pfit_enable(intel_crtc);
4127 * On ILK+ LUT must be loaded before the pipe is running but with
4130 intel_crtc_load_lut(crtc);
4132 intel_ddi_set_pipe_settings(crtc);
4133 intel_ddi_enable_transcoder_func(crtc);
4135 intel_update_watermarks(crtc);
4136 intel_enable_pipe(intel_crtc);
4138 if (intel_crtc->config.has_pch_encoder)
4139 lpt_pch_enable(crtc);
4141 if (intel_crtc->config.dp_encoder_is_mst)
4142 intel_ddi_set_vc_payload_alloc(crtc, true);
4144 for_each_encoder_on_crtc(dev, crtc, encoder) {
4145 encoder->enable(encoder);
4146 intel_opregion_notify_encoder(encoder, true);
4149 /* If we change the relative order between pipe/planes enabling, we need
4150 * to change the workaround. */
4151 haswell_mode_set_planes_workaround(intel_crtc);
4152 intel_crtc_enable_planes(crtc);
4155 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4157 struct drm_device *dev = crtc->base.dev;
4158 struct drm_i915_private *dev_priv = dev->dev_private;
4159 int pipe = crtc->pipe;
4161 /* To avoid upsetting the power well on haswell only disable the pfit if
4162 * it's in use. The hw state code will make sure we get this right. */
4163 if (crtc->config.pch_pfit.enabled) {
4164 I915_WRITE(PF_CTL(pipe), 0);
4165 I915_WRITE(PF_WIN_POS(pipe), 0);
4166 I915_WRITE(PF_WIN_SZ(pipe), 0);
4170 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4172 struct drm_device *dev = crtc->dev;
4173 struct drm_i915_private *dev_priv = dev->dev_private;
4174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4175 struct intel_encoder *encoder;
4176 int pipe = intel_crtc->pipe;
4179 if (!intel_crtc->active)
4182 intel_crtc_disable_planes(crtc);
4184 for_each_encoder_on_crtc(dev, crtc, encoder)
4185 encoder->disable(encoder);
4187 if (intel_crtc->config.has_pch_encoder)
4188 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4190 intel_disable_pipe(dev_priv, pipe);
4192 if (intel_crtc->config.dp_encoder_is_mst)
4193 intel_ddi_set_vc_payload_alloc(crtc, false);
4195 ironlake_pfit_disable(intel_crtc);
4197 for_each_encoder_on_crtc(dev, crtc, encoder)
4198 if (encoder->post_disable)
4199 encoder->post_disable(encoder);
4201 if (intel_crtc->config.has_pch_encoder) {
4202 ironlake_fdi_disable(crtc);
4204 ironlake_disable_pch_transcoder(dev_priv, pipe);
4205 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4207 if (HAS_PCH_CPT(dev)) {
4208 /* disable TRANS_DP_CTL */
4209 reg = TRANS_DP_CTL(pipe);
4210 temp = I915_READ(reg);
4211 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4212 TRANS_DP_PORT_SEL_MASK);
4213 temp |= TRANS_DP_PORT_SEL_NONE;
4214 I915_WRITE(reg, temp);
4216 /* disable DPLL_SEL */
4217 temp = I915_READ(PCH_DPLL_SEL);
4218 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4219 I915_WRITE(PCH_DPLL_SEL, temp);
4222 /* disable PCH DPLL */
4223 intel_disable_shared_dpll(intel_crtc);
4225 ironlake_fdi_pll_disable(intel_crtc);
4228 intel_crtc->active = false;
4229 intel_update_watermarks(crtc);
4231 mutex_lock(&dev->struct_mutex);
4232 intel_update_fbc(dev);
4233 mutex_unlock(&dev->struct_mutex);
4236 static void haswell_crtc_disable(struct drm_crtc *crtc)
4238 struct drm_device *dev = crtc->dev;
4239 struct drm_i915_private *dev_priv = dev->dev_private;
4240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4241 struct intel_encoder *encoder;
4242 int pipe = intel_crtc->pipe;
4243 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4245 if (!intel_crtc->active)
4248 intel_crtc_disable_planes(crtc);
4250 for_each_encoder_on_crtc(dev, crtc, encoder) {
4251 intel_opregion_notify_encoder(encoder, false);
4252 encoder->disable(encoder);
4255 if (intel_crtc->config.has_pch_encoder)
4256 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4257 intel_disable_pipe(dev_priv, pipe);
4259 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4261 ironlake_pfit_disable(intel_crtc);
4263 intel_ddi_disable_pipe_clock(intel_crtc);
4265 if (intel_crtc->config.has_pch_encoder) {
4266 lpt_disable_pch_transcoder(dev_priv);
4267 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4268 intel_ddi_fdi_disable(crtc);
4271 for_each_encoder_on_crtc(dev, crtc, encoder)
4272 if (encoder->post_disable)
4273 encoder->post_disable(encoder);
4275 intel_crtc->active = false;
4276 intel_update_watermarks(crtc);
4278 mutex_lock(&dev->struct_mutex);
4279 intel_update_fbc(dev);
4280 mutex_unlock(&dev->struct_mutex);
4282 if (intel_crtc_to_shared_dpll(intel_crtc))
4283 intel_disable_shared_dpll(intel_crtc);
4286 static void ironlake_crtc_off(struct drm_crtc *crtc)
4288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4289 intel_put_shared_dpll(intel_crtc);
4293 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4295 struct drm_device *dev = crtc->base.dev;
4296 struct drm_i915_private *dev_priv = dev->dev_private;
4297 struct intel_crtc_config *pipe_config = &crtc->config;
4299 if (!crtc->config.gmch_pfit.control)
4303 * The panel fitter should only be adjusted whilst the pipe is disabled,
4304 * according to register description and PRM.
4306 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4307 assert_pipe_disabled(dev_priv, crtc->pipe);
4309 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4310 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4312 /* Border color in case we don't scale up to the full screen. Black by
4313 * default, change to something else for debugging. */
4314 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4317 static enum intel_display_power_domain port_to_power_domain(enum port port)
4321 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4323 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4325 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4327 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4330 return POWER_DOMAIN_PORT_OTHER;
4334 #define for_each_power_domain(domain, mask) \
4335 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4336 if ((1 << (domain)) & (mask))
4338 enum intel_display_power_domain
4339 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4341 struct drm_device *dev = intel_encoder->base.dev;
4342 struct intel_digital_port *intel_dig_port;
4344 switch (intel_encoder->type) {
4345 case INTEL_OUTPUT_UNKNOWN:
4346 /* Only DDI platforms should ever use this output type */
4347 WARN_ON_ONCE(!HAS_DDI(dev));
4348 case INTEL_OUTPUT_DISPLAYPORT:
4349 case INTEL_OUTPUT_HDMI:
4350 case INTEL_OUTPUT_EDP:
4351 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4352 return port_to_power_domain(intel_dig_port->port);
4353 case INTEL_OUTPUT_DP_MST:
4354 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4355 return port_to_power_domain(intel_dig_port->port);
4356 case INTEL_OUTPUT_ANALOG:
4357 return POWER_DOMAIN_PORT_CRT;
4358 case INTEL_OUTPUT_DSI:
4359 return POWER_DOMAIN_PORT_DSI;
4361 return POWER_DOMAIN_PORT_OTHER;
4365 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4367 struct drm_device *dev = crtc->dev;
4368 struct intel_encoder *intel_encoder;
4369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4370 enum pipe pipe = intel_crtc->pipe;
4372 enum transcoder transcoder;
4374 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4376 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4377 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4378 if (intel_crtc->config.pch_pfit.enabled ||
4379 intel_crtc->config.pch_pfit.force_thru)
4380 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4382 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4383 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4388 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4391 if (dev_priv->power_domains.init_power_on == enable)
4395 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4397 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4399 dev_priv->power_domains.init_power_on = enable;
4402 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4404 struct drm_i915_private *dev_priv = dev->dev_private;
4405 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4406 struct intel_crtc *crtc;
4409 * First get all needed power domains, then put all unneeded, to avoid
4410 * any unnecessary toggling of the power wells.
4412 for_each_intel_crtc(dev, crtc) {
4413 enum intel_display_power_domain domain;
4415 if (!crtc->base.enabled)
4418 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4420 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4421 intel_display_power_get(dev_priv, domain);
4424 for_each_intel_crtc(dev, crtc) {
4425 enum intel_display_power_domain domain;
4427 for_each_power_domain(domain, crtc->enabled_power_domains)
4428 intel_display_power_put(dev_priv, domain);
4430 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4433 intel_display_set_init_power(dev_priv, false);
4436 /* returns HPLL frequency in kHz */
4437 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4439 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4441 /* Obtain SKU information */
4442 mutex_lock(&dev_priv->dpio_lock);
4443 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4444 CCK_FUSE_HPLL_FREQ_MASK;
4445 mutex_unlock(&dev_priv->dpio_lock);
4447 return vco_freq[hpll_freq] * 1000;
4450 static void vlv_update_cdclk(struct drm_device *dev)
4452 struct drm_i915_private *dev_priv = dev->dev_private;
4454 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4455 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4456 dev_priv->vlv_cdclk_freq);
4459 * Program the gmbus_freq based on the cdclk frequency.
4460 * BSpec erroneously claims we should aim for 4MHz, but
4461 * in fact 1MHz is the correct frequency.
4463 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4466 /* Adjust CDclk dividers to allow high res or save power if possible */
4467 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4469 struct drm_i915_private *dev_priv = dev->dev_private;
4472 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4474 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4476 else if (cdclk == 266667)
4481 mutex_lock(&dev_priv->rps.hw_lock);
4482 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4483 val &= ~DSPFREQGUAR_MASK;
4484 val |= (cmd << DSPFREQGUAR_SHIFT);
4485 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4486 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4487 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4489 DRM_ERROR("timed out waiting for CDclk change\n");
4491 mutex_unlock(&dev_priv->rps.hw_lock);
4493 if (cdclk == 400000) {
4496 vco = valleyview_get_vco(dev_priv);
4497 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4499 mutex_lock(&dev_priv->dpio_lock);
4500 /* adjust cdclk divider */
4501 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4502 val &= ~DISPLAY_FREQUENCY_VALUES;
4504 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4506 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4507 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4509 DRM_ERROR("timed out waiting for CDclk change\n");
4510 mutex_unlock(&dev_priv->dpio_lock);
4513 mutex_lock(&dev_priv->dpio_lock);
4514 /* adjust self-refresh exit latency value */
4515 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4519 * For high bandwidth configs, we set a higher latency in the bunit
4520 * so that the core display fetch happens in time to avoid underruns.
4522 if (cdclk == 400000)
4523 val |= 4500 / 250; /* 4.5 usec */
4525 val |= 3000 / 250; /* 3.0 usec */
4526 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4527 mutex_unlock(&dev_priv->dpio_lock);
4529 vlv_update_cdclk(dev);
4532 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4535 int vco = valleyview_get_vco(dev_priv);
4536 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4539 * Really only a few cases to deal with, as only 4 CDclks are supported:
4542 * 320/333MHz (depends on HPLL freq)
4544 * So we check to see whether we're above 90% of the lower bin and
4547 * We seem to get an unstable or solid color picture at 200MHz.
4548 * Not sure what's wrong. For now use 200MHz only when all pipes
4551 if (max_pixclk > freq_320*9/10)
4553 else if (max_pixclk > 266667*9/10)
4555 else if (max_pixclk > 0)
4561 /* compute the max pixel clock for new configuration */
4562 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4564 struct drm_device *dev = dev_priv->dev;
4565 struct intel_crtc *intel_crtc;
4568 for_each_intel_crtc(dev, intel_crtc) {
4569 if (intel_crtc->new_enabled)
4570 max_pixclk = max(max_pixclk,
4571 intel_crtc->new_config->adjusted_mode.crtc_clock);
4577 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4578 unsigned *prepare_pipes)
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 struct intel_crtc *intel_crtc;
4582 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4584 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4585 dev_priv->vlv_cdclk_freq)
4588 /* disable/enable all currently active pipes while we change cdclk */
4589 for_each_intel_crtc(dev, intel_crtc)
4590 if (intel_crtc->base.enabled)
4591 *prepare_pipes |= (1 << intel_crtc->pipe);
4594 static void valleyview_modeset_global_resources(struct drm_device *dev)
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4598 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4600 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4601 valleyview_set_cdclk(dev, req_cdclk);
4602 modeset_update_crtc_power_domains(dev);
4605 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4607 struct drm_device *dev = crtc->dev;
4608 struct drm_i915_private *dev_priv = dev->dev_private;
4609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4610 struct intel_encoder *encoder;
4611 int pipe = intel_crtc->pipe;
4612 int plane = intel_crtc->plane;
4616 WARN_ON(!crtc->enabled);
4618 if (intel_crtc->active)
4621 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4623 if (!is_dsi && !IS_CHERRYVIEW(dev))
4624 vlv_prepare_pll(intel_crtc);
4626 /* Set up the display plane register */
4627 dspcntr = DISPPLANE_GAMMA_ENABLE;
4629 if (intel_crtc->config.has_dp_encoder)
4630 intel_dp_set_m_n(intel_crtc);
4632 intel_set_pipe_timings(intel_crtc);
4634 /* pipesrc and dspsize control the size that is scaled from,
4635 * which should always be the user's requested size.
4637 I915_WRITE(DSPSIZE(plane),
4638 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4639 (intel_crtc->config.pipe_src_w - 1));
4640 I915_WRITE(DSPPOS(plane), 0);
4642 i9xx_set_pipeconf(intel_crtc);
4644 I915_WRITE(DSPCNTR(plane), dspcntr);
4645 POSTING_READ(DSPCNTR(plane));
4647 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4650 intel_crtc->active = true;
4652 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4654 for_each_encoder_on_crtc(dev, crtc, encoder)
4655 if (encoder->pre_pll_enable)
4656 encoder->pre_pll_enable(encoder);
4659 if (IS_CHERRYVIEW(dev))
4660 chv_enable_pll(intel_crtc);
4662 vlv_enable_pll(intel_crtc);
4665 for_each_encoder_on_crtc(dev, crtc, encoder)
4666 if (encoder->pre_enable)
4667 encoder->pre_enable(encoder);
4669 i9xx_pfit_enable(intel_crtc);
4671 intel_crtc_load_lut(crtc);
4673 intel_update_watermarks(crtc);
4674 intel_enable_pipe(intel_crtc);
4676 for_each_encoder_on_crtc(dev, crtc, encoder)
4677 encoder->enable(encoder);
4679 intel_crtc_enable_planes(crtc);
4681 /* Underruns don't raise interrupts, so check manually. */
4682 i9xx_check_fifo_underruns(dev);
4685 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4687 struct drm_device *dev = crtc->base.dev;
4688 struct drm_i915_private *dev_priv = dev->dev_private;
4690 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4691 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4694 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4696 struct drm_device *dev = crtc->dev;
4697 struct drm_i915_private *dev_priv = dev->dev_private;
4698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4699 struct intel_encoder *encoder;
4700 int pipe = intel_crtc->pipe;
4701 int plane = intel_crtc->plane;
4704 WARN_ON(!crtc->enabled);
4706 if (intel_crtc->active)
4709 i9xx_set_pll_dividers(intel_crtc);
4711 /* Set up the display plane register */
4712 dspcntr = DISPPLANE_GAMMA_ENABLE;
4715 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4717 dspcntr |= DISPPLANE_SEL_PIPE_B;
4719 if (intel_crtc->config.has_dp_encoder)
4720 intel_dp_set_m_n(intel_crtc);
4722 intel_set_pipe_timings(intel_crtc);
4724 /* pipesrc and dspsize control the size that is scaled from,
4725 * which should always be the user's requested size.
4727 I915_WRITE(DSPSIZE(plane),
4728 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4729 (intel_crtc->config.pipe_src_w - 1));
4730 I915_WRITE(DSPPOS(plane), 0);
4732 i9xx_set_pipeconf(intel_crtc);
4734 I915_WRITE(DSPCNTR(plane), dspcntr);
4735 POSTING_READ(DSPCNTR(plane));
4737 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4740 intel_crtc->active = true;
4743 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4745 for_each_encoder_on_crtc(dev, crtc, encoder)
4746 if (encoder->pre_enable)
4747 encoder->pre_enable(encoder);
4749 i9xx_enable_pll(intel_crtc);
4751 i9xx_pfit_enable(intel_crtc);
4753 intel_crtc_load_lut(crtc);
4755 intel_update_watermarks(crtc);
4756 intel_enable_pipe(intel_crtc);
4758 for_each_encoder_on_crtc(dev, crtc, encoder)
4759 encoder->enable(encoder);
4761 intel_crtc_enable_planes(crtc);
4764 * Gen2 reports pipe underruns whenever all planes are disabled.
4765 * So don't enable underrun reporting before at least some planes
4767 * FIXME: Need to fix the logic to work when we turn off all planes
4768 * but leave the pipe running.
4771 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4773 /* Underruns don't raise interrupts, so check manually. */
4774 i9xx_check_fifo_underruns(dev);
4777 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4779 struct drm_device *dev = crtc->base.dev;
4780 struct drm_i915_private *dev_priv = dev->dev_private;
4782 if (!crtc->config.gmch_pfit.control)
4785 assert_pipe_disabled(dev_priv, crtc->pipe);
4787 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4788 I915_READ(PFIT_CONTROL));
4789 I915_WRITE(PFIT_CONTROL, 0);
4792 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4794 struct drm_device *dev = crtc->dev;
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4797 struct intel_encoder *encoder;
4798 int pipe = intel_crtc->pipe;
4800 if (!intel_crtc->active)
4804 * Gen2 reports pipe underruns whenever all planes are disabled.
4805 * So diasble underrun reporting before all the planes get disabled.
4806 * FIXME: Need to fix the logic to work when we turn off all planes
4807 * but leave the pipe running.
4810 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4813 * Vblank time updates from the shadow to live plane control register
4814 * are blocked if the memory self-refresh mode is active at that
4815 * moment. So to make sure the plane gets truly disabled, disable
4816 * first the self-refresh mode. The self-refresh enable bit in turn
4817 * will be checked/applied by the HW only at the next frame start
4818 * event which is after the vblank start event, so we need to have a
4819 * wait-for-vblank between disabling the plane and the pipe.
4821 intel_set_memory_cxsr(dev_priv, false);
4822 intel_crtc_disable_planes(crtc);
4824 for_each_encoder_on_crtc(dev, crtc, encoder)
4825 encoder->disable(encoder);
4828 * On gen2 planes are double buffered but the pipe isn't, so we must
4829 * wait for planes to fully turn off before disabling the pipe.
4830 * We also need to wait on all gmch platforms because of the
4831 * self-refresh mode constraint explained above.
4833 intel_wait_for_vblank(dev, pipe);
4835 intel_disable_pipe(dev_priv, pipe);
4837 i9xx_pfit_disable(intel_crtc);
4839 for_each_encoder_on_crtc(dev, crtc, encoder)
4840 if (encoder->post_disable)
4841 encoder->post_disable(encoder);
4843 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4844 if (IS_CHERRYVIEW(dev))
4845 chv_disable_pll(dev_priv, pipe);
4846 else if (IS_VALLEYVIEW(dev))
4847 vlv_disable_pll(dev_priv, pipe);
4849 i9xx_disable_pll(dev_priv, pipe);
4853 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4855 intel_crtc->active = false;
4856 intel_update_watermarks(crtc);
4858 mutex_lock(&dev->struct_mutex);
4859 intel_update_fbc(dev);
4860 mutex_unlock(&dev->struct_mutex);
4863 static void i9xx_crtc_off(struct drm_crtc *crtc)
4867 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4870 struct drm_device *dev = crtc->dev;
4871 struct drm_i915_master_private *master_priv;
4872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4873 int pipe = intel_crtc->pipe;
4875 if (!dev->primary->master)
4878 master_priv = dev->primary->master->driver_priv;
4879 if (!master_priv->sarea_priv)
4884 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4885 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4888 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4889 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4892 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4897 /* Master function to enable/disable CRTC and corresponding power wells */
4898 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4900 struct drm_device *dev = crtc->dev;
4901 struct drm_i915_private *dev_priv = dev->dev_private;
4902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4903 enum intel_display_power_domain domain;
4904 unsigned long domains;
4907 if (!intel_crtc->active) {
4908 domains = get_crtc_power_domains(crtc);
4909 for_each_power_domain(domain, domains)
4910 intel_display_power_get(dev_priv, domain);
4911 intel_crtc->enabled_power_domains = domains;
4913 dev_priv->display.crtc_enable(crtc);
4916 if (intel_crtc->active) {
4917 dev_priv->display.crtc_disable(crtc);
4919 domains = intel_crtc->enabled_power_domains;
4920 for_each_power_domain(domain, domains)
4921 intel_display_power_put(dev_priv, domain);
4922 intel_crtc->enabled_power_domains = 0;
4928 * Sets the power management mode of the pipe and plane.
4930 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4932 struct drm_device *dev = crtc->dev;
4933 struct intel_encoder *intel_encoder;
4934 bool enable = false;
4936 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4937 enable |= intel_encoder->connectors_active;
4939 intel_crtc_control(crtc, enable);
4941 intel_crtc_update_sarea(crtc, enable);
4944 static void intel_crtc_disable(struct drm_crtc *crtc)
4946 struct drm_device *dev = crtc->dev;
4947 struct drm_connector *connector;
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4950 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4952 /* crtc should still be enabled when we disable it. */
4953 WARN_ON(!crtc->enabled);
4955 dev_priv->display.crtc_disable(crtc);
4956 intel_crtc_update_sarea(crtc, false);
4957 dev_priv->display.off(crtc);
4959 if (crtc->primary->fb) {
4960 mutex_lock(&dev->struct_mutex);
4961 intel_unpin_fb_obj(old_obj);
4962 i915_gem_track_fb(old_obj, NULL,
4963 INTEL_FRONTBUFFER_PRIMARY(pipe));
4964 mutex_unlock(&dev->struct_mutex);
4965 crtc->primary->fb = NULL;
4968 /* Update computed state. */
4969 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4970 if (!connector->encoder || !connector->encoder->crtc)
4973 if (connector->encoder->crtc != crtc)
4976 connector->dpms = DRM_MODE_DPMS_OFF;
4977 to_intel_encoder(connector->encoder)->connectors_active = false;
4981 void intel_encoder_destroy(struct drm_encoder *encoder)
4983 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4985 drm_encoder_cleanup(encoder);
4986 kfree(intel_encoder);
4989 /* Simple dpms helper for encoders with just one connector, no cloning and only
4990 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4991 * state of the entire output pipe. */
4992 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4994 if (mode == DRM_MODE_DPMS_ON) {
4995 encoder->connectors_active = true;
4997 intel_crtc_update_dpms(encoder->base.crtc);
4999 encoder->connectors_active = false;
5001 intel_crtc_update_dpms(encoder->base.crtc);
5005 /* Cross check the actual hw state with our own modeset state tracking (and it's
5006 * internal consistency). */
5007 static void intel_connector_check_state(struct intel_connector *connector)
5009 if (connector->get_hw_state(connector)) {
5010 struct intel_encoder *encoder = connector->encoder;
5011 struct drm_crtc *crtc;
5012 bool encoder_enabled;
5015 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5016 connector->base.base.id,
5017 connector->base.name);
5019 /* there is no real hw state for MST connectors */
5020 if (connector->mst_port)
5023 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5024 "wrong connector dpms state\n");
5025 WARN(connector->base.encoder != &encoder->base,
5026 "active connector not linked to encoder\n");
5029 WARN(!encoder->connectors_active,
5030 "encoder->connectors_active not set\n");
5032 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5033 WARN(!encoder_enabled, "encoder not enabled\n");
5034 if (WARN_ON(!encoder->base.crtc))
5037 crtc = encoder->base.crtc;
5039 WARN(!crtc->enabled, "crtc not enabled\n");
5040 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5041 WARN(pipe != to_intel_crtc(crtc)->pipe,
5042 "encoder active on the wrong pipe\n");
5047 /* Even simpler default implementation, if there's really no special case to
5049 void intel_connector_dpms(struct drm_connector *connector, int mode)
5051 /* All the simple cases only support two dpms states. */
5052 if (mode != DRM_MODE_DPMS_ON)
5053 mode = DRM_MODE_DPMS_OFF;
5055 if (mode == connector->dpms)
5058 connector->dpms = mode;
5060 /* Only need to change hw state when actually enabled */
5061 if (connector->encoder)
5062 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5064 intel_modeset_check_state(connector->dev);
5067 /* Simple connector->get_hw_state implementation for encoders that support only
5068 * one connector and no cloning and hence the encoder state determines the state
5069 * of the connector. */
5070 bool intel_connector_get_hw_state(struct intel_connector *connector)
5073 struct intel_encoder *encoder = connector->encoder;
5075 return encoder->get_hw_state(encoder, &pipe);
5078 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5079 struct intel_crtc_config *pipe_config)
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 struct intel_crtc *pipe_B_crtc =
5083 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5085 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5086 pipe_name(pipe), pipe_config->fdi_lanes);
5087 if (pipe_config->fdi_lanes > 4) {
5088 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5089 pipe_name(pipe), pipe_config->fdi_lanes);
5093 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5094 if (pipe_config->fdi_lanes > 2) {
5095 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5096 pipe_config->fdi_lanes);
5103 if (INTEL_INFO(dev)->num_pipes == 2)
5106 /* Ivybridge 3 pipe is really complicated */
5111 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5112 pipe_config->fdi_lanes > 2) {
5113 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5114 pipe_name(pipe), pipe_config->fdi_lanes);
5119 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5120 pipe_B_crtc->config.fdi_lanes <= 2) {
5121 if (pipe_config->fdi_lanes > 2) {
5122 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5123 pipe_name(pipe), pipe_config->fdi_lanes);
5127 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5137 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5138 struct intel_crtc_config *pipe_config)
5140 struct drm_device *dev = intel_crtc->base.dev;
5141 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5142 int lane, link_bw, fdi_dotclock;
5143 bool setup_ok, needs_recompute = false;
5146 /* FDI is a binary signal running at ~2.7GHz, encoding
5147 * each output octet as 10 bits. The actual frequency
5148 * is stored as a divider into a 100MHz clock, and the
5149 * mode pixel clock is stored in units of 1KHz.
5150 * Hence the bw of each lane in terms of the mode signal
5153 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5155 fdi_dotclock = adjusted_mode->crtc_clock;
5157 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5158 pipe_config->pipe_bpp);
5160 pipe_config->fdi_lanes = lane;
5162 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5163 link_bw, &pipe_config->fdi_m_n);
5165 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5166 intel_crtc->pipe, pipe_config);
5167 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5168 pipe_config->pipe_bpp -= 2*3;
5169 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5170 pipe_config->pipe_bpp);
5171 needs_recompute = true;
5172 pipe_config->bw_constrained = true;
5177 if (needs_recompute)
5180 return setup_ok ? 0 : -EINVAL;
5183 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5184 struct intel_crtc_config *pipe_config)
5186 pipe_config->ips_enabled = i915.enable_ips &&
5187 hsw_crtc_supports_ips(crtc) &&
5188 pipe_config->pipe_bpp <= 24;
5191 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5192 struct intel_crtc_config *pipe_config)
5194 struct drm_device *dev = crtc->base.dev;
5195 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5197 /* FIXME should check pixel clock limits on all platforms */
5198 if (INTEL_INFO(dev)->gen < 4) {
5199 struct drm_i915_private *dev_priv = dev->dev_private;
5201 dev_priv->display.get_display_clock_speed(dev);
5204 * Enable pixel doubling when the dot clock
5205 * is > 90% of the (display) core speed.
5207 * GDG double wide on either pipe,
5208 * otherwise pipe A only.
5210 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5211 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5213 pipe_config->double_wide = true;
5216 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5221 * Pipe horizontal size must be even in:
5223 * - LVDS dual channel mode
5224 * - Double wide pipe
5226 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5227 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5228 pipe_config->pipe_src_w &= ~1;
5230 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5231 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5233 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5234 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5237 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5238 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5239 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5240 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5242 pipe_config->pipe_bpp = 8*3;
5246 hsw_compute_ips_config(crtc, pipe_config);
5249 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5250 * old clock survives for now.
5252 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5253 pipe_config->shared_dpll = crtc->config.shared_dpll;
5255 if (pipe_config->has_pch_encoder)
5256 return ironlake_fdi_compute_config(crtc, pipe_config);
5261 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5263 struct drm_i915_private *dev_priv = dev->dev_private;
5264 int vco = valleyview_get_vco(dev_priv);
5268 mutex_lock(&dev_priv->dpio_lock);
5269 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5270 mutex_unlock(&dev_priv->dpio_lock);
5272 divider = val & DISPLAY_FREQUENCY_VALUES;
5274 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5275 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5276 "cdclk change in progress\n");
5278 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5281 static int i945_get_display_clock_speed(struct drm_device *dev)
5286 static int i915_get_display_clock_speed(struct drm_device *dev)
5291 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5296 static int pnv_get_display_clock_speed(struct drm_device *dev)
5300 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5302 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5303 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5305 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5307 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5309 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5312 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5313 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5315 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5320 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5324 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5326 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5329 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5330 case GC_DISPLAY_CLOCK_333_MHZ:
5333 case GC_DISPLAY_CLOCK_190_200_MHZ:
5339 static int i865_get_display_clock_speed(struct drm_device *dev)
5344 static int i855_get_display_clock_speed(struct drm_device *dev)
5347 /* Assume that the hardware is in the high speed state. This
5348 * should be the default.
5350 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5351 case GC_CLOCK_133_200:
5352 case GC_CLOCK_100_200:
5354 case GC_CLOCK_166_250:
5356 case GC_CLOCK_100_133:
5360 /* Shouldn't happen */
5364 static int i830_get_display_clock_speed(struct drm_device *dev)
5370 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5372 while (*num > DATA_LINK_M_N_MASK ||
5373 *den > DATA_LINK_M_N_MASK) {
5379 static void compute_m_n(unsigned int m, unsigned int n,
5380 uint32_t *ret_m, uint32_t *ret_n)
5382 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5383 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5384 intel_reduce_m_n_ratio(ret_m, ret_n);
5388 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5389 int pixel_clock, int link_clock,
5390 struct intel_link_m_n *m_n)
5394 compute_m_n(bits_per_pixel * pixel_clock,
5395 link_clock * nlanes * 8,
5396 &m_n->gmch_m, &m_n->gmch_n);
5398 compute_m_n(pixel_clock, link_clock,
5399 &m_n->link_m, &m_n->link_n);
5402 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5404 if (i915.panel_use_ssc >= 0)
5405 return i915.panel_use_ssc != 0;
5406 return dev_priv->vbt.lvds_use_ssc
5407 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5410 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5412 struct drm_device *dev = crtc->dev;
5413 struct drm_i915_private *dev_priv = dev->dev_private;
5416 if (IS_VALLEYVIEW(dev)) {
5418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5419 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5420 refclk = dev_priv->vbt.lvds_ssc_freq;
5421 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5422 } else if (!IS_GEN2(dev)) {
5431 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5433 return (1 << dpll->n) << 16 | dpll->m2;
5436 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5438 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5441 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5442 intel_clock_t *reduced_clock)
5444 struct drm_device *dev = crtc->base.dev;
5447 if (IS_PINEVIEW(dev)) {
5448 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5450 fp2 = pnv_dpll_compute_fp(reduced_clock);
5452 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5454 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5457 crtc->config.dpll_hw_state.fp0 = fp;
5459 crtc->lowfreq_avail = false;
5460 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5461 reduced_clock && i915.powersave) {
5462 crtc->config.dpll_hw_state.fp1 = fp2;
5463 crtc->lowfreq_avail = true;
5465 crtc->config.dpll_hw_state.fp1 = fp;
5469 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5475 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5476 * and set it to a reasonable value instead.
5478 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5479 reg_val &= 0xffffff00;
5480 reg_val |= 0x00000030;
5481 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5483 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5484 reg_val &= 0x8cffffff;
5485 reg_val = 0x8c000000;
5486 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5488 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5489 reg_val &= 0xffffff00;
5490 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5492 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5493 reg_val &= 0x00ffffff;
5494 reg_val |= 0xb0000000;
5495 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5498 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5499 struct intel_link_m_n *m_n)
5501 struct drm_device *dev = crtc->base.dev;
5502 struct drm_i915_private *dev_priv = dev->dev_private;
5503 int pipe = crtc->pipe;
5505 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5506 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5507 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5508 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5511 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5512 struct intel_link_m_n *m_n)
5514 struct drm_device *dev = crtc->base.dev;
5515 struct drm_i915_private *dev_priv = dev->dev_private;
5516 int pipe = crtc->pipe;
5517 enum transcoder transcoder = crtc->config.cpu_transcoder;
5519 if (INTEL_INFO(dev)->gen >= 5) {
5520 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5521 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5522 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5523 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5525 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5526 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5527 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5528 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5532 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5534 if (crtc->config.has_pch_encoder)
5535 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5537 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5540 static void vlv_update_pll(struct intel_crtc *crtc)
5545 * Enable DPIO clock input. We should never disable the reference
5546 * clock for pipe B, since VGA hotplug / manual detection depends
5549 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5550 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5551 /* We should never disable this, set it here for state tracking */
5552 if (crtc->pipe == PIPE_B)
5553 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5554 dpll |= DPLL_VCO_ENABLE;
5555 crtc->config.dpll_hw_state.dpll = dpll;
5557 dpll_md = (crtc->config.pixel_multiplier - 1)
5558 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5559 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5562 static void vlv_prepare_pll(struct intel_crtc *crtc)
5564 struct drm_device *dev = crtc->base.dev;
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566 int pipe = crtc->pipe;
5568 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5569 u32 coreclk, reg_val;
5571 mutex_lock(&dev_priv->dpio_lock);
5573 bestn = crtc->config.dpll.n;
5574 bestm1 = crtc->config.dpll.m1;
5575 bestm2 = crtc->config.dpll.m2;
5576 bestp1 = crtc->config.dpll.p1;
5577 bestp2 = crtc->config.dpll.p2;
5579 /* See eDP HDMI DPIO driver vbios notes doc */
5581 /* PLL B needs special handling */
5583 vlv_pllb_recal_opamp(dev_priv, pipe);
5585 /* Set up Tx target for periodic Rcomp update */
5586 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5588 /* Disable target IRef on PLL */
5589 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5590 reg_val &= 0x00ffffff;
5591 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5593 /* Disable fast lock */
5594 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5596 /* Set idtafcrecal before PLL is enabled */
5597 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5598 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5599 mdiv |= ((bestn << DPIO_N_SHIFT));
5600 mdiv |= (1 << DPIO_K_SHIFT);
5603 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5604 * but we don't support that).
5605 * Note: don't use the DAC post divider as it seems unstable.
5607 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5608 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5610 mdiv |= DPIO_ENABLE_CALIBRATION;
5611 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5613 /* Set HBR and RBR LPF coefficients */
5614 if (crtc->config.port_clock == 162000 ||
5615 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5616 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5617 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5620 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5623 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5624 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5625 /* Use SSC source */
5627 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5630 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5632 } else { /* HDMI or VGA */
5633 /* Use bend source */
5635 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5638 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5642 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5643 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5644 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5645 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5646 coreclk |= 0x01000000;
5647 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5649 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5650 mutex_unlock(&dev_priv->dpio_lock);
5653 static void chv_update_pll(struct intel_crtc *crtc)
5655 struct drm_device *dev = crtc->base.dev;
5656 struct drm_i915_private *dev_priv = dev->dev_private;
5657 int pipe = crtc->pipe;
5658 int dpll_reg = DPLL(crtc->pipe);
5659 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5660 u32 loopfilter, intcoeff;
5661 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5664 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5665 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5668 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5670 crtc->config.dpll_hw_state.dpll_md =
5671 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5673 bestn = crtc->config.dpll.n;
5674 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5675 bestm1 = crtc->config.dpll.m1;
5676 bestm2 = crtc->config.dpll.m2 >> 22;
5677 bestp1 = crtc->config.dpll.p1;
5678 bestp2 = crtc->config.dpll.p2;
5681 * Enable Refclk and SSC
5683 I915_WRITE(dpll_reg,
5684 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5686 mutex_lock(&dev_priv->dpio_lock);
5688 /* p1 and p2 divider */
5689 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5690 5 << DPIO_CHV_S1_DIV_SHIFT |
5691 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5692 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5693 1 << DPIO_CHV_K_DIV_SHIFT);
5695 /* Feedback post-divider - m2 */
5696 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5698 /* Feedback refclk divider - n and m1 */
5699 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5700 DPIO_CHV_M1_DIV_BY_2 |
5701 1 << DPIO_CHV_N_DIV_SHIFT);
5703 /* M2 fraction division */
5704 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5706 /* M2 fraction division enable */
5707 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5708 DPIO_CHV_FRAC_DIV_EN |
5709 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5712 refclk = i9xx_get_refclk(&crtc->base, 0);
5713 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5714 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5715 if (refclk == 100000)
5717 else if (refclk == 38400)
5721 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5722 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5725 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5726 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5729 mutex_unlock(&dev_priv->dpio_lock);
5732 static void i9xx_update_pll(struct intel_crtc *crtc,
5733 intel_clock_t *reduced_clock,
5736 struct drm_device *dev = crtc->base.dev;
5737 struct drm_i915_private *dev_priv = dev->dev_private;
5740 struct dpll *clock = &crtc->config.dpll;
5742 i9xx_update_pll_dividers(crtc, reduced_clock);
5744 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5745 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5747 dpll = DPLL_VGA_MODE_DIS;
5749 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5750 dpll |= DPLLB_MODE_LVDS;
5752 dpll |= DPLLB_MODE_DAC_SERIAL;
5754 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5755 dpll |= (crtc->config.pixel_multiplier - 1)
5756 << SDVO_MULTIPLIER_SHIFT_HIRES;
5760 dpll |= DPLL_SDVO_HIGH_SPEED;
5762 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5763 dpll |= DPLL_SDVO_HIGH_SPEED;
5765 /* compute bitmask from p1 value */
5766 if (IS_PINEVIEW(dev))
5767 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5769 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5770 if (IS_G4X(dev) && reduced_clock)
5771 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5773 switch (clock->p2) {
5775 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5778 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5781 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5784 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5787 if (INTEL_INFO(dev)->gen >= 4)
5788 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5790 if (crtc->config.sdvo_tv_clock)
5791 dpll |= PLL_REF_INPUT_TVCLKINBC;
5792 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5793 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5794 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5796 dpll |= PLL_REF_INPUT_DREFCLK;
5798 dpll |= DPLL_VCO_ENABLE;
5799 crtc->config.dpll_hw_state.dpll = dpll;
5801 if (INTEL_INFO(dev)->gen >= 4) {
5802 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5803 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5804 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5808 static void i8xx_update_pll(struct intel_crtc *crtc,
5809 intel_clock_t *reduced_clock,
5812 struct drm_device *dev = crtc->base.dev;
5813 struct drm_i915_private *dev_priv = dev->dev_private;
5815 struct dpll *clock = &crtc->config.dpll;
5817 i9xx_update_pll_dividers(crtc, reduced_clock);
5819 dpll = DPLL_VGA_MODE_DIS;
5821 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5822 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5825 dpll |= PLL_P1_DIVIDE_BY_TWO;
5827 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5829 dpll |= PLL_P2_DIVIDE_BY_4;
5832 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5833 dpll |= DPLL_DVO_2X_MODE;
5835 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5836 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5837 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5839 dpll |= PLL_REF_INPUT_DREFCLK;
5841 dpll |= DPLL_VCO_ENABLE;
5842 crtc->config.dpll_hw_state.dpll = dpll;
5845 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5847 struct drm_device *dev = intel_crtc->base.dev;
5848 struct drm_i915_private *dev_priv = dev->dev_private;
5849 enum pipe pipe = intel_crtc->pipe;
5850 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5851 struct drm_display_mode *adjusted_mode =
5852 &intel_crtc->config.adjusted_mode;
5853 uint32_t crtc_vtotal, crtc_vblank_end;
5856 /* We need to be careful not to changed the adjusted mode, for otherwise
5857 * the hw state checker will get angry at the mismatch. */
5858 crtc_vtotal = adjusted_mode->crtc_vtotal;
5859 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5861 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5862 /* the chip adds 2 halflines automatically */
5864 crtc_vblank_end -= 1;
5866 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5867 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5869 vsyncshift = adjusted_mode->crtc_hsync_start -
5870 adjusted_mode->crtc_htotal / 2;
5872 vsyncshift += adjusted_mode->crtc_htotal;
5875 if (INTEL_INFO(dev)->gen > 3)
5876 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5878 I915_WRITE(HTOTAL(cpu_transcoder),
5879 (adjusted_mode->crtc_hdisplay - 1) |
5880 ((adjusted_mode->crtc_htotal - 1) << 16));
5881 I915_WRITE(HBLANK(cpu_transcoder),
5882 (adjusted_mode->crtc_hblank_start - 1) |
5883 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5884 I915_WRITE(HSYNC(cpu_transcoder),
5885 (adjusted_mode->crtc_hsync_start - 1) |
5886 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5888 I915_WRITE(VTOTAL(cpu_transcoder),
5889 (adjusted_mode->crtc_vdisplay - 1) |
5890 ((crtc_vtotal - 1) << 16));
5891 I915_WRITE(VBLANK(cpu_transcoder),
5892 (adjusted_mode->crtc_vblank_start - 1) |
5893 ((crtc_vblank_end - 1) << 16));
5894 I915_WRITE(VSYNC(cpu_transcoder),
5895 (adjusted_mode->crtc_vsync_start - 1) |
5896 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5898 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5899 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5900 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5902 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5903 (pipe == PIPE_B || pipe == PIPE_C))
5904 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5906 /* pipesrc controls the size that is scaled from, which should
5907 * always be the user's requested size.
5909 I915_WRITE(PIPESRC(pipe),
5910 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5911 (intel_crtc->config.pipe_src_h - 1));
5914 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5915 struct intel_crtc_config *pipe_config)
5917 struct drm_device *dev = crtc->base.dev;
5918 struct drm_i915_private *dev_priv = dev->dev_private;
5919 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5922 tmp = I915_READ(HTOTAL(cpu_transcoder));
5923 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5924 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5925 tmp = I915_READ(HBLANK(cpu_transcoder));
5926 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5927 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5928 tmp = I915_READ(HSYNC(cpu_transcoder));
5929 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5930 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5932 tmp = I915_READ(VTOTAL(cpu_transcoder));
5933 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5934 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5935 tmp = I915_READ(VBLANK(cpu_transcoder));
5936 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5937 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5938 tmp = I915_READ(VSYNC(cpu_transcoder));
5939 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5940 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5942 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5943 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5944 pipe_config->adjusted_mode.crtc_vtotal += 1;
5945 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5948 tmp = I915_READ(PIPESRC(crtc->pipe));
5949 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5950 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5952 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5953 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5956 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5957 struct intel_crtc_config *pipe_config)
5959 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5960 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5961 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5962 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5964 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5965 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5966 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5967 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5969 mode->flags = pipe_config->adjusted_mode.flags;
5971 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5972 mode->flags |= pipe_config->adjusted_mode.flags;
5975 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5977 struct drm_device *dev = intel_crtc->base.dev;
5978 struct drm_i915_private *dev_priv = dev->dev_private;
5983 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5984 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5985 pipeconf |= PIPECONF_ENABLE;
5987 if (intel_crtc->config.double_wide)
5988 pipeconf |= PIPECONF_DOUBLE_WIDE;
5990 /* only g4x and later have fancy bpc/dither controls */
5991 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5992 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5993 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5994 pipeconf |= PIPECONF_DITHER_EN |
5995 PIPECONF_DITHER_TYPE_SP;
5997 switch (intel_crtc->config.pipe_bpp) {
5999 pipeconf |= PIPECONF_6BPC;
6002 pipeconf |= PIPECONF_8BPC;
6005 pipeconf |= PIPECONF_10BPC;
6008 /* Case prevented by intel_choose_pipe_bpp_dither. */
6013 if (HAS_PIPE_CXSR(dev)) {
6014 if (intel_crtc->lowfreq_avail) {
6015 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6016 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6018 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6022 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6023 if (INTEL_INFO(dev)->gen < 4 ||
6024 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6025 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6027 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6029 pipeconf |= PIPECONF_PROGRESSIVE;
6031 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6032 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6034 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6035 POSTING_READ(PIPECONF(intel_crtc->pipe));
6038 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6040 struct drm_framebuffer *fb)
6042 struct drm_device *dev = crtc->dev;
6043 struct drm_i915_private *dev_priv = dev->dev_private;
6044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6045 int refclk, num_connectors = 0;
6046 intel_clock_t clock, reduced_clock;
6047 bool ok, has_reduced_clock = false;
6048 bool is_lvds = false, is_dsi = false;
6049 struct intel_encoder *encoder;
6050 const intel_limit_t *limit;
6052 for_each_encoder_on_crtc(dev, crtc, encoder) {
6053 switch (encoder->type) {
6054 case INTEL_OUTPUT_LVDS:
6057 case INTEL_OUTPUT_DSI:
6068 if (!intel_crtc->config.clock_set) {
6069 refclk = i9xx_get_refclk(crtc, num_connectors);
6072 * Returns a set of divisors for the desired target clock with
6073 * the given refclk, or FALSE. The returned values represent
6074 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6077 limit = intel_limit(crtc, refclk);
6078 ok = dev_priv->display.find_dpll(limit, crtc,
6079 intel_crtc->config.port_clock,
6080 refclk, NULL, &clock);
6082 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6086 if (is_lvds && dev_priv->lvds_downclock_avail) {
6088 * Ensure we match the reduced clock's P to the target
6089 * clock. If the clocks don't match, we can't switch
6090 * the display clock by using the FP0/FP1. In such case
6091 * we will disable the LVDS downclock feature.
6094 dev_priv->display.find_dpll(limit, crtc,
6095 dev_priv->lvds_downclock,
6099 /* Compat-code for transition, will disappear. */
6100 intel_crtc->config.dpll.n = clock.n;
6101 intel_crtc->config.dpll.m1 = clock.m1;
6102 intel_crtc->config.dpll.m2 = clock.m2;
6103 intel_crtc->config.dpll.p1 = clock.p1;
6104 intel_crtc->config.dpll.p2 = clock.p2;
6108 i8xx_update_pll(intel_crtc,
6109 has_reduced_clock ? &reduced_clock : NULL,
6111 } else if (IS_CHERRYVIEW(dev)) {
6112 chv_update_pll(intel_crtc);
6113 } else if (IS_VALLEYVIEW(dev)) {
6114 vlv_update_pll(intel_crtc);
6116 i9xx_update_pll(intel_crtc,
6117 has_reduced_clock ? &reduced_clock : NULL,
6124 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6125 struct intel_crtc_config *pipe_config)
6127 struct drm_device *dev = crtc->base.dev;
6128 struct drm_i915_private *dev_priv = dev->dev_private;
6131 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6134 tmp = I915_READ(PFIT_CONTROL);
6135 if (!(tmp & PFIT_ENABLE))
6138 /* Check whether the pfit is attached to our pipe. */
6139 if (INTEL_INFO(dev)->gen < 4) {
6140 if (crtc->pipe != PIPE_B)
6143 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6147 pipe_config->gmch_pfit.control = tmp;
6148 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6149 if (INTEL_INFO(dev)->gen < 5)
6150 pipe_config->gmch_pfit.lvds_border_bits =
6151 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6154 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6155 struct intel_crtc_config *pipe_config)
6157 struct drm_device *dev = crtc->base.dev;
6158 struct drm_i915_private *dev_priv = dev->dev_private;
6159 int pipe = pipe_config->cpu_transcoder;
6160 intel_clock_t clock;
6162 int refclk = 100000;
6164 /* In case of MIPI DPLL will not even be used */
6165 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6168 mutex_lock(&dev_priv->dpio_lock);
6169 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6170 mutex_unlock(&dev_priv->dpio_lock);
6172 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6173 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6174 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6175 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6176 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6178 vlv_clock(refclk, &clock);
6180 /* clock.dot is the fast clock */
6181 pipe_config->port_clock = clock.dot / 5;
6184 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6185 struct intel_plane_config *plane_config)
6187 struct drm_device *dev = crtc->base.dev;
6188 struct drm_i915_private *dev_priv = dev->dev_private;
6189 u32 val, base, offset;
6190 int pipe = crtc->pipe, plane = crtc->plane;
6191 int fourcc, pixel_format;
6194 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6195 if (!crtc->base.primary->fb) {
6196 DRM_DEBUG_KMS("failed to alloc fb\n");
6200 val = I915_READ(DSPCNTR(plane));
6202 if (INTEL_INFO(dev)->gen >= 4)
6203 if (val & DISPPLANE_TILED)
6204 plane_config->tiled = true;
6206 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6207 fourcc = intel_format_to_fourcc(pixel_format);
6208 crtc->base.primary->fb->pixel_format = fourcc;
6209 crtc->base.primary->fb->bits_per_pixel =
6210 drm_format_plane_cpp(fourcc, 0) * 8;
6212 if (INTEL_INFO(dev)->gen >= 4) {
6213 if (plane_config->tiled)
6214 offset = I915_READ(DSPTILEOFF(plane));
6216 offset = I915_READ(DSPLINOFF(plane));
6217 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6219 base = I915_READ(DSPADDR(plane));
6221 plane_config->base = base;
6223 val = I915_READ(PIPESRC(pipe));
6224 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6225 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6227 val = I915_READ(DSPSTRIDE(pipe));
6228 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6230 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6231 plane_config->tiled);
6233 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6236 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6237 pipe, plane, crtc->base.primary->fb->width,
6238 crtc->base.primary->fb->height,
6239 crtc->base.primary->fb->bits_per_pixel, base,
6240 crtc->base.primary->fb->pitches[0],
6241 plane_config->size);
6245 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6246 struct intel_crtc_config *pipe_config)
6248 struct drm_device *dev = crtc->base.dev;
6249 struct drm_i915_private *dev_priv = dev->dev_private;
6250 int pipe = pipe_config->cpu_transcoder;
6251 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6252 intel_clock_t clock;
6253 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6254 int refclk = 100000;
6256 mutex_lock(&dev_priv->dpio_lock);
6257 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6258 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6259 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6260 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6261 mutex_unlock(&dev_priv->dpio_lock);
6263 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6264 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6265 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6266 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6267 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6269 chv_clock(refclk, &clock);
6271 /* clock.dot is the fast clock */
6272 pipe_config->port_clock = clock.dot / 5;
6275 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6276 struct intel_crtc_config *pipe_config)
6278 struct drm_device *dev = crtc->base.dev;
6279 struct drm_i915_private *dev_priv = dev->dev_private;
6282 if (!intel_display_power_enabled(dev_priv,
6283 POWER_DOMAIN_PIPE(crtc->pipe)))
6286 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6287 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6289 tmp = I915_READ(PIPECONF(crtc->pipe));
6290 if (!(tmp & PIPECONF_ENABLE))
6293 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6294 switch (tmp & PIPECONF_BPC_MASK) {
6296 pipe_config->pipe_bpp = 18;
6299 pipe_config->pipe_bpp = 24;
6301 case PIPECONF_10BPC:
6302 pipe_config->pipe_bpp = 30;
6309 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6310 pipe_config->limited_color_range = true;
6312 if (INTEL_INFO(dev)->gen < 4)
6313 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6315 intel_get_pipe_timings(crtc, pipe_config);
6317 i9xx_get_pfit_config(crtc, pipe_config);
6319 if (INTEL_INFO(dev)->gen >= 4) {
6320 tmp = I915_READ(DPLL_MD(crtc->pipe));
6321 pipe_config->pixel_multiplier =
6322 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6323 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6324 pipe_config->dpll_hw_state.dpll_md = tmp;
6325 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6326 tmp = I915_READ(DPLL(crtc->pipe));
6327 pipe_config->pixel_multiplier =
6328 ((tmp & SDVO_MULTIPLIER_MASK)
6329 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6331 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6332 * port and will be fixed up in the encoder->get_config
6334 pipe_config->pixel_multiplier = 1;
6336 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6337 if (!IS_VALLEYVIEW(dev)) {
6338 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6339 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6341 /* Mask out read-only status bits. */
6342 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6343 DPLL_PORTC_READY_MASK |
6344 DPLL_PORTB_READY_MASK);
6347 if (IS_CHERRYVIEW(dev))
6348 chv_crtc_clock_get(crtc, pipe_config);
6349 else if (IS_VALLEYVIEW(dev))
6350 vlv_crtc_clock_get(crtc, pipe_config);
6352 i9xx_crtc_clock_get(crtc, pipe_config);
6357 static void ironlake_init_pch_refclk(struct drm_device *dev)
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct drm_mode_config *mode_config = &dev->mode_config;
6361 struct intel_encoder *encoder;
6363 bool has_lvds = false;
6364 bool has_cpu_edp = false;
6365 bool has_panel = false;
6366 bool has_ck505 = false;
6367 bool can_ssc = false;
6369 /* We need to take the global config into account */
6370 list_for_each_entry(encoder, &mode_config->encoder_list,
6372 switch (encoder->type) {
6373 case INTEL_OUTPUT_LVDS:
6377 case INTEL_OUTPUT_EDP:
6379 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6385 if (HAS_PCH_IBX(dev)) {
6386 has_ck505 = dev_priv->vbt.display_clock_mode;
6387 can_ssc = has_ck505;
6393 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6394 has_panel, has_lvds, has_ck505);
6396 /* Ironlake: try to setup display ref clock before DPLL
6397 * enabling. This is only under driver's control after
6398 * PCH B stepping, previous chipset stepping should be
6399 * ignoring this setting.
6401 val = I915_READ(PCH_DREF_CONTROL);
6403 /* As we must carefully and slowly disable/enable each source in turn,
6404 * compute the final state we want first and check if we need to
6405 * make any changes at all.
6408 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6410 final |= DREF_NONSPREAD_CK505_ENABLE;
6412 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6414 final &= ~DREF_SSC_SOURCE_MASK;
6415 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6416 final &= ~DREF_SSC1_ENABLE;
6419 final |= DREF_SSC_SOURCE_ENABLE;
6421 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6422 final |= DREF_SSC1_ENABLE;
6425 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6426 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6428 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6430 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6432 final |= DREF_SSC_SOURCE_DISABLE;
6433 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6439 /* Always enable nonspread source */
6440 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6443 val |= DREF_NONSPREAD_CK505_ENABLE;
6445 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6448 val &= ~DREF_SSC_SOURCE_MASK;
6449 val |= DREF_SSC_SOURCE_ENABLE;
6451 /* SSC must be turned on before enabling the CPU output */
6452 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6453 DRM_DEBUG_KMS("Using SSC on panel\n");
6454 val |= DREF_SSC1_ENABLE;
6456 val &= ~DREF_SSC1_ENABLE;
6458 /* Get SSC going before enabling the outputs */
6459 I915_WRITE(PCH_DREF_CONTROL, val);
6460 POSTING_READ(PCH_DREF_CONTROL);
6463 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6465 /* Enable CPU source on CPU attached eDP */
6467 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6468 DRM_DEBUG_KMS("Using SSC on eDP\n");
6469 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6471 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6473 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6475 I915_WRITE(PCH_DREF_CONTROL, val);
6476 POSTING_READ(PCH_DREF_CONTROL);
6479 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6481 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6483 /* Turn off CPU output */
6484 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6486 I915_WRITE(PCH_DREF_CONTROL, val);
6487 POSTING_READ(PCH_DREF_CONTROL);
6490 /* Turn off the SSC source */
6491 val &= ~DREF_SSC_SOURCE_MASK;
6492 val |= DREF_SSC_SOURCE_DISABLE;
6495 val &= ~DREF_SSC1_ENABLE;
6497 I915_WRITE(PCH_DREF_CONTROL, val);
6498 POSTING_READ(PCH_DREF_CONTROL);
6502 BUG_ON(val != final);
6505 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6509 tmp = I915_READ(SOUTH_CHICKEN2);
6510 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6511 I915_WRITE(SOUTH_CHICKEN2, tmp);
6513 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6514 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6515 DRM_ERROR("FDI mPHY reset assert timeout\n");
6517 tmp = I915_READ(SOUTH_CHICKEN2);
6518 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6519 I915_WRITE(SOUTH_CHICKEN2, tmp);
6521 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6522 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6523 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6526 /* WaMPhyProgramming:hsw */
6527 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6531 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6532 tmp &= ~(0xFF << 24);
6533 tmp |= (0x12 << 24);
6534 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6536 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6538 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6540 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6542 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6544 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6545 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6546 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6548 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6549 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6550 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6552 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6555 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6557 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6560 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6562 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6565 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6567 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6570 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6572 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6573 tmp &= ~(0xFF << 16);
6574 tmp |= (0x1C << 16);
6575 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6577 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6578 tmp &= ~(0xFF << 16);
6579 tmp |= (0x1C << 16);
6580 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6582 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6584 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6586 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6588 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6590 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6591 tmp &= ~(0xF << 28);
6593 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6595 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6596 tmp &= ~(0xF << 28);
6598 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6601 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6602 * Programming" based on the parameters passed:
6603 * - Sequence to enable CLKOUT_DP
6604 * - Sequence to enable CLKOUT_DP without spread
6605 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6607 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6610 struct drm_i915_private *dev_priv = dev->dev_private;
6613 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6615 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6616 with_fdi, "LP PCH doesn't have FDI\n"))
6619 mutex_lock(&dev_priv->dpio_lock);
6621 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6622 tmp &= ~SBI_SSCCTL_DISABLE;
6623 tmp |= SBI_SSCCTL_PATHALT;
6624 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6629 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6630 tmp &= ~SBI_SSCCTL_PATHALT;
6631 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6634 lpt_reset_fdi_mphy(dev_priv);
6635 lpt_program_fdi_mphy(dev_priv);
6639 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6640 SBI_GEN0 : SBI_DBUFF0;
6641 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6642 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6643 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6645 mutex_unlock(&dev_priv->dpio_lock);
6648 /* Sequence to disable CLKOUT_DP */
6649 static void lpt_disable_clkout_dp(struct drm_device *dev)
6651 struct drm_i915_private *dev_priv = dev->dev_private;
6654 mutex_lock(&dev_priv->dpio_lock);
6656 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6657 SBI_GEN0 : SBI_DBUFF0;
6658 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6659 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6660 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6662 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6663 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6664 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6665 tmp |= SBI_SSCCTL_PATHALT;
6666 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6669 tmp |= SBI_SSCCTL_DISABLE;
6670 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6673 mutex_unlock(&dev_priv->dpio_lock);
6676 static void lpt_init_pch_refclk(struct drm_device *dev)
6678 struct drm_mode_config *mode_config = &dev->mode_config;
6679 struct intel_encoder *encoder;
6680 bool has_vga = false;
6682 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6683 switch (encoder->type) {
6684 case INTEL_OUTPUT_ANALOG:
6691 lpt_enable_clkout_dp(dev, true, true);
6693 lpt_disable_clkout_dp(dev);
6697 * Initialize reference clocks when the driver loads
6699 void intel_init_pch_refclk(struct drm_device *dev)
6701 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6702 ironlake_init_pch_refclk(dev);
6703 else if (HAS_PCH_LPT(dev))
6704 lpt_init_pch_refclk(dev);
6707 static int ironlake_get_refclk(struct drm_crtc *crtc)
6709 struct drm_device *dev = crtc->dev;
6710 struct drm_i915_private *dev_priv = dev->dev_private;
6711 struct intel_encoder *encoder;
6712 int num_connectors = 0;
6713 bool is_lvds = false;
6715 for_each_encoder_on_crtc(dev, crtc, encoder) {
6716 switch (encoder->type) {
6717 case INTEL_OUTPUT_LVDS:
6724 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6725 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6726 dev_priv->vbt.lvds_ssc_freq);
6727 return dev_priv->vbt.lvds_ssc_freq;
6733 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6735 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6737 int pipe = intel_crtc->pipe;
6742 switch (intel_crtc->config.pipe_bpp) {
6744 val |= PIPECONF_6BPC;
6747 val |= PIPECONF_8BPC;
6750 val |= PIPECONF_10BPC;
6753 val |= PIPECONF_12BPC;
6756 /* Case prevented by intel_choose_pipe_bpp_dither. */
6760 if (intel_crtc->config.dither)
6761 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6763 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6764 val |= PIPECONF_INTERLACED_ILK;
6766 val |= PIPECONF_PROGRESSIVE;
6768 if (intel_crtc->config.limited_color_range)
6769 val |= PIPECONF_COLOR_RANGE_SELECT;
6771 I915_WRITE(PIPECONF(pipe), val);
6772 POSTING_READ(PIPECONF(pipe));
6776 * Set up the pipe CSC unit.
6778 * Currently only full range RGB to limited range RGB conversion
6779 * is supported, but eventually this should handle various
6780 * RGB<->YCbCr scenarios as well.
6782 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6784 struct drm_device *dev = crtc->dev;
6785 struct drm_i915_private *dev_priv = dev->dev_private;
6786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6787 int pipe = intel_crtc->pipe;
6788 uint16_t coeff = 0x7800; /* 1.0 */
6791 * TODO: Check what kind of values actually come out of the pipe
6792 * with these coeff/postoff values and adjust to get the best
6793 * accuracy. Perhaps we even need to take the bpc value into
6797 if (intel_crtc->config.limited_color_range)
6798 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6801 * GY/GU and RY/RU should be the other way around according
6802 * to BSpec, but reality doesn't agree. Just set them up in
6803 * a way that results in the correct picture.
6805 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6806 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6808 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6809 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6811 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6812 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6814 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6815 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6816 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6818 if (INTEL_INFO(dev)->gen > 6) {
6819 uint16_t postoff = 0;
6821 if (intel_crtc->config.limited_color_range)
6822 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6824 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6825 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6826 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6828 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6830 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6832 if (intel_crtc->config.limited_color_range)
6833 mode |= CSC_BLACK_SCREEN_OFFSET;
6835 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6839 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6841 struct drm_device *dev = crtc->dev;
6842 struct drm_i915_private *dev_priv = dev->dev_private;
6843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6844 enum pipe pipe = intel_crtc->pipe;
6845 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6850 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6851 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6853 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6854 val |= PIPECONF_INTERLACED_ILK;
6856 val |= PIPECONF_PROGRESSIVE;
6858 I915_WRITE(PIPECONF(cpu_transcoder), val);
6859 POSTING_READ(PIPECONF(cpu_transcoder));
6861 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6862 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6864 if (IS_BROADWELL(dev)) {
6867 switch (intel_crtc->config.pipe_bpp) {
6869 val |= PIPEMISC_DITHER_6_BPC;
6872 val |= PIPEMISC_DITHER_8_BPC;
6875 val |= PIPEMISC_DITHER_10_BPC;
6878 val |= PIPEMISC_DITHER_12_BPC;
6881 /* Case prevented by pipe_config_set_bpp. */
6885 if (intel_crtc->config.dither)
6886 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6888 I915_WRITE(PIPEMISC(pipe), val);
6892 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6893 intel_clock_t *clock,
6894 bool *has_reduced_clock,
6895 intel_clock_t *reduced_clock)
6897 struct drm_device *dev = crtc->dev;
6898 struct drm_i915_private *dev_priv = dev->dev_private;
6899 struct intel_encoder *intel_encoder;
6901 const intel_limit_t *limit;
6902 bool ret, is_lvds = false;
6904 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6905 switch (intel_encoder->type) {
6906 case INTEL_OUTPUT_LVDS:
6912 refclk = ironlake_get_refclk(crtc);
6915 * Returns a set of divisors for the desired target clock with the given
6916 * refclk, or FALSE. The returned values represent the clock equation:
6917 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6919 limit = intel_limit(crtc, refclk);
6920 ret = dev_priv->display.find_dpll(limit, crtc,
6921 to_intel_crtc(crtc)->config.port_clock,
6922 refclk, NULL, clock);
6926 if (is_lvds && dev_priv->lvds_downclock_avail) {
6928 * Ensure we match the reduced clock's P to the target clock.
6929 * If the clocks don't match, we can't switch the display clock
6930 * by using the FP0/FP1. In such case we will disable the LVDS
6931 * downclock feature.
6933 *has_reduced_clock =
6934 dev_priv->display.find_dpll(limit, crtc,
6935 dev_priv->lvds_downclock,
6943 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6946 * Account for spread spectrum to avoid
6947 * oversubscribing the link. Max center spread
6948 * is 2.5%; use 5% for safety's sake.
6950 u32 bps = target_clock * bpp * 21 / 20;
6951 return DIV_ROUND_UP(bps, link_bw * 8);
6954 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6956 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6959 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6961 intel_clock_t *reduced_clock, u32 *fp2)
6963 struct drm_crtc *crtc = &intel_crtc->base;
6964 struct drm_device *dev = crtc->dev;
6965 struct drm_i915_private *dev_priv = dev->dev_private;
6966 struct intel_encoder *intel_encoder;
6968 int factor, num_connectors = 0;
6969 bool is_lvds = false, is_sdvo = false;
6971 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6972 switch (intel_encoder->type) {
6973 case INTEL_OUTPUT_LVDS:
6976 case INTEL_OUTPUT_SDVO:
6977 case INTEL_OUTPUT_HDMI:
6985 /* Enable autotuning of the PLL clock (if permissible) */
6988 if ((intel_panel_use_ssc(dev_priv) &&
6989 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6990 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6992 } else if (intel_crtc->config.sdvo_tv_clock)
6995 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6998 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7004 dpll |= DPLLB_MODE_LVDS;
7006 dpll |= DPLLB_MODE_DAC_SERIAL;
7008 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7009 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7012 dpll |= DPLL_SDVO_HIGH_SPEED;
7013 if (intel_crtc->config.has_dp_encoder)
7014 dpll |= DPLL_SDVO_HIGH_SPEED;
7016 /* compute bitmask from p1 value */
7017 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7019 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7021 switch (intel_crtc->config.dpll.p2) {
7023 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7026 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7029 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7032 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7036 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7037 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7039 dpll |= PLL_REF_INPUT_DREFCLK;
7041 return dpll | DPLL_VCO_ENABLE;
7044 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7046 struct drm_framebuffer *fb)
7048 struct drm_device *dev = crtc->dev;
7049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7050 int num_connectors = 0;
7051 intel_clock_t clock, reduced_clock;
7052 u32 dpll = 0, fp = 0, fp2 = 0;
7053 bool ok, has_reduced_clock = false;
7054 bool is_lvds = false;
7055 struct intel_encoder *encoder;
7056 struct intel_shared_dpll *pll;
7058 for_each_encoder_on_crtc(dev, crtc, encoder) {
7059 switch (encoder->type) {
7060 case INTEL_OUTPUT_LVDS:
7068 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7069 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7071 ok = ironlake_compute_clocks(crtc, &clock,
7072 &has_reduced_clock, &reduced_clock);
7073 if (!ok && !intel_crtc->config.clock_set) {
7074 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7077 /* Compat-code for transition, will disappear. */
7078 if (!intel_crtc->config.clock_set) {
7079 intel_crtc->config.dpll.n = clock.n;
7080 intel_crtc->config.dpll.m1 = clock.m1;
7081 intel_crtc->config.dpll.m2 = clock.m2;
7082 intel_crtc->config.dpll.p1 = clock.p1;
7083 intel_crtc->config.dpll.p2 = clock.p2;
7086 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7087 if (intel_crtc->config.has_pch_encoder) {
7088 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7089 if (has_reduced_clock)
7090 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7092 dpll = ironlake_compute_dpll(intel_crtc,
7093 &fp, &reduced_clock,
7094 has_reduced_clock ? &fp2 : NULL);
7096 intel_crtc->config.dpll_hw_state.dpll = dpll;
7097 intel_crtc->config.dpll_hw_state.fp0 = fp;
7098 if (has_reduced_clock)
7099 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7101 intel_crtc->config.dpll_hw_state.fp1 = fp;
7103 pll = intel_get_shared_dpll(intel_crtc);
7105 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7106 pipe_name(intel_crtc->pipe));
7110 intel_put_shared_dpll(intel_crtc);
7112 if (is_lvds && has_reduced_clock && i915.powersave)
7113 intel_crtc->lowfreq_avail = true;
7115 intel_crtc->lowfreq_avail = false;
7120 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7121 struct intel_link_m_n *m_n)
7123 struct drm_device *dev = crtc->base.dev;
7124 struct drm_i915_private *dev_priv = dev->dev_private;
7125 enum pipe pipe = crtc->pipe;
7127 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7128 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7129 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7131 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7132 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7133 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7136 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7137 enum transcoder transcoder,
7138 struct intel_link_m_n *m_n)
7140 struct drm_device *dev = crtc->base.dev;
7141 struct drm_i915_private *dev_priv = dev->dev_private;
7142 enum pipe pipe = crtc->pipe;
7144 if (INTEL_INFO(dev)->gen >= 5) {
7145 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7146 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7147 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7149 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7150 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7151 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7153 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7154 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7155 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7157 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7158 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7159 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7163 void intel_dp_get_m_n(struct intel_crtc *crtc,
7164 struct intel_crtc_config *pipe_config)
7166 if (crtc->config.has_pch_encoder)
7167 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7169 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7170 &pipe_config->dp_m_n);
7173 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7174 struct intel_crtc_config *pipe_config)
7176 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7177 &pipe_config->fdi_m_n);
7180 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7181 struct intel_crtc_config *pipe_config)
7183 struct drm_device *dev = crtc->base.dev;
7184 struct drm_i915_private *dev_priv = dev->dev_private;
7187 tmp = I915_READ(PF_CTL(crtc->pipe));
7189 if (tmp & PF_ENABLE) {
7190 pipe_config->pch_pfit.enabled = true;
7191 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7192 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7194 /* We currently do not free assignements of panel fitters on
7195 * ivb/hsw (since we don't use the higher upscaling modes which
7196 * differentiates them) so just WARN about this case for now. */
7198 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7199 PF_PIPE_SEL_IVB(crtc->pipe));
7204 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7205 struct intel_plane_config *plane_config)
7207 struct drm_device *dev = crtc->base.dev;
7208 struct drm_i915_private *dev_priv = dev->dev_private;
7209 u32 val, base, offset;
7210 int pipe = crtc->pipe, plane = crtc->plane;
7211 int fourcc, pixel_format;
7214 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7215 if (!crtc->base.primary->fb) {
7216 DRM_DEBUG_KMS("failed to alloc fb\n");
7220 val = I915_READ(DSPCNTR(plane));
7222 if (INTEL_INFO(dev)->gen >= 4)
7223 if (val & DISPPLANE_TILED)
7224 plane_config->tiled = true;
7226 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7227 fourcc = intel_format_to_fourcc(pixel_format);
7228 crtc->base.primary->fb->pixel_format = fourcc;
7229 crtc->base.primary->fb->bits_per_pixel =
7230 drm_format_plane_cpp(fourcc, 0) * 8;
7232 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7233 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7234 offset = I915_READ(DSPOFFSET(plane));
7236 if (plane_config->tiled)
7237 offset = I915_READ(DSPTILEOFF(plane));
7239 offset = I915_READ(DSPLINOFF(plane));
7241 plane_config->base = base;
7243 val = I915_READ(PIPESRC(pipe));
7244 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7245 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7247 val = I915_READ(DSPSTRIDE(pipe));
7248 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7250 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7251 plane_config->tiled);
7253 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7256 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7257 pipe, plane, crtc->base.primary->fb->width,
7258 crtc->base.primary->fb->height,
7259 crtc->base.primary->fb->bits_per_pixel, base,
7260 crtc->base.primary->fb->pitches[0],
7261 plane_config->size);
7264 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7265 struct intel_crtc_config *pipe_config)
7267 struct drm_device *dev = crtc->base.dev;
7268 struct drm_i915_private *dev_priv = dev->dev_private;
7271 if (!intel_display_power_enabled(dev_priv,
7272 POWER_DOMAIN_PIPE(crtc->pipe)))
7275 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7276 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7278 tmp = I915_READ(PIPECONF(crtc->pipe));
7279 if (!(tmp & PIPECONF_ENABLE))
7282 switch (tmp & PIPECONF_BPC_MASK) {
7284 pipe_config->pipe_bpp = 18;
7287 pipe_config->pipe_bpp = 24;
7289 case PIPECONF_10BPC:
7290 pipe_config->pipe_bpp = 30;
7292 case PIPECONF_12BPC:
7293 pipe_config->pipe_bpp = 36;
7299 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7300 pipe_config->limited_color_range = true;
7302 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7303 struct intel_shared_dpll *pll;
7305 pipe_config->has_pch_encoder = true;
7307 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7308 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7309 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7311 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7313 if (HAS_PCH_IBX(dev_priv->dev)) {
7314 pipe_config->shared_dpll =
7315 (enum intel_dpll_id) crtc->pipe;
7317 tmp = I915_READ(PCH_DPLL_SEL);
7318 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7319 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7321 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7324 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7326 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7327 &pipe_config->dpll_hw_state));
7329 tmp = pipe_config->dpll_hw_state.dpll;
7330 pipe_config->pixel_multiplier =
7331 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7332 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7334 ironlake_pch_clock_get(crtc, pipe_config);
7336 pipe_config->pixel_multiplier = 1;
7339 intel_get_pipe_timings(crtc, pipe_config);
7341 ironlake_get_pfit_config(crtc, pipe_config);
7346 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7348 struct drm_device *dev = dev_priv->dev;
7349 struct intel_crtc *crtc;
7351 for_each_intel_crtc(dev, crtc)
7352 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7353 pipe_name(crtc->pipe));
7355 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7356 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7357 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7358 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7359 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7360 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7361 "CPU PWM1 enabled\n");
7362 if (IS_HASWELL(dev))
7363 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7364 "CPU PWM2 enabled\n");
7365 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7366 "PCH PWM1 enabled\n");
7367 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7368 "Utility pin enabled\n");
7369 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7372 * In theory we can still leave IRQs enabled, as long as only the HPD
7373 * interrupts remain enabled. We used to check for that, but since it's
7374 * gen-specific and since we only disable LCPLL after we fully disable
7375 * the interrupts, the check below should be enough.
7377 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7380 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7382 struct drm_device *dev = dev_priv->dev;
7384 if (IS_HASWELL(dev))
7385 return I915_READ(D_COMP_HSW);
7387 return I915_READ(D_COMP_BDW);
7390 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7392 struct drm_device *dev = dev_priv->dev;
7394 if (IS_HASWELL(dev)) {
7395 mutex_lock(&dev_priv->rps.hw_lock);
7396 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7398 DRM_ERROR("Failed to write to D_COMP\n");
7399 mutex_unlock(&dev_priv->rps.hw_lock);
7401 I915_WRITE(D_COMP_BDW, val);
7402 POSTING_READ(D_COMP_BDW);
7407 * This function implements pieces of two sequences from BSpec:
7408 * - Sequence for display software to disable LCPLL
7409 * - Sequence for display software to allow package C8+
7410 * The steps implemented here are just the steps that actually touch the LCPLL
7411 * register. Callers should take care of disabling all the display engine
7412 * functions, doing the mode unset, fixing interrupts, etc.
7414 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7415 bool switch_to_fclk, bool allow_power_down)
7419 assert_can_disable_lcpll(dev_priv);
7421 val = I915_READ(LCPLL_CTL);
7423 if (switch_to_fclk) {
7424 val |= LCPLL_CD_SOURCE_FCLK;
7425 I915_WRITE(LCPLL_CTL, val);
7427 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7428 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7429 DRM_ERROR("Switching to FCLK failed\n");
7431 val = I915_READ(LCPLL_CTL);
7434 val |= LCPLL_PLL_DISABLE;
7435 I915_WRITE(LCPLL_CTL, val);
7436 POSTING_READ(LCPLL_CTL);
7438 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7439 DRM_ERROR("LCPLL still locked\n");
7441 val = hsw_read_dcomp(dev_priv);
7442 val |= D_COMP_COMP_DISABLE;
7443 hsw_write_dcomp(dev_priv, val);
7446 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7448 DRM_ERROR("D_COMP RCOMP still in progress\n");
7450 if (allow_power_down) {
7451 val = I915_READ(LCPLL_CTL);
7452 val |= LCPLL_POWER_DOWN_ALLOW;
7453 I915_WRITE(LCPLL_CTL, val);
7454 POSTING_READ(LCPLL_CTL);
7459 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7462 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7465 unsigned long irqflags;
7467 val = I915_READ(LCPLL_CTL);
7469 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7470 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7474 * Make sure we're not on PC8 state before disabling PC8, otherwise
7475 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7477 * The other problem is that hsw_restore_lcpll() is called as part of
7478 * the runtime PM resume sequence, so we can't just call
7479 * gen6_gt_force_wake_get() because that function calls
7480 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7481 * while we are on the resume sequence. So to solve this problem we have
7482 * to call special forcewake code that doesn't touch runtime PM and
7483 * doesn't enable the forcewake delayed work.
7485 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7486 if (dev_priv->uncore.forcewake_count++ == 0)
7487 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7488 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7490 if (val & LCPLL_POWER_DOWN_ALLOW) {
7491 val &= ~LCPLL_POWER_DOWN_ALLOW;
7492 I915_WRITE(LCPLL_CTL, val);
7493 POSTING_READ(LCPLL_CTL);
7496 val = hsw_read_dcomp(dev_priv);
7497 val |= D_COMP_COMP_FORCE;
7498 val &= ~D_COMP_COMP_DISABLE;
7499 hsw_write_dcomp(dev_priv, val);
7501 val = I915_READ(LCPLL_CTL);
7502 val &= ~LCPLL_PLL_DISABLE;
7503 I915_WRITE(LCPLL_CTL, val);
7505 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7506 DRM_ERROR("LCPLL not locked yet\n");
7508 if (val & LCPLL_CD_SOURCE_FCLK) {
7509 val = I915_READ(LCPLL_CTL);
7510 val &= ~LCPLL_CD_SOURCE_FCLK;
7511 I915_WRITE(LCPLL_CTL, val);
7513 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7514 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7515 DRM_ERROR("Switching back to LCPLL failed\n");
7518 /* See the big comment above. */
7519 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7520 if (--dev_priv->uncore.forcewake_count == 0)
7521 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7522 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7526 * Package states C8 and deeper are really deep PC states that can only be
7527 * reached when all the devices on the system allow it, so even if the graphics
7528 * device allows PC8+, it doesn't mean the system will actually get to these
7529 * states. Our driver only allows PC8+ when going into runtime PM.
7531 * The requirements for PC8+ are that all the outputs are disabled, the power
7532 * well is disabled and most interrupts are disabled, and these are also
7533 * requirements for runtime PM. When these conditions are met, we manually do
7534 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7535 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7538 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7539 * the state of some registers, so when we come back from PC8+ we need to
7540 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7541 * need to take care of the registers kept by RC6. Notice that this happens even
7542 * if we don't put the device in PCI D3 state (which is what currently happens
7543 * because of the runtime PM support).
7545 * For more, read "Display Sequences for Package C8" on the hardware
7548 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7550 struct drm_device *dev = dev_priv->dev;
7553 DRM_DEBUG_KMS("Enabling package C8+\n");
7555 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7556 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7557 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7558 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7561 lpt_disable_clkout_dp(dev);
7562 hsw_disable_lcpll(dev_priv, true, true);
7565 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7567 struct drm_device *dev = dev_priv->dev;
7570 DRM_DEBUG_KMS("Disabling package C8+\n");
7572 hsw_restore_lcpll(dev_priv);
7573 lpt_init_pch_refclk(dev);
7575 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7576 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7577 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7578 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7581 intel_prepare_ddi(dev);
7584 static void snb_modeset_global_resources(struct drm_device *dev)
7586 modeset_update_crtc_power_domains(dev);
7589 static void haswell_modeset_global_resources(struct drm_device *dev)
7591 modeset_update_crtc_power_domains(dev);
7594 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7596 struct drm_framebuffer *fb)
7598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7600 if (!intel_ddi_pll_select(intel_crtc))
7603 intel_crtc->lowfreq_avail = false;
7608 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7609 struct intel_crtc_config *pipe_config)
7611 struct drm_device *dev = crtc->base.dev;
7612 struct drm_i915_private *dev_priv = dev->dev_private;
7613 struct intel_shared_dpll *pll;
7617 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7619 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7621 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7623 switch (pipe_config->ddi_pll_sel) {
7624 case PORT_CLK_SEL_WRPLL1:
7625 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7627 case PORT_CLK_SEL_WRPLL2:
7628 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7632 if (pipe_config->shared_dpll >= 0) {
7633 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7635 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7636 &pipe_config->dpll_hw_state));
7640 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7641 * DDI E. So just check whether this pipe is wired to DDI E and whether
7642 * the PCH transcoder is on.
7644 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7645 pipe_config->has_pch_encoder = true;
7647 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7648 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7649 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7651 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7655 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7656 struct intel_crtc_config *pipe_config)
7658 struct drm_device *dev = crtc->base.dev;
7659 struct drm_i915_private *dev_priv = dev->dev_private;
7660 enum intel_display_power_domain pfit_domain;
7663 if (!intel_display_power_enabled(dev_priv,
7664 POWER_DOMAIN_PIPE(crtc->pipe)))
7667 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7668 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7670 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7671 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7672 enum pipe trans_edp_pipe;
7673 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7675 WARN(1, "unknown pipe linked to edp transcoder\n");
7676 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7677 case TRANS_DDI_EDP_INPUT_A_ON:
7678 trans_edp_pipe = PIPE_A;
7680 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7681 trans_edp_pipe = PIPE_B;
7683 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7684 trans_edp_pipe = PIPE_C;
7688 if (trans_edp_pipe == crtc->pipe)
7689 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7692 if (!intel_display_power_enabled(dev_priv,
7693 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7696 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7697 if (!(tmp & PIPECONF_ENABLE))
7700 haswell_get_ddi_port_state(crtc, pipe_config);
7702 intel_get_pipe_timings(crtc, pipe_config);
7704 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7705 if (intel_display_power_enabled(dev_priv, pfit_domain))
7706 ironlake_get_pfit_config(crtc, pipe_config);
7708 if (IS_HASWELL(dev))
7709 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7710 (I915_READ(IPS_CTL) & IPS_ENABLE);
7712 pipe_config->pixel_multiplier = 1;
7720 } hdmi_audio_clock[] = {
7721 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7722 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7723 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7724 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7725 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7726 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7727 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7728 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7729 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7730 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7733 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7734 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7738 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7739 if (mode->clock == hdmi_audio_clock[i].clock)
7743 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7744 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7748 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7749 hdmi_audio_clock[i].clock,
7750 hdmi_audio_clock[i].config);
7752 return hdmi_audio_clock[i].config;
7755 static bool intel_eld_uptodate(struct drm_connector *connector,
7756 int reg_eldv, uint32_t bits_eldv,
7757 int reg_elda, uint32_t bits_elda,
7760 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7761 uint8_t *eld = connector->eld;
7764 i = I915_READ(reg_eldv);
7773 i = I915_READ(reg_elda);
7775 I915_WRITE(reg_elda, i);
7777 for (i = 0; i < eld[2]; i++)
7778 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7784 static void g4x_write_eld(struct drm_connector *connector,
7785 struct drm_crtc *crtc,
7786 struct drm_display_mode *mode)
7788 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7789 uint8_t *eld = connector->eld;
7794 i = I915_READ(G4X_AUD_VID_DID);
7796 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7797 eldv = G4X_ELDV_DEVCL_DEVBLC;
7799 eldv = G4X_ELDV_DEVCTG;
7801 if (intel_eld_uptodate(connector,
7802 G4X_AUD_CNTL_ST, eldv,
7803 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7804 G4X_HDMIW_HDMIEDID))
7807 i = I915_READ(G4X_AUD_CNTL_ST);
7808 i &= ~(eldv | G4X_ELD_ADDR);
7809 len = (i >> 9) & 0x1f; /* ELD buffer size */
7810 I915_WRITE(G4X_AUD_CNTL_ST, i);
7815 len = min_t(uint8_t, eld[2], len);
7816 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7817 for (i = 0; i < len; i++)
7818 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7820 i = I915_READ(G4X_AUD_CNTL_ST);
7822 I915_WRITE(G4X_AUD_CNTL_ST, i);
7825 static void haswell_write_eld(struct drm_connector *connector,
7826 struct drm_crtc *crtc,
7827 struct drm_display_mode *mode)
7829 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7830 uint8_t *eld = connector->eld;
7834 int pipe = to_intel_crtc(crtc)->pipe;
7837 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7838 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7839 int aud_config = HSW_AUD_CFG(pipe);
7840 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7842 /* Audio output enable */
7843 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7844 tmp = I915_READ(aud_cntrl_st2);
7845 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7846 I915_WRITE(aud_cntrl_st2, tmp);
7847 POSTING_READ(aud_cntrl_st2);
7849 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7851 /* Set ELD valid state */
7852 tmp = I915_READ(aud_cntrl_st2);
7853 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7854 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7855 I915_WRITE(aud_cntrl_st2, tmp);
7856 tmp = I915_READ(aud_cntrl_st2);
7857 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7859 /* Enable HDMI mode */
7860 tmp = I915_READ(aud_config);
7861 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7862 /* clear N_programing_enable and N_value_index */
7863 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7864 I915_WRITE(aud_config, tmp);
7866 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7868 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7870 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7871 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7872 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7873 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7875 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7878 if (intel_eld_uptodate(connector,
7879 aud_cntrl_st2, eldv,
7880 aud_cntl_st, IBX_ELD_ADDRESS,
7884 i = I915_READ(aud_cntrl_st2);
7886 I915_WRITE(aud_cntrl_st2, i);
7891 i = I915_READ(aud_cntl_st);
7892 i &= ~IBX_ELD_ADDRESS;
7893 I915_WRITE(aud_cntl_st, i);
7894 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7895 DRM_DEBUG_DRIVER("port num:%d\n", i);
7897 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7898 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7899 for (i = 0; i < len; i++)
7900 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7902 i = I915_READ(aud_cntrl_st2);
7904 I915_WRITE(aud_cntrl_st2, i);
7908 static void ironlake_write_eld(struct drm_connector *connector,
7909 struct drm_crtc *crtc,
7910 struct drm_display_mode *mode)
7912 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7913 uint8_t *eld = connector->eld;
7921 int pipe = to_intel_crtc(crtc)->pipe;
7923 if (HAS_PCH_IBX(connector->dev)) {
7924 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7925 aud_config = IBX_AUD_CFG(pipe);
7926 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7927 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7928 } else if (IS_VALLEYVIEW(connector->dev)) {
7929 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7930 aud_config = VLV_AUD_CFG(pipe);
7931 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7932 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7934 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7935 aud_config = CPT_AUD_CFG(pipe);
7936 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7937 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7940 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7942 if (IS_VALLEYVIEW(connector->dev)) {
7943 struct intel_encoder *intel_encoder;
7944 struct intel_digital_port *intel_dig_port;
7946 intel_encoder = intel_attached_encoder(connector);
7947 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7948 i = intel_dig_port->port;
7950 i = I915_READ(aud_cntl_st);
7951 i = (i >> 29) & DIP_PORT_SEL_MASK;
7952 /* DIP_Port_Select, 0x1 = PortB */
7956 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7957 /* operate blindly on all ports */
7958 eldv = IBX_ELD_VALIDB;
7959 eldv |= IBX_ELD_VALIDB << 4;
7960 eldv |= IBX_ELD_VALIDB << 8;
7962 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7963 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7966 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7967 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7968 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7969 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7971 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7974 if (intel_eld_uptodate(connector,
7975 aud_cntrl_st2, eldv,
7976 aud_cntl_st, IBX_ELD_ADDRESS,
7980 i = I915_READ(aud_cntrl_st2);
7982 I915_WRITE(aud_cntrl_st2, i);
7987 i = I915_READ(aud_cntl_st);
7988 i &= ~IBX_ELD_ADDRESS;
7989 I915_WRITE(aud_cntl_st, i);
7991 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7992 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7993 for (i = 0; i < len; i++)
7994 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7996 i = I915_READ(aud_cntrl_st2);
7998 I915_WRITE(aud_cntrl_st2, i);
8001 void intel_write_eld(struct drm_encoder *encoder,
8002 struct drm_display_mode *mode)
8004 struct drm_crtc *crtc = encoder->crtc;
8005 struct drm_connector *connector;
8006 struct drm_device *dev = encoder->dev;
8007 struct drm_i915_private *dev_priv = dev->dev_private;
8009 connector = drm_select_eld(encoder, mode);
8013 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8016 connector->encoder->base.id,
8017 connector->encoder->name);
8019 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8021 if (dev_priv->display.write_eld)
8022 dev_priv->display.write_eld(connector, crtc, mode);
8025 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8027 struct drm_device *dev = crtc->dev;
8028 struct drm_i915_private *dev_priv = dev->dev_private;
8029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8032 if (base != intel_crtc->cursor_base) {
8033 /* On these chipsets we can only modify the base whilst
8034 * the cursor is disabled.
8036 if (intel_crtc->cursor_cntl) {
8037 I915_WRITE(_CURACNTR, 0);
8038 POSTING_READ(_CURACNTR);
8039 intel_crtc->cursor_cntl = 0;
8042 I915_WRITE(_CURABASE, base);
8043 POSTING_READ(_CURABASE);
8046 /* XXX width must be 64, stride 256 => 0x00 << 28 */
8049 cntl = (CURSOR_ENABLE |
8050 CURSOR_GAMMA_ENABLE |
8051 CURSOR_FORMAT_ARGB);
8052 if (intel_crtc->cursor_cntl != cntl) {
8053 I915_WRITE(_CURACNTR, cntl);
8054 POSTING_READ(_CURACNTR);
8055 intel_crtc->cursor_cntl = cntl;
8059 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8061 struct drm_device *dev = crtc->dev;
8062 struct drm_i915_private *dev_priv = dev->dev_private;
8063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8064 int pipe = intel_crtc->pipe;
8069 cntl = MCURSOR_GAMMA_ENABLE;
8070 switch (intel_crtc->cursor_width) {
8072 cntl |= CURSOR_MODE_64_ARGB_AX;
8075 cntl |= CURSOR_MODE_128_ARGB_AX;
8078 cntl |= CURSOR_MODE_256_ARGB_AX;
8084 cntl |= pipe << 28; /* Connect to correct pipe */
8086 if (intel_crtc->cursor_cntl != cntl) {
8087 I915_WRITE(CURCNTR(pipe), cntl);
8088 POSTING_READ(CURCNTR(pipe));
8089 intel_crtc->cursor_cntl = cntl;
8092 /* and commit changes on next vblank */
8093 I915_WRITE(CURBASE(pipe), base);
8094 POSTING_READ(CURBASE(pipe));
8097 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8099 struct drm_device *dev = crtc->dev;
8100 struct drm_i915_private *dev_priv = dev->dev_private;
8101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8102 int pipe = intel_crtc->pipe;
8107 cntl = MCURSOR_GAMMA_ENABLE;
8108 switch (intel_crtc->cursor_width) {
8110 cntl |= CURSOR_MODE_64_ARGB_AX;
8113 cntl |= CURSOR_MODE_128_ARGB_AX;
8116 cntl |= CURSOR_MODE_256_ARGB_AX;
8123 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8124 cntl |= CURSOR_PIPE_CSC_ENABLE;
8126 if (intel_crtc->cursor_cntl != cntl) {
8127 I915_WRITE(CURCNTR(pipe), cntl);
8128 POSTING_READ(CURCNTR(pipe));
8129 intel_crtc->cursor_cntl = cntl;
8132 /* and commit changes on next vblank */
8133 I915_WRITE(CURBASE(pipe), base);
8134 POSTING_READ(CURBASE(pipe));
8137 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8138 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8141 struct drm_device *dev = crtc->dev;
8142 struct drm_i915_private *dev_priv = dev->dev_private;
8143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8144 int pipe = intel_crtc->pipe;
8145 int x = crtc->cursor_x;
8146 int y = crtc->cursor_y;
8147 u32 base = 0, pos = 0;
8150 base = intel_crtc->cursor_addr;
8152 if (x >= intel_crtc->config.pipe_src_w)
8155 if (y >= intel_crtc->config.pipe_src_h)
8159 if (x + intel_crtc->cursor_width <= 0)
8162 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8165 pos |= x << CURSOR_X_SHIFT;
8168 if (y + intel_crtc->cursor_height <= 0)
8171 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8174 pos |= y << CURSOR_Y_SHIFT;
8176 if (base == 0 && intel_crtc->cursor_base == 0)
8179 I915_WRITE(CURPOS(pipe), pos);
8181 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8182 ivb_update_cursor(crtc, base);
8183 else if (IS_845G(dev) || IS_I865G(dev))
8184 i845_update_cursor(crtc, base);
8186 i9xx_update_cursor(crtc, base);
8187 intel_crtc->cursor_base = base;
8191 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8193 * Note that the object's reference will be consumed if the update fails. If
8194 * the update succeeds, the reference of the old object (if any) will be
8197 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8198 struct drm_i915_gem_object *obj,
8199 uint32_t width, uint32_t height)
8201 struct drm_device *dev = crtc->dev;
8202 struct drm_i915_private *dev_priv = dev->dev_private;
8203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8204 enum pipe pipe = intel_crtc->pipe;
8209 /* if we want to turn off the cursor ignore width and height */
8211 DRM_DEBUG_KMS("cursor off\n");
8214 mutex_lock(&dev->struct_mutex);
8218 /* Check for which cursor types we support */
8219 if (!((width == 64 && height == 64) ||
8220 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8221 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8222 DRM_DEBUG("Cursor dimension not supported\n");
8226 if (obj->base.size < width * height * 4) {
8227 DRM_DEBUG_KMS("buffer is too small\n");
8232 /* we only need to pin inside GTT if cursor is non-phy */
8233 mutex_lock(&dev->struct_mutex);
8234 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8237 if (obj->tiling_mode) {
8238 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8243 /* Note that the w/a also requires 2 PTE of padding following
8244 * the bo. We currently fill all unused PTE with the shadow
8245 * page and so we should always have valid PTE following the
8246 * cursor preventing the VT-d warning.
8249 if (need_vtd_wa(dev))
8250 alignment = 64*1024;
8252 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8254 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8258 ret = i915_gem_object_put_fence(obj);
8260 DRM_DEBUG_KMS("failed to release fence for cursor");
8264 addr = i915_gem_obj_ggtt_offset(obj);
8266 int align = IS_I830(dev) ? 16 * 1024 : 256;
8267 ret = i915_gem_object_attach_phys(obj, align);
8269 DRM_DEBUG_KMS("failed to attach phys object\n");
8272 addr = obj->phys_handle->busaddr;
8276 I915_WRITE(CURSIZE, (height << 12) | width);
8279 if (intel_crtc->cursor_bo) {
8280 if (!INTEL_INFO(dev)->cursor_needs_physical)
8281 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8284 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8285 INTEL_FRONTBUFFER_CURSOR(pipe));
8286 mutex_unlock(&dev->struct_mutex);
8288 old_width = intel_crtc->cursor_width;
8290 intel_crtc->cursor_addr = addr;
8291 intel_crtc->cursor_bo = obj;
8292 intel_crtc->cursor_width = width;
8293 intel_crtc->cursor_height = height;
8295 if (intel_crtc->active) {
8296 if (old_width != width)
8297 intel_update_watermarks(crtc);
8298 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8301 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8305 i915_gem_object_unpin_from_display_plane(obj);
8307 mutex_unlock(&dev->struct_mutex);
8309 drm_gem_object_unreference_unlocked(&obj->base);
8313 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8314 u16 *blue, uint32_t start, uint32_t size)
8316 int end = (start + size > 256) ? 256 : start + size, i;
8317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8319 for (i = start; i < end; i++) {
8320 intel_crtc->lut_r[i] = red[i] >> 8;
8321 intel_crtc->lut_g[i] = green[i] >> 8;
8322 intel_crtc->lut_b[i] = blue[i] >> 8;
8325 intel_crtc_load_lut(crtc);
8328 /* VESA 640x480x72Hz mode to set on the pipe */
8329 static struct drm_display_mode load_detect_mode = {
8330 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8331 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8334 struct drm_framebuffer *
8335 __intel_framebuffer_create(struct drm_device *dev,
8336 struct drm_mode_fb_cmd2 *mode_cmd,
8337 struct drm_i915_gem_object *obj)
8339 struct intel_framebuffer *intel_fb;
8342 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8344 drm_gem_object_unreference_unlocked(&obj->base);
8345 return ERR_PTR(-ENOMEM);
8348 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8352 return &intel_fb->base;
8354 drm_gem_object_unreference_unlocked(&obj->base);
8357 return ERR_PTR(ret);
8360 static struct drm_framebuffer *
8361 intel_framebuffer_create(struct drm_device *dev,
8362 struct drm_mode_fb_cmd2 *mode_cmd,
8363 struct drm_i915_gem_object *obj)
8365 struct drm_framebuffer *fb;
8368 ret = i915_mutex_lock_interruptible(dev);
8370 return ERR_PTR(ret);
8371 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8372 mutex_unlock(&dev->struct_mutex);
8378 intel_framebuffer_pitch_for_width(int width, int bpp)
8380 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8381 return ALIGN(pitch, 64);
8385 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8387 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8388 return PAGE_ALIGN(pitch * mode->vdisplay);
8391 static struct drm_framebuffer *
8392 intel_framebuffer_create_for_mode(struct drm_device *dev,
8393 struct drm_display_mode *mode,
8396 struct drm_i915_gem_object *obj;
8397 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8399 obj = i915_gem_alloc_object(dev,
8400 intel_framebuffer_size_for_mode(mode, bpp));
8402 return ERR_PTR(-ENOMEM);
8404 mode_cmd.width = mode->hdisplay;
8405 mode_cmd.height = mode->vdisplay;
8406 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8408 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8410 return intel_framebuffer_create(dev, &mode_cmd, obj);
8413 static struct drm_framebuffer *
8414 mode_fits_in_fbdev(struct drm_device *dev,
8415 struct drm_display_mode *mode)
8417 #ifdef CONFIG_DRM_I915_FBDEV
8418 struct drm_i915_private *dev_priv = dev->dev_private;
8419 struct drm_i915_gem_object *obj;
8420 struct drm_framebuffer *fb;
8422 if (!dev_priv->fbdev)
8425 if (!dev_priv->fbdev->fb)
8428 obj = dev_priv->fbdev->fb->obj;
8431 fb = &dev_priv->fbdev->fb->base;
8432 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8433 fb->bits_per_pixel))
8436 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8445 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8446 struct drm_display_mode *mode,
8447 struct intel_load_detect_pipe *old,
8448 struct drm_modeset_acquire_ctx *ctx)
8450 struct intel_crtc *intel_crtc;
8451 struct intel_encoder *intel_encoder =
8452 intel_attached_encoder(connector);
8453 struct drm_crtc *possible_crtc;
8454 struct drm_encoder *encoder = &intel_encoder->base;
8455 struct drm_crtc *crtc = NULL;
8456 struct drm_device *dev = encoder->dev;
8457 struct drm_framebuffer *fb;
8458 struct drm_mode_config *config = &dev->mode_config;
8461 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8462 connector->base.id, connector->name,
8463 encoder->base.id, encoder->name);
8466 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8471 * Algorithm gets a little messy:
8473 * - if the connector already has an assigned crtc, use it (but make
8474 * sure it's on first)
8476 * - try to find the first unused crtc that can drive this connector,
8477 * and use that if we find one
8480 /* See if we already have a CRTC for this connector */
8481 if (encoder->crtc) {
8482 crtc = encoder->crtc;
8484 ret = drm_modeset_lock(&crtc->mutex, ctx);
8488 old->dpms_mode = connector->dpms;
8489 old->load_detect_temp = false;
8491 /* Make sure the crtc and connector are running */
8492 if (connector->dpms != DRM_MODE_DPMS_ON)
8493 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8498 /* Find an unused one (if possible) */
8499 for_each_crtc(dev, possible_crtc) {
8501 if (!(encoder->possible_crtcs & (1 << i)))
8503 if (possible_crtc->enabled)
8505 /* This can occur when applying the pipe A quirk on resume. */
8506 if (to_intel_crtc(possible_crtc)->new_enabled)
8509 crtc = possible_crtc;
8514 * If we didn't find an unused CRTC, don't use any.
8517 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8521 ret = drm_modeset_lock(&crtc->mutex, ctx);
8524 intel_encoder->new_crtc = to_intel_crtc(crtc);
8525 to_intel_connector(connector)->new_encoder = intel_encoder;
8527 intel_crtc = to_intel_crtc(crtc);
8528 intel_crtc->new_enabled = true;
8529 intel_crtc->new_config = &intel_crtc->config;
8530 old->dpms_mode = connector->dpms;
8531 old->load_detect_temp = true;
8532 old->release_fb = NULL;
8535 mode = &load_detect_mode;
8537 /* We need a framebuffer large enough to accommodate all accesses
8538 * that the plane may generate whilst we perform load detection.
8539 * We can not rely on the fbcon either being present (we get called
8540 * during its initialisation to detect all boot displays, or it may
8541 * not even exist) or that it is large enough to satisfy the
8544 fb = mode_fits_in_fbdev(dev, mode);
8546 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8547 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8548 old->release_fb = fb;
8550 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8552 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8556 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8557 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8558 if (old->release_fb)
8559 old->release_fb->funcs->destroy(old->release_fb);
8563 /* let the connector get through one full cycle before testing */
8564 intel_wait_for_vblank(dev, intel_crtc->pipe);
8568 intel_crtc->new_enabled = crtc->enabled;
8569 if (intel_crtc->new_enabled)
8570 intel_crtc->new_config = &intel_crtc->config;
8572 intel_crtc->new_config = NULL;
8574 if (ret == -EDEADLK) {
8575 drm_modeset_backoff(ctx);
8582 void intel_release_load_detect_pipe(struct drm_connector *connector,
8583 struct intel_load_detect_pipe *old)
8585 struct intel_encoder *intel_encoder =
8586 intel_attached_encoder(connector);
8587 struct drm_encoder *encoder = &intel_encoder->base;
8588 struct drm_crtc *crtc = encoder->crtc;
8589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8591 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8592 connector->base.id, connector->name,
8593 encoder->base.id, encoder->name);
8595 if (old->load_detect_temp) {
8596 to_intel_connector(connector)->new_encoder = NULL;
8597 intel_encoder->new_crtc = NULL;
8598 intel_crtc->new_enabled = false;
8599 intel_crtc->new_config = NULL;
8600 intel_set_mode(crtc, NULL, 0, 0, NULL);
8602 if (old->release_fb) {
8603 drm_framebuffer_unregister_private(old->release_fb);
8604 drm_framebuffer_unreference(old->release_fb);
8610 /* Switch crtc and encoder back off if necessary */
8611 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8612 connector->funcs->dpms(connector, old->dpms_mode);
8615 static int i9xx_pll_refclk(struct drm_device *dev,
8616 const struct intel_crtc_config *pipe_config)
8618 struct drm_i915_private *dev_priv = dev->dev_private;
8619 u32 dpll = pipe_config->dpll_hw_state.dpll;
8621 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8622 return dev_priv->vbt.lvds_ssc_freq;
8623 else if (HAS_PCH_SPLIT(dev))
8625 else if (!IS_GEN2(dev))
8631 /* Returns the clock of the currently programmed mode of the given pipe. */
8632 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8633 struct intel_crtc_config *pipe_config)
8635 struct drm_device *dev = crtc->base.dev;
8636 struct drm_i915_private *dev_priv = dev->dev_private;
8637 int pipe = pipe_config->cpu_transcoder;
8638 u32 dpll = pipe_config->dpll_hw_state.dpll;
8640 intel_clock_t clock;
8641 int refclk = i9xx_pll_refclk(dev, pipe_config);
8643 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8644 fp = pipe_config->dpll_hw_state.fp0;
8646 fp = pipe_config->dpll_hw_state.fp1;
8648 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8649 if (IS_PINEVIEW(dev)) {
8650 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8651 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8653 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8654 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8657 if (!IS_GEN2(dev)) {
8658 if (IS_PINEVIEW(dev))
8659 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8660 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8662 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8663 DPLL_FPA01_P1_POST_DIV_SHIFT);
8665 switch (dpll & DPLL_MODE_MASK) {
8666 case DPLLB_MODE_DAC_SERIAL:
8667 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8670 case DPLLB_MODE_LVDS:
8671 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8675 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8676 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8680 if (IS_PINEVIEW(dev))
8681 pineview_clock(refclk, &clock);
8683 i9xx_clock(refclk, &clock);
8685 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8686 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8689 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8690 DPLL_FPA01_P1_POST_DIV_SHIFT);
8692 if (lvds & LVDS_CLKB_POWER_UP)
8697 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8700 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8701 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8703 if (dpll & PLL_P2_DIVIDE_BY_4)
8709 i9xx_clock(refclk, &clock);
8713 * This value includes pixel_multiplier. We will use
8714 * port_clock to compute adjusted_mode.crtc_clock in the
8715 * encoder's get_config() function.
8717 pipe_config->port_clock = clock.dot;
8720 int intel_dotclock_calculate(int link_freq,
8721 const struct intel_link_m_n *m_n)
8724 * The calculation for the data clock is:
8725 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8726 * But we want to avoid losing precison if possible, so:
8727 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8729 * and the link clock is simpler:
8730 * link_clock = (m * link_clock) / n
8736 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8739 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8740 struct intel_crtc_config *pipe_config)
8742 struct drm_device *dev = crtc->base.dev;
8744 /* read out port_clock from the DPLL */
8745 i9xx_crtc_clock_get(crtc, pipe_config);
8748 * This value does not include pixel_multiplier.
8749 * We will check that port_clock and adjusted_mode.crtc_clock
8750 * agree once we know their relationship in the encoder's
8751 * get_config() function.
8753 pipe_config->adjusted_mode.crtc_clock =
8754 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8755 &pipe_config->fdi_m_n);
8758 /** Returns the currently programmed mode of the given pipe. */
8759 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8760 struct drm_crtc *crtc)
8762 struct drm_i915_private *dev_priv = dev->dev_private;
8763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8764 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8765 struct drm_display_mode *mode;
8766 struct intel_crtc_config pipe_config;
8767 int htot = I915_READ(HTOTAL(cpu_transcoder));
8768 int hsync = I915_READ(HSYNC(cpu_transcoder));
8769 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8770 int vsync = I915_READ(VSYNC(cpu_transcoder));
8771 enum pipe pipe = intel_crtc->pipe;
8773 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8778 * Construct a pipe_config sufficient for getting the clock info
8779 * back out of crtc_clock_get.
8781 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8782 * to use a real value here instead.
8784 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8785 pipe_config.pixel_multiplier = 1;
8786 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8787 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8788 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8789 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8791 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8792 mode->hdisplay = (htot & 0xffff) + 1;
8793 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8794 mode->hsync_start = (hsync & 0xffff) + 1;
8795 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8796 mode->vdisplay = (vtot & 0xffff) + 1;
8797 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8798 mode->vsync_start = (vsync & 0xffff) + 1;
8799 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8801 drm_mode_set_name(mode);
8806 static void intel_increase_pllclock(struct drm_device *dev,
8809 struct drm_i915_private *dev_priv = dev->dev_private;
8810 int dpll_reg = DPLL(pipe);
8813 if (!HAS_GMCH_DISPLAY(dev))
8816 if (!dev_priv->lvds_downclock_avail)
8819 dpll = I915_READ(dpll_reg);
8820 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8821 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8823 assert_panel_unlocked(dev_priv, pipe);
8825 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8826 I915_WRITE(dpll_reg, dpll);
8827 intel_wait_for_vblank(dev, pipe);
8829 dpll = I915_READ(dpll_reg);
8830 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8831 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8835 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8837 struct drm_device *dev = crtc->dev;
8838 struct drm_i915_private *dev_priv = dev->dev_private;
8839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8841 if (!HAS_GMCH_DISPLAY(dev))
8844 if (!dev_priv->lvds_downclock_avail)
8848 * Since this is called by a timer, we should never get here in
8851 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8852 int pipe = intel_crtc->pipe;
8853 int dpll_reg = DPLL(pipe);
8856 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8858 assert_panel_unlocked(dev_priv, pipe);
8860 dpll = I915_READ(dpll_reg);
8861 dpll |= DISPLAY_RATE_SELECT_FPA1;
8862 I915_WRITE(dpll_reg, dpll);
8863 intel_wait_for_vblank(dev, pipe);
8864 dpll = I915_READ(dpll_reg);
8865 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8866 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8871 void intel_mark_busy(struct drm_device *dev)
8873 struct drm_i915_private *dev_priv = dev->dev_private;
8875 if (dev_priv->mm.busy)
8878 intel_runtime_pm_get(dev_priv);
8879 i915_update_gfx_val(dev_priv);
8880 dev_priv->mm.busy = true;
8883 void intel_mark_idle(struct drm_device *dev)
8885 struct drm_i915_private *dev_priv = dev->dev_private;
8886 struct drm_crtc *crtc;
8888 if (!dev_priv->mm.busy)
8891 dev_priv->mm.busy = false;
8893 if (!i915.powersave)
8896 for_each_crtc(dev, crtc) {
8897 if (!crtc->primary->fb)
8900 intel_decrease_pllclock(crtc);
8903 if (INTEL_INFO(dev)->gen >= 6)
8904 gen6_rps_idle(dev->dev_private);
8907 intel_runtime_pm_put(dev_priv);
8912 * intel_mark_fb_busy - mark given planes as busy
8914 * @frontbuffer_bits: bits for the affected planes
8915 * @ring: optional ring for asynchronous commands
8917 * This function gets called every time the screen contents change. It can be
8918 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8920 static void intel_mark_fb_busy(struct drm_device *dev,
8921 unsigned frontbuffer_bits,
8922 struct intel_engine_cs *ring)
8926 if (!i915.powersave)
8929 for_each_pipe(pipe) {
8930 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8933 intel_increase_pllclock(dev, pipe);
8934 if (ring && intel_fbc_enabled(dev))
8935 ring->fbc_dirty = true;
8940 * intel_fb_obj_invalidate - invalidate frontbuffer object
8941 * @obj: GEM object to invalidate
8942 * @ring: set for asynchronous rendering
8944 * This function gets called every time rendering on the given object starts and
8945 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8946 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8947 * until the rendering completes or a flip on this frontbuffer plane is
8950 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8951 struct intel_engine_cs *ring)
8953 struct drm_device *dev = obj->base.dev;
8954 struct drm_i915_private *dev_priv = dev->dev_private;
8956 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8958 if (!obj->frontbuffer_bits)
8962 mutex_lock(&dev_priv->fb_tracking.lock);
8963 dev_priv->fb_tracking.busy_bits
8964 |= obj->frontbuffer_bits;
8965 dev_priv->fb_tracking.flip_bits
8966 &= ~obj->frontbuffer_bits;
8967 mutex_unlock(&dev_priv->fb_tracking.lock);
8970 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8972 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
8976 * intel_frontbuffer_flush - flush frontbuffer
8978 * @frontbuffer_bits: frontbuffer plane tracking bits
8980 * This function gets called every time rendering on the given planes has
8981 * completed and frontbuffer caching can be started again. Flushes will get
8982 * delayed if they're blocked by some oustanding asynchronous rendering.
8984 * Can be called without any locks held.
8986 void intel_frontbuffer_flush(struct drm_device *dev,
8987 unsigned frontbuffer_bits)
8989 struct drm_i915_private *dev_priv = dev->dev_private;
8991 /* Delay flushing when rings are still busy.*/
8992 mutex_lock(&dev_priv->fb_tracking.lock);
8993 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
8994 mutex_unlock(&dev_priv->fb_tracking.lock);
8996 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
8998 intel_edp_psr_flush(dev, frontbuffer_bits);
9002 * intel_fb_obj_flush - flush frontbuffer object
9003 * @obj: GEM object to flush
9004 * @retire: set when retiring asynchronous rendering
9006 * This function gets called every time rendering on the given object has
9007 * completed and frontbuffer caching can be started again. If @retire is true
9008 * then any delayed flushes will be unblocked.
9010 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9013 struct drm_device *dev = obj->base.dev;
9014 struct drm_i915_private *dev_priv = dev->dev_private;
9015 unsigned frontbuffer_bits;
9017 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9019 if (!obj->frontbuffer_bits)
9022 frontbuffer_bits = obj->frontbuffer_bits;
9025 mutex_lock(&dev_priv->fb_tracking.lock);
9026 /* Filter out new bits since rendering started. */
9027 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9029 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9030 mutex_unlock(&dev_priv->fb_tracking.lock);
9033 intel_frontbuffer_flush(dev, frontbuffer_bits);
9037 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9039 * @frontbuffer_bits: frontbuffer plane tracking bits
9041 * This function gets called after scheduling a flip on @obj. The actual
9042 * frontbuffer flushing will be delayed until completion is signalled with
9043 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9044 * flush will be cancelled.
9046 * Can be called without any locks held.
9048 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9049 unsigned frontbuffer_bits)
9051 struct drm_i915_private *dev_priv = dev->dev_private;
9053 mutex_lock(&dev_priv->fb_tracking.lock);
9054 dev_priv->fb_tracking.flip_bits
9055 |= frontbuffer_bits;
9056 mutex_unlock(&dev_priv->fb_tracking.lock);
9060 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9062 * @frontbuffer_bits: frontbuffer plane tracking bits
9064 * This function gets called after the flip has been latched and will complete
9065 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9067 * Can be called without any locks held.
9069 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9070 unsigned frontbuffer_bits)
9072 struct drm_i915_private *dev_priv = dev->dev_private;
9074 mutex_lock(&dev_priv->fb_tracking.lock);
9075 /* Mask any cancelled flips. */
9076 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9077 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9078 mutex_unlock(&dev_priv->fb_tracking.lock);
9080 intel_frontbuffer_flush(dev, frontbuffer_bits);
9083 static void intel_crtc_destroy(struct drm_crtc *crtc)
9085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9086 struct drm_device *dev = crtc->dev;
9087 struct intel_unpin_work *work;
9088 unsigned long flags;
9090 spin_lock_irqsave(&dev->event_lock, flags);
9091 work = intel_crtc->unpin_work;
9092 intel_crtc->unpin_work = NULL;
9093 spin_unlock_irqrestore(&dev->event_lock, flags);
9096 cancel_work_sync(&work->work);
9100 drm_crtc_cleanup(crtc);
9105 static void intel_unpin_work_fn(struct work_struct *__work)
9107 struct intel_unpin_work *work =
9108 container_of(__work, struct intel_unpin_work, work);
9109 struct drm_device *dev = work->crtc->dev;
9110 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9112 mutex_lock(&dev->struct_mutex);
9113 intel_unpin_fb_obj(work->old_fb_obj);
9114 drm_gem_object_unreference(&work->pending_flip_obj->base);
9115 drm_gem_object_unreference(&work->old_fb_obj->base);
9117 intel_update_fbc(dev);
9118 mutex_unlock(&dev->struct_mutex);
9120 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9122 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9123 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9128 static void do_intel_finish_page_flip(struct drm_device *dev,
9129 struct drm_crtc *crtc)
9131 struct drm_i915_private *dev_priv = dev->dev_private;
9132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9133 struct intel_unpin_work *work;
9134 unsigned long flags;
9136 /* Ignore early vblank irqs */
9137 if (intel_crtc == NULL)
9140 spin_lock_irqsave(&dev->event_lock, flags);
9141 work = intel_crtc->unpin_work;
9143 /* Ensure we don't miss a work->pending update ... */
9146 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9147 spin_unlock_irqrestore(&dev->event_lock, flags);
9151 /* and that the unpin work is consistent wrt ->pending. */
9154 intel_crtc->unpin_work = NULL;
9157 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9159 drm_crtc_vblank_put(crtc);
9161 spin_unlock_irqrestore(&dev->event_lock, flags);
9163 wake_up_all(&dev_priv->pending_flip_queue);
9165 queue_work(dev_priv->wq, &work->work);
9167 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9170 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9172 struct drm_i915_private *dev_priv = dev->dev_private;
9173 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9175 do_intel_finish_page_flip(dev, crtc);
9178 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9180 struct drm_i915_private *dev_priv = dev->dev_private;
9181 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9183 do_intel_finish_page_flip(dev, crtc);
9186 /* Is 'a' after or equal to 'b'? */
9187 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9189 return !((a - b) & 0x80000000);
9192 static bool page_flip_finished(struct intel_crtc *crtc)
9194 struct drm_device *dev = crtc->base.dev;
9195 struct drm_i915_private *dev_priv = dev->dev_private;
9198 * The relevant registers doen't exist on pre-ctg.
9199 * As the flip done interrupt doesn't trigger for mmio
9200 * flips on gmch platforms, a flip count check isn't
9201 * really needed there. But since ctg has the registers,
9202 * include it in the check anyway.
9204 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9208 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9209 * used the same base address. In that case the mmio flip might
9210 * have completed, but the CS hasn't even executed the flip yet.
9212 * A flip count check isn't enough as the CS might have updated
9213 * the base address just after start of vblank, but before we
9214 * managed to process the interrupt. This means we'd complete the
9217 * Combining both checks should get us a good enough result. It may
9218 * still happen that the CS flip has been executed, but has not
9219 * yet actually completed. But in case the base address is the same
9220 * anyway, we don't really care.
9222 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9223 crtc->unpin_work->gtt_offset &&
9224 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9225 crtc->unpin_work->flip_count);
9228 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9230 struct drm_i915_private *dev_priv = dev->dev_private;
9231 struct intel_crtc *intel_crtc =
9232 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9233 unsigned long flags;
9235 /* NB: An MMIO update of the plane base pointer will also
9236 * generate a page-flip completion irq, i.e. every modeset
9237 * is also accompanied by a spurious intel_prepare_page_flip().
9239 spin_lock_irqsave(&dev->event_lock, flags);
9240 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9241 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9242 spin_unlock_irqrestore(&dev->event_lock, flags);
9245 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9247 /* Ensure that the work item is consistent when activating it ... */
9249 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9250 /* and that it is marked active as soon as the irq could fire. */
9254 static int intel_gen2_queue_flip(struct drm_device *dev,
9255 struct drm_crtc *crtc,
9256 struct drm_framebuffer *fb,
9257 struct drm_i915_gem_object *obj,
9258 struct intel_engine_cs *ring,
9261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9265 ret = intel_ring_begin(ring, 6);
9269 /* Can't queue multiple flips, so wait for the previous
9270 * one to finish before executing the next.
9272 if (intel_crtc->plane)
9273 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9275 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9276 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9277 intel_ring_emit(ring, MI_NOOP);
9278 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9279 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9280 intel_ring_emit(ring, fb->pitches[0]);
9281 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9282 intel_ring_emit(ring, 0); /* aux display base address, unused */
9284 intel_mark_page_flip_active(intel_crtc);
9285 __intel_ring_advance(ring);
9289 static int intel_gen3_queue_flip(struct drm_device *dev,
9290 struct drm_crtc *crtc,
9291 struct drm_framebuffer *fb,
9292 struct drm_i915_gem_object *obj,
9293 struct intel_engine_cs *ring,
9296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9300 ret = intel_ring_begin(ring, 6);
9304 if (intel_crtc->plane)
9305 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9307 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9308 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9309 intel_ring_emit(ring, MI_NOOP);
9310 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9311 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9312 intel_ring_emit(ring, fb->pitches[0]);
9313 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9314 intel_ring_emit(ring, MI_NOOP);
9316 intel_mark_page_flip_active(intel_crtc);
9317 __intel_ring_advance(ring);
9321 static int intel_gen4_queue_flip(struct drm_device *dev,
9322 struct drm_crtc *crtc,
9323 struct drm_framebuffer *fb,
9324 struct drm_i915_gem_object *obj,
9325 struct intel_engine_cs *ring,
9328 struct drm_i915_private *dev_priv = dev->dev_private;
9329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9330 uint32_t pf, pipesrc;
9333 ret = intel_ring_begin(ring, 4);
9337 /* i965+ uses the linear or tiled offsets from the
9338 * Display Registers (which do not change across a page-flip)
9339 * so we need only reprogram the base address.
9341 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9342 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9343 intel_ring_emit(ring, fb->pitches[0]);
9344 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9347 /* XXX Enabling the panel-fitter across page-flip is so far
9348 * untested on non-native modes, so ignore it for now.
9349 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9352 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9353 intel_ring_emit(ring, pf | pipesrc);
9355 intel_mark_page_flip_active(intel_crtc);
9356 __intel_ring_advance(ring);
9360 static int intel_gen6_queue_flip(struct drm_device *dev,
9361 struct drm_crtc *crtc,
9362 struct drm_framebuffer *fb,
9363 struct drm_i915_gem_object *obj,
9364 struct intel_engine_cs *ring,
9367 struct drm_i915_private *dev_priv = dev->dev_private;
9368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9369 uint32_t pf, pipesrc;
9372 ret = intel_ring_begin(ring, 4);
9376 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9377 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9378 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9379 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9381 /* Contrary to the suggestions in the documentation,
9382 * "Enable Panel Fitter" does not seem to be required when page
9383 * flipping with a non-native mode, and worse causes a normal
9385 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9388 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9389 intel_ring_emit(ring, pf | pipesrc);
9391 intel_mark_page_flip_active(intel_crtc);
9392 __intel_ring_advance(ring);
9396 static int intel_gen7_queue_flip(struct drm_device *dev,
9397 struct drm_crtc *crtc,
9398 struct drm_framebuffer *fb,
9399 struct drm_i915_gem_object *obj,
9400 struct intel_engine_cs *ring,
9403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9404 uint32_t plane_bit = 0;
9407 switch (intel_crtc->plane) {
9409 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9412 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9415 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9418 WARN_ONCE(1, "unknown plane in flip command\n");
9423 if (ring->id == RCS) {
9426 * On Gen 8, SRM is now taking an extra dword to accommodate
9427 * 48bits addresses, and we need a NOOP for the batch size to
9435 * BSpec MI_DISPLAY_FLIP for IVB:
9436 * "The full packet must be contained within the same cache line."
9438 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9439 * cacheline, if we ever start emitting more commands before
9440 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9441 * then do the cacheline alignment, and finally emit the
9444 ret = intel_ring_cacheline_align(ring);
9448 ret = intel_ring_begin(ring, len);
9452 /* Unmask the flip-done completion message. Note that the bspec says that
9453 * we should do this for both the BCS and RCS, and that we must not unmask
9454 * more than one flip event at any time (or ensure that one flip message
9455 * can be sent by waiting for flip-done prior to queueing new flips).
9456 * Experimentation says that BCS works despite DERRMR masking all
9457 * flip-done completion events and that unmasking all planes at once
9458 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9459 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9461 if (ring->id == RCS) {
9462 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9463 intel_ring_emit(ring, DERRMR);
9464 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9465 DERRMR_PIPEB_PRI_FLIP_DONE |
9466 DERRMR_PIPEC_PRI_FLIP_DONE));
9468 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9469 MI_SRM_LRM_GLOBAL_GTT);
9471 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9472 MI_SRM_LRM_GLOBAL_GTT);
9473 intel_ring_emit(ring, DERRMR);
9474 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9476 intel_ring_emit(ring, 0);
9477 intel_ring_emit(ring, MI_NOOP);
9481 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9482 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9483 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9484 intel_ring_emit(ring, (MI_NOOP));
9486 intel_mark_page_flip_active(intel_crtc);
9487 __intel_ring_advance(ring);
9491 static bool use_mmio_flip(struct intel_engine_cs *ring,
9492 struct drm_i915_gem_object *obj)
9495 * This is not being used for older platforms, because
9496 * non-availability of flip done interrupt forces us to use
9497 * CS flips. Older platforms derive flip done using some clever
9498 * tricks involving the flip_pending status bits and vblank irqs.
9499 * So using MMIO flips there would disrupt this mechanism.
9505 if (INTEL_INFO(ring->dev)->gen < 5)
9508 if (i915.use_mmio_flip < 0)
9510 else if (i915.use_mmio_flip > 0)
9513 return ring != obj->ring;
9516 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9518 struct drm_device *dev = intel_crtc->base.dev;
9519 struct drm_i915_private *dev_priv = dev->dev_private;
9520 struct intel_framebuffer *intel_fb =
9521 to_intel_framebuffer(intel_crtc->base.primary->fb);
9522 struct drm_i915_gem_object *obj = intel_fb->obj;
9526 intel_mark_page_flip_active(intel_crtc);
9528 reg = DSPCNTR(intel_crtc->plane);
9529 dspcntr = I915_READ(reg);
9531 if (INTEL_INFO(dev)->gen >= 4) {
9532 if (obj->tiling_mode != I915_TILING_NONE)
9533 dspcntr |= DISPPLANE_TILED;
9535 dspcntr &= ~DISPPLANE_TILED;
9537 I915_WRITE(reg, dspcntr);
9539 I915_WRITE(DSPSURF(intel_crtc->plane),
9540 intel_crtc->unpin_work->gtt_offset);
9541 POSTING_READ(DSPSURF(intel_crtc->plane));
9544 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9546 struct intel_engine_cs *ring;
9549 lockdep_assert_held(&obj->base.dev->struct_mutex);
9551 if (!obj->last_write_seqno)
9556 if (i915_seqno_passed(ring->get_seqno(ring, true),
9557 obj->last_write_seqno))
9560 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9564 if (WARN_ON(!ring->irq_get(ring)))
9570 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9572 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9573 struct intel_crtc *intel_crtc;
9574 unsigned long irq_flags;
9577 seqno = ring->get_seqno(ring, false);
9579 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9580 for_each_intel_crtc(ring->dev, intel_crtc) {
9581 struct intel_mmio_flip *mmio_flip;
9583 mmio_flip = &intel_crtc->mmio_flip;
9584 if (mmio_flip->seqno == 0)
9587 if (ring->id != mmio_flip->ring_id)
9590 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9591 intel_do_mmio_flip(intel_crtc);
9592 mmio_flip->seqno = 0;
9593 ring->irq_put(ring);
9596 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9599 static int intel_queue_mmio_flip(struct drm_device *dev,
9600 struct drm_crtc *crtc,
9601 struct drm_framebuffer *fb,
9602 struct drm_i915_gem_object *obj,
9603 struct intel_engine_cs *ring,
9606 struct drm_i915_private *dev_priv = dev->dev_private;
9607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9608 unsigned long irq_flags;
9611 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9614 ret = intel_postpone_flip(obj);
9618 intel_do_mmio_flip(intel_crtc);
9622 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9623 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9624 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9625 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9628 * Double check to catch cases where irq fired before
9629 * mmio flip data was ready
9631 intel_notify_mmio_flip(obj->ring);
9635 static int intel_default_queue_flip(struct drm_device *dev,
9636 struct drm_crtc *crtc,
9637 struct drm_framebuffer *fb,
9638 struct drm_i915_gem_object *obj,
9639 struct intel_engine_cs *ring,
9645 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9646 struct drm_framebuffer *fb,
9647 struct drm_pending_vblank_event *event,
9648 uint32_t page_flip_flags)
9650 struct drm_device *dev = crtc->dev;
9651 struct drm_i915_private *dev_priv = dev->dev_private;
9652 struct drm_framebuffer *old_fb = crtc->primary->fb;
9653 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9655 enum pipe pipe = intel_crtc->pipe;
9656 struct intel_unpin_work *work;
9657 struct intel_engine_cs *ring;
9658 unsigned long flags;
9662 * drm_mode_page_flip_ioctl() should already catch this, but double
9663 * check to be safe. In the future we may enable pageflipping from
9664 * a disabled primary plane.
9666 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9669 /* Can't change pixel format via MI display flips. */
9670 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9674 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9675 * Note that pitch changes could also affect these register.
9677 if (INTEL_INFO(dev)->gen > 3 &&
9678 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9679 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9682 if (i915_terminally_wedged(&dev_priv->gpu_error))
9685 work = kzalloc(sizeof(*work), GFP_KERNEL);
9689 work->event = event;
9691 work->old_fb_obj = intel_fb_obj(old_fb);
9692 INIT_WORK(&work->work, intel_unpin_work_fn);
9694 ret = drm_crtc_vblank_get(crtc);
9698 /* We borrow the event spin lock for protecting unpin_work */
9699 spin_lock_irqsave(&dev->event_lock, flags);
9700 if (intel_crtc->unpin_work) {
9701 spin_unlock_irqrestore(&dev->event_lock, flags);
9703 drm_crtc_vblank_put(crtc);
9705 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9708 intel_crtc->unpin_work = work;
9709 spin_unlock_irqrestore(&dev->event_lock, flags);
9711 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9712 flush_workqueue(dev_priv->wq);
9714 ret = i915_mutex_lock_interruptible(dev);
9718 /* Reference the objects for the scheduled work. */
9719 drm_gem_object_reference(&work->old_fb_obj->base);
9720 drm_gem_object_reference(&obj->base);
9722 crtc->primary->fb = fb;
9724 work->pending_flip_obj = obj;
9726 work->enable_stall_check = true;
9728 atomic_inc(&intel_crtc->unpin_work_count);
9729 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9731 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9732 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9734 if (IS_VALLEYVIEW(dev)) {
9735 ring = &dev_priv->ring[BCS];
9736 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9737 /* vlv: DISPLAY_FLIP fails to change tiling */
9739 } else if (IS_IVYBRIDGE(dev)) {
9740 ring = &dev_priv->ring[BCS];
9741 } else if (INTEL_INFO(dev)->gen >= 7) {
9743 if (ring == NULL || ring->id != RCS)
9744 ring = &dev_priv->ring[BCS];
9746 ring = &dev_priv->ring[RCS];
9749 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9751 goto cleanup_pending;
9754 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9756 if (use_mmio_flip(ring, obj))
9757 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9760 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9765 i915_gem_track_fb(work->old_fb_obj, obj,
9766 INTEL_FRONTBUFFER_PRIMARY(pipe));
9768 intel_disable_fbc(dev);
9769 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9770 mutex_unlock(&dev->struct_mutex);
9772 trace_i915_flip_request(intel_crtc->plane, obj);
9777 intel_unpin_fb_obj(obj);
9779 atomic_dec(&intel_crtc->unpin_work_count);
9780 crtc->primary->fb = old_fb;
9781 drm_gem_object_unreference(&work->old_fb_obj->base);
9782 drm_gem_object_unreference(&obj->base);
9783 mutex_unlock(&dev->struct_mutex);
9786 spin_lock_irqsave(&dev->event_lock, flags);
9787 intel_crtc->unpin_work = NULL;
9788 spin_unlock_irqrestore(&dev->event_lock, flags);
9790 drm_crtc_vblank_put(crtc);
9796 intel_crtc_wait_for_pending_flips(crtc);
9797 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9798 if (ret == 0 && event)
9799 drm_send_vblank_event(dev, pipe, event);
9804 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9805 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9806 .load_lut = intel_crtc_load_lut,
9810 * intel_modeset_update_staged_output_state
9812 * Updates the staged output configuration state, e.g. after we've read out the
9815 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9817 struct intel_crtc *crtc;
9818 struct intel_encoder *encoder;
9819 struct intel_connector *connector;
9821 list_for_each_entry(connector, &dev->mode_config.connector_list,
9823 connector->new_encoder =
9824 to_intel_encoder(connector->base.encoder);
9827 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9830 to_intel_crtc(encoder->base.crtc);
9833 for_each_intel_crtc(dev, crtc) {
9834 crtc->new_enabled = crtc->base.enabled;
9836 if (crtc->new_enabled)
9837 crtc->new_config = &crtc->config;
9839 crtc->new_config = NULL;
9844 * intel_modeset_commit_output_state
9846 * This function copies the stage display pipe configuration to the real one.
9848 static void intel_modeset_commit_output_state(struct drm_device *dev)
9850 struct intel_crtc *crtc;
9851 struct intel_encoder *encoder;
9852 struct intel_connector *connector;
9854 list_for_each_entry(connector, &dev->mode_config.connector_list,
9856 connector->base.encoder = &connector->new_encoder->base;
9859 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9861 encoder->base.crtc = &encoder->new_crtc->base;
9864 for_each_intel_crtc(dev, crtc) {
9865 crtc->base.enabled = crtc->new_enabled;
9870 connected_sink_compute_bpp(struct intel_connector *connector,
9871 struct intel_crtc_config *pipe_config)
9873 int bpp = pipe_config->pipe_bpp;
9875 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9876 connector->base.base.id,
9877 connector->base.name);
9879 /* Don't use an invalid EDID bpc value */
9880 if (connector->base.display_info.bpc &&
9881 connector->base.display_info.bpc * 3 < bpp) {
9882 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9883 bpp, connector->base.display_info.bpc*3);
9884 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9887 /* Clamp bpp to 8 on screens without EDID 1.4 */
9888 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9889 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9891 pipe_config->pipe_bpp = 24;
9896 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9897 struct drm_framebuffer *fb,
9898 struct intel_crtc_config *pipe_config)
9900 struct drm_device *dev = crtc->base.dev;
9901 struct intel_connector *connector;
9904 switch (fb->pixel_format) {
9906 bpp = 8*3; /* since we go through a colormap */
9908 case DRM_FORMAT_XRGB1555:
9909 case DRM_FORMAT_ARGB1555:
9910 /* checked in intel_framebuffer_init already */
9911 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9913 case DRM_FORMAT_RGB565:
9914 bpp = 6*3; /* min is 18bpp */
9916 case DRM_FORMAT_XBGR8888:
9917 case DRM_FORMAT_ABGR8888:
9918 /* checked in intel_framebuffer_init already */
9919 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9921 case DRM_FORMAT_XRGB8888:
9922 case DRM_FORMAT_ARGB8888:
9925 case DRM_FORMAT_XRGB2101010:
9926 case DRM_FORMAT_ARGB2101010:
9927 case DRM_FORMAT_XBGR2101010:
9928 case DRM_FORMAT_ABGR2101010:
9929 /* checked in intel_framebuffer_init already */
9930 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9934 /* TODO: gen4+ supports 16 bpc floating point, too. */
9936 DRM_DEBUG_KMS("unsupported depth\n");
9940 pipe_config->pipe_bpp = bpp;
9942 /* Clamp display bpp to EDID value */
9943 list_for_each_entry(connector, &dev->mode_config.connector_list,
9945 if (!connector->new_encoder ||
9946 connector->new_encoder->new_crtc != crtc)
9949 connected_sink_compute_bpp(connector, pipe_config);
9955 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9957 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9958 "type: 0x%x flags: 0x%x\n",
9960 mode->crtc_hdisplay, mode->crtc_hsync_start,
9961 mode->crtc_hsync_end, mode->crtc_htotal,
9962 mode->crtc_vdisplay, mode->crtc_vsync_start,
9963 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9966 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9967 struct intel_crtc_config *pipe_config,
9968 const char *context)
9970 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9971 context, pipe_name(crtc->pipe));
9973 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9974 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9975 pipe_config->pipe_bpp, pipe_config->dither);
9976 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9977 pipe_config->has_pch_encoder,
9978 pipe_config->fdi_lanes,
9979 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9980 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9981 pipe_config->fdi_m_n.tu);
9982 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9983 pipe_config->has_dp_encoder,
9984 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9985 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9986 pipe_config->dp_m_n.tu);
9987 DRM_DEBUG_KMS("requested mode:\n");
9988 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9989 DRM_DEBUG_KMS("adjusted mode:\n");
9990 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9991 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9992 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9993 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9994 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9995 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9996 pipe_config->gmch_pfit.control,
9997 pipe_config->gmch_pfit.pgm_ratios,
9998 pipe_config->gmch_pfit.lvds_border_bits);
9999 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10000 pipe_config->pch_pfit.pos,
10001 pipe_config->pch_pfit.size,
10002 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10003 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10004 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10007 static bool encoders_cloneable(const struct intel_encoder *a,
10008 const struct intel_encoder *b)
10010 /* masks could be asymmetric, so check both ways */
10011 return a == b || (a->cloneable & (1 << b->type) &&
10012 b->cloneable & (1 << a->type));
10015 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10016 struct intel_encoder *encoder)
10018 struct drm_device *dev = crtc->base.dev;
10019 struct intel_encoder *source_encoder;
10021 list_for_each_entry(source_encoder,
10022 &dev->mode_config.encoder_list, base.head) {
10023 if (source_encoder->new_crtc != crtc)
10026 if (!encoders_cloneable(encoder, source_encoder))
10033 static bool check_encoder_cloning(struct intel_crtc *crtc)
10035 struct drm_device *dev = crtc->base.dev;
10036 struct intel_encoder *encoder;
10038 list_for_each_entry(encoder,
10039 &dev->mode_config.encoder_list, base.head) {
10040 if (encoder->new_crtc != crtc)
10043 if (!check_single_encoder_cloning(crtc, encoder))
10050 static struct intel_crtc_config *
10051 intel_modeset_pipe_config(struct drm_crtc *crtc,
10052 struct drm_framebuffer *fb,
10053 struct drm_display_mode *mode)
10055 struct drm_device *dev = crtc->dev;
10056 struct intel_encoder *encoder;
10057 struct intel_crtc_config *pipe_config;
10058 int plane_bpp, ret = -EINVAL;
10061 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10062 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10063 return ERR_PTR(-EINVAL);
10066 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10068 return ERR_PTR(-ENOMEM);
10070 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10071 drm_mode_copy(&pipe_config->requested_mode, mode);
10073 pipe_config->cpu_transcoder =
10074 (enum transcoder) to_intel_crtc(crtc)->pipe;
10075 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10078 * Sanitize sync polarity flags based on requested ones. If neither
10079 * positive or negative polarity is requested, treat this as meaning
10080 * negative polarity.
10082 if (!(pipe_config->adjusted_mode.flags &
10083 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10084 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10086 if (!(pipe_config->adjusted_mode.flags &
10087 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10088 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10090 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10091 * plane pixel format and any sink constraints into account. Returns the
10092 * source plane bpp so that dithering can be selected on mismatches
10093 * after encoders and crtc also have had their say. */
10094 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10100 * Determine the real pipe dimensions. Note that stereo modes can
10101 * increase the actual pipe size due to the frame doubling and
10102 * insertion of additional space for blanks between the frame. This
10103 * is stored in the crtc timings. We use the requested mode to do this
10104 * computation to clearly distinguish it from the adjusted mode, which
10105 * can be changed by the connectors in the below retry loop.
10107 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10108 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10109 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10112 /* Ensure the port clock defaults are reset when retrying. */
10113 pipe_config->port_clock = 0;
10114 pipe_config->pixel_multiplier = 1;
10116 /* Fill in default crtc timings, allow encoders to overwrite them. */
10117 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10119 /* Pass our mode to the connectors and the CRTC to give them a chance to
10120 * adjust it according to limitations or connector properties, and also
10121 * a chance to reject the mode entirely.
10123 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10126 if (&encoder->new_crtc->base != crtc)
10129 if (!(encoder->compute_config(encoder, pipe_config))) {
10130 DRM_DEBUG_KMS("Encoder config failure\n");
10135 /* Set default port clock if not overwritten by the encoder. Needs to be
10136 * done afterwards in case the encoder adjusts the mode. */
10137 if (!pipe_config->port_clock)
10138 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10139 * pipe_config->pixel_multiplier;
10141 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10143 DRM_DEBUG_KMS("CRTC fixup failed\n");
10147 if (ret == RETRY) {
10148 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10153 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10155 goto encoder_retry;
10158 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10159 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10160 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10162 return pipe_config;
10164 kfree(pipe_config);
10165 return ERR_PTR(ret);
10168 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10169 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10171 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10172 unsigned *prepare_pipes, unsigned *disable_pipes)
10174 struct intel_crtc *intel_crtc;
10175 struct drm_device *dev = crtc->dev;
10176 struct intel_encoder *encoder;
10177 struct intel_connector *connector;
10178 struct drm_crtc *tmp_crtc;
10180 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10182 /* Check which crtcs have changed outputs connected to them, these need
10183 * to be part of the prepare_pipes mask. We don't (yet) support global
10184 * modeset across multiple crtcs, so modeset_pipes will only have one
10185 * bit set at most. */
10186 list_for_each_entry(connector, &dev->mode_config.connector_list,
10188 if (connector->base.encoder == &connector->new_encoder->base)
10191 if (connector->base.encoder) {
10192 tmp_crtc = connector->base.encoder->crtc;
10194 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10197 if (connector->new_encoder)
10199 1 << connector->new_encoder->new_crtc->pipe;
10202 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10204 if (encoder->base.crtc == &encoder->new_crtc->base)
10207 if (encoder->base.crtc) {
10208 tmp_crtc = encoder->base.crtc;
10210 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10213 if (encoder->new_crtc)
10214 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10217 /* Check for pipes that will be enabled/disabled ... */
10218 for_each_intel_crtc(dev, intel_crtc) {
10219 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10222 if (!intel_crtc->new_enabled)
10223 *disable_pipes |= 1 << intel_crtc->pipe;
10225 *prepare_pipes |= 1 << intel_crtc->pipe;
10229 /* set_mode is also used to update properties on life display pipes. */
10230 intel_crtc = to_intel_crtc(crtc);
10231 if (intel_crtc->new_enabled)
10232 *prepare_pipes |= 1 << intel_crtc->pipe;
10235 * For simplicity do a full modeset on any pipe where the output routing
10236 * changed. We could be more clever, but that would require us to be
10237 * more careful with calling the relevant encoder->mode_set functions.
10239 if (*prepare_pipes)
10240 *modeset_pipes = *prepare_pipes;
10242 /* ... and mask these out. */
10243 *modeset_pipes &= ~(*disable_pipes);
10244 *prepare_pipes &= ~(*disable_pipes);
10247 * HACK: We don't (yet) fully support global modesets. intel_set_config
10248 * obies this rule, but the modeset restore mode of
10249 * intel_modeset_setup_hw_state does not.
10251 *modeset_pipes &= 1 << intel_crtc->pipe;
10252 *prepare_pipes &= 1 << intel_crtc->pipe;
10254 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10255 *modeset_pipes, *prepare_pipes, *disable_pipes);
10258 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10260 struct drm_encoder *encoder;
10261 struct drm_device *dev = crtc->dev;
10263 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10264 if (encoder->crtc == crtc)
10271 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10273 struct intel_encoder *intel_encoder;
10274 struct intel_crtc *intel_crtc;
10275 struct drm_connector *connector;
10277 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10279 if (!intel_encoder->base.crtc)
10282 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10284 if (prepare_pipes & (1 << intel_crtc->pipe))
10285 intel_encoder->connectors_active = false;
10288 intel_modeset_commit_output_state(dev);
10290 /* Double check state. */
10291 for_each_intel_crtc(dev, intel_crtc) {
10292 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10293 WARN_ON(intel_crtc->new_config &&
10294 intel_crtc->new_config != &intel_crtc->config);
10295 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10298 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10299 if (!connector->encoder || !connector->encoder->crtc)
10302 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10304 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10305 struct drm_property *dpms_property =
10306 dev->mode_config.dpms_property;
10308 connector->dpms = DRM_MODE_DPMS_ON;
10309 drm_object_property_set_value(&connector->base,
10313 intel_encoder = to_intel_encoder(connector->encoder);
10314 intel_encoder->connectors_active = true;
10320 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10324 if (clock1 == clock2)
10327 if (!clock1 || !clock2)
10330 diff = abs(clock1 - clock2);
10332 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10338 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10339 list_for_each_entry((intel_crtc), \
10340 &(dev)->mode_config.crtc_list, \
10342 if (mask & (1 <<(intel_crtc)->pipe))
10345 intel_pipe_config_compare(struct drm_device *dev,
10346 struct intel_crtc_config *current_config,
10347 struct intel_crtc_config *pipe_config)
10349 #define PIPE_CONF_CHECK_X(name) \
10350 if (current_config->name != pipe_config->name) { \
10351 DRM_ERROR("mismatch in " #name " " \
10352 "(expected 0x%08x, found 0x%08x)\n", \
10353 current_config->name, \
10354 pipe_config->name); \
10358 #define PIPE_CONF_CHECK_I(name) \
10359 if (current_config->name != pipe_config->name) { \
10360 DRM_ERROR("mismatch in " #name " " \
10361 "(expected %i, found %i)\n", \
10362 current_config->name, \
10363 pipe_config->name); \
10367 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10368 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10369 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10370 "(expected %i, found %i)\n", \
10371 current_config->name & (mask), \
10372 pipe_config->name & (mask)); \
10376 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10377 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10378 DRM_ERROR("mismatch in " #name " " \
10379 "(expected %i, found %i)\n", \
10380 current_config->name, \
10381 pipe_config->name); \
10385 #define PIPE_CONF_QUIRK(quirk) \
10386 ((current_config->quirks | pipe_config->quirks) & (quirk))
10388 PIPE_CONF_CHECK_I(cpu_transcoder);
10390 PIPE_CONF_CHECK_I(has_pch_encoder);
10391 PIPE_CONF_CHECK_I(fdi_lanes);
10392 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10393 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10394 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10395 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10396 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10398 PIPE_CONF_CHECK_I(has_dp_encoder);
10399 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10400 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10401 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10402 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10403 PIPE_CONF_CHECK_I(dp_m_n.tu);
10405 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10406 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10407 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10408 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10409 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10410 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10412 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10413 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10414 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10415 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10416 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10417 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10419 PIPE_CONF_CHECK_I(pixel_multiplier);
10420 PIPE_CONF_CHECK_I(has_hdmi_sink);
10421 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10422 IS_VALLEYVIEW(dev))
10423 PIPE_CONF_CHECK_I(limited_color_range);
10425 PIPE_CONF_CHECK_I(has_audio);
10427 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10428 DRM_MODE_FLAG_INTERLACE);
10430 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10431 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10432 DRM_MODE_FLAG_PHSYNC);
10433 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10434 DRM_MODE_FLAG_NHSYNC);
10435 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10436 DRM_MODE_FLAG_PVSYNC);
10437 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10438 DRM_MODE_FLAG_NVSYNC);
10441 PIPE_CONF_CHECK_I(pipe_src_w);
10442 PIPE_CONF_CHECK_I(pipe_src_h);
10445 * FIXME: BIOS likes to set up a cloned config with lvds+external
10446 * screen. Since we don't yet re-compute the pipe config when moving
10447 * just the lvds port away to another pipe the sw tracking won't match.
10449 * Proper atomic modesets with recomputed global state will fix this.
10450 * Until then just don't check gmch state for inherited modes.
10452 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10453 PIPE_CONF_CHECK_I(gmch_pfit.control);
10454 /* pfit ratios are autocomputed by the hw on gen4+ */
10455 if (INTEL_INFO(dev)->gen < 4)
10456 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10457 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10460 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10461 if (current_config->pch_pfit.enabled) {
10462 PIPE_CONF_CHECK_I(pch_pfit.pos);
10463 PIPE_CONF_CHECK_I(pch_pfit.size);
10466 /* BDW+ don't expose a synchronous way to read the state */
10467 if (IS_HASWELL(dev))
10468 PIPE_CONF_CHECK_I(ips_enabled);
10470 PIPE_CONF_CHECK_I(double_wide);
10472 PIPE_CONF_CHECK_X(ddi_pll_sel);
10474 PIPE_CONF_CHECK_I(shared_dpll);
10475 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10476 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10477 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10478 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10479 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10481 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10482 PIPE_CONF_CHECK_I(pipe_bpp);
10484 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10485 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10487 #undef PIPE_CONF_CHECK_X
10488 #undef PIPE_CONF_CHECK_I
10489 #undef PIPE_CONF_CHECK_FLAGS
10490 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10491 #undef PIPE_CONF_QUIRK
10497 check_connector_state(struct drm_device *dev)
10499 struct intel_connector *connector;
10501 list_for_each_entry(connector, &dev->mode_config.connector_list,
10503 /* This also checks the encoder/connector hw state with the
10504 * ->get_hw_state callbacks. */
10505 intel_connector_check_state(connector);
10507 WARN(&connector->new_encoder->base != connector->base.encoder,
10508 "connector's staged encoder doesn't match current encoder\n");
10513 check_encoder_state(struct drm_device *dev)
10515 struct intel_encoder *encoder;
10516 struct intel_connector *connector;
10518 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10520 bool enabled = false;
10521 bool active = false;
10522 enum pipe pipe, tracked_pipe;
10524 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10525 encoder->base.base.id,
10526 encoder->base.name);
10528 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10529 "encoder's stage crtc doesn't match current crtc\n");
10530 WARN(encoder->connectors_active && !encoder->base.crtc,
10531 "encoder's active_connectors set, but no crtc\n");
10533 list_for_each_entry(connector, &dev->mode_config.connector_list,
10535 if (connector->base.encoder != &encoder->base)
10538 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10542 * for MST connectors if we unplug the connector is gone
10543 * away but the encoder is still connected to a crtc
10544 * until a modeset happens in response to the hotplug.
10546 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10549 WARN(!!encoder->base.crtc != enabled,
10550 "encoder's enabled state mismatch "
10551 "(expected %i, found %i)\n",
10552 !!encoder->base.crtc, enabled);
10553 WARN(active && !encoder->base.crtc,
10554 "active encoder with no crtc\n");
10556 WARN(encoder->connectors_active != active,
10557 "encoder's computed active state doesn't match tracked active state "
10558 "(expected %i, found %i)\n", active, encoder->connectors_active);
10560 active = encoder->get_hw_state(encoder, &pipe);
10561 WARN(active != encoder->connectors_active,
10562 "encoder's hw state doesn't match sw tracking "
10563 "(expected %i, found %i)\n",
10564 encoder->connectors_active, active);
10566 if (!encoder->base.crtc)
10569 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10570 WARN(active && pipe != tracked_pipe,
10571 "active encoder's pipe doesn't match"
10572 "(expected %i, found %i)\n",
10573 tracked_pipe, pipe);
10579 check_crtc_state(struct drm_device *dev)
10581 struct drm_i915_private *dev_priv = dev->dev_private;
10582 struct intel_crtc *crtc;
10583 struct intel_encoder *encoder;
10584 struct intel_crtc_config pipe_config;
10586 for_each_intel_crtc(dev, crtc) {
10587 bool enabled = false;
10588 bool active = false;
10590 memset(&pipe_config, 0, sizeof(pipe_config));
10592 DRM_DEBUG_KMS("[CRTC:%d]\n",
10593 crtc->base.base.id);
10595 WARN(crtc->active && !crtc->base.enabled,
10596 "active crtc, but not enabled in sw tracking\n");
10598 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10600 if (encoder->base.crtc != &crtc->base)
10603 if (encoder->connectors_active)
10607 WARN(active != crtc->active,
10608 "crtc's computed active state doesn't match tracked active state "
10609 "(expected %i, found %i)\n", active, crtc->active);
10610 WARN(enabled != crtc->base.enabled,
10611 "crtc's computed enabled state doesn't match tracked enabled state "
10612 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10614 active = dev_priv->display.get_pipe_config(crtc,
10617 /* hw state is inconsistent with the pipe A quirk */
10618 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10619 active = crtc->active;
10621 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10624 if (encoder->base.crtc != &crtc->base)
10626 if (encoder->get_hw_state(encoder, &pipe))
10627 encoder->get_config(encoder, &pipe_config);
10630 WARN(crtc->active != active,
10631 "crtc active state doesn't match with hw state "
10632 "(expected %i, found %i)\n", crtc->active, active);
10635 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10636 WARN(1, "pipe state doesn't match!\n");
10637 intel_dump_pipe_config(crtc, &pipe_config,
10639 intel_dump_pipe_config(crtc, &crtc->config,
10646 check_shared_dpll_state(struct drm_device *dev)
10648 struct drm_i915_private *dev_priv = dev->dev_private;
10649 struct intel_crtc *crtc;
10650 struct intel_dpll_hw_state dpll_hw_state;
10653 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10654 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10655 int enabled_crtcs = 0, active_crtcs = 0;
10658 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10660 DRM_DEBUG_KMS("%s\n", pll->name);
10662 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10664 WARN(pll->active > pll->refcount,
10665 "more active pll users than references: %i vs %i\n",
10666 pll->active, pll->refcount);
10667 WARN(pll->active && !pll->on,
10668 "pll in active use but not on in sw tracking\n");
10669 WARN(pll->on && !pll->active,
10670 "pll in on but not on in use in sw tracking\n");
10671 WARN(pll->on != active,
10672 "pll on state mismatch (expected %i, found %i)\n",
10675 for_each_intel_crtc(dev, crtc) {
10676 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10678 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10681 WARN(pll->active != active_crtcs,
10682 "pll active crtcs mismatch (expected %i, found %i)\n",
10683 pll->active, active_crtcs);
10684 WARN(pll->refcount != enabled_crtcs,
10685 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10686 pll->refcount, enabled_crtcs);
10688 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10689 sizeof(dpll_hw_state)),
10690 "pll hw state mismatch\n");
10695 intel_modeset_check_state(struct drm_device *dev)
10697 check_connector_state(dev);
10698 check_encoder_state(dev);
10699 check_crtc_state(dev);
10700 check_shared_dpll_state(dev);
10703 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10707 * FDI already provided one idea for the dotclock.
10708 * Yell if the encoder disagrees.
10710 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10711 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10712 pipe_config->adjusted_mode.crtc_clock, dotclock);
10715 static void update_scanline_offset(struct intel_crtc *crtc)
10717 struct drm_device *dev = crtc->base.dev;
10720 * The scanline counter increments at the leading edge of hsync.
10722 * On most platforms it starts counting from vtotal-1 on the
10723 * first active line. That means the scanline counter value is
10724 * always one less than what we would expect. Ie. just after
10725 * start of vblank, which also occurs at start of hsync (on the
10726 * last active line), the scanline counter will read vblank_start-1.
10728 * On gen2 the scanline counter starts counting from 1 instead
10729 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10730 * to keep the value positive), instead of adding one.
10732 * On HSW+ the behaviour of the scanline counter depends on the output
10733 * type. For DP ports it behaves like most other platforms, but on HDMI
10734 * there's an extra 1 line difference. So we need to add two instead of
10735 * one to the value.
10737 if (IS_GEN2(dev)) {
10738 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10741 vtotal = mode->crtc_vtotal;
10742 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10745 crtc->scanline_offset = vtotal - 1;
10746 } else if (HAS_DDI(dev) &&
10747 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10748 crtc->scanline_offset = 2;
10750 crtc->scanline_offset = 1;
10753 static int __intel_set_mode(struct drm_crtc *crtc,
10754 struct drm_display_mode *mode,
10755 int x, int y, struct drm_framebuffer *fb)
10757 struct drm_device *dev = crtc->dev;
10758 struct drm_i915_private *dev_priv = dev->dev_private;
10759 struct drm_display_mode *saved_mode;
10760 struct intel_crtc_config *pipe_config = NULL;
10761 struct intel_crtc *intel_crtc;
10762 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10765 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10769 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10770 &prepare_pipes, &disable_pipes);
10772 *saved_mode = crtc->mode;
10774 /* Hack: Because we don't (yet) support global modeset on multiple
10775 * crtcs, we don't keep track of the new mode for more than one crtc.
10776 * Hence simply check whether any bit is set in modeset_pipes in all the
10777 * pieces of code that are not yet converted to deal with mutliple crtcs
10778 * changing their mode at the same time. */
10779 if (modeset_pipes) {
10780 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10781 if (IS_ERR(pipe_config)) {
10782 ret = PTR_ERR(pipe_config);
10783 pipe_config = NULL;
10787 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10789 to_intel_crtc(crtc)->new_config = pipe_config;
10793 * See if the config requires any additional preparation, e.g.
10794 * to adjust global state with pipes off. We need to do this
10795 * here so we can get the modeset_pipe updated config for the new
10796 * mode set on this crtc. For other crtcs we need to use the
10797 * adjusted_mode bits in the crtc directly.
10799 if (IS_VALLEYVIEW(dev)) {
10800 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10802 /* may have added more to prepare_pipes than we should */
10803 prepare_pipes &= ~disable_pipes;
10806 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10807 intel_crtc_disable(&intel_crtc->base);
10809 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10810 if (intel_crtc->base.enabled)
10811 dev_priv->display.crtc_disable(&intel_crtc->base);
10814 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10815 * to set it here already despite that we pass it down the callchain.
10817 if (modeset_pipes) {
10818 crtc->mode = *mode;
10819 /* mode_set/enable/disable functions rely on a correct pipe
10821 to_intel_crtc(crtc)->config = *pipe_config;
10822 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10825 * Calculate and store various constants which
10826 * are later needed by vblank and swap-completion
10827 * timestamping. They are derived from true hwmode.
10829 drm_calc_timestamping_constants(crtc,
10830 &pipe_config->adjusted_mode);
10833 /* Only after disabling all output pipelines that will be changed can we
10834 * update the the output configuration. */
10835 intel_modeset_update_state(dev, prepare_pipes);
10837 if (dev_priv->display.modeset_global_resources)
10838 dev_priv->display.modeset_global_resources(dev);
10840 /* Set up the DPLL and any encoders state that needs to adjust or depend
10843 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10844 struct drm_framebuffer *old_fb = crtc->primary->fb;
10845 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10846 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10848 mutex_lock(&dev->struct_mutex);
10849 ret = intel_pin_and_fence_fb_obj(dev,
10853 DRM_ERROR("pin & fence failed\n");
10854 mutex_unlock(&dev->struct_mutex);
10858 intel_unpin_fb_obj(old_obj);
10859 i915_gem_track_fb(old_obj, obj,
10860 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10861 mutex_unlock(&dev->struct_mutex);
10863 crtc->primary->fb = fb;
10867 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10873 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10874 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10875 update_scanline_offset(intel_crtc);
10877 dev_priv->display.crtc_enable(&intel_crtc->base);
10880 /* FIXME: add subpixel order */
10882 if (ret && crtc->enabled)
10883 crtc->mode = *saved_mode;
10886 kfree(pipe_config);
10891 static int intel_set_mode(struct drm_crtc *crtc,
10892 struct drm_display_mode *mode,
10893 int x, int y, struct drm_framebuffer *fb)
10897 ret = __intel_set_mode(crtc, mode, x, y, fb);
10900 intel_modeset_check_state(crtc->dev);
10905 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10907 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10910 #undef for_each_intel_crtc_masked
10912 static void intel_set_config_free(struct intel_set_config *config)
10917 kfree(config->save_connector_encoders);
10918 kfree(config->save_encoder_crtcs);
10919 kfree(config->save_crtc_enabled);
10923 static int intel_set_config_save_state(struct drm_device *dev,
10924 struct intel_set_config *config)
10926 struct drm_crtc *crtc;
10927 struct drm_encoder *encoder;
10928 struct drm_connector *connector;
10931 config->save_crtc_enabled =
10932 kcalloc(dev->mode_config.num_crtc,
10933 sizeof(bool), GFP_KERNEL);
10934 if (!config->save_crtc_enabled)
10937 config->save_encoder_crtcs =
10938 kcalloc(dev->mode_config.num_encoder,
10939 sizeof(struct drm_crtc *), GFP_KERNEL);
10940 if (!config->save_encoder_crtcs)
10943 config->save_connector_encoders =
10944 kcalloc(dev->mode_config.num_connector,
10945 sizeof(struct drm_encoder *), GFP_KERNEL);
10946 if (!config->save_connector_encoders)
10949 /* Copy data. Note that driver private data is not affected.
10950 * Should anything bad happen only the expected state is
10951 * restored, not the drivers personal bookkeeping.
10954 for_each_crtc(dev, crtc) {
10955 config->save_crtc_enabled[count++] = crtc->enabled;
10959 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10960 config->save_encoder_crtcs[count++] = encoder->crtc;
10964 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10965 config->save_connector_encoders[count++] = connector->encoder;
10971 static void intel_set_config_restore_state(struct drm_device *dev,
10972 struct intel_set_config *config)
10974 struct intel_crtc *crtc;
10975 struct intel_encoder *encoder;
10976 struct intel_connector *connector;
10980 for_each_intel_crtc(dev, crtc) {
10981 crtc->new_enabled = config->save_crtc_enabled[count++];
10983 if (crtc->new_enabled)
10984 crtc->new_config = &crtc->config;
10986 crtc->new_config = NULL;
10990 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10991 encoder->new_crtc =
10992 to_intel_crtc(config->save_encoder_crtcs[count++]);
10996 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10997 connector->new_encoder =
10998 to_intel_encoder(config->save_connector_encoders[count++]);
11003 is_crtc_connector_off(struct drm_mode_set *set)
11007 if (set->num_connectors == 0)
11010 if (WARN_ON(set->connectors == NULL))
11013 for (i = 0; i < set->num_connectors; i++)
11014 if (set->connectors[i]->encoder &&
11015 set->connectors[i]->encoder->crtc == set->crtc &&
11016 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11023 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11024 struct intel_set_config *config)
11027 /* We should be able to check here if the fb has the same properties
11028 * and then just flip_or_move it */
11029 if (is_crtc_connector_off(set)) {
11030 config->mode_changed = true;
11031 } else if (set->crtc->primary->fb != set->fb) {
11033 * If we have no fb, we can only flip as long as the crtc is
11034 * active, otherwise we need a full mode set. The crtc may
11035 * be active if we've only disabled the primary plane, or
11036 * in fastboot situations.
11038 if (set->crtc->primary->fb == NULL) {
11039 struct intel_crtc *intel_crtc =
11040 to_intel_crtc(set->crtc);
11042 if (intel_crtc->active) {
11043 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11044 config->fb_changed = true;
11046 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11047 config->mode_changed = true;
11049 } else if (set->fb == NULL) {
11050 config->mode_changed = true;
11051 } else if (set->fb->pixel_format !=
11052 set->crtc->primary->fb->pixel_format) {
11053 config->mode_changed = true;
11055 config->fb_changed = true;
11059 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11060 config->fb_changed = true;
11062 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11063 DRM_DEBUG_KMS("modes are different, full mode set\n");
11064 drm_mode_debug_printmodeline(&set->crtc->mode);
11065 drm_mode_debug_printmodeline(set->mode);
11066 config->mode_changed = true;
11069 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11070 set->crtc->base.id, config->mode_changed, config->fb_changed);
11074 intel_modeset_stage_output_state(struct drm_device *dev,
11075 struct drm_mode_set *set,
11076 struct intel_set_config *config)
11078 struct intel_connector *connector;
11079 struct intel_encoder *encoder;
11080 struct intel_crtc *crtc;
11083 /* The upper layers ensure that we either disable a crtc or have a list
11084 * of connectors. For paranoia, double-check this. */
11085 WARN_ON(!set->fb && (set->num_connectors != 0));
11086 WARN_ON(set->fb && (set->num_connectors == 0));
11088 list_for_each_entry(connector, &dev->mode_config.connector_list,
11090 /* Otherwise traverse passed in connector list and get encoders
11092 for (ro = 0; ro < set->num_connectors; ro++) {
11093 if (set->connectors[ro] == &connector->base) {
11094 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11099 /* If we disable the crtc, disable all its connectors. Also, if
11100 * the connector is on the changing crtc but not on the new
11101 * connector list, disable it. */
11102 if ((!set->fb || ro == set->num_connectors) &&
11103 connector->base.encoder &&
11104 connector->base.encoder->crtc == set->crtc) {
11105 connector->new_encoder = NULL;
11107 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11108 connector->base.base.id,
11109 connector->base.name);
11113 if (&connector->new_encoder->base != connector->base.encoder) {
11114 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11115 config->mode_changed = true;
11118 /* connector->new_encoder is now updated for all connectors. */
11120 /* Update crtc of enabled connectors. */
11121 list_for_each_entry(connector, &dev->mode_config.connector_list,
11123 struct drm_crtc *new_crtc;
11125 if (!connector->new_encoder)
11128 new_crtc = connector->new_encoder->base.crtc;
11130 for (ro = 0; ro < set->num_connectors; ro++) {
11131 if (set->connectors[ro] == &connector->base)
11132 new_crtc = set->crtc;
11135 /* Make sure the new CRTC will work with the encoder */
11136 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11140 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11142 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11143 connector->base.base.id,
11144 connector->base.name,
11145 new_crtc->base.id);
11148 /* Check for any encoders that needs to be disabled. */
11149 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11151 int num_connectors = 0;
11152 list_for_each_entry(connector,
11153 &dev->mode_config.connector_list,
11155 if (connector->new_encoder == encoder) {
11156 WARN_ON(!connector->new_encoder->new_crtc);
11161 if (num_connectors == 0)
11162 encoder->new_crtc = NULL;
11163 else if (num_connectors > 1)
11166 /* Only now check for crtc changes so we don't miss encoders
11167 * that will be disabled. */
11168 if (&encoder->new_crtc->base != encoder->base.crtc) {
11169 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11170 config->mode_changed = true;
11173 /* Now we've also updated encoder->new_crtc for all encoders. */
11174 list_for_each_entry(connector, &dev->mode_config.connector_list,
11176 if (connector->new_encoder)
11177 if (connector->new_encoder != connector->encoder)
11178 connector->encoder = connector->new_encoder;
11180 for_each_intel_crtc(dev, crtc) {
11181 crtc->new_enabled = false;
11183 list_for_each_entry(encoder,
11184 &dev->mode_config.encoder_list,
11186 if (encoder->new_crtc == crtc) {
11187 crtc->new_enabled = true;
11192 if (crtc->new_enabled != crtc->base.enabled) {
11193 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11194 crtc->new_enabled ? "en" : "dis");
11195 config->mode_changed = true;
11198 if (crtc->new_enabled)
11199 crtc->new_config = &crtc->config;
11201 crtc->new_config = NULL;
11207 static void disable_crtc_nofb(struct intel_crtc *crtc)
11209 struct drm_device *dev = crtc->base.dev;
11210 struct intel_encoder *encoder;
11211 struct intel_connector *connector;
11213 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11214 pipe_name(crtc->pipe));
11216 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11217 if (connector->new_encoder &&
11218 connector->new_encoder->new_crtc == crtc)
11219 connector->new_encoder = NULL;
11222 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11223 if (encoder->new_crtc == crtc)
11224 encoder->new_crtc = NULL;
11227 crtc->new_enabled = false;
11228 crtc->new_config = NULL;
11231 static int intel_crtc_set_config(struct drm_mode_set *set)
11233 struct drm_device *dev;
11234 struct drm_mode_set save_set;
11235 struct intel_set_config *config;
11239 BUG_ON(!set->crtc);
11240 BUG_ON(!set->crtc->helper_private);
11242 /* Enforce sane interface api - has been abused by the fb helper. */
11243 BUG_ON(!set->mode && set->fb);
11244 BUG_ON(set->fb && set->num_connectors == 0);
11247 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11248 set->crtc->base.id, set->fb->base.id,
11249 (int)set->num_connectors, set->x, set->y);
11251 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11254 dev = set->crtc->dev;
11257 config = kzalloc(sizeof(*config), GFP_KERNEL);
11261 ret = intel_set_config_save_state(dev, config);
11265 save_set.crtc = set->crtc;
11266 save_set.mode = &set->crtc->mode;
11267 save_set.x = set->crtc->x;
11268 save_set.y = set->crtc->y;
11269 save_set.fb = set->crtc->primary->fb;
11271 /* Compute whether we need a full modeset, only an fb base update or no
11272 * change at all. In the future we might also check whether only the
11273 * mode changed, e.g. for LVDS where we only change the panel fitter in
11275 intel_set_config_compute_mode_changes(set, config);
11277 ret = intel_modeset_stage_output_state(dev, set, config);
11281 if (config->mode_changed) {
11282 ret = intel_set_mode(set->crtc, set->mode,
11283 set->x, set->y, set->fb);
11284 } else if (config->fb_changed) {
11285 struct drm_i915_private *dev_priv = dev->dev_private;
11286 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11288 intel_crtc_wait_for_pending_flips(set->crtc);
11290 ret = intel_pipe_set_base(set->crtc,
11291 set->x, set->y, set->fb);
11294 * We need to make sure the primary plane is re-enabled if it
11295 * has previously been turned off.
11297 if (!intel_crtc->primary_enabled && ret == 0) {
11298 WARN_ON(!intel_crtc->active);
11299 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11304 * In the fastboot case this may be our only check of the
11305 * state after boot. It would be better to only do it on
11306 * the first update, but we don't have a nice way of doing that
11307 * (and really, set_config isn't used much for high freq page
11308 * flipping, so increasing its cost here shouldn't be a big
11311 if (i915.fastboot && ret == 0)
11312 intel_modeset_check_state(set->crtc->dev);
11316 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11317 set->crtc->base.id, ret);
11319 intel_set_config_restore_state(dev, config);
11322 * HACK: if the pipe was on, but we didn't have a framebuffer,
11323 * force the pipe off to avoid oopsing in the modeset code
11324 * due to fb==NULL. This should only happen during boot since
11325 * we don't yet reconstruct the FB from the hardware state.
11327 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11328 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11330 /* Try to restore the config */
11331 if (config->mode_changed &&
11332 intel_set_mode(save_set.crtc, save_set.mode,
11333 save_set.x, save_set.y, save_set.fb))
11334 DRM_ERROR("failed to restore config after modeset failure\n");
11338 intel_set_config_free(config);
11342 static const struct drm_crtc_funcs intel_crtc_funcs = {
11343 .gamma_set = intel_crtc_gamma_set,
11344 .set_config = intel_crtc_set_config,
11345 .destroy = intel_crtc_destroy,
11346 .page_flip = intel_crtc_page_flip,
11349 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11350 struct intel_shared_dpll *pll,
11351 struct intel_dpll_hw_state *hw_state)
11355 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11358 val = I915_READ(PCH_DPLL(pll->id));
11359 hw_state->dpll = val;
11360 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11361 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11363 return val & DPLL_VCO_ENABLE;
11366 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11367 struct intel_shared_dpll *pll)
11369 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11370 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11373 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11374 struct intel_shared_dpll *pll)
11376 /* PCH refclock must be enabled first */
11377 ibx_assert_pch_refclk_enabled(dev_priv);
11379 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11381 /* Wait for the clocks to stabilize. */
11382 POSTING_READ(PCH_DPLL(pll->id));
11385 /* The pixel multiplier can only be updated once the
11386 * DPLL is enabled and the clocks are stable.
11388 * So write it again.
11390 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11391 POSTING_READ(PCH_DPLL(pll->id));
11395 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11396 struct intel_shared_dpll *pll)
11398 struct drm_device *dev = dev_priv->dev;
11399 struct intel_crtc *crtc;
11401 /* Make sure no transcoder isn't still depending on us. */
11402 for_each_intel_crtc(dev, crtc) {
11403 if (intel_crtc_to_shared_dpll(crtc) == pll)
11404 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11407 I915_WRITE(PCH_DPLL(pll->id), 0);
11408 POSTING_READ(PCH_DPLL(pll->id));
11412 static char *ibx_pch_dpll_names[] = {
11417 static void ibx_pch_dpll_init(struct drm_device *dev)
11419 struct drm_i915_private *dev_priv = dev->dev_private;
11422 dev_priv->num_shared_dpll = 2;
11424 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11425 dev_priv->shared_dplls[i].id = i;
11426 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11427 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11428 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11429 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11430 dev_priv->shared_dplls[i].get_hw_state =
11431 ibx_pch_dpll_get_hw_state;
11435 static void intel_shared_dpll_init(struct drm_device *dev)
11437 struct drm_i915_private *dev_priv = dev->dev_private;
11440 intel_ddi_pll_init(dev);
11441 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11442 ibx_pch_dpll_init(dev);
11444 dev_priv->num_shared_dpll = 0;
11446 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11450 intel_primary_plane_disable(struct drm_plane *plane)
11452 struct drm_device *dev = plane->dev;
11453 struct drm_i915_private *dev_priv = dev->dev_private;
11454 struct intel_plane *intel_plane = to_intel_plane(plane);
11455 struct intel_crtc *intel_crtc;
11460 BUG_ON(!plane->crtc);
11462 intel_crtc = to_intel_crtc(plane->crtc);
11465 * Even though we checked plane->fb above, it's still possible that
11466 * the primary plane has been implicitly disabled because the crtc
11467 * coordinates given weren't visible, or because we detected
11468 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11469 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11470 * In either case, we need to unpin the FB and let the fb pointer get
11471 * updated, but otherwise we don't need to touch the hardware.
11473 if (!intel_crtc->primary_enabled)
11474 goto disable_unpin;
11476 intel_crtc_wait_for_pending_flips(plane->crtc);
11477 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11478 intel_plane->pipe);
11480 mutex_lock(&dev->struct_mutex);
11481 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11482 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11483 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11484 mutex_unlock(&dev->struct_mutex);
11491 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11492 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11493 unsigned int crtc_w, unsigned int crtc_h,
11494 uint32_t src_x, uint32_t src_y,
11495 uint32_t src_w, uint32_t src_h)
11497 struct drm_device *dev = crtc->dev;
11498 struct drm_i915_private *dev_priv = dev->dev_private;
11499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11500 struct intel_plane *intel_plane = to_intel_plane(plane);
11501 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11502 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11503 struct drm_rect dest = {
11504 /* integer pixels */
11507 .x2 = crtc_x + crtc_w,
11508 .y2 = crtc_y + crtc_h,
11510 struct drm_rect src = {
11511 /* 16.16 fixed point */
11514 .x2 = src_x + src_w,
11515 .y2 = src_y + src_h,
11517 const struct drm_rect clip = {
11518 /* integer pixels */
11519 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11520 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11525 ret = drm_plane_helper_check_update(plane, crtc, fb,
11526 &src, &dest, &clip,
11527 DRM_PLANE_HELPER_NO_SCALING,
11528 DRM_PLANE_HELPER_NO_SCALING,
11529 false, true, &visible);
11535 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11536 * updating the fb pointer, and returning without touching the
11537 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11538 * turn on the display with all planes setup as desired.
11540 if (!crtc->enabled) {
11541 mutex_lock(&dev->struct_mutex);
11544 * If we already called setplane while the crtc was disabled,
11545 * we may have an fb pinned; unpin it.
11548 intel_unpin_fb_obj(old_obj);
11550 i915_gem_track_fb(old_obj, obj,
11551 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11553 /* Pin and return without programming hardware */
11554 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11555 mutex_unlock(&dev->struct_mutex);
11560 intel_crtc_wait_for_pending_flips(crtc);
11563 * If clipping results in a non-visible primary plane, we'll disable
11564 * the primary plane. Note that this is a bit different than what
11565 * happens if userspace explicitly disables the plane by passing fb=0
11566 * because plane->fb still gets set and pinned.
11569 mutex_lock(&dev->struct_mutex);
11572 * Try to pin the new fb first so that we can bail out if we
11575 if (plane->fb != fb) {
11576 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11578 mutex_unlock(&dev->struct_mutex);
11583 i915_gem_track_fb(old_obj, obj,
11584 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11586 if (intel_crtc->primary_enabled)
11587 intel_disable_primary_hw_plane(dev_priv,
11588 intel_plane->plane,
11589 intel_plane->pipe);
11592 if (plane->fb != fb)
11594 intel_unpin_fb_obj(old_obj);
11596 mutex_unlock(&dev->struct_mutex);
11601 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11605 if (!intel_crtc->primary_enabled)
11606 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11612 /* Common destruction function for both primary and cursor planes */
11613 static void intel_plane_destroy(struct drm_plane *plane)
11615 struct intel_plane *intel_plane = to_intel_plane(plane);
11616 drm_plane_cleanup(plane);
11617 kfree(intel_plane);
11620 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11621 .update_plane = intel_primary_plane_setplane,
11622 .disable_plane = intel_primary_plane_disable,
11623 .destroy = intel_plane_destroy,
11626 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11629 struct intel_plane *primary;
11630 const uint32_t *intel_primary_formats;
11633 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11634 if (primary == NULL)
11637 primary->can_scale = false;
11638 primary->max_downscale = 1;
11639 primary->pipe = pipe;
11640 primary->plane = pipe;
11641 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11642 primary->plane = !pipe;
11644 if (INTEL_INFO(dev)->gen <= 3) {
11645 intel_primary_formats = intel_primary_formats_gen2;
11646 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11648 intel_primary_formats = intel_primary_formats_gen4;
11649 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11652 drm_universal_plane_init(dev, &primary->base, 0,
11653 &intel_primary_plane_funcs,
11654 intel_primary_formats, num_formats,
11655 DRM_PLANE_TYPE_PRIMARY);
11656 return &primary->base;
11660 intel_cursor_plane_disable(struct drm_plane *plane)
11665 BUG_ON(!plane->crtc);
11667 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11671 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11672 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11673 unsigned int crtc_w, unsigned int crtc_h,
11674 uint32_t src_x, uint32_t src_y,
11675 uint32_t src_w, uint32_t src_h)
11677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11678 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11679 struct drm_i915_gem_object *obj = intel_fb->obj;
11680 struct drm_rect dest = {
11681 /* integer pixels */
11684 .x2 = crtc_x + crtc_w,
11685 .y2 = crtc_y + crtc_h,
11687 struct drm_rect src = {
11688 /* 16.16 fixed point */
11691 .x2 = src_x + src_w,
11692 .y2 = src_y + src_h,
11694 const struct drm_rect clip = {
11695 /* integer pixels */
11696 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11697 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11702 ret = drm_plane_helper_check_update(plane, crtc, fb,
11703 &src, &dest, &clip,
11704 DRM_PLANE_HELPER_NO_SCALING,
11705 DRM_PLANE_HELPER_NO_SCALING,
11706 true, true, &visible);
11710 crtc->cursor_x = crtc_x;
11711 crtc->cursor_y = crtc_y;
11712 if (fb != crtc->cursor->fb) {
11713 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11715 intel_crtc_update_cursor(crtc, visible);
11719 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11720 .update_plane = intel_cursor_plane_update,
11721 .disable_plane = intel_cursor_plane_disable,
11722 .destroy = intel_plane_destroy,
11725 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11728 struct intel_plane *cursor;
11730 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11731 if (cursor == NULL)
11734 cursor->can_scale = false;
11735 cursor->max_downscale = 1;
11736 cursor->pipe = pipe;
11737 cursor->plane = pipe;
11739 drm_universal_plane_init(dev, &cursor->base, 0,
11740 &intel_cursor_plane_funcs,
11741 intel_cursor_formats,
11742 ARRAY_SIZE(intel_cursor_formats),
11743 DRM_PLANE_TYPE_CURSOR);
11744 return &cursor->base;
11747 static void intel_crtc_init(struct drm_device *dev, int pipe)
11749 struct drm_i915_private *dev_priv = dev->dev_private;
11750 struct intel_crtc *intel_crtc;
11751 struct drm_plane *primary = NULL;
11752 struct drm_plane *cursor = NULL;
11755 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11756 if (intel_crtc == NULL)
11759 primary = intel_primary_plane_create(dev, pipe);
11763 cursor = intel_cursor_plane_create(dev, pipe);
11767 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11768 cursor, &intel_crtc_funcs);
11772 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11773 for (i = 0; i < 256; i++) {
11774 intel_crtc->lut_r[i] = i;
11775 intel_crtc->lut_g[i] = i;
11776 intel_crtc->lut_b[i] = i;
11780 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11781 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11783 intel_crtc->pipe = pipe;
11784 intel_crtc->plane = pipe;
11785 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11786 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11787 intel_crtc->plane = !pipe;
11790 intel_crtc->cursor_base = ~0;
11791 intel_crtc->cursor_cntl = ~0;
11793 init_waitqueue_head(&intel_crtc->vbl_wait);
11795 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11796 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11797 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11798 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11800 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11802 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11807 drm_plane_cleanup(primary);
11809 drm_plane_cleanup(cursor);
11813 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11815 struct drm_encoder *encoder = connector->base.encoder;
11816 struct drm_device *dev = connector->base.dev;
11818 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11821 return INVALID_PIPE;
11823 return to_intel_crtc(encoder->crtc)->pipe;
11826 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11827 struct drm_file *file)
11829 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11830 struct drm_crtc *drmmode_crtc;
11831 struct intel_crtc *crtc;
11833 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11836 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11838 if (!drmmode_crtc) {
11839 DRM_ERROR("no such CRTC id\n");
11843 crtc = to_intel_crtc(drmmode_crtc);
11844 pipe_from_crtc_id->pipe = crtc->pipe;
11849 static int intel_encoder_clones(struct intel_encoder *encoder)
11851 struct drm_device *dev = encoder->base.dev;
11852 struct intel_encoder *source_encoder;
11853 int index_mask = 0;
11856 list_for_each_entry(source_encoder,
11857 &dev->mode_config.encoder_list, base.head) {
11858 if (encoders_cloneable(encoder, source_encoder))
11859 index_mask |= (1 << entry);
11867 static bool has_edp_a(struct drm_device *dev)
11869 struct drm_i915_private *dev_priv = dev->dev_private;
11871 if (!IS_MOBILE(dev))
11874 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11877 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11883 const char *intel_output_name(int output)
11885 static const char *names[] = {
11886 [INTEL_OUTPUT_UNUSED] = "Unused",
11887 [INTEL_OUTPUT_ANALOG] = "Analog",
11888 [INTEL_OUTPUT_DVO] = "DVO",
11889 [INTEL_OUTPUT_SDVO] = "SDVO",
11890 [INTEL_OUTPUT_LVDS] = "LVDS",
11891 [INTEL_OUTPUT_TVOUT] = "TV",
11892 [INTEL_OUTPUT_HDMI] = "HDMI",
11893 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11894 [INTEL_OUTPUT_EDP] = "eDP",
11895 [INTEL_OUTPUT_DSI] = "DSI",
11896 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11899 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11902 return names[output];
11905 static bool intel_crt_present(struct drm_device *dev)
11907 struct drm_i915_private *dev_priv = dev->dev_private;
11912 if (IS_CHERRYVIEW(dev))
11915 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11921 static void intel_setup_outputs(struct drm_device *dev)
11923 struct drm_i915_private *dev_priv = dev->dev_private;
11924 struct intel_encoder *encoder;
11925 bool dpd_is_edp = false;
11927 intel_lvds_init(dev);
11929 if (intel_crt_present(dev))
11930 intel_crt_init(dev);
11932 if (HAS_DDI(dev)) {
11935 /* Haswell uses DDI functions to detect digital outputs */
11936 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11937 /* DDI A only supports eDP */
11939 intel_ddi_init(dev, PORT_A);
11941 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11943 found = I915_READ(SFUSE_STRAP);
11945 if (found & SFUSE_STRAP_DDIB_DETECTED)
11946 intel_ddi_init(dev, PORT_B);
11947 if (found & SFUSE_STRAP_DDIC_DETECTED)
11948 intel_ddi_init(dev, PORT_C);
11949 if (found & SFUSE_STRAP_DDID_DETECTED)
11950 intel_ddi_init(dev, PORT_D);
11951 } else if (HAS_PCH_SPLIT(dev)) {
11953 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11955 if (has_edp_a(dev))
11956 intel_dp_init(dev, DP_A, PORT_A);
11958 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11959 /* PCH SDVOB multiplex with HDMIB */
11960 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11962 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11963 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11964 intel_dp_init(dev, PCH_DP_B, PORT_B);
11967 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11968 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11970 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11971 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11973 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11974 intel_dp_init(dev, PCH_DP_C, PORT_C);
11976 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11977 intel_dp_init(dev, PCH_DP_D, PORT_D);
11978 } else if (IS_VALLEYVIEW(dev)) {
11979 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11980 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11982 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11983 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11986 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11987 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11989 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11990 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11993 if (IS_CHERRYVIEW(dev)) {
11994 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11995 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11997 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11998 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12002 intel_dsi_init(dev);
12003 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12004 bool found = false;
12006 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12007 DRM_DEBUG_KMS("probing SDVOB\n");
12008 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12009 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12010 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12011 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12014 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12015 intel_dp_init(dev, DP_B, PORT_B);
12018 /* Before G4X SDVOC doesn't have its own detect register */
12020 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12021 DRM_DEBUG_KMS("probing SDVOC\n");
12022 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12025 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12027 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12028 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12029 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12031 if (SUPPORTS_INTEGRATED_DP(dev))
12032 intel_dp_init(dev, DP_C, PORT_C);
12035 if (SUPPORTS_INTEGRATED_DP(dev) &&
12036 (I915_READ(DP_D) & DP_DETECTED))
12037 intel_dp_init(dev, DP_D, PORT_D);
12038 } else if (IS_GEN2(dev))
12039 intel_dvo_init(dev);
12041 if (SUPPORTS_TV(dev))
12042 intel_tv_init(dev);
12044 intel_edp_psr_init(dev);
12046 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
12047 encoder->base.possible_crtcs = encoder->crtc_mask;
12048 encoder->base.possible_clones =
12049 intel_encoder_clones(encoder);
12052 intel_init_pch_refclk(dev);
12054 drm_helper_move_panel_connectors_to_head(dev);
12057 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12059 struct drm_device *dev = fb->dev;
12060 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12062 drm_framebuffer_cleanup(fb);
12063 mutex_lock(&dev->struct_mutex);
12064 WARN_ON(!intel_fb->obj->framebuffer_references--);
12065 drm_gem_object_unreference(&intel_fb->obj->base);
12066 mutex_unlock(&dev->struct_mutex);
12070 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12071 struct drm_file *file,
12072 unsigned int *handle)
12074 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12075 struct drm_i915_gem_object *obj = intel_fb->obj;
12077 return drm_gem_handle_create(file, &obj->base, handle);
12080 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12081 .destroy = intel_user_framebuffer_destroy,
12082 .create_handle = intel_user_framebuffer_create_handle,
12085 static int intel_framebuffer_init(struct drm_device *dev,
12086 struct intel_framebuffer *intel_fb,
12087 struct drm_mode_fb_cmd2 *mode_cmd,
12088 struct drm_i915_gem_object *obj)
12090 int aligned_height;
12094 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12096 if (obj->tiling_mode == I915_TILING_Y) {
12097 DRM_DEBUG("hardware does not support tiling Y\n");
12101 if (mode_cmd->pitches[0] & 63) {
12102 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12103 mode_cmd->pitches[0]);
12107 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12108 pitch_limit = 32*1024;
12109 } else if (INTEL_INFO(dev)->gen >= 4) {
12110 if (obj->tiling_mode)
12111 pitch_limit = 16*1024;
12113 pitch_limit = 32*1024;
12114 } else if (INTEL_INFO(dev)->gen >= 3) {
12115 if (obj->tiling_mode)
12116 pitch_limit = 8*1024;
12118 pitch_limit = 16*1024;
12120 /* XXX DSPC is limited to 4k tiled */
12121 pitch_limit = 8*1024;
12123 if (mode_cmd->pitches[0] > pitch_limit) {
12124 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12125 obj->tiling_mode ? "tiled" : "linear",
12126 mode_cmd->pitches[0], pitch_limit);
12130 if (obj->tiling_mode != I915_TILING_NONE &&
12131 mode_cmd->pitches[0] != obj->stride) {
12132 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12133 mode_cmd->pitches[0], obj->stride);
12137 /* Reject formats not supported by any plane early. */
12138 switch (mode_cmd->pixel_format) {
12139 case DRM_FORMAT_C8:
12140 case DRM_FORMAT_RGB565:
12141 case DRM_FORMAT_XRGB8888:
12142 case DRM_FORMAT_ARGB8888:
12144 case DRM_FORMAT_XRGB1555:
12145 case DRM_FORMAT_ARGB1555:
12146 if (INTEL_INFO(dev)->gen > 3) {
12147 DRM_DEBUG("unsupported pixel format: %s\n",
12148 drm_get_format_name(mode_cmd->pixel_format));
12152 case DRM_FORMAT_XBGR8888:
12153 case DRM_FORMAT_ABGR8888:
12154 case DRM_FORMAT_XRGB2101010:
12155 case DRM_FORMAT_ARGB2101010:
12156 case DRM_FORMAT_XBGR2101010:
12157 case DRM_FORMAT_ABGR2101010:
12158 if (INTEL_INFO(dev)->gen < 4) {
12159 DRM_DEBUG("unsupported pixel format: %s\n",
12160 drm_get_format_name(mode_cmd->pixel_format));
12164 case DRM_FORMAT_YUYV:
12165 case DRM_FORMAT_UYVY:
12166 case DRM_FORMAT_YVYU:
12167 case DRM_FORMAT_VYUY:
12168 if (INTEL_INFO(dev)->gen < 5) {
12169 DRM_DEBUG("unsupported pixel format: %s\n",
12170 drm_get_format_name(mode_cmd->pixel_format));
12175 DRM_DEBUG("unsupported pixel format: %s\n",
12176 drm_get_format_name(mode_cmd->pixel_format));
12180 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12181 if (mode_cmd->offsets[0] != 0)
12184 aligned_height = intel_align_height(dev, mode_cmd->height,
12186 /* FIXME drm helper for size checks (especially planar formats)? */
12187 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12190 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12191 intel_fb->obj = obj;
12192 intel_fb->obj->framebuffer_references++;
12194 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12196 DRM_ERROR("framebuffer init failed %d\n", ret);
12203 static struct drm_framebuffer *
12204 intel_user_framebuffer_create(struct drm_device *dev,
12205 struct drm_file *filp,
12206 struct drm_mode_fb_cmd2 *mode_cmd)
12208 struct drm_i915_gem_object *obj;
12210 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12211 mode_cmd->handles[0]));
12212 if (&obj->base == NULL)
12213 return ERR_PTR(-ENOENT);
12215 return intel_framebuffer_create(dev, mode_cmd, obj);
12218 #ifndef CONFIG_DRM_I915_FBDEV
12219 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12224 static const struct drm_mode_config_funcs intel_mode_funcs = {
12225 .fb_create = intel_user_framebuffer_create,
12226 .output_poll_changed = intel_fbdev_output_poll_changed,
12229 /* Set up chip specific display functions */
12230 static void intel_init_display(struct drm_device *dev)
12232 struct drm_i915_private *dev_priv = dev->dev_private;
12234 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12235 dev_priv->display.find_dpll = g4x_find_best_dpll;
12236 else if (IS_CHERRYVIEW(dev))
12237 dev_priv->display.find_dpll = chv_find_best_dpll;
12238 else if (IS_VALLEYVIEW(dev))
12239 dev_priv->display.find_dpll = vlv_find_best_dpll;
12240 else if (IS_PINEVIEW(dev))
12241 dev_priv->display.find_dpll = pnv_find_best_dpll;
12243 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12245 if (HAS_DDI(dev)) {
12246 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12247 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12248 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12249 dev_priv->display.crtc_enable = haswell_crtc_enable;
12250 dev_priv->display.crtc_disable = haswell_crtc_disable;
12251 dev_priv->display.off = ironlake_crtc_off;
12252 dev_priv->display.update_primary_plane =
12253 ironlake_update_primary_plane;
12254 } else if (HAS_PCH_SPLIT(dev)) {
12255 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12256 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12257 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12258 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12259 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12260 dev_priv->display.off = ironlake_crtc_off;
12261 dev_priv->display.update_primary_plane =
12262 ironlake_update_primary_plane;
12263 } else if (IS_VALLEYVIEW(dev)) {
12264 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12265 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12266 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12267 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12268 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12269 dev_priv->display.off = i9xx_crtc_off;
12270 dev_priv->display.update_primary_plane =
12271 i9xx_update_primary_plane;
12273 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12274 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12275 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12276 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12277 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12278 dev_priv->display.off = i9xx_crtc_off;
12279 dev_priv->display.update_primary_plane =
12280 i9xx_update_primary_plane;
12283 /* Returns the core display clock speed */
12284 if (IS_VALLEYVIEW(dev))
12285 dev_priv->display.get_display_clock_speed =
12286 valleyview_get_display_clock_speed;
12287 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12288 dev_priv->display.get_display_clock_speed =
12289 i945_get_display_clock_speed;
12290 else if (IS_I915G(dev))
12291 dev_priv->display.get_display_clock_speed =
12292 i915_get_display_clock_speed;
12293 else if (IS_I945GM(dev) || IS_845G(dev))
12294 dev_priv->display.get_display_clock_speed =
12295 i9xx_misc_get_display_clock_speed;
12296 else if (IS_PINEVIEW(dev))
12297 dev_priv->display.get_display_clock_speed =
12298 pnv_get_display_clock_speed;
12299 else if (IS_I915GM(dev))
12300 dev_priv->display.get_display_clock_speed =
12301 i915gm_get_display_clock_speed;
12302 else if (IS_I865G(dev))
12303 dev_priv->display.get_display_clock_speed =
12304 i865_get_display_clock_speed;
12305 else if (IS_I85X(dev))
12306 dev_priv->display.get_display_clock_speed =
12307 i855_get_display_clock_speed;
12308 else /* 852, 830 */
12309 dev_priv->display.get_display_clock_speed =
12310 i830_get_display_clock_speed;
12312 if (HAS_PCH_SPLIT(dev)) {
12313 if (IS_GEN5(dev)) {
12314 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12315 dev_priv->display.write_eld = ironlake_write_eld;
12316 } else if (IS_GEN6(dev)) {
12317 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12318 dev_priv->display.write_eld = ironlake_write_eld;
12319 dev_priv->display.modeset_global_resources =
12320 snb_modeset_global_resources;
12321 } else if (IS_IVYBRIDGE(dev)) {
12322 /* FIXME: detect B0+ stepping and use auto training */
12323 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12324 dev_priv->display.write_eld = ironlake_write_eld;
12325 dev_priv->display.modeset_global_resources =
12326 ivb_modeset_global_resources;
12327 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12328 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12329 dev_priv->display.write_eld = haswell_write_eld;
12330 dev_priv->display.modeset_global_resources =
12331 haswell_modeset_global_resources;
12333 } else if (IS_G4X(dev)) {
12334 dev_priv->display.write_eld = g4x_write_eld;
12335 } else if (IS_VALLEYVIEW(dev)) {
12336 dev_priv->display.modeset_global_resources =
12337 valleyview_modeset_global_resources;
12338 dev_priv->display.write_eld = ironlake_write_eld;
12341 /* Default just returns -ENODEV to indicate unsupported */
12342 dev_priv->display.queue_flip = intel_default_queue_flip;
12344 switch (INTEL_INFO(dev)->gen) {
12346 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12350 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12355 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12359 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12362 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12363 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12367 intel_panel_init_backlight_funcs(dev);
12371 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12372 * resume, or other times. This quirk makes sure that's the case for
12373 * affected systems.
12375 static void quirk_pipea_force(struct drm_device *dev)
12377 struct drm_i915_private *dev_priv = dev->dev_private;
12379 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12380 DRM_INFO("applying pipe a force quirk\n");
12384 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12386 static void quirk_ssc_force_disable(struct drm_device *dev)
12388 struct drm_i915_private *dev_priv = dev->dev_private;
12389 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12390 DRM_INFO("applying lvds SSC disable quirk\n");
12394 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12397 static void quirk_invert_brightness(struct drm_device *dev)
12399 struct drm_i915_private *dev_priv = dev->dev_private;
12400 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12401 DRM_INFO("applying inverted panel brightness quirk\n");
12404 /* Some VBT's incorrectly indicate no backlight is present */
12405 static void quirk_backlight_present(struct drm_device *dev)
12407 struct drm_i915_private *dev_priv = dev->dev_private;
12408 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12409 DRM_INFO("applying backlight present quirk\n");
12412 struct intel_quirk {
12414 int subsystem_vendor;
12415 int subsystem_device;
12416 void (*hook)(struct drm_device *dev);
12419 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12420 struct intel_dmi_quirk {
12421 void (*hook)(struct drm_device *dev);
12422 const struct dmi_system_id (*dmi_id_list)[];
12425 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12427 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12431 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12433 .dmi_id_list = &(const struct dmi_system_id[]) {
12435 .callback = intel_dmi_reverse_brightness,
12436 .ident = "NCR Corporation",
12437 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12438 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12441 { } /* terminating entry */
12443 .hook = quirk_invert_brightness,
12447 static struct intel_quirk intel_quirks[] = {
12448 /* HP Mini needs pipe A force quirk (LP: #322104) */
12449 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12451 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12452 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12454 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12455 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12457 /* Lenovo U160 cannot use SSC on LVDS */
12458 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12460 /* Sony Vaio Y cannot use SSC on LVDS */
12461 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12463 /* Acer Aspire 5734Z must invert backlight brightness */
12464 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12466 /* Acer/eMachines G725 */
12467 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12469 /* Acer/eMachines e725 */
12470 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12472 /* Acer/Packard Bell NCL20 */
12473 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12475 /* Acer Aspire 4736Z */
12476 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12478 /* Acer Aspire 5336 */
12479 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12481 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12482 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12484 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12485 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12487 /* HP Chromebook 14 (Celeron 2955U) */
12488 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12491 static void intel_init_quirks(struct drm_device *dev)
12493 struct pci_dev *d = dev->pdev;
12496 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12497 struct intel_quirk *q = &intel_quirks[i];
12499 if (d->device == q->device &&
12500 (d->subsystem_vendor == q->subsystem_vendor ||
12501 q->subsystem_vendor == PCI_ANY_ID) &&
12502 (d->subsystem_device == q->subsystem_device ||
12503 q->subsystem_device == PCI_ANY_ID))
12506 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12507 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12508 intel_dmi_quirks[i].hook(dev);
12512 /* Disable the VGA plane that we never use */
12513 static void i915_disable_vga(struct drm_device *dev)
12515 struct drm_i915_private *dev_priv = dev->dev_private;
12517 u32 vga_reg = i915_vgacntrl_reg(dev);
12519 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12520 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12521 outb(SR01, VGA_SR_INDEX);
12522 sr1 = inb(VGA_SR_DATA);
12523 outb(sr1 | 1<<5, VGA_SR_DATA);
12524 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12527 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12528 POSTING_READ(vga_reg);
12531 void intel_modeset_init_hw(struct drm_device *dev)
12533 intel_prepare_ddi(dev);
12535 if (IS_VALLEYVIEW(dev))
12536 vlv_update_cdclk(dev);
12538 intel_init_clock_gating(dev);
12540 intel_reset_dpio(dev);
12542 intel_enable_gt_powersave(dev);
12545 void intel_modeset_suspend_hw(struct drm_device *dev)
12547 intel_suspend_hw(dev);
12550 void intel_modeset_init(struct drm_device *dev)
12552 struct drm_i915_private *dev_priv = dev->dev_private;
12555 struct intel_crtc *crtc;
12557 drm_mode_config_init(dev);
12559 dev->mode_config.min_width = 0;
12560 dev->mode_config.min_height = 0;
12562 dev->mode_config.preferred_depth = 24;
12563 dev->mode_config.prefer_shadow = 1;
12565 dev->mode_config.funcs = &intel_mode_funcs;
12567 intel_init_quirks(dev);
12569 intel_init_pm(dev);
12571 if (INTEL_INFO(dev)->num_pipes == 0)
12574 intel_init_display(dev);
12576 if (IS_GEN2(dev)) {
12577 dev->mode_config.max_width = 2048;
12578 dev->mode_config.max_height = 2048;
12579 } else if (IS_GEN3(dev)) {
12580 dev->mode_config.max_width = 4096;
12581 dev->mode_config.max_height = 4096;
12583 dev->mode_config.max_width = 8192;
12584 dev->mode_config.max_height = 8192;
12587 if (IS_GEN2(dev)) {
12588 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12589 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12591 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12592 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12595 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12597 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12598 INTEL_INFO(dev)->num_pipes,
12599 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12601 for_each_pipe(pipe) {
12602 intel_crtc_init(dev, pipe);
12603 for_each_sprite(pipe, sprite) {
12604 ret = intel_plane_init(dev, pipe, sprite);
12606 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12607 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12611 intel_init_dpio(dev);
12612 intel_reset_dpio(dev);
12614 intel_shared_dpll_init(dev);
12616 /* Just disable it once at startup */
12617 i915_disable_vga(dev);
12618 intel_setup_outputs(dev);
12620 /* Just in case the BIOS is doing something questionable. */
12621 intel_disable_fbc(dev);
12623 drm_modeset_lock_all(dev);
12624 intel_modeset_setup_hw_state(dev, false);
12625 drm_modeset_unlock_all(dev);
12627 for_each_intel_crtc(dev, crtc) {
12632 * Note that reserving the BIOS fb up front prevents us
12633 * from stuffing other stolen allocations like the ring
12634 * on top. This prevents some ugliness at boot time, and
12635 * can even allow for smooth boot transitions if the BIOS
12636 * fb is large enough for the active pipe configuration.
12638 if (dev_priv->display.get_plane_config) {
12639 dev_priv->display.get_plane_config(crtc,
12640 &crtc->plane_config);
12642 * If the fb is shared between multiple heads, we'll
12643 * just get the first one.
12645 intel_find_plane_obj(crtc, &crtc->plane_config);
12650 static void intel_enable_pipe_a(struct drm_device *dev)
12652 struct intel_connector *connector;
12653 struct drm_connector *crt = NULL;
12654 struct intel_load_detect_pipe load_detect_temp;
12655 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12657 /* We can't just switch on the pipe A, we need to set things up with a
12658 * proper mode and output configuration. As a gross hack, enable pipe A
12659 * by enabling the load detect pipe once. */
12660 list_for_each_entry(connector,
12661 &dev->mode_config.connector_list,
12663 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12664 crt = &connector->base;
12672 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12673 intel_release_load_detect_pipe(crt, &load_detect_temp);
12677 intel_check_plane_mapping(struct intel_crtc *crtc)
12679 struct drm_device *dev = crtc->base.dev;
12680 struct drm_i915_private *dev_priv = dev->dev_private;
12683 if (INTEL_INFO(dev)->num_pipes == 1)
12686 reg = DSPCNTR(!crtc->plane);
12687 val = I915_READ(reg);
12689 if ((val & DISPLAY_PLANE_ENABLE) &&
12690 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12696 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12698 struct drm_device *dev = crtc->base.dev;
12699 struct drm_i915_private *dev_priv = dev->dev_private;
12702 /* Clear any frame start delays used for debugging left by the BIOS */
12703 reg = PIPECONF(crtc->config.cpu_transcoder);
12704 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12706 /* restore vblank interrupts to correct state */
12708 drm_vblank_on(dev, crtc->pipe);
12710 drm_vblank_off(dev, crtc->pipe);
12712 /* We need to sanitize the plane -> pipe mapping first because this will
12713 * disable the crtc (and hence change the state) if it is wrong. Note
12714 * that gen4+ has a fixed plane -> pipe mapping. */
12715 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12716 struct intel_connector *connector;
12719 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12720 crtc->base.base.id);
12722 /* Pipe has the wrong plane attached and the plane is active.
12723 * Temporarily change the plane mapping and disable everything
12725 plane = crtc->plane;
12726 crtc->plane = !plane;
12727 crtc->primary_enabled = true;
12728 dev_priv->display.crtc_disable(&crtc->base);
12729 crtc->plane = plane;
12731 /* ... and break all links. */
12732 list_for_each_entry(connector, &dev->mode_config.connector_list,
12734 if (connector->encoder->base.crtc != &crtc->base)
12737 connector->base.dpms = DRM_MODE_DPMS_OFF;
12738 connector->base.encoder = NULL;
12740 /* multiple connectors may have the same encoder:
12741 * handle them and break crtc link separately */
12742 list_for_each_entry(connector, &dev->mode_config.connector_list,
12744 if (connector->encoder->base.crtc == &crtc->base) {
12745 connector->encoder->base.crtc = NULL;
12746 connector->encoder->connectors_active = false;
12749 WARN_ON(crtc->active);
12750 crtc->base.enabled = false;
12753 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12754 crtc->pipe == PIPE_A && !crtc->active) {
12755 /* BIOS forgot to enable pipe A, this mostly happens after
12756 * resume. Force-enable the pipe to fix this, the update_dpms
12757 * call below we restore the pipe to the right state, but leave
12758 * the required bits on. */
12759 intel_enable_pipe_a(dev);
12762 /* Adjust the state of the output pipe according to whether we
12763 * have active connectors/encoders. */
12764 intel_crtc_update_dpms(&crtc->base);
12766 if (crtc->active != crtc->base.enabled) {
12767 struct intel_encoder *encoder;
12769 /* This can happen either due to bugs in the get_hw_state
12770 * functions or because the pipe is force-enabled due to the
12772 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12773 crtc->base.base.id,
12774 crtc->base.enabled ? "enabled" : "disabled",
12775 crtc->active ? "enabled" : "disabled");
12777 crtc->base.enabled = crtc->active;
12779 /* Because we only establish the connector -> encoder ->
12780 * crtc links if something is active, this means the
12781 * crtc is now deactivated. Break the links. connector
12782 * -> encoder links are only establish when things are
12783 * actually up, hence no need to break them. */
12784 WARN_ON(crtc->active);
12786 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12787 WARN_ON(encoder->connectors_active);
12788 encoder->base.crtc = NULL;
12792 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12794 * We start out with underrun reporting disabled to avoid races.
12795 * For correct bookkeeping mark this on active crtcs.
12797 * Also on gmch platforms we dont have any hardware bits to
12798 * disable the underrun reporting. Which means we need to start
12799 * out with underrun reporting disabled also on inactive pipes,
12800 * since otherwise we'll complain about the garbage we read when
12801 * e.g. coming up after runtime pm.
12803 * No protection against concurrent access is required - at
12804 * worst a fifo underrun happens which also sets this to false.
12806 crtc->cpu_fifo_underrun_disabled = true;
12807 crtc->pch_fifo_underrun_disabled = true;
12809 update_scanline_offset(crtc);
12813 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12815 struct intel_connector *connector;
12816 struct drm_device *dev = encoder->base.dev;
12818 /* We need to check both for a crtc link (meaning that the
12819 * encoder is active and trying to read from a pipe) and the
12820 * pipe itself being active. */
12821 bool has_active_crtc = encoder->base.crtc &&
12822 to_intel_crtc(encoder->base.crtc)->active;
12824 if (encoder->connectors_active && !has_active_crtc) {
12825 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12826 encoder->base.base.id,
12827 encoder->base.name);
12829 /* Connector is active, but has no active pipe. This is
12830 * fallout from our resume register restoring. Disable
12831 * the encoder manually again. */
12832 if (encoder->base.crtc) {
12833 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12834 encoder->base.base.id,
12835 encoder->base.name);
12836 encoder->disable(encoder);
12837 if (encoder->post_disable)
12838 encoder->post_disable(encoder);
12840 encoder->base.crtc = NULL;
12841 encoder->connectors_active = false;
12843 /* Inconsistent output/port/pipe state happens presumably due to
12844 * a bug in one of the get_hw_state functions. Or someplace else
12845 * in our code, like the register restore mess on resume. Clamp
12846 * things to off as a safer default. */
12847 list_for_each_entry(connector,
12848 &dev->mode_config.connector_list,
12850 if (connector->encoder != encoder)
12852 connector->base.dpms = DRM_MODE_DPMS_OFF;
12853 connector->base.encoder = NULL;
12856 /* Enabled encoders without active connectors will be fixed in
12857 * the crtc fixup. */
12860 void i915_redisable_vga_power_on(struct drm_device *dev)
12862 struct drm_i915_private *dev_priv = dev->dev_private;
12863 u32 vga_reg = i915_vgacntrl_reg(dev);
12865 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12866 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12867 i915_disable_vga(dev);
12871 void i915_redisable_vga(struct drm_device *dev)
12873 struct drm_i915_private *dev_priv = dev->dev_private;
12875 /* This function can be called both from intel_modeset_setup_hw_state or
12876 * at a very early point in our resume sequence, where the power well
12877 * structures are not yet restored. Since this function is at a very
12878 * paranoid "someone might have enabled VGA while we were not looking"
12879 * level, just check if the power well is enabled instead of trying to
12880 * follow the "don't touch the power well if we don't need it" policy
12881 * the rest of the driver uses. */
12882 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12885 i915_redisable_vga_power_on(dev);
12888 static bool primary_get_hw_state(struct intel_crtc *crtc)
12890 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12895 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12898 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12900 struct drm_i915_private *dev_priv = dev->dev_private;
12902 struct intel_crtc *crtc;
12903 struct intel_encoder *encoder;
12904 struct intel_connector *connector;
12907 for_each_intel_crtc(dev, crtc) {
12908 memset(&crtc->config, 0, sizeof(crtc->config));
12910 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12912 crtc->active = dev_priv->display.get_pipe_config(crtc,
12915 crtc->base.enabled = crtc->active;
12916 crtc->primary_enabled = primary_get_hw_state(crtc);
12918 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12919 crtc->base.base.id,
12920 crtc->active ? "enabled" : "disabled");
12923 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12924 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12926 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12928 for_each_intel_crtc(dev, crtc) {
12929 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12932 pll->refcount = pll->active;
12934 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12935 pll->name, pll->refcount, pll->on);
12938 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
12941 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12945 if (encoder->get_hw_state(encoder, &pipe)) {
12946 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12947 encoder->base.crtc = &crtc->base;
12948 encoder->get_config(encoder, &crtc->config);
12950 encoder->base.crtc = NULL;
12953 encoder->connectors_active = false;
12954 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12955 encoder->base.base.id,
12956 encoder->base.name,
12957 encoder->base.crtc ? "enabled" : "disabled",
12961 list_for_each_entry(connector, &dev->mode_config.connector_list,
12963 if (connector->get_hw_state(connector)) {
12964 connector->base.dpms = DRM_MODE_DPMS_ON;
12965 connector->encoder->connectors_active = true;
12966 connector->base.encoder = &connector->encoder->base;
12968 connector->base.dpms = DRM_MODE_DPMS_OFF;
12969 connector->base.encoder = NULL;
12971 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12972 connector->base.base.id,
12973 connector->base.name,
12974 connector->base.encoder ? "enabled" : "disabled");
12978 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12979 * and i915 state tracking structures. */
12980 void intel_modeset_setup_hw_state(struct drm_device *dev,
12981 bool force_restore)
12983 struct drm_i915_private *dev_priv = dev->dev_private;
12985 struct intel_crtc *crtc;
12986 struct intel_encoder *encoder;
12989 intel_modeset_readout_hw_state(dev);
12992 * Now that we have the config, copy it to each CRTC struct
12993 * Note that this could go away if we move to using crtc_config
12994 * checking everywhere.
12996 for_each_intel_crtc(dev, crtc) {
12997 if (crtc->active && i915.fastboot) {
12998 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12999 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13000 crtc->base.base.id);
13001 drm_mode_debug_printmodeline(&crtc->base.mode);
13005 /* HW state is read out, now we need to sanitize this mess. */
13006 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
13008 intel_sanitize_encoder(encoder);
13011 for_each_pipe(pipe) {
13012 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13013 intel_sanitize_crtc(crtc);
13014 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13017 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13018 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13020 if (!pll->on || pll->active)
13023 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13025 pll->disable(dev_priv, pll);
13029 if (HAS_PCH_SPLIT(dev))
13030 ilk_wm_get_hw_state(dev);
13032 if (force_restore) {
13033 i915_redisable_vga(dev);
13036 * We need to use raw interfaces for restoring state to avoid
13037 * checking (bogus) intermediate states.
13039 for_each_pipe(pipe) {
13040 struct drm_crtc *crtc =
13041 dev_priv->pipe_to_crtc_mapping[pipe];
13043 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13044 crtc->primary->fb);
13047 intel_modeset_update_staged_output_state(dev);
13050 intel_modeset_check_state(dev);
13053 void intel_modeset_gem_init(struct drm_device *dev)
13055 struct drm_crtc *c;
13056 struct drm_i915_gem_object *obj;
13058 mutex_lock(&dev->struct_mutex);
13059 intel_init_gt_powersave(dev);
13060 mutex_unlock(&dev->struct_mutex);
13062 intel_modeset_init_hw(dev);
13064 intel_setup_overlay(dev);
13067 * Make sure any fbs we allocated at startup are properly
13068 * pinned & fenced. When we do the allocation it's too early
13071 mutex_lock(&dev->struct_mutex);
13072 for_each_crtc(dev, c) {
13073 obj = intel_fb_obj(c->primary->fb);
13077 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13078 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13079 to_intel_crtc(c)->pipe);
13080 drm_framebuffer_unreference(c->primary->fb);
13081 c->primary->fb = NULL;
13084 mutex_unlock(&dev->struct_mutex);
13087 void intel_connector_unregister(struct intel_connector *intel_connector)
13089 struct drm_connector *connector = &intel_connector->base;
13091 intel_panel_destroy_backlight(connector);
13092 drm_connector_unregister(connector);
13095 void intel_modeset_cleanup(struct drm_device *dev)
13097 struct drm_i915_private *dev_priv = dev->dev_private;
13098 struct drm_connector *connector;
13101 * Interrupts and polling as the first thing to avoid creating havoc.
13102 * Too much stuff here (turning of rps, connectors, ...) would
13103 * experience fancy races otherwise.
13105 drm_irq_uninstall(dev);
13106 intel_hpd_cancel_work(dev_priv);
13107 dev_priv->pm._irqs_disabled = true;
13110 * Due to the hpd irq storm handling the hotplug work can re-arm the
13111 * poll handlers. Hence disable polling after hpd handling is shut down.
13113 drm_kms_helper_poll_fini(dev);
13115 mutex_lock(&dev->struct_mutex);
13117 intel_unregister_dsm_handler();
13119 intel_disable_fbc(dev);
13121 intel_disable_gt_powersave(dev);
13123 ironlake_teardown_rc6(dev);
13125 mutex_unlock(&dev->struct_mutex);
13127 /* flush any delayed tasks or pending work */
13128 flush_scheduled_work();
13130 /* destroy the backlight and sysfs files before encoders/connectors */
13131 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13132 struct intel_connector *intel_connector;
13134 intel_connector = to_intel_connector(connector);
13135 intel_connector->unregister(intel_connector);
13138 drm_mode_config_cleanup(dev);
13140 intel_cleanup_overlay(dev);
13142 mutex_lock(&dev->struct_mutex);
13143 intel_cleanup_gt_powersave(dev);
13144 mutex_unlock(&dev->struct_mutex);
13148 * Return which encoder is currently attached for connector.
13150 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13152 return &intel_attached_encoder(connector)->base;
13155 void intel_connector_attach_encoder(struct intel_connector *connector,
13156 struct intel_encoder *encoder)
13158 connector->encoder = encoder;
13159 drm_mode_connector_attach_encoder(&connector->base,
13164 * set vga decode state - true == enable VGA decode
13166 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13168 struct drm_i915_private *dev_priv = dev->dev_private;
13169 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13172 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13173 DRM_ERROR("failed to read control word\n");
13177 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13181 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13183 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13185 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13186 DRM_ERROR("failed to write control word\n");
13193 struct intel_display_error_state {
13195 u32 power_well_driver;
13197 int num_transcoders;
13199 struct intel_cursor_error_state {
13204 } cursor[I915_MAX_PIPES];
13206 struct intel_pipe_error_state {
13207 bool power_domain_on;
13210 } pipe[I915_MAX_PIPES];
13212 struct intel_plane_error_state {
13220 } plane[I915_MAX_PIPES];
13222 struct intel_transcoder_error_state {
13223 bool power_domain_on;
13224 enum transcoder cpu_transcoder;
13237 struct intel_display_error_state *
13238 intel_display_capture_error_state(struct drm_device *dev)
13240 struct drm_i915_private *dev_priv = dev->dev_private;
13241 struct intel_display_error_state *error;
13242 int transcoders[] = {
13250 if (INTEL_INFO(dev)->num_pipes == 0)
13253 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13257 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13258 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13261 error->pipe[i].power_domain_on =
13262 intel_display_power_enabled_unlocked(dev_priv,
13263 POWER_DOMAIN_PIPE(i));
13264 if (!error->pipe[i].power_domain_on)
13267 error->cursor[i].control = I915_READ(CURCNTR(i));
13268 error->cursor[i].position = I915_READ(CURPOS(i));
13269 error->cursor[i].base = I915_READ(CURBASE(i));
13271 error->plane[i].control = I915_READ(DSPCNTR(i));
13272 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13273 if (INTEL_INFO(dev)->gen <= 3) {
13274 error->plane[i].size = I915_READ(DSPSIZE(i));
13275 error->plane[i].pos = I915_READ(DSPPOS(i));
13277 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13278 error->plane[i].addr = I915_READ(DSPADDR(i));
13279 if (INTEL_INFO(dev)->gen >= 4) {
13280 error->plane[i].surface = I915_READ(DSPSURF(i));
13281 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13284 error->pipe[i].source = I915_READ(PIPESRC(i));
13286 if (HAS_GMCH_DISPLAY(dev))
13287 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13290 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13291 if (HAS_DDI(dev_priv->dev))
13292 error->num_transcoders++; /* Account for eDP. */
13294 for (i = 0; i < error->num_transcoders; i++) {
13295 enum transcoder cpu_transcoder = transcoders[i];
13297 error->transcoder[i].power_domain_on =
13298 intel_display_power_enabled_unlocked(dev_priv,
13299 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13300 if (!error->transcoder[i].power_domain_on)
13303 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13305 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13306 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13307 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13308 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13309 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13310 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13311 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13317 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13320 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13321 struct drm_device *dev,
13322 struct intel_display_error_state *error)
13329 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13330 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13331 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13332 error->power_well_driver);
13334 err_printf(m, "Pipe [%d]:\n", i);
13335 err_printf(m, " Power: %s\n",
13336 error->pipe[i].power_domain_on ? "on" : "off");
13337 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13338 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13340 err_printf(m, "Plane [%d]:\n", i);
13341 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13342 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13343 if (INTEL_INFO(dev)->gen <= 3) {
13344 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13345 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13347 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13348 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13349 if (INTEL_INFO(dev)->gen >= 4) {
13350 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13351 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13354 err_printf(m, "Cursor [%d]:\n", i);
13355 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13356 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13357 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13360 for (i = 0; i < error->num_transcoders; i++) {
13361 err_printf(m, "CPU transcoder: %c\n",
13362 transcoder_name(error->transcoder[i].cpu_transcoder));
13363 err_printf(m, " Power: %s\n",
13364 error->transcoder[i].power_domain_on ? "on" : "off");
13365 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13366 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13367 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13368 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13369 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13370 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13371 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);