drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc);
  98 static void chv_prepare_pll(struct intel_crtc *crtc);
  99
 100 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 101 {
 102         if (!connector->mst_port)
 103                 return connector->encoder;
 104         else
 105                 return &connector->mst_port->mst_encoders[pipe]->base;
 106 }
 107
 108 typedef struct {
 109         int     min, max;
 110 } intel_range_t;
 111
 112 typedef struct {
 113         int     dot_limit;
 114         int     p2_slow, p2_fast;
 115 } intel_p2_t;
 116
 117 typedef struct intel_limit intel_limit_t;
 118 struct intel_limit {
 119         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 120         intel_p2_t          p2;
 121 };
 122
 123 int
 124 intel_pch_rawclk(struct drm_device *dev)
 125 {
 126         struct drm_i915_private *dev_priv = dev->dev_private;
 127
 128         WARN_ON(!HAS_PCH_SPLIT(dev));
 129
 130         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 131 }
 132
 133 static inline u32 /* units of 100MHz */
 134 intel_fdi_link_freq(struct drm_device *dev)
 135 {
 136         if (IS_GEN5(dev)) {
 137                 struct drm_i915_private *dev_priv = dev->dev_private;
 138                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 139         } else
 140                 return 27;
 141 }
 142
 143 static const intel_limit_t intel_limits_i8xx_dac = {
 144         .dot = { .min = 25000, .max = 350000 },
 145         .vco = { .min = 908000, .max = 1512000 },
 146         .n = { .min = 2, .max = 16 },
 147         .m = { .min = 96, .max = 140 },
 148         .m1 = { .min = 18, .max = 26 },
 149         .m2 = { .min = 6, .max = 16 },
 150         .p = { .min = 4, .max = 128 },
 151         .p1 = { .min = 2, .max = 33 },
 152         .p2 = { .dot_limit = 165000,
 153                 .p2_slow = 4, .p2_fast = 2 },
 154 };
 155
 156 static const intel_limit_t intel_limits_i8xx_dvo = {
 157         .dot = { .min = 25000, .max = 350000 },
 158         .vco = { .min = 908000, .max = 1512000 },
 159         .n = { .min = 2, .max = 16 },
 160         .m = { .min = 96, .max = 140 },
 161         .m1 = { .min = 18, .max = 26 },
 162         .m2 = { .min = 6, .max = 16 },
 163         .p = { .min = 4, .max = 128 },
 164         .p1 = { .min = 2, .max = 33 },
 165         .p2 = { .dot_limit = 165000,
 166                 .p2_slow = 4, .p2_fast = 4 },
 167 };
 168
 169 static const intel_limit_t intel_limits_i8xx_lvds = {
 170         .dot = { .min = 25000, .max = 350000 },
 171         .vco = { .min = 908000, .max = 1512000 },
 172         .n = { .min = 2, .max = 16 },
 173         .m = { .min = 96, .max = 140 },
 174         .m1 = { .min = 18, .max = 26 },
 175         .m2 = { .min = 6, .max = 16 },
 176         .p = { .min = 4, .max = 128 },
 177         .p1 = { .min = 1, .max = 6 },
 178         .p2 = { .dot_limit = 165000,
 179                 .p2_slow = 14, .p2_fast = 7 },
 180 };
 181
 182 static const intel_limit_t intel_limits_i9xx_sdvo = {
 183         .dot = { .min = 20000, .max = 400000 },
 184         .vco = { .min = 1400000, .max = 2800000 },
 185         .n = { .min = 1, .max = 6 },
 186         .m = { .min = 70, .max = 120 },
 187         .m1 = { .min = 8, .max = 18 },
 188         .m2 = { .min = 3, .max = 7 },
 189         .p = { .min = 5, .max = 80 },
 190         .p1 = { .min = 1, .max = 8 },
 191         .p2 = { .dot_limit = 200000,
 192                 .p2_slow = 10, .p2_fast = 5 },
 193 };
 194
 195 static const intel_limit_t intel_limits_i9xx_lvds = {
 196         .dot = { .min = 20000, .max = 400000 },
 197         .vco = { .min = 1400000, .max = 2800000 },
 198         .n = { .min = 1, .max = 6 },
 199         .m = { .min = 70, .max = 120 },
 200         .m1 = { .min = 8, .max = 18 },
 201         .m2 = { .min = 3, .max = 7 },
 202         .p = { .min = 7, .max = 98 },
 203         .p1 = { .min = 1, .max = 8 },
 204         .p2 = { .dot_limit = 112000,
 205                 .p2_slow = 14, .p2_fast = 7 },
 206 };
 207
 208
 209 static const intel_limit_t intel_limits_g4x_sdvo = {
 210         .dot = { .min = 25000, .max = 270000 },
 211         .vco = { .min = 1750000, .max = 3500000},
 212         .n = { .min = 1, .max = 4 },
 213         .m = { .min = 104, .max = 138 },
 214         .m1 = { .min = 17, .max = 23 },
 215         .m2 = { .min = 5, .max = 11 },
 216         .p = { .min = 10, .max = 30 },
 217         .p1 = { .min = 1, .max = 3},
 218         .p2 = { .dot_limit = 270000,
 219                 .p2_slow = 10,
 220                 .p2_fast = 10
 221         },
 222 };
 223
 224 static const intel_limit_t intel_limits_g4x_hdmi = {
 225         .dot = { .min = 22000, .max = 400000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 4 },
 228         .m = { .min = 104, .max = 138 },
 229         .m1 = { .min = 16, .max = 23 },
 230         .m2 = { .min = 5, .max = 11 },
 231         .p = { .min = 5, .max = 80 },
 232         .p1 = { .min = 1, .max = 8},
 233         .p2 = { .dot_limit = 165000,
 234                 .p2_slow = 10, .p2_fast = 5 },
 235 };
 236
 237 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 238         .dot = { .min = 20000, .max = 115000 },
 239         .vco = { .min = 1750000, .max = 3500000 },
 240         .n = { .min = 1, .max = 3 },
 241         .m = { .min = 104, .max = 138 },
 242         .m1 = { .min = 17, .max = 23 },
 243         .m2 = { .min = 5, .max = 11 },
 244         .p = { .min = 28, .max = 112 },
 245         .p1 = { .min = 2, .max = 8 },
 246         .p2 = { .dot_limit = 0,
 247                 .p2_slow = 14, .p2_fast = 14
 248         },
 249 };
 250
 251 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 252         .dot = { .min = 80000, .max = 224000 },
 253         .vco = { .min = 1750000, .max = 3500000 },
 254         .n = { .min = 1, .max = 3 },
 255         .m = { .min = 104, .max = 138 },
 256         .m1 = { .min = 17, .max = 23 },
 257         .m2 = { .min = 5, .max = 11 },
 258         .p = { .min = 14, .max = 42 },
 259         .p1 = { .min = 2, .max = 6 },
 260         .p2 = { .dot_limit = 0,
 261                 .p2_slow = 7, .p2_fast = 7
 262         },
 263 };
 264
 265 static const intel_limit_t intel_limits_pineview_sdvo = {
 266         .dot = { .min = 20000, .max = 400000},
 267         .vco = { .min = 1700000, .max = 3500000 },
 268         /* Pineview's Ncounter is a ring counter */
 269         .n = { .min = 3, .max = 6 },
 270         .m = { .min = 2, .max = 256 },
 271         /* Pineview only has one combined m divider, which we treat as m2. */
 272         .m1 = { .min = 0, .max = 0 },
 273         .m2 = { .min = 0, .max = 254 },
 274         .p = { .min = 5, .max = 80 },
 275         .p1 = { .min = 1, .max = 8 },
 276         .p2 = { .dot_limit = 200000,
 277                 .p2_slow = 10, .p2_fast = 5 },
 278 };
 279
 280 static const intel_limit_t intel_limits_pineview_lvds = {
 281         .dot = { .min = 20000, .max = 400000 },
 282         .vco = { .min = 1700000, .max = 3500000 },
 283         .n = { .min = 3, .max = 6 },
 284         .m = { .min = 2, .max = 256 },
 285         .m1 = { .min = 0, .max = 0 },
 286         .m2 = { .min = 0, .max = 254 },
 287         .p = { .min = 7, .max = 112 },
 288         .p1 = { .min = 1, .max = 8 },
 289         .p2 = { .dot_limit = 112000,
 290                 .p2_slow = 14, .p2_fast = 14 },
 291 };
 292
 293 /* Ironlake / Sandybridge
 294  *
 295  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 296  * the range value for them is (actual_value - 2).
 297  */
 298 static const intel_limit_t intel_limits_ironlake_dac = {
 299         .dot = { .min = 25000, .max = 350000 },
 300         .vco = { .min = 1760000, .max = 3510000 },
 301         .n = { .min = 1, .max = 5 },
 302         .m = { .min = 79, .max = 127 },
 303         .m1 = { .min = 12, .max = 22 },
 304         .m2 = { .min = 5, .max = 9 },
 305         .p = { .min = 5, .max = 80 },
 306         .p1 = { .min = 1, .max = 8 },
 307         .p2 = { .dot_limit = 225000,
 308                 .p2_slow = 10, .p2_fast = 5 },
 309 };
 310
 311 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 312         .dot = { .min = 25000, .max = 350000 },
 313         .vco = { .min = 1760000, .max = 3510000 },
 314         .n = { .min = 1, .max = 3 },
 315         .m = { .min = 79, .max = 118 },
 316         .m1 = { .min = 12, .max = 22 },
 317         .m2 = { .min = 5, .max = 9 },
 318         .p = { .min = 28, .max = 112 },
 319         .p1 = { .min = 2, .max = 8 },
 320         .p2 = { .dot_limit = 225000,
 321                 .p2_slow = 14, .p2_fast = 14 },
 322 };
 323
 324 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 325         .dot = { .min = 25000, .max = 350000 },
 326         .vco = { .min = 1760000, .max = 3510000 },
 327         .n = { .min = 1, .max = 3 },
 328         .m = { .min = 79, .max = 127 },
 329         .m1 = { .min = 12, .max = 22 },
 330         .m2 = { .min = 5, .max = 9 },
 331         .p = { .min = 14, .max = 56 },
 332         .p1 = { .min = 2, .max = 8 },
 333         .p2 = { .dot_limit = 225000,
 334                 .p2_slow = 7, .p2_fast = 7 },
 335 };
 336
 337 /* LVDS 100mhz refclk limits. */
 338 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 339         .dot = { .min = 25000, .max = 350000 },
 340         .vco = { .min = 1760000, .max = 3510000 },
 341         .n = { .min = 1, .max = 2 },
 342         .m = { .min = 79, .max = 126 },
 343         .m1 = { .min = 12, .max = 22 },
 344         .m2 = { .min = 5, .max = 9 },
 345         .p = { .min = 28, .max = 112 },
 346         .p1 = { .min = 2, .max = 8 },
 347         .p2 = { .dot_limit = 225000,
 348                 .p2_slow = 14, .p2_fast = 14 },
 349 };
 350
 351 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 352         .dot = { .min = 25000, .max = 350000 },
 353         .vco = { .min = 1760000, .max = 3510000 },
 354         .n = { .min = 1, .max = 3 },
 355         .m = { .min = 79, .max = 126 },
 356         .m1 = { .min = 12, .max = 22 },
 357         .m2 = { .min = 5, .max = 9 },
 358         .p = { .min = 14, .max = 42 },
 359         .p1 = { .min = 2, .max = 6 },
 360         .p2 = { .dot_limit = 225000,
 361                 .p2_slow = 7, .p2_fast = 7 },
 362 };
 363
 364 static const intel_limit_t intel_limits_vlv = {
 365          /*
 366           * These are the data rate limits (measured in fast clocks)
 367           * since those are the strictest limits we have. The fast
 368           * clock and actual rate limits are more relaxed, so checking
 369           * them would make no difference.
 370           */
 371         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 372         .vco = { .min = 4000000, .max = 6000000 },
 373         .n = { .min = 1, .max = 7 },
 374         .m1 = { .min = 2, .max = 3 },
 375         .m2 = { .min = 11, .max = 156 },
 376         .p1 = { .min = 2, .max = 3 },
 377         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 378 };
 379
 380 static const intel_limit_t intel_limits_chv = {
 381         /*
 382          * These are the data rate limits (measured in fast clocks)
 383          * since those are the strictest limits we have.  The fast
 384          * clock and actual rate limits are more relaxed, so checking
 385          * them would make no difference.
 386          */
 387         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 388         .vco = { .min = 4860000, .max = 6700000 },
 389         .n = { .min = 1, .max = 1 },
 390         .m1 = { .min = 2, .max = 2 },
 391         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 392         .p1 = { .min = 2, .max = 4 },
 393         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 394 };
 395
 396 static void vlv_clock(int refclk, intel_clock_t *clock)
 397 {
 398         clock->m = clock->m1 * clock->m2;
 399         clock->p = clock->p1 * clock->p2;
 400         if (WARN_ON(clock->n == 0 || clock->p == 0))
 401                 return;
 402         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 403         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 404 }
 405
 406 /**
 407  * Returns whether any output on the specified pipe is of the specified type
 408  */
 409 static bool intel_pipe_has_type(struct intel_crtc *crtc, int type)
 410 {
 411         struct drm_device *dev = crtc->base.dev;
 412         struct intel_encoder *encoder;
 413
 414         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 415                 if (encoder->type == type)
 416                         return true;
 417
 418         return false;
 419 }
 420
 421 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 422                                                 int refclk)
 423 {
 424         struct drm_device *dev = crtc->base.dev;
 425         const intel_limit_t *limit;
 426
 427         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 428                 if (intel_is_dual_link_lvds(dev)) {
 429                         if (refclk == 100000)
 430                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 431                         else
 432                                 limit = &intel_limits_ironlake_dual_lvds;
 433                 } else {
 434                         if (refclk == 100000)
 435                                 limit = &intel_limits_ironlake_single_lvds_100m;
 436                         else
 437                                 limit = &intel_limits_ironlake_single_lvds;
 438                 }
 439         } else
 440                 limit = &intel_limits_ironlake_dac;
 441
 442         return limit;
 443 }
 444
 445 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 446 {
 447         struct drm_device *dev = crtc->base.dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev))
 452                         limit = &intel_limits_g4x_dual_channel_lvds;
 453                 else
 454                         limit = &intel_limits_g4x_single_channel_lvds;
 455         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 456                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 457                 limit = &intel_limits_g4x_hdmi;
 458         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 459                 limit = &intel_limits_g4x_sdvo;
 460         } else /* The option is for other outputs */
 461                 limit = &intel_limits_i9xx_sdvo;
 462
 463         return limit;
 464 }
 465
 466 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 467 {
 468         struct drm_device *dev = crtc->base.dev;
 469         const intel_limit_t *limit;
 470
 471         if (HAS_PCH_SPLIT(dev))
 472                 limit = intel_ironlake_limit(crtc, refclk);
 473         else if (IS_G4X(dev)) {
 474                 limit = intel_g4x_limit(crtc);
 475         } else if (IS_PINEVIEW(dev)) {
 476                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 477                         limit = &intel_limits_pineview_lvds;
 478                 else
 479                         limit = &intel_limits_pineview_sdvo;
 480         } else if (IS_CHERRYVIEW(dev)) {
 481                 limit = &intel_limits_chv;
 482         } else if (IS_VALLEYVIEW(dev)) {
 483                 limit = &intel_limits_vlv;
 484         } else if (!IS_GEN2(dev)) {
 485                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 486                         limit = &intel_limits_i9xx_lvds;
 487                 else
 488                         limit = &intel_limits_i9xx_sdvo;
 489         } else {
 490                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 491                         limit = &intel_limits_i8xx_lvds;
 492                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 493                         limit = &intel_limits_i8xx_dvo;
 494                 else
 495                         limit = &intel_limits_i8xx_dac;
 496         }
 497         return limit;
 498 }
 499
 500 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 501 static void pineview_clock(int refclk, intel_clock_t *clock)
 502 {
 503         clock->m = clock->m2 + 2;
 504         clock->p = clock->p1 * clock->p2;
 505         if (WARN_ON(clock->n == 0 || clock->p == 0))
 506                 return;
 507         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 508         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 509 }
 510
 511 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 512 {
 513         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 514 }
 515
 516 static void i9xx_clock(int refclk, intel_clock_t *clock)
 517 {
 518         clock->m = i9xx_dpll_compute_m(clock);
 519         clock->p = clock->p1 * clock->p2;
 520         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 521                 return;
 522         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 523         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 524 }
 525
 526 static void chv_clock(int refclk, intel_clock_t *clock)
 527 {
 528         clock->m = clock->m1 * clock->m2;
 529         clock->p = clock->p1 * clock->p2;
 530         if (WARN_ON(clock->n == 0 || clock->p == 0))
 531                 return;
 532         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 533                         clock->n << 22);
 534         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 535 }
 536
 537 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 538 /**
 539  * Returns whether the given set of divisors are valid for a given refclk with
 540  * the given connectors.
 541  */
 542
 543 static bool intel_PLL_is_valid(struct drm_device *dev,
 544                                const intel_limit_t *limit,
 545                                const intel_clock_t *clock)
 546 {
 547         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 548                 INTELPllInvalid("n out of range\n");
 549         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 550                 INTELPllInvalid("p1 out of range\n");
 551         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 552                 INTELPllInvalid("m2 out of range\n");
 553         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 554                 INTELPllInvalid("m1 out of range\n");
 555
 556         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 557                 if (clock->m1 <= clock->m2)
 558                         INTELPllInvalid("m1 <= m2\n");
 559
 560         if (!IS_VALLEYVIEW(dev)) {
 561                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 562                         INTELPllInvalid("p out of range\n");
 563                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 564                         INTELPllInvalid("m out of range\n");
 565         }
 566
 567         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 568                 INTELPllInvalid("vco out of range\n");
 569         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 570          * connector, etc., rather than just a single range.
 571          */
 572         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 573                 INTELPllInvalid("dot out of range\n");
 574
 575         return true;
 576 }
 577
 578 static bool
 579 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 580                     int target, int refclk, intel_clock_t *match_clock,
 581                     intel_clock_t *best_clock)
 582 {
 583         struct drm_device *dev = crtc->base.dev;
 584         intel_clock_t clock;
 585         int err = target;
 586
 587         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         clock.p2 = limit->p2.p2_fast;
 595                 else
 596                         clock.p2 = limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         clock.p2 = limit->p2.p2_slow;
 600                 else
 601                         clock.p2 = limit->p2.p2_fast;
 602         }
 603
 604         memset(best_clock, 0, sizeof(*best_clock));
 605
 606         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 607              clock.m1++) {
 608                 for (clock.m2 = limit->m2.min;
 609                      clock.m2 <= limit->m2.max; clock.m2++) {
 610                         if (clock.m2 >= clock.m1)
 611                                 break;
 612                         for (clock.n = limit->n.min;
 613                              clock.n <= limit->n.max; clock.n++) {
 614                                 for (clock.p1 = limit->p1.min;
 615                                         clock.p1 <= limit->p1.max; clock.p1++) {
 616                                         int this_err;
 617
 618                                         i9xx_clock(refclk, &clock);
 619                                         if (!intel_PLL_is_valid(dev, limit,
 620                                                                 &clock))
 621                                                 continue;
 622                                         if (match_clock &&
 623                                             clock.p != match_clock->p)
 624                                                 continue;
 625
 626                                         this_err = abs(clock.dot - target);
 627                                         if (this_err < err) {
 628                                                 *best_clock = clock;
 629                                                 err = this_err;
 630                                         }
 631                                 }
 632                         }
 633                 }
 634         }
 635
 636         return (err != target);
 637 }
 638
 639 static bool
 640 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 641                    int target, int refclk, intel_clock_t *match_clock,
 642                    intel_clock_t *best_clock)
 643 {
 644         struct drm_device *dev = crtc->base.dev;
 645         intel_clock_t clock;
 646         int err = target;
 647
 648         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 649                 /*
 650                  * For LVDS just rely on its current settings for dual-channel.
 651                  * We haven't figured out how to reliably set up different
 652                  * single/dual channel state, if we even can.
 653                  */
 654                 if (intel_is_dual_link_lvds(dev))
 655                         clock.p2 = limit->p2.p2_fast;
 656                 else
 657                         clock.p2 = limit->p2.p2_slow;
 658         } else {
 659                 if (target < limit->p2.dot_limit)
 660                         clock.p2 = limit->p2.p2_slow;
 661                 else
 662                         clock.p2 = limit->p2.p2_fast;
 663         }
 664
 665         memset(best_clock, 0, sizeof(*best_clock));
 666
 667         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 668              clock.m1++) {
 669                 for (clock.m2 = limit->m2.min;
 670                      clock.m2 <= limit->m2.max; clock.m2++) {
 671                         for (clock.n = limit->n.min;
 672                              clock.n <= limit->n.max; clock.n++) {
 673                                 for (clock.p1 = limit->p1.min;
 674                                         clock.p1 <= limit->p1.max; clock.p1++) {
 675                                         int this_err;
 676
 677                                         pineview_clock(refclk, &clock);
 678                                         if (!intel_PLL_is_valid(dev, limit,
 679                                                                 &clock))
 680                                                 continue;
 681                                         if (match_clock &&
 682                                             clock.p != match_clock->p)
 683                                                 continue;
 684
 685                                         this_err = abs(clock.dot - target);
 686                                         if (this_err < err) {
 687                                                 *best_clock = clock;
 688                                                 err = this_err;
 689                                         }
 690                                 }
 691                         }
 692                 }
 693         }
 694
 695         return (err != target);
 696 }
 697
 698 static bool
 699 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 700                    int target, int refclk, intel_clock_t *match_clock,
 701                    intel_clock_t *best_clock)
 702 {
 703         struct drm_device *dev = crtc->base.dev;
 704         intel_clock_t clock;
 705         int max_n;
 706         bool found;
 707         /* approximately equals target * 0.00585 */
 708         int err_most = (target >> 8) + (target >> 9);
 709         found = false;
 710
 711         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 712                 if (intel_is_dual_link_lvds(dev))
 713                         clock.p2 = limit->p2.p2_fast;
 714                 else
 715                         clock.p2 = limit->p2.p2_slow;
 716         } else {
 717                 if (target < limit->p2.dot_limit)
 718                         clock.p2 = limit->p2.p2_slow;
 719                 else
 720                         clock.p2 = limit->p2.p2_fast;
 721         }
 722
 723         memset(best_clock, 0, sizeof(*best_clock));
 724         max_n = limit->n.max;
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 727                 /* based on hardware requirement, prefere larger m1,m2 */
 728                 for (clock.m1 = limit->m1.max;
 729                      clock.m1 >= limit->m1.min; clock.m1--) {
 730                         for (clock.m2 = limit->m2.max;
 731                              clock.m2 >= limit->m2.min; clock.m2--) {
 732                                 for (clock.p1 = limit->p1.max;
 733                                      clock.p1 >= limit->p1.min; clock.p1--) {
 734                                         int this_err;
 735
 736                                         i9xx_clock(refclk, &clock);
 737                                         if (!intel_PLL_is_valid(dev, limit,
 738                                                                 &clock))
 739                                                 continue;
 740
 741                                         this_err = abs(clock.dot - target);
 742                                         if (this_err < err_most) {
 743                                                 *best_clock = clock;
 744                                                 err_most = this_err;
 745                                                 max_n = clock.n;
 746                                                 found = true;
 747                                         }
 748                                 }
 749                         }
 750                 }
 751         }
 752         return found;
 753 }
 754
 755 static bool
 756 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 757                    int target, int refclk, intel_clock_t *match_clock,
 758                    intel_clock_t *best_clock)
 759 {
 760         struct drm_device *dev = crtc->base.dev;
 761         intel_clock_t clock;
 762         unsigned int bestppm = 1000000;
 763         /* min update 19.2 MHz */
 764         int max_n = min(limit->n.max, refclk / 19200);
 765         bool found = false;
 766
 767         target *= 5; /* fast clock */
 768
 769         memset(best_clock, 0, sizeof(*best_clock));
 770
 771         /* based on hardware requirement, prefer smaller n to precision */
 772         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 773                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 774                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 775                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 776                                 clock.p = clock.p1 * clock.p2;
 777                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 778                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 779                                         unsigned int ppm, diff;
 780
 781                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 782                                                                      refclk * clock.m1);
 783
 784                                         vlv_clock(refclk, &clock);
 785
 786                                         if (!intel_PLL_is_valid(dev, limit,
 787                                                                 &clock))
 788                                                 continue;
 789
 790                                         diff = abs(clock.dot - target);
 791                                         ppm = div_u64(1000000ULL * diff, target);
 792
 793                                         if (ppm < 100 && clock.p > best_clock->p) {
 794                                                 bestppm = 0;
 795                                                 *best_clock = clock;
 796                                                 found = true;
 797                                         }
 798
 799                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 800                                                 bestppm = ppm;
 801                                                 *best_clock = clock;
 802                                                 found = true;
 803                                         }
 804                                 }
 805                         }
 806                 }
 807         }
 808
 809         return found;
 810 }
 811
 812 static bool
 813 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc->base.dev;
 818         intel_clock_t clock;
 819         uint64_t m2;
 820         int found = false;
 821
 822         memset(best_clock, 0, sizeof(*best_clock));
 823
 824         /*
 825          * Based on hardware doc, the n always set to 1, and m1 always
 826          * set to 2.  If requires to support 200Mhz refclk, we need to
 827          * revisit this because n may not 1 anymore.
 828          */
 829         clock.n = 1, clock.m1 = 2;
 830         target *= 5;    /* fast clock */
 831
 832         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 833                 for (clock.p2 = limit->p2.p2_fast;
 834                                 clock.p2 >= limit->p2.p2_slow;
 835                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 836
 837                         clock.p = clock.p1 * clock.p2;
 838
 839                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 840                                         clock.n) << 22, refclk * clock.m1);
 841
 842                         if (m2 > INT_MAX/clock.m1)
 843                                 continue;
 844
 845                         clock.m2 = m2;
 846
 847                         chv_clock(refclk, &clock);
 848
 849                         if (!intel_PLL_is_valid(dev, limit, &clock))
 850                                 continue;
 851
 852                         /* based on hardware requirement, prefer bigger p
 853                          */
 854                         if (clock.p > best_clock->p) {
 855                                 *best_clock = clock;
 856                                 found = true;
 857                         }
 858                 }
 859         }
 860
 861         return found;
 862 }
 863
 864 bool intel_crtc_active(struct drm_crtc *crtc)
 865 {
 866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 867
 868         /* Be paranoid as we can arrive here with only partial
 869          * state retrieved from the hardware during setup.
 870          *
 871          * We can ditch the adjusted_mode.crtc_clock check as soon
 872          * as Haswell has gained clock readout/fastboot support.
 873          *
 874          * We can ditch the crtc->primary->fb check as soon as we can
 875          * properly reconstruct framebuffers.
 876          */
 877         return intel_crtc->active && crtc->primary->fb &&
 878                 intel_crtc->config.adjusted_mode.crtc_clock;
 879 }
 880
 881 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 882                                              enum pipe pipe)
 883 {
 884         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 886
 887         return intel_crtc->config.cpu_transcoder;
 888 }
 889
 890 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 891 {
 892         struct drm_i915_private *dev_priv = dev->dev_private;
 893         u32 reg = PIPEDSL(pipe);
 894         u32 line1, line2;
 895         u32 line_mask;
 896
 897         if (IS_GEN2(dev))
 898                 line_mask = DSL_LINEMASK_GEN2;
 899         else
 900                 line_mask = DSL_LINEMASK_GEN3;
 901
 902         line1 = I915_READ(reg) & line_mask;
 903         mdelay(5);
 904         line2 = I915_READ(reg) & line_mask;
 905
 906         return line1 == line2;
 907 }
 908
 909 /*
 910  * intel_wait_for_pipe_off - wait for pipe to turn off
 911  * @crtc: crtc whose pipe to wait for
 912  *
 913  * After disabling a pipe, we can't wait for vblank in the usual way,
 914  * spinning on the vblank interrupt status bit, since we won't actually
 915  * see an interrupt when the pipe is disabled.
 916  *
 917  * On Gen4 and above:
 918  *   wait for the pipe register state bit to turn off
 919  *
 920  * Otherwise:
 921  *   wait for the display line value to settle (it usually
 922  *   ends up stopping at the start of the next frame).
 923  *
 924  */
 925 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 926 {
 927         struct drm_device *dev = crtc->base.dev;
 928         struct drm_i915_private *dev_priv = dev->dev_private;
 929         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 930         enum pipe pipe = crtc->pipe;
 931
 932         if (INTEL_INFO(dev)->gen >= 4) {
 933                 int reg = PIPECONF(cpu_transcoder);
 934
 935                 /* Wait for the Pipe State to go off */
 936                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 937                              100))
 938                         WARN(1, "pipe_off wait timed out\n");
 939         } else {
 940                 /* Wait for the display line to settle */
 941                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 942                         WARN(1, "pipe_off wait timed out\n");
 943         }
 944 }
 945
 946 /*
 947  * ibx_digital_port_connected - is the specified port connected?
 948  * @dev_priv: i915 private structure
 949  * @port: the port to test
 950  *
 951  * Returns true if @port is connected, false otherwise.
 952  */
 953 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 954                                 struct intel_digital_port *port)
 955 {
 956         u32 bit;
 957
 958         if (HAS_PCH_IBX(dev_priv->dev)) {
 959                 switch (port->port) {
 960                 case PORT_B:
 961                         bit = SDE_PORTB_HOTPLUG;
 962                         break;
 963                 case PORT_C:
 964                         bit = SDE_PORTC_HOTPLUG;
 965                         break;
 966                 case PORT_D:
 967                         bit = SDE_PORTD_HOTPLUG;
 968                         break;
 969                 default:
 970                         return true;
 971                 }
 972         } else {
 973                 switch (port->port) {
 974                 case PORT_B:
 975                         bit = SDE_PORTB_HOTPLUG_CPT;
 976                         break;
 977                 case PORT_C:
 978                         bit = SDE_PORTC_HOTPLUG_CPT;
 979                         break;
 980                 case PORT_D:
 981                         bit = SDE_PORTD_HOTPLUG_CPT;
 982                         break;
 983                 default:
 984                         return true;
 985                 }
 986         }
 987
 988         return I915_READ(SDEISR) & bit;
 989 }
 990
 991 static const char *state_string(bool enabled)
 992 {
 993         return enabled ? "on" : "off";
 994 }
 995
 996 /* Only for pre-ILK configs */
 997 void assert_pll(struct drm_i915_private *dev_priv,
 998                 enum pipe pipe, bool state)
 999 {
1000         int reg;
1001         u32 val;
1002         bool cur_state;
1003
1004         reg = DPLL(pipe);
1005         val = I915_READ(reg);
1006         cur_state = !!(val & DPLL_VCO_ENABLE);
1007         WARN(cur_state != state,
1008              "PLL state assertion failure (expected %s, current %s)\n",
1009              state_string(state), state_string(cur_state));
1010 }
1011
1012 /* XXX: the dsi pll is shared between MIPI DSI ports */
1013 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1014 {
1015         u32 val;
1016         bool cur_state;
1017
1018         mutex_lock(&dev_priv->dpio_lock);
1019         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1020         mutex_unlock(&dev_priv->dpio_lock);
1021
1022         cur_state = val & DSI_PLL_VCO_EN;
1023         WARN(cur_state != state,
1024              "DSI PLL state assertion failure (expected %s, current %s)\n",
1025              state_string(state), state_string(cur_state));
1026 }
1027 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1028 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1029
1030 struct intel_shared_dpll *
1031 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1032 {
1033         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1034
1035         if (crtc->config.shared_dpll < 0)
1036                 return NULL;
1037
1038         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1039 }
1040
1041 /* For ILK+ */
1042 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1043                         struct intel_shared_dpll *pll,
1044                         bool state)
1045 {
1046         bool cur_state;
1047         struct intel_dpll_hw_state hw_state;
1048
1049         if (WARN (!pll,
1050                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1051                 return;
1052
1053         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1054         WARN(cur_state != state,
1055              "%s assertion failure (expected %s, current %s)\n",
1056              pll->name, state_string(state), state_string(cur_state));
1057 }
1058
1059 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1060                           enum pipe pipe, bool state)
1061 {
1062         int reg;
1063         u32 val;
1064         bool cur_state;
1065         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1066                                                                       pipe);
1067
1068         if (HAS_DDI(dev_priv->dev)) {
1069                 /* DDI does not have a specific FDI_TX register */
1070                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1071                 val = I915_READ(reg);
1072                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1073         } else {
1074                 reg = FDI_TX_CTL(pipe);
1075                 val = I915_READ(reg);
1076                 cur_state = !!(val & FDI_TX_ENABLE);
1077         }
1078         WARN(cur_state != state,
1079              "FDI TX state assertion failure (expected %s, current %s)\n",
1080              state_string(state), state_string(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086                           enum pipe pipe, bool state)
1087 {
1088         int reg;
1089         u32 val;
1090         bool cur_state;
1091
1092         reg = FDI_RX_CTL(pipe);
1093         val = I915_READ(reg);
1094         cur_state = !!(val & FDI_RX_ENABLE);
1095         WARN(cur_state != state,
1096              "FDI RX state assertion failure (expected %s, current %s)\n",
1097              state_string(state), state_string(cur_state));
1098 }
1099 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1100 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1101
1102 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1103                                       enum pipe pipe)
1104 {
1105         int reg;
1106         u32 val;
1107
1108         /* ILK FDI PLL is always enabled */
1109         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1110                 return;
1111
1112         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1113         if (HAS_DDI(dev_priv->dev))
1114                 return;
1115
1116         reg = FDI_TX_CTL(pipe);
1117         val = I915_READ(reg);
1118         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1119 }
1120
1121 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1122                        enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127
1128         reg = FDI_RX_CTL(pipe);
1129         val = I915_READ(reg);
1130         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1131         WARN(cur_state != state,
1132              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1133              state_string(state), state_string(cur_state));
1134 }
1135
1136 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1137                            enum pipe pipe)
1138 {
1139         struct drm_device *dev = dev_priv->dev;
1140         int pp_reg;
1141         u32 val;
1142         enum pipe panel_pipe = PIPE_A;
1143         bool locked = true;
1144
1145         if (WARN_ON(HAS_DDI(dev)))
1146                 return;
1147
1148         if (HAS_PCH_SPLIT(dev)) {
1149                 u32 port_sel;
1150
1151                 pp_reg = PCH_PP_CONTROL;
1152                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1153
1154                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1155                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1156                         panel_pipe = PIPE_B;
1157                 /* XXX: else fix for eDP */
1158         } else if (IS_VALLEYVIEW(dev)) {
1159                 /* presumably write lock depends on pipe, not port select */
1160                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1161                 panel_pipe = pipe;
1162         } else {
1163                 pp_reg = PP_CONTROL;
1164                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1165                         panel_pipe = PIPE_B;
1166         }
1167
1168         val = I915_READ(pp_reg);
1169         if (!(val & PANEL_POWER_ON) ||
1170             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1171                 locked = false;
1172
1173         WARN(panel_pipe == pipe && locked,
1174              "panel assertion failure, pipe %c regs locked\n",
1175              pipe_name(pipe));
1176 }
1177
1178 static void assert_cursor(struct drm_i915_private *dev_priv,
1179                           enum pipe pipe, bool state)
1180 {
1181         struct drm_device *dev = dev_priv->dev;
1182         bool cur_state;
1183
1184         if (IS_845G(dev) || IS_I865G(dev))
1185                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1186         else
1187                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1188
1189         WARN(cur_state != state,
1190              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191              pipe_name(pipe), state_string(state), state_string(cur_state));
1192 }
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1195
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197                  enum pipe pipe, bool state)
1198 {
1199         int reg;
1200         u32 val;
1201         bool cur_state;
1202         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1203                                                                       pipe);
1204
1205         /* if we need the pipe quirk it must be always on */
1206         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1207             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1208                 state = true;
1209
1210         if (!intel_display_power_is_enabled(dev_priv,
1211                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1212                 cur_state = false;
1213         } else {
1214                 reg = PIPECONF(cpu_transcoder);
1215                 val = I915_READ(reg);
1216                 cur_state = !!(val & PIPECONF_ENABLE);
1217         }
1218
1219         WARN(cur_state != state,
1220              "pipe %c assertion failure (expected %s, current %s)\n",
1221              pipe_name(pipe), state_string(state), state_string(cur_state));
1222 }
1223
1224 static void assert_plane(struct drm_i915_private *dev_priv,
1225                          enum plane plane, bool state)
1226 {
1227         int reg;
1228         u32 val;
1229         bool cur_state;
1230
1231         reg = DSPCNTR(plane);
1232         val = I915_READ(reg);
1233         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1234         WARN(cur_state != state,
1235              "plane %c assertion failure (expected %s, current %s)\n",
1236              plane_name(plane), state_string(state), state_string(cur_state));
1237 }
1238
1239 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1240 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1241
1242 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1243                                    enum pipe pipe)
1244 {
1245         struct drm_device *dev = dev_priv->dev;
1246         int reg, i;
1247         u32 val;
1248         int cur_pipe;
1249
1250         /* Primary planes are fixed to pipes on gen4+ */
1251         if (INTEL_INFO(dev)->gen >= 4) {
1252                 reg = DSPCNTR(pipe);
1253                 val = I915_READ(reg);
1254                 WARN(val & DISPLAY_PLANE_ENABLE,
1255                      "plane %c assertion failure, should be disabled but not\n",
1256                      plane_name(pipe));
1257                 return;
1258         }
1259
1260         /* Need to check both planes against the pipe */
1261         for_each_pipe(dev_priv, i) {
1262                 reg = DSPCNTR(i);
1263                 val = I915_READ(reg);
1264                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1265                         DISPPLANE_SEL_PIPE_SHIFT;
1266                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1267                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1268                      plane_name(i), pipe_name(pipe));
1269         }
1270 }
1271
1272 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1273                                     enum pipe pipe)
1274 {
1275         struct drm_device *dev = dev_priv->dev;
1276         int reg, sprite;
1277         u32 val;
1278
1279         if (INTEL_INFO(dev)->gen >= 9) {
1280                 for_each_sprite(pipe, sprite) {
1281                         val = I915_READ(PLANE_CTL(pipe, sprite));
1282                         WARN(val & PLANE_CTL_ENABLE,
1283                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1284                              sprite, pipe_name(pipe));
1285                 }
1286         } else if (IS_VALLEYVIEW(dev)) {
1287                 for_each_sprite(pipe, sprite) {
1288                         reg = SPCNTR(pipe, sprite);
1289                         val = I915_READ(reg);
1290                         WARN(val & SP_ENABLE,
1291                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1292                              sprite_name(pipe, sprite), pipe_name(pipe));
1293                 }
1294         } else if (INTEL_INFO(dev)->gen >= 7) {
1295                 reg = SPRCTL(pipe);
1296                 val = I915_READ(reg);
1297                 WARN(val & SPRITE_ENABLE,
1298                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1299                      plane_name(pipe), pipe_name(pipe));
1300         } else if (INTEL_INFO(dev)->gen >= 5) {
1301                 reg = DVSCNTR(pipe);
1302                 val = I915_READ(reg);
1303                 WARN(val & DVS_ENABLE,
1304                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1305                      plane_name(pipe), pipe_name(pipe));
1306         }
1307 }
1308
1309 static void assert_vblank_disabled(struct drm_crtc *crtc)
1310 {
1311         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1312                 drm_crtc_vblank_put(crtc);
1313 }
1314
1315 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1316 {
1317         u32 val;
1318         bool enabled;
1319
1320         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1321
1322         val = I915_READ(PCH_DREF_CONTROL);
1323         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1324                             DREF_SUPERSPREAD_SOURCE_MASK));
1325         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1326 }
1327
1328 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1329                                            enum pipe pipe)
1330 {
1331         int reg;
1332         u32 val;
1333         bool enabled;
1334
1335         reg = PCH_TRANSCONF(pipe);
1336         val = I915_READ(reg);
1337         enabled = !!(val & TRANS_ENABLE);
1338         WARN(enabled,
1339              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1340              pipe_name(pipe));
1341 }
1342
1343 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1344                             enum pipe pipe, u32 port_sel, u32 val)
1345 {
1346         if ((val & DP_PORT_EN) == 0)
1347                 return false;
1348
1349         if (HAS_PCH_CPT(dev_priv->dev)) {
1350                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1351                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1352                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1353                         return false;
1354         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1355                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1356                         return false;
1357         } else {
1358                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1359                         return false;
1360         }
1361         return true;
1362 }
1363
1364 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1365                               enum pipe pipe, u32 val)
1366 {
1367         if ((val & SDVO_ENABLE) == 0)
1368                 return false;
1369
1370         if (HAS_PCH_CPT(dev_priv->dev)) {
1371                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1372                         return false;
1373         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1374                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1375                         return false;
1376         } else {
1377                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1378                         return false;
1379         }
1380         return true;
1381 }
1382
1383 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1384                               enum pipe pipe, u32 val)
1385 {
1386         if ((val & LVDS_PORT_EN) == 0)
1387                 return false;
1388
1389         if (HAS_PCH_CPT(dev_priv->dev)) {
1390                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1391                         return false;
1392         } else {
1393                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1394                         return false;
1395         }
1396         return true;
1397 }
1398
1399 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1400                               enum pipe pipe, u32 val)
1401 {
1402         if ((val & ADPA_DAC_ENABLE) == 0)
1403                 return false;
1404         if (HAS_PCH_CPT(dev_priv->dev)) {
1405                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1406                         return false;
1407         } else {
1408                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1409                         return false;
1410         }
1411         return true;
1412 }
1413
1414 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1415                                    enum pipe pipe, int reg, u32 port_sel)
1416 {
1417         u32 val = I915_READ(reg);
1418         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1419              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1420              reg, pipe_name(pipe));
1421
1422         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1423              && (val & DP_PIPEB_SELECT),
1424              "IBX PCH dp port still using transcoder B\n");
1425 }
1426
1427 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1428                                      enum pipe pipe, int reg)
1429 {
1430         u32 val = I915_READ(reg);
1431         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1432              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1433              reg, pipe_name(pipe));
1434
1435         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1436              && (val & SDVO_PIPE_B_SELECT),
1437              "IBX PCH hdmi port still using transcoder B\n");
1438 }
1439
1440 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1441                                       enum pipe pipe)
1442 {
1443         int reg;
1444         u32 val;
1445
1446         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1447         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1448         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1449
1450         reg = PCH_ADPA;
1451         val = I915_READ(reg);
1452         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1453              "PCH VGA enabled on transcoder %c, should be disabled\n",
1454              pipe_name(pipe));
1455
1456         reg = PCH_LVDS;
1457         val = I915_READ(reg);
1458         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1459              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1460              pipe_name(pipe));
1461
1462         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1463         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1464         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1465 }
1466
1467 static void intel_init_dpio(struct drm_device *dev)
1468 {
1469         struct drm_i915_private *dev_priv = dev->dev_private;
1470
1471         if (!IS_VALLEYVIEW(dev))
1472                 return;
1473
1474         /*
1475          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1476          * CHV x1 PHY (DP/HDMI D)
1477          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1478          */
1479         if (IS_CHERRYVIEW(dev)) {
1480                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1481                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1482         } else {
1483                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1484         }
1485 }
1486
1487 static void vlv_enable_pll(struct intel_crtc *crtc)
1488 {
1489         struct drm_device *dev = crtc->base.dev;
1490         struct drm_i915_private *dev_priv = dev->dev_private;
1491         int reg = DPLL(crtc->pipe);
1492         u32 dpll = crtc->config.dpll_hw_state.dpll;
1493
1494         assert_pipe_disabled(dev_priv, crtc->pipe);
1495
1496         /* No really, not for ILK+ */
1497         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1498
1499         /* PLL is protected by panel, make sure we can write it */
1500         if (IS_MOBILE(dev_priv->dev))
1501                 assert_panel_unlocked(dev_priv, crtc->pipe);
1502
1503         I915_WRITE(reg, dpll);
1504         POSTING_READ(reg);
1505         udelay(150);
1506
1507         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1508                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1509
1510         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1511         POSTING_READ(DPLL_MD(crtc->pipe));
1512
1513         /* We do this three times for luck */
1514         I915_WRITE(reg, dpll);
1515         POSTING_READ(reg);
1516         udelay(150); /* wait for warmup */
1517         I915_WRITE(reg, dpll);
1518         POSTING_READ(reg);
1519         udelay(150); /* wait for warmup */
1520         I915_WRITE(reg, dpll);
1521         POSTING_READ(reg);
1522         udelay(150); /* wait for warmup */
1523 }
1524
1525 static void chv_enable_pll(struct intel_crtc *crtc)
1526 {
1527         struct drm_device *dev = crtc->base.dev;
1528         struct drm_i915_private *dev_priv = dev->dev_private;
1529         int pipe = crtc->pipe;
1530         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531         u32 tmp;
1532
1533         assert_pipe_disabled(dev_priv, crtc->pipe);
1534
1535         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1536
1537         mutex_lock(&dev_priv->dpio_lock);
1538
1539         /* Enable back the 10bit clock to display controller */
1540         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1541         tmp |= DPIO_DCLKP_EN;
1542         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1543
1544         /*
1545          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1546          */
1547         udelay(1);
1548
1549         /* Enable PLL */
1550         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1551
1552         /* Check PLL is locked */
1553         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1554                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555
1556         /* not sure when this should be written */
1557         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1558         POSTING_READ(DPLL_MD(pipe));
1559
1560         mutex_unlock(&dev_priv->dpio_lock);
1561 }
1562
1563 static int intel_num_dvo_pipes(struct drm_device *dev)
1564 {
1565         struct intel_crtc *crtc;
1566         int count = 0;
1567
1568         for_each_intel_crtc(dev, crtc)
1569                 count += crtc->active &&
1570                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1571
1572         return count;
1573 }
1574
1575 static void i9xx_enable_pll(struct intel_crtc *crtc)
1576 {
1577         struct drm_device *dev = crtc->base.dev;
1578         struct drm_i915_private *dev_priv = dev->dev_private;
1579         int reg = DPLL(crtc->pipe);
1580         u32 dpll = crtc->config.dpll_hw_state.dpll;
1581
1582         assert_pipe_disabled(dev_priv, crtc->pipe);
1583
1584         /* No really, not for ILK+ */
1585         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1586
1587         /* PLL is protected by panel, make sure we can write it */
1588         if (IS_MOBILE(dev) && !IS_I830(dev))
1589                 assert_panel_unlocked(dev_priv, crtc->pipe);
1590
1591         /* Enable DVO 2x clock on both PLLs if necessary */
1592         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1593                 /*
1594                  * It appears to be important that we don't enable this
1595                  * for the current pipe before otherwise configuring the
1596                  * PLL. No idea how this should be handled if multiple
1597                  * DVO outputs are enabled simultaneosly.
1598                  */
1599                 dpll |= DPLL_DVO_2X_MODE;
1600                 I915_WRITE(DPLL(!crtc->pipe),
1601                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1602         }
1603
1604         /* Wait for the clocks to stabilize. */
1605         POSTING_READ(reg);
1606         udelay(150);
1607
1608         if (INTEL_INFO(dev)->gen >= 4) {
1609                 I915_WRITE(DPLL_MD(crtc->pipe),
1610                            crtc->config.dpll_hw_state.dpll_md);
1611         } else {
1612                 /* The pixel multiplier can only be updated once the
1613                  * DPLL is enabled and the clocks are stable.
1614                  *
1615                  * So write it again.
1616                  */
1617                 I915_WRITE(reg, dpll);
1618         }
1619
1620         /* We do this three times for luck */
1621         I915_WRITE(reg, dpll);
1622         POSTING_READ(reg);
1623         udelay(150); /* wait for warmup */
1624         I915_WRITE(reg, dpll);
1625         POSTING_READ(reg);
1626         udelay(150); /* wait for warmup */
1627         I915_WRITE(reg, dpll);
1628         POSTING_READ(reg);
1629         udelay(150); /* wait for warmup */
1630 }
1631
1632 /**
1633  * i9xx_disable_pll - disable a PLL
1634  * @dev_priv: i915 private structure
1635  * @pipe: pipe PLL to disable
1636  *
1637  * Disable the PLL for @pipe, making sure the pipe is off first.
1638  *
1639  * Note!  This is for pre-ILK only.
1640  */
1641 static void i9xx_disable_pll(struct intel_crtc *crtc)
1642 {
1643         struct drm_device *dev = crtc->base.dev;
1644         struct drm_i915_private *dev_priv = dev->dev_private;
1645         enum pipe pipe = crtc->pipe;
1646
1647         /* Disable DVO 2x clock on both PLLs if necessary */
1648         if (IS_I830(dev) &&
1649             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1650             intel_num_dvo_pipes(dev) == 1) {
1651                 I915_WRITE(DPLL(PIPE_B),
1652                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1653                 I915_WRITE(DPLL(PIPE_A),
1654                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1655         }
1656
1657         /* Don't disable pipe or pipe PLLs if needed */
1658         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1659             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1660                 return;
1661
1662         /* Make sure the pipe isn't still relying on us */
1663         assert_pipe_disabled(dev_priv, pipe);
1664
1665         I915_WRITE(DPLL(pipe), 0);
1666         POSTING_READ(DPLL(pipe));
1667 }
1668
1669 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1670 {
1671         u32 val = 0;
1672
1673         /* Make sure the pipe isn't still relying on us */
1674         assert_pipe_disabled(dev_priv, pipe);
1675
1676         /*
1677          * Leave integrated clock source and reference clock enabled for pipe B.
1678          * The latter is needed for VGA hotplug / manual detection.
1679          */
1680         if (pipe == PIPE_B)
1681                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1682         I915_WRITE(DPLL(pipe), val);
1683         POSTING_READ(DPLL(pipe));
1684
1685 }
1686
1687 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1688 {
1689         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1690         u32 val;
1691
1692         /* Make sure the pipe isn't still relying on us */
1693         assert_pipe_disabled(dev_priv, pipe);
1694
1695         /* Set PLL en = 0 */
1696         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1697         if (pipe != PIPE_A)
1698                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1699         I915_WRITE(DPLL(pipe), val);
1700         POSTING_READ(DPLL(pipe));
1701
1702         mutex_lock(&dev_priv->dpio_lock);
1703
1704         /* Disable 10bit clock to display controller */
1705         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1706         val &= ~DPIO_DCLKP_EN;
1707         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1708
1709         /* disable left/right clock distribution */
1710         if (pipe != PIPE_B) {
1711                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1712                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1713                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1714         } else {
1715                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1716                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1717                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1718         }
1719
1720         mutex_unlock(&dev_priv->dpio_lock);
1721 }
1722
1723 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1724                 struct intel_digital_port *dport)
1725 {
1726         u32 port_mask;
1727         int dpll_reg;
1728
1729         switch (dport->port) {
1730         case PORT_B:
1731                 port_mask = DPLL_PORTB_READY_MASK;
1732                 dpll_reg = DPLL(0);
1733                 break;
1734         case PORT_C:
1735                 port_mask = DPLL_PORTC_READY_MASK;
1736                 dpll_reg = DPLL(0);
1737                 break;
1738         case PORT_D:
1739                 port_mask = DPLL_PORTD_READY_MASK;
1740                 dpll_reg = DPIO_PHY_STATUS;
1741                 break;
1742         default:
1743                 BUG();
1744         }
1745
1746         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1747                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1748                      port_name(dport->port), I915_READ(dpll_reg));
1749 }
1750
1751 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1752 {
1753         struct drm_device *dev = crtc->base.dev;
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1756
1757         if (WARN_ON(pll == NULL))
1758                 return;
1759
1760         WARN_ON(!pll->refcount);
1761         if (pll->active == 0) {
1762                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1763                 WARN_ON(pll->on);
1764                 assert_shared_dpll_disabled(dev_priv, pll);
1765
1766                 pll->mode_set(dev_priv, pll);
1767         }
1768 }
1769
1770 /**
1771  * intel_enable_shared_dpll - enable PCH PLL
1772  * @dev_priv: i915 private structure
1773  * @pipe: pipe PLL to enable
1774  *
1775  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1776  * drives the transcoder clock.
1777  */
1778 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1779 {
1780         struct drm_device *dev = crtc->base.dev;
1781         struct drm_i915_private *dev_priv = dev->dev_private;
1782         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1783
1784         if (WARN_ON(pll == NULL))
1785                 return;
1786
1787         if (WARN_ON(pll->refcount == 0))
1788                 return;
1789
1790         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1791                       pll->name, pll->active, pll->on,
1792                       crtc->base.base.id);
1793
1794         if (pll->active++) {
1795                 WARN_ON(!pll->on);
1796                 assert_shared_dpll_enabled(dev_priv, pll);
1797                 return;
1798         }
1799         WARN_ON(pll->on);
1800
1801         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1802
1803         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1804         pll->enable(dev_priv, pll);
1805         pll->on = true;
1806 }
1807
1808 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1809 {
1810         struct drm_device *dev = crtc->base.dev;
1811         struct drm_i915_private *dev_priv = dev->dev_private;
1812         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1813
1814         /* PCH only available on ILK+ */
1815         BUG_ON(INTEL_INFO(dev)->gen < 5);
1816         if (WARN_ON(pll == NULL))
1817                return;
1818
1819         if (WARN_ON(pll->refcount == 0))
1820                 return;
1821
1822         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1823                       pll->name, pll->active, pll->on,
1824                       crtc->base.base.id);
1825
1826         if (WARN_ON(pll->active == 0)) {
1827                 assert_shared_dpll_disabled(dev_priv, pll);
1828                 return;
1829         }
1830
1831         assert_shared_dpll_enabled(dev_priv, pll);
1832         WARN_ON(!pll->on);
1833         if (--pll->active)
1834                 return;
1835
1836         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1837         pll->disable(dev_priv, pll);
1838         pll->on = false;
1839
1840         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1841 }
1842
1843 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1844                                            enum pipe pipe)
1845 {
1846         struct drm_device *dev = dev_priv->dev;
1847         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1849         uint32_t reg, val, pipeconf_val;
1850
1851         /* PCH only available on ILK+ */
1852         BUG_ON(!HAS_PCH_SPLIT(dev));
1853
1854         /* Make sure PCH DPLL is enabled */
1855         assert_shared_dpll_enabled(dev_priv,
1856                                    intel_crtc_to_shared_dpll(intel_crtc));
1857
1858         /* FDI must be feeding us bits for PCH ports */
1859         assert_fdi_tx_enabled(dev_priv, pipe);
1860         assert_fdi_rx_enabled(dev_priv, pipe);
1861
1862         if (HAS_PCH_CPT(dev)) {
1863                 /* Workaround: Set the timing override bit before enabling the
1864                  * pch transcoder. */
1865                 reg = TRANS_CHICKEN2(pipe);
1866                 val = I915_READ(reg);
1867                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1868                 I915_WRITE(reg, val);
1869         }
1870
1871         reg = PCH_TRANSCONF(pipe);
1872         val = I915_READ(reg);
1873         pipeconf_val = I915_READ(PIPECONF(pipe));
1874
1875         if (HAS_PCH_IBX(dev_priv->dev)) {
1876                 /*
1877                  * make the BPC in transcoder be consistent with
1878                  * that in pipeconf reg.
1879                  */
1880                 val &= ~PIPECONF_BPC_MASK;
1881                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1882         }
1883
1884         val &= ~TRANS_INTERLACE_MASK;
1885         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1886                 if (HAS_PCH_IBX(dev_priv->dev) &&
1887                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1888                         val |= TRANS_LEGACY_INTERLACED_ILK;
1889                 else
1890                         val |= TRANS_INTERLACED;
1891         else
1892                 val |= TRANS_PROGRESSIVE;
1893
1894         I915_WRITE(reg, val | TRANS_ENABLE);
1895         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1896                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1897 }
1898
1899 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1900                                       enum transcoder cpu_transcoder)
1901 {
1902         u32 val, pipeconf_val;
1903
1904         /* PCH only available on ILK+ */
1905         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1906
1907         /* FDI must be feeding us bits for PCH ports */
1908         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1909         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1910
1911         /* Workaround: set timing override bit. */
1912         val = I915_READ(_TRANSA_CHICKEN2);
1913         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1914         I915_WRITE(_TRANSA_CHICKEN2, val);
1915
1916         val = TRANS_ENABLE;
1917         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1918
1919         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1920             PIPECONF_INTERLACED_ILK)
1921                 val |= TRANS_INTERLACED;
1922         else
1923                 val |= TRANS_PROGRESSIVE;
1924
1925         I915_WRITE(LPT_TRANSCONF, val);
1926         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1927                 DRM_ERROR("Failed to enable PCH transcoder\n");
1928 }
1929
1930 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1931                                             enum pipe pipe)
1932 {
1933         struct drm_device *dev = dev_priv->dev;
1934         uint32_t reg, val;
1935
1936         /* FDI relies on the transcoder */
1937         assert_fdi_tx_disabled(dev_priv, pipe);
1938         assert_fdi_rx_disabled(dev_priv, pipe);
1939
1940         /* Ports must be off as well */
1941         assert_pch_ports_disabled(dev_priv, pipe);
1942
1943         reg = PCH_TRANSCONF(pipe);
1944         val = I915_READ(reg);
1945         val &= ~TRANS_ENABLE;
1946         I915_WRITE(reg, val);
1947         /* wait for PCH transcoder off, transcoder state */
1948         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1949                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1950
1951         if (!HAS_PCH_IBX(dev)) {
1952                 /* Workaround: Clear the timing override chicken bit again. */
1953                 reg = TRANS_CHICKEN2(pipe);
1954                 val = I915_READ(reg);
1955                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1956                 I915_WRITE(reg, val);
1957         }
1958 }
1959
1960 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1961 {
1962         u32 val;
1963
1964         val = I915_READ(LPT_TRANSCONF);
1965         val &= ~TRANS_ENABLE;
1966         I915_WRITE(LPT_TRANSCONF, val);
1967         /* wait for PCH transcoder off, transcoder state */
1968         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1969                 DRM_ERROR("Failed to disable PCH transcoder\n");
1970
1971         /* Workaround: clear timing override bit. */
1972         val = I915_READ(_TRANSA_CHICKEN2);
1973         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1974         I915_WRITE(_TRANSA_CHICKEN2, val);
1975 }
1976
1977 /**
1978  * intel_enable_pipe - enable a pipe, asserting requirements
1979  * @crtc: crtc responsible for the pipe
1980  *
1981  * Enable @crtc's pipe, making sure that various hardware specific requirements
1982  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1983  */
1984 static void intel_enable_pipe(struct intel_crtc *crtc)
1985 {
1986         struct drm_device *dev = crtc->base.dev;
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         enum pipe pipe = crtc->pipe;
1989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1990                                                                       pipe);
1991         enum pipe pch_transcoder;
1992         int reg;
1993         u32 val;
1994
1995         assert_planes_disabled(dev_priv, pipe);
1996         assert_cursor_disabled(dev_priv, pipe);
1997         assert_sprites_disabled(dev_priv, pipe);
1998
1999         if (HAS_PCH_LPT(dev_priv->dev))
2000                 pch_transcoder = TRANSCODER_A;
2001         else
2002                 pch_transcoder = pipe;
2003
2004         /*
2005          * A pipe without a PLL won't actually be able to drive bits from
2006          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2007          * need the check.
2008          */
2009         if (!HAS_PCH_SPLIT(dev_priv->dev))
2010                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2011                         assert_dsi_pll_enabled(dev_priv);
2012                 else
2013                         assert_pll_enabled(dev_priv, pipe);
2014         else {
2015                 if (crtc->config.has_pch_encoder) {
2016                         /* if driving the PCH, we need FDI enabled */
2017                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2018                         assert_fdi_tx_pll_enabled(dev_priv,
2019                                                   (enum pipe) cpu_transcoder);
2020                 }
2021                 /* FIXME: assert CPU port conditions for SNB+ */
2022         }
2023
2024         reg = PIPECONF(cpu_transcoder);
2025         val = I915_READ(reg);
2026         if (val & PIPECONF_ENABLE) {
2027                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2028                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2029                 return;
2030         }
2031
2032         I915_WRITE(reg, val | PIPECONF_ENABLE);
2033         POSTING_READ(reg);
2034 }
2035
2036 /**
2037  * intel_disable_pipe - disable a pipe, asserting requirements
2038  * @crtc: crtc whose pipes is to be disabled
2039  *
2040  * Disable the pipe of @crtc, making sure that various hardware
2041  * specific requirements are met, if applicable, e.g. plane
2042  * disabled, panel fitter off, etc.
2043  *
2044  * Will wait until the pipe has shut down before returning.
2045  */
2046 static void intel_disable_pipe(struct intel_crtc *crtc)
2047 {
2048         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2049         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2050         enum pipe pipe = crtc->pipe;
2051         int reg;
2052         u32 val;
2053
2054         /*
2055          * Make sure planes won't keep trying to pump pixels to us,
2056          * or we might hang the display.
2057          */
2058         assert_planes_disabled(dev_priv, pipe);
2059         assert_cursor_disabled(dev_priv, pipe);
2060         assert_sprites_disabled(dev_priv, pipe);
2061
2062         reg = PIPECONF(cpu_transcoder);
2063         val = I915_READ(reg);
2064         if ((val & PIPECONF_ENABLE) == 0)
2065                 return;
2066
2067         /*
2068          * Double wide has implications for planes
2069          * so best keep it disabled when not needed.
2070          */
2071         if (crtc->config.double_wide)
2072                 val &= ~PIPECONF_DOUBLE_WIDE;
2073
2074         /* Don't disable pipe or pipe PLLs if needed */
2075         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2076             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2077                 val &= ~PIPECONF_ENABLE;
2078
2079         I915_WRITE(reg, val);
2080         if ((val & PIPECONF_ENABLE) == 0)
2081                 intel_wait_for_pipe_off(crtc);
2082 }
2083
2084 /*
2085  * Plane regs are double buffered, going from enabled->disabled needs a
2086  * trigger in order to latch.  The display address reg provides this.
2087  */
2088 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2089                                enum plane plane)
2090 {
2091         struct drm_device *dev = dev_priv->dev;
2092         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2093
2094         I915_WRITE(reg, I915_READ(reg));
2095         POSTING_READ(reg);
2096 }
2097
2098 /**
2099  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2100  * @plane:  plane to be enabled
2101  * @crtc: crtc for the plane
2102  *
2103  * Enable @plane on @crtc, making sure that the pipe is running first.
2104  */
2105 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2106                                           struct drm_crtc *crtc)
2107 {
2108         struct drm_device *dev = plane->dev;
2109         struct drm_i915_private *dev_priv = dev->dev_private;
2110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2111
2112         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2113         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2114
2115         if (intel_crtc->primary_enabled)
2116                 return;
2117
2118         intel_crtc->primary_enabled = true;
2119
2120         dev_priv->display.update_primary_plane(crtc, plane->fb,
2121                                                crtc->x, crtc->y);
2122
2123         /*
2124          * BDW signals flip done immediately if the plane
2125          * is disabled, even if the plane enable is already
2126          * armed to occur at the next vblank :(
2127          */
2128         if (IS_BROADWELL(dev))
2129                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2130 }
2131
2132 /**
2133  * intel_disable_primary_hw_plane - disable the primary hardware plane
2134  * @plane: plane to be disabled
2135  * @crtc: crtc for the plane
2136  *
2137  * Disable @plane on @crtc, making sure that the pipe is running first.
2138  */
2139 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2140                                            struct drm_crtc *crtc)
2141 {
2142         struct drm_device *dev = plane->dev;
2143         struct drm_i915_private *dev_priv = dev->dev_private;
2144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2145
2146         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2147
2148         if (!intel_crtc->primary_enabled)
2149                 return;
2150
2151         intel_crtc->primary_enabled = false;
2152
2153         dev_priv->display.update_primary_plane(crtc, plane->fb,
2154                                                crtc->x, crtc->y);
2155 }
2156
2157 static bool need_vtd_wa(struct drm_device *dev)
2158 {
2159 #ifdef CONFIG_INTEL_IOMMU
2160         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2161                 return true;
2162 #endif
2163         return false;
2164 }
2165
2166 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2167 {
2168         int tile_height;
2169
2170         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2171         return ALIGN(height, tile_height);
2172 }
2173
2174 int
2175 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2176                            struct drm_i915_gem_object *obj,
2177                            struct intel_engine_cs *pipelined)
2178 {
2179         struct drm_i915_private *dev_priv = dev->dev_private;
2180         u32 alignment;
2181         int ret;
2182
2183         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2184
2185         switch (obj->tiling_mode) {
2186         case I915_TILING_NONE:
2187                 if (INTEL_INFO(dev)->gen >= 9)
2188                         alignment = 256 * 1024;
2189                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2190                         alignment = 128 * 1024;
2191                 else if (INTEL_INFO(dev)->gen >= 4)
2192                         alignment = 4 * 1024;
2193                 else
2194                         alignment = 64 * 1024;
2195                 break;
2196         case I915_TILING_X:
2197                 if (INTEL_INFO(dev)->gen >= 9)
2198                         alignment = 256 * 1024;
2199                 else {
2200                         /* pin() will align the object as required by fence */
2201                         alignment = 0;
2202                 }
2203                 break;
2204         case I915_TILING_Y:
2205                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2206                 return -EINVAL;
2207         default:
2208                 BUG();
2209         }
2210
2211         /* Note that the w/a also requires 64 PTE of padding following the
2212          * bo. We currently fill all unused PTE with the shadow page and so
2213          * we should always have valid PTE following the scanout preventing
2214          * the VT-d warning.
2215          */
2216         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2217                 alignment = 256 * 1024;
2218
2219         /*
2220          * Global gtt pte registers are special registers which actually forward
2221          * writes to a chunk of system memory. Which means that there is no risk
2222          * that the register values disappear as soon as we call
2223          * intel_runtime_pm_put(), so it is correct to wrap only the
2224          * pin/unpin/fence and not more.
2225          */
2226         intel_runtime_pm_get(dev_priv);
2227
2228         dev_priv->mm.interruptible = false;
2229         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2230         if (ret)
2231                 goto err_interruptible;
2232
2233         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2234          * fence, whereas 965+ only requires a fence if using
2235          * framebuffer compression.  For simplicity, we always install
2236          * a fence as the cost is not that onerous.
2237          */
2238         ret = i915_gem_object_get_fence(obj);
2239         if (ret)
2240                 goto err_unpin;
2241
2242         i915_gem_object_pin_fence(obj);
2243
2244         dev_priv->mm.interruptible = true;
2245         intel_runtime_pm_put(dev_priv);
2246         return 0;
2247
2248 err_unpin:
2249         i915_gem_object_unpin_from_display_plane(obj);
2250 err_interruptible:
2251         dev_priv->mm.interruptible = true;
2252         intel_runtime_pm_put(dev_priv);
2253         return ret;
2254 }
2255
2256 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2257 {
2258         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2259
2260         i915_gem_object_unpin_fence(obj);
2261         i915_gem_object_unpin_from_display_plane(obj);
2262 }
2263
2264 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2265  * is assumed to be a power-of-two. */
2266 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2267                                              unsigned int tiling_mode,
2268                                              unsigned int cpp,
2269                                              unsigned int pitch)
2270 {
2271         if (tiling_mode != I915_TILING_NONE) {
2272                 unsigned int tile_rows, tiles;
2273
2274                 tile_rows = *y / 8;
2275                 *y %= 8;
2276
2277                 tiles = *x / (512/cpp);
2278                 *x %= 512/cpp;
2279
2280                 return tile_rows * pitch * 8 + tiles * 4096;
2281         } else {
2282                 unsigned int offset;
2283
2284                 offset = *y * pitch + *x * cpp;
2285                 *y = 0;
2286                 *x = (offset & 4095) / cpp;
2287                 return offset & -4096;
2288         }
2289 }
2290
2291 int intel_format_to_fourcc(int format)
2292 {
2293         switch (format) {
2294         case DISPPLANE_8BPP:
2295                 return DRM_FORMAT_C8;
2296         case DISPPLANE_BGRX555:
2297                 return DRM_FORMAT_XRGB1555;
2298         case DISPPLANE_BGRX565:
2299                 return DRM_FORMAT_RGB565;
2300         default:
2301         case DISPPLANE_BGRX888:
2302                 return DRM_FORMAT_XRGB8888;
2303         case DISPPLANE_RGBX888:
2304                 return DRM_FORMAT_XBGR8888;
2305         case DISPPLANE_BGRX101010:
2306                 return DRM_FORMAT_XRGB2101010;
2307         case DISPPLANE_RGBX101010:
2308                 return DRM_FORMAT_XBGR2101010;
2309         }
2310 }
2311
2312 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2313                                   struct intel_plane_config *plane_config)
2314 {
2315         struct drm_device *dev = crtc->base.dev;
2316         struct drm_i915_gem_object *obj = NULL;
2317         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2318         u32 base = plane_config->base;
2319
2320         if (plane_config->size == 0)
2321                 return false;
2322
2323         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2324                                                              plane_config->size);
2325         if (!obj)
2326                 return false;
2327
2328         if (plane_config->tiled) {
2329                 obj->tiling_mode = I915_TILING_X;
2330                 obj->stride = crtc->base.primary->fb->pitches[0];
2331         }
2332
2333         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2334         mode_cmd.width = crtc->base.primary->fb->width;
2335         mode_cmd.height = crtc->base.primary->fb->height;
2336         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2337
2338         mutex_lock(&dev->struct_mutex);
2339
2340         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2341                                    &mode_cmd, obj)) {
2342                 DRM_DEBUG_KMS("intel fb init failed\n");
2343                 goto out_unref_obj;
2344         }
2345
2346         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2347         mutex_unlock(&dev->struct_mutex);
2348
2349         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2350         return true;
2351
2352 out_unref_obj:
2353         drm_gem_object_unreference(&obj->base);
2354         mutex_unlock(&dev->struct_mutex);
2355         return false;
2356 }
2357
2358 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2359                                  struct intel_plane_config *plane_config)
2360 {
2361         struct drm_device *dev = intel_crtc->base.dev;
2362         struct drm_crtc *c;
2363         struct intel_crtc *i;
2364         struct drm_i915_gem_object *obj;
2365
2366         if (!intel_crtc->base.primary->fb)
2367                 return;
2368
2369         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2370                 return;
2371
2372         kfree(intel_crtc->base.primary->fb);
2373         intel_crtc->base.primary->fb = NULL;
2374
2375         /*
2376          * Failed to alloc the obj, check to see if we should share
2377          * an fb with another CRTC instead
2378          */
2379         for_each_crtc(dev, c) {
2380                 i = to_intel_crtc(c);
2381
2382                 if (c == &intel_crtc->base)
2383                         continue;
2384
2385                 if (!i->active)
2386                         continue;
2387
2388                 obj = intel_fb_obj(c->primary->fb);
2389                 if (obj == NULL)
2390                         continue;
2391
2392                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2393                         drm_framebuffer_reference(c->primary->fb);
2394                         intel_crtc->base.primary->fb = c->primary->fb;
2395                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2396                         break;
2397                 }
2398         }
2399 }
2400
2401 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2402                                       struct drm_framebuffer *fb,
2403                                       int x, int y)
2404 {
2405         struct drm_device *dev = crtc->dev;
2406         struct drm_i915_private *dev_priv = dev->dev_private;
2407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2408         struct drm_i915_gem_object *obj;
2409         int plane = intel_crtc->plane;
2410         unsigned long linear_offset;
2411         u32 dspcntr;
2412         u32 reg = DSPCNTR(plane);
2413         int pixel_size;
2414
2415         if (!intel_crtc->primary_enabled) {
2416                 I915_WRITE(reg, 0);
2417                 if (INTEL_INFO(dev)->gen >= 4)
2418                         I915_WRITE(DSPSURF(plane), 0);
2419                 else
2420                         I915_WRITE(DSPADDR(plane), 0);
2421                 POSTING_READ(reg);
2422                 return;
2423         }
2424
2425         obj = intel_fb_obj(fb);
2426         if (WARN_ON(obj == NULL))
2427                 return;
2428
2429         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2430
2431         dspcntr = DISPPLANE_GAMMA_ENABLE;
2432
2433         dspcntr |= DISPLAY_PLANE_ENABLE;
2434
2435         if (INTEL_INFO(dev)->gen < 4) {
2436                 if (intel_crtc->pipe == PIPE_B)
2437                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2438
2439                 /* pipesrc and dspsize control the size that is scaled from,
2440                  * which should always be the user's requested size.
2441                  */
2442                 I915_WRITE(DSPSIZE(plane),
2443                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2444                            (intel_crtc->config.pipe_src_w - 1));
2445                 I915_WRITE(DSPPOS(plane), 0);
2446         }
2447
2448         switch (fb->pixel_format) {
2449         case DRM_FORMAT_C8:
2450                 dspcntr |= DISPPLANE_8BPP;
2451                 break;
2452         case DRM_FORMAT_XRGB1555:
2453         case DRM_FORMAT_ARGB1555:
2454                 dspcntr |= DISPPLANE_BGRX555;
2455                 break;
2456         case DRM_FORMAT_RGB565:
2457                 dspcntr |= DISPPLANE_BGRX565;
2458                 break;
2459         case DRM_FORMAT_XRGB8888:
2460         case DRM_FORMAT_ARGB8888:
2461                 dspcntr |= DISPPLANE_BGRX888;
2462                 break;
2463         case DRM_FORMAT_XBGR8888:
2464         case DRM_FORMAT_ABGR8888:
2465                 dspcntr |= DISPPLANE_RGBX888;
2466                 break;
2467         case DRM_FORMAT_XRGB2101010:
2468         case DRM_FORMAT_ARGB2101010:
2469                 dspcntr |= DISPPLANE_BGRX101010;
2470                 break;
2471         case DRM_FORMAT_XBGR2101010:
2472         case DRM_FORMAT_ABGR2101010:
2473                 dspcntr |= DISPPLANE_RGBX101010;
2474                 break;
2475         default:
2476                 BUG();
2477         }
2478
2479         if (INTEL_INFO(dev)->gen >= 4 &&
2480             obj->tiling_mode != I915_TILING_NONE)
2481                 dspcntr |= DISPPLANE_TILED;
2482
2483         if (IS_G4X(dev))
2484                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2485
2486         linear_offset = y * fb->pitches[0] + x * pixel_size;
2487
2488         if (INTEL_INFO(dev)->gen >= 4) {
2489                 intel_crtc->dspaddr_offset =
2490                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2491                                                        pixel_size,
2492                                                        fb->pitches[0]);
2493                 linear_offset -= intel_crtc->dspaddr_offset;
2494         } else {
2495                 intel_crtc->dspaddr_offset = linear_offset;
2496         }
2497
2498         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2499                 dspcntr |= DISPPLANE_ROTATE_180;
2500
2501                 x += (intel_crtc->config.pipe_src_w - 1);
2502                 y += (intel_crtc->config.pipe_src_h - 1);
2503
2504                 /* Finding the last pixel of the last line of the display
2505                 data and adding to linear_offset*/
2506                 linear_offset +=
2507                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2508                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2509         }
2510
2511         I915_WRITE(reg, dspcntr);
2512
2513         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2514                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2515                       fb->pitches[0]);
2516         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2517         if (INTEL_INFO(dev)->gen >= 4) {
2518                 I915_WRITE(DSPSURF(plane),
2519                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2520                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2521                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2522         } else
2523                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2524         POSTING_READ(reg);
2525 }
2526
2527 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2528                                           struct drm_framebuffer *fb,
2529                                           int x, int y)
2530 {
2531         struct drm_device *dev = crtc->dev;
2532         struct drm_i915_private *dev_priv = dev->dev_private;
2533         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2534         struct drm_i915_gem_object *obj;
2535         int plane = intel_crtc->plane;
2536         unsigned long linear_offset;
2537         u32 dspcntr;
2538         u32 reg = DSPCNTR(plane);
2539         int pixel_size;
2540
2541         if (!intel_crtc->primary_enabled) {
2542                 I915_WRITE(reg, 0);
2543                 I915_WRITE(DSPSURF(plane), 0);
2544                 POSTING_READ(reg);
2545                 return;
2546         }
2547
2548         obj = intel_fb_obj(fb);
2549         if (WARN_ON(obj == NULL))
2550                 return;
2551
2552         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2553
2554         dspcntr = DISPPLANE_GAMMA_ENABLE;
2555
2556         dspcntr |= DISPLAY_PLANE_ENABLE;
2557
2558         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2559                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2560
2561         switch (fb->pixel_format) {
2562         case DRM_FORMAT_C8:
2563                 dspcntr |= DISPPLANE_8BPP;
2564                 break;
2565         case DRM_FORMAT_RGB565:
2566                 dspcntr |= DISPPLANE_BGRX565;
2567                 break;
2568         case DRM_FORMAT_XRGB8888:
2569         case DRM_FORMAT_ARGB8888:
2570                 dspcntr |= DISPPLANE_BGRX888;
2571                 break;
2572         case DRM_FORMAT_XBGR8888:
2573         case DRM_FORMAT_ABGR8888:
2574                 dspcntr |= DISPPLANE_RGBX888;
2575                 break;
2576         case DRM_FORMAT_XRGB2101010:
2577         case DRM_FORMAT_ARGB2101010:
2578                 dspcntr |= DISPPLANE_BGRX101010;
2579                 break;
2580         case DRM_FORMAT_XBGR2101010:
2581         case DRM_FORMAT_ABGR2101010:
2582                 dspcntr |= DISPPLANE_RGBX101010;
2583                 break;
2584         default:
2585                 BUG();
2586         }
2587
2588         if (obj->tiling_mode != I915_TILING_NONE)
2589                 dspcntr |= DISPPLANE_TILED;
2590
2591         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2592                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2593
2594         linear_offset = y * fb->pitches[0] + x * pixel_size;
2595         intel_crtc->dspaddr_offset =
2596                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2597                                                pixel_size,
2598                                                fb->pitches[0]);
2599         linear_offset -= intel_crtc->dspaddr_offset;
2600         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2601                 dspcntr |= DISPPLANE_ROTATE_180;
2602
2603                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2604                         x += (intel_crtc->config.pipe_src_w - 1);
2605                         y += (intel_crtc->config.pipe_src_h - 1);
2606
2607                         /* Finding the last pixel of the last line of the display
2608                         data and adding to linear_offset*/
2609                         linear_offset +=
2610                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2611                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2612                 }
2613         }
2614
2615         I915_WRITE(reg, dspcntr);
2616
2617         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2618                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2619                       fb->pitches[0]);
2620         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2621         I915_WRITE(DSPSURF(plane),
2622                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2623         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2624                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2625         } else {
2626                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2627                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2628         }
2629         POSTING_READ(reg);
2630 }
2631
2632 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2633                                          struct drm_framebuffer *fb,
2634                                          int x, int y)
2635 {
2636         struct drm_device *dev = crtc->dev;
2637         struct drm_i915_private *dev_priv = dev->dev_private;
2638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2639         struct intel_framebuffer *intel_fb;
2640         struct drm_i915_gem_object *obj;
2641         int pipe = intel_crtc->pipe;
2642         u32 plane_ctl, stride;
2643
2644         if (!intel_crtc->primary_enabled) {
2645                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2646                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2647                 POSTING_READ(PLANE_CTL(pipe, 0));
2648                 return;
2649         }
2650
2651         plane_ctl = PLANE_CTL_ENABLE |
2652                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2653                     PLANE_CTL_PIPE_CSC_ENABLE;
2654
2655         switch (fb->pixel_format) {
2656         case DRM_FORMAT_RGB565:
2657                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2658                 break;
2659         case DRM_FORMAT_XRGB8888:
2660                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2661                 break;
2662         case DRM_FORMAT_XBGR8888:
2663                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2664                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2665                 break;
2666         case DRM_FORMAT_XRGB2101010:
2667                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2668                 break;
2669         case DRM_FORMAT_XBGR2101010:
2670                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2671                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2672                 break;
2673         default:
2674                 BUG();
2675         }
2676
2677         intel_fb = to_intel_framebuffer(fb);
2678         obj = intel_fb->obj;
2679
2680         /*
2681          * The stride is either expressed as a multiple of 64 bytes chunks for
2682          * linear buffers or in number of tiles for tiled buffers.
2683          */
2684         switch (obj->tiling_mode) {
2685         case I915_TILING_NONE:
2686                 stride = fb->pitches[0] >> 6;
2687                 break;
2688         case I915_TILING_X:
2689                 plane_ctl |= PLANE_CTL_TILED_X;
2690                 stride = fb->pitches[0] >> 9;
2691                 break;
2692         default:
2693                 BUG();
2694         }
2695
2696         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2697         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2698                 plane_ctl |= PLANE_CTL_ROTATE_180;
2699
2700         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2701
2702         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2703                       i915_gem_obj_ggtt_offset(obj),
2704                       x, y, fb->width, fb->height,
2705                       fb->pitches[0]);
2706
2707         I915_WRITE(PLANE_POS(pipe, 0), 0);
2708         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2709         I915_WRITE(PLANE_SIZE(pipe, 0),
2710                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2711                    (intel_crtc->config.pipe_src_w - 1));
2712         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2713         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2714
2715         POSTING_READ(PLANE_SURF(pipe, 0));
2716 }
2717
2718 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2719 static int
2720 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2721                            int x, int y, enum mode_set_atomic state)
2722 {
2723         struct drm_device *dev = crtc->dev;
2724         struct drm_i915_private *dev_priv = dev->dev_private;
2725
2726         if (dev_priv->display.disable_fbc)
2727                 dev_priv->display.disable_fbc(dev);
2728
2729         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2730
2731         return 0;
2732 }
2733
2734 void intel_display_handle_reset(struct drm_device *dev)
2735 {
2736         struct drm_i915_private *dev_priv = dev->dev_private;
2737         struct drm_crtc *crtc;
2738
2739         /*
2740          * Flips in the rings have been nuked by the reset,
2741          * so complete all pending flips so that user space
2742          * will get its events and not get stuck.
2743          *
2744          * Also update the base address of all primary
2745          * planes to the the last fb to make sure we're
2746          * showing the correct fb after a reset.
2747          *
2748          * Need to make two loops over the crtcs so that we
2749          * don't try to grab a crtc mutex before the
2750          * pending_flip_queue really got woken up.
2751          */
2752
2753         for_each_crtc(dev, crtc) {
2754                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2755                 enum plane plane = intel_crtc->plane;
2756
2757                 intel_prepare_page_flip(dev, plane);
2758                 intel_finish_page_flip_plane(dev, plane);
2759         }
2760
2761         for_each_crtc(dev, crtc) {
2762                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2763
2764                 drm_modeset_lock(&crtc->mutex, NULL);
2765                 /*
2766                  * FIXME: Once we have proper support for primary planes (and
2767                  * disabling them without disabling the entire crtc) allow again
2768                  * a NULL crtc->primary->fb.
2769                  */
2770                 if (intel_crtc->active && crtc->primary->fb)
2771                         dev_priv->display.update_primary_plane(crtc,
2772                                                                crtc->primary->fb,
2773                                                                crtc->x,
2774                                                                crtc->y);
2775                 drm_modeset_unlock(&crtc->mutex);
2776         }
2777 }
2778
2779 static int
2780 intel_finish_fb(struct drm_framebuffer *old_fb)
2781 {
2782         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2783         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2784         bool was_interruptible = dev_priv->mm.interruptible;
2785         int ret;
2786
2787         /* Big Hammer, we also need to ensure that any pending
2788          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2789          * current scanout is retired before unpinning the old
2790          * framebuffer.
2791          *
2792          * This should only fail upon a hung GPU, in which case we
2793          * can safely continue.
2794          */
2795         dev_priv->mm.interruptible = false;
2796         ret = i915_gem_object_finish_gpu(obj);
2797         dev_priv->mm.interruptible = was_interruptible;
2798
2799         return ret;
2800 }
2801
2802 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2803 {
2804         struct drm_device *dev = crtc->dev;
2805         struct drm_i915_private *dev_priv = dev->dev_private;
2806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2807         bool pending;
2808
2809         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2810             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2811                 return false;
2812
2813         spin_lock_irq(&dev->event_lock);
2814         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2815         spin_unlock_irq(&dev->event_lock);
2816
2817         return pending;
2818 }
2819
2820 static void intel_update_pipe_size(struct intel_crtc *crtc)
2821 {
2822         struct drm_device *dev = crtc->base.dev;
2823         struct drm_i915_private *dev_priv = dev->dev_private;
2824         const struct drm_display_mode *adjusted_mode;
2825
2826         if (!i915.fastboot)
2827                 return;
2828
2829         /*
2830          * Update pipe size and adjust fitter if needed: the reason for this is
2831          * that in compute_mode_changes we check the native mode (not the pfit
2832          * mode) to see if we can flip rather than do a full mode set. In the
2833          * fastboot case, we'll flip, but if we don't update the pipesrc and
2834          * pfit state, we'll end up with a big fb scanned out into the wrong
2835          * sized surface.
2836          *
2837          * To fix this properly, we need to hoist the checks up into
2838          * compute_mode_changes (or above), check the actual pfit state and
2839          * whether the platform allows pfit disable with pipe active, and only
2840          * then update the pipesrc and pfit state, even on the flip path.
2841          */
2842
2843         adjusted_mode = &crtc->config.adjusted_mode;
2844
2845         I915_WRITE(PIPESRC(crtc->pipe),
2846                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2847                    (adjusted_mode->crtc_vdisplay - 1));
2848         if (!crtc->config.pch_pfit.enabled &&
2849             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2850              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2851                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2852                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2853                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2854         }
2855         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2856         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2857 }
2858
2859 static int
2860 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2861                     struct drm_framebuffer *fb)
2862 {
2863         struct drm_device *dev = crtc->dev;
2864         struct drm_i915_private *dev_priv = dev->dev_private;
2865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2866         enum pipe pipe = intel_crtc->pipe;
2867         struct drm_framebuffer *old_fb = crtc->primary->fb;
2868         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2869         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2870         int ret;
2871
2872         if (intel_crtc_has_pending_flip(crtc)) {
2873                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2874                 return -EBUSY;
2875         }
2876
2877         /* no fb bound */
2878         if (!fb) {
2879                 DRM_ERROR("No FB bound\n");
2880                 return 0;
2881         }
2882
2883         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2884                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2885                           plane_name(intel_crtc->plane),
2886                           INTEL_INFO(dev)->num_pipes);
2887                 return -EINVAL;
2888         }
2889
2890         mutex_lock(&dev->struct_mutex);
2891         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2892         if (ret == 0)
2893                 i915_gem_track_fb(old_obj, obj,
2894                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2895         mutex_unlock(&dev->struct_mutex);
2896         if (ret != 0) {
2897                 DRM_ERROR("pin & fence failed\n");
2898                 return ret;
2899         }
2900
2901         intel_update_pipe_size(intel_crtc);
2902
2903         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2904
2905         if (intel_crtc->active)
2906                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2907
2908         crtc->primary->fb = fb;
2909         crtc->x = x;
2910         crtc->y = y;
2911
2912         if (old_fb) {
2913                 if (intel_crtc->active && old_fb != fb)
2914                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2915                 mutex_lock(&dev->struct_mutex);
2916                 intel_unpin_fb_obj(old_obj);
2917                 mutex_unlock(&dev->struct_mutex);
2918         }
2919
2920         mutex_lock(&dev->struct_mutex);
2921         intel_update_fbc(dev);
2922         mutex_unlock(&dev->struct_mutex);
2923
2924         return 0;
2925 }
2926
2927 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2928 {
2929         struct drm_device *dev = crtc->dev;
2930         struct drm_i915_private *dev_priv = dev->dev_private;
2931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2932         int pipe = intel_crtc->pipe;
2933         u32 reg, temp;
2934
2935         /* enable normal train */
2936         reg = FDI_TX_CTL(pipe);
2937         temp = I915_READ(reg);
2938         if (IS_IVYBRIDGE(dev)) {
2939                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2940                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2941         } else {
2942                 temp &= ~FDI_LINK_TRAIN_NONE;
2943                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2944         }
2945         I915_WRITE(reg, temp);
2946
2947         reg = FDI_RX_CTL(pipe);
2948         temp = I915_READ(reg);
2949         if (HAS_PCH_CPT(dev)) {
2950                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2951                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2952         } else {
2953                 temp &= ~FDI_LINK_TRAIN_NONE;
2954                 temp |= FDI_LINK_TRAIN_NONE;
2955         }
2956         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2957
2958         /* wait one idle pattern time */
2959         POSTING_READ(reg);
2960         udelay(1000);
2961
2962         /* IVB wants error correction enabled */
2963         if (IS_IVYBRIDGE(dev))
2964                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2965                            FDI_FE_ERRC_ENABLE);
2966 }
2967
2968 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2969 {
2970         return crtc->base.enabled && crtc->active &&
2971                 crtc->config.has_pch_encoder;
2972 }
2973
2974 static void ivb_modeset_global_resources(struct drm_device *dev)
2975 {
2976         struct drm_i915_private *dev_priv = dev->dev_private;
2977         struct intel_crtc *pipe_B_crtc =
2978                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2979         struct intel_crtc *pipe_C_crtc =
2980                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2981         uint32_t temp;
2982
2983         /*
2984          * When everything is off disable fdi C so that we could enable fdi B
2985          * with all lanes. Note that we don't care about enabled pipes without
2986          * an enabled pch encoder.
2987          */
2988         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2989             !pipe_has_enabled_pch(pipe_C_crtc)) {
2990                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2991                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2992
2993                 temp = I915_READ(SOUTH_CHICKEN1);
2994                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2995                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2996                 I915_WRITE(SOUTH_CHICKEN1, temp);
2997         }
2998 }
2999
3000 /* The FDI link training functions for ILK/Ibexpeak. */
3001 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3002 {
3003         struct drm_device *dev = crtc->dev;
3004         struct drm_i915_private *dev_priv = dev->dev_private;
3005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3006         int pipe = intel_crtc->pipe;
3007         u32 reg, temp, tries;
3008
3009         /* FDI needs bits from pipe first */
3010         assert_pipe_enabled(dev_priv, pipe);
3011
3012         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3013            for train result */
3014         reg = FDI_RX_IMR(pipe);
3015         temp = I915_READ(reg);
3016         temp &= ~FDI_RX_SYMBOL_LOCK;
3017         temp &= ~FDI_RX_BIT_LOCK;
3018         I915_WRITE(reg, temp);
3019         I915_READ(reg);
3020         udelay(150);
3021
3022         /* enable CPU FDI TX and PCH FDI RX */
3023         reg = FDI_TX_CTL(pipe);
3024         temp = I915_READ(reg);
3025         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3026         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3027         temp &= ~FDI_LINK_TRAIN_NONE;
3028         temp |= FDI_LINK_TRAIN_PATTERN_1;
3029         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3030
3031         reg = FDI_RX_CTL(pipe);
3032         temp = I915_READ(reg);
3033         temp &= ~FDI_LINK_TRAIN_NONE;
3034         temp |= FDI_LINK_TRAIN_PATTERN_1;
3035         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3036
3037         POSTING_READ(reg);
3038         udelay(150);
3039
3040         /* Ironlake workaround, enable clock pointer after FDI enable*/
3041         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3042         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3043                    FDI_RX_PHASE_SYNC_POINTER_EN);
3044
3045         reg = FDI_RX_IIR(pipe);
3046         for (tries = 0; tries < 5; tries++) {
3047                 temp = I915_READ(reg);
3048                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3049
3050                 if ((temp & FDI_RX_BIT_LOCK)) {
3051                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3052                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3053                         break;
3054                 }
3055         }
3056         if (tries == 5)
3057                 DRM_ERROR("FDI train 1 fail!\n");
3058
3059         /* Train 2 */
3060         reg = FDI_TX_CTL(pipe);
3061         temp = I915_READ(reg);
3062         temp &= ~FDI_LINK_TRAIN_NONE;
3063         temp |= FDI_LINK_TRAIN_PATTERN_2;
3064         I915_WRITE(reg, temp);
3065
3066         reg = FDI_RX_CTL(pipe);
3067         temp = I915_READ(reg);
3068         temp &= ~FDI_LINK_TRAIN_NONE;
3069         temp |= FDI_LINK_TRAIN_PATTERN_2;
3070         I915_WRITE(reg, temp);
3071
3072         POSTING_READ(reg);
3073         udelay(150);
3074
3075         reg = FDI_RX_IIR(pipe);
3076         for (tries = 0; tries < 5; tries++) {
3077                 temp = I915_READ(reg);
3078                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3079
3080                 if (temp & FDI_RX_SYMBOL_LOCK) {
3081                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3082                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3083                         break;
3084                 }
3085         }
3086         if (tries == 5)
3087                 DRM_ERROR("FDI train 2 fail!\n");
3088
3089         DRM_DEBUG_KMS("FDI train done\n");
3090
3091 }
3092
3093 static const int snb_b_fdi_train_param[] = {
3094         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3095         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3096         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3097         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3098 };
3099
3100 /* The FDI link training functions for SNB/Cougarpoint. */
3101 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3102 {
3103         struct drm_device *dev = crtc->dev;
3104         struct drm_i915_private *dev_priv = dev->dev_private;
3105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3106         int pipe = intel_crtc->pipe;
3107         u32 reg, temp, i, retry;
3108
3109         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3110            for train result */
3111         reg = FDI_RX_IMR(pipe);
3112         temp = I915_READ(reg);
3113         temp &= ~FDI_RX_SYMBOL_LOCK;
3114         temp &= ~FDI_RX_BIT_LOCK;
3115         I915_WRITE(reg, temp);
3116
3117         POSTING_READ(reg);
3118         udelay(150);
3119
3120         /* enable CPU FDI TX and PCH FDI RX */
3121         reg = FDI_TX_CTL(pipe);
3122         temp = I915_READ(reg);
3123         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3124         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3125         temp &= ~FDI_LINK_TRAIN_NONE;
3126         temp |= FDI_LINK_TRAIN_PATTERN_1;
3127         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3128         /* SNB-B */
3129         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3130         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3131
3132         I915_WRITE(FDI_RX_MISC(pipe),
3133                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3134
3135         reg = FDI_RX_CTL(pipe);
3136         temp = I915_READ(reg);
3137         if (HAS_PCH_CPT(dev)) {
3138                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3139                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3140         } else {
3141                 temp &= ~FDI_LINK_TRAIN_NONE;
3142                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3143         }
3144         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3145
3146         POSTING_READ(reg);
3147         udelay(150);
3148
3149         for (i = 0; i < 4; i++) {
3150                 reg = FDI_TX_CTL(pipe);
3151                 temp = I915_READ(reg);
3152                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3153                 temp |= snb_b_fdi_train_param[i];
3154                 I915_WRITE(reg, temp);
3155
3156                 POSTING_READ(reg);
3157                 udelay(500);
3158
3159                 for (retry = 0; retry < 5; retry++) {
3160                         reg = FDI_RX_IIR(pipe);
3161                         temp = I915_READ(reg);
3162                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3163                         if (temp & FDI_RX_BIT_LOCK) {
3164                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3165                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3166                                 break;
3167                         }
3168                         udelay(50);
3169                 }
3170                 if (retry < 5)
3171                         break;
3172         }
3173         if (i == 4)
3174                 DRM_ERROR("FDI train 1 fail!\n");
3175
3176         /* Train 2 */
3177         reg = FDI_TX_CTL(pipe);
3178         temp = I915_READ(reg);
3179         temp &= ~FDI_LINK_TRAIN_NONE;
3180         temp |= FDI_LINK_TRAIN_PATTERN_2;
3181         if (IS_GEN6(dev)) {
3182                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3183                 /* SNB-B */
3184                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3185         }
3186         I915_WRITE(reg, temp);
3187
3188         reg = FDI_RX_CTL(pipe);
3189         temp = I915_READ(reg);
3190         if (HAS_PCH_CPT(dev)) {
3191                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3192                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3193         } else {
3194                 temp &= ~FDI_LINK_TRAIN_NONE;
3195                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3196         }
3197         I915_WRITE(reg, temp);
3198
3199         POSTING_READ(reg);
3200         udelay(150);
3201
3202         for (i = 0; i < 4; i++) {
3203                 reg = FDI_TX_CTL(pipe);
3204                 temp = I915_READ(reg);
3205                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3206                 temp |= snb_b_fdi_train_param[i];
3207                 I915_WRITE(reg, temp);
3208
3209                 POSTING_READ(reg);
3210                 udelay(500);
3211
3212                 for (retry = 0; retry < 5; retry++) {
3213                         reg = FDI_RX_IIR(pipe);
3214                         temp = I915_READ(reg);
3215                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3216                         if (temp & FDI_RX_SYMBOL_LOCK) {
3217                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3218                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3219                                 break;
3220                         }
3221                         udelay(50);
3222                 }
3223                 if (retry < 5)
3224                         break;
3225         }
3226         if (i == 4)
3227                 DRM_ERROR("FDI train 2 fail!\n");
3228
3229         DRM_DEBUG_KMS("FDI train done.\n");
3230 }
3231
3232 /* Manual link training for Ivy Bridge A0 parts */
3233 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3234 {
3235         struct drm_device *dev = crtc->dev;
3236         struct drm_i915_private *dev_priv = dev->dev_private;
3237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3238         int pipe = intel_crtc->pipe;
3239         u32 reg, temp, i, j;
3240
3241         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3242            for train result */
3243         reg = FDI_RX_IMR(pipe);
3244         temp = I915_READ(reg);
3245         temp &= ~FDI_RX_SYMBOL_LOCK;
3246         temp &= ~FDI_RX_BIT_LOCK;
3247         I915_WRITE(reg, temp);
3248
3249         POSTING_READ(reg);
3250         udelay(150);
3251
3252         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3253                       I915_READ(FDI_RX_IIR(pipe)));
3254
3255         /* Try each vswing and preemphasis setting twice before moving on */
3256         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3257                 /* disable first in case we need to retry */
3258                 reg = FDI_TX_CTL(pipe);
3259                 temp = I915_READ(reg);
3260                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3261                 temp &= ~FDI_TX_ENABLE;
3262                 I915_WRITE(reg, temp);
3263
3264                 reg = FDI_RX_CTL(pipe);
3265                 temp = I915_READ(reg);
3266                 temp &= ~FDI_LINK_TRAIN_AUTO;
3267                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3268                 temp &= ~FDI_RX_ENABLE;
3269                 I915_WRITE(reg, temp);
3270
3271                 /* enable CPU FDI TX and PCH FDI RX */
3272                 reg = FDI_TX_CTL(pipe);
3273                 temp = I915_READ(reg);
3274                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3275                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3276                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3277                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3278                 temp |= snb_b_fdi_train_param[j/2];
3279                 temp |= FDI_COMPOSITE_SYNC;
3280                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3281
3282                 I915_WRITE(FDI_RX_MISC(pipe),
3283                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3284
3285                 reg = FDI_RX_CTL(pipe);
3286                 temp = I915_READ(reg);
3287                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3288                 temp |= FDI_COMPOSITE_SYNC;
3289                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3290
3291                 POSTING_READ(reg);
3292                 udelay(1); /* should be 0.5us */
3293
3294                 for (i = 0; i < 4; i++) {
3295                         reg = FDI_RX_IIR(pipe);
3296                         temp = I915_READ(reg);
3297                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3298
3299                         if (temp & FDI_RX_BIT_LOCK ||
3300                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3301                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3302                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3303                                               i);
3304                                 break;
3305                         }
3306                         udelay(1); /* should be 0.5us */
3307                 }
3308                 if (i == 4) {
3309                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3310                         continue;
3311                 }
3312
3313                 /* Train 2 */
3314                 reg = FDI_TX_CTL(pipe);
3315                 temp = I915_READ(reg);
3316                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3317                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3318                 I915_WRITE(reg, temp);
3319
3320                 reg = FDI_RX_CTL(pipe);
3321                 temp = I915_READ(reg);
3322                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3323                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3324                 I915_WRITE(reg, temp);
3325
3326                 POSTING_READ(reg);
3327                 udelay(2); /* should be 1.5us */
3328
3329                 for (i = 0; i < 4; i++) {
3330                         reg = FDI_RX_IIR(pipe);
3331                         temp = I915_READ(reg);
3332                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3333
3334                         if (temp & FDI_RX_SYMBOL_LOCK ||
3335                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3336                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3337                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3338                                               i);
3339                                 goto train_done;
3340                         }
3341                         udelay(2); /* should be 1.5us */
3342                 }
3343                 if (i == 4)
3344                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3345         }
3346
3347 train_done:
3348         DRM_DEBUG_KMS("FDI train done.\n");
3349 }
3350
3351 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3352 {
3353         struct drm_device *dev = intel_crtc->base.dev;
3354         struct drm_i915_private *dev_priv = dev->dev_private;
3355         int pipe = intel_crtc->pipe;
3356         u32 reg, temp;
3357
3358
3359         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3360         reg = FDI_RX_CTL(pipe);
3361         temp = I915_READ(reg);
3362         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3363         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3364         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3365         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3366
3367         POSTING_READ(reg);
3368         udelay(200);
3369
3370         /* Switch from Rawclk to PCDclk */
3371         temp = I915_READ(reg);
3372         I915_WRITE(reg, temp | FDI_PCDCLK);
3373
3374         POSTING_READ(reg);
3375         udelay(200);
3376
3377         /* Enable CPU FDI TX PLL, always on for Ironlake */
3378         reg = FDI_TX_CTL(pipe);
3379         temp = I915_READ(reg);
3380         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3381                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3382
3383                 POSTING_READ(reg);
3384                 udelay(100);
3385         }
3386 }
3387
3388 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3389 {
3390         struct drm_device *dev = intel_crtc->base.dev;
3391         struct drm_i915_private *dev_priv = dev->dev_private;
3392         int pipe = intel_crtc->pipe;
3393         u32 reg, temp;
3394
3395         /* Switch from PCDclk to Rawclk */
3396         reg = FDI_RX_CTL(pipe);
3397         temp = I915_READ(reg);
3398         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3399
3400         /* Disable CPU FDI TX PLL */
3401         reg = FDI_TX_CTL(pipe);
3402         temp = I915_READ(reg);
3403         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3404
3405         POSTING_READ(reg);
3406         udelay(100);
3407
3408         reg = FDI_RX_CTL(pipe);
3409         temp = I915_READ(reg);
3410         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3411
3412         /* Wait for the clocks to turn off. */
3413         POSTING_READ(reg);
3414         udelay(100);
3415 }
3416
3417 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3418 {
3419         struct drm_device *dev = crtc->dev;
3420         struct drm_i915_private *dev_priv = dev->dev_private;
3421         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3422         int pipe = intel_crtc->pipe;
3423         u32 reg, temp;
3424
3425         /* disable CPU FDI tx and PCH FDI rx */
3426         reg = FDI_TX_CTL(pipe);
3427         temp = I915_READ(reg);
3428         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3429         POSTING_READ(reg);
3430
3431         reg = FDI_RX_CTL(pipe);
3432         temp = I915_READ(reg);
3433         temp &= ~(0x7 << 16);
3434         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3435         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3436
3437         POSTING_READ(reg);
3438         udelay(100);
3439
3440         /* Ironlake workaround, disable clock pointer after downing FDI */
3441         if (HAS_PCH_IBX(dev))
3442                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3443
3444         /* still set train pattern 1 */
3445         reg = FDI_TX_CTL(pipe);
3446         temp = I915_READ(reg);
3447         temp &= ~FDI_LINK_TRAIN_NONE;
3448         temp |= FDI_LINK_TRAIN_PATTERN_1;
3449         I915_WRITE(reg, temp);
3450
3451         reg = FDI_RX_CTL(pipe);
3452         temp = I915_READ(reg);
3453         if (HAS_PCH_CPT(dev)) {
3454                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3455                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3456         } else {
3457                 temp &= ~FDI_LINK_TRAIN_NONE;
3458                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3459         }
3460         /* BPC in FDI rx is consistent with that in PIPECONF */
3461         temp &= ~(0x07 << 16);
3462         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3463         I915_WRITE(reg, temp);
3464
3465         POSTING_READ(reg);
3466         udelay(100);
3467 }
3468
3469 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3470 {
3471         struct intel_crtc *crtc;
3472
3473         /* Note that we don't need to be called with mode_config.lock here
3474          * as our list of CRTC objects is static for the lifetime of the
3475          * device and so cannot disappear as we iterate. Similarly, we can
3476          * happily treat the predicates as racy, atomic checks as userspace
3477          * cannot claim and pin a new fb without at least acquring the
3478          * struct_mutex and so serialising with us.
3479          */
3480         for_each_intel_crtc(dev, crtc) {
3481                 if (atomic_read(&crtc->unpin_work_count) == 0)
3482                         continue;
3483
3484                 if (crtc->unpin_work)
3485                         intel_wait_for_vblank(dev, crtc->pipe);
3486
3487                 return true;
3488         }
3489
3490         return false;
3491 }
3492
3493 static void page_flip_completed(struct intel_crtc *intel_crtc)
3494 {
3495         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3496         struct intel_unpin_work *work = intel_crtc->unpin_work;
3497
3498         /* ensure that the unpin work is consistent wrt ->pending. */
3499         smp_rmb();
3500         intel_crtc->unpin_work = NULL;
3501
3502         if (work->event)
3503                 drm_send_vblank_event(intel_crtc->base.dev,
3504                                       intel_crtc->pipe,
3505                                       work->event);
3506
3507         drm_crtc_vblank_put(&intel_crtc->base);
3508
3509         wake_up_all(&dev_priv->pending_flip_queue);
3510         queue_work(dev_priv->wq, &work->work);
3511
3512         trace_i915_flip_complete(intel_crtc->plane,
3513                                  work->pending_flip_obj);
3514 }
3515
3516 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3517 {
3518         struct drm_device *dev = crtc->dev;
3519         struct drm_i915_private *dev_priv = dev->dev_private;
3520
3521         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3522         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3523                                        !intel_crtc_has_pending_flip(crtc),
3524                                        60*HZ) == 0)) {
3525                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3526
3527                 spin_lock_irq(&dev->event_lock);
3528                 if (intel_crtc->unpin_work) {
3529                         WARN_ONCE(1, "Removing stuck page flip\n");
3530                         page_flip_completed(intel_crtc);
3531                 }
3532                 spin_unlock_irq(&dev->event_lock);
3533         }
3534
3535         if (crtc->primary->fb) {
3536                 mutex_lock(&dev->struct_mutex);
3537                 intel_finish_fb(crtc->primary->fb);
3538                 mutex_unlock(&dev->struct_mutex);
3539         }
3540 }
3541
3542 /* Program iCLKIP clock to the desired frequency */
3543 static void lpt_program_iclkip(struct drm_crtc *crtc)
3544 {
3545         struct drm_device *dev = crtc->dev;
3546         struct drm_i915_private *dev_priv = dev->dev_private;
3547         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3548         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3549         u32 temp;
3550
3551         mutex_lock(&dev_priv->dpio_lock);
3552
3553         /* It is necessary to ungate the pixclk gate prior to programming
3554          * the divisors, and gate it back when it is done.
3555          */
3556         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3557
3558         /* Disable SSCCTL */
3559         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3560                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3561                                 SBI_SSCCTL_DISABLE,
3562                         SBI_ICLK);
3563
3564         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3565         if (clock == 20000) {
3566                 auxdiv = 1;
3567                 divsel = 0x41;
3568                 phaseinc = 0x20;
3569         } else {
3570                 /* The iCLK virtual clock root frequency is in MHz,
3571                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3572                  * divisors, it is necessary to divide one by another, so we
3573                  * convert the virtual clock precision to KHz here for higher
3574                  * precision.
3575                  */
3576                 u32 iclk_virtual_root_freq = 172800 * 1000;
3577                 u32 iclk_pi_range = 64;
3578                 u32 desired_divisor, msb_divisor_value, pi_value;
3579
3580                 desired_divisor = (iclk_virtual_root_freq / clock);
3581                 msb_divisor_value = desired_divisor / iclk_pi_range;
3582                 pi_value = desired_divisor % iclk_pi_range;
3583
3584                 auxdiv = 0;
3585                 divsel = msb_divisor_value - 2;
3586                 phaseinc = pi_value;
3587         }
3588
3589         /* This should not happen with any sane values */
3590         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3591                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3592         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3593                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3594
3595         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3596                         clock,
3597                         auxdiv,
3598                         divsel,
3599                         phasedir,
3600                         phaseinc);
3601
3602         /* Program SSCDIVINTPHASE6 */
3603         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3604         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3605         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3606         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3607         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3608         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3609         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3610         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3611
3612         /* Program SSCAUXDIV */
3613         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3614         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3615         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3616         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3617
3618         /* Enable modulator and associated divider */
3619         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3620         temp &= ~SBI_SSCCTL_DISABLE;
3621         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3622
3623         /* Wait for initialization time */
3624         udelay(24);
3625
3626         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3627
3628         mutex_unlock(&dev_priv->dpio_lock);
3629 }
3630
3631 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3632                                                 enum pipe pch_transcoder)
3633 {
3634         struct drm_device *dev = crtc->base.dev;
3635         struct drm_i915_private *dev_priv = dev->dev_private;
3636         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3637
3638         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3639                    I915_READ(HTOTAL(cpu_transcoder)));
3640         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3641                    I915_READ(HBLANK(cpu_transcoder)));
3642         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3643                    I915_READ(HSYNC(cpu_transcoder)));
3644
3645         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3646                    I915_READ(VTOTAL(cpu_transcoder)));
3647         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3648                    I915_READ(VBLANK(cpu_transcoder)));
3649         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3650                    I915_READ(VSYNC(cpu_transcoder)));
3651         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3652                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3653 }
3654
3655 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3656 {
3657         struct drm_i915_private *dev_priv = dev->dev_private;
3658         uint32_t temp;
3659
3660         temp = I915_READ(SOUTH_CHICKEN1);
3661         if (temp & FDI_BC_BIFURCATION_SELECT)
3662                 return;
3663
3664         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3665         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3666
3667         temp |= FDI_BC_BIFURCATION_SELECT;
3668         DRM_DEBUG_KMS("enabling fdi C rx\n");
3669         I915_WRITE(SOUTH_CHICKEN1, temp);
3670         POSTING_READ(SOUTH_CHICKEN1);
3671 }
3672
3673 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3674 {
3675         struct drm_device *dev = intel_crtc->base.dev;
3676         struct drm_i915_private *dev_priv = dev->dev_private;
3677
3678         switch (intel_crtc->pipe) {
3679         case PIPE_A:
3680                 break;
3681         case PIPE_B:
3682                 if (intel_crtc->config.fdi_lanes > 2)
3683                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3684                 else
3685                         cpt_enable_fdi_bc_bifurcation(dev);
3686
3687                 break;
3688         case PIPE_C:
3689                 cpt_enable_fdi_bc_bifurcation(dev);
3690
3691                 break;
3692         default:
3693                 BUG();
3694         }
3695 }
3696
3697 /*
3698  * Enable PCH resources required for PCH ports:
3699  *   - PCH PLLs
3700  *   - FDI training & RX/TX
3701  *   - update transcoder timings
3702  *   - DP transcoding bits
3703  *   - transcoder
3704  */
3705 static void ironlake_pch_enable(struct drm_crtc *crtc)
3706 {
3707         struct drm_device *dev = crtc->dev;
3708         struct drm_i915_private *dev_priv = dev->dev_private;
3709         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3710         int pipe = intel_crtc->pipe;
3711         u32 reg, temp;
3712
3713         assert_pch_transcoder_disabled(dev_priv, pipe);
3714
3715         if (IS_IVYBRIDGE(dev))
3716                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3717
3718         /* Write the TU size bits before fdi link training, so that error
3719          * detection works. */
3720         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3721                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3722
3723         /* For PCH output, training FDI link */
3724         dev_priv->display.fdi_link_train(crtc);
3725
3726         /* We need to program the right clock selection before writing the pixel
3727          * mutliplier into the DPLL. */
3728         if (HAS_PCH_CPT(dev)) {
3729                 u32 sel;
3730
3731                 temp = I915_READ(PCH_DPLL_SEL);
3732                 temp |= TRANS_DPLL_ENABLE(pipe);
3733                 sel = TRANS_DPLLB_SEL(pipe);
3734                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3735                         temp |= sel;
3736                 else
3737                         temp &= ~sel;
3738                 I915_WRITE(PCH_DPLL_SEL, temp);
3739         }
3740
3741         /* XXX: pch pll's can be enabled any time before we enable the PCH
3742          * transcoder, and we actually should do this to not upset any PCH
3743          * transcoder that already use the clock when we share it.
3744          *
3745          * Note that enable_shared_dpll tries to do the right thing, but
3746          * get_shared_dpll unconditionally resets the pll - we need that to have
3747          * the right LVDS enable sequence. */
3748         intel_enable_shared_dpll(intel_crtc);
3749
3750         /* set transcoder timing, panel must allow it */
3751         assert_panel_unlocked(dev_priv, pipe);
3752         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3753
3754         intel_fdi_normal_train(crtc);
3755
3756         /* For PCH DP, enable TRANS_DP_CTL */
3757         if (HAS_PCH_CPT(dev) &&
3758             (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3759              intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_EDP))) {
3760                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3761                 reg = TRANS_DP_CTL(pipe);
3762                 temp = I915_READ(reg);
3763                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3764                           TRANS_DP_SYNC_MASK |
3765                           TRANS_DP_BPC_MASK);
3766                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3767                          TRANS_DP_ENH_FRAMING);
3768                 temp |= bpc << 9; /* same format but at 11:9 */
3769
3770                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3771                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3772                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3773                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3774
3775                 switch (intel_trans_dp_port_sel(crtc)) {
3776                 case PCH_DP_B:
3777                         temp |= TRANS_DP_PORT_SEL_B;
3778                         break;
3779                 case PCH_DP_C:
3780                         temp |= TRANS_DP_PORT_SEL_C;
3781                         break;
3782                 case PCH_DP_D:
3783                         temp |= TRANS_DP_PORT_SEL_D;
3784                         break;
3785                 default:
3786                         BUG();
3787                 }
3788
3789                 I915_WRITE(reg, temp);
3790         }
3791
3792         ironlake_enable_pch_transcoder(dev_priv, pipe);
3793 }
3794
3795 static void lpt_pch_enable(struct drm_crtc *crtc)
3796 {
3797         struct drm_device *dev = crtc->dev;
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3800         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3801
3802         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3803
3804         lpt_program_iclkip(crtc);
3805
3806         /* Set transcoder timing. */
3807         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3808
3809         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3810 }
3811
3812 void intel_put_shared_dpll(struct intel_crtc *crtc)
3813 {
3814         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3815
3816         if (pll == NULL)
3817                 return;
3818
3819         if (pll->refcount == 0) {
3820                 WARN(1, "bad %s refcount\n", pll->name);
3821                 return;
3822         }
3823
3824         if (--pll->refcount == 0) {
3825                 WARN_ON(pll->on);
3826                 WARN_ON(pll->active);
3827         }
3828
3829         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3830 }
3831
3832 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3833 {
3834         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3835         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3836         enum intel_dpll_id i;
3837
3838         if (pll) {
3839                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3840                               crtc->base.base.id, pll->name);
3841                 intel_put_shared_dpll(crtc);
3842         }
3843
3844         if (HAS_PCH_IBX(dev_priv->dev)) {
3845                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3846                 i = (enum intel_dpll_id) crtc->pipe;
3847                 pll = &dev_priv->shared_dplls[i];
3848
3849                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3850                               crtc->base.base.id, pll->name);
3851
3852                 WARN_ON(pll->refcount);
3853
3854                 goto found;
3855         }
3856
3857         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3858                 pll = &dev_priv->shared_dplls[i];
3859
3860                 /* Only want to check enabled timings first */
3861                 if (pll->refcount == 0)
3862                         continue;
3863
3864                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3865                            sizeof(pll->hw_state)) == 0) {
3866                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3867                                       crtc->base.base.id,
3868                                       pll->name, pll->refcount, pll->active);
3869
3870                         goto found;
3871                 }
3872         }
3873
3874         /* Ok no matching timings, maybe there's a free one? */
3875         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3876                 pll = &dev_priv->shared_dplls[i];
3877                 if (pll->refcount == 0) {
3878                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3879                                       crtc->base.base.id, pll->name);
3880                         goto found;
3881                 }
3882         }
3883
3884         return NULL;
3885
3886 found:
3887         if (pll->refcount == 0)
3888                 pll->hw_state = crtc->config.dpll_hw_state;
3889
3890         crtc->config.shared_dpll = i;
3891         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3892                          pipe_name(crtc->pipe));
3893
3894         pll->refcount++;
3895
3896         return pll;
3897 }
3898
3899 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3900 {
3901         struct drm_i915_private *dev_priv = dev->dev_private;
3902         int dslreg = PIPEDSL(pipe);
3903         u32 temp;
3904
3905         temp = I915_READ(dslreg);
3906         udelay(500);
3907         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3908                 if (wait_for(I915_READ(dslreg) != temp, 5))
3909                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3910         }
3911 }
3912
3913 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3914 {
3915         struct drm_device *dev = crtc->base.dev;
3916         struct drm_i915_private *dev_priv = dev->dev_private;
3917         int pipe = crtc->pipe;
3918
3919         if (crtc->config.pch_pfit.enabled) {
3920                 /* Force use of hard-coded filter coefficients
3921                  * as some pre-programmed values are broken,
3922                  * e.g. x201.
3923                  */
3924                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3925                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3926                                                  PF_PIPE_SEL_IVB(pipe));
3927                 else
3928                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3929                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3930                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3931         }
3932 }
3933
3934 static void intel_enable_planes(struct drm_crtc *crtc)
3935 {
3936         struct drm_device *dev = crtc->dev;
3937         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3938         struct drm_plane *plane;
3939         struct intel_plane *intel_plane;
3940
3941         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3942                 intel_plane = to_intel_plane(plane);
3943                 if (intel_plane->pipe == pipe)
3944                         intel_plane_restore(&intel_plane->base);
3945         }
3946 }
3947
3948 static void intel_disable_planes(struct drm_crtc *crtc)
3949 {
3950         struct drm_device *dev = crtc->dev;
3951         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3952         struct drm_plane *plane;
3953         struct intel_plane *intel_plane;
3954
3955         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3956                 intel_plane = to_intel_plane(plane);
3957                 if (intel_plane->pipe == pipe)
3958                         intel_plane_disable(&intel_plane->base);
3959         }
3960 }
3961
3962 void hsw_enable_ips(struct intel_crtc *crtc)
3963 {
3964         struct drm_device *dev = crtc->base.dev;
3965         struct drm_i915_private *dev_priv = dev->dev_private;
3966
3967         if (!crtc->config.ips_enabled)
3968                 return;
3969
3970         /* We can only enable IPS after we enable a plane and wait for a vblank */
3971         intel_wait_for_vblank(dev, crtc->pipe);
3972
3973         assert_plane_enabled(dev_priv, crtc->plane);
3974         if (IS_BROADWELL(dev)) {
3975                 mutex_lock(&dev_priv->rps.hw_lock);
3976                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3977                 mutex_unlock(&dev_priv->rps.hw_lock);
3978                 /* Quoting Art Runyan: "its not safe to expect any particular
3979                  * value in IPS_CTL bit 31 after enabling IPS through the
3980                  * mailbox." Moreover, the mailbox may return a bogus state,
3981                  * so we need to just enable it and continue on.
3982                  */
3983         } else {
3984                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3985                 /* The bit only becomes 1 in the next vblank, so this wait here
3986                  * is essentially intel_wait_for_vblank. If we don't have this
3987                  * and don't wait for vblanks until the end of crtc_enable, then
3988                  * the HW state readout code will complain that the expected
3989                  * IPS_CTL value is not the one we read. */
3990                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3991                         DRM_ERROR("Timed out waiting for IPS enable\n");
3992         }
3993 }
3994
3995 void hsw_disable_ips(struct intel_crtc *crtc)
3996 {
3997         struct drm_device *dev = crtc->base.dev;
3998         struct drm_i915_private *dev_priv = dev->dev_private;
3999
4000         if (!crtc->config.ips_enabled)
4001                 return;
4002
4003         assert_plane_enabled(dev_priv, crtc->plane);
4004         if (IS_BROADWELL(dev)) {
4005                 mutex_lock(&dev_priv->rps.hw_lock);
4006                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4007                 mutex_unlock(&dev_priv->rps.hw_lock);
4008                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4009                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4010                         DRM_ERROR("Timed out waiting for IPS disable\n");
4011         } else {
4012                 I915_WRITE(IPS_CTL, 0);
4013                 POSTING_READ(IPS_CTL);
4014         }
4015
4016         /* We need to wait for a vblank before we can disable the plane. */
4017         intel_wait_for_vblank(dev, crtc->pipe);
4018 }
4019
4020 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4021 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4022 {
4023         struct drm_device *dev = crtc->dev;
4024         struct drm_i915_private *dev_priv = dev->dev_private;
4025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4026         enum pipe pipe = intel_crtc->pipe;
4027         int palreg = PALETTE(pipe);
4028         int i;
4029         bool reenable_ips = false;
4030
4031         /* The clocks have to be on to load the palette. */
4032         if (!crtc->enabled || !intel_crtc->active)
4033                 return;
4034
4035         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4036                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4037                         assert_dsi_pll_enabled(dev_priv);
4038                 else
4039                         assert_pll_enabled(dev_priv, pipe);
4040         }
4041
4042         /* use legacy palette for Ironlake */
4043         if (!HAS_GMCH_DISPLAY(dev))
4044                 palreg = LGC_PALETTE(pipe);
4045
4046         /* Workaround : Do not read or write the pipe palette/gamma data while
4047          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4048          */
4049         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4050             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4051              GAMMA_MODE_MODE_SPLIT)) {
4052                 hsw_disable_ips(intel_crtc);
4053                 reenable_ips = true;
4054         }
4055
4056         for (i = 0; i < 256; i++) {
4057                 I915_WRITE(palreg + 4 * i,
4058                            (intel_crtc->lut_r[i] << 16) |
4059                            (intel_crtc->lut_g[i] << 8) |
4060                            intel_crtc->lut_b[i]);
4061         }
4062
4063         if (reenable_ips)
4064                 hsw_enable_ips(intel_crtc);
4065 }
4066
4067 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4068 {
4069         if (!enable && intel_crtc->overlay) {
4070                 struct drm_device *dev = intel_crtc->base.dev;
4071                 struct drm_i915_private *dev_priv = dev->dev_private;
4072
4073                 mutex_lock(&dev->struct_mutex);
4074                 dev_priv->mm.interruptible = false;
4075                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4076                 dev_priv->mm.interruptible = true;
4077                 mutex_unlock(&dev->struct_mutex);
4078         }
4079
4080         /* Let userspace switch the overlay on again. In most cases userspace
4081          * has to recompute where to put it anyway.
4082          */
4083 }
4084
4085 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4086 {
4087         struct drm_device *dev = crtc->dev;
4088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4089         int pipe = intel_crtc->pipe;
4090
4091         intel_enable_primary_hw_plane(crtc->primary, crtc);
4092         intel_enable_planes(crtc);
4093         intel_crtc_update_cursor(crtc, true);
4094         intel_crtc_dpms_overlay(intel_crtc, true);
4095
4096         hsw_enable_ips(intel_crtc);
4097
4098         mutex_lock(&dev->struct_mutex);
4099         intel_update_fbc(dev);
4100         mutex_unlock(&dev->struct_mutex);
4101
4102         /*
4103          * FIXME: Once we grow proper nuclear flip support out of this we need
4104          * to compute the mask of flip planes precisely. For the time being
4105          * consider this a flip from a NULL plane.
4106          */
4107         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4108 }
4109
4110 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4111 {
4112         struct drm_device *dev = crtc->dev;
4113         struct drm_i915_private *dev_priv = dev->dev_private;
4114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4115         int pipe = intel_crtc->pipe;
4116         int plane = intel_crtc->plane;
4117
4118         intel_crtc_wait_for_pending_flips(crtc);
4119
4120         if (dev_priv->fbc.plane == plane)
4121                 intel_disable_fbc(dev);
4122
4123         hsw_disable_ips(intel_crtc);
4124
4125         intel_crtc_dpms_overlay(intel_crtc, false);
4126         intel_crtc_update_cursor(crtc, false);
4127         intel_disable_planes(crtc);
4128         intel_disable_primary_hw_plane(crtc->primary, crtc);
4129
4130         /*
4131          * FIXME: Once we grow proper nuclear flip support out of this we need
4132          * to compute the mask of flip planes precisely. For the time being
4133          * consider this a flip to a NULL plane.
4134          */
4135         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4136 }
4137
4138 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4139 {
4140         struct drm_device *dev = crtc->dev;
4141         struct drm_i915_private *dev_priv = dev->dev_private;
4142         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4143         struct intel_encoder *encoder;
4144         int pipe = intel_crtc->pipe;
4145
4146         WARN_ON(!crtc->enabled);
4147
4148         if (intel_crtc->active)
4149                 return;
4150
4151         if (intel_crtc->config.has_pch_encoder)
4152                 intel_prepare_shared_dpll(intel_crtc);
4153
4154         if (intel_crtc->config.has_dp_encoder)
4155                 intel_dp_set_m_n(intel_crtc);
4156
4157         intel_set_pipe_timings(intel_crtc);
4158
4159         if (intel_crtc->config.has_pch_encoder) {
4160                 intel_cpu_transcoder_set_m_n(intel_crtc,
4161                                      &intel_crtc->config.fdi_m_n, NULL);
4162         }
4163
4164         ironlake_set_pipeconf(crtc);
4165
4166         intel_crtc->active = true;
4167
4168         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4169         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4170
4171         for_each_encoder_on_crtc(dev, crtc, encoder)
4172                 if (encoder->pre_enable)
4173                         encoder->pre_enable(encoder);
4174
4175         if (intel_crtc->config.has_pch_encoder) {
4176                 /* Note: FDI PLL enabling _must_ be done before we enable the
4177                  * cpu pipes, hence this is separate from all the other fdi/pch
4178                  * enabling. */
4179                 ironlake_fdi_pll_enable(intel_crtc);
4180         } else {
4181                 assert_fdi_tx_disabled(dev_priv, pipe);
4182                 assert_fdi_rx_disabled(dev_priv, pipe);
4183         }
4184
4185         ironlake_pfit_enable(intel_crtc);
4186
4187         /*
4188          * On ILK+ LUT must be loaded before the pipe is running but with
4189          * clocks enabled
4190          */
4191         intel_crtc_load_lut(crtc);
4192
4193         intel_update_watermarks(crtc);
4194         intel_enable_pipe(intel_crtc);
4195
4196         if (intel_crtc->config.has_pch_encoder)
4197                 ironlake_pch_enable(crtc);
4198
4199         for_each_encoder_on_crtc(dev, crtc, encoder)
4200                 encoder->enable(encoder);
4201
4202         if (HAS_PCH_CPT(dev))
4203                 cpt_verify_modeset(dev, intel_crtc->pipe);
4204
4205         assert_vblank_disabled(crtc);
4206         drm_crtc_vblank_on(crtc);
4207
4208         intel_crtc_enable_planes(crtc);
4209 }
4210
4211 /* IPS only exists on ULT machines and is tied to pipe A. */
4212 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4213 {
4214         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4215 }
4216
4217 /*
4218  * This implements the workaround described in the "notes" section of the mode
4219  * set sequence documentation. When going from no pipes or single pipe to
4220  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4221  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4222  */
4223 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4224 {
4225         struct drm_device *dev = crtc->base.dev;
4226         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4227
4228         /* We want to get the other_active_crtc only if there's only 1 other
4229          * active crtc. */
4230         for_each_intel_crtc(dev, crtc_it) {
4231                 if (!crtc_it->active || crtc_it == crtc)
4232                         continue;
4233
4234                 if (other_active_crtc)
4235                         return;
4236
4237                 other_active_crtc = crtc_it;
4238         }
4239         if (!other_active_crtc)
4240                 return;
4241
4242         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4243         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4244 }
4245
4246 static void haswell_crtc_enable(struct drm_crtc *crtc)
4247 {
4248         struct drm_device *dev = crtc->dev;
4249         struct drm_i915_private *dev_priv = dev->dev_private;
4250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4251         struct intel_encoder *encoder;
4252         int pipe = intel_crtc->pipe;
4253
4254         WARN_ON(!crtc->enabled);
4255
4256         if (intel_crtc->active)
4257                 return;
4258
4259         if (intel_crtc_to_shared_dpll(intel_crtc))
4260                 intel_enable_shared_dpll(intel_crtc);
4261
4262         if (intel_crtc->config.has_dp_encoder)
4263                 intel_dp_set_m_n(intel_crtc);
4264
4265         intel_set_pipe_timings(intel_crtc);
4266
4267         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4268                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4269                            intel_crtc->config.pixel_multiplier - 1);
4270         }
4271
4272         if (intel_crtc->config.has_pch_encoder) {
4273                 intel_cpu_transcoder_set_m_n(intel_crtc,
4274                                      &intel_crtc->config.fdi_m_n, NULL);
4275         }
4276
4277         haswell_set_pipeconf(crtc);
4278
4279         intel_set_pipe_csc(crtc);
4280
4281         intel_crtc->active = true;
4282
4283         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4284         for_each_encoder_on_crtc(dev, crtc, encoder)
4285                 if (encoder->pre_enable)
4286                         encoder->pre_enable(encoder);
4287
4288         if (intel_crtc->config.has_pch_encoder) {
4289                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4290                                                       true);
4291                 dev_priv->display.fdi_link_train(crtc);
4292         }
4293
4294         intel_ddi_enable_pipe_clock(intel_crtc);
4295
4296         ironlake_pfit_enable(intel_crtc);
4297
4298         /*
4299          * On ILK+ LUT must be loaded before the pipe is running but with
4300          * clocks enabled
4301          */
4302         intel_crtc_load_lut(crtc);
4303
4304         intel_ddi_set_pipe_settings(crtc);
4305         intel_ddi_enable_transcoder_func(crtc);
4306
4307         intel_update_watermarks(crtc);
4308         intel_enable_pipe(intel_crtc);
4309
4310         if (intel_crtc->config.has_pch_encoder)
4311                 lpt_pch_enable(crtc);
4312
4313         if (intel_crtc->config.dp_encoder_is_mst)
4314                 intel_ddi_set_vc_payload_alloc(crtc, true);
4315
4316         for_each_encoder_on_crtc(dev, crtc, encoder) {
4317                 encoder->enable(encoder);
4318                 intel_opregion_notify_encoder(encoder, true);
4319         }
4320
4321         assert_vblank_disabled(crtc);
4322         drm_crtc_vblank_on(crtc);
4323
4324         /* If we change the relative order between pipe/planes enabling, we need
4325          * to change the workaround. */
4326         haswell_mode_set_planes_workaround(intel_crtc);
4327         intel_crtc_enable_planes(crtc);
4328 }
4329
4330 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4331 {
4332         struct drm_device *dev = crtc->base.dev;
4333         struct drm_i915_private *dev_priv = dev->dev_private;
4334         int pipe = crtc->pipe;
4335
4336         /* To avoid upsetting the power well on haswell only disable the pfit if
4337          * it's in use. The hw state code will make sure we get this right. */
4338         if (crtc->config.pch_pfit.enabled) {
4339                 I915_WRITE(PF_CTL(pipe), 0);
4340                 I915_WRITE(PF_WIN_POS(pipe), 0);
4341                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4342         }
4343 }
4344
4345 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4346 {
4347         struct drm_device *dev = crtc->dev;
4348         struct drm_i915_private *dev_priv = dev->dev_private;
4349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4350         struct intel_encoder *encoder;
4351         int pipe = intel_crtc->pipe;
4352         u32 reg, temp;
4353
4354         if (!intel_crtc->active)
4355                 return;
4356
4357         intel_crtc_disable_planes(crtc);
4358
4359         drm_crtc_vblank_off(crtc);
4360         assert_vblank_disabled(crtc);
4361
4362         for_each_encoder_on_crtc(dev, crtc, encoder)
4363                 encoder->disable(encoder);
4364
4365         if (intel_crtc->config.has_pch_encoder)
4366                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4367
4368         intel_disable_pipe(intel_crtc);
4369
4370         ironlake_pfit_disable(intel_crtc);
4371
4372         for_each_encoder_on_crtc(dev, crtc, encoder)
4373                 if (encoder->post_disable)
4374                         encoder->post_disable(encoder);
4375
4376         if (intel_crtc->config.has_pch_encoder) {
4377                 ironlake_fdi_disable(crtc);
4378
4379                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4380                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4381
4382                 if (HAS_PCH_CPT(dev)) {
4383                         /* disable TRANS_DP_CTL */
4384                         reg = TRANS_DP_CTL(pipe);
4385                         temp = I915_READ(reg);
4386                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4387                                   TRANS_DP_PORT_SEL_MASK);
4388                         temp |= TRANS_DP_PORT_SEL_NONE;
4389                         I915_WRITE(reg, temp);
4390
4391                         /* disable DPLL_SEL */
4392                         temp = I915_READ(PCH_DPLL_SEL);
4393                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4394                         I915_WRITE(PCH_DPLL_SEL, temp);
4395                 }
4396
4397                 /* disable PCH DPLL */
4398                 intel_disable_shared_dpll(intel_crtc);
4399
4400                 ironlake_fdi_pll_disable(intel_crtc);
4401         }
4402
4403         intel_crtc->active = false;
4404         intel_update_watermarks(crtc);
4405
4406         mutex_lock(&dev->struct_mutex);
4407         intel_update_fbc(dev);
4408         mutex_unlock(&dev->struct_mutex);
4409 }
4410
4411 static void haswell_crtc_disable(struct drm_crtc *crtc)
4412 {
4413         struct drm_device *dev = crtc->dev;
4414         struct drm_i915_private *dev_priv = dev->dev_private;
4415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4416         struct intel_encoder *encoder;
4417         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4418
4419         if (!intel_crtc->active)
4420                 return;
4421
4422         intel_crtc_disable_planes(crtc);
4423
4424         drm_crtc_vblank_off(crtc);
4425         assert_vblank_disabled(crtc);
4426
4427         for_each_encoder_on_crtc(dev, crtc, encoder) {
4428                 intel_opregion_notify_encoder(encoder, false);
4429                 encoder->disable(encoder);
4430         }
4431
4432         if (intel_crtc->config.has_pch_encoder)
4433                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4434                                                       false);
4435         intel_disable_pipe(intel_crtc);
4436
4437         if (intel_crtc->config.dp_encoder_is_mst)
4438                 intel_ddi_set_vc_payload_alloc(crtc, false);
4439
4440         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4441
4442         ironlake_pfit_disable(intel_crtc);
4443
4444         intel_ddi_disable_pipe_clock(intel_crtc);
4445
4446         if (intel_crtc->config.has_pch_encoder) {
4447                 lpt_disable_pch_transcoder(dev_priv);
4448                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4449                                                       true);
4450                 intel_ddi_fdi_disable(crtc);
4451         }
4452
4453         for_each_encoder_on_crtc(dev, crtc, encoder)
4454                 if (encoder->post_disable)
4455                         encoder->post_disable(encoder);
4456
4457         intel_crtc->active = false;
4458         intel_update_watermarks(crtc);
4459
4460         mutex_lock(&dev->struct_mutex);
4461         intel_update_fbc(dev);
4462         mutex_unlock(&dev->struct_mutex);
4463
4464         if (intel_crtc_to_shared_dpll(intel_crtc))
4465                 intel_disable_shared_dpll(intel_crtc);
4466 }
4467
4468 static void ironlake_crtc_off(struct drm_crtc *crtc)
4469 {
4470         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4471         intel_put_shared_dpll(intel_crtc);
4472 }
4473
4474
4475 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4476 {
4477         struct drm_device *dev = crtc->base.dev;
4478         struct drm_i915_private *dev_priv = dev->dev_private;
4479         struct intel_crtc_config *pipe_config = &crtc->config;
4480
4481         if (!crtc->config.gmch_pfit.control)
4482                 return;
4483
4484         /*
4485          * The panel fitter should only be adjusted whilst the pipe is disabled,
4486          * according to register description and PRM.
4487          */
4488         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4489         assert_pipe_disabled(dev_priv, crtc->pipe);
4490
4491         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4492         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4493
4494         /* Border color in case we don't scale up to the full screen. Black by
4495          * default, change to something else for debugging. */
4496         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4497 }
4498
4499 static enum intel_display_power_domain port_to_power_domain(enum port port)
4500 {
4501         switch (port) {
4502         case PORT_A:
4503                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4504         case PORT_B:
4505                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4506         case PORT_C:
4507                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4508         case PORT_D:
4509                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4510         default:
4511                 WARN_ON_ONCE(1);
4512                 return POWER_DOMAIN_PORT_OTHER;
4513         }
4514 }
4515
4516 #define for_each_power_domain(domain, mask)                             \
4517         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4518                 if ((1 << (domain)) & (mask))
4519
4520 enum intel_display_power_domain
4521 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4522 {
4523         struct drm_device *dev = intel_encoder->base.dev;
4524         struct intel_digital_port *intel_dig_port;
4525
4526         switch (intel_encoder->type) {
4527         case INTEL_OUTPUT_UNKNOWN:
4528                 /* Only DDI platforms should ever use this output type */
4529                 WARN_ON_ONCE(!HAS_DDI(dev));
4530         case INTEL_OUTPUT_DISPLAYPORT:
4531         case INTEL_OUTPUT_HDMI:
4532         case INTEL_OUTPUT_EDP:
4533                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4534                 return port_to_power_domain(intel_dig_port->port);
4535         case INTEL_OUTPUT_DP_MST:
4536                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4537                 return port_to_power_domain(intel_dig_port->port);
4538         case INTEL_OUTPUT_ANALOG:
4539                 return POWER_DOMAIN_PORT_CRT;
4540         case INTEL_OUTPUT_DSI:
4541                 return POWER_DOMAIN_PORT_DSI;
4542         default:
4543                 return POWER_DOMAIN_PORT_OTHER;
4544         }
4545 }
4546
4547 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4548 {
4549         struct drm_device *dev = crtc->dev;
4550         struct intel_encoder *intel_encoder;
4551         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4552         enum pipe pipe = intel_crtc->pipe;
4553         unsigned long mask;
4554         enum transcoder transcoder;
4555
4556         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4557
4558         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4559         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4560         if (intel_crtc->config.pch_pfit.enabled ||
4561             intel_crtc->config.pch_pfit.force_thru)
4562                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4563
4564         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4565                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4566
4567         return mask;
4568 }
4569
4570 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4571 {
4572         struct drm_i915_private *dev_priv = dev->dev_private;
4573         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4574         struct intel_crtc *crtc;
4575
4576         /*
4577          * First get all needed power domains, then put all unneeded, to avoid
4578          * any unnecessary toggling of the power wells.
4579          */
4580         for_each_intel_crtc(dev, crtc) {
4581                 enum intel_display_power_domain domain;
4582
4583                 if (!crtc->base.enabled)
4584                         continue;
4585
4586                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4587
4588                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4589                         intel_display_power_get(dev_priv, domain);
4590         }
4591
4592         for_each_intel_crtc(dev, crtc) {
4593                 enum intel_display_power_domain domain;
4594
4595                 for_each_power_domain(domain, crtc->enabled_power_domains)
4596                         intel_display_power_put(dev_priv, domain);
4597
4598                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4599         }
4600
4601         intel_display_set_init_power(dev_priv, false);
4602 }
4603
4604 /* returns HPLL frequency in kHz */
4605 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4606 {
4607         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4608
4609         /* Obtain SKU information */
4610         mutex_lock(&dev_priv->dpio_lock);
4611         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4612                 CCK_FUSE_HPLL_FREQ_MASK;
4613         mutex_unlock(&dev_priv->dpio_lock);
4614
4615         return vco_freq[hpll_freq] * 1000;
4616 }
4617
4618 static void vlv_update_cdclk(struct drm_device *dev)
4619 {
4620         struct drm_i915_private *dev_priv = dev->dev_private;
4621
4622         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4623         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4624                          dev_priv->vlv_cdclk_freq);
4625
4626         /*
4627          * Program the gmbus_freq based on the cdclk frequency.
4628          * BSpec erroneously claims we should aim for 4MHz, but
4629          * in fact 1MHz is the correct frequency.
4630          */
4631         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4632 }
4633
4634 /* Adjust CDclk dividers to allow high res or save power if possible */
4635 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4636 {
4637         struct drm_i915_private *dev_priv = dev->dev_private;
4638         u32 val, cmd;
4639
4640         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4641
4642         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4643                 cmd = 2;
4644         else if (cdclk == 266667)
4645                 cmd = 1;
4646         else
4647                 cmd = 0;
4648
4649         mutex_lock(&dev_priv->rps.hw_lock);
4650         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4651         val &= ~DSPFREQGUAR_MASK;
4652         val |= (cmd << DSPFREQGUAR_SHIFT);
4653         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4654         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4655                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4656                      50)) {
4657                 DRM_ERROR("timed out waiting for CDclk change\n");
4658         }
4659         mutex_unlock(&dev_priv->rps.hw_lock);
4660
4661         if (cdclk == 400000) {
4662                 u32 divider, vco;
4663
4664                 vco = valleyview_get_vco(dev_priv);
4665                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4666
4667                 mutex_lock(&dev_priv->dpio_lock);
4668                 /* adjust cdclk divider */
4669                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4670                 val &= ~DISPLAY_FREQUENCY_VALUES;
4671                 val |= divider;
4672                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4673
4674                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4675                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4676                              50))
4677                         DRM_ERROR("timed out waiting for CDclk change\n");
4678                 mutex_unlock(&dev_priv->dpio_lock);
4679         }
4680
4681         mutex_lock(&dev_priv->dpio_lock);
4682         /* adjust self-refresh exit latency value */
4683         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4684         val &= ~0x7f;
4685
4686         /*
4687          * For high bandwidth configs, we set a higher latency in the bunit
4688          * so that the core display fetch happens in time to avoid underruns.
4689          */
4690         if (cdclk == 400000)
4691                 val |= 4500 / 250; /* 4.5 usec */
4692         else
4693                 val |= 3000 / 250; /* 3.0 usec */
4694         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4695         mutex_unlock(&dev_priv->dpio_lock);
4696
4697         vlv_update_cdclk(dev);
4698 }
4699
4700 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4701 {
4702         struct drm_i915_private *dev_priv = dev->dev_private;
4703         u32 val, cmd;
4704
4705         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4706
4707         switch (cdclk) {
4708         case 400000:
4709                 cmd = 3;
4710                 break;
4711         case 333333:
4712         case 320000:
4713                 cmd = 2;
4714                 break;
4715         case 266667:
4716                 cmd = 1;
4717                 break;
4718         case 200000:
4719                 cmd = 0;
4720                 break;
4721         default:
4722                 WARN_ON(1);
4723                 return;
4724         }
4725
4726         mutex_lock(&dev_priv->rps.hw_lock);
4727         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4728         val &= ~DSPFREQGUAR_MASK_CHV;
4729         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4730         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4731         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4732                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4733                      50)) {
4734                 DRM_ERROR("timed out waiting for CDclk change\n");
4735         }
4736         mutex_unlock(&dev_priv->rps.hw_lock);
4737
4738         vlv_update_cdclk(dev);
4739 }
4740
4741 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4742                                  int max_pixclk)
4743 {
4744         int vco = valleyview_get_vco(dev_priv);
4745         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4746
4747         /* FIXME: Punit isn't quite ready yet */
4748         if (IS_CHERRYVIEW(dev_priv->dev))
4749                 return 400000;
4750
4751         /*
4752          * Really only a few cases to deal with, as only 4 CDclks are supported:
4753          *   200MHz
4754          *   267MHz
4755          *   320/333MHz (depends on HPLL freq)
4756          *   400MHz
4757          * So we check to see whether we're above 90% of the lower bin and
4758          * adjust if needed.
4759          *
4760          * We seem to get an unstable or solid color picture at 200MHz.
4761          * Not sure what's wrong. For now use 200MHz only when all pipes
4762          * are off.
4763          */
4764         if (max_pixclk > freq_320*9/10)
4765                 return 400000;
4766         else if (max_pixclk > 266667*9/10)
4767                 return freq_320;
4768         else if (max_pixclk > 0)
4769                 return 266667;
4770         else
4771                 return 200000;
4772 }
4773
4774 /* compute the max pixel clock for new configuration */
4775 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4776 {
4777         struct drm_device *dev = dev_priv->dev;
4778         struct intel_crtc *intel_crtc;
4779         int max_pixclk = 0;
4780
4781         for_each_intel_crtc(dev, intel_crtc) {
4782                 if (intel_crtc->new_enabled)
4783                         max_pixclk = max(max_pixclk,
4784                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4785         }
4786
4787         return max_pixclk;
4788 }
4789
4790 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4791                                             unsigned *prepare_pipes)
4792 {
4793         struct drm_i915_private *dev_priv = dev->dev_private;
4794         struct intel_crtc *intel_crtc;
4795         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4796
4797         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4798             dev_priv->vlv_cdclk_freq)
4799                 return;
4800
4801         /* disable/enable all currently active pipes while we change cdclk */
4802         for_each_intel_crtc(dev, intel_crtc)
4803                 if (intel_crtc->base.enabled)
4804                         *prepare_pipes |= (1 << intel_crtc->pipe);
4805 }
4806
4807 static void valleyview_modeset_global_resources(struct drm_device *dev)
4808 {
4809         struct drm_i915_private *dev_priv = dev->dev_private;
4810         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4811         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4812
4813         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4814                 if (IS_CHERRYVIEW(dev))
4815                         cherryview_set_cdclk(dev, req_cdclk);
4816                 else
4817                         valleyview_set_cdclk(dev, req_cdclk);
4818         }
4819
4820         modeset_update_crtc_power_domains(dev);
4821 }
4822
4823 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4824 {
4825         struct drm_device *dev = crtc->dev;
4826         struct drm_i915_private *dev_priv = to_i915(dev);
4827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4828         struct intel_encoder *encoder;
4829         int pipe = intel_crtc->pipe;
4830         bool is_dsi;
4831
4832         WARN_ON(!crtc->enabled);
4833
4834         if (intel_crtc->active)
4835                 return;
4836
4837         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4838
4839         if (!is_dsi) {
4840                 if (IS_CHERRYVIEW(dev))
4841                         chv_prepare_pll(intel_crtc);
4842                 else
4843                         vlv_prepare_pll(intel_crtc);
4844         }
4845
4846         if (intel_crtc->config.has_dp_encoder)
4847                 intel_dp_set_m_n(intel_crtc);
4848
4849         intel_set_pipe_timings(intel_crtc);
4850
4851         i9xx_set_pipeconf(intel_crtc);
4852
4853         intel_crtc->active = true;
4854
4855         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4856
4857         for_each_encoder_on_crtc(dev, crtc, encoder)
4858                 if (encoder->pre_pll_enable)
4859                         encoder->pre_pll_enable(encoder);
4860
4861         if (!is_dsi) {
4862                 if (IS_CHERRYVIEW(dev))
4863                         chv_enable_pll(intel_crtc);
4864                 else
4865                         vlv_enable_pll(intel_crtc);
4866         }
4867
4868         for_each_encoder_on_crtc(dev, crtc, encoder)
4869                 if (encoder->pre_enable)
4870                         encoder->pre_enable(encoder);
4871
4872         i9xx_pfit_enable(intel_crtc);
4873
4874         intel_crtc_load_lut(crtc);
4875
4876         intel_update_watermarks(crtc);
4877         intel_enable_pipe(intel_crtc);
4878
4879         for_each_encoder_on_crtc(dev, crtc, encoder)
4880                 encoder->enable(encoder);
4881
4882         assert_vblank_disabled(crtc);
4883         drm_crtc_vblank_on(crtc);
4884
4885         intel_crtc_enable_planes(crtc);
4886
4887         /* Underruns don't raise interrupts, so check manually. */
4888         i9xx_check_fifo_underruns(dev_priv);
4889 }
4890
4891 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4892 {
4893         struct drm_device *dev = crtc->base.dev;
4894         struct drm_i915_private *dev_priv = dev->dev_private;
4895
4896         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4897         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4898 }
4899
4900 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4901 {
4902         struct drm_device *dev = crtc->dev;
4903         struct drm_i915_private *dev_priv = to_i915(dev);
4904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4905         struct intel_encoder *encoder;
4906         int pipe = intel_crtc->pipe;
4907
4908         WARN_ON(!crtc->enabled);
4909
4910         if (intel_crtc->active)
4911                 return;
4912
4913         i9xx_set_pll_dividers(intel_crtc);
4914
4915         if (intel_crtc->config.has_dp_encoder)
4916                 intel_dp_set_m_n(intel_crtc);
4917
4918         intel_set_pipe_timings(intel_crtc);
4919
4920         i9xx_set_pipeconf(intel_crtc);
4921
4922         intel_crtc->active = true;
4923
4924         if (!IS_GEN2(dev))
4925                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4926
4927         for_each_encoder_on_crtc(dev, crtc, encoder)
4928                 if (encoder->pre_enable)
4929                         encoder->pre_enable(encoder);
4930
4931         i9xx_enable_pll(intel_crtc);
4932
4933         i9xx_pfit_enable(intel_crtc);
4934
4935         intel_crtc_load_lut(crtc);
4936
4937         intel_update_watermarks(crtc);
4938         intel_enable_pipe(intel_crtc);
4939
4940         for_each_encoder_on_crtc(dev, crtc, encoder)
4941                 encoder->enable(encoder);
4942
4943         assert_vblank_disabled(crtc);
4944         drm_crtc_vblank_on(crtc);
4945
4946         intel_crtc_enable_planes(crtc);
4947
4948         /*
4949          * Gen2 reports pipe underruns whenever all planes are disabled.
4950          * So don't enable underrun reporting before at least some planes
4951          * are enabled.
4952          * FIXME: Need to fix the logic to work when we turn off all planes
4953          * but leave the pipe running.
4954          */
4955         if (IS_GEN2(dev))
4956                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4957
4958         /* Underruns don't raise interrupts, so check manually. */
4959         i9xx_check_fifo_underruns(dev_priv);
4960 }
4961
4962 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4963 {
4964         struct drm_device *dev = crtc->base.dev;
4965         struct drm_i915_private *dev_priv = dev->dev_private;
4966
4967         if (!crtc->config.gmch_pfit.control)
4968                 return;
4969
4970         assert_pipe_disabled(dev_priv, crtc->pipe);
4971
4972         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4973                          I915_READ(PFIT_CONTROL));
4974         I915_WRITE(PFIT_CONTROL, 0);
4975 }
4976
4977 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4978 {
4979         struct drm_device *dev = crtc->dev;
4980         struct drm_i915_private *dev_priv = dev->dev_private;
4981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4982         struct intel_encoder *encoder;
4983         int pipe = intel_crtc->pipe;
4984
4985         if (!intel_crtc->active)
4986                 return;
4987
4988         /*
4989          * Gen2 reports pipe underruns whenever all planes are disabled.
4990          * So diasble underrun reporting before all the planes get disabled.
4991          * FIXME: Need to fix the logic to work when we turn off all planes
4992          * but leave the pipe running.
4993          */
4994         if (IS_GEN2(dev))
4995                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4996
4997         /*
4998          * Vblank time updates from the shadow to live plane control register
4999          * are blocked if the memory self-refresh mode is active at that
5000          * moment. So to make sure the plane gets truly disabled, disable
5001          * first the self-refresh mode. The self-refresh enable bit in turn
5002          * will be checked/applied by the HW only at the next frame start
5003          * event which is after the vblank start event, so we need to have a
5004          * wait-for-vblank between disabling the plane and the pipe.
5005          */
5006         intel_set_memory_cxsr(dev_priv, false);
5007         intel_crtc_disable_planes(crtc);
5008
5009         /*
5010          * On gen2 planes are double buffered but the pipe isn't, so we must
5011          * wait for planes to fully turn off before disabling the pipe.
5012          * We also need to wait on all gmch platforms because of the
5013          * self-refresh mode constraint explained above.
5014          */
5015         intel_wait_for_vblank(dev, pipe);
5016
5017         drm_crtc_vblank_off(crtc);
5018         assert_vblank_disabled(crtc);
5019
5020         for_each_encoder_on_crtc(dev, crtc, encoder)
5021                 encoder->disable(encoder);
5022
5023         intel_disable_pipe(intel_crtc);
5024
5025         i9xx_pfit_disable(intel_crtc);
5026
5027         for_each_encoder_on_crtc(dev, crtc, encoder)
5028                 if (encoder->post_disable)
5029                         encoder->post_disable(encoder);
5030
5031         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5032                 if (IS_CHERRYVIEW(dev))
5033                         chv_disable_pll(dev_priv, pipe);
5034                 else if (IS_VALLEYVIEW(dev))
5035                         vlv_disable_pll(dev_priv, pipe);
5036                 else
5037                         i9xx_disable_pll(intel_crtc);
5038         }
5039
5040         if (!IS_GEN2(dev))
5041                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5042
5043         intel_crtc->active = false;
5044         intel_update_watermarks(crtc);
5045
5046         mutex_lock(&dev->struct_mutex);
5047         intel_update_fbc(dev);
5048         mutex_unlock(&dev->struct_mutex);
5049 }
5050
5051 static void i9xx_crtc_off(struct drm_crtc *crtc)
5052 {
5053 }
5054
5055 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5056                                     bool enabled)
5057 {
5058         struct drm_device *dev = crtc->dev;
5059         struct drm_i915_master_private *master_priv;
5060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5061         int pipe = intel_crtc->pipe;
5062
5063         if (!dev->primary->master)
5064                 return;
5065
5066         master_priv = dev->primary->master->driver_priv;
5067         if (!master_priv->sarea_priv)
5068                 return;
5069
5070         switch (pipe) {
5071         case 0:
5072                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5073                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5074                 break;
5075         case 1:
5076                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5077                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5078                 break;
5079         default:
5080                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5081                 break;
5082         }
5083 }
5084
5085 /* Master function to enable/disable CRTC and corresponding power wells */
5086 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5087 {
5088         struct drm_device *dev = crtc->dev;
5089         struct drm_i915_private *dev_priv = dev->dev_private;
5090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5091         enum intel_display_power_domain domain;
5092         unsigned long domains;
5093
5094         if (enable) {
5095                 if (!intel_crtc->active) {
5096                         domains = get_crtc_power_domains(crtc);
5097                         for_each_power_domain(domain, domains)
5098                                 intel_display_power_get(dev_priv, domain);
5099                         intel_crtc->enabled_power_domains = domains;
5100
5101                         dev_priv->display.crtc_enable(crtc);
5102                 }
5103         } else {
5104                 if (intel_crtc->active) {
5105                         dev_priv->display.crtc_disable(crtc);
5106
5107                         domains = intel_crtc->enabled_power_domains;
5108                         for_each_power_domain(domain, domains)
5109                                 intel_display_power_put(dev_priv, domain);
5110                         intel_crtc->enabled_power_domains = 0;
5111                 }
5112         }
5113 }
5114
5115 /**
5116  * Sets the power management mode of the pipe and plane.
5117  */
5118 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5119 {
5120         struct drm_device *dev = crtc->dev;
5121         struct intel_encoder *intel_encoder;
5122         bool enable = false;
5123
5124         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5125                 enable |= intel_encoder->connectors_active;
5126
5127         intel_crtc_control(crtc, enable);
5128
5129         intel_crtc_update_sarea(crtc, enable);
5130 }
5131
5132 static void intel_crtc_disable(struct drm_crtc *crtc)
5133 {
5134         struct drm_device *dev = crtc->dev;
5135         struct drm_connector *connector;
5136         struct drm_i915_private *dev_priv = dev->dev_private;
5137         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5138         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5139
5140         /* crtc should still be enabled when we disable it. */
5141         WARN_ON(!crtc->enabled);
5142
5143         dev_priv->display.crtc_disable(crtc);
5144         intel_crtc_update_sarea(crtc, false);
5145         dev_priv->display.off(crtc);
5146
5147         if (crtc->primary->fb) {
5148                 mutex_lock(&dev->struct_mutex);
5149                 intel_unpin_fb_obj(old_obj);
5150                 i915_gem_track_fb(old_obj, NULL,
5151                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5152                 mutex_unlock(&dev->struct_mutex);
5153                 crtc->primary->fb = NULL;
5154         }
5155
5156         /* Update computed state. */
5157         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5158                 if (!connector->encoder || !connector->encoder->crtc)
5159                         continue;
5160
5161                 if (connector->encoder->crtc != crtc)
5162                         continue;
5163
5164                 connector->dpms = DRM_MODE_DPMS_OFF;
5165                 to_intel_encoder(connector->encoder)->connectors_active = false;
5166         }
5167 }
5168
5169 void intel_encoder_destroy(struct drm_encoder *encoder)
5170 {
5171         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5172
5173         drm_encoder_cleanup(encoder);
5174         kfree(intel_encoder);
5175 }
5176
5177 /* Simple dpms helper for encoders with just one connector, no cloning and only
5178  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5179  * state of the entire output pipe. */
5180 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5181 {
5182         if (mode == DRM_MODE_DPMS_ON) {
5183                 encoder->connectors_active = true;
5184
5185                 intel_crtc_update_dpms(encoder->base.crtc);
5186         } else {
5187                 encoder->connectors_active = false;
5188
5189                 intel_crtc_update_dpms(encoder->base.crtc);
5190         }
5191 }
5192
5193 /* Cross check the actual hw state with our own modeset state tracking (and it's
5194  * internal consistency). */
5195 static void intel_connector_check_state(struct intel_connector *connector)
5196 {
5197         if (connector->get_hw_state(connector)) {
5198                 struct intel_encoder *encoder = connector->encoder;
5199                 struct drm_crtc *crtc;
5200                 bool encoder_enabled;
5201                 enum pipe pipe;
5202
5203                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5204                               connector->base.base.id,
5205                               connector->base.name);
5206
5207                 /* there is no real hw state for MST connectors */
5208                 if (connector->mst_port)
5209                         return;
5210
5211                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5212                      "wrong connector dpms state\n");
5213                 WARN(connector->base.encoder != &encoder->base,
5214                      "active connector not linked to encoder\n");
5215
5216                 if (encoder) {
5217                         WARN(!encoder->connectors_active,
5218                              "encoder->connectors_active not set\n");
5219
5220                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5221                         WARN(!encoder_enabled, "encoder not enabled\n");
5222                         if (WARN_ON(!encoder->base.crtc))
5223                                 return;
5224
5225                         crtc = encoder->base.crtc;
5226
5227                         WARN(!crtc->enabled, "crtc not enabled\n");
5228                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5229                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5230                              "encoder active on the wrong pipe\n");
5231                 }
5232         }
5233 }
5234
5235 /* Even simpler default implementation, if there's really no special case to
5236  * consider. */
5237 void intel_connector_dpms(struct drm_connector *connector, int mode)
5238 {
5239         /* All the simple cases only support two dpms states. */
5240         if (mode != DRM_MODE_DPMS_ON)
5241                 mode = DRM_MODE_DPMS_OFF;
5242
5243         if (mode == connector->dpms)
5244                 return;
5245
5246         connector->dpms = mode;
5247
5248         /* Only need to change hw state when actually enabled */
5249         if (connector->encoder)
5250                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5251
5252         intel_modeset_check_state(connector->dev);
5253 }
5254
5255 /* Simple connector->get_hw_state implementation for encoders that support only
5256  * one connector and no cloning and hence the encoder state determines the state
5257  * of the connector. */
5258 bool intel_connector_get_hw_state(struct intel_connector *connector)
5259 {
5260         enum pipe pipe = 0;
5261         struct intel_encoder *encoder = connector->encoder;
5262
5263         return encoder->get_hw_state(encoder, &pipe);
5264 }
5265
5266 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5267                                      struct intel_crtc_config *pipe_config)
5268 {
5269         struct drm_i915_private *dev_priv = dev->dev_private;
5270         struct intel_crtc *pipe_B_crtc =
5271                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5272
5273         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5274                       pipe_name(pipe), pipe_config->fdi_lanes);
5275         if (pipe_config->fdi_lanes > 4) {
5276                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5277                               pipe_name(pipe), pipe_config->fdi_lanes);
5278                 return false;
5279         }
5280
5281         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5282                 if (pipe_config->fdi_lanes > 2) {
5283                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5284                                       pipe_config->fdi_lanes);
5285                         return false;
5286                 } else {
5287                         return true;
5288                 }
5289         }
5290
5291         if (INTEL_INFO(dev)->num_pipes == 2)
5292                 return true;
5293
5294         /* Ivybridge 3 pipe is really complicated */
5295         switch (pipe) {
5296         case PIPE_A:
5297                 return true;
5298         case PIPE_B:
5299                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5300                     pipe_config->fdi_lanes > 2) {
5301                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5302                                       pipe_name(pipe), pipe_config->fdi_lanes);
5303                         return false;
5304                 }
5305                 return true;
5306         case PIPE_C:
5307                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5308                     pipe_B_crtc->config.fdi_lanes <= 2) {
5309                         if (pipe_config->fdi_lanes > 2) {
5310                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5311                                               pipe_name(pipe), pipe_config->fdi_lanes);
5312                                 return false;
5313                         }
5314                 } else {
5315                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5316                         return false;
5317                 }
5318                 return true;
5319         default:
5320                 BUG();
5321         }
5322 }
5323
5324 #define RETRY 1
5325 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5326                                        struct intel_crtc_config *pipe_config)
5327 {
5328         struct drm_device *dev = intel_crtc->base.dev;
5329         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5330         int lane, link_bw, fdi_dotclock;
5331         bool setup_ok, needs_recompute = false;
5332
5333 retry:
5334         /* FDI is a binary signal running at ~2.7GHz, encoding
5335          * each output octet as 10 bits. The actual frequency
5336          * is stored as a divider into a 100MHz clock, and the
5337          * mode pixel clock is stored in units of 1KHz.
5338          * Hence the bw of each lane in terms of the mode signal
5339          * is:
5340          */
5341         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5342
5343         fdi_dotclock = adjusted_mode->crtc_clock;
5344
5345         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5346                                            pipe_config->pipe_bpp);
5347
5348         pipe_config->fdi_lanes = lane;
5349
5350         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5351                                link_bw, &pipe_config->fdi_m_n);
5352
5353         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5354                                             intel_crtc->pipe, pipe_config);
5355         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5356                 pipe_config->pipe_bpp -= 2*3;
5357                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5358                               pipe_config->pipe_bpp);
5359                 needs_recompute = true;
5360                 pipe_config->bw_constrained = true;
5361
5362                 goto retry;
5363         }
5364
5365         if (needs_recompute)
5366                 return RETRY;
5367
5368         return setup_ok ? 0 : -EINVAL;
5369 }
5370
5371 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5372                                    struct intel_crtc_config *pipe_config)
5373 {
5374         pipe_config->ips_enabled = i915.enable_ips &&
5375                                    hsw_crtc_supports_ips(crtc) &&
5376                                    pipe_config->pipe_bpp <= 24;
5377 }
5378
5379 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5380                                      struct intel_crtc_config *pipe_config)
5381 {
5382         struct drm_device *dev = crtc->base.dev;
5383         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5384
5385         /* FIXME should check pixel clock limits on all platforms */
5386         if (INTEL_INFO(dev)->gen < 4) {
5387                 struct drm_i915_private *dev_priv = dev->dev_private;
5388                 int clock_limit =
5389                         dev_priv->display.get_display_clock_speed(dev);
5390
5391                 /*
5392                  * Enable pixel doubling when the dot clock
5393                  * is > 90% of the (display) core speed.
5394                  *
5395                  * GDG double wide on either pipe,
5396                  * otherwise pipe A only.
5397                  */
5398                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5399                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5400                         clock_limit *= 2;
5401                         pipe_config->double_wide = true;
5402                 }
5403
5404                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5405                         return -EINVAL;
5406         }
5407
5408         /*
5409          * Pipe horizontal size must be even in:
5410          * - DVO ganged mode
5411          * - LVDS dual channel mode
5412          * - Double wide pipe
5413          */
5414         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5415              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5416                 pipe_config->pipe_src_w &= ~1;
5417
5418         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5419          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5420          */
5421         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5422                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5423                 return -EINVAL;
5424
5425         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5426                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5427         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5428                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5429                  * for lvds. */
5430                 pipe_config->pipe_bpp = 8*3;
5431         }
5432
5433         if (HAS_IPS(dev))
5434                 hsw_compute_ips_config(crtc, pipe_config);
5435
5436         /*
5437          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5438          * old clock survives for now.
5439          */
5440         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5441                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5442
5443         if (pipe_config->has_pch_encoder)
5444                 return ironlake_fdi_compute_config(crtc, pipe_config);
5445
5446         return 0;
5447 }
5448
5449 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5450 {
5451         struct drm_i915_private *dev_priv = dev->dev_private;
5452         int vco = valleyview_get_vco(dev_priv);
5453         u32 val;
5454         int divider;
5455
5456         /* FIXME: Punit isn't quite ready yet */
5457         if (IS_CHERRYVIEW(dev))
5458                 return 400000;
5459
5460         mutex_lock(&dev_priv->dpio_lock);
5461         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5462         mutex_unlock(&dev_priv->dpio_lock);
5463
5464         divider = val & DISPLAY_FREQUENCY_VALUES;
5465
5466         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5467              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5468              "cdclk change in progress\n");
5469
5470         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5471 }
5472
5473 static int i945_get_display_clock_speed(struct drm_device *dev)
5474 {
5475         return 400000;
5476 }
5477
5478 static int i915_get_display_clock_speed(struct drm_device *dev)
5479 {
5480         return 333000;
5481 }
5482
5483 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5484 {
5485         return 200000;
5486 }
5487
5488 static int pnv_get_display_clock_speed(struct drm_device *dev)
5489 {
5490         u16 gcfgc = 0;
5491
5492         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5493
5494         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5495         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5496                 return 267000;
5497         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5498                 return 333000;
5499         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5500                 return 444000;
5501         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5502                 return 200000;
5503         default:
5504                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5505         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5506                 return 133000;
5507         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5508                 return 167000;
5509         }
5510 }
5511
5512 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5513 {
5514         u16 gcfgc = 0;
5515
5516         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5517
5518         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5519                 return 133000;
5520         else {
5521                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5522                 case GC_DISPLAY_CLOCK_333_MHZ:
5523                         return 333000;
5524                 default:
5525                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5526                         return 190000;
5527                 }
5528         }
5529 }
5530
5531 static int i865_get_display_clock_speed(struct drm_device *dev)
5532 {
5533         return 266000;
5534 }
5535
5536 static int i855_get_display_clock_speed(struct drm_device *dev)
5537 {
5538         u16 hpllcc = 0;
5539         /* Assume that the hardware is in the high speed state.  This
5540          * should be the default.
5541          */
5542         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5543         case GC_CLOCK_133_200:
5544         case GC_CLOCK_100_200:
5545                 return 200000;
5546         case GC_CLOCK_166_250:
5547                 return 250000;
5548         case GC_CLOCK_100_133:
5549                 return 133000;
5550         }
5551
5552         /* Shouldn't happen */
5553         return 0;
5554 }
5555
5556 static int i830_get_display_clock_speed(struct drm_device *dev)
5557 {
5558         return 133000;
5559 }
5560
5561 static void
5562 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5563 {
5564         while (*num > DATA_LINK_M_N_MASK ||
5565                *den > DATA_LINK_M_N_MASK) {
5566                 *num >>= 1;
5567                 *den >>= 1;
5568         }
5569 }
5570
5571 static void compute_m_n(unsigned int m, unsigned int n,
5572                         uint32_t *ret_m, uint32_t *ret_n)
5573 {
5574         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5575         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5576         intel_reduce_m_n_ratio(ret_m, ret_n);
5577 }
5578
5579 void
5580 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5581                        int pixel_clock, int link_clock,
5582                        struct intel_link_m_n *m_n)
5583 {
5584         m_n->tu = 64;
5585
5586         compute_m_n(bits_per_pixel * pixel_clock,
5587                     link_clock * nlanes * 8,
5588                     &m_n->gmch_m, &m_n->gmch_n);
5589
5590         compute_m_n(pixel_clock, link_clock,
5591                     &m_n->link_m, &m_n->link_n);
5592 }
5593
5594 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5595 {
5596         if (i915.panel_use_ssc >= 0)
5597                 return i915.panel_use_ssc != 0;
5598         return dev_priv->vbt.lvds_use_ssc
5599                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5600 }
5601
5602 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5603 {
5604         struct drm_device *dev = crtc->base.dev;
5605         struct drm_i915_private *dev_priv = dev->dev_private;
5606         int refclk;
5607
5608         if (IS_VALLEYVIEW(dev)) {
5609                 refclk = 100000;
5610         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5611             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5612                 refclk = dev_priv->vbt.lvds_ssc_freq;
5613                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5614         } else if (!IS_GEN2(dev)) {
5615                 refclk = 96000;
5616         } else {
5617                 refclk = 48000;
5618         }
5619
5620         return refclk;
5621 }
5622
5623 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5624 {
5625         return (1 << dpll->n) << 16 | dpll->m2;
5626 }
5627
5628 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5629 {
5630         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5631 }
5632
5633 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5634                                      intel_clock_t *reduced_clock)
5635 {
5636         struct drm_device *dev = crtc->base.dev;
5637         u32 fp, fp2 = 0;
5638
5639         if (IS_PINEVIEW(dev)) {
5640                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5641                 if (reduced_clock)
5642                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5643         } else {
5644                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5645                 if (reduced_clock)
5646                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5647         }
5648
5649         crtc->config.dpll_hw_state.fp0 = fp;
5650
5651         crtc->lowfreq_avail = false;
5652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5653             reduced_clock && i915.powersave) {
5654                 crtc->config.dpll_hw_state.fp1 = fp2;
5655                 crtc->lowfreq_avail = true;
5656         } else {
5657                 crtc->config.dpll_hw_state.fp1 = fp;
5658         }
5659 }
5660
5661 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5662                 pipe)
5663 {
5664         u32 reg_val;
5665
5666         /*
5667          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5668          * and set it to a reasonable value instead.
5669          */
5670         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5671         reg_val &= 0xffffff00;
5672         reg_val |= 0x00000030;
5673         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5674
5675         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5676         reg_val &= 0x8cffffff;
5677         reg_val = 0x8c000000;
5678         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5679
5680         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5681         reg_val &= 0xffffff00;
5682         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5683
5684         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5685         reg_val &= 0x00ffffff;
5686         reg_val |= 0xb0000000;
5687         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5688 }
5689
5690 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5691                                          struct intel_link_m_n *m_n)
5692 {
5693         struct drm_device *dev = crtc->base.dev;
5694         struct drm_i915_private *dev_priv = dev->dev_private;
5695         int pipe = crtc->pipe;
5696
5697         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5698         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5699         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5700         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5701 }
5702
5703 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5704                                          struct intel_link_m_n *m_n,
5705                                          struct intel_link_m_n *m2_n2)
5706 {
5707         struct drm_device *dev = crtc->base.dev;
5708         struct drm_i915_private *dev_priv = dev->dev_private;
5709         int pipe = crtc->pipe;
5710         enum transcoder transcoder = crtc->config.cpu_transcoder;
5711
5712         if (INTEL_INFO(dev)->gen >= 5) {
5713                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5714                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5715                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5716                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5717                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5718                  * for gen < 8) and if DRRS is supported (to make sure the
5719                  * registers are not unnecessarily accessed).
5720                  */
5721                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5722                         crtc->config.has_drrs) {
5723                         I915_WRITE(PIPE_DATA_M2(transcoder),
5724                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5725                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5726                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5727                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5728                 }
5729         } else {
5730                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5731                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5732                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5733                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5734         }
5735 }
5736
5737 void intel_dp_set_m_n(struct intel_crtc *crtc)
5738 {
5739         if (crtc->config.has_pch_encoder)
5740                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5741         else
5742                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5743                                                    &crtc->config.dp_m2_n2);
5744 }
5745
5746 static void vlv_update_pll(struct intel_crtc *crtc)
5747 {
5748         u32 dpll, dpll_md;
5749
5750         /*
5751          * Enable DPIO clock input. We should never disable the reference
5752          * clock for pipe B, since VGA hotplug / manual detection depends
5753          * on it.
5754          */
5755         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5756                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5757         /* We should never disable this, set it here for state tracking */
5758         if (crtc->pipe == PIPE_B)
5759                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5760         dpll |= DPLL_VCO_ENABLE;
5761         crtc->config.dpll_hw_state.dpll = dpll;
5762
5763         dpll_md = (crtc->config.pixel_multiplier - 1)
5764                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5765         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5766 }
5767
5768 static void vlv_prepare_pll(struct intel_crtc *crtc)
5769 {
5770         struct drm_device *dev = crtc->base.dev;
5771         struct drm_i915_private *dev_priv = dev->dev_private;
5772         int pipe = crtc->pipe;
5773         u32 mdiv;
5774         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5775         u32 coreclk, reg_val;
5776
5777         mutex_lock(&dev_priv->dpio_lock);
5778
5779         bestn = crtc->config.dpll.n;
5780         bestm1 = crtc->config.dpll.m1;
5781         bestm2 = crtc->config.dpll.m2;
5782         bestp1 = crtc->config.dpll.p1;
5783         bestp2 = crtc->config.dpll.p2;
5784
5785         /* See eDP HDMI DPIO driver vbios notes doc */
5786
5787         /* PLL B needs special handling */
5788         if (pipe == PIPE_B)
5789                 vlv_pllb_recal_opamp(dev_priv, pipe);
5790
5791         /* Set up Tx target for periodic Rcomp update */
5792         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5793
5794         /* Disable target IRef on PLL */
5795         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5796         reg_val &= 0x00ffffff;
5797         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5798
5799         /* Disable fast lock */
5800         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5801
5802         /* Set idtafcrecal before PLL is enabled */
5803         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5804         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5805         mdiv |= ((bestn << DPIO_N_SHIFT));
5806         mdiv |= (1 << DPIO_K_SHIFT);
5807
5808         /*
5809          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5810          * but we don't support that).
5811          * Note: don't use the DAC post divider as it seems unstable.
5812          */
5813         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5814         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5815
5816         mdiv |= DPIO_ENABLE_CALIBRATION;
5817         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5818
5819         /* Set HBR and RBR LPF coefficients */
5820         if (crtc->config.port_clock == 162000 ||
5821             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5822             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5823                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5824                                  0x009f0003);
5825         else
5826                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5827                                  0x00d0000f);
5828
5829         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP) ||
5830             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5831                 /* Use SSC source */
5832                 if (pipe == PIPE_A)
5833                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5834                                          0x0df40000);
5835                 else
5836                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5837                                          0x0df70000);
5838         } else { /* HDMI or VGA */
5839                 /* Use bend source */
5840                 if (pipe == PIPE_A)
5841                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5842                                          0x0df70000);
5843                 else
5844                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5845                                          0x0df40000);
5846         }
5847
5848         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5849         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5850         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5851             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5852                 coreclk |= 0x01000000;
5853         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5854
5855         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5856         mutex_unlock(&dev_priv->dpio_lock);
5857 }
5858
5859 static void chv_update_pll(struct intel_crtc *crtc)
5860 {
5861         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5862                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5863                 DPLL_VCO_ENABLE;
5864         if (crtc->pipe != PIPE_A)
5865                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5866
5867         crtc->config.dpll_hw_state.dpll_md =
5868                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5869 }
5870
5871 static void chv_prepare_pll(struct intel_crtc *crtc)
5872 {
5873         struct drm_device *dev = crtc->base.dev;
5874         struct drm_i915_private *dev_priv = dev->dev_private;
5875         int pipe = crtc->pipe;
5876         int dpll_reg = DPLL(crtc->pipe);
5877         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5878         u32 loopfilter, intcoeff;
5879         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5880         int refclk;
5881
5882         bestn = crtc->config.dpll.n;
5883         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5884         bestm1 = crtc->config.dpll.m1;
5885         bestm2 = crtc->config.dpll.m2 >> 22;
5886         bestp1 = crtc->config.dpll.p1;
5887         bestp2 = crtc->config.dpll.p2;
5888
5889         /*
5890          * Enable Refclk and SSC
5891          */
5892         I915_WRITE(dpll_reg,
5893                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5894
5895         mutex_lock(&dev_priv->dpio_lock);
5896
5897         /* p1 and p2 divider */
5898         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5899                         5 << DPIO_CHV_S1_DIV_SHIFT |
5900                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5901                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5902                         1 << DPIO_CHV_K_DIV_SHIFT);
5903
5904         /* Feedback post-divider - m2 */
5905         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5906
5907         /* Feedback refclk divider - n and m1 */
5908         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5909                         DPIO_CHV_M1_DIV_BY_2 |
5910                         1 << DPIO_CHV_N_DIV_SHIFT);
5911
5912         /* M2 fraction division */
5913         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5914
5915         /* M2 fraction division enable */
5916         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5917                        DPIO_CHV_FRAC_DIV_EN |
5918                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5919
5920         /* Loop filter */
5921         refclk = i9xx_get_refclk(crtc, 0);
5922         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5923                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5924         if (refclk == 100000)
5925                 intcoeff = 11;
5926         else if (refclk == 38400)
5927                 intcoeff = 10;
5928         else
5929                 intcoeff = 9;
5930         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5931         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5932
5933         /* AFC Recal */
5934         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5935                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5936                         DPIO_AFC_RECAL);
5937
5938         mutex_unlock(&dev_priv->dpio_lock);
5939 }
5940
5941 static void i9xx_update_pll(struct intel_crtc *crtc,
5942                             intel_clock_t *reduced_clock,
5943                             int num_connectors)
5944 {
5945         struct drm_device *dev = crtc->base.dev;
5946         struct drm_i915_private *dev_priv = dev->dev_private;
5947         u32 dpll;
5948         bool is_sdvo;
5949         struct dpll *clock = &crtc->config.dpll;
5950
5951         i9xx_update_pll_dividers(crtc, reduced_clock);
5952
5953         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
5954                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
5955
5956         dpll = DPLL_VGA_MODE_DIS;
5957
5958         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5959                 dpll |= DPLLB_MODE_LVDS;
5960         else
5961                 dpll |= DPLLB_MODE_DAC_SERIAL;
5962
5963         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5964                 dpll |= (crtc->config.pixel_multiplier - 1)
5965                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5966         }
5967
5968         if (is_sdvo)
5969                 dpll |= DPLL_SDVO_HIGH_SPEED;
5970
5971         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5972                 dpll |= DPLL_SDVO_HIGH_SPEED;
5973
5974         /* compute bitmask from p1 value */
5975         if (IS_PINEVIEW(dev))
5976                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5977         else {
5978                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5979                 if (IS_G4X(dev) && reduced_clock)
5980                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5981         }
5982         switch (clock->p2) {
5983         case 5:
5984                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5985                 break;
5986         case 7:
5987                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5988                 break;
5989         case 10:
5990                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5991                 break;
5992         case 14:
5993                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5994                 break;
5995         }
5996         if (INTEL_INFO(dev)->gen >= 4)
5997                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5998
5999         if (crtc->config.sdvo_tv_clock)
6000                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6001         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6002                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6003                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6004         else
6005                 dpll |= PLL_REF_INPUT_DREFCLK;
6006
6007         dpll |= DPLL_VCO_ENABLE;
6008         crtc->config.dpll_hw_state.dpll = dpll;
6009
6010         if (INTEL_INFO(dev)->gen >= 4) {
6011                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
6012                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6013                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
6014         }
6015 }
6016
6017 static void i8xx_update_pll(struct intel_crtc *crtc,
6018                             intel_clock_t *reduced_clock,
6019                             int num_connectors)
6020 {
6021         struct drm_device *dev = crtc->base.dev;
6022         struct drm_i915_private *dev_priv = dev->dev_private;
6023         u32 dpll;
6024         struct dpll *clock = &crtc->config.dpll;
6025
6026         i9xx_update_pll_dividers(crtc, reduced_clock);
6027
6028         dpll = DPLL_VGA_MODE_DIS;
6029
6030         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
6031                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6032         } else {
6033                 if (clock->p1 == 2)
6034                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6035                 else
6036                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6037                 if (clock->p2 == 4)
6038                         dpll |= PLL_P2_DIVIDE_BY_4;
6039         }
6040
6041         if (!IS_I830(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
6042                 dpll |= DPLL_DVO_2X_MODE;
6043
6044         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6045                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6046                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6047         else
6048                 dpll |= PLL_REF_INPUT_DREFCLK;
6049
6050         dpll |= DPLL_VCO_ENABLE;
6051         crtc->config.dpll_hw_state.dpll = dpll;
6052 }
6053
6054 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6055 {
6056         struct drm_device *dev = intel_crtc->base.dev;
6057         struct drm_i915_private *dev_priv = dev->dev_private;
6058         enum pipe pipe = intel_crtc->pipe;
6059         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6060         struct drm_display_mode *adjusted_mode =
6061                 &intel_crtc->config.adjusted_mode;
6062         uint32_t crtc_vtotal, crtc_vblank_end;
6063         int vsyncshift = 0;
6064
6065         /* We need to be careful not to changed the adjusted mode, for otherwise
6066          * the hw state checker will get angry at the mismatch. */
6067         crtc_vtotal = adjusted_mode->crtc_vtotal;
6068         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6069
6070         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6071                 /* the chip adds 2 halflines automatically */
6072                 crtc_vtotal -= 1;
6073                 crtc_vblank_end -= 1;
6074
6075                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6076                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6077                 else
6078                         vsyncshift = adjusted_mode->crtc_hsync_start -
6079                                 adjusted_mode->crtc_htotal / 2;
6080                 if (vsyncshift < 0)
6081                         vsyncshift += adjusted_mode->crtc_htotal;
6082         }
6083
6084         if (INTEL_INFO(dev)->gen > 3)
6085                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6086
6087         I915_WRITE(HTOTAL(cpu_transcoder),
6088                    (adjusted_mode->crtc_hdisplay - 1) |
6089                    ((adjusted_mode->crtc_htotal - 1) << 16));
6090         I915_WRITE(HBLANK(cpu_transcoder),
6091                    (adjusted_mode->crtc_hblank_start - 1) |
6092                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6093         I915_WRITE(HSYNC(cpu_transcoder),
6094                    (adjusted_mode->crtc_hsync_start - 1) |
6095                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6096
6097         I915_WRITE(VTOTAL(cpu_transcoder),
6098                    (adjusted_mode->crtc_vdisplay - 1) |
6099                    ((crtc_vtotal - 1) << 16));
6100         I915_WRITE(VBLANK(cpu_transcoder),
6101                    (adjusted_mode->crtc_vblank_start - 1) |
6102                    ((crtc_vblank_end - 1) << 16));
6103         I915_WRITE(VSYNC(cpu_transcoder),
6104                    (adjusted_mode->crtc_vsync_start - 1) |
6105                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6106
6107         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6108          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6109          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6110          * bits. */
6111         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6112             (pipe == PIPE_B || pipe == PIPE_C))
6113                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6114
6115         /* pipesrc controls the size that is scaled from, which should
6116          * always be the user's requested size.
6117          */
6118         I915_WRITE(PIPESRC(pipe),
6119                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6120                    (intel_crtc->config.pipe_src_h - 1));
6121 }
6122
6123 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6124                                    struct intel_crtc_config *pipe_config)
6125 {
6126         struct drm_device *dev = crtc->base.dev;
6127         struct drm_i915_private *dev_priv = dev->dev_private;
6128         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6129         uint32_t tmp;
6130
6131         tmp = I915_READ(HTOTAL(cpu_transcoder));
6132         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6133         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6134         tmp = I915_READ(HBLANK(cpu_transcoder));
6135         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6136         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6137         tmp = I915_READ(HSYNC(cpu_transcoder));
6138         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6139         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6140
6141         tmp = I915_READ(VTOTAL(cpu_transcoder));
6142         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6143         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6144         tmp = I915_READ(VBLANK(cpu_transcoder));
6145         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6146         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6147         tmp = I915_READ(VSYNC(cpu_transcoder));
6148         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6149         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6150
6151         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6152                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6153                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6154                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6155         }
6156
6157         tmp = I915_READ(PIPESRC(crtc->pipe));
6158         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6159         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6160
6161         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6162         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6163 }
6164
6165 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6166                                  struct intel_crtc_config *pipe_config)
6167 {
6168         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6169         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6170         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6171         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6172
6173         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6174         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6175         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6176         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6177
6178         mode->flags = pipe_config->adjusted_mode.flags;
6179
6180         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6181         mode->flags |= pipe_config->adjusted_mode.flags;
6182 }
6183
6184 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6185 {
6186         struct drm_device *dev = intel_crtc->base.dev;
6187         struct drm_i915_private *dev_priv = dev->dev_private;
6188         uint32_t pipeconf;
6189
6190         pipeconf = 0;
6191
6192         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6193             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6194                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6195
6196         if (intel_crtc->config.double_wide)
6197                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6198
6199         /* only g4x and later have fancy bpc/dither controls */
6200         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6201                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6202                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6203                         pipeconf |= PIPECONF_DITHER_EN |
6204                                     PIPECONF_DITHER_TYPE_SP;
6205
6206                 switch (intel_crtc->config.pipe_bpp) {
6207                 case 18:
6208                         pipeconf |= PIPECONF_6BPC;
6209                         break;
6210                 case 24:
6211                         pipeconf |= PIPECONF_8BPC;
6212                         break;
6213                 case 30:
6214                         pipeconf |= PIPECONF_10BPC;
6215                         break;
6216                 default:
6217                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6218                         BUG();
6219                 }
6220         }
6221
6222         if (HAS_PIPE_CXSR(dev)) {
6223                 if (intel_crtc->lowfreq_avail) {
6224                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6225                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6226                 } else {
6227                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6228                 }
6229         }
6230
6231         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6232                 if (INTEL_INFO(dev)->gen < 4 ||
6233                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6234                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6235                 else
6236                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6237         } else
6238                 pipeconf |= PIPECONF_PROGRESSIVE;
6239
6240         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6241                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6242
6243         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6244         POSTING_READ(PIPECONF(intel_crtc->pipe));
6245 }
6246
6247 static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
6248                               int x, int y,
6249                               struct drm_framebuffer *fb)
6250 {
6251         struct drm_device *dev = crtc->base.dev;
6252         struct drm_i915_private *dev_priv = dev->dev_private;
6253         int refclk, num_connectors = 0;
6254         intel_clock_t clock, reduced_clock;
6255         bool ok, has_reduced_clock = false;
6256         bool is_lvds = false, is_dsi = false;
6257         struct intel_encoder *encoder;
6258         const intel_limit_t *limit;
6259
6260         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6261                 switch (encoder->type) {
6262                 case INTEL_OUTPUT_LVDS:
6263                         is_lvds = true;
6264                         break;
6265                 case INTEL_OUTPUT_DSI:
6266                         is_dsi = true;
6267                         break;
6268                 }
6269
6270                 num_connectors++;
6271         }
6272
6273         if (is_dsi)
6274                 return 0;
6275
6276         if (!crtc->config.clock_set) {
6277                 refclk = i9xx_get_refclk(crtc, num_connectors);
6278
6279                 /*
6280                  * Returns a set of divisors for the desired target clock with
6281                  * the given refclk, or FALSE.  The returned values represent
6282                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6283                  * 2) / p1 / p2.
6284                  */
6285                 limit = intel_limit(crtc, refclk);
6286                 ok = dev_priv->display.find_dpll(limit, crtc,
6287                                                  crtc->config.port_clock,
6288                                                  refclk, NULL, &clock);
6289                 if (!ok) {
6290                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6291                         return -EINVAL;
6292                 }
6293
6294                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6295                         /*
6296                          * Ensure we match the reduced clock's P to the target
6297                          * clock.  If the clocks don't match, we can't switch
6298                          * the display clock by using the FP0/FP1. In such case
6299                          * we will disable the LVDS downclock feature.
6300                          */
6301                         has_reduced_clock =
6302                                 dev_priv->display.find_dpll(limit, crtc,
6303                                                             dev_priv->lvds_downclock,
6304                                                             refclk, &clock,
6305                                                             &reduced_clock);
6306                 }
6307                 /* Compat-code for transition, will disappear. */
6308                 crtc->config.dpll.n = clock.n;
6309                 crtc->config.dpll.m1 = clock.m1;
6310                 crtc->config.dpll.m2 = clock.m2;
6311                 crtc->config.dpll.p1 = clock.p1;
6312                 crtc->config.dpll.p2 = clock.p2;
6313         }
6314
6315         if (IS_GEN2(dev)) {
6316                 i8xx_update_pll(crtc,
6317                                 has_reduced_clock ? &reduced_clock : NULL,
6318                                 num_connectors);
6319         } else if (IS_CHERRYVIEW(dev)) {
6320                 chv_update_pll(crtc);
6321         } else if (IS_VALLEYVIEW(dev)) {
6322                 vlv_update_pll(crtc);
6323         } else {
6324                 i9xx_update_pll(crtc,
6325                                 has_reduced_clock ? &reduced_clock : NULL,
6326                                 num_connectors);
6327         }
6328
6329         return 0;
6330 }
6331
6332 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6333                                  struct intel_crtc_config *pipe_config)
6334 {
6335         struct drm_device *dev = crtc->base.dev;
6336         struct drm_i915_private *dev_priv = dev->dev_private;
6337         uint32_t tmp;
6338
6339         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6340                 return;
6341
6342         tmp = I915_READ(PFIT_CONTROL);
6343         if (!(tmp & PFIT_ENABLE))
6344                 return;
6345
6346         /* Check whether the pfit is attached to our pipe. */
6347         if (INTEL_INFO(dev)->gen < 4) {
6348                 if (crtc->pipe != PIPE_B)
6349                         return;
6350         } else {
6351                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6352                         return;
6353         }
6354
6355         pipe_config->gmch_pfit.control = tmp;
6356         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6357         if (INTEL_INFO(dev)->gen < 5)
6358                 pipe_config->gmch_pfit.lvds_border_bits =
6359                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6360 }
6361
6362 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6363                                struct intel_crtc_config *pipe_config)
6364 {
6365         struct drm_device *dev = crtc->base.dev;
6366         struct drm_i915_private *dev_priv = dev->dev_private;
6367         int pipe = pipe_config->cpu_transcoder;
6368         intel_clock_t clock;
6369         u32 mdiv;
6370         int refclk = 100000;
6371
6372         /* In case of MIPI DPLL will not even be used */
6373         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6374                 return;
6375
6376         mutex_lock(&dev_priv->dpio_lock);
6377         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6378         mutex_unlock(&dev_priv->dpio_lock);
6379
6380         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6381         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6382         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6383         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6384         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6385
6386         vlv_clock(refclk, &clock);
6387
6388         /* clock.dot is the fast clock */
6389         pipe_config->port_clock = clock.dot / 5;
6390 }
6391
6392 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6393                                   struct intel_plane_config *plane_config)
6394 {
6395         struct drm_device *dev = crtc->base.dev;
6396         struct drm_i915_private *dev_priv = dev->dev_private;
6397         u32 val, base, offset;
6398         int pipe = crtc->pipe, plane = crtc->plane;
6399         int fourcc, pixel_format;
6400         int aligned_height;
6401
6402         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6403         if (!crtc->base.primary->fb) {
6404                 DRM_DEBUG_KMS("failed to alloc fb\n");
6405                 return;
6406         }
6407
6408         val = I915_READ(DSPCNTR(plane));
6409
6410         if (INTEL_INFO(dev)->gen >= 4)
6411                 if (val & DISPPLANE_TILED)
6412                         plane_config->tiled = true;
6413
6414         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6415         fourcc = intel_format_to_fourcc(pixel_format);
6416         crtc->base.primary->fb->pixel_format = fourcc;
6417         crtc->base.primary->fb->bits_per_pixel =
6418                 drm_format_plane_cpp(fourcc, 0) * 8;
6419
6420         if (INTEL_INFO(dev)->gen >= 4) {
6421                 if (plane_config->tiled)
6422                         offset = I915_READ(DSPTILEOFF(plane));
6423                 else
6424                         offset = I915_READ(DSPLINOFF(plane));
6425                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6426         } else {
6427                 base = I915_READ(DSPADDR(plane));
6428         }
6429         plane_config->base = base;
6430
6431         val = I915_READ(PIPESRC(pipe));
6432         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6433         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6434
6435         val = I915_READ(DSPSTRIDE(pipe));
6436         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6437
6438         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6439                                             plane_config->tiled);
6440
6441         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6442                                         aligned_height);
6443
6444         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6445                       pipe, plane, crtc->base.primary->fb->width,
6446                       crtc->base.primary->fb->height,
6447                       crtc->base.primary->fb->bits_per_pixel, base,
6448                       crtc->base.primary->fb->pitches[0],
6449                       plane_config->size);
6450
6451 }
6452
6453 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6454                                struct intel_crtc_config *pipe_config)
6455 {
6456         struct drm_device *dev = crtc->base.dev;
6457         struct drm_i915_private *dev_priv = dev->dev_private;
6458         int pipe = pipe_config->cpu_transcoder;
6459         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6460         intel_clock_t clock;
6461         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6462         int refclk = 100000;
6463
6464         mutex_lock(&dev_priv->dpio_lock);
6465         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6466         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6467         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6468         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6469         mutex_unlock(&dev_priv->dpio_lock);
6470
6471         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6472         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6473         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6474         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6475         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6476
6477         chv_clock(refclk, &clock);
6478
6479         /* clock.dot is the fast clock */
6480         pipe_config->port_clock = clock.dot / 5;
6481 }
6482
6483 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6484                                  struct intel_crtc_config *pipe_config)
6485 {
6486         struct drm_device *dev = crtc->base.dev;
6487         struct drm_i915_private *dev_priv = dev->dev_private;
6488         uint32_t tmp;
6489
6490         if (!intel_display_power_is_enabled(dev_priv,
6491                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6492                 return false;
6493
6494         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6495         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6496
6497         tmp = I915_READ(PIPECONF(crtc->pipe));
6498         if (!(tmp & PIPECONF_ENABLE))
6499                 return false;
6500
6501         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6502                 switch (tmp & PIPECONF_BPC_MASK) {
6503                 case PIPECONF_6BPC:
6504                         pipe_config->pipe_bpp = 18;
6505                         break;
6506                 case PIPECONF_8BPC:
6507                         pipe_config->pipe_bpp = 24;
6508                         break;
6509                 case PIPECONF_10BPC:
6510                         pipe_config->pipe_bpp = 30;
6511                         break;
6512                 default:
6513                         break;
6514                 }
6515         }
6516
6517         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6518                 pipe_config->limited_color_range = true;
6519
6520         if (INTEL_INFO(dev)->gen < 4)
6521                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6522
6523         intel_get_pipe_timings(crtc, pipe_config);
6524
6525         i9xx_get_pfit_config(crtc, pipe_config);
6526
6527         if (INTEL_INFO(dev)->gen >= 4) {
6528                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6529                 pipe_config->pixel_multiplier =
6530                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6531                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6532                 pipe_config->dpll_hw_state.dpll_md = tmp;
6533         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6534                 tmp = I915_READ(DPLL(crtc->pipe));
6535                 pipe_config->pixel_multiplier =
6536                         ((tmp & SDVO_MULTIPLIER_MASK)
6537                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6538         } else {
6539                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6540                  * port and will be fixed up in the encoder->get_config
6541                  * function. */
6542                 pipe_config->pixel_multiplier = 1;
6543         }
6544         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6545         if (!IS_VALLEYVIEW(dev)) {
6546                 /*
6547                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6548                  * on 830. Filter it out here so that we don't
6549                  * report errors due to that.
6550                  */
6551                 if (IS_I830(dev))
6552                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6553
6554                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6555                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6556         } else {
6557                 /* Mask out read-only status bits. */
6558                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6559                                                      DPLL_PORTC_READY_MASK |
6560                                                      DPLL_PORTB_READY_MASK);
6561         }
6562
6563         if (IS_CHERRYVIEW(dev))
6564                 chv_crtc_clock_get(crtc, pipe_config);
6565         else if (IS_VALLEYVIEW(dev))
6566                 vlv_crtc_clock_get(crtc, pipe_config);
6567         else
6568                 i9xx_crtc_clock_get(crtc, pipe_config);
6569
6570         return true;
6571 }
6572
6573 static void ironlake_init_pch_refclk(struct drm_device *dev)
6574 {
6575         struct drm_i915_private *dev_priv = dev->dev_private;
6576         struct intel_encoder *encoder;
6577         u32 val, final;
6578         bool has_lvds = false;
6579         bool has_cpu_edp = false;
6580         bool has_panel = false;
6581         bool has_ck505 = false;
6582         bool can_ssc = false;
6583
6584         /* We need to take the global config into account */
6585         for_each_intel_encoder(dev, encoder) {
6586                 switch (encoder->type) {
6587                 case INTEL_OUTPUT_LVDS:
6588                         has_panel = true;
6589                         has_lvds = true;
6590                         break;
6591                 case INTEL_OUTPUT_EDP:
6592                         has_panel = true;
6593                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6594                                 has_cpu_edp = true;
6595                         break;
6596                 }
6597         }
6598
6599         if (HAS_PCH_IBX(dev)) {
6600                 has_ck505 = dev_priv->vbt.display_clock_mode;
6601                 can_ssc = has_ck505;
6602         } else {
6603                 has_ck505 = false;
6604                 can_ssc = true;
6605         }
6606
6607         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6608                       has_panel, has_lvds, has_ck505);
6609
6610         /* Ironlake: try to setup display ref clock before DPLL
6611          * enabling. This is only under driver's control after
6612          * PCH B stepping, previous chipset stepping should be
6613          * ignoring this setting.
6614          */
6615         val = I915_READ(PCH_DREF_CONTROL);
6616
6617         /* As we must carefully and slowly disable/enable each source in turn,
6618          * compute the final state we want first and check if we need to
6619          * make any changes at all.
6620          */
6621         final = val;
6622         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6623         if (has_ck505)
6624                 final |= DREF_NONSPREAD_CK505_ENABLE;
6625         else
6626                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6627
6628         final &= ~DREF_SSC_SOURCE_MASK;
6629         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6630         final &= ~DREF_SSC1_ENABLE;
6631
6632         if (has_panel) {
6633                 final |= DREF_SSC_SOURCE_ENABLE;
6634
6635                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6636                         final |= DREF_SSC1_ENABLE;
6637
6638                 if (has_cpu_edp) {
6639                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6640                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6641                         else
6642                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6643                 } else
6644                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6645         } else {
6646                 final |= DREF_SSC_SOURCE_DISABLE;
6647                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6648         }
6649
6650         if (final == val)
6651                 return;
6652
6653         /* Always enable nonspread source */
6654         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6655
6656         if (has_ck505)
6657                 val |= DREF_NONSPREAD_CK505_ENABLE;
6658         else
6659                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6660
6661         if (has_panel) {
6662                 val &= ~DREF_SSC_SOURCE_MASK;
6663                 val |= DREF_SSC_SOURCE_ENABLE;
6664
6665                 /* SSC must be turned on before enabling the CPU output  */
6666                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6667                         DRM_DEBUG_KMS("Using SSC on panel\n");
6668                         val |= DREF_SSC1_ENABLE;
6669                 } else
6670                         val &= ~DREF_SSC1_ENABLE;
6671
6672                 /* Get SSC going before enabling the outputs */
6673                 I915_WRITE(PCH_DREF_CONTROL, val);
6674                 POSTING_READ(PCH_DREF_CONTROL);
6675                 udelay(200);
6676
6677                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6678
6679                 /* Enable CPU source on CPU attached eDP */
6680                 if (has_cpu_edp) {
6681                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6682                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6683                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6684                         } else
6685                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6686                 } else
6687                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6688
6689                 I915_WRITE(PCH_DREF_CONTROL, val);
6690                 POSTING_READ(PCH_DREF_CONTROL);
6691                 udelay(200);
6692         } else {
6693                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6694
6695                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6696
6697                 /* Turn off CPU output */
6698                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6699
6700                 I915_WRITE(PCH_DREF_CONTROL, val);
6701                 POSTING_READ(PCH_DREF_CONTROL);
6702                 udelay(200);
6703
6704                 /* Turn off the SSC source */
6705                 val &= ~DREF_SSC_SOURCE_MASK;
6706                 val |= DREF_SSC_SOURCE_DISABLE;
6707
6708                 /* Turn off SSC1 */
6709                 val &= ~DREF_SSC1_ENABLE;
6710
6711                 I915_WRITE(PCH_DREF_CONTROL, val);
6712                 POSTING_READ(PCH_DREF_CONTROL);
6713                 udelay(200);
6714         }
6715
6716         BUG_ON(val != final);
6717 }
6718
6719 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6720 {
6721         uint32_t tmp;
6722
6723         tmp = I915_READ(SOUTH_CHICKEN2);
6724         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6725         I915_WRITE(SOUTH_CHICKEN2, tmp);
6726
6727         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6728                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6729                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6730
6731         tmp = I915_READ(SOUTH_CHICKEN2);
6732         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6733         I915_WRITE(SOUTH_CHICKEN2, tmp);
6734
6735         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6736                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6737                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6738 }
6739
6740 /* WaMPhyProgramming:hsw */
6741 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6742 {
6743         uint32_t tmp;
6744
6745         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6746         tmp &= ~(0xFF << 24);
6747         tmp |= (0x12 << 24);
6748         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6749
6750         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6751         tmp |= (1 << 11);
6752         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6753
6754         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6755         tmp |= (1 << 11);
6756         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6757
6758         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6759         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6760         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6761
6762         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6763         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6764         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6765
6766         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6767         tmp &= ~(7 << 13);
6768         tmp |= (5 << 13);
6769         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6770
6771         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6772         tmp &= ~(7 << 13);
6773         tmp |= (5 << 13);
6774         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6775
6776         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6777         tmp &= ~0xFF;
6778         tmp |= 0x1C;
6779         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6780
6781         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6782         tmp &= ~0xFF;
6783         tmp |= 0x1C;
6784         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6785
6786         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6787         tmp &= ~(0xFF << 16);
6788         tmp |= (0x1C << 16);
6789         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6790
6791         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6792         tmp &= ~(0xFF << 16);
6793         tmp |= (0x1C << 16);
6794         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6795
6796         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6797         tmp |= (1 << 27);
6798         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6799
6800         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6801         tmp |= (1 << 27);
6802         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6803
6804         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6805         tmp &= ~(0xF << 28);
6806         tmp |= (4 << 28);
6807         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6808
6809         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6810         tmp &= ~(0xF << 28);
6811         tmp |= (4 << 28);
6812         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6813 }
6814
6815 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6816  * Programming" based on the parameters passed:
6817  * - Sequence to enable CLKOUT_DP
6818  * - Sequence to enable CLKOUT_DP without spread
6819  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6820  */
6821 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6822                                  bool with_fdi)
6823 {
6824         struct drm_i915_private *dev_priv = dev->dev_private;
6825         uint32_t reg, tmp;
6826
6827         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6828                 with_spread = true;
6829         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6830                  with_fdi, "LP PCH doesn't have FDI\n"))
6831                 with_fdi = false;
6832
6833         mutex_lock(&dev_priv->dpio_lock);
6834
6835         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6836         tmp &= ~SBI_SSCCTL_DISABLE;
6837         tmp |= SBI_SSCCTL_PATHALT;
6838         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6839
6840         udelay(24);
6841
6842         if (with_spread) {
6843                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6844                 tmp &= ~SBI_SSCCTL_PATHALT;
6845                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6846
6847                 if (with_fdi) {
6848                         lpt_reset_fdi_mphy(dev_priv);
6849                         lpt_program_fdi_mphy(dev_priv);
6850                 }
6851         }
6852
6853         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6854                SBI_GEN0 : SBI_DBUFF0;
6855         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6856         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6857         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6858
6859         mutex_unlock(&dev_priv->dpio_lock);
6860 }
6861
6862 /* Sequence to disable CLKOUT_DP */
6863 static void lpt_disable_clkout_dp(struct drm_device *dev)
6864 {
6865         struct drm_i915_private *dev_priv = dev->dev_private;
6866         uint32_t reg, tmp;
6867
6868         mutex_lock(&dev_priv->dpio_lock);
6869
6870         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6871                SBI_GEN0 : SBI_DBUFF0;
6872         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6873         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6874         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6875
6876         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6877         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6878                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6879                         tmp |= SBI_SSCCTL_PATHALT;
6880                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6881                         udelay(32);
6882                 }
6883                 tmp |= SBI_SSCCTL_DISABLE;
6884                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6885         }
6886
6887         mutex_unlock(&dev_priv->dpio_lock);
6888 }
6889
6890 static void lpt_init_pch_refclk(struct drm_device *dev)
6891 {
6892         struct intel_encoder *encoder;
6893         bool has_vga = false;
6894
6895         for_each_intel_encoder(dev, encoder) {
6896                 switch (encoder->type) {
6897                 case INTEL_OUTPUT_ANALOG:
6898                         has_vga = true;
6899                         break;
6900                 }
6901         }
6902
6903         if (has_vga)
6904                 lpt_enable_clkout_dp(dev, true, true);
6905         else
6906                 lpt_disable_clkout_dp(dev);
6907 }
6908
6909 /*
6910  * Initialize reference clocks when the driver loads
6911  */
6912 void intel_init_pch_refclk(struct drm_device *dev)
6913 {
6914         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6915                 ironlake_init_pch_refclk(dev);
6916         else if (HAS_PCH_LPT(dev))
6917                 lpt_init_pch_refclk(dev);
6918 }
6919
6920 static int ironlake_get_refclk(struct drm_crtc *crtc)
6921 {
6922         struct drm_device *dev = crtc->dev;
6923         struct drm_i915_private *dev_priv = dev->dev_private;
6924         struct intel_encoder *encoder;
6925         int num_connectors = 0;
6926         bool is_lvds = false;
6927
6928         for_each_encoder_on_crtc(dev, crtc, encoder) {
6929                 switch (encoder->type) {
6930                 case INTEL_OUTPUT_LVDS:
6931                         is_lvds = true;
6932                         break;
6933                 }
6934                 num_connectors++;
6935         }
6936
6937         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6938                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6939                               dev_priv->vbt.lvds_ssc_freq);
6940                 return dev_priv->vbt.lvds_ssc_freq;
6941         }
6942
6943         return 120000;
6944 }
6945
6946 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6947 {
6948         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6949         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6950         int pipe = intel_crtc->pipe;
6951         uint32_t val;
6952
6953         val = 0;
6954
6955         switch (intel_crtc->config.pipe_bpp) {
6956         case 18:
6957                 val |= PIPECONF_6BPC;
6958                 break;
6959         case 24:
6960                 val |= PIPECONF_8BPC;
6961                 break;
6962         case 30:
6963                 val |= PIPECONF_10BPC;
6964                 break;
6965         case 36:
6966                 val |= PIPECONF_12BPC;
6967                 break;
6968         default:
6969                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6970                 BUG();
6971         }
6972
6973         if (intel_crtc->config.dither)
6974                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6975
6976         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6977                 val |= PIPECONF_INTERLACED_ILK;
6978         else
6979                 val |= PIPECONF_PROGRESSIVE;
6980
6981         if (intel_crtc->config.limited_color_range)
6982                 val |= PIPECONF_COLOR_RANGE_SELECT;
6983
6984         I915_WRITE(PIPECONF(pipe), val);
6985         POSTING_READ(PIPECONF(pipe));
6986 }
6987
6988 /*
6989  * Set up the pipe CSC unit.
6990  *
6991  * Currently only full range RGB to limited range RGB conversion
6992  * is supported, but eventually this should handle various
6993  * RGB<->YCbCr scenarios as well.
6994  */
6995 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6996 {
6997         struct drm_device *dev = crtc->dev;
6998         struct drm_i915_private *dev_priv = dev->dev_private;
6999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7000         int pipe = intel_crtc->pipe;
7001         uint16_t coeff = 0x7800; /* 1.0 */
7002
7003         /*
7004          * TODO: Check what kind of values actually come out of the pipe
7005          * with these coeff/postoff values and adjust to get the best
7006          * accuracy. Perhaps we even need to take the bpc value into
7007          * consideration.
7008          */
7009
7010         if (intel_crtc->config.limited_color_range)
7011                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7012
7013         /*
7014          * GY/GU and RY/RU should be the other way around according
7015          * to BSpec, but reality doesn't agree. Just set them up in
7016          * a way that results in the correct picture.
7017          */
7018         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7019         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7020
7021         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7022         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7023
7024         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7025         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7026
7027         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7028         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7029         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7030
7031         if (INTEL_INFO(dev)->gen > 6) {
7032                 uint16_t postoff = 0;
7033
7034                 if (intel_crtc->config.limited_color_range)
7035                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7036
7037                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7038                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7039                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7040
7041                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7042         } else {
7043                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7044
7045                 if (intel_crtc->config.limited_color_range)
7046                         mode |= CSC_BLACK_SCREEN_OFFSET;
7047
7048                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7049         }
7050 }
7051
7052 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7053 {
7054         struct drm_device *dev = crtc->dev;
7055         struct drm_i915_private *dev_priv = dev->dev_private;
7056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7057         enum pipe pipe = intel_crtc->pipe;
7058         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7059         uint32_t val;
7060
7061         val = 0;
7062
7063         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7064                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7065
7066         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7067                 val |= PIPECONF_INTERLACED_ILK;
7068         else
7069                 val |= PIPECONF_PROGRESSIVE;
7070
7071         I915_WRITE(PIPECONF(cpu_transcoder), val);
7072         POSTING_READ(PIPECONF(cpu_transcoder));
7073
7074         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7075         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7076
7077         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7078                 val = 0;
7079
7080                 switch (intel_crtc->config.pipe_bpp) {
7081                 case 18:
7082                         val |= PIPEMISC_DITHER_6_BPC;
7083                         break;
7084                 case 24:
7085                         val |= PIPEMISC_DITHER_8_BPC;
7086                         break;
7087                 case 30:
7088                         val |= PIPEMISC_DITHER_10_BPC;
7089                         break;
7090                 case 36:
7091                         val |= PIPEMISC_DITHER_12_BPC;
7092                         break;
7093                 default:
7094                         /* Case prevented by pipe_config_set_bpp. */
7095                         BUG();
7096                 }
7097
7098                 if (intel_crtc->config.dither)
7099                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7100
7101                 I915_WRITE(PIPEMISC(pipe), val);
7102         }
7103 }
7104
7105 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7106                                     intel_clock_t *clock,
7107                                     bool *has_reduced_clock,
7108                                     intel_clock_t *reduced_clock)
7109 {
7110         struct drm_device *dev = crtc->dev;
7111         struct drm_i915_private *dev_priv = dev->dev_private;
7112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7113         int refclk;
7114         const intel_limit_t *limit;
7115         bool ret, is_lvds = false;
7116
7117         is_lvds = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_LVDS);
7118
7119         refclk = ironlake_get_refclk(crtc);
7120
7121         /*
7122          * Returns a set of divisors for the desired target clock with the given
7123          * refclk, or FALSE.  The returned values represent the clock equation:
7124          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7125          */
7126         limit = intel_limit(intel_crtc, refclk);
7127         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7128                                           intel_crtc->config.port_clock,
7129                                           refclk, NULL, clock);
7130         if (!ret)
7131                 return false;
7132
7133         if (is_lvds && dev_priv->lvds_downclock_avail) {
7134                 /*
7135                  * Ensure we match the reduced clock's P to the target clock.
7136                  * If the clocks don't match, we can't switch the display clock
7137                  * by using the FP0/FP1. In such case we will disable the LVDS
7138                  * downclock feature.
7139                 */
7140                 *has_reduced_clock =
7141                         dev_priv->display.find_dpll(limit, intel_crtc,
7142                                                     dev_priv->lvds_downclock,
7143                                                     refclk, clock,
7144                                                     reduced_clock);
7145         }
7146
7147         return true;
7148 }
7149
7150 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7151 {
7152         /*
7153          * Account for spread spectrum to avoid
7154          * oversubscribing the link. Max center spread
7155          * is 2.5%; use 5% for safety's sake.
7156          */
7157         u32 bps = target_clock * bpp * 21 / 20;
7158         return DIV_ROUND_UP(bps, link_bw * 8);
7159 }
7160
7161 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7162 {
7163         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7164 }
7165
7166 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7167                                       u32 *fp,
7168                                       intel_clock_t *reduced_clock, u32 *fp2)
7169 {
7170         struct drm_crtc *crtc = &intel_crtc->base;
7171         struct drm_device *dev = crtc->dev;
7172         struct drm_i915_private *dev_priv = dev->dev_private;
7173         struct intel_encoder *intel_encoder;
7174         uint32_t dpll;
7175         int factor, num_connectors = 0;
7176         bool is_lvds = false, is_sdvo = false;
7177
7178         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7179                 switch (intel_encoder->type) {
7180                 case INTEL_OUTPUT_LVDS:
7181                         is_lvds = true;
7182                         break;
7183                 case INTEL_OUTPUT_SDVO:
7184                 case INTEL_OUTPUT_HDMI:
7185                         is_sdvo = true;
7186                         break;
7187                 }
7188
7189                 num_connectors++;
7190         }
7191
7192         /* Enable autotuning of the PLL clock (if permissible) */
7193         factor = 21;
7194         if (is_lvds) {
7195                 if ((intel_panel_use_ssc(dev_priv) &&
7196                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7197                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7198                         factor = 25;
7199         } else if (intel_crtc->config.sdvo_tv_clock)
7200                 factor = 20;
7201
7202         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7203                 *fp |= FP_CB_TUNE;
7204
7205         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7206                 *fp2 |= FP_CB_TUNE;
7207
7208         dpll = 0;
7209
7210         if (is_lvds)
7211                 dpll |= DPLLB_MODE_LVDS;
7212         else
7213                 dpll |= DPLLB_MODE_DAC_SERIAL;
7214
7215         dpll |= (intel_crtc->config.pixel_multiplier - 1)
7216                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7217
7218         if (is_sdvo)
7219                 dpll |= DPLL_SDVO_HIGH_SPEED;
7220         if (intel_crtc->config.has_dp_encoder)
7221                 dpll |= DPLL_SDVO_HIGH_SPEED;
7222
7223         /* compute bitmask from p1 value */
7224         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7225         /* also FPA1 */
7226         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7227
7228         switch (intel_crtc->config.dpll.p2) {
7229         case 5:
7230                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7231                 break;
7232         case 7:
7233                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7234                 break;
7235         case 10:
7236                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7237                 break;
7238         case 14:
7239                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7240                 break;
7241         }
7242
7243         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7244                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7245         else
7246                 dpll |= PLL_REF_INPUT_DREFCLK;
7247
7248         return dpll | DPLL_VCO_ENABLE;
7249 }
7250
7251 static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
7252                                   int x, int y,
7253                                   struct drm_framebuffer *fb)
7254 {
7255         struct drm_device *dev = crtc->base.dev;
7256         intel_clock_t clock, reduced_clock;
7257         u32 dpll = 0, fp = 0, fp2 = 0;
7258         bool ok, has_reduced_clock = false;
7259         bool is_lvds = false;
7260         struct intel_shared_dpll *pll;
7261
7262         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7263
7264         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7265              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7266
7267         ok = ironlake_compute_clocks(&crtc->base, &clock,
7268                                      &has_reduced_clock, &reduced_clock);
7269         if (!ok && !crtc->config.clock_set) {
7270                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7271                 return -EINVAL;
7272         }
7273         /* Compat-code for transition, will disappear. */
7274         if (!crtc->config.clock_set) {
7275                 crtc->config.dpll.n = clock.n;
7276                 crtc->config.dpll.m1 = clock.m1;
7277                 crtc->config.dpll.m2 = clock.m2;
7278                 crtc->config.dpll.p1 = clock.p1;
7279                 crtc->config.dpll.p2 = clock.p2;
7280         }
7281
7282         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7283         if (crtc->config.has_pch_encoder) {
7284                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
7285                 if (has_reduced_clock)
7286                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7287
7288                 dpll = ironlake_compute_dpll(crtc,
7289                                              &fp, &reduced_clock,
7290                                              has_reduced_clock ? &fp2 : NULL);
7291
7292                 crtc->config.dpll_hw_state.dpll = dpll;
7293                 crtc->config.dpll_hw_state.fp0 = fp;
7294                 if (has_reduced_clock)
7295                         crtc->config.dpll_hw_state.fp1 = fp2;
7296                 else
7297                         crtc->config.dpll_hw_state.fp1 = fp;
7298
7299                 pll = intel_get_shared_dpll(crtc);
7300                 if (pll == NULL) {
7301                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7302                                          pipe_name(crtc->pipe));
7303                         return -EINVAL;
7304                 }
7305         } else
7306                 intel_put_shared_dpll(crtc);
7307
7308         if (is_lvds && has_reduced_clock && i915.powersave)
7309                 crtc->lowfreq_avail = true;
7310         else
7311                 crtc->lowfreq_avail = false;
7312
7313         return 0;
7314 }
7315
7316 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7317                                          struct intel_link_m_n *m_n)
7318 {
7319         struct drm_device *dev = crtc->base.dev;
7320         struct drm_i915_private *dev_priv = dev->dev_private;
7321         enum pipe pipe = crtc->pipe;
7322
7323         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7324         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7325         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7326                 & ~TU_SIZE_MASK;
7327         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7328         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7329                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7330 }
7331
7332 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7333                                          enum transcoder transcoder,
7334                                          struct intel_link_m_n *m_n,
7335                                          struct intel_link_m_n *m2_n2)
7336 {
7337         struct drm_device *dev = crtc->base.dev;
7338         struct drm_i915_private *dev_priv = dev->dev_private;
7339         enum pipe pipe = crtc->pipe;
7340
7341         if (INTEL_INFO(dev)->gen >= 5) {
7342                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7343                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7344                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7345                         & ~TU_SIZE_MASK;
7346                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7347                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7348                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7349                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7350                  * gen < 8) and if DRRS is supported (to make sure the
7351                  * registers are not unnecessarily read).
7352                  */
7353                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7354                         crtc->config.has_drrs) {
7355                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7356                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7357                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7358                                         & ~TU_SIZE_MASK;
7359                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7360                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7361                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7362                 }
7363         } else {
7364                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7365                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7366                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7367                         & ~TU_SIZE_MASK;
7368                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7369                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7370                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7371         }
7372 }
7373
7374 void intel_dp_get_m_n(struct intel_crtc *crtc,
7375                       struct intel_crtc_config *pipe_config)
7376 {
7377         if (crtc->config.has_pch_encoder)
7378                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7379         else
7380                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7381                                              &pipe_config->dp_m_n,
7382                                              &pipe_config->dp_m2_n2);
7383 }
7384
7385 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7386                                         struct intel_crtc_config *pipe_config)
7387 {
7388         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7389                                      &pipe_config->fdi_m_n, NULL);
7390 }
7391
7392 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7393                                      struct intel_crtc_config *pipe_config)
7394 {
7395         struct drm_device *dev = crtc->base.dev;
7396         struct drm_i915_private *dev_priv = dev->dev_private;
7397         uint32_t tmp;
7398
7399         tmp = I915_READ(PF_CTL(crtc->pipe));
7400
7401         if (tmp & PF_ENABLE) {
7402                 pipe_config->pch_pfit.enabled = true;
7403                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7404                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7405
7406                 /* We currently do not free assignements of panel fitters on
7407                  * ivb/hsw (since we don't use the higher upscaling modes which
7408                  * differentiates them) so just WARN about this case for now. */
7409                 if (IS_GEN7(dev)) {
7410                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7411                                 PF_PIPE_SEL_IVB(crtc->pipe));
7412                 }
7413         }
7414 }
7415
7416 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7417                                       struct intel_plane_config *plane_config)
7418 {
7419         struct drm_device *dev = crtc->base.dev;
7420         struct drm_i915_private *dev_priv = dev->dev_private;
7421         u32 val, base, offset;
7422         int pipe = crtc->pipe, plane = crtc->plane;
7423         int fourcc, pixel_format;
7424         int aligned_height;
7425
7426         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7427         if (!crtc->base.primary->fb) {
7428                 DRM_DEBUG_KMS("failed to alloc fb\n");
7429                 return;
7430         }
7431
7432         val = I915_READ(DSPCNTR(plane));
7433
7434         if (INTEL_INFO(dev)->gen >= 4)
7435                 if (val & DISPPLANE_TILED)
7436                         plane_config->tiled = true;
7437
7438         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7439         fourcc = intel_format_to_fourcc(pixel_format);
7440         crtc->base.primary->fb->pixel_format = fourcc;
7441         crtc->base.primary->fb->bits_per_pixel =
7442                 drm_format_plane_cpp(fourcc, 0) * 8;
7443
7444         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7445         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7446                 offset = I915_READ(DSPOFFSET(plane));
7447         } else {
7448                 if (plane_config->tiled)
7449                         offset = I915_READ(DSPTILEOFF(plane));
7450                 else
7451                         offset = I915_READ(DSPLINOFF(plane));
7452         }
7453         plane_config->base = base;
7454
7455         val = I915_READ(PIPESRC(pipe));
7456         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7457         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7458
7459         val = I915_READ(DSPSTRIDE(pipe));
7460         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7461
7462         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7463                                             plane_config->tiled);
7464
7465         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7466                                         aligned_height);
7467
7468         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7469                       pipe, plane, crtc->base.primary->fb->width,
7470                       crtc->base.primary->fb->height,
7471                       crtc->base.primary->fb->bits_per_pixel, base,
7472                       crtc->base.primary->fb->pitches[0],
7473                       plane_config->size);
7474 }
7475
7476 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7477                                      struct intel_crtc_config *pipe_config)
7478 {
7479         struct drm_device *dev = crtc->base.dev;
7480         struct drm_i915_private *dev_priv = dev->dev_private;
7481         uint32_t tmp;
7482
7483         if (!intel_display_power_is_enabled(dev_priv,
7484                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7485                 return false;
7486
7487         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7488         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7489
7490         tmp = I915_READ(PIPECONF(crtc->pipe));
7491         if (!(tmp & PIPECONF_ENABLE))
7492                 return false;
7493
7494         switch (tmp & PIPECONF_BPC_MASK) {
7495         case PIPECONF_6BPC:
7496                 pipe_config->pipe_bpp = 18;
7497                 break;
7498         case PIPECONF_8BPC:
7499                 pipe_config->pipe_bpp = 24;
7500                 break;
7501         case PIPECONF_10BPC:
7502                 pipe_config->pipe_bpp = 30;
7503                 break;
7504         case PIPECONF_12BPC:
7505                 pipe_config->pipe_bpp = 36;
7506                 break;
7507         default:
7508                 break;
7509         }
7510
7511         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7512                 pipe_config->limited_color_range = true;
7513
7514         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7515                 struct intel_shared_dpll *pll;
7516
7517                 pipe_config->has_pch_encoder = true;
7518
7519                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7520                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7521                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7522
7523                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7524
7525                 if (HAS_PCH_IBX(dev_priv->dev)) {
7526                         pipe_config->shared_dpll =
7527                                 (enum intel_dpll_id) crtc->pipe;
7528                 } else {
7529                         tmp = I915_READ(PCH_DPLL_SEL);
7530                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7531                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7532                         else
7533                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7534                 }
7535
7536                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7537
7538                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7539                                            &pipe_config->dpll_hw_state));
7540
7541                 tmp = pipe_config->dpll_hw_state.dpll;
7542                 pipe_config->pixel_multiplier =
7543                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7544                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7545
7546                 ironlake_pch_clock_get(crtc, pipe_config);
7547         } else {
7548                 pipe_config->pixel_multiplier = 1;
7549         }
7550
7551         intel_get_pipe_timings(crtc, pipe_config);
7552
7553         ironlake_get_pfit_config(crtc, pipe_config);
7554
7555         return true;
7556 }
7557
7558 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7559 {
7560         struct drm_device *dev = dev_priv->dev;
7561         struct intel_crtc *crtc;
7562
7563         for_each_intel_crtc(dev, crtc)
7564                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7565                      pipe_name(crtc->pipe));
7566
7567         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7568         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7569         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7570         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7571         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7572         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7573              "CPU PWM1 enabled\n");
7574         if (IS_HASWELL(dev))
7575                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7576                      "CPU PWM2 enabled\n");
7577         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7578              "PCH PWM1 enabled\n");
7579         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7580              "Utility pin enabled\n");
7581         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7582
7583         /*
7584          * In theory we can still leave IRQs enabled, as long as only the HPD
7585          * interrupts remain enabled. We used to check for that, but since it's
7586          * gen-specific and since we only disable LCPLL after we fully disable
7587          * the interrupts, the check below should be enough.
7588          */
7589         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7590 }
7591
7592 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7593 {
7594         struct drm_device *dev = dev_priv->dev;
7595
7596         if (IS_HASWELL(dev))
7597                 return I915_READ(D_COMP_HSW);
7598         else
7599                 return I915_READ(D_COMP_BDW);
7600 }
7601
7602 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7603 {
7604         struct drm_device *dev = dev_priv->dev;
7605
7606         if (IS_HASWELL(dev)) {
7607                 mutex_lock(&dev_priv->rps.hw_lock);
7608                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7609                                             val))
7610                         DRM_ERROR("Failed to write to D_COMP\n");
7611                 mutex_unlock(&dev_priv->rps.hw_lock);
7612         } else {
7613                 I915_WRITE(D_COMP_BDW, val);
7614                 POSTING_READ(D_COMP_BDW);
7615         }
7616 }
7617
7618 /*
7619  * This function implements pieces of two sequences from BSpec:
7620  * - Sequence for display software to disable LCPLL
7621  * - Sequence for display software to allow package C8+
7622  * The steps implemented here are just the steps that actually touch the LCPLL
7623  * register. Callers should take care of disabling all the display engine
7624  * functions, doing the mode unset, fixing interrupts, etc.
7625  */
7626 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7627                               bool switch_to_fclk, bool allow_power_down)
7628 {
7629         uint32_t val;
7630
7631         assert_can_disable_lcpll(dev_priv);
7632
7633         val = I915_READ(LCPLL_CTL);
7634
7635         if (switch_to_fclk) {
7636                 val |= LCPLL_CD_SOURCE_FCLK;
7637                 I915_WRITE(LCPLL_CTL, val);
7638
7639                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7640                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7641                         DRM_ERROR("Switching to FCLK failed\n");
7642
7643                 val = I915_READ(LCPLL_CTL);
7644         }
7645
7646         val |= LCPLL_PLL_DISABLE;
7647         I915_WRITE(LCPLL_CTL, val);
7648         POSTING_READ(LCPLL_CTL);
7649
7650         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7651                 DRM_ERROR("LCPLL still locked\n");
7652
7653         val = hsw_read_dcomp(dev_priv);
7654         val |= D_COMP_COMP_DISABLE;
7655         hsw_write_dcomp(dev_priv, val);
7656         ndelay(100);
7657
7658         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7659                      1))
7660                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7661
7662         if (allow_power_down) {
7663                 val = I915_READ(LCPLL_CTL);
7664                 val |= LCPLL_POWER_DOWN_ALLOW;
7665                 I915_WRITE(LCPLL_CTL, val);
7666                 POSTING_READ(LCPLL_CTL);
7667         }
7668 }
7669
7670 /*
7671  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7672  * source.
7673  */
7674 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7675 {
7676         uint32_t val;
7677
7678         val = I915_READ(LCPLL_CTL);
7679
7680         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7681                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7682                 return;
7683
7684         /*
7685          * Make sure we're not on PC8 state before disabling PC8, otherwise
7686          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7687          *
7688          * The other problem is that hsw_restore_lcpll() is called as part of
7689          * the runtime PM resume sequence, so we can't just call
7690          * gen6_gt_force_wake_get() because that function calls
7691          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7692          * while we are on the resume sequence. So to solve this problem we have
7693          * to call special forcewake code that doesn't touch runtime PM and
7694          * doesn't enable the forcewake delayed work.
7695          */
7696         spin_lock_irq(&dev_priv->uncore.lock);
7697         if (dev_priv->uncore.forcewake_count++ == 0)
7698                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7699         spin_unlock_irq(&dev_priv->uncore.lock);
7700
7701         if (val & LCPLL_POWER_DOWN_ALLOW) {
7702                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7703                 I915_WRITE(LCPLL_CTL, val);
7704                 POSTING_READ(LCPLL_CTL);
7705         }
7706
7707         val = hsw_read_dcomp(dev_priv);
7708         val |= D_COMP_COMP_FORCE;
7709         val &= ~D_COMP_COMP_DISABLE;
7710         hsw_write_dcomp(dev_priv, val);
7711
7712         val = I915_READ(LCPLL_CTL);
7713         val &= ~LCPLL_PLL_DISABLE;
7714         I915_WRITE(LCPLL_CTL, val);
7715
7716         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7717                 DRM_ERROR("LCPLL not locked yet\n");
7718
7719         if (val & LCPLL_CD_SOURCE_FCLK) {
7720                 val = I915_READ(LCPLL_CTL);
7721                 val &= ~LCPLL_CD_SOURCE_FCLK;
7722                 I915_WRITE(LCPLL_CTL, val);
7723
7724                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7725                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7726                         DRM_ERROR("Switching back to LCPLL failed\n");
7727         }
7728
7729         /* See the big comment above. */
7730         spin_lock_irq(&dev_priv->uncore.lock);
7731         if (--dev_priv->uncore.forcewake_count == 0)
7732                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7733         spin_unlock_irq(&dev_priv->uncore.lock);
7734 }
7735
7736 /*
7737  * Package states C8 and deeper are really deep PC states that can only be
7738  * reached when all the devices on the system allow it, so even if the graphics
7739  * device allows PC8+, it doesn't mean the system will actually get to these
7740  * states. Our driver only allows PC8+ when going into runtime PM.
7741  *
7742  * The requirements for PC8+ are that all the outputs are disabled, the power
7743  * well is disabled and most interrupts are disabled, and these are also
7744  * requirements for runtime PM. When these conditions are met, we manually do
7745  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7746  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7747  * hang the machine.
7748  *
7749  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7750  * the state of some registers, so when we come back from PC8+ we need to
7751  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7752  * need to take care of the registers kept by RC6. Notice that this happens even
7753  * if we don't put the device in PCI D3 state (which is what currently happens
7754  * because of the runtime PM support).
7755  *
7756  * For more, read "Display Sequences for Package C8" on the hardware
7757  * documentation.
7758  */
7759 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7760 {
7761         struct drm_device *dev = dev_priv->dev;
7762         uint32_t val;
7763
7764         DRM_DEBUG_KMS("Enabling package C8+\n");
7765
7766         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7767                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7768                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7769                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7770         }
7771
7772         lpt_disable_clkout_dp(dev);
7773         hsw_disable_lcpll(dev_priv, true, true);
7774 }
7775
7776 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7777 {
7778         struct drm_device *dev = dev_priv->dev;
7779         uint32_t val;
7780
7781         DRM_DEBUG_KMS("Disabling package C8+\n");
7782
7783         hsw_restore_lcpll(dev_priv);
7784         lpt_init_pch_refclk(dev);
7785
7786         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7787                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7788                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7789                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7790         }
7791
7792         intel_prepare_ddi(dev);
7793 }
7794
7795 static void snb_modeset_global_resources(struct drm_device *dev)
7796 {
7797         modeset_update_crtc_power_domains(dev);
7798 }
7799
7800 static void haswell_modeset_global_resources(struct drm_device *dev)
7801 {
7802         modeset_update_crtc_power_domains(dev);
7803 }
7804
7805 static int haswell_crtc_mode_set(struct intel_crtc *crtc,
7806                                  int x, int y,
7807                                  struct drm_framebuffer *fb)
7808 {
7809         if (!intel_ddi_pll_select(crtc))
7810                 return -EINVAL;
7811
7812         crtc->lowfreq_avail = false;
7813
7814         return 0;
7815 }
7816
7817 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7818                                 enum port port,
7819                                 struct intel_crtc_config *pipe_config)
7820 {
7821         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7822
7823         switch (pipe_config->ddi_pll_sel) {
7824         case PORT_CLK_SEL_WRPLL1:
7825                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7826                 break;
7827         case PORT_CLK_SEL_WRPLL2:
7828                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7829                 break;
7830         }
7831 }
7832
7833 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7834                                        struct intel_crtc_config *pipe_config)
7835 {
7836         struct drm_device *dev = crtc->base.dev;
7837         struct drm_i915_private *dev_priv = dev->dev_private;
7838         struct intel_shared_dpll *pll;
7839         enum port port;
7840         uint32_t tmp;
7841
7842         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7843
7844         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7845
7846         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7847
7848         if (pipe_config->shared_dpll >= 0) {
7849                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7850
7851                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7852                                            &pipe_config->dpll_hw_state));
7853         }
7854
7855         /*
7856          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7857          * DDI E. So just check whether this pipe is wired to DDI E and whether
7858          * the PCH transcoder is on.
7859          */
7860         if (INTEL_INFO(dev)->gen < 9 &&
7861             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7862                 pipe_config->has_pch_encoder = true;
7863
7864                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7865                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7866                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7867
7868                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7869         }
7870 }
7871
7872 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7873                                     struct intel_crtc_config *pipe_config)
7874 {
7875         struct drm_device *dev = crtc->base.dev;
7876         struct drm_i915_private *dev_priv = dev->dev_private;
7877         enum intel_display_power_domain pfit_domain;
7878         uint32_t tmp;
7879
7880         if (!intel_display_power_is_enabled(dev_priv,
7881                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7882                 return false;
7883
7884         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7885         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7886
7887         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7888         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7889                 enum pipe trans_edp_pipe;
7890                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7891                 default:
7892                         WARN(1, "unknown pipe linked to edp transcoder\n");
7893                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7894                 case TRANS_DDI_EDP_INPUT_A_ON:
7895                         trans_edp_pipe = PIPE_A;
7896                         break;
7897                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7898                         trans_edp_pipe = PIPE_B;
7899                         break;
7900                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7901                         trans_edp_pipe = PIPE_C;
7902                         break;
7903                 }
7904
7905                 if (trans_edp_pipe == crtc->pipe)
7906                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7907         }
7908
7909         if (!intel_display_power_is_enabled(dev_priv,
7910                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7911                 return false;
7912
7913         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7914         if (!(tmp & PIPECONF_ENABLE))
7915                 return false;
7916
7917         haswell_get_ddi_port_state(crtc, pipe_config);
7918
7919         intel_get_pipe_timings(crtc, pipe_config);
7920
7921         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7922         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
7923                 ironlake_get_pfit_config(crtc, pipe_config);
7924
7925         if (IS_HASWELL(dev))
7926                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7927                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7928
7929         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
7930                 pipe_config->pixel_multiplier =
7931                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
7932         } else {
7933                 pipe_config->pixel_multiplier = 1;
7934         }
7935
7936         return true;
7937 }
7938
7939 static struct {
7940         int clock;
7941         u32 config;
7942 } hdmi_audio_clock[] = {
7943         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7944         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7945         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7946         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7947         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7948         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7949         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7950         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7951         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7952         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7953 };
7954
7955 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7956 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7957 {
7958         int i;
7959
7960         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7961                 if (mode->clock == hdmi_audio_clock[i].clock)
7962                         break;
7963         }
7964
7965         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7966                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7967                 i = 1;
7968         }
7969
7970         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7971                       hdmi_audio_clock[i].clock,
7972                       hdmi_audio_clock[i].config);
7973
7974         return hdmi_audio_clock[i].config;
7975 }
7976
7977 static bool intel_eld_uptodate(struct drm_connector *connector,
7978                                int reg_eldv, uint32_t bits_eldv,
7979                                int reg_elda, uint32_t bits_elda,
7980                                int reg_edid)
7981 {
7982         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7983         uint8_t *eld = connector->eld;
7984         uint32_t i;
7985
7986         i = I915_READ(reg_eldv);
7987         i &= bits_eldv;
7988
7989         if (!eld[0])
7990                 return !i;
7991
7992         if (!i)
7993                 return false;
7994
7995         i = I915_READ(reg_elda);
7996         i &= ~bits_elda;
7997         I915_WRITE(reg_elda, i);
7998
7999         for (i = 0; i < eld[2]; i++)
8000                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
8001                         return false;
8002
8003         return true;
8004 }
8005
8006 static void g4x_write_eld(struct drm_connector *connector,
8007                           struct drm_crtc *crtc,
8008                           struct drm_display_mode *mode)
8009 {
8010         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8011         uint8_t *eld = connector->eld;
8012         uint32_t eldv;
8013         uint32_t len;
8014         uint32_t i;
8015
8016         i = I915_READ(G4X_AUD_VID_DID);
8017
8018         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
8019                 eldv = G4X_ELDV_DEVCL_DEVBLC;
8020         else
8021                 eldv = G4X_ELDV_DEVCTG;
8022
8023         if (intel_eld_uptodate(connector,
8024                                G4X_AUD_CNTL_ST, eldv,
8025                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
8026                                G4X_HDMIW_HDMIEDID))
8027                 return;
8028
8029         i = I915_READ(G4X_AUD_CNTL_ST);
8030         i &= ~(eldv | G4X_ELD_ADDR);
8031         len = (i >> 9) & 0x1f;          /* ELD buffer size */
8032         I915_WRITE(G4X_AUD_CNTL_ST, i);
8033
8034         if (!eld[0])
8035                 return;
8036
8037         len = min_t(uint8_t, eld[2], len);
8038         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8039         for (i = 0; i < len; i++)
8040                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
8041
8042         i = I915_READ(G4X_AUD_CNTL_ST);
8043         i |= eldv;
8044         I915_WRITE(G4X_AUD_CNTL_ST, i);
8045 }
8046
8047 static void haswell_write_eld(struct drm_connector *connector,
8048                               struct drm_crtc *crtc,
8049                               struct drm_display_mode *mode)
8050 {
8051         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8053         uint8_t *eld = connector->eld;
8054         uint32_t eldv;
8055         uint32_t i;
8056         int len;
8057         int pipe = to_intel_crtc(crtc)->pipe;
8058         int tmp;
8059
8060         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
8061         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
8062         int aud_config = HSW_AUD_CFG(pipe);
8063         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
8064
8065         /* Audio output enable */
8066         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8067         tmp = I915_READ(aud_cntrl_st2);
8068         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
8069         I915_WRITE(aud_cntrl_st2, tmp);
8070         POSTING_READ(aud_cntrl_st2);
8071
8072         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
8073
8074         /* Set ELD valid state */
8075         tmp = I915_READ(aud_cntrl_st2);
8076         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
8077         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
8078         I915_WRITE(aud_cntrl_st2, tmp);
8079         tmp = I915_READ(aud_cntrl_st2);
8080         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
8081
8082         /* Enable HDMI mode */
8083         tmp = I915_READ(aud_config);
8084         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
8085         /* clear N_programing_enable and N_value_index */
8086         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8087         I915_WRITE(aud_config, tmp);
8088
8089         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8090
8091         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8092
8093         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8094                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8095                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
8096                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8097         } else {
8098                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8099         }
8100
8101         if (intel_eld_uptodate(connector,
8102                                aud_cntrl_st2, eldv,
8103                                aud_cntl_st, IBX_ELD_ADDRESS,
8104                                hdmiw_hdmiedid))
8105                 return;
8106
8107         i = I915_READ(aud_cntrl_st2);
8108         i &= ~eldv;
8109         I915_WRITE(aud_cntrl_st2, i);
8110
8111         if (!eld[0])
8112                 return;
8113
8114         i = I915_READ(aud_cntl_st);
8115         i &= ~IBX_ELD_ADDRESS;
8116         I915_WRITE(aud_cntl_st, i);
8117         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
8118         DRM_DEBUG_DRIVER("port num:%d\n", i);
8119
8120         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
8121         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8122         for (i = 0; i < len; i++)
8123                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8124
8125         i = I915_READ(aud_cntrl_st2);
8126         i |= eldv;
8127         I915_WRITE(aud_cntrl_st2, i);
8128
8129 }
8130
8131 static void ironlake_write_eld(struct drm_connector *connector,
8132                                struct drm_crtc *crtc,
8133                                struct drm_display_mode *mode)
8134 {
8135         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8137         uint8_t *eld = connector->eld;
8138         uint32_t eldv;
8139         uint32_t i;
8140         int len;
8141         int hdmiw_hdmiedid;
8142         int aud_config;
8143         int aud_cntl_st;
8144         int aud_cntrl_st2;
8145         int pipe = to_intel_crtc(crtc)->pipe;
8146
8147         if (HAS_PCH_IBX(connector->dev)) {
8148                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8149                 aud_config = IBX_AUD_CFG(pipe);
8150                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8151                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8152         } else if (IS_VALLEYVIEW(connector->dev)) {
8153                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8154                 aud_config = VLV_AUD_CFG(pipe);
8155                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8156                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8157         } else {
8158                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8159                 aud_config = CPT_AUD_CFG(pipe);
8160                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8161                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8162         }
8163
8164         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8165
8166         if (IS_VALLEYVIEW(connector->dev))  {
8167                 struct intel_encoder *intel_encoder;
8168                 struct intel_digital_port *intel_dig_port;
8169
8170                 intel_encoder = intel_attached_encoder(connector);
8171                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8172                 i = intel_dig_port->port;
8173         } else {
8174                 i = I915_READ(aud_cntl_st);
8175                 i = (i >> 29) & DIP_PORT_SEL_MASK;
8176                 /* DIP_Port_Select, 0x1 = PortB */
8177         }
8178
8179         if (!i) {
8180                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8181                 /* operate blindly on all ports */
8182                 eldv = IBX_ELD_VALIDB;
8183                 eldv |= IBX_ELD_VALIDB << 4;
8184                 eldv |= IBX_ELD_VALIDB << 8;
8185         } else {
8186                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8187                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8188         }
8189
8190         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8191                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8192                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
8193                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8194         } else {
8195                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8196         }
8197
8198         if (intel_eld_uptodate(connector,
8199                                aud_cntrl_st2, eldv,
8200                                aud_cntl_st, IBX_ELD_ADDRESS,
8201                                hdmiw_hdmiedid))
8202                 return;
8203
8204         i = I915_READ(aud_cntrl_st2);
8205         i &= ~eldv;
8206         I915_WRITE(aud_cntrl_st2, i);
8207
8208         if (!eld[0])
8209                 return;
8210
8211         i = I915_READ(aud_cntl_st);
8212         i &= ~IBX_ELD_ADDRESS;
8213         I915_WRITE(aud_cntl_st, i);
8214
8215         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
8216         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8217         for (i = 0; i < len; i++)
8218                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8219
8220         i = I915_READ(aud_cntrl_st2);
8221         i |= eldv;
8222         I915_WRITE(aud_cntrl_st2, i);
8223 }
8224
8225 void intel_write_eld(struct drm_encoder *encoder,
8226                      struct drm_display_mode *mode)
8227 {
8228         struct drm_crtc *crtc = encoder->crtc;
8229         struct drm_connector *connector;
8230         struct drm_device *dev = encoder->dev;
8231         struct drm_i915_private *dev_priv = dev->dev_private;
8232
8233         connector = drm_select_eld(encoder, mode);
8234         if (!connector)
8235                 return;
8236
8237         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8238                          connector->base.id,
8239                          connector->name,
8240                          connector->encoder->base.id,
8241                          connector->encoder->name);
8242
8243         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8244
8245         if (dev_priv->display.write_eld)
8246                 dev_priv->display.write_eld(connector, crtc, mode);
8247 }
8248
8249 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8250 {
8251         struct drm_device *dev = crtc->dev;
8252         struct drm_i915_private *dev_priv = dev->dev_private;
8253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8254         uint32_t cntl = 0, size = 0;
8255
8256         if (base) {
8257                 unsigned int width = intel_crtc->cursor_width;
8258                 unsigned int height = intel_crtc->cursor_height;
8259                 unsigned int stride = roundup_pow_of_two(width) * 4;
8260
8261                 switch (stride) {
8262                 default:
8263                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8264                                   width, stride);
8265                         stride = 256;
8266                         /* fallthrough */
8267                 case 256:
8268                 case 512:
8269                 case 1024:
8270                 case 2048:
8271                         break;
8272                 }
8273
8274                 cntl |= CURSOR_ENABLE |
8275                         CURSOR_GAMMA_ENABLE |
8276                         CURSOR_FORMAT_ARGB |
8277                         CURSOR_STRIDE(stride);
8278
8279                 size = (height << 12) | width;
8280         }
8281
8282         if (intel_crtc->cursor_cntl != 0 &&
8283             (intel_crtc->cursor_base != base ||
8284              intel_crtc->cursor_size != size ||
8285              intel_crtc->cursor_cntl != cntl)) {
8286                 /* On these chipsets we can only modify the base/size/stride
8287                  * whilst the cursor is disabled.
8288                  */
8289                 I915_WRITE(_CURACNTR, 0);
8290                 POSTING_READ(_CURACNTR);
8291                 intel_crtc->cursor_cntl = 0;
8292         }
8293
8294         if (intel_crtc->cursor_base != base) {
8295                 I915_WRITE(_CURABASE, base);
8296                 intel_crtc->cursor_base = base;
8297         }
8298
8299         if (intel_crtc->cursor_size != size) {
8300                 I915_WRITE(CURSIZE, size);
8301                 intel_crtc->cursor_size = size;
8302         }
8303
8304         if (intel_crtc->cursor_cntl != cntl) {
8305                 I915_WRITE(_CURACNTR, cntl);
8306                 POSTING_READ(_CURACNTR);
8307                 intel_crtc->cursor_cntl = cntl;
8308         }
8309 }
8310
8311 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8312 {
8313         struct drm_device *dev = crtc->dev;
8314         struct drm_i915_private *dev_priv = dev->dev_private;
8315         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8316         int pipe = intel_crtc->pipe;
8317         uint32_t cntl;
8318
8319         cntl = 0;
8320         if (base) {
8321                 cntl = MCURSOR_GAMMA_ENABLE;
8322                 switch (intel_crtc->cursor_width) {
8323                         case 64:
8324                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8325                                 break;
8326                         case 128:
8327                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8328                                 break;
8329                         case 256:
8330                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8331                                 break;
8332                         default:
8333                                 WARN_ON(1);
8334                                 return;
8335                 }
8336                 cntl |= pipe << 28; /* Connect to correct pipe */
8337
8338                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8339                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8340         }
8341
8342         if (intel_crtc->cursor_cntl != cntl) {
8343                 I915_WRITE(CURCNTR(pipe), cntl);
8344                 POSTING_READ(CURCNTR(pipe));
8345                 intel_crtc->cursor_cntl = cntl;
8346         }
8347
8348         /* and commit changes on next vblank */
8349         I915_WRITE(CURBASE(pipe), base);
8350         POSTING_READ(CURBASE(pipe));
8351
8352         intel_crtc->cursor_base = base;
8353 }
8354
8355 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8356 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8357                                      bool on)
8358 {
8359         struct drm_device *dev = crtc->dev;
8360         struct drm_i915_private *dev_priv = dev->dev_private;
8361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8362         int pipe = intel_crtc->pipe;
8363         int x = crtc->cursor_x;
8364         int y = crtc->cursor_y;
8365         u32 base = 0, pos = 0;
8366
8367         if (on)
8368                 base = intel_crtc->cursor_addr;
8369
8370         if (x >= intel_crtc->config.pipe_src_w)
8371                 base = 0;
8372
8373         if (y >= intel_crtc->config.pipe_src_h)
8374                 base = 0;
8375
8376         if (x < 0) {
8377                 if (x + intel_crtc->cursor_width <= 0)
8378                         base = 0;
8379
8380                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8381                 x = -x;
8382         }
8383         pos |= x << CURSOR_X_SHIFT;
8384
8385         if (y < 0) {
8386                 if (y + intel_crtc->cursor_height <= 0)
8387                         base = 0;
8388
8389                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8390                 y = -y;
8391         }
8392         pos |= y << CURSOR_Y_SHIFT;
8393
8394         if (base == 0 && intel_crtc->cursor_base == 0)
8395                 return;
8396
8397         I915_WRITE(CURPOS(pipe), pos);
8398
8399         if (IS_845G(dev) || IS_I865G(dev))
8400                 i845_update_cursor(crtc, base);
8401         else
8402                 i9xx_update_cursor(crtc, base);
8403 }
8404
8405 static bool cursor_size_ok(struct drm_device *dev,
8406                            uint32_t width, uint32_t height)
8407 {
8408         if (width == 0 || height == 0)
8409                 return false;
8410
8411         /*
8412          * 845g/865g are special in that they are only limited by
8413          * the width of their cursors, the height is arbitrary up to
8414          * the precision of the register. Everything else requires
8415          * square cursors, limited to a few power-of-two sizes.
8416          */
8417         if (IS_845G(dev) || IS_I865G(dev)) {
8418                 if ((width & 63) != 0)
8419                         return false;
8420
8421                 if (width > (IS_845G(dev) ? 64 : 512))
8422                         return false;
8423
8424                 if (height > 1023)
8425                         return false;
8426         } else {
8427                 switch (width | height) {
8428                 case 256:
8429                 case 128:
8430                         if (IS_GEN2(dev))
8431                                 return false;
8432                 case 64:
8433                         break;
8434                 default:
8435                         return false;
8436                 }
8437         }
8438
8439         return true;
8440 }
8441
8442 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8443                                      struct drm_i915_gem_object *obj,
8444                                      uint32_t width, uint32_t height)
8445 {
8446         struct drm_device *dev = crtc->dev;
8447         struct drm_i915_private *dev_priv = dev->dev_private;
8448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8449         enum pipe pipe = intel_crtc->pipe;
8450         unsigned old_width;
8451         uint32_t addr;
8452         int ret;
8453
8454         /* if we want to turn off the cursor ignore width and height */
8455         if (!obj) {
8456                 DRM_DEBUG_KMS("cursor off\n");
8457                 addr = 0;
8458                 mutex_lock(&dev->struct_mutex);
8459                 goto finish;
8460         }
8461
8462         /* we only need to pin inside GTT if cursor is non-phy */
8463         mutex_lock(&dev->struct_mutex);
8464         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8465                 unsigned alignment;
8466
8467                 /*
8468                  * Global gtt pte registers are special registers which actually
8469                  * forward writes to a chunk of system memory. Which means that
8470                  * there is no risk that the register values disappear as soon
8471                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8472                  * only the pin/unpin/fence and not more.
8473                  */
8474                 intel_runtime_pm_get(dev_priv);
8475
8476                 /* Note that the w/a also requires 2 PTE of padding following
8477                  * the bo. We currently fill all unused PTE with the shadow
8478                  * page and so we should always have valid PTE following the
8479                  * cursor preventing the VT-d warning.
8480                  */
8481                 alignment = 0;
8482                 if (need_vtd_wa(dev))
8483                         alignment = 64*1024;
8484
8485                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8486                 if (ret) {
8487                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8488                         intel_runtime_pm_put(dev_priv);
8489                         goto fail_locked;
8490                 }
8491
8492                 ret = i915_gem_object_put_fence(obj);
8493                 if (ret) {
8494                         DRM_DEBUG_KMS("failed to release fence for cursor");
8495                         intel_runtime_pm_put(dev_priv);
8496                         goto fail_unpin;
8497                 }
8498
8499                 addr = i915_gem_obj_ggtt_offset(obj);
8500
8501                 intel_runtime_pm_put(dev_priv);
8502         } else {
8503                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8504                 ret = i915_gem_object_attach_phys(obj, align);
8505                 if (ret) {
8506                         DRM_DEBUG_KMS("failed to attach phys object\n");
8507                         goto fail_locked;
8508                 }
8509                 addr = obj->phys_handle->busaddr;
8510         }
8511
8512  finish:
8513         if (intel_crtc->cursor_bo) {
8514                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8515                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8516         }
8517
8518         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8519                           INTEL_FRONTBUFFER_CURSOR(pipe));
8520         mutex_unlock(&dev->struct_mutex);
8521
8522         old_width = intel_crtc->cursor_width;
8523
8524         intel_crtc->cursor_addr = addr;
8525         intel_crtc->cursor_bo = obj;
8526         intel_crtc->cursor_width = width;
8527         intel_crtc->cursor_height = height;
8528
8529         if (intel_crtc->active) {
8530                 if (old_width != width)
8531                         intel_update_watermarks(crtc);
8532                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8533         }
8534
8535         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8536
8537         return 0;
8538 fail_unpin:
8539         i915_gem_object_unpin_from_display_plane(obj);
8540 fail_locked:
8541         mutex_unlock(&dev->struct_mutex);
8542         return ret;
8543 }
8544
8545 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8546                                  u16 *blue, uint32_t start, uint32_t size)
8547 {
8548         int end = (start + size > 256) ? 256 : start + size, i;
8549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8550
8551         for (i = start; i < end; i++) {
8552                 intel_crtc->lut_r[i] = red[i] >> 8;
8553                 intel_crtc->lut_g[i] = green[i] >> 8;
8554                 intel_crtc->lut_b[i] = blue[i] >> 8;
8555         }
8556
8557         intel_crtc_load_lut(crtc);
8558 }
8559
8560 /* VESA 640x480x72Hz mode to set on the pipe */
8561 static struct drm_display_mode load_detect_mode = {
8562         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8563                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8564 };
8565
8566 struct drm_framebuffer *
8567 __intel_framebuffer_create(struct drm_device *dev,
8568                            struct drm_mode_fb_cmd2 *mode_cmd,
8569                            struct drm_i915_gem_object *obj)
8570 {
8571         struct intel_framebuffer *intel_fb;
8572         int ret;
8573
8574         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8575         if (!intel_fb) {
8576                 drm_gem_object_unreference_unlocked(&obj->base);
8577                 return ERR_PTR(-ENOMEM);
8578         }
8579
8580         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8581         if (ret)
8582                 goto err;
8583
8584         return &intel_fb->base;
8585 err:
8586         drm_gem_object_unreference_unlocked(&obj->base);
8587         kfree(intel_fb);
8588
8589         return ERR_PTR(ret);
8590 }
8591
8592 static struct drm_framebuffer *
8593 intel_framebuffer_create(struct drm_device *dev,
8594                          struct drm_mode_fb_cmd2 *mode_cmd,
8595                          struct drm_i915_gem_object *obj)
8596 {
8597         struct drm_framebuffer *fb;
8598         int ret;
8599
8600         ret = i915_mutex_lock_interruptible(dev);
8601         if (ret)
8602                 return ERR_PTR(ret);
8603         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8604         mutex_unlock(&dev->struct_mutex);
8605
8606         return fb;
8607 }
8608
8609 static u32
8610 intel_framebuffer_pitch_for_width(int width, int bpp)
8611 {
8612         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8613         return ALIGN(pitch, 64);
8614 }
8615
8616 static u32
8617 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8618 {
8619         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8620         return PAGE_ALIGN(pitch * mode->vdisplay);
8621 }
8622
8623 static struct drm_framebuffer *
8624 intel_framebuffer_create_for_mode(struct drm_device *dev,
8625                                   struct drm_display_mode *mode,
8626                                   int depth, int bpp)
8627 {
8628         struct drm_i915_gem_object *obj;
8629         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8630
8631         obj = i915_gem_alloc_object(dev,
8632                                     intel_framebuffer_size_for_mode(mode, bpp));
8633         if (obj == NULL)
8634                 return ERR_PTR(-ENOMEM);
8635
8636         mode_cmd.width = mode->hdisplay;
8637         mode_cmd.height = mode->vdisplay;
8638         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8639                                                                 bpp);
8640         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8641
8642         return intel_framebuffer_create(dev, &mode_cmd, obj);
8643 }
8644
8645 static struct drm_framebuffer *
8646 mode_fits_in_fbdev(struct drm_device *dev,
8647                    struct drm_display_mode *mode)
8648 {
8649 #ifdef CONFIG_DRM_I915_FBDEV
8650         struct drm_i915_private *dev_priv = dev->dev_private;
8651         struct drm_i915_gem_object *obj;
8652         struct drm_framebuffer *fb;
8653
8654         if (!dev_priv->fbdev)
8655                 return NULL;
8656
8657         if (!dev_priv->fbdev->fb)
8658                 return NULL;
8659
8660         obj = dev_priv->fbdev->fb->obj;
8661         BUG_ON(!obj);
8662
8663         fb = &dev_priv->fbdev->fb->base;
8664         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8665                                                                fb->bits_per_pixel))
8666                 return NULL;
8667
8668         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8669                 return NULL;
8670
8671         return fb;
8672 #else
8673         return NULL;
8674 #endif
8675 }
8676
8677 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8678                                 struct drm_display_mode *mode,
8679                                 struct intel_load_detect_pipe *old,
8680                                 struct drm_modeset_acquire_ctx *ctx)
8681 {
8682         struct intel_crtc *intel_crtc;
8683         struct intel_encoder *intel_encoder =
8684                 intel_attached_encoder(connector);
8685         struct drm_crtc *possible_crtc;
8686         struct drm_encoder *encoder = &intel_encoder->base;
8687         struct drm_crtc *crtc = NULL;
8688         struct drm_device *dev = encoder->dev;
8689         struct drm_framebuffer *fb;
8690         struct drm_mode_config *config = &dev->mode_config;
8691         int ret, i = -1;
8692
8693         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8694                       connector->base.id, connector->name,
8695                       encoder->base.id, encoder->name);
8696
8697 retry:
8698         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8699         if (ret)
8700                 goto fail_unlock;
8701
8702         /*
8703          * Algorithm gets a little messy:
8704          *
8705          *   - if the connector already has an assigned crtc, use it (but make
8706          *     sure it's on first)
8707          *
8708          *   - try to find the first unused crtc that can drive this connector,
8709          *     and use that if we find one
8710          */
8711
8712         /* See if we already have a CRTC for this connector */
8713         if (encoder->crtc) {
8714                 crtc = encoder->crtc;
8715
8716                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8717                 if (ret)
8718                         goto fail_unlock;
8719
8720                 old->dpms_mode = connector->dpms;
8721                 old->load_detect_temp = false;
8722
8723                 /* Make sure the crtc and connector are running */
8724                 if (connector->dpms != DRM_MODE_DPMS_ON)
8725                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8726
8727                 return true;
8728         }
8729
8730         /* Find an unused one (if possible) */
8731         for_each_crtc(dev, possible_crtc) {
8732                 i++;
8733                 if (!(encoder->possible_crtcs & (1 << i)))
8734                         continue;
8735                 if (possible_crtc->enabled)
8736                         continue;
8737                 /* This can occur when applying the pipe A quirk on resume. */
8738                 if (to_intel_crtc(possible_crtc)->new_enabled)
8739                         continue;
8740
8741                 crtc = possible_crtc;
8742                 break;
8743         }
8744
8745         /*
8746          * If we didn't find an unused CRTC, don't use any.
8747          */
8748         if (!crtc) {
8749                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8750                 goto fail_unlock;
8751         }
8752
8753         ret = drm_modeset_lock(&crtc->mutex, ctx);
8754         if (ret)
8755                 goto fail_unlock;
8756         intel_encoder->new_crtc = to_intel_crtc(crtc);
8757         to_intel_connector(connector)->new_encoder = intel_encoder;
8758
8759         intel_crtc = to_intel_crtc(crtc);
8760         intel_crtc->new_enabled = true;
8761         intel_crtc->new_config = &intel_crtc->config;
8762         old->dpms_mode = connector->dpms;
8763         old->load_detect_temp = true;
8764         old->release_fb = NULL;
8765
8766         if (!mode)
8767                 mode = &load_detect_mode;
8768
8769         /* We need a framebuffer large enough to accommodate all accesses
8770          * that the plane may generate whilst we perform load detection.
8771          * We can not rely on the fbcon either being present (we get called
8772          * during its initialisation to detect all boot displays, or it may
8773          * not even exist) or that it is large enough to satisfy the
8774          * requested mode.
8775          */
8776         fb = mode_fits_in_fbdev(dev, mode);
8777         if (fb == NULL) {
8778                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8779                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8780                 old->release_fb = fb;
8781         } else
8782                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8783         if (IS_ERR(fb)) {
8784                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8785                 goto fail;
8786         }
8787
8788         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8789                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8790                 if (old->release_fb)
8791                         old->release_fb->funcs->destroy(old->release_fb);
8792                 goto fail;
8793         }
8794
8795         /* let the connector get through one full cycle before testing */
8796         intel_wait_for_vblank(dev, intel_crtc->pipe);
8797         return true;
8798
8799  fail:
8800         intel_crtc->new_enabled = crtc->enabled;
8801         if (intel_crtc->new_enabled)
8802                 intel_crtc->new_config = &intel_crtc->config;
8803         else
8804                 intel_crtc->new_config = NULL;
8805 fail_unlock:
8806         if (ret == -EDEADLK) {
8807                 drm_modeset_backoff(ctx);
8808                 goto retry;
8809         }
8810
8811         return false;
8812 }
8813
8814 void intel_release_load_detect_pipe(struct drm_connector *connector,
8815                                     struct intel_load_detect_pipe *old)
8816 {
8817         struct intel_encoder *intel_encoder =
8818                 intel_attached_encoder(connector);
8819         struct drm_encoder *encoder = &intel_encoder->base;
8820         struct drm_crtc *crtc = encoder->crtc;
8821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8822
8823         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8824                       connector->base.id, connector->name,
8825                       encoder->base.id, encoder->name);
8826
8827         if (old->load_detect_temp) {
8828                 to_intel_connector(connector)->new_encoder = NULL;
8829                 intel_encoder->new_crtc = NULL;
8830                 intel_crtc->new_enabled = false;
8831                 intel_crtc->new_config = NULL;
8832                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8833
8834                 if (old->release_fb) {
8835                         drm_framebuffer_unregister_private(old->release_fb);
8836                         drm_framebuffer_unreference(old->release_fb);
8837                 }
8838
8839                 return;
8840         }
8841
8842         /* Switch crtc and encoder back off if necessary */
8843         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8844                 connector->funcs->dpms(connector, old->dpms_mode);
8845 }
8846
8847 static int i9xx_pll_refclk(struct drm_device *dev,
8848                            const struct intel_crtc_config *pipe_config)
8849 {
8850         struct drm_i915_private *dev_priv = dev->dev_private;
8851         u32 dpll = pipe_config->dpll_hw_state.dpll;
8852
8853         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8854                 return dev_priv->vbt.lvds_ssc_freq;
8855         else if (HAS_PCH_SPLIT(dev))
8856                 return 120000;
8857         else if (!IS_GEN2(dev))
8858                 return 96000;
8859         else
8860                 return 48000;
8861 }
8862
8863 /* Returns the clock of the currently programmed mode of the given pipe. */
8864 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8865                                 struct intel_crtc_config *pipe_config)
8866 {
8867         struct drm_device *dev = crtc->base.dev;
8868         struct drm_i915_private *dev_priv = dev->dev_private;
8869         int pipe = pipe_config->cpu_transcoder;
8870         u32 dpll = pipe_config->dpll_hw_state.dpll;
8871         u32 fp;
8872         intel_clock_t clock;
8873         int refclk = i9xx_pll_refclk(dev, pipe_config);
8874
8875         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8876                 fp = pipe_config->dpll_hw_state.fp0;
8877         else
8878                 fp = pipe_config->dpll_hw_state.fp1;
8879
8880         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8881         if (IS_PINEVIEW(dev)) {
8882                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8883                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8884         } else {
8885                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8886                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8887         }
8888
8889         if (!IS_GEN2(dev)) {
8890                 if (IS_PINEVIEW(dev))
8891                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8892                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8893                 else
8894                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8895                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8896
8897                 switch (dpll & DPLL_MODE_MASK) {
8898                 case DPLLB_MODE_DAC_SERIAL:
8899                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8900                                 5 : 10;
8901                         break;
8902                 case DPLLB_MODE_LVDS:
8903                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8904                                 7 : 14;
8905                         break;
8906                 default:
8907                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8908                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8909                         return;
8910                 }
8911
8912                 if (IS_PINEVIEW(dev))
8913                         pineview_clock(refclk, &clock);
8914                 else
8915                         i9xx_clock(refclk, &clock);
8916         } else {
8917                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8918                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8919
8920                 if (is_lvds) {
8921                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8922                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8923
8924                         if (lvds & LVDS_CLKB_POWER_UP)
8925                                 clock.p2 = 7;
8926                         else
8927                                 clock.p2 = 14;
8928                 } else {
8929                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8930                                 clock.p1 = 2;
8931                         else {
8932                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8933                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8934                         }
8935                         if (dpll & PLL_P2_DIVIDE_BY_4)
8936                                 clock.p2 = 4;
8937                         else
8938                                 clock.p2 = 2;
8939                 }
8940
8941                 i9xx_clock(refclk, &clock);
8942         }
8943
8944         /*
8945          * This value includes pixel_multiplier. We will use
8946          * port_clock to compute adjusted_mode.crtc_clock in the
8947          * encoder's get_config() function.
8948          */
8949         pipe_config->port_clock = clock.dot;
8950 }
8951
8952 int intel_dotclock_calculate(int link_freq,
8953                              const struct intel_link_m_n *m_n)
8954 {
8955         /*
8956          * The calculation for the data clock is:
8957          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8958          * But we want to avoid losing precison if possible, so:
8959          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8960          *
8961          * and the link clock is simpler:
8962          * link_clock = (m * link_clock) / n
8963          */
8964
8965         if (!m_n->link_n)
8966                 return 0;
8967
8968         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8969 }
8970
8971 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8972                                    struct intel_crtc_config *pipe_config)
8973 {
8974         struct drm_device *dev = crtc->base.dev;
8975
8976         /* read out port_clock from the DPLL */
8977         i9xx_crtc_clock_get(crtc, pipe_config);
8978
8979         /*
8980          * This value does not include pixel_multiplier.
8981          * We will check that port_clock and adjusted_mode.crtc_clock
8982          * agree once we know their relationship in the encoder's
8983          * get_config() function.
8984          */
8985         pipe_config->adjusted_mode.crtc_clock =
8986                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8987                                          &pipe_config->fdi_m_n);
8988 }
8989
8990 /** Returns the currently programmed mode of the given pipe. */
8991 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8992                                              struct drm_crtc *crtc)
8993 {
8994         struct drm_i915_private *dev_priv = dev->dev_private;
8995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8996         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8997         struct drm_display_mode *mode;
8998         struct intel_crtc_config pipe_config;
8999         int htot = I915_READ(HTOTAL(cpu_transcoder));
9000         int hsync = I915_READ(HSYNC(cpu_transcoder));
9001         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9002         int vsync = I915_READ(VSYNC(cpu_transcoder));
9003         enum pipe pipe = intel_crtc->pipe;
9004
9005         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9006         if (!mode)
9007                 return NULL;
9008
9009         /*
9010          * Construct a pipe_config sufficient for getting the clock info
9011          * back out of crtc_clock_get.
9012          *
9013          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9014          * to use a real value here instead.
9015          */
9016         pipe_config.cpu_transcoder = (enum transcoder) pipe;
9017         pipe_config.pixel_multiplier = 1;
9018         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9019         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9020         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9021         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9022
9023         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9024         mode->hdisplay = (htot & 0xffff) + 1;
9025         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9026         mode->hsync_start = (hsync & 0xffff) + 1;
9027         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9028         mode->vdisplay = (vtot & 0xffff) + 1;
9029         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9030         mode->vsync_start = (vsync & 0xffff) + 1;
9031         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9032
9033         drm_mode_set_name(mode);
9034
9035         return mode;
9036 }
9037
9038 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9039 {
9040         struct drm_device *dev = crtc->dev;
9041         struct drm_i915_private *dev_priv = dev->dev_private;
9042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9043
9044         if (!HAS_GMCH_DISPLAY(dev))
9045                 return;
9046
9047         if (!dev_priv->lvds_downclock_avail)
9048                 return;
9049
9050         /*
9051          * Since this is called by a timer, we should never get here in
9052          * the manual case.
9053          */
9054         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9055                 int pipe = intel_crtc->pipe;
9056                 int dpll_reg = DPLL(pipe);
9057                 int dpll;
9058
9059                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9060
9061                 assert_panel_unlocked(dev_priv, pipe);
9062
9063                 dpll = I915_READ(dpll_reg);
9064                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9065                 I915_WRITE(dpll_reg, dpll);
9066                 intel_wait_for_vblank(dev, pipe);
9067                 dpll = I915_READ(dpll_reg);
9068                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9069                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9070         }
9071
9072 }
9073
9074 void intel_mark_busy(struct drm_device *dev)
9075 {
9076         struct drm_i915_private *dev_priv = dev->dev_private;
9077
9078         if (dev_priv->mm.busy)
9079                 return;
9080
9081         intel_runtime_pm_get(dev_priv);
9082         i915_update_gfx_val(dev_priv);
9083         dev_priv->mm.busy = true;
9084 }
9085
9086 void intel_mark_idle(struct drm_device *dev)
9087 {
9088         struct drm_i915_private *dev_priv = dev->dev_private;
9089         struct drm_crtc *crtc;
9090
9091         if (!dev_priv->mm.busy)
9092                 return;
9093
9094         dev_priv->mm.busy = false;
9095
9096         if (!i915.powersave)
9097                 goto out;
9098
9099         for_each_crtc(dev, crtc) {
9100                 if (!crtc->primary->fb)
9101                         continue;
9102
9103                 intel_decrease_pllclock(crtc);
9104         }
9105
9106         if (INTEL_INFO(dev)->gen >= 6)
9107                 gen6_rps_idle(dev->dev_private);
9108
9109 out:
9110         intel_runtime_pm_put(dev_priv);
9111 }
9112
9113 static void intel_crtc_destroy(struct drm_crtc *crtc)
9114 {
9115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9116         struct drm_device *dev = crtc->dev;
9117         struct intel_unpin_work *work;
9118
9119         spin_lock_irq(&dev->event_lock);
9120         work = intel_crtc->unpin_work;
9121         intel_crtc->unpin_work = NULL;
9122         spin_unlock_irq(&dev->event_lock);
9123
9124         if (work) {
9125                 cancel_work_sync(&work->work);
9126                 kfree(work);
9127         }
9128
9129         drm_crtc_cleanup(crtc);
9130
9131         kfree(intel_crtc);
9132 }
9133
9134 static void intel_unpin_work_fn(struct work_struct *__work)
9135 {
9136         struct intel_unpin_work *work =
9137                 container_of(__work, struct intel_unpin_work, work);
9138         struct drm_device *dev = work->crtc->dev;
9139         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9140
9141         mutex_lock(&dev->struct_mutex);
9142         intel_unpin_fb_obj(work->old_fb_obj);
9143         drm_gem_object_unreference(&work->pending_flip_obj->base);
9144         drm_gem_object_unreference(&work->old_fb_obj->base);
9145
9146         intel_update_fbc(dev);
9147         mutex_unlock(&dev->struct_mutex);
9148
9149         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9150
9151         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9152         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9153
9154         kfree(work);
9155 }
9156
9157 static void do_intel_finish_page_flip(struct drm_device *dev,
9158                                       struct drm_crtc *crtc)
9159 {
9160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9161         struct intel_unpin_work *work;
9162         unsigned long flags;
9163
9164         /* Ignore early vblank irqs */
9165         if (intel_crtc == NULL)
9166                 return;
9167
9168         /*
9169          * This is called both by irq handlers and the reset code (to complete
9170          * lost pageflips) so needs the full irqsave spinlocks.
9171          */
9172         spin_lock_irqsave(&dev->event_lock, flags);
9173         work = intel_crtc->unpin_work;
9174
9175         /* Ensure we don't miss a work->pending update ... */
9176         smp_rmb();
9177
9178         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9179                 spin_unlock_irqrestore(&dev->event_lock, flags);
9180                 return;
9181         }
9182
9183         page_flip_completed(intel_crtc);
9184
9185         spin_unlock_irqrestore(&dev->event_lock, flags);
9186 }
9187
9188 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9189 {
9190         struct drm_i915_private *dev_priv = dev->dev_private;
9191         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9192
9193         do_intel_finish_page_flip(dev, crtc);
9194 }
9195
9196 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9197 {
9198         struct drm_i915_private *dev_priv = dev->dev_private;
9199         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9200
9201         do_intel_finish_page_flip(dev, crtc);
9202 }
9203
9204 /* Is 'a' after or equal to 'b'? */
9205 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9206 {
9207         return !((a - b) & 0x80000000);
9208 }
9209
9210 static bool page_flip_finished(struct intel_crtc *crtc)
9211 {
9212         struct drm_device *dev = crtc->base.dev;
9213         struct drm_i915_private *dev_priv = dev->dev_private;
9214
9215         /*
9216          * The relevant registers doen't exist on pre-ctg.
9217          * As the flip done interrupt doesn't trigger for mmio
9218          * flips on gmch platforms, a flip count check isn't
9219          * really needed there. But since ctg has the registers,
9220          * include it in the check anyway.
9221          */
9222         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9223                 return true;
9224
9225         /*
9226          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9227          * used the same base address. In that case the mmio flip might
9228          * have completed, but the CS hasn't even executed the flip yet.
9229          *
9230          * A flip count check isn't enough as the CS might have updated
9231          * the base address just after start of vblank, but before we
9232          * managed to process the interrupt. This means we'd complete the
9233          * CS flip too soon.
9234          *
9235          * Combining both checks should get us a good enough result. It may
9236          * still happen that the CS flip has been executed, but has not
9237          * yet actually completed. But in case the base address is the same
9238          * anyway, we don't really care.
9239          */
9240         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9241                 crtc->unpin_work->gtt_offset &&
9242                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9243                                     crtc->unpin_work->flip_count);
9244 }
9245
9246 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9247 {
9248         struct drm_i915_private *dev_priv = dev->dev_private;
9249         struct intel_crtc *intel_crtc =
9250                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9251         unsigned long flags;
9252
9253
9254         /*
9255          * This is called both by irq handlers and the reset code (to complete
9256          * lost pageflips) so needs the full irqsave spinlocks.
9257          *
9258          * NB: An MMIO update of the plane base pointer will also
9259          * generate a page-flip completion irq, i.e. every modeset
9260          * is also accompanied by a spurious intel_prepare_page_flip().
9261          */
9262         spin_lock_irqsave(&dev->event_lock, flags);
9263         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9264                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9265         spin_unlock_irqrestore(&dev->event_lock, flags);
9266 }
9267
9268 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9269 {
9270         /* Ensure that the work item is consistent when activating it ... */
9271         smp_wmb();
9272         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9273         /* and that it is marked active as soon as the irq could fire. */
9274         smp_wmb();
9275 }
9276
9277 static int intel_gen2_queue_flip(struct drm_device *dev,
9278                                  struct drm_crtc *crtc,
9279                                  struct drm_framebuffer *fb,
9280                                  struct drm_i915_gem_object *obj,
9281                                  struct intel_engine_cs *ring,
9282                                  uint32_t flags)
9283 {
9284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9285         u32 flip_mask;
9286         int ret;
9287
9288         ret = intel_ring_begin(ring, 6);
9289         if (ret)
9290                 return ret;
9291
9292         /* Can't queue multiple flips, so wait for the previous
9293          * one to finish before executing the next.
9294          */
9295         if (intel_crtc->plane)
9296                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9297         else
9298                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9299         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9300         intel_ring_emit(ring, MI_NOOP);
9301         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9302                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9303         intel_ring_emit(ring, fb->pitches[0]);
9304         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9305         intel_ring_emit(ring, 0); /* aux display base address, unused */
9306
9307         intel_mark_page_flip_active(intel_crtc);
9308         __intel_ring_advance(ring);
9309         return 0;
9310 }
9311
9312 static int intel_gen3_queue_flip(struct drm_device *dev,
9313                                  struct drm_crtc *crtc,
9314                                  struct drm_framebuffer *fb,
9315                                  struct drm_i915_gem_object *obj,
9316                                  struct intel_engine_cs *ring,
9317                                  uint32_t flags)
9318 {
9319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9320         u32 flip_mask;
9321         int ret;
9322
9323         ret = intel_ring_begin(ring, 6);
9324         if (ret)
9325                 return ret;
9326
9327         if (intel_crtc->plane)
9328                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9329         else
9330                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9331         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9332         intel_ring_emit(ring, MI_NOOP);
9333         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9334                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9335         intel_ring_emit(ring, fb->pitches[0]);
9336         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9337         intel_ring_emit(ring, MI_NOOP);
9338
9339         intel_mark_page_flip_active(intel_crtc);
9340         __intel_ring_advance(ring);
9341         return 0;
9342 }
9343
9344 static int intel_gen4_queue_flip(struct drm_device *dev,
9345                                  struct drm_crtc *crtc,
9346                                  struct drm_framebuffer *fb,
9347                                  struct drm_i915_gem_object *obj,
9348                                  struct intel_engine_cs *ring,
9349                                  uint32_t flags)
9350 {
9351         struct drm_i915_private *dev_priv = dev->dev_private;
9352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9353         uint32_t pf, pipesrc;
9354         int ret;
9355
9356         ret = intel_ring_begin(ring, 4);
9357         if (ret)
9358                 return ret;
9359
9360         /* i965+ uses the linear or tiled offsets from the
9361          * Display Registers (which do not change across a page-flip)
9362          * so we need only reprogram the base address.
9363          */
9364         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9365                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9366         intel_ring_emit(ring, fb->pitches[0]);
9367         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9368                         obj->tiling_mode);
9369
9370         /* XXX Enabling the panel-fitter across page-flip is so far
9371          * untested on non-native modes, so ignore it for now.
9372          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9373          */
9374         pf = 0;
9375         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9376         intel_ring_emit(ring, pf | pipesrc);
9377
9378         intel_mark_page_flip_active(intel_crtc);
9379         __intel_ring_advance(ring);
9380         return 0;
9381 }
9382
9383 static int intel_gen6_queue_flip(struct drm_device *dev,
9384                                  struct drm_crtc *crtc,
9385                                  struct drm_framebuffer *fb,
9386                                  struct drm_i915_gem_object *obj,
9387                                  struct intel_engine_cs *ring,
9388                                  uint32_t flags)
9389 {
9390         struct drm_i915_private *dev_priv = dev->dev_private;
9391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9392         uint32_t pf, pipesrc;
9393         int ret;
9394
9395         ret = intel_ring_begin(ring, 4);
9396         if (ret)
9397                 return ret;
9398
9399         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9400                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9401         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9402         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9403
9404         /* Contrary to the suggestions in the documentation,
9405          * "Enable Panel Fitter" does not seem to be required when page
9406          * flipping with a non-native mode, and worse causes a normal
9407          * modeset to fail.
9408          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9409          */
9410         pf = 0;
9411         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9412         intel_ring_emit(ring, pf | pipesrc);
9413
9414         intel_mark_page_flip_active(intel_crtc);
9415         __intel_ring_advance(ring);
9416         return 0;
9417 }
9418
9419 static int intel_gen7_queue_flip(struct drm_device *dev,
9420                                  struct drm_crtc *crtc,
9421                                  struct drm_framebuffer *fb,
9422                                  struct drm_i915_gem_object *obj,
9423                                  struct intel_engine_cs *ring,
9424                                  uint32_t flags)
9425 {
9426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9427         uint32_t plane_bit = 0;
9428         int len, ret;
9429
9430         switch (intel_crtc->plane) {
9431         case PLANE_A:
9432                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9433                 break;
9434         case PLANE_B:
9435                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9436                 break;
9437         case PLANE_C:
9438                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9439                 break;
9440         default:
9441                 WARN_ONCE(1, "unknown plane in flip command\n");
9442                 return -ENODEV;
9443         }
9444
9445         len = 4;
9446         if (ring->id == RCS) {
9447                 len += 6;
9448                 /*
9449                  * On Gen 8, SRM is now taking an extra dword to accommodate
9450                  * 48bits addresses, and we need a NOOP for the batch size to
9451                  * stay even.
9452                  */
9453                 if (IS_GEN8(dev))
9454                         len += 2;
9455         }
9456
9457         /*
9458          * BSpec MI_DISPLAY_FLIP for IVB:
9459          * "The full packet must be contained within the same cache line."
9460          *
9461          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9462          * cacheline, if we ever start emitting more commands before
9463          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9464          * then do the cacheline alignment, and finally emit the
9465          * MI_DISPLAY_FLIP.
9466          */
9467         ret = intel_ring_cacheline_align(ring);
9468         if (ret)
9469                 return ret;
9470
9471         ret = intel_ring_begin(ring, len);
9472         if (ret)
9473                 return ret;
9474
9475         /* Unmask the flip-done completion message. Note that the bspec says that
9476          * we should do this for both the BCS and RCS, and that we must not unmask
9477          * more than one flip event at any time (or ensure that one flip message
9478          * can be sent by waiting for flip-done prior to queueing new flips).
9479          * Experimentation says that BCS works despite DERRMR masking all
9480          * flip-done completion events and that unmasking all planes at once
9481          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9482          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9483          */
9484         if (ring->id == RCS) {
9485                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9486                 intel_ring_emit(ring, DERRMR);
9487                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9488                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9489                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9490                 if (IS_GEN8(dev))
9491                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9492                                               MI_SRM_LRM_GLOBAL_GTT);
9493                 else
9494                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9495                                               MI_SRM_LRM_GLOBAL_GTT);
9496                 intel_ring_emit(ring, DERRMR);
9497                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9498                 if (IS_GEN8(dev)) {
9499                         intel_ring_emit(ring, 0);
9500                         intel_ring_emit(ring, MI_NOOP);
9501                 }
9502         }
9503
9504         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9505         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9506         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9507         intel_ring_emit(ring, (MI_NOOP));
9508
9509         intel_mark_page_flip_active(intel_crtc);
9510         __intel_ring_advance(ring);
9511         return 0;
9512 }
9513
9514 static bool use_mmio_flip(struct intel_engine_cs *ring,
9515                           struct drm_i915_gem_object *obj)
9516 {
9517         /*
9518          * This is not being used for older platforms, because
9519          * non-availability of flip done interrupt forces us to use
9520          * CS flips. Older platforms derive flip done using some clever
9521          * tricks involving the flip_pending status bits and vblank irqs.
9522          * So using MMIO flips there would disrupt this mechanism.
9523          */
9524
9525         if (ring == NULL)
9526                 return true;
9527
9528         if (INTEL_INFO(ring->dev)->gen < 5)
9529                 return false;
9530
9531         if (i915.use_mmio_flip < 0)
9532                 return false;
9533         else if (i915.use_mmio_flip > 0)
9534                 return true;
9535         else if (i915.enable_execlists)
9536                 return true;
9537         else
9538                 return ring != obj->ring;
9539 }
9540
9541 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9542 {
9543         struct drm_device *dev = intel_crtc->base.dev;
9544         struct drm_i915_private *dev_priv = dev->dev_private;
9545         struct intel_framebuffer *intel_fb =
9546                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9547         struct drm_i915_gem_object *obj = intel_fb->obj;
9548         u32 dspcntr;
9549         u32 reg;
9550
9551         intel_mark_page_flip_active(intel_crtc);
9552
9553         reg = DSPCNTR(intel_crtc->plane);
9554         dspcntr = I915_READ(reg);
9555
9556         if (INTEL_INFO(dev)->gen >= 4) {
9557                 if (obj->tiling_mode != I915_TILING_NONE)
9558                         dspcntr |= DISPPLANE_TILED;
9559                 else
9560                         dspcntr &= ~DISPPLANE_TILED;
9561         }
9562         I915_WRITE(reg, dspcntr);
9563
9564         I915_WRITE(DSPSURF(intel_crtc->plane),
9565                    intel_crtc->unpin_work->gtt_offset);
9566         POSTING_READ(DSPSURF(intel_crtc->plane));
9567 }
9568
9569 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9570 {
9571         struct intel_engine_cs *ring;
9572         int ret;
9573
9574         lockdep_assert_held(&obj->base.dev->struct_mutex);
9575
9576         if (!obj->last_write_seqno)
9577                 return 0;
9578
9579         ring = obj->ring;
9580
9581         if (i915_seqno_passed(ring->get_seqno(ring, true),
9582                               obj->last_write_seqno))
9583                 return 0;
9584
9585         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9586         if (ret)
9587                 return ret;
9588
9589         if (WARN_ON(!ring->irq_get(ring)))
9590                 return 0;
9591
9592         return 1;
9593 }
9594
9595 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9596 {
9597         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9598         struct intel_crtc *intel_crtc;
9599         unsigned long irq_flags;
9600         u32 seqno;
9601
9602         seqno = ring->get_seqno(ring, false);
9603
9604         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9605         for_each_intel_crtc(ring->dev, intel_crtc) {
9606                 struct intel_mmio_flip *mmio_flip;
9607
9608                 mmio_flip = &intel_crtc->mmio_flip;
9609                 if (mmio_flip->seqno == 0)
9610                         continue;
9611
9612                 if (ring->id != mmio_flip->ring_id)
9613                         continue;
9614
9615                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9616                         intel_do_mmio_flip(intel_crtc);
9617                         mmio_flip->seqno = 0;
9618                         ring->irq_put(ring);
9619                 }
9620         }
9621         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9622 }
9623
9624 static int intel_queue_mmio_flip(struct drm_device *dev,
9625                                  struct drm_crtc *crtc,
9626                                  struct drm_framebuffer *fb,
9627                                  struct drm_i915_gem_object *obj,
9628                                  struct intel_engine_cs *ring,
9629                                  uint32_t flags)
9630 {
9631         struct drm_i915_private *dev_priv = dev->dev_private;
9632         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9633         int ret;
9634
9635         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9636                 return -EBUSY;
9637
9638         ret = intel_postpone_flip(obj);
9639         if (ret < 0)
9640                 return ret;
9641         if (ret == 0) {
9642                 intel_do_mmio_flip(intel_crtc);
9643                 return 0;
9644         }
9645
9646         spin_lock_irq(&dev_priv->mmio_flip_lock);
9647         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9648         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9649         spin_unlock_irq(&dev_priv->mmio_flip_lock);
9650
9651         /*
9652          * Double check to catch cases where irq fired before
9653          * mmio flip data was ready
9654          */
9655         intel_notify_mmio_flip(obj->ring);
9656         return 0;
9657 }
9658
9659 static int intel_default_queue_flip(struct drm_device *dev,
9660                                     struct drm_crtc *crtc,
9661                                     struct drm_framebuffer *fb,
9662                                     struct drm_i915_gem_object *obj,
9663                                     struct intel_engine_cs *ring,
9664                                     uint32_t flags)
9665 {
9666         return -ENODEV;
9667 }
9668
9669 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9670                                          struct drm_crtc *crtc)
9671 {
9672         struct drm_i915_private *dev_priv = dev->dev_private;
9673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9674         struct intel_unpin_work *work = intel_crtc->unpin_work;
9675         u32 addr;
9676
9677         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9678                 return true;
9679
9680         if (!work->enable_stall_check)
9681                 return false;
9682
9683         if (work->flip_ready_vblank == 0) {
9684                 if (work->flip_queued_ring &&
9685                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9686                                        work->flip_queued_seqno))
9687                         return false;
9688
9689                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9690         }
9691
9692         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9693                 return false;
9694
9695         /* Potential stall - if we see that the flip has happened,
9696          * assume a missed interrupt. */
9697         if (INTEL_INFO(dev)->gen >= 4)
9698                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9699         else
9700                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9701
9702         /* There is a potential issue here with a false positive after a flip
9703          * to the same address. We could address this by checking for a
9704          * non-incrementing frame counter.
9705          */
9706         return addr == work->gtt_offset;
9707 }
9708
9709 void intel_check_page_flip(struct drm_device *dev, int pipe)
9710 {
9711         struct drm_i915_private *dev_priv = dev->dev_private;
9712         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9714
9715         WARN_ON(!in_irq());
9716
9717         if (crtc == NULL)
9718                 return;
9719
9720         spin_lock(&dev->event_lock);
9721         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9722                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9723                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9724                 page_flip_completed(intel_crtc);
9725         }
9726         spin_unlock(&dev->event_lock);
9727 }
9728
9729 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9730                                 struct drm_framebuffer *fb,
9731                                 struct drm_pending_vblank_event *event,
9732                                 uint32_t page_flip_flags)
9733 {
9734         struct drm_device *dev = crtc->dev;
9735         struct drm_i915_private *dev_priv = dev->dev_private;
9736         struct drm_framebuffer *old_fb = crtc->primary->fb;
9737         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9739         enum pipe pipe = intel_crtc->pipe;
9740         struct intel_unpin_work *work;
9741         struct intel_engine_cs *ring;
9742         int ret;
9743
9744         /*
9745          * drm_mode_page_flip_ioctl() should already catch this, but double
9746          * check to be safe.  In the future we may enable pageflipping from
9747          * a disabled primary plane.
9748          */
9749         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9750                 return -EBUSY;
9751
9752         /* Can't change pixel format via MI display flips. */
9753         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9754                 return -EINVAL;
9755
9756         /*
9757          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9758          * Note that pitch changes could also affect these register.
9759          */
9760         if (INTEL_INFO(dev)->gen > 3 &&
9761             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9762              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9763                 return -EINVAL;
9764
9765         if (i915_terminally_wedged(&dev_priv->gpu_error))
9766                 goto out_hang;
9767
9768         work = kzalloc(sizeof(*work), GFP_KERNEL);
9769         if (work == NULL)
9770                 return -ENOMEM;
9771
9772         work->event = event;
9773         work->crtc = crtc;
9774         work->old_fb_obj = intel_fb_obj(old_fb);
9775         INIT_WORK(&work->work, intel_unpin_work_fn);
9776
9777         ret = drm_crtc_vblank_get(crtc);
9778         if (ret)
9779                 goto free_work;
9780
9781         /* We borrow the event spin lock for protecting unpin_work */
9782         spin_lock_irq(&dev->event_lock);
9783         if (intel_crtc->unpin_work) {
9784                 /* Before declaring the flip queue wedged, check if
9785                  * the hardware completed the operation behind our backs.
9786                  */
9787                 if (__intel_pageflip_stall_check(dev, crtc)) {
9788                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9789                         page_flip_completed(intel_crtc);
9790                 } else {
9791                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9792                         spin_unlock_irq(&dev->event_lock);
9793
9794                         drm_crtc_vblank_put(crtc);
9795                         kfree(work);
9796                         return -EBUSY;
9797                 }
9798         }
9799         intel_crtc->unpin_work = work;
9800         spin_unlock_irq(&dev->event_lock);
9801
9802         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9803                 flush_workqueue(dev_priv->wq);
9804
9805         ret = i915_mutex_lock_interruptible(dev);
9806         if (ret)
9807                 goto cleanup;
9808
9809         /* Reference the objects for the scheduled work. */
9810         drm_gem_object_reference(&work->old_fb_obj->base);
9811         drm_gem_object_reference(&obj->base);
9812
9813         crtc->primary->fb = fb;
9814
9815         work->pending_flip_obj = obj;
9816
9817         atomic_inc(&intel_crtc->unpin_work_count);
9818         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9819
9820         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9821                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9822
9823         if (IS_VALLEYVIEW(dev)) {
9824                 ring = &dev_priv->ring[BCS];
9825                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9826                         /* vlv: DISPLAY_FLIP fails to change tiling */
9827                         ring = NULL;
9828         } else if (IS_IVYBRIDGE(dev)) {
9829                 ring = &dev_priv->ring[BCS];
9830         } else if (INTEL_INFO(dev)->gen >= 7) {
9831                 ring = obj->ring;
9832                 if (ring == NULL || ring->id != RCS)
9833                         ring = &dev_priv->ring[BCS];
9834         } else {
9835                 ring = &dev_priv->ring[RCS];
9836         }
9837
9838         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9839         if (ret)
9840                 goto cleanup_pending;
9841
9842         work->gtt_offset =
9843                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9844
9845         if (use_mmio_flip(ring, obj)) {
9846                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9847                                             page_flip_flags);
9848                 if (ret)
9849                         goto cleanup_unpin;
9850
9851                 work->flip_queued_seqno = obj->last_write_seqno;
9852                 work->flip_queued_ring = obj->ring;
9853         } else {
9854                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9855                                                    page_flip_flags);
9856                 if (ret)
9857                         goto cleanup_unpin;
9858
9859                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9860                 work->flip_queued_ring = ring;
9861         }
9862
9863         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9864         work->enable_stall_check = true;
9865
9866         i915_gem_track_fb(work->old_fb_obj, obj,
9867                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9868
9869         intel_disable_fbc(dev);
9870         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9871         mutex_unlock(&dev->struct_mutex);
9872
9873         trace_i915_flip_request(intel_crtc->plane, obj);
9874
9875         return 0;
9876
9877 cleanup_unpin:
9878         intel_unpin_fb_obj(obj);
9879 cleanup_pending:
9880         atomic_dec(&intel_crtc->unpin_work_count);
9881         crtc->primary->fb = old_fb;
9882         drm_gem_object_unreference(&work->old_fb_obj->base);
9883         drm_gem_object_unreference(&obj->base);
9884         mutex_unlock(&dev->struct_mutex);
9885
9886 cleanup:
9887         spin_lock_irq(&dev->event_lock);
9888         intel_crtc->unpin_work = NULL;
9889         spin_unlock_irq(&dev->event_lock);
9890
9891         drm_crtc_vblank_put(crtc);
9892 free_work:
9893         kfree(work);
9894
9895         if (ret == -EIO) {
9896 out_hang:
9897                 intel_crtc_wait_for_pending_flips(crtc);
9898                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9899                 if (ret == 0 && event) {
9900                         spin_lock_irq(&dev->event_lock);
9901                         drm_send_vblank_event(dev, pipe, event);
9902                         spin_unlock_irq(&dev->event_lock);
9903                 }
9904         }
9905         return ret;
9906 }
9907
9908 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9909         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9910         .load_lut = intel_crtc_load_lut,
9911 };
9912
9913 /**
9914  * intel_modeset_update_staged_output_state
9915  *
9916  * Updates the staged output configuration state, e.g. after we've read out the
9917  * current hw state.
9918  */
9919 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9920 {
9921         struct intel_crtc *crtc;
9922         struct intel_encoder *encoder;
9923         struct intel_connector *connector;
9924
9925         list_for_each_entry(connector, &dev->mode_config.connector_list,
9926                             base.head) {
9927                 connector->new_encoder =
9928                         to_intel_encoder(connector->base.encoder);
9929         }
9930
9931         for_each_intel_encoder(dev, encoder) {
9932                 encoder->new_crtc =
9933                         to_intel_crtc(encoder->base.crtc);
9934         }
9935
9936         for_each_intel_crtc(dev, crtc) {
9937                 crtc->new_enabled = crtc->base.enabled;
9938
9939                 if (crtc->new_enabled)
9940                         crtc->new_config = &crtc->config;
9941                 else
9942                         crtc->new_config = NULL;
9943         }
9944 }
9945
9946 /**
9947  * intel_modeset_commit_output_state
9948  *
9949  * This function copies the stage display pipe configuration to the real one.
9950  */
9951 static void intel_modeset_commit_output_state(struct drm_device *dev)
9952 {
9953         struct intel_crtc *crtc;
9954         struct intel_encoder *encoder;
9955         struct intel_connector *connector;
9956
9957         list_for_each_entry(connector, &dev->mode_config.connector_list,
9958                             base.head) {
9959                 connector->base.encoder = &connector->new_encoder->base;
9960         }
9961
9962         for_each_intel_encoder(dev, encoder) {
9963                 encoder->base.crtc = &encoder->new_crtc->base;
9964         }
9965
9966         for_each_intel_crtc(dev, crtc) {
9967                 crtc->base.enabled = crtc->new_enabled;
9968         }
9969 }
9970
9971 static void
9972 connected_sink_compute_bpp(struct intel_connector *connector,
9973                            struct intel_crtc_config *pipe_config)
9974 {
9975         int bpp = pipe_config->pipe_bpp;
9976
9977         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9978                 connector->base.base.id,
9979                 connector->base.name);
9980
9981         /* Don't use an invalid EDID bpc value */
9982         if (connector->base.display_info.bpc &&
9983             connector->base.display_info.bpc * 3 < bpp) {
9984                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9985                               bpp, connector->base.display_info.bpc*3);
9986                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9987         }
9988
9989         /* Clamp bpp to 8 on screens without EDID 1.4 */
9990         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9991                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9992                               bpp);
9993                 pipe_config->pipe_bpp = 24;
9994         }
9995 }
9996
9997 static int
9998 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9999                           struct drm_framebuffer *fb,
10000                           struct intel_crtc_config *pipe_config)
10001 {
10002         struct drm_device *dev = crtc->base.dev;
10003         struct intel_connector *connector;
10004         int bpp;
10005
10006         switch (fb->pixel_format) {
10007         case DRM_FORMAT_C8:
10008                 bpp = 8*3; /* since we go through a colormap */
10009                 break;
10010         case DRM_FORMAT_XRGB1555:
10011         case DRM_FORMAT_ARGB1555:
10012                 /* checked in intel_framebuffer_init already */
10013                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10014                         return -EINVAL;
10015         case DRM_FORMAT_RGB565:
10016                 bpp = 6*3; /* min is 18bpp */
10017                 break;
10018         case DRM_FORMAT_XBGR8888:
10019         case DRM_FORMAT_ABGR8888:
10020                 /* checked in intel_framebuffer_init already */
10021                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10022                         return -EINVAL;
10023         case DRM_FORMAT_XRGB8888:
10024         case DRM_FORMAT_ARGB8888:
10025                 bpp = 8*3;
10026                 break;
10027         case DRM_FORMAT_XRGB2101010:
10028         case DRM_FORMAT_ARGB2101010:
10029         case DRM_FORMAT_XBGR2101010:
10030         case DRM_FORMAT_ABGR2101010:
10031                 /* checked in intel_framebuffer_init already */
10032                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10033                         return -EINVAL;
10034                 bpp = 10*3;
10035                 break;
10036         /* TODO: gen4+ supports 16 bpc floating point, too. */
10037         default:
10038                 DRM_DEBUG_KMS("unsupported depth\n");
10039                 return -EINVAL;
10040         }
10041
10042         pipe_config->pipe_bpp = bpp;
10043
10044         /* Clamp display bpp to EDID value */
10045         list_for_each_entry(connector, &dev->mode_config.connector_list,
10046                             base.head) {
10047                 if (!connector->new_encoder ||
10048                     connector->new_encoder->new_crtc != crtc)
10049                         continue;
10050
10051                 connected_sink_compute_bpp(connector, pipe_config);
10052         }
10053
10054         return bpp;
10055 }
10056
10057 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10058 {
10059         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10060                         "type: 0x%x flags: 0x%x\n",
10061                 mode->crtc_clock,
10062                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10063                 mode->crtc_hsync_end, mode->crtc_htotal,
10064                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10065                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10066 }
10067
10068 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10069                                    struct intel_crtc_config *pipe_config,
10070                                    const char *context)
10071 {
10072         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10073                       context, pipe_name(crtc->pipe));
10074
10075         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10076         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10077                       pipe_config->pipe_bpp, pipe_config->dither);
10078         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10079                       pipe_config->has_pch_encoder,
10080                       pipe_config->fdi_lanes,
10081                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10082                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10083                       pipe_config->fdi_m_n.tu);
10084         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10085                       pipe_config->has_dp_encoder,
10086                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10087                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10088                       pipe_config->dp_m_n.tu);
10089
10090         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10091                       pipe_config->has_dp_encoder,
10092                       pipe_config->dp_m2_n2.gmch_m,
10093                       pipe_config->dp_m2_n2.gmch_n,
10094                       pipe_config->dp_m2_n2.link_m,
10095                       pipe_config->dp_m2_n2.link_n,
10096                       pipe_config->dp_m2_n2.tu);
10097
10098         DRM_DEBUG_KMS("requested mode:\n");
10099         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10100         DRM_DEBUG_KMS("adjusted mode:\n");
10101         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10102         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10103         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10104         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10105                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10106         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10107                       pipe_config->gmch_pfit.control,
10108                       pipe_config->gmch_pfit.pgm_ratios,
10109                       pipe_config->gmch_pfit.lvds_border_bits);
10110         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10111                       pipe_config->pch_pfit.pos,
10112                       pipe_config->pch_pfit.size,
10113                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10114         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10115         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10116 }
10117
10118 static bool encoders_cloneable(const struct intel_encoder *a,
10119                                const struct intel_encoder *b)
10120 {
10121         /* masks could be asymmetric, so check both ways */
10122         return a == b || (a->cloneable & (1 << b->type) &&
10123                           b->cloneable & (1 << a->type));
10124 }
10125
10126 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10127                                          struct intel_encoder *encoder)
10128 {
10129         struct drm_device *dev = crtc->base.dev;
10130         struct intel_encoder *source_encoder;
10131
10132         for_each_intel_encoder(dev, source_encoder) {
10133                 if (source_encoder->new_crtc != crtc)
10134                         continue;
10135
10136                 if (!encoders_cloneable(encoder, source_encoder))
10137                         return false;
10138         }
10139
10140         return true;
10141 }
10142
10143 static bool check_encoder_cloning(struct intel_crtc *crtc)
10144 {
10145         struct drm_device *dev = crtc->base.dev;
10146         struct intel_encoder *encoder;
10147
10148         for_each_intel_encoder(dev, encoder) {
10149                 if (encoder->new_crtc != crtc)
10150                         continue;
10151
10152                 if (!check_single_encoder_cloning(crtc, encoder))
10153                         return false;
10154         }
10155
10156         return true;
10157 }
10158
10159 static struct intel_crtc_config *
10160 intel_modeset_pipe_config(struct drm_crtc *crtc,
10161                           struct drm_framebuffer *fb,
10162                           struct drm_display_mode *mode)
10163 {
10164         struct drm_device *dev = crtc->dev;
10165         struct intel_encoder *encoder;
10166         struct intel_crtc_config *pipe_config;
10167         int plane_bpp, ret = -EINVAL;
10168         bool retry = true;
10169
10170         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10171                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10172                 return ERR_PTR(-EINVAL);
10173         }
10174
10175         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10176         if (!pipe_config)
10177                 return ERR_PTR(-ENOMEM);
10178
10179         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10180         drm_mode_copy(&pipe_config->requested_mode, mode);
10181
10182         pipe_config->cpu_transcoder =
10183                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10184         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10185
10186         /*
10187          * Sanitize sync polarity flags based on requested ones. If neither
10188          * positive or negative polarity is requested, treat this as meaning
10189          * negative polarity.
10190          */
10191         if (!(pipe_config->adjusted_mode.flags &
10192               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10193                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10194
10195         if (!(pipe_config->adjusted_mode.flags &
10196               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10197                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10198
10199         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10200          * plane pixel format and any sink constraints into account. Returns the
10201          * source plane bpp so that dithering can be selected on mismatches
10202          * after encoders and crtc also have had their say. */
10203         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10204                                               fb, pipe_config);
10205         if (plane_bpp < 0)
10206                 goto fail;
10207
10208         /*
10209          * Determine the real pipe dimensions. Note that stereo modes can
10210          * increase the actual pipe size due to the frame doubling and
10211          * insertion of additional space for blanks between the frame. This
10212          * is stored in the crtc timings. We use the requested mode to do this
10213          * computation to clearly distinguish it from the adjusted mode, which
10214          * can be changed by the connectors in the below retry loop.
10215          */
10216         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10217         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10218         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10219
10220 encoder_retry:
10221         /* Ensure the port clock defaults are reset when retrying. */
10222         pipe_config->port_clock = 0;
10223         pipe_config->pixel_multiplier = 1;
10224
10225         /* Fill in default crtc timings, allow encoders to overwrite them. */
10226         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10227
10228         /* Pass our mode to the connectors and the CRTC to give them a chance to
10229          * adjust it according to limitations or connector properties, and also
10230          * a chance to reject the mode entirely.
10231          */
10232         for_each_intel_encoder(dev, encoder) {
10233
10234                 if (&encoder->new_crtc->base != crtc)
10235                         continue;
10236
10237                 if (!(encoder->compute_config(encoder, pipe_config))) {
10238                         DRM_DEBUG_KMS("Encoder config failure\n");
10239                         goto fail;
10240                 }
10241         }
10242
10243         /* Set default port clock if not overwritten by the encoder. Needs to be
10244          * done afterwards in case the encoder adjusts the mode. */
10245         if (!pipe_config->port_clock)
10246                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10247                         * pipe_config->pixel_multiplier;
10248
10249         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10250         if (ret < 0) {
10251                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10252                 goto fail;
10253         }
10254
10255         if (ret == RETRY) {
10256                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10257                         ret = -EINVAL;
10258                         goto fail;
10259                 }
10260
10261                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10262                 retry = false;
10263                 goto encoder_retry;
10264         }
10265
10266         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10267         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10268                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10269
10270         return pipe_config;
10271 fail:
10272         kfree(pipe_config);
10273         return ERR_PTR(ret);
10274 }
10275
10276 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10277  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10278 static void
10279 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10280                              unsigned *prepare_pipes, unsigned *disable_pipes)
10281 {
10282         struct intel_crtc *intel_crtc;
10283         struct drm_device *dev = crtc->dev;
10284         struct intel_encoder *encoder;
10285         struct intel_connector *connector;
10286         struct drm_crtc *tmp_crtc;
10287
10288         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10289
10290         /* Check which crtcs have changed outputs connected to them, these need
10291          * to be part of the prepare_pipes mask. We don't (yet) support global
10292          * modeset across multiple crtcs, so modeset_pipes will only have one
10293          * bit set at most. */
10294         list_for_each_entry(connector, &dev->mode_config.connector_list,
10295                             base.head) {
10296                 if (connector->base.encoder == &connector->new_encoder->base)
10297                         continue;
10298
10299                 if (connector->base.encoder) {
10300                         tmp_crtc = connector->base.encoder->crtc;
10301
10302                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10303                 }
10304
10305                 if (connector->new_encoder)
10306                         *prepare_pipes |=
10307                                 1 << connector->new_encoder->new_crtc->pipe;
10308         }
10309
10310         for_each_intel_encoder(dev, encoder) {
10311                 if (encoder->base.crtc == &encoder->new_crtc->base)
10312                         continue;
10313
10314                 if (encoder->base.crtc) {
10315                         tmp_crtc = encoder->base.crtc;
10316
10317                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10318                 }
10319
10320                 if (encoder->new_crtc)
10321                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10322         }
10323
10324         /* Check for pipes that will be enabled/disabled ... */
10325         for_each_intel_crtc(dev, intel_crtc) {
10326                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10327                         continue;
10328
10329                 if (!intel_crtc->new_enabled)
10330                         *disable_pipes |= 1 << intel_crtc->pipe;
10331                 else
10332                         *prepare_pipes |= 1 << intel_crtc->pipe;
10333         }
10334
10335
10336         /* set_mode is also used to update properties on life display pipes. */
10337         intel_crtc = to_intel_crtc(crtc);
10338         if (intel_crtc->new_enabled)
10339                 *prepare_pipes |= 1 << intel_crtc->pipe;
10340
10341         /*
10342          * For simplicity do a full modeset on any pipe where the output routing
10343          * changed. We could be more clever, but that would require us to be
10344          * more careful with calling the relevant encoder->mode_set functions.
10345          */
10346         if (*prepare_pipes)
10347                 *modeset_pipes = *prepare_pipes;
10348
10349         /* ... and mask these out. */
10350         *modeset_pipes &= ~(*disable_pipes);
10351         *prepare_pipes &= ~(*disable_pipes);
10352
10353         /*
10354          * HACK: We don't (yet) fully support global modesets. intel_set_config
10355          * obies this rule, but the modeset restore mode of
10356          * intel_modeset_setup_hw_state does not.
10357          */
10358         *modeset_pipes &= 1 << intel_crtc->pipe;
10359         *prepare_pipes &= 1 << intel_crtc->pipe;
10360
10361         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10362                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10363 }
10364
10365 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10366 {
10367         struct drm_encoder *encoder;
10368         struct drm_device *dev = crtc->dev;
10369
10370         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10371                 if (encoder->crtc == crtc)
10372                         return true;
10373
10374         return false;
10375 }
10376
10377 static void
10378 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10379 {
10380         struct intel_encoder *intel_encoder;
10381         struct intel_crtc *intel_crtc;
10382         struct drm_connector *connector;
10383
10384         for_each_intel_encoder(dev, intel_encoder) {
10385                 if (!intel_encoder->base.crtc)
10386                         continue;
10387
10388                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10389
10390                 if (prepare_pipes & (1 << intel_crtc->pipe))
10391                         intel_encoder->connectors_active = false;
10392         }
10393
10394         intel_modeset_commit_output_state(dev);
10395
10396         /* Double check state. */
10397         for_each_intel_crtc(dev, intel_crtc) {
10398                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10399                 WARN_ON(intel_crtc->new_config &&
10400                         intel_crtc->new_config != &intel_crtc->config);
10401                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10402         }
10403
10404         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10405                 if (!connector->encoder || !connector->encoder->crtc)
10406                         continue;
10407
10408                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10409
10410                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10411                         struct drm_property *dpms_property =
10412                                 dev->mode_config.dpms_property;
10413
10414                         connector->dpms = DRM_MODE_DPMS_ON;
10415                         drm_object_property_set_value(&connector->base,
10416                                                          dpms_property,
10417                                                          DRM_MODE_DPMS_ON);
10418
10419                         intel_encoder = to_intel_encoder(connector->encoder);
10420                         intel_encoder->connectors_active = true;
10421                 }
10422         }
10423
10424 }
10425
10426 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10427 {
10428         int diff;
10429
10430         if (clock1 == clock2)
10431                 return true;
10432
10433         if (!clock1 || !clock2)
10434                 return false;
10435
10436         diff = abs(clock1 - clock2);
10437
10438         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10439                 return true;
10440
10441         return false;
10442 }
10443
10444 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10445         list_for_each_entry((intel_crtc), \
10446                             &(dev)->mode_config.crtc_list, \
10447                             base.head) \
10448                 if (mask & (1 <<(intel_crtc)->pipe))
10449
10450 static bool
10451 intel_pipe_config_compare(struct drm_device *dev,
10452                           struct intel_crtc_config *current_config,
10453                           struct intel_crtc_config *pipe_config)
10454 {
10455 #define PIPE_CONF_CHECK_X(name) \
10456         if (current_config->name != pipe_config->name) { \
10457                 DRM_ERROR("mismatch in " #name " " \
10458                           "(expected 0x%08x, found 0x%08x)\n", \
10459                           current_config->name, \
10460                           pipe_config->name); \
10461                 return false; \
10462         }
10463
10464 #define PIPE_CONF_CHECK_I(name) \
10465         if (current_config->name != pipe_config->name) { \
10466                 DRM_ERROR("mismatch in " #name " " \
10467                           "(expected %i, found %i)\n", \
10468                           current_config->name, \
10469                           pipe_config->name); \
10470                 return false; \
10471         }
10472
10473 /* This is required for BDW+ where there is only one set of registers for
10474  * switching between high and low RR.
10475  * This macro can be used whenever a comparison has to be made between one
10476  * hw state and multiple sw state variables.
10477  */
10478 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10479         if ((current_config->name != pipe_config->name) && \
10480                 (current_config->alt_name != pipe_config->name)) { \
10481                         DRM_ERROR("mismatch in " #name " " \
10482                                   "(expected %i or %i, found %i)\n", \
10483                                   current_config->name, \
10484                                   current_config->alt_name, \
10485                                   pipe_config->name); \
10486                         return false; \
10487         }
10488
10489 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10490         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10491                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10492                           "(expected %i, found %i)\n", \
10493                           current_config->name & (mask), \
10494                           pipe_config->name & (mask)); \
10495                 return false; \
10496         }
10497
10498 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10499         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10500                 DRM_ERROR("mismatch in " #name " " \
10501                           "(expected %i, found %i)\n", \
10502                           current_config->name, \
10503                           pipe_config->name); \
10504                 return false; \
10505         }
10506
10507 #define PIPE_CONF_QUIRK(quirk)  \
10508         ((current_config->quirks | pipe_config->quirks) & (quirk))
10509
10510         PIPE_CONF_CHECK_I(cpu_transcoder);
10511
10512         PIPE_CONF_CHECK_I(has_pch_encoder);
10513         PIPE_CONF_CHECK_I(fdi_lanes);
10514         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10515         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10516         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10517         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10518         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10519
10520         PIPE_CONF_CHECK_I(has_dp_encoder);
10521
10522         if (INTEL_INFO(dev)->gen < 8) {
10523                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10524                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10525                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10526                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10527                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10528
10529                 if (current_config->has_drrs) {
10530                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10531                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10532                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10533                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10534                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10535                 }
10536         } else {
10537                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10538                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10539                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10540                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10541                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10542         }
10543
10544         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10545         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10546         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10547         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10548         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10549         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10550
10551         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10552         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10553         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10554         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10555         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10556         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10557
10558         PIPE_CONF_CHECK_I(pixel_multiplier);
10559         PIPE_CONF_CHECK_I(has_hdmi_sink);
10560         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10561             IS_VALLEYVIEW(dev))
10562                 PIPE_CONF_CHECK_I(limited_color_range);
10563
10564         PIPE_CONF_CHECK_I(has_audio);
10565
10566         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10567                               DRM_MODE_FLAG_INTERLACE);
10568
10569         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10570                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10571                                       DRM_MODE_FLAG_PHSYNC);
10572                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10573                                       DRM_MODE_FLAG_NHSYNC);
10574                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10575                                       DRM_MODE_FLAG_PVSYNC);
10576                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10577                                       DRM_MODE_FLAG_NVSYNC);
10578         }
10579
10580         PIPE_CONF_CHECK_I(pipe_src_w);
10581         PIPE_CONF_CHECK_I(pipe_src_h);
10582
10583         /*
10584          * FIXME: BIOS likes to set up a cloned config with lvds+external
10585          * screen. Since we don't yet re-compute the pipe config when moving
10586          * just the lvds port away to another pipe the sw tracking won't match.
10587          *
10588          * Proper atomic modesets with recomputed global state will fix this.
10589          * Until then just don't check gmch state for inherited modes.
10590          */
10591         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10592                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10593                 /* pfit ratios are autocomputed by the hw on gen4+ */
10594                 if (INTEL_INFO(dev)->gen < 4)
10595                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10596                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10597         }
10598
10599         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10600         if (current_config->pch_pfit.enabled) {
10601                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10602                 PIPE_CONF_CHECK_I(pch_pfit.size);
10603         }
10604
10605         /* BDW+ don't expose a synchronous way to read the state */
10606         if (IS_HASWELL(dev))
10607                 PIPE_CONF_CHECK_I(ips_enabled);
10608
10609         PIPE_CONF_CHECK_I(double_wide);
10610
10611         PIPE_CONF_CHECK_X(ddi_pll_sel);
10612
10613         PIPE_CONF_CHECK_I(shared_dpll);
10614         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10615         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10616         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10617         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10618         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10619
10620         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10621                 PIPE_CONF_CHECK_I(pipe_bpp);
10622
10623         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10624         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10625
10626 #undef PIPE_CONF_CHECK_X
10627 #undef PIPE_CONF_CHECK_I
10628 #undef PIPE_CONF_CHECK_I_ALT
10629 #undef PIPE_CONF_CHECK_FLAGS
10630 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10631 #undef PIPE_CONF_QUIRK
10632
10633         return true;
10634 }
10635
10636 static void
10637 check_connector_state(struct drm_device *dev)
10638 {
10639         struct intel_connector *connector;
10640
10641         list_for_each_entry(connector, &dev->mode_config.connector_list,
10642                             base.head) {
10643                 /* This also checks the encoder/connector hw state with the
10644                  * ->get_hw_state callbacks. */
10645                 intel_connector_check_state(connector);
10646
10647                 WARN(&connector->new_encoder->base != connector->base.encoder,
10648                      "connector's staged encoder doesn't match current encoder\n");
10649         }
10650 }
10651
10652 static void
10653 check_encoder_state(struct drm_device *dev)
10654 {
10655         struct intel_encoder *encoder;
10656         struct intel_connector *connector;
10657
10658         for_each_intel_encoder(dev, encoder) {
10659                 bool enabled = false;
10660                 bool active = false;
10661                 enum pipe pipe, tracked_pipe;
10662
10663                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10664                               encoder->base.base.id,
10665                               encoder->base.name);
10666
10667                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10668                      "encoder's stage crtc doesn't match current crtc\n");
10669                 WARN(encoder->connectors_active && !encoder->base.crtc,
10670                      "encoder's active_connectors set, but no crtc\n");
10671
10672                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10673                                     base.head) {
10674                         if (connector->base.encoder != &encoder->base)
10675                                 continue;
10676                         enabled = true;
10677                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10678                                 active = true;
10679                 }
10680                 /*
10681                  * for MST connectors if we unplug the connector is gone
10682                  * away but the encoder is still connected to a crtc
10683                  * until a modeset happens in response to the hotplug.
10684                  */
10685                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10686                         continue;
10687
10688                 WARN(!!encoder->base.crtc != enabled,
10689                      "encoder's enabled state mismatch "
10690                      "(expected %i, found %i)\n",
10691                      !!encoder->base.crtc, enabled);
10692                 WARN(active && !encoder->base.crtc,
10693                      "active encoder with no crtc\n");
10694
10695                 WARN(encoder->connectors_active != active,
10696                      "encoder's computed active state doesn't match tracked active state "
10697                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10698
10699                 active = encoder->get_hw_state(encoder, &pipe);
10700                 WARN(active != encoder->connectors_active,
10701                      "encoder's hw state doesn't match sw tracking "
10702                      "(expected %i, found %i)\n",
10703                      encoder->connectors_active, active);
10704
10705                 if (!encoder->base.crtc)
10706                         continue;
10707
10708                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10709                 WARN(active && pipe != tracked_pipe,
10710                      "active encoder's pipe doesn't match"
10711                      "(expected %i, found %i)\n",
10712                      tracked_pipe, pipe);
10713
10714         }
10715 }
10716
10717 static void
10718 check_crtc_state(struct drm_device *dev)
10719 {
10720         struct drm_i915_private *dev_priv = dev->dev_private;
10721         struct intel_crtc *crtc;
10722         struct intel_encoder *encoder;
10723         struct intel_crtc_config pipe_config;
10724
10725         for_each_intel_crtc(dev, crtc) {
10726                 bool enabled = false;
10727                 bool active = false;
10728
10729                 memset(&pipe_config, 0, sizeof(pipe_config));
10730
10731                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10732                               crtc->base.base.id);
10733
10734                 WARN(crtc->active && !crtc->base.enabled,
10735                      "active crtc, but not enabled in sw tracking\n");
10736
10737                 for_each_intel_encoder(dev, encoder) {
10738                         if (encoder->base.crtc != &crtc->base)
10739                                 continue;
10740                         enabled = true;
10741                         if (encoder->connectors_active)
10742                                 active = true;
10743                 }
10744
10745                 WARN(active != crtc->active,
10746                      "crtc's computed active state doesn't match tracked active state "
10747                      "(expected %i, found %i)\n", active, crtc->active);
10748                 WARN(enabled != crtc->base.enabled,
10749                      "crtc's computed enabled state doesn't match tracked enabled state "
10750                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10751
10752                 active = dev_priv->display.get_pipe_config(crtc,
10753                                                            &pipe_config);
10754
10755                 /* hw state is inconsistent with the pipe quirk */
10756                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10757                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10758                         active = crtc->active;
10759
10760                 for_each_intel_encoder(dev, encoder) {
10761                         enum pipe pipe;
10762                         if (encoder->base.crtc != &crtc->base)
10763                                 continue;
10764                         if (encoder->get_hw_state(encoder, &pipe))
10765                                 encoder->get_config(encoder, &pipe_config);
10766                 }
10767
10768                 WARN(crtc->active != active,
10769                      "crtc active state doesn't match with hw state "
10770                      "(expected %i, found %i)\n", crtc->active, active);
10771
10772                 if (active &&
10773                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10774                         WARN(1, "pipe state doesn't match!\n");
10775                         intel_dump_pipe_config(crtc, &pipe_config,
10776                                                "[hw state]");
10777                         intel_dump_pipe_config(crtc, &crtc->config,
10778                                                "[sw state]");
10779                 }
10780         }
10781 }
10782
10783 static void
10784 check_shared_dpll_state(struct drm_device *dev)
10785 {
10786         struct drm_i915_private *dev_priv = dev->dev_private;
10787         struct intel_crtc *crtc;
10788         struct intel_dpll_hw_state dpll_hw_state;
10789         int i;
10790
10791         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10792                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10793                 int enabled_crtcs = 0, active_crtcs = 0;
10794                 bool active;
10795
10796                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10797
10798                 DRM_DEBUG_KMS("%s\n", pll->name);
10799
10800                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10801
10802                 WARN(pll->active > pll->refcount,
10803                      "more active pll users than references: %i vs %i\n",
10804                      pll->active, pll->refcount);
10805                 WARN(pll->active && !pll->on,
10806                      "pll in active use but not on in sw tracking\n");
10807                 WARN(pll->on && !pll->active,
10808                      "pll in on but not on in use in sw tracking\n");
10809                 WARN(pll->on != active,
10810                      "pll on state mismatch (expected %i, found %i)\n",
10811                      pll->on, active);
10812
10813                 for_each_intel_crtc(dev, crtc) {
10814                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10815                                 enabled_crtcs++;
10816                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10817                                 active_crtcs++;
10818                 }
10819                 WARN(pll->active != active_crtcs,
10820                      "pll active crtcs mismatch (expected %i, found %i)\n",
10821                      pll->active, active_crtcs);
10822                 WARN(pll->refcount != enabled_crtcs,
10823                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10824                      pll->refcount, enabled_crtcs);
10825
10826                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10827                                        sizeof(dpll_hw_state)),
10828                      "pll hw state mismatch\n");
10829         }
10830 }
10831
10832 void
10833 intel_modeset_check_state(struct drm_device *dev)
10834 {
10835         check_connector_state(dev);
10836         check_encoder_state(dev);
10837         check_crtc_state(dev);
10838         check_shared_dpll_state(dev);
10839 }
10840
10841 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10842                                      int dotclock)
10843 {
10844         /*
10845          * FDI already provided one idea for the dotclock.
10846          * Yell if the encoder disagrees.
10847          */
10848         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10849              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10850              pipe_config->adjusted_mode.crtc_clock, dotclock);
10851 }
10852
10853 static void update_scanline_offset(struct intel_crtc *crtc)
10854 {
10855         struct drm_device *dev = crtc->base.dev;
10856
10857         /*
10858          * The scanline counter increments at the leading edge of hsync.
10859          *
10860          * On most platforms it starts counting from vtotal-1 on the
10861          * first active line. That means the scanline counter value is
10862          * always one less than what we would expect. Ie. just after
10863          * start of vblank, which also occurs at start of hsync (on the
10864          * last active line), the scanline counter will read vblank_start-1.
10865          *
10866          * On gen2 the scanline counter starts counting from 1 instead
10867          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10868          * to keep the value positive), instead of adding one.
10869          *
10870          * On HSW+ the behaviour of the scanline counter depends on the output
10871          * type. For DP ports it behaves like most other platforms, but on HDMI
10872          * there's an extra 1 line difference. So we need to add two instead of
10873          * one to the value.
10874          */
10875         if (IS_GEN2(dev)) {
10876                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10877                 int vtotal;
10878
10879                 vtotal = mode->crtc_vtotal;
10880                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10881                         vtotal /= 2;
10882
10883                 crtc->scanline_offset = vtotal - 1;
10884         } else if (HAS_DDI(dev) &&
10885                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10886                 crtc->scanline_offset = 2;
10887         } else
10888                 crtc->scanline_offset = 1;
10889 }
10890
10891 static int __intel_set_mode(struct drm_crtc *crtc,
10892                             struct drm_display_mode *mode,
10893                             int x, int y, struct drm_framebuffer *fb)
10894 {
10895         struct drm_device *dev = crtc->dev;
10896         struct drm_i915_private *dev_priv = dev->dev_private;
10897         struct drm_display_mode *saved_mode;
10898         struct intel_crtc_config *pipe_config = NULL;
10899         struct intel_crtc *intel_crtc;
10900         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10901         int ret = 0;
10902
10903         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10904         if (!saved_mode)
10905                 return -ENOMEM;
10906
10907         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10908                                      &prepare_pipes, &disable_pipes);
10909
10910         *saved_mode = crtc->mode;
10911
10912         /* Hack: Because we don't (yet) support global modeset on multiple
10913          * crtcs, we don't keep track of the new mode for more than one crtc.
10914          * Hence simply check whether any bit is set in modeset_pipes in all the
10915          * pieces of code that are not yet converted to deal with mutliple crtcs
10916          * changing their mode at the same time. */
10917         if (modeset_pipes) {
10918                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10919                 if (IS_ERR(pipe_config)) {
10920                         ret = PTR_ERR(pipe_config);
10921                         pipe_config = NULL;
10922
10923                         goto out;
10924                 }
10925                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10926                                        "[modeset]");
10927                 to_intel_crtc(crtc)->new_config = pipe_config;
10928         }
10929
10930         /*
10931          * See if the config requires any additional preparation, e.g.
10932          * to adjust global state with pipes off.  We need to do this
10933          * here so we can get the modeset_pipe updated config for the new
10934          * mode set on this crtc.  For other crtcs we need to use the
10935          * adjusted_mode bits in the crtc directly.
10936          */
10937         if (IS_VALLEYVIEW(dev)) {
10938                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10939
10940                 /* may have added more to prepare_pipes than we should */
10941                 prepare_pipes &= ~disable_pipes;
10942         }
10943
10944         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10945                 intel_crtc_disable(&intel_crtc->base);
10946
10947         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10948                 if (intel_crtc->base.enabled)
10949                         dev_priv->display.crtc_disable(&intel_crtc->base);
10950         }
10951
10952         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10953          * to set it here already despite that we pass it down the callchain.
10954          */
10955         if (modeset_pipes) {
10956                 crtc->mode = *mode;
10957                 /* mode_set/enable/disable functions rely on a correct pipe
10958                  * config. */
10959                 to_intel_crtc(crtc)->config = *pipe_config;
10960                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10961
10962                 /*
10963                  * Calculate and store various constants which
10964                  * are later needed by vblank and swap-completion
10965                  * timestamping. They are derived from true hwmode.
10966                  */
10967                 drm_calc_timestamping_constants(crtc,
10968                                                 &pipe_config->adjusted_mode);
10969         }
10970
10971         /* Only after disabling all output pipelines that will be changed can we
10972          * update the the output configuration. */
10973         intel_modeset_update_state(dev, prepare_pipes);
10974
10975         if (dev_priv->display.modeset_global_resources)
10976                 dev_priv->display.modeset_global_resources(dev);
10977
10978         /* Set up the DPLL and any encoders state that needs to adjust or depend
10979          * on the DPLL.
10980          */
10981         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10982                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10983                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10984                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10985
10986                 mutex_lock(&dev->struct_mutex);
10987                 ret = intel_pin_and_fence_fb_obj(dev,
10988                                                  obj,
10989                                                  NULL);
10990                 if (ret != 0) {
10991                         DRM_ERROR("pin & fence failed\n");
10992                         mutex_unlock(&dev->struct_mutex);
10993                         goto done;
10994                 }
10995                 if (old_fb)
10996                         intel_unpin_fb_obj(old_obj);
10997                 i915_gem_track_fb(old_obj, obj,
10998                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10999                 mutex_unlock(&dev->struct_mutex);
11000
11001                 crtc->primary->fb = fb;
11002                 crtc->x = x;
11003                 crtc->y = y;
11004
11005                 ret = dev_priv->display.crtc_mode_set(intel_crtc, x, y, fb);
11006                 if (ret)
11007                         goto done;
11008         }
11009
11010         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11011         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11012                 update_scanline_offset(intel_crtc);
11013
11014                 dev_priv->display.crtc_enable(&intel_crtc->base);
11015         }
11016
11017         /* FIXME: add subpixel order */
11018 done:
11019         if (ret && crtc->enabled)
11020                 crtc->mode = *saved_mode;
11021
11022 out:
11023         kfree(pipe_config);
11024         kfree(saved_mode);
11025         return ret;
11026 }
11027
11028 static int intel_set_mode(struct drm_crtc *crtc,
11029                           struct drm_display_mode *mode,
11030                           int x, int y, struct drm_framebuffer *fb)
11031 {
11032         int ret;
11033
11034         ret = __intel_set_mode(crtc, mode, x, y, fb);
11035
11036         if (ret == 0)
11037                 intel_modeset_check_state(crtc->dev);
11038
11039         return ret;
11040 }
11041
11042 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11043 {
11044         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11045 }
11046
11047 #undef for_each_intel_crtc_masked
11048
11049 static void intel_set_config_free(struct intel_set_config *config)
11050 {
11051         if (!config)
11052                 return;
11053
11054         kfree(config->save_connector_encoders);
11055         kfree(config->save_encoder_crtcs);
11056         kfree(config->save_crtc_enabled);
11057         kfree(config);
11058 }
11059
11060 static int intel_set_config_save_state(struct drm_device *dev,
11061                                        struct intel_set_config *config)
11062 {
11063         struct drm_crtc *crtc;
11064         struct drm_encoder *encoder;
11065         struct drm_connector *connector;
11066         int count;
11067
11068         config->save_crtc_enabled =
11069                 kcalloc(dev->mode_config.num_crtc,
11070                         sizeof(bool), GFP_KERNEL);
11071         if (!config->save_crtc_enabled)
11072                 return -ENOMEM;
11073
11074         config->save_encoder_crtcs =
11075                 kcalloc(dev->mode_config.num_encoder,
11076                         sizeof(struct drm_crtc *), GFP_KERNEL);
11077         if (!config->save_encoder_crtcs)
11078                 return -ENOMEM;
11079
11080         config->save_connector_encoders =
11081                 kcalloc(dev->mode_config.num_connector,
11082                         sizeof(struct drm_encoder *), GFP_KERNEL);
11083         if (!config->save_connector_encoders)
11084                 return -ENOMEM;
11085
11086         /* Copy data. Note that driver private data is not affected.
11087          * Should anything bad happen only the expected state is
11088          * restored, not the drivers personal bookkeeping.
11089          */
11090         count = 0;
11091         for_each_crtc(dev, crtc) {
11092                 config->save_crtc_enabled[count++] = crtc->enabled;
11093         }
11094
11095         count = 0;
11096         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11097                 config->save_encoder_crtcs[count++] = encoder->crtc;
11098         }
11099
11100         count = 0;
11101         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11102                 config->save_connector_encoders[count++] = connector->encoder;
11103         }
11104
11105         return 0;
11106 }
11107
11108 static void intel_set_config_restore_state(struct drm_device *dev,
11109                                            struct intel_set_config *config)
11110 {
11111         struct intel_crtc *crtc;
11112         struct intel_encoder *encoder;
11113         struct intel_connector *connector;
11114         int count;
11115
11116         count = 0;
11117         for_each_intel_crtc(dev, crtc) {
11118                 crtc->new_enabled = config->save_crtc_enabled[count++];
11119
11120                 if (crtc->new_enabled)
11121                         crtc->new_config = &crtc->config;
11122                 else
11123                         crtc->new_config = NULL;
11124         }
11125
11126         count = 0;
11127         for_each_intel_encoder(dev, encoder) {
11128                 encoder->new_crtc =
11129                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11130         }
11131
11132         count = 0;
11133         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11134                 connector->new_encoder =
11135                         to_intel_encoder(config->save_connector_encoders[count++]);
11136         }
11137 }
11138
11139 static bool
11140 is_crtc_connector_off(struct drm_mode_set *set)
11141 {
11142         int i;
11143
11144         if (set->num_connectors == 0)
11145                 return false;
11146
11147         if (WARN_ON(set->connectors == NULL))
11148                 return false;
11149
11150         for (i = 0; i < set->num_connectors; i++)
11151                 if (set->connectors[i]->encoder &&
11152                     set->connectors[i]->encoder->crtc == set->crtc &&
11153                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11154                         return true;
11155
11156         return false;
11157 }
11158
11159 static void
11160 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11161                                       struct intel_set_config *config)
11162 {
11163
11164         /* We should be able to check here if the fb has the same properties
11165          * and then just flip_or_move it */
11166         if (is_crtc_connector_off(set)) {
11167                 config->mode_changed = true;
11168         } else if (set->crtc->primary->fb != set->fb) {
11169                 /*
11170                  * If we have no fb, we can only flip as long as the crtc is
11171                  * active, otherwise we need a full mode set.  The crtc may
11172                  * be active if we've only disabled the primary plane, or
11173                  * in fastboot situations.
11174                  */
11175                 if (set->crtc->primary->fb == NULL) {
11176                         struct intel_crtc *intel_crtc =
11177                                 to_intel_crtc(set->crtc);
11178
11179                         if (intel_crtc->active) {
11180                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11181                                 config->fb_changed = true;
11182                         } else {
11183                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11184                                 config->mode_changed = true;
11185                         }
11186                 } else if (set->fb == NULL) {
11187                         config->mode_changed = true;
11188                 } else if (set->fb->pixel_format !=
11189                            set->crtc->primary->fb->pixel_format) {
11190                         config->mode_changed = true;
11191                 } else {
11192                         config->fb_changed = true;
11193                 }
11194         }
11195
11196         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11197                 config->fb_changed = true;
11198
11199         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11200                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11201                 drm_mode_debug_printmodeline(&set->crtc->mode);
11202                 drm_mode_debug_printmodeline(set->mode);
11203                 config->mode_changed = true;
11204         }
11205
11206         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11207                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11208 }
11209
11210 static int
11211 intel_modeset_stage_output_state(struct drm_device *dev,
11212                                  struct drm_mode_set *set,
11213                                  struct intel_set_config *config)
11214 {
11215         struct intel_connector *connector;
11216         struct intel_encoder *encoder;
11217         struct intel_crtc *crtc;
11218         int ro;
11219
11220         /* The upper layers ensure that we either disable a crtc or have a list
11221          * of connectors. For paranoia, double-check this. */
11222         WARN_ON(!set->fb && (set->num_connectors != 0));
11223         WARN_ON(set->fb && (set->num_connectors == 0));
11224
11225         list_for_each_entry(connector, &dev->mode_config.connector_list,
11226                             base.head) {
11227                 /* Otherwise traverse passed in connector list and get encoders
11228                  * for them. */
11229                 for (ro = 0; ro < set->num_connectors; ro++) {
11230                         if (set->connectors[ro] == &connector->base) {
11231                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11232                                 break;
11233                         }
11234                 }
11235
11236                 /* If we disable the crtc, disable all its connectors. Also, if
11237                  * the connector is on the changing crtc but not on the new
11238                  * connector list, disable it. */
11239                 if ((!set->fb || ro == set->num_connectors) &&
11240                     connector->base.encoder &&
11241                     connector->base.encoder->crtc == set->crtc) {
11242                         connector->new_encoder = NULL;
11243
11244                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11245                                 connector->base.base.id,
11246                                 connector->base.name);
11247                 }
11248
11249
11250                 if (&connector->new_encoder->base != connector->base.encoder) {
11251                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11252                         config->mode_changed = true;
11253                 }
11254         }
11255         /* connector->new_encoder is now updated for all connectors. */
11256
11257         /* Update crtc of enabled connectors. */
11258         list_for_each_entry(connector, &dev->mode_config.connector_list,
11259                             base.head) {
11260                 struct drm_crtc *new_crtc;
11261
11262                 if (!connector->new_encoder)
11263                         continue;
11264
11265                 new_crtc = connector->new_encoder->base.crtc;
11266
11267                 for (ro = 0; ro < set->num_connectors; ro++) {
11268                         if (set->connectors[ro] == &connector->base)
11269                                 new_crtc = set->crtc;
11270                 }
11271
11272                 /* Make sure the new CRTC will work with the encoder */
11273                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11274                                          new_crtc)) {
11275                         return -EINVAL;
11276                 }
11277                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11278
11279                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11280                         connector->base.base.id,
11281                         connector->base.name,
11282                         new_crtc->base.id);
11283         }
11284
11285         /* Check for any encoders that needs to be disabled. */
11286         for_each_intel_encoder(dev, encoder) {
11287                 int num_connectors = 0;
11288                 list_for_each_entry(connector,
11289                                     &dev->mode_config.connector_list,
11290                                     base.head) {
11291                         if (connector->new_encoder == encoder) {
11292                                 WARN_ON(!connector->new_encoder->new_crtc);
11293                                 num_connectors++;
11294                         }
11295                 }
11296
11297                 if (num_connectors == 0)
11298                         encoder->new_crtc = NULL;
11299                 else if (num_connectors > 1)
11300                         return -EINVAL;
11301
11302                 /* Only now check for crtc changes so we don't miss encoders
11303                  * that will be disabled. */
11304                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11305                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11306                         config->mode_changed = true;
11307                 }
11308         }
11309         /* Now we've also updated encoder->new_crtc for all encoders. */
11310         list_for_each_entry(connector, &dev->mode_config.connector_list,
11311                             base.head) {
11312                 if (connector->new_encoder)
11313                         if (connector->new_encoder != connector->encoder)
11314                                 connector->encoder = connector->new_encoder;
11315         }
11316         for_each_intel_crtc(dev, crtc) {
11317                 crtc->new_enabled = false;
11318
11319                 for_each_intel_encoder(dev, encoder) {
11320                         if (encoder->new_crtc == crtc) {
11321                                 crtc->new_enabled = true;
11322                                 break;
11323                         }
11324                 }
11325
11326                 if (crtc->new_enabled != crtc->base.enabled) {
11327                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11328                                       crtc->new_enabled ? "en" : "dis");
11329                         config->mode_changed = true;
11330                 }
11331
11332                 if (crtc->new_enabled)
11333                         crtc->new_config = &crtc->config;
11334                 else
11335                         crtc->new_config = NULL;
11336         }
11337
11338         return 0;
11339 }
11340
11341 static void disable_crtc_nofb(struct intel_crtc *crtc)
11342 {
11343         struct drm_device *dev = crtc->base.dev;
11344         struct intel_encoder *encoder;
11345         struct intel_connector *connector;
11346
11347         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11348                       pipe_name(crtc->pipe));
11349
11350         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11351                 if (connector->new_encoder &&
11352                     connector->new_encoder->new_crtc == crtc)
11353                         connector->new_encoder = NULL;
11354         }
11355
11356         for_each_intel_encoder(dev, encoder) {
11357                 if (encoder->new_crtc == crtc)
11358                         encoder->new_crtc = NULL;
11359         }
11360
11361         crtc->new_enabled = false;
11362         crtc->new_config = NULL;
11363 }
11364
11365 static int intel_crtc_set_config(struct drm_mode_set *set)
11366 {
11367         struct drm_device *dev;
11368         struct drm_mode_set save_set;
11369         struct intel_set_config *config;
11370         int ret;
11371
11372         BUG_ON(!set);
11373         BUG_ON(!set->crtc);
11374         BUG_ON(!set->crtc->helper_private);
11375
11376         /* Enforce sane interface api - has been abused by the fb helper. */
11377         BUG_ON(!set->mode && set->fb);
11378         BUG_ON(set->fb && set->num_connectors == 0);
11379
11380         if (set->fb) {
11381                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11382                                 set->crtc->base.id, set->fb->base.id,
11383                                 (int)set->num_connectors, set->x, set->y);
11384         } else {
11385                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11386         }
11387
11388         dev = set->crtc->dev;
11389
11390         ret = -ENOMEM;
11391         config = kzalloc(sizeof(*config), GFP_KERNEL);
11392         if (!config)
11393                 goto out_config;
11394
11395         ret = intel_set_config_save_state(dev, config);
11396         if (ret)
11397                 goto out_config;
11398
11399         save_set.crtc = set->crtc;
11400         save_set.mode = &set->crtc->mode;
11401         save_set.x = set->crtc->x;
11402         save_set.y = set->crtc->y;
11403         save_set.fb = set->crtc->primary->fb;
11404
11405         /* Compute whether we need a full modeset, only an fb base update or no
11406          * change at all. In the future we might also check whether only the
11407          * mode changed, e.g. for LVDS where we only change the panel fitter in
11408          * such cases. */
11409         intel_set_config_compute_mode_changes(set, config);
11410
11411         ret = intel_modeset_stage_output_state(dev, set, config);
11412         if (ret)
11413                 goto fail;
11414
11415         if (config->mode_changed) {
11416                 ret = intel_set_mode(set->crtc, set->mode,
11417                                      set->x, set->y, set->fb);
11418         } else if (config->fb_changed) {
11419                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11420
11421                 intel_crtc_wait_for_pending_flips(set->crtc);
11422
11423                 ret = intel_pipe_set_base(set->crtc,
11424                                           set->x, set->y, set->fb);
11425
11426                 /*
11427                  * We need to make sure the primary plane is re-enabled if it
11428                  * has previously been turned off.
11429                  */
11430                 if (!intel_crtc->primary_enabled && ret == 0) {
11431                         WARN_ON(!intel_crtc->active);
11432                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11433                 }
11434
11435                 /*
11436                  * In the fastboot case this may be our only check of the
11437                  * state after boot.  It would be better to only do it on
11438                  * the first update, but we don't have a nice way of doing that
11439                  * (and really, set_config isn't used much for high freq page
11440                  * flipping, so increasing its cost here shouldn't be a big
11441                  * deal).
11442                  */
11443                 if (i915.fastboot && ret == 0)
11444                         intel_modeset_check_state(set->crtc->dev);
11445         }
11446
11447         if (ret) {
11448                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11449                               set->crtc->base.id, ret);
11450 fail:
11451                 intel_set_config_restore_state(dev, config);
11452
11453                 /*
11454                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11455                  * force the pipe off to avoid oopsing in the modeset code
11456                  * due to fb==NULL. This should only happen during boot since
11457                  * we don't yet reconstruct the FB from the hardware state.
11458                  */
11459                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11460                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11461
11462                 /* Try to restore the config */
11463                 if (config->mode_changed &&
11464                     intel_set_mode(save_set.crtc, save_set.mode,
11465                                    save_set.x, save_set.y, save_set.fb))
11466                         DRM_ERROR("failed to restore config after modeset failure\n");
11467         }
11468
11469 out_config:
11470         intel_set_config_free(config);
11471         return ret;
11472 }
11473
11474 static const struct drm_crtc_funcs intel_crtc_funcs = {
11475         .gamma_set = intel_crtc_gamma_set,
11476         .set_config = intel_crtc_set_config,
11477         .destroy = intel_crtc_destroy,
11478         .page_flip = intel_crtc_page_flip,
11479 };
11480
11481 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11482                                       struct intel_shared_dpll *pll,
11483                                       struct intel_dpll_hw_state *hw_state)
11484 {
11485         uint32_t val;
11486
11487         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11488                 return false;
11489
11490         val = I915_READ(PCH_DPLL(pll->id));
11491         hw_state->dpll = val;
11492         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11493         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11494
11495         return val & DPLL_VCO_ENABLE;
11496 }
11497
11498 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11499                                   struct intel_shared_dpll *pll)
11500 {
11501         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11502         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11503 }
11504
11505 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11506                                 struct intel_shared_dpll *pll)
11507 {
11508         /* PCH refclock must be enabled first */
11509         ibx_assert_pch_refclk_enabled(dev_priv);
11510
11511         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11512
11513         /* Wait for the clocks to stabilize. */
11514         POSTING_READ(PCH_DPLL(pll->id));
11515         udelay(150);
11516
11517         /* The pixel multiplier can only be updated once the
11518          * DPLL is enabled and the clocks are stable.
11519          *
11520          * So write it again.
11521          */
11522         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11523         POSTING_READ(PCH_DPLL(pll->id));
11524         udelay(200);
11525 }
11526
11527 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11528                                  struct intel_shared_dpll *pll)
11529 {
11530         struct drm_device *dev = dev_priv->dev;
11531         struct intel_crtc *crtc;
11532
11533         /* Make sure no transcoder isn't still depending on us. */
11534         for_each_intel_crtc(dev, crtc) {
11535                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11536                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11537         }
11538
11539         I915_WRITE(PCH_DPLL(pll->id), 0);
11540         POSTING_READ(PCH_DPLL(pll->id));
11541         udelay(200);
11542 }
11543
11544 static char *ibx_pch_dpll_names[] = {
11545         "PCH DPLL A",
11546         "PCH DPLL B",
11547 };
11548
11549 static void ibx_pch_dpll_init(struct drm_device *dev)
11550 {
11551         struct drm_i915_private *dev_priv = dev->dev_private;
11552         int i;
11553
11554         dev_priv->num_shared_dpll = 2;
11555
11556         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11557                 dev_priv->shared_dplls[i].id = i;
11558                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11559                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11560                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11561                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11562                 dev_priv->shared_dplls[i].get_hw_state =
11563                         ibx_pch_dpll_get_hw_state;
11564         }
11565 }
11566
11567 static void intel_shared_dpll_init(struct drm_device *dev)
11568 {
11569         struct drm_i915_private *dev_priv = dev->dev_private;
11570
11571         if (HAS_DDI(dev))
11572                 intel_ddi_pll_init(dev);
11573         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11574                 ibx_pch_dpll_init(dev);
11575         else
11576                 dev_priv->num_shared_dpll = 0;
11577
11578         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11579 }
11580
11581 static int
11582 intel_primary_plane_disable(struct drm_plane *plane)
11583 {
11584         struct drm_device *dev = plane->dev;
11585         struct intel_crtc *intel_crtc;
11586
11587         if (!plane->fb)
11588                 return 0;
11589
11590         BUG_ON(!plane->crtc);
11591
11592         intel_crtc = to_intel_crtc(plane->crtc);
11593
11594         /*
11595          * Even though we checked plane->fb above, it's still possible that
11596          * the primary plane has been implicitly disabled because the crtc
11597          * coordinates given weren't visible, or because we detected
11598          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11599          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11600          * In either case, we need to unpin the FB and let the fb pointer get
11601          * updated, but otherwise we don't need to touch the hardware.
11602          */
11603         if (!intel_crtc->primary_enabled)
11604                 goto disable_unpin;
11605
11606         intel_crtc_wait_for_pending_flips(plane->crtc);
11607         intel_disable_primary_hw_plane(plane, plane->crtc);
11608
11609 disable_unpin:
11610         mutex_lock(&dev->struct_mutex);
11611         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11612                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11613         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11614         mutex_unlock(&dev->struct_mutex);
11615         plane->fb = NULL;
11616
11617         return 0;
11618 }
11619
11620 static int
11621 intel_check_primary_plane(struct drm_plane *plane,
11622                           struct intel_plane_state *state)
11623 {
11624         struct drm_crtc *crtc = state->crtc;
11625         struct drm_framebuffer *fb = state->fb;
11626         struct drm_rect *dest = &state->dst;
11627         struct drm_rect *src = &state->src;
11628         const struct drm_rect *clip = &state->clip;
11629         int ret;
11630
11631         ret = drm_plane_helper_check_update(plane, crtc, fb,
11632                                             src, dest, clip,
11633                                             DRM_PLANE_HELPER_NO_SCALING,
11634                                             DRM_PLANE_HELPER_NO_SCALING,
11635                                             false, true, &state->visible);
11636         if (ret)
11637                 return ret;
11638
11639         /* no fb bound */
11640         if (state->visible && !fb) {
11641                 DRM_ERROR("No FB bound\n");
11642                 return -EINVAL;
11643         }
11644
11645         return 0;
11646 }
11647
11648 static int
11649 intel_commit_primary_plane(struct drm_plane *plane,
11650                            struct intel_plane_state *state)
11651 {
11652         struct drm_crtc *crtc = state->crtc;
11653         struct drm_framebuffer *fb = state->fb;
11654         struct drm_device *dev = crtc->dev;
11655         struct drm_i915_private *dev_priv = dev->dev_private;
11656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11657         enum pipe pipe = intel_crtc->pipe;
11658         struct drm_framebuffer *old_fb = plane->fb;
11659         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11660         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11661         struct intel_plane *intel_plane = to_intel_plane(plane);
11662         struct drm_rect *src = &state->src;
11663         int ret;
11664
11665         intel_crtc_wait_for_pending_flips(crtc);
11666
11667         if (intel_crtc_has_pending_flip(crtc)) {
11668                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11669                 return -EBUSY;
11670         }
11671
11672         if (plane->fb != fb) {
11673                 mutex_lock(&dev->struct_mutex);
11674                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11675                 if (ret == 0)
11676                         i915_gem_track_fb(old_obj, obj,
11677                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11678                 mutex_unlock(&dev->struct_mutex);
11679                 if (ret != 0) {
11680                         DRM_DEBUG_KMS("pin & fence failed\n");
11681                         return ret;
11682                 }
11683         }
11684
11685         crtc->primary->fb = fb;
11686         crtc->x = src->x1;
11687         crtc->y = src->y1;
11688
11689         intel_plane->crtc_x = state->orig_dst.x1;
11690         intel_plane->crtc_y = state->orig_dst.y1;
11691         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11692         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11693         intel_plane->src_x = state->orig_src.x1;
11694         intel_plane->src_y = state->orig_src.y1;
11695         intel_plane->src_w = drm_rect_width(&state->orig_src);
11696         intel_plane->src_h = drm_rect_height(&state->orig_src);
11697         intel_plane->obj = obj;
11698
11699         if (intel_crtc->active) {
11700                 /*
11701                  * FBC does not work on some platforms for rotated
11702                  * planes, so disable it when rotation is not 0 and
11703                  * update it when rotation is set back to 0.
11704                  *
11705                  * FIXME: This is redundant with the fbc update done in
11706                  * the primary plane enable function except that that
11707                  * one is done too late. We eventually need to unify
11708                  * this.
11709                  */
11710                 if (intel_crtc->primary_enabled &&
11711                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11712                     dev_priv->fbc.plane == intel_crtc->plane &&
11713                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11714                         intel_disable_fbc(dev);
11715                 }
11716
11717                 if (state->visible) {
11718                         bool was_enabled = intel_crtc->primary_enabled;
11719
11720                         /* FIXME: kill this fastboot hack */
11721                         intel_update_pipe_size(intel_crtc);
11722
11723                         intel_crtc->primary_enabled = true;
11724
11725                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11726                                         crtc->x, crtc->y);
11727
11728                         /*
11729                          * BDW signals flip done immediately if the plane
11730                          * is disabled, even if the plane enable is already
11731                          * armed to occur at the next vblank :(
11732                          */
11733                         if (IS_BROADWELL(dev) && !was_enabled)
11734                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11735                 } else {
11736                         /*
11737                          * If clipping results in a non-visible primary plane,
11738                          * we'll disable the primary plane.  Note that this is
11739                          * a bit different than what happens if userspace
11740                          * explicitly disables the plane by passing fb=0
11741                          * because plane->fb still gets set and pinned.
11742                          */
11743                         intel_disable_primary_hw_plane(plane, crtc);
11744                 }
11745
11746                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11747
11748                 mutex_lock(&dev->struct_mutex);
11749                 intel_update_fbc(dev);
11750                 mutex_unlock(&dev->struct_mutex);
11751         }
11752
11753         if (old_fb && old_fb != fb) {
11754                 if (intel_crtc->active)
11755                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11756
11757                 mutex_lock(&dev->struct_mutex);
11758                 intel_unpin_fb_obj(old_obj);
11759                 mutex_unlock(&dev->struct_mutex);
11760         }
11761
11762         return 0;
11763 }
11764
11765 static int
11766 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11767                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11768                              unsigned int crtc_w, unsigned int crtc_h,
11769                              uint32_t src_x, uint32_t src_y,
11770                              uint32_t src_w, uint32_t src_h)
11771 {
11772         struct intel_plane_state state;
11773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11774         int ret;
11775
11776         state.crtc = crtc;
11777         state.fb = fb;
11778
11779         /* sample coordinates in 16.16 fixed point */
11780         state.src.x1 = src_x;
11781         state.src.x2 = src_x + src_w;
11782         state.src.y1 = src_y;
11783         state.src.y2 = src_y + src_h;
11784
11785         /* integer pixels */
11786         state.dst.x1 = crtc_x;
11787         state.dst.x2 = crtc_x + crtc_w;
11788         state.dst.y1 = crtc_y;
11789         state.dst.y2 = crtc_y + crtc_h;
11790
11791         state.clip.x1 = 0;
11792         state.clip.y1 = 0;
11793         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11794         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11795
11796         state.orig_src = state.src;
11797         state.orig_dst = state.dst;
11798
11799         ret = intel_check_primary_plane(plane, &state);
11800         if (ret)
11801                 return ret;
11802
11803         intel_commit_primary_plane(plane, &state);
11804
11805         return 0;
11806 }
11807
11808 /* Common destruction function for both primary and cursor planes */
11809 static void intel_plane_destroy(struct drm_plane *plane)
11810 {
11811         struct intel_plane *intel_plane = to_intel_plane(plane);
11812         drm_plane_cleanup(plane);
11813         kfree(intel_plane);
11814 }
11815
11816 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11817         .update_plane = intel_primary_plane_setplane,
11818         .disable_plane = intel_primary_plane_disable,
11819         .destroy = intel_plane_destroy,
11820         .set_property = intel_plane_set_property
11821 };
11822
11823 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11824                                                     int pipe)
11825 {
11826         struct intel_plane *primary;
11827         const uint32_t *intel_primary_formats;
11828         int num_formats;
11829
11830         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11831         if (primary == NULL)
11832                 return NULL;
11833
11834         primary->can_scale = false;
11835         primary->max_downscale = 1;
11836         primary->pipe = pipe;
11837         primary->plane = pipe;
11838         primary->rotation = BIT(DRM_ROTATE_0);
11839         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11840                 primary->plane = !pipe;
11841
11842         if (INTEL_INFO(dev)->gen <= 3) {
11843                 intel_primary_formats = intel_primary_formats_gen2;
11844                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11845         } else {
11846                 intel_primary_formats = intel_primary_formats_gen4;
11847                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11848         }
11849
11850         drm_universal_plane_init(dev, &primary->base, 0,
11851                                  &intel_primary_plane_funcs,
11852                                  intel_primary_formats, num_formats,
11853                                  DRM_PLANE_TYPE_PRIMARY);
11854
11855         if (INTEL_INFO(dev)->gen >= 4) {
11856                 if (!dev->mode_config.rotation_property)
11857                         dev->mode_config.rotation_property =
11858                                 drm_mode_create_rotation_property(dev,
11859                                                         BIT(DRM_ROTATE_0) |
11860                                                         BIT(DRM_ROTATE_180));
11861                 if (dev->mode_config.rotation_property)
11862                         drm_object_attach_property(&primary->base.base,
11863                                 dev->mode_config.rotation_property,
11864                                 primary->rotation);
11865         }
11866
11867         return &primary->base;
11868 }
11869
11870 static int
11871 intel_cursor_plane_disable(struct drm_plane *plane)
11872 {
11873         if (!plane->fb)
11874                 return 0;
11875
11876         BUG_ON(!plane->crtc);
11877
11878         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11879 }
11880
11881 static int
11882 intel_check_cursor_plane(struct drm_plane *plane,
11883                          struct intel_plane_state *state)
11884 {
11885         struct drm_crtc *crtc = state->crtc;
11886         struct drm_device *dev = crtc->dev;
11887         struct drm_framebuffer *fb = state->fb;
11888         struct drm_rect *dest = &state->dst;
11889         struct drm_rect *src = &state->src;
11890         const struct drm_rect *clip = &state->clip;
11891         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11892         int crtc_w, crtc_h;
11893         unsigned stride;
11894         int ret;
11895
11896         ret = drm_plane_helper_check_update(plane, crtc, fb,
11897                                             src, dest, clip,
11898                                             DRM_PLANE_HELPER_NO_SCALING,
11899                                             DRM_PLANE_HELPER_NO_SCALING,
11900                                             true, true, &state->visible);
11901         if (ret)
11902                 return ret;
11903
11904
11905         /* if we want to turn off the cursor ignore width and height */
11906         if (!obj)
11907                 return 0;
11908
11909         /* Check for which cursor types we support */
11910         crtc_w = drm_rect_width(&state->orig_dst);
11911         crtc_h = drm_rect_height(&state->orig_dst);
11912         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11913                 DRM_DEBUG("Cursor dimension not supported\n");
11914                 return -EINVAL;
11915         }
11916
11917         stride = roundup_pow_of_two(crtc_w) * 4;
11918         if (obj->base.size < stride * crtc_h) {
11919                 DRM_DEBUG_KMS("buffer is too small\n");
11920                 return -ENOMEM;
11921         }
11922
11923         if (fb == crtc->cursor->fb)
11924                 return 0;
11925
11926         /* we only need to pin inside GTT if cursor is non-phy */
11927         mutex_lock(&dev->struct_mutex);
11928         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11929                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11930                 ret = -EINVAL;
11931         }
11932         mutex_unlock(&dev->struct_mutex);
11933
11934         return ret;
11935 }
11936
11937 static int
11938 intel_commit_cursor_plane(struct drm_plane *plane,
11939                           struct intel_plane_state *state)
11940 {
11941         struct drm_crtc *crtc = state->crtc;
11942         struct drm_framebuffer *fb = state->fb;
11943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11944         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11945         struct drm_i915_gem_object *obj = intel_fb->obj;
11946         int crtc_w, crtc_h;
11947
11948         crtc->cursor_x = state->orig_dst.x1;
11949         crtc->cursor_y = state->orig_dst.y1;
11950         if (fb != crtc->cursor->fb) {
11951                 crtc_w = drm_rect_width(&state->orig_dst);
11952                 crtc_h = drm_rect_height(&state->orig_dst);
11953                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11954         } else {
11955                 intel_crtc_update_cursor(crtc, state->visible);
11956
11957                 intel_frontbuffer_flip(crtc->dev,
11958                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11959
11960                 return 0;
11961         }
11962 }
11963
11964 static int
11965 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11966                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11967                           unsigned int crtc_w, unsigned int crtc_h,
11968                           uint32_t src_x, uint32_t src_y,
11969                           uint32_t src_w, uint32_t src_h)
11970 {
11971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11972         struct intel_plane_state state;
11973         int ret;
11974
11975         state.crtc = crtc;
11976         state.fb = fb;
11977
11978         /* sample coordinates in 16.16 fixed point */
11979         state.src.x1 = src_x;
11980         state.src.x2 = src_x + src_w;
11981         state.src.y1 = src_y;
11982         state.src.y2 = src_y + src_h;
11983
11984         /* integer pixels */
11985         state.dst.x1 = crtc_x;
11986         state.dst.x2 = crtc_x + crtc_w;
11987         state.dst.y1 = crtc_y;
11988         state.dst.y2 = crtc_y + crtc_h;
11989
11990         state.clip.x1 = 0;
11991         state.clip.y1 = 0;
11992         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11993         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11994
11995         state.orig_src = state.src;
11996         state.orig_dst = state.dst;
11997
11998         ret = intel_check_cursor_plane(plane, &state);
11999         if (ret)
12000                 return ret;
12001
12002         return intel_commit_cursor_plane(plane, &state);
12003 }
12004
12005 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12006         .update_plane = intel_cursor_plane_update,
12007         .disable_plane = intel_cursor_plane_disable,
12008         .destroy = intel_plane_destroy,
12009 };
12010
12011 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12012                                                    int pipe)
12013 {
12014         struct intel_plane *cursor;
12015
12016         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12017         if (cursor == NULL)
12018                 return NULL;
12019
12020         cursor->can_scale = false;
12021         cursor->max_downscale = 1;
12022         cursor->pipe = pipe;
12023         cursor->plane = pipe;
12024
12025         drm_universal_plane_init(dev, &cursor->base, 0,
12026                                  &intel_cursor_plane_funcs,
12027                                  intel_cursor_formats,
12028                                  ARRAY_SIZE(intel_cursor_formats),
12029                                  DRM_PLANE_TYPE_CURSOR);
12030         return &cursor->base;
12031 }
12032
12033 static void intel_crtc_init(struct drm_device *dev, int pipe)
12034 {
12035         struct drm_i915_private *dev_priv = dev->dev_private;
12036         struct intel_crtc *intel_crtc;
12037         struct drm_plane *primary = NULL;
12038         struct drm_plane *cursor = NULL;
12039         int i, ret;
12040
12041         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12042         if (intel_crtc == NULL)
12043                 return;
12044
12045         primary = intel_primary_plane_create(dev, pipe);
12046         if (!primary)
12047                 goto fail;
12048
12049         cursor = intel_cursor_plane_create(dev, pipe);
12050         if (!cursor)
12051                 goto fail;
12052
12053         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12054                                         cursor, &intel_crtc_funcs);
12055         if (ret)
12056                 goto fail;
12057
12058         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12059         for (i = 0; i < 256; i++) {
12060                 intel_crtc->lut_r[i] = i;
12061                 intel_crtc->lut_g[i] = i;
12062                 intel_crtc->lut_b[i] = i;
12063         }
12064
12065         /*
12066          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12067          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12068          */
12069         intel_crtc->pipe = pipe;
12070         intel_crtc->plane = pipe;
12071         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12072                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12073                 intel_crtc->plane = !pipe;
12074         }
12075
12076         intel_crtc->cursor_base = ~0;
12077         intel_crtc->cursor_cntl = ~0;
12078         intel_crtc->cursor_size = ~0;
12079
12080         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12081                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12082         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12083         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12084
12085         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12086
12087         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12088         return;
12089
12090 fail:
12091         if (primary)
12092                 drm_plane_cleanup(primary);
12093         if (cursor)
12094                 drm_plane_cleanup(cursor);
12095         kfree(intel_crtc);
12096 }
12097
12098 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12099 {
12100         struct drm_encoder *encoder = connector->base.encoder;
12101         struct drm_device *dev = connector->base.dev;
12102
12103         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12104
12105         if (!encoder)
12106                 return INVALID_PIPE;
12107
12108         return to_intel_crtc(encoder->crtc)->pipe;
12109 }
12110
12111 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12112                                 struct drm_file *file)
12113 {
12114         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12115         struct drm_crtc *drmmode_crtc;
12116         struct intel_crtc *crtc;
12117
12118         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12119                 return -ENODEV;
12120
12121         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12122
12123         if (!drmmode_crtc) {
12124                 DRM_ERROR("no such CRTC id\n");
12125                 return -ENOENT;
12126         }
12127
12128         crtc = to_intel_crtc(drmmode_crtc);
12129         pipe_from_crtc_id->pipe = crtc->pipe;
12130
12131         return 0;
12132 }
12133
12134 static int intel_encoder_clones(struct intel_encoder *encoder)
12135 {
12136         struct drm_device *dev = encoder->base.dev;
12137         struct intel_encoder *source_encoder;
12138         int index_mask = 0;
12139         int entry = 0;
12140
12141         for_each_intel_encoder(dev, source_encoder) {
12142                 if (encoders_cloneable(encoder, source_encoder))
12143                         index_mask |= (1 << entry);
12144
12145                 entry++;
12146         }
12147
12148         return index_mask;
12149 }
12150
12151 static bool has_edp_a(struct drm_device *dev)
12152 {
12153         struct drm_i915_private *dev_priv = dev->dev_private;
12154
12155         if (!IS_MOBILE(dev))
12156                 return false;
12157
12158         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12159                 return false;
12160
12161         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12162                 return false;
12163
12164         return true;
12165 }
12166
12167 const char *intel_output_name(int output)
12168 {
12169         static const char *names[] = {
12170                 [INTEL_OUTPUT_UNUSED] = "Unused",
12171                 [INTEL_OUTPUT_ANALOG] = "Analog",
12172                 [INTEL_OUTPUT_DVO] = "DVO",
12173                 [INTEL_OUTPUT_SDVO] = "SDVO",
12174                 [INTEL_OUTPUT_LVDS] = "LVDS",
12175                 [INTEL_OUTPUT_TVOUT] = "TV",
12176                 [INTEL_OUTPUT_HDMI] = "HDMI",
12177                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12178                 [INTEL_OUTPUT_EDP] = "eDP",
12179                 [INTEL_OUTPUT_DSI] = "DSI",
12180                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12181         };
12182
12183         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12184                 return "Invalid";
12185
12186         return names[output];
12187 }
12188
12189 static bool intel_crt_present(struct drm_device *dev)
12190 {
12191         struct drm_i915_private *dev_priv = dev->dev_private;
12192
12193         if (INTEL_INFO(dev)->gen >= 9)
12194                 return false;
12195
12196         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12197                 return false;
12198
12199         if (IS_CHERRYVIEW(dev))
12200                 return false;
12201
12202         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12203                 return false;
12204
12205         return true;
12206 }
12207
12208 static void intel_setup_outputs(struct drm_device *dev)
12209 {
12210         struct drm_i915_private *dev_priv = dev->dev_private;
12211         struct intel_encoder *encoder;
12212         bool dpd_is_edp = false;
12213
12214         intel_lvds_init(dev);
12215
12216         if (intel_crt_present(dev))
12217                 intel_crt_init(dev);
12218
12219         if (HAS_DDI(dev)) {
12220                 int found;
12221
12222                 /* Haswell uses DDI functions to detect digital outputs */
12223                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12224                 /* DDI A only supports eDP */
12225                 if (found)
12226                         intel_ddi_init(dev, PORT_A);
12227
12228                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12229                  * register */
12230                 found = I915_READ(SFUSE_STRAP);
12231
12232                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12233                         intel_ddi_init(dev, PORT_B);
12234                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12235                         intel_ddi_init(dev, PORT_C);
12236                 if (found & SFUSE_STRAP_DDID_DETECTED)
12237                         intel_ddi_init(dev, PORT_D);
12238         } else if (HAS_PCH_SPLIT(dev)) {
12239                 int found;
12240                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12241
12242                 if (has_edp_a(dev))
12243                         intel_dp_init(dev, DP_A, PORT_A);
12244
12245                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12246                         /* PCH SDVOB multiplex with HDMIB */
12247                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12248                         if (!found)
12249                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12250                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12251                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12252                 }
12253
12254                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12255                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12256
12257                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12258                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12259
12260                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12261                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12262
12263                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12264                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12265         } else if (IS_VALLEYVIEW(dev)) {
12266                 /*
12267                  * The DP_DETECTED bit is the latched state of the DDC
12268                  * SDA pin at boot. However since eDP doesn't require DDC
12269                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12270                  * eDP ports may have been muxed to an alternate function.
12271                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12272                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12273                  * detect eDP ports.
12274                  */
12275                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12276                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12277                                         PORT_B);
12278                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12279                     intel_dp_is_edp(dev, PORT_B))
12280                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12281
12282                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12283                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12284                                         PORT_C);
12285                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12286                     intel_dp_is_edp(dev, PORT_C))
12287                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12288
12289                 if (IS_CHERRYVIEW(dev)) {
12290                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12291                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12292                                                 PORT_D);
12293                         /* eDP not supported on port D, so don't check VBT */
12294                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12295                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12296                 }
12297
12298                 intel_dsi_init(dev);
12299         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12300                 bool found = false;
12301
12302                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12303                         DRM_DEBUG_KMS("probing SDVOB\n");
12304                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12305                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12306                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12307                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12308                         }
12309
12310                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12311                                 intel_dp_init(dev, DP_B, PORT_B);
12312                 }
12313
12314                 /* Before G4X SDVOC doesn't have its own detect register */
12315
12316                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12317                         DRM_DEBUG_KMS("probing SDVOC\n");
12318                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12319                 }
12320
12321                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12322
12323                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12324                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12325                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12326                         }
12327                         if (SUPPORTS_INTEGRATED_DP(dev))
12328                                 intel_dp_init(dev, DP_C, PORT_C);
12329                 }
12330
12331                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12332                     (I915_READ(DP_D) & DP_DETECTED))
12333                         intel_dp_init(dev, DP_D, PORT_D);
12334         } else if (IS_GEN2(dev))
12335                 intel_dvo_init(dev);
12336
12337         if (SUPPORTS_TV(dev))
12338                 intel_tv_init(dev);
12339
12340         intel_edp_psr_init(dev);
12341
12342         for_each_intel_encoder(dev, encoder) {
12343                 encoder->base.possible_crtcs = encoder->crtc_mask;
12344                 encoder->base.possible_clones =
12345                         intel_encoder_clones(encoder);
12346         }
12347
12348         intel_init_pch_refclk(dev);
12349
12350         drm_helper_move_panel_connectors_to_head(dev);
12351 }
12352
12353 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12354 {
12355         struct drm_device *dev = fb->dev;
12356         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12357
12358         drm_framebuffer_cleanup(fb);
12359         mutex_lock(&dev->struct_mutex);
12360         WARN_ON(!intel_fb->obj->framebuffer_references--);
12361         drm_gem_object_unreference(&intel_fb->obj->base);
12362         mutex_unlock(&dev->struct_mutex);
12363         kfree(intel_fb);
12364 }
12365
12366 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12367                                                 struct drm_file *file,
12368                                                 unsigned int *handle)
12369 {
12370         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12371         struct drm_i915_gem_object *obj = intel_fb->obj;
12372
12373         return drm_gem_handle_create(file, &obj->base, handle);
12374 }
12375
12376 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12377         .destroy = intel_user_framebuffer_destroy,
12378         .create_handle = intel_user_framebuffer_create_handle,
12379 };
12380
12381 static int intel_framebuffer_init(struct drm_device *dev,
12382                                   struct intel_framebuffer *intel_fb,
12383                                   struct drm_mode_fb_cmd2 *mode_cmd,
12384                                   struct drm_i915_gem_object *obj)
12385 {
12386         int aligned_height;
12387         int pitch_limit;
12388         int ret;
12389
12390         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12391
12392         if (obj->tiling_mode == I915_TILING_Y) {
12393                 DRM_DEBUG("hardware does not support tiling Y\n");
12394                 return -EINVAL;
12395         }
12396
12397         if (mode_cmd->pitches[0] & 63) {
12398                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12399                           mode_cmd->pitches[0]);
12400                 return -EINVAL;
12401         }
12402
12403         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12404                 pitch_limit = 32*1024;
12405         } else if (INTEL_INFO(dev)->gen >= 4) {
12406                 if (obj->tiling_mode)
12407                         pitch_limit = 16*1024;
12408                 else
12409                         pitch_limit = 32*1024;
12410         } else if (INTEL_INFO(dev)->gen >= 3) {
12411                 if (obj->tiling_mode)
12412                         pitch_limit = 8*1024;
12413                 else
12414                         pitch_limit = 16*1024;
12415         } else
12416                 /* XXX DSPC is limited to 4k tiled */
12417                 pitch_limit = 8*1024;
12418
12419         if (mode_cmd->pitches[0] > pitch_limit) {
12420                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12421                           obj->tiling_mode ? "tiled" : "linear",
12422                           mode_cmd->pitches[0], pitch_limit);
12423                 return -EINVAL;
12424         }
12425
12426         if (obj->tiling_mode != I915_TILING_NONE &&
12427             mode_cmd->pitches[0] != obj->stride) {
12428                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12429                           mode_cmd->pitches[0], obj->stride);
12430                 return -EINVAL;
12431         }
12432
12433         /* Reject formats not supported by any plane early. */
12434         switch (mode_cmd->pixel_format) {
12435         case DRM_FORMAT_C8:
12436         case DRM_FORMAT_RGB565:
12437         case DRM_FORMAT_XRGB8888:
12438         case DRM_FORMAT_ARGB8888:
12439                 break;
12440         case DRM_FORMAT_XRGB1555:
12441         case DRM_FORMAT_ARGB1555:
12442                 if (INTEL_INFO(dev)->gen > 3) {
12443                         DRM_DEBUG("unsupported pixel format: %s\n",
12444                                   drm_get_format_name(mode_cmd->pixel_format));
12445                         return -EINVAL;
12446                 }
12447                 break;
12448         case DRM_FORMAT_XBGR8888:
12449         case DRM_FORMAT_ABGR8888:
12450         case DRM_FORMAT_XRGB2101010:
12451         case DRM_FORMAT_ARGB2101010:
12452         case DRM_FORMAT_XBGR2101010:
12453         case DRM_FORMAT_ABGR2101010:
12454                 if (INTEL_INFO(dev)->gen < 4) {
12455                         DRM_DEBUG("unsupported pixel format: %s\n",
12456                                   drm_get_format_name(mode_cmd->pixel_format));
12457                         return -EINVAL;
12458                 }
12459                 break;
12460         case DRM_FORMAT_YUYV:
12461         case DRM_FORMAT_UYVY:
12462         case DRM_FORMAT_YVYU:
12463         case DRM_FORMAT_VYUY:
12464                 if (INTEL_INFO(dev)->gen < 5) {
12465                         DRM_DEBUG("unsupported pixel format: %s\n",
12466                                   drm_get_format_name(mode_cmd->pixel_format));
12467                         return -EINVAL;
12468                 }
12469                 break;
12470         default:
12471                 DRM_DEBUG("unsupported pixel format: %s\n",
12472                           drm_get_format_name(mode_cmd->pixel_format));
12473                 return -EINVAL;
12474         }
12475
12476         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12477         if (mode_cmd->offsets[0] != 0)
12478                 return -EINVAL;
12479
12480         aligned_height = intel_align_height(dev, mode_cmd->height,
12481                                             obj->tiling_mode);
12482         /* FIXME drm helper for size checks (especially planar formats)? */
12483         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12484                 return -EINVAL;
12485
12486         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12487         intel_fb->obj = obj;
12488         intel_fb->obj->framebuffer_references++;
12489
12490         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12491         if (ret) {
12492                 DRM_ERROR("framebuffer init failed %d\n", ret);
12493                 return ret;
12494         }
12495
12496         return 0;
12497 }
12498
12499 static struct drm_framebuffer *
12500 intel_user_framebuffer_create(struct drm_device *dev,
12501                               struct drm_file *filp,
12502                               struct drm_mode_fb_cmd2 *mode_cmd)
12503 {
12504         struct drm_i915_gem_object *obj;
12505
12506         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12507                                                 mode_cmd->handles[0]));
12508         if (&obj->base == NULL)
12509                 return ERR_PTR(-ENOENT);
12510
12511         return intel_framebuffer_create(dev, mode_cmd, obj);
12512 }
12513
12514 #ifndef CONFIG_DRM_I915_FBDEV
12515 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12516 {
12517 }
12518 #endif
12519
12520 static const struct drm_mode_config_funcs intel_mode_funcs = {
12521         .fb_create = intel_user_framebuffer_create,
12522         .output_poll_changed = intel_fbdev_output_poll_changed,
12523 };
12524
12525 /* Set up chip specific display functions */
12526 static void intel_init_display(struct drm_device *dev)
12527 {
12528         struct drm_i915_private *dev_priv = dev->dev_private;
12529
12530         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12531                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12532         else if (IS_CHERRYVIEW(dev))
12533                 dev_priv->display.find_dpll = chv_find_best_dpll;
12534         else if (IS_VALLEYVIEW(dev))
12535                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12536         else if (IS_PINEVIEW(dev))
12537                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12538         else
12539                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12540
12541         if (HAS_DDI(dev)) {
12542                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12543                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12544                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12545                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12546                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12547                 dev_priv->display.off = ironlake_crtc_off;
12548                 if (INTEL_INFO(dev)->gen >= 9)
12549                         dev_priv->display.update_primary_plane =
12550                                 skylake_update_primary_plane;
12551                 else
12552                         dev_priv->display.update_primary_plane =
12553                                 ironlake_update_primary_plane;
12554         } else if (HAS_PCH_SPLIT(dev)) {
12555                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12556                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12557                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12558                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12559                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12560                 dev_priv->display.off = ironlake_crtc_off;
12561                 dev_priv->display.update_primary_plane =
12562                         ironlake_update_primary_plane;
12563         } else if (IS_VALLEYVIEW(dev)) {
12564                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12565                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12566                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12567                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12568                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12569                 dev_priv->display.off = i9xx_crtc_off;
12570                 dev_priv->display.update_primary_plane =
12571                         i9xx_update_primary_plane;
12572         } else {
12573                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12574                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12575                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12576                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12577                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12578                 dev_priv->display.off = i9xx_crtc_off;
12579                 dev_priv->display.update_primary_plane =
12580                         i9xx_update_primary_plane;
12581         }
12582
12583         /* Returns the core display clock speed */
12584         if (IS_VALLEYVIEW(dev))
12585                 dev_priv->display.get_display_clock_speed =
12586                         valleyview_get_display_clock_speed;
12587         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12588                 dev_priv->display.get_display_clock_speed =
12589                         i945_get_display_clock_speed;
12590         else if (IS_I915G(dev))
12591                 dev_priv->display.get_display_clock_speed =
12592                         i915_get_display_clock_speed;
12593         else if (IS_I945GM(dev) || IS_845G(dev))
12594                 dev_priv->display.get_display_clock_speed =
12595                         i9xx_misc_get_display_clock_speed;
12596         else if (IS_PINEVIEW(dev))
12597                 dev_priv->display.get_display_clock_speed =
12598                         pnv_get_display_clock_speed;
12599         else if (IS_I915GM(dev))
12600                 dev_priv->display.get_display_clock_speed =
12601                         i915gm_get_display_clock_speed;
12602         else if (IS_I865G(dev))
12603                 dev_priv->display.get_display_clock_speed =
12604                         i865_get_display_clock_speed;
12605         else if (IS_I85X(dev))
12606                 dev_priv->display.get_display_clock_speed =
12607                         i855_get_display_clock_speed;
12608         else /* 852, 830 */
12609                 dev_priv->display.get_display_clock_speed =
12610                         i830_get_display_clock_speed;
12611
12612         if (IS_G4X(dev)) {
12613                 dev_priv->display.write_eld = g4x_write_eld;
12614         } else if (IS_GEN5(dev)) {
12615                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12616                 dev_priv->display.write_eld = ironlake_write_eld;
12617         } else if (IS_GEN6(dev)) {
12618                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12619                 dev_priv->display.write_eld = ironlake_write_eld;
12620                 dev_priv->display.modeset_global_resources =
12621                         snb_modeset_global_resources;
12622         } else if (IS_IVYBRIDGE(dev)) {
12623                 /* FIXME: detect B0+ stepping and use auto training */
12624                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12625                 dev_priv->display.write_eld = ironlake_write_eld;
12626                 dev_priv->display.modeset_global_resources =
12627                         ivb_modeset_global_resources;
12628         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12629                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12630                 dev_priv->display.write_eld = haswell_write_eld;
12631                 dev_priv->display.modeset_global_resources =
12632                         haswell_modeset_global_resources;
12633         } else if (IS_VALLEYVIEW(dev)) {
12634                 dev_priv->display.modeset_global_resources =
12635                         valleyview_modeset_global_resources;
12636                 dev_priv->display.write_eld = ironlake_write_eld;
12637         } else if (INTEL_INFO(dev)->gen >= 9) {
12638                 dev_priv->display.write_eld = haswell_write_eld;
12639                 dev_priv->display.modeset_global_resources =
12640                         haswell_modeset_global_resources;
12641         }
12642
12643         /* Default just returns -ENODEV to indicate unsupported */
12644         dev_priv->display.queue_flip = intel_default_queue_flip;
12645
12646         switch (INTEL_INFO(dev)->gen) {
12647         case 2:
12648                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12649                 break;
12650
12651         case 3:
12652                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12653                 break;
12654
12655         case 4:
12656         case 5:
12657                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12658                 break;
12659
12660         case 6:
12661                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12662                 break;
12663         case 7:
12664         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12665                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12666                 break;
12667         }
12668
12669         intel_panel_init_backlight_funcs(dev);
12670
12671         mutex_init(&dev_priv->pps_mutex);
12672 }
12673
12674 /*
12675  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12676  * resume, or other times.  This quirk makes sure that's the case for
12677  * affected systems.
12678  */
12679 static void quirk_pipea_force(struct drm_device *dev)
12680 {
12681         struct drm_i915_private *dev_priv = dev->dev_private;
12682
12683         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12684         DRM_INFO("applying pipe a force quirk\n");
12685 }
12686
12687 static void quirk_pipeb_force(struct drm_device *dev)
12688 {
12689         struct drm_i915_private *dev_priv = dev->dev_private;
12690
12691         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12692         DRM_INFO("applying pipe b force quirk\n");
12693 }
12694
12695 /*
12696  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12697  */
12698 static void quirk_ssc_force_disable(struct drm_device *dev)
12699 {
12700         struct drm_i915_private *dev_priv = dev->dev_private;
12701         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12702         DRM_INFO("applying lvds SSC disable quirk\n");
12703 }
12704
12705 /*
12706  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12707  * brightness value
12708  */
12709 static void quirk_invert_brightness(struct drm_device *dev)
12710 {
12711         struct drm_i915_private *dev_priv = dev->dev_private;
12712         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12713         DRM_INFO("applying inverted panel brightness quirk\n");
12714 }
12715
12716 /* Some VBT's incorrectly indicate no backlight is present */
12717 static void quirk_backlight_present(struct drm_device *dev)
12718 {
12719         struct drm_i915_private *dev_priv = dev->dev_private;
12720         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12721         DRM_INFO("applying backlight present quirk\n");
12722 }
12723
12724 struct intel_quirk {
12725         int device;
12726         int subsystem_vendor;
12727         int subsystem_device;
12728         void (*hook)(struct drm_device *dev);
12729 };
12730
12731 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12732 struct intel_dmi_quirk {
12733         void (*hook)(struct drm_device *dev);
12734         const struct dmi_system_id (*dmi_id_list)[];
12735 };
12736
12737 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12738 {
12739         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12740         return 1;
12741 }
12742
12743 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12744         {
12745                 .dmi_id_list = &(const struct dmi_system_id[]) {
12746                         {
12747                                 .callback = intel_dmi_reverse_brightness,
12748                                 .ident = "NCR Corporation",
12749                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12750                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12751                                 },
12752                         },
12753                         { }  /* terminating entry */
12754                 },
12755                 .hook = quirk_invert_brightness,
12756         },
12757 };
12758
12759 static struct intel_quirk intel_quirks[] = {
12760         /* HP Mini needs pipe A force quirk (LP: #322104) */
12761         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12762
12763         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12764         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12765
12766         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12767         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12768
12769         /* 830 needs to leave pipe A & dpll A up */
12770         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12771
12772         /* 830 needs to leave pipe B & dpll B up */
12773         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12774
12775         /* Lenovo U160 cannot use SSC on LVDS */
12776         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12777
12778         /* Sony Vaio Y cannot use SSC on LVDS */
12779         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12780
12781         /* Acer Aspire 5734Z must invert backlight brightness */
12782         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12783
12784         /* Acer/eMachines G725 */
12785         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12786
12787         /* Acer/eMachines e725 */
12788         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12789
12790         /* Acer/Packard Bell NCL20 */
12791         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12792
12793         /* Acer Aspire 4736Z */
12794         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12795
12796         /* Acer Aspire 5336 */
12797         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12798
12799         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12800         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12801
12802         /* Acer C720 Chromebook (Core i3 4005U) */
12803         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12804
12805         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12806         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12807
12808         /* HP Chromebook 14 (Celeron 2955U) */
12809         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12810 };
12811
12812 static void intel_init_quirks(struct drm_device *dev)
12813 {
12814         struct pci_dev *d = dev->pdev;
12815         int i;
12816
12817         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12818                 struct intel_quirk *q = &intel_quirks[i];
12819
12820                 if (d->device == q->device &&
12821                     (d->subsystem_vendor == q->subsystem_vendor ||
12822                      q->subsystem_vendor == PCI_ANY_ID) &&
12823                     (d->subsystem_device == q->subsystem_device ||
12824                      q->subsystem_device == PCI_ANY_ID))
12825                         q->hook(dev);
12826         }
12827         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12828                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12829                         intel_dmi_quirks[i].hook(dev);
12830         }
12831 }
12832
12833 /* Disable the VGA plane that we never use */
12834 static void i915_disable_vga(struct drm_device *dev)
12835 {
12836         struct drm_i915_private *dev_priv = dev->dev_private;
12837         u8 sr1;
12838         u32 vga_reg = i915_vgacntrl_reg(dev);
12839
12840         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12841         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12842         outb(SR01, VGA_SR_INDEX);
12843         sr1 = inb(VGA_SR_DATA);
12844         outb(sr1 | 1<<5, VGA_SR_DATA);
12845         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12846         udelay(300);
12847
12848         /*
12849          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12850          * from S3 without preserving (some of?) the other bits.
12851          */
12852         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12853         POSTING_READ(vga_reg);
12854 }
12855
12856 void intel_modeset_init_hw(struct drm_device *dev)
12857 {
12858         intel_prepare_ddi(dev);
12859
12860         if (IS_VALLEYVIEW(dev))
12861                 vlv_update_cdclk(dev);
12862
12863         intel_init_clock_gating(dev);
12864
12865         intel_enable_gt_powersave(dev);
12866 }
12867
12868 void intel_modeset_init(struct drm_device *dev)
12869 {
12870         struct drm_i915_private *dev_priv = dev->dev_private;
12871         int sprite, ret;
12872         enum pipe pipe;
12873         struct intel_crtc *crtc;
12874
12875         drm_mode_config_init(dev);
12876
12877         dev->mode_config.min_width = 0;
12878         dev->mode_config.min_height = 0;
12879
12880         dev->mode_config.preferred_depth = 24;
12881         dev->mode_config.prefer_shadow = 1;
12882
12883         dev->mode_config.funcs = &intel_mode_funcs;
12884
12885         intel_init_quirks(dev);
12886
12887         intel_init_pm(dev);
12888
12889         if (INTEL_INFO(dev)->num_pipes == 0)
12890                 return;
12891
12892         intel_init_display(dev);
12893
12894         if (IS_GEN2(dev)) {
12895                 dev->mode_config.max_width = 2048;
12896                 dev->mode_config.max_height = 2048;
12897         } else if (IS_GEN3(dev)) {
12898                 dev->mode_config.max_width = 4096;
12899                 dev->mode_config.max_height = 4096;
12900         } else {
12901                 dev->mode_config.max_width = 8192;
12902                 dev->mode_config.max_height = 8192;
12903         }
12904
12905         if (IS_845G(dev) || IS_I865G(dev)) {
12906                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12907                 dev->mode_config.cursor_height = 1023;
12908         } else if (IS_GEN2(dev)) {
12909                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12910                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12911         } else {
12912                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12913                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12914         }
12915
12916         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12917
12918         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12919                       INTEL_INFO(dev)->num_pipes,
12920                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12921
12922         for_each_pipe(dev_priv, pipe) {
12923                 intel_crtc_init(dev, pipe);
12924                 for_each_sprite(pipe, sprite) {
12925                         ret = intel_plane_init(dev, pipe, sprite);
12926                         if (ret)
12927                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12928                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12929                 }
12930         }
12931
12932         intel_init_dpio(dev);
12933
12934         intel_shared_dpll_init(dev);
12935
12936         /* save the BIOS value before clobbering it */
12937         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12938         /* Just disable it once at startup */
12939         i915_disable_vga(dev);
12940         intel_setup_outputs(dev);
12941
12942         /* Just in case the BIOS is doing something questionable. */
12943         intel_disable_fbc(dev);
12944
12945         drm_modeset_lock_all(dev);
12946         intel_modeset_setup_hw_state(dev, false);
12947         drm_modeset_unlock_all(dev);
12948
12949         for_each_intel_crtc(dev, crtc) {
12950                 if (!crtc->active)
12951                         continue;
12952
12953                 /*
12954                  * Note that reserving the BIOS fb up front prevents us
12955                  * from stuffing other stolen allocations like the ring
12956                  * on top.  This prevents some ugliness at boot time, and
12957                  * can even allow for smooth boot transitions if the BIOS
12958                  * fb is large enough for the active pipe configuration.
12959                  */
12960                 if (dev_priv->display.get_plane_config) {
12961                         dev_priv->display.get_plane_config(crtc,
12962                                                            &crtc->plane_config);
12963                         /*
12964                          * If the fb is shared between multiple heads, we'll
12965                          * just get the first one.
12966                          */
12967                         intel_find_plane_obj(crtc, &crtc->plane_config);
12968                 }
12969         }
12970 }
12971
12972 static void intel_enable_pipe_a(struct drm_device *dev)
12973 {
12974         struct intel_connector *connector;
12975         struct drm_connector *crt = NULL;
12976         struct intel_load_detect_pipe load_detect_temp;
12977         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12978
12979         /* We can't just switch on the pipe A, we need to set things up with a
12980          * proper mode and output configuration. As a gross hack, enable pipe A
12981          * by enabling the load detect pipe once. */
12982         list_for_each_entry(connector,
12983                             &dev->mode_config.connector_list,
12984                             base.head) {
12985                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12986                         crt = &connector->base;
12987                         break;
12988                 }
12989         }
12990
12991         if (!crt)
12992                 return;
12993
12994         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12995                 intel_release_load_detect_pipe(crt, &load_detect_temp);
12996 }
12997
12998 static bool
12999 intel_check_plane_mapping(struct intel_crtc *crtc)
13000 {
13001         struct drm_device *dev = crtc->base.dev;
13002         struct drm_i915_private *dev_priv = dev->dev_private;
13003         u32 reg, val;
13004
13005         if (INTEL_INFO(dev)->num_pipes == 1)
13006                 return true;
13007
13008         reg = DSPCNTR(!crtc->plane);
13009         val = I915_READ(reg);
13010
13011         if ((val & DISPLAY_PLANE_ENABLE) &&
13012             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13013                 return false;
13014
13015         return true;
13016 }
13017
13018 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13019 {
13020         struct drm_device *dev = crtc->base.dev;
13021         struct drm_i915_private *dev_priv = dev->dev_private;
13022         u32 reg;
13023
13024         /* Clear any frame start delays used for debugging left by the BIOS */
13025         reg = PIPECONF(crtc->config.cpu_transcoder);
13026         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13027
13028         /* restore vblank interrupts to correct state */
13029         if (crtc->active) {
13030                 update_scanline_offset(crtc);
13031                 drm_vblank_on(dev, crtc->pipe);
13032         } else
13033                 drm_vblank_off(dev, crtc->pipe);
13034
13035         /* We need to sanitize the plane -> pipe mapping first because this will
13036          * disable the crtc (and hence change the state) if it is wrong. Note
13037          * that gen4+ has a fixed plane -> pipe mapping.  */
13038         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13039                 struct intel_connector *connector;
13040                 bool plane;
13041
13042                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13043                               crtc->base.base.id);
13044
13045                 /* Pipe has the wrong plane attached and the plane is active.
13046                  * Temporarily change the plane mapping and disable everything
13047                  * ...  */
13048                 plane = crtc->plane;
13049                 crtc->plane = !plane;
13050                 crtc->primary_enabled = true;
13051                 dev_priv->display.crtc_disable(&crtc->base);
13052                 crtc->plane = plane;
13053
13054                 /* ... and break all links. */
13055                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13056                                     base.head) {
13057                         if (connector->encoder->base.crtc != &crtc->base)
13058                                 continue;
13059
13060                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13061                         connector->base.encoder = NULL;
13062                 }
13063                 /* multiple connectors may have the same encoder:
13064                  *  handle them and break crtc link separately */
13065                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13066                                     base.head)
13067                         if (connector->encoder->base.crtc == &crtc->base) {
13068                                 connector->encoder->base.crtc = NULL;
13069                                 connector->encoder->connectors_active = false;
13070                         }
13071
13072                 WARN_ON(crtc->active);
13073                 crtc->base.enabled = false;
13074         }
13075
13076         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13077             crtc->pipe == PIPE_A && !crtc->active) {
13078                 /* BIOS forgot to enable pipe A, this mostly happens after
13079                  * resume. Force-enable the pipe to fix this, the update_dpms
13080                  * call below we restore the pipe to the right state, but leave
13081                  * the required bits on. */
13082                 intel_enable_pipe_a(dev);
13083         }
13084
13085         /* Adjust the state of the output pipe according to whether we
13086          * have active connectors/encoders. */
13087         intel_crtc_update_dpms(&crtc->base);
13088
13089         if (crtc->active != crtc->base.enabled) {
13090                 struct intel_encoder *encoder;
13091
13092                 /* This can happen either due to bugs in the get_hw_state
13093                  * functions or because the pipe is force-enabled due to the
13094                  * pipe A quirk. */
13095                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13096                               crtc->base.base.id,
13097                               crtc->base.enabled ? "enabled" : "disabled",
13098                               crtc->active ? "enabled" : "disabled");
13099
13100                 crtc->base.enabled = crtc->active;
13101
13102                 /* Because we only establish the connector -> encoder ->
13103                  * crtc links if something is active, this means the
13104                  * crtc is now deactivated. Break the links. connector
13105                  * -> encoder links are only establish when things are
13106                  *  actually up, hence no need to break them. */
13107                 WARN_ON(crtc->active);
13108
13109                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13110                         WARN_ON(encoder->connectors_active);
13111                         encoder->base.crtc = NULL;
13112                 }
13113         }
13114
13115         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13116                 /*
13117                  * We start out with underrun reporting disabled to avoid races.
13118                  * For correct bookkeeping mark this on active crtcs.
13119                  *
13120                  * Also on gmch platforms we dont have any hardware bits to
13121                  * disable the underrun reporting. Which means we need to start
13122                  * out with underrun reporting disabled also on inactive pipes,
13123                  * since otherwise we'll complain about the garbage we read when
13124                  * e.g. coming up after runtime pm.
13125                  *
13126                  * No protection against concurrent access is required - at
13127                  * worst a fifo underrun happens which also sets this to false.
13128                  */
13129                 crtc->cpu_fifo_underrun_disabled = true;
13130                 crtc->pch_fifo_underrun_disabled = true;
13131         }
13132 }
13133
13134 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13135 {
13136         struct intel_connector *connector;
13137         struct drm_device *dev = encoder->base.dev;
13138
13139         /* We need to check both for a crtc link (meaning that the
13140          * encoder is active and trying to read from a pipe) and the
13141          * pipe itself being active. */
13142         bool has_active_crtc = encoder->base.crtc &&
13143                 to_intel_crtc(encoder->base.crtc)->active;
13144
13145         if (encoder->connectors_active && !has_active_crtc) {
13146                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13147                               encoder->base.base.id,
13148                               encoder->base.name);
13149
13150                 /* Connector is active, but has no active pipe. This is
13151                  * fallout from our resume register restoring. Disable
13152                  * the encoder manually again. */
13153                 if (encoder->base.crtc) {
13154                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13155                                       encoder->base.base.id,
13156                                       encoder->base.name);
13157                         encoder->disable(encoder);
13158                         if (encoder->post_disable)
13159                                 encoder->post_disable(encoder);
13160                 }
13161                 encoder->base.crtc = NULL;
13162                 encoder->connectors_active = false;
13163
13164                 /* Inconsistent output/port/pipe state happens presumably due to
13165                  * a bug in one of the get_hw_state functions. Or someplace else
13166                  * in our code, like the register restore mess on resume. Clamp
13167                  * things to off as a safer default. */
13168                 list_for_each_entry(connector,
13169                                     &dev->mode_config.connector_list,
13170                                     base.head) {
13171                         if (connector->encoder != encoder)
13172                                 continue;
13173                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13174                         connector->base.encoder = NULL;
13175                 }
13176         }
13177         /* Enabled encoders without active connectors will be fixed in
13178          * the crtc fixup. */
13179 }
13180
13181 void i915_redisable_vga_power_on(struct drm_device *dev)
13182 {
13183         struct drm_i915_private *dev_priv = dev->dev_private;
13184         u32 vga_reg = i915_vgacntrl_reg(dev);
13185
13186         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13187                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13188                 i915_disable_vga(dev);
13189         }
13190 }
13191
13192 void i915_redisable_vga(struct drm_device *dev)
13193 {
13194         struct drm_i915_private *dev_priv = dev->dev_private;
13195
13196         /* This function can be called both from intel_modeset_setup_hw_state or
13197          * at a very early point in our resume sequence, where the power well
13198          * structures are not yet restored. Since this function is at a very
13199          * paranoid "someone might have enabled VGA while we were not looking"
13200          * level, just check if the power well is enabled instead of trying to
13201          * follow the "don't touch the power well if we don't need it" policy
13202          * the rest of the driver uses. */
13203         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13204                 return;
13205
13206         i915_redisable_vga_power_on(dev);
13207 }
13208
13209 static bool primary_get_hw_state(struct intel_crtc *crtc)
13210 {
13211         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13212
13213         if (!crtc->active)
13214                 return false;
13215
13216         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13217 }
13218
13219 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13220 {
13221         struct drm_i915_private *dev_priv = dev->dev_private;
13222         enum pipe pipe;
13223         struct intel_crtc *crtc;
13224         struct intel_encoder *encoder;
13225         struct intel_connector *connector;
13226         int i;
13227
13228         for_each_intel_crtc(dev, crtc) {
13229                 memset(&crtc->config, 0, sizeof(crtc->config));
13230
13231                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13232
13233                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13234                                                                  &crtc->config);
13235
13236                 crtc->base.enabled = crtc->active;
13237                 crtc->primary_enabled = primary_get_hw_state(crtc);
13238
13239                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13240                               crtc->base.base.id,
13241                               crtc->active ? "enabled" : "disabled");
13242         }
13243
13244         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13245                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13246
13247                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13248                 pll->active = 0;
13249                 for_each_intel_crtc(dev, crtc) {
13250                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13251                                 pll->active++;
13252                 }
13253                 pll->refcount = pll->active;
13254
13255                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13256                               pll->name, pll->refcount, pll->on);
13257
13258                 if (pll->refcount)
13259                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13260         }
13261
13262         for_each_intel_encoder(dev, encoder) {
13263                 pipe = 0;
13264
13265                 if (encoder->get_hw_state(encoder, &pipe)) {
13266                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13267                         encoder->base.crtc = &crtc->base;
13268                         encoder->get_config(encoder, &crtc->config);
13269                 } else {
13270                         encoder->base.crtc = NULL;
13271                 }
13272
13273                 encoder->connectors_active = false;
13274                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13275                               encoder->base.base.id,
13276                               encoder->base.name,
13277                               encoder->base.crtc ? "enabled" : "disabled",
13278                               pipe_name(pipe));
13279         }
13280
13281         list_for_each_entry(connector, &dev->mode_config.connector_list,
13282                             base.head) {
13283                 if (connector->get_hw_state(connector)) {
13284                         connector->base.dpms = DRM_MODE_DPMS_ON;
13285                         connector->encoder->connectors_active = true;
13286                         connector->base.encoder = &connector->encoder->base;
13287                 } else {
13288                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13289                         connector->base.encoder = NULL;
13290                 }
13291                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13292                               connector->base.base.id,
13293                               connector->base.name,
13294                               connector->base.encoder ? "enabled" : "disabled");
13295         }
13296 }
13297
13298 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13299  * and i915 state tracking structures. */
13300 void intel_modeset_setup_hw_state(struct drm_device *dev,
13301                                   bool force_restore)
13302 {
13303         struct drm_i915_private *dev_priv = dev->dev_private;
13304         enum pipe pipe;
13305         struct intel_crtc *crtc;
13306         struct intel_encoder *encoder;
13307         int i;
13308
13309         intel_modeset_readout_hw_state(dev);
13310
13311         /*
13312          * Now that we have the config, copy it to each CRTC struct
13313          * Note that this could go away if we move to using crtc_config
13314          * checking everywhere.
13315          */
13316         for_each_intel_crtc(dev, crtc) {
13317                 if (crtc->active && i915.fastboot) {
13318                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13319                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13320                                       crtc->base.base.id);
13321                         drm_mode_debug_printmodeline(&crtc->base.mode);
13322                 }
13323         }
13324
13325         /* HW state is read out, now we need to sanitize this mess. */
13326         for_each_intel_encoder(dev, encoder) {
13327                 intel_sanitize_encoder(encoder);
13328         }
13329
13330         for_each_pipe(dev_priv, pipe) {
13331                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13332                 intel_sanitize_crtc(crtc);
13333                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13334         }
13335
13336         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13337                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13338
13339                 if (!pll->on || pll->active)
13340                         continue;
13341
13342                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13343
13344                 pll->disable(dev_priv, pll);
13345                 pll->on = false;
13346         }
13347
13348         if (HAS_PCH_SPLIT(dev))
13349                 ilk_wm_get_hw_state(dev);
13350
13351         if (force_restore) {
13352                 i915_redisable_vga(dev);
13353
13354                 /*
13355                  * We need to use raw interfaces for restoring state to avoid
13356                  * checking (bogus) intermediate states.
13357                  */
13358                 for_each_pipe(dev_priv, pipe) {
13359                         struct drm_crtc *crtc =
13360                                 dev_priv->pipe_to_crtc_mapping[pipe];
13361
13362                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13363                                          crtc->primary->fb);
13364                 }
13365         } else {
13366                 intel_modeset_update_staged_output_state(dev);
13367         }
13368
13369         intel_modeset_check_state(dev);
13370 }
13371
13372 void intel_modeset_gem_init(struct drm_device *dev)
13373 {
13374         struct drm_crtc *c;
13375         struct drm_i915_gem_object *obj;
13376
13377         mutex_lock(&dev->struct_mutex);
13378         intel_init_gt_powersave(dev);
13379         mutex_unlock(&dev->struct_mutex);
13380
13381         intel_modeset_init_hw(dev);
13382
13383         intel_setup_overlay(dev);
13384
13385         /*
13386          * Make sure any fbs we allocated at startup are properly
13387          * pinned & fenced.  When we do the allocation it's too early
13388          * for this.
13389          */
13390         mutex_lock(&dev->struct_mutex);
13391         for_each_crtc(dev, c) {
13392                 obj = intel_fb_obj(c->primary->fb);
13393                 if (obj == NULL)
13394                         continue;
13395
13396                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13397                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13398                                   to_intel_crtc(c)->pipe);
13399                         drm_framebuffer_unreference(c->primary->fb);
13400                         c->primary->fb = NULL;
13401                 }
13402         }
13403         mutex_unlock(&dev->struct_mutex);
13404 }
13405
13406 void intel_connector_unregister(struct intel_connector *intel_connector)
13407 {
13408         struct drm_connector *connector = &intel_connector->base;
13409
13410         intel_panel_destroy_backlight(connector);
13411         drm_connector_unregister(connector);
13412 }
13413
13414 void intel_modeset_cleanup(struct drm_device *dev)
13415 {
13416         struct drm_i915_private *dev_priv = dev->dev_private;
13417         struct drm_connector *connector;
13418
13419         /*
13420          * Interrupts and polling as the first thing to avoid creating havoc.
13421          * Too much stuff here (turning of rps, connectors, ...) would
13422          * experience fancy races otherwise.
13423          */
13424         intel_irq_uninstall(dev_priv);
13425
13426         /*
13427          * Due to the hpd irq storm handling the hotplug work can re-arm the
13428          * poll handlers. Hence disable polling after hpd handling is shut down.
13429          */
13430         drm_kms_helper_poll_fini(dev);
13431
13432         mutex_lock(&dev->struct_mutex);
13433
13434         intel_unregister_dsm_handler();
13435
13436         intel_disable_fbc(dev);
13437
13438         intel_disable_gt_powersave(dev);
13439
13440         ironlake_teardown_rc6(dev);
13441
13442         mutex_unlock(&dev->struct_mutex);
13443
13444         /* flush any delayed tasks or pending work */
13445         flush_scheduled_work();
13446
13447         /* destroy the backlight and sysfs files before encoders/connectors */
13448         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13449                 struct intel_connector *intel_connector;
13450
13451                 intel_connector = to_intel_connector(connector);
13452                 intel_connector->unregister(intel_connector);
13453         }
13454
13455         drm_mode_config_cleanup(dev);
13456
13457         intel_cleanup_overlay(dev);
13458
13459         mutex_lock(&dev->struct_mutex);
13460         intel_cleanup_gt_powersave(dev);
13461         mutex_unlock(&dev->struct_mutex);
13462 }
13463
13464 /*
13465  * Return which encoder is currently attached for connector.
13466  */
13467 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13468 {
13469         return &intel_attached_encoder(connector)->base;
13470 }
13471
13472 void intel_connector_attach_encoder(struct intel_connector *connector,
13473                                     struct intel_encoder *encoder)
13474 {
13475         connector->encoder = encoder;
13476         drm_mode_connector_attach_encoder(&connector->base,
13477                                           &encoder->base);
13478 }
13479
13480 /*
13481  * set vga decode state - true == enable VGA decode
13482  */
13483 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13484 {
13485         struct drm_i915_private *dev_priv = dev->dev_private;
13486         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13487         u16 gmch_ctrl;
13488
13489         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13490                 DRM_ERROR("failed to read control word\n");
13491                 return -EIO;
13492         }
13493
13494         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13495                 return 0;
13496
13497         if (state)
13498                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13499         else
13500                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13501
13502         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13503                 DRM_ERROR("failed to write control word\n");
13504                 return -EIO;
13505         }
13506
13507         return 0;
13508 }
13509
13510 struct intel_display_error_state {
13511
13512         u32 power_well_driver;
13513
13514         int num_transcoders;
13515
13516         struct intel_cursor_error_state {
13517                 u32 control;
13518                 u32 position;
13519                 u32 base;
13520                 u32 size;
13521         } cursor[I915_MAX_PIPES];
13522
13523         struct intel_pipe_error_state {
13524                 bool power_domain_on;
13525                 u32 source;
13526                 u32 stat;
13527         } pipe[I915_MAX_PIPES];
13528
13529         struct intel_plane_error_state {
13530                 u32 control;
13531                 u32 stride;
13532                 u32 size;
13533                 u32 pos;
13534                 u32 addr;
13535                 u32 surface;
13536                 u32 tile_offset;
13537         } plane[I915_MAX_PIPES];
13538
13539         struct intel_transcoder_error_state {
13540                 bool power_domain_on;
13541                 enum transcoder cpu_transcoder;
13542
13543                 u32 conf;
13544
13545                 u32 htotal;
13546                 u32 hblank;
13547                 u32 hsync;
13548                 u32 vtotal;
13549                 u32 vblank;
13550                 u32 vsync;
13551         } transcoder[4];
13552 };
13553
13554 struct intel_display_error_state *
13555 intel_display_capture_error_state(struct drm_device *dev)
13556 {
13557         struct drm_i915_private *dev_priv = dev->dev_private;
13558         struct intel_display_error_state *error;
13559         int transcoders[] = {
13560                 TRANSCODER_A,
13561                 TRANSCODER_B,
13562                 TRANSCODER_C,
13563                 TRANSCODER_EDP,
13564         };
13565         int i;
13566
13567         if (INTEL_INFO(dev)->num_pipes == 0)
13568                 return NULL;
13569
13570         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13571         if (error == NULL)
13572                 return NULL;
13573
13574         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13575                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13576
13577         for_each_pipe(dev_priv, i) {
13578                 error->pipe[i].power_domain_on =
13579                         __intel_display_power_is_enabled(dev_priv,
13580                                                          POWER_DOMAIN_PIPE(i));
13581                 if (!error->pipe[i].power_domain_on)
13582                         continue;
13583
13584                 error->cursor[i].control = I915_READ(CURCNTR(i));
13585                 error->cursor[i].position = I915_READ(CURPOS(i));
13586                 error->cursor[i].base = I915_READ(CURBASE(i));
13587
13588                 error->plane[i].control = I915_READ(DSPCNTR(i));
13589                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13590                 if (INTEL_INFO(dev)->gen <= 3) {
13591                         error->plane[i].size = I915_READ(DSPSIZE(i));
13592                         error->plane[i].pos = I915_READ(DSPPOS(i));
13593                 }
13594                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13595                         error->plane[i].addr = I915_READ(DSPADDR(i));
13596                 if (INTEL_INFO(dev)->gen >= 4) {
13597                         error->plane[i].surface = I915_READ(DSPSURF(i));
13598                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13599                 }
13600
13601                 error->pipe[i].source = I915_READ(PIPESRC(i));
13602
13603                 if (HAS_GMCH_DISPLAY(dev))
13604                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13605         }
13606
13607         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13608         if (HAS_DDI(dev_priv->dev))
13609                 error->num_transcoders++; /* Account for eDP. */
13610
13611         for (i = 0; i < error->num_transcoders; i++) {
13612                 enum transcoder cpu_transcoder = transcoders[i];
13613
13614                 error->transcoder[i].power_domain_on =
13615                         __intel_display_power_is_enabled(dev_priv,
13616                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13617                 if (!error->transcoder[i].power_domain_on)
13618                         continue;
13619
13620                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13621
13622                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13623                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13624                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13625                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13626                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13627                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13628                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13629         }
13630
13631         return error;
13632 }
13633
13634 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13635
13636 void
13637 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13638                                 struct drm_device *dev,
13639                                 struct intel_display_error_state *error)
13640 {
13641         struct drm_i915_private *dev_priv = dev->dev_private;
13642         int i;
13643
13644         if (!error)
13645                 return;
13646
13647         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13648         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13649                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13650                            error->power_well_driver);
13651         for_each_pipe(dev_priv, i) {
13652                 err_printf(m, "Pipe [%d]:\n", i);
13653                 err_printf(m, "  Power: %s\n",
13654                            error->pipe[i].power_domain_on ? "on" : "off");
13655                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13656                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13657
13658                 err_printf(m, "Plane [%d]:\n", i);
13659                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13660                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13661                 if (INTEL_INFO(dev)->gen <= 3) {
13662                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13663                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13664                 }
13665                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13666                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13667                 if (INTEL_INFO(dev)->gen >= 4) {
13668                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13669                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13670                 }
13671
13672                 err_printf(m, "Cursor [%d]:\n", i);
13673                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13674                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13675                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13676         }
13677
13678         for (i = 0; i < error->num_transcoders; i++) {
13679                 err_printf(m, "CPU transcoder: %c\n",
13680                            transcoder_name(error->transcoder[i].cpu_transcoder));
13681                 err_printf(m, "  Power: %s\n",
13682                            error->transcoder[i].power_domain_on ? "on" : "off");
13683                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13684                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13685                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13686                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13687                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13688                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13689                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13690         }
13691 }
13692
13693 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13694 {
13695         struct intel_crtc *crtc;
13696
13697         for_each_intel_crtc(dev, crtc) {
13698                 struct intel_unpin_work *work;
13699
13700                 spin_lock_irq(&dev->event_lock);
13701
13702                 work = crtc->unpin_work;
13703
13704                 if (work && work->event &&
13705                     work->event->base.file_priv == file) {
13706                         kfree(work->event);
13707                         work->event = NULL;
13708                 }
13709
13710                 spin_unlock_irq(&dev->event_lock);
13711         }
13712 }