drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *match_clock,
  87                     intel_clock_t *best_clock);
  88 static bool
  89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  90                         int target, int refclk, intel_clock_t *match_clock,
  91                         intel_clock_t *best_clock);
  92
  93 static bool
  94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                       int target, int refclk, intel_clock_t *match_clock,
  96                       intel_clock_t *best_clock);
  97 static bool
  98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  99                            int target, int refclk, intel_clock_t *match_clock,
 100                            intel_clock_t *best_clock);
 101
 102 static inline u32 /* units of 100MHz */
 103 intel_fdi_link_freq(struct drm_device *dev)
 104 {
 105         if (IS_GEN5(dev)) {
 106                 struct drm_i915_private *dev_priv = dev->dev_private;
 107                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 108         } else
 109                 return 27;
 110 }
 111
 112 static const intel_limit_t intel_limits_i8xx_dvo = {
 113         .dot = { .min = 25000, .max = 350000 },
 114         .vco = { .min = 930000, .max = 1400000 },
 115         .n = { .min = 3, .max = 16 },
 116         .m = { .min = 96, .max = 140 },
 117         .m1 = { .min = 18, .max = 26 },
 118         .m2 = { .min = 6, .max = 16 },
 119         .p = { .min = 4, .max = 128 },
 120         .p1 = { .min = 2, .max = 33 },
 121         .p2 = { .dot_limit = 165000,
 122                 .p2_slow = 4, .p2_fast = 2 },
 123         .find_pll = intel_find_best_PLL,
 124 };
 125
 126 static const intel_limit_t intel_limits_i8xx_lvds = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 1, .max = 6 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i9xx_sdvo = {
 141         .dot = { .min = 20000, .max = 400000 },
 142         .vco = { .min = 1400000, .max = 2800000 },
 143         .n = { .min = 1, .max = 6 },
 144         .m = { .min = 70, .max = 120 },
 145         .m1 = { .min = 10, .max = 22 },
 146         .m2 = { .min = 5, .max = 9 },
 147         .p = { .min = 5, .max = 80 },
 148         .p1 = { .min = 1, .max = 8 },
 149         .p2 = { .dot_limit = 200000,
 150                 .p2_slow = 10, .p2_fast = 5 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_lvds = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 7, .max = 98 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 112000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168
 169 static const intel_limit_t intel_limits_g4x_sdvo = {
 170         .dot = { .min = 25000, .max = 270000 },
 171         .vco = { .min = 1750000, .max = 3500000},
 172         .n = { .min = 1, .max = 4 },
 173         .m = { .min = 104, .max = 138 },
 174         .m1 = { .min = 17, .max = 23 },
 175         .m2 = { .min = 5, .max = 11 },
 176         .p = { .min = 10, .max = 30 },
 177         .p1 = { .min = 1, .max = 3},
 178         .p2 = { .dot_limit = 270000,
 179                 .p2_slow = 10,
 180                 .p2_fast = 10
 181         },
 182         .find_pll = intel_g4x_find_best_PLL,
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_hdmi = {
 186         .dot = { .min = 22000, .max = 400000 },
 187         .vco = { .min = 1750000, .max = 3500000},
 188         .n = { .min = 1, .max = 4 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 16, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 5, .max = 80 },
 193         .p1 = { .min = 1, .max = 8},
 194         .p2 = { .dot_limit = 165000,
 195                 .p2_slow = 10, .p2_fast = 5 },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 200         .dot = { .min = 20000, .max = 115000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 28, .max = 112 },
 207         .p1 = { .min = 2, .max = 8 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 14, .p2_fast = 14
 210         },
 211         .find_pll = intel_g4x_find_best_PLL,
 212 };
 213
 214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 215         .dot = { .min = 80000, .max = 224000 },
 216         .vco = { .min = 1750000, .max = 3500000 },
 217         .n = { .min = 1, .max = 3 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 14, .max = 42 },
 222         .p1 = { .min = 2, .max = 6 },
 223         .p2 = { .dot_limit = 0,
 224                 .p2_slow = 7, .p2_fast = 7
 225         },
 226         .find_pll = intel_g4x_find_best_PLL,
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_display_port = {
 230         .dot = { .min = 161670, .max = 227000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 2 },
 233         .m = { .min = 97, .max = 108 },
 234         .m1 = { .min = 0x10, .max = 0x12 },
 235         .m2 = { .min = 0x05, .max = 0x06 },
 236         .p = { .min = 10, .max = 20 },
 237         .p1 = { .min = 1, .max = 2},
 238         .p2 = { .dot_limit = 0,
 239                 .p2_slow = 10, .p2_fast = 10 },
 240         .find_pll = intel_find_pll_g4x_dp,
 241 };
 242
 243 static const intel_limit_t intel_limits_pineview_sdvo = {
 244         .dot = { .min = 20000, .max = 400000},
 245         .vco = { .min = 1700000, .max = 3500000 },
 246         /* Pineview's Ncounter is a ring counter */
 247         .n = { .min = 3, .max = 6 },
 248         .m = { .min = 2, .max = 256 },
 249         /* Pineview only has one combined m divider, which we treat as m2. */
 250         .m1 = { .min = 0, .max = 0 },
 251         .m2 = { .min = 0, .max = 254 },
 252         .p = { .min = 5, .max = 80 },
 253         .p1 = { .min = 1, .max = 8 },
 254         .p2 = { .dot_limit = 200000,
 255                 .p2_slow = 10, .p2_fast = 5 },
 256         .find_pll = intel_find_best_PLL,
 257 };
 258
 259 static const intel_limit_t intel_limits_pineview_lvds = {
 260         .dot = { .min = 20000, .max = 400000 },
 261         .vco = { .min = 1700000, .max = 3500000 },
 262         .n = { .min = 3, .max = 6 },
 263         .m = { .min = 2, .max = 256 },
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 7, .max = 112 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 112000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 /* Ironlake / Sandybridge
 274  *
 275  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 276  * the range value for them is (actual_value - 2).
 277  */
 278 static const intel_limit_t intel_limits_ironlake_dac = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 5 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 5, .max = 80 },
 286         .p1 = { .min = 1, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 10, .p2_fast = 5 },
 289         .find_pll = intel_g4x_find_best_PLL,
 290 };
 291
 292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 3 },
 296         .m = { .min = 79, .max = 118 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 14, .max = 56 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 7, .p2_fast = 7 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 /* LVDS 100mhz refclk limits. */
 321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 322         .dot = { .min = 25000, .max = 350000 },
 323         .vco = { .min = 1760000, .max = 3510000 },
 324         .n = { .min = 1, .max = 2 },
 325         .m = { .min = 79, .max = 126 },
 326         .m1 = { .min = 12, .max = 22 },
 327         .m2 = { .min = 5, .max = 9 },
 328         .p = { .min = 28, .max = 112 },
 329         .p1 = { .min = 2, .max = 8 },
 330         .p2 = { .dot_limit = 225000,
 331                 .p2_slow = 14, .p2_fast = 14 },
 332         .find_pll = intel_g4x_find_best_PLL,
 333 };
 334
 335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 3 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 14, .max = 42 },
 343         .p1 = { .min = 2, .max = 6 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 7, .p2_fast = 7 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_display_port = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000},
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 81, .max = 90 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 10, .max = 20 },
 357         .p1 = { .min = 1, .max = 2},
 358         .p2 = { .dot_limit = 0,
 359                 .p2_slow = 10, .p2_fast = 10 },
 360         .find_pll = intel_find_pll_ironlake_dp,
 361 };
 362
 363 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 364                               unsigned int reg)
 365 {
 366         unsigned int val;
 367
 368         /* use the module option value if specified */
 369         if (i915_lvds_channel_mode > 0)
 370                 return i915_lvds_channel_mode == 2;
 371
 372         if (dev_priv->lvds_val)
 373                 val = dev_priv->lvds_val;
 374         else {
 375                 /* BIOS should set the proper LVDS register value at boot, but
 376                  * in reality, it doesn't set the value when the lid is closed;
 377                  * we need to check "the value to be set" in VBT when LVDS
 378                  * register is uninitialized.
 379                  */
 380                 val = I915_READ(reg);
 381                 if (!(val & ~LVDS_DETECTED))
 382                         val = dev_priv->bios_lvds_val;
 383                 dev_priv->lvds_val = val;
 384         }
 385         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 386 }
 387
 388 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 389                                                 int refclk)
 390 {
 391         struct drm_device *dev = crtc->dev;
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         const intel_limit_t *limit;
 394
 395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 396                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 397                         /* LVDS dual channel */
 398                         if (refclk == 100000)
 399                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 400                         else
 401                                 limit = &intel_limits_ironlake_dual_lvds;
 402                 } else {
 403                         if (refclk == 100000)
 404                                 limit = &intel_limits_ironlake_single_lvds_100m;
 405                         else
 406                                 limit = &intel_limits_ironlake_single_lvds;
 407                 }
 408         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 409                         HAS_eDP)
 410                 limit = &intel_limits_ironlake_display_port;
 411         else
 412                 limit = &intel_limits_ironlake_dac;
 413
 414         return limit;
 415 }
 416
 417 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 418 {
 419         struct drm_device *dev = crtc->dev;
 420         struct drm_i915_private *dev_priv = dev->dev_private;
 421         const intel_limit_t *limit;
 422
 423         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 424                 if (is_dual_link_lvds(dev_priv, LVDS))
 425                         /* LVDS with dual channel */
 426                         limit = &intel_limits_g4x_dual_channel_lvds;
 427                 else
 428                         /* LVDS with dual channel */
 429                         limit = &intel_limits_g4x_single_channel_lvds;
 430         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 431                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 432                 limit = &intel_limits_g4x_hdmi;
 433         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 434                 limit = &intel_limits_g4x_sdvo;
 435         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 436                 limit = &intel_limits_g4x_display_port;
 437         } else /* The option is for other outputs */
 438                 limit = &intel_limits_i9xx_sdvo;
 439
 440         return limit;
 441 }
 442
 443 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 444 {
 445         struct drm_device *dev = crtc->dev;
 446         const intel_limit_t *limit;
 447
 448         if (HAS_PCH_SPLIT(dev))
 449                 limit = intel_ironlake_limit(crtc, refclk);
 450         else if (IS_G4X(dev)) {
 451                 limit = intel_g4x_limit(crtc);
 452         } else if (IS_PINEVIEW(dev)) {
 453                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 454                         limit = &intel_limits_pineview_lvds;
 455                 else
 456                         limit = &intel_limits_pineview_sdvo;
 457         } else if (!IS_GEN2(dev)) {
 458                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 459                         limit = &intel_limits_i9xx_lvds;
 460                 else
 461                         limit = &intel_limits_i9xx_sdvo;
 462         } else {
 463                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 464                         limit = &intel_limits_i8xx_lvds;
 465                 else
 466                         limit = &intel_limits_i8xx_dvo;
 467         }
 468         return limit;
 469 }
 470
 471 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 472 static void pineview_clock(int refclk, intel_clock_t *clock)
 473 {
 474         clock->m = clock->m2 + 2;
 475         clock->p = clock->p1 * clock->p2;
 476         clock->vco = refclk * clock->m / clock->n;
 477         clock->dot = clock->vco / clock->p;
 478 }
 479
 480 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 481 {
 482         if (IS_PINEVIEW(dev)) {
 483                 pineview_clock(refclk, clock);
 484                 return;
 485         }
 486         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 487         clock->p = clock->p1 * clock->p2;
 488         clock->vco = refclk * clock->m / (clock->n + 2);
 489         clock->dot = clock->vco / clock->p;
 490 }
 491
 492 /**
 493  * Returns whether any output on the specified pipe is of the specified type
 494  */
 495 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 496 {
 497         struct drm_device *dev = crtc->dev;
 498         struct drm_mode_config *mode_config = &dev->mode_config;
 499         struct intel_encoder *encoder;
 500
 501         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 502                 if (encoder->base.crtc == crtc && encoder->type == type)
 503                         return true;
 504
 505         return false;
 506 }
 507
 508 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 509 /**
 510  * Returns whether the given set of divisors are valid for a given refclk with
 511  * the given connectors.
 512  */
 513
 514 static bool intel_PLL_is_valid(struct drm_device *dev,
 515                                const intel_limit_t *limit,
 516                                const intel_clock_t *clock)
 517 {
 518         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 519                 INTELPllInvalid("p1 out of range\n");
 520         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 521                 INTELPllInvalid("p out of range\n");
 522         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 523                 INTELPllInvalid("m2 out of range\n");
 524         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 525                 INTELPllInvalid("m1 out of range\n");
 526         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 527                 INTELPllInvalid("m1 <= m2\n");
 528         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 529                 INTELPllInvalid("m out of range\n");
 530         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 531                 INTELPllInvalid("n out of range\n");
 532         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 533                 INTELPllInvalid("vco out of range\n");
 534         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 535          * connector, etc., rather than just a single range.
 536          */
 537         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 538                 INTELPllInvalid("dot out of range\n");
 539
 540         return true;
 541 }
 542
 543 static bool
 544 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 545                     int target, int refclk, intel_clock_t *match_clock,
 546                     intel_clock_t *best_clock)
 547
 548 {
 549         struct drm_device *dev = crtc->dev;
 550         struct drm_i915_private *dev_priv = dev->dev_private;
 551         intel_clock_t clock;
 552         int err = target;
 553
 554         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 555             (I915_READ(LVDS)) != 0) {
 556                 /*
 557                  * For LVDS, if the panel is on, just rely on its current
 558                  * settings for dual-channel.  We haven't figured out how to
 559                  * reliably set up different single/dual channel state, if we
 560                  * even can.
 561                  */
 562                 if (is_dual_link_lvds(dev_priv, LVDS))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         /* m1 is always 0 in Pineview */
 580                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 581                                 break;
 582                         for (clock.n = limit->n.min;
 583                              clock.n <= limit->n.max; clock.n++) {
 584                                 for (clock.p1 = limit->p1.min;
 585                                         clock.p1 <= limit->p1.max; clock.p1++) {
 586                                         int this_err;
 587
 588                                         intel_clock(dev, refclk, &clock);
 589                                         if (!intel_PLL_is_valid(dev, limit,
 590                                                                 &clock))
 591                                                 continue;
 592                                         if (match_clock &&
 593                                             clock.p != match_clock->p)
 594                                                 continue;
 595
 596                                         this_err = abs(clock.dot - target);
 597                                         if (this_err < err) {
 598                                                 *best_clock = clock;
 599                                                 err = this_err;
 600                                         }
 601                                 }
 602                         }
 603                 }
 604         }
 605
 606         return (err != target);
 607 }
 608
 609 static bool
 610 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 611                         int target, int refclk, intel_clock_t *match_clock,
 612                         intel_clock_t *best_clock)
 613 {
 614         struct drm_device *dev = crtc->dev;
 615         struct drm_i915_private *dev_priv = dev->dev_private;
 616         intel_clock_t clock;
 617         int max_n;
 618         bool found;
 619         /* approximately equals target * 0.00585 */
 620         int err_most = (target >> 8) + (target >> 9);
 621         found = false;
 622
 623         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 624                 int lvds_reg;
 625
 626                 if (HAS_PCH_SPLIT(dev))
 627                         lvds_reg = PCH_LVDS;
 628                 else
 629                         lvds_reg = LVDS;
 630                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 631                     LVDS_CLKB_POWER_UP)
 632                         clock.p2 = limit->p2.p2_fast;
 633                 else
 634                         clock.p2 = limit->p2.p2_slow;
 635         } else {
 636                 if (target < limit->p2.dot_limit)
 637                         clock.p2 = limit->p2.p2_slow;
 638                 else
 639                         clock.p2 = limit->p2.p2_fast;
 640         }
 641
 642         memset(best_clock, 0, sizeof(*best_clock));
 643         max_n = limit->n.max;
 644         /* based on hardware requirement, prefer smaller n to precision */
 645         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 646                 /* based on hardware requirement, prefere larger m1,m2 */
 647                 for (clock.m1 = limit->m1.max;
 648                      clock.m1 >= limit->m1.min; clock.m1--) {
 649                         for (clock.m2 = limit->m2.max;
 650                              clock.m2 >= limit->m2.min; clock.m2--) {
 651                                 for (clock.p1 = limit->p1.max;
 652                                      clock.p1 >= limit->p1.min; clock.p1--) {
 653                                         int this_err;
 654
 655                                         intel_clock(dev, refclk, &clock);
 656                                         if (!intel_PLL_is_valid(dev, limit,
 657                                                                 &clock))
 658                                                 continue;
 659                                         if (match_clock &&
 660                                             clock.p != match_clock->p)
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err_most) {
 665                                                 *best_clock = clock;
 666                                                 err_most = this_err;
 667                                                 max_n = clock.n;
 668                                                 found = true;
 669                                         }
 670                                 }
 671                         }
 672                 }
 673         }
 674         return found;
 675 }
 676
 677 static bool
 678 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                            int target, int refclk, intel_clock_t *match_clock,
 680                            intel_clock_t *best_clock)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         intel_clock_t clock;
 684
 685         if (target < 200000) {
 686                 clock.n = 1;
 687                 clock.p1 = 2;
 688                 clock.p2 = 10;
 689                 clock.m1 = 12;
 690                 clock.m2 = 9;
 691         } else {
 692                 clock.n = 2;
 693                 clock.p1 = 1;
 694                 clock.p2 = 10;
 695                 clock.m1 = 14;
 696                 clock.m2 = 8;
 697         }
 698         intel_clock(dev, refclk, &clock);
 699         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 700         return true;
 701 }
 702
 703 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 704 static bool
 705 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 706                       int target, int refclk, intel_clock_t *match_clock,
 707                       intel_clock_t *best_clock)
 708 {
 709         intel_clock_t clock;
 710         if (target < 200000) {
 711                 clock.p1 = 2;
 712                 clock.p2 = 10;
 713                 clock.n = 2;
 714                 clock.m1 = 23;
 715                 clock.m2 = 8;
 716         } else {
 717                 clock.p1 = 1;
 718                 clock.p2 = 10;
 719                 clock.n = 1;
 720                 clock.m1 = 14;
 721                 clock.m2 = 2;
 722         }
 723         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 724         clock.p = (clock.p1 * clock.p2);
 725         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 726         clock.vco = 0;
 727         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 728         return true;
 729 }
 730
 731 /**
 732  * intel_wait_for_vblank - wait for vblank on a given pipe
 733  * @dev: drm device
 734  * @pipe: pipe to wait for
 735  *
 736  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 737  * mode setting code.
 738  */
 739 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 740 {
 741         struct drm_i915_private *dev_priv = dev->dev_private;
 742         int pipestat_reg = PIPESTAT(pipe);
 743
 744         /* Clear existing vblank status. Note this will clear any other
 745          * sticky status fields as well.
 746          *
 747          * This races with i915_driver_irq_handler() with the result
 748          * that either function could miss a vblank event.  Here it is not
 749          * fatal, as we will either wait upon the next vblank interrupt or
 750          * timeout.  Generally speaking intel_wait_for_vblank() is only
 751          * called during modeset at which time the GPU should be idle and
 752          * should *not* be performing page flips and thus not waiting on
 753          * vblanks...
 754          * Currently, the result of us stealing a vblank from the irq
 755          * handler is that a single frame will be skipped during swapbuffers.
 756          */
 757         I915_WRITE(pipestat_reg,
 758                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 759
 760         /* Wait for vblank interrupt bit to set */
 761         if (wait_for(I915_READ(pipestat_reg) &
 762                      PIPE_VBLANK_INTERRUPT_STATUS,
 763                      50))
 764                 DRM_DEBUG_KMS("vblank wait timed out\n");
 765 }
 766
 767 /*
 768  * intel_wait_for_pipe_off - wait for pipe to turn off
 769  * @dev: drm device
 770  * @pipe: pipe to wait for
 771  *
 772  * After disabling a pipe, we can't wait for vblank in the usual way,
 773  * spinning on the vblank interrupt status bit, since we won't actually
 774  * see an interrupt when the pipe is disabled.
 775  *
 776  * On Gen4 and above:
 777  *   wait for the pipe register state bit to turn off
 778  *
 779  * Otherwise:
 780  *   wait for the display line value to settle (it usually
 781  *   ends up stopping at the start of the next frame).
 782  *
 783  */
 784 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 785 {
 786         struct drm_i915_private *dev_priv = dev->dev_private;
 787
 788         if (INTEL_INFO(dev)->gen >= 4) {
 789                 int reg = PIPECONF(pipe);
 790
 791                 /* Wait for the Pipe State to go off */
 792                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 793                              100))
 794                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 795         } else {
 796                 u32 last_line;
 797                 int reg = PIPEDSL(pipe);
 798                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 799
 800                 /* Wait for the display line to settle */
 801                 do {
 802                         last_line = I915_READ(reg) & DSL_LINEMASK;
 803                         mdelay(5);
 804                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 805                          time_after(timeout, jiffies));
 806                 if (time_after(jiffies, timeout))
 807                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 808         }
 809 }
 810
 811 static const char *state_string(bool enabled)
 812 {
 813         return enabled ? "on" : "off";
 814 }
 815
 816 /* Only for pre-ILK configs */
 817 static void assert_pll(struct drm_i915_private *dev_priv,
 818                        enum pipe pipe, bool state)
 819 {
 820         int reg;
 821         u32 val;
 822         bool cur_state;
 823
 824         reg = DPLL(pipe);
 825         val = I915_READ(reg);
 826         cur_state = !!(val & DPLL_VCO_ENABLE);
 827         WARN(cur_state != state,
 828              "PLL state assertion failure (expected %s, current %s)\n",
 829              state_string(state), state_string(cur_state));
 830 }
 831 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 832 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 833
 834 /* For ILK+ */
 835 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 836                            enum pipe pipe, bool state)
 837 {
 838         int reg;
 839         u32 val;
 840         bool cur_state;
 841
 842         if (HAS_PCH_CPT(dev_priv->dev)) {
 843                 u32 pch_dpll;
 844
 845                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 846
 847                 /* Make sure the selected PLL is enabled to the transcoder */
 848                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 849                      "transcoder %d PLL not enabled\n", pipe);
 850
 851                 /* Convert the transcoder pipe number to a pll pipe number */
 852                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 853         }
 854
 855         reg = PCH_DPLL(pipe);
 856         val = I915_READ(reg);
 857         cur_state = !!(val & DPLL_VCO_ENABLE);
 858         WARN(cur_state != state,
 859              "PCH PLL state assertion failure (expected %s, current %s)\n",
 860              state_string(state), state_string(cur_state));
 861 }
 862 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 863 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 864
 865 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 866                           enum pipe pipe, bool state)
 867 {
 868         int reg;
 869         u32 val;
 870         bool cur_state;
 871
 872         reg = FDI_TX_CTL(pipe);
 873         val = I915_READ(reg);
 874         cur_state = !!(val & FDI_TX_ENABLE);
 875         WARN(cur_state != state,
 876              "FDI TX state assertion failure (expected %s, current %s)\n",
 877              state_string(state), state_string(cur_state));
 878 }
 879 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 880 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 881
 882 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 883                           enum pipe pipe, bool state)
 884 {
 885         int reg;
 886         u32 val;
 887         bool cur_state;
 888
 889         reg = FDI_RX_CTL(pipe);
 890         val = I915_READ(reg);
 891         cur_state = !!(val & FDI_RX_ENABLE);
 892         WARN(cur_state != state,
 893              "FDI RX state assertion failure (expected %s, current %s)\n",
 894              state_string(state), state_string(cur_state));
 895 }
 896 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 897 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 898
 899 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 900                                       enum pipe pipe)
 901 {
 902         int reg;
 903         u32 val;
 904
 905         /* ILK FDI PLL is always enabled */
 906         if (dev_priv->info->gen == 5)
 907                 return;
 908
 909         reg = FDI_TX_CTL(pipe);
 910         val = I915_READ(reg);
 911         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 912 }
 913
 914 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 915                                       enum pipe pipe)
 916 {
 917         int reg;
 918         u32 val;
 919
 920         reg = FDI_RX_CTL(pipe);
 921         val = I915_READ(reg);
 922         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 923 }
 924
 925 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 926                                   enum pipe pipe)
 927 {
 928         int pp_reg, lvds_reg;
 929         u32 val;
 930         enum pipe panel_pipe = PIPE_A;
 931         bool locked = true;
 932
 933         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 934                 pp_reg = PCH_PP_CONTROL;
 935                 lvds_reg = PCH_LVDS;
 936         } else {
 937                 pp_reg = PP_CONTROL;
 938                 lvds_reg = LVDS;
 939         }
 940
 941         val = I915_READ(pp_reg);
 942         if (!(val & PANEL_POWER_ON) ||
 943             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 944                 locked = false;
 945
 946         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 947                 panel_pipe = PIPE_B;
 948
 949         WARN(panel_pipe == pipe && locked,
 950              "panel assertion failure, pipe %c regs locked\n",
 951              pipe_name(pipe));
 952 }
 953
 954 void assert_pipe(struct drm_i915_private *dev_priv,
 955                  enum pipe pipe, bool state)
 956 {
 957         int reg;
 958         u32 val;
 959         bool cur_state;
 960
 961         /* if we need the pipe A quirk it must be always on */
 962         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
 963                 state = true;
 964
 965         reg = PIPECONF(pipe);
 966         val = I915_READ(reg);
 967         cur_state = !!(val & PIPECONF_ENABLE);
 968         WARN(cur_state != state,
 969              "pipe %c assertion failure (expected %s, current %s)\n",
 970              pipe_name(pipe), state_string(state), state_string(cur_state));
 971 }
 972
 973 static void assert_plane(struct drm_i915_private *dev_priv,
 974                          enum plane plane, bool state)
 975 {
 976         int reg;
 977         u32 val;
 978         bool cur_state;
 979
 980         reg = DSPCNTR(plane);
 981         val = I915_READ(reg);
 982         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
 983         WARN(cur_state != state,
 984              "plane %c assertion failure (expected %s, current %s)\n",
 985              plane_name(plane), state_string(state), state_string(cur_state));
 986 }
 987
 988 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
 989 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
 990
 991 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 992                                    enum pipe pipe)
 993 {
 994         int reg, i;
 995         u32 val;
 996         int cur_pipe;
 997
 998         /* Planes are fixed to pipes on ILK+ */
 999         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1000                 reg = DSPCNTR(pipe);
1001                 val = I915_READ(reg);
1002                 WARN((val & DISPLAY_PLANE_ENABLE),
1003                      "plane %c assertion failure, should be disabled but not\n",
1004                      plane_name(pipe));
1005                 return;
1006         }
1007
1008         /* Need to check both planes against the pipe */
1009         for (i = 0; i < 2; i++) {
1010                 reg = DSPCNTR(i);
1011                 val = I915_READ(reg);
1012                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1013                         DISPPLANE_SEL_PIPE_SHIFT;
1014                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1015                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1016                      plane_name(i), pipe_name(pipe));
1017         }
1018 }
1019
1020 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1021 {
1022         u32 val;
1023         bool enabled;
1024
1025         val = I915_READ(PCH_DREF_CONTROL);
1026         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1027                             DREF_SUPERSPREAD_SOURCE_MASK));
1028         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1029 }
1030
1031 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1032                                        enum pipe pipe)
1033 {
1034         int reg;
1035         u32 val;
1036         bool enabled;
1037
1038         reg = TRANSCONF(pipe);
1039         val = I915_READ(reg);
1040         enabled = !!(val & TRANS_ENABLE);
1041         WARN(enabled,
1042              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1043              pipe_name(pipe));
1044 }
1045
1046 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1047                             enum pipe pipe, u32 port_sel, u32 val)
1048 {
1049         if ((val & DP_PORT_EN) == 0)
1050                 return false;
1051
1052         if (HAS_PCH_CPT(dev_priv->dev)) {
1053                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1054                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1055                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1056                         return false;
1057         } else {
1058                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1059                         return false;
1060         }
1061         return true;
1062 }
1063
1064 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1065                               enum pipe pipe, u32 val)
1066 {
1067         if ((val & PORT_ENABLE) == 0)
1068                 return false;
1069
1070         if (HAS_PCH_CPT(dev_priv->dev)) {
1071                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1072                         return false;
1073         } else {
1074                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1075                         return false;
1076         }
1077         return true;
1078 }
1079
1080 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1081                               enum pipe pipe, u32 val)
1082 {
1083         if ((val & LVDS_PORT_EN) == 0)
1084                 return false;
1085
1086         if (HAS_PCH_CPT(dev_priv->dev)) {
1087                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1088                         return false;
1089         } else {
1090                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1091                         return false;
1092         }
1093         return true;
1094 }
1095
1096 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1097                               enum pipe pipe, u32 val)
1098 {
1099         if ((val & ADPA_DAC_ENABLE) == 0)
1100                 return false;
1101         if (HAS_PCH_CPT(dev_priv->dev)) {
1102                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1103                         return false;
1104         } else {
1105                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1106                         return false;
1107         }
1108         return true;
1109 }
1110
1111 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1112                                    enum pipe pipe, int reg, u32 port_sel)
1113 {
1114         u32 val = I915_READ(reg);
1115         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1116              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1117              reg, pipe_name(pipe));
1118 }
1119
1120 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1121                                      enum pipe pipe, int reg)
1122 {
1123         u32 val = I915_READ(reg);
1124         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1125              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1126              reg, pipe_name(pipe));
1127 }
1128
1129 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1130                                       enum pipe pipe)
1131 {
1132         int reg;
1133         u32 val;
1134
1135         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1136         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1137         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1138
1139         reg = PCH_ADPA;
1140         val = I915_READ(reg);
1141         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1142              "PCH VGA enabled on transcoder %c, should be disabled\n",
1143              pipe_name(pipe));
1144
1145         reg = PCH_LVDS;
1146         val = I915_READ(reg);
1147         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1148              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1149              pipe_name(pipe));
1150
1151         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1152         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1153         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1154 }
1155
1156 /**
1157  * intel_enable_pll - enable a PLL
1158  * @dev_priv: i915 private structure
1159  * @pipe: pipe PLL to enable
1160  *
1161  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1162  * make sure the PLL reg is writable first though, since the panel write
1163  * protect mechanism may be enabled.
1164  *
1165  * Note!  This is for pre-ILK only.
1166  */
1167 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1168 {
1169         int reg;
1170         u32 val;
1171
1172         /* No really, not for ILK+ */
1173         BUG_ON(dev_priv->info->gen >= 5);
1174
1175         /* PLL is protected by panel, make sure we can write it */
1176         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1177                 assert_panel_unlocked(dev_priv, pipe);
1178
1179         reg = DPLL(pipe);
1180         val = I915_READ(reg);
1181         val |= DPLL_VCO_ENABLE;
1182
1183         /* We do this three times for luck */
1184         I915_WRITE(reg, val);
1185         POSTING_READ(reg);
1186         udelay(150); /* wait for warmup */
1187         I915_WRITE(reg, val);
1188         POSTING_READ(reg);
1189         udelay(150); /* wait for warmup */
1190         I915_WRITE(reg, val);
1191         POSTING_READ(reg);
1192         udelay(150); /* wait for warmup */
1193 }
1194
1195 /**
1196  * intel_disable_pll - disable a PLL
1197  * @dev_priv: i915 private structure
1198  * @pipe: pipe PLL to disable
1199  *
1200  * Disable the PLL for @pipe, making sure the pipe is off first.
1201  *
1202  * Note!  This is for pre-ILK only.
1203  */
1204 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1205 {
1206         int reg;
1207         u32 val;
1208
1209         /* Don't disable pipe A or pipe A PLLs if needed */
1210         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1211                 return;
1212
1213         /* Make sure the pipe isn't still relying on us */
1214         assert_pipe_disabled(dev_priv, pipe);
1215
1216         reg = DPLL(pipe);
1217         val = I915_READ(reg);
1218         val &= ~DPLL_VCO_ENABLE;
1219         I915_WRITE(reg, val);
1220         POSTING_READ(reg);
1221 }
1222
1223 /**
1224  * intel_enable_pch_pll - enable PCH PLL
1225  * @dev_priv: i915 private structure
1226  * @pipe: pipe PLL to enable
1227  *
1228  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1229  * drives the transcoder clock.
1230  */
1231 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1232                                  enum pipe pipe)
1233 {
1234         int reg;
1235         u32 val;
1236
1237         if (pipe > 1)
1238                 return;
1239
1240         /* PCH only available on ILK+ */
1241         BUG_ON(dev_priv->info->gen < 5);
1242
1243         /* PCH refclock must be enabled first */
1244         assert_pch_refclk_enabled(dev_priv);
1245
1246         reg = PCH_DPLL(pipe);
1247         val = I915_READ(reg);
1248         val |= DPLL_VCO_ENABLE;
1249         I915_WRITE(reg, val);
1250         POSTING_READ(reg);
1251         udelay(200);
1252 }
1253
1254 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1255                                   enum pipe pipe)
1256 {
1257         int reg;
1258         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1259                 pll_sel = TRANSC_DPLL_ENABLE;
1260
1261         if (pipe > 1)
1262                 return;
1263
1264         /* PCH only available on ILK+ */
1265         BUG_ON(dev_priv->info->gen < 5);
1266
1267         /* Make sure transcoder isn't still depending on us */
1268         assert_transcoder_disabled(dev_priv, pipe);
1269
1270         if (pipe == 0)
1271                 pll_sel |= TRANSC_DPLLA_SEL;
1272         else if (pipe == 1)
1273                 pll_sel |= TRANSC_DPLLB_SEL;
1274
1275
1276         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1277                 return;
1278
1279         reg = PCH_DPLL(pipe);
1280         val = I915_READ(reg);
1281         val &= ~DPLL_VCO_ENABLE;
1282         I915_WRITE(reg, val);
1283         POSTING_READ(reg);
1284         udelay(200);
1285 }
1286
1287 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1288                                     enum pipe pipe)
1289 {
1290         int reg;
1291         u32 val, pipeconf_val;
1292         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1293
1294         /* PCH only available on ILK+ */
1295         BUG_ON(dev_priv->info->gen < 5);
1296
1297         /* Make sure PCH DPLL is enabled */
1298         assert_pch_pll_enabled(dev_priv, pipe);
1299
1300         /* FDI must be feeding us bits for PCH ports */
1301         assert_fdi_tx_enabled(dev_priv, pipe);
1302         assert_fdi_rx_enabled(dev_priv, pipe);
1303
1304         reg = TRANSCONF(pipe);
1305         val = I915_READ(reg);
1306         pipeconf_val = I915_READ(PIPECONF(pipe));
1307
1308         if (HAS_PCH_IBX(dev_priv->dev)) {
1309                 /*
1310                  * make the BPC in transcoder be consistent with
1311                  * that in pipeconf reg.
1312                  */
1313                 val &= ~PIPE_BPC_MASK;
1314                 val |= pipeconf_val & PIPE_BPC_MASK;
1315         }
1316
1317         val &= ~TRANS_INTERLACE_MASK;
1318         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1319                 if (HAS_PCH_IBX(dev_priv->dev) &&
1320                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1321                         val |= TRANS_LEGACY_INTERLACED_ILK;
1322                 else
1323                         val |= TRANS_INTERLACED;
1324         else
1325                 val |= TRANS_PROGRESSIVE;
1326
1327         I915_WRITE(reg, val | TRANS_ENABLE);
1328         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1329                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1330 }
1331
1332 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1333                                      enum pipe pipe)
1334 {
1335         int reg;
1336         u32 val;
1337
1338         /* FDI relies on the transcoder */
1339         assert_fdi_tx_disabled(dev_priv, pipe);
1340         assert_fdi_rx_disabled(dev_priv, pipe);
1341
1342         /* Ports must be off as well */
1343         assert_pch_ports_disabled(dev_priv, pipe);
1344
1345         reg = TRANSCONF(pipe);
1346         val = I915_READ(reg);
1347         val &= ~TRANS_ENABLE;
1348         I915_WRITE(reg, val);
1349         /* wait for PCH transcoder off, transcoder state */
1350         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1351                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1352 }
1353
1354 /**
1355  * intel_enable_pipe - enable a pipe, asserting requirements
1356  * @dev_priv: i915 private structure
1357  * @pipe: pipe to enable
1358  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1359  *
1360  * Enable @pipe, making sure that various hardware specific requirements
1361  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1362  *
1363  * @pipe should be %PIPE_A or %PIPE_B.
1364  *
1365  * Will wait until the pipe is actually running (i.e. first vblank) before
1366  * returning.
1367  */
1368 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1369                               bool pch_port)
1370 {
1371         int reg;
1372         u32 val;
1373
1374         /*
1375          * A pipe without a PLL won't actually be able to drive bits from
1376          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1377          * need the check.
1378          */
1379         if (!HAS_PCH_SPLIT(dev_priv->dev))
1380                 assert_pll_enabled(dev_priv, pipe);
1381         else {
1382                 if (pch_port) {
1383                         /* if driving the PCH, we need FDI enabled */
1384                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1385                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1386                 }
1387                 /* FIXME: assert CPU port conditions for SNB+ */
1388         }
1389
1390         reg = PIPECONF(pipe);
1391         val = I915_READ(reg);
1392         if (val & PIPECONF_ENABLE)
1393                 return;
1394
1395         I915_WRITE(reg, val | PIPECONF_ENABLE);
1396         intel_wait_for_vblank(dev_priv->dev, pipe);
1397 }
1398
1399 /**
1400  * intel_disable_pipe - disable a pipe, asserting requirements
1401  * @dev_priv: i915 private structure
1402  * @pipe: pipe to disable
1403  *
1404  * Disable @pipe, making sure that various hardware specific requirements
1405  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1406  *
1407  * @pipe should be %PIPE_A or %PIPE_B.
1408  *
1409  * Will wait until the pipe has shut down before returning.
1410  */
1411 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1412                                enum pipe pipe)
1413 {
1414         int reg;
1415         u32 val;
1416
1417         /*
1418          * Make sure planes won't keep trying to pump pixels to us,
1419          * or we might hang the display.
1420          */
1421         assert_planes_disabled(dev_priv, pipe);
1422
1423         /* Don't disable pipe A or pipe A PLLs if needed */
1424         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1425                 return;
1426
1427         reg = PIPECONF(pipe);
1428         val = I915_READ(reg);
1429         if ((val & PIPECONF_ENABLE) == 0)
1430                 return;
1431
1432         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1433         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1434 }
1435
1436 /*
1437  * Plane regs are double buffered, going from enabled->disabled needs a
1438  * trigger in order to latch.  The display address reg provides this.
1439  */
1440 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1441                                       enum plane plane)
1442 {
1443         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1444         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1445 }
1446
1447 /**
1448  * intel_enable_plane - enable a display plane on a given pipe
1449  * @dev_priv: i915 private structure
1450  * @plane: plane to enable
1451  * @pipe: pipe being fed
1452  *
1453  * Enable @plane on @pipe, making sure that @pipe is running first.
1454  */
1455 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1456                                enum plane plane, enum pipe pipe)
1457 {
1458         int reg;
1459         u32 val;
1460
1461         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1462         assert_pipe_enabled(dev_priv, pipe);
1463
1464         reg = DSPCNTR(plane);
1465         val = I915_READ(reg);
1466         if (val & DISPLAY_PLANE_ENABLE)
1467                 return;
1468
1469         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1470         intel_flush_display_plane(dev_priv, plane);
1471         intel_wait_for_vblank(dev_priv->dev, pipe);
1472 }
1473
1474 /**
1475  * intel_disable_plane - disable a display plane
1476  * @dev_priv: i915 private structure
1477  * @plane: plane to disable
1478  * @pipe: pipe consuming the data
1479  *
1480  * Disable @plane; should be an independent operation.
1481  */
1482 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1483                                 enum plane plane, enum pipe pipe)
1484 {
1485         int reg;
1486         u32 val;
1487
1488         reg = DSPCNTR(plane);
1489         val = I915_READ(reg);
1490         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1491                 return;
1492
1493         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1494         intel_flush_display_plane(dev_priv, plane);
1495         intel_wait_for_vblank(dev_priv->dev, pipe);
1496 }
1497
1498 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1499                            enum pipe pipe, int reg, u32 port_sel)
1500 {
1501         u32 val = I915_READ(reg);
1502         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1503                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1504                 I915_WRITE(reg, val & ~DP_PORT_EN);
1505         }
1506 }
1507
1508 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1509                              enum pipe pipe, int reg)
1510 {
1511         u32 val = I915_READ(reg);
1512         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1513                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1514                               reg, pipe);
1515                 I915_WRITE(reg, val & ~PORT_ENABLE);
1516         }
1517 }
1518
1519 /* Disable any ports connected to this transcoder */
1520 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1521                                     enum pipe pipe)
1522 {
1523         u32 reg, val;
1524
1525         val = I915_READ(PCH_PP_CONTROL);
1526         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1527
1528         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1529         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1530         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1531
1532         reg = PCH_ADPA;
1533         val = I915_READ(reg);
1534         if (adpa_pipe_enabled(dev_priv, val, pipe))
1535                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1536
1537         reg = PCH_LVDS;
1538         val = I915_READ(reg);
1539         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1540                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1541                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1542                 POSTING_READ(reg);
1543                 udelay(100);
1544         }
1545
1546         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1547         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1548         disable_pch_hdmi(dev_priv, pipe, HDMID);
1549 }
1550
1551 static void i8xx_disable_fbc(struct drm_device *dev)
1552 {
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         u32 fbc_ctl;
1555
1556         /* Disable compression */
1557         fbc_ctl = I915_READ(FBC_CONTROL);
1558         if ((fbc_ctl & FBC_CTL_EN) == 0)
1559                 return;
1560
1561         fbc_ctl &= ~FBC_CTL_EN;
1562         I915_WRITE(FBC_CONTROL, fbc_ctl);
1563
1564         /* Wait for compressing bit to clear */
1565         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1566                 DRM_DEBUG_KMS("FBC idle timed out\n");
1567                 return;
1568         }
1569
1570         DRM_DEBUG_KMS("disabled FBC\n");
1571 }
1572
1573 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1574 {
1575         struct drm_device *dev = crtc->dev;
1576         struct drm_i915_private *dev_priv = dev->dev_private;
1577         struct drm_framebuffer *fb = crtc->fb;
1578         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1579         struct drm_i915_gem_object *obj = intel_fb->obj;
1580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1581         int cfb_pitch;
1582         int plane, i;
1583         u32 fbc_ctl, fbc_ctl2;
1584
1585         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1586         if (fb->pitches[0] < cfb_pitch)
1587                 cfb_pitch = fb->pitches[0];
1588
1589         /* FBC_CTL wants 64B units */
1590         cfb_pitch = (cfb_pitch / 64) - 1;
1591         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1592
1593         /* Clear old tags */
1594         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1595                 I915_WRITE(FBC_TAG + (i * 4), 0);
1596
1597         /* Set it up... */
1598         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1599         fbc_ctl2 |= plane;
1600         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1601         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1602
1603         /* enable it... */
1604         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1605         if (IS_I945GM(dev))
1606                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1607         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1608         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1609         fbc_ctl |= obj->fence_reg;
1610         I915_WRITE(FBC_CONTROL, fbc_ctl);
1611
1612         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1613                       cfb_pitch, crtc->y, intel_crtc->plane);
1614 }
1615
1616 static bool i8xx_fbc_enabled(struct drm_device *dev)
1617 {
1618         struct drm_i915_private *dev_priv = dev->dev_private;
1619
1620         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1621 }
1622
1623 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1624 {
1625         struct drm_device *dev = crtc->dev;
1626         struct drm_i915_private *dev_priv = dev->dev_private;
1627         struct drm_framebuffer *fb = crtc->fb;
1628         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1629         struct drm_i915_gem_object *obj = intel_fb->obj;
1630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1631         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1632         unsigned long stall_watermark = 200;
1633         u32 dpfc_ctl;
1634
1635         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1636         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1637         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1638
1639         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1640                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1641                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1642         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1643
1644         /* enable it... */
1645         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1646
1647         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1648 }
1649
1650 static void g4x_disable_fbc(struct drm_device *dev)
1651 {
1652         struct drm_i915_private *dev_priv = dev->dev_private;
1653         u32 dpfc_ctl;
1654
1655         /* Disable compression */
1656         dpfc_ctl = I915_READ(DPFC_CONTROL);
1657         if (dpfc_ctl & DPFC_CTL_EN) {
1658                 dpfc_ctl &= ~DPFC_CTL_EN;
1659                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1660
1661                 DRM_DEBUG_KMS("disabled FBC\n");
1662         }
1663 }
1664
1665 static bool g4x_fbc_enabled(struct drm_device *dev)
1666 {
1667         struct drm_i915_private *dev_priv = dev->dev_private;
1668
1669         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1670 }
1671
1672 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1673 {
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675         u32 blt_ecoskpd;
1676
1677         /* Make sure blitter notifies FBC of writes */
1678         gen6_gt_force_wake_get(dev_priv);
1679         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1680         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1681                 GEN6_BLITTER_LOCK_SHIFT;
1682         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1683         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1684         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1685         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1686                          GEN6_BLITTER_LOCK_SHIFT);
1687         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1688         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1689         gen6_gt_force_wake_put(dev_priv);
1690 }
1691
1692 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1693 {
1694         struct drm_device *dev = crtc->dev;
1695         struct drm_i915_private *dev_priv = dev->dev_private;
1696         struct drm_framebuffer *fb = crtc->fb;
1697         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1698         struct drm_i915_gem_object *obj = intel_fb->obj;
1699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1700         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1701         unsigned long stall_watermark = 200;
1702         u32 dpfc_ctl;
1703
1704         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1705         dpfc_ctl &= DPFC_RESERVED;
1706         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1707         /* Set persistent mode for front-buffer rendering, ala X. */
1708         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1709         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1710         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1711
1712         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1713                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1714                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1715         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1716         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1717         /* enable it... */
1718         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1719
1720         if (IS_GEN6(dev)) {
1721                 I915_WRITE(SNB_DPFC_CTL_SA,
1722                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1723                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1724                 sandybridge_blit_fbc_update(dev);
1725         }
1726
1727         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1728 }
1729
1730 static void ironlake_disable_fbc(struct drm_device *dev)
1731 {
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733         u32 dpfc_ctl;
1734
1735         /* Disable compression */
1736         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1737         if (dpfc_ctl & DPFC_CTL_EN) {
1738                 dpfc_ctl &= ~DPFC_CTL_EN;
1739                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1740
1741                 DRM_DEBUG_KMS("disabled FBC\n");
1742         }
1743 }
1744
1745 static bool ironlake_fbc_enabled(struct drm_device *dev)
1746 {
1747         struct drm_i915_private *dev_priv = dev->dev_private;
1748
1749         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1750 }
1751
1752 bool intel_fbc_enabled(struct drm_device *dev)
1753 {
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755
1756         if (!dev_priv->display.fbc_enabled)
1757                 return false;
1758
1759         return dev_priv->display.fbc_enabled(dev);
1760 }
1761
1762 static void intel_fbc_work_fn(struct work_struct *__work)
1763 {
1764         struct intel_fbc_work *work =
1765                 container_of(to_delayed_work(__work),
1766                              struct intel_fbc_work, work);
1767         struct drm_device *dev = work->crtc->dev;
1768         struct drm_i915_private *dev_priv = dev->dev_private;
1769
1770         mutex_lock(&dev->struct_mutex);
1771         if (work == dev_priv->fbc_work) {
1772                 /* Double check that we haven't switched fb without cancelling
1773                  * the prior work.
1774                  */
1775                 if (work->crtc->fb == work->fb) {
1776                         dev_priv->display.enable_fbc(work->crtc,
1777                                                      work->interval);
1778
1779                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1780                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1781                         dev_priv->cfb_y = work->crtc->y;
1782                 }
1783
1784                 dev_priv->fbc_work = NULL;
1785         }
1786         mutex_unlock(&dev->struct_mutex);
1787
1788         kfree(work);
1789 }
1790
1791 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1792 {
1793         if (dev_priv->fbc_work == NULL)
1794                 return;
1795
1796         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1797
1798         /* Synchronisation is provided by struct_mutex and checking of
1799          * dev_priv->fbc_work, so we can perform the cancellation
1800          * entirely asynchronously.
1801          */
1802         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1803                 /* tasklet was killed before being run, clean up */
1804                 kfree(dev_priv->fbc_work);
1805
1806         /* Mark the work as no longer wanted so that if it does
1807          * wake-up (because the work was already running and waiting
1808          * for our mutex), it will discover that is no longer
1809          * necessary to run.
1810          */
1811         dev_priv->fbc_work = NULL;
1812 }
1813
1814 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1815 {
1816         struct intel_fbc_work *work;
1817         struct drm_device *dev = crtc->dev;
1818         struct drm_i915_private *dev_priv = dev->dev_private;
1819
1820         if (!dev_priv->display.enable_fbc)
1821                 return;
1822
1823         intel_cancel_fbc_work(dev_priv);
1824
1825         work = kzalloc(sizeof *work, GFP_KERNEL);
1826         if (work == NULL) {
1827                 dev_priv->display.enable_fbc(crtc, interval);
1828                 return;
1829         }
1830
1831         work->crtc = crtc;
1832         work->fb = crtc->fb;
1833         work->interval = interval;
1834         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1835
1836         dev_priv->fbc_work = work;
1837
1838         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1839
1840         /* Delay the actual enabling to let pageflipping cease and the
1841          * display to settle before starting the compression. Note that
1842          * this delay also serves a second purpose: it allows for a
1843          * vblank to pass after disabling the FBC before we attempt
1844          * to modify the control registers.
1845          *
1846          * A more complicated solution would involve tracking vblanks
1847          * following the termination of the page-flipping sequence
1848          * and indeed performing the enable as a co-routine and not
1849          * waiting synchronously upon the vblank.
1850          */
1851         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1852 }
1853
1854 void intel_disable_fbc(struct drm_device *dev)
1855 {
1856         struct drm_i915_private *dev_priv = dev->dev_private;
1857
1858         intel_cancel_fbc_work(dev_priv);
1859
1860         if (!dev_priv->display.disable_fbc)
1861                 return;
1862
1863         dev_priv->display.disable_fbc(dev);
1864         dev_priv->cfb_plane = -1;
1865 }
1866
1867 /**
1868  * intel_update_fbc - enable/disable FBC as needed
1869  * @dev: the drm_device
1870  *
1871  * Set up the framebuffer compression hardware at mode set time.  We
1872  * enable it if possible:
1873  *   - plane A only (on pre-965)
1874  *   - no pixel mulitply/line duplication
1875  *   - no alpha buffer discard
1876  *   - no dual wide
1877  *   - framebuffer <= 2048 in width, 1536 in height
1878  *
1879  * We can't assume that any compression will take place (worst case),
1880  * so the compressed buffer has to be the same size as the uncompressed
1881  * one.  It also must reside (along with the line length buffer) in
1882  * stolen memory.
1883  *
1884  * We need to enable/disable FBC on a global basis.
1885  */
1886 static void intel_update_fbc(struct drm_device *dev)
1887 {
1888         struct drm_i915_private *dev_priv = dev->dev_private;
1889         struct drm_crtc *crtc = NULL, *tmp_crtc;
1890         struct intel_crtc *intel_crtc;
1891         struct drm_framebuffer *fb;
1892         struct intel_framebuffer *intel_fb;
1893         struct drm_i915_gem_object *obj;
1894         int enable_fbc;
1895
1896         DRM_DEBUG_KMS("\n");
1897
1898         if (!i915_powersave)
1899                 return;
1900
1901         if (!I915_HAS_FBC(dev))
1902                 return;
1903
1904         /*
1905          * If FBC is already on, we just have to verify that we can
1906          * keep it that way...
1907          * Need to disable if:
1908          *   - more than one pipe is active
1909          *   - changing FBC params (stride, fence, mode)
1910          *   - new fb is too large to fit in compressed buffer
1911          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1912          */
1913         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1914                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1915                         if (crtc) {
1916                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1917                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1918                                 goto out_disable;
1919                         }
1920                         crtc = tmp_crtc;
1921                 }
1922         }
1923
1924         if (!crtc || crtc->fb == NULL) {
1925                 DRM_DEBUG_KMS("no output, disabling\n");
1926                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1927                 goto out_disable;
1928         }
1929
1930         intel_crtc = to_intel_crtc(crtc);
1931         fb = crtc->fb;
1932         intel_fb = to_intel_framebuffer(fb);
1933         obj = intel_fb->obj;
1934
1935         enable_fbc = i915_enable_fbc;
1936         if (enable_fbc < 0) {
1937                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1938                 enable_fbc = 1;
1939                 if (INTEL_INFO(dev)->gen <= 6)
1940                         enable_fbc = 0;
1941         }
1942         if (!enable_fbc) {
1943                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1944                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1945                 goto out_disable;
1946         }
1947         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1948                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1949                               "compression\n");
1950                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1951                 goto out_disable;
1952         }
1953         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1954             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1955                 DRM_DEBUG_KMS("mode incompatible with compression, "
1956                               "disabling\n");
1957                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1958                 goto out_disable;
1959         }
1960         if ((crtc->mode.hdisplay > 2048) ||
1961             (crtc->mode.vdisplay > 1536)) {
1962                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1963                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1964                 goto out_disable;
1965         }
1966         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1967                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1968                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1969                 goto out_disable;
1970         }
1971
1972         /* The use of a CPU fence is mandatory in order to detect writes
1973          * by the CPU to the scanout and trigger updates to the FBC.
1974          */
1975         if (obj->tiling_mode != I915_TILING_X ||
1976             obj->fence_reg == I915_FENCE_REG_NONE) {
1977                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1978                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1979                 goto out_disable;
1980         }
1981
1982         /* If the kernel debugger is active, always disable compression */
1983         if (in_dbg_master())
1984                 goto out_disable;
1985
1986         /* If the scanout has not changed, don't modify the FBC settings.
1987          * Note that we make the fundamental assumption that the fb->obj
1988          * cannot be unpinned (and have its GTT offset and fence revoked)
1989          * without first being decoupled from the scanout and FBC disabled.
1990          */
1991         if (dev_priv->cfb_plane == intel_crtc->plane &&
1992             dev_priv->cfb_fb == fb->base.id &&
1993             dev_priv->cfb_y == crtc->y)
1994                 return;
1995
1996         if (intel_fbc_enabled(dev)) {
1997                 /* We update FBC along two paths, after changing fb/crtc
1998                  * configuration (modeswitching) and after page-flipping
1999                  * finishes. For the latter, we know that not only did
2000                  * we disable the FBC at the start of the page-flip
2001                  * sequence, but also more than one vblank has passed.
2002                  *
2003                  * For the former case of modeswitching, it is possible
2004                  * to switch between two FBC valid configurations
2005                  * instantaneously so we do need to disable the FBC
2006                  * before we can modify its control registers. We also
2007                  * have to wait for the next vblank for that to take
2008                  * effect. However, since we delay enabling FBC we can
2009                  * assume that a vblank has passed since disabling and
2010                  * that we can safely alter the registers in the deferred
2011                  * callback.
2012                  *
2013                  * In the scenario that we go from a valid to invalid
2014                  * and then back to valid FBC configuration we have
2015                  * no strict enforcement that a vblank occurred since
2016                  * disabling the FBC. However, along all current pipe
2017                  * disabling paths we do need to wait for a vblank at
2018                  * some point. And we wait before enabling FBC anyway.
2019                  */
2020                 DRM_DEBUG_KMS("disabling active FBC for update\n");
2021                 intel_disable_fbc(dev);
2022         }
2023
2024         intel_enable_fbc(crtc, 500);
2025         return;
2026
2027 out_disable:
2028         /* Multiple disables should be harmless */
2029         if (intel_fbc_enabled(dev)) {
2030                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2031                 intel_disable_fbc(dev);
2032         }
2033 }
2034
2035 int
2036 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2037                            struct drm_i915_gem_object *obj,
2038                            struct intel_ring_buffer *pipelined)
2039 {
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041         u32 alignment;
2042         int ret;
2043
2044         switch (obj->tiling_mode) {
2045         case I915_TILING_NONE:
2046                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2047                         alignment = 128 * 1024;
2048                 else if (INTEL_INFO(dev)->gen >= 4)
2049                         alignment = 4 * 1024;
2050                 else
2051                         alignment = 64 * 1024;
2052                 break;
2053         case I915_TILING_X:
2054                 /* pin() will align the object as required by fence */
2055                 alignment = 0;
2056                 break;
2057         case I915_TILING_Y:
2058                 /* FIXME: Is this true? */
2059                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2060                 return -EINVAL;
2061         default:
2062                 BUG();
2063         }
2064
2065         dev_priv->mm.interruptible = false;
2066         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2067         if (ret)
2068                 goto err_interruptible;
2069
2070         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2071          * fence, whereas 965+ only requires a fence if using
2072          * framebuffer compression.  For simplicity, we always install
2073          * a fence as the cost is not that onerous.
2074          */
2075         if (obj->tiling_mode != I915_TILING_NONE) {
2076                 ret = i915_gem_object_get_fence(obj, pipelined);
2077                 if (ret)
2078                         goto err_unpin;
2079
2080                 i915_gem_object_pin_fence(obj);
2081         }
2082
2083         dev_priv->mm.interruptible = true;
2084         return 0;
2085
2086 err_unpin:
2087         i915_gem_object_unpin(obj);
2088 err_interruptible:
2089         dev_priv->mm.interruptible = true;
2090         return ret;
2091 }
2092
2093 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2094 {
2095         i915_gem_object_unpin_fence(obj);
2096         i915_gem_object_unpin(obj);
2097 }
2098
2099 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2100                              int x, int y)
2101 {
2102         struct drm_device *dev = crtc->dev;
2103         struct drm_i915_private *dev_priv = dev->dev_private;
2104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2105         struct intel_framebuffer *intel_fb;
2106         struct drm_i915_gem_object *obj;
2107         int plane = intel_crtc->plane;
2108         unsigned long Start, Offset;
2109         u32 dspcntr;
2110         u32 reg;
2111
2112         switch (plane) {
2113         case 0:
2114         case 1:
2115                 break;
2116         default:
2117                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2118                 return -EINVAL;
2119         }
2120
2121         intel_fb = to_intel_framebuffer(fb);
2122         obj = intel_fb->obj;
2123
2124         reg = DSPCNTR(plane);
2125         dspcntr = I915_READ(reg);
2126         /* Mask out pixel format bits in case we change it */
2127         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2128         switch (fb->bits_per_pixel) {
2129         case 8:
2130                 dspcntr |= DISPPLANE_8BPP;
2131                 break;
2132         case 16:
2133                 if (fb->depth == 15)
2134                         dspcntr |= DISPPLANE_15_16BPP;
2135                 else
2136                         dspcntr |= DISPPLANE_16BPP;
2137                 break;
2138         case 24:
2139         case 32:
2140                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2141                 break;
2142         default:
2143                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2144                 return -EINVAL;
2145         }
2146         if (INTEL_INFO(dev)->gen >= 4) {
2147                 if (obj->tiling_mode != I915_TILING_NONE)
2148                         dspcntr |= DISPPLANE_TILED;
2149                 else
2150                         dspcntr &= ~DISPPLANE_TILED;
2151         }
2152
2153         I915_WRITE(reg, dspcntr);
2154
2155         Start = obj->gtt_offset;
2156         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2157
2158         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2159                       Start, Offset, x, y, fb->pitches[0]);
2160         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2161         if (INTEL_INFO(dev)->gen >= 4) {
2162                 I915_WRITE(DSPSURF(plane), Start);
2163                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164                 I915_WRITE(DSPADDR(plane), Offset);
2165         } else
2166                 I915_WRITE(DSPADDR(plane), Start + Offset);
2167         POSTING_READ(reg);
2168
2169         return 0;
2170 }
2171
2172 static int ironlake_update_plane(struct drm_crtc *crtc,
2173                                  struct drm_framebuffer *fb, int x, int y)
2174 {
2175         struct drm_device *dev = crtc->dev;
2176         struct drm_i915_private *dev_priv = dev->dev_private;
2177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2178         struct intel_framebuffer *intel_fb;
2179         struct drm_i915_gem_object *obj;
2180         int plane = intel_crtc->plane;
2181         unsigned long Start, Offset;
2182         u32 dspcntr;
2183         u32 reg;
2184
2185         switch (plane) {
2186         case 0:
2187         case 1:
2188         case 2:
2189                 break;
2190         default:
2191                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2192                 return -EINVAL;
2193         }
2194
2195         intel_fb = to_intel_framebuffer(fb);
2196         obj = intel_fb->obj;
2197
2198         reg = DSPCNTR(plane);
2199         dspcntr = I915_READ(reg);
2200         /* Mask out pixel format bits in case we change it */
2201         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2202         switch (fb->bits_per_pixel) {
2203         case 8:
2204                 dspcntr |= DISPPLANE_8BPP;
2205                 break;
2206         case 16:
2207                 if (fb->depth != 16)
2208                         return -EINVAL;
2209
2210                 dspcntr |= DISPPLANE_16BPP;
2211                 break;
2212         case 24:
2213         case 32:
2214                 if (fb->depth == 24)
2215                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2216                 else if (fb->depth == 30)
2217                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2218                 else
2219                         return -EINVAL;
2220                 break;
2221         default:
2222                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2223                 return -EINVAL;
2224         }
2225
2226         if (obj->tiling_mode != I915_TILING_NONE)
2227                 dspcntr |= DISPPLANE_TILED;
2228         else
2229                 dspcntr &= ~DISPPLANE_TILED;
2230
2231         /* must disable */
2232         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2233
2234         I915_WRITE(reg, dspcntr);
2235
2236         Start = obj->gtt_offset;
2237         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2238
2239         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2240                       Start, Offset, x, y, fb->pitches[0]);
2241         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2242         I915_WRITE(DSPSURF(plane), Start);
2243         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2244         I915_WRITE(DSPADDR(plane), Offset);
2245         POSTING_READ(reg);
2246
2247         return 0;
2248 }
2249
2250 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2251 static int
2252 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2253                            int x, int y, enum mode_set_atomic state)
2254 {
2255         struct drm_device *dev = crtc->dev;
2256         struct drm_i915_private *dev_priv = dev->dev_private;
2257         int ret;
2258
2259         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2260         if (ret)
2261                 return ret;
2262
2263         intel_update_fbc(dev);
2264         intel_increase_pllclock(crtc);
2265
2266         return 0;
2267 }
2268
2269 static int
2270 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2271                     struct drm_framebuffer *old_fb)
2272 {
2273         struct drm_device *dev = crtc->dev;
2274         struct drm_i915_master_private *master_priv;
2275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2276         int ret;
2277
2278         /* no fb bound */
2279         if (!crtc->fb) {
2280                 DRM_ERROR("No FB bound\n");
2281                 return 0;
2282         }
2283
2284         switch (intel_crtc->plane) {
2285         case 0:
2286         case 1:
2287                 break;
2288         case 2:
2289                 if (IS_IVYBRIDGE(dev))
2290                         break;
2291                 /* fall through otherwise */
2292         default:
2293                 DRM_ERROR("no plane for crtc\n");
2294                 return -EINVAL;
2295         }
2296
2297         mutex_lock(&dev->struct_mutex);
2298         ret = intel_pin_and_fence_fb_obj(dev,
2299                                          to_intel_framebuffer(crtc->fb)->obj,
2300                                          NULL);
2301         if (ret != 0) {
2302                 mutex_unlock(&dev->struct_mutex);
2303                 DRM_ERROR("pin & fence failed\n");
2304                 return ret;
2305         }
2306
2307         if (old_fb) {
2308                 struct drm_i915_private *dev_priv = dev->dev_private;
2309                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2310
2311                 wait_event(dev_priv->pending_flip_queue,
2312                            atomic_read(&dev_priv->mm.wedged) ||
2313                            atomic_read(&obj->pending_flip) == 0);
2314
2315                 /* Big Hammer, we also need to ensure that any pending
2316                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2317                  * current scanout is retired before unpinning the old
2318                  * framebuffer.
2319                  *
2320                  * This should only fail upon a hung GPU, in which case we
2321                  * can safely continue.
2322                  */
2323                 ret = i915_gem_object_finish_gpu(obj);
2324                 (void) ret;
2325         }
2326
2327         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2328                                          LEAVE_ATOMIC_MODE_SET);
2329         if (ret) {
2330                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2331                 mutex_unlock(&dev->struct_mutex);
2332                 DRM_ERROR("failed to update base address\n");
2333                 return ret;
2334         }
2335
2336         if (old_fb) {
2337                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2338                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2339         }
2340
2341         mutex_unlock(&dev->struct_mutex);
2342
2343         if (!dev->primary->master)
2344                 return 0;
2345
2346         master_priv = dev->primary->master->driver_priv;
2347         if (!master_priv->sarea_priv)
2348                 return 0;
2349
2350         if (intel_crtc->pipe) {
2351                 master_priv->sarea_priv->pipeB_x = x;
2352                 master_priv->sarea_priv->pipeB_y = y;
2353         } else {
2354                 master_priv->sarea_priv->pipeA_x = x;
2355                 master_priv->sarea_priv->pipeA_y = y;
2356         }
2357
2358         return 0;
2359 }
2360
2361 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2362 {
2363         struct drm_device *dev = crtc->dev;
2364         struct drm_i915_private *dev_priv = dev->dev_private;
2365         u32 dpa_ctl;
2366
2367         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2368         dpa_ctl = I915_READ(DP_A);
2369         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2370
2371         if (clock < 200000) {
2372                 u32 temp;
2373                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2374                 /* workaround for 160Mhz:
2375                    1) program 0x4600c bits 15:0 = 0x8124
2376                    2) program 0x46010 bit 0 = 1
2377                    3) program 0x46034 bit 24 = 1
2378                    4) program 0x64000 bit 14 = 1
2379                    */
2380                 temp = I915_READ(0x4600c);
2381                 temp &= 0xffff0000;
2382                 I915_WRITE(0x4600c, temp | 0x8124);
2383
2384                 temp = I915_READ(0x46010);
2385                 I915_WRITE(0x46010, temp | 1);
2386
2387                 temp = I915_READ(0x46034);
2388                 I915_WRITE(0x46034, temp | (1 << 24));
2389         } else {
2390                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2391         }
2392         I915_WRITE(DP_A, dpa_ctl);
2393
2394         POSTING_READ(DP_A);
2395         udelay(500);
2396 }
2397
2398 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2399 {
2400         struct drm_device *dev = crtc->dev;
2401         struct drm_i915_private *dev_priv = dev->dev_private;
2402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403         int pipe = intel_crtc->pipe;
2404         u32 reg, temp;
2405
2406         /* enable normal train */
2407         reg = FDI_TX_CTL(pipe);
2408         temp = I915_READ(reg);
2409         if (IS_IVYBRIDGE(dev)) {
2410                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2411                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2412         } else {
2413                 temp &= ~FDI_LINK_TRAIN_NONE;
2414                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2415         }
2416         I915_WRITE(reg, temp);
2417
2418         reg = FDI_RX_CTL(pipe);
2419         temp = I915_READ(reg);
2420         if (HAS_PCH_CPT(dev)) {
2421                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2422                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2423         } else {
2424                 temp &= ~FDI_LINK_TRAIN_NONE;
2425                 temp |= FDI_LINK_TRAIN_NONE;
2426         }
2427         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2428
2429         /* wait one idle pattern time */
2430         POSTING_READ(reg);
2431         udelay(1000);
2432
2433         /* IVB wants error correction enabled */
2434         if (IS_IVYBRIDGE(dev))
2435                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2436                            FDI_FE_ERRC_ENABLE);
2437 }
2438
2439 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2440 {
2441         struct drm_i915_private *dev_priv = dev->dev_private;
2442         u32 flags = I915_READ(SOUTH_CHICKEN1);
2443
2444         flags |= FDI_PHASE_SYNC_OVR(pipe);
2445         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2446         flags |= FDI_PHASE_SYNC_EN(pipe);
2447         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2448         POSTING_READ(SOUTH_CHICKEN1);
2449 }
2450
2451 /* The FDI link training functions for ILK/Ibexpeak. */
2452 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2453 {
2454         struct drm_device *dev = crtc->dev;
2455         struct drm_i915_private *dev_priv = dev->dev_private;
2456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2457         int pipe = intel_crtc->pipe;
2458         int plane = intel_crtc->plane;
2459         u32 reg, temp, tries;
2460
2461         /* FDI needs bits from pipe & plane first */
2462         assert_pipe_enabled(dev_priv, pipe);
2463         assert_plane_enabled(dev_priv, plane);
2464
2465         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2466            for train result */
2467         reg = FDI_RX_IMR(pipe);
2468         temp = I915_READ(reg);
2469         temp &= ~FDI_RX_SYMBOL_LOCK;
2470         temp &= ~FDI_RX_BIT_LOCK;
2471         I915_WRITE(reg, temp);
2472         I915_READ(reg);
2473         udelay(150);
2474
2475         /* enable CPU FDI TX and PCH FDI RX */
2476         reg = FDI_TX_CTL(pipe);
2477         temp = I915_READ(reg);
2478         temp &= ~(7 << 19);
2479         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2480         temp &= ~FDI_LINK_TRAIN_NONE;
2481         temp |= FDI_LINK_TRAIN_PATTERN_1;
2482         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2483
2484         reg = FDI_RX_CTL(pipe);
2485         temp = I915_READ(reg);
2486         temp &= ~FDI_LINK_TRAIN_NONE;
2487         temp |= FDI_LINK_TRAIN_PATTERN_1;
2488         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2489
2490         POSTING_READ(reg);
2491         udelay(150);
2492
2493         /* Ironlake workaround, enable clock pointer after FDI enable*/
2494         if (HAS_PCH_IBX(dev)) {
2495                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2496                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2497                            FDI_RX_PHASE_SYNC_POINTER_EN);
2498         }
2499
2500         reg = FDI_RX_IIR(pipe);
2501         for (tries = 0; tries < 5; tries++) {
2502                 temp = I915_READ(reg);
2503                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2504
2505                 if ((temp & FDI_RX_BIT_LOCK)) {
2506                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2507                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2508                         break;
2509                 }
2510         }
2511         if (tries == 5)
2512                 DRM_ERROR("FDI train 1 fail!\n");
2513
2514         /* Train 2 */
2515         reg = FDI_TX_CTL(pipe);
2516         temp = I915_READ(reg);
2517         temp &= ~FDI_LINK_TRAIN_NONE;
2518         temp |= FDI_LINK_TRAIN_PATTERN_2;
2519         I915_WRITE(reg, temp);
2520
2521         reg = FDI_RX_CTL(pipe);
2522         temp = I915_READ(reg);
2523         temp &= ~FDI_LINK_TRAIN_NONE;
2524         temp |= FDI_LINK_TRAIN_PATTERN_2;
2525         I915_WRITE(reg, temp);
2526
2527         POSTING_READ(reg);
2528         udelay(150);
2529
2530         reg = FDI_RX_IIR(pipe);
2531         for (tries = 0; tries < 5; tries++) {
2532                 temp = I915_READ(reg);
2533                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2534
2535                 if (temp & FDI_RX_SYMBOL_LOCK) {
2536                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2537                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2538                         break;
2539                 }
2540         }
2541         if (tries == 5)
2542                 DRM_ERROR("FDI train 2 fail!\n");
2543
2544         DRM_DEBUG_KMS("FDI train done\n");
2545
2546 }
2547
2548 static const int snb_b_fdi_train_param[] = {
2549         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2550         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2551         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2552         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2553 };
2554
2555 /* The FDI link training functions for SNB/Cougarpoint. */
2556 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2557 {
2558         struct drm_device *dev = crtc->dev;
2559         struct drm_i915_private *dev_priv = dev->dev_private;
2560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2561         int pipe = intel_crtc->pipe;
2562         u32 reg, temp, i, retry;
2563
2564         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2565            for train result */
2566         reg = FDI_RX_IMR(pipe);
2567         temp = I915_READ(reg);
2568         temp &= ~FDI_RX_SYMBOL_LOCK;
2569         temp &= ~FDI_RX_BIT_LOCK;
2570         I915_WRITE(reg, temp);
2571
2572         POSTING_READ(reg);
2573         udelay(150);
2574
2575         /* enable CPU FDI TX and PCH FDI RX */
2576         reg = FDI_TX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         temp &= ~(7 << 19);
2579         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2580         temp &= ~FDI_LINK_TRAIN_NONE;
2581         temp |= FDI_LINK_TRAIN_PATTERN_1;
2582         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583         /* SNB-B */
2584         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2585         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586
2587         reg = FDI_RX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         if (HAS_PCH_CPT(dev)) {
2590                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2592         } else {
2593                 temp &= ~FDI_LINK_TRAIN_NONE;
2594                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2595         }
2596         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2597
2598         POSTING_READ(reg);
2599         udelay(150);
2600
2601         if (HAS_PCH_CPT(dev))
2602                 cpt_phase_pointer_enable(dev, pipe);
2603
2604         for (i = 0; i < 4; i++) {
2605                 reg = FDI_TX_CTL(pipe);
2606                 temp = I915_READ(reg);
2607                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2608                 temp |= snb_b_fdi_train_param[i];
2609                 I915_WRITE(reg, temp);
2610
2611                 POSTING_READ(reg);
2612                 udelay(500);
2613
2614                 for (retry = 0; retry < 5; retry++) {
2615                         reg = FDI_RX_IIR(pipe);
2616                         temp = I915_READ(reg);
2617                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2618                         if (temp & FDI_RX_BIT_LOCK) {
2619                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2620                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2621                                 break;
2622                         }
2623                         udelay(50);
2624                 }
2625                 if (retry < 5)
2626                         break;
2627         }
2628         if (i == 4)
2629                 DRM_ERROR("FDI train 1 fail!\n");
2630
2631         /* Train 2 */
2632         reg = FDI_TX_CTL(pipe);
2633         temp = I915_READ(reg);
2634         temp &= ~FDI_LINK_TRAIN_NONE;
2635         temp |= FDI_LINK_TRAIN_PATTERN_2;
2636         if (IS_GEN6(dev)) {
2637                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2638                 /* SNB-B */
2639                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2640         }
2641         I915_WRITE(reg, temp);
2642
2643         reg = FDI_RX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         if (HAS_PCH_CPT(dev)) {
2646                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2647                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2648         } else {
2649                 temp &= ~FDI_LINK_TRAIN_NONE;
2650                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2651         }
2652         I915_WRITE(reg, temp);
2653
2654         POSTING_READ(reg);
2655         udelay(150);
2656
2657         for (i = 0; i < 4; i++) {
2658                 reg = FDI_TX_CTL(pipe);
2659                 temp = I915_READ(reg);
2660                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2661                 temp |= snb_b_fdi_train_param[i];
2662                 I915_WRITE(reg, temp);
2663
2664                 POSTING_READ(reg);
2665                 udelay(500);
2666
2667                 for (retry = 0; retry < 5; retry++) {
2668                         reg = FDI_RX_IIR(pipe);
2669                         temp = I915_READ(reg);
2670                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2671                         if (temp & FDI_RX_SYMBOL_LOCK) {
2672                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2673                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2674                                 break;
2675                         }
2676                         udelay(50);
2677                 }
2678                 if (retry < 5)
2679                         break;
2680         }
2681         if (i == 4)
2682                 DRM_ERROR("FDI train 2 fail!\n");
2683
2684         DRM_DEBUG_KMS("FDI train done.\n");
2685 }
2686
2687 /* Manual link training for Ivy Bridge A0 parts */
2688 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2689 {
2690         struct drm_device *dev = crtc->dev;
2691         struct drm_i915_private *dev_priv = dev->dev_private;
2692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2693         int pipe = intel_crtc->pipe;
2694         u32 reg, temp, i;
2695
2696         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2697            for train result */
2698         reg = FDI_RX_IMR(pipe);
2699         temp = I915_READ(reg);
2700         temp &= ~FDI_RX_SYMBOL_LOCK;
2701         temp &= ~FDI_RX_BIT_LOCK;
2702         I915_WRITE(reg, temp);
2703
2704         POSTING_READ(reg);
2705         udelay(150);
2706
2707         /* enable CPU FDI TX and PCH FDI RX */
2708         reg = FDI_TX_CTL(pipe);
2709         temp = I915_READ(reg);
2710         temp &= ~(7 << 19);
2711         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2712         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2713         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2714         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2715         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2716         temp |= FDI_COMPOSITE_SYNC;
2717         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2718
2719         reg = FDI_RX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         temp &= ~FDI_LINK_TRAIN_AUTO;
2722         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2723         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2724         temp |= FDI_COMPOSITE_SYNC;
2725         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2726
2727         POSTING_READ(reg);
2728         udelay(150);
2729
2730         if (HAS_PCH_CPT(dev))
2731                 cpt_phase_pointer_enable(dev, pipe);
2732
2733         for (i = 0; i < 4; i++) {
2734                 reg = FDI_TX_CTL(pipe);
2735                 temp = I915_READ(reg);
2736                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2737                 temp |= snb_b_fdi_train_param[i];
2738                 I915_WRITE(reg, temp);
2739
2740                 POSTING_READ(reg);
2741                 udelay(500);
2742
2743                 reg = FDI_RX_IIR(pipe);
2744                 temp = I915_READ(reg);
2745                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2746
2747                 if (temp & FDI_RX_BIT_LOCK ||
2748                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2749                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2750                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2751                         break;
2752                 }
2753         }
2754         if (i == 4)
2755                 DRM_ERROR("FDI train 1 fail!\n");
2756
2757         /* Train 2 */
2758         reg = FDI_TX_CTL(pipe);
2759         temp = I915_READ(reg);
2760         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2761         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2762         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2763         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2764         I915_WRITE(reg, temp);
2765
2766         reg = FDI_RX_CTL(pipe);
2767         temp = I915_READ(reg);
2768         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2769         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2770         I915_WRITE(reg, temp);
2771
2772         POSTING_READ(reg);
2773         udelay(150);
2774
2775         for (i = 0; i < 4; i++) {
2776                 reg = FDI_TX_CTL(pipe);
2777                 temp = I915_READ(reg);
2778                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779                 temp |= snb_b_fdi_train_param[i];
2780                 I915_WRITE(reg, temp);
2781
2782                 POSTING_READ(reg);
2783                 udelay(500);
2784
2785                 reg = FDI_RX_IIR(pipe);
2786                 temp = I915_READ(reg);
2787                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2788
2789                 if (temp & FDI_RX_SYMBOL_LOCK) {
2790                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2791                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2792                         break;
2793                 }
2794         }
2795         if (i == 4)
2796                 DRM_ERROR("FDI train 2 fail!\n");
2797
2798         DRM_DEBUG_KMS("FDI train done.\n");
2799 }
2800
2801 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2802 {
2803         struct drm_device *dev = crtc->dev;
2804         struct drm_i915_private *dev_priv = dev->dev_private;
2805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2806         int pipe = intel_crtc->pipe;
2807         u32 reg, temp;
2808
2809         /* Write the TU size bits so error detection works */
2810         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2811                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2812
2813         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~((0x7 << 19) | (0x7 << 16));
2817         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2818         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821         POSTING_READ(reg);
2822         udelay(200);
2823
2824         /* Switch from Rawclk to PCDclk */
2825         temp = I915_READ(reg);
2826         I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828         POSTING_READ(reg);
2829         udelay(200);
2830
2831         /* Enable CPU FDI TX PLL, always on for Ironlake */
2832         reg = FDI_TX_CTL(pipe);
2833         temp = I915_READ(reg);
2834         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2835                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2836
2837                 POSTING_READ(reg);
2838                 udelay(100);
2839         }
2840 }
2841
2842 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2843 {
2844         struct drm_i915_private *dev_priv = dev->dev_private;
2845         u32 flags = I915_READ(SOUTH_CHICKEN1);
2846
2847         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2848         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2849         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2850         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2851         POSTING_READ(SOUTH_CHICKEN1);
2852 }
2853 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2854 {
2855         struct drm_device *dev = crtc->dev;
2856         struct drm_i915_private *dev_priv = dev->dev_private;
2857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2858         int pipe = intel_crtc->pipe;
2859         u32 reg, temp;
2860
2861         /* disable CPU FDI tx and PCH FDI rx */
2862         reg = FDI_TX_CTL(pipe);
2863         temp = I915_READ(reg);
2864         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2865         POSTING_READ(reg);
2866
2867         reg = FDI_RX_CTL(pipe);
2868         temp = I915_READ(reg);
2869         temp &= ~(0x7 << 16);
2870         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2871         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2872
2873         POSTING_READ(reg);
2874         udelay(100);
2875
2876         /* Ironlake workaround, disable clock pointer after downing FDI */
2877         if (HAS_PCH_IBX(dev)) {
2878                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2879                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2880                            I915_READ(FDI_RX_CHICKEN(pipe) &
2881                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2882         } else if (HAS_PCH_CPT(dev)) {
2883                 cpt_phase_pointer_disable(dev, pipe);
2884         }
2885
2886         /* still set train pattern 1 */
2887         reg = FDI_TX_CTL(pipe);
2888         temp = I915_READ(reg);
2889         temp &= ~FDI_LINK_TRAIN_NONE;
2890         temp |= FDI_LINK_TRAIN_PATTERN_1;
2891         I915_WRITE(reg, temp);
2892
2893         reg = FDI_RX_CTL(pipe);
2894         temp = I915_READ(reg);
2895         if (HAS_PCH_CPT(dev)) {
2896                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2897                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2898         } else {
2899                 temp &= ~FDI_LINK_TRAIN_NONE;
2900                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2901         }
2902         /* BPC in FDI rx is consistent with that in PIPECONF */
2903         temp &= ~(0x07 << 16);
2904         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2905         I915_WRITE(reg, temp);
2906
2907         POSTING_READ(reg);
2908         udelay(100);
2909 }
2910
2911 /*
2912  * When we disable a pipe, we need to clear any pending scanline wait events
2913  * to avoid hanging the ring, which we assume we are waiting on.
2914  */
2915 static void intel_clear_scanline_wait(struct drm_device *dev)
2916 {
2917         struct drm_i915_private *dev_priv = dev->dev_private;
2918         struct intel_ring_buffer *ring;
2919         u32 tmp;
2920
2921         if (IS_GEN2(dev))
2922                 /* Can't break the hang on i8xx */
2923                 return;
2924
2925         ring = LP_RING(dev_priv);
2926         tmp = I915_READ_CTL(ring);
2927         if (tmp & RING_WAIT)
2928                 I915_WRITE_CTL(ring, tmp);
2929 }
2930
2931 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2932 {
2933         struct drm_i915_gem_object *obj;
2934         struct drm_i915_private *dev_priv;
2935
2936         if (crtc->fb == NULL)
2937                 return;
2938
2939         obj = to_intel_framebuffer(crtc->fb)->obj;
2940         dev_priv = crtc->dev->dev_private;
2941         wait_event(dev_priv->pending_flip_queue,
2942                    atomic_read(&obj->pending_flip) == 0);
2943 }
2944
2945 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2946 {
2947         struct drm_device *dev = crtc->dev;
2948         struct drm_mode_config *mode_config = &dev->mode_config;
2949         struct intel_encoder *encoder;
2950
2951         /*
2952          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2953          * must be driven by its own crtc; no sharing is possible.
2954          */
2955         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2956                 if (encoder->base.crtc != crtc)
2957                         continue;
2958
2959                 switch (encoder->type) {
2960                 case INTEL_OUTPUT_EDP:
2961                         if (!intel_encoder_is_pch_edp(&encoder->base))
2962                                 return false;
2963                         continue;
2964                 }
2965         }
2966
2967         return true;
2968 }
2969
2970 /*
2971  * Enable PCH resources required for PCH ports:
2972  *   - PCH PLLs
2973  *   - FDI training & RX/TX
2974  *   - update transcoder timings
2975  *   - DP transcoding bits
2976  *   - transcoder
2977  */
2978 static void ironlake_pch_enable(struct drm_crtc *crtc)
2979 {
2980         struct drm_device *dev = crtc->dev;
2981         struct drm_i915_private *dev_priv = dev->dev_private;
2982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2983         int pipe = intel_crtc->pipe;
2984         u32 reg, temp, transc_sel;
2985
2986         /* For PCH output, training FDI link */
2987         dev_priv->display.fdi_link_train(crtc);
2988
2989         intel_enable_pch_pll(dev_priv, pipe);
2990
2991         if (HAS_PCH_CPT(dev)) {
2992                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2993                         TRANSC_DPLLB_SEL;
2994
2995                 /* Be sure PCH DPLL SEL is set */
2996                 temp = I915_READ(PCH_DPLL_SEL);
2997                 if (pipe == 0) {
2998                         temp &= ~(TRANSA_DPLLB_SEL);
2999                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3000                 } else if (pipe == 1) {
3001                         temp &= ~(TRANSB_DPLLB_SEL);
3002                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3003                 } else if (pipe == 2) {
3004                         temp &= ~(TRANSC_DPLLB_SEL);
3005                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
3006                 }
3007                 I915_WRITE(PCH_DPLL_SEL, temp);
3008         }
3009
3010         /* set transcoder timing, panel must allow it */
3011         assert_panel_unlocked(dev_priv, pipe);
3012         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3013         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3014         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3015
3016         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3017         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3018         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3019         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3020
3021         intel_fdi_normal_train(crtc);
3022
3023         /* For PCH DP, enable TRANS_DP_CTL */
3024         if (HAS_PCH_CPT(dev) &&
3025             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3026              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3027                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3028                 reg = TRANS_DP_CTL(pipe);
3029                 temp = I915_READ(reg);
3030                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3031                           TRANS_DP_SYNC_MASK |
3032                           TRANS_DP_BPC_MASK);
3033                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3034                          TRANS_DP_ENH_FRAMING);
3035                 temp |= bpc << 9; /* same format but at 11:9 */
3036
3037                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3038                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3039                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3040                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3041
3042                 switch (intel_trans_dp_port_sel(crtc)) {
3043                 case PCH_DP_B:
3044                         temp |= TRANS_DP_PORT_SEL_B;
3045                         break;
3046                 case PCH_DP_C:
3047                         temp |= TRANS_DP_PORT_SEL_C;
3048                         break;
3049                 case PCH_DP_D:
3050                         temp |= TRANS_DP_PORT_SEL_D;
3051                         break;
3052                 default:
3053                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3054                         temp |= TRANS_DP_PORT_SEL_B;
3055                         break;
3056                 }
3057
3058                 I915_WRITE(reg, temp);
3059         }
3060
3061         intel_enable_transcoder(dev_priv, pipe);
3062 }
3063
3064 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3065 {
3066         struct drm_i915_private *dev_priv = dev->dev_private;
3067         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3068         u32 temp;
3069
3070         temp = I915_READ(dslreg);
3071         udelay(500);
3072         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3073                 /* Without this, mode sets may fail silently on FDI */
3074                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3075                 udelay(250);
3076                 I915_WRITE(tc2reg, 0);
3077                 if (wait_for(I915_READ(dslreg) != temp, 5))
3078                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3079         }
3080 }
3081
3082 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3083 {
3084         struct drm_device *dev = crtc->dev;
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087         int pipe = intel_crtc->pipe;
3088         int plane = intel_crtc->plane;
3089         u32 temp;
3090         bool is_pch_port;
3091
3092         if (intel_crtc->active)
3093                 return;
3094
3095         intel_crtc->active = true;
3096         intel_update_watermarks(dev);
3097
3098         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3099                 temp = I915_READ(PCH_LVDS);
3100                 if ((temp & LVDS_PORT_EN) == 0)
3101                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3102         }
3103
3104         is_pch_port = intel_crtc_driving_pch(crtc);
3105
3106         if (is_pch_port)
3107                 ironlake_fdi_pll_enable(crtc);
3108         else
3109                 ironlake_fdi_disable(crtc);
3110
3111         /* Enable panel fitting for LVDS */
3112         if (dev_priv->pch_pf_size &&
3113             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3114                 /* Force use of hard-coded filter coefficients
3115                  * as some pre-programmed values are broken,
3116                  * e.g. x201.
3117                  */
3118                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3119                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3120                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3121         }
3122
3123         /*
3124          * On ILK+ LUT must be loaded before the pipe is running but with
3125          * clocks enabled
3126          */
3127         intel_crtc_load_lut(crtc);
3128
3129         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3130         intel_enable_plane(dev_priv, plane, pipe);
3131
3132         if (is_pch_port)
3133                 ironlake_pch_enable(crtc);
3134
3135         mutex_lock(&dev->struct_mutex);
3136         intel_update_fbc(dev);
3137         mutex_unlock(&dev->struct_mutex);
3138
3139         intel_crtc_update_cursor(crtc, true);
3140 }
3141
3142 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3143 {
3144         struct drm_device *dev = crtc->dev;
3145         struct drm_i915_private *dev_priv = dev->dev_private;
3146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3147         int pipe = intel_crtc->pipe;
3148         int plane = intel_crtc->plane;
3149         u32 reg, temp;
3150
3151         if (!intel_crtc->active)
3152                 return;
3153
3154         intel_crtc_wait_for_pending_flips(crtc);
3155         drm_vblank_off(dev, pipe);
3156         intel_crtc_update_cursor(crtc, false);
3157
3158         intel_disable_plane(dev_priv, plane, pipe);
3159
3160         if (dev_priv->cfb_plane == plane)
3161                 intel_disable_fbc(dev);
3162
3163         intel_disable_pipe(dev_priv, pipe);
3164
3165         /* Disable PF */
3166         I915_WRITE(PF_CTL(pipe), 0);
3167         I915_WRITE(PF_WIN_SZ(pipe), 0);
3168
3169         ironlake_fdi_disable(crtc);
3170
3171         /* This is a horrible layering violation; we should be doing this in
3172          * the connector/encoder ->prepare instead, but we don't always have
3173          * enough information there about the config to know whether it will
3174          * actually be necessary or just cause undesired flicker.
3175          */
3176         intel_disable_pch_ports(dev_priv, pipe);
3177
3178         intel_disable_transcoder(dev_priv, pipe);
3179
3180         if (HAS_PCH_CPT(dev)) {
3181                 /* disable TRANS_DP_CTL */
3182                 reg = TRANS_DP_CTL(pipe);
3183                 temp = I915_READ(reg);
3184                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3185                 temp |= TRANS_DP_PORT_SEL_NONE;
3186                 I915_WRITE(reg, temp);
3187
3188                 /* disable DPLL_SEL */
3189                 temp = I915_READ(PCH_DPLL_SEL);
3190                 switch (pipe) {
3191                 case 0:
3192                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3193                         break;
3194                 case 1:
3195                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3196                         break;
3197                 case 2:
3198                         /* C shares PLL A or B */
3199                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3200                         break;
3201                 default:
3202                         BUG(); /* wtf */
3203                 }
3204                 I915_WRITE(PCH_DPLL_SEL, temp);
3205         }
3206
3207         /* disable PCH DPLL */
3208         if (!intel_crtc->no_pll)
3209                 intel_disable_pch_pll(dev_priv, pipe);
3210
3211         /* Switch from PCDclk to Rawclk */
3212         reg = FDI_RX_CTL(pipe);
3213         temp = I915_READ(reg);
3214         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3215
3216         /* Disable CPU FDI TX PLL */
3217         reg = FDI_TX_CTL(pipe);
3218         temp = I915_READ(reg);
3219         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3220
3221         POSTING_READ(reg);
3222         udelay(100);
3223
3224         reg = FDI_RX_CTL(pipe);
3225         temp = I915_READ(reg);
3226         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3227
3228         /* Wait for the clocks to turn off. */
3229         POSTING_READ(reg);
3230         udelay(100);
3231
3232         intel_crtc->active = false;
3233         intel_update_watermarks(dev);
3234
3235         mutex_lock(&dev->struct_mutex);
3236         intel_update_fbc(dev);
3237         intel_clear_scanline_wait(dev);
3238         mutex_unlock(&dev->struct_mutex);
3239 }
3240
3241 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3242 {
3243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3244         int pipe = intel_crtc->pipe;
3245         int plane = intel_crtc->plane;
3246
3247         /* XXX: When our outputs are all unaware of DPMS modes other than off
3248          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3249          */
3250         switch (mode) {
3251         case DRM_MODE_DPMS_ON:
3252         case DRM_MODE_DPMS_STANDBY:
3253         case DRM_MODE_DPMS_SUSPEND:
3254                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3255                 ironlake_crtc_enable(crtc);
3256                 break;
3257
3258         case DRM_MODE_DPMS_OFF:
3259                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3260                 ironlake_crtc_disable(crtc);
3261                 break;
3262         }
3263 }
3264
3265 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3266 {
3267         if (!enable && intel_crtc->overlay) {
3268                 struct drm_device *dev = intel_crtc->base.dev;
3269                 struct drm_i915_private *dev_priv = dev->dev_private;
3270
3271                 mutex_lock(&dev->struct_mutex);
3272                 dev_priv->mm.interruptible = false;
3273                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3274                 dev_priv->mm.interruptible = true;
3275                 mutex_unlock(&dev->struct_mutex);
3276         }
3277
3278         /* Let userspace switch the overlay on again. In most cases userspace
3279          * has to recompute where to put it anyway.
3280          */
3281 }
3282
3283 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3284 {
3285         struct drm_device *dev = crtc->dev;
3286         struct drm_i915_private *dev_priv = dev->dev_private;
3287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3288         int pipe = intel_crtc->pipe;
3289         int plane = intel_crtc->plane;
3290
3291         if (intel_crtc->active)
3292                 return;
3293
3294         intel_crtc->active = true;
3295         intel_update_watermarks(dev);
3296
3297         intel_enable_pll(dev_priv, pipe);
3298         intel_enable_pipe(dev_priv, pipe, false);
3299         intel_enable_plane(dev_priv, plane, pipe);
3300
3301         intel_crtc_load_lut(crtc);
3302         intel_update_fbc(dev);
3303
3304         /* Give the overlay scaler a chance to enable if it's on this pipe */
3305         intel_crtc_dpms_overlay(intel_crtc, true);
3306         intel_crtc_update_cursor(crtc, true);
3307 }
3308
3309 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3310 {
3311         struct drm_device *dev = crtc->dev;
3312         struct drm_i915_private *dev_priv = dev->dev_private;
3313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3314         int pipe = intel_crtc->pipe;
3315         int plane = intel_crtc->plane;
3316
3317         if (!intel_crtc->active)
3318                 return;
3319
3320         /* Give the overlay scaler a chance to disable if it's on this pipe */
3321         intel_crtc_wait_for_pending_flips(crtc);
3322         drm_vblank_off(dev, pipe);
3323         intel_crtc_dpms_overlay(intel_crtc, false);
3324         intel_crtc_update_cursor(crtc, false);
3325
3326         if (dev_priv->cfb_plane == plane)
3327                 intel_disable_fbc(dev);
3328
3329         intel_disable_plane(dev_priv, plane, pipe);
3330         intel_disable_pipe(dev_priv, pipe);
3331         intel_disable_pll(dev_priv, pipe);
3332
3333         intel_crtc->active = false;
3334         intel_update_fbc(dev);
3335         intel_update_watermarks(dev);
3336         intel_clear_scanline_wait(dev);
3337 }
3338
3339 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3340 {
3341         /* XXX: When our outputs are all unaware of DPMS modes other than off
3342          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3343          */
3344         switch (mode) {
3345         case DRM_MODE_DPMS_ON:
3346         case DRM_MODE_DPMS_STANDBY:
3347         case DRM_MODE_DPMS_SUSPEND:
3348                 i9xx_crtc_enable(crtc);
3349                 break;
3350         case DRM_MODE_DPMS_OFF:
3351                 i9xx_crtc_disable(crtc);
3352                 break;
3353         }
3354 }
3355
3356 /**
3357  * Sets the power management mode of the pipe and plane.
3358  */
3359 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3360 {
3361         struct drm_device *dev = crtc->dev;
3362         struct drm_i915_private *dev_priv = dev->dev_private;
3363         struct drm_i915_master_private *master_priv;
3364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365         int pipe = intel_crtc->pipe;
3366         bool enabled;
3367
3368         if (intel_crtc->dpms_mode == mode)
3369                 return;
3370
3371         intel_crtc->dpms_mode = mode;
3372
3373         dev_priv->display.dpms(crtc, mode);
3374
3375         if (!dev->primary->master)
3376                 return;
3377
3378         master_priv = dev->primary->master->driver_priv;
3379         if (!master_priv->sarea_priv)
3380                 return;
3381
3382         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3383
3384         switch (pipe) {
3385         case 0:
3386                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3387                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3388                 break;
3389         case 1:
3390                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3391                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3392                 break;
3393         default:
3394                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3395                 break;
3396         }
3397 }
3398
3399 static void intel_crtc_disable(struct drm_crtc *crtc)
3400 {
3401         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3402         struct drm_device *dev = crtc->dev;
3403
3404         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3405         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3406         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3407
3408         if (crtc->fb) {
3409                 mutex_lock(&dev->struct_mutex);
3410                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3411                 mutex_unlock(&dev->struct_mutex);
3412         }
3413 }
3414
3415 /* Prepare for a mode set.
3416  *
3417  * Note we could be a lot smarter here.  We need to figure out which outputs
3418  * will be enabled, which disabled (in short, how the config will changes)
3419  * and perform the minimum necessary steps to accomplish that, e.g. updating
3420  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3421  * panel fitting is in the proper state, etc.
3422  */
3423 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3424 {
3425         i9xx_crtc_disable(crtc);
3426 }
3427
3428 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3429 {
3430         i9xx_crtc_enable(crtc);
3431 }
3432
3433 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3434 {
3435         ironlake_crtc_disable(crtc);
3436 }
3437
3438 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3439 {
3440         ironlake_crtc_enable(crtc);
3441 }
3442
3443 void intel_encoder_prepare(struct drm_encoder *encoder)
3444 {
3445         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3446         /* lvds has its own version of prepare see intel_lvds_prepare */
3447         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3448 }
3449
3450 void intel_encoder_commit(struct drm_encoder *encoder)
3451 {
3452         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3453         struct drm_device *dev = encoder->dev;
3454         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3455         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3456
3457         /* lvds has its own version of commit see intel_lvds_commit */
3458         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3459
3460         if (HAS_PCH_CPT(dev))
3461                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3462 }
3463
3464 void intel_encoder_destroy(struct drm_encoder *encoder)
3465 {
3466         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3467
3468         drm_encoder_cleanup(encoder);
3469         kfree(intel_encoder);
3470 }
3471
3472 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3473                                   struct drm_display_mode *mode,
3474                                   struct drm_display_mode *adjusted_mode)
3475 {
3476         struct drm_device *dev = crtc->dev;
3477
3478         if (HAS_PCH_SPLIT(dev)) {
3479                 /* FDI link clock is fixed at 2.7G */
3480                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3481                         return false;
3482         }
3483
3484         /* All interlaced capable intel hw wants timings in frames. */
3485         drm_mode_set_crtcinfo(adjusted_mode, 0);
3486
3487         return true;
3488 }
3489
3490 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3491 {
3492         return 400000; /* FIXME */
3493 }
3494
3495 static int i945_get_display_clock_speed(struct drm_device *dev)
3496 {
3497         return 400000;
3498 }
3499
3500 static int i915_get_display_clock_speed(struct drm_device *dev)
3501 {
3502         return 333000;
3503 }
3504
3505 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3506 {
3507         return 200000;
3508 }
3509
3510 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3511 {
3512         u16 gcfgc = 0;
3513
3514         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3515
3516         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3517                 return 133000;
3518         else {
3519                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3520                 case GC_DISPLAY_CLOCK_333_MHZ:
3521                         return 333000;
3522                 default:
3523                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3524                         return 190000;
3525                 }
3526         }
3527 }
3528
3529 static int i865_get_display_clock_speed(struct drm_device *dev)
3530 {
3531         return 266000;
3532 }
3533
3534 static int i855_get_display_clock_speed(struct drm_device *dev)
3535 {
3536         u16 hpllcc = 0;
3537         /* Assume that the hardware is in the high speed state.  This
3538          * should be the default.
3539          */
3540         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3541         case GC_CLOCK_133_200:
3542         case GC_CLOCK_100_200:
3543                 return 200000;
3544         case GC_CLOCK_166_250:
3545                 return 250000;
3546         case GC_CLOCK_100_133:
3547                 return 133000;
3548         }
3549
3550         /* Shouldn't happen */
3551         return 0;
3552 }
3553
3554 static int i830_get_display_clock_speed(struct drm_device *dev)
3555 {
3556         return 133000;
3557 }
3558
3559 struct fdi_m_n {
3560         u32        tu;
3561         u32        gmch_m;
3562         u32        gmch_n;
3563         u32        link_m;
3564         u32        link_n;
3565 };
3566
3567 static void
3568 fdi_reduce_ratio(u32 *num, u32 *den)
3569 {
3570         while (*num > 0xffffff || *den > 0xffffff) {
3571                 *num >>= 1;
3572                 *den >>= 1;
3573         }
3574 }
3575
3576 static void
3577 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3578                      int link_clock, struct fdi_m_n *m_n)
3579 {
3580         m_n->tu = 64; /* default size */
3581
3582         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3583         m_n->gmch_m = bits_per_pixel * pixel_clock;
3584         m_n->gmch_n = link_clock * nlanes * 8;
3585         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3586
3587         m_n->link_m = pixel_clock;
3588         m_n->link_n = link_clock;
3589         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3590 }
3591
3592
3593 struct intel_watermark_params {
3594         unsigned long fifo_size;
3595         unsigned long max_wm;
3596         unsigned long default_wm;
3597         unsigned long guard_size;
3598         unsigned long cacheline_size;
3599 };
3600
3601 /* Pineview has different values for various configs */
3602 static const struct intel_watermark_params pineview_display_wm = {
3603         PINEVIEW_DISPLAY_FIFO,
3604         PINEVIEW_MAX_WM,
3605         PINEVIEW_DFT_WM,
3606         PINEVIEW_GUARD_WM,
3607         PINEVIEW_FIFO_LINE_SIZE
3608 };
3609 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3610         PINEVIEW_DISPLAY_FIFO,
3611         PINEVIEW_MAX_WM,
3612         PINEVIEW_DFT_HPLLOFF_WM,
3613         PINEVIEW_GUARD_WM,
3614         PINEVIEW_FIFO_LINE_SIZE
3615 };
3616 static const struct intel_watermark_params pineview_cursor_wm = {
3617         PINEVIEW_CURSOR_FIFO,
3618         PINEVIEW_CURSOR_MAX_WM,
3619         PINEVIEW_CURSOR_DFT_WM,
3620         PINEVIEW_CURSOR_GUARD_WM,
3621         PINEVIEW_FIFO_LINE_SIZE,
3622 };
3623 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3624         PINEVIEW_CURSOR_FIFO,
3625         PINEVIEW_CURSOR_MAX_WM,
3626         PINEVIEW_CURSOR_DFT_WM,
3627         PINEVIEW_CURSOR_GUARD_WM,
3628         PINEVIEW_FIFO_LINE_SIZE
3629 };
3630 static const struct intel_watermark_params g4x_wm_info = {
3631         G4X_FIFO_SIZE,
3632         G4X_MAX_WM,
3633         G4X_MAX_WM,
3634         2,
3635         G4X_FIFO_LINE_SIZE,
3636 };
3637 static const struct intel_watermark_params g4x_cursor_wm_info = {
3638         I965_CURSOR_FIFO,
3639         I965_CURSOR_MAX_WM,
3640         I965_CURSOR_DFT_WM,
3641         2,
3642         G4X_FIFO_LINE_SIZE,
3643 };
3644 static const struct intel_watermark_params valleyview_wm_info = {
3645         VALLEYVIEW_FIFO_SIZE,
3646         VALLEYVIEW_MAX_WM,
3647         VALLEYVIEW_MAX_WM,
3648         2,
3649         G4X_FIFO_LINE_SIZE,
3650 };
3651 static const struct intel_watermark_params valleyview_cursor_wm_info = {
3652         I965_CURSOR_FIFO,
3653         VALLEYVIEW_CURSOR_MAX_WM,
3654         I965_CURSOR_DFT_WM,
3655         2,
3656         G4X_FIFO_LINE_SIZE,
3657 };
3658 static const struct intel_watermark_params i965_cursor_wm_info = {
3659         I965_CURSOR_FIFO,
3660         I965_CURSOR_MAX_WM,
3661         I965_CURSOR_DFT_WM,
3662         2,
3663         I915_FIFO_LINE_SIZE,
3664 };
3665 static const struct intel_watermark_params i945_wm_info = {
3666         I945_FIFO_SIZE,
3667         I915_MAX_WM,
3668         1,
3669         2,
3670         I915_FIFO_LINE_SIZE
3671 };
3672 static const struct intel_watermark_params i915_wm_info = {
3673         I915_FIFO_SIZE,
3674         I915_MAX_WM,
3675         1,
3676         2,
3677         I915_FIFO_LINE_SIZE
3678 };
3679 static const struct intel_watermark_params i855_wm_info = {
3680         I855GM_FIFO_SIZE,
3681         I915_MAX_WM,
3682         1,
3683         2,
3684         I830_FIFO_LINE_SIZE
3685 };
3686 static const struct intel_watermark_params i830_wm_info = {
3687         I830_FIFO_SIZE,
3688         I915_MAX_WM,
3689         1,
3690         2,
3691         I830_FIFO_LINE_SIZE
3692 };
3693
3694 static const struct intel_watermark_params ironlake_display_wm_info = {
3695         ILK_DISPLAY_FIFO,
3696         ILK_DISPLAY_MAXWM,
3697         ILK_DISPLAY_DFTWM,
3698         2,
3699         ILK_FIFO_LINE_SIZE
3700 };
3701 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3702         ILK_CURSOR_FIFO,
3703         ILK_CURSOR_MAXWM,
3704         ILK_CURSOR_DFTWM,
3705         2,
3706         ILK_FIFO_LINE_SIZE
3707 };
3708 static const struct intel_watermark_params ironlake_display_srwm_info = {
3709         ILK_DISPLAY_SR_FIFO,
3710         ILK_DISPLAY_MAX_SRWM,
3711         ILK_DISPLAY_DFT_SRWM,
3712         2,
3713         ILK_FIFO_LINE_SIZE
3714 };
3715 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3716         ILK_CURSOR_SR_FIFO,
3717         ILK_CURSOR_MAX_SRWM,
3718         ILK_CURSOR_DFT_SRWM,
3719         2,
3720         ILK_FIFO_LINE_SIZE
3721 };
3722
3723 static const struct intel_watermark_params sandybridge_display_wm_info = {
3724         SNB_DISPLAY_FIFO,
3725         SNB_DISPLAY_MAXWM,
3726         SNB_DISPLAY_DFTWM,
3727         2,
3728         SNB_FIFO_LINE_SIZE
3729 };
3730 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3731         SNB_CURSOR_FIFO,
3732         SNB_CURSOR_MAXWM,
3733         SNB_CURSOR_DFTWM,
3734         2,
3735         SNB_FIFO_LINE_SIZE
3736 };
3737 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3738         SNB_DISPLAY_SR_FIFO,
3739         SNB_DISPLAY_MAX_SRWM,
3740         SNB_DISPLAY_DFT_SRWM,
3741         2,
3742         SNB_FIFO_LINE_SIZE
3743 };
3744 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3745         SNB_CURSOR_SR_FIFO,
3746         SNB_CURSOR_MAX_SRWM,
3747         SNB_CURSOR_DFT_SRWM,
3748         2,
3749         SNB_FIFO_LINE_SIZE
3750 };
3751
3752
3753 /**
3754  * intel_calculate_wm - calculate watermark level
3755  * @clock_in_khz: pixel clock
3756  * @wm: chip FIFO params
3757  * @pixel_size: display pixel size
3758  * @latency_ns: memory latency for the platform
3759  *
3760  * Calculate the watermark level (the level at which the display plane will
3761  * start fetching from memory again).  Each chip has a different display
3762  * FIFO size and allocation, so the caller needs to figure that out and pass
3763  * in the correct intel_watermark_params structure.
3764  *
3765  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3766  * on the pixel size.  When it reaches the watermark level, it'll start
3767  * fetching FIFO line sized based chunks from memory until the FIFO fills
3768  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3769  * will occur, and a display engine hang could result.
3770  */
3771 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3772                                         const struct intel_watermark_params *wm,
3773                                         int fifo_size,
3774                                         int pixel_size,
3775                                         unsigned long latency_ns)
3776 {
3777         long entries_required, wm_size;
3778
3779         /*
3780          * Note: we need to make sure we don't overflow for various clock &
3781          * latency values.
3782          * clocks go from a few thousand to several hundred thousand.
3783          * latency is usually a few thousand
3784          */
3785         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3786                 1000;
3787         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3788
3789         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3790
3791         wm_size = fifo_size - (entries_required + wm->guard_size);
3792
3793         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3794
3795         /* Don't promote wm_size to unsigned... */
3796         if (wm_size > (long)wm->max_wm)
3797                 wm_size = wm->max_wm;
3798         if (wm_size <= 0)
3799                 wm_size = wm->default_wm;
3800         return wm_size;
3801 }
3802
3803 struct cxsr_latency {
3804         int is_desktop;
3805         int is_ddr3;
3806         unsigned long fsb_freq;
3807         unsigned long mem_freq;
3808         unsigned long display_sr;
3809         unsigned long display_hpll_disable;
3810         unsigned long cursor_sr;
3811         unsigned long cursor_hpll_disable;
3812 };
3813
3814 static const struct cxsr_latency cxsr_latency_table[] = {
3815         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3816         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3817         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3818         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3819         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3820
3821         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3822         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3823         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3824         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3825         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3826
3827         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3828         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3829         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3830         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3831         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3832
3833         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3834         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3835         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3836         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3837         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3838
3839         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3840         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3841         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3842         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3843         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3844
3845         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3846         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3847         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3848         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3849         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3850 };
3851
3852 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3853                                                          int is_ddr3,
3854                                                          int fsb,
3855                                                          int mem)
3856 {
3857         const struct cxsr_latency *latency;
3858         int i;
3859
3860         if (fsb == 0 || mem == 0)
3861                 return NULL;
3862
3863         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3864                 latency = &cxsr_latency_table[i];
3865                 if (is_desktop == latency->is_desktop &&
3866                     is_ddr3 == latency->is_ddr3 &&
3867                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3868                         return latency;
3869         }
3870
3871         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3872
3873         return NULL;
3874 }
3875
3876 static void pineview_disable_cxsr(struct drm_device *dev)
3877 {
3878         struct drm_i915_private *dev_priv = dev->dev_private;
3879
3880         /* deactivate cxsr */
3881         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3882 }
3883
3884 /*
3885  * Latency for FIFO fetches is dependent on several factors:
3886  *   - memory configuration (speed, channels)
3887  *   - chipset
3888  *   - current MCH state
3889  * It can be fairly high in some situations, so here we assume a fairly
3890  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3891  * set this value too high, the FIFO will fetch frequently to stay full)
3892  * and power consumption (set it too low to save power and we might see
3893  * FIFO underruns and display "flicker").
3894  *
3895  * A value of 5us seems to be a good balance; safe for very low end
3896  * platforms but not overly aggressive on lower latency configs.
3897  */
3898 static const int latency_ns = 5000;
3899
3900 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3901 {
3902         struct drm_i915_private *dev_priv = dev->dev_private;
3903         uint32_t dsparb = I915_READ(DSPARB);
3904         int size;
3905
3906         size = dsparb & 0x7f;
3907         if (plane)
3908                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3909
3910         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3911                       plane ? "B" : "A", size);
3912
3913         return size;
3914 }
3915
3916 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3917 {
3918         struct drm_i915_private *dev_priv = dev->dev_private;
3919         uint32_t dsparb = I915_READ(DSPARB);
3920         int size;
3921
3922         size = dsparb & 0x1ff;
3923         if (plane)
3924                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3925         size >>= 1; /* Convert to cachelines */
3926
3927         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3928                       plane ? "B" : "A", size);
3929
3930         return size;
3931 }
3932
3933 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3934 {
3935         struct drm_i915_private *dev_priv = dev->dev_private;
3936         uint32_t dsparb = I915_READ(DSPARB);
3937         int size;
3938
3939         size = dsparb & 0x7f;
3940         size >>= 2; /* Convert to cachelines */
3941
3942         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3943                       plane ? "B" : "A",
3944                       size);
3945
3946         return size;
3947 }
3948
3949 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3950 {
3951         struct drm_i915_private *dev_priv = dev->dev_private;
3952         uint32_t dsparb = I915_READ(DSPARB);
3953         int size;
3954
3955         size = dsparb & 0x7f;
3956         size >>= 1; /* Convert to cachelines */
3957
3958         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3959                       plane ? "B" : "A", size);
3960
3961         return size;
3962 }
3963
3964 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3965 {
3966         struct drm_crtc *crtc, *enabled = NULL;
3967
3968         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3969                 if (crtc->enabled && crtc->fb) {
3970                         if (enabled)
3971                                 return NULL;
3972                         enabled = crtc;
3973                 }
3974         }
3975
3976         return enabled;
3977 }
3978
3979 static void pineview_update_wm(struct drm_device *dev)
3980 {
3981         struct drm_i915_private *dev_priv = dev->dev_private;
3982         struct drm_crtc *crtc;
3983         const struct cxsr_latency *latency;
3984         u32 reg;
3985         unsigned long wm;
3986
3987         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3988                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3989         if (!latency) {
3990                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3991                 pineview_disable_cxsr(dev);
3992                 return;
3993         }
3994
3995         crtc = single_enabled_crtc(dev);
3996         if (crtc) {
3997                 int clock = crtc->mode.clock;
3998                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3999
4000                 /* Display SR */
4001                 wm = intel_calculate_wm(clock, &pineview_display_wm,
4002                                         pineview_display_wm.fifo_size,
4003                                         pixel_size, latency->display_sr);
4004                 reg = I915_READ(DSPFW1);
4005                 reg &= ~DSPFW_SR_MASK;
4006                 reg |= wm << DSPFW_SR_SHIFT;
4007                 I915_WRITE(DSPFW1, reg);
4008                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
4009
4010                 /* cursor SR */
4011                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
4012                                         pineview_display_wm.fifo_size,
4013                                         pixel_size, latency->cursor_sr);
4014                 reg = I915_READ(DSPFW3);
4015                 reg &= ~DSPFW_CURSOR_SR_MASK;
4016                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
4017                 I915_WRITE(DSPFW3, reg);
4018
4019                 /* Display HPLL off SR */
4020                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4021                                         pineview_display_hplloff_wm.fifo_size,
4022                                         pixel_size, latency->display_hpll_disable);
4023                 reg = I915_READ(DSPFW3);
4024                 reg &= ~DSPFW_HPLL_SR_MASK;
4025                 reg |= wm & DSPFW_HPLL_SR_MASK;
4026                 I915_WRITE(DSPFW3, reg);
4027
4028                 /* cursor HPLL off SR */
4029                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4030                                         pineview_display_hplloff_wm.fifo_size,
4031                                         pixel_size, latency->cursor_hpll_disable);
4032                 reg = I915_READ(DSPFW3);
4033                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4034                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4035                 I915_WRITE(DSPFW3, reg);
4036                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4037
4038                 /* activate cxsr */
4039                 I915_WRITE(DSPFW3,
4040                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4041                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4042         } else {
4043                 pineview_disable_cxsr(dev);
4044                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4045         }
4046 }
4047
4048 static bool g4x_compute_wm0(struct drm_device *dev,
4049                             int plane,
4050                             const struct intel_watermark_params *display,
4051                             int display_latency_ns,
4052                             const struct intel_watermark_params *cursor,
4053                             int cursor_latency_ns,
4054                             int *plane_wm,
4055                             int *cursor_wm)
4056 {
4057         struct drm_crtc *crtc;
4058         int htotal, hdisplay, clock, pixel_size;
4059         int line_time_us, line_count;
4060         int entries, tlb_miss;
4061
4062         crtc = intel_get_crtc_for_plane(dev, plane);
4063         if (crtc->fb == NULL || !crtc->enabled) {
4064                 *cursor_wm = cursor->guard_size;
4065                 *plane_wm = display->guard_size;
4066                 return false;
4067         }
4068
4069         htotal = crtc->mode.htotal;
4070         hdisplay = crtc->mode.hdisplay;
4071         clock = crtc->mode.clock;
4072         pixel_size = crtc->fb->bits_per_pixel / 8;
4073
4074         /* Use the small buffer method to calculate plane watermark */
4075         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4076         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4077         if (tlb_miss > 0)
4078                 entries += tlb_miss;
4079         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4080         *plane_wm = entries + display->guard_size;
4081         if (*plane_wm > (int)display->max_wm)
4082                 *plane_wm = display->max_wm;
4083
4084         /* Use the large buffer method to calculate cursor watermark */
4085         line_time_us = ((htotal * 1000) / clock);
4086         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4087         entries = line_count * 64 * pixel_size;
4088         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4089         if (tlb_miss > 0)
4090                 entries += tlb_miss;
4091         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4092         *cursor_wm = entries + cursor->guard_size;
4093         if (*cursor_wm > (int)cursor->max_wm)
4094                 *cursor_wm = (int)cursor->max_wm;
4095
4096         return true;
4097 }
4098
4099 /*
4100  * Check the wm result.
4101  *
4102  * If any calculated watermark values is larger than the maximum value that
4103  * can be programmed into the associated watermark register, that watermark
4104  * must be disabled.
4105  */
4106 static bool g4x_check_srwm(struct drm_device *dev,
4107                            int display_wm, int cursor_wm,
4108                            const struct intel_watermark_params *display,
4109                            const struct intel_watermark_params *cursor)
4110 {
4111         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4112                       display_wm, cursor_wm);
4113
4114         if (display_wm > display->max_wm) {
4115                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4116                               display_wm, display->max_wm);
4117                 return false;
4118         }
4119
4120         if (cursor_wm > cursor->max_wm) {
4121                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4122                               cursor_wm, cursor->max_wm);
4123                 return false;
4124         }
4125
4126         if (!(display_wm || cursor_wm)) {
4127                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4128                 return false;
4129         }
4130
4131         return true;
4132 }
4133
4134 static bool g4x_compute_srwm(struct drm_device *dev,
4135                              int plane,
4136                              int latency_ns,
4137                              const struct intel_watermark_params *display,
4138                              const struct intel_watermark_params *cursor,
4139                              int *display_wm, int *cursor_wm)
4140 {
4141         struct drm_crtc *crtc;
4142         int hdisplay, htotal, pixel_size, clock;
4143         unsigned long line_time_us;
4144         int line_count, line_size;
4145         int small, large;
4146         int entries;
4147
4148         if (!latency_ns) {
4149                 *display_wm = *cursor_wm = 0;
4150                 return false;
4151         }
4152
4153         crtc = intel_get_crtc_for_plane(dev, plane);
4154         hdisplay = crtc->mode.hdisplay;
4155         htotal = crtc->mode.htotal;
4156         clock = crtc->mode.clock;
4157         pixel_size = crtc->fb->bits_per_pixel / 8;
4158
4159         line_time_us = (htotal * 1000) / clock;
4160         line_count = (latency_ns / line_time_us + 1000) / 1000;
4161         line_size = hdisplay * pixel_size;
4162
4163         /* Use the minimum of the small and large buffer method for primary */
4164         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4165         large = line_count * line_size;
4166
4167         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4168         *display_wm = entries + display->guard_size;
4169
4170         /* calculate the self-refresh watermark for display cursor */
4171         entries = line_count * pixel_size * 64;
4172         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4173         *cursor_wm = entries + cursor->guard_size;
4174
4175         return g4x_check_srwm(dev,
4176                               *display_wm, *cursor_wm,
4177                               display, cursor);
4178 }
4179
4180 #define single_plane_enabled(mask) is_power_of_2(mask)
4181
4182 static void valleyview_update_wm(struct drm_device *dev)
4183 {
4184         static const int sr_latency_ns = 12000;
4185         struct drm_i915_private *dev_priv = dev->dev_private;
4186         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4187         int plane_sr, cursor_sr;
4188         unsigned int enabled = 0;
4189
4190         if (g4x_compute_wm0(dev, 0,
4191                             &valleyview_wm_info, latency_ns,
4192                             &valleyview_cursor_wm_info, latency_ns,
4193                             &planea_wm, &cursora_wm))
4194                 enabled |= 1;
4195
4196         if (g4x_compute_wm0(dev, 1,
4197                             &valleyview_wm_info, latency_ns,
4198                             &valleyview_cursor_wm_info, latency_ns,
4199                             &planeb_wm, &cursorb_wm))
4200                 enabled |= 2;
4201
4202         plane_sr = cursor_sr = 0;
4203         if (single_plane_enabled(enabled) &&
4204             g4x_compute_srwm(dev, ffs(enabled) - 1,
4205                              sr_latency_ns,
4206                              &valleyview_wm_info,
4207                              &valleyview_cursor_wm_info,
4208                              &plane_sr, &cursor_sr))
4209                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
4210         else
4211                 I915_WRITE(FW_BLC_SELF_VLV,
4212                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
4213
4214         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4215                       planea_wm, cursora_wm,
4216                       planeb_wm, cursorb_wm,
4217                       plane_sr, cursor_sr);
4218
4219         I915_WRITE(DSPFW1,
4220                    (plane_sr << DSPFW_SR_SHIFT) |
4221                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4222                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4223                    planea_wm);
4224         I915_WRITE(DSPFW2,
4225                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4226                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4227         I915_WRITE(DSPFW3,
4228                    (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
4229 }
4230
4231 static void g4x_update_wm(struct drm_device *dev)
4232 {
4233         static const int sr_latency_ns = 12000;
4234         struct drm_i915_private *dev_priv = dev->dev_private;
4235         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4236         int plane_sr, cursor_sr;
4237         unsigned int enabled = 0;
4238
4239         if (g4x_compute_wm0(dev, 0,
4240                             &g4x_wm_info, latency_ns,
4241                             &g4x_cursor_wm_info, latency_ns,
4242                             &planea_wm, &cursora_wm))
4243                 enabled |= 1;
4244
4245         if (g4x_compute_wm0(dev, 1,
4246                             &g4x_wm_info, latency_ns,
4247                             &g4x_cursor_wm_info, latency_ns,
4248                             &planeb_wm, &cursorb_wm))
4249                 enabled |= 2;
4250
4251         plane_sr = cursor_sr = 0;
4252         if (single_plane_enabled(enabled) &&
4253             g4x_compute_srwm(dev, ffs(enabled) - 1,
4254                              sr_latency_ns,
4255                              &g4x_wm_info,
4256                              &g4x_cursor_wm_info,
4257                              &plane_sr, &cursor_sr))
4258                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4259         else
4260                 I915_WRITE(FW_BLC_SELF,
4261                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4262
4263         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4264                       planea_wm, cursora_wm,
4265                       planeb_wm, cursorb_wm,
4266                       plane_sr, cursor_sr);
4267
4268         I915_WRITE(DSPFW1,
4269                    (plane_sr << DSPFW_SR_SHIFT) |
4270                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4271                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4272                    planea_wm);
4273         I915_WRITE(DSPFW2,
4274                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4275                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4276         /* HPLL off in SR has some issues on G4x... disable it */
4277         I915_WRITE(DSPFW3,
4278                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4279                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4280 }
4281
4282 static void i965_update_wm(struct drm_device *dev)
4283 {
4284         struct drm_i915_private *dev_priv = dev->dev_private;
4285         struct drm_crtc *crtc;
4286         int srwm = 1;
4287         int cursor_sr = 16;
4288
4289         /* Calc sr entries for one plane configs */
4290         crtc = single_enabled_crtc(dev);
4291         if (crtc) {
4292                 /* self-refresh has much higher latency */
4293                 static const int sr_latency_ns = 12000;
4294                 int clock = crtc->mode.clock;
4295                 int htotal = crtc->mode.htotal;
4296                 int hdisplay = crtc->mode.hdisplay;
4297                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4298                 unsigned long line_time_us;
4299                 int entries;
4300
4301                 line_time_us = ((htotal * 1000) / clock);
4302
4303                 /* Use ns/us then divide to preserve precision */
4304                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4305                         pixel_size * hdisplay;
4306                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4307                 srwm = I965_FIFO_SIZE - entries;
4308                 if (srwm < 0)
4309                         srwm = 1;
4310                 srwm &= 0x1ff;
4311                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4312                               entries, srwm);
4313
4314                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4315                         pixel_size * 64;
4316                 entries = DIV_ROUND_UP(entries,
4317                                           i965_cursor_wm_info.cacheline_size);
4318                 cursor_sr = i965_cursor_wm_info.fifo_size -
4319                         (entries + i965_cursor_wm_info.guard_size);
4320
4321                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4322                         cursor_sr = i965_cursor_wm_info.max_wm;
4323
4324                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4325                               "cursor %d\n", srwm, cursor_sr);
4326
4327                 if (IS_CRESTLINE(dev))
4328                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4329         } else {
4330                 /* Turn off self refresh if both pipes are enabled */
4331                 if (IS_CRESTLINE(dev))
4332                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4333                                    & ~FW_BLC_SELF_EN);
4334         }
4335
4336         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4337                       srwm);
4338
4339         /* 965 has limitations... */
4340         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4341                    (8 << 16) | (8 << 8) | (8 << 0));
4342         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4343         /* update cursor SR watermark */
4344         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4345 }
4346
4347 static void i9xx_update_wm(struct drm_device *dev)
4348 {
4349         struct drm_i915_private *dev_priv = dev->dev_private;
4350         const struct intel_watermark_params *wm_info;
4351         uint32_t fwater_lo;
4352         uint32_t fwater_hi;
4353         int cwm, srwm = 1;
4354         int fifo_size;
4355         int planea_wm, planeb_wm;
4356         struct drm_crtc *crtc, *enabled = NULL;
4357
4358         if (IS_I945GM(dev))
4359                 wm_info = &i945_wm_info;
4360         else if (!IS_GEN2(dev))
4361                 wm_info = &i915_wm_info;
4362         else
4363                 wm_info = &i855_wm_info;
4364
4365         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4366         crtc = intel_get_crtc_for_plane(dev, 0);
4367         if (crtc->enabled && crtc->fb) {
4368                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4369                                                wm_info, fifo_size,
4370                                                crtc->fb->bits_per_pixel / 8,
4371                                                latency_ns);
4372                 enabled = crtc;
4373         } else
4374                 planea_wm = fifo_size - wm_info->guard_size;
4375
4376         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4377         crtc = intel_get_crtc_for_plane(dev, 1);
4378         if (crtc->enabled && crtc->fb) {
4379                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4380                                                wm_info, fifo_size,
4381                                                crtc->fb->bits_per_pixel / 8,
4382                                                latency_ns);
4383                 if (enabled == NULL)
4384                         enabled = crtc;
4385                 else
4386                         enabled = NULL;
4387         } else
4388                 planeb_wm = fifo_size - wm_info->guard_size;
4389
4390         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4391
4392         /*
4393          * Overlay gets an aggressive default since video jitter is bad.
4394          */
4395         cwm = 2;
4396
4397         /* Play safe and disable self-refresh before adjusting watermarks. */
4398         if (IS_I945G(dev) || IS_I945GM(dev))
4399                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4400         else if (IS_I915GM(dev))
4401                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4402
4403         /* Calc sr entries for one plane configs */
4404         if (HAS_FW_BLC(dev) && enabled) {
4405                 /* self-refresh has much higher latency */
4406                 static const int sr_latency_ns = 6000;
4407                 int clock = enabled->mode.clock;
4408                 int htotal = enabled->mode.htotal;
4409                 int hdisplay = enabled->mode.hdisplay;
4410                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4411                 unsigned long line_time_us;
4412                 int entries;
4413
4414                 line_time_us = (htotal * 1000) / clock;
4415
4416                 /* Use ns/us then divide to preserve precision */
4417                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4418                         pixel_size * hdisplay;
4419                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4420                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4421                 srwm = wm_info->fifo_size - entries;
4422                 if (srwm < 0)
4423                         srwm = 1;
4424
4425                 if (IS_I945G(dev) || IS_I945GM(dev))
4426                         I915_WRITE(FW_BLC_SELF,
4427                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4428                 else if (IS_I915GM(dev))
4429                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4430         }
4431
4432         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4433                       planea_wm, planeb_wm, cwm, srwm);
4434
4435         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4436         fwater_hi = (cwm & 0x1f);
4437
4438         /* Set request length to 8 cachelines per fetch */
4439         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4440         fwater_hi = fwater_hi | (1 << 8);
4441
4442         I915_WRITE(FW_BLC, fwater_lo);
4443         I915_WRITE(FW_BLC2, fwater_hi);
4444
4445         if (HAS_FW_BLC(dev)) {
4446                 if (enabled) {
4447                         if (IS_I945G(dev) || IS_I945GM(dev))
4448                                 I915_WRITE(FW_BLC_SELF,
4449                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4450                         else if (IS_I915GM(dev))
4451                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4452                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4453                 } else
4454                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4455         }
4456 }
4457
4458 static void i830_update_wm(struct drm_device *dev)
4459 {
4460         struct drm_i915_private *dev_priv = dev->dev_private;
4461         struct drm_crtc *crtc;
4462         uint32_t fwater_lo;
4463         int planea_wm;
4464
4465         crtc = single_enabled_crtc(dev);
4466         if (crtc == NULL)
4467                 return;
4468
4469         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4470                                        dev_priv->display.get_fifo_size(dev, 0),
4471                                        crtc->fb->bits_per_pixel / 8,
4472                                        latency_ns);
4473         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4474         fwater_lo |= (3<<8) | planea_wm;
4475
4476         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4477
4478         I915_WRITE(FW_BLC, fwater_lo);
4479 }
4480
4481 #define ILK_LP0_PLANE_LATENCY           700
4482 #define ILK_LP0_CURSOR_LATENCY          1300
4483
4484 /*
4485  * Check the wm result.
4486  *
4487  * If any calculated watermark values is larger than the maximum value that
4488  * can be programmed into the associated watermark register, that watermark
4489  * must be disabled.
4490  */
4491 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4492                                 int fbc_wm, int display_wm, int cursor_wm,
4493                                 const struct intel_watermark_params *display,
4494                                 const struct intel_watermark_params *cursor)
4495 {
4496         struct drm_i915_private *dev_priv = dev->dev_private;
4497
4498         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4499                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4500
4501         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4502                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4503                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4504
4505                 /* fbc has it's own way to disable FBC WM */
4506                 I915_WRITE(DISP_ARB_CTL,
4507                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4508                 return false;
4509         }
4510
4511         if (display_wm > display->max_wm) {
4512                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4513                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4514                 return false;
4515         }
4516
4517         if (cursor_wm > cursor->max_wm) {
4518                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4519                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4520                 return false;
4521         }
4522
4523         if (!(fbc_wm || display_wm || cursor_wm)) {
4524                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4525                 return false;
4526         }
4527
4528         return true;
4529 }
4530
4531 /*
4532  * Compute watermark values of WM[1-3],
4533  */
4534 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4535                                   int latency_ns,
4536                                   const struct intel_watermark_params *display,
4537                                   const struct intel_watermark_params *cursor,
4538                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4539 {
4540         struct drm_crtc *crtc;
4541         unsigned long line_time_us;
4542         int hdisplay, htotal, pixel_size, clock;
4543         int line_count, line_size;
4544         int small, large;
4545         int entries;
4546
4547         if (!latency_ns) {
4548                 *fbc_wm = *display_wm = *cursor_wm = 0;
4549                 return false;
4550         }
4551
4552         crtc = intel_get_crtc_for_plane(dev, plane);
4553         hdisplay = crtc->mode.hdisplay;
4554         htotal = crtc->mode.htotal;
4555         clock = crtc->mode.clock;
4556         pixel_size = crtc->fb->bits_per_pixel / 8;
4557
4558         line_time_us = (htotal * 1000) / clock;
4559         line_count = (latency_ns / line_time_us + 1000) / 1000;
4560         line_size = hdisplay * pixel_size;
4561
4562         /* Use the minimum of the small and large buffer method for primary */
4563         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4564         large = line_count * line_size;
4565
4566         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4567         *display_wm = entries + display->guard_size;
4568
4569         /*
4570          * Spec says:
4571          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4572          */
4573         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4574
4575         /* calculate the self-refresh watermark for display cursor */
4576         entries = line_count * pixel_size * 64;
4577         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4578         *cursor_wm = entries + cursor->guard_size;
4579
4580         return ironlake_check_srwm(dev, level,
4581                                    *fbc_wm, *display_wm, *cursor_wm,
4582                                    display, cursor);
4583 }
4584
4585 static void ironlake_update_wm(struct drm_device *dev)
4586 {
4587         struct drm_i915_private *dev_priv = dev->dev_private;
4588         int fbc_wm, plane_wm, cursor_wm;
4589         unsigned int enabled;
4590
4591         enabled = 0;
4592         if (g4x_compute_wm0(dev, 0,
4593                             &ironlake_display_wm_info,
4594                             ILK_LP0_PLANE_LATENCY,
4595                             &ironlake_cursor_wm_info,
4596                             ILK_LP0_CURSOR_LATENCY,
4597                             &plane_wm, &cursor_wm)) {
4598                 I915_WRITE(WM0_PIPEA_ILK,
4599                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4600                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4601                               " plane %d, " "cursor: %d\n",
4602                               plane_wm, cursor_wm);
4603                 enabled |= 1;
4604         }
4605
4606         if (g4x_compute_wm0(dev, 1,
4607                             &ironlake_display_wm_info,
4608                             ILK_LP0_PLANE_LATENCY,
4609                             &ironlake_cursor_wm_info,
4610                             ILK_LP0_CURSOR_LATENCY,
4611                             &plane_wm, &cursor_wm)) {
4612                 I915_WRITE(WM0_PIPEB_ILK,
4613                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4614                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4615                               " plane %d, cursor: %d\n",
4616                               plane_wm, cursor_wm);
4617                 enabled |= 2;
4618         }
4619
4620         /*
4621          * Calculate and update the self-refresh watermark only when one
4622          * display plane is used.
4623          */
4624         I915_WRITE(WM3_LP_ILK, 0);
4625         I915_WRITE(WM2_LP_ILK, 0);
4626         I915_WRITE(WM1_LP_ILK, 0);
4627
4628         if (!single_plane_enabled(enabled))
4629                 return;
4630         enabled = ffs(enabled) - 1;
4631
4632         /* WM1 */
4633         if (!ironlake_compute_srwm(dev, 1, enabled,
4634                                    ILK_READ_WM1_LATENCY() * 500,
4635                                    &ironlake_display_srwm_info,
4636                                    &ironlake_cursor_srwm_info,
4637                                    &fbc_wm, &plane_wm, &cursor_wm))
4638                 return;
4639
4640         I915_WRITE(WM1_LP_ILK,
4641                    WM1_LP_SR_EN |
4642                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4643                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4644                    (plane_wm << WM1_LP_SR_SHIFT) |
4645                    cursor_wm);
4646
4647         /* WM2 */
4648         if (!ironlake_compute_srwm(dev, 2, enabled,
4649                                    ILK_READ_WM2_LATENCY() * 500,
4650                                    &ironlake_display_srwm_info,
4651                                    &ironlake_cursor_srwm_info,
4652                                    &fbc_wm, &plane_wm, &cursor_wm))
4653                 return;
4654
4655         I915_WRITE(WM2_LP_ILK,
4656                    WM2_LP_EN |
4657                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4658                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4659                    (plane_wm << WM1_LP_SR_SHIFT) |
4660                    cursor_wm);
4661
4662         /*
4663          * WM3 is unsupported on ILK, probably because we don't have latency
4664          * data for that power state
4665          */
4666 }
4667
4668 void sandybridge_update_wm(struct drm_device *dev)
4669 {
4670         struct drm_i915_private *dev_priv = dev->dev_private;
4671         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4672         u32 val;
4673         int fbc_wm, plane_wm, cursor_wm;
4674         unsigned int enabled;
4675
4676         enabled = 0;
4677         if (g4x_compute_wm0(dev, 0,
4678                             &sandybridge_display_wm_info, latency,
4679                             &sandybridge_cursor_wm_info, latency,
4680                             &plane_wm, &cursor_wm)) {
4681                 val = I915_READ(WM0_PIPEA_ILK);
4682                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4683                 I915_WRITE(WM0_PIPEA_ILK, val |
4684                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4685                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4686                               " plane %d, " "cursor: %d\n",
4687                               plane_wm, cursor_wm);
4688                 enabled |= 1;
4689         }
4690
4691         if (g4x_compute_wm0(dev, 1,
4692                             &sandybridge_display_wm_info, latency,
4693                             &sandybridge_cursor_wm_info, latency,
4694                             &plane_wm, &cursor_wm)) {
4695                 val = I915_READ(WM0_PIPEB_ILK);
4696                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4697                 I915_WRITE(WM0_PIPEB_ILK, val |
4698                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4699                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4700                               " plane %d, cursor: %d\n",
4701                               plane_wm, cursor_wm);
4702                 enabled |= 2;
4703         }
4704
4705         /* IVB has 3 pipes */
4706         if (IS_IVYBRIDGE(dev) &&
4707             g4x_compute_wm0(dev, 2,
4708                             &sandybridge_display_wm_info, latency,
4709                             &sandybridge_cursor_wm_info, latency,
4710                             &plane_wm, &cursor_wm)) {
4711                 val = I915_READ(WM0_PIPEC_IVB);
4712                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4713                 I915_WRITE(WM0_PIPEC_IVB, val |
4714                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4715                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4716                               " plane %d, cursor: %d\n",
4717                               plane_wm, cursor_wm);
4718                 enabled |= 3;
4719         }
4720
4721         /*
4722          * Calculate and update the self-refresh watermark only when one
4723          * display plane is used.
4724          *
4725          * SNB support 3 levels of watermark.
4726          *
4727          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4728          * and disabled in the descending order
4729          *
4730          */
4731         I915_WRITE(WM3_LP_ILK, 0);
4732         I915_WRITE(WM2_LP_ILK, 0);
4733         I915_WRITE(WM1_LP_ILK, 0);
4734
4735         if (!single_plane_enabled(enabled) ||
4736             dev_priv->sprite_scaling_enabled)
4737                 return;
4738         enabled = ffs(enabled) - 1;
4739
4740         /* WM1 */
4741         if (!ironlake_compute_srwm(dev, 1, enabled,
4742                                    SNB_READ_WM1_LATENCY() * 500,
4743                                    &sandybridge_display_srwm_info,
4744                                    &sandybridge_cursor_srwm_info,
4745                                    &fbc_wm, &plane_wm, &cursor_wm))
4746                 return;
4747
4748         I915_WRITE(WM1_LP_ILK,
4749                    WM1_LP_SR_EN |
4750                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4751                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4752                    (plane_wm << WM1_LP_SR_SHIFT) |
4753                    cursor_wm);
4754
4755         /* WM2 */
4756         if (!ironlake_compute_srwm(dev, 2, enabled,
4757                                    SNB_READ_WM2_LATENCY() * 500,
4758                                    &sandybridge_display_srwm_info,
4759                                    &sandybridge_cursor_srwm_info,
4760                                    &fbc_wm, &plane_wm, &cursor_wm))
4761                 return;
4762
4763         I915_WRITE(WM2_LP_ILK,
4764                    WM2_LP_EN |
4765                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4766                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4767                    (plane_wm << WM1_LP_SR_SHIFT) |
4768                    cursor_wm);
4769
4770         /* WM3 */
4771         if (!ironlake_compute_srwm(dev, 3, enabled,
4772                                    SNB_READ_WM3_LATENCY() * 500,
4773                                    &sandybridge_display_srwm_info,
4774                                    &sandybridge_cursor_srwm_info,
4775                                    &fbc_wm, &plane_wm, &cursor_wm))
4776                 return;
4777
4778         I915_WRITE(WM3_LP_ILK,
4779                    WM3_LP_EN |
4780                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4781                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4782                    (plane_wm << WM1_LP_SR_SHIFT) |
4783                    cursor_wm);
4784 }
4785
4786 static bool
4787 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4788                               uint32_t sprite_width, int pixel_size,
4789                               const struct intel_watermark_params *display,
4790                               int display_latency_ns, int *sprite_wm)
4791 {
4792         struct drm_crtc *crtc;
4793         int clock;
4794         int entries, tlb_miss;
4795
4796         crtc = intel_get_crtc_for_plane(dev, plane);
4797         if (crtc->fb == NULL || !crtc->enabled) {
4798                 *sprite_wm = display->guard_size;
4799                 return false;
4800         }
4801
4802         clock = crtc->mode.clock;
4803
4804         /* Use the small buffer method to calculate the sprite watermark */
4805         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4806         tlb_miss = display->fifo_size*display->cacheline_size -
4807                 sprite_width * 8;
4808         if (tlb_miss > 0)
4809                 entries += tlb_miss;
4810         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4811         *sprite_wm = entries + display->guard_size;
4812         if (*sprite_wm > (int)display->max_wm)
4813                 *sprite_wm = display->max_wm;
4814
4815         return true;
4816 }
4817
4818 static bool
4819 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4820                                 uint32_t sprite_width, int pixel_size,
4821                                 const struct intel_watermark_params *display,
4822                                 int latency_ns, int *sprite_wm)
4823 {
4824         struct drm_crtc *crtc;
4825         unsigned long line_time_us;
4826         int clock;
4827         int line_count, line_size;
4828         int small, large;
4829         int entries;
4830
4831         if (!latency_ns) {
4832                 *sprite_wm = 0;
4833                 return false;
4834         }
4835
4836         crtc = intel_get_crtc_for_plane(dev, plane);
4837         clock = crtc->mode.clock;
4838
4839         line_time_us = (sprite_width * 1000) / clock;
4840         line_count = (latency_ns / line_time_us + 1000) / 1000;
4841         line_size = sprite_width * pixel_size;
4842
4843         /* Use the minimum of the small and large buffer method for primary */
4844         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4845         large = line_count * line_size;
4846
4847         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4848         *sprite_wm = entries + display->guard_size;
4849
4850         return *sprite_wm > 0x3ff ? false : true;
4851 }
4852
4853 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4854                                          uint32_t sprite_width, int pixel_size)
4855 {
4856         struct drm_i915_private *dev_priv = dev->dev_private;
4857         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4858         u32 val;
4859         int sprite_wm, reg;
4860         int ret;
4861
4862         switch (pipe) {
4863         case 0:
4864                 reg = WM0_PIPEA_ILK;
4865                 break;
4866         case 1:
4867                 reg = WM0_PIPEB_ILK;
4868                 break;
4869         case 2:
4870                 reg = WM0_PIPEC_IVB;
4871                 break;
4872         default:
4873                 return; /* bad pipe */
4874         }
4875
4876         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4877                                             &sandybridge_display_wm_info,
4878                                             latency, &sprite_wm);
4879         if (!ret) {
4880                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4881                               pipe);
4882                 return;
4883         }
4884
4885         val = I915_READ(reg);
4886         val &= ~WM0_PIPE_SPRITE_MASK;
4887         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4888         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4889
4890
4891         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4892                                               pixel_size,
4893                                               &sandybridge_display_srwm_info,
4894                                               SNB_READ_WM1_LATENCY() * 500,
4895                                               &sprite_wm);
4896         if (!ret) {
4897                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4898                               pipe);
4899                 return;
4900         }
4901         I915_WRITE(WM1S_LP_ILK, sprite_wm);
4902
4903         /* Only IVB has two more LP watermarks for sprite */
4904         if (!IS_IVYBRIDGE(dev))
4905                 return;
4906
4907         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4908                                               pixel_size,
4909                                               &sandybridge_display_srwm_info,
4910                                               SNB_READ_WM2_LATENCY() * 500,
4911                                               &sprite_wm);
4912         if (!ret) {
4913                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4914                               pipe);
4915                 return;
4916         }
4917         I915_WRITE(WM2S_LP_IVB, sprite_wm);
4918
4919         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4920                                               pixel_size,
4921                                               &sandybridge_display_srwm_info,
4922                                               SNB_READ_WM3_LATENCY() * 500,
4923                                               &sprite_wm);
4924         if (!ret) {
4925                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4926                               pipe);
4927                 return;
4928         }
4929         I915_WRITE(WM3S_LP_IVB, sprite_wm);
4930 }
4931
4932 /**
4933  * intel_update_watermarks - update FIFO watermark values based on current modes
4934  *
4935  * Calculate watermark values for the various WM regs based on current mode
4936  * and plane configuration.
4937  *
4938  * There are several cases to deal with here:
4939  *   - normal (i.e. non-self-refresh)
4940  *   - self-refresh (SR) mode
4941  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4942  *   - lines are small relative to FIFO size (buffer can hold more than 2
4943  *     lines), so need to account for TLB latency
4944  *
4945  *   The normal calculation is:
4946  *     watermark = dotclock * bytes per pixel * latency
4947  *   where latency is platform & configuration dependent (we assume pessimal
4948  *   values here).
4949  *
4950  *   The SR calculation is:
4951  *     watermark = (trunc(latency/line time)+1) * surface width *
4952  *       bytes per pixel
4953  *   where
4954  *     line time = htotal / dotclock
4955  *     surface width = hdisplay for normal plane and 64 for cursor
4956  *   and latency is assumed to be high, as above.
4957  *
4958  * The final value programmed to the register should always be rounded up,
4959  * and include an extra 2 entries to account for clock crossings.
4960  *
4961  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4962  * to set the non-SR watermarks to 8.
4963  */
4964 static void intel_update_watermarks(struct drm_device *dev)
4965 {
4966         struct drm_i915_private *dev_priv = dev->dev_private;
4967
4968         if (dev_priv->display.update_wm)
4969                 dev_priv->display.update_wm(dev);
4970 }
4971
4972 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4973                                     uint32_t sprite_width, int pixel_size)
4974 {
4975         struct drm_i915_private *dev_priv = dev->dev_private;
4976
4977         if (dev_priv->display.update_sprite_wm)
4978                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4979                                                    pixel_size);
4980 }
4981
4982 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4983 {
4984         if (i915_panel_use_ssc >= 0)
4985                 return i915_panel_use_ssc != 0;
4986         return dev_priv->lvds_use_ssc
4987                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4988 }
4989
4990 /**
4991  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4992  * @crtc: CRTC structure
4993  * @mode: requested mode
4994  *
4995  * A pipe may be connected to one or more outputs.  Based on the depth of the
4996  * attached framebuffer, choose a good color depth to use on the pipe.
4997  *
4998  * If possible, match the pipe depth to the fb depth.  In some cases, this
4999  * isn't ideal, because the connected output supports a lesser or restricted
5000  * set of depths.  Resolve that here:
5001  *    LVDS typically supports only 6bpc, so clamp down in that case
5002  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
5003  *    Displays may support a restricted set as well, check EDID and clamp as
5004  *      appropriate.
5005  *    DP may want to dither down to 6bpc to fit larger modes
5006  *
5007  * RETURNS:
5008  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
5009  * true if they don't match).
5010  */
5011 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
5012                                          unsigned int *pipe_bpp,
5013                                          struct drm_display_mode *mode)
5014 {
5015         struct drm_device *dev = crtc->dev;
5016         struct drm_i915_private *dev_priv = dev->dev_private;
5017         struct drm_encoder *encoder;
5018         struct drm_connector *connector;
5019         unsigned int display_bpc = UINT_MAX, bpc;
5020
5021         /* Walk the encoders & connectors on this crtc, get min bpc */
5022         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5023                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5024
5025                 if (encoder->crtc != crtc)
5026                         continue;
5027
5028                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
5029                         unsigned int lvds_bpc;
5030
5031                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
5032                             LVDS_A3_POWER_UP)
5033                                 lvds_bpc = 8;
5034                         else
5035                                 lvds_bpc = 6;
5036
5037                         if (lvds_bpc < display_bpc) {
5038                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5039                                 display_bpc = lvds_bpc;
5040                         }
5041                         continue;
5042                 }
5043
5044                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
5045                         /* Use VBT settings if we have an eDP panel */
5046                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
5047
5048                         if (edp_bpc < display_bpc) {
5049                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5050                                 display_bpc = edp_bpc;
5051                         }
5052                         continue;
5053                 }
5054
5055                 /* Not one of the known troublemakers, check the EDID */
5056                 list_for_each_entry(connector, &dev->mode_config.connector_list,
5057                                     head) {
5058                         if (connector->encoder != encoder)
5059                                 continue;
5060
5061                         /* Don't use an invalid EDID bpc value */
5062                         if (connector->display_info.bpc &&
5063                             connector->display_info.bpc < display_bpc) {
5064                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5065                                 display_bpc = connector->display_info.bpc;
5066                         }
5067                 }
5068
5069                 /*
5070                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5071                  * through, clamp it down.  (Note: >12bpc will be caught below.)
5072                  */
5073                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5074                         if (display_bpc > 8 && display_bpc < 12) {
5075                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5076                                 display_bpc = 12;
5077                         } else {
5078                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5079                                 display_bpc = 8;
5080                         }
5081                 }
5082         }
5083
5084         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5085                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5086                 display_bpc = 6;
5087         }
5088
5089         /*
5090          * We could just drive the pipe at the highest bpc all the time and
5091          * enable dithering as needed, but that costs bandwidth.  So choose
5092          * the minimum value that expresses the full color range of the fb but
5093          * also stays within the max display bpc discovered above.
5094          */
5095
5096         switch (crtc->fb->depth) {
5097         case 8:
5098                 bpc = 8; /* since we go through a colormap */
5099                 break;
5100         case 15:
5101         case 16:
5102                 bpc = 6; /* min is 18bpp */
5103                 break;
5104         case 24:
5105                 bpc = 8;
5106                 break;
5107         case 30:
5108                 bpc = 10;
5109                 break;
5110         case 48:
5111                 bpc = 12;
5112                 break;
5113         default:
5114                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5115                 bpc = min((unsigned int)8, display_bpc);
5116                 break;
5117         }
5118
5119         display_bpc = min(display_bpc, bpc);
5120
5121         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5122                       bpc, display_bpc);
5123
5124         *pipe_bpp = display_bpc * 3;
5125
5126         return display_bpc != bpc;
5127 }
5128
5129 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5130 {
5131         struct drm_device *dev = crtc->dev;
5132         struct drm_i915_private *dev_priv = dev->dev_private;
5133         int refclk;
5134
5135         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5136             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5137                 refclk = dev_priv->lvds_ssc_freq * 1000;
5138                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5139                               refclk / 1000);
5140         } else if (!IS_GEN2(dev)) {
5141                 refclk = 96000;
5142         } else {
5143                 refclk = 48000;
5144         }
5145
5146         return refclk;
5147 }
5148
5149 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5150                                       intel_clock_t *clock)
5151 {
5152         /* SDVO TV has fixed PLL values depend on its clock range,
5153            this mirrors vbios setting. */
5154         if (adjusted_mode->clock >= 100000
5155             && adjusted_mode->clock < 140500) {
5156                 clock->p1 = 2;
5157                 clock->p2 = 10;
5158                 clock->n = 3;
5159                 clock->m1 = 16;
5160                 clock->m2 = 8;
5161         } else if (adjusted_mode->clock >= 140500
5162                    && adjusted_mode->clock <= 200000) {
5163                 clock->p1 = 1;
5164                 clock->p2 = 10;
5165                 clock->n = 6;
5166                 clock->m1 = 12;
5167                 clock->m2 = 8;
5168         }
5169 }
5170
5171 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5172                                      intel_clock_t *clock,
5173                                      intel_clock_t *reduced_clock)
5174 {
5175         struct drm_device *dev = crtc->dev;
5176         struct drm_i915_private *dev_priv = dev->dev_private;
5177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5178         int pipe = intel_crtc->pipe;
5179         u32 fp, fp2 = 0;
5180
5181         if (IS_PINEVIEW(dev)) {
5182                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5183                 if (reduced_clock)
5184                         fp2 = (1 << reduced_clock->n) << 16 |
5185                                 reduced_clock->m1 << 8 | reduced_clock->m2;
5186         } else {
5187                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5188                 if (reduced_clock)
5189                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5190                                 reduced_clock->m2;
5191         }
5192
5193         I915_WRITE(FP0(pipe), fp);
5194
5195         intel_crtc->lowfreq_avail = false;
5196         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5197             reduced_clock && i915_powersave) {
5198                 I915_WRITE(FP1(pipe), fp2);
5199                 intel_crtc->lowfreq_avail = true;
5200         } else {
5201                 I915_WRITE(FP1(pipe), fp);
5202         }
5203 }
5204
5205 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
5206                               struct drm_display_mode *adjusted_mode)
5207 {
5208         struct drm_device *dev = crtc->dev;
5209         struct drm_i915_private *dev_priv = dev->dev_private;
5210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5211         int pipe = intel_crtc->pipe;
5212         u32 temp, lvds_sync = 0;
5213
5214         temp = I915_READ(LVDS);
5215         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5216         if (pipe == 1) {
5217                 temp |= LVDS_PIPEB_SELECT;
5218         } else {
5219                 temp &= ~LVDS_PIPEB_SELECT;
5220         }
5221         /* set the corresponsding LVDS_BORDER bit */
5222         temp |= dev_priv->lvds_border_bits;
5223         /* Set the B0-B3 data pairs corresponding to whether we're going to
5224          * set the DPLLs for dual-channel mode or not.
5225          */
5226         if (clock->p2 == 7)
5227                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5228         else
5229                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5230
5231         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5232          * appropriately here, but we need to look more thoroughly into how
5233          * panels behave in the two modes.
5234          */
5235         /* set the dithering flag on LVDS as needed */
5236         if (INTEL_INFO(dev)->gen >= 4) {
5237                 if (dev_priv->lvds_dither)
5238                         temp |= LVDS_ENABLE_DITHER;
5239                 else
5240                         temp &= ~LVDS_ENABLE_DITHER;
5241         }
5242         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5243                 lvds_sync |= LVDS_HSYNC_POLARITY;
5244         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5245                 lvds_sync |= LVDS_VSYNC_POLARITY;
5246         if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5247             != lvds_sync) {
5248                 char flags[2] = "-+";
5249                 DRM_INFO("Changing LVDS panel from "
5250                          "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5251                          flags[!(temp & LVDS_HSYNC_POLARITY)],
5252                          flags[!(temp & LVDS_VSYNC_POLARITY)],
5253                          flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5254                          flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5255                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5256                 temp |= lvds_sync;
5257         }
5258         I915_WRITE(LVDS, temp);
5259 }
5260
5261 static void i9xx_update_pll(struct drm_crtc *crtc,
5262                             struct drm_display_mode *mode,
5263                             struct drm_display_mode *adjusted_mode,
5264                             intel_clock_t *clock, intel_clock_t *reduced_clock,
5265                             int num_connectors)
5266 {
5267         struct drm_device *dev = crtc->dev;
5268         struct drm_i915_private *dev_priv = dev->dev_private;
5269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5270         int pipe = intel_crtc->pipe;
5271         u32 dpll;
5272         bool is_sdvo;
5273
5274         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
5275                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
5276
5277         dpll = DPLL_VGA_MODE_DIS;
5278
5279         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5280                 dpll |= DPLLB_MODE_LVDS;
5281         else
5282                 dpll |= DPLLB_MODE_DAC_SERIAL;
5283         if (is_sdvo) {
5284                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5285                 if (pixel_multiplier > 1) {
5286                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5287                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5288                 }
5289                 dpll |= DPLL_DVO_HIGH_SPEED;
5290         }
5291         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5292                 dpll |= DPLL_DVO_HIGH_SPEED;
5293
5294         /* compute bitmask from p1 value */
5295         if (IS_PINEVIEW(dev))
5296                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5297         else {
5298                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5299                 if (IS_G4X(dev) && reduced_clock)
5300                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5301         }
5302         switch (clock->p2) {
5303         case 5:
5304                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5305                 break;
5306         case 7:
5307                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5308                 break;
5309         case 10:
5310                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5311                 break;
5312         case 14:
5313                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5314                 break;
5315         }
5316         if (INTEL_INFO(dev)->gen >= 4)
5317                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5318
5319         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5320                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5321         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5322                 /* XXX: just matching BIOS for now */
5323                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5324                 dpll |= 3;
5325         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5326                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5327                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5328         else
5329                 dpll |= PLL_REF_INPUT_DREFCLK;
5330
5331         dpll |= DPLL_VCO_ENABLE;
5332         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5333         POSTING_READ(DPLL(pipe));
5334         udelay(150);
5335
5336         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5337          * This is an exception to the general rule that mode_set doesn't turn
5338          * things on.
5339          */
5340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5341                 intel_update_lvds(crtc, clock, adjusted_mode);
5342
5343         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5344                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5345
5346         I915_WRITE(DPLL(pipe), dpll);
5347
5348         /* Wait for the clocks to stabilize. */
5349         POSTING_READ(DPLL(pipe));
5350         udelay(150);
5351
5352         if (INTEL_INFO(dev)->gen >= 4) {
5353                 u32 temp = 0;
5354                 if (is_sdvo) {
5355                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5356                         if (temp > 1)
5357                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5358                         else
5359                                 temp = 0;
5360                 }
5361                 I915_WRITE(DPLL_MD(pipe), temp);
5362         } else {
5363                 /* The pixel multiplier can only be updated once the
5364                  * DPLL is enabled and the clocks are stable.
5365                  *
5366                  * So write it again.
5367                  */
5368                 I915_WRITE(DPLL(pipe), dpll);
5369         }
5370 }
5371
5372 static void i8xx_update_pll(struct drm_crtc *crtc,
5373                             struct drm_display_mode *adjusted_mode,
5374                             intel_clock_t *clock,
5375                             int num_connectors)
5376 {
5377         struct drm_device *dev = crtc->dev;
5378         struct drm_i915_private *dev_priv = dev->dev_private;
5379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5380         int pipe = intel_crtc->pipe;
5381         u32 dpll;
5382
5383         dpll = DPLL_VGA_MODE_DIS;
5384
5385         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
5386                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5387         } else {
5388                 if (clock->p1 == 2)
5389                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5390                 else
5391                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5392                 if (clock->p2 == 4)
5393                         dpll |= PLL_P2_DIVIDE_BY_4;
5394         }
5395
5396         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5397                 /* XXX: just matching BIOS for now */
5398                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5399                 dpll |= 3;
5400         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5401                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5402                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5403         else
5404                 dpll |= PLL_REF_INPUT_DREFCLK;
5405
5406         dpll |= DPLL_VCO_ENABLE;
5407         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5408         POSTING_READ(DPLL(pipe));
5409         udelay(150);
5410
5411         I915_WRITE(DPLL(pipe), dpll);
5412
5413         /* Wait for the clocks to stabilize. */
5414         POSTING_READ(DPLL(pipe));
5415         udelay(150);
5416
5417         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5418          * This is an exception to the general rule that mode_set doesn't turn
5419          * things on.
5420          */
5421         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5422                 intel_update_lvds(crtc, clock, adjusted_mode);
5423
5424         /* The pixel multiplier can only be updated once the
5425          * DPLL is enabled and the clocks are stable.
5426          *
5427          * So write it again.
5428          */
5429         I915_WRITE(DPLL(pipe), dpll);
5430 }
5431
5432 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5433                               struct drm_display_mode *mode,
5434                               struct drm_display_mode *adjusted_mode,
5435                               int x, int y,
5436                               struct drm_framebuffer *old_fb)
5437 {
5438         struct drm_device *dev = crtc->dev;
5439         struct drm_i915_private *dev_priv = dev->dev_private;
5440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5441         int pipe = intel_crtc->pipe;
5442         int plane = intel_crtc->plane;
5443         int refclk, num_connectors = 0;
5444         intel_clock_t clock, reduced_clock;
5445         u32 dspcntr, pipeconf, vsyncshift;
5446         bool ok, has_reduced_clock = false, is_sdvo = false;
5447         bool is_lvds = false, is_tv = false, is_dp = false;
5448         struct drm_mode_config *mode_config = &dev->mode_config;
5449         struct intel_encoder *encoder;
5450         const intel_limit_t *limit;
5451         int ret;
5452
5453         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5454                 if (encoder->base.crtc != crtc)
5455                         continue;
5456
5457                 switch (encoder->type) {
5458                 case INTEL_OUTPUT_LVDS:
5459                         is_lvds = true;
5460                         break;
5461                 case INTEL_OUTPUT_SDVO:
5462                 case INTEL_OUTPUT_HDMI:
5463                         is_sdvo = true;
5464                         if (encoder->needs_tv_clock)
5465                                 is_tv = true;
5466                         break;
5467                 case INTEL_OUTPUT_TVOUT:
5468                         is_tv = true;
5469                         break;
5470                 case INTEL_OUTPUT_DISPLAYPORT:
5471                         is_dp = true;
5472                         break;
5473                 }
5474
5475                 num_connectors++;
5476         }
5477
5478         refclk = i9xx_get_refclk(crtc, num_connectors);
5479
5480         /*
5481          * Returns a set of divisors for the desired target clock with the given
5482          * refclk, or FALSE.  The returned values represent the clock equation:
5483          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5484          */
5485         limit = intel_limit(crtc, refclk);
5486         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5487                              &clock);
5488         if (!ok) {
5489                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5490                 return -EINVAL;
5491         }
5492
5493         /* Ensure that the cursor is valid for the new mode before changing... */
5494         intel_crtc_update_cursor(crtc, true);
5495
5496         if (is_lvds && dev_priv->lvds_downclock_avail) {
5497                 /*
5498                  * Ensure we match the reduced clock's P to the target clock.
5499                  * If the clocks don't match, we can't switch the display clock
5500                  * by using the FP0/FP1. In such case we will disable the LVDS
5501                  * downclock feature.
5502                 */
5503                 has_reduced_clock = limit->find_pll(limit, crtc,
5504                                                     dev_priv->lvds_downclock,
5505                                                     refclk,
5506                                                     &clock,
5507                                                     &reduced_clock);
5508         }
5509
5510         if (is_sdvo && is_tv)
5511                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5512
5513         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5514                                  &reduced_clock : NULL);
5515
5516         if (IS_GEN2(dev))
5517                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
5518         else
5519                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
5520                                 has_reduced_clock ? &reduced_clock : NULL,
5521                                 num_connectors);
5522
5523         /* setup pipeconf */
5524         pipeconf = I915_READ(PIPECONF(pipe));
5525
5526         /* Set up the display plane register */
5527         dspcntr = DISPPLANE_GAMMA_ENABLE;
5528
5529         if (pipe == 0)
5530                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5531         else
5532                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5533
5534         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5535                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5536                  * core speed.
5537                  *
5538                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5539                  * pipe == 0 check?
5540                  */
5541                 if (mode->clock >
5542                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5543                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5544                 else
5545                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5546         }
5547
5548         /* default to 8bpc */
5549         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5550         if (is_dp) {
5551                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5552                         pipeconf |= PIPECONF_BPP_6 |
5553                                     PIPECONF_DITHER_EN |
5554                                     PIPECONF_DITHER_TYPE_SP;
5555                 }
5556         }
5557
5558         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5559         drm_mode_debug_printmodeline(mode);
5560
5561         if (HAS_PIPE_CXSR(dev)) {
5562                 if (intel_crtc->lowfreq_avail) {
5563                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5564                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5565                 } else {
5566                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5567                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5568                 }
5569         }
5570
5571         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5572         if (!IS_GEN2(dev) &&
5573             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5574                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5575                 /* the chip adds 2 halflines automatically */
5576                 adjusted_mode->crtc_vtotal -= 1;
5577                 adjusted_mode->crtc_vblank_end -= 1;
5578                 vsyncshift = adjusted_mode->crtc_hsync_start
5579                              - adjusted_mode->crtc_htotal/2;
5580         } else {
5581                 pipeconf |= PIPECONF_PROGRESSIVE;
5582                 vsyncshift = 0;
5583         }
5584
5585         if (!IS_GEN3(dev))
5586                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5587
5588         I915_WRITE(HTOTAL(pipe),
5589                    (adjusted_mode->crtc_hdisplay - 1) |
5590                    ((adjusted_mode->crtc_htotal - 1) << 16));
5591         I915_WRITE(HBLANK(pipe),
5592                    (adjusted_mode->crtc_hblank_start - 1) |
5593                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5594         I915_WRITE(HSYNC(pipe),
5595                    (adjusted_mode->crtc_hsync_start - 1) |
5596                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5597
5598         I915_WRITE(VTOTAL(pipe),
5599                    (adjusted_mode->crtc_vdisplay - 1) |
5600                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5601         I915_WRITE(VBLANK(pipe),
5602                    (adjusted_mode->crtc_vblank_start - 1) |
5603                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5604         I915_WRITE(VSYNC(pipe),
5605                    (adjusted_mode->crtc_vsync_start - 1) |
5606                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5607
5608         /* pipesrc and dspsize control the size that is scaled from,
5609          * which should always be the user's requested size.
5610          */
5611         I915_WRITE(DSPSIZE(plane),
5612                    ((mode->vdisplay - 1) << 16) |
5613                    (mode->hdisplay - 1));
5614         I915_WRITE(DSPPOS(plane), 0);
5615         I915_WRITE(PIPESRC(pipe),
5616                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5617
5618         I915_WRITE(PIPECONF(pipe), pipeconf);
5619         POSTING_READ(PIPECONF(pipe));
5620         intel_enable_pipe(dev_priv, pipe, false);
5621
5622         intel_wait_for_vblank(dev, pipe);
5623
5624         I915_WRITE(DSPCNTR(plane), dspcntr);
5625         POSTING_READ(DSPCNTR(plane));
5626         intel_enable_plane(dev_priv, plane, pipe);
5627
5628         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5629
5630         intel_update_watermarks(dev);
5631
5632         return ret;
5633 }
5634
5635 /*
5636  * Initialize reference clocks when the driver loads
5637  */
5638 void ironlake_init_pch_refclk(struct drm_device *dev)
5639 {
5640         struct drm_i915_private *dev_priv = dev->dev_private;
5641         struct drm_mode_config *mode_config = &dev->mode_config;
5642         struct intel_encoder *encoder;
5643         u32 temp;
5644         bool has_lvds = false;
5645         bool has_cpu_edp = false;
5646         bool has_pch_edp = false;
5647         bool has_panel = false;
5648         bool has_ck505 = false;
5649         bool can_ssc = false;
5650
5651         /* We need to take the global config into account */
5652         list_for_each_entry(encoder, &mode_config->encoder_list,
5653                             base.head) {
5654                 switch (encoder->type) {
5655                 case INTEL_OUTPUT_LVDS:
5656                         has_panel = true;
5657                         has_lvds = true;
5658                         break;
5659                 case INTEL_OUTPUT_EDP:
5660                         has_panel = true;
5661                         if (intel_encoder_is_pch_edp(&encoder->base))
5662                                 has_pch_edp = true;
5663                         else
5664                                 has_cpu_edp = true;
5665                         break;
5666                 }
5667         }
5668
5669         if (HAS_PCH_IBX(dev)) {
5670                 has_ck505 = dev_priv->display_clock_mode;
5671                 can_ssc = has_ck505;
5672         } else {
5673                 has_ck505 = false;
5674                 can_ssc = true;
5675         }
5676
5677         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5678                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5679                       has_ck505);
5680
5681         /* Ironlake: try to setup display ref clock before DPLL
5682          * enabling. This is only under driver's control after
5683          * PCH B stepping, previous chipset stepping should be
5684          * ignoring this setting.
5685          */
5686         temp = I915_READ(PCH_DREF_CONTROL);
5687         /* Always enable nonspread source */
5688         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5689
5690         if (has_ck505)
5691                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5692         else
5693                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5694
5695         if (has_panel) {
5696                 temp &= ~DREF_SSC_SOURCE_MASK;
5697                 temp |= DREF_SSC_SOURCE_ENABLE;
5698
5699                 /* SSC must be turned on before enabling the CPU output  */
5700                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5701                         DRM_DEBUG_KMS("Using SSC on panel\n");
5702                         temp |= DREF_SSC1_ENABLE;
5703                 }
5704
5705                 /* Get SSC going before enabling the outputs */
5706                 I915_WRITE(PCH_DREF_CONTROL, temp);
5707                 POSTING_READ(PCH_DREF_CONTROL);
5708                 udelay(200);
5709
5710                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5711
5712                 /* Enable CPU source on CPU attached eDP */
5713                 if (has_cpu_edp) {
5714                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5715                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5716                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5717                         }
5718                         else
5719                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5720                 } else
5721                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5722
5723                 I915_WRITE(PCH_DREF_CONTROL, temp);
5724                 POSTING_READ(PCH_DREF_CONTROL);
5725                 udelay(200);
5726         } else {
5727                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5728
5729                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5730
5731                 /* Turn off CPU output */
5732                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5733
5734                 I915_WRITE(PCH_DREF_CONTROL, temp);
5735                 POSTING_READ(PCH_DREF_CONTROL);
5736                 udelay(200);
5737
5738                 /* Turn off the SSC source */
5739                 temp &= ~DREF_SSC_SOURCE_MASK;
5740                 temp |= DREF_SSC_SOURCE_DISABLE;
5741
5742                 /* Turn off SSC1 */
5743                 temp &= ~ DREF_SSC1_ENABLE;
5744
5745                 I915_WRITE(PCH_DREF_CONTROL, temp);
5746                 POSTING_READ(PCH_DREF_CONTROL);
5747                 udelay(200);
5748         }
5749 }
5750
5751 static int ironlake_get_refclk(struct drm_crtc *crtc)
5752 {
5753         struct drm_device *dev = crtc->dev;
5754         struct drm_i915_private *dev_priv = dev->dev_private;
5755         struct intel_encoder *encoder;
5756         struct drm_mode_config *mode_config = &dev->mode_config;
5757         struct intel_encoder *edp_encoder = NULL;
5758         int num_connectors = 0;
5759         bool is_lvds = false;
5760
5761         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5762                 if (encoder->base.crtc != crtc)
5763                         continue;
5764
5765                 switch (encoder->type) {
5766                 case INTEL_OUTPUT_LVDS:
5767                         is_lvds = true;
5768                         break;
5769                 case INTEL_OUTPUT_EDP:
5770                         edp_encoder = encoder;
5771                         break;
5772                 }
5773                 num_connectors++;
5774         }
5775
5776         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5777                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5778                               dev_priv->lvds_ssc_freq);
5779                 return dev_priv->lvds_ssc_freq * 1000;
5780         }
5781
5782         return 120000;
5783 }
5784
5785 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5786                                   struct drm_display_mode *mode,
5787                                   struct drm_display_mode *adjusted_mode,
5788                                   int x, int y,
5789                                   struct drm_framebuffer *old_fb)
5790 {
5791         struct drm_device *dev = crtc->dev;
5792         struct drm_i915_private *dev_priv = dev->dev_private;
5793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5794         int pipe = intel_crtc->pipe;
5795         int plane = intel_crtc->plane;
5796         int refclk, num_connectors = 0;
5797         intel_clock_t clock, reduced_clock;
5798         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5799         bool ok, has_reduced_clock = false, is_sdvo = false;
5800         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5801         struct intel_encoder *has_edp_encoder = NULL;
5802         struct drm_mode_config *mode_config = &dev->mode_config;
5803         struct intel_encoder *encoder;
5804         const intel_limit_t *limit;
5805         int ret;
5806         struct fdi_m_n m_n = {0};
5807         u32 temp;
5808         u32 lvds_sync = 0;
5809         int target_clock, pixel_multiplier, lane, link_bw, factor;
5810         unsigned int pipe_bpp;
5811         bool dither;
5812
5813         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5814                 if (encoder->base.crtc != crtc)
5815                         continue;
5816
5817                 switch (encoder->type) {
5818                 case INTEL_OUTPUT_LVDS:
5819                         is_lvds = true;
5820                         break;
5821                 case INTEL_OUTPUT_SDVO:
5822                 case INTEL_OUTPUT_HDMI:
5823                         is_sdvo = true;
5824                         if (encoder->needs_tv_clock)
5825                                 is_tv = true;
5826                         break;
5827                 case INTEL_OUTPUT_TVOUT:
5828                         is_tv = true;
5829                         break;
5830                 case INTEL_OUTPUT_ANALOG:
5831                         is_crt = true;
5832                         break;
5833                 case INTEL_OUTPUT_DISPLAYPORT:
5834                         is_dp = true;
5835                         break;
5836                 case INTEL_OUTPUT_EDP:
5837                         has_edp_encoder = encoder;
5838                         break;
5839                 }
5840
5841                 num_connectors++;
5842         }
5843
5844         refclk = ironlake_get_refclk(crtc);
5845
5846         /*
5847          * Returns a set of divisors for the desired target clock with the given
5848          * refclk, or FALSE.  The returned values represent the clock equation:
5849          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5850          */
5851         limit = intel_limit(crtc, refclk);
5852         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5853                              &clock);
5854         if (!ok) {
5855                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5856                 return -EINVAL;
5857         }
5858
5859         /* Ensure that the cursor is valid for the new mode before changing... */
5860         intel_crtc_update_cursor(crtc, true);
5861
5862         if (is_lvds && dev_priv->lvds_downclock_avail) {
5863                 /*
5864                  * Ensure we match the reduced clock's P to the target clock.
5865                  * If the clocks don't match, we can't switch the display clock
5866                  * by using the FP0/FP1. In such case we will disable the LVDS
5867                  * downclock feature.
5868                 */
5869                 has_reduced_clock = limit->find_pll(limit, crtc,
5870                                                     dev_priv->lvds_downclock,
5871                                                     refclk,
5872                                                     &clock,
5873                                                     &reduced_clock);
5874         }
5875         /* SDVO TV has fixed PLL values depend on its clock range,
5876            this mirrors vbios setting. */
5877         if (is_sdvo && is_tv) {
5878                 if (adjusted_mode->clock >= 100000
5879                     && adjusted_mode->clock < 140500) {
5880                         clock.p1 = 2;
5881                         clock.p2 = 10;
5882                         clock.n = 3;
5883                         clock.m1 = 16;
5884                         clock.m2 = 8;
5885                 } else if (adjusted_mode->clock >= 140500
5886                            && adjusted_mode->clock <= 200000) {
5887                         clock.p1 = 1;
5888                         clock.p2 = 10;
5889                         clock.n = 6;
5890                         clock.m1 = 12;
5891                         clock.m2 = 8;
5892                 }
5893         }
5894
5895         /* FDI link */
5896         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5897         lane = 0;
5898         /* CPU eDP doesn't require FDI link, so just set DP M/N
5899            according to current link config */
5900         if (has_edp_encoder &&
5901             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5902                 target_clock = mode->clock;
5903                 intel_edp_link_config(has_edp_encoder,
5904                                       &lane, &link_bw);
5905         } else {
5906                 /* [e]DP over FDI requires target mode clock
5907                    instead of link clock */
5908                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5909                         target_clock = mode->clock;
5910                 else
5911                         target_clock = adjusted_mode->clock;
5912
5913                 /* FDI is a binary signal running at ~2.7GHz, encoding
5914                  * each output octet as 10 bits. The actual frequency
5915                  * is stored as a divider into a 100MHz clock, and the
5916                  * mode pixel clock is stored in units of 1KHz.
5917                  * Hence the bw of each lane in terms of the mode signal
5918                  * is:
5919                  */
5920                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5921         }
5922
5923         /* determine panel color depth */
5924         temp = I915_READ(PIPECONF(pipe));
5925         temp &= ~PIPE_BPC_MASK;
5926         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5927         switch (pipe_bpp) {
5928         case 18:
5929                 temp |= PIPE_6BPC;
5930                 break;
5931         case 24:
5932                 temp |= PIPE_8BPC;
5933                 break;
5934         case 30:
5935                 temp |= PIPE_10BPC;
5936                 break;
5937         case 36:
5938                 temp |= PIPE_12BPC;
5939                 break;
5940         default:
5941                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5942                         pipe_bpp);
5943                 temp |= PIPE_8BPC;
5944                 pipe_bpp = 24;
5945                 break;
5946         }
5947
5948         intel_crtc->bpp = pipe_bpp;
5949         I915_WRITE(PIPECONF(pipe), temp);
5950
5951         if (!lane) {
5952                 /*
5953                  * Account for spread spectrum to avoid
5954                  * oversubscribing the link. Max center spread
5955                  * is 2.5%; use 5% for safety's sake.
5956                  */
5957                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5958                 lane = bps / (link_bw * 8) + 1;
5959         }
5960
5961         intel_crtc->fdi_lanes = lane;
5962
5963         if (pixel_multiplier > 1)
5964                 link_bw *= pixel_multiplier;
5965         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5966                              &m_n);
5967
5968         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5969         if (has_reduced_clock)
5970                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5971                         reduced_clock.m2;
5972
5973         /* Enable autotuning of the PLL clock (if permissible) */
5974         factor = 21;
5975         if (is_lvds) {
5976                 if ((intel_panel_use_ssc(dev_priv) &&
5977                      dev_priv->lvds_ssc_freq == 100) ||
5978                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5979                         factor = 25;
5980         } else if (is_sdvo && is_tv)
5981                 factor = 20;
5982
5983         if (clock.m < factor * clock.n)
5984                 fp |= FP_CB_TUNE;
5985
5986         dpll = 0;
5987
5988         if (is_lvds)
5989                 dpll |= DPLLB_MODE_LVDS;
5990         else
5991                 dpll |= DPLLB_MODE_DAC_SERIAL;
5992         if (is_sdvo) {
5993                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5994                 if (pixel_multiplier > 1) {
5995                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5996                 }
5997                 dpll |= DPLL_DVO_HIGH_SPEED;
5998         }
5999         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
6000                 dpll |= DPLL_DVO_HIGH_SPEED;
6001
6002         /* compute bitmask from p1 value */
6003         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6004         /* also FPA1 */
6005         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6006
6007         switch (clock.p2) {
6008         case 5:
6009                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6010                 break;
6011         case 7:
6012                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6013                 break;
6014         case 10:
6015                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6016                 break;
6017         case 14:
6018                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6019                 break;
6020         }
6021
6022         if (is_sdvo && is_tv)
6023                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6024         else if (is_tv)
6025                 /* XXX: just matching BIOS for now */
6026                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
6027                 dpll |= 3;
6028         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6029                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6030         else
6031                 dpll |= PLL_REF_INPUT_DREFCLK;
6032
6033         /* setup pipeconf */
6034         pipeconf = I915_READ(PIPECONF(pipe));
6035
6036         /* Set up the display plane register */
6037         dspcntr = DISPPLANE_GAMMA_ENABLE;
6038
6039         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
6040         drm_mode_debug_printmodeline(mode);
6041
6042         /* PCH eDP needs FDI, but CPU eDP does not */
6043         if (!intel_crtc->no_pll) {
6044                 if (!has_edp_encoder ||
6045                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6046                         I915_WRITE(PCH_FP0(pipe), fp);
6047                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
6048
6049                         POSTING_READ(PCH_DPLL(pipe));
6050                         udelay(150);
6051                 }
6052         } else {
6053                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
6054                     fp == I915_READ(PCH_FP0(0))) {
6055                         intel_crtc->use_pll_a = true;
6056                         DRM_DEBUG_KMS("using pipe a dpll\n");
6057                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
6058                            fp == I915_READ(PCH_FP0(1))) {
6059                         intel_crtc->use_pll_a = false;
6060                         DRM_DEBUG_KMS("using pipe b dpll\n");
6061                 } else {
6062                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
6063                         return -EINVAL;
6064                 }
6065         }
6066
6067         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
6068          * This is an exception to the general rule that mode_set doesn't turn
6069          * things on.
6070          */
6071         if (is_lvds) {
6072                 temp = I915_READ(PCH_LVDS);
6073                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
6074                 if (HAS_PCH_CPT(dev)) {
6075                         temp &= ~PORT_TRANS_SEL_MASK;
6076                         temp |= PORT_TRANS_SEL_CPT(pipe);
6077                 } else {
6078                         if (pipe == 1)
6079                                 temp |= LVDS_PIPEB_SELECT;
6080                         else
6081                                 temp &= ~LVDS_PIPEB_SELECT;
6082                 }
6083
6084                 /* set the corresponsding LVDS_BORDER bit */
6085                 temp |= dev_priv->lvds_border_bits;
6086                 /* Set the B0-B3 data pairs corresponding to whether we're going to
6087                  * set the DPLLs for dual-channel mode or not.
6088                  */
6089                 if (clock.p2 == 7)
6090                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
6091                 else
6092                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
6093
6094                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
6095                  * appropriately here, but we need to look more thoroughly into how
6096                  * panels behave in the two modes.
6097                  */
6098                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
6099                         lvds_sync |= LVDS_HSYNC_POLARITY;
6100                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
6101                         lvds_sync |= LVDS_VSYNC_POLARITY;
6102                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
6103                     != lvds_sync) {
6104                         char flags[2] = "-+";
6105                         DRM_INFO("Changing LVDS panel from "
6106                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
6107                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
6108                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
6109                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
6110                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
6111                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
6112                         temp |= lvds_sync;
6113                 }
6114                 I915_WRITE(PCH_LVDS, temp);
6115         }
6116
6117         pipeconf &= ~PIPECONF_DITHER_EN;
6118         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
6119         if ((is_lvds && dev_priv->lvds_dither) || dither) {
6120                 pipeconf |= PIPECONF_DITHER_EN;
6121                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
6122         }
6123         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6124                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
6125         } else {
6126                 /* For non-DP output, clear any trans DP clock recovery setting.*/
6127                 I915_WRITE(TRANSDATA_M1(pipe), 0);
6128                 I915_WRITE(TRANSDATA_N1(pipe), 0);
6129                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
6130                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
6131         }
6132
6133         if (!intel_crtc->no_pll &&
6134             (!has_edp_encoder ||
6135              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
6136                 I915_WRITE(PCH_DPLL(pipe), dpll);
6137
6138                 /* Wait for the clocks to stabilize. */
6139                 POSTING_READ(PCH_DPLL(pipe));
6140                 udelay(150);
6141
6142                 /* The pixel multiplier can only be updated once the
6143                  * DPLL is enabled and the clocks are stable.
6144                  *
6145                  * So write it again.
6146                  */
6147                 I915_WRITE(PCH_DPLL(pipe), dpll);
6148         }
6149
6150         intel_crtc->lowfreq_avail = false;
6151         if (!intel_crtc->no_pll) {
6152                 if (is_lvds && has_reduced_clock && i915_powersave) {
6153                         I915_WRITE(PCH_FP1(pipe), fp2);
6154                         intel_crtc->lowfreq_avail = true;
6155                         if (HAS_PIPE_CXSR(dev)) {
6156                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6157                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6158                         }
6159                 } else {
6160                         I915_WRITE(PCH_FP1(pipe), fp);
6161                         if (HAS_PIPE_CXSR(dev)) {
6162                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6163                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6164                         }
6165                 }
6166         }
6167
6168         pipeconf &= ~PIPECONF_INTERLACE_MASK;
6169         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6170                 pipeconf |= PIPECONF_INTERLACED_ILK;
6171                 /* the chip adds 2 halflines automatically */
6172                 adjusted_mode->crtc_vtotal -= 1;
6173                 adjusted_mode->crtc_vblank_end -= 1;
6174                 I915_WRITE(VSYNCSHIFT(pipe),
6175                            adjusted_mode->crtc_hsync_start
6176                            - adjusted_mode->crtc_htotal/2);
6177         } else {
6178                 pipeconf |= PIPECONF_PROGRESSIVE;
6179                 I915_WRITE(VSYNCSHIFT(pipe), 0);
6180         }
6181
6182         I915_WRITE(HTOTAL(pipe),
6183                    (adjusted_mode->crtc_hdisplay - 1) |
6184                    ((adjusted_mode->crtc_htotal - 1) << 16));
6185         I915_WRITE(HBLANK(pipe),
6186                    (adjusted_mode->crtc_hblank_start - 1) |
6187                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6188         I915_WRITE(HSYNC(pipe),
6189                    (adjusted_mode->crtc_hsync_start - 1) |
6190                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6191
6192         I915_WRITE(VTOTAL(pipe),
6193                    (adjusted_mode->crtc_vdisplay - 1) |
6194                    ((adjusted_mode->crtc_vtotal - 1) << 16));
6195         I915_WRITE(VBLANK(pipe),
6196                    (adjusted_mode->crtc_vblank_start - 1) |
6197                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
6198         I915_WRITE(VSYNC(pipe),
6199                    (adjusted_mode->crtc_vsync_start - 1) |
6200                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6201
6202         /* pipesrc controls the size that is scaled from, which should
6203          * always be the user's requested size.
6204          */
6205         I915_WRITE(PIPESRC(pipe),
6206                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6207
6208         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6209         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6210         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6211         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6212
6213         if (has_edp_encoder &&
6214             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6215                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6216         }
6217
6218         I915_WRITE(PIPECONF(pipe), pipeconf);
6219         POSTING_READ(PIPECONF(pipe));
6220
6221         intel_wait_for_vblank(dev, pipe);
6222
6223         I915_WRITE(DSPCNTR(plane), dspcntr);
6224         POSTING_READ(DSPCNTR(plane));
6225
6226         ret = intel_pipe_set_base(crtc, x, y, old_fb);
6227
6228         intel_update_watermarks(dev);
6229
6230         return ret;
6231 }
6232
6233 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6234                                struct drm_display_mode *mode,
6235                                struct drm_display_mode *adjusted_mode,
6236                                int x, int y,
6237                                struct drm_framebuffer *old_fb)
6238 {
6239         struct drm_device *dev = crtc->dev;
6240         struct drm_i915_private *dev_priv = dev->dev_private;
6241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6242         int pipe = intel_crtc->pipe;
6243         int ret;
6244
6245         drm_vblank_pre_modeset(dev, pipe);
6246
6247         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6248                                               x, y, old_fb);
6249         drm_vblank_post_modeset(dev, pipe);
6250
6251         if (ret)
6252                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6253         else
6254                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6255
6256         return ret;
6257 }
6258
6259 static bool intel_eld_uptodate(struct drm_connector *connector,
6260                                int reg_eldv, uint32_t bits_eldv,
6261                                int reg_elda, uint32_t bits_elda,
6262                                int reg_edid)
6263 {
6264         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6265         uint8_t *eld = connector->eld;
6266         uint32_t i;
6267
6268         i = I915_READ(reg_eldv);
6269         i &= bits_eldv;
6270
6271         if (!eld[0])
6272                 return !i;
6273
6274         if (!i)
6275                 return false;
6276
6277         i = I915_READ(reg_elda);
6278         i &= ~bits_elda;
6279         I915_WRITE(reg_elda, i);
6280
6281         for (i = 0; i < eld[2]; i++)
6282                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6283                         return false;
6284
6285         return true;
6286 }
6287
6288 static void g4x_write_eld(struct drm_connector *connector,
6289                           struct drm_crtc *crtc)
6290 {
6291         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6292         uint8_t *eld = connector->eld;
6293         uint32_t eldv;
6294         uint32_t len;
6295         uint32_t i;
6296
6297         i = I915_READ(G4X_AUD_VID_DID);
6298
6299         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6300                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6301         else
6302                 eldv = G4X_ELDV_DEVCTG;
6303
6304         if (intel_eld_uptodate(connector,
6305                                G4X_AUD_CNTL_ST, eldv,
6306                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6307                                G4X_HDMIW_HDMIEDID))
6308                 return;
6309
6310         i = I915_READ(G4X_AUD_CNTL_ST);
6311         i &= ~(eldv | G4X_ELD_ADDR);
6312         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6313         I915_WRITE(G4X_AUD_CNTL_ST, i);
6314
6315         if (!eld[0])
6316                 return;
6317
6318         len = min_t(uint8_t, eld[2], len);
6319         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6320         for (i = 0; i < len; i++)
6321                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6322
6323         i = I915_READ(G4X_AUD_CNTL_ST);
6324         i |= eldv;
6325         I915_WRITE(G4X_AUD_CNTL_ST, i);
6326 }
6327
6328 static void ironlake_write_eld(struct drm_connector *connector,
6329                                      struct drm_crtc *crtc)
6330 {
6331         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6332         uint8_t *eld = connector->eld;
6333         uint32_t eldv;
6334         uint32_t i;
6335         int len;
6336         int hdmiw_hdmiedid;
6337         int aud_config;
6338         int aud_cntl_st;
6339         int aud_cntrl_st2;
6340
6341         if (HAS_PCH_IBX(connector->dev)) {
6342                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6343                 aud_config = IBX_AUD_CONFIG_A;
6344                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6345                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6346         } else {
6347                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6348                 aud_config = CPT_AUD_CONFIG_A;
6349                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6350                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6351         }
6352
6353         i = to_intel_crtc(crtc)->pipe;
6354         hdmiw_hdmiedid += i * 0x100;
6355         aud_cntl_st += i * 0x100;
6356         aud_config += i * 0x100;
6357
6358         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6359
6360         i = I915_READ(aud_cntl_st);
6361         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
6362         if (!i) {
6363                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6364                 /* operate blindly on all ports */
6365                 eldv = IBX_ELD_VALIDB;
6366                 eldv |= IBX_ELD_VALIDB << 4;
6367                 eldv |= IBX_ELD_VALIDB << 8;
6368         } else {
6369                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6370                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6371         }
6372
6373         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6374                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6375                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6376                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6377         } else
6378                 I915_WRITE(aud_config, 0);
6379
6380         if (intel_eld_uptodate(connector,
6381                                aud_cntrl_st2, eldv,
6382                                aud_cntl_st, IBX_ELD_ADDRESS,
6383                                hdmiw_hdmiedid))
6384                 return;
6385
6386         i = I915_READ(aud_cntrl_st2);
6387         i &= ~eldv;
6388         I915_WRITE(aud_cntrl_st2, i);
6389
6390         if (!eld[0])
6391                 return;
6392
6393         i = I915_READ(aud_cntl_st);
6394         i &= ~IBX_ELD_ADDRESS;
6395         I915_WRITE(aud_cntl_st, i);
6396
6397         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6398         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6399         for (i = 0; i < len; i++)
6400                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6401
6402         i = I915_READ(aud_cntrl_st2);
6403         i |= eldv;
6404         I915_WRITE(aud_cntrl_st2, i);
6405 }
6406
6407 void intel_write_eld(struct drm_encoder *encoder,
6408                      struct drm_display_mode *mode)
6409 {
6410         struct drm_crtc *crtc = encoder->crtc;
6411         struct drm_connector *connector;
6412         struct drm_device *dev = encoder->dev;
6413         struct drm_i915_private *dev_priv = dev->dev_private;
6414
6415         connector = drm_select_eld(encoder, mode);
6416         if (!connector)
6417                 return;
6418
6419         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6420                          connector->base.id,
6421                          drm_get_connector_name(connector),
6422                          connector->encoder->base.id,
6423                          drm_get_encoder_name(connector->encoder));
6424
6425         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6426
6427         if (dev_priv->display.write_eld)
6428                 dev_priv->display.write_eld(connector, crtc);
6429 }
6430
6431 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6432 void intel_crtc_load_lut(struct drm_crtc *crtc)
6433 {
6434         struct drm_device *dev = crtc->dev;
6435         struct drm_i915_private *dev_priv = dev->dev_private;
6436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6437         int palreg = PALETTE(intel_crtc->pipe);
6438         int i;
6439
6440         /* The clocks have to be on to load the palette. */
6441         if (!crtc->enabled)
6442                 return;
6443
6444         /* use legacy palette for Ironlake */
6445         if (HAS_PCH_SPLIT(dev))
6446                 palreg = LGC_PALETTE(intel_crtc->pipe);
6447
6448         for (i = 0; i < 256; i++) {
6449                 I915_WRITE(palreg + 4 * i,
6450                            (intel_crtc->lut_r[i] << 16) |
6451                            (intel_crtc->lut_g[i] << 8) |
6452                            intel_crtc->lut_b[i]);
6453         }
6454 }
6455
6456 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6457 {
6458         struct drm_device *dev = crtc->dev;
6459         struct drm_i915_private *dev_priv = dev->dev_private;
6460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6461         bool visible = base != 0;
6462         u32 cntl;
6463
6464         if (intel_crtc->cursor_visible == visible)
6465                 return;
6466
6467         cntl = I915_READ(_CURACNTR);
6468         if (visible) {
6469                 /* On these chipsets we can only modify the base whilst
6470                  * the cursor is disabled.
6471                  */
6472                 I915_WRITE(_CURABASE, base);
6473
6474                 cntl &= ~(CURSOR_FORMAT_MASK);
6475                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6476                 cntl |= CURSOR_ENABLE |
6477                         CURSOR_GAMMA_ENABLE |
6478                         CURSOR_FORMAT_ARGB;
6479         } else
6480                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6481         I915_WRITE(_CURACNTR, cntl);
6482
6483         intel_crtc->cursor_visible = visible;
6484 }
6485
6486 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6487 {
6488         struct drm_device *dev = crtc->dev;
6489         struct drm_i915_private *dev_priv = dev->dev_private;
6490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6491         int pipe = intel_crtc->pipe;
6492         bool visible = base != 0;
6493
6494         if (intel_crtc->cursor_visible != visible) {
6495                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6496                 if (base) {
6497                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6498                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6499                         cntl |= pipe << 28; /* Connect to correct pipe */
6500                 } else {
6501                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6502                         cntl |= CURSOR_MODE_DISABLE;
6503                 }
6504                 I915_WRITE(CURCNTR(pipe), cntl);
6505
6506                 intel_crtc->cursor_visible = visible;
6507         }
6508         /* and commit changes on next vblank */
6509         I915_WRITE(CURBASE(pipe), base);
6510 }
6511
6512 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6513 {
6514         struct drm_device *dev = crtc->dev;
6515         struct drm_i915_private *dev_priv = dev->dev_private;
6516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6517         int pipe = intel_crtc->pipe;
6518         bool visible = base != 0;
6519
6520         if (intel_crtc->cursor_visible != visible) {
6521                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6522                 if (base) {
6523                         cntl &= ~CURSOR_MODE;
6524                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6525                 } else {
6526                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6527                         cntl |= CURSOR_MODE_DISABLE;
6528                 }
6529                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6530
6531                 intel_crtc->cursor_visible = visible;
6532         }
6533         /* and commit changes on next vblank */
6534         I915_WRITE(CURBASE_IVB(pipe), base);
6535 }
6536
6537 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6538 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6539                                      bool on)
6540 {
6541         struct drm_device *dev = crtc->dev;
6542         struct drm_i915_private *dev_priv = dev->dev_private;
6543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6544         int pipe = intel_crtc->pipe;
6545         int x = intel_crtc->cursor_x;
6546         int y = intel_crtc->cursor_y;
6547         u32 base, pos;
6548         bool visible;
6549
6550         pos = 0;
6551
6552         if (on && crtc->enabled && crtc->fb) {
6553                 base = intel_crtc->cursor_addr;
6554                 if (x > (int) crtc->fb->width)
6555                         base = 0;
6556
6557                 if (y > (int) crtc->fb->height)
6558                         base = 0;
6559         } else
6560                 base = 0;
6561
6562         if (x < 0) {
6563                 if (x + intel_crtc->cursor_width < 0)
6564                         base = 0;
6565
6566                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6567                 x = -x;
6568         }
6569         pos |= x << CURSOR_X_SHIFT;
6570
6571         if (y < 0) {
6572                 if (y + intel_crtc->cursor_height < 0)
6573                         base = 0;
6574
6575                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6576                 y = -y;
6577         }
6578         pos |= y << CURSOR_Y_SHIFT;
6579
6580         visible = base != 0;
6581         if (!visible && !intel_crtc->cursor_visible)
6582                 return;
6583
6584         if (IS_IVYBRIDGE(dev)) {
6585                 I915_WRITE(CURPOS_IVB(pipe), pos);
6586                 ivb_update_cursor(crtc, base);
6587         } else {
6588                 I915_WRITE(CURPOS(pipe), pos);
6589                 if (IS_845G(dev) || IS_I865G(dev))
6590                         i845_update_cursor(crtc, base);
6591                 else
6592                         i9xx_update_cursor(crtc, base);
6593         }
6594
6595         if (visible)
6596                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6597 }
6598
6599 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6600                                  struct drm_file *file,
6601                                  uint32_t handle,
6602                                  uint32_t width, uint32_t height)
6603 {
6604         struct drm_device *dev = crtc->dev;
6605         struct drm_i915_private *dev_priv = dev->dev_private;
6606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6607         struct drm_i915_gem_object *obj;
6608         uint32_t addr;
6609         int ret;
6610
6611         DRM_DEBUG_KMS("\n");
6612
6613         /* if we want to turn off the cursor ignore width and height */
6614         if (!handle) {
6615                 DRM_DEBUG_KMS("cursor off\n");
6616                 addr = 0;
6617                 obj = NULL;
6618                 mutex_lock(&dev->struct_mutex);
6619                 goto finish;
6620         }
6621
6622         /* Currently we only support 64x64 cursors */
6623         if (width != 64 || height != 64) {
6624                 DRM_ERROR("we currently only support 64x64 cursors\n");
6625                 return -EINVAL;
6626         }
6627
6628         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6629         if (&obj->base == NULL)
6630                 return -ENOENT;
6631
6632         if (obj->base.size < width * height * 4) {
6633                 DRM_ERROR("buffer is to small\n");
6634                 ret = -ENOMEM;
6635                 goto fail;
6636         }
6637
6638         /* we only need to pin inside GTT if cursor is non-phy */
6639         mutex_lock(&dev->struct_mutex);
6640         if (!dev_priv->info->cursor_needs_physical) {
6641                 if (obj->tiling_mode) {
6642                         DRM_ERROR("cursor cannot be tiled\n");
6643                         ret = -EINVAL;
6644                         goto fail_locked;
6645                 }
6646
6647                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6648                 if (ret) {
6649                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6650                         goto fail_locked;
6651                 }
6652
6653                 ret = i915_gem_object_put_fence(obj);
6654                 if (ret) {
6655                         DRM_ERROR("failed to release fence for cursor");
6656                         goto fail_unpin;
6657                 }
6658
6659                 addr = obj->gtt_offset;
6660         } else {
6661                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6662                 ret = i915_gem_attach_phys_object(dev, obj,
6663                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6664                                                   align);
6665                 if (ret) {
6666                         DRM_ERROR("failed to attach phys object\n");
6667                         goto fail_locked;
6668                 }
6669                 addr = obj->phys_obj->handle->busaddr;
6670         }
6671
6672         if (IS_GEN2(dev))
6673                 I915_WRITE(CURSIZE, (height << 12) | width);
6674
6675  finish:
6676         if (intel_crtc->cursor_bo) {
6677                 if (dev_priv->info->cursor_needs_physical) {
6678                         if (intel_crtc->cursor_bo != obj)
6679                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6680                 } else
6681                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6682                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6683         }
6684
6685         mutex_unlock(&dev->struct_mutex);
6686
6687         intel_crtc->cursor_addr = addr;
6688         intel_crtc->cursor_bo = obj;
6689         intel_crtc->cursor_width = width;
6690         intel_crtc->cursor_height = height;
6691
6692         intel_crtc_update_cursor(crtc, true);
6693
6694         return 0;
6695 fail_unpin:
6696         i915_gem_object_unpin(obj);
6697 fail_locked:
6698         mutex_unlock(&dev->struct_mutex);
6699 fail:
6700         drm_gem_object_unreference_unlocked(&obj->base);
6701         return ret;
6702 }
6703
6704 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6705 {
6706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6707
6708         intel_crtc->cursor_x = x;
6709         intel_crtc->cursor_y = y;
6710
6711         intel_crtc_update_cursor(crtc, true);
6712
6713         return 0;
6714 }
6715
6716 /** Sets the color ramps on behalf of RandR */
6717 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6718                                  u16 blue, int regno)
6719 {
6720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6721
6722         intel_crtc->lut_r[regno] = red >> 8;
6723         intel_crtc->lut_g[regno] = green >> 8;
6724         intel_crtc->lut_b[regno] = blue >> 8;
6725 }
6726
6727 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6728                              u16 *blue, int regno)
6729 {
6730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6731
6732         *red = intel_crtc->lut_r[regno] << 8;
6733         *green = intel_crtc->lut_g[regno] << 8;
6734         *blue = intel_crtc->lut_b[regno] << 8;
6735 }
6736
6737 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6738                                  u16 *blue, uint32_t start, uint32_t size)
6739 {
6740         int end = (start + size > 256) ? 256 : start + size, i;
6741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6742
6743         for (i = start; i < end; i++) {
6744                 intel_crtc->lut_r[i] = red[i] >> 8;
6745                 intel_crtc->lut_g[i] = green[i] >> 8;
6746                 intel_crtc->lut_b[i] = blue[i] >> 8;
6747         }
6748
6749         intel_crtc_load_lut(crtc);
6750 }
6751
6752 /**
6753  * Get a pipe with a simple mode set on it for doing load-based monitor
6754  * detection.
6755  *
6756  * It will be up to the load-detect code to adjust the pipe as appropriate for
6757  * its requirements.  The pipe will be connected to no other encoders.
6758  *
6759  * Currently this code will only succeed if there is a pipe with no encoders
6760  * configured for it.  In the future, it could choose to temporarily disable
6761  * some outputs to free up a pipe for its use.
6762  *
6763  * \return crtc, or NULL if no pipes are available.
6764  */
6765
6766 /* VESA 640x480x72Hz mode to set on the pipe */
6767 static struct drm_display_mode load_detect_mode = {
6768         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6769                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6770 };
6771
6772 static struct drm_framebuffer *
6773 intel_framebuffer_create(struct drm_device *dev,
6774                          struct drm_mode_fb_cmd2 *mode_cmd,
6775                          struct drm_i915_gem_object *obj)
6776 {
6777         struct intel_framebuffer *intel_fb;
6778         int ret;
6779
6780         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6781         if (!intel_fb) {
6782                 drm_gem_object_unreference_unlocked(&obj->base);
6783                 return ERR_PTR(-ENOMEM);
6784         }
6785
6786         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6787         if (ret) {
6788                 drm_gem_object_unreference_unlocked(&obj->base);
6789                 kfree(intel_fb);
6790                 return ERR_PTR(ret);
6791         }
6792
6793         return &intel_fb->base;
6794 }
6795
6796 static u32
6797 intel_framebuffer_pitch_for_width(int width, int bpp)
6798 {
6799         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6800         return ALIGN(pitch, 64);
6801 }
6802
6803 static u32
6804 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6805 {
6806         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6807         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6808 }
6809
6810 static struct drm_framebuffer *
6811 intel_framebuffer_create_for_mode(struct drm_device *dev,
6812                                   struct drm_display_mode *mode,
6813                                   int depth, int bpp)
6814 {
6815         struct drm_i915_gem_object *obj;
6816         struct drm_mode_fb_cmd2 mode_cmd;
6817
6818         obj = i915_gem_alloc_object(dev,
6819                                     intel_framebuffer_size_for_mode(mode, bpp));
6820         if (obj == NULL)
6821                 return ERR_PTR(-ENOMEM);
6822
6823         mode_cmd.width = mode->hdisplay;
6824         mode_cmd.height = mode->vdisplay;
6825         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6826                                                                 bpp);
6827         mode_cmd.pixel_format = 0;
6828
6829         return intel_framebuffer_create(dev, &mode_cmd, obj);
6830 }
6831
6832 static struct drm_framebuffer *
6833 mode_fits_in_fbdev(struct drm_device *dev,
6834                    struct drm_display_mode *mode)
6835 {
6836         struct drm_i915_private *dev_priv = dev->dev_private;
6837         struct drm_i915_gem_object *obj;
6838         struct drm_framebuffer *fb;
6839
6840         if (dev_priv->fbdev == NULL)
6841                 return NULL;
6842
6843         obj = dev_priv->fbdev->ifb.obj;
6844         if (obj == NULL)
6845                 return NULL;
6846
6847         fb = &dev_priv->fbdev->ifb.base;
6848         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6849                                                                fb->bits_per_pixel))
6850                 return NULL;
6851
6852         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6853                 return NULL;
6854
6855         return fb;
6856 }
6857
6858 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6859                                 struct drm_connector *connector,
6860                                 struct drm_display_mode *mode,
6861                                 struct intel_load_detect_pipe *old)
6862 {
6863         struct intel_crtc *intel_crtc;
6864         struct drm_crtc *possible_crtc;
6865         struct drm_encoder *encoder = &intel_encoder->base;
6866         struct drm_crtc *crtc = NULL;
6867         struct drm_device *dev = encoder->dev;
6868         struct drm_framebuffer *old_fb;
6869         int i = -1;
6870
6871         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6872                       connector->base.id, drm_get_connector_name(connector),
6873                       encoder->base.id, drm_get_encoder_name(encoder));
6874
6875         /*
6876          * Algorithm gets a little messy:
6877          *
6878          *   - if the connector already has an assigned crtc, use it (but make
6879          *     sure it's on first)
6880          *
6881          *   - try to find the first unused crtc that can drive this connector,
6882          *     and use that if we find one
6883          */
6884
6885         /* See if we already have a CRTC for this connector */
6886         if (encoder->crtc) {
6887                 crtc = encoder->crtc;
6888
6889                 intel_crtc = to_intel_crtc(crtc);
6890                 old->dpms_mode = intel_crtc->dpms_mode;
6891                 old->load_detect_temp = false;
6892
6893                 /* Make sure the crtc and connector are running */
6894                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6895                         struct drm_encoder_helper_funcs *encoder_funcs;
6896                         struct drm_crtc_helper_funcs *crtc_funcs;
6897
6898                         crtc_funcs = crtc->helper_private;
6899                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6900
6901                         encoder_funcs = encoder->helper_private;
6902                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6903                 }
6904
6905                 return true;
6906         }
6907
6908         /* Find an unused one (if possible) */
6909         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6910                 i++;
6911                 if (!(encoder->possible_crtcs & (1 << i)))
6912                         continue;
6913                 if (!possible_crtc->enabled) {
6914                         crtc = possible_crtc;
6915                         break;
6916                 }
6917         }
6918
6919         /*
6920          * If we didn't find an unused CRTC, don't use any.
6921          */
6922         if (!crtc) {
6923                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6924                 return false;
6925         }
6926
6927         encoder->crtc = crtc;
6928         connector->encoder = encoder;
6929
6930         intel_crtc = to_intel_crtc(crtc);
6931         old->dpms_mode = intel_crtc->dpms_mode;
6932         old->load_detect_temp = true;
6933         old->release_fb = NULL;
6934
6935         if (!mode)
6936                 mode = &load_detect_mode;
6937
6938         old_fb = crtc->fb;
6939
6940         /* We need a framebuffer large enough to accommodate all accesses
6941          * that the plane may generate whilst we perform load detection.
6942          * We can not rely on the fbcon either being present (we get called
6943          * during its initialisation to detect all boot displays, or it may
6944          * not even exist) or that it is large enough to satisfy the
6945          * requested mode.
6946          */
6947         crtc->fb = mode_fits_in_fbdev(dev, mode);
6948         if (crtc->fb == NULL) {
6949                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6950                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6951                 old->release_fb = crtc->fb;
6952         } else
6953                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6954         if (IS_ERR(crtc->fb)) {
6955                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6956                 crtc->fb = old_fb;
6957                 return false;
6958         }
6959
6960         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6961                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6962                 if (old->release_fb)
6963                         old->release_fb->funcs->destroy(old->release_fb);
6964                 crtc->fb = old_fb;
6965                 return false;
6966         }
6967
6968         /* let the connector get through one full cycle before testing */
6969         intel_wait_for_vblank(dev, intel_crtc->pipe);
6970
6971         return true;
6972 }
6973
6974 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6975                                     struct drm_connector *connector,
6976                                     struct intel_load_detect_pipe *old)
6977 {
6978         struct drm_encoder *encoder = &intel_encoder->base;
6979         struct drm_device *dev = encoder->dev;
6980         struct drm_crtc *crtc = encoder->crtc;
6981         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6982         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6983
6984         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6985                       connector->base.id, drm_get_connector_name(connector),
6986                       encoder->base.id, drm_get_encoder_name(encoder));
6987
6988         if (old->load_detect_temp) {
6989                 connector->encoder = NULL;
6990                 drm_helper_disable_unused_functions(dev);
6991
6992                 if (old->release_fb)
6993                         old->release_fb->funcs->destroy(old->release_fb);
6994
6995                 return;
6996         }
6997
6998         /* Switch crtc and encoder back off if necessary */
6999         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
7000                 encoder_funcs->dpms(encoder, old->dpms_mode);
7001                 crtc_funcs->dpms(crtc, old->dpms_mode);
7002         }
7003 }
7004
7005 /* Returns the clock of the currently programmed mode of the given pipe. */
7006 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
7007 {
7008         struct drm_i915_private *dev_priv = dev->dev_private;
7009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7010         int pipe = intel_crtc->pipe;
7011         u32 dpll = I915_READ(DPLL(pipe));
7012         u32 fp;
7013         intel_clock_t clock;
7014
7015         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7016                 fp = I915_READ(FP0(pipe));
7017         else
7018                 fp = I915_READ(FP1(pipe));
7019
7020         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7021         if (IS_PINEVIEW(dev)) {
7022                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7023                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7024         } else {
7025                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7026                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7027         }
7028
7029         if (!IS_GEN2(dev)) {
7030                 if (IS_PINEVIEW(dev))
7031                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7032                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7033                 else
7034                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7035                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7036
7037                 switch (dpll & DPLL_MODE_MASK) {
7038                 case DPLLB_MODE_DAC_SERIAL:
7039                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7040                                 5 : 10;
7041                         break;
7042                 case DPLLB_MODE_LVDS:
7043                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7044                                 7 : 14;
7045                         break;
7046                 default:
7047                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7048                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7049                         return 0;
7050                 }
7051
7052                 /* XXX: Handle the 100Mhz refclk */
7053                 intel_clock(dev, 96000, &clock);
7054         } else {
7055                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7056
7057                 if (is_lvds) {
7058                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7059                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7060                         clock.p2 = 14;
7061
7062                         if ((dpll & PLL_REF_INPUT_MASK) ==
7063                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7064                                 /* XXX: might not be 66MHz */
7065                                 intel_clock(dev, 66000, &clock);
7066                         } else
7067                                 intel_clock(dev, 48000, &clock);
7068                 } else {
7069                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7070                                 clock.p1 = 2;
7071                         else {
7072                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7073                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7074                         }
7075                         if (dpll & PLL_P2_DIVIDE_BY_4)
7076                                 clock.p2 = 4;
7077                         else
7078                                 clock.p2 = 2;
7079
7080                         intel_clock(dev, 48000, &clock);
7081                 }
7082         }
7083
7084         /* XXX: It would be nice to validate the clocks, but we can't reuse
7085          * i830PllIsValid() because it relies on the xf86_config connector
7086          * configuration being accurate, which it isn't necessarily.
7087          */
7088
7089         return clock.dot;
7090 }
7091
7092 /** Returns the currently programmed mode of the given pipe. */
7093 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7094                                              struct drm_crtc *crtc)
7095 {
7096         struct drm_i915_private *dev_priv = dev->dev_private;
7097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7098         int pipe = intel_crtc->pipe;
7099         struct drm_display_mode *mode;
7100         int htot = I915_READ(HTOTAL(pipe));
7101         int hsync = I915_READ(HSYNC(pipe));
7102         int vtot = I915_READ(VTOTAL(pipe));
7103         int vsync = I915_READ(VSYNC(pipe));
7104
7105         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7106         if (!mode)
7107                 return NULL;
7108
7109         mode->clock = intel_crtc_clock_get(dev, crtc);
7110         mode->hdisplay = (htot & 0xffff) + 1;
7111         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7112         mode->hsync_start = (hsync & 0xffff) + 1;
7113         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7114         mode->vdisplay = (vtot & 0xffff) + 1;
7115         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7116         mode->vsync_start = (vsync & 0xffff) + 1;
7117         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7118
7119         drm_mode_set_name(mode);
7120         drm_mode_set_crtcinfo(mode, 0);
7121
7122         return mode;
7123 }
7124
7125 #define GPU_IDLE_TIMEOUT 500 /* ms */
7126
7127 /* When this timer fires, we've been idle for awhile */
7128 static void intel_gpu_idle_timer(unsigned long arg)
7129 {
7130         struct drm_device *dev = (struct drm_device *)arg;
7131         drm_i915_private_t *dev_priv = dev->dev_private;
7132
7133         if (!list_empty(&dev_priv->mm.active_list)) {
7134                 /* Still processing requests, so just re-arm the timer. */
7135                 mod_timer(&dev_priv->idle_timer, jiffies +
7136                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7137                 return;
7138         }
7139
7140         dev_priv->busy = false;
7141         queue_work(dev_priv->wq, &dev_priv->idle_work);
7142 }
7143
7144 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
7145
7146 static void intel_crtc_idle_timer(unsigned long arg)
7147 {
7148         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
7149         struct drm_crtc *crtc = &intel_crtc->base;
7150         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
7151         struct intel_framebuffer *intel_fb;
7152
7153         intel_fb = to_intel_framebuffer(crtc->fb);
7154         if (intel_fb && intel_fb->obj->active) {
7155                 /* The framebuffer is still being accessed by the GPU. */
7156                 mod_timer(&intel_crtc->idle_timer, jiffies +
7157                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7158                 return;
7159         }
7160
7161         intel_crtc->busy = false;
7162         queue_work(dev_priv->wq, &dev_priv->idle_work);
7163 }
7164
7165 static void intel_increase_pllclock(struct drm_crtc *crtc)
7166 {
7167         struct drm_device *dev = crtc->dev;
7168         drm_i915_private_t *dev_priv = dev->dev_private;
7169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7170         int pipe = intel_crtc->pipe;
7171         int dpll_reg = DPLL(pipe);
7172         int dpll;
7173
7174         if (HAS_PCH_SPLIT(dev))
7175                 return;
7176
7177         if (!dev_priv->lvds_downclock_avail)
7178                 return;
7179
7180         dpll = I915_READ(dpll_reg);
7181         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7182                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7183
7184                 assert_panel_unlocked(dev_priv, pipe);
7185
7186                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7187                 I915_WRITE(dpll_reg, dpll);
7188                 intel_wait_for_vblank(dev, pipe);
7189
7190                 dpll = I915_READ(dpll_reg);
7191                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7192                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7193         }
7194
7195         /* Schedule downclock */
7196         mod_timer(&intel_crtc->idle_timer, jiffies +
7197                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7198 }
7199
7200 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7201 {
7202         struct drm_device *dev = crtc->dev;
7203         drm_i915_private_t *dev_priv = dev->dev_private;
7204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7205         int pipe = intel_crtc->pipe;
7206         int dpll_reg = DPLL(pipe);
7207         int dpll = I915_READ(dpll_reg);
7208
7209         if (HAS_PCH_SPLIT(dev))
7210                 return;
7211
7212         if (!dev_priv->lvds_downclock_avail)
7213                 return;
7214
7215         /*
7216          * Since this is called by a timer, we should never get here in
7217          * the manual case.
7218          */
7219         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7220                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7221
7222                 assert_panel_unlocked(dev_priv, pipe);
7223
7224                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7225                 I915_WRITE(dpll_reg, dpll);
7226                 intel_wait_for_vblank(dev, pipe);
7227                 dpll = I915_READ(dpll_reg);
7228                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7229                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7230         }
7231
7232 }
7233
7234 /**
7235  * intel_idle_update - adjust clocks for idleness
7236  * @work: work struct
7237  *
7238  * Either the GPU or display (or both) went idle.  Check the busy status
7239  * here and adjust the CRTC and GPU clocks as necessary.
7240  */
7241 static void intel_idle_update(struct work_struct *work)
7242 {
7243         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7244                                                     idle_work);
7245         struct drm_device *dev = dev_priv->dev;
7246         struct drm_crtc *crtc;
7247         struct intel_crtc *intel_crtc;
7248
7249         if (!i915_powersave)
7250                 return;
7251
7252         mutex_lock(&dev->struct_mutex);
7253
7254         i915_update_gfx_val(dev_priv);
7255
7256         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7257                 /* Skip inactive CRTCs */
7258                 if (!crtc->fb)
7259                         continue;
7260
7261                 intel_crtc = to_intel_crtc(crtc);
7262                 if (!intel_crtc->busy)
7263                         intel_decrease_pllclock(crtc);
7264         }
7265
7266
7267         mutex_unlock(&dev->struct_mutex);
7268 }
7269
7270 /**
7271  * intel_mark_busy - mark the GPU and possibly the display busy
7272  * @dev: drm device
7273  * @obj: object we're operating on
7274  *
7275  * Callers can use this function to indicate that the GPU is busy processing
7276  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
7277  * buffer), we'll also mark the display as busy, so we know to increase its
7278  * clock frequency.
7279  */
7280 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7281 {
7282         drm_i915_private_t *dev_priv = dev->dev_private;
7283         struct drm_crtc *crtc = NULL;
7284         struct intel_framebuffer *intel_fb;
7285         struct intel_crtc *intel_crtc;
7286
7287         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7288                 return;
7289
7290         if (!dev_priv->busy)
7291                 dev_priv->busy = true;
7292         else
7293                 mod_timer(&dev_priv->idle_timer, jiffies +
7294                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7295
7296         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7297                 if (!crtc->fb)
7298                         continue;
7299
7300                 intel_crtc = to_intel_crtc(crtc);
7301                 intel_fb = to_intel_framebuffer(crtc->fb);
7302                 if (intel_fb->obj == obj) {
7303                         if (!intel_crtc->busy) {
7304                                 /* Non-busy -> busy, upclock */
7305                                 intel_increase_pllclock(crtc);
7306                                 intel_crtc->busy = true;
7307                         } else {
7308                                 /* Busy -> busy, put off timer */
7309                                 mod_timer(&intel_crtc->idle_timer, jiffies +
7310                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7311                         }
7312                 }
7313         }
7314 }
7315
7316 static void intel_crtc_destroy(struct drm_crtc *crtc)
7317 {
7318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7319         struct drm_device *dev = crtc->dev;
7320         struct intel_unpin_work *work;
7321         unsigned long flags;
7322
7323         spin_lock_irqsave(&dev->event_lock, flags);
7324         work = intel_crtc->unpin_work;
7325         intel_crtc->unpin_work = NULL;
7326         spin_unlock_irqrestore(&dev->event_lock, flags);
7327
7328         if (work) {
7329                 cancel_work_sync(&work->work);
7330                 kfree(work);
7331         }
7332
7333         drm_crtc_cleanup(crtc);
7334
7335         kfree(intel_crtc);
7336 }
7337
7338 static void intel_unpin_work_fn(struct work_struct *__work)
7339 {
7340         struct intel_unpin_work *work =
7341                 container_of(__work, struct intel_unpin_work, work);
7342
7343         mutex_lock(&work->dev->struct_mutex);
7344         intel_unpin_fb_obj(work->old_fb_obj);
7345         drm_gem_object_unreference(&work->pending_flip_obj->base);
7346         drm_gem_object_unreference(&work->old_fb_obj->base);
7347
7348         intel_update_fbc(work->dev);
7349         mutex_unlock(&work->dev->struct_mutex);
7350         kfree(work);
7351 }
7352
7353 static void do_intel_finish_page_flip(struct drm_device *dev,
7354                                       struct drm_crtc *crtc)
7355 {
7356         drm_i915_private_t *dev_priv = dev->dev_private;
7357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7358         struct intel_unpin_work *work;
7359         struct drm_i915_gem_object *obj;
7360         struct drm_pending_vblank_event *e;
7361         struct timeval tnow, tvbl;
7362         unsigned long flags;
7363
7364         /* Ignore early vblank irqs */
7365         if (intel_crtc == NULL)
7366                 return;
7367
7368         do_gettimeofday(&tnow);
7369
7370         spin_lock_irqsave(&dev->event_lock, flags);
7371         work = intel_crtc->unpin_work;
7372         if (work == NULL || !work->pending) {
7373                 spin_unlock_irqrestore(&dev->event_lock, flags);
7374                 return;
7375         }
7376
7377         intel_crtc->unpin_work = NULL;
7378
7379         if (work->event) {
7380                 e = work->event;
7381                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7382
7383                 /* Called before vblank count and timestamps have
7384                  * been updated for the vblank interval of flip
7385                  * completion? Need to increment vblank count and
7386                  * add one videorefresh duration to returned timestamp
7387                  * to account for this. We assume this happened if we
7388                  * get called over 0.9 frame durations after the last
7389                  * timestamped vblank.
7390                  *
7391                  * This calculation can not be used with vrefresh rates
7392                  * below 5Hz (10Hz to be on the safe side) without
7393                  * promoting to 64 integers.
7394                  */
7395                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7396                     9 * crtc->framedur_ns) {
7397                         e->event.sequence++;
7398                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7399                                              crtc->framedur_ns);
7400                 }
7401
7402                 e->event.tv_sec = tvbl.tv_sec;
7403                 e->event.tv_usec = tvbl.tv_usec;
7404
7405                 list_add_tail(&e->base.link,
7406                               &e->base.file_priv->event_list);
7407                 wake_up_interruptible(&e->base.file_priv->event_wait);
7408         }
7409
7410         drm_vblank_put(dev, intel_crtc->pipe);
7411
7412         spin_unlock_irqrestore(&dev->event_lock, flags);
7413
7414         obj = work->old_fb_obj;
7415
7416         atomic_clear_mask(1 << intel_crtc->plane,
7417                           &obj->pending_flip.counter);
7418         if (atomic_read(&obj->pending_flip) == 0)
7419                 wake_up(&dev_priv->pending_flip_queue);
7420
7421         schedule_work(&work->work);
7422
7423         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7424 }
7425
7426 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7427 {
7428         drm_i915_private_t *dev_priv = dev->dev_private;
7429         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7430
7431         do_intel_finish_page_flip(dev, crtc);
7432 }
7433
7434 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7435 {
7436         drm_i915_private_t *dev_priv = dev->dev_private;
7437         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7438
7439         do_intel_finish_page_flip(dev, crtc);
7440 }
7441
7442 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7443 {
7444         drm_i915_private_t *dev_priv = dev->dev_private;
7445         struct intel_crtc *intel_crtc =
7446                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7447         unsigned long flags;
7448
7449         spin_lock_irqsave(&dev->event_lock, flags);
7450         if (intel_crtc->unpin_work) {
7451                 if ((++intel_crtc->unpin_work->pending) > 1)
7452                         DRM_ERROR("Prepared flip multiple times\n");
7453         } else {
7454                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7455         }
7456         spin_unlock_irqrestore(&dev->event_lock, flags);
7457 }
7458
7459 static int intel_gen2_queue_flip(struct drm_device *dev,
7460                                  struct drm_crtc *crtc,
7461                                  struct drm_framebuffer *fb,
7462                                  struct drm_i915_gem_object *obj)
7463 {
7464         struct drm_i915_private *dev_priv = dev->dev_private;
7465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7466         unsigned long offset;
7467         u32 flip_mask;
7468         int ret;
7469
7470         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7471         if (ret)
7472                 goto out;
7473
7474         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7475         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7476
7477         ret = BEGIN_LP_RING(6);
7478         if (ret)
7479                 goto out;
7480
7481         /* Can't queue multiple flips, so wait for the previous
7482          * one to finish before executing the next.
7483          */
7484         if (intel_crtc->plane)
7485                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7486         else
7487                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7488         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7489         OUT_RING(MI_NOOP);
7490         OUT_RING(MI_DISPLAY_FLIP |
7491                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7492         OUT_RING(fb->pitches[0]);
7493         OUT_RING(obj->gtt_offset + offset);
7494         OUT_RING(0); /* aux display base address, unused */
7495         ADVANCE_LP_RING();
7496 out:
7497         return ret;
7498 }
7499
7500 static int intel_gen3_queue_flip(struct drm_device *dev,
7501                                  struct drm_crtc *crtc,
7502                                  struct drm_framebuffer *fb,
7503                                  struct drm_i915_gem_object *obj)
7504 {
7505         struct drm_i915_private *dev_priv = dev->dev_private;
7506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7507         unsigned long offset;
7508         u32 flip_mask;
7509         int ret;
7510
7511         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7512         if (ret)
7513                 goto out;
7514
7515         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7516         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7517
7518         ret = BEGIN_LP_RING(6);
7519         if (ret)
7520                 goto out;
7521
7522         if (intel_crtc->plane)
7523                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7524         else
7525                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7526         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7527         OUT_RING(MI_NOOP);
7528         OUT_RING(MI_DISPLAY_FLIP_I915 |
7529                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7530         OUT_RING(fb->pitches[0]);
7531         OUT_RING(obj->gtt_offset + offset);
7532         OUT_RING(MI_NOOP);
7533
7534         ADVANCE_LP_RING();
7535 out:
7536         return ret;
7537 }
7538
7539 static int intel_gen4_queue_flip(struct drm_device *dev,
7540                                  struct drm_crtc *crtc,
7541                                  struct drm_framebuffer *fb,
7542                                  struct drm_i915_gem_object *obj)
7543 {
7544         struct drm_i915_private *dev_priv = dev->dev_private;
7545         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7546         uint32_t pf, pipesrc;
7547         int ret;
7548
7549         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7550         if (ret)
7551                 goto out;
7552
7553         ret = BEGIN_LP_RING(4);
7554         if (ret)
7555                 goto out;
7556
7557         /* i965+ uses the linear or tiled offsets from the
7558          * Display Registers (which do not change across a page-flip)
7559          * so we need only reprogram the base address.
7560          */
7561         OUT_RING(MI_DISPLAY_FLIP |
7562                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7563         OUT_RING(fb->pitches[0]);
7564         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7565
7566         /* XXX Enabling the panel-fitter across page-flip is so far
7567          * untested on non-native modes, so ignore it for now.
7568          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7569          */
7570         pf = 0;
7571         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7572         OUT_RING(pf | pipesrc);
7573         ADVANCE_LP_RING();
7574 out:
7575         return ret;
7576 }
7577
7578 static int intel_gen6_queue_flip(struct drm_device *dev,
7579                                  struct drm_crtc *crtc,
7580                                  struct drm_framebuffer *fb,
7581                                  struct drm_i915_gem_object *obj)
7582 {
7583         struct drm_i915_private *dev_priv = dev->dev_private;
7584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7585         uint32_t pf, pipesrc;
7586         int ret;
7587
7588         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7589         if (ret)
7590                 goto out;
7591
7592         ret = BEGIN_LP_RING(4);
7593         if (ret)
7594                 goto out;
7595
7596         OUT_RING(MI_DISPLAY_FLIP |
7597                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7598         OUT_RING(fb->pitches[0] | obj->tiling_mode);
7599         OUT_RING(obj->gtt_offset);
7600
7601         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7602         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7603         OUT_RING(pf | pipesrc);
7604         ADVANCE_LP_RING();
7605 out:
7606         return ret;
7607 }
7608
7609 /*
7610  * On gen7 we currently use the blit ring because (in early silicon at least)
7611  * the render ring doesn't give us interrpts for page flip completion, which
7612  * means clients will hang after the first flip is queued.  Fortunately the
7613  * blit ring generates interrupts properly, so use it instead.
7614  */
7615 static int intel_gen7_queue_flip(struct drm_device *dev,
7616                                  struct drm_crtc *crtc,
7617                                  struct drm_framebuffer *fb,
7618                                  struct drm_i915_gem_object *obj)
7619 {
7620         struct drm_i915_private *dev_priv = dev->dev_private;
7621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7622         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7623         int ret;
7624
7625         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7626         if (ret)
7627                 goto out;
7628
7629         ret = intel_ring_begin(ring, 4);
7630         if (ret)
7631                 goto out;
7632
7633         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7634         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7635         intel_ring_emit(ring, (obj->gtt_offset));
7636         intel_ring_emit(ring, (MI_NOOP));
7637         intel_ring_advance(ring);
7638 out:
7639         return ret;
7640 }
7641
7642 static int intel_default_queue_flip(struct drm_device *dev,
7643                                     struct drm_crtc *crtc,
7644                                     struct drm_framebuffer *fb,
7645                                     struct drm_i915_gem_object *obj)
7646 {
7647         return -ENODEV;
7648 }
7649
7650 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7651                                 struct drm_framebuffer *fb,
7652                                 struct drm_pending_vblank_event *event)
7653 {
7654         struct drm_device *dev = crtc->dev;
7655         struct drm_i915_private *dev_priv = dev->dev_private;
7656         struct intel_framebuffer *intel_fb;
7657         struct drm_i915_gem_object *obj;
7658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7659         struct intel_unpin_work *work;
7660         unsigned long flags;
7661         int ret;
7662
7663         work = kzalloc(sizeof *work, GFP_KERNEL);
7664         if (work == NULL)
7665                 return -ENOMEM;
7666
7667         work->event = event;
7668         work->dev = crtc->dev;
7669         intel_fb = to_intel_framebuffer(crtc->fb);
7670         work->old_fb_obj = intel_fb->obj;
7671         INIT_WORK(&work->work, intel_unpin_work_fn);
7672
7673         ret = drm_vblank_get(dev, intel_crtc->pipe);
7674         if (ret)
7675                 goto free_work;
7676
7677         /* We borrow the event spin lock for protecting unpin_work */
7678         spin_lock_irqsave(&dev->event_lock, flags);
7679         if (intel_crtc->unpin_work) {
7680                 spin_unlock_irqrestore(&dev->event_lock, flags);
7681                 kfree(work);
7682                 drm_vblank_put(dev, intel_crtc->pipe);
7683
7684                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7685                 return -EBUSY;
7686         }
7687         intel_crtc->unpin_work = work;
7688         spin_unlock_irqrestore(&dev->event_lock, flags);
7689
7690         intel_fb = to_intel_framebuffer(fb);
7691         obj = intel_fb->obj;
7692
7693         mutex_lock(&dev->struct_mutex);
7694
7695         /* Reference the objects for the scheduled work. */
7696         drm_gem_object_reference(&work->old_fb_obj->base);
7697         drm_gem_object_reference(&obj->base);
7698
7699         crtc->fb = fb;
7700
7701         work->pending_flip_obj = obj;
7702
7703         work->enable_stall_check = true;
7704
7705         /* Block clients from rendering to the new back buffer until
7706          * the flip occurs and the object is no longer visible.
7707          */
7708         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7709
7710         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7711         if (ret)
7712                 goto cleanup_pending;
7713
7714         intel_disable_fbc(dev);
7715         mutex_unlock(&dev->struct_mutex);
7716
7717         trace_i915_flip_request(intel_crtc->plane, obj);
7718
7719         return 0;
7720
7721 cleanup_pending:
7722         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7723         drm_gem_object_unreference(&work->old_fb_obj->base);
7724         drm_gem_object_unreference(&obj->base);
7725         mutex_unlock(&dev->struct_mutex);
7726
7727         spin_lock_irqsave(&dev->event_lock, flags);
7728         intel_crtc->unpin_work = NULL;
7729         spin_unlock_irqrestore(&dev->event_lock, flags);
7730
7731         drm_vblank_put(dev, intel_crtc->pipe);
7732 free_work:
7733         kfree(work);
7734
7735         return ret;
7736 }
7737
7738 static void intel_sanitize_modesetting(struct drm_device *dev,
7739                                        int pipe, int plane)
7740 {
7741         struct drm_i915_private *dev_priv = dev->dev_private;
7742         u32 reg, val;
7743
7744         if (HAS_PCH_SPLIT(dev))
7745                 return;
7746
7747         /* Who knows what state these registers were left in by the BIOS or
7748          * grub?
7749          *
7750          * If we leave the registers in a conflicting state (e.g. with the
7751          * display plane reading from the other pipe than the one we intend
7752          * to use) then when we attempt to teardown the active mode, we will
7753          * not disable the pipes and planes in the correct order -- leaving
7754          * a plane reading from a disabled pipe and possibly leading to
7755          * undefined behaviour.
7756          */
7757
7758         reg = DSPCNTR(plane);
7759         val = I915_READ(reg);
7760
7761         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7762                 return;
7763         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7764                 return;
7765
7766         /* This display plane is active and attached to the other CPU pipe. */
7767         pipe = !pipe;
7768
7769         /* Disable the plane and wait for it to stop reading from the pipe. */
7770         intel_disable_plane(dev_priv, plane, pipe);
7771         intel_disable_pipe(dev_priv, pipe);
7772 }
7773
7774 static void intel_crtc_reset(struct drm_crtc *crtc)
7775 {
7776         struct drm_device *dev = crtc->dev;
7777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7778
7779         /* Reset flags back to the 'unknown' status so that they
7780          * will be correctly set on the initial modeset.
7781          */
7782         intel_crtc->dpms_mode = -1;
7783
7784         /* We need to fix up any BIOS configuration that conflicts with
7785          * our expectations.
7786          */
7787         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7788 }
7789
7790 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7791         .dpms = intel_crtc_dpms,
7792         .mode_fixup = intel_crtc_mode_fixup,
7793         .mode_set = intel_crtc_mode_set,
7794         .mode_set_base = intel_pipe_set_base,
7795         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7796         .load_lut = intel_crtc_load_lut,
7797         .disable = intel_crtc_disable,
7798 };
7799
7800 static const struct drm_crtc_funcs intel_crtc_funcs = {
7801         .reset = intel_crtc_reset,
7802         .cursor_set = intel_crtc_cursor_set,
7803         .cursor_move = intel_crtc_cursor_move,
7804         .gamma_set = intel_crtc_gamma_set,
7805         .set_config = drm_crtc_helper_set_config,
7806         .destroy = intel_crtc_destroy,
7807         .page_flip = intel_crtc_page_flip,
7808 };
7809
7810 static void intel_crtc_init(struct drm_device *dev, int pipe)
7811 {
7812         drm_i915_private_t *dev_priv = dev->dev_private;
7813         struct intel_crtc *intel_crtc;
7814         int i;
7815
7816         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7817         if (intel_crtc == NULL)
7818                 return;
7819
7820         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7821
7822         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7823         for (i = 0; i < 256; i++) {
7824                 intel_crtc->lut_r[i] = i;
7825                 intel_crtc->lut_g[i] = i;
7826                 intel_crtc->lut_b[i] = i;
7827         }
7828
7829         /* Swap pipes & planes for FBC on pre-965 */
7830         intel_crtc->pipe = pipe;
7831         intel_crtc->plane = pipe;
7832         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7833                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7834                 intel_crtc->plane = !pipe;
7835         }
7836
7837         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7838                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7839         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7840         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7841
7842         intel_crtc_reset(&intel_crtc->base);
7843         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7844         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7845
7846         if (HAS_PCH_SPLIT(dev)) {
7847                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7848                         intel_crtc->no_pll = true;
7849                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7850                 intel_helper_funcs.commit = ironlake_crtc_commit;
7851         } else {
7852                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7853                 intel_helper_funcs.commit = i9xx_crtc_commit;
7854         }
7855
7856         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7857
7858         intel_crtc->busy = false;
7859
7860         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7861                     (unsigned long)intel_crtc);
7862 }
7863
7864 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7865                                 struct drm_file *file)
7866 {
7867         drm_i915_private_t *dev_priv = dev->dev_private;
7868         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7869         struct drm_mode_object *drmmode_obj;
7870         struct intel_crtc *crtc;
7871
7872         if (!dev_priv) {
7873                 DRM_ERROR("called with no initialization\n");
7874                 return -EINVAL;
7875         }
7876
7877         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7878                         DRM_MODE_OBJECT_CRTC);
7879
7880         if (!drmmode_obj) {
7881                 DRM_ERROR("no such CRTC id\n");
7882                 return -EINVAL;
7883         }
7884
7885         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7886         pipe_from_crtc_id->pipe = crtc->pipe;
7887
7888         return 0;
7889 }
7890
7891 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7892 {
7893         struct intel_encoder *encoder;
7894         int index_mask = 0;
7895         int entry = 0;
7896
7897         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7898                 if (type_mask & encoder->clone_mask)
7899                         index_mask |= (1 << entry);
7900                 entry++;
7901         }
7902
7903         return index_mask;
7904 }
7905
7906 static bool has_edp_a(struct drm_device *dev)
7907 {
7908         struct drm_i915_private *dev_priv = dev->dev_private;
7909
7910         if (!IS_MOBILE(dev))
7911                 return false;
7912
7913         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7914                 return false;
7915
7916         if (IS_GEN5(dev) &&
7917             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7918                 return false;
7919
7920         return true;
7921 }
7922
7923 static void intel_setup_outputs(struct drm_device *dev)
7924 {
7925         struct drm_i915_private *dev_priv = dev->dev_private;
7926         struct intel_encoder *encoder;
7927         bool dpd_is_edp = false;
7928         bool has_lvds;
7929
7930         has_lvds = intel_lvds_init(dev);
7931         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7932                 /* disable the panel fitter on everything but LVDS */
7933                 I915_WRITE(PFIT_CONTROL, 0);
7934         }
7935
7936         if (HAS_PCH_SPLIT(dev)) {
7937                 dpd_is_edp = intel_dpd_is_edp(dev);
7938
7939                 if (has_edp_a(dev))
7940                         intel_dp_init(dev, DP_A);
7941
7942                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7943                         intel_dp_init(dev, PCH_DP_D);
7944         }
7945
7946         intel_crt_init(dev);
7947
7948         if (HAS_PCH_SPLIT(dev)) {
7949                 int found;
7950
7951                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7952                         /* PCH SDVOB multiplex with HDMIB */
7953                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
7954                         if (!found)
7955                                 intel_hdmi_init(dev, HDMIB);
7956                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7957                                 intel_dp_init(dev, PCH_DP_B);
7958                 }
7959
7960                 if (I915_READ(HDMIC) & PORT_DETECTED)
7961                         intel_hdmi_init(dev, HDMIC);
7962
7963                 if (I915_READ(HDMID) & PORT_DETECTED)
7964                         intel_hdmi_init(dev, HDMID);
7965
7966                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7967                         intel_dp_init(dev, PCH_DP_C);
7968
7969                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7970                         intel_dp_init(dev, PCH_DP_D);
7971
7972         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7973                 bool found = false;
7974
7975                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7976                         DRM_DEBUG_KMS("probing SDVOB\n");
7977                         found = intel_sdvo_init(dev, SDVOB, true);
7978                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7979                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7980                                 intel_hdmi_init(dev, SDVOB);
7981                         }
7982
7983                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7984                                 DRM_DEBUG_KMS("probing DP_B\n");
7985                                 intel_dp_init(dev, DP_B);
7986                         }
7987                 }
7988
7989                 /* Before G4X SDVOC doesn't have its own detect register */
7990
7991                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7992                         DRM_DEBUG_KMS("probing SDVOC\n");
7993                         found = intel_sdvo_init(dev, SDVOC, false);
7994                 }
7995
7996                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7997
7998                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7999                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8000                                 intel_hdmi_init(dev, SDVOC);
8001                         }
8002                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8003                                 DRM_DEBUG_KMS("probing DP_C\n");
8004                                 intel_dp_init(dev, DP_C);
8005                         }
8006                 }
8007
8008                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8009                     (I915_READ(DP_D) & DP_DETECTED)) {
8010                         DRM_DEBUG_KMS("probing DP_D\n");
8011                         intel_dp_init(dev, DP_D);
8012                 }
8013         } else if (IS_GEN2(dev))
8014                 intel_dvo_init(dev);
8015
8016         if (SUPPORTS_TV(dev))
8017                 intel_tv_init(dev);
8018
8019         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8020                 encoder->base.possible_crtcs = encoder->crtc_mask;
8021                 encoder->base.possible_clones =
8022                         intel_encoder_clones(dev, encoder->clone_mask);
8023         }
8024
8025         /* disable all the possible outputs/crtcs before entering KMS mode */
8026         drm_helper_disable_unused_functions(dev);
8027
8028         if (HAS_PCH_SPLIT(dev))
8029                 ironlake_init_pch_refclk(dev);
8030 }
8031
8032 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8033 {
8034         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8035
8036         drm_framebuffer_cleanup(fb);
8037         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8038
8039         kfree(intel_fb);
8040 }
8041
8042 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8043                                                 struct drm_file *file,
8044                                                 unsigned int *handle)
8045 {
8046         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8047         struct drm_i915_gem_object *obj = intel_fb->obj;
8048
8049         return drm_gem_handle_create(file, &obj->base, handle);
8050 }
8051
8052 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8053         .destroy = intel_user_framebuffer_destroy,
8054         .create_handle = intel_user_framebuffer_create_handle,
8055 };
8056
8057 int intel_framebuffer_init(struct drm_device *dev,
8058                            struct intel_framebuffer *intel_fb,
8059                            struct drm_mode_fb_cmd2 *mode_cmd,
8060                            struct drm_i915_gem_object *obj)
8061 {
8062         int ret;
8063
8064         if (obj->tiling_mode == I915_TILING_Y)
8065                 return -EINVAL;
8066
8067         if (mode_cmd->pitches[0] & 63)
8068                 return -EINVAL;
8069
8070         switch (mode_cmd->pixel_format) {
8071         case DRM_FORMAT_RGB332:
8072         case DRM_FORMAT_RGB565:
8073         case DRM_FORMAT_XRGB8888:
8074         case DRM_FORMAT_ARGB8888:
8075         case DRM_FORMAT_XRGB2101010:
8076         case DRM_FORMAT_ARGB2101010:
8077                 /* RGB formats are common across chipsets */
8078                 break;
8079         case DRM_FORMAT_YUYV:
8080         case DRM_FORMAT_UYVY:
8081         case DRM_FORMAT_YVYU:
8082         case DRM_FORMAT_VYUY:
8083                 break;
8084         default:
8085                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8086                                 mode_cmd->pixel_format);
8087                 return -EINVAL;
8088         }
8089
8090         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8091         if (ret) {
8092                 DRM_ERROR("framebuffer init failed %d\n", ret);
8093                 return ret;
8094         }
8095
8096         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8097         intel_fb->obj = obj;
8098         return 0;
8099 }
8100
8101 static struct drm_framebuffer *
8102 intel_user_framebuffer_create(struct drm_device *dev,
8103                               struct drm_file *filp,
8104                               struct drm_mode_fb_cmd2 *mode_cmd)
8105 {
8106         struct drm_i915_gem_object *obj;
8107
8108         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8109                                                 mode_cmd->handles[0]));
8110         if (&obj->base == NULL)
8111                 return ERR_PTR(-ENOENT);
8112
8113         return intel_framebuffer_create(dev, mode_cmd, obj);
8114 }
8115
8116 static const struct drm_mode_config_funcs intel_mode_funcs = {
8117         .fb_create = intel_user_framebuffer_create,
8118         .output_poll_changed = intel_fb_output_poll_changed,
8119 };
8120
8121 static struct drm_i915_gem_object *
8122 intel_alloc_context_page(struct drm_device *dev)
8123 {
8124         struct drm_i915_gem_object *ctx;
8125         int ret;
8126
8127         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8128
8129         ctx = i915_gem_alloc_object(dev, 4096);
8130         if (!ctx) {
8131                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8132                 return NULL;
8133         }
8134
8135         ret = i915_gem_object_pin(ctx, 4096, true);
8136         if (ret) {
8137                 DRM_ERROR("failed to pin power context: %d\n", ret);
8138                 goto err_unref;
8139         }
8140
8141         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
8142         if (ret) {
8143                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8144                 goto err_unpin;
8145         }
8146
8147         return ctx;
8148
8149 err_unpin:
8150         i915_gem_object_unpin(ctx);
8151 err_unref:
8152         drm_gem_object_unreference(&ctx->base);
8153         mutex_unlock(&dev->struct_mutex);
8154         return NULL;
8155 }
8156
8157 bool ironlake_set_drps(struct drm_device *dev, u8 val)
8158 {
8159         struct drm_i915_private *dev_priv = dev->dev_private;
8160         u16 rgvswctl;
8161
8162         rgvswctl = I915_READ16(MEMSWCTL);
8163         if (rgvswctl & MEMCTL_CMD_STS) {
8164                 DRM_DEBUG("gpu busy, RCS change rejected\n");
8165                 return false; /* still busy with another command */
8166         }
8167
8168         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8169                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8170         I915_WRITE16(MEMSWCTL, rgvswctl);
8171         POSTING_READ16(MEMSWCTL);
8172
8173         rgvswctl |= MEMCTL_CMD_STS;
8174         I915_WRITE16(MEMSWCTL, rgvswctl);
8175
8176         return true;
8177 }
8178
8179 void ironlake_enable_drps(struct drm_device *dev)
8180 {
8181         struct drm_i915_private *dev_priv = dev->dev_private;
8182         u32 rgvmodectl = I915_READ(MEMMODECTL);
8183         u8 fmax, fmin, fstart, vstart;
8184
8185         /* Enable temp reporting */
8186         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8187         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8188
8189         /* 100ms RC evaluation intervals */
8190         I915_WRITE(RCUPEI, 100000);
8191         I915_WRITE(RCDNEI, 100000);
8192
8193         /* Set max/min thresholds to 90ms and 80ms respectively */
8194         I915_WRITE(RCBMAXAVG, 90000);
8195         I915_WRITE(RCBMINAVG, 80000);
8196
8197         I915_WRITE(MEMIHYST, 1);
8198
8199         /* Set up min, max, and cur for interrupt handling */
8200         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8201         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8202         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8203                 MEMMODE_FSTART_SHIFT;
8204
8205         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8206                 PXVFREQ_PX_SHIFT;
8207
8208         dev_priv->fmax = fmax; /* IPS callback will increase this */
8209         dev_priv->fstart = fstart;
8210
8211         dev_priv->max_delay = fstart;
8212         dev_priv->min_delay = fmin;
8213         dev_priv->cur_delay = fstart;
8214
8215         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8216                          fmax, fmin, fstart);
8217
8218         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8219
8220         /*
8221          * Interrupts will be enabled in ironlake_irq_postinstall
8222          */
8223
8224         I915_WRITE(VIDSTART, vstart);
8225         POSTING_READ(VIDSTART);
8226
8227         rgvmodectl |= MEMMODE_SWMODE_EN;
8228         I915_WRITE(MEMMODECTL, rgvmodectl);
8229
8230         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8231                 DRM_ERROR("stuck trying to change perf mode\n");
8232         msleep(1);
8233
8234         ironlake_set_drps(dev, fstart);
8235
8236         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8237                 I915_READ(0x112e0);
8238         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8239         dev_priv->last_count2 = I915_READ(0x112f4);
8240         getrawmonotonic(&dev_priv->last_time2);
8241 }
8242
8243 void ironlake_disable_drps(struct drm_device *dev)
8244 {
8245         struct drm_i915_private *dev_priv = dev->dev_private;
8246         u16 rgvswctl = I915_READ16(MEMSWCTL);
8247
8248         /* Ack interrupts, disable EFC interrupt */
8249         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8250         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8251         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8252         I915_WRITE(DEIIR, DE_PCU_EVENT);
8253         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8254
8255         /* Go back to the starting frequency */
8256         ironlake_set_drps(dev, dev_priv->fstart);
8257         msleep(1);
8258         rgvswctl |= MEMCTL_CMD_STS;
8259         I915_WRITE(MEMSWCTL, rgvswctl);
8260         msleep(1);
8261
8262 }
8263
8264 void gen6_set_rps(struct drm_device *dev, u8 val)
8265 {
8266         struct drm_i915_private *dev_priv = dev->dev_private;
8267         u32 swreq;
8268
8269         swreq = (val & 0x3ff) << 25;
8270         I915_WRITE(GEN6_RPNSWREQ, swreq);
8271 }
8272
8273 void gen6_disable_rps(struct drm_device *dev)
8274 {
8275         struct drm_i915_private *dev_priv = dev->dev_private;
8276
8277         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8278         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8279         I915_WRITE(GEN6_PMIER, 0);
8280         /* Complete PM interrupt masking here doesn't race with the rps work
8281          * item again unmasking PM interrupts because that is using a different
8282          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8283          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8284
8285         spin_lock_irq(&dev_priv->rps_lock);
8286         dev_priv->pm_iir = 0;
8287         spin_unlock_irq(&dev_priv->rps_lock);
8288
8289         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8290 }
8291
8292 static unsigned long intel_pxfreq(u32 vidfreq)
8293 {
8294         unsigned long freq;
8295         int div = (vidfreq & 0x3f0000) >> 16;
8296         int post = (vidfreq & 0x3000) >> 12;
8297         int pre = (vidfreq & 0x7);
8298
8299         if (!pre)
8300                 return 0;
8301
8302         freq = ((div * 133333) / ((1<<post) * pre));
8303
8304         return freq;
8305 }
8306
8307 void intel_init_emon(struct drm_device *dev)
8308 {
8309         struct drm_i915_private *dev_priv = dev->dev_private;
8310         u32 lcfuse;
8311         u8 pxw[16];
8312         int i;
8313
8314         /* Disable to program */
8315         I915_WRITE(ECR, 0);
8316         POSTING_READ(ECR);
8317
8318         /* Program energy weights for various events */
8319         I915_WRITE(SDEW, 0x15040d00);
8320         I915_WRITE(CSIEW0, 0x007f0000);
8321         I915_WRITE(CSIEW1, 0x1e220004);
8322         I915_WRITE(CSIEW2, 0x04000004);
8323
8324         for (i = 0; i < 5; i++)
8325                 I915_WRITE(PEW + (i * 4), 0);
8326         for (i = 0; i < 3; i++)
8327                 I915_WRITE(DEW + (i * 4), 0);
8328
8329         /* Program P-state weights to account for frequency power adjustment */
8330         for (i = 0; i < 16; i++) {
8331                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8332                 unsigned long freq = intel_pxfreq(pxvidfreq);
8333                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8334                         PXVFREQ_PX_SHIFT;
8335                 unsigned long val;
8336
8337                 val = vid * vid;
8338                 val *= (freq / 1000);
8339                 val *= 255;
8340                 val /= (127*127*900);
8341                 if (val > 0xff)
8342                         DRM_ERROR("bad pxval: %ld\n", val);
8343                 pxw[i] = val;
8344         }
8345         /* Render standby states get 0 weight */
8346         pxw[14] = 0;
8347         pxw[15] = 0;
8348
8349         for (i = 0; i < 4; i++) {
8350                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8351                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8352                 I915_WRITE(PXW + (i * 4), val);
8353         }
8354
8355         /* Adjust magic regs to magic values (more experimental results) */
8356         I915_WRITE(OGW0, 0);
8357         I915_WRITE(OGW1, 0);
8358         I915_WRITE(EG0, 0x00007f00);
8359         I915_WRITE(EG1, 0x0000000e);
8360         I915_WRITE(EG2, 0x000e0000);
8361         I915_WRITE(EG3, 0x68000300);
8362         I915_WRITE(EG4, 0x42000000);
8363         I915_WRITE(EG5, 0x00140031);
8364         I915_WRITE(EG6, 0);
8365         I915_WRITE(EG7, 0);
8366
8367         for (i = 0; i < 8; i++)
8368                 I915_WRITE(PXWL + (i * 4), 0);
8369
8370         /* Enable PMON + select events */
8371         I915_WRITE(ECR, 0x80000019);
8372
8373         lcfuse = I915_READ(LCFUSE02);
8374
8375         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8376 }
8377
8378 static bool intel_enable_rc6(struct drm_device *dev)
8379 {
8380         /*
8381          * Respect the kernel parameter if it is set
8382          */
8383         if (i915_enable_rc6 >= 0)
8384                 return i915_enable_rc6;
8385
8386         /*
8387          * Disable RC6 on Ironlake
8388          */
8389         if (INTEL_INFO(dev)->gen == 5)
8390                 return 0;
8391
8392         /*
8393          * Disable rc6 on Sandybridge
8394          */
8395         if (INTEL_INFO(dev)->gen == 6) {
8396                 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8397                 return 0;
8398         }
8399         DRM_DEBUG_DRIVER("RC6 enabled\n");
8400         return 1;
8401 }
8402
8403 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8404 {
8405         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8406         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8407         u32 pcu_mbox, rc6_mask = 0;
8408         u32 gtfifodbg;
8409         int cur_freq, min_freq, max_freq;
8410         int i;
8411
8412         /* Here begins a magic sequence of register writes to enable
8413          * auto-downclocking.
8414          *
8415          * Perhaps there might be some value in exposing these to
8416          * userspace...
8417          */
8418         I915_WRITE(GEN6_RC_STATE, 0);
8419         mutex_lock(&dev_priv->dev->struct_mutex);
8420
8421         /* Clear the DBG now so we don't confuse earlier errors */
8422         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8423                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8424                 I915_WRITE(GTFIFODBG, gtfifodbg);
8425         }
8426
8427         gen6_gt_force_wake_get(dev_priv);
8428
8429         /* disable the counters and set deterministic thresholds */
8430         I915_WRITE(GEN6_RC_CONTROL, 0);
8431
8432         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8433         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8434         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8435         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8436         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8437
8438         for (i = 0; i < I915_NUM_RINGS; i++)
8439                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8440
8441         I915_WRITE(GEN6_RC_SLEEP, 0);
8442         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8443         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8444         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8445         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8446
8447         if (intel_enable_rc6(dev_priv->dev))
8448                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8449                         GEN6_RC_CTL_RC6_ENABLE;
8450
8451         I915_WRITE(GEN6_RC_CONTROL,
8452                    rc6_mask |
8453                    GEN6_RC_CTL_EI_MODE(1) |
8454                    GEN6_RC_CTL_HW_ENABLE);
8455
8456         I915_WRITE(GEN6_RPNSWREQ,
8457                    GEN6_FREQUENCY(10) |
8458                    GEN6_OFFSET(0) |
8459                    GEN6_AGGRESSIVE_TURBO);
8460         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8461                    GEN6_FREQUENCY(12));
8462
8463         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8464         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8465                    18 << 24 |
8466                    6 << 16);
8467         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8468         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8469         I915_WRITE(GEN6_RP_UP_EI, 100000);
8470         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8471         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8472         I915_WRITE(GEN6_RP_CONTROL,
8473                    GEN6_RP_MEDIA_TURBO |
8474                    GEN6_RP_MEDIA_HW_MODE |
8475                    GEN6_RP_MEDIA_IS_GFX |
8476                    GEN6_RP_ENABLE |
8477                    GEN6_RP_UP_BUSY_AVG |
8478                    GEN6_RP_DOWN_IDLE_CONT);
8479
8480         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8481                      500))
8482                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8483
8484         I915_WRITE(GEN6_PCODE_DATA, 0);
8485         I915_WRITE(GEN6_PCODE_MAILBOX,
8486                    GEN6_PCODE_READY |
8487                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8488         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8489                      500))
8490                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8491
8492         min_freq = (rp_state_cap & 0xff0000) >> 16;
8493         max_freq = rp_state_cap & 0xff;
8494         cur_freq = (gt_perf_status & 0xff00) >> 8;
8495
8496         /* Check for overclock support */
8497         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8498                      500))
8499                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8500         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8501         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8502         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8503                      500))
8504                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8505         if (pcu_mbox & (1<<31)) { /* OC supported */
8506                 max_freq = pcu_mbox & 0xff;
8507                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8508         }
8509
8510         /* In units of 100MHz */
8511         dev_priv->max_delay = max_freq;
8512         dev_priv->min_delay = min_freq;
8513         dev_priv->cur_delay = cur_freq;
8514
8515         /* requires MSI enabled */
8516         I915_WRITE(GEN6_PMIER,
8517                    GEN6_PM_MBOX_EVENT |
8518                    GEN6_PM_THERMAL_EVENT |
8519                    GEN6_PM_RP_DOWN_TIMEOUT |
8520                    GEN6_PM_RP_UP_THRESHOLD |
8521                    GEN6_PM_RP_DOWN_THRESHOLD |
8522                    GEN6_PM_RP_UP_EI_EXPIRED |
8523                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8524         spin_lock_irq(&dev_priv->rps_lock);
8525         WARN_ON(dev_priv->pm_iir != 0);
8526         I915_WRITE(GEN6_PMIMR, 0);
8527         spin_unlock_irq(&dev_priv->rps_lock);
8528         /* enable all PM interrupts */
8529         I915_WRITE(GEN6_PMINTRMSK, 0);
8530
8531         gen6_gt_force_wake_put(dev_priv);
8532         mutex_unlock(&dev_priv->dev->struct_mutex);
8533 }
8534
8535 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8536 {
8537         int min_freq = 15;
8538         int gpu_freq, ia_freq, max_ia_freq;
8539         int scaling_factor = 180;
8540
8541         max_ia_freq = cpufreq_quick_get_max(0);
8542         /*
8543          * Default to measured freq if none found, PCU will ensure we don't go
8544          * over
8545          */
8546         if (!max_ia_freq)
8547                 max_ia_freq = tsc_khz;
8548
8549         /* Convert from kHz to MHz */
8550         max_ia_freq /= 1000;
8551
8552         mutex_lock(&dev_priv->dev->struct_mutex);
8553
8554         /*
8555          * For each potential GPU frequency, load a ring frequency we'd like
8556          * to use for memory access.  We do this by specifying the IA frequency
8557          * the PCU should use as a reference to determine the ring frequency.
8558          */
8559         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8560              gpu_freq--) {
8561                 int diff = dev_priv->max_delay - gpu_freq;
8562
8563                 /*
8564                  * For GPU frequencies less than 750MHz, just use the lowest
8565                  * ring freq.
8566                  */
8567                 if (gpu_freq < min_freq)
8568                         ia_freq = 800;
8569                 else
8570                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8571                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8572
8573                 I915_WRITE(GEN6_PCODE_DATA,
8574                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8575                            gpu_freq);
8576                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8577                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8578                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8579                               GEN6_PCODE_READY) == 0, 10)) {
8580                         DRM_ERROR("pcode write of freq table timed out\n");
8581                         continue;
8582                 }
8583         }
8584
8585         mutex_unlock(&dev_priv->dev->struct_mutex);
8586 }
8587
8588 static void ironlake_init_clock_gating(struct drm_device *dev)
8589 {
8590         struct drm_i915_private *dev_priv = dev->dev_private;
8591         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8592
8593         /* Required for FBC */
8594         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8595                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8596                 DPFDUNIT_CLOCK_GATE_DISABLE;
8597         /* Required for CxSR */
8598         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8599
8600         I915_WRITE(PCH_3DCGDIS0,
8601                    MARIUNIT_CLOCK_GATE_DISABLE |
8602                    SVSMUNIT_CLOCK_GATE_DISABLE);
8603         I915_WRITE(PCH_3DCGDIS1,
8604                    VFMUNIT_CLOCK_GATE_DISABLE);
8605
8606         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8607
8608         /*
8609          * According to the spec the following bits should be set in
8610          * order to enable memory self-refresh
8611          * The bit 22/21 of 0x42004
8612          * The bit 5 of 0x42020
8613          * The bit 15 of 0x45000
8614          */
8615         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8616                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8617                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8618         I915_WRITE(ILK_DSPCLK_GATE,
8619                    (I915_READ(ILK_DSPCLK_GATE) |
8620                     ILK_DPARB_CLK_GATE));
8621         I915_WRITE(DISP_ARB_CTL,
8622                    (I915_READ(DISP_ARB_CTL) |
8623                     DISP_FBC_WM_DIS));
8624         I915_WRITE(WM3_LP_ILK, 0);
8625         I915_WRITE(WM2_LP_ILK, 0);
8626         I915_WRITE(WM1_LP_ILK, 0);
8627
8628         /*
8629          * Based on the document from hardware guys the following bits
8630          * should be set unconditionally in order to enable FBC.
8631          * The bit 22 of 0x42000
8632          * The bit 22 of 0x42004
8633          * The bit 7,8,9 of 0x42020.
8634          */
8635         if (IS_IRONLAKE_M(dev)) {
8636                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8637                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8638                            ILK_FBCQ_DIS);
8639                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8640                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8641                            ILK_DPARB_GATE);
8642                 I915_WRITE(ILK_DSPCLK_GATE,
8643                            I915_READ(ILK_DSPCLK_GATE) |
8644                            ILK_DPFC_DIS1 |
8645                            ILK_DPFC_DIS2 |
8646                            ILK_CLK_FBC);
8647         }
8648
8649         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8650                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8651                    ILK_ELPIN_409_SELECT);
8652         I915_WRITE(_3D_CHICKEN2,
8653                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8654                    _3D_CHICKEN2_WM_READ_PIPELINED);
8655 }
8656
8657 static void gen6_init_clock_gating(struct drm_device *dev)
8658 {
8659         struct drm_i915_private *dev_priv = dev->dev_private;
8660         int pipe;
8661         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8662
8663         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8664
8665         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8666                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8667                    ILK_ELPIN_409_SELECT);
8668
8669         I915_WRITE(WM3_LP_ILK, 0);
8670         I915_WRITE(WM2_LP_ILK, 0);
8671         I915_WRITE(WM1_LP_ILK, 0);
8672
8673         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8674          * gating disable must be set.  Failure to set it results in
8675          * flickering pixels due to Z write ordering failures after
8676          * some amount of runtime in the Mesa "fire" demo, and Unigine
8677          * Sanctuary and Tropics, and apparently anything else with
8678          * alpha test or pixel discard.
8679          *
8680          * According to the spec, bit 11 (RCCUNIT) must also be set,
8681          * but we didn't debug actual testcases to find it out.
8682          */
8683         I915_WRITE(GEN6_UCGCTL2,
8684                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8685                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8686
8687         /*
8688          * According to the spec the following bits should be
8689          * set in order to enable memory self-refresh and fbc:
8690          * The bit21 and bit22 of 0x42000
8691          * The bit21 and bit22 of 0x42004
8692          * The bit5 and bit7 of 0x42020
8693          * The bit14 of 0x70180
8694          * The bit14 of 0x71180
8695          */
8696         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8697                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8698                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8699         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8700                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8701                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8702         I915_WRITE(ILK_DSPCLK_GATE,
8703                    I915_READ(ILK_DSPCLK_GATE) |
8704                    ILK_DPARB_CLK_GATE  |
8705                    ILK_DPFD_CLK_GATE);
8706
8707         for_each_pipe(pipe) {
8708                 I915_WRITE(DSPCNTR(pipe),
8709                            I915_READ(DSPCNTR(pipe)) |
8710                            DISPPLANE_TRICKLE_FEED_DISABLE);
8711                 intel_flush_display_plane(dev_priv, pipe);
8712         }
8713 }
8714
8715 static void ivybridge_init_clock_gating(struct drm_device *dev)
8716 {
8717         struct drm_i915_private *dev_priv = dev->dev_private;
8718         int pipe;
8719         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8720
8721         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8722
8723         I915_WRITE(WM3_LP_ILK, 0);
8724         I915_WRITE(WM2_LP_ILK, 0);
8725         I915_WRITE(WM1_LP_ILK, 0);
8726
8727         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8728
8729         I915_WRITE(IVB_CHICKEN3,
8730                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8731                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8732
8733         for_each_pipe(pipe) {
8734                 I915_WRITE(DSPCNTR(pipe),
8735                            I915_READ(DSPCNTR(pipe)) |
8736                            DISPPLANE_TRICKLE_FEED_DISABLE);
8737                 intel_flush_display_plane(dev_priv, pipe);
8738         }
8739 }
8740
8741 static void g4x_init_clock_gating(struct drm_device *dev)
8742 {
8743         struct drm_i915_private *dev_priv = dev->dev_private;
8744         uint32_t dspclk_gate;
8745
8746         I915_WRITE(RENCLK_GATE_D1, 0);
8747         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8748                    GS_UNIT_CLOCK_GATE_DISABLE |
8749                    CL_UNIT_CLOCK_GATE_DISABLE);
8750         I915_WRITE(RAMCLK_GATE_D, 0);
8751         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8752                 OVRUNIT_CLOCK_GATE_DISABLE |
8753                 OVCUNIT_CLOCK_GATE_DISABLE;
8754         if (IS_GM45(dev))
8755                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8756         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8757 }
8758
8759 static void crestline_init_clock_gating(struct drm_device *dev)
8760 {
8761         struct drm_i915_private *dev_priv = dev->dev_private;
8762
8763         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8764         I915_WRITE(RENCLK_GATE_D2, 0);
8765         I915_WRITE(DSPCLK_GATE_D, 0);
8766         I915_WRITE(RAMCLK_GATE_D, 0);
8767         I915_WRITE16(DEUC, 0);
8768 }
8769
8770 static void broadwater_init_clock_gating(struct drm_device *dev)
8771 {
8772         struct drm_i915_private *dev_priv = dev->dev_private;
8773
8774         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8775                    I965_RCC_CLOCK_GATE_DISABLE |
8776                    I965_RCPB_CLOCK_GATE_DISABLE |
8777                    I965_ISC_CLOCK_GATE_DISABLE |
8778                    I965_FBC_CLOCK_GATE_DISABLE);
8779         I915_WRITE(RENCLK_GATE_D2, 0);
8780 }
8781
8782 static void gen3_init_clock_gating(struct drm_device *dev)
8783 {
8784         struct drm_i915_private *dev_priv = dev->dev_private;
8785         u32 dstate = I915_READ(D_STATE);
8786
8787         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8788                 DSTATE_DOT_CLOCK_GATING;
8789         I915_WRITE(D_STATE, dstate);
8790 }
8791
8792 static void i85x_init_clock_gating(struct drm_device *dev)
8793 {
8794         struct drm_i915_private *dev_priv = dev->dev_private;
8795
8796         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8797 }
8798
8799 static void i830_init_clock_gating(struct drm_device *dev)
8800 {
8801         struct drm_i915_private *dev_priv = dev->dev_private;
8802
8803         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8804 }
8805
8806 static void ibx_init_clock_gating(struct drm_device *dev)
8807 {
8808         struct drm_i915_private *dev_priv = dev->dev_private;
8809
8810         /*
8811          * On Ibex Peak and Cougar Point, we need to disable clock
8812          * gating for the panel power sequencer or it will fail to
8813          * start up when no ports are active.
8814          */
8815         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8816 }
8817
8818 static void cpt_init_clock_gating(struct drm_device *dev)
8819 {
8820         struct drm_i915_private *dev_priv = dev->dev_private;
8821         int pipe;
8822
8823         /*
8824          * On Ibex Peak and Cougar Point, we need to disable clock
8825          * gating for the panel power sequencer or it will fail to
8826          * start up when no ports are active.
8827          */
8828         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8829         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8830                    DPLS_EDP_PPS_FIX_DIS);
8831         /* Without this, mode sets may fail silently on FDI */
8832         for_each_pipe(pipe)
8833                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8834 }
8835
8836 static void ironlake_teardown_rc6(struct drm_device *dev)
8837 {
8838         struct drm_i915_private *dev_priv = dev->dev_private;
8839
8840         if (dev_priv->renderctx) {
8841                 i915_gem_object_unpin(dev_priv->renderctx);
8842                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8843                 dev_priv->renderctx = NULL;
8844         }
8845
8846         if (dev_priv->pwrctx) {
8847                 i915_gem_object_unpin(dev_priv->pwrctx);
8848                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8849                 dev_priv->pwrctx = NULL;
8850         }
8851 }
8852
8853 static void ironlake_disable_rc6(struct drm_device *dev)
8854 {
8855         struct drm_i915_private *dev_priv = dev->dev_private;
8856
8857         if (I915_READ(PWRCTXA)) {
8858                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8859                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8860                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8861                          50);
8862
8863                 I915_WRITE(PWRCTXA, 0);
8864                 POSTING_READ(PWRCTXA);
8865
8866                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8867                 POSTING_READ(RSTDBYCTL);
8868         }
8869
8870         ironlake_teardown_rc6(dev);
8871 }
8872
8873 static int ironlake_setup_rc6(struct drm_device *dev)
8874 {
8875         struct drm_i915_private *dev_priv = dev->dev_private;
8876
8877         if (dev_priv->renderctx == NULL)
8878                 dev_priv->renderctx = intel_alloc_context_page(dev);
8879         if (!dev_priv->renderctx)
8880                 return -ENOMEM;
8881
8882         if (dev_priv->pwrctx == NULL)
8883                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8884         if (!dev_priv->pwrctx) {
8885                 ironlake_teardown_rc6(dev);
8886                 return -ENOMEM;
8887         }
8888
8889         return 0;
8890 }
8891
8892 void ironlake_enable_rc6(struct drm_device *dev)
8893 {
8894         struct drm_i915_private *dev_priv = dev->dev_private;
8895         int ret;
8896
8897         /* rc6 disabled by default due to repeated reports of hanging during
8898          * boot and resume.
8899          */
8900         if (!intel_enable_rc6(dev))
8901                 return;
8902
8903         mutex_lock(&dev->struct_mutex);
8904         ret = ironlake_setup_rc6(dev);
8905         if (ret) {
8906                 mutex_unlock(&dev->struct_mutex);
8907                 return;
8908         }
8909
8910         /*
8911          * GPU can automatically power down the render unit if given a page
8912          * to save state.
8913          */
8914         ret = BEGIN_LP_RING(6);
8915         if (ret) {
8916                 ironlake_teardown_rc6(dev);
8917                 mutex_unlock(&dev->struct_mutex);
8918                 return;
8919         }
8920
8921         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8922         OUT_RING(MI_SET_CONTEXT);
8923         OUT_RING(dev_priv->renderctx->gtt_offset |
8924                  MI_MM_SPACE_GTT |
8925                  MI_SAVE_EXT_STATE_EN |
8926                  MI_RESTORE_EXT_STATE_EN |
8927                  MI_RESTORE_INHIBIT);
8928         OUT_RING(MI_SUSPEND_FLUSH);
8929         OUT_RING(MI_NOOP);
8930         OUT_RING(MI_FLUSH);
8931         ADVANCE_LP_RING();
8932
8933         /*
8934          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8935          * does an implicit flush, combined with MI_FLUSH above, it should be
8936          * safe to assume that renderctx is valid
8937          */
8938         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8939         if (ret) {
8940                 DRM_ERROR("failed to enable ironlake power power savings\n");
8941                 ironlake_teardown_rc6(dev);
8942                 mutex_unlock(&dev->struct_mutex);
8943                 return;
8944         }
8945
8946         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8947         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8948         mutex_unlock(&dev->struct_mutex);
8949 }
8950
8951 void intel_init_clock_gating(struct drm_device *dev)
8952 {
8953         struct drm_i915_private *dev_priv = dev->dev_private;
8954
8955         dev_priv->display.init_clock_gating(dev);
8956
8957         if (dev_priv->display.init_pch_clock_gating)
8958                 dev_priv->display.init_pch_clock_gating(dev);
8959 }
8960
8961 /* Set up chip specific display functions */
8962 static void intel_init_display(struct drm_device *dev)
8963 {
8964         struct drm_i915_private *dev_priv = dev->dev_private;
8965
8966         /* We always want a DPMS function */
8967         if (HAS_PCH_SPLIT(dev)) {
8968                 dev_priv->display.dpms = ironlake_crtc_dpms;
8969                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8970                 dev_priv->display.update_plane = ironlake_update_plane;
8971         } else {
8972                 dev_priv->display.dpms = i9xx_crtc_dpms;
8973                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8974                 dev_priv->display.update_plane = i9xx_update_plane;
8975         }
8976
8977         if (I915_HAS_FBC(dev)) {
8978                 if (HAS_PCH_SPLIT(dev)) {
8979                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8980                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8981                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8982                 } else if (IS_GM45(dev)) {
8983                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8984                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8985                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8986                 } else if (IS_CRESTLINE(dev)) {
8987                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8988                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8989                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8990                 }
8991                 /* 855GM needs testing */
8992         }
8993
8994         /* Returns the core display clock speed */
8995         if (IS_VALLEYVIEW(dev))
8996                 dev_priv->display.get_display_clock_speed =
8997                         valleyview_get_display_clock_speed;
8998         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8999                 dev_priv->display.get_display_clock_speed =
9000                         i945_get_display_clock_speed;
9001         else if (IS_I915G(dev))
9002                 dev_priv->display.get_display_clock_speed =
9003                         i915_get_display_clock_speed;
9004         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9005                 dev_priv->display.get_display_clock_speed =
9006                         i9xx_misc_get_display_clock_speed;
9007         else if (IS_I915GM(dev))
9008                 dev_priv->display.get_display_clock_speed =
9009                         i915gm_get_display_clock_speed;
9010         else if (IS_I865G(dev))
9011                 dev_priv->display.get_display_clock_speed =
9012                         i865_get_display_clock_speed;
9013         else if (IS_I85X(dev))
9014                 dev_priv->display.get_display_clock_speed =
9015                         i855_get_display_clock_speed;
9016         else /* 852, 830 */
9017                 dev_priv->display.get_display_clock_speed =
9018                         i830_get_display_clock_speed;
9019
9020         /* For FIFO watermark updates */
9021         if (HAS_PCH_SPLIT(dev)) {
9022                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
9023                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
9024
9025                 /* IVB configs may use multi-threaded forcewake */
9026                 if (IS_IVYBRIDGE(dev)) {
9027                         u32     ecobus;
9028
9029                         /* A small trick here - if the bios hasn't configured MT forcewake,
9030                          * and if the device is in RC6, then force_wake_mt_get will not wake
9031                          * the device and the ECOBUS read will return zero. Which will be
9032                          * (correctly) interpreted by the test below as MT forcewake being
9033                          * disabled.
9034                          */
9035                         mutex_lock(&dev->struct_mutex);
9036                         __gen6_gt_force_wake_mt_get(dev_priv);
9037                         ecobus = I915_READ_NOTRACE(ECOBUS);
9038                         __gen6_gt_force_wake_mt_put(dev_priv);
9039                         mutex_unlock(&dev->struct_mutex);
9040
9041                         if (ecobus & FORCEWAKE_MT_ENABLE) {
9042                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
9043                                 dev_priv->display.force_wake_get =
9044                                         __gen6_gt_force_wake_mt_get;
9045                                 dev_priv->display.force_wake_put =
9046                                         __gen6_gt_force_wake_mt_put;
9047                         }
9048                 }
9049
9050                 if (HAS_PCH_IBX(dev))
9051                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
9052                 else if (HAS_PCH_CPT(dev))
9053                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
9054
9055                 if (IS_GEN5(dev)) {
9056                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
9057                                 dev_priv->display.update_wm = ironlake_update_wm;
9058                         else {
9059                                 DRM_DEBUG_KMS("Failed to get proper latency. "
9060                                               "Disable CxSR\n");
9061                                 dev_priv->display.update_wm = NULL;
9062                         }
9063                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9064                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
9065                         dev_priv->display.write_eld = ironlake_write_eld;
9066                 } else if (IS_GEN6(dev)) {
9067                         if (SNB_READ_WM0_LATENCY()) {
9068                                 dev_priv->display.update_wm = sandybridge_update_wm;
9069                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9070                         } else {
9071                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
9072                                               "Disable CxSR\n");
9073                                 dev_priv->display.update_wm = NULL;
9074                         }
9075                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9076                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9077                         dev_priv->display.write_eld = ironlake_write_eld;
9078                 } else if (IS_IVYBRIDGE(dev)) {
9079                         /* FIXME: detect B0+ stepping and use auto training */
9080                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9081                         if (SNB_READ_WM0_LATENCY()) {
9082                                 dev_priv->display.update_wm = sandybridge_update_wm;
9083                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9084                         } else {
9085                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
9086                                               "Disable CxSR\n");
9087                                 dev_priv->display.update_wm = NULL;
9088                         }
9089                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
9090                         dev_priv->display.write_eld = ironlake_write_eld;
9091                 } else
9092                         dev_priv->display.update_wm = NULL;
9093         } else if (IS_VALLEYVIEW(dev)) {
9094                 dev_priv->display.update_wm = valleyview_update_wm;
9095         } else if (IS_PINEVIEW(dev)) {
9096                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
9097                                             dev_priv->is_ddr3,
9098                                             dev_priv->fsb_freq,
9099                                             dev_priv->mem_freq)) {
9100                         DRM_INFO("failed to find known CxSR latency "
9101                                  "(found ddr%s fsb freq %d, mem freq %d), "
9102                                  "disabling CxSR\n",
9103                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
9104                                  dev_priv->fsb_freq, dev_priv->mem_freq);
9105                         /* Disable CxSR and never update its watermark again */
9106                         pineview_disable_cxsr(dev);
9107                         dev_priv->display.update_wm = NULL;
9108                 } else
9109                         dev_priv->display.update_wm = pineview_update_wm;
9110                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9111         } else if (IS_G4X(dev)) {
9112                 dev_priv->display.write_eld = g4x_write_eld;
9113                 dev_priv->display.update_wm = g4x_update_wm;
9114                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9115         } else if (IS_GEN4(dev)) {
9116                 dev_priv->display.update_wm = i965_update_wm;
9117                 if (IS_CRESTLINE(dev))
9118                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
9119                 else if (IS_BROADWATER(dev))
9120                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
9121         } else if (IS_GEN3(dev)) {
9122                 dev_priv->display.update_wm = i9xx_update_wm;
9123                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9124                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9125         } else if (IS_I865G(dev)) {
9126                 dev_priv->display.update_wm = i830_update_wm;
9127                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9128                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9129         } else if (IS_I85X(dev)) {
9130                 dev_priv->display.update_wm = i9xx_update_wm;
9131                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
9132                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9133         } else {
9134                 dev_priv->display.update_wm = i830_update_wm;
9135                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9136                 if (IS_845G(dev))
9137                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
9138                 else
9139                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
9140         }
9141
9142         /* Default just returns -ENODEV to indicate unsupported */
9143         dev_priv->display.queue_flip = intel_default_queue_flip;
9144
9145         switch (INTEL_INFO(dev)->gen) {
9146         case 2:
9147                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9148                 break;
9149
9150         case 3:
9151                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9152                 break;
9153
9154         case 4:
9155         case 5:
9156                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9157                 break;
9158
9159         case 6:
9160                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9161                 break;
9162         case 7:
9163                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9164                 break;
9165         }
9166 }
9167
9168 /*
9169  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9170  * resume, or other times.  This quirk makes sure that's the case for
9171  * affected systems.
9172  */
9173 static void quirk_pipea_force(struct drm_device *dev)
9174 {
9175         struct drm_i915_private *dev_priv = dev->dev_private;
9176
9177         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9178         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9179 }
9180
9181 /*
9182  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9183  */
9184 static void quirk_ssc_force_disable(struct drm_device *dev)
9185 {
9186         struct drm_i915_private *dev_priv = dev->dev_private;
9187         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9188 }
9189
9190 /*
9191  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9192  * brightness value
9193  */
9194 static void quirk_invert_brightness(struct drm_device *dev)
9195 {
9196         struct drm_i915_private *dev_priv = dev->dev_private;
9197         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9198 }
9199
9200 struct intel_quirk {
9201         int device;
9202         int subsystem_vendor;
9203         int subsystem_device;
9204         void (*hook)(struct drm_device *dev);
9205 };
9206
9207 struct intel_quirk intel_quirks[] = {
9208         /* HP Mini needs pipe A force quirk (LP: #322104) */
9209         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9210
9211         /* Thinkpad R31 needs pipe A force quirk */
9212         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9213         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9214         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9215
9216         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9217         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
9218         /* ThinkPad X40 needs pipe A force quirk */
9219
9220         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9221         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9222
9223         /* 855 & before need to leave pipe A & dpll A up */
9224         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9225         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9226
9227         /* Lenovo U160 cannot use SSC on LVDS */
9228         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9229
9230         /* Sony Vaio Y cannot use SSC on LVDS */
9231         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9232
9233         /* Acer Aspire 5734Z must invert backlight brightness */
9234         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9235 };
9236
9237 static void intel_init_quirks(struct drm_device *dev)
9238 {
9239         struct pci_dev *d = dev->pdev;
9240         int i;
9241
9242         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9243                 struct intel_quirk *q = &intel_quirks[i];
9244
9245                 if (d->device == q->device &&
9246                     (d->subsystem_vendor == q->subsystem_vendor ||
9247                      q->subsystem_vendor == PCI_ANY_ID) &&
9248                     (d->subsystem_device == q->subsystem_device ||
9249                      q->subsystem_device == PCI_ANY_ID))
9250                         q->hook(dev);
9251         }
9252 }
9253
9254 /* Disable the VGA plane that we never use */
9255 static void i915_disable_vga(struct drm_device *dev)
9256 {
9257         struct drm_i915_private *dev_priv = dev->dev_private;
9258         u8 sr1;
9259         u32 vga_reg;
9260
9261         if (HAS_PCH_SPLIT(dev))
9262                 vga_reg = CPU_VGACNTRL;
9263         else
9264                 vga_reg = VGACNTRL;
9265
9266         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9267         outb(1, VGA_SR_INDEX);
9268         sr1 = inb(VGA_SR_DATA);
9269         outb(sr1 | 1<<5, VGA_SR_DATA);
9270         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9271         udelay(300);
9272
9273         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9274         POSTING_READ(vga_reg);
9275 }
9276
9277 void intel_modeset_init(struct drm_device *dev)
9278 {
9279         struct drm_i915_private *dev_priv = dev->dev_private;
9280         int i, ret;
9281
9282         drm_mode_config_init(dev);
9283
9284         dev->mode_config.min_width = 0;
9285         dev->mode_config.min_height = 0;
9286
9287         dev->mode_config.preferred_depth = 24;
9288         dev->mode_config.prefer_shadow = 1;
9289
9290         dev->mode_config.funcs = (void *)&intel_mode_funcs;
9291
9292         intel_init_quirks(dev);
9293
9294         intel_init_display(dev);
9295
9296         if (IS_GEN2(dev)) {
9297                 dev->mode_config.max_width = 2048;
9298                 dev->mode_config.max_height = 2048;
9299         } else if (IS_GEN3(dev)) {
9300                 dev->mode_config.max_width = 4096;
9301                 dev->mode_config.max_height = 4096;
9302         } else {
9303                 dev->mode_config.max_width = 8192;
9304                 dev->mode_config.max_height = 8192;
9305         }
9306         dev->mode_config.fb_base = dev->agp->base;
9307
9308         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9309                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9310
9311         for (i = 0; i < dev_priv->num_pipe; i++) {
9312                 intel_crtc_init(dev, i);
9313                 ret = intel_plane_init(dev, i);
9314                 if (ret)
9315                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9316         }
9317
9318         /* Just disable it once at startup */
9319         i915_disable_vga(dev);
9320         intel_setup_outputs(dev);
9321
9322         intel_init_clock_gating(dev);
9323
9324         if (IS_IRONLAKE_M(dev)) {
9325                 ironlake_enable_drps(dev);
9326                 intel_init_emon(dev);
9327         }
9328
9329         if (IS_GEN6(dev) || IS_GEN7(dev)) {
9330                 gen6_enable_rps(dev_priv);
9331                 gen6_update_ring_freq(dev_priv);
9332         }
9333
9334         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9335         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9336                     (unsigned long)dev);
9337 }
9338
9339 void intel_modeset_gem_init(struct drm_device *dev)
9340 {
9341         if (IS_IRONLAKE_M(dev))
9342                 ironlake_enable_rc6(dev);
9343
9344         intel_setup_overlay(dev);
9345 }
9346
9347 void intel_modeset_cleanup(struct drm_device *dev)
9348 {
9349         struct drm_i915_private *dev_priv = dev->dev_private;
9350         struct drm_crtc *crtc;
9351         struct intel_crtc *intel_crtc;
9352
9353         drm_kms_helper_poll_fini(dev);
9354         mutex_lock(&dev->struct_mutex);
9355
9356         intel_unregister_dsm_handler();
9357
9358
9359         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9360                 /* Skip inactive CRTCs */
9361                 if (!crtc->fb)
9362                         continue;
9363
9364                 intel_crtc = to_intel_crtc(crtc);
9365                 intel_increase_pllclock(crtc);
9366         }
9367
9368         intel_disable_fbc(dev);
9369
9370         if (IS_IRONLAKE_M(dev))
9371                 ironlake_disable_drps(dev);
9372         if (IS_GEN6(dev) || IS_GEN7(dev))
9373                 gen6_disable_rps(dev);
9374
9375         if (IS_IRONLAKE_M(dev))
9376                 ironlake_disable_rc6(dev);
9377
9378         mutex_unlock(&dev->struct_mutex);
9379
9380         /* Disable the irq before mode object teardown, for the irq might
9381          * enqueue unpin/hotplug work. */
9382         drm_irq_uninstall(dev);
9383         cancel_work_sync(&dev_priv->hotplug_work);
9384         cancel_work_sync(&dev_priv->rps_work);
9385
9386         /* flush any delayed tasks or pending work */
9387         flush_scheduled_work();
9388
9389         /* Shut off idle work before the crtcs get freed. */
9390         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9391                 intel_crtc = to_intel_crtc(crtc);
9392                 del_timer_sync(&intel_crtc->idle_timer);
9393         }
9394         del_timer_sync(&dev_priv->idle_timer);
9395         cancel_work_sync(&dev_priv->idle_work);
9396
9397         drm_mode_config_cleanup(dev);
9398 }
9399
9400 /*
9401  * Return which encoder is currently attached for connector.
9402  */
9403 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9404 {
9405         return &intel_attached_encoder(connector)->base;
9406 }
9407
9408 void intel_connector_attach_encoder(struct intel_connector *connector,
9409                                     struct intel_encoder *encoder)
9410 {
9411         connector->encoder = encoder;
9412         drm_mode_connector_attach_encoder(&connector->base,
9413                                           &encoder->base);
9414 }
9415
9416 /*
9417  * set vga decode state - true == enable VGA decode
9418  */
9419 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9420 {
9421         struct drm_i915_private *dev_priv = dev->dev_private;
9422         u16 gmch_ctrl;
9423
9424         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9425         if (state)
9426                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9427         else
9428                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9429         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9430         return 0;
9431 }
9432
9433 #ifdef CONFIG_DEBUG_FS
9434 #include <linux/seq_file.h>
9435
9436 struct intel_display_error_state {
9437         struct intel_cursor_error_state {
9438                 u32 control;
9439                 u32 position;
9440                 u32 base;
9441                 u32 size;
9442         } cursor[2];
9443
9444         struct intel_pipe_error_state {
9445                 u32 conf;
9446                 u32 source;
9447
9448                 u32 htotal;
9449                 u32 hblank;
9450                 u32 hsync;
9451                 u32 vtotal;
9452                 u32 vblank;
9453                 u32 vsync;
9454         } pipe[2];
9455
9456         struct intel_plane_error_state {
9457                 u32 control;
9458                 u32 stride;
9459                 u32 size;
9460                 u32 pos;
9461                 u32 addr;
9462                 u32 surface;
9463                 u32 tile_offset;
9464         } plane[2];
9465 };
9466
9467 struct intel_display_error_state *
9468 intel_display_capture_error_state(struct drm_device *dev)
9469 {
9470         drm_i915_private_t *dev_priv = dev->dev_private;
9471         struct intel_display_error_state *error;
9472         int i;
9473
9474         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9475         if (error == NULL)
9476                 return NULL;
9477
9478         for (i = 0; i < 2; i++) {
9479                 error->cursor[i].control = I915_READ(CURCNTR(i));
9480                 error->cursor[i].position = I915_READ(CURPOS(i));
9481                 error->cursor[i].base = I915_READ(CURBASE(i));
9482
9483                 error->plane[i].control = I915_READ(DSPCNTR(i));
9484                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9485                 error->plane[i].size = I915_READ(DSPSIZE(i));
9486                 error->plane[i].pos = I915_READ(DSPPOS(i));
9487                 error->plane[i].addr = I915_READ(DSPADDR(i));
9488                 if (INTEL_INFO(dev)->gen >= 4) {
9489                         error->plane[i].surface = I915_READ(DSPSURF(i));
9490                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9491                 }
9492
9493                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9494                 error->pipe[i].source = I915_READ(PIPESRC(i));
9495                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9496                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9497                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9498                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9499                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9500                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9501         }
9502
9503         return error;
9504 }
9505
9506 void
9507 intel_display_print_error_state(struct seq_file *m,
9508                                 struct drm_device *dev,
9509                                 struct intel_display_error_state *error)
9510 {
9511         int i;
9512
9513         for (i = 0; i < 2; i++) {
9514                 seq_printf(m, "Pipe [%d]:\n", i);
9515                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9516                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9517                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9518                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9519                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9520                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9521                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9522                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9523
9524                 seq_printf(m, "Plane [%d]:\n", i);
9525                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9526                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9527                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9528                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9529                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9530                 if (INTEL_INFO(dev)->gen >= 4) {
9531                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9532                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9533                 }
9534
9535                 seq_printf(m, "Cursor [%d]:\n", i);
9536                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9537                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9538                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9539         }
9540 }
9541 #endif