2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
72 static const uint32_t intel_cursor_formats[] = {
76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_config *pipe_config);
80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config);
83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
85 static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
92 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
97 static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_config *pipe_config);
99 static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_config *pipe_config);
102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
104 if (!connector->mst_port)
105 return connector->encoder;
107 return &connector->mst_port->mst_encoders[pipe]->base;
116 int p2_slow, p2_fast;
119 typedef struct intel_limit intel_limit_t;
121 intel_range_t dot, vco, n, m, m1, m2, p, p1;
126 intel_pch_rawclk(struct drm_device *dev)
128 struct drm_i915_private *dev_priv = dev->dev_private;
130 WARN_ON(!HAS_PCH_SPLIT(dev));
132 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
135 static inline u32 /* units of 100MHz */
136 intel_fdi_link_freq(struct drm_device *dev)
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145 static const intel_limit_t intel_limits_i8xx_dac = {
146 .dot = { .min = 25000, .max = 350000 },
147 .vco = { .min = 908000, .max = 1512000 },
148 .n = { .min = 2, .max = 16 },
149 .m = { .min = 96, .max = 140 },
150 .m1 = { .min = 18, .max = 26 },
151 .m2 = { .min = 6, .max = 16 },
152 .p = { .min = 4, .max = 128 },
153 .p1 = { .min = 2, .max = 33 },
154 .p2 = { .dot_limit = 165000,
155 .p2_slow = 4, .p2_fast = 2 },
158 static const intel_limit_t intel_limits_i8xx_dvo = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 4 },
171 static const intel_limit_t intel_limits_i8xx_lvds = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 1, .max = 6 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 14, .p2_fast = 7 },
184 static const intel_limit_t intel_limits_i9xx_sdvo = {
185 .dot = { .min = 20000, .max = 400000 },
186 .vco = { .min = 1400000, .max = 2800000 },
187 .n = { .min = 1, .max = 6 },
188 .m = { .min = 70, .max = 120 },
189 .m1 = { .min = 8, .max = 18 },
190 .m2 = { .min = 3, .max = 7 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8 },
193 .p2 = { .dot_limit = 200000,
194 .p2_slow = 10, .p2_fast = 5 },
197 static const intel_limit_t intel_limits_i9xx_lvds = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 7, .max = 98 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 112000,
207 .p2_slow = 14, .p2_fast = 7 },
211 static const intel_limit_t intel_limits_g4x_sdvo = {
212 .dot = { .min = 25000, .max = 270000 },
213 .vco = { .min = 1750000, .max = 3500000},
214 .n = { .min = 1, .max = 4 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 10, .max = 30 },
219 .p1 = { .min = 1, .max = 3},
220 .p2 = { .dot_limit = 270000,
226 static const intel_limit_t intel_limits_g4x_hdmi = {
227 .dot = { .min = 22000, .max = 400000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 16, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 5, .max = 80 },
234 .p1 = { .min = 1, .max = 8},
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 10, .p2_fast = 5 },
239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
240 .dot = { .min = 20000, .max = 115000 },
241 .vco = { .min = 1750000, .max = 3500000 },
242 .n = { .min = 1, .max = 3 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 17, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
248 .p2 = { .dot_limit = 0,
249 .p2_slow = 14, .p2_fast = 14
253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
254 .dot = { .min = 80000, .max = 224000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 14, .max = 42 },
261 .p1 = { .min = 2, .max = 6 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 7, .p2_fast = 7
267 static const intel_limit_t intel_limits_pineview_sdvo = {
268 .dot = { .min = 20000, .max = 400000},
269 .vco = { .min = 1700000, .max = 3500000 },
270 /* Pineview's Ncounter is a ring counter */
271 .n = { .min = 3, .max = 6 },
272 .m = { .min = 2, .max = 256 },
273 /* Pineview only has one combined m divider, which we treat as m2. */
274 .m1 = { .min = 0, .max = 0 },
275 .m2 = { .min = 0, .max = 254 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8 },
278 .p2 = { .dot_limit = 200000,
279 .p2_slow = 10, .p2_fast = 5 },
282 static const intel_limit_t intel_limits_pineview_lvds = {
283 .dot = { .min = 20000, .max = 400000 },
284 .vco = { .min = 1700000, .max = 3500000 },
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 7, .max = 112 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 112000,
292 .p2_slow = 14, .p2_fast = 14 },
295 /* Ironlake / Sandybridge
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
300 static const intel_limit_t intel_limits_ironlake_dac = {
301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 5 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 5, .max = 80 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 10, .p2_fast = 5 },
313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 3 },
317 .m = { .min = 79, .max = 118 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 28, .max = 112 },
321 .p1 = { .min = 2, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 14, .p2_fast = 14 },
326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 127 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 14, .max = 56 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 7, .p2_fast = 7 },
339 /* LVDS 100mhz refclk limits. */
340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 2 },
344 .m = { .min = 79, .max = 126 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 28, .max = 112 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 14, .p2_fast = 14 },
353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 14, .max = 42 },
361 .p1 = { .min = 2, .max = 6 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 7, .p2_fast = 7 },
366 static const intel_limit_t intel_limits_vlv = {
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
373 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
374 .vco = { .min = 4000000, .max = 6000000 },
375 .n = { .min = 1, .max = 7 },
376 .m1 = { .min = 2, .max = 3 },
377 .m2 = { .min = 11, .max = 156 },
378 .p1 = { .min = 2, .max = 3 },
379 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
382 static const intel_limit_t intel_limits_chv = {
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
389 .dot = { .min = 25000 * 5, .max = 540000 * 5},
390 .vco = { .min = 4860000, .max = 6700000 },
391 .n = { .min = 1, .max = 1 },
392 .m1 = { .min = 2, .max = 2 },
393 .m2 = { .min = 24 << 22, .max = 175 << 22 },
394 .p1 = { .min = 2, .max = 4 },
395 .p2 = { .p2_slow = 1, .p2_fast = 14 },
398 static void vlv_clock(int refclk, intel_clock_t *clock)
400 clock->m = clock->m1 * clock->m2;
401 clock->p = clock->p1 * clock->p2;
402 if (WARN_ON(clock->n == 0 || clock->p == 0))
404 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
405 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 * Returns whether any output on the specified pipe is of the specified type
411 bool intel_pipe_has_type(struct intel_crtc *crtc, int type)
413 struct drm_device *dev = crtc->base.dev;
414 struct intel_encoder *encoder;
416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
417 if (encoder->type == type)
423 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
426 struct drm_device *dev = crtc->base.dev;
427 const intel_limit_t *limit;
429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
430 if (intel_is_dual_link_lvds(dev)) {
431 if (refclk == 100000)
432 limit = &intel_limits_ironlake_dual_lvds_100m;
434 limit = &intel_limits_ironlake_dual_lvds;
436 if (refclk == 100000)
437 limit = &intel_limits_ironlake_single_lvds_100m;
439 limit = &intel_limits_ironlake_single_lvds;
442 limit = &intel_limits_ironlake_dac;
447 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
449 struct drm_device *dev = crtc->base.dev;
450 const intel_limit_t *limit;
452 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
453 if (intel_is_dual_link_lvds(dev))
454 limit = &intel_limits_g4x_dual_channel_lvds;
456 limit = &intel_limits_g4x_single_channel_lvds;
457 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
458 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
459 limit = &intel_limits_g4x_hdmi;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
461 limit = &intel_limits_g4x_sdvo;
462 } else /* The option is for other outputs */
463 limit = &intel_limits_i9xx_sdvo;
468 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
473 if (HAS_PCH_SPLIT(dev))
474 limit = intel_ironlake_limit(crtc, refclk);
475 else if (IS_G4X(dev)) {
476 limit = intel_g4x_limit(crtc);
477 } else if (IS_PINEVIEW(dev)) {
478 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
479 limit = &intel_limits_pineview_lvds;
481 limit = &intel_limits_pineview_sdvo;
482 } else if (IS_CHERRYVIEW(dev)) {
483 limit = &intel_limits_chv;
484 } else if (IS_VALLEYVIEW(dev)) {
485 limit = &intel_limits_vlv;
486 } else if (!IS_GEN2(dev)) {
487 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
488 limit = &intel_limits_i9xx_lvds;
490 limit = &intel_limits_i9xx_sdvo;
492 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
493 limit = &intel_limits_i8xx_lvds;
494 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
495 limit = &intel_limits_i8xx_dvo;
497 limit = &intel_limits_i8xx_dac;
502 /* m1 is reserved as 0 in Pineview, n is a ring counter */
503 static void pineview_clock(int refclk, intel_clock_t *clock)
505 clock->m = clock->m2 + 2;
506 clock->p = clock->p1 * clock->p2;
507 if (WARN_ON(clock->n == 0 || clock->p == 0))
509 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
510 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
513 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
515 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
518 static void i9xx_clock(int refclk, intel_clock_t *clock)
520 clock->m = i9xx_dpll_compute_m(clock);
521 clock->p = clock->p1 * clock->p2;
522 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
524 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
525 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
528 static void chv_clock(int refclk, intel_clock_t *clock)
530 clock->m = clock->m1 * clock->m2;
531 clock->p = clock->p1 * clock->p2;
532 if (WARN_ON(clock->n == 0 || clock->p == 0))
534 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
536 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
539 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
541 * Returns whether the given set of divisors are valid for a given refclk with
542 * the given connectors.
545 static bool intel_PLL_is_valid(struct drm_device *dev,
546 const intel_limit_t *limit,
547 const intel_clock_t *clock)
549 if (clock->n < limit->n.min || limit->n.max < clock->n)
550 INTELPllInvalid("n out of range\n");
551 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
552 INTELPllInvalid("p1 out of range\n");
553 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
554 INTELPllInvalid("m2 out of range\n");
555 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
556 INTELPllInvalid("m1 out of range\n");
558 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
559 if (clock->m1 <= clock->m2)
560 INTELPllInvalid("m1 <= m2\n");
562 if (!IS_VALLEYVIEW(dev)) {
563 if (clock->p < limit->p.min || limit->p.max < clock->p)
564 INTELPllInvalid("p out of range\n");
565 if (clock->m < limit->m.min || limit->m.max < clock->m)
566 INTELPllInvalid("m out of range\n");
569 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
570 INTELPllInvalid("vco out of range\n");
571 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
572 * connector, etc., rather than just a single range.
574 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
575 INTELPllInvalid("dot out of range\n");
581 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
582 int target, int refclk, intel_clock_t *match_clock,
583 intel_clock_t *best_clock)
585 struct drm_device *dev = crtc->base.dev;
589 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
591 * For LVDS just rely on its current settings for dual-channel.
592 * We haven't figured out how to reliably set up different
593 * single/dual channel state, if we even can.
595 if (intel_is_dual_link_lvds(dev))
596 clock.p2 = limit->p2.p2_fast;
598 clock.p2 = limit->p2.p2_slow;
600 if (target < limit->p2.dot_limit)
601 clock.p2 = limit->p2.p2_slow;
603 clock.p2 = limit->p2.p2_fast;
606 memset(best_clock, 0, sizeof(*best_clock));
608 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
610 for (clock.m2 = limit->m2.min;
611 clock.m2 <= limit->m2.max; clock.m2++) {
612 if (clock.m2 >= clock.m1)
614 for (clock.n = limit->n.min;
615 clock.n <= limit->n.max; clock.n++) {
616 for (clock.p1 = limit->p1.min;
617 clock.p1 <= limit->p1.max; clock.p1++) {
620 i9xx_clock(refclk, &clock);
621 if (!intel_PLL_is_valid(dev, limit,
625 clock.p != match_clock->p)
628 this_err = abs(clock.dot - target);
629 if (this_err < err) {
638 return (err != target);
642 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
643 int target, int refclk, intel_clock_t *match_clock,
644 intel_clock_t *best_clock)
646 struct drm_device *dev = crtc->base.dev;
650 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
652 * For LVDS just rely on its current settings for dual-channel.
653 * We haven't figured out how to reliably set up different
654 * single/dual channel state, if we even can.
656 if (intel_is_dual_link_lvds(dev))
657 clock.p2 = limit->p2.p2_fast;
659 clock.p2 = limit->p2.p2_slow;
661 if (target < limit->p2.dot_limit)
662 clock.p2 = limit->p2.p2_slow;
664 clock.p2 = limit->p2.p2_fast;
667 memset(best_clock, 0, sizeof(*best_clock));
669 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
671 for (clock.m2 = limit->m2.min;
672 clock.m2 <= limit->m2.max; clock.m2++) {
673 for (clock.n = limit->n.min;
674 clock.n <= limit->n.max; clock.n++) {
675 for (clock.p1 = limit->p1.min;
676 clock.p1 <= limit->p1.max; clock.p1++) {
679 pineview_clock(refclk, &clock);
680 if (!intel_PLL_is_valid(dev, limit,
684 clock.p != match_clock->p)
687 this_err = abs(clock.dot - target);
688 if (this_err < err) {
697 return (err != target);
701 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
702 int target, int refclk, intel_clock_t *match_clock,
703 intel_clock_t *best_clock)
705 struct drm_device *dev = crtc->base.dev;
709 /* approximately equals target * 0.00585 */
710 int err_most = (target >> 8) + (target >> 9);
713 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
714 if (intel_is_dual_link_lvds(dev))
715 clock.p2 = limit->p2.p2_fast;
717 clock.p2 = limit->p2.p2_slow;
719 if (target < limit->p2.dot_limit)
720 clock.p2 = limit->p2.p2_slow;
722 clock.p2 = limit->p2.p2_fast;
725 memset(best_clock, 0, sizeof(*best_clock));
726 max_n = limit->n.max;
727 /* based on hardware requirement, prefer smaller n to precision */
728 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
729 /* based on hardware requirement, prefere larger m1,m2 */
730 for (clock.m1 = limit->m1.max;
731 clock.m1 >= limit->m1.min; clock.m1--) {
732 for (clock.m2 = limit->m2.max;
733 clock.m2 >= limit->m2.min; clock.m2--) {
734 for (clock.p1 = limit->p1.max;
735 clock.p1 >= limit->p1.min; clock.p1--) {
738 i9xx_clock(refclk, &clock);
739 if (!intel_PLL_is_valid(dev, limit,
743 this_err = abs(clock.dot - target);
744 if (this_err < err_most) {
758 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
759 int target, int refclk, intel_clock_t *match_clock,
760 intel_clock_t *best_clock)
762 struct drm_device *dev = crtc->base.dev;
764 unsigned int bestppm = 1000000;
765 /* min update 19.2 MHz */
766 int max_n = min(limit->n.max, refclk / 19200);
769 target *= 5; /* fast clock */
771 memset(best_clock, 0, sizeof(*best_clock));
773 /* based on hardware requirement, prefer smaller n to precision */
774 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
775 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
776 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
777 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
778 clock.p = clock.p1 * clock.p2;
779 /* based on hardware requirement, prefer bigger m1,m2 values */
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
781 unsigned int ppm, diff;
783 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
786 vlv_clock(refclk, &clock);
788 if (!intel_PLL_is_valid(dev, limit,
792 diff = abs(clock.dot - target);
793 ppm = div_u64(1000000ULL * diff, target);
795 if (ppm < 100 && clock.p > best_clock->p) {
801 if (bestppm >= 10 && ppm < bestppm - 10) {
815 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
816 int target, int refclk, intel_clock_t *match_clock,
817 intel_clock_t *best_clock)
819 struct drm_device *dev = crtc->base.dev;
824 memset(best_clock, 0, sizeof(*best_clock));
827 * Based on hardware doc, the n always set to 1, and m1 always
828 * set to 2. If requires to support 200Mhz refclk, we need to
829 * revisit this because n may not 1 anymore.
831 clock.n = 1, clock.m1 = 2;
832 target *= 5; /* fast clock */
834 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
835 for (clock.p2 = limit->p2.p2_fast;
836 clock.p2 >= limit->p2.p2_slow;
837 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
839 clock.p = clock.p1 * clock.p2;
841 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
842 clock.n) << 22, refclk * clock.m1);
844 if (m2 > INT_MAX/clock.m1)
849 chv_clock(refclk, &clock);
851 if (!intel_PLL_is_valid(dev, limit, &clock))
854 /* based on hardware requirement, prefer bigger p
856 if (clock.p > best_clock->p) {
866 bool intel_crtc_active(struct drm_crtc *crtc)
868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
870 /* Be paranoid as we can arrive here with only partial
871 * state retrieved from the hardware during setup.
873 * We can ditch the adjusted_mode.crtc_clock check as soon
874 * as Haswell has gained clock readout/fastboot support.
876 * We can ditch the crtc->primary->fb check as soon as we can
877 * properly reconstruct framebuffers.
879 return intel_crtc->active && crtc->primary->fb &&
880 intel_crtc->config.adjusted_mode.crtc_clock;
883 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
886 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
889 return intel_crtc->config.cpu_transcoder;
892 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
894 struct drm_i915_private *dev_priv = dev->dev_private;
895 u32 reg = PIPEDSL(pipe);
900 line_mask = DSL_LINEMASK_GEN2;
902 line_mask = DSL_LINEMASK_GEN3;
904 line1 = I915_READ(reg) & line_mask;
906 line2 = I915_READ(reg) & line_mask;
908 return line1 == line2;
912 * intel_wait_for_pipe_off - wait for pipe to turn off
913 * @crtc: crtc whose pipe to wait for
915 * After disabling a pipe, we can't wait for vblank in the usual way,
916 * spinning on the vblank interrupt status bit, since we won't actually
917 * see an interrupt when the pipe is disabled.
920 * wait for the pipe register state bit to turn off
923 * wait for the display line value to settle (it usually
924 * ends up stopping at the start of the next frame).
927 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
929 struct drm_device *dev = crtc->base.dev;
930 struct drm_i915_private *dev_priv = dev->dev_private;
931 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
932 enum pipe pipe = crtc->pipe;
934 if (INTEL_INFO(dev)->gen >= 4) {
935 int reg = PIPECONF(cpu_transcoder);
937 /* Wait for the Pipe State to go off */
938 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
940 WARN(1, "pipe_off wait timed out\n");
942 /* Wait for the display line to settle */
943 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
944 WARN(1, "pipe_off wait timed out\n");
949 * ibx_digital_port_connected - is the specified port connected?
950 * @dev_priv: i915 private structure
951 * @port: the port to test
953 * Returns true if @port is connected, false otherwise.
955 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
956 struct intel_digital_port *port)
960 if (HAS_PCH_IBX(dev_priv->dev)) {
961 switch (port->port) {
963 bit = SDE_PORTB_HOTPLUG;
966 bit = SDE_PORTC_HOTPLUG;
969 bit = SDE_PORTD_HOTPLUG;
975 switch (port->port) {
977 bit = SDE_PORTB_HOTPLUG_CPT;
980 bit = SDE_PORTC_HOTPLUG_CPT;
983 bit = SDE_PORTD_HOTPLUG_CPT;
990 return I915_READ(SDEISR) & bit;
993 static const char *state_string(bool enabled)
995 return enabled ? "on" : "off";
998 /* Only for pre-ILK configs */
999 void assert_pll(struct drm_i915_private *dev_priv,
1000 enum pipe pipe, bool state)
1007 val = I915_READ(reg);
1008 cur_state = !!(val & DPLL_VCO_ENABLE);
1009 WARN(cur_state != state,
1010 "PLL state assertion failure (expected %s, current %s)\n",
1011 state_string(state), state_string(cur_state));
1014 /* XXX: the dsi pll is shared between MIPI DSI ports */
1015 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1020 mutex_lock(&dev_priv->dpio_lock);
1021 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1022 mutex_unlock(&dev_priv->dpio_lock);
1024 cur_state = val & DSI_PLL_VCO_EN;
1025 WARN(cur_state != state,
1026 "DSI PLL state assertion failure (expected %s, current %s)\n",
1027 state_string(state), state_string(cur_state));
1029 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1030 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1032 struct intel_shared_dpll *
1033 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1035 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1037 if (crtc->config.shared_dpll < 0)
1040 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1044 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1045 struct intel_shared_dpll *pll,
1049 struct intel_dpll_hw_state hw_state;
1052 "asserting DPLL %s with no DPLL\n", state_string(state)))
1055 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1056 WARN(cur_state != state,
1057 "%s assertion failure (expected %s, current %s)\n",
1058 pll->name, state_string(state), state_string(cur_state));
1061 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1062 enum pipe pipe, bool state)
1067 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1070 if (HAS_DDI(dev_priv->dev)) {
1071 /* DDI does not have a specific FDI_TX register */
1072 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1073 val = I915_READ(reg);
1074 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1076 reg = FDI_TX_CTL(pipe);
1077 val = I915_READ(reg);
1078 cur_state = !!(val & FDI_TX_ENABLE);
1080 WARN(cur_state != state,
1081 "FDI TX state assertion failure (expected %s, current %s)\n",
1082 state_string(state), state_string(cur_state));
1084 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1085 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1087 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1088 enum pipe pipe, bool state)
1094 reg = FDI_RX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_RX_ENABLE);
1097 WARN(cur_state != state,
1098 "FDI RX state assertion failure (expected %s, current %s)\n",
1099 state_string(state), state_string(cur_state));
1101 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1102 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1104 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1110 /* ILK FDI PLL is always enabled */
1111 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1114 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1115 if (HAS_DDI(dev_priv->dev))
1118 reg = FDI_TX_CTL(pipe);
1119 val = I915_READ(reg);
1120 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1123 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1130 reg = FDI_RX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1133 WARN(cur_state != state,
1134 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1138 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1141 struct drm_device *dev = dev_priv->dev;
1144 enum pipe panel_pipe = PIPE_A;
1147 if (WARN_ON(HAS_DDI(dev)))
1150 if (HAS_PCH_SPLIT(dev)) {
1153 pp_reg = PCH_PP_CONTROL;
1154 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1156 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1157 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1158 panel_pipe = PIPE_B;
1159 /* XXX: else fix for eDP */
1160 } else if (IS_VALLEYVIEW(dev)) {
1161 /* presumably write lock depends on pipe, not port select */
1162 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1165 pp_reg = PP_CONTROL;
1166 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1167 panel_pipe = PIPE_B;
1170 val = I915_READ(pp_reg);
1171 if (!(val & PANEL_POWER_ON) ||
1172 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1175 WARN(panel_pipe == pipe && locked,
1176 "panel assertion failure, pipe %c regs locked\n",
1180 static void assert_cursor(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1183 struct drm_device *dev = dev_priv->dev;
1186 if (IS_845G(dev) || IS_I865G(dev))
1187 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1189 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1191 WARN(cur_state != state,
1192 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1193 pipe_name(pipe), state_string(state), state_string(cur_state));
1195 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1196 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1198 void assert_pipe(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1204 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1207 /* if we need the pipe quirk it must be always on */
1208 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1209 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1212 if (!intel_display_power_is_enabled(dev_priv,
1213 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1216 reg = PIPECONF(cpu_transcoder);
1217 val = I915_READ(reg);
1218 cur_state = !!(val & PIPECONF_ENABLE);
1221 WARN(cur_state != state,
1222 "pipe %c assertion failure (expected %s, current %s)\n",
1223 pipe_name(pipe), state_string(state), state_string(cur_state));
1226 static void assert_plane(struct drm_i915_private *dev_priv,
1227 enum plane plane, bool state)
1233 reg = DSPCNTR(plane);
1234 val = I915_READ(reg);
1235 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1236 WARN(cur_state != state,
1237 "plane %c assertion failure (expected %s, current %s)\n",
1238 plane_name(plane), state_string(state), state_string(cur_state));
1241 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1242 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1244 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 struct drm_device *dev = dev_priv->dev;
1252 /* Primary planes are fixed to pipes on gen4+ */
1253 if (INTEL_INFO(dev)->gen >= 4) {
1254 reg = DSPCNTR(pipe);
1255 val = I915_READ(reg);
1256 WARN(val & DISPLAY_PLANE_ENABLE,
1257 "plane %c assertion failure, should be disabled but not\n",
1262 /* Need to check both planes against the pipe */
1263 for_each_pipe(dev_priv, i) {
1265 val = I915_READ(reg);
1266 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1267 DISPPLANE_SEL_PIPE_SHIFT;
1268 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1269 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1270 plane_name(i), pipe_name(pipe));
1274 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1277 struct drm_device *dev = dev_priv->dev;
1281 if (INTEL_INFO(dev)->gen >= 9) {
1282 for_each_sprite(pipe, sprite) {
1283 val = I915_READ(PLANE_CTL(pipe, sprite));
1284 WARN(val & PLANE_CTL_ENABLE,
1285 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1286 sprite, pipe_name(pipe));
1288 } else if (IS_VALLEYVIEW(dev)) {
1289 for_each_sprite(pipe, sprite) {
1290 reg = SPCNTR(pipe, sprite);
1291 val = I915_READ(reg);
1292 WARN(val & SP_ENABLE,
1293 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1294 sprite_name(pipe, sprite), pipe_name(pipe));
1296 } else if (INTEL_INFO(dev)->gen >= 7) {
1298 val = I915_READ(reg);
1299 WARN(val & SPRITE_ENABLE,
1300 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1301 plane_name(pipe), pipe_name(pipe));
1302 } else if (INTEL_INFO(dev)->gen >= 5) {
1303 reg = DVSCNTR(pipe);
1304 val = I915_READ(reg);
1305 WARN(val & DVS_ENABLE,
1306 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1307 plane_name(pipe), pipe_name(pipe));
1311 static void assert_vblank_disabled(struct drm_crtc *crtc)
1313 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1314 drm_crtc_vblank_put(crtc);
1317 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1322 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1324 val = I915_READ(PCH_DREF_CONTROL);
1325 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1326 DREF_SUPERSPREAD_SOURCE_MASK));
1327 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1330 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1337 reg = PCH_TRANSCONF(pipe);
1338 val = I915_READ(reg);
1339 enabled = !!(val & TRANS_ENABLE);
1341 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1345 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1346 enum pipe pipe, u32 port_sel, u32 val)
1348 if ((val & DP_PORT_EN) == 0)
1351 if (HAS_PCH_CPT(dev_priv->dev)) {
1352 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1353 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1354 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1356 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1357 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1360 if ((val & DP_PIPE_MASK) != (pipe << 30))
1366 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1367 enum pipe pipe, u32 val)
1369 if ((val & SDVO_ENABLE) == 0)
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1375 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1376 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1379 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1385 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe, u32 val)
1388 if ((val & LVDS_PORT_EN) == 0)
1391 if (HAS_PCH_CPT(dev_priv->dev)) {
1392 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1395 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1401 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1402 enum pipe pipe, u32 val)
1404 if ((val & ADPA_DAC_ENABLE) == 0)
1406 if (HAS_PCH_CPT(dev_priv->dev)) {
1407 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1410 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1416 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, int reg, u32 port_sel)
1419 u32 val = I915_READ(reg);
1420 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1421 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1422 reg, pipe_name(pipe));
1424 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1425 && (val & DP_PIPEB_SELECT),
1426 "IBX PCH dp port still using transcoder B\n");
1429 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1430 enum pipe pipe, int reg)
1432 u32 val = I915_READ(reg);
1433 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1434 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1435 reg, pipe_name(pipe));
1437 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1438 && (val & SDVO_PIPE_B_SELECT),
1439 "IBX PCH hdmi port still using transcoder B\n");
1442 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1448 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1449 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1450 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1453 val = I915_READ(reg);
1454 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1455 "PCH VGA enabled on transcoder %c, should be disabled\n",
1459 val = I915_READ(reg);
1460 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1461 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1464 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1465 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1466 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1469 static void intel_init_dpio(struct drm_device *dev)
1471 struct drm_i915_private *dev_priv = dev->dev_private;
1473 if (!IS_VALLEYVIEW(dev))
1477 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1478 * CHV x1 PHY (DP/HDMI D)
1479 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1481 if (IS_CHERRYVIEW(dev)) {
1482 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1483 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1485 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1489 static void vlv_enable_pll(struct intel_crtc *crtc,
1490 const struct intel_crtc_config *pipe_config)
1492 struct drm_device *dev = crtc->base.dev;
1493 struct drm_i915_private *dev_priv = dev->dev_private;
1494 int reg = DPLL(crtc->pipe);
1495 u32 dpll = pipe_config->dpll_hw_state.dpll;
1497 assert_pipe_disabled(dev_priv, crtc->pipe);
1499 /* No really, not for ILK+ */
1500 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1502 /* PLL is protected by panel, make sure we can write it */
1503 if (IS_MOBILE(dev_priv->dev))
1504 assert_panel_unlocked(dev_priv, crtc->pipe);
1506 I915_WRITE(reg, dpll);
1510 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1511 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1513 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1514 POSTING_READ(DPLL_MD(crtc->pipe));
1516 /* We do this three times for luck */
1517 I915_WRITE(reg, dpll);
1519 udelay(150); /* wait for warmup */
1520 I915_WRITE(reg, dpll);
1522 udelay(150); /* wait for warmup */
1523 I915_WRITE(reg, dpll);
1525 udelay(150); /* wait for warmup */
1528 static void chv_enable_pll(struct intel_crtc *crtc,
1529 const struct intel_crtc_config *pipe_config)
1531 struct drm_device *dev = crtc->base.dev;
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533 int pipe = crtc->pipe;
1534 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1537 assert_pipe_disabled(dev_priv, crtc->pipe);
1539 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1541 mutex_lock(&dev_priv->dpio_lock);
1543 /* Enable back the 10bit clock to display controller */
1544 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1545 tmp |= DPIO_DCLKP_EN;
1546 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1549 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1554 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1556 /* Check PLL is locked */
1557 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1558 DRM_ERROR("PLL %d failed to lock\n", pipe);
1560 /* not sure when this should be written */
1561 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1562 POSTING_READ(DPLL_MD(pipe));
1564 mutex_unlock(&dev_priv->dpio_lock);
1567 static int intel_num_dvo_pipes(struct drm_device *dev)
1569 struct intel_crtc *crtc;
1572 for_each_intel_crtc(dev, crtc)
1573 count += crtc->active &&
1574 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1579 static void i9xx_enable_pll(struct intel_crtc *crtc)
1581 struct drm_device *dev = crtc->base.dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 int reg = DPLL(crtc->pipe);
1584 u32 dpll = crtc->config.dpll_hw_state.dpll;
1586 assert_pipe_disabled(dev_priv, crtc->pipe);
1588 /* No really, not for ILK+ */
1589 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1591 /* PLL is protected by panel, make sure we can write it */
1592 if (IS_MOBILE(dev) && !IS_I830(dev))
1593 assert_panel_unlocked(dev_priv, crtc->pipe);
1595 /* Enable DVO 2x clock on both PLLs if necessary */
1596 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1598 * It appears to be important that we don't enable this
1599 * for the current pipe before otherwise configuring the
1600 * PLL. No idea how this should be handled if multiple
1601 * DVO outputs are enabled simultaneosly.
1603 dpll |= DPLL_DVO_2X_MODE;
1604 I915_WRITE(DPLL(!crtc->pipe),
1605 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1608 /* Wait for the clocks to stabilize. */
1612 if (INTEL_INFO(dev)->gen >= 4) {
1613 I915_WRITE(DPLL_MD(crtc->pipe),
1614 crtc->config.dpll_hw_state.dpll_md);
1616 /* The pixel multiplier can only be updated once the
1617 * DPLL is enabled and the clocks are stable.
1619 * So write it again.
1621 I915_WRITE(reg, dpll);
1624 /* We do this three times for luck */
1625 I915_WRITE(reg, dpll);
1627 udelay(150); /* wait for warmup */
1628 I915_WRITE(reg, dpll);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg, dpll);
1633 udelay(150); /* wait for warmup */
1637 * i9xx_disable_pll - disable a PLL
1638 * @dev_priv: i915 private structure
1639 * @pipe: pipe PLL to disable
1641 * Disable the PLL for @pipe, making sure the pipe is off first.
1643 * Note! This is for pre-ILK only.
1645 static void i9xx_disable_pll(struct intel_crtc *crtc)
1647 struct drm_device *dev = crtc->base.dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 enum pipe pipe = crtc->pipe;
1651 /* Disable DVO 2x clock on both PLLs if necessary */
1653 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1654 intel_num_dvo_pipes(dev) == 1) {
1655 I915_WRITE(DPLL(PIPE_B),
1656 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1657 I915_WRITE(DPLL(PIPE_A),
1658 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1661 /* Don't disable pipe or pipe PLLs if needed */
1662 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1663 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1666 /* Make sure the pipe isn't still relying on us */
1667 assert_pipe_disabled(dev_priv, pipe);
1669 I915_WRITE(DPLL(pipe), 0);
1670 POSTING_READ(DPLL(pipe));
1673 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1677 /* Make sure the pipe isn't still relying on us */
1678 assert_pipe_disabled(dev_priv, pipe);
1681 * Leave integrated clock source and reference clock enabled for pipe B.
1682 * The latter is needed for VGA hotplug / manual detection.
1685 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1686 I915_WRITE(DPLL(pipe), val);
1687 POSTING_READ(DPLL(pipe));
1691 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1693 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1696 /* Make sure the pipe isn't still relying on us */
1697 assert_pipe_disabled(dev_priv, pipe);
1699 /* Set PLL en = 0 */
1700 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1702 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1703 I915_WRITE(DPLL(pipe), val);
1704 POSTING_READ(DPLL(pipe));
1706 mutex_lock(&dev_priv->dpio_lock);
1708 /* Disable 10bit clock to display controller */
1709 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1710 val &= ~DPIO_DCLKP_EN;
1711 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1713 /* disable left/right clock distribution */
1714 if (pipe != PIPE_B) {
1715 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1716 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1717 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1719 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1720 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1721 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1724 mutex_unlock(&dev_priv->dpio_lock);
1727 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1728 struct intel_digital_port *dport)
1733 switch (dport->port) {
1735 port_mask = DPLL_PORTB_READY_MASK;
1739 port_mask = DPLL_PORTC_READY_MASK;
1743 port_mask = DPLL_PORTD_READY_MASK;
1744 dpll_reg = DPIO_PHY_STATUS;
1750 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1751 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1752 port_name(dport->port), I915_READ(dpll_reg));
1755 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1757 struct drm_device *dev = crtc->base.dev;
1758 struct drm_i915_private *dev_priv = dev->dev_private;
1759 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1761 if (WARN_ON(pll == NULL))
1764 WARN_ON(!pll->refcount);
1765 if (pll->active == 0) {
1766 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1768 assert_shared_dpll_disabled(dev_priv, pll);
1770 pll->mode_set(dev_priv, pll);
1775 * intel_enable_shared_dpll - enable PCH PLL
1776 * @dev_priv: i915 private structure
1777 * @pipe: pipe PLL to enable
1779 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1780 * drives the transcoder clock.
1782 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1784 struct drm_device *dev = crtc->base.dev;
1785 struct drm_i915_private *dev_priv = dev->dev_private;
1786 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1788 if (WARN_ON(pll == NULL))
1791 if (WARN_ON(pll->refcount == 0))
1794 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1795 pll->name, pll->active, pll->on,
1796 crtc->base.base.id);
1798 if (pll->active++) {
1800 assert_shared_dpll_enabled(dev_priv, pll);
1805 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1807 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1808 pll->enable(dev_priv, pll);
1812 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1814 struct drm_device *dev = crtc->base.dev;
1815 struct drm_i915_private *dev_priv = dev->dev_private;
1816 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1818 /* PCH only available on ILK+ */
1819 BUG_ON(INTEL_INFO(dev)->gen < 5);
1820 if (WARN_ON(pll == NULL))
1823 if (WARN_ON(pll->refcount == 0))
1826 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1827 pll->name, pll->active, pll->on,
1828 crtc->base.base.id);
1830 if (WARN_ON(pll->active == 0)) {
1831 assert_shared_dpll_disabled(dev_priv, pll);
1835 assert_shared_dpll_enabled(dev_priv, pll);
1840 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1841 pll->disable(dev_priv, pll);
1844 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1847 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1850 struct drm_device *dev = dev_priv->dev;
1851 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1853 uint32_t reg, val, pipeconf_val;
1855 /* PCH only available on ILK+ */
1856 BUG_ON(!HAS_PCH_SPLIT(dev));
1858 /* Make sure PCH DPLL is enabled */
1859 assert_shared_dpll_enabled(dev_priv,
1860 intel_crtc_to_shared_dpll(intel_crtc));
1862 /* FDI must be feeding us bits for PCH ports */
1863 assert_fdi_tx_enabled(dev_priv, pipe);
1864 assert_fdi_rx_enabled(dev_priv, pipe);
1866 if (HAS_PCH_CPT(dev)) {
1867 /* Workaround: Set the timing override bit before enabling the
1868 * pch transcoder. */
1869 reg = TRANS_CHICKEN2(pipe);
1870 val = I915_READ(reg);
1871 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1872 I915_WRITE(reg, val);
1875 reg = PCH_TRANSCONF(pipe);
1876 val = I915_READ(reg);
1877 pipeconf_val = I915_READ(PIPECONF(pipe));
1879 if (HAS_PCH_IBX(dev_priv->dev)) {
1881 * make the BPC in transcoder be consistent with
1882 * that in pipeconf reg.
1884 val &= ~PIPECONF_BPC_MASK;
1885 val |= pipeconf_val & PIPECONF_BPC_MASK;
1888 val &= ~TRANS_INTERLACE_MASK;
1889 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1890 if (HAS_PCH_IBX(dev_priv->dev) &&
1891 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1892 val |= TRANS_LEGACY_INTERLACED_ILK;
1894 val |= TRANS_INTERLACED;
1896 val |= TRANS_PROGRESSIVE;
1898 I915_WRITE(reg, val | TRANS_ENABLE);
1899 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1900 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1903 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1904 enum transcoder cpu_transcoder)
1906 u32 val, pipeconf_val;
1908 /* PCH only available on ILK+ */
1909 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1911 /* FDI must be feeding us bits for PCH ports */
1912 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1913 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1915 /* Workaround: set timing override bit. */
1916 val = I915_READ(_TRANSA_CHICKEN2);
1917 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1918 I915_WRITE(_TRANSA_CHICKEN2, val);
1921 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1923 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1924 PIPECONF_INTERLACED_ILK)
1925 val |= TRANS_INTERLACED;
1927 val |= TRANS_PROGRESSIVE;
1929 I915_WRITE(LPT_TRANSCONF, val);
1930 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1931 DRM_ERROR("Failed to enable PCH transcoder\n");
1934 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1937 struct drm_device *dev = dev_priv->dev;
1940 /* FDI relies on the transcoder */
1941 assert_fdi_tx_disabled(dev_priv, pipe);
1942 assert_fdi_rx_disabled(dev_priv, pipe);
1944 /* Ports must be off as well */
1945 assert_pch_ports_disabled(dev_priv, pipe);
1947 reg = PCH_TRANSCONF(pipe);
1948 val = I915_READ(reg);
1949 val &= ~TRANS_ENABLE;
1950 I915_WRITE(reg, val);
1951 /* wait for PCH transcoder off, transcoder state */
1952 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1953 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1955 if (!HAS_PCH_IBX(dev)) {
1956 /* Workaround: Clear the timing override chicken bit again. */
1957 reg = TRANS_CHICKEN2(pipe);
1958 val = I915_READ(reg);
1959 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1960 I915_WRITE(reg, val);
1964 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1968 val = I915_READ(LPT_TRANSCONF);
1969 val &= ~TRANS_ENABLE;
1970 I915_WRITE(LPT_TRANSCONF, val);
1971 /* wait for PCH transcoder off, transcoder state */
1972 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1973 DRM_ERROR("Failed to disable PCH transcoder\n");
1975 /* Workaround: clear timing override bit. */
1976 val = I915_READ(_TRANSA_CHICKEN2);
1977 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978 I915_WRITE(_TRANSA_CHICKEN2, val);
1982 * intel_enable_pipe - enable a pipe, asserting requirements
1983 * @crtc: crtc responsible for the pipe
1985 * Enable @crtc's pipe, making sure that various hardware specific requirements
1986 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1988 static void intel_enable_pipe(struct intel_crtc *crtc)
1990 struct drm_device *dev = crtc->base.dev;
1991 struct drm_i915_private *dev_priv = dev->dev_private;
1992 enum pipe pipe = crtc->pipe;
1993 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1995 enum pipe pch_transcoder;
1999 assert_planes_disabled(dev_priv, pipe);
2000 assert_cursor_disabled(dev_priv, pipe);
2001 assert_sprites_disabled(dev_priv, pipe);
2003 if (HAS_PCH_LPT(dev_priv->dev))
2004 pch_transcoder = TRANSCODER_A;
2006 pch_transcoder = pipe;
2009 * A pipe without a PLL won't actually be able to drive bits from
2010 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2013 if (!HAS_PCH_SPLIT(dev_priv->dev))
2014 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2015 assert_dsi_pll_enabled(dev_priv);
2017 assert_pll_enabled(dev_priv, pipe);
2019 if (crtc->config.has_pch_encoder) {
2020 /* if driving the PCH, we need FDI enabled */
2021 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2022 assert_fdi_tx_pll_enabled(dev_priv,
2023 (enum pipe) cpu_transcoder);
2025 /* FIXME: assert CPU port conditions for SNB+ */
2028 reg = PIPECONF(cpu_transcoder);
2029 val = I915_READ(reg);
2030 if (val & PIPECONF_ENABLE) {
2031 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2032 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2036 I915_WRITE(reg, val | PIPECONF_ENABLE);
2041 * intel_disable_pipe - disable a pipe, asserting requirements
2042 * @crtc: crtc whose pipes is to be disabled
2044 * Disable the pipe of @crtc, making sure that various hardware
2045 * specific requirements are met, if applicable, e.g. plane
2046 * disabled, panel fitter off, etc.
2048 * Will wait until the pipe has shut down before returning.
2050 static void intel_disable_pipe(struct intel_crtc *crtc)
2052 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2053 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2054 enum pipe pipe = crtc->pipe;
2059 * Make sure planes won't keep trying to pump pixels to us,
2060 * or we might hang the display.
2062 assert_planes_disabled(dev_priv, pipe);
2063 assert_cursor_disabled(dev_priv, pipe);
2064 assert_sprites_disabled(dev_priv, pipe);
2066 reg = PIPECONF(cpu_transcoder);
2067 val = I915_READ(reg);
2068 if ((val & PIPECONF_ENABLE) == 0)
2072 * Double wide has implications for planes
2073 * so best keep it disabled when not needed.
2075 if (crtc->config.double_wide)
2076 val &= ~PIPECONF_DOUBLE_WIDE;
2078 /* Don't disable pipe or pipe PLLs if needed */
2079 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2080 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2081 val &= ~PIPECONF_ENABLE;
2083 I915_WRITE(reg, val);
2084 if ((val & PIPECONF_ENABLE) == 0)
2085 intel_wait_for_pipe_off(crtc);
2089 * Plane regs are double buffered, going from enabled->disabled needs a
2090 * trigger in order to latch. The display address reg provides this.
2092 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2095 struct drm_device *dev = dev_priv->dev;
2096 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2098 I915_WRITE(reg, I915_READ(reg));
2103 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2104 * @plane: plane to be enabled
2105 * @crtc: crtc for the plane
2107 * Enable @plane on @crtc, making sure that the pipe is running first.
2109 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2110 struct drm_crtc *crtc)
2112 struct drm_device *dev = plane->dev;
2113 struct drm_i915_private *dev_priv = dev->dev_private;
2114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2116 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2117 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2119 if (intel_crtc->primary_enabled)
2122 intel_crtc->primary_enabled = true;
2124 dev_priv->display.update_primary_plane(crtc, plane->fb,
2128 * BDW signals flip done immediately if the plane
2129 * is disabled, even if the plane enable is already
2130 * armed to occur at the next vblank :(
2132 if (IS_BROADWELL(dev))
2133 intel_wait_for_vblank(dev, intel_crtc->pipe);
2137 * intel_disable_primary_hw_plane - disable the primary hardware plane
2138 * @plane: plane to be disabled
2139 * @crtc: crtc for the plane
2141 * Disable @plane on @crtc, making sure that the pipe is running first.
2143 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2144 struct drm_crtc *crtc)
2146 struct drm_device *dev = plane->dev;
2147 struct drm_i915_private *dev_priv = dev->dev_private;
2148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2150 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2152 if (!intel_crtc->primary_enabled)
2155 intel_crtc->primary_enabled = false;
2157 dev_priv->display.update_primary_plane(crtc, plane->fb,
2161 static bool need_vtd_wa(struct drm_device *dev)
2163 #ifdef CONFIG_INTEL_IOMMU
2164 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2170 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2174 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2175 return ALIGN(height, tile_height);
2179 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2180 struct drm_i915_gem_object *obj,
2181 struct intel_engine_cs *pipelined)
2183 struct drm_i915_private *dev_priv = dev->dev_private;
2187 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2189 switch (obj->tiling_mode) {
2190 case I915_TILING_NONE:
2191 if (INTEL_INFO(dev)->gen >= 9)
2192 alignment = 256 * 1024;
2193 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2194 alignment = 128 * 1024;
2195 else if (INTEL_INFO(dev)->gen >= 4)
2196 alignment = 4 * 1024;
2198 alignment = 64 * 1024;
2201 if (INTEL_INFO(dev)->gen >= 9)
2202 alignment = 256 * 1024;
2204 /* pin() will align the object as required by fence */
2209 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2215 /* Note that the w/a also requires 64 PTE of padding following the
2216 * bo. We currently fill all unused PTE with the shadow page and so
2217 * we should always have valid PTE following the scanout preventing
2220 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2221 alignment = 256 * 1024;
2224 * Global gtt pte registers are special registers which actually forward
2225 * writes to a chunk of system memory. Which means that there is no risk
2226 * that the register values disappear as soon as we call
2227 * intel_runtime_pm_put(), so it is correct to wrap only the
2228 * pin/unpin/fence and not more.
2230 intel_runtime_pm_get(dev_priv);
2232 dev_priv->mm.interruptible = false;
2233 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2235 goto err_interruptible;
2237 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2238 * fence, whereas 965+ only requires a fence if using
2239 * framebuffer compression. For simplicity, we always install
2240 * a fence as the cost is not that onerous.
2242 ret = i915_gem_object_get_fence(obj);
2246 i915_gem_object_pin_fence(obj);
2248 dev_priv->mm.interruptible = true;
2249 intel_runtime_pm_put(dev_priv);
2253 i915_gem_object_unpin_from_display_plane(obj);
2255 dev_priv->mm.interruptible = true;
2256 intel_runtime_pm_put(dev_priv);
2260 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2262 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2264 i915_gem_object_unpin_fence(obj);
2265 i915_gem_object_unpin_from_display_plane(obj);
2268 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2269 * is assumed to be a power-of-two. */
2270 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2271 unsigned int tiling_mode,
2275 if (tiling_mode != I915_TILING_NONE) {
2276 unsigned int tile_rows, tiles;
2281 tiles = *x / (512/cpp);
2284 return tile_rows * pitch * 8 + tiles * 4096;
2286 unsigned int offset;
2288 offset = *y * pitch + *x * cpp;
2290 *x = (offset & 4095) / cpp;
2291 return offset & -4096;
2295 int intel_format_to_fourcc(int format)
2298 case DISPPLANE_8BPP:
2299 return DRM_FORMAT_C8;
2300 case DISPPLANE_BGRX555:
2301 return DRM_FORMAT_XRGB1555;
2302 case DISPPLANE_BGRX565:
2303 return DRM_FORMAT_RGB565;
2305 case DISPPLANE_BGRX888:
2306 return DRM_FORMAT_XRGB8888;
2307 case DISPPLANE_RGBX888:
2308 return DRM_FORMAT_XBGR8888;
2309 case DISPPLANE_BGRX101010:
2310 return DRM_FORMAT_XRGB2101010;
2311 case DISPPLANE_RGBX101010:
2312 return DRM_FORMAT_XBGR2101010;
2316 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2317 struct intel_plane_config *plane_config)
2319 struct drm_device *dev = crtc->base.dev;
2320 struct drm_i915_gem_object *obj = NULL;
2321 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2322 u32 base = plane_config->base;
2324 if (plane_config->size == 0)
2327 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2328 plane_config->size);
2332 if (plane_config->tiled) {
2333 obj->tiling_mode = I915_TILING_X;
2334 obj->stride = crtc->base.primary->fb->pitches[0];
2337 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2338 mode_cmd.width = crtc->base.primary->fb->width;
2339 mode_cmd.height = crtc->base.primary->fb->height;
2340 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2342 mutex_lock(&dev->struct_mutex);
2344 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2346 DRM_DEBUG_KMS("intel fb init failed\n");
2350 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2351 mutex_unlock(&dev->struct_mutex);
2353 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2357 drm_gem_object_unreference(&obj->base);
2358 mutex_unlock(&dev->struct_mutex);
2362 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2363 struct intel_plane_config *plane_config)
2365 struct drm_device *dev = intel_crtc->base.dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2368 struct intel_crtc *i;
2369 struct drm_i915_gem_object *obj;
2371 if (!intel_crtc->base.primary->fb)
2374 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2377 kfree(intel_crtc->base.primary->fb);
2378 intel_crtc->base.primary->fb = NULL;
2381 * Failed to alloc the obj, check to see if we should share
2382 * an fb with another CRTC instead
2384 for_each_crtc(dev, c) {
2385 i = to_intel_crtc(c);
2387 if (c == &intel_crtc->base)
2393 obj = intel_fb_obj(c->primary->fb);
2397 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2398 if (obj->tiling_mode != I915_TILING_NONE)
2399 dev_priv->preserve_bios_swizzle = true;
2401 drm_framebuffer_reference(c->primary->fb);
2402 intel_crtc->base.primary->fb = c->primary->fb;
2403 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2409 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2410 struct drm_framebuffer *fb,
2413 struct drm_device *dev = crtc->dev;
2414 struct drm_i915_private *dev_priv = dev->dev_private;
2415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2416 struct drm_i915_gem_object *obj;
2417 int plane = intel_crtc->plane;
2418 unsigned long linear_offset;
2420 u32 reg = DSPCNTR(plane);
2423 if (!intel_crtc->primary_enabled) {
2425 if (INTEL_INFO(dev)->gen >= 4)
2426 I915_WRITE(DSPSURF(plane), 0);
2428 I915_WRITE(DSPADDR(plane), 0);
2433 obj = intel_fb_obj(fb);
2434 if (WARN_ON(obj == NULL))
2437 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2439 dspcntr = DISPPLANE_GAMMA_ENABLE;
2441 dspcntr |= DISPLAY_PLANE_ENABLE;
2443 if (INTEL_INFO(dev)->gen < 4) {
2444 if (intel_crtc->pipe == PIPE_B)
2445 dspcntr |= DISPPLANE_SEL_PIPE_B;
2447 /* pipesrc and dspsize control the size that is scaled from,
2448 * which should always be the user's requested size.
2450 I915_WRITE(DSPSIZE(plane),
2451 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2452 (intel_crtc->config.pipe_src_w - 1));
2453 I915_WRITE(DSPPOS(plane), 0);
2456 switch (fb->pixel_format) {
2458 dspcntr |= DISPPLANE_8BPP;
2460 case DRM_FORMAT_XRGB1555:
2461 case DRM_FORMAT_ARGB1555:
2462 dspcntr |= DISPPLANE_BGRX555;
2464 case DRM_FORMAT_RGB565:
2465 dspcntr |= DISPPLANE_BGRX565;
2467 case DRM_FORMAT_XRGB8888:
2468 case DRM_FORMAT_ARGB8888:
2469 dspcntr |= DISPPLANE_BGRX888;
2471 case DRM_FORMAT_XBGR8888:
2472 case DRM_FORMAT_ABGR8888:
2473 dspcntr |= DISPPLANE_RGBX888;
2475 case DRM_FORMAT_XRGB2101010:
2476 case DRM_FORMAT_ARGB2101010:
2477 dspcntr |= DISPPLANE_BGRX101010;
2479 case DRM_FORMAT_XBGR2101010:
2480 case DRM_FORMAT_ABGR2101010:
2481 dspcntr |= DISPPLANE_RGBX101010;
2487 if (INTEL_INFO(dev)->gen >= 4 &&
2488 obj->tiling_mode != I915_TILING_NONE)
2489 dspcntr |= DISPPLANE_TILED;
2492 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2494 linear_offset = y * fb->pitches[0] + x * pixel_size;
2496 if (INTEL_INFO(dev)->gen >= 4) {
2497 intel_crtc->dspaddr_offset =
2498 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2501 linear_offset -= intel_crtc->dspaddr_offset;
2503 intel_crtc->dspaddr_offset = linear_offset;
2506 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2507 dspcntr |= DISPPLANE_ROTATE_180;
2509 x += (intel_crtc->config.pipe_src_w - 1);
2510 y += (intel_crtc->config.pipe_src_h - 1);
2512 /* Finding the last pixel of the last line of the display
2513 data and adding to linear_offset*/
2515 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2516 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2519 I915_WRITE(reg, dspcntr);
2521 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2522 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2524 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2525 if (INTEL_INFO(dev)->gen >= 4) {
2526 I915_WRITE(DSPSURF(plane),
2527 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2528 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2529 I915_WRITE(DSPLINOFF(plane), linear_offset);
2531 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2535 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2536 struct drm_framebuffer *fb,
2539 struct drm_device *dev = crtc->dev;
2540 struct drm_i915_private *dev_priv = dev->dev_private;
2541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2542 struct drm_i915_gem_object *obj;
2543 int plane = intel_crtc->plane;
2544 unsigned long linear_offset;
2546 u32 reg = DSPCNTR(plane);
2549 if (!intel_crtc->primary_enabled) {
2551 I915_WRITE(DSPSURF(plane), 0);
2556 obj = intel_fb_obj(fb);
2557 if (WARN_ON(obj == NULL))
2560 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2562 dspcntr = DISPPLANE_GAMMA_ENABLE;
2564 dspcntr |= DISPLAY_PLANE_ENABLE;
2566 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2567 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2569 switch (fb->pixel_format) {
2571 dspcntr |= DISPPLANE_8BPP;
2573 case DRM_FORMAT_RGB565:
2574 dspcntr |= DISPPLANE_BGRX565;
2576 case DRM_FORMAT_XRGB8888:
2577 case DRM_FORMAT_ARGB8888:
2578 dspcntr |= DISPPLANE_BGRX888;
2580 case DRM_FORMAT_XBGR8888:
2581 case DRM_FORMAT_ABGR8888:
2582 dspcntr |= DISPPLANE_RGBX888;
2584 case DRM_FORMAT_XRGB2101010:
2585 case DRM_FORMAT_ARGB2101010:
2586 dspcntr |= DISPPLANE_BGRX101010;
2588 case DRM_FORMAT_XBGR2101010:
2589 case DRM_FORMAT_ABGR2101010:
2590 dspcntr |= DISPPLANE_RGBX101010;
2596 if (obj->tiling_mode != I915_TILING_NONE)
2597 dspcntr |= DISPPLANE_TILED;
2599 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2600 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2602 linear_offset = y * fb->pitches[0] + x * pixel_size;
2603 intel_crtc->dspaddr_offset =
2604 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2607 linear_offset -= intel_crtc->dspaddr_offset;
2608 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2609 dspcntr |= DISPPLANE_ROTATE_180;
2611 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2612 x += (intel_crtc->config.pipe_src_w - 1);
2613 y += (intel_crtc->config.pipe_src_h - 1);
2615 /* Finding the last pixel of the last line of the display
2616 data and adding to linear_offset*/
2618 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2619 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2623 I915_WRITE(reg, dspcntr);
2625 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2626 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2628 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2629 I915_WRITE(DSPSURF(plane),
2630 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2631 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2632 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2634 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2635 I915_WRITE(DSPLINOFF(plane), linear_offset);
2640 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2641 struct drm_framebuffer *fb,
2644 struct drm_device *dev = crtc->dev;
2645 struct drm_i915_private *dev_priv = dev->dev_private;
2646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2647 struct intel_framebuffer *intel_fb;
2648 struct drm_i915_gem_object *obj;
2649 int pipe = intel_crtc->pipe;
2650 u32 plane_ctl, stride;
2652 if (!intel_crtc->primary_enabled) {
2653 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2654 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2655 POSTING_READ(PLANE_CTL(pipe, 0));
2659 plane_ctl = PLANE_CTL_ENABLE |
2660 PLANE_CTL_PIPE_GAMMA_ENABLE |
2661 PLANE_CTL_PIPE_CSC_ENABLE;
2663 switch (fb->pixel_format) {
2664 case DRM_FORMAT_RGB565:
2665 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2667 case DRM_FORMAT_XRGB8888:
2668 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2670 case DRM_FORMAT_XBGR8888:
2671 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2672 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2674 case DRM_FORMAT_XRGB2101010:
2675 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2677 case DRM_FORMAT_XBGR2101010:
2678 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2679 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2685 intel_fb = to_intel_framebuffer(fb);
2686 obj = intel_fb->obj;
2689 * The stride is either expressed as a multiple of 64 bytes chunks for
2690 * linear buffers or in number of tiles for tiled buffers.
2692 switch (obj->tiling_mode) {
2693 case I915_TILING_NONE:
2694 stride = fb->pitches[0] >> 6;
2697 plane_ctl |= PLANE_CTL_TILED_X;
2698 stride = fb->pitches[0] >> 9;
2704 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2705 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2706 plane_ctl |= PLANE_CTL_ROTATE_180;
2708 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2710 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2711 i915_gem_obj_ggtt_offset(obj),
2712 x, y, fb->width, fb->height,
2715 I915_WRITE(PLANE_POS(pipe, 0), 0);
2716 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2717 I915_WRITE(PLANE_SIZE(pipe, 0),
2718 (intel_crtc->config.pipe_src_h - 1) << 16 |
2719 (intel_crtc->config.pipe_src_w - 1));
2720 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2721 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2723 POSTING_READ(PLANE_SURF(pipe, 0));
2726 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2728 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2729 int x, int y, enum mode_set_atomic state)
2731 struct drm_device *dev = crtc->dev;
2732 struct drm_i915_private *dev_priv = dev->dev_private;
2734 if (dev_priv->display.disable_fbc)
2735 dev_priv->display.disable_fbc(dev);
2737 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2742 void intel_display_handle_reset(struct drm_device *dev)
2744 struct drm_i915_private *dev_priv = dev->dev_private;
2745 struct drm_crtc *crtc;
2748 * Flips in the rings have been nuked by the reset,
2749 * so complete all pending flips so that user space
2750 * will get its events and not get stuck.
2752 * Also update the base address of all primary
2753 * planes to the the last fb to make sure we're
2754 * showing the correct fb after a reset.
2756 * Need to make two loops over the crtcs so that we
2757 * don't try to grab a crtc mutex before the
2758 * pending_flip_queue really got woken up.
2761 for_each_crtc(dev, crtc) {
2762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2763 enum plane plane = intel_crtc->plane;
2765 intel_prepare_page_flip(dev, plane);
2766 intel_finish_page_flip_plane(dev, plane);
2769 for_each_crtc(dev, crtc) {
2770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2772 drm_modeset_lock(&crtc->mutex, NULL);
2774 * FIXME: Once we have proper support for primary planes (and
2775 * disabling them without disabling the entire crtc) allow again
2776 * a NULL crtc->primary->fb.
2778 if (intel_crtc->active && crtc->primary->fb)
2779 dev_priv->display.update_primary_plane(crtc,
2783 drm_modeset_unlock(&crtc->mutex);
2788 intel_finish_fb(struct drm_framebuffer *old_fb)
2790 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2791 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2792 bool was_interruptible = dev_priv->mm.interruptible;
2795 /* Big Hammer, we also need to ensure that any pending
2796 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2797 * current scanout is retired before unpinning the old
2800 * This should only fail upon a hung GPU, in which case we
2801 * can safely continue.
2803 dev_priv->mm.interruptible = false;
2804 ret = i915_gem_object_finish_gpu(obj);
2805 dev_priv->mm.interruptible = was_interruptible;
2810 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2812 struct drm_device *dev = crtc->dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2817 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2818 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2821 spin_lock_irq(&dev->event_lock);
2822 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2823 spin_unlock_irq(&dev->event_lock);
2828 static void intel_update_pipe_size(struct intel_crtc *crtc)
2830 struct drm_device *dev = crtc->base.dev;
2831 struct drm_i915_private *dev_priv = dev->dev_private;
2832 const struct drm_display_mode *adjusted_mode;
2838 * Update pipe size and adjust fitter if needed: the reason for this is
2839 * that in compute_mode_changes we check the native mode (not the pfit
2840 * mode) to see if we can flip rather than do a full mode set. In the
2841 * fastboot case, we'll flip, but if we don't update the pipesrc and
2842 * pfit state, we'll end up with a big fb scanned out into the wrong
2845 * To fix this properly, we need to hoist the checks up into
2846 * compute_mode_changes (or above), check the actual pfit state and
2847 * whether the platform allows pfit disable with pipe active, and only
2848 * then update the pipesrc and pfit state, even on the flip path.
2851 adjusted_mode = &crtc->config.adjusted_mode;
2853 I915_WRITE(PIPESRC(crtc->pipe),
2854 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2855 (adjusted_mode->crtc_vdisplay - 1));
2856 if (!crtc->config.pch_pfit.enabled &&
2857 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2858 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2859 I915_WRITE(PF_CTL(crtc->pipe), 0);
2860 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2861 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2863 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2864 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2868 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2869 struct drm_framebuffer *fb)
2871 struct drm_device *dev = crtc->dev;
2872 struct drm_i915_private *dev_priv = dev->dev_private;
2873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2874 enum pipe pipe = intel_crtc->pipe;
2875 struct drm_framebuffer *old_fb = crtc->primary->fb;
2876 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2877 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2880 if (intel_crtc_has_pending_flip(crtc)) {
2881 DRM_ERROR("pipe is still busy with an old pageflip\n");
2887 DRM_ERROR("No FB bound\n");
2891 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2892 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2893 plane_name(intel_crtc->plane),
2894 INTEL_INFO(dev)->num_pipes);
2898 mutex_lock(&dev->struct_mutex);
2899 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2901 i915_gem_track_fb(old_obj, obj,
2902 INTEL_FRONTBUFFER_PRIMARY(pipe));
2903 mutex_unlock(&dev->struct_mutex);
2905 DRM_ERROR("pin & fence failed\n");
2909 intel_update_pipe_size(intel_crtc);
2911 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2913 if (intel_crtc->active)
2914 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2916 crtc->primary->fb = fb;
2921 if (intel_crtc->active && old_fb != fb)
2922 intel_wait_for_vblank(dev, intel_crtc->pipe);
2923 mutex_lock(&dev->struct_mutex);
2924 intel_unpin_fb_obj(old_obj);
2925 mutex_unlock(&dev->struct_mutex);
2928 mutex_lock(&dev->struct_mutex);
2929 intel_update_fbc(dev);
2930 mutex_unlock(&dev->struct_mutex);
2935 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2937 struct drm_device *dev = crtc->dev;
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2940 int pipe = intel_crtc->pipe;
2943 /* enable normal train */
2944 reg = FDI_TX_CTL(pipe);
2945 temp = I915_READ(reg);
2946 if (IS_IVYBRIDGE(dev)) {
2947 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2948 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2950 temp &= ~FDI_LINK_TRAIN_NONE;
2951 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2953 I915_WRITE(reg, temp);
2955 reg = FDI_RX_CTL(pipe);
2956 temp = I915_READ(reg);
2957 if (HAS_PCH_CPT(dev)) {
2958 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2959 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2961 temp &= ~FDI_LINK_TRAIN_NONE;
2962 temp |= FDI_LINK_TRAIN_NONE;
2964 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2966 /* wait one idle pattern time */
2970 /* IVB wants error correction enabled */
2971 if (IS_IVYBRIDGE(dev))
2972 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2973 FDI_FE_ERRC_ENABLE);
2976 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2978 return crtc->base.enabled && crtc->active &&
2979 crtc->config.has_pch_encoder;
2982 static void ivb_modeset_global_resources(struct drm_device *dev)
2984 struct drm_i915_private *dev_priv = dev->dev_private;
2985 struct intel_crtc *pipe_B_crtc =
2986 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2987 struct intel_crtc *pipe_C_crtc =
2988 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2992 * When everything is off disable fdi C so that we could enable fdi B
2993 * with all lanes. Note that we don't care about enabled pipes without
2994 * an enabled pch encoder.
2996 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2997 !pipe_has_enabled_pch(pipe_C_crtc)) {
2998 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2999 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3001 temp = I915_READ(SOUTH_CHICKEN1);
3002 temp &= ~FDI_BC_BIFURCATION_SELECT;
3003 DRM_DEBUG_KMS("disabling fdi C rx\n");
3004 I915_WRITE(SOUTH_CHICKEN1, temp);
3008 /* The FDI link training functions for ILK/Ibexpeak. */
3009 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3011 struct drm_device *dev = crtc->dev;
3012 struct drm_i915_private *dev_priv = dev->dev_private;
3013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3014 int pipe = intel_crtc->pipe;
3015 u32 reg, temp, tries;
3017 /* FDI needs bits from pipe first */
3018 assert_pipe_enabled(dev_priv, pipe);
3020 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3022 reg = FDI_RX_IMR(pipe);
3023 temp = I915_READ(reg);
3024 temp &= ~FDI_RX_SYMBOL_LOCK;
3025 temp &= ~FDI_RX_BIT_LOCK;
3026 I915_WRITE(reg, temp);
3030 /* enable CPU FDI TX and PCH FDI RX */
3031 reg = FDI_TX_CTL(pipe);
3032 temp = I915_READ(reg);
3033 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3034 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3035 temp &= ~FDI_LINK_TRAIN_NONE;
3036 temp |= FDI_LINK_TRAIN_PATTERN_1;
3037 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3039 reg = FDI_RX_CTL(pipe);
3040 temp = I915_READ(reg);
3041 temp &= ~FDI_LINK_TRAIN_NONE;
3042 temp |= FDI_LINK_TRAIN_PATTERN_1;
3043 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3048 /* Ironlake workaround, enable clock pointer after FDI enable*/
3049 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3050 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3051 FDI_RX_PHASE_SYNC_POINTER_EN);
3053 reg = FDI_RX_IIR(pipe);
3054 for (tries = 0; tries < 5; tries++) {
3055 temp = I915_READ(reg);
3056 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3058 if ((temp & FDI_RX_BIT_LOCK)) {
3059 DRM_DEBUG_KMS("FDI train 1 done.\n");
3060 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3065 DRM_ERROR("FDI train 1 fail!\n");
3068 reg = FDI_TX_CTL(pipe);
3069 temp = I915_READ(reg);
3070 temp &= ~FDI_LINK_TRAIN_NONE;
3071 temp |= FDI_LINK_TRAIN_PATTERN_2;
3072 I915_WRITE(reg, temp);
3074 reg = FDI_RX_CTL(pipe);
3075 temp = I915_READ(reg);
3076 temp &= ~FDI_LINK_TRAIN_NONE;
3077 temp |= FDI_LINK_TRAIN_PATTERN_2;
3078 I915_WRITE(reg, temp);
3083 reg = FDI_RX_IIR(pipe);
3084 for (tries = 0; tries < 5; tries++) {
3085 temp = I915_READ(reg);
3086 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3088 if (temp & FDI_RX_SYMBOL_LOCK) {
3089 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3090 DRM_DEBUG_KMS("FDI train 2 done.\n");
3095 DRM_ERROR("FDI train 2 fail!\n");
3097 DRM_DEBUG_KMS("FDI train done\n");
3101 static const int snb_b_fdi_train_param[] = {
3102 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3103 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3104 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3105 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3108 /* The FDI link training functions for SNB/Cougarpoint. */
3109 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3111 struct drm_device *dev = crtc->dev;
3112 struct drm_i915_private *dev_priv = dev->dev_private;
3113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3114 int pipe = intel_crtc->pipe;
3115 u32 reg, temp, i, retry;
3117 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3119 reg = FDI_RX_IMR(pipe);
3120 temp = I915_READ(reg);
3121 temp &= ~FDI_RX_SYMBOL_LOCK;
3122 temp &= ~FDI_RX_BIT_LOCK;
3123 I915_WRITE(reg, temp);
3128 /* enable CPU FDI TX and PCH FDI RX */
3129 reg = FDI_TX_CTL(pipe);
3130 temp = I915_READ(reg);
3131 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3132 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3133 temp &= ~FDI_LINK_TRAIN_NONE;
3134 temp |= FDI_LINK_TRAIN_PATTERN_1;
3135 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3137 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3138 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3140 I915_WRITE(FDI_RX_MISC(pipe),
3141 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3143 reg = FDI_RX_CTL(pipe);
3144 temp = I915_READ(reg);
3145 if (HAS_PCH_CPT(dev)) {
3146 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3147 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3149 temp &= ~FDI_LINK_TRAIN_NONE;
3150 temp |= FDI_LINK_TRAIN_PATTERN_1;
3152 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3157 for (i = 0; i < 4; i++) {
3158 reg = FDI_TX_CTL(pipe);
3159 temp = I915_READ(reg);
3160 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3161 temp |= snb_b_fdi_train_param[i];
3162 I915_WRITE(reg, temp);
3167 for (retry = 0; retry < 5; retry++) {
3168 reg = FDI_RX_IIR(pipe);
3169 temp = I915_READ(reg);
3170 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3171 if (temp & FDI_RX_BIT_LOCK) {
3172 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3173 DRM_DEBUG_KMS("FDI train 1 done.\n");
3182 DRM_ERROR("FDI train 1 fail!\n");
3185 reg = FDI_TX_CTL(pipe);
3186 temp = I915_READ(reg);
3187 temp &= ~FDI_LINK_TRAIN_NONE;
3188 temp |= FDI_LINK_TRAIN_PATTERN_2;
3190 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3192 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3194 I915_WRITE(reg, temp);
3196 reg = FDI_RX_CTL(pipe);
3197 temp = I915_READ(reg);
3198 if (HAS_PCH_CPT(dev)) {
3199 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3200 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3202 temp &= ~FDI_LINK_TRAIN_NONE;
3203 temp |= FDI_LINK_TRAIN_PATTERN_2;
3205 I915_WRITE(reg, temp);
3210 for (i = 0; i < 4; i++) {
3211 reg = FDI_TX_CTL(pipe);
3212 temp = I915_READ(reg);
3213 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3214 temp |= snb_b_fdi_train_param[i];
3215 I915_WRITE(reg, temp);
3220 for (retry = 0; retry < 5; retry++) {
3221 reg = FDI_RX_IIR(pipe);
3222 temp = I915_READ(reg);
3223 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3224 if (temp & FDI_RX_SYMBOL_LOCK) {
3225 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3226 DRM_DEBUG_KMS("FDI train 2 done.\n");
3235 DRM_ERROR("FDI train 2 fail!\n");
3237 DRM_DEBUG_KMS("FDI train done.\n");
3240 /* Manual link training for Ivy Bridge A0 parts */
3241 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3243 struct drm_device *dev = crtc->dev;
3244 struct drm_i915_private *dev_priv = dev->dev_private;
3245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3246 int pipe = intel_crtc->pipe;
3247 u32 reg, temp, i, j;
3249 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3251 reg = FDI_RX_IMR(pipe);
3252 temp = I915_READ(reg);
3253 temp &= ~FDI_RX_SYMBOL_LOCK;
3254 temp &= ~FDI_RX_BIT_LOCK;
3255 I915_WRITE(reg, temp);
3260 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3261 I915_READ(FDI_RX_IIR(pipe)));
3263 /* Try each vswing and preemphasis setting twice before moving on */
3264 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3265 /* disable first in case we need to retry */
3266 reg = FDI_TX_CTL(pipe);
3267 temp = I915_READ(reg);
3268 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3269 temp &= ~FDI_TX_ENABLE;
3270 I915_WRITE(reg, temp);
3272 reg = FDI_RX_CTL(pipe);
3273 temp = I915_READ(reg);
3274 temp &= ~FDI_LINK_TRAIN_AUTO;
3275 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3276 temp &= ~FDI_RX_ENABLE;
3277 I915_WRITE(reg, temp);
3279 /* enable CPU FDI TX and PCH FDI RX */
3280 reg = FDI_TX_CTL(pipe);
3281 temp = I915_READ(reg);
3282 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3283 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3284 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3285 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3286 temp |= snb_b_fdi_train_param[j/2];
3287 temp |= FDI_COMPOSITE_SYNC;
3288 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3290 I915_WRITE(FDI_RX_MISC(pipe),
3291 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3293 reg = FDI_RX_CTL(pipe);
3294 temp = I915_READ(reg);
3295 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3296 temp |= FDI_COMPOSITE_SYNC;
3297 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3300 udelay(1); /* should be 0.5us */
3302 for (i = 0; i < 4; i++) {
3303 reg = FDI_RX_IIR(pipe);
3304 temp = I915_READ(reg);
3305 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3307 if (temp & FDI_RX_BIT_LOCK ||
3308 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3309 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3310 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3314 udelay(1); /* should be 0.5us */
3317 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3322 reg = FDI_TX_CTL(pipe);
3323 temp = I915_READ(reg);
3324 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3325 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3326 I915_WRITE(reg, temp);
3328 reg = FDI_RX_CTL(pipe);
3329 temp = I915_READ(reg);
3330 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3331 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3332 I915_WRITE(reg, temp);
3335 udelay(2); /* should be 1.5us */
3337 for (i = 0; i < 4; i++) {
3338 reg = FDI_RX_IIR(pipe);
3339 temp = I915_READ(reg);
3340 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3342 if (temp & FDI_RX_SYMBOL_LOCK ||
3343 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3344 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3345 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3349 udelay(2); /* should be 1.5us */
3352 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3356 DRM_DEBUG_KMS("FDI train done.\n");
3359 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3361 struct drm_device *dev = intel_crtc->base.dev;
3362 struct drm_i915_private *dev_priv = dev->dev_private;
3363 int pipe = intel_crtc->pipe;
3367 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3368 reg = FDI_RX_CTL(pipe);
3369 temp = I915_READ(reg);
3370 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3371 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3372 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3373 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3378 /* Switch from Rawclk to PCDclk */
3379 temp = I915_READ(reg);
3380 I915_WRITE(reg, temp | FDI_PCDCLK);
3385 /* Enable CPU FDI TX PLL, always on for Ironlake */
3386 reg = FDI_TX_CTL(pipe);
3387 temp = I915_READ(reg);
3388 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3389 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3396 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3398 struct drm_device *dev = intel_crtc->base.dev;
3399 struct drm_i915_private *dev_priv = dev->dev_private;
3400 int pipe = intel_crtc->pipe;
3403 /* Switch from PCDclk to Rawclk */
3404 reg = FDI_RX_CTL(pipe);
3405 temp = I915_READ(reg);
3406 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3408 /* Disable CPU FDI TX PLL */
3409 reg = FDI_TX_CTL(pipe);
3410 temp = I915_READ(reg);
3411 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3416 reg = FDI_RX_CTL(pipe);
3417 temp = I915_READ(reg);
3418 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3420 /* Wait for the clocks to turn off. */
3425 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3427 struct drm_device *dev = crtc->dev;
3428 struct drm_i915_private *dev_priv = dev->dev_private;
3429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3430 int pipe = intel_crtc->pipe;
3433 /* disable CPU FDI tx and PCH FDI rx */
3434 reg = FDI_TX_CTL(pipe);
3435 temp = I915_READ(reg);
3436 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3439 reg = FDI_RX_CTL(pipe);
3440 temp = I915_READ(reg);
3441 temp &= ~(0x7 << 16);
3442 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3443 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3448 /* Ironlake workaround, disable clock pointer after downing FDI */
3449 if (HAS_PCH_IBX(dev))
3450 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3452 /* still set train pattern 1 */
3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_1;
3457 I915_WRITE(reg, temp);
3459 reg = FDI_RX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 if (HAS_PCH_CPT(dev)) {
3462 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3463 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3465 temp &= ~FDI_LINK_TRAIN_NONE;
3466 temp |= FDI_LINK_TRAIN_PATTERN_1;
3468 /* BPC in FDI rx is consistent with that in PIPECONF */
3469 temp &= ~(0x07 << 16);
3470 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3471 I915_WRITE(reg, temp);
3477 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3479 struct intel_crtc *crtc;
3481 /* Note that we don't need to be called with mode_config.lock here
3482 * as our list of CRTC objects is static for the lifetime of the
3483 * device and so cannot disappear as we iterate. Similarly, we can
3484 * happily treat the predicates as racy, atomic checks as userspace
3485 * cannot claim and pin a new fb without at least acquring the
3486 * struct_mutex and so serialising with us.
3488 for_each_intel_crtc(dev, crtc) {
3489 if (atomic_read(&crtc->unpin_work_count) == 0)
3492 if (crtc->unpin_work)
3493 intel_wait_for_vblank(dev, crtc->pipe);
3501 static void page_flip_completed(struct intel_crtc *intel_crtc)
3503 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3504 struct intel_unpin_work *work = intel_crtc->unpin_work;
3506 /* ensure that the unpin work is consistent wrt ->pending. */
3508 intel_crtc->unpin_work = NULL;
3511 drm_send_vblank_event(intel_crtc->base.dev,
3515 drm_crtc_vblank_put(&intel_crtc->base);
3517 wake_up_all(&dev_priv->pending_flip_queue);
3518 queue_work(dev_priv->wq, &work->work);
3520 trace_i915_flip_complete(intel_crtc->plane,
3521 work->pending_flip_obj);
3524 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3526 struct drm_device *dev = crtc->dev;
3527 struct drm_i915_private *dev_priv = dev->dev_private;
3529 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3530 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3531 !intel_crtc_has_pending_flip(crtc),
3533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3535 spin_lock_irq(&dev->event_lock);
3536 if (intel_crtc->unpin_work) {
3537 WARN_ONCE(1, "Removing stuck page flip\n");
3538 page_flip_completed(intel_crtc);
3540 spin_unlock_irq(&dev->event_lock);
3543 if (crtc->primary->fb) {
3544 mutex_lock(&dev->struct_mutex);
3545 intel_finish_fb(crtc->primary->fb);
3546 mutex_unlock(&dev->struct_mutex);
3550 /* Program iCLKIP clock to the desired frequency */
3551 static void lpt_program_iclkip(struct drm_crtc *crtc)
3553 struct drm_device *dev = crtc->dev;
3554 struct drm_i915_private *dev_priv = dev->dev_private;
3555 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3556 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3559 mutex_lock(&dev_priv->dpio_lock);
3561 /* It is necessary to ungate the pixclk gate prior to programming
3562 * the divisors, and gate it back when it is done.
3564 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3566 /* Disable SSCCTL */
3567 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3568 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3572 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3573 if (clock == 20000) {
3578 /* The iCLK virtual clock root frequency is in MHz,
3579 * but the adjusted_mode->crtc_clock in in KHz. To get the
3580 * divisors, it is necessary to divide one by another, so we
3581 * convert the virtual clock precision to KHz here for higher
3584 u32 iclk_virtual_root_freq = 172800 * 1000;
3585 u32 iclk_pi_range = 64;
3586 u32 desired_divisor, msb_divisor_value, pi_value;
3588 desired_divisor = (iclk_virtual_root_freq / clock);
3589 msb_divisor_value = desired_divisor / iclk_pi_range;
3590 pi_value = desired_divisor % iclk_pi_range;
3593 divsel = msb_divisor_value - 2;
3594 phaseinc = pi_value;
3597 /* This should not happen with any sane values */
3598 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3599 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3600 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3601 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3603 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3610 /* Program SSCDIVINTPHASE6 */
3611 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3612 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3613 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3614 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3615 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3616 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3617 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3618 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3620 /* Program SSCAUXDIV */
3621 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3622 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3623 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3624 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3626 /* Enable modulator and associated divider */
3627 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3628 temp &= ~SBI_SSCCTL_DISABLE;
3629 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3631 /* Wait for initialization time */
3634 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3636 mutex_unlock(&dev_priv->dpio_lock);
3639 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3640 enum pipe pch_transcoder)
3642 struct drm_device *dev = crtc->base.dev;
3643 struct drm_i915_private *dev_priv = dev->dev_private;
3644 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3646 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3647 I915_READ(HTOTAL(cpu_transcoder)));
3648 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3649 I915_READ(HBLANK(cpu_transcoder)));
3650 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3651 I915_READ(HSYNC(cpu_transcoder)));
3653 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3654 I915_READ(VTOTAL(cpu_transcoder)));
3655 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3656 I915_READ(VBLANK(cpu_transcoder)));
3657 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3658 I915_READ(VSYNC(cpu_transcoder)));
3659 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3660 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3663 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3665 struct drm_i915_private *dev_priv = dev->dev_private;
3668 temp = I915_READ(SOUTH_CHICKEN1);
3669 if (temp & FDI_BC_BIFURCATION_SELECT)
3672 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3673 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3675 temp |= FDI_BC_BIFURCATION_SELECT;
3676 DRM_DEBUG_KMS("enabling fdi C rx\n");
3677 I915_WRITE(SOUTH_CHICKEN1, temp);
3678 POSTING_READ(SOUTH_CHICKEN1);
3681 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3683 struct drm_device *dev = intel_crtc->base.dev;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3686 switch (intel_crtc->pipe) {
3690 if (intel_crtc->config.fdi_lanes > 2)
3691 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3693 cpt_enable_fdi_bc_bifurcation(dev);
3697 cpt_enable_fdi_bc_bifurcation(dev);
3706 * Enable PCH resources required for PCH ports:
3708 * - FDI training & RX/TX
3709 * - update transcoder timings
3710 * - DP transcoding bits
3713 static void ironlake_pch_enable(struct drm_crtc *crtc)
3715 struct drm_device *dev = crtc->dev;
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3718 int pipe = intel_crtc->pipe;
3721 assert_pch_transcoder_disabled(dev_priv, pipe);
3723 if (IS_IVYBRIDGE(dev))
3724 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3726 /* Write the TU size bits before fdi link training, so that error
3727 * detection works. */
3728 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3729 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3731 /* For PCH output, training FDI link */
3732 dev_priv->display.fdi_link_train(crtc);
3734 /* We need to program the right clock selection before writing the pixel
3735 * mutliplier into the DPLL. */
3736 if (HAS_PCH_CPT(dev)) {
3739 temp = I915_READ(PCH_DPLL_SEL);
3740 temp |= TRANS_DPLL_ENABLE(pipe);
3741 sel = TRANS_DPLLB_SEL(pipe);
3742 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3746 I915_WRITE(PCH_DPLL_SEL, temp);
3749 /* XXX: pch pll's can be enabled any time before we enable the PCH
3750 * transcoder, and we actually should do this to not upset any PCH
3751 * transcoder that already use the clock when we share it.
3753 * Note that enable_shared_dpll tries to do the right thing, but
3754 * get_shared_dpll unconditionally resets the pll - we need that to have
3755 * the right LVDS enable sequence. */
3756 intel_enable_shared_dpll(intel_crtc);
3758 /* set transcoder timing, panel must allow it */
3759 assert_panel_unlocked(dev_priv, pipe);
3760 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3762 intel_fdi_normal_train(crtc);
3764 /* For PCH DP, enable TRANS_DP_CTL */
3765 if (HAS_PCH_CPT(dev) &&
3766 (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3767 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_EDP))) {
3768 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3769 reg = TRANS_DP_CTL(pipe);
3770 temp = I915_READ(reg);
3771 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3772 TRANS_DP_SYNC_MASK |
3774 temp |= (TRANS_DP_OUTPUT_ENABLE |
3775 TRANS_DP_ENH_FRAMING);
3776 temp |= bpc << 9; /* same format but at 11:9 */
3778 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3779 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3780 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3781 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3783 switch (intel_trans_dp_port_sel(crtc)) {
3785 temp |= TRANS_DP_PORT_SEL_B;
3788 temp |= TRANS_DP_PORT_SEL_C;
3791 temp |= TRANS_DP_PORT_SEL_D;
3797 I915_WRITE(reg, temp);
3800 ironlake_enable_pch_transcoder(dev_priv, pipe);
3803 static void lpt_pch_enable(struct drm_crtc *crtc)
3805 struct drm_device *dev = crtc->dev;
3806 struct drm_i915_private *dev_priv = dev->dev_private;
3807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3808 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3810 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3812 lpt_program_iclkip(crtc);
3814 /* Set transcoder timing. */
3815 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3817 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3820 void intel_put_shared_dpll(struct intel_crtc *crtc)
3822 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3827 if (pll->refcount == 0) {
3828 WARN(1, "bad %s refcount\n", pll->name);
3832 if (--pll->refcount == 0) {
3834 WARN_ON(pll->active);
3837 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3840 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3842 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3843 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3844 enum intel_dpll_id i;
3847 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3848 crtc->base.base.id, pll->name);
3849 intel_put_shared_dpll(crtc);
3852 if (HAS_PCH_IBX(dev_priv->dev)) {
3853 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3854 i = (enum intel_dpll_id) crtc->pipe;
3855 pll = &dev_priv->shared_dplls[i];
3857 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3858 crtc->base.base.id, pll->name);
3860 WARN_ON(pll->refcount);
3865 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3866 pll = &dev_priv->shared_dplls[i];
3868 /* Only want to check enabled timings first */
3869 if (pll->refcount == 0)
3872 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3873 sizeof(pll->hw_state)) == 0) {
3874 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3876 pll->name, pll->refcount, pll->active);
3882 /* Ok no matching timings, maybe there's a free one? */
3883 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3884 pll = &dev_priv->shared_dplls[i];
3885 if (pll->refcount == 0) {
3886 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3887 crtc->base.base.id, pll->name);
3895 if (pll->refcount == 0)
3896 pll->hw_state = crtc->config.dpll_hw_state;
3898 crtc->config.shared_dpll = i;
3899 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3900 pipe_name(crtc->pipe));
3907 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3909 struct drm_i915_private *dev_priv = dev->dev_private;
3910 int dslreg = PIPEDSL(pipe);
3913 temp = I915_READ(dslreg);
3915 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3916 if (wait_for(I915_READ(dslreg) != temp, 5))
3917 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3921 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3923 struct drm_device *dev = crtc->base.dev;
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925 int pipe = crtc->pipe;
3927 if (crtc->config.pch_pfit.enabled) {
3928 /* Force use of hard-coded filter coefficients
3929 * as some pre-programmed values are broken,
3932 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3933 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3934 PF_PIPE_SEL_IVB(pipe));
3936 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3937 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3938 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3942 static void intel_enable_planes(struct drm_crtc *crtc)
3944 struct drm_device *dev = crtc->dev;
3945 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3946 struct drm_plane *plane;
3947 struct intel_plane *intel_plane;
3949 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3950 intel_plane = to_intel_plane(plane);
3951 if (intel_plane->pipe == pipe)
3952 intel_plane_restore(&intel_plane->base);
3956 static void intel_disable_planes(struct drm_crtc *crtc)
3958 struct drm_device *dev = crtc->dev;
3959 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3960 struct drm_plane *plane;
3961 struct intel_plane *intel_plane;
3963 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3964 intel_plane = to_intel_plane(plane);
3965 if (intel_plane->pipe == pipe)
3966 intel_plane_disable(&intel_plane->base);
3970 void hsw_enable_ips(struct intel_crtc *crtc)
3972 struct drm_device *dev = crtc->base.dev;
3973 struct drm_i915_private *dev_priv = dev->dev_private;
3975 if (!crtc->config.ips_enabled)
3978 /* We can only enable IPS after we enable a plane and wait for a vblank */
3979 intel_wait_for_vblank(dev, crtc->pipe);
3981 assert_plane_enabled(dev_priv, crtc->plane);
3982 if (IS_BROADWELL(dev)) {
3983 mutex_lock(&dev_priv->rps.hw_lock);
3984 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3985 mutex_unlock(&dev_priv->rps.hw_lock);
3986 /* Quoting Art Runyan: "its not safe to expect any particular
3987 * value in IPS_CTL bit 31 after enabling IPS through the
3988 * mailbox." Moreover, the mailbox may return a bogus state,
3989 * so we need to just enable it and continue on.
3992 I915_WRITE(IPS_CTL, IPS_ENABLE);
3993 /* The bit only becomes 1 in the next vblank, so this wait here
3994 * is essentially intel_wait_for_vblank. If we don't have this
3995 * and don't wait for vblanks until the end of crtc_enable, then
3996 * the HW state readout code will complain that the expected
3997 * IPS_CTL value is not the one we read. */
3998 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3999 DRM_ERROR("Timed out waiting for IPS enable\n");
4003 void hsw_disable_ips(struct intel_crtc *crtc)
4005 struct drm_device *dev = crtc->base.dev;
4006 struct drm_i915_private *dev_priv = dev->dev_private;
4008 if (!crtc->config.ips_enabled)
4011 assert_plane_enabled(dev_priv, crtc->plane);
4012 if (IS_BROADWELL(dev)) {
4013 mutex_lock(&dev_priv->rps.hw_lock);
4014 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4015 mutex_unlock(&dev_priv->rps.hw_lock);
4016 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4017 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4018 DRM_ERROR("Timed out waiting for IPS disable\n");
4020 I915_WRITE(IPS_CTL, 0);
4021 POSTING_READ(IPS_CTL);
4024 /* We need to wait for a vblank before we can disable the plane. */
4025 intel_wait_for_vblank(dev, crtc->pipe);
4028 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4029 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4031 struct drm_device *dev = crtc->dev;
4032 struct drm_i915_private *dev_priv = dev->dev_private;
4033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4034 enum pipe pipe = intel_crtc->pipe;
4035 int palreg = PALETTE(pipe);
4037 bool reenable_ips = false;
4039 /* The clocks have to be on to load the palette. */
4040 if (!crtc->enabled || !intel_crtc->active)
4043 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4044 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4045 assert_dsi_pll_enabled(dev_priv);
4047 assert_pll_enabled(dev_priv, pipe);
4050 /* use legacy palette for Ironlake */
4051 if (!HAS_GMCH_DISPLAY(dev))
4052 palreg = LGC_PALETTE(pipe);
4054 /* Workaround : Do not read or write the pipe palette/gamma data while
4055 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4057 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4058 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4059 GAMMA_MODE_MODE_SPLIT)) {
4060 hsw_disable_ips(intel_crtc);
4061 reenable_ips = true;
4064 for (i = 0; i < 256; i++) {
4065 I915_WRITE(palreg + 4 * i,
4066 (intel_crtc->lut_r[i] << 16) |
4067 (intel_crtc->lut_g[i] << 8) |
4068 intel_crtc->lut_b[i]);
4072 hsw_enable_ips(intel_crtc);
4075 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4077 if (!enable && intel_crtc->overlay) {
4078 struct drm_device *dev = intel_crtc->base.dev;
4079 struct drm_i915_private *dev_priv = dev->dev_private;
4081 mutex_lock(&dev->struct_mutex);
4082 dev_priv->mm.interruptible = false;
4083 (void) intel_overlay_switch_off(intel_crtc->overlay);
4084 dev_priv->mm.interruptible = true;
4085 mutex_unlock(&dev->struct_mutex);
4088 /* Let userspace switch the overlay on again. In most cases userspace
4089 * has to recompute where to put it anyway.
4093 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4095 struct drm_device *dev = crtc->dev;
4096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4097 int pipe = intel_crtc->pipe;
4099 intel_enable_primary_hw_plane(crtc->primary, crtc);
4100 intel_enable_planes(crtc);
4101 intel_crtc_update_cursor(crtc, true);
4102 intel_crtc_dpms_overlay(intel_crtc, true);
4104 hsw_enable_ips(intel_crtc);
4106 mutex_lock(&dev->struct_mutex);
4107 intel_update_fbc(dev);
4108 mutex_unlock(&dev->struct_mutex);
4111 * FIXME: Once we grow proper nuclear flip support out of this we need
4112 * to compute the mask of flip planes precisely. For the time being
4113 * consider this a flip from a NULL plane.
4115 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4118 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4120 struct drm_device *dev = crtc->dev;
4121 struct drm_i915_private *dev_priv = dev->dev_private;
4122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4123 int pipe = intel_crtc->pipe;
4124 int plane = intel_crtc->plane;
4126 intel_crtc_wait_for_pending_flips(crtc);
4128 if (dev_priv->fbc.plane == plane)
4129 intel_disable_fbc(dev);
4131 hsw_disable_ips(intel_crtc);
4133 intel_crtc_dpms_overlay(intel_crtc, false);
4134 intel_crtc_update_cursor(crtc, false);
4135 intel_disable_planes(crtc);
4136 intel_disable_primary_hw_plane(crtc->primary, crtc);
4139 * FIXME: Once we grow proper nuclear flip support out of this we need
4140 * to compute the mask of flip planes precisely. For the time being
4141 * consider this a flip to a NULL plane.
4143 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4146 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4148 struct drm_device *dev = crtc->dev;
4149 struct drm_i915_private *dev_priv = dev->dev_private;
4150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4151 struct intel_encoder *encoder;
4152 int pipe = intel_crtc->pipe;
4154 WARN_ON(!crtc->enabled);
4156 if (intel_crtc->active)
4159 if (intel_crtc->config.has_pch_encoder)
4160 intel_prepare_shared_dpll(intel_crtc);
4162 if (intel_crtc->config.has_dp_encoder)
4163 intel_dp_set_m_n(intel_crtc);
4165 intel_set_pipe_timings(intel_crtc);
4167 if (intel_crtc->config.has_pch_encoder) {
4168 intel_cpu_transcoder_set_m_n(intel_crtc,
4169 &intel_crtc->config.fdi_m_n, NULL);
4172 ironlake_set_pipeconf(crtc);
4174 intel_crtc->active = true;
4176 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4177 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4179 for_each_encoder_on_crtc(dev, crtc, encoder)
4180 if (encoder->pre_enable)
4181 encoder->pre_enable(encoder);
4183 if (intel_crtc->config.has_pch_encoder) {
4184 /* Note: FDI PLL enabling _must_ be done before we enable the
4185 * cpu pipes, hence this is separate from all the other fdi/pch
4187 ironlake_fdi_pll_enable(intel_crtc);
4189 assert_fdi_tx_disabled(dev_priv, pipe);
4190 assert_fdi_rx_disabled(dev_priv, pipe);
4193 ironlake_pfit_enable(intel_crtc);
4196 * On ILK+ LUT must be loaded before the pipe is running but with
4199 intel_crtc_load_lut(crtc);
4201 intel_update_watermarks(crtc);
4202 intel_enable_pipe(intel_crtc);
4204 if (intel_crtc->config.has_pch_encoder)
4205 ironlake_pch_enable(crtc);
4207 for_each_encoder_on_crtc(dev, crtc, encoder)
4208 encoder->enable(encoder);
4210 if (HAS_PCH_CPT(dev))
4211 cpt_verify_modeset(dev, intel_crtc->pipe);
4213 assert_vblank_disabled(crtc);
4214 drm_crtc_vblank_on(crtc);
4216 intel_crtc_enable_planes(crtc);
4219 /* IPS only exists on ULT machines and is tied to pipe A. */
4220 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4222 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4226 * This implements the workaround described in the "notes" section of the mode
4227 * set sequence documentation. When going from no pipes or single pipe to
4228 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4229 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4231 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4233 struct drm_device *dev = crtc->base.dev;
4234 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4236 /* We want to get the other_active_crtc only if there's only 1 other
4238 for_each_intel_crtc(dev, crtc_it) {
4239 if (!crtc_it->active || crtc_it == crtc)
4242 if (other_active_crtc)
4245 other_active_crtc = crtc_it;
4247 if (!other_active_crtc)
4250 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4251 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4254 static void haswell_crtc_enable(struct drm_crtc *crtc)
4256 struct drm_device *dev = crtc->dev;
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4259 struct intel_encoder *encoder;
4260 int pipe = intel_crtc->pipe;
4262 WARN_ON(!crtc->enabled);
4264 if (intel_crtc->active)
4267 if (intel_crtc_to_shared_dpll(intel_crtc))
4268 intel_enable_shared_dpll(intel_crtc);
4270 if (intel_crtc->config.has_dp_encoder)
4271 intel_dp_set_m_n(intel_crtc);
4273 intel_set_pipe_timings(intel_crtc);
4275 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4276 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4277 intel_crtc->config.pixel_multiplier - 1);
4280 if (intel_crtc->config.has_pch_encoder) {
4281 intel_cpu_transcoder_set_m_n(intel_crtc,
4282 &intel_crtc->config.fdi_m_n, NULL);
4285 haswell_set_pipeconf(crtc);
4287 intel_set_pipe_csc(crtc);
4289 intel_crtc->active = true;
4291 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4292 for_each_encoder_on_crtc(dev, crtc, encoder)
4293 if (encoder->pre_enable)
4294 encoder->pre_enable(encoder);
4296 if (intel_crtc->config.has_pch_encoder) {
4297 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4299 dev_priv->display.fdi_link_train(crtc);
4302 intel_ddi_enable_pipe_clock(intel_crtc);
4304 ironlake_pfit_enable(intel_crtc);
4307 * On ILK+ LUT must be loaded before the pipe is running but with
4310 intel_crtc_load_lut(crtc);
4312 intel_ddi_set_pipe_settings(crtc);
4313 intel_ddi_enable_transcoder_func(crtc);
4315 intel_update_watermarks(crtc);
4316 intel_enable_pipe(intel_crtc);
4318 if (intel_crtc->config.has_pch_encoder)
4319 lpt_pch_enable(crtc);
4321 if (intel_crtc->config.dp_encoder_is_mst)
4322 intel_ddi_set_vc_payload_alloc(crtc, true);
4324 for_each_encoder_on_crtc(dev, crtc, encoder) {
4325 encoder->enable(encoder);
4326 intel_opregion_notify_encoder(encoder, true);
4329 assert_vblank_disabled(crtc);
4330 drm_crtc_vblank_on(crtc);
4332 /* If we change the relative order between pipe/planes enabling, we need
4333 * to change the workaround. */
4334 haswell_mode_set_planes_workaround(intel_crtc);
4335 intel_crtc_enable_planes(crtc);
4338 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4340 struct drm_device *dev = crtc->base.dev;
4341 struct drm_i915_private *dev_priv = dev->dev_private;
4342 int pipe = crtc->pipe;
4344 /* To avoid upsetting the power well on haswell only disable the pfit if
4345 * it's in use. The hw state code will make sure we get this right. */
4346 if (crtc->config.pch_pfit.enabled) {
4347 I915_WRITE(PF_CTL(pipe), 0);
4348 I915_WRITE(PF_WIN_POS(pipe), 0);
4349 I915_WRITE(PF_WIN_SZ(pipe), 0);
4353 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4355 struct drm_device *dev = crtc->dev;
4356 struct drm_i915_private *dev_priv = dev->dev_private;
4357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4358 struct intel_encoder *encoder;
4359 int pipe = intel_crtc->pipe;
4362 if (!intel_crtc->active)
4365 intel_crtc_disable_planes(crtc);
4367 drm_crtc_vblank_off(crtc);
4368 assert_vblank_disabled(crtc);
4370 for_each_encoder_on_crtc(dev, crtc, encoder)
4371 encoder->disable(encoder);
4373 if (intel_crtc->config.has_pch_encoder)
4374 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4376 intel_disable_pipe(intel_crtc);
4378 ironlake_pfit_disable(intel_crtc);
4380 for_each_encoder_on_crtc(dev, crtc, encoder)
4381 if (encoder->post_disable)
4382 encoder->post_disable(encoder);
4384 if (intel_crtc->config.has_pch_encoder) {
4385 ironlake_fdi_disable(crtc);
4387 ironlake_disable_pch_transcoder(dev_priv, pipe);
4388 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4390 if (HAS_PCH_CPT(dev)) {
4391 /* disable TRANS_DP_CTL */
4392 reg = TRANS_DP_CTL(pipe);
4393 temp = I915_READ(reg);
4394 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4395 TRANS_DP_PORT_SEL_MASK);
4396 temp |= TRANS_DP_PORT_SEL_NONE;
4397 I915_WRITE(reg, temp);
4399 /* disable DPLL_SEL */
4400 temp = I915_READ(PCH_DPLL_SEL);
4401 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4402 I915_WRITE(PCH_DPLL_SEL, temp);
4405 /* disable PCH DPLL */
4406 intel_disable_shared_dpll(intel_crtc);
4408 ironlake_fdi_pll_disable(intel_crtc);
4411 intel_crtc->active = false;
4412 intel_update_watermarks(crtc);
4414 mutex_lock(&dev->struct_mutex);
4415 intel_update_fbc(dev);
4416 mutex_unlock(&dev->struct_mutex);
4419 static void haswell_crtc_disable(struct drm_crtc *crtc)
4421 struct drm_device *dev = crtc->dev;
4422 struct drm_i915_private *dev_priv = dev->dev_private;
4423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4424 struct intel_encoder *encoder;
4425 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4427 if (!intel_crtc->active)
4430 intel_crtc_disable_planes(crtc);
4432 drm_crtc_vblank_off(crtc);
4433 assert_vblank_disabled(crtc);
4435 for_each_encoder_on_crtc(dev, crtc, encoder) {
4436 intel_opregion_notify_encoder(encoder, false);
4437 encoder->disable(encoder);
4440 if (intel_crtc->config.has_pch_encoder)
4441 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4443 intel_disable_pipe(intel_crtc);
4445 if (intel_crtc->config.dp_encoder_is_mst)
4446 intel_ddi_set_vc_payload_alloc(crtc, false);
4448 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4450 ironlake_pfit_disable(intel_crtc);
4452 intel_ddi_disable_pipe_clock(intel_crtc);
4454 if (intel_crtc->config.has_pch_encoder) {
4455 lpt_disable_pch_transcoder(dev_priv);
4456 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4458 intel_ddi_fdi_disable(crtc);
4461 for_each_encoder_on_crtc(dev, crtc, encoder)
4462 if (encoder->post_disable)
4463 encoder->post_disable(encoder);
4465 intel_crtc->active = false;
4466 intel_update_watermarks(crtc);
4468 mutex_lock(&dev->struct_mutex);
4469 intel_update_fbc(dev);
4470 mutex_unlock(&dev->struct_mutex);
4472 if (intel_crtc_to_shared_dpll(intel_crtc))
4473 intel_disable_shared_dpll(intel_crtc);
4476 static void ironlake_crtc_off(struct drm_crtc *crtc)
4478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4479 intel_put_shared_dpll(intel_crtc);
4483 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4485 struct drm_device *dev = crtc->base.dev;
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487 struct intel_crtc_config *pipe_config = &crtc->config;
4489 if (!crtc->config.gmch_pfit.control)
4493 * The panel fitter should only be adjusted whilst the pipe is disabled,
4494 * according to register description and PRM.
4496 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4497 assert_pipe_disabled(dev_priv, crtc->pipe);
4499 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4500 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4502 /* Border color in case we don't scale up to the full screen. Black by
4503 * default, change to something else for debugging. */
4504 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4507 static enum intel_display_power_domain port_to_power_domain(enum port port)
4511 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4513 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4515 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4517 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4520 return POWER_DOMAIN_PORT_OTHER;
4524 #define for_each_power_domain(domain, mask) \
4525 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4526 if ((1 << (domain)) & (mask))
4528 enum intel_display_power_domain
4529 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4531 struct drm_device *dev = intel_encoder->base.dev;
4532 struct intel_digital_port *intel_dig_port;
4534 switch (intel_encoder->type) {
4535 case INTEL_OUTPUT_UNKNOWN:
4536 /* Only DDI platforms should ever use this output type */
4537 WARN_ON_ONCE(!HAS_DDI(dev));
4538 case INTEL_OUTPUT_DISPLAYPORT:
4539 case INTEL_OUTPUT_HDMI:
4540 case INTEL_OUTPUT_EDP:
4541 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4542 return port_to_power_domain(intel_dig_port->port);
4543 case INTEL_OUTPUT_DP_MST:
4544 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4545 return port_to_power_domain(intel_dig_port->port);
4546 case INTEL_OUTPUT_ANALOG:
4547 return POWER_DOMAIN_PORT_CRT;
4548 case INTEL_OUTPUT_DSI:
4549 return POWER_DOMAIN_PORT_DSI;
4551 return POWER_DOMAIN_PORT_OTHER;
4555 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4557 struct drm_device *dev = crtc->dev;
4558 struct intel_encoder *intel_encoder;
4559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4560 enum pipe pipe = intel_crtc->pipe;
4562 enum transcoder transcoder;
4564 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4566 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4567 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4568 if (intel_crtc->config.pch_pfit.enabled ||
4569 intel_crtc->config.pch_pfit.force_thru)
4570 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4572 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4573 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4578 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4582 struct intel_crtc *crtc;
4585 * First get all needed power domains, then put all unneeded, to avoid
4586 * any unnecessary toggling of the power wells.
4588 for_each_intel_crtc(dev, crtc) {
4589 enum intel_display_power_domain domain;
4591 if (!crtc->base.enabled)
4594 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4596 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4597 intel_display_power_get(dev_priv, domain);
4600 for_each_intel_crtc(dev, crtc) {
4601 enum intel_display_power_domain domain;
4603 for_each_power_domain(domain, crtc->enabled_power_domains)
4604 intel_display_power_put(dev_priv, domain);
4606 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4609 intel_display_set_init_power(dev_priv, false);
4612 /* returns HPLL frequency in kHz */
4613 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4615 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4617 /* Obtain SKU information */
4618 mutex_lock(&dev_priv->dpio_lock);
4619 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4620 CCK_FUSE_HPLL_FREQ_MASK;
4621 mutex_unlock(&dev_priv->dpio_lock);
4623 return vco_freq[hpll_freq] * 1000;
4626 static void vlv_update_cdclk(struct drm_device *dev)
4628 struct drm_i915_private *dev_priv = dev->dev_private;
4630 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4631 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4632 dev_priv->vlv_cdclk_freq);
4635 * Program the gmbus_freq based on the cdclk frequency.
4636 * BSpec erroneously claims we should aim for 4MHz, but
4637 * in fact 1MHz is the correct frequency.
4639 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4642 /* Adjust CDclk dividers to allow high res or save power if possible */
4643 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4648 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4650 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4652 else if (cdclk == 266667)
4657 mutex_lock(&dev_priv->rps.hw_lock);
4658 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4659 val &= ~DSPFREQGUAR_MASK;
4660 val |= (cmd << DSPFREQGUAR_SHIFT);
4661 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4662 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4663 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4665 DRM_ERROR("timed out waiting for CDclk change\n");
4667 mutex_unlock(&dev_priv->rps.hw_lock);
4669 if (cdclk == 400000) {
4672 vco = valleyview_get_vco(dev_priv);
4673 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4675 mutex_lock(&dev_priv->dpio_lock);
4676 /* adjust cdclk divider */
4677 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4678 val &= ~DISPLAY_FREQUENCY_VALUES;
4680 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4682 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4683 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4685 DRM_ERROR("timed out waiting for CDclk change\n");
4686 mutex_unlock(&dev_priv->dpio_lock);
4689 mutex_lock(&dev_priv->dpio_lock);
4690 /* adjust self-refresh exit latency value */
4691 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4695 * For high bandwidth configs, we set a higher latency in the bunit
4696 * so that the core display fetch happens in time to avoid underruns.
4698 if (cdclk == 400000)
4699 val |= 4500 / 250; /* 4.5 usec */
4701 val |= 3000 / 250; /* 3.0 usec */
4702 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4703 mutex_unlock(&dev_priv->dpio_lock);
4705 vlv_update_cdclk(dev);
4708 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4713 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4734 mutex_lock(&dev_priv->rps.hw_lock);
4735 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4736 val &= ~DSPFREQGUAR_MASK_CHV;
4737 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4738 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4739 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4740 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4742 DRM_ERROR("timed out waiting for CDclk change\n");
4744 mutex_unlock(&dev_priv->rps.hw_lock);
4746 vlv_update_cdclk(dev);
4749 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4752 int vco = valleyview_get_vco(dev_priv);
4753 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4755 /* FIXME: Punit isn't quite ready yet */
4756 if (IS_CHERRYVIEW(dev_priv->dev))
4760 * Really only a few cases to deal with, as only 4 CDclks are supported:
4763 * 320/333MHz (depends on HPLL freq)
4765 * So we check to see whether we're above 90% of the lower bin and
4768 * We seem to get an unstable or solid color picture at 200MHz.
4769 * Not sure what's wrong. For now use 200MHz only when all pipes
4772 if (max_pixclk > freq_320*9/10)
4774 else if (max_pixclk > 266667*9/10)
4776 else if (max_pixclk > 0)
4782 /* compute the max pixel clock for new configuration */
4783 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4785 struct drm_device *dev = dev_priv->dev;
4786 struct intel_crtc *intel_crtc;
4789 for_each_intel_crtc(dev, intel_crtc) {
4790 if (intel_crtc->new_enabled)
4791 max_pixclk = max(max_pixclk,
4792 intel_crtc->new_config->adjusted_mode.crtc_clock);
4798 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4799 unsigned *prepare_pipes)
4801 struct drm_i915_private *dev_priv = dev->dev_private;
4802 struct intel_crtc *intel_crtc;
4803 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4805 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4806 dev_priv->vlv_cdclk_freq)
4809 /* disable/enable all currently active pipes while we change cdclk */
4810 for_each_intel_crtc(dev, intel_crtc)
4811 if (intel_crtc->base.enabled)
4812 *prepare_pipes |= (1 << intel_crtc->pipe);
4815 static void valleyview_modeset_global_resources(struct drm_device *dev)
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4819 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4821 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4822 if (IS_CHERRYVIEW(dev))
4823 cherryview_set_cdclk(dev, req_cdclk);
4825 valleyview_set_cdclk(dev, req_cdclk);
4828 modeset_update_crtc_power_domains(dev);
4831 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4833 struct drm_device *dev = crtc->dev;
4834 struct drm_i915_private *dev_priv = to_i915(dev);
4835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4836 struct intel_encoder *encoder;
4837 int pipe = intel_crtc->pipe;
4840 WARN_ON(!crtc->enabled);
4842 if (intel_crtc->active)
4845 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4848 if (IS_CHERRYVIEW(dev))
4849 chv_prepare_pll(intel_crtc, &intel_crtc->config);
4851 vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4854 if (intel_crtc->config.has_dp_encoder)
4855 intel_dp_set_m_n(intel_crtc);
4857 intel_set_pipe_timings(intel_crtc);
4859 i9xx_set_pipeconf(intel_crtc);
4861 intel_crtc->active = true;
4863 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4865 for_each_encoder_on_crtc(dev, crtc, encoder)
4866 if (encoder->pre_pll_enable)
4867 encoder->pre_pll_enable(encoder);
4870 if (IS_CHERRYVIEW(dev))
4871 chv_enable_pll(intel_crtc, &intel_crtc->config);
4873 vlv_enable_pll(intel_crtc, &intel_crtc->config);
4876 for_each_encoder_on_crtc(dev, crtc, encoder)
4877 if (encoder->pre_enable)
4878 encoder->pre_enable(encoder);
4880 i9xx_pfit_enable(intel_crtc);
4882 intel_crtc_load_lut(crtc);
4884 intel_update_watermarks(crtc);
4885 intel_enable_pipe(intel_crtc);
4887 for_each_encoder_on_crtc(dev, crtc, encoder)
4888 encoder->enable(encoder);
4890 assert_vblank_disabled(crtc);
4891 drm_crtc_vblank_on(crtc);
4893 intel_crtc_enable_planes(crtc);
4895 /* Underruns don't raise interrupts, so check manually. */
4896 i9xx_check_fifo_underruns(dev_priv);
4899 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4901 struct drm_device *dev = crtc->base.dev;
4902 struct drm_i915_private *dev_priv = dev->dev_private;
4904 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4905 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4908 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4910 struct drm_device *dev = crtc->dev;
4911 struct drm_i915_private *dev_priv = to_i915(dev);
4912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4913 struct intel_encoder *encoder;
4914 int pipe = intel_crtc->pipe;
4916 WARN_ON(!crtc->enabled);
4918 if (intel_crtc->active)
4921 i9xx_set_pll_dividers(intel_crtc);
4923 if (intel_crtc->config.has_dp_encoder)
4924 intel_dp_set_m_n(intel_crtc);
4926 intel_set_pipe_timings(intel_crtc);
4928 i9xx_set_pipeconf(intel_crtc);
4930 intel_crtc->active = true;
4933 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4935 for_each_encoder_on_crtc(dev, crtc, encoder)
4936 if (encoder->pre_enable)
4937 encoder->pre_enable(encoder);
4939 i9xx_enable_pll(intel_crtc);
4941 i9xx_pfit_enable(intel_crtc);
4943 intel_crtc_load_lut(crtc);
4945 intel_update_watermarks(crtc);
4946 intel_enable_pipe(intel_crtc);
4948 for_each_encoder_on_crtc(dev, crtc, encoder)
4949 encoder->enable(encoder);
4951 assert_vblank_disabled(crtc);
4952 drm_crtc_vblank_on(crtc);
4954 intel_crtc_enable_planes(crtc);
4957 * Gen2 reports pipe underruns whenever all planes are disabled.
4958 * So don't enable underrun reporting before at least some planes
4960 * FIXME: Need to fix the logic to work when we turn off all planes
4961 * but leave the pipe running.
4964 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4966 /* Underruns don't raise interrupts, so check manually. */
4967 i9xx_check_fifo_underruns(dev_priv);
4970 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4972 struct drm_device *dev = crtc->base.dev;
4973 struct drm_i915_private *dev_priv = dev->dev_private;
4975 if (!crtc->config.gmch_pfit.control)
4978 assert_pipe_disabled(dev_priv, crtc->pipe);
4980 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4981 I915_READ(PFIT_CONTROL));
4982 I915_WRITE(PFIT_CONTROL, 0);
4985 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4987 struct drm_device *dev = crtc->dev;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4990 struct intel_encoder *encoder;
4991 int pipe = intel_crtc->pipe;
4993 if (!intel_crtc->active)
4997 * Gen2 reports pipe underruns whenever all planes are disabled.
4998 * So diasble underrun reporting before all the planes get disabled.
4999 * FIXME: Need to fix the logic to work when we turn off all planes
5000 * but leave the pipe running.
5003 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5006 * Vblank time updates from the shadow to live plane control register
5007 * are blocked if the memory self-refresh mode is active at that
5008 * moment. So to make sure the plane gets truly disabled, disable
5009 * first the self-refresh mode. The self-refresh enable bit in turn
5010 * will be checked/applied by the HW only at the next frame start
5011 * event which is after the vblank start event, so we need to have a
5012 * wait-for-vblank between disabling the plane and the pipe.
5014 intel_set_memory_cxsr(dev_priv, false);
5015 intel_crtc_disable_planes(crtc);
5018 * On gen2 planes are double buffered but the pipe isn't, so we must
5019 * wait for planes to fully turn off before disabling the pipe.
5020 * We also need to wait on all gmch platforms because of the
5021 * self-refresh mode constraint explained above.
5023 intel_wait_for_vblank(dev, pipe);
5025 drm_crtc_vblank_off(crtc);
5026 assert_vblank_disabled(crtc);
5028 for_each_encoder_on_crtc(dev, crtc, encoder)
5029 encoder->disable(encoder);
5031 intel_disable_pipe(intel_crtc);
5033 i9xx_pfit_disable(intel_crtc);
5035 for_each_encoder_on_crtc(dev, crtc, encoder)
5036 if (encoder->post_disable)
5037 encoder->post_disable(encoder);
5039 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5040 if (IS_CHERRYVIEW(dev))
5041 chv_disable_pll(dev_priv, pipe);
5042 else if (IS_VALLEYVIEW(dev))
5043 vlv_disable_pll(dev_priv, pipe);
5045 i9xx_disable_pll(intel_crtc);
5049 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5051 intel_crtc->active = false;
5052 intel_update_watermarks(crtc);
5054 mutex_lock(&dev->struct_mutex);
5055 intel_update_fbc(dev);
5056 mutex_unlock(&dev->struct_mutex);
5059 static void i9xx_crtc_off(struct drm_crtc *crtc)
5063 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5066 struct drm_device *dev = crtc->dev;
5067 struct drm_i915_master_private *master_priv;
5068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5069 int pipe = intel_crtc->pipe;
5071 if (!dev->primary->master)
5074 master_priv = dev->primary->master->driver_priv;
5075 if (!master_priv->sarea_priv)
5080 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5081 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5084 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5085 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5088 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5093 /* Master function to enable/disable CRTC and corresponding power wells */
5094 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5096 struct drm_device *dev = crtc->dev;
5097 struct drm_i915_private *dev_priv = dev->dev_private;
5098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5099 enum intel_display_power_domain domain;
5100 unsigned long domains;
5103 if (!intel_crtc->active) {
5104 domains = get_crtc_power_domains(crtc);
5105 for_each_power_domain(domain, domains)
5106 intel_display_power_get(dev_priv, domain);
5107 intel_crtc->enabled_power_domains = domains;
5109 dev_priv->display.crtc_enable(crtc);
5112 if (intel_crtc->active) {
5113 dev_priv->display.crtc_disable(crtc);
5115 domains = intel_crtc->enabled_power_domains;
5116 for_each_power_domain(domain, domains)
5117 intel_display_power_put(dev_priv, domain);
5118 intel_crtc->enabled_power_domains = 0;
5124 * Sets the power management mode of the pipe and plane.
5126 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5128 struct drm_device *dev = crtc->dev;
5129 struct intel_encoder *intel_encoder;
5130 bool enable = false;
5132 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5133 enable |= intel_encoder->connectors_active;
5135 intel_crtc_control(crtc, enable);
5137 intel_crtc_update_sarea(crtc, enable);
5140 static void intel_crtc_disable(struct drm_crtc *crtc)
5142 struct drm_device *dev = crtc->dev;
5143 struct drm_connector *connector;
5144 struct drm_i915_private *dev_priv = dev->dev_private;
5145 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5146 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5148 /* crtc should still be enabled when we disable it. */
5149 WARN_ON(!crtc->enabled);
5151 dev_priv->display.crtc_disable(crtc);
5152 intel_crtc_update_sarea(crtc, false);
5153 dev_priv->display.off(crtc);
5155 if (crtc->primary->fb) {
5156 mutex_lock(&dev->struct_mutex);
5157 intel_unpin_fb_obj(old_obj);
5158 i915_gem_track_fb(old_obj, NULL,
5159 INTEL_FRONTBUFFER_PRIMARY(pipe));
5160 mutex_unlock(&dev->struct_mutex);
5161 crtc->primary->fb = NULL;
5164 /* Update computed state. */
5165 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5166 if (!connector->encoder || !connector->encoder->crtc)
5169 if (connector->encoder->crtc != crtc)
5172 connector->dpms = DRM_MODE_DPMS_OFF;
5173 to_intel_encoder(connector->encoder)->connectors_active = false;
5177 void intel_encoder_destroy(struct drm_encoder *encoder)
5179 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5181 drm_encoder_cleanup(encoder);
5182 kfree(intel_encoder);
5185 /* Simple dpms helper for encoders with just one connector, no cloning and only
5186 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5187 * state of the entire output pipe. */
5188 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5190 if (mode == DRM_MODE_DPMS_ON) {
5191 encoder->connectors_active = true;
5193 intel_crtc_update_dpms(encoder->base.crtc);
5195 encoder->connectors_active = false;
5197 intel_crtc_update_dpms(encoder->base.crtc);
5201 /* Cross check the actual hw state with our own modeset state tracking (and it's
5202 * internal consistency). */
5203 static void intel_connector_check_state(struct intel_connector *connector)
5205 if (connector->get_hw_state(connector)) {
5206 struct intel_encoder *encoder = connector->encoder;
5207 struct drm_crtc *crtc;
5208 bool encoder_enabled;
5211 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5212 connector->base.base.id,
5213 connector->base.name);
5215 /* there is no real hw state for MST connectors */
5216 if (connector->mst_port)
5219 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5220 "wrong connector dpms state\n");
5221 WARN(connector->base.encoder != &encoder->base,
5222 "active connector not linked to encoder\n");
5225 WARN(!encoder->connectors_active,
5226 "encoder->connectors_active not set\n");
5228 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5229 WARN(!encoder_enabled, "encoder not enabled\n");
5230 if (WARN_ON(!encoder->base.crtc))
5233 crtc = encoder->base.crtc;
5235 WARN(!crtc->enabled, "crtc not enabled\n");
5236 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5237 WARN(pipe != to_intel_crtc(crtc)->pipe,
5238 "encoder active on the wrong pipe\n");
5243 /* Even simpler default implementation, if there's really no special case to
5245 void intel_connector_dpms(struct drm_connector *connector, int mode)
5247 /* All the simple cases only support two dpms states. */
5248 if (mode != DRM_MODE_DPMS_ON)
5249 mode = DRM_MODE_DPMS_OFF;
5251 if (mode == connector->dpms)
5254 connector->dpms = mode;
5256 /* Only need to change hw state when actually enabled */
5257 if (connector->encoder)
5258 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5260 intel_modeset_check_state(connector->dev);
5263 /* Simple connector->get_hw_state implementation for encoders that support only
5264 * one connector and no cloning and hence the encoder state determines the state
5265 * of the connector. */
5266 bool intel_connector_get_hw_state(struct intel_connector *connector)
5269 struct intel_encoder *encoder = connector->encoder;
5271 return encoder->get_hw_state(encoder, &pipe);
5274 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5275 struct intel_crtc_config *pipe_config)
5277 struct drm_i915_private *dev_priv = dev->dev_private;
5278 struct intel_crtc *pipe_B_crtc =
5279 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5281 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5282 pipe_name(pipe), pipe_config->fdi_lanes);
5283 if (pipe_config->fdi_lanes > 4) {
5284 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5285 pipe_name(pipe), pipe_config->fdi_lanes);
5289 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5290 if (pipe_config->fdi_lanes > 2) {
5291 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5292 pipe_config->fdi_lanes);
5299 if (INTEL_INFO(dev)->num_pipes == 2)
5302 /* Ivybridge 3 pipe is really complicated */
5307 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5308 pipe_config->fdi_lanes > 2) {
5309 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5310 pipe_name(pipe), pipe_config->fdi_lanes);
5315 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5316 pipe_B_crtc->config.fdi_lanes <= 2) {
5317 if (pipe_config->fdi_lanes > 2) {
5318 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5319 pipe_name(pipe), pipe_config->fdi_lanes);
5323 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5333 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5334 struct intel_crtc_config *pipe_config)
5336 struct drm_device *dev = intel_crtc->base.dev;
5337 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5338 int lane, link_bw, fdi_dotclock;
5339 bool setup_ok, needs_recompute = false;
5342 /* FDI is a binary signal running at ~2.7GHz, encoding
5343 * each output octet as 10 bits. The actual frequency
5344 * is stored as a divider into a 100MHz clock, and the
5345 * mode pixel clock is stored in units of 1KHz.
5346 * Hence the bw of each lane in terms of the mode signal
5349 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5351 fdi_dotclock = adjusted_mode->crtc_clock;
5353 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5354 pipe_config->pipe_bpp);
5356 pipe_config->fdi_lanes = lane;
5358 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5359 link_bw, &pipe_config->fdi_m_n);
5361 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5362 intel_crtc->pipe, pipe_config);
5363 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5364 pipe_config->pipe_bpp -= 2*3;
5365 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5366 pipe_config->pipe_bpp);
5367 needs_recompute = true;
5368 pipe_config->bw_constrained = true;
5373 if (needs_recompute)
5376 return setup_ok ? 0 : -EINVAL;
5379 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5380 struct intel_crtc_config *pipe_config)
5382 pipe_config->ips_enabled = i915.enable_ips &&
5383 hsw_crtc_supports_ips(crtc) &&
5384 pipe_config->pipe_bpp <= 24;
5387 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5388 struct intel_crtc_config *pipe_config)
5390 struct drm_device *dev = crtc->base.dev;
5391 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5393 /* FIXME should check pixel clock limits on all platforms */
5394 if (INTEL_INFO(dev)->gen < 4) {
5395 struct drm_i915_private *dev_priv = dev->dev_private;
5397 dev_priv->display.get_display_clock_speed(dev);
5400 * Enable pixel doubling when the dot clock
5401 * is > 90% of the (display) core speed.
5403 * GDG double wide on either pipe,
5404 * otherwise pipe A only.
5406 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5407 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5409 pipe_config->double_wide = true;
5412 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5417 * Pipe horizontal size must be even in:
5419 * - LVDS dual channel mode
5420 * - Double wide pipe
5422 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5423 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5424 pipe_config->pipe_src_w &= ~1;
5426 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5427 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5429 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5430 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5433 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5434 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5435 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5436 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5438 pipe_config->pipe_bpp = 8*3;
5442 hsw_compute_ips_config(crtc, pipe_config);
5445 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5446 * old clock survives for now.
5448 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5449 pipe_config->shared_dpll = crtc->config.shared_dpll;
5451 if (pipe_config->has_pch_encoder)
5452 return ironlake_fdi_compute_config(crtc, pipe_config);
5457 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5459 struct drm_i915_private *dev_priv = dev->dev_private;
5460 int vco = valleyview_get_vco(dev_priv);
5464 /* FIXME: Punit isn't quite ready yet */
5465 if (IS_CHERRYVIEW(dev))
5468 mutex_lock(&dev_priv->dpio_lock);
5469 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5470 mutex_unlock(&dev_priv->dpio_lock);
5472 divider = val & DISPLAY_FREQUENCY_VALUES;
5474 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5475 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5476 "cdclk change in progress\n");
5478 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5481 static int i945_get_display_clock_speed(struct drm_device *dev)
5486 static int i915_get_display_clock_speed(struct drm_device *dev)
5491 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5496 static int pnv_get_display_clock_speed(struct drm_device *dev)
5500 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5502 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5503 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5505 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5507 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5509 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5512 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5513 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5515 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5520 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5524 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5526 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5529 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5530 case GC_DISPLAY_CLOCK_333_MHZ:
5533 case GC_DISPLAY_CLOCK_190_200_MHZ:
5539 static int i865_get_display_clock_speed(struct drm_device *dev)
5544 static int i855_get_display_clock_speed(struct drm_device *dev)
5547 /* Assume that the hardware is in the high speed state. This
5548 * should be the default.
5550 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5551 case GC_CLOCK_133_200:
5552 case GC_CLOCK_100_200:
5554 case GC_CLOCK_166_250:
5556 case GC_CLOCK_100_133:
5560 /* Shouldn't happen */
5564 static int i830_get_display_clock_speed(struct drm_device *dev)
5570 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5572 while (*num > DATA_LINK_M_N_MASK ||
5573 *den > DATA_LINK_M_N_MASK) {
5579 static void compute_m_n(unsigned int m, unsigned int n,
5580 uint32_t *ret_m, uint32_t *ret_n)
5582 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5583 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5584 intel_reduce_m_n_ratio(ret_m, ret_n);
5588 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5589 int pixel_clock, int link_clock,
5590 struct intel_link_m_n *m_n)
5594 compute_m_n(bits_per_pixel * pixel_clock,
5595 link_clock * nlanes * 8,
5596 &m_n->gmch_m, &m_n->gmch_n);
5598 compute_m_n(pixel_clock, link_clock,
5599 &m_n->link_m, &m_n->link_n);
5602 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5604 if (i915.panel_use_ssc >= 0)
5605 return i915.panel_use_ssc != 0;
5606 return dev_priv->vbt.lvds_use_ssc
5607 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5610 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5612 struct drm_device *dev = crtc->base.dev;
5613 struct drm_i915_private *dev_priv = dev->dev_private;
5616 if (IS_VALLEYVIEW(dev)) {
5618 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5619 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5620 refclk = dev_priv->vbt.lvds_ssc_freq;
5621 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5622 } else if (!IS_GEN2(dev)) {
5631 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5633 return (1 << dpll->n) << 16 | dpll->m2;
5636 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5638 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5641 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5642 intel_clock_t *reduced_clock)
5644 struct drm_device *dev = crtc->base.dev;
5647 if (IS_PINEVIEW(dev)) {
5648 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5650 fp2 = pnv_dpll_compute_fp(reduced_clock);
5652 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5654 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5657 crtc->config.dpll_hw_state.fp0 = fp;
5659 crtc->lowfreq_avail = false;
5660 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5661 reduced_clock && i915.powersave) {
5662 crtc->config.dpll_hw_state.fp1 = fp2;
5663 crtc->lowfreq_avail = true;
5665 crtc->config.dpll_hw_state.fp1 = fp;
5669 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5675 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5676 * and set it to a reasonable value instead.
5678 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5679 reg_val &= 0xffffff00;
5680 reg_val |= 0x00000030;
5681 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5683 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5684 reg_val &= 0x8cffffff;
5685 reg_val = 0x8c000000;
5686 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5688 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5689 reg_val &= 0xffffff00;
5690 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5692 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5693 reg_val &= 0x00ffffff;
5694 reg_val |= 0xb0000000;
5695 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5698 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5699 struct intel_link_m_n *m_n)
5701 struct drm_device *dev = crtc->base.dev;
5702 struct drm_i915_private *dev_priv = dev->dev_private;
5703 int pipe = crtc->pipe;
5705 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5706 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5707 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5708 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5711 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5712 struct intel_link_m_n *m_n,
5713 struct intel_link_m_n *m2_n2)
5715 struct drm_device *dev = crtc->base.dev;
5716 struct drm_i915_private *dev_priv = dev->dev_private;
5717 int pipe = crtc->pipe;
5718 enum transcoder transcoder = crtc->config.cpu_transcoder;
5720 if (INTEL_INFO(dev)->gen >= 5) {
5721 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5722 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5723 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5724 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5725 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5726 * for gen < 8) and if DRRS is supported (to make sure the
5727 * registers are not unnecessarily accessed).
5729 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5730 crtc->config.has_drrs) {
5731 I915_WRITE(PIPE_DATA_M2(transcoder),
5732 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5733 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5734 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5735 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5738 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5739 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5740 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5741 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5745 void intel_dp_set_m_n(struct intel_crtc *crtc)
5747 if (crtc->config.has_pch_encoder)
5748 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5750 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5751 &crtc->config.dp_m2_n2);
5754 static void vlv_update_pll(struct intel_crtc *crtc,
5755 struct intel_crtc_config *pipe_config)
5760 * Enable DPIO clock input. We should never disable the reference
5761 * clock for pipe B, since VGA hotplug / manual detection depends
5764 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5765 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5766 /* We should never disable this, set it here for state tracking */
5767 if (crtc->pipe == PIPE_B)
5768 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5769 dpll |= DPLL_VCO_ENABLE;
5770 pipe_config->dpll_hw_state.dpll = dpll;
5772 dpll_md = (pipe_config->pixel_multiplier - 1)
5773 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5774 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5777 static void vlv_prepare_pll(struct intel_crtc *crtc,
5778 const struct intel_crtc_config *pipe_config)
5780 struct drm_device *dev = crtc->base.dev;
5781 struct drm_i915_private *dev_priv = dev->dev_private;
5782 int pipe = crtc->pipe;
5784 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5785 u32 coreclk, reg_val;
5787 mutex_lock(&dev_priv->dpio_lock);
5789 bestn = pipe_config->dpll.n;
5790 bestm1 = pipe_config->dpll.m1;
5791 bestm2 = pipe_config->dpll.m2;
5792 bestp1 = pipe_config->dpll.p1;
5793 bestp2 = pipe_config->dpll.p2;
5795 /* See eDP HDMI DPIO driver vbios notes doc */
5797 /* PLL B needs special handling */
5799 vlv_pllb_recal_opamp(dev_priv, pipe);
5801 /* Set up Tx target for periodic Rcomp update */
5802 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5804 /* Disable target IRef on PLL */
5805 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5806 reg_val &= 0x00ffffff;
5807 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5809 /* Disable fast lock */
5810 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5812 /* Set idtafcrecal before PLL is enabled */
5813 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5814 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5815 mdiv |= ((bestn << DPIO_N_SHIFT));
5816 mdiv |= (1 << DPIO_K_SHIFT);
5819 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5820 * but we don't support that).
5821 * Note: don't use the DAC post divider as it seems unstable.
5823 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5824 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5826 mdiv |= DPIO_ENABLE_CALIBRATION;
5827 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5829 /* Set HBR and RBR LPF coefficients */
5830 if (pipe_config->port_clock == 162000 ||
5831 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5832 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5833 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5836 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5839 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP) ||
5840 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5841 /* Use SSC source */
5843 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5846 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5848 } else { /* HDMI or VGA */
5849 /* Use bend source */
5851 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5854 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5858 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5859 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5860 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5861 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5862 coreclk |= 0x01000000;
5863 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5865 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5866 mutex_unlock(&dev_priv->dpio_lock);
5869 static void chv_update_pll(struct intel_crtc *crtc,
5870 struct intel_crtc_config *pipe_config)
5872 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5873 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5875 if (crtc->pipe != PIPE_A)
5876 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5878 pipe_config->dpll_hw_state.dpll_md =
5879 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5882 static void chv_prepare_pll(struct intel_crtc *crtc,
5883 const struct intel_crtc_config *pipe_config)
5885 struct drm_device *dev = crtc->base.dev;
5886 struct drm_i915_private *dev_priv = dev->dev_private;
5887 int pipe = crtc->pipe;
5888 int dpll_reg = DPLL(crtc->pipe);
5889 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5890 u32 loopfilter, intcoeff;
5891 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5894 bestn = pipe_config->dpll.n;
5895 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5896 bestm1 = pipe_config->dpll.m1;
5897 bestm2 = pipe_config->dpll.m2 >> 22;
5898 bestp1 = pipe_config->dpll.p1;
5899 bestp2 = pipe_config->dpll.p2;
5902 * Enable Refclk and SSC
5904 I915_WRITE(dpll_reg,
5905 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5907 mutex_lock(&dev_priv->dpio_lock);
5909 /* p1 and p2 divider */
5910 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5911 5 << DPIO_CHV_S1_DIV_SHIFT |
5912 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5913 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5914 1 << DPIO_CHV_K_DIV_SHIFT);
5916 /* Feedback post-divider - m2 */
5917 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5919 /* Feedback refclk divider - n and m1 */
5920 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5921 DPIO_CHV_M1_DIV_BY_2 |
5922 1 << DPIO_CHV_N_DIV_SHIFT);
5924 /* M2 fraction division */
5925 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5927 /* M2 fraction division enable */
5928 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5929 DPIO_CHV_FRAC_DIV_EN |
5930 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5933 refclk = i9xx_get_refclk(crtc, 0);
5934 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5935 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5936 if (refclk == 100000)
5938 else if (refclk == 38400)
5942 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5943 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5946 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5947 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5950 mutex_unlock(&dev_priv->dpio_lock);
5954 * vlv_force_pll_on - forcibly enable just the PLL
5955 * @dev_priv: i915 private structure
5956 * @pipe: pipe PLL to enable
5957 * @dpll: PLL configuration
5959 * Enable the PLL for @pipe using the supplied @dpll config. To be used
5960 * in cases where we need the PLL enabled even when @pipe is not going to
5963 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
5964 const struct dpll *dpll)
5966 struct intel_crtc *crtc =
5967 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5968 struct intel_crtc_config pipe_config = {
5969 .pixel_multiplier = 1,
5973 if (IS_CHERRYVIEW(dev)) {
5974 chv_update_pll(crtc, &pipe_config);
5975 chv_prepare_pll(crtc, &pipe_config);
5976 chv_enable_pll(crtc, &pipe_config);
5978 vlv_update_pll(crtc, &pipe_config);
5979 vlv_prepare_pll(crtc, &pipe_config);
5980 vlv_enable_pll(crtc, &pipe_config);
5985 * vlv_force_pll_off - forcibly disable just the PLL
5986 * @dev_priv: i915 private structure
5987 * @pipe: pipe PLL to disable
5989 * Disable the PLL for @pipe. To be used in cases where we need
5990 * the PLL enabled even when @pipe is not going to be enabled.
5992 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
5994 if (IS_CHERRYVIEW(dev))
5995 chv_disable_pll(to_i915(dev), pipe);
5997 vlv_disable_pll(to_i915(dev), pipe);
6000 static void i9xx_update_pll(struct intel_crtc *crtc,
6001 intel_clock_t *reduced_clock,
6004 struct drm_device *dev = crtc->base.dev;
6005 struct drm_i915_private *dev_priv = dev->dev_private;
6008 struct dpll *clock = &crtc->config.dpll;
6010 i9xx_update_pll_dividers(crtc, reduced_clock);
6012 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
6013 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
6015 dpll = DPLL_VGA_MODE_DIS;
6017 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
6018 dpll |= DPLLB_MODE_LVDS;
6020 dpll |= DPLLB_MODE_DAC_SERIAL;
6022 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6023 dpll |= (crtc->config.pixel_multiplier - 1)
6024 << SDVO_MULTIPLIER_SHIFT_HIRES;
6028 dpll |= DPLL_SDVO_HIGH_SPEED;
6030 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
6031 dpll |= DPLL_SDVO_HIGH_SPEED;
6033 /* compute bitmask from p1 value */
6034 if (IS_PINEVIEW(dev))
6035 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6037 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6038 if (IS_G4X(dev) && reduced_clock)
6039 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6041 switch (clock->p2) {
6043 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6046 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6049 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6052 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6055 if (INTEL_INFO(dev)->gen >= 4)
6056 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6058 if (crtc->config.sdvo_tv_clock)
6059 dpll |= PLL_REF_INPUT_TVCLKINBC;
6060 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6061 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6062 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6064 dpll |= PLL_REF_INPUT_DREFCLK;
6066 dpll |= DPLL_VCO_ENABLE;
6067 crtc->config.dpll_hw_state.dpll = dpll;
6069 if (INTEL_INFO(dev)->gen >= 4) {
6070 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
6071 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6072 crtc->config.dpll_hw_state.dpll_md = dpll_md;
6076 static void i8xx_update_pll(struct intel_crtc *crtc,
6077 intel_clock_t *reduced_clock,
6080 struct drm_device *dev = crtc->base.dev;
6081 struct drm_i915_private *dev_priv = dev->dev_private;
6083 struct dpll *clock = &crtc->config.dpll;
6085 i9xx_update_pll_dividers(crtc, reduced_clock);
6087 dpll = DPLL_VGA_MODE_DIS;
6089 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
6090 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6093 dpll |= PLL_P1_DIVIDE_BY_TWO;
6095 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6097 dpll |= PLL_P2_DIVIDE_BY_4;
6100 if (!IS_I830(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
6101 dpll |= DPLL_DVO_2X_MODE;
6103 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6104 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6105 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6107 dpll |= PLL_REF_INPUT_DREFCLK;
6109 dpll |= DPLL_VCO_ENABLE;
6110 crtc->config.dpll_hw_state.dpll = dpll;
6113 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6115 struct drm_device *dev = intel_crtc->base.dev;
6116 struct drm_i915_private *dev_priv = dev->dev_private;
6117 enum pipe pipe = intel_crtc->pipe;
6118 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6119 struct drm_display_mode *adjusted_mode =
6120 &intel_crtc->config.adjusted_mode;
6121 uint32_t crtc_vtotal, crtc_vblank_end;
6124 /* We need to be careful not to changed the adjusted mode, for otherwise
6125 * the hw state checker will get angry at the mismatch. */
6126 crtc_vtotal = adjusted_mode->crtc_vtotal;
6127 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6129 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6130 /* the chip adds 2 halflines automatically */
6132 crtc_vblank_end -= 1;
6134 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6135 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6137 vsyncshift = adjusted_mode->crtc_hsync_start -
6138 adjusted_mode->crtc_htotal / 2;
6140 vsyncshift += adjusted_mode->crtc_htotal;
6143 if (INTEL_INFO(dev)->gen > 3)
6144 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6146 I915_WRITE(HTOTAL(cpu_transcoder),
6147 (adjusted_mode->crtc_hdisplay - 1) |
6148 ((adjusted_mode->crtc_htotal - 1) << 16));
6149 I915_WRITE(HBLANK(cpu_transcoder),
6150 (adjusted_mode->crtc_hblank_start - 1) |
6151 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6152 I915_WRITE(HSYNC(cpu_transcoder),
6153 (adjusted_mode->crtc_hsync_start - 1) |
6154 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6156 I915_WRITE(VTOTAL(cpu_transcoder),
6157 (adjusted_mode->crtc_vdisplay - 1) |
6158 ((crtc_vtotal - 1) << 16));
6159 I915_WRITE(VBLANK(cpu_transcoder),
6160 (adjusted_mode->crtc_vblank_start - 1) |
6161 ((crtc_vblank_end - 1) << 16));
6162 I915_WRITE(VSYNC(cpu_transcoder),
6163 (adjusted_mode->crtc_vsync_start - 1) |
6164 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6166 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6167 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6168 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6170 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6171 (pipe == PIPE_B || pipe == PIPE_C))
6172 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6174 /* pipesrc controls the size that is scaled from, which should
6175 * always be the user's requested size.
6177 I915_WRITE(PIPESRC(pipe),
6178 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6179 (intel_crtc->config.pipe_src_h - 1));
6182 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6183 struct intel_crtc_config *pipe_config)
6185 struct drm_device *dev = crtc->base.dev;
6186 struct drm_i915_private *dev_priv = dev->dev_private;
6187 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6190 tmp = I915_READ(HTOTAL(cpu_transcoder));
6191 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6192 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6193 tmp = I915_READ(HBLANK(cpu_transcoder));
6194 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6195 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6196 tmp = I915_READ(HSYNC(cpu_transcoder));
6197 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6198 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6200 tmp = I915_READ(VTOTAL(cpu_transcoder));
6201 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6202 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6203 tmp = I915_READ(VBLANK(cpu_transcoder));
6204 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6205 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6206 tmp = I915_READ(VSYNC(cpu_transcoder));
6207 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6208 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6210 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6211 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6212 pipe_config->adjusted_mode.crtc_vtotal += 1;
6213 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6216 tmp = I915_READ(PIPESRC(crtc->pipe));
6217 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6218 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6220 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6221 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6224 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6225 struct intel_crtc_config *pipe_config)
6227 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6228 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6229 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6230 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6232 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6233 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6234 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6235 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6237 mode->flags = pipe_config->adjusted_mode.flags;
6239 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6240 mode->flags |= pipe_config->adjusted_mode.flags;
6243 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6245 struct drm_device *dev = intel_crtc->base.dev;
6246 struct drm_i915_private *dev_priv = dev->dev_private;
6251 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6252 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6253 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6255 if (intel_crtc->config.double_wide)
6256 pipeconf |= PIPECONF_DOUBLE_WIDE;
6258 /* only g4x and later have fancy bpc/dither controls */
6259 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6260 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6261 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6262 pipeconf |= PIPECONF_DITHER_EN |
6263 PIPECONF_DITHER_TYPE_SP;
6265 switch (intel_crtc->config.pipe_bpp) {
6267 pipeconf |= PIPECONF_6BPC;
6270 pipeconf |= PIPECONF_8BPC;
6273 pipeconf |= PIPECONF_10BPC;
6276 /* Case prevented by intel_choose_pipe_bpp_dither. */
6281 if (HAS_PIPE_CXSR(dev)) {
6282 if (intel_crtc->lowfreq_avail) {
6283 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6284 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6286 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6290 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6291 if (INTEL_INFO(dev)->gen < 4 ||
6292 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6293 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6295 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6297 pipeconf |= PIPECONF_PROGRESSIVE;
6299 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6300 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6302 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6303 POSTING_READ(PIPECONF(intel_crtc->pipe));
6306 static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
6308 struct drm_framebuffer *fb)
6310 struct drm_device *dev = crtc->base.dev;
6311 struct drm_i915_private *dev_priv = dev->dev_private;
6312 int refclk, num_connectors = 0;
6313 intel_clock_t clock, reduced_clock;
6314 bool ok, has_reduced_clock = false;
6315 bool is_lvds = false, is_dsi = false;
6316 struct intel_encoder *encoder;
6317 const intel_limit_t *limit;
6319 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6320 switch (encoder->type) {
6321 case INTEL_OUTPUT_LVDS:
6324 case INTEL_OUTPUT_DSI:
6337 if (!crtc->config.clock_set) {
6338 refclk = i9xx_get_refclk(crtc, num_connectors);
6341 * Returns a set of divisors for the desired target clock with
6342 * the given refclk, or FALSE. The returned values represent
6343 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6346 limit = intel_limit(crtc, refclk);
6347 ok = dev_priv->display.find_dpll(limit, crtc,
6348 crtc->config.port_clock,
6349 refclk, NULL, &clock);
6351 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6355 if (is_lvds && dev_priv->lvds_downclock_avail) {
6357 * Ensure we match the reduced clock's P to the target
6358 * clock. If the clocks don't match, we can't switch
6359 * the display clock by using the FP0/FP1. In such case
6360 * we will disable the LVDS downclock feature.
6363 dev_priv->display.find_dpll(limit, crtc,
6364 dev_priv->lvds_downclock,
6368 /* Compat-code for transition, will disappear. */
6369 crtc->config.dpll.n = clock.n;
6370 crtc->config.dpll.m1 = clock.m1;
6371 crtc->config.dpll.m2 = clock.m2;
6372 crtc->config.dpll.p1 = clock.p1;
6373 crtc->config.dpll.p2 = clock.p2;
6377 i8xx_update_pll(crtc,
6378 has_reduced_clock ? &reduced_clock : NULL,
6380 } else if (IS_CHERRYVIEW(dev)) {
6381 chv_update_pll(crtc, &crtc->config);
6382 } else if (IS_VALLEYVIEW(dev)) {
6383 vlv_update_pll(crtc, &crtc->config);
6385 i9xx_update_pll(crtc,
6386 has_reduced_clock ? &reduced_clock : NULL,
6393 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6394 struct intel_crtc_config *pipe_config)
6396 struct drm_device *dev = crtc->base.dev;
6397 struct drm_i915_private *dev_priv = dev->dev_private;
6400 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6403 tmp = I915_READ(PFIT_CONTROL);
6404 if (!(tmp & PFIT_ENABLE))
6407 /* Check whether the pfit is attached to our pipe. */
6408 if (INTEL_INFO(dev)->gen < 4) {
6409 if (crtc->pipe != PIPE_B)
6412 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6416 pipe_config->gmch_pfit.control = tmp;
6417 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6418 if (INTEL_INFO(dev)->gen < 5)
6419 pipe_config->gmch_pfit.lvds_border_bits =
6420 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6423 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6424 struct intel_crtc_config *pipe_config)
6426 struct drm_device *dev = crtc->base.dev;
6427 struct drm_i915_private *dev_priv = dev->dev_private;
6428 int pipe = pipe_config->cpu_transcoder;
6429 intel_clock_t clock;
6431 int refclk = 100000;
6433 /* In case of MIPI DPLL will not even be used */
6434 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6437 mutex_lock(&dev_priv->dpio_lock);
6438 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6439 mutex_unlock(&dev_priv->dpio_lock);
6441 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6442 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6443 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6444 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6445 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6447 vlv_clock(refclk, &clock);
6449 /* clock.dot is the fast clock */
6450 pipe_config->port_clock = clock.dot / 5;
6453 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6454 struct intel_plane_config *plane_config)
6456 struct drm_device *dev = crtc->base.dev;
6457 struct drm_i915_private *dev_priv = dev->dev_private;
6458 u32 val, base, offset;
6459 int pipe = crtc->pipe, plane = crtc->plane;
6460 int fourcc, pixel_format;
6463 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6464 if (!crtc->base.primary->fb) {
6465 DRM_DEBUG_KMS("failed to alloc fb\n");
6469 val = I915_READ(DSPCNTR(plane));
6471 if (INTEL_INFO(dev)->gen >= 4)
6472 if (val & DISPPLANE_TILED)
6473 plane_config->tiled = true;
6475 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6476 fourcc = intel_format_to_fourcc(pixel_format);
6477 crtc->base.primary->fb->pixel_format = fourcc;
6478 crtc->base.primary->fb->bits_per_pixel =
6479 drm_format_plane_cpp(fourcc, 0) * 8;
6481 if (INTEL_INFO(dev)->gen >= 4) {
6482 if (plane_config->tiled)
6483 offset = I915_READ(DSPTILEOFF(plane));
6485 offset = I915_READ(DSPLINOFF(plane));
6486 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6488 base = I915_READ(DSPADDR(plane));
6490 plane_config->base = base;
6492 val = I915_READ(PIPESRC(pipe));
6493 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6494 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6496 val = I915_READ(DSPSTRIDE(pipe));
6497 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6499 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6500 plane_config->tiled);
6502 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6505 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6506 pipe, plane, crtc->base.primary->fb->width,
6507 crtc->base.primary->fb->height,
6508 crtc->base.primary->fb->bits_per_pixel, base,
6509 crtc->base.primary->fb->pitches[0],
6510 plane_config->size);
6514 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6515 struct intel_crtc_config *pipe_config)
6517 struct drm_device *dev = crtc->base.dev;
6518 struct drm_i915_private *dev_priv = dev->dev_private;
6519 int pipe = pipe_config->cpu_transcoder;
6520 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6521 intel_clock_t clock;
6522 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6523 int refclk = 100000;
6525 mutex_lock(&dev_priv->dpio_lock);
6526 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6527 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6528 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6529 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6530 mutex_unlock(&dev_priv->dpio_lock);
6532 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6533 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6534 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6535 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6536 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6538 chv_clock(refclk, &clock);
6540 /* clock.dot is the fast clock */
6541 pipe_config->port_clock = clock.dot / 5;
6544 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6545 struct intel_crtc_config *pipe_config)
6547 struct drm_device *dev = crtc->base.dev;
6548 struct drm_i915_private *dev_priv = dev->dev_private;
6551 if (!intel_display_power_is_enabled(dev_priv,
6552 POWER_DOMAIN_PIPE(crtc->pipe)))
6555 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6556 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6558 tmp = I915_READ(PIPECONF(crtc->pipe));
6559 if (!(tmp & PIPECONF_ENABLE))
6562 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6563 switch (tmp & PIPECONF_BPC_MASK) {
6565 pipe_config->pipe_bpp = 18;
6568 pipe_config->pipe_bpp = 24;
6570 case PIPECONF_10BPC:
6571 pipe_config->pipe_bpp = 30;
6578 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6579 pipe_config->limited_color_range = true;
6581 if (INTEL_INFO(dev)->gen < 4)
6582 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6584 intel_get_pipe_timings(crtc, pipe_config);
6586 i9xx_get_pfit_config(crtc, pipe_config);
6588 if (INTEL_INFO(dev)->gen >= 4) {
6589 tmp = I915_READ(DPLL_MD(crtc->pipe));
6590 pipe_config->pixel_multiplier =
6591 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6592 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6593 pipe_config->dpll_hw_state.dpll_md = tmp;
6594 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6595 tmp = I915_READ(DPLL(crtc->pipe));
6596 pipe_config->pixel_multiplier =
6597 ((tmp & SDVO_MULTIPLIER_MASK)
6598 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6600 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6601 * port and will be fixed up in the encoder->get_config
6603 pipe_config->pixel_multiplier = 1;
6605 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6606 if (!IS_VALLEYVIEW(dev)) {
6608 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6609 * on 830. Filter it out here so that we don't
6610 * report errors due to that.
6613 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6615 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6616 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6618 /* Mask out read-only status bits. */
6619 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6620 DPLL_PORTC_READY_MASK |
6621 DPLL_PORTB_READY_MASK);
6624 if (IS_CHERRYVIEW(dev))
6625 chv_crtc_clock_get(crtc, pipe_config);
6626 else if (IS_VALLEYVIEW(dev))
6627 vlv_crtc_clock_get(crtc, pipe_config);
6629 i9xx_crtc_clock_get(crtc, pipe_config);
6634 static void ironlake_init_pch_refclk(struct drm_device *dev)
6636 struct drm_i915_private *dev_priv = dev->dev_private;
6637 struct intel_encoder *encoder;
6639 bool has_lvds = false;
6640 bool has_cpu_edp = false;
6641 bool has_panel = false;
6642 bool has_ck505 = false;
6643 bool can_ssc = false;
6645 /* We need to take the global config into account */
6646 for_each_intel_encoder(dev, encoder) {
6647 switch (encoder->type) {
6648 case INTEL_OUTPUT_LVDS:
6652 case INTEL_OUTPUT_EDP:
6654 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6662 if (HAS_PCH_IBX(dev)) {
6663 has_ck505 = dev_priv->vbt.display_clock_mode;
6664 can_ssc = has_ck505;
6670 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6671 has_panel, has_lvds, has_ck505);
6673 /* Ironlake: try to setup display ref clock before DPLL
6674 * enabling. This is only under driver's control after
6675 * PCH B stepping, previous chipset stepping should be
6676 * ignoring this setting.
6678 val = I915_READ(PCH_DREF_CONTROL);
6680 /* As we must carefully and slowly disable/enable each source in turn,
6681 * compute the final state we want first and check if we need to
6682 * make any changes at all.
6685 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6687 final |= DREF_NONSPREAD_CK505_ENABLE;
6689 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6691 final &= ~DREF_SSC_SOURCE_MASK;
6692 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6693 final &= ~DREF_SSC1_ENABLE;
6696 final |= DREF_SSC_SOURCE_ENABLE;
6698 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6699 final |= DREF_SSC1_ENABLE;
6702 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6703 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6705 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6707 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6709 final |= DREF_SSC_SOURCE_DISABLE;
6710 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6716 /* Always enable nonspread source */
6717 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6720 val |= DREF_NONSPREAD_CK505_ENABLE;
6722 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6725 val &= ~DREF_SSC_SOURCE_MASK;
6726 val |= DREF_SSC_SOURCE_ENABLE;
6728 /* SSC must be turned on before enabling the CPU output */
6729 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6730 DRM_DEBUG_KMS("Using SSC on panel\n");
6731 val |= DREF_SSC1_ENABLE;
6733 val &= ~DREF_SSC1_ENABLE;
6735 /* Get SSC going before enabling the outputs */
6736 I915_WRITE(PCH_DREF_CONTROL, val);
6737 POSTING_READ(PCH_DREF_CONTROL);
6740 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6742 /* Enable CPU source on CPU attached eDP */
6744 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6745 DRM_DEBUG_KMS("Using SSC on eDP\n");
6746 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6748 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6750 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6752 I915_WRITE(PCH_DREF_CONTROL, val);
6753 POSTING_READ(PCH_DREF_CONTROL);
6756 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6758 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6760 /* Turn off CPU output */
6761 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6763 I915_WRITE(PCH_DREF_CONTROL, val);
6764 POSTING_READ(PCH_DREF_CONTROL);
6767 /* Turn off the SSC source */
6768 val &= ~DREF_SSC_SOURCE_MASK;
6769 val |= DREF_SSC_SOURCE_DISABLE;
6772 val &= ~DREF_SSC1_ENABLE;
6774 I915_WRITE(PCH_DREF_CONTROL, val);
6775 POSTING_READ(PCH_DREF_CONTROL);
6779 BUG_ON(val != final);
6782 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6786 tmp = I915_READ(SOUTH_CHICKEN2);
6787 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6788 I915_WRITE(SOUTH_CHICKEN2, tmp);
6790 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6791 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6792 DRM_ERROR("FDI mPHY reset assert timeout\n");
6794 tmp = I915_READ(SOUTH_CHICKEN2);
6795 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6796 I915_WRITE(SOUTH_CHICKEN2, tmp);
6798 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6799 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6800 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6803 /* WaMPhyProgramming:hsw */
6804 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6808 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6809 tmp &= ~(0xFF << 24);
6810 tmp |= (0x12 << 24);
6811 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6813 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6815 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6817 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6819 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6821 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6822 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6823 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6825 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6826 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6827 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6829 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6832 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6834 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6837 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6839 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6842 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6844 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6847 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6849 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6850 tmp &= ~(0xFF << 16);
6851 tmp |= (0x1C << 16);
6852 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6854 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6855 tmp &= ~(0xFF << 16);
6856 tmp |= (0x1C << 16);
6857 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6859 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6861 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6863 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6865 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6867 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6868 tmp &= ~(0xF << 28);
6870 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6872 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6873 tmp &= ~(0xF << 28);
6875 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6878 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6879 * Programming" based on the parameters passed:
6880 * - Sequence to enable CLKOUT_DP
6881 * - Sequence to enable CLKOUT_DP without spread
6882 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6884 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6887 struct drm_i915_private *dev_priv = dev->dev_private;
6890 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6892 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6893 with_fdi, "LP PCH doesn't have FDI\n"))
6896 mutex_lock(&dev_priv->dpio_lock);
6898 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6899 tmp &= ~SBI_SSCCTL_DISABLE;
6900 tmp |= SBI_SSCCTL_PATHALT;
6901 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6906 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6907 tmp &= ~SBI_SSCCTL_PATHALT;
6908 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6911 lpt_reset_fdi_mphy(dev_priv);
6912 lpt_program_fdi_mphy(dev_priv);
6916 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6917 SBI_GEN0 : SBI_DBUFF0;
6918 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6919 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6920 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6922 mutex_unlock(&dev_priv->dpio_lock);
6925 /* Sequence to disable CLKOUT_DP */
6926 static void lpt_disable_clkout_dp(struct drm_device *dev)
6928 struct drm_i915_private *dev_priv = dev->dev_private;
6931 mutex_lock(&dev_priv->dpio_lock);
6933 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6934 SBI_GEN0 : SBI_DBUFF0;
6935 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6936 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6937 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6939 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6940 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6941 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6942 tmp |= SBI_SSCCTL_PATHALT;
6943 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6946 tmp |= SBI_SSCCTL_DISABLE;
6947 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6950 mutex_unlock(&dev_priv->dpio_lock);
6953 static void lpt_init_pch_refclk(struct drm_device *dev)
6955 struct intel_encoder *encoder;
6956 bool has_vga = false;
6958 for_each_intel_encoder(dev, encoder) {
6959 switch (encoder->type) {
6960 case INTEL_OUTPUT_ANALOG:
6969 lpt_enable_clkout_dp(dev, true, true);
6971 lpt_disable_clkout_dp(dev);
6975 * Initialize reference clocks when the driver loads
6977 void intel_init_pch_refclk(struct drm_device *dev)
6979 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6980 ironlake_init_pch_refclk(dev);
6981 else if (HAS_PCH_LPT(dev))
6982 lpt_init_pch_refclk(dev);
6985 static int ironlake_get_refclk(struct drm_crtc *crtc)
6987 struct drm_device *dev = crtc->dev;
6988 struct drm_i915_private *dev_priv = dev->dev_private;
6989 struct intel_encoder *encoder;
6990 int num_connectors = 0;
6991 bool is_lvds = false;
6993 for_each_encoder_on_crtc(dev, crtc, encoder) {
6994 switch (encoder->type) {
6995 case INTEL_OUTPUT_LVDS:
7004 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7005 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7006 dev_priv->vbt.lvds_ssc_freq);
7007 return dev_priv->vbt.lvds_ssc_freq;
7013 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7015 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7017 int pipe = intel_crtc->pipe;
7022 switch (intel_crtc->config.pipe_bpp) {
7024 val |= PIPECONF_6BPC;
7027 val |= PIPECONF_8BPC;
7030 val |= PIPECONF_10BPC;
7033 val |= PIPECONF_12BPC;
7036 /* Case prevented by intel_choose_pipe_bpp_dither. */
7040 if (intel_crtc->config.dither)
7041 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7043 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7044 val |= PIPECONF_INTERLACED_ILK;
7046 val |= PIPECONF_PROGRESSIVE;
7048 if (intel_crtc->config.limited_color_range)
7049 val |= PIPECONF_COLOR_RANGE_SELECT;
7051 I915_WRITE(PIPECONF(pipe), val);
7052 POSTING_READ(PIPECONF(pipe));
7056 * Set up the pipe CSC unit.
7058 * Currently only full range RGB to limited range RGB conversion
7059 * is supported, but eventually this should handle various
7060 * RGB<->YCbCr scenarios as well.
7062 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7064 struct drm_device *dev = crtc->dev;
7065 struct drm_i915_private *dev_priv = dev->dev_private;
7066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7067 int pipe = intel_crtc->pipe;
7068 uint16_t coeff = 0x7800; /* 1.0 */
7071 * TODO: Check what kind of values actually come out of the pipe
7072 * with these coeff/postoff values and adjust to get the best
7073 * accuracy. Perhaps we even need to take the bpc value into
7077 if (intel_crtc->config.limited_color_range)
7078 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7081 * GY/GU and RY/RU should be the other way around according
7082 * to BSpec, but reality doesn't agree. Just set them up in
7083 * a way that results in the correct picture.
7085 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7086 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7088 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7089 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7091 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7092 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7094 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7095 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7096 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7098 if (INTEL_INFO(dev)->gen > 6) {
7099 uint16_t postoff = 0;
7101 if (intel_crtc->config.limited_color_range)
7102 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7104 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7105 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7106 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7108 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7110 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7112 if (intel_crtc->config.limited_color_range)
7113 mode |= CSC_BLACK_SCREEN_OFFSET;
7115 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7119 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7121 struct drm_device *dev = crtc->dev;
7122 struct drm_i915_private *dev_priv = dev->dev_private;
7123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7124 enum pipe pipe = intel_crtc->pipe;
7125 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7130 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7131 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7133 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7134 val |= PIPECONF_INTERLACED_ILK;
7136 val |= PIPECONF_PROGRESSIVE;
7138 I915_WRITE(PIPECONF(cpu_transcoder), val);
7139 POSTING_READ(PIPECONF(cpu_transcoder));
7141 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7142 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7144 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7147 switch (intel_crtc->config.pipe_bpp) {
7149 val |= PIPEMISC_DITHER_6_BPC;
7152 val |= PIPEMISC_DITHER_8_BPC;
7155 val |= PIPEMISC_DITHER_10_BPC;
7158 val |= PIPEMISC_DITHER_12_BPC;
7161 /* Case prevented by pipe_config_set_bpp. */
7165 if (intel_crtc->config.dither)
7166 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7168 I915_WRITE(PIPEMISC(pipe), val);
7172 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7173 intel_clock_t *clock,
7174 bool *has_reduced_clock,
7175 intel_clock_t *reduced_clock)
7177 struct drm_device *dev = crtc->dev;
7178 struct drm_i915_private *dev_priv = dev->dev_private;
7179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7181 const intel_limit_t *limit;
7182 bool ret, is_lvds = false;
7184 is_lvds = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_LVDS);
7186 refclk = ironlake_get_refclk(crtc);
7189 * Returns a set of divisors for the desired target clock with the given
7190 * refclk, or FALSE. The returned values represent the clock equation:
7191 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7193 limit = intel_limit(intel_crtc, refclk);
7194 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7195 intel_crtc->config.port_clock,
7196 refclk, NULL, clock);
7200 if (is_lvds && dev_priv->lvds_downclock_avail) {
7202 * Ensure we match the reduced clock's P to the target clock.
7203 * If the clocks don't match, we can't switch the display clock
7204 * by using the FP0/FP1. In such case we will disable the LVDS
7205 * downclock feature.
7207 *has_reduced_clock =
7208 dev_priv->display.find_dpll(limit, intel_crtc,
7209 dev_priv->lvds_downclock,
7217 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7220 * Account for spread spectrum to avoid
7221 * oversubscribing the link. Max center spread
7222 * is 2.5%; use 5% for safety's sake.
7224 u32 bps = target_clock * bpp * 21 / 20;
7225 return DIV_ROUND_UP(bps, link_bw * 8);
7228 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7230 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7233 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7235 intel_clock_t *reduced_clock, u32 *fp2)
7237 struct drm_crtc *crtc = &intel_crtc->base;
7238 struct drm_device *dev = crtc->dev;
7239 struct drm_i915_private *dev_priv = dev->dev_private;
7240 struct intel_encoder *intel_encoder;
7242 int factor, num_connectors = 0;
7243 bool is_lvds = false, is_sdvo = false;
7245 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7246 switch (intel_encoder->type) {
7247 case INTEL_OUTPUT_LVDS:
7250 case INTEL_OUTPUT_SDVO:
7251 case INTEL_OUTPUT_HDMI:
7261 /* Enable autotuning of the PLL clock (if permissible) */
7264 if ((intel_panel_use_ssc(dev_priv) &&
7265 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7266 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7268 } else if (intel_crtc->config.sdvo_tv_clock)
7271 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7274 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7280 dpll |= DPLLB_MODE_LVDS;
7282 dpll |= DPLLB_MODE_DAC_SERIAL;
7284 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7285 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7288 dpll |= DPLL_SDVO_HIGH_SPEED;
7289 if (intel_crtc->config.has_dp_encoder)
7290 dpll |= DPLL_SDVO_HIGH_SPEED;
7292 /* compute bitmask from p1 value */
7293 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7295 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7297 switch (intel_crtc->config.dpll.p2) {
7299 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7302 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7305 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7308 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7312 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7313 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7315 dpll |= PLL_REF_INPUT_DREFCLK;
7317 return dpll | DPLL_VCO_ENABLE;
7320 static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
7322 struct drm_framebuffer *fb)
7324 struct drm_device *dev = crtc->base.dev;
7325 intel_clock_t clock, reduced_clock;
7326 u32 dpll = 0, fp = 0, fp2 = 0;
7327 bool ok, has_reduced_clock = false;
7328 bool is_lvds = false;
7329 struct intel_shared_dpll *pll;
7331 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7333 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7334 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7336 ok = ironlake_compute_clocks(&crtc->base, &clock,
7337 &has_reduced_clock, &reduced_clock);
7338 if (!ok && !crtc->config.clock_set) {
7339 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7342 /* Compat-code for transition, will disappear. */
7343 if (!crtc->config.clock_set) {
7344 crtc->config.dpll.n = clock.n;
7345 crtc->config.dpll.m1 = clock.m1;
7346 crtc->config.dpll.m2 = clock.m2;
7347 crtc->config.dpll.p1 = clock.p1;
7348 crtc->config.dpll.p2 = clock.p2;
7351 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7352 if (crtc->config.has_pch_encoder) {
7353 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
7354 if (has_reduced_clock)
7355 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7357 dpll = ironlake_compute_dpll(crtc,
7358 &fp, &reduced_clock,
7359 has_reduced_clock ? &fp2 : NULL);
7361 crtc->config.dpll_hw_state.dpll = dpll;
7362 crtc->config.dpll_hw_state.fp0 = fp;
7363 if (has_reduced_clock)
7364 crtc->config.dpll_hw_state.fp1 = fp2;
7366 crtc->config.dpll_hw_state.fp1 = fp;
7368 pll = intel_get_shared_dpll(crtc);
7370 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7371 pipe_name(crtc->pipe));
7375 intel_put_shared_dpll(crtc);
7377 if (is_lvds && has_reduced_clock && i915.powersave)
7378 crtc->lowfreq_avail = true;
7380 crtc->lowfreq_avail = false;
7385 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7386 struct intel_link_m_n *m_n)
7388 struct drm_device *dev = crtc->base.dev;
7389 struct drm_i915_private *dev_priv = dev->dev_private;
7390 enum pipe pipe = crtc->pipe;
7392 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7393 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7394 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7396 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7397 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7398 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7401 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7402 enum transcoder transcoder,
7403 struct intel_link_m_n *m_n,
7404 struct intel_link_m_n *m2_n2)
7406 struct drm_device *dev = crtc->base.dev;
7407 struct drm_i915_private *dev_priv = dev->dev_private;
7408 enum pipe pipe = crtc->pipe;
7410 if (INTEL_INFO(dev)->gen >= 5) {
7411 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7412 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7413 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7415 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7416 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7417 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7418 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7419 * gen < 8) and if DRRS is supported (to make sure the
7420 * registers are not unnecessarily read).
7422 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7423 crtc->config.has_drrs) {
7424 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7425 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7426 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7428 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7429 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7430 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7433 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7434 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7435 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7437 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7438 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7439 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7443 void intel_dp_get_m_n(struct intel_crtc *crtc,
7444 struct intel_crtc_config *pipe_config)
7446 if (crtc->config.has_pch_encoder)
7447 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7449 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7450 &pipe_config->dp_m_n,
7451 &pipe_config->dp_m2_n2);
7454 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7455 struct intel_crtc_config *pipe_config)
7457 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7458 &pipe_config->fdi_m_n, NULL);
7461 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7462 struct intel_crtc_config *pipe_config)
7464 struct drm_device *dev = crtc->base.dev;
7465 struct drm_i915_private *dev_priv = dev->dev_private;
7468 tmp = I915_READ(PF_CTL(crtc->pipe));
7470 if (tmp & PF_ENABLE) {
7471 pipe_config->pch_pfit.enabled = true;
7472 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7473 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7475 /* We currently do not free assignements of panel fitters on
7476 * ivb/hsw (since we don't use the higher upscaling modes which
7477 * differentiates them) so just WARN about this case for now. */
7479 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7480 PF_PIPE_SEL_IVB(crtc->pipe));
7485 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7486 struct intel_plane_config *plane_config)
7488 struct drm_device *dev = crtc->base.dev;
7489 struct drm_i915_private *dev_priv = dev->dev_private;
7490 u32 val, base, offset;
7491 int pipe = crtc->pipe, plane = crtc->plane;
7492 int fourcc, pixel_format;
7495 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7496 if (!crtc->base.primary->fb) {
7497 DRM_DEBUG_KMS("failed to alloc fb\n");
7501 val = I915_READ(DSPCNTR(plane));
7503 if (INTEL_INFO(dev)->gen >= 4)
7504 if (val & DISPPLANE_TILED)
7505 plane_config->tiled = true;
7507 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7508 fourcc = intel_format_to_fourcc(pixel_format);
7509 crtc->base.primary->fb->pixel_format = fourcc;
7510 crtc->base.primary->fb->bits_per_pixel =
7511 drm_format_plane_cpp(fourcc, 0) * 8;
7513 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7514 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7515 offset = I915_READ(DSPOFFSET(plane));
7517 if (plane_config->tiled)
7518 offset = I915_READ(DSPTILEOFF(plane));
7520 offset = I915_READ(DSPLINOFF(plane));
7522 plane_config->base = base;
7524 val = I915_READ(PIPESRC(pipe));
7525 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7526 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7528 val = I915_READ(DSPSTRIDE(pipe));
7529 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7531 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7532 plane_config->tiled);
7534 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7537 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7538 pipe, plane, crtc->base.primary->fb->width,
7539 crtc->base.primary->fb->height,
7540 crtc->base.primary->fb->bits_per_pixel, base,
7541 crtc->base.primary->fb->pitches[0],
7542 plane_config->size);
7545 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7546 struct intel_crtc_config *pipe_config)
7548 struct drm_device *dev = crtc->base.dev;
7549 struct drm_i915_private *dev_priv = dev->dev_private;
7552 if (!intel_display_power_is_enabled(dev_priv,
7553 POWER_DOMAIN_PIPE(crtc->pipe)))
7556 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7557 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7559 tmp = I915_READ(PIPECONF(crtc->pipe));
7560 if (!(tmp & PIPECONF_ENABLE))
7563 switch (tmp & PIPECONF_BPC_MASK) {
7565 pipe_config->pipe_bpp = 18;
7568 pipe_config->pipe_bpp = 24;
7570 case PIPECONF_10BPC:
7571 pipe_config->pipe_bpp = 30;
7573 case PIPECONF_12BPC:
7574 pipe_config->pipe_bpp = 36;
7580 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7581 pipe_config->limited_color_range = true;
7583 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7584 struct intel_shared_dpll *pll;
7586 pipe_config->has_pch_encoder = true;
7588 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7589 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7590 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7592 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7594 if (HAS_PCH_IBX(dev_priv->dev)) {
7595 pipe_config->shared_dpll =
7596 (enum intel_dpll_id) crtc->pipe;
7598 tmp = I915_READ(PCH_DPLL_SEL);
7599 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7600 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7602 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7605 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7607 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7608 &pipe_config->dpll_hw_state));
7610 tmp = pipe_config->dpll_hw_state.dpll;
7611 pipe_config->pixel_multiplier =
7612 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7613 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7615 ironlake_pch_clock_get(crtc, pipe_config);
7617 pipe_config->pixel_multiplier = 1;
7620 intel_get_pipe_timings(crtc, pipe_config);
7622 ironlake_get_pfit_config(crtc, pipe_config);
7627 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7629 struct drm_device *dev = dev_priv->dev;
7630 struct intel_crtc *crtc;
7632 for_each_intel_crtc(dev, crtc)
7633 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7634 pipe_name(crtc->pipe));
7636 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7637 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7638 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7639 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7640 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7641 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7642 "CPU PWM1 enabled\n");
7643 if (IS_HASWELL(dev))
7644 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7645 "CPU PWM2 enabled\n");
7646 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7647 "PCH PWM1 enabled\n");
7648 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7649 "Utility pin enabled\n");
7650 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7653 * In theory we can still leave IRQs enabled, as long as only the HPD
7654 * interrupts remain enabled. We used to check for that, but since it's
7655 * gen-specific and since we only disable LCPLL after we fully disable
7656 * the interrupts, the check below should be enough.
7658 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7661 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7663 struct drm_device *dev = dev_priv->dev;
7665 if (IS_HASWELL(dev))
7666 return I915_READ(D_COMP_HSW);
7668 return I915_READ(D_COMP_BDW);
7671 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7673 struct drm_device *dev = dev_priv->dev;
7675 if (IS_HASWELL(dev)) {
7676 mutex_lock(&dev_priv->rps.hw_lock);
7677 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7679 DRM_ERROR("Failed to write to D_COMP\n");
7680 mutex_unlock(&dev_priv->rps.hw_lock);
7682 I915_WRITE(D_COMP_BDW, val);
7683 POSTING_READ(D_COMP_BDW);
7688 * This function implements pieces of two sequences from BSpec:
7689 * - Sequence for display software to disable LCPLL
7690 * - Sequence for display software to allow package C8+
7691 * The steps implemented here are just the steps that actually touch the LCPLL
7692 * register. Callers should take care of disabling all the display engine
7693 * functions, doing the mode unset, fixing interrupts, etc.
7695 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7696 bool switch_to_fclk, bool allow_power_down)
7700 assert_can_disable_lcpll(dev_priv);
7702 val = I915_READ(LCPLL_CTL);
7704 if (switch_to_fclk) {
7705 val |= LCPLL_CD_SOURCE_FCLK;
7706 I915_WRITE(LCPLL_CTL, val);
7708 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7709 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7710 DRM_ERROR("Switching to FCLK failed\n");
7712 val = I915_READ(LCPLL_CTL);
7715 val |= LCPLL_PLL_DISABLE;
7716 I915_WRITE(LCPLL_CTL, val);
7717 POSTING_READ(LCPLL_CTL);
7719 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7720 DRM_ERROR("LCPLL still locked\n");
7722 val = hsw_read_dcomp(dev_priv);
7723 val |= D_COMP_COMP_DISABLE;
7724 hsw_write_dcomp(dev_priv, val);
7727 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7729 DRM_ERROR("D_COMP RCOMP still in progress\n");
7731 if (allow_power_down) {
7732 val = I915_READ(LCPLL_CTL);
7733 val |= LCPLL_POWER_DOWN_ALLOW;
7734 I915_WRITE(LCPLL_CTL, val);
7735 POSTING_READ(LCPLL_CTL);
7740 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7743 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7747 val = I915_READ(LCPLL_CTL);
7749 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7750 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7754 * Make sure we're not on PC8 state before disabling PC8, otherwise
7755 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7757 * The other problem is that hsw_restore_lcpll() is called as part of
7758 * the runtime PM resume sequence, so we can't just call
7759 * gen6_gt_force_wake_get() because that function calls
7760 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7761 * while we are on the resume sequence. So to solve this problem we have
7762 * to call special forcewake code that doesn't touch runtime PM and
7763 * doesn't enable the forcewake delayed work.
7765 spin_lock_irq(&dev_priv->uncore.lock);
7766 if (dev_priv->uncore.forcewake_count++ == 0)
7767 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7768 spin_unlock_irq(&dev_priv->uncore.lock);
7770 if (val & LCPLL_POWER_DOWN_ALLOW) {
7771 val &= ~LCPLL_POWER_DOWN_ALLOW;
7772 I915_WRITE(LCPLL_CTL, val);
7773 POSTING_READ(LCPLL_CTL);
7776 val = hsw_read_dcomp(dev_priv);
7777 val |= D_COMP_COMP_FORCE;
7778 val &= ~D_COMP_COMP_DISABLE;
7779 hsw_write_dcomp(dev_priv, val);
7781 val = I915_READ(LCPLL_CTL);
7782 val &= ~LCPLL_PLL_DISABLE;
7783 I915_WRITE(LCPLL_CTL, val);
7785 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7786 DRM_ERROR("LCPLL not locked yet\n");
7788 if (val & LCPLL_CD_SOURCE_FCLK) {
7789 val = I915_READ(LCPLL_CTL);
7790 val &= ~LCPLL_CD_SOURCE_FCLK;
7791 I915_WRITE(LCPLL_CTL, val);
7793 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7794 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7795 DRM_ERROR("Switching back to LCPLL failed\n");
7798 /* See the big comment above. */
7799 spin_lock_irq(&dev_priv->uncore.lock);
7800 if (--dev_priv->uncore.forcewake_count == 0)
7801 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7802 spin_unlock_irq(&dev_priv->uncore.lock);
7806 * Package states C8 and deeper are really deep PC states that can only be
7807 * reached when all the devices on the system allow it, so even if the graphics
7808 * device allows PC8+, it doesn't mean the system will actually get to these
7809 * states. Our driver only allows PC8+ when going into runtime PM.
7811 * The requirements for PC8+ are that all the outputs are disabled, the power
7812 * well is disabled and most interrupts are disabled, and these are also
7813 * requirements for runtime PM. When these conditions are met, we manually do
7814 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7815 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7818 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7819 * the state of some registers, so when we come back from PC8+ we need to
7820 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7821 * need to take care of the registers kept by RC6. Notice that this happens even
7822 * if we don't put the device in PCI D3 state (which is what currently happens
7823 * because of the runtime PM support).
7825 * For more, read "Display Sequences for Package C8" on the hardware
7828 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7830 struct drm_device *dev = dev_priv->dev;
7833 DRM_DEBUG_KMS("Enabling package C8+\n");
7835 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7836 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7837 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7838 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7841 lpt_disable_clkout_dp(dev);
7842 hsw_disable_lcpll(dev_priv, true, true);
7845 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7847 struct drm_device *dev = dev_priv->dev;
7850 DRM_DEBUG_KMS("Disabling package C8+\n");
7852 hsw_restore_lcpll(dev_priv);
7853 lpt_init_pch_refclk(dev);
7855 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7856 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7857 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7858 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7861 intel_prepare_ddi(dev);
7864 static void snb_modeset_global_resources(struct drm_device *dev)
7866 modeset_update_crtc_power_domains(dev);
7869 static void haswell_modeset_global_resources(struct drm_device *dev)
7871 modeset_update_crtc_power_domains(dev);
7874 static int haswell_crtc_mode_set(struct intel_crtc *crtc,
7876 struct drm_framebuffer *fb)
7878 if (!intel_ddi_pll_select(crtc))
7881 crtc->lowfreq_avail = false;
7886 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7888 struct intel_crtc_config *pipe_config)
7890 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7892 switch (pipe_config->ddi_pll_sel) {
7893 case PORT_CLK_SEL_WRPLL1:
7894 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7896 case PORT_CLK_SEL_WRPLL2:
7897 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7902 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7903 struct intel_crtc_config *pipe_config)
7905 struct drm_device *dev = crtc->base.dev;
7906 struct drm_i915_private *dev_priv = dev->dev_private;
7907 struct intel_shared_dpll *pll;
7911 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7913 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7915 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7917 if (pipe_config->shared_dpll >= 0) {
7918 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7920 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7921 &pipe_config->dpll_hw_state));
7925 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7926 * DDI E. So just check whether this pipe is wired to DDI E and whether
7927 * the PCH transcoder is on.
7929 if (INTEL_INFO(dev)->gen < 9 &&
7930 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7931 pipe_config->has_pch_encoder = true;
7933 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7934 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7935 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7937 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7941 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7942 struct intel_crtc_config *pipe_config)
7944 struct drm_device *dev = crtc->base.dev;
7945 struct drm_i915_private *dev_priv = dev->dev_private;
7946 enum intel_display_power_domain pfit_domain;
7949 if (!intel_display_power_is_enabled(dev_priv,
7950 POWER_DOMAIN_PIPE(crtc->pipe)))
7953 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7954 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7956 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7957 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7958 enum pipe trans_edp_pipe;
7959 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7961 WARN(1, "unknown pipe linked to edp transcoder\n");
7962 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7963 case TRANS_DDI_EDP_INPUT_A_ON:
7964 trans_edp_pipe = PIPE_A;
7966 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7967 trans_edp_pipe = PIPE_B;
7969 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7970 trans_edp_pipe = PIPE_C;
7974 if (trans_edp_pipe == crtc->pipe)
7975 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7978 if (!intel_display_power_is_enabled(dev_priv,
7979 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7982 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7983 if (!(tmp & PIPECONF_ENABLE))
7986 haswell_get_ddi_port_state(crtc, pipe_config);
7988 intel_get_pipe_timings(crtc, pipe_config);
7990 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7991 if (intel_display_power_is_enabled(dev_priv, pfit_domain))
7992 ironlake_get_pfit_config(crtc, pipe_config);
7994 if (IS_HASWELL(dev))
7995 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7996 (I915_READ(IPS_CTL) & IPS_ENABLE);
7998 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
7999 pipe_config->pixel_multiplier =
8000 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8002 pipe_config->pixel_multiplier = 1;
8008 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8010 struct drm_device *dev = crtc->dev;
8011 struct drm_i915_private *dev_priv = dev->dev_private;
8012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8013 uint32_t cntl = 0, size = 0;
8016 unsigned int width = intel_crtc->cursor_width;
8017 unsigned int height = intel_crtc->cursor_height;
8018 unsigned int stride = roundup_pow_of_two(width) * 4;
8022 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8033 cntl |= CURSOR_ENABLE |
8034 CURSOR_GAMMA_ENABLE |
8035 CURSOR_FORMAT_ARGB |
8036 CURSOR_STRIDE(stride);
8038 size = (height << 12) | width;
8041 if (intel_crtc->cursor_cntl != 0 &&
8042 (intel_crtc->cursor_base != base ||
8043 intel_crtc->cursor_size != size ||
8044 intel_crtc->cursor_cntl != cntl)) {
8045 /* On these chipsets we can only modify the base/size/stride
8046 * whilst the cursor is disabled.
8048 I915_WRITE(_CURACNTR, 0);
8049 POSTING_READ(_CURACNTR);
8050 intel_crtc->cursor_cntl = 0;
8053 if (intel_crtc->cursor_base != base) {
8054 I915_WRITE(_CURABASE, base);
8055 intel_crtc->cursor_base = base;
8058 if (intel_crtc->cursor_size != size) {
8059 I915_WRITE(CURSIZE, size);
8060 intel_crtc->cursor_size = size;
8063 if (intel_crtc->cursor_cntl != cntl) {
8064 I915_WRITE(_CURACNTR, cntl);
8065 POSTING_READ(_CURACNTR);
8066 intel_crtc->cursor_cntl = cntl;
8070 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8072 struct drm_device *dev = crtc->dev;
8073 struct drm_i915_private *dev_priv = dev->dev_private;
8074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8075 int pipe = intel_crtc->pipe;
8080 cntl = MCURSOR_GAMMA_ENABLE;
8081 switch (intel_crtc->cursor_width) {
8083 cntl |= CURSOR_MODE_64_ARGB_AX;
8086 cntl |= CURSOR_MODE_128_ARGB_AX;
8089 cntl |= CURSOR_MODE_256_ARGB_AX;
8095 cntl |= pipe << 28; /* Connect to correct pipe */
8097 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8098 cntl |= CURSOR_PIPE_CSC_ENABLE;
8101 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8102 cntl |= CURSOR_ROTATE_180;
8104 if (intel_crtc->cursor_cntl != cntl) {
8105 I915_WRITE(CURCNTR(pipe), cntl);
8106 POSTING_READ(CURCNTR(pipe));
8107 intel_crtc->cursor_cntl = cntl;
8110 /* and commit changes on next vblank */
8111 I915_WRITE(CURBASE(pipe), base);
8112 POSTING_READ(CURBASE(pipe));
8114 intel_crtc->cursor_base = base;
8117 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8118 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8121 struct drm_device *dev = crtc->dev;
8122 struct drm_i915_private *dev_priv = dev->dev_private;
8123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8124 int pipe = intel_crtc->pipe;
8125 int x = crtc->cursor_x;
8126 int y = crtc->cursor_y;
8127 u32 base = 0, pos = 0;
8130 base = intel_crtc->cursor_addr;
8132 if (x >= intel_crtc->config.pipe_src_w)
8135 if (y >= intel_crtc->config.pipe_src_h)
8139 if (x + intel_crtc->cursor_width <= 0)
8142 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8145 pos |= x << CURSOR_X_SHIFT;
8148 if (y + intel_crtc->cursor_height <= 0)
8151 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8154 pos |= y << CURSOR_Y_SHIFT;
8156 if (base == 0 && intel_crtc->cursor_base == 0)
8159 I915_WRITE(CURPOS(pipe), pos);
8161 /* ILK+ do this automagically */
8162 if (HAS_GMCH_DISPLAY(dev) &&
8163 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8164 base += (intel_crtc->cursor_height *
8165 intel_crtc->cursor_width - 1) * 4;
8168 if (IS_845G(dev) || IS_I865G(dev))
8169 i845_update_cursor(crtc, base);
8171 i9xx_update_cursor(crtc, base);
8174 static bool cursor_size_ok(struct drm_device *dev,
8175 uint32_t width, uint32_t height)
8177 if (width == 0 || height == 0)
8181 * 845g/865g are special in that they are only limited by
8182 * the width of their cursors, the height is arbitrary up to
8183 * the precision of the register. Everything else requires
8184 * square cursors, limited to a few power-of-two sizes.
8186 if (IS_845G(dev) || IS_I865G(dev)) {
8187 if ((width & 63) != 0)
8190 if (width > (IS_845G(dev) ? 64 : 512))
8196 switch (width | height) {
8211 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8212 struct drm_i915_gem_object *obj,
8213 uint32_t width, uint32_t height)
8215 struct drm_device *dev = crtc->dev;
8216 struct drm_i915_private *dev_priv = dev->dev_private;
8217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8218 enum pipe pipe = intel_crtc->pipe;
8223 /* if we want to turn off the cursor ignore width and height */
8225 DRM_DEBUG_KMS("cursor off\n");
8227 mutex_lock(&dev->struct_mutex);
8231 /* we only need to pin inside GTT if cursor is non-phy */
8232 mutex_lock(&dev->struct_mutex);
8233 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8237 * Global gtt pte registers are special registers which actually
8238 * forward writes to a chunk of system memory. Which means that
8239 * there is no risk that the register values disappear as soon
8240 * as we call intel_runtime_pm_put(), so it is correct to wrap
8241 * only the pin/unpin/fence and not more.
8243 intel_runtime_pm_get(dev_priv);
8245 /* Note that the w/a also requires 2 PTE of padding following
8246 * the bo. We currently fill all unused PTE with the shadow
8247 * page and so we should always have valid PTE following the
8248 * cursor preventing the VT-d warning.
8251 if (need_vtd_wa(dev))
8252 alignment = 64*1024;
8254 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8256 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8257 intel_runtime_pm_put(dev_priv);
8261 ret = i915_gem_object_put_fence(obj);
8263 DRM_DEBUG_KMS("failed to release fence for cursor");
8264 intel_runtime_pm_put(dev_priv);
8268 addr = i915_gem_obj_ggtt_offset(obj);
8270 intel_runtime_pm_put(dev_priv);
8272 int align = IS_I830(dev) ? 16 * 1024 : 256;
8273 ret = i915_gem_object_attach_phys(obj, align);
8275 DRM_DEBUG_KMS("failed to attach phys object\n");
8278 addr = obj->phys_handle->busaddr;
8282 if (intel_crtc->cursor_bo) {
8283 if (!INTEL_INFO(dev)->cursor_needs_physical)
8284 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8287 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8288 INTEL_FRONTBUFFER_CURSOR(pipe));
8289 mutex_unlock(&dev->struct_mutex);
8291 old_width = intel_crtc->cursor_width;
8293 intel_crtc->cursor_addr = addr;
8294 intel_crtc->cursor_bo = obj;
8295 intel_crtc->cursor_width = width;
8296 intel_crtc->cursor_height = height;
8298 if (intel_crtc->active) {
8299 if (old_width != width)
8300 intel_update_watermarks(crtc);
8301 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8303 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8308 i915_gem_object_unpin_from_display_plane(obj);
8310 mutex_unlock(&dev->struct_mutex);
8314 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8315 u16 *blue, uint32_t start, uint32_t size)
8317 int end = (start + size > 256) ? 256 : start + size, i;
8318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8320 for (i = start; i < end; i++) {
8321 intel_crtc->lut_r[i] = red[i] >> 8;
8322 intel_crtc->lut_g[i] = green[i] >> 8;
8323 intel_crtc->lut_b[i] = blue[i] >> 8;
8326 intel_crtc_load_lut(crtc);
8329 /* VESA 640x480x72Hz mode to set on the pipe */
8330 static struct drm_display_mode load_detect_mode = {
8331 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8332 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8335 struct drm_framebuffer *
8336 __intel_framebuffer_create(struct drm_device *dev,
8337 struct drm_mode_fb_cmd2 *mode_cmd,
8338 struct drm_i915_gem_object *obj)
8340 struct intel_framebuffer *intel_fb;
8343 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8345 drm_gem_object_unreference_unlocked(&obj->base);
8346 return ERR_PTR(-ENOMEM);
8349 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8353 return &intel_fb->base;
8355 drm_gem_object_unreference_unlocked(&obj->base);
8358 return ERR_PTR(ret);
8361 static struct drm_framebuffer *
8362 intel_framebuffer_create(struct drm_device *dev,
8363 struct drm_mode_fb_cmd2 *mode_cmd,
8364 struct drm_i915_gem_object *obj)
8366 struct drm_framebuffer *fb;
8369 ret = i915_mutex_lock_interruptible(dev);
8371 return ERR_PTR(ret);
8372 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8373 mutex_unlock(&dev->struct_mutex);
8379 intel_framebuffer_pitch_for_width(int width, int bpp)
8381 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8382 return ALIGN(pitch, 64);
8386 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8388 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8389 return PAGE_ALIGN(pitch * mode->vdisplay);
8392 static struct drm_framebuffer *
8393 intel_framebuffer_create_for_mode(struct drm_device *dev,
8394 struct drm_display_mode *mode,
8397 struct drm_i915_gem_object *obj;
8398 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8400 obj = i915_gem_alloc_object(dev,
8401 intel_framebuffer_size_for_mode(mode, bpp));
8403 return ERR_PTR(-ENOMEM);
8405 mode_cmd.width = mode->hdisplay;
8406 mode_cmd.height = mode->vdisplay;
8407 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8409 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8411 return intel_framebuffer_create(dev, &mode_cmd, obj);
8414 static struct drm_framebuffer *
8415 mode_fits_in_fbdev(struct drm_device *dev,
8416 struct drm_display_mode *mode)
8418 #ifdef CONFIG_DRM_I915_FBDEV
8419 struct drm_i915_private *dev_priv = dev->dev_private;
8420 struct drm_i915_gem_object *obj;
8421 struct drm_framebuffer *fb;
8423 if (!dev_priv->fbdev)
8426 if (!dev_priv->fbdev->fb)
8429 obj = dev_priv->fbdev->fb->obj;
8432 fb = &dev_priv->fbdev->fb->base;
8433 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8434 fb->bits_per_pixel))
8437 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8446 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8447 struct drm_display_mode *mode,
8448 struct intel_load_detect_pipe *old,
8449 struct drm_modeset_acquire_ctx *ctx)
8451 struct intel_crtc *intel_crtc;
8452 struct intel_encoder *intel_encoder =
8453 intel_attached_encoder(connector);
8454 struct drm_crtc *possible_crtc;
8455 struct drm_encoder *encoder = &intel_encoder->base;
8456 struct drm_crtc *crtc = NULL;
8457 struct drm_device *dev = encoder->dev;
8458 struct drm_framebuffer *fb;
8459 struct drm_mode_config *config = &dev->mode_config;
8462 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8463 connector->base.id, connector->name,
8464 encoder->base.id, encoder->name);
8467 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8472 * Algorithm gets a little messy:
8474 * - if the connector already has an assigned crtc, use it (but make
8475 * sure it's on first)
8477 * - try to find the first unused crtc that can drive this connector,
8478 * and use that if we find one
8481 /* See if we already have a CRTC for this connector */
8482 if (encoder->crtc) {
8483 crtc = encoder->crtc;
8485 ret = drm_modeset_lock(&crtc->mutex, ctx);
8489 old->dpms_mode = connector->dpms;
8490 old->load_detect_temp = false;
8492 /* Make sure the crtc and connector are running */
8493 if (connector->dpms != DRM_MODE_DPMS_ON)
8494 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8499 /* Find an unused one (if possible) */
8500 for_each_crtc(dev, possible_crtc) {
8502 if (!(encoder->possible_crtcs & (1 << i)))
8504 if (possible_crtc->enabled)
8506 /* This can occur when applying the pipe A quirk on resume. */
8507 if (to_intel_crtc(possible_crtc)->new_enabled)
8510 crtc = possible_crtc;
8515 * If we didn't find an unused CRTC, don't use any.
8518 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8522 ret = drm_modeset_lock(&crtc->mutex, ctx);
8525 intel_encoder->new_crtc = to_intel_crtc(crtc);
8526 to_intel_connector(connector)->new_encoder = intel_encoder;
8528 intel_crtc = to_intel_crtc(crtc);
8529 intel_crtc->new_enabled = true;
8530 intel_crtc->new_config = &intel_crtc->config;
8531 old->dpms_mode = connector->dpms;
8532 old->load_detect_temp = true;
8533 old->release_fb = NULL;
8536 mode = &load_detect_mode;
8538 /* We need a framebuffer large enough to accommodate all accesses
8539 * that the plane may generate whilst we perform load detection.
8540 * We can not rely on the fbcon either being present (we get called
8541 * during its initialisation to detect all boot displays, or it may
8542 * not even exist) or that it is large enough to satisfy the
8545 fb = mode_fits_in_fbdev(dev, mode);
8547 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8548 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8549 old->release_fb = fb;
8551 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8553 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8557 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8558 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8559 if (old->release_fb)
8560 old->release_fb->funcs->destroy(old->release_fb);
8564 /* let the connector get through one full cycle before testing */
8565 intel_wait_for_vblank(dev, intel_crtc->pipe);
8569 intel_crtc->new_enabled = crtc->enabled;
8570 if (intel_crtc->new_enabled)
8571 intel_crtc->new_config = &intel_crtc->config;
8573 intel_crtc->new_config = NULL;
8575 if (ret == -EDEADLK) {
8576 drm_modeset_backoff(ctx);
8583 void intel_release_load_detect_pipe(struct drm_connector *connector,
8584 struct intel_load_detect_pipe *old)
8586 struct intel_encoder *intel_encoder =
8587 intel_attached_encoder(connector);
8588 struct drm_encoder *encoder = &intel_encoder->base;
8589 struct drm_crtc *crtc = encoder->crtc;
8590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8592 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8593 connector->base.id, connector->name,
8594 encoder->base.id, encoder->name);
8596 if (old->load_detect_temp) {
8597 to_intel_connector(connector)->new_encoder = NULL;
8598 intel_encoder->new_crtc = NULL;
8599 intel_crtc->new_enabled = false;
8600 intel_crtc->new_config = NULL;
8601 intel_set_mode(crtc, NULL, 0, 0, NULL);
8603 if (old->release_fb) {
8604 drm_framebuffer_unregister_private(old->release_fb);
8605 drm_framebuffer_unreference(old->release_fb);
8611 /* Switch crtc and encoder back off if necessary */
8612 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8613 connector->funcs->dpms(connector, old->dpms_mode);
8616 static int i9xx_pll_refclk(struct drm_device *dev,
8617 const struct intel_crtc_config *pipe_config)
8619 struct drm_i915_private *dev_priv = dev->dev_private;
8620 u32 dpll = pipe_config->dpll_hw_state.dpll;
8622 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8623 return dev_priv->vbt.lvds_ssc_freq;
8624 else if (HAS_PCH_SPLIT(dev))
8626 else if (!IS_GEN2(dev))
8632 /* Returns the clock of the currently programmed mode of the given pipe. */
8633 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8634 struct intel_crtc_config *pipe_config)
8636 struct drm_device *dev = crtc->base.dev;
8637 struct drm_i915_private *dev_priv = dev->dev_private;
8638 int pipe = pipe_config->cpu_transcoder;
8639 u32 dpll = pipe_config->dpll_hw_state.dpll;
8641 intel_clock_t clock;
8642 int refclk = i9xx_pll_refclk(dev, pipe_config);
8644 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8645 fp = pipe_config->dpll_hw_state.fp0;
8647 fp = pipe_config->dpll_hw_state.fp1;
8649 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8650 if (IS_PINEVIEW(dev)) {
8651 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8652 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8654 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8655 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8658 if (!IS_GEN2(dev)) {
8659 if (IS_PINEVIEW(dev))
8660 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8661 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8663 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8664 DPLL_FPA01_P1_POST_DIV_SHIFT);
8666 switch (dpll & DPLL_MODE_MASK) {
8667 case DPLLB_MODE_DAC_SERIAL:
8668 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8671 case DPLLB_MODE_LVDS:
8672 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8676 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8677 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8681 if (IS_PINEVIEW(dev))
8682 pineview_clock(refclk, &clock);
8684 i9xx_clock(refclk, &clock);
8686 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8687 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8690 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8691 DPLL_FPA01_P1_POST_DIV_SHIFT);
8693 if (lvds & LVDS_CLKB_POWER_UP)
8698 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8701 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8702 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8704 if (dpll & PLL_P2_DIVIDE_BY_4)
8710 i9xx_clock(refclk, &clock);
8714 * This value includes pixel_multiplier. We will use
8715 * port_clock to compute adjusted_mode.crtc_clock in the
8716 * encoder's get_config() function.
8718 pipe_config->port_clock = clock.dot;
8721 int intel_dotclock_calculate(int link_freq,
8722 const struct intel_link_m_n *m_n)
8725 * The calculation for the data clock is:
8726 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8727 * But we want to avoid losing precison if possible, so:
8728 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8730 * and the link clock is simpler:
8731 * link_clock = (m * link_clock) / n
8737 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8740 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8741 struct intel_crtc_config *pipe_config)
8743 struct drm_device *dev = crtc->base.dev;
8745 /* read out port_clock from the DPLL */
8746 i9xx_crtc_clock_get(crtc, pipe_config);
8749 * This value does not include pixel_multiplier.
8750 * We will check that port_clock and adjusted_mode.crtc_clock
8751 * agree once we know their relationship in the encoder's
8752 * get_config() function.
8754 pipe_config->adjusted_mode.crtc_clock =
8755 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8756 &pipe_config->fdi_m_n);
8759 /** Returns the currently programmed mode of the given pipe. */
8760 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8761 struct drm_crtc *crtc)
8763 struct drm_i915_private *dev_priv = dev->dev_private;
8764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8765 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8766 struct drm_display_mode *mode;
8767 struct intel_crtc_config pipe_config;
8768 int htot = I915_READ(HTOTAL(cpu_transcoder));
8769 int hsync = I915_READ(HSYNC(cpu_transcoder));
8770 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8771 int vsync = I915_READ(VSYNC(cpu_transcoder));
8772 enum pipe pipe = intel_crtc->pipe;
8774 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8779 * Construct a pipe_config sufficient for getting the clock info
8780 * back out of crtc_clock_get.
8782 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8783 * to use a real value here instead.
8785 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8786 pipe_config.pixel_multiplier = 1;
8787 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8788 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8789 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8790 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8792 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8793 mode->hdisplay = (htot & 0xffff) + 1;
8794 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8795 mode->hsync_start = (hsync & 0xffff) + 1;
8796 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8797 mode->vdisplay = (vtot & 0xffff) + 1;
8798 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8799 mode->vsync_start = (vsync & 0xffff) + 1;
8800 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8802 drm_mode_set_name(mode);
8807 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8809 struct drm_device *dev = crtc->dev;
8810 struct drm_i915_private *dev_priv = dev->dev_private;
8811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8813 if (!HAS_GMCH_DISPLAY(dev))
8816 if (!dev_priv->lvds_downclock_avail)
8820 * Since this is called by a timer, we should never get here in
8823 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8824 int pipe = intel_crtc->pipe;
8825 int dpll_reg = DPLL(pipe);
8828 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8830 assert_panel_unlocked(dev_priv, pipe);
8832 dpll = I915_READ(dpll_reg);
8833 dpll |= DISPLAY_RATE_SELECT_FPA1;
8834 I915_WRITE(dpll_reg, dpll);
8835 intel_wait_for_vblank(dev, pipe);
8836 dpll = I915_READ(dpll_reg);
8837 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8838 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8843 void intel_mark_busy(struct drm_device *dev)
8845 struct drm_i915_private *dev_priv = dev->dev_private;
8847 if (dev_priv->mm.busy)
8850 intel_runtime_pm_get(dev_priv);
8851 i915_update_gfx_val(dev_priv);
8852 dev_priv->mm.busy = true;
8855 void intel_mark_idle(struct drm_device *dev)
8857 struct drm_i915_private *dev_priv = dev->dev_private;
8858 struct drm_crtc *crtc;
8860 if (!dev_priv->mm.busy)
8863 dev_priv->mm.busy = false;
8865 if (!i915.powersave)
8868 for_each_crtc(dev, crtc) {
8869 if (!crtc->primary->fb)
8872 intel_decrease_pllclock(crtc);
8875 if (INTEL_INFO(dev)->gen >= 6)
8876 gen6_rps_idle(dev->dev_private);
8879 intel_runtime_pm_put(dev_priv);
8882 static void intel_crtc_destroy(struct drm_crtc *crtc)
8884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8885 struct drm_device *dev = crtc->dev;
8886 struct intel_unpin_work *work;
8888 spin_lock_irq(&dev->event_lock);
8889 work = intel_crtc->unpin_work;
8890 intel_crtc->unpin_work = NULL;
8891 spin_unlock_irq(&dev->event_lock);
8894 cancel_work_sync(&work->work);
8898 drm_crtc_cleanup(crtc);
8903 static void intel_unpin_work_fn(struct work_struct *__work)
8905 struct intel_unpin_work *work =
8906 container_of(__work, struct intel_unpin_work, work);
8907 struct drm_device *dev = work->crtc->dev;
8908 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8910 mutex_lock(&dev->struct_mutex);
8911 intel_unpin_fb_obj(work->old_fb_obj);
8912 drm_gem_object_unreference(&work->pending_flip_obj->base);
8913 drm_gem_object_unreference(&work->old_fb_obj->base);
8915 intel_update_fbc(dev);
8916 mutex_unlock(&dev->struct_mutex);
8918 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8920 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8921 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8926 static void do_intel_finish_page_flip(struct drm_device *dev,
8927 struct drm_crtc *crtc)
8929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8930 struct intel_unpin_work *work;
8931 unsigned long flags;
8933 /* Ignore early vblank irqs */
8934 if (intel_crtc == NULL)
8938 * This is called both by irq handlers and the reset code (to complete
8939 * lost pageflips) so needs the full irqsave spinlocks.
8941 spin_lock_irqsave(&dev->event_lock, flags);
8942 work = intel_crtc->unpin_work;
8944 /* Ensure we don't miss a work->pending update ... */
8947 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8948 spin_unlock_irqrestore(&dev->event_lock, flags);
8952 page_flip_completed(intel_crtc);
8954 spin_unlock_irqrestore(&dev->event_lock, flags);
8957 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8959 struct drm_i915_private *dev_priv = dev->dev_private;
8960 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8962 do_intel_finish_page_flip(dev, crtc);
8965 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8967 struct drm_i915_private *dev_priv = dev->dev_private;
8968 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8970 do_intel_finish_page_flip(dev, crtc);
8973 /* Is 'a' after or equal to 'b'? */
8974 static bool g4x_flip_count_after_eq(u32 a, u32 b)
8976 return !((a - b) & 0x80000000);
8979 static bool page_flip_finished(struct intel_crtc *crtc)
8981 struct drm_device *dev = crtc->base.dev;
8982 struct drm_i915_private *dev_priv = dev->dev_private;
8985 * The relevant registers doen't exist on pre-ctg.
8986 * As the flip done interrupt doesn't trigger for mmio
8987 * flips on gmch platforms, a flip count check isn't
8988 * really needed there. But since ctg has the registers,
8989 * include it in the check anyway.
8991 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
8995 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8996 * used the same base address. In that case the mmio flip might
8997 * have completed, but the CS hasn't even executed the flip yet.
8999 * A flip count check isn't enough as the CS might have updated
9000 * the base address just after start of vblank, but before we
9001 * managed to process the interrupt. This means we'd complete the
9004 * Combining both checks should get us a good enough result. It may
9005 * still happen that the CS flip has been executed, but has not
9006 * yet actually completed. But in case the base address is the same
9007 * anyway, we don't really care.
9009 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9010 crtc->unpin_work->gtt_offset &&
9011 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9012 crtc->unpin_work->flip_count);
9015 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9017 struct drm_i915_private *dev_priv = dev->dev_private;
9018 struct intel_crtc *intel_crtc =
9019 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9020 unsigned long flags;
9024 * This is called both by irq handlers and the reset code (to complete
9025 * lost pageflips) so needs the full irqsave spinlocks.
9027 * NB: An MMIO update of the plane base pointer will also
9028 * generate a page-flip completion irq, i.e. every modeset
9029 * is also accompanied by a spurious intel_prepare_page_flip().
9031 spin_lock_irqsave(&dev->event_lock, flags);
9032 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9033 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9034 spin_unlock_irqrestore(&dev->event_lock, flags);
9037 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9039 /* Ensure that the work item is consistent when activating it ... */
9041 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9042 /* and that it is marked active as soon as the irq could fire. */
9046 static int intel_gen2_queue_flip(struct drm_device *dev,
9047 struct drm_crtc *crtc,
9048 struct drm_framebuffer *fb,
9049 struct drm_i915_gem_object *obj,
9050 struct intel_engine_cs *ring,
9053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9057 ret = intel_ring_begin(ring, 6);
9061 /* Can't queue multiple flips, so wait for the previous
9062 * one to finish before executing the next.
9064 if (intel_crtc->plane)
9065 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9067 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9068 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9069 intel_ring_emit(ring, MI_NOOP);
9070 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9071 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9072 intel_ring_emit(ring, fb->pitches[0]);
9073 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9074 intel_ring_emit(ring, 0); /* aux display base address, unused */
9076 intel_mark_page_flip_active(intel_crtc);
9077 __intel_ring_advance(ring);
9081 static int intel_gen3_queue_flip(struct drm_device *dev,
9082 struct drm_crtc *crtc,
9083 struct drm_framebuffer *fb,
9084 struct drm_i915_gem_object *obj,
9085 struct intel_engine_cs *ring,
9088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9092 ret = intel_ring_begin(ring, 6);
9096 if (intel_crtc->plane)
9097 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9099 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9100 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9101 intel_ring_emit(ring, MI_NOOP);
9102 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9103 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9104 intel_ring_emit(ring, fb->pitches[0]);
9105 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9106 intel_ring_emit(ring, MI_NOOP);
9108 intel_mark_page_flip_active(intel_crtc);
9109 __intel_ring_advance(ring);
9113 static int intel_gen4_queue_flip(struct drm_device *dev,
9114 struct drm_crtc *crtc,
9115 struct drm_framebuffer *fb,
9116 struct drm_i915_gem_object *obj,
9117 struct intel_engine_cs *ring,
9120 struct drm_i915_private *dev_priv = dev->dev_private;
9121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9122 uint32_t pf, pipesrc;
9125 ret = intel_ring_begin(ring, 4);
9129 /* i965+ uses the linear or tiled offsets from the
9130 * Display Registers (which do not change across a page-flip)
9131 * so we need only reprogram the base address.
9133 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9134 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9135 intel_ring_emit(ring, fb->pitches[0]);
9136 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9139 /* XXX Enabling the panel-fitter across page-flip is so far
9140 * untested on non-native modes, so ignore it for now.
9141 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9144 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9145 intel_ring_emit(ring, pf | pipesrc);
9147 intel_mark_page_flip_active(intel_crtc);
9148 __intel_ring_advance(ring);
9152 static int intel_gen6_queue_flip(struct drm_device *dev,
9153 struct drm_crtc *crtc,
9154 struct drm_framebuffer *fb,
9155 struct drm_i915_gem_object *obj,
9156 struct intel_engine_cs *ring,
9159 struct drm_i915_private *dev_priv = dev->dev_private;
9160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9161 uint32_t pf, pipesrc;
9164 ret = intel_ring_begin(ring, 4);
9168 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9169 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9170 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9171 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9173 /* Contrary to the suggestions in the documentation,
9174 * "Enable Panel Fitter" does not seem to be required when page
9175 * flipping with a non-native mode, and worse causes a normal
9177 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9180 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9181 intel_ring_emit(ring, pf | pipesrc);
9183 intel_mark_page_flip_active(intel_crtc);
9184 __intel_ring_advance(ring);
9188 static int intel_gen7_queue_flip(struct drm_device *dev,
9189 struct drm_crtc *crtc,
9190 struct drm_framebuffer *fb,
9191 struct drm_i915_gem_object *obj,
9192 struct intel_engine_cs *ring,
9195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9196 uint32_t plane_bit = 0;
9199 switch (intel_crtc->plane) {
9201 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9204 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9207 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9210 WARN_ONCE(1, "unknown plane in flip command\n");
9215 if (ring->id == RCS) {
9218 * On Gen 8, SRM is now taking an extra dword to accommodate
9219 * 48bits addresses, and we need a NOOP for the batch size to
9227 * BSpec MI_DISPLAY_FLIP for IVB:
9228 * "The full packet must be contained within the same cache line."
9230 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9231 * cacheline, if we ever start emitting more commands before
9232 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9233 * then do the cacheline alignment, and finally emit the
9236 ret = intel_ring_cacheline_align(ring);
9240 ret = intel_ring_begin(ring, len);
9244 /* Unmask the flip-done completion message. Note that the bspec says that
9245 * we should do this for both the BCS and RCS, and that we must not unmask
9246 * more than one flip event at any time (or ensure that one flip message
9247 * can be sent by waiting for flip-done prior to queueing new flips).
9248 * Experimentation says that BCS works despite DERRMR masking all
9249 * flip-done completion events and that unmasking all planes at once
9250 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9251 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9253 if (ring->id == RCS) {
9254 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9255 intel_ring_emit(ring, DERRMR);
9256 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9257 DERRMR_PIPEB_PRI_FLIP_DONE |
9258 DERRMR_PIPEC_PRI_FLIP_DONE));
9260 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9261 MI_SRM_LRM_GLOBAL_GTT);
9263 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9264 MI_SRM_LRM_GLOBAL_GTT);
9265 intel_ring_emit(ring, DERRMR);
9266 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9268 intel_ring_emit(ring, 0);
9269 intel_ring_emit(ring, MI_NOOP);
9273 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9274 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9275 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9276 intel_ring_emit(ring, (MI_NOOP));
9278 intel_mark_page_flip_active(intel_crtc);
9279 __intel_ring_advance(ring);
9283 static bool use_mmio_flip(struct intel_engine_cs *ring,
9284 struct drm_i915_gem_object *obj)
9287 * This is not being used for older platforms, because
9288 * non-availability of flip done interrupt forces us to use
9289 * CS flips. Older platforms derive flip done using some clever
9290 * tricks involving the flip_pending status bits and vblank irqs.
9291 * So using MMIO flips there would disrupt this mechanism.
9297 if (INTEL_INFO(ring->dev)->gen < 5)
9300 if (i915.use_mmio_flip < 0)
9302 else if (i915.use_mmio_flip > 0)
9304 else if (i915.enable_execlists)
9307 return ring != obj->ring;
9310 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9312 struct drm_device *dev = intel_crtc->base.dev;
9313 struct drm_i915_private *dev_priv = dev->dev_private;
9314 struct intel_framebuffer *intel_fb =
9315 to_intel_framebuffer(intel_crtc->base.primary->fb);
9316 struct drm_i915_gem_object *obj = intel_fb->obj;
9320 intel_mark_page_flip_active(intel_crtc);
9322 reg = DSPCNTR(intel_crtc->plane);
9323 dspcntr = I915_READ(reg);
9325 if (obj->tiling_mode != I915_TILING_NONE)
9326 dspcntr |= DISPPLANE_TILED;
9328 dspcntr &= ~DISPPLANE_TILED;
9330 I915_WRITE(reg, dspcntr);
9332 I915_WRITE(DSPSURF(intel_crtc->plane),
9333 intel_crtc->unpin_work->gtt_offset);
9334 POSTING_READ(DSPSURF(intel_crtc->plane));
9337 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9339 struct intel_engine_cs *ring;
9342 lockdep_assert_held(&obj->base.dev->struct_mutex);
9344 if (!obj->last_write_seqno)
9349 if (i915_seqno_passed(ring->get_seqno(ring, true),
9350 obj->last_write_seqno))
9353 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9357 if (WARN_ON(!ring->irq_get(ring)))
9363 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9365 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9366 struct intel_crtc *intel_crtc;
9367 unsigned long irq_flags;
9370 seqno = ring->get_seqno(ring, false);
9372 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9373 for_each_intel_crtc(ring->dev, intel_crtc) {
9374 struct intel_mmio_flip *mmio_flip;
9376 mmio_flip = &intel_crtc->mmio_flip;
9377 if (mmio_flip->seqno == 0)
9380 if (ring->id != mmio_flip->ring_id)
9383 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9384 intel_do_mmio_flip(intel_crtc);
9385 mmio_flip->seqno = 0;
9386 ring->irq_put(ring);
9389 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9392 static int intel_queue_mmio_flip(struct drm_device *dev,
9393 struct drm_crtc *crtc,
9394 struct drm_framebuffer *fb,
9395 struct drm_i915_gem_object *obj,
9396 struct intel_engine_cs *ring,
9399 struct drm_i915_private *dev_priv = dev->dev_private;
9400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9403 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9406 ret = intel_postpone_flip(obj);
9410 intel_do_mmio_flip(intel_crtc);
9414 spin_lock_irq(&dev_priv->mmio_flip_lock);
9415 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9416 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9417 spin_unlock_irq(&dev_priv->mmio_flip_lock);
9420 * Double check to catch cases where irq fired before
9421 * mmio flip data was ready
9423 intel_notify_mmio_flip(obj->ring);
9427 static int intel_default_queue_flip(struct drm_device *dev,
9428 struct drm_crtc *crtc,
9429 struct drm_framebuffer *fb,
9430 struct drm_i915_gem_object *obj,
9431 struct intel_engine_cs *ring,
9437 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9438 struct drm_crtc *crtc)
9440 struct drm_i915_private *dev_priv = dev->dev_private;
9441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9442 struct intel_unpin_work *work = intel_crtc->unpin_work;
9445 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9448 if (!work->enable_stall_check)
9451 if (work->flip_ready_vblank == 0) {
9452 if (work->flip_queued_ring &&
9453 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9454 work->flip_queued_seqno))
9457 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9460 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9463 /* Potential stall - if we see that the flip has happened,
9464 * assume a missed interrupt. */
9465 if (INTEL_INFO(dev)->gen >= 4)
9466 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9468 addr = I915_READ(DSPADDR(intel_crtc->plane));
9470 /* There is a potential issue here with a false positive after a flip
9471 * to the same address. We could address this by checking for a
9472 * non-incrementing frame counter.
9474 return addr == work->gtt_offset;
9477 void intel_check_page_flip(struct drm_device *dev, int pipe)
9479 struct drm_i915_private *dev_priv = dev->dev_private;
9480 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9488 spin_lock(&dev->event_lock);
9489 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9490 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9491 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9492 page_flip_completed(intel_crtc);
9494 spin_unlock(&dev->event_lock);
9497 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9498 struct drm_framebuffer *fb,
9499 struct drm_pending_vblank_event *event,
9500 uint32_t page_flip_flags)
9502 struct drm_device *dev = crtc->dev;
9503 struct drm_i915_private *dev_priv = dev->dev_private;
9504 struct drm_framebuffer *old_fb = crtc->primary->fb;
9505 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9507 enum pipe pipe = intel_crtc->pipe;
9508 struct intel_unpin_work *work;
9509 struct intel_engine_cs *ring;
9513 * drm_mode_page_flip_ioctl() should already catch this, but double
9514 * check to be safe. In the future we may enable pageflipping from
9515 * a disabled primary plane.
9517 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9520 /* Can't change pixel format via MI display flips. */
9521 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9525 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9526 * Note that pitch changes could also affect these register.
9528 if (INTEL_INFO(dev)->gen > 3 &&
9529 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9530 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9533 if (i915_terminally_wedged(&dev_priv->gpu_error))
9536 work = kzalloc(sizeof(*work), GFP_KERNEL);
9540 work->event = event;
9542 work->old_fb_obj = intel_fb_obj(old_fb);
9543 INIT_WORK(&work->work, intel_unpin_work_fn);
9545 ret = drm_crtc_vblank_get(crtc);
9549 /* We borrow the event spin lock for protecting unpin_work */
9550 spin_lock_irq(&dev->event_lock);
9551 if (intel_crtc->unpin_work) {
9552 /* Before declaring the flip queue wedged, check if
9553 * the hardware completed the operation behind our backs.
9555 if (__intel_pageflip_stall_check(dev, crtc)) {
9556 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9557 page_flip_completed(intel_crtc);
9559 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9560 spin_unlock_irq(&dev->event_lock);
9562 drm_crtc_vblank_put(crtc);
9567 intel_crtc->unpin_work = work;
9568 spin_unlock_irq(&dev->event_lock);
9570 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9571 flush_workqueue(dev_priv->wq);
9573 ret = i915_mutex_lock_interruptible(dev);
9577 /* Reference the objects for the scheduled work. */
9578 drm_gem_object_reference(&work->old_fb_obj->base);
9579 drm_gem_object_reference(&obj->base);
9581 crtc->primary->fb = fb;
9583 work->pending_flip_obj = obj;
9585 atomic_inc(&intel_crtc->unpin_work_count);
9586 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9588 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9589 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9591 if (IS_VALLEYVIEW(dev)) {
9592 ring = &dev_priv->ring[BCS];
9593 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9594 /* vlv: DISPLAY_FLIP fails to change tiling */
9596 } else if (IS_IVYBRIDGE(dev)) {
9597 ring = &dev_priv->ring[BCS];
9598 } else if (INTEL_INFO(dev)->gen >= 7) {
9600 if (ring == NULL || ring->id != RCS)
9601 ring = &dev_priv->ring[BCS];
9603 ring = &dev_priv->ring[RCS];
9606 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9608 goto cleanup_pending;
9611 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9613 if (use_mmio_flip(ring, obj)) {
9614 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9619 work->flip_queued_seqno = obj->last_write_seqno;
9620 work->flip_queued_ring = obj->ring;
9622 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9627 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9628 work->flip_queued_ring = ring;
9631 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9632 work->enable_stall_check = true;
9634 i915_gem_track_fb(work->old_fb_obj, obj,
9635 INTEL_FRONTBUFFER_PRIMARY(pipe));
9637 intel_disable_fbc(dev);
9638 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9639 mutex_unlock(&dev->struct_mutex);
9641 trace_i915_flip_request(intel_crtc->plane, obj);
9646 intel_unpin_fb_obj(obj);
9648 atomic_dec(&intel_crtc->unpin_work_count);
9649 crtc->primary->fb = old_fb;
9650 drm_gem_object_unreference(&work->old_fb_obj->base);
9651 drm_gem_object_unreference(&obj->base);
9652 mutex_unlock(&dev->struct_mutex);
9655 spin_lock_irq(&dev->event_lock);
9656 intel_crtc->unpin_work = NULL;
9657 spin_unlock_irq(&dev->event_lock);
9659 drm_crtc_vblank_put(crtc);
9665 intel_crtc_wait_for_pending_flips(crtc);
9666 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9667 if (ret == 0 && event) {
9668 spin_lock_irq(&dev->event_lock);
9669 drm_send_vblank_event(dev, pipe, event);
9670 spin_unlock_irq(&dev->event_lock);
9676 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9677 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9678 .load_lut = intel_crtc_load_lut,
9682 * intel_modeset_update_staged_output_state
9684 * Updates the staged output configuration state, e.g. after we've read out the
9687 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9689 struct intel_crtc *crtc;
9690 struct intel_encoder *encoder;
9691 struct intel_connector *connector;
9693 list_for_each_entry(connector, &dev->mode_config.connector_list,
9695 connector->new_encoder =
9696 to_intel_encoder(connector->base.encoder);
9699 for_each_intel_encoder(dev, encoder) {
9701 to_intel_crtc(encoder->base.crtc);
9704 for_each_intel_crtc(dev, crtc) {
9705 crtc->new_enabled = crtc->base.enabled;
9707 if (crtc->new_enabled)
9708 crtc->new_config = &crtc->config;
9710 crtc->new_config = NULL;
9715 * intel_modeset_commit_output_state
9717 * This function copies the stage display pipe configuration to the real one.
9719 static void intel_modeset_commit_output_state(struct drm_device *dev)
9721 struct intel_crtc *crtc;
9722 struct intel_encoder *encoder;
9723 struct intel_connector *connector;
9725 list_for_each_entry(connector, &dev->mode_config.connector_list,
9727 connector->base.encoder = &connector->new_encoder->base;
9730 for_each_intel_encoder(dev, encoder) {
9731 encoder->base.crtc = &encoder->new_crtc->base;
9734 for_each_intel_crtc(dev, crtc) {
9735 crtc->base.enabled = crtc->new_enabled;
9740 connected_sink_compute_bpp(struct intel_connector *connector,
9741 struct intel_crtc_config *pipe_config)
9743 int bpp = pipe_config->pipe_bpp;
9745 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9746 connector->base.base.id,
9747 connector->base.name);
9749 /* Don't use an invalid EDID bpc value */
9750 if (connector->base.display_info.bpc &&
9751 connector->base.display_info.bpc * 3 < bpp) {
9752 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9753 bpp, connector->base.display_info.bpc*3);
9754 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9757 /* Clamp bpp to 8 on screens without EDID 1.4 */
9758 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9759 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9761 pipe_config->pipe_bpp = 24;
9766 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9767 struct drm_framebuffer *fb,
9768 struct intel_crtc_config *pipe_config)
9770 struct drm_device *dev = crtc->base.dev;
9771 struct intel_connector *connector;
9774 switch (fb->pixel_format) {
9776 bpp = 8*3; /* since we go through a colormap */
9778 case DRM_FORMAT_XRGB1555:
9779 case DRM_FORMAT_ARGB1555:
9780 /* checked in intel_framebuffer_init already */
9781 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9783 case DRM_FORMAT_RGB565:
9784 bpp = 6*3; /* min is 18bpp */
9786 case DRM_FORMAT_XBGR8888:
9787 case DRM_FORMAT_ABGR8888:
9788 /* checked in intel_framebuffer_init already */
9789 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9791 case DRM_FORMAT_XRGB8888:
9792 case DRM_FORMAT_ARGB8888:
9795 case DRM_FORMAT_XRGB2101010:
9796 case DRM_FORMAT_ARGB2101010:
9797 case DRM_FORMAT_XBGR2101010:
9798 case DRM_FORMAT_ABGR2101010:
9799 /* checked in intel_framebuffer_init already */
9800 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9804 /* TODO: gen4+ supports 16 bpc floating point, too. */
9806 DRM_DEBUG_KMS("unsupported depth\n");
9810 pipe_config->pipe_bpp = bpp;
9812 /* Clamp display bpp to EDID value */
9813 list_for_each_entry(connector, &dev->mode_config.connector_list,
9815 if (!connector->new_encoder ||
9816 connector->new_encoder->new_crtc != crtc)
9819 connected_sink_compute_bpp(connector, pipe_config);
9825 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9827 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9828 "type: 0x%x flags: 0x%x\n",
9830 mode->crtc_hdisplay, mode->crtc_hsync_start,
9831 mode->crtc_hsync_end, mode->crtc_htotal,
9832 mode->crtc_vdisplay, mode->crtc_vsync_start,
9833 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9836 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9837 struct intel_crtc_config *pipe_config,
9838 const char *context)
9840 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9841 context, pipe_name(crtc->pipe));
9843 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9844 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9845 pipe_config->pipe_bpp, pipe_config->dither);
9846 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9847 pipe_config->has_pch_encoder,
9848 pipe_config->fdi_lanes,
9849 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9850 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9851 pipe_config->fdi_m_n.tu);
9852 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9853 pipe_config->has_dp_encoder,
9854 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9855 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9856 pipe_config->dp_m_n.tu);
9858 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9859 pipe_config->has_dp_encoder,
9860 pipe_config->dp_m2_n2.gmch_m,
9861 pipe_config->dp_m2_n2.gmch_n,
9862 pipe_config->dp_m2_n2.link_m,
9863 pipe_config->dp_m2_n2.link_n,
9864 pipe_config->dp_m2_n2.tu);
9866 DRM_DEBUG_KMS("requested mode:\n");
9867 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9868 DRM_DEBUG_KMS("adjusted mode:\n");
9869 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9870 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9871 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9872 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9873 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9874 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9875 pipe_config->gmch_pfit.control,
9876 pipe_config->gmch_pfit.pgm_ratios,
9877 pipe_config->gmch_pfit.lvds_border_bits);
9878 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9879 pipe_config->pch_pfit.pos,
9880 pipe_config->pch_pfit.size,
9881 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9882 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9883 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9886 static bool encoders_cloneable(const struct intel_encoder *a,
9887 const struct intel_encoder *b)
9889 /* masks could be asymmetric, so check both ways */
9890 return a == b || (a->cloneable & (1 << b->type) &&
9891 b->cloneable & (1 << a->type));
9894 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9895 struct intel_encoder *encoder)
9897 struct drm_device *dev = crtc->base.dev;
9898 struct intel_encoder *source_encoder;
9900 for_each_intel_encoder(dev, source_encoder) {
9901 if (source_encoder->new_crtc != crtc)
9904 if (!encoders_cloneable(encoder, source_encoder))
9911 static bool check_encoder_cloning(struct intel_crtc *crtc)
9913 struct drm_device *dev = crtc->base.dev;
9914 struct intel_encoder *encoder;
9916 for_each_intel_encoder(dev, encoder) {
9917 if (encoder->new_crtc != crtc)
9920 if (!check_single_encoder_cloning(crtc, encoder))
9927 static struct intel_crtc_config *
9928 intel_modeset_pipe_config(struct drm_crtc *crtc,
9929 struct drm_framebuffer *fb,
9930 struct drm_display_mode *mode)
9932 struct drm_device *dev = crtc->dev;
9933 struct intel_encoder *encoder;
9934 struct intel_crtc_config *pipe_config;
9935 int plane_bpp, ret = -EINVAL;
9938 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9939 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9940 return ERR_PTR(-EINVAL);
9943 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9945 return ERR_PTR(-ENOMEM);
9947 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9948 drm_mode_copy(&pipe_config->requested_mode, mode);
9950 pipe_config->cpu_transcoder =
9951 (enum transcoder) to_intel_crtc(crtc)->pipe;
9952 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9955 * Sanitize sync polarity flags based on requested ones. If neither
9956 * positive or negative polarity is requested, treat this as meaning
9957 * negative polarity.
9959 if (!(pipe_config->adjusted_mode.flags &
9960 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9961 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9963 if (!(pipe_config->adjusted_mode.flags &
9964 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9965 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9967 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9968 * plane pixel format and any sink constraints into account. Returns the
9969 * source plane bpp so that dithering can be selected on mismatches
9970 * after encoders and crtc also have had their say. */
9971 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9977 * Determine the real pipe dimensions. Note that stereo modes can
9978 * increase the actual pipe size due to the frame doubling and
9979 * insertion of additional space for blanks between the frame. This
9980 * is stored in the crtc timings. We use the requested mode to do this
9981 * computation to clearly distinguish it from the adjusted mode, which
9982 * can be changed by the connectors in the below retry loop.
9984 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9985 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9986 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9989 /* Ensure the port clock defaults are reset when retrying. */
9990 pipe_config->port_clock = 0;
9991 pipe_config->pixel_multiplier = 1;
9993 /* Fill in default crtc timings, allow encoders to overwrite them. */
9994 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9996 /* Pass our mode to the connectors and the CRTC to give them a chance to
9997 * adjust it according to limitations or connector properties, and also
9998 * a chance to reject the mode entirely.
10000 for_each_intel_encoder(dev, encoder) {
10002 if (&encoder->new_crtc->base != crtc)
10005 if (!(encoder->compute_config(encoder, pipe_config))) {
10006 DRM_DEBUG_KMS("Encoder config failure\n");
10011 /* Set default port clock if not overwritten by the encoder. Needs to be
10012 * done afterwards in case the encoder adjusts the mode. */
10013 if (!pipe_config->port_clock)
10014 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10015 * pipe_config->pixel_multiplier;
10017 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10019 DRM_DEBUG_KMS("CRTC fixup failed\n");
10023 if (ret == RETRY) {
10024 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10029 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10031 goto encoder_retry;
10034 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10035 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10036 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10038 return pipe_config;
10040 kfree(pipe_config);
10041 return ERR_PTR(ret);
10044 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10045 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10047 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10048 unsigned *prepare_pipes, unsigned *disable_pipes)
10050 struct intel_crtc *intel_crtc;
10051 struct drm_device *dev = crtc->dev;
10052 struct intel_encoder *encoder;
10053 struct intel_connector *connector;
10054 struct drm_crtc *tmp_crtc;
10056 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10058 /* Check which crtcs have changed outputs connected to them, these need
10059 * to be part of the prepare_pipes mask. We don't (yet) support global
10060 * modeset across multiple crtcs, so modeset_pipes will only have one
10061 * bit set at most. */
10062 list_for_each_entry(connector, &dev->mode_config.connector_list,
10064 if (connector->base.encoder == &connector->new_encoder->base)
10067 if (connector->base.encoder) {
10068 tmp_crtc = connector->base.encoder->crtc;
10070 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10073 if (connector->new_encoder)
10075 1 << connector->new_encoder->new_crtc->pipe;
10078 for_each_intel_encoder(dev, encoder) {
10079 if (encoder->base.crtc == &encoder->new_crtc->base)
10082 if (encoder->base.crtc) {
10083 tmp_crtc = encoder->base.crtc;
10085 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10088 if (encoder->new_crtc)
10089 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10092 /* Check for pipes that will be enabled/disabled ... */
10093 for_each_intel_crtc(dev, intel_crtc) {
10094 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10097 if (!intel_crtc->new_enabled)
10098 *disable_pipes |= 1 << intel_crtc->pipe;
10100 *prepare_pipes |= 1 << intel_crtc->pipe;
10104 /* set_mode is also used to update properties on life display pipes. */
10105 intel_crtc = to_intel_crtc(crtc);
10106 if (intel_crtc->new_enabled)
10107 *prepare_pipes |= 1 << intel_crtc->pipe;
10110 * For simplicity do a full modeset on any pipe where the output routing
10111 * changed. We could be more clever, but that would require us to be
10112 * more careful with calling the relevant encoder->mode_set functions.
10114 if (*prepare_pipes)
10115 *modeset_pipes = *prepare_pipes;
10117 /* ... and mask these out. */
10118 *modeset_pipes &= ~(*disable_pipes);
10119 *prepare_pipes &= ~(*disable_pipes);
10122 * HACK: We don't (yet) fully support global modesets. intel_set_config
10123 * obies this rule, but the modeset restore mode of
10124 * intel_modeset_setup_hw_state does not.
10126 *modeset_pipes &= 1 << intel_crtc->pipe;
10127 *prepare_pipes &= 1 << intel_crtc->pipe;
10129 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10130 *modeset_pipes, *prepare_pipes, *disable_pipes);
10133 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10135 struct drm_encoder *encoder;
10136 struct drm_device *dev = crtc->dev;
10138 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10139 if (encoder->crtc == crtc)
10146 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10148 struct intel_encoder *intel_encoder;
10149 struct intel_crtc *intel_crtc;
10150 struct drm_connector *connector;
10152 for_each_intel_encoder(dev, intel_encoder) {
10153 if (!intel_encoder->base.crtc)
10156 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10158 if (prepare_pipes & (1 << intel_crtc->pipe))
10159 intel_encoder->connectors_active = false;
10162 intel_modeset_commit_output_state(dev);
10164 /* Double check state. */
10165 for_each_intel_crtc(dev, intel_crtc) {
10166 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10167 WARN_ON(intel_crtc->new_config &&
10168 intel_crtc->new_config != &intel_crtc->config);
10169 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10172 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10173 if (!connector->encoder || !connector->encoder->crtc)
10176 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10178 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10179 struct drm_property *dpms_property =
10180 dev->mode_config.dpms_property;
10182 connector->dpms = DRM_MODE_DPMS_ON;
10183 drm_object_property_set_value(&connector->base,
10187 intel_encoder = to_intel_encoder(connector->encoder);
10188 intel_encoder->connectors_active = true;
10194 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10198 if (clock1 == clock2)
10201 if (!clock1 || !clock2)
10204 diff = abs(clock1 - clock2);
10206 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10212 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10213 list_for_each_entry((intel_crtc), \
10214 &(dev)->mode_config.crtc_list, \
10216 if (mask & (1 <<(intel_crtc)->pipe))
10219 intel_pipe_config_compare(struct drm_device *dev,
10220 struct intel_crtc_config *current_config,
10221 struct intel_crtc_config *pipe_config)
10223 #define PIPE_CONF_CHECK_X(name) \
10224 if (current_config->name != pipe_config->name) { \
10225 DRM_ERROR("mismatch in " #name " " \
10226 "(expected 0x%08x, found 0x%08x)\n", \
10227 current_config->name, \
10228 pipe_config->name); \
10232 #define PIPE_CONF_CHECK_I(name) \
10233 if (current_config->name != pipe_config->name) { \
10234 DRM_ERROR("mismatch in " #name " " \
10235 "(expected %i, found %i)\n", \
10236 current_config->name, \
10237 pipe_config->name); \
10241 /* This is required for BDW+ where there is only one set of registers for
10242 * switching between high and low RR.
10243 * This macro can be used whenever a comparison has to be made between one
10244 * hw state and multiple sw state variables.
10246 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10247 if ((current_config->name != pipe_config->name) && \
10248 (current_config->alt_name != pipe_config->name)) { \
10249 DRM_ERROR("mismatch in " #name " " \
10250 "(expected %i or %i, found %i)\n", \
10251 current_config->name, \
10252 current_config->alt_name, \
10253 pipe_config->name); \
10257 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10258 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10259 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10260 "(expected %i, found %i)\n", \
10261 current_config->name & (mask), \
10262 pipe_config->name & (mask)); \
10266 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10267 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10268 DRM_ERROR("mismatch in " #name " " \
10269 "(expected %i, found %i)\n", \
10270 current_config->name, \
10271 pipe_config->name); \
10275 #define PIPE_CONF_QUIRK(quirk) \
10276 ((current_config->quirks | pipe_config->quirks) & (quirk))
10278 PIPE_CONF_CHECK_I(cpu_transcoder);
10280 PIPE_CONF_CHECK_I(has_pch_encoder);
10281 PIPE_CONF_CHECK_I(fdi_lanes);
10282 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10283 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10284 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10285 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10286 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10288 PIPE_CONF_CHECK_I(has_dp_encoder);
10290 if (INTEL_INFO(dev)->gen < 8) {
10291 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10292 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10293 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10294 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10295 PIPE_CONF_CHECK_I(dp_m_n.tu);
10297 if (current_config->has_drrs) {
10298 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10299 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10300 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10301 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10302 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10305 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10306 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10307 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10308 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10309 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10312 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10313 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10314 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10315 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10316 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10317 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10319 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10320 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10321 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10322 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10323 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10324 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10326 PIPE_CONF_CHECK_I(pixel_multiplier);
10327 PIPE_CONF_CHECK_I(has_hdmi_sink);
10328 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10329 IS_VALLEYVIEW(dev))
10330 PIPE_CONF_CHECK_I(limited_color_range);
10332 PIPE_CONF_CHECK_I(has_audio);
10334 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10335 DRM_MODE_FLAG_INTERLACE);
10337 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10338 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10339 DRM_MODE_FLAG_PHSYNC);
10340 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10341 DRM_MODE_FLAG_NHSYNC);
10342 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10343 DRM_MODE_FLAG_PVSYNC);
10344 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10345 DRM_MODE_FLAG_NVSYNC);
10348 PIPE_CONF_CHECK_I(pipe_src_w);
10349 PIPE_CONF_CHECK_I(pipe_src_h);
10352 * FIXME: BIOS likes to set up a cloned config with lvds+external
10353 * screen. Since we don't yet re-compute the pipe config when moving
10354 * just the lvds port away to another pipe the sw tracking won't match.
10356 * Proper atomic modesets with recomputed global state will fix this.
10357 * Until then just don't check gmch state for inherited modes.
10359 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10360 PIPE_CONF_CHECK_I(gmch_pfit.control);
10361 /* pfit ratios are autocomputed by the hw on gen4+ */
10362 if (INTEL_INFO(dev)->gen < 4)
10363 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10364 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10367 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10368 if (current_config->pch_pfit.enabled) {
10369 PIPE_CONF_CHECK_I(pch_pfit.pos);
10370 PIPE_CONF_CHECK_I(pch_pfit.size);
10373 /* BDW+ don't expose a synchronous way to read the state */
10374 if (IS_HASWELL(dev))
10375 PIPE_CONF_CHECK_I(ips_enabled);
10377 PIPE_CONF_CHECK_I(double_wide);
10379 PIPE_CONF_CHECK_X(ddi_pll_sel);
10381 PIPE_CONF_CHECK_I(shared_dpll);
10382 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10383 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10384 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10385 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10386 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10388 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10389 PIPE_CONF_CHECK_I(pipe_bpp);
10391 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10392 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10394 #undef PIPE_CONF_CHECK_X
10395 #undef PIPE_CONF_CHECK_I
10396 #undef PIPE_CONF_CHECK_I_ALT
10397 #undef PIPE_CONF_CHECK_FLAGS
10398 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10399 #undef PIPE_CONF_QUIRK
10405 check_connector_state(struct drm_device *dev)
10407 struct intel_connector *connector;
10409 list_for_each_entry(connector, &dev->mode_config.connector_list,
10411 /* This also checks the encoder/connector hw state with the
10412 * ->get_hw_state callbacks. */
10413 intel_connector_check_state(connector);
10415 WARN(&connector->new_encoder->base != connector->base.encoder,
10416 "connector's staged encoder doesn't match current encoder\n");
10421 check_encoder_state(struct drm_device *dev)
10423 struct intel_encoder *encoder;
10424 struct intel_connector *connector;
10426 for_each_intel_encoder(dev, encoder) {
10427 bool enabled = false;
10428 bool active = false;
10429 enum pipe pipe, tracked_pipe;
10431 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10432 encoder->base.base.id,
10433 encoder->base.name);
10435 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10436 "encoder's stage crtc doesn't match current crtc\n");
10437 WARN(encoder->connectors_active && !encoder->base.crtc,
10438 "encoder's active_connectors set, but no crtc\n");
10440 list_for_each_entry(connector, &dev->mode_config.connector_list,
10442 if (connector->base.encoder != &encoder->base)
10445 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10449 * for MST connectors if we unplug the connector is gone
10450 * away but the encoder is still connected to a crtc
10451 * until a modeset happens in response to the hotplug.
10453 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10456 WARN(!!encoder->base.crtc != enabled,
10457 "encoder's enabled state mismatch "
10458 "(expected %i, found %i)\n",
10459 !!encoder->base.crtc, enabled);
10460 WARN(active && !encoder->base.crtc,
10461 "active encoder with no crtc\n");
10463 WARN(encoder->connectors_active != active,
10464 "encoder's computed active state doesn't match tracked active state "
10465 "(expected %i, found %i)\n", active, encoder->connectors_active);
10467 active = encoder->get_hw_state(encoder, &pipe);
10468 WARN(active != encoder->connectors_active,
10469 "encoder's hw state doesn't match sw tracking "
10470 "(expected %i, found %i)\n",
10471 encoder->connectors_active, active);
10473 if (!encoder->base.crtc)
10476 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10477 WARN(active && pipe != tracked_pipe,
10478 "active encoder's pipe doesn't match"
10479 "(expected %i, found %i)\n",
10480 tracked_pipe, pipe);
10486 check_crtc_state(struct drm_device *dev)
10488 struct drm_i915_private *dev_priv = dev->dev_private;
10489 struct intel_crtc *crtc;
10490 struct intel_encoder *encoder;
10491 struct intel_crtc_config pipe_config;
10493 for_each_intel_crtc(dev, crtc) {
10494 bool enabled = false;
10495 bool active = false;
10497 memset(&pipe_config, 0, sizeof(pipe_config));
10499 DRM_DEBUG_KMS("[CRTC:%d]\n",
10500 crtc->base.base.id);
10502 WARN(crtc->active && !crtc->base.enabled,
10503 "active crtc, but not enabled in sw tracking\n");
10505 for_each_intel_encoder(dev, encoder) {
10506 if (encoder->base.crtc != &crtc->base)
10509 if (encoder->connectors_active)
10513 WARN(active != crtc->active,
10514 "crtc's computed active state doesn't match tracked active state "
10515 "(expected %i, found %i)\n", active, crtc->active);
10516 WARN(enabled != crtc->base.enabled,
10517 "crtc's computed enabled state doesn't match tracked enabled state "
10518 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10520 active = dev_priv->display.get_pipe_config(crtc,
10523 /* hw state is inconsistent with the pipe quirk */
10524 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10525 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10526 active = crtc->active;
10528 for_each_intel_encoder(dev, encoder) {
10530 if (encoder->base.crtc != &crtc->base)
10532 if (encoder->get_hw_state(encoder, &pipe))
10533 encoder->get_config(encoder, &pipe_config);
10536 WARN(crtc->active != active,
10537 "crtc active state doesn't match with hw state "
10538 "(expected %i, found %i)\n", crtc->active, active);
10541 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10542 WARN(1, "pipe state doesn't match!\n");
10543 intel_dump_pipe_config(crtc, &pipe_config,
10545 intel_dump_pipe_config(crtc, &crtc->config,
10552 check_shared_dpll_state(struct drm_device *dev)
10554 struct drm_i915_private *dev_priv = dev->dev_private;
10555 struct intel_crtc *crtc;
10556 struct intel_dpll_hw_state dpll_hw_state;
10559 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10560 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10561 int enabled_crtcs = 0, active_crtcs = 0;
10564 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10566 DRM_DEBUG_KMS("%s\n", pll->name);
10568 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10570 WARN(pll->active > pll->refcount,
10571 "more active pll users than references: %i vs %i\n",
10572 pll->active, pll->refcount);
10573 WARN(pll->active && !pll->on,
10574 "pll in active use but not on in sw tracking\n");
10575 WARN(pll->on && !pll->active,
10576 "pll in on but not on in use in sw tracking\n");
10577 WARN(pll->on != active,
10578 "pll on state mismatch (expected %i, found %i)\n",
10581 for_each_intel_crtc(dev, crtc) {
10582 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10584 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10587 WARN(pll->active != active_crtcs,
10588 "pll active crtcs mismatch (expected %i, found %i)\n",
10589 pll->active, active_crtcs);
10590 WARN(pll->refcount != enabled_crtcs,
10591 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10592 pll->refcount, enabled_crtcs);
10594 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10595 sizeof(dpll_hw_state)),
10596 "pll hw state mismatch\n");
10601 intel_modeset_check_state(struct drm_device *dev)
10603 check_connector_state(dev);
10604 check_encoder_state(dev);
10605 check_crtc_state(dev);
10606 check_shared_dpll_state(dev);
10609 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10613 * FDI already provided one idea for the dotclock.
10614 * Yell if the encoder disagrees.
10616 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10617 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10618 pipe_config->adjusted_mode.crtc_clock, dotclock);
10621 static void update_scanline_offset(struct intel_crtc *crtc)
10623 struct drm_device *dev = crtc->base.dev;
10626 * The scanline counter increments at the leading edge of hsync.
10628 * On most platforms it starts counting from vtotal-1 on the
10629 * first active line. That means the scanline counter value is
10630 * always one less than what we would expect. Ie. just after
10631 * start of vblank, which also occurs at start of hsync (on the
10632 * last active line), the scanline counter will read vblank_start-1.
10634 * On gen2 the scanline counter starts counting from 1 instead
10635 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10636 * to keep the value positive), instead of adding one.
10638 * On HSW+ the behaviour of the scanline counter depends on the output
10639 * type. For DP ports it behaves like most other platforms, but on HDMI
10640 * there's an extra 1 line difference. So we need to add two instead of
10641 * one to the value.
10643 if (IS_GEN2(dev)) {
10644 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10647 vtotal = mode->crtc_vtotal;
10648 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10651 crtc->scanline_offset = vtotal - 1;
10652 } else if (HAS_DDI(dev) &&
10653 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10654 crtc->scanline_offset = 2;
10656 crtc->scanline_offset = 1;
10659 static int __intel_set_mode(struct drm_crtc *crtc,
10660 struct drm_display_mode *mode,
10661 int x, int y, struct drm_framebuffer *fb)
10663 struct drm_device *dev = crtc->dev;
10664 struct drm_i915_private *dev_priv = dev->dev_private;
10665 struct drm_display_mode *saved_mode;
10666 struct intel_crtc_config *pipe_config = NULL;
10667 struct intel_crtc *intel_crtc;
10668 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10671 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10675 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10676 &prepare_pipes, &disable_pipes);
10678 *saved_mode = crtc->mode;
10680 /* Hack: Because we don't (yet) support global modeset on multiple
10681 * crtcs, we don't keep track of the new mode for more than one crtc.
10682 * Hence simply check whether any bit is set in modeset_pipes in all the
10683 * pieces of code that are not yet converted to deal with mutliple crtcs
10684 * changing their mode at the same time. */
10685 if (modeset_pipes) {
10686 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10687 if (IS_ERR(pipe_config)) {
10688 ret = PTR_ERR(pipe_config);
10689 pipe_config = NULL;
10693 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10695 to_intel_crtc(crtc)->new_config = pipe_config;
10699 * See if the config requires any additional preparation, e.g.
10700 * to adjust global state with pipes off. We need to do this
10701 * here so we can get the modeset_pipe updated config for the new
10702 * mode set on this crtc. For other crtcs we need to use the
10703 * adjusted_mode bits in the crtc directly.
10705 if (IS_VALLEYVIEW(dev)) {
10706 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10708 /* may have added more to prepare_pipes than we should */
10709 prepare_pipes &= ~disable_pipes;
10712 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10713 intel_crtc_disable(&intel_crtc->base);
10715 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10716 if (intel_crtc->base.enabled)
10717 dev_priv->display.crtc_disable(&intel_crtc->base);
10720 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10721 * to set it here already despite that we pass it down the callchain.
10723 if (modeset_pipes) {
10724 crtc->mode = *mode;
10725 /* mode_set/enable/disable functions rely on a correct pipe
10727 to_intel_crtc(crtc)->config = *pipe_config;
10728 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10731 * Calculate and store various constants which
10732 * are later needed by vblank and swap-completion
10733 * timestamping. They are derived from true hwmode.
10735 drm_calc_timestamping_constants(crtc,
10736 &pipe_config->adjusted_mode);
10739 /* Only after disabling all output pipelines that will be changed can we
10740 * update the the output configuration. */
10741 intel_modeset_update_state(dev, prepare_pipes);
10743 if (dev_priv->display.modeset_global_resources)
10744 dev_priv->display.modeset_global_resources(dev);
10746 /* Set up the DPLL and any encoders state that needs to adjust or depend
10749 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10750 struct drm_framebuffer *old_fb = crtc->primary->fb;
10751 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10752 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10754 mutex_lock(&dev->struct_mutex);
10755 ret = intel_pin_and_fence_fb_obj(dev,
10759 DRM_ERROR("pin & fence failed\n");
10760 mutex_unlock(&dev->struct_mutex);
10764 intel_unpin_fb_obj(old_obj);
10765 i915_gem_track_fb(old_obj, obj,
10766 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10767 mutex_unlock(&dev->struct_mutex);
10769 crtc->primary->fb = fb;
10773 ret = dev_priv->display.crtc_mode_set(intel_crtc, x, y, fb);
10778 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10779 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10780 update_scanline_offset(intel_crtc);
10782 dev_priv->display.crtc_enable(&intel_crtc->base);
10785 /* FIXME: add subpixel order */
10787 if (ret && crtc->enabled)
10788 crtc->mode = *saved_mode;
10791 kfree(pipe_config);
10796 static int intel_set_mode(struct drm_crtc *crtc,
10797 struct drm_display_mode *mode,
10798 int x, int y, struct drm_framebuffer *fb)
10802 ret = __intel_set_mode(crtc, mode, x, y, fb);
10805 intel_modeset_check_state(crtc->dev);
10810 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10812 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10815 #undef for_each_intel_crtc_masked
10817 static void intel_set_config_free(struct intel_set_config *config)
10822 kfree(config->save_connector_encoders);
10823 kfree(config->save_encoder_crtcs);
10824 kfree(config->save_crtc_enabled);
10828 static int intel_set_config_save_state(struct drm_device *dev,
10829 struct intel_set_config *config)
10831 struct drm_crtc *crtc;
10832 struct drm_encoder *encoder;
10833 struct drm_connector *connector;
10836 config->save_crtc_enabled =
10837 kcalloc(dev->mode_config.num_crtc,
10838 sizeof(bool), GFP_KERNEL);
10839 if (!config->save_crtc_enabled)
10842 config->save_encoder_crtcs =
10843 kcalloc(dev->mode_config.num_encoder,
10844 sizeof(struct drm_crtc *), GFP_KERNEL);
10845 if (!config->save_encoder_crtcs)
10848 config->save_connector_encoders =
10849 kcalloc(dev->mode_config.num_connector,
10850 sizeof(struct drm_encoder *), GFP_KERNEL);
10851 if (!config->save_connector_encoders)
10854 /* Copy data. Note that driver private data is not affected.
10855 * Should anything bad happen only the expected state is
10856 * restored, not the drivers personal bookkeeping.
10859 for_each_crtc(dev, crtc) {
10860 config->save_crtc_enabled[count++] = crtc->enabled;
10864 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10865 config->save_encoder_crtcs[count++] = encoder->crtc;
10869 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10870 config->save_connector_encoders[count++] = connector->encoder;
10876 static void intel_set_config_restore_state(struct drm_device *dev,
10877 struct intel_set_config *config)
10879 struct intel_crtc *crtc;
10880 struct intel_encoder *encoder;
10881 struct intel_connector *connector;
10885 for_each_intel_crtc(dev, crtc) {
10886 crtc->new_enabled = config->save_crtc_enabled[count++];
10888 if (crtc->new_enabled)
10889 crtc->new_config = &crtc->config;
10891 crtc->new_config = NULL;
10895 for_each_intel_encoder(dev, encoder) {
10896 encoder->new_crtc =
10897 to_intel_crtc(config->save_encoder_crtcs[count++]);
10901 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10902 connector->new_encoder =
10903 to_intel_encoder(config->save_connector_encoders[count++]);
10908 is_crtc_connector_off(struct drm_mode_set *set)
10912 if (set->num_connectors == 0)
10915 if (WARN_ON(set->connectors == NULL))
10918 for (i = 0; i < set->num_connectors; i++)
10919 if (set->connectors[i]->encoder &&
10920 set->connectors[i]->encoder->crtc == set->crtc &&
10921 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10928 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10929 struct intel_set_config *config)
10932 /* We should be able to check here if the fb has the same properties
10933 * and then just flip_or_move it */
10934 if (is_crtc_connector_off(set)) {
10935 config->mode_changed = true;
10936 } else if (set->crtc->primary->fb != set->fb) {
10938 * If we have no fb, we can only flip as long as the crtc is
10939 * active, otherwise we need a full mode set. The crtc may
10940 * be active if we've only disabled the primary plane, or
10941 * in fastboot situations.
10943 if (set->crtc->primary->fb == NULL) {
10944 struct intel_crtc *intel_crtc =
10945 to_intel_crtc(set->crtc);
10947 if (intel_crtc->active) {
10948 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10949 config->fb_changed = true;
10951 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10952 config->mode_changed = true;
10954 } else if (set->fb == NULL) {
10955 config->mode_changed = true;
10956 } else if (set->fb->pixel_format !=
10957 set->crtc->primary->fb->pixel_format) {
10958 config->mode_changed = true;
10960 config->fb_changed = true;
10964 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10965 config->fb_changed = true;
10967 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10968 DRM_DEBUG_KMS("modes are different, full mode set\n");
10969 drm_mode_debug_printmodeline(&set->crtc->mode);
10970 drm_mode_debug_printmodeline(set->mode);
10971 config->mode_changed = true;
10974 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10975 set->crtc->base.id, config->mode_changed, config->fb_changed);
10979 intel_modeset_stage_output_state(struct drm_device *dev,
10980 struct drm_mode_set *set,
10981 struct intel_set_config *config)
10983 struct intel_connector *connector;
10984 struct intel_encoder *encoder;
10985 struct intel_crtc *crtc;
10988 /* The upper layers ensure that we either disable a crtc or have a list
10989 * of connectors. For paranoia, double-check this. */
10990 WARN_ON(!set->fb && (set->num_connectors != 0));
10991 WARN_ON(set->fb && (set->num_connectors == 0));
10993 list_for_each_entry(connector, &dev->mode_config.connector_list,
10995 /* Otherwise traverse passed in connector list and get encoders
10997 for (ro = 0; ro < set->num_connectors; ro++) {
10998 if (set->connectors[ro] == &connector->base) {
10999 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11004 /* If we disable the crtc, disable all its connectors. Also, if
11005 * the connector is on the changing crtc but not on the new
11006 * connector list, disable it. */
11007 if ((!set->fb || ro == set->num_connectors) &&
11008 connector->base.encoder &&
11009 connector->base.encoder->crtc == set->crtc) {
11010 connector->new_encoder = NULL;
11012 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11013 connector->base.base.id,
11014 connector->base.name);
11018 if (&connector->new_encoder->base != connector->base.encoder) {
11019 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11020 config->mode_changed = true;
11023 /* connector->new_encoder is now updated for all connectors. */
11025 /* Update crtc of enabled connectors. */
11026 list_for_each_entry(connector, &dev->mode_config.connector_list,
11028 struct drm_crtc *new_crtc;
11030 if (!connector->new_encoder)
11033 new_crtc = connector->new_encoder->base.crtc;
11035 for (ro = 0; ro < set->num_connectors; ro++) {
11036 if (set->connectors[ro] == &connector->base)
11037 new_crtc = set->crtc;
11040 /* Make sure the new CRTC will work with the encoder */
11041 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11045 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11047 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11048 connector->base.base.id,
11049 connector->base.name,
11050 new_crtc->base.id);
11053 /* Check for any encoders that needs to be disabled. */
11054 for_each_intel_encoder(dev, encoder) {
11055 int num_connectors = 0;
11056 list_for_each_entry(connector,
11057 &dev->mode_config.connector_list,
11059 if (connector->new_encoder == encoder) {
11060 WARN_ON(!connector->new_encoder->new_crtc);
11065 if (num_connectors == 0)
11066 encoder->new_crtc = NULL;
11067 else if (num_connectors > 1)
11070 /* Only now check for crtc changes so we don't miss encoders
11071 * that will be disabled. */
11072 if (&encoder->new_crtc->base != encoder->base.crtc) {
11073 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11074 config->mode_changed = true;
11077 /* Now we've also updated encoder->new_crtc for all encoders. */
11078 list_for_each_entry(connector, &dev->mode_config.connector_list,
11080 if (connector->new_encoder)
11081 if (connector->new_encoder != connector->encoder)
11082 connector->encoder = connector->new_encoder;
11084 for_each_intel_crtc(dev, crtc) {
11085 crtc->new_enabled = false;
11087 for_each_intel_encoder(dev, encoder) {
11088 if (encoder->new_crtc == crtc) {
11089 crtc->new_enabled = true;
11094 if (crtc->new_enabled != crtc->base.enabled) {
11095 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11096 crtc->new_enabled ? "en" : "dis");
11097 config->mode_changed = true;
11100 if (crtc->new_enabled)
11101 crtc->new_config = &crtc->config;
11103 crtc->new_config = NULL;
11109 static void disable_crtc_nofb(struct intel_crtc *crtc)
11111 struct drm_device *dev = crtc->base.dev;
11112 struct intel_encoder *encoder;
11113 struct intel_connector *connector;
11115 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11116 pipe_name(crtc->pipe));
11118 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11119 if (connector->new_encoder &&
11120 connector->new_encoder->new_crtc == crtc)
11121 connector->new_encoder = NULL;
11124 for_each_intel_encoder(dev, encoder) {
11125 if (encoder->new_crtc == crtc)
11126 encoder->new_crtc = NULL;
11129 crtc->new_enabled = false;
11130 crtc->new_config = NULL;
11133 static int intel_crtc_set_config(struct drm_mode_set *set)
11135 struct drm_device *dev;
11136 struct drm_mode_set save_set;
11137 struct intel_set_config *config;
11141 BUG_ON(!set->crtc);
11142 BUG_ON(!set->crtc->helper_private);
11144 /* Enforce sane interface api - has been abused by the fb helper. */
11145 BUG_ON(!set->mode && set->fb);
11146 BUG_ON(set->fb && set->num_connectors == 0);
11149 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11150 set->crtc->base.id, set->fb->base.id,
11151 (int)set->num_connectors, set->x, set->y);
11153 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11156 dev = set->crtc->dev;
11159 config = kzalloc(sizeof(*config), GFP_KERNEL);
11163 ret = intel_set_config_save_state(dev, config);
11167 save_set.crtc = set->crtc;
11168 save_set.mode = &set->crtc->mode;
11169 save_set.x = set->crtc->x;
11170 save_set.y = set->crtc->y;
11171 save_set.fb = set->crtc->primary->fb;
11173 /* Compute whether we need a full modeset, only an fb base update or no
11174 * change at all. In the future we might also check whether only the
11175 * mode changed, e.g. for LVDS where we only change the panel fitter in
11177 intel_set_config_compute_mode_changes(set, config);
11179 ret = intel_modeset_stage_output_state(dev, set, config);
11183 if (config->mode_changed) {
11184 ret = intel_set_mode(set->crtc, set->mode,
11185 set->x, set->y, set->fb);
11186 } else if (config->fb_changed) {
11187 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11189 intel_crtc_wait_for_pending_flips(set->crtc);
11191 ret = intel_pipe_set_base(set->crtc,
11192 set->x, set->y, set->fb);
11195 * We need to make sure the primary plane is re-enabled if it
11196 * has previously been turned off.
11198 if (!intel_crtc->primary_enabled && ret == 0) {
11199 WARN_ON(!intel_crtc->active);
11200 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11204 * In the fastboot case this may be our only check of the
11205 * state after boot. It would be better to only do it on
11206 * the first update, but we don't have a nice way of doing that
11207 * (and really, set_config isn't used much for high freq page
11208 * flipping, so increasing its cost here shouldn't be a big
11211 if (i915.fastboot && ret == 0)
11212 intel_modeset_check_state(set->crtc->dev);
11216 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11217 set->crtc->base.id, ret);
11219 intel_set_config_restore_state(dev, config);
11222 * HACK: if the pipe was on, but we didn't have a framebuffer,
11223 * force the pipe off to avoid oopsing in the modeset code
11224 * due to fb==NULL. This should only happen during boot since
11225 * we don't yet reconstruct the FB from the hardware state.
11227 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11228 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11230 /* Try to restore the config */
11231 if (config->mode_changed &&
11232 intel_set_mode(save_set.crtc, save_set.mode,
11233 save_set.x, save_set.y, save_set.fb))
11234 DRM_ERROR("failed to restore config after modeset failure\n");
11238 intel_set_config_free(config);
11242 static const struct drm_crtc_funcs intel_crtc_funcs = {
11243 .gamma_set = intel_crtc_gamma_set,
11244 .set_config = intel_crtc_set_config,
11245 .destroy = intel_crtc_destroy,
11246 .page_flip = intel_crtc_page_flip,
11249 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11250 struct intel_shared_dpll *pll,
11251 struct intel_dpll_hw_state *hw_state)
11255 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11258 val = I915_READ(PCH_DPLL(pll->id));
11259 hw_state->dpll = val;
11260 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11261 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11263 return val & DPLL_VCO_ENABLE;
11266 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11267 struct intel_shared_dpll *pll)
11269 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11270 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11273 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11274 struct intel_shared_dpll *pll)
11276 /* PCH refclock must be enabled first */
11277 ibx_assert_pch_refclk_enabled(dev_priv);
11279 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11281 /* Wait for the clocks to stabilize. */
11282 POSTING_READ(PCH_DPLL(pll->id));
11285 /* The pixel multiplier can only be updated once the
11286 * DPLL is enabled and the clocks are stable.
11288 * So write it again.
11290 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11291 POSTING_READ(PCH_DPLL(pll->id));
11295 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11296 struct intel_shared_dpll *pll)
11298 struct drm_device *dev = dev_priv->dev;
11299 struct intel_crtc *crtc;
11301 /* Make sure no transcoder isn't still depending on us. */
11302 for_each_intel_crtc(dev, crtc) {
11303 if (intel_crtc_to_shared_dpll(crtc) == pll)
11304 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11307 I915_WRITE(PCH_DPLL(pll->id), 0);
11308 POSTING_READ(PCH_DPLL(pll->id));
11312 static char *ibx_pch_dpll_names[] = {
11317 static void ibx_pch_dpll_init(struct drm_device *dev)
11319 struct drm_i915_private *dev_priv = dev->dev_private;
11322 dev_priv->num_shared_dpll = 2;
11324 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11325 dev_priv->shared_dplls[i].id = i;
11326 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11327 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11328 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11329 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11330 dev_priv->shared_dplls[i].get_hw_state =
11331 ibx_pch_dpll_get_hw_state;
11335 static void intel_shared_dpll_init(struct drm_device *dev)
11337 struct drm_i915_private *dev_priv = dev->dev_private;
11340 intel_ddi_pll_init(dev);
11341 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11342 ibx_pch_dpll_init(dev);
11344 dev_priv->num_shared_dpll = 0;
11346 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11350 intel_primary_plane_disable(struct drm_plane *plane)
11352 struct drm_device *dev = plane->dev;
11353 struct intel_crtc *intel_crtc;
11358 BUG_ON(!plane->crtc);
11360 intel_crtc = to_intel_crtc(plane->crtc);
11363 * Even though we checked plane->fb above, it's still possible that
11364 * the primary plane has been implicitly disabled because the crtc
11365 * coordinates given weren't visible, or because we detected
11366 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11367 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11368 * In either case, we need to unpin the FB and let the fb pointer get
11369 * updated, but otherwise we don't need to touch the hardware.
11371 if (!intel_crtc->primary_enabled)
11372 goto disable_unpin;
11374 intel_crtc_wait_for_pending_flips(plane->crtc);
11375 intel_disable_primary_hw_plane(plane, plane->crtc);
11378 mutex_lock(&dev->struct_mutex);
11379 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11380 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11381 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11382 mutex_unlock(&dev->struct_mutex);
11389 intel_check_primary_plane(struct drm_plane *plane,
11390 struct intel_plane_state *state)
11392 struct drm_crtc *crtc = state->crtc;
11393 struct drm_framebuffer *fb = state->fb;
11394 struct drm_rect *dest = &state->dst;
11395 struct drm_rect *src = &state->src;
11396 const struct drm_rect *clip = &state->clip;
11398 return drm_plane_helper_check_update(plane, crtc, fb,
11400 DRM_PLANE_HELPER_NO_SCALING,
11401 DRM_PLANE_HELPER_NO_SCALING,
11402 false, true, &state->visible);
11406 intel_prepare_primary_plane(struct drm_plane *plane,
11407 struct intel_plane_state *state)
11409 struct drm_crtc *crtc = state->crtc;
11410 struct drm_framebuffer *fb = state->fb;
11411 struct drm_device *dev = crtc->dev;
11412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11413 enum pipe pipe = intel_crtc->pipe;
11414 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11415 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11418 intel_crtc_wait_for_pending_flips(crtc);
11420 if (intel_crtc_has_pending_flip(crtc)) {
11421 DRM_ERROR("pipe is still busy with an old pageflip\n");
11425 if (old_obj != obj) {
11426 mutex_lock(&dev->struct_mutex);
11427 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11429 i915_gem_track_fb(old_obj, obj,
11430 INTEL_FRONTBUFFER_PRIMARY(pipe));
11431 mutex_unlock(&dev->struct_mutex);
11433 DRM_DEBUG_KMS("pin & fence failed\n");
11442 intel_commit_primary_plane(struct drm_plane *plane,
11443 struct intel_plane_state *state)
11445 struct drm_crtc *crtc = state->crtc;
11446 struct drm_framebuffer *fb = state->fb;
11447 struct drm_device *dev = crtc->dev;
11448 struct drm_i915_private *dev_priv = dev->dev_private;
11449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11450 enum pipe pipe = intel_crtc->pipe;
11451 struct drm_framebuffer *old_fb = plane->fb;
11452 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11453 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11454 struct intel_plane *intel_plane = to_intel_plane(plane);
11455 struct drm_rect *src = &state->src;
11457 crtc->primary->fb = fb;
11461 intel_plane->crtc_x = state->orig_dst.x1;
11462 intel_plane->crtc_y = state->orig_dst.y1;
11463 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11464 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11465 intel_plane->src_x = state->orig_src.x1;
11466 intel_plane->src_y = state->orig_src.y1;
11467 intel_plane->src_w = drm_rect_width(&state->orig_src);
11468 intel_plane->src_h = drm_rect_height(&state->orig_src);
11469 intel_plane->obj = obj;
11471 if (intel_crtc->active) {
11473 * FBC does not work on some platforms for rotated
11474 * planes, so disable it when rotation is not 0 and
11475 * update it when rotation is set back to 0.
11477 * FIXME: This is redundant with the fbc update done in
11478 * the primary plane enable function except that that
11479 * one is done too late. We eventually need to unify
11482 if (intel_crtc->primary_enabled &&
11483 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11484 dev_priv->fbc.plane == intel_crtc->plane &&
11485 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11486 intel_disable_fbc(dev);
11489 if (state->visible) {
11490 bool was_enabled = intel_crtc->primary_enabled;
11492 /* FIXME: kill this fastboot hack */
11493 intel_update_pipe_size(intel_crtc);
11495 intel_crtc->primary_enabled = true;
11497 dev_priv->display.update_primary_plane(crtc, plane->fb,
11501 * BDW signals flip done immediately if the plane
11502 * is disabled, even if the plane enable is already
11503 * armed to occur at the next vblank :(
11505 if (IS_BROADWELL(dev) && !was_enabled)
11506 intel_wait_for_vblank(dev, intel_crtc->pipe);
11509 * If clipping results in a non-visible primary plane,
11510 * we'll disable the primary plane. Note that this is
11511 * a bit different than what happens if userspace
11512 * explicitly disables the plane by passing fb=0
11513 * because plane->fb still gets set and pinned.
11515 intel_disable_primary_hw_plane(plane, crtc);
11518 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11520 mutex_lock(&dev->struct_mutex);
11521 intel_update_fbc(dev);
11522 mutex_unlock(&dev->struct_mutex);
11525 if (old_fb && old_fb != fb) {
11526 if (intel_crtc->active)
11527 intel_wait_for_vblank(dev, intel_crtc->pipe);
11529 mutex_lock(&dev->struct_mutex);
11530 intel_unpin_fb_obj(old_obj);
11531 mutex_unlock(&dev->struct_mutex);
11536 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11537 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11538 unsigned int crtc_w, unsigned int crtc_h,
11539 uint32_t src_x, uint32_t src_y,
11540 uint32_t src_w, uint32_t src_h)
11542 struct intel_plane_state state;
11543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11549 /* sample coordinates in 16.16 fixed point */
11550 state.src.x1 = src_x;
11551 state.src.x2 = src_x + src_w;
11552 state.src.y1 = src_y;
11553 state.src.y2 = src_y + src_h;
11555 /* integer pixels */
11556 state.dst.x1 = crtc_x;
11557 state.dst.x2 = crtc_x + crtc_w;
11558 state.dst.y1 = crtc_y;
11559 state.dst.y2 = crtc_y + crtc_h;
11563 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11564 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11566 state.orig_src = state.src;
11567 state.orig_dst = state.dst;
11569 ret = intel_check_primary_plane(plane, &state);
11573 ret = intel_prepare_primary_plane(plane, &state);
11577 intel_commit_primary_plane(plane, &state);
11582 /* Common destruction function for both primary and cursor planes */
11583 static void intel_plane_destroy(struct drm_plane *plane)
11585 struct intel_plane *intel_plane = to_intel_plane(plane);
11586 drm_plane_cleanup(plane);
11587 kfree(intel_plane);
11590 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11591 .update_plane = intel_primary_plane_setplane,
11592 .disable_plane = intel_primary_plane_disable,
11593 .destroy = intel_plane_destroy,
11594 .set_property = intel_plane_set_property
11597 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11600 struct intel_plane *primary;
11601 const uint32_t *intel_primary_formats;
11604 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11605 if (primary == NULL)
11608 primary->can_scale = false;
11609 primary->max_downscale = 1;
11610 primary->pipe = pipe;
11611 primary->plane = pipe;
11612 primary->rotation = BIT(DRM_ROTATE_0);
11613 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11614 primary->plane = !pipe;
11616 if (INTEL_INFO(dev)->gen <= 3) {
11617 intel_primary_formats = intel_primary_formats_gen2;
11618 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11620 intel_primary_formats = intel_primary_formats_gen4;
11621 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11624 drm_universal_plane_init(dev, &primary->base, 0,
11625 &intel_primary_plane_funcs,
11626 intel_primary_formats, num_formats,
11627 DRM_PLANE_TYPE_PRIMARY);
11629 if (INTEL_INFO(dev)->gen >= 4) {
11630 if (!dev->mode_config.rotation_property)
11631 dev->mode_config.rotation_property =
11632 drm_mode_create_rotation_property(dev,
11633 BIT(DRM_ROTATE_0) |
11634 BIT(DRM_ROTATE_180));
11635 if (dev->mode_config.rotation_property)
11636 drm_object_attach_property(&primary->base.base,
11637 dev->mode_config.rotation_property,
11638 primary->rotation);
11641 return &primary->base;
11645 intel_cursor_plane_disable(struct drm_plane *plane)
11650 BUG_ON(!plane->crtc);
11652 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11656 intel_check_cursor_plane(struct drm_plane *plane,
11657 struct intel_plane_state *state)
11659 struct drm_crtc *crtc = state->crtc;
11660 struct drm_device *dev = crtc->dev;
11661 struct drm_framebuffer *fb = state->fb;
11662 struct drm_rect *dest = &state->dst;
11663 struct drm_rect *src = &state->src;
11664 const struct drm_rect *clip = &state->clip;
11665 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11666 int crtc_w, crtc_h;
11670 ret = drm_plane_helper_check_update(plane, crtc, fb,
11672 DRM_PLANE_HELPER_NO_SCALING,
11673 DRM_PLANE_HELPER_NO_SCALING,
11674 true, true, &state->visible);
11679 /* if we want to turn off the cursor ignore width and height */
11683 /* Check for which cursor types we support */
11684 crtc_w = drm_rect_width(&state->orig_dst);
11685 crtc_h = drm_rect_height(&state->orig_dst);
11686 if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11687 DRM_DEBUG("Cursor dimension not supported\n");
11691 stride = roundup_pow_of_two(crtc_w) * 4;
11692 if (obj->base.size < stride * crtc_h) {
11693 DRM_DEBUG_KMS("buffer is too small\n");
11697 if (fb == crtc->cursor->fb)
11700 /* we only need to pin inside GTT if cursor is non-phy */
11701 mutex_lock(&dev->struct_mutex);
11702 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11703 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11706 mutex_unlock(&dev->struct_mutex);
11712 intel_commit_cursor_plane(struct drm_plane *plane,
11713 struct intel_plane_state *state)
11715 struct drm_crtc *crtc = state->crtc;
11716 struct drm_framebuffer *fb = state->fb;
11717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11718 struct intel_plane *intel_plane = to_intel_plane(plane);
11719 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11720 struct drm_i915_gem_object *obj = intel_fb->obj;
11721 int crtc_w, crtc_h;
11723 crtc->cursor_x = state->orig_dst.x1;
11724 crtc->cursor_y = state->orig_dst.y1;
11726 intel_plane->crtc_x = state->orig_dst.x1;
11727 intel_plane->crtc_y = state->orig_dst.y1;
11728 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11729 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11730 intel_plane->src_x = state->orig_src.x1;
11731 intel_plane->src_y = state->orig_src.y1;
11732 intel_plane->src_w = drm_rect_width(&state->orig_src);
11733 intel_plane->src_h = drm_rect_height(&state->orig_src);
11734 intel_plane->obj = obj;
11736 if (fb != crtc->cursor->fb) {
11737 crtc_w = drm_rect_width(&state->orig_dst);
11738 crtc_h = drm_rect_height(&state->orig_dst);
11739 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11741 intel_crtc_update_cursor(crtc, state->visible);
11743 intel_frontbuffer_flip(crtc->dev,
11744 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11751 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11752 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11753 unsigned int crtc_w, unsigned int crtc_h,
11754 uint32_t src_x, uint32_t src_y,
11755 uint32_t src_w, uint32_t src_h)
11757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11758 struct intel_plane_state state;
11764 /* sample coordinates in 16.16 fixed point */
11765 state.src.x1 = src_x;
11766 state.src.x2 = src_x + src_w;
11767 state.src.y1 = src_y;
11768 state.src.y2 = src_y + src_h;
11770 /* integer pixels */
11771 state.dst.x1 = crtc_x;
11772 state.dst.x2 = crtc_x + crtc_w;
11773 state.dst.y1 = crtc_y;
11774 state.dst.y2 = crtc_y + crtc_h;
11778 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11779 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11781 state.orig_src = state.src;
11782 state.orig_dst = state.dst;
11784 ret = intel_check_cursor_plane(plane, &state);
11788 return intel_commit_cursor_plane(plane, &state);
11791 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11792 .update_plane = intel_cursor_plane_update,
11793 .disable_plane = intel_cursor_plane_disable,
11794 .destroy = intel_plane_destroy,
11795 .set_property = intel_plane_set_property,
11798 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11801 struct intel_plane *cursor;
11803 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11804 if (cursor == NULL)
11807 cursor->can_scale = false;
11808 cursor->max_downscale = 1;
11809 cursor->pipe = pipe;
11810 cursor->plane = pipe;
11811 cursor->rotation = BIT(DRM_ROTATE_0);
11813 drm_universal_plane_init(dev, &cursor->base, 0,
11814 &intel_cursor_plane_funcs,
11815 intel_cursor_formats,
11816 ARRAY_SIZE(intel_cursor_formats),
11817 DRM_PLANE_TYPE_CURSOR);
11819 if (INTEL_INFO(dev)->gen >= 4) {
11820 if (!dev->mode_config.rotation_property)
11821 dev->mode_config.rotation_property =
11822 drm_mode_create_rotation_property(dev,
11823 BIT(DRM_ROTATE_0) |
11824 BIT(DRM_ROTATE_180));
11825 if (dev->mode_config.rotation_property)
11826 drm_object_attach_property(&cursor->base.base,
11827 dev->mode_config.rotation_property,
11831 return &cursor->base;
11834 static void intel_crtc_init(struct drm_device *dev, int pipe)
11836 struct drm_i915_private *dev_priv = dev->dev_private;
11837 struct intel_crtc *intel_crtc;
11838 struct drm_plane *primary = NULL;
11839 struct drm_plane *cursor = NULL;
11842 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11843 if (intel_crtc == NULL)
11846 primary = intel_primary_plane_create(dev, pipe);
11850 cursor = intel_cursor_plane_create(dev, pipe);
11854 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11855 cursor, &intel_crtc_funcs);
11859 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11860 for (i = 0; i < 256; i++) {
11861 intel_crtc->lut_r[i] = i;
11862 intel_crtc->lut_g[i] = i;
11863 intel_crtc->lut_b[i] = i;
11867 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11868 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11870 intel_crtc->pipe = pipe;
11871 intel_crtc->plane = pipe;
11872 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11873 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11874 intel_crtc->plane = !pipe;
11877 intel_crtc->cursor_base = ~0;
11878 intel_crtc->cursor_cntl = ~0;
11879 intel_crtc->cursor_size = ~0;
11881 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11882 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11883 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11884 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11886 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11888 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11893 drm_plane_cleanup(primary);
11895 drm_plane_cleanup(cursor);
11899 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11901 struct drm_encoder *encoder = connector->base.encoder;
11902 struct drm_device *dev = connector->base.dev;
11904 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11907 return INVALID_PIPE;
11909 return to_intel_crtc(encoder->crtc)->pipe;
11912 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11913 struct drm_file *file)
11915 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11916 struct drm_crtc *drmmode_crtc;
11917 struct intel_crtc *crtc;
11919 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11922 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11924 if (!drmmode_crtc) {
11925 DRM_ERROR("no such CRTC id\n");
11929 crtc = to_intel_crtc(drmmode_crtc);
11930 pipe_from_crtc_id->pipe = crtc->pipe;
11935 static int intel_encoder_clones(struct intel_encoder *encoder)
11937 struct drm_device *dev = encoder->base.dev;
11938 struct intel_encoder *source_encoder;
11939 int index_mask = 0;
11942 for_each_intel_encoder(dev, source_encoder) {
11943 if (encoders_cloneable(encoder, source_encoder))
11944 index_mask |= (1 << entry);
11952 static bool has_edp_a(struct drm_device *dev)
11954 struct drm_i915_private *dev_priv = dev->dev_private;
11956 if (!IS_MOBILE(dev))
11959 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11962 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11968 const char *intel_output_name(int output)
11970 static const char *names[] = {
11971 [INTEL_OUTPUT_UNUSED] = "Unused",
11972 [INTEL_OUTPUT_ANALOG] = "Analog",
11973 [INTEL_OUTPUT_DVO] = "DVO",
11974 [INTEL_OUTPUT_SDVO] = "SDVO",
11975 [INTEL_OUTPUT_LVDS] = "LVDS",
11976 [INTEL_OUTPUT_TVOUT] = "TV",
11977 [INTEL_OUTPUT_HDMI] = "HDMI",
11978 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11979 [INTEL_OUTPUT_EDP] = "eDP",
11980 [INTEL_OUTPUT_DSI] = "DSI",
11981 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11984 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11987 return names[output];
11990 static bool intel_crt_present(struct drm_device *dev)
11992 struct drm_i915_private *dev_priv = dev->dev_private;
11994 if (INTEL_INFO(dev)->gen >= 9)
11997 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12000 if (IS_CHERRYVIEW(dev))
12003 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12009 static void intel_setup_outputs(struct drm_device *dev)
12011 struct drm_i915_private *dev_priv = dev->dev_private;
12012 struct intel_encoder *encoder;
12013 bool dpd_is_edp = false;
12015 intel_lvds_init(dev);
12017 if (intel_crt_present(dev))
12018 intel_crt_init(dev);
12020 if (HAS_DDI(dev)) {
12023 /* Haswell uses DDI functions to detect digital outputs */
12024 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12025 /* DDI A only supports eDP */
12027 intel_ddi_init(dev, PORT_A);
12029 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12031 found = I915_READ(SFUSE_STRAP);
12033 if (found & SFUSE_STRAP_DDIB_DETECTED)
12034 intel_ddi_init(dev, PORT_B);
12035 if (found & SFUSE_STRAP_DDIC_DETECTED)
12036 intel_ddi_init(dev, PORT_C);
12037 if (found & SFUSE_STRAP_DDID_DETECTED)
12038 intel_ddi_init(dev, PORT_D);
12039 } else if (HAS_PCH_SPLIT(dev)) {
12041 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12043 if (has_edp_a(dev))
12044 intel_dp_init(dev, DP_A, PORT_A);
12046 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12047 /* PCH SDVOB multiplex with HDMIB */
12048 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12050 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12051 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12052 intel_dp_init(dev, PCH_DP_B, PORT_B);
12055 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12056 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12058 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12059 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12061 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12062 intel_dp_init(dev, PCH_DP_C, PORT_C);
12064 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12065 intel_dp_init(dev, PCH_DP_D, PORT_D);
12066 } else if (IS_VALLEYVIEW(dev)) {
12068 * The DP_DETECTED bit is the latched state of the DDC
12069 * SDA pin at boot. However since eDP doesn't require DDC
12070 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12071 * eDP ports may have been muxed to an alternate function.
12072 * Thus we can't rely on the DP_DETECTED bit alone to detect
12073 * eDP ports. Consult the VBT as well as DP_DETECTED to
12074 * detect eDP ports.
12076 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12077 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12079 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12080 intel_dp_is_edp(dev, PORT_B))
12081 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12083 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12084 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12086 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12087 intel_dp_is_edp(dev, PORT_C))
12088 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12090 if (IS_CHERRYVIEW(dev)) {
12091 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12092 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12094 /* eDP not supported on port D, so don't check VBT */
12095 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12096 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12099 intel_dsi_init(dev);
12100 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12101 bool found = false;
12103 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12104 DRM_DEBUG_KMS("probing SDVOB\n");
12105 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12106 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12107 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12108 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12111 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12112 intel_dp_init(dev, DP_B, PORT_B);
12115 /* Before G4X SDVOC doesn't have its own detect register */
12117 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12118 DRM_DEBUG_KMS("probing SDVOC\n");
12119 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12122 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12124 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12125 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12126 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12128 if (SUPPORTS_INTEGRATED_DP(dev))
12129 intel_dp_init(dev, DP_C, PORT_C);
12132 if (SUPPORTS_INTEGRATED_DP(dev) &&
12133 (I915_READ(DP_D) & DP_DETECTED))
12134 intel_dp_init(dev, DP_D, PORT_D);
12135 } else if (IS_GEN2(dev))
12136 intel_dvo_init(dev);
12138 if (SUPPORTS_TV(dev))
12139 intel_tv_init(dev);
12141 intel_edp_psr_init(dev);
12143 for_each_intel_encoder(dev, encoder) {
12144 encoder->base.possible_crtcs = encoder->crtc_mask;
12145 encoder->base.possible_clones =
12146 intel_encoder_clones(encoder);
12149 intel_init_pch_refclk(dev);
12151 drm_helper_move_panel_connectors_to_head(dev);
12154 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12156 struct drm_device *dev = fb->dev;
12157 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12159 drm_framebuffer_cleanup(fb);
12160 mutex_lock(&dev->struct_mutex);
12161 WARN_ON(!intel_fb->obj->framebuffer_references--);
12162 drm_gem_object_unreference(&intel_fb->obj->base);
12163 mutex_unlock(&dev->struct_mutex);
12167 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12168 struct drm_file *file,
12169 unsigned int *handle)
12171 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12172 struct drm_i915_gem_object *obj = intel_fb->obj;
12174 return drm_gem_handle_create(file, &obj->base, handle);
12177 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12178 .destroy = intel_user_framebuffer_destroy,
12179 .create_handle = intel_user_framebuffer_create_handle,
12182 static int intel_framebuffer_init(struct drm_device *dev,
12183 struct intel_framebuffer *intel_fb,
12184 struct drm_mode_fb_cmd2 *mode_cmd,
12185 struct drm_i915_gem_object *obj)
12187 int aligned_height;
12191 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12193 if (obj->tiling_mode == I915_TILING_Y) {
12194 DRM_DEBUG("hardware does not support tiling Y\n");
12198 if (mode_cmd->pitches[0] & 63) {
12199 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12200 mode_cmd->pitches[0]);
12204 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12205 pitch_limit = 32*1024;
12206 } else if (INTEL_INFO(dev)->gen >= 4) {
12207 if (obj->tiling_mode)
12208 pitch_limit = 16*1024;
12210 pitch_limit = 32*1024;
12211 } else if (INTEL_INFO(dev)->gen >= 3) {
12212 if (obj->tiling_mode)
12213 pitch_limit = 8*1024;
12215 pitch_limit = 16*1024;
12217 /* XXX DSPC is limited to 4k tiled */
12218 pitch_limit = 8*1024;
12220 if (mode_cmd->pitches[0] > pitch_limit) {
12221 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12222 obj->tiling_mode ? "tiled" : "linear",
12223 mode_cmd->pitches[0], pitch_limit);
12227 if (obj->tiling_mode != I915_TILING_NONE &&
12228 mode_cmd->pitches[0] != obj->stride) {
12229 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12230 mode_cmd->pitches[0], obj->stride);
12234 /* Reject formats not supported by any plane early. */
12235 switch (mode_cmd->pixel_format) {
12236 case DRM_FORMAT_C8:
12237 case DRM_FORMAT_RGB565:
12238 case DRM_FORMAT_XRGB8888:
12239 case DRM_FORMAT_ARGB8888:
12241 case DRM_FORMAT_XRGB1555:
12242 case DRM_FORMAT_ARGB1555:
12243 if (INTEL_INFO(dev)->gen > 3) {
12244 DRM_DEBUG("unsupported pixel format: %s\n",
12245 drm_get_format_name(mode_cmd->pixel_format));
12249 case DRM_FORMAT_XBGR8888:
12250 case DRM_FORMAT_ABGR8888:
12251 case DRM_FORMAT_XRGB2101010:
12252 case DRM_FORMAT_ARGB2101010:
12253 case DRM_FORMAT_XBGR2101010:
12254 case DRM_FORMAT_ABGR2101010:
12255 if (INTEL_INFO(dev)->gen < 4) {
12256 DRM_DEBUG("unsupported pixel format: %s\n",
12257 drm_get_format_name(mode_cmd->pixel_format));
12261 case DRM_FORMAT_YUYV:
12262 case DRM_FORMAT_UYVY:
12263 case DRM_FORMAT_YVYU:
12264 case DRM_FORMAT_VYUY:
12265 if (INTEL_INFO(dev)->gen < 5) {
12266 DRM_DEBUG("unsupported pixel format: %s\n",
12267 drm_get_format_name(mode_cmd->pixel_format));
12272 DRM_DEBUG("unsupported pixel format: %s\n",
12273 drm_get_format_name(mode_cmd->pixel_format));
12277 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12278 if (mode_cmd->offsets[0] != 0)
12281 aligned_height = intel_align_height(dev, mode_cmd->height,
12283 /* FIXME drm helper for size checks (especially planar formats)? */
12284 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12287 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12288 intel_fb->obj = obj;
12289 intel_fb->obj->framebuffer_references++;
12291 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12293 DRM_ERROR("framebuffer init failed %d\n", ret);
12300 static struct drm_framebuffer *
12301 intel_user_framebuffer_create(struct drm_device *dev,
12302 struct drm_file *filp,
12303 struct drm_mode_fb_cmd2 *mode_cmd)
12305 struct drm_i915_gem_object *obj;
12307 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12308 mode_cmd->handles[0]));
12309 if (&obj->base == NULL)
12310 return ERR_PTR(-ENOENT);
12312 return intel_framebuffer_create(dev, mode_cmd, obj);
12315 #ifndef CONFIG_DRM_I915_FBDEV
12316 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12321 static const struct drm_mode_config_funcs intel_mode_funcs = {
12322 .fb_create = intel_user_framebuffer_create,
12323 .output_poll_changed = intel_fbdev_output_poll_changed,
12326 /* Set up chip specific display functions */
12327 static void intel_init_display(struct drm_device *dev)
12329 struct drm_i915_private *dev_priv = dev->dev_private;
12331 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12332 dev_priv->display.find_dpll = g4x_find_best_dpll;
12333 else if (IS_CHERRYVIEW(dev))
12334 dev_priv->display.find_dpll = chv_find_best_dpll;
12335 else if (IS_VALLEYVIEW(dev))
12336 dev_priv->display.find_dpll = vlv_find_best_dpll;
12337 else if (IS_PINEVIEW(dev))
12338 dev_priv->display.find_dpll = pnv_find_best_dpll;
12340 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12342 if (HAS_DDI(dev)) {
12343 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12344 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12345 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12346 dev_priv->display.crtc_enable = haswell_crtc_enable;
12347 dev_priv->display.crtc_disable = haswell_crtc_disable;
12348 dev_priv->display.off = ironlake_crtc_off;
12349 if (INTEL_INFO(dev)->gen >= 9)
12350 dev_priv->display.update_primary_plane =
12351 skylake_update_primary_plane;
12353 dev_priv->display.update_primary_plane =
12354 ironlake_update_primary_plane;
12355 } else if (HAS_PCH_SPLIT(dev)) {
12356 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12357 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12358 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12359 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12360 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12361 dev_priv->display.off = ironlake_crtc_off;
12362 dev_priv->display.update_primary_plane =
12363 ironlake_update_primary_plane;
12364 } else if (IS_VALLEYVIEW(dev)) {
12365 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12366 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12367 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12368 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12369 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12370 dev_priv->display.off = i9xx_crtc_off;
12371 dev_priv->display.update_primary_plane =
12372 i9xx_update_primary_plane;
12374 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12375 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12376 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12377 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12378 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12379 dev_priv->display.off = i9xx_crtc_off;
12380 dev_priv->display.update_primary_plane =
12381 i9xx_update_primary_plane;
12384 /* Returns the core display clock speed */
12385 if (IS_VALLEYVIEW(dev))
12386 dev_priv->display.get_display_clock_speed =
12387 valleyview_get_display_clock_speed;
12388 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12389 dev_priv->display.get_display_clock_speed =
12390 i945_get_display_clock_speed;
12391 else if (IS_I915G(dev))
12392 dev_priv->display.get_display_clock_speed =
12393 i915_get_display_clock_speed;
12394 else if (IS_I945GM(dev) || IS_845G(dev))
12395 dev_priv->display.get_display_clock_speed =
12396 i9xx_misc_get_display_clock_speed;
12397 else if (IS_PINEVIEW(dev))
12398 dev_priv->display.get_display_clock_speed =
12399 pnv_get_display_clock_speed;
12400 else if (IS_I915GM(dev))
12401 dev_priv->display.get_display_clock_speed =
12402 i915gm_get_display_clock_speed;
12403 else if (IS_I865G(dev))
12404 dev_priv->display.get_display_clock_speed =
12405 i865_get_display_clock_speed;
12406 else if (IS_I85X(dev))
12407 dev_priv->display.get_display_clock_speed =
12408 i855_get_display_clock_speed;
12409 else /* 852, 830 */
12410 dev_priv->display.get_display_clock_speed =
12411 i830_get_display_clock_speed;
12413 if (IS_GEN5(dev)) {
12414 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12415 } else if (IS_GEN6(dev)) {
12416 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12417 dev_priv->display.modeset_global_resources =
12418 snb_modeset_global_resources;
12419 } else if (IS_IVYBRIDGE(dev)) {
12420 /* FIXME: detect B0+ stepping and use auto training */
12421 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12422 dev_priv->display.modeset_global_resources =
12423 ivb_modeset_global_resources;
12424 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12425 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12426 dev_priv->display.modeset_global_resources =
12427 haswell_modeset_global_resources;
12428 } else if (IS_VALLEYVIEW(dev)) {
12429 dev_priv->display.modeset_global_resources =
12430 valleyview_modeset_global_resources;
12431 } else if (INTEL_INFO(dev)->gen >= 9) {
12432 dev_priv->display.modeset_global_resources =
12433 haswell_modeset_global_resources;
12436 /* Default just returns -ENODEV to indicate unsupported */
12437 dev_priv->display.queue_flip = intel_default_queue_flip;
12439 switch (INTEL_INFO(dev)->gen) {
12441 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12445 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12450 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12454 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12457 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12458 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12462 intel_panel_init_backlight_funcs(dev);
12464 mutex_init(&dev_priv->pps_mutex);
12468 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12469 * resume, or other times. This quirk makes sure that's the case for
12470 * affected systems.
12472 static void quirk_pipea_force(struct drm_device *dev)
12474 struct drm_i915_private *dev_priv = dev->dev_private;
12476 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12477 DRM_INFO("applying pipe a force quirk\n");
12480 static void quirk_pipeb_force(struct drm_device *dev)
12482 struct drm_i915_private *dev_priv = dev->dev_private;
12484 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12485 DRM_INFO("applying pipe b force quirk\n");
12489 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12491 static void quirk_ssc_force_disable(struct drm_device *dev)
12493 struct drm_i915_private *dev_priv = dev->dev_private;
12494 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12495 DRM_INFO("applying lvds SSC disable quirk\n");
12499 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12502 static void quirk_invert_brightness(struct drm_device *dev)
12504 struct drm_i915_private *dev_priv = dev->dev_private;
12505 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12506 DRM_INFO("applying inverted panel brightness quirk\n");
12509 /* Some VBT's incorrectly indicate no backlight is present */
12510 static void quirk_backlight_present(struct drm_device *dev)
12512 struct drm_i915_private *dev_priv = dev->dev_private;
12513 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12514 DRM_INFO("applying backlight present quirk\n");
12517 struct intel_quirk {
12519 int subsystem_vendor;
12520 int subsystem_device;
12521 void (*hook)(struct drm_device *dev);
12524 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12525 struct intel_dmi_quirk {
12526 void (*hook)(struct drm_device *dev);
12527 const struct dmi_system_id (*dmi_id_list)[];
12530 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12532 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12536 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12538 .dmi_id_list = &(const struct dmi_system_id[]) {
12540 .callback = intel_dmi_reverse_brightness,
12541 .ident = "NCR Corporation",
12542 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12543 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12546 { } /* terminating entry */
12548 .hook = quirk_invert_brightness,
12552 static struct intel_quirk intel_quirks[] = {
12553 /* HP Mini needs pipe A force quirk (LP: #322104) */
12554 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12556 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12557 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12559 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12560 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12562 /* 830 needs to leave pipe A & dpll A up */
12563 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12565 /* 830 needs to leave pipe B & dpll B up */
12566 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12568 /* Lenovo U160 cannot use SSC on LVDS */
12569 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12571 /* Sony Vaio Y cannot use SSC on LVDS */
12572 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12574 /* Acer Aspire 5734Z must invert backlight brightness */
12575 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12577 /* Acer/eMachines G725 */
12578 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12580 /* Acer/eMachines e725 */
12581 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12583 /* Acer/Packard Bell NCL20 */
12584 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12586 /* Acer Aspire 4736Z */
12587 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12589 /* Acer Aspire 5336 */
12590 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12592 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12593 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12595 /* Acer C720 Chromebook (Core i3 4005U) */
12596 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12598 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12599 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12601 /* HP Chromebook 14 (Celeron 2955U) */
12602 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12605 static void intel_init_quirks(struct drm_device *dev)
12607 struct pci_dev *d = dev->pdev;
12610 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12611 struct intel_quirk *q = &intel_quirks[i];
12613 if (d->device == q->device &&
12614 (d->subsystem_vendor == q->subsystem_vendor ||
12615 q->subsystem_vendor == PCI_ANY_ID) &&
12616 (d->subsystem_device == q->subsystem_device ||
12617 q->subsystem_device == PCI_ANY_ID))
12620 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12621 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12622 intel_dmi_quirks[i].hook(dev);
12626 /* Disable the VGA plane that we never use */
12627 static void i915_disable_vga(struct drm_device *dev)
12629 struct drm_i915_private *dev_priv = dev->dev_private;
12631 u32 vga_reg = i915_vgacntrl_reg(dev);
12633 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12634 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12635 outb(SR01, VGA_SR_INDEX);
12636 sr1 = inb(VGA_SR_DATA);
12637 outb(sr1 | 1<<5, VGA_SR_DATA);
12638 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12642 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12643 * from S3 without preserving (some of?) the other bits.
12645 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12646 POSTING_READ(vga_reg);
12649 void intel_modeset_init_hw(struct drm_device *dev)
12651 intel_prepare_ddi(dev);
12653 if (IS_VALLEYVIEW(dev))
12654 vlv_update_cdclk(dev);
12656 intel_init_clock_gating(dev);
12658 intel_enable_gt_powersave(dev);
12661 void intel_modeset_init(struct drm_device *dev)
12663 struct drm_i915_private *dev_priv = dev->dev_private;
12666 struct intel_crtc *crtc;
12668 drm_mode_config_init(dev);
12670 dev->mode_config.min_width = 0;
12671 dev->mode_config.min_height = 0;
12673 dev->mode_config.preferred_depth = 24;
12674 dev->mode_config.prefer_shadow = 1;
12676 dev->mode_config.funcs = &intel_mode_funcs;
12678 intel_init_quirks(dev);
12680 intel_init_pm(dev);
12682 if (INTEL_INFO(dev)->num_pipes == 0)
12685 intel_init_display(dev);
12686 intel_init_audio(dev);
12688 if (IS_GEN2(dev)) {
12689 dev->mode_config.max_width = 2048;
12690 dev->mode_config.max_height = 2048;
12691 } else if (IS_GEN3(dev)) {
12692 dev->mode_config.max_width = 4096;
12693 dev->mode_config.max_height = 4096;
12695 dev->mode_config.max_width = 8192;
12696 dev->mode_config.max_height = 8192;
12699 if (IS_845G(dev) || IS_I865G(dev)) {
12700 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12701 dev->mode_config.cursor_height = 1023;
12702 } else if (IS_GEN2(dev)) {
12703 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12704 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12706 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12707 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12710 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12712 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12713 INTEL_INFO(dev)->num_pipes,
12714 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12716 for_each_pipe(dev_priv, pipe) {
12717 intel_crtc_init(dev, pipe);
12718 for_each_sprite(pipe, sprite) {
12719 ret = intel_plane_init(dev, pipe, sprite);
12721 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12722 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12726 intel_init_dpio(dev);
12728 intel_shared_dpll_init(dev);
12730 /* save the BIOS value before clobbering it */
12731 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12732 /* Just disable it once at startup */
12733 i915_disable_vga(dev);
12734 intel_setup_outputs(dev);
12736 /* Just in case the BIOS is doing something questionable. */
12737 intel_disable_fbc(dev);
12739 drm_modeset_lock_all(dev);
12740 intel_modeset_setup_hw_state(dev, false);
12741 drm_modeset_unlock_all(dev);
12743 for_each_intel_crtc(dev, crtc) {
12748 * Note that reserving the BIOS fb up front prevents us
12749 * from stuffing other stolen allocations like the ring
12750 * on top. This prevents some ugliness at boot time, and
12751 * can even allow for smooth boot transitions if the BIOS
12752 * fb is large enough for the active pipe configuration.
12754 if (dev_priv->display.get_plane_config) {
12755 dev_priv->display.get_plane_config(crtc,
12756 &crtc->plane_config);
12758 * If the fb is shared between multiple heads, we'll
12759 * just get the first one.
12761 intel_find_plane_obj(crtc, &crtc->plane_config);
12766 static void intel_enable_pipe_a(struct drm_device *dev)
12768 struct intel_connector *connector;
12769 struct drm_connector *crt = NULL;
12770 struct intel_load_detect_pipe load_detect_temp;
12771 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12773 /* We can't just switch on the pipe A, we need to set things up with a
12774 * proper mode and output configuration. As a gross hack, enable pipe A
12775 * by enabling the load detect pipe once. */
12776 list_for_each_entry(connector,
12777 &dev->mode_config.connector_list,
12779 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12780 crt = &connector->base;
12788 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12789 intel_release_load_detect_pipe(crt, &load_detect_temp);
12793 intel_check_plane_mapping(struct intel_crtc *crtc)
12795 struct drm_device *dev = crtc->base.dev;
12796 struct drm_i915_private *dev_priv = dev->dev_private;
12799 if (INTEL_INFO(dev)->num_pipes == 1)
12802 reg = DSPCNTR(!crtc->plane);
12803 val = I915_READ(reg);
12805 if ((val & DISPLAY_PLANE_ENABLE) &&
12806 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12812 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12814 struct drm_device *dev = crtc->base.dev;
12815 struct drm_i915_private *dev_priv = dev->dev_private;
12818 /* Clear any frame start delays used for debugging left by the BIOS */
12819 reg = PIPECONF(crtc->config.cpu_transcoder);
12820 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12822 /* restore vblank interrupts to correct state */
12823 if (crtc->active) {
12824 update_scanline_offset(crtc);
12825 drm_vblank_on(dev, crtc->pipe);
12827 drm_vblank_off(dev, crtc->pipe);
12829 /* We need to sanitize the plane -> pipe mapping first because this will
12830 * disable the crtc (and hence change the state) if it is wrong. Note
12831 * that gen4+ has a fixed plane -> pipe mapping. */
12832 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12833 struct intel_connector *connector;
12836 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12837 crtc->base.base.id);
12839 /* Pipe has the wrong plane attached and the plane is active.
12840 * Temporarily change the plane mapping and disable everything
12842 plane = crtc->plane;
12843 crtc->plane = !plane;
12844 crtc->primary_enabled = true;
12845 dev_priv->display.crtc_disable(&crtc->base);
12846 crtc->plane = plane;
12848 /* ... and break all links. */
12849 list_for_each_entry(connector, &dev->mode_config.connector_list,
12851 if (connector->encoder->base.crtc != &crtc->base)
12854 connector->base.dpms = DRM_MODE_DPMS_OFF;
12855 connector->base.encoder = NULL;
12857 /* multiple connectors may have the same encoder:
12858 * handle them and break crtc link separately */
12859 list_for_each_entry(connector, &dev->mode_config.connector_list,
12861 if (connector->encoder->base.crtc == &crtc->base) {
12862 connector->encoder->base.crtc = NULL;
12863 connector->encoder->connectors_active = false;
12866 WARN_ON(crtc->active);
12867 crtc->base.enabled = false;
12870 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12871 crtc->pipe == PIPE_A && !crtc->active) {
12872 /* BIOS forgot to enable pipe A, this mostly happens after
12873 * resume. Force-enable the pipe to fix this, the update_dpms
12874 * call below we restore the pipe to the right state, but leave
12875 * the required bits on. */
12876 intel_enable_pipe_a(dev);
12879 /* Adjust the state of the output pipe according to whether we
12880 * have active connectors/encoders. */
12881 intel_crtc_update_dpms(&crtc->base);
12883 if (crtc->active != crtc->base.enabled) {
12884 struct intel_encoder *encoder;
12886 /* This can happen either due to bugs in the get_hw_state
12887 * functions or because the pipe is force-enabled due to the
12889 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12890 crtc->base.base.id,
12891 crtc->base.enabled ? "enabled" : "disabled",
12892 crtc->active ? "enabled" : "disabled");
12894 crtc->base.enabled = crtc->active;
12896 /* Because we only establish the connector -> encoder ->
12897 * crtc links if something is active, this means the
12898 * crtc is now deactivated. Break the links. connector
12899 * -> encoder links are only establish when things are
12900 * actually up, hence no need to break them. */
12901 WARN_ON(crtc->active);
12903 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12904 WARN_ON(encoder->connectors_active);
12905 encoder->base.crtc = NULL;
12909 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
12911 * We start out with underrun reporting disabled to avoid races.
12912 * For correct bookkeeping mark this on active crtcs.
12914 * Also on gmch platforms we dont have any hardware bits to
12915 * disable the underrun reporting. Which means we need to start
12916 * out with underrun reporting disabled also on inactive pipes,
12917 * since otherwise we'll complain about the garbage we read when
12918 * e.g. coming up after runtime pm.
12920 * No protection against concurrent access is required - at
12921 * worst a fifo underrun happens which also sets this to false.
12923 crtc->cpu_fifo_underrun_disabled = true;
12924 crtc->pch_fifo_underrun_disabled = true;
12928 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12930 struct intel_connector *connector;
12931 struct drm_device *dev = encoder->base.dev;
12933 /* We need to check both for a crtc link (meaning that the
12934 * encoder is active and trying to read from a pipe) and the
12935 * pipe itself being active. */
12936 bool has_active_crtc = encoder->base.crtc &&
12937 to_intel_crtc(encoder->base.crtc)->active;
12939 if (encoder->connectors_active && !has_active_crtc) {
12940 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12941 encoder->base.base.id,
12942 encoder->base.name);
12944 /* Connector is active, but has no active pipe. This is
12945 * fallout from our resume register restoring. Disable
12946 * the encoder manually again. */
12947 if (encoder->base.crtc) {
12948 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12949 encoder->base.base.id,
12950 encoder->base.name);
12951 encoder->disable(encoder);
12952 if (encoder->post_disable)
12953 encoder->post_disable(encoder);
12955 encoder->base.crtc = NULL;
12956 encoder->connectors_active = false;
12958 /* Inconsistent output/port/pipe state happens presumably due to
12959 * a bug in one of the get_hw_state functions. Or someplace else
12960 * in our code, like the register restore mess on resume. Clamp
12961 * things to off as a safer default. */
12962 list_for_each_entry(connector,
12963 &dev->mode_config.connector_list,
12965 if (connector->encoder != encoder)
12967 connector->base.dpms = DRM_MODE_DPMS_OFF;
12968 connector->base.encoder = NULL;
12971 /* Enabled encoders without active connectors will be fixed in
12972 * the crtc fixup. */
12975 void i915_redisable_vga_power_on(struct drm_device *dev)
12977 struct drm_i915_private *dev_priv = dev->dev_private;
12978 u32 vga_reg = i915_vgacntrl_reg(dev);
12980 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12981 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12982 i915_disable_vga(dev);
12986 void i915_redisable_vga(struct drm_device *dev)
12988 struct drm_i915_private *dev_priv = dev->dev_private;
12990 /* This function can be called both from intel_modeset_setup_hw_state or
12991 * at a very early point in our resume sequence, where the power well
12992 * structures are not yet restored. Since this function is at a very
12993 * paranoid "someone might have enabled VGA while we were not looking"
12994 * level, just check if the power well is enabled instead of trying to
12995 * follow the "don't touch the power well if we don't need it" policy
12996 * the rest of the driver uses. */
12997 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13000 i915_redisable_vga_power_on(dev);
13003 static bool primary_get_hw_state(struct intel_crtc *crtc)
13005 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13010 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13013 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13015 struct drm_i915_private *dev_priv = dev->dev_private;
13017 struct intel_crtc *crtc;
13018 struct intel_encoder *encoder;
13019 struct intel_connector *connector;
13022 for_each_intel_crtc(dev, crtc) {
13023 memset(&crtc->config, 0, sizeof(crtc->config));
13025 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13027 crtc->active = dev_priv->display.get_pipe_config(crtc,
13030 crtc->base.enabled = crtc->active;
13031 crtc->primary_enabled = primary_get_hw_state(crtc);
13033 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13034 crtc->base.base.id,
13035 crtc->active ? "enabled" : "disabled");
13038 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13039 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13041 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13043 for_each_intel_crtc(dev, crtc) {
13044 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13047 pll->refcount = pll->active;
13049 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13050 pll->name, pll->refcount, pll->on);
13053 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13056 for_each_intel_encoder(dev, encoder) {
13059 if (encoder->get_hw_state(encoder, &pipe)) {
13060 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13061 encoder->base.crtc = &crtc->base;
13062 encoder->get_config(encoder, &crtc->config);
13064 encoder->base.crtc = NULL;
13067 encoder->connectors_active = false;
13068 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13069 encoder->base.base.id,
13070 encoder->base.name,
13071 encoder->base.crtc ? "enabled" : "disabled",
13075 list_for_each_entry(connector, &dev->mode_config.connector_list,
13077 if (connector->get_hw_state(connector)) {
13078 connector->base.dpms = DRM_MODE_DPMS_ON;
13079 connector->encoder->connectors_active = true;
13080 connector->base.encoder = &connector->encoder->base;
13082 connector->base.dpms = DRM_MODE_DPMS_OFF;
13083 connector->base.encoder = NULL;
13085 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13086 connector->base.base.id,
13087 connector->base.name,
13088 connector->base.encoder ? "enabled" : "disabled");
13092 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13093 * and i915 state tracking structures. */
13094 void intel_modeset_setup_hw_state(struct drm_device *dev,
13095 bool force_restore)
13097 struct drm_i915_private *dev_priv = dev->dev_private;
13099 struct intel_crtc *crtc;
13100 struct intel_encoder *encoder;
13103 intel_modeset_readout_hw_state(dev);
13106 * Now that we have the config, copy it to each CRTC struct
13107 * Note that this could go away if we move to using crtc_config
13108 * checking everywhere.
13110 for_each_intel_crtc(dev, crtc) {
13111 if (crtc->active && i915.fastboot) {
13112 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13113 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13114 crtc->base.base.id);
13115 drm_mode_debug_printmodeline(&crtc->base.mode);
13119 /* HW state is read out, now we need to sanitize this mess. */
13120 for_each_intel_encoder(dev, encoder) {
13121 intel_sanitize_encoder(encoder);
13124 for_each_pipe(dev_priv, pipe) {
13125 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13126 intel_sanitize_crtc(crtc);
13127 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13130 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13131 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13133 if (!pll->on || pll->active)
13136 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13138 pll->disable(dev_priv, pll);
13142 if (HAS_PCH_SPLIT(dev))
13143 ilk_wm_get_hw_state(dev);
13145 if (force_restore) {
13146 i915_redisable_vga(dev);
13149 * We need to use raw interfaces for restoring state to avoid
13150 * checking (bogus) intermediate states.
13152 for_each_pipe(dev_priv, pipe) {
13153 struct drm_crtc *crtc =
13154 dev_priv->pipe_to_crtc_mapping[pipe];
13156 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13157 crtc->primary->fb);
13160 intel_modeset_update_staged_output_state(dev);
13163 intel_modeset_check_state(dev);
13166 void intel_modeset_gem_init(struct drm_device *dev)
13168 struct drm_crtc *c;
13169 struct drm_i915_gem_object *obj;
13171 mutex_lock(&dev->struct_mutex);
13172 intel_init_gt_powersave(dev);
13173 mutex_unlock(&dev->struct_mutex);
13175 intel_modeset_init_hw(dev);
13177 intel_setup_overlay(dev);
13180 * Make sure any fbs we allocated at startup are properly
13181 * pinned & fenced. When we do the allocation it's too early
13184 mutex_lock(&dev->struct_mutex);
13185 for_each_crtc(dev, c) {
13186 obj = intel_fb_obj(c->primary->fb);
13190 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13191 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13192 to_intel_crtc(c)->pipe);
13193 drm_framebuffer_unreference(c->primary->fb);
13194 c->primary->fb = NULL;
13197 mutex_unlock(&dev->struct_mutex);
13200 void intel_connector_unregister(struct intel_connector *intel_connector)
13202 struct drm_connector *connector = &intel_connector->base;
13204 intel_panel_destroy_backlight(connector);
13205 drm_connector_unregister(connector);
13208 void intel_modeset_cleanup(struct drm_device *dev)
13210 struct drm_i915_private *dev_priv = dev->dev_private;
13211 struct drm_connector *connector;
13214 * Interrupts and polling as the first thing to avoid creating havoc.
13215 * Too much stuff here (turning of rps, connectors, ...) would
13216 * experience fancy races otherwise.
13218 intel_irq_uninstall(dev_priv);
13221 * Due to the hpd irq storm handling the hotplug work can re-arm the
13222 * poll handlers. Hence disable polling after hpd handling is shut down.
13224 drm_kms_helper_poll_fini(dev);
13226 mutex_lock(&dev->struct_mutex);
13228 intel_unregister_dsm_handler();
13230 intel_disable_fbc(dev);
13232 intel_disable_gt_powersave(dev);
13234 ironlake_teardown_rc6(dev);
13236 mutex_unlock(&dev->struct_mutex);
13238 /* flush any delayed tasks or pending work */
13239 flush_scheduled_work();
13241 /* destroy the backlight and sysfs files before encoders/connectors */
13242 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13243 struct intel_connector *intel_connector;
13245 intel_connector = to_intel_connector(connector);
13246 intel_connector->unregister(intel_connector);
13249 drm_mode_config_cleanup(dev);
13251 intel_cleanup_overlay(dev);
13253 mutex_lock(&dev->struct_mutex);
13254 intel_cleanup_gt_powersave(dev);
13255 mutex_unlock(&dev->struct_mutex);
13259 * Return which encoder is currently attached for connector.
13261 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13263 return &intel_attached_encoder(connector)->base;
13266 void intel_connector_attach_encoder(struct intel_connector *connector,
13267 struct intel_encoder *encoder)
13269 connector->encoder = encoder;
13270 drm_mode_connector_attach_encoder(&connector->base,
13275 * set vga decode state - true == enable VGA decode
13277 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13279 struct drm_i915_private *dev_priv = dev->dev_private;
13280 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13283 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13284 DRM_ERROR("failed to read control word\n");
13288 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13292 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13294 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13296 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13297 DRM_ERROR("failed to write control word\n");
13304 struct intel_display_error_state {
13306 u32 power_well_driver;
13308 int num_transcoders;
13310 struct intel_cursor_error_state {
13315 } cursor[I915_MAX_PIPES];
13317 struct intel_pipe_error_state {
13318 bool power_domain_on;
13321 } pipe[I915_MAX_PIPES];
13323 struct intel_plane_error_state {
13331 } plane[I915_MAX_PIPES];
13333 struct intel_transcoder_error_state {
13334 bool power_domain_on;
13335 enum transcoder cpu_transcoder;
13348 struct intel_display_error_state *
13349 intel_display_capture_error_state(struct drm_device *dev)
13351 struct drm_i915_private *dev_priv = dev->dev_private;
13352 struct intel_display_error_state *error;
13353 int transcoders[] = {
13361 if (INTEL_INFO(dev)->num_pipes == 0)
13364 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13368 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13369 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13371 for_each_pipe(dev_priv, i) {
13372 error->pipe[i].power_domain_on =
13373 __intel_display_power_is_enabled(dev_priv,
13374 POWER_DOMAIN_PIPE(i));
13375 if (!error->pipe[i].power_domain_on)
13378 error->cursor[i].control = I915_READ(CURCNTR(i));
13379 error->cursor[i].position = I915_READ(CURPOS(i));
13380 error->cursor[i].base = I915_READ(CURBASE(i));
13382 error->plane[i].control = I915_READ(DSPCNTR(i));
13383 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13384 if (INTEL_INFO(dev)->gen <= 3) {
13385 error->plane[i].size = I915_READ(DSPSIZE(i));
13386 error->plane[i].pos = I915_READ(DSPPOS(i));
13388 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13389 error->plane[i].addr = I915_READ(DSPADDR(i));
13390 if (INTEL_INFO(dev)->gen >= 4) {
13391 error->plane[i].surface = I915_READ(DSPSURF(i));
13392 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13395 error->pipe[i].source = I915_READ(PIPESRC(i));
13397 if (HAS_GMCH_DISPLAY(dev))
13398 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13401 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13402 if (HAS_DDI(dev_priv->dev))
13403 error->num_transcoders++; /* Account for eDP. */
13405 for (i = 0; i < error->num_transcoders; i++) {
13406 enum transcoder cpu_transcoder = transcoders[i];
13408 error->transcoder[i].power_domain_on =
13409 __intel_display_power_is_enabled(dev_priv,
13410 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13411 if (!error->transcoder[i].power_domain_on)
13414 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13416 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13417 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13418 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13419 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13420 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13421 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13422 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13428 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13431 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13432 struct drm_device *dev,
13433 struct intel_display_error_state *error)
13435 struct drm_i915_private *dev_priv = dev->dev_private;
13441 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13442 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13443 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13444 error->power_well_driver);
13445 for_each_pipe(dev_priv, i) {
13446 err_printf(m, "Pipe [%d]:\n", i);
13447 err_printf(m, " Power: %s\n",
13448 error->pipe[i].power_domain_on ? "on" : "off");
13449 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13450 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13452 err_printf(m, "Plane [%d]:\n", i);
13453 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13454 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13455 if (INTEL_INFO(dev)->gen <= 3) {
13456 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13457 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13459 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13460 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13461 if (INTEL_INFO(dev)->gen >= 4) {
13462 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13463 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13466 err_printf(m, "Cursor [%d]:\n", i);
13467 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13468 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13469 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13472 for (i = 0; i < error->num_transcoders; i++) {
13473 err_printf(m, "CPU transcoder: %c\n",
13474 transcoder_name(error->transcoder[i].cpu_transcoder));
13475 err_printf(m, " Power: %s\n",
13476 error->transcoder[i].power_domain_on ? "on" : "off");
13477 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13478 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13479 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13480 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13481 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13482 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13483 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13487 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13489 struct intel_crtc *crtc;
13491 for_each_intel_crtc(dev, crtc) {
13492 struct intel_unpin_work *work;
13494 spin_lock_irq(&dev->event_lock);
13496 work = crtc->unpin_work;
13498 if (work && work->event &&
13499 work->event->base.file_priv == file) {
13500 kfree(work->event);
13501 work->event = NULL;
13504 spin_unlock_irq(&dev->event_lock);