2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *, intel_clock_t *);
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
102 static inline u32 /* units of 100MHz */
103 intel_fdi_link_freq(struct drm_device *dev)
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 static const intel_limit_t intel_limits_i8xx_dvo = {
113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
123 .find_pll = intel_find_best_PLL,
126 static const intel_limit_t intel_limits_i8xx_lvds = {
127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
137 .find_pll = intel_find_best_PLL,
140 static const intel_limit_t intel_limits_i9xx_sdvo = {
141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
151 .find_pll = intel_find_best_PLL,
154 static const intel_limit_t intel_limits_i9xx_lvds = {
155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
169 static const intel_limit_t intel_limits_g4x_sdvo = {
170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
182 .find_pll = intel_g4x_find_best_PLL,
185 static const intel_limit_t intel_limits_g4x_hdmi = {
186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
196 .find_pll = intel_g4x_find_best_PLL,
199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
211 .find_pll = intel_g4x_find_best_PLL,
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
226 .find_pll = intel_g4x_find_best_PLL,
229 static const intel_limit_t intel_limits_g4x_display_port = {
230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
239 .p2_slow = 10, .p2_fast = 10 },
240 .find_pll = intel_find_pll_g4x_dp,
243 static const intel_limit_t intel_limits_pineview_sdvo = {
244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
246 /* Pineview's Ncounter is a ring counter */
247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
249 /* Pineview only has one combined m divider, which we treat as m2. */
250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
256 .find_pll = intel_find_best_PLL,
259 static const intel_limit_t intel_limits_pineview_lvds = {
260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
270 .find_pll = intel_find_best_PLL,
273 /* Ironlake / Sandybridge
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
278 static const intel_limit_t intel_limits_ironlake_dac = {
279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
289 .find_pll = intel_g4x_find_best_PLL,
292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
303 .find_pll = intel_g4x_find_best_PLL,
306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
317 .find_pll = intel_g4x_find_best_PLL,
320 /* LVDS 100mhz refclk limits. */
321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
329 .p1 = { .min = 2, .max = 8 },
330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
332 .find_pll = intel_g4x_find_best_PLL,
335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
343 .p1 = { .min = 2, .max = 6 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
346 .find_pll = intel_g4x_find_best_PLL,
349 static const intel_limit_t intel_limits_ironlake_display_port = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
359 .p2_slow = 10, .p2_fast = 10 },
360 .find_pll = intel_find_pll_ironlake_dp,
363 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
368 /* use the module option value if specified */
369 if (i915_lvds_channel_mode > 0)
370 return i915_lvds_channel_mode == 2;
372 if (dev_priv->lvds_val)
373 val = dev_priv->lvds_val;
375 /* BIOS should set the proper LVDS register value at boot, but
376 * in reality, it doesn't set the value when the lid is closed;
377 * we need to check "the value to be set" in VBT when LVDS
378 * register is uninitialized.
380 val = I915_READ(reg);
381 if (!(val & ~LVDS_DETECTED))
382 val = dev_priv->bios_lvds_val;
383 dev_priv->lvds_val = val;
385 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
388 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
391 struct drm_device *dev = crtc->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 const intel_limit_t *limit;
395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
397 /* LVDS dual channel */
398 if (refclk == 100000)
399 limit = &intel_limits_ironlake_dual_lvds_100m;
401 limit = &intel_limits_ironlake_dual_lvds;
403 if (refclk == 100000)
404 limit = &intel_limits_ironlake_single_lvds_100m;
406 limit = &intel_limits_ironlake_single_lvds;
408 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
410 limit = &intel_limits_ironlake_display_port;
412 limit = &intel_limits_ironlake_dac;
417 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
419 struct drm_device *dev = crtc->dev;
420 struct drm_i915_private *dev_priv = dev->dev_private;
421 const intel_limit_t *limit;
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
424 if (is_dual_link_lvds(dev_priv, LVDS))
425 /* LVDS with dual channel */
426 limit = &intel_limits_g4x_dual_channel_lvds;
428 /* LVDS with dual channel */
429 limit = &intel_limits_g4x_single_channel_lvds;
430 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
431 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
432 limit = &intel_limits_g4x_hdmi;
433 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
434 limit = &intel_limits_g4x_sdvo;
435 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
436 limit = &intel_limits_g4x_display_port;
437 } else /* The option is for other outputs */
438 limit = &intel_limits_i9xx_sdvo;
443 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
445 struct drm_device *dev = crtc->dev;
446 const intel_limit_t *limit;
448 if (HAS_PCH_SPLIT(dev))
449 limit = intel_ironlake_limit(crtc, refclk);
450 else if (IS_G4X(dev)) {
451 limit = intel_g4x_limit(crtc);
452 } else if (IS_PINEVIEW(dev)) {
453 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
454 limit = &intel_limits_pineview_lvds;
456 limit = &intel_limits_pineview_sdvo;
457 } else if (!IS_GEN2(dev)) {
458 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
459 limit = &intel_limits_i9xx_lvds;
461 limit = &intel_limits_i9xx_sdvo;
463 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
464 limit = &intel_limits_i8xx_lvds;
466 limit = &intel_limits_i8xx_dvo;
471 /* m1 is reserved as 0 in Pineview, n is a ring counter */
472 static void pineview_clock(int refclk, intel_clock_t *clock)
474 clock->m = clock->m2 + 2;
475 clock->p = clock->p1 * clock->p2;
476 clock->vco = refclk * clock->m / clock->n;
477 clock->dot = clock->vco / clock->p;
480 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
482 if (IS_PINEVIEW(dev)) {
483 pineview_clock(refclk, clock);
486 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
487 clock->p = clock->p1 * clock->p2;
488 clock->vco = refclk * clock->m / (clock->n + 2);
489 clock->dot = clock->vco / clock->p;
493 * Returns whether any output on the specified pipe is of the specified type
495 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
497 struct drm_device *dev = crtc->dev;
498 struct drm_mode_config *mode_config = &dev->mode_config;
499 struct intel_encoder *encoder;
501 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
502 if (encoder->base.crtc == crtc && encoder->type == type)
508 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
510 * Returns whether the given set of divisors are valid for a given refclk with
511 * the given connectors.
514 static bool intel_PLL_is_valid(struct drm_device *dev,
515 const intel_limit_t *limit,
516 const intel_clock_t *clock)
518 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
519 INTELPllInvalid("p1 out of range\n");
520 if (clock->p < limit->p.min || limit->p.max < clock->p)
521 INTELPllInvalid("p out of range\n");
522 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
523 INTELPllInvalid("m2 out of range\n");
524 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
525 INTELPllInvalid("m1 out of range\n");
526 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
527 INTELPllInvalid("m1 <= m2\n");
528 if (clock->m < limit->m.min || limit->m.max < clock->m)
529 INTELPllInvalid("m out of range\n");
530 if (clock->n < limit->n.min || limit->n.max < clock->n)
531 INTELPllInvalid("n out of range\n");
532 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
533 INTELPllInvalid("vco out of range\n");
534 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
535 * connector, etc., rather than just a single range.
537 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
538 INTELPllInvalid("dot out of range\n");
544 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
545 int target, int refclk, intel_clock_t *match_clock,
546 intel_clock_t *best_clock)
549 struct drm_device *dev = crtc->dev;
550 struct drm_i915_private *dev_priv = dev->dev_private;
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
555 (I915_READ(LVDS)) != 0) {
557 * For LVDS, if the panel is on, just rely on its current
558 * settings for dual-channel. We haven't figured out how to
559 * reliably set up different single/dual channel state, if we
562 if (is_dual_link_lvds(dev_priv, LVDS))
563 clock.p2 = limit->p2.p2_fast;
565 clock.p2 = limit->p2.p2_slow;
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
570 clock.p2 = limit->p2.p2_fast;
573 memset(best_clock, 0, sizeof(*best_clock));
575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
579 /* m1 is always 0 in Pineview */
580 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
582 for (clock.n = limit->n.min;
583 clock.n <= limit->n.max; clock.n++) {
584 for (clock.p1 = limit->p1.min;
585 clock.p1 <= limit->p1.max; clock.p1++) {
588 intel_clock(dev, refclk, &clock);
589 if (!intel_PLL_is_valid(dev, limit,
593 clock.p != match_clock->p)
596 this_err = abs(clock.dot - target);
597 if (this_err < err) {
606 return (err != target);
610 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
611 int target, int refclk, intel_clock_t *match_clock,
612 intel_clock_t *best_clock)
614 struct drm_device *dev = crtc->dev;
615 struct drm_i915_private *dev_priv = dev->dev_private;
619 /* approximately equals target * 0.00585 */
620 int err_most = (target >> 8) + (target >> 9);
623 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
626 if (HAS_PCH_SPLIT(dev))
630 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
632 clock.p2 = limit->p2.p2_fast;
634 clock.p2 = limit->p2.p2_slow;
636 if (target < limit->p2.dot_limit)
637 clock.p2 = limit->p2.p2_slow;
639 clock.p2 = limit->p2.p2_fast;
642 memset(best_clock, 0, sizeof(*best_clock));
643 max_n = limit->n.max;
644 /* based on hardware requirement, prefer smaller n to precision */
645 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
646 /* based on hardware requirement, prefere larger m1,m2 */
647 for (clock.m1 = limit->m1.max;
648 clock.m1 >= limit->m1.min; clock.m1--) {
649 for (clock.m2 = limit->m2.max;
650 clock.m2 >= limit->m2.min; clock.m2--) {
651 for (clock.p1 = limit->p1.max;
652 clock.p1 >= limit->p1.min; clock.p1--) {
655 intel_clock(dev, refclk, &clock);
656 if (!intel_PLL_is_valid(dev, limit,
660 clock.p != match_clock->p)
663 this_err = abs(clock.dot - target);
664 if (this_err < err_most) {
678 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
679 int target, int refclk, intel_clock_t *match_clock,
680 intel_clock_t *best_clock)
682 struct drm_device *dev = crtc->dev;
685 if (target < 200000) {
698 intel_clock(dev, refclk, &clock);
699 memcpy(best_clock, &clock, sizeof(intel_clock_t));
703 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
705 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
706 int target, int refclk, intel_clock_t *match_clock,
707 intel_clock_t *best_clock)
710 if (target < 200000) {
723 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
724 clock.p = (clock.p1 * clock.p2);
725 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
727 memcpy(best_clock, &clock, sizeof(intel_clock_t));
732 * intel_wait_for_vblank - wait for vblank on a given pipe
734 * @pipe: pipe to wait for
736 * Wait for vblank to occur on a given pipe. Needed for various bits of
739 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
741 struct drm_i915_private *dev_priv = dev->dev_private;
742 int pipestat_reg = PIPESTAT(pipe);
744 /* Clear existing vblank status. Note this will clear any other
745 * sticky status fields as well.
747 * This races with i915_driver_irq_handler() with the result
748 * that either function could miss a vblank event. Here it is not
749 * fatal, as we will either wait upon the next vblank interrupt or
750 * timeout. Generally speaking intel_wait_for_vblank() is only
751 * called during modeset at which time the GPU should be idle and
752 * should *not* be performing page flips and thus not waiting on
754 * Currently, the result of us stealing a vblank from the irq
755 * handler is that a single frame will be skipped during swapbuffers.
757 I915_WRITE(pipestat_reg,
758 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
760 /* Wait for vblank interrupt bit to set */
761 if (wait_for(I915_READ(pipestat_reg) &
762 PIPE_VBLANK_INTERRUPT_STATUS,
764 DRM_DEBUG_KMS("vblank wait timed out\n");
768 * intel_wait_for_pipe_off - wait for pipe to turn off
770 * @pipe: pipe to wait for
772 * After disabling a pipe, we can't wait for vblank in the usual way,
773 * spinning on the vblank interrupt status bit, since we won't actually
774 * see an interrupt when the pipe is disabled.
777 * wait for the pipe register state bit to turn off
780 * wait for the display line value to settle (it usually
781 * ends up stopping at the start of the next frame).
784 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
786 struct drm_i915_private *dev_priv = dev->dev_private;
788 if (INTEL_INFO(dev)->gen >= 4) {
789 int reg = PIPECONF(pipe);
791 /* Wait for the Pipe State to go off */
792 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
794 DRM_DEBUG_KMS("pipe_off wait timed out\n");
797 int reg = PIPEDSL(pipe);
798 unsigned long timeout = jiffies + msecs_to_jiffies(100);
800 /* Wait for the display line to settle */
802 last_line = I915_READ(reg) & DSL_LINEMASK;
804 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
805 time_after(timeout, jiffies));
806 if (time_after(jiffies, timeout))
807 DRM_DEBUG_KMS("pipe_off wait timed out\n");
811 static const char *state_string(bool enabled)
813 return enabled ? "on" : "off";
816 /* Only for pre-ILK configs */
817 static void assert_pll(struct drm_i915_private *dev_priv,
818 enum pipe pipe, bool state)
825 val = I915_READ(reg);
826 cur_state = !!(val & DPLL_VCO_ENABLE);
827 WARN(cur_state != state,
828 "PLL state assertion failure (expected %s, current %s)\n",
829 state_string(state), state_string(cur_state));
831 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
832 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
835 static void assert_pch_pll(struct drm_i915_private *dev_priv,
836 enum pipe pipe, bool state)
842 if (HAS_PCH_CPT(dev_priv->dev)) {
845 pch_dpll = I915_READ(PCH_DPLL_SEL);
847 /* Make sure the selected PLL is enabled to the transcoder */
848 WARN(!((pch_dpll >> (4 * pipe)) & 8),
849 "transcoder %d PLL not enabled\n", pipe);
851 /* Convert the transcoder pipe number to a pll pipe number */
852 pipe = (pch_dpll >> (4 * pipe)) & 1;
855 reg = PCH_DPLL(pipe);
856 val = I915_READ(reg);
857 cur_state = !!(val & DPLL_VCO_ENABLE);
858 WARN(cur_state != state,
859 "PCH PLL state assertion failure (expected %s, current %s)\n",
860 state_string(state), state_string(cur_state));
862 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
863 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
865 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
866 enum pipe pipe, bool state)
872 reg = FDI_TX_CTL(pipe);
873 val = I915_READ(reg);
874 cur_state = !!(val & FDI_TX_ENABLE);
875 WARN(cur_state != state,
876 "FDI TX state assertion failure (expected %s, current %s)\n",
877 state_string(state), state_string(cur_state));
879 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
880 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
882 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
883 enum pipe pipe, bool state)
889 reg = FDI_RX_CTL(pipe);
890 val = I915_READ(reg);
891 cur_state = !!(val & FDI_RX_ENABLE);
892 WARN(cur_state != state,
893 "FDI RX state assertion failure (expected %s, current %s)\n",
894 state_string(state), state_string(cur_state));
896 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
897 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
899 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
905 /* ILK FDI PLL is always enabled */
906 if (dev_priv->info->gen == 5)
909 reg = FDI_TX_CTL(pipe);
910 val = I915_READ(reg);
911 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
914 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
920 reg = FDI_RX_CTL(pipe);
921 val = I915_READ(reg);
922 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
925 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
928 int pp_reg, lvds_reg;
930 enum pipe panel_pipe = PIPE_A;
933 if (HAS_PCH_SPLIT(dev_priv->dev)) {
934 pp_reg = PCH_PP_CONTROL;
941 val = I915_READ(pp_reg);
942 if (!(val & PANEL_POWER_ON) ||
943 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
946 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
949 WARN(panel_pipe == pipe && locked,
950 "panel assertion failure, pipe %c regs locked\n",
954 void assert_pipe(struct drm_i915_private *dev_priv,
955 enum pipe pipe, bool state)
961 /* if we need the pipe A quirk it must be always on */
962 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
965 reg = PIPECONF(pipe);
966 val = I915_READ(reg);
967 cur_state = !!(val & PIPECONF_ENABLE);
968 WARN(cur_state != state,
969 "pipe %c assertion failure (expected %s, current %s)\n",
970 pipe_name(pipe), state_string(state), state_string(cur_state));
973 static void assert_plane(struct drm_i915_private *dev_priv,
974 enum plane plane, bool state)
980 reg = DSPCNTR(plane);
981 val = I915_READ(reg);
982 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
983 WARN(cur_state != state,
984 "plane %c assertion failure (expected %s, current %s)\n",
985 plane_name(plane), state_string(state), state_string(cur_state));
988 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
989 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
991 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
998 /* Planes are fixed to pipes on ILK+ */
999 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1000 reg = DSPCNTR(pipe);
1001 val = I915_READ(reg);
1002 WARN((val & DISPLAY_PLANE_ENABLE),
1003 "plane %c assertion failure, should be disabled but not\n",
1008 /* Need to check both planes against the pipe */
1009 for (i = 0; i < 2; i++) {
1011 val = I915_READ(reg);
1012 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1013 DISPPLANE_SEL_PIPE_SHIFT;
1014 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1015 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1016 plane_name(i), pipe_name(pipe));
1020 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1025 val = I915_READ(PCH_DREF_CONTROL);
1026 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1027 DREF_SUPERSPREAD_SOURCE_MASK));
1028 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1031 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1038 reg = TRANSCONF(pipe);
1039 val = I915_READ(reg);
1040 enabled = !!(val & TRANS_ENABLE);
1042 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1046 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1047 enum pipe pipe, u32 port_sel, u32 val)
1049 if ((val & DP_PORT_EN) == 0)
1052 if (HAS_PCH_CPT(dev_priv->dev)) {
1053 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1054 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1055 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1058 if ((val & DP_PIPE_MASK) != (pipe << 30))
1064 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, u32 val)
1067 if ((val & PORT_ENABLE) == 0)
1070 if (HAS_PCH_CPT(dev_priv->dev)) {
1071 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1074 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1080 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1081 enum pipe pipe, u32 val)
1083 if ((val & LVDS_PORT_EN) == 0)
1086 if (HAS_PCH_CPT(dev_priv->dev)) {
1087 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1090 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1096 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1097 enum pipe pipe, u32 val)
1099 if ((val & ADPA_DAC_ENABLE) == 0)
1101 if (HAS_PCH_CPT(dev_priv->dev)) {
1102 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1105 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1111 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1112 enum pipe pipe, int reg, u32 port_sel)
1114 u32 val = I915_READ(reg);
1115 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1116 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1117 reg, pipe_name(pipe));
1120 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1121 enum pipe pipe, int reg)
1123 u32 val = I915_READ(reg);
1124 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1125 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1126 reg, pipe_name(pipe));
1129 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1135 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1136 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1137 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1140 val = I915_READ(reg);
1141 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1142 "PCH VGA enabled on transcoder %c, should be disabled\n",
1146 val = I915_READ(reg);
1147 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1148 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1151 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1152 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1153 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1157 * intel_enable_pll - enable a PLL
1158 * @dev_priv: i915 private structure
1159 * @pipe: pipe PLL to enable
1161 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1162 * make sure the PLL reg is writable first though, since the panel write
1163 * protect mechanism may be enabled.
1165 * Note! This is for pre-ILK only.
1167 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1172 /* No really, not for ILK+ */
1173 BUG_ON(dev_priv->info->gen >= 5);
1175 /* PLL is protected by panel, make sure we can write it */
1176 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1177 assert_panel_unlocked(dev_priv, pipe);
1180 val = I915_READ(reg);
1181 val |= DPLL_VCO_ENABLE;
1183 /* We do this three times for luck */
1184 I915_WRITE(reg, val);
1186 udelay(150); /* wait for warmup */
1187 I915_WRITE(reg, val);
1189 udelay(150); /* wait for warmup */
1190 I915_WRITE(reg, val);
1192 udelay(150); /* wait for warmup */
1196 * intel_disable_pll - disable a PLL
1197 * @dev_priv: i915 private structure
1198 * @pipe: pipe PLL to disable
1200 * Disable the PLL for @pipe, making sure the pipe is off first.
1202 * Note! This is for pre-ILK only.
1204 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1209 /* Don't disable pipe A or pipe A PLLs if needed */
1210 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1213 /* Make sure the pipe isn't still relying on us */
1214 assert_pipe_disabled(dev_priv, pipe);
1217 val = I915_READ(reg);
1218 val &= ~DPLL_VCO_ENABLE;
1219 I915_WRITE(reg, val);
1224 * intel_enable_pch_pll - enable PCH PLL
1225 * @dev_priv: i915 private structure
1226 * @pipe: pipe PLL to enable
1228 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1229 * drives the transcoder clock.
1231 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1240 /* PCH only available on ILK+ */
1241 BUG_ON(dev_priv->info->gen < 5);
1243 /* PCH refclock must be enabled first */
1244 assert_pch_refclk_enabled(dev_priv);
1246 reg = PCH_DPLL(pipe);
1247 val = I915_READ(reg);
1248 val |= DPLL_VCO_ENABLE;
1249 I915_WRITE(reg, val);
1254 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1258 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1259 pll_sel = TRANSC_DPLL_ENABLE;
1264 /* PCH only available on ILK+ */
1265 BUG_ON(dev_priv->info->gen < 5);
1267 /* Make sure transcoder isn't still depending on us */
1268 assert_transcoder_disabled(dev_priv, pipe);
1271 pll_sel |= TRANSC_DPLLA_SEL;
1273 pll_sel |= TRANSC_DPLLB_SEL;
1276 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1279 reg = PCH_DPLL(pipe);
1280 val = I915_READ(reg);
1281 val &= ~DPLL_VCO_ENABLE;
1282 I915_WRITE(reg, val);
1287 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1291 u32 val, pipeconf_val;
1292 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1294 /* PCH only available on ILK+ */
1295 BUG_ON(dev_priv->info->gen < 5);
1297 /* Make sure PCH DPLL is enabled */
1298 assert_pch_pll_enabled(dev_priv, pipe);
1300 /* FDI must be feeding us bits for PCH ports */
1301 assert_fdi_tx_enabled(dev_priv, pipe);
1302 assert_fdi_rx_enabled(dev_priv, pipe);
1304 reg = TRANSCONF(pipe);
1305 val = I915_READ(reg);
1306 pipeconf_val = I915_READ(PIPECONF(pipe));
1308 if (HAS_PCH_IBX(dev_priv->dev)) {
1310 * make the BPC in transcoder be consistent with
1311 * that in pipeconf reg.
1313 val &= ~PIPE_BPC_MASK;
1314 val |= pipeconf_val & PIPE_BPC_MASK;
1317 val &= ~TRANS_INTERLACE_MASK;
1318 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1319 if (HAS_PCH_IBX(dev_priv->dev) &&
1320 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1321 val |= TRANS_LEGACY_INTERLACED_ILK;
1323 val |= TRANS_INTERLACED;
1325 val |= TRANS_PROGRESSIVE;
1327 I915_WRITE(reg, val | TRANS_ENABLE);
1328 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1329 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1332 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1338 /* FDI relies on the transcoder */
1339 assert_fdi_tx_disabled(dev_priv, pipe);
1340 assert_fdi_rx_disabled(dev_priv, pipe);
1342 /* Ports must be off as well */
1343 assert_pch_ports_disabled(dev_priv, pipe);
1345 reg = TRANSCONF(pipe);
1346 val = I915_READ(reg);
1347 val &= ~TRANS_ENABLE;
1348 I915_WRITE(reg, val);
1349 /* wait for PCH transcoder off, transcoder state */
1350 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1351 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1355 * intel_enable_pipe - enable a pipe, asserting requirements
1356 * @dev_priv: i915 private structure
1357 * @pipe: pipe to enable
1358 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1360 * Enable @pipe, making sure that various hardware specific requirements
1361 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1363 * @pipe should be %PIPE_A or %PIPE_B.
1365 * Will wait until the pipe is actually running (i.e. first vblank) before
1368 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1375 * A pipe without a PLL won't actually be able to drive bits from
1376 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1379 if (!HAS_PCH_SPLIT(dev_priv->dev))
1380 assert_pll_enabled(dev_priv, pipe);
1383 /* if driving the PCH, we need FDI enabled */
1384 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1385 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1387 /* FIXME: assert CPU port conditions for SNB+ */
1390 reg = PIPECONF(pipe);
1391 val = I915_READ(reg);
1392 if (val & PIPECONF_ENABLE)
1395 I915_WRITE(reg, val | PIPECONF_ENABLE);
1396 intel_wait_for_vblank(dev_priv->dev, pipe);
1400 * intel_disable_pipe - disable a pipe, asserting requirements
1401 * @dev_priv: i915 private structure
1402 * @pipe: pipe to disable
1404 * Disable @pipe, making sure that various hardware specific requirements
1405 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1407 * @pipe should be %PIPE_A or %PIPE_B.
1409 * Will wait until the pipe has shut down before returning.
1411 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1418 * Make sure planes won't keep trying to pump pixels to us,
1419 * or we might hang the display.
1421 assert_planes_disabled(dev_priv, pipe);
1423 /* Don't disable pipe A or pipe A PLLs if needed */
1424 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1427 reg = PIPECONF(pipe);
1428 val = I915_READ(reg);
1429 if ((val & PIPECONF_ENABLE) == 0)
1432 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1433 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1437 * Plane regs are double buffered, going from enabled->disabled needs a
1438 * trigger in order to latch. The display address reg provides this.
1440 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1443 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1444 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1448 * intel_enable_plane - enable a display plane on a given pipe
1449 * @dev_priv: i915 private structure
1450 * @plane: plane to enable
1451 * @pipe: pipe being fed
1453 * Enable @plane on @pipe, making sure that @pipe is running first.
1455 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1456 enum plane plane, enum pipe pipe)
1461 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1462 assert_pipe_enabled(dev_priv, pipe);
1464 reg = DSPCNTR(plane);
1465 val = I915_READ(reg);
1466 if (val & DISPLAY_PLANE_ENABLE)
1469 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1470 intel_flush_display_plane(dev_priv, plane);
1471 intel_wait_for_vblank(dev_priv->dev, pipe);
1475 * intel_disable_plane - disable a display plane
1476 * @dev_priv: i915 private structure
1477 * @plane: plane to disable
1478 * @pipe: pipe consuming the data
1480 * Disable @plane; should be an independent operation.
1482 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1483 enum plane plane, enum pipe pipe)
1488 reg = DSPCNTR(plane);
1489 val = I915_READ(reg);
1490 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1493 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1494 intel_flush_display_plane(dev_priv, plane);
1495 intel_wait_for_vblank(dev_priv->dev, pipe);
1498 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1499 enum pipe pipe, int reg, u32 port_sel)
1501 u32 val = I915_READ(reg);
1502 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1503 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1504 I915_WRITE(reg, val & ~DP_PORT_EN);
1508 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, int reg)
1511 u32 val = I915_READ(reg);
1512 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1513 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1515 I915_WRITE(reg, val & ~PORT_ENABLE);
1519 /* Disable any ports connected to this transcoder */
1520 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1525 val = I915_READ(PCH_PP_CONTROL);
1526 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1528 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1529 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1530 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1533 val = I915_READ(reg);
1534 if (adpa_pipe_enabled(dev_priv, val, pipe))
1535 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1538 val = I915_READ(reg);
1539 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1540 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1541 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1546 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1547 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1548 disable_pch_hdmi(dev_priv, pipe, HDMID);
1551 static void i8xx_disable_fbc(struct drm_device *dev)
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1556 /* Disable compression */
1557 fbc_ctl = I915_READ(FBC_CONTROL);
1558 if ((fbc_ctl & FBC_CTL_EN) == 0)
1561 fbc_ctl &= ~FBC_CTL_EN;
1562 I915_WRITE(FBC_CONTROL, fbc_ctl);
1564 /* Wait for compressing bit to clear */
1565 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1566 DRM_DEBUG_KMS("FBC idle timed out\n");
1570 DRM_DEBUG_KMS("disabled FBC\n");
1573 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1575 struct drm_device *dev = crtc->dev;
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1577 struct drm_framebuffer *fb = crtc->fb;
1578 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1579 struct drm_i915_gem_object *obj = intel_fb->obj;
1580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1583 u32 fbc_ctl, fbc_ctl2;
1585 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1586 if (fb->pitches[0] < cfb_pitch)
1587 cfb_pitch = fb->pitches[0];
1589 /* FBC_CTL wants 64B units */
1590 cfb_pitch = (cfb_pitch / 64) - 1;
1591 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1593 /* Clear old tags */
1594 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1595 I915_WRITE(FBC_TAG + (i * 4), 0);
1598 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1600 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1601 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1604 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1606 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1607 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1608 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1609 fbc_ctl |= obj->fence_reg;
1610 I915_WRITE(FBC_CONTROL, fbc_ctl);
1612 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1613 cfb_pitch, crtc->y, intel_crtc->plane);
1616 static bool i8xx_fbc_enabled(struct drm_device *dev)
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1620 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1623 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1625 struct drm_device *dev = crtc->dev;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627 struct drm_framebuffer *fb = crtc->fb;
1628 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1629 struct drm_i915_gem_object *obj = intel_fb->obj;
1630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1631 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1632 unsigned long stall_watermark = 200;
1635 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1636 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1637 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1639 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1640 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1641 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1642 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1645 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1647 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1650 static void g4x_disable_fbc(struct drm_device *dev)
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1655 /* Disable compression */
1656 dpfc_ctl = I915_READ(DPFC_CONTROL);
1657 if (dpfc_ctl & DPFC_CTL_EN) {
1658 dpfc_ctl &= ~DPFC_CTL_EN;
1659 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1661 DRM_DEBUG_KMS("disabled FBC\n");
1665 static bool g4x_fbc_enabled(struct drm_device *dev)
1667 struct drm_i915_private *dev_priv = dev->dev_private;
1669 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1672 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1674 struct drm_i915_private *dev_priv = dev->dev_private;
1677 /* Make sure blitter notifies FBC of writes */
1678 gen6_gt_force_wake_get(dev_priv);
1679 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1680 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1681 GEN6_BLITTER_LOCK_SHIFT;
1682 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1683 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1684 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1685 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1686 GEN6_BLITTER_LOCK_SHIFT);
1687 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1688 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1689 gen6_gt_force_wake_put(dev_priv);
1692 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1694 struct drm_device *dev = crtc->dev;
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 struct drm_framebuffer *fb = crtc->fb;
1697 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1698 struct drm_i915_gem_object *obj = intel_fb->obj;
1699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1700 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1701 unsigned long stall_watermark = 200;
1704 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1705 dpfc_ctl &= DPFC_RESERVED;
1706 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1707 /* Set persistent mode for front-buffer rendering, ala X. */
1708 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1709 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1710 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1712 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1713 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1714 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1715 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1716 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1718 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1721 I915_WRITE(SNB_DPFC_CTL_SA,
1722 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1723 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1724 sandybridge_blit_fbc_update(dev);
1727 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1730 static void ironlake_disable_fbc(struct drm_device *dev)
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1735 /* Disable compression */
1736 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1737 if (dpfc_ctl & DPFC_CTL_EN) {
1738 dpfc_ctl &= ~DPFC_CTL_EN;
1739 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1741 DRM_DEBUG_KMS("disabled FBC\n");
1745 static bool ironlake_fbc_enabled(struct drm_device *dev)
1747 struct drm_i915_private *dev_priv = dev->dev_private;
1749 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1752 bool intel_fbc_enabled(struct drm_device *dev)
1754 struct drm_i915_private *dev_priv = dev->dev_private;
1756 if (!dev_priv->display.fbc_enabled)
1759 return dev_priv->display.fbc_enabled(dev);
1762 static void intel_fbc_work_fn(struct work_struct *__work)
1764 struct intel_fbc_work *work =
1765 container_of(to_delayed_work(__work),
1766 struct intel_fbc_work, work);
1767 struct drm_device *dev = work->crtc->dev;
1768 struct drm_i915_private *dev_priv = dev->dev_private;
1770 mutex_lock(&dev->struct_mutex);
1771 if (work == dev_priv->fbc_work) {
1772 /* Double check that we haven't switched fb without cancelling
1775 if (work->crtc->fb == work->fb) {
1776 dev_priv->display.enable_fbc(work->crtc,
1779 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1780 dev_priv->cfb_fb = work->crtc->fb->base.id;
1781 dev_priv->cfb_y = work->crtc->y;
1784 dev_priv->fbc_work = NULL;
1786 mutex_unlock(&dev->struct_mutex);
1791 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1793 if (dev_priv->fbc_work == NULL)
1796 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1798 /* Synchronisation is provided by struct_mutex and checking of
1799 * dev_priv->fbc_work, so we can perform the cancellation
1800 * entirely asynchronously.
1802 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1803 /* tasklet was killed before being run, clean up */
1804 kfree(dev_priv->fbc_work);
1806 /* Mark the work as no longer wanted so that if it does
1807 * wake-up (because the work was already running and waiting
1808 * for our mutex), it will discover that is no longer
1811 dev_priv->fbc_work = NULL;
1814 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1816 struct intel_fbc_work *work;
1817 struct drm_device *dev = crtc->dev;
1818 struct drm_i915_private *dev_priv = dev->dev_private;
1820 if (!dev_priv->display.enable_fbc)
1823 intel_cancel_fbc_work(dev_priv);
1825 work = kzalloc(sizeof *work, GFP_KERNEL);
1827 dev_priv->display.enable_fbc(crtc, interval);
1832 work->fb = crtc->fb;
1833 work->interval = interval;
1834 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1836 dev_priv->fbc_work = work;
1838 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1840 /* Delay the actual enabling to let pageflipping cease and the
1841 * display to settle before starting the compression. Note that
1842 * this delay also serves a second purpose: it allows for a
1843 * vblank to pass after disabling the FBC before we attempt
1844 * to modify the control registers.
1846 * A more complicated solution would involve tracking vblanks
1847 * following the termination of the page-flipping sequence
1848 * and indeed performing the enable as a co-routine and not
1849 * waiting synchronously upon the vblank.
1851 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1854 void intel_disable_fbc(struct drm_device *dev)
1856 struct drm_i915_private *dev_priv = dev->dev_private;
1858 intel_cancel_fbc_work(dev_priv);
1860 if (!dev_priv->display.disable_fbc)
1863 dev_priv->display.disable_fbc(dev);
1864 dev_priv->cfb_plane = -1;
1868 * intel_update_fbc - enable/disable FBC as needed
1869 * @dev: the drm_device
1871 * Set up the framebuffer compression hardware at mode set time. We
1872 * enable it if possible:
1873 * - plane A only (on pre-965)
1874 * - no pixel mulitply/line duplication
1875 * - no alpha buffer discard
1877 * - framebuffer <= 2048 in width, 1536 in height
1879 * We can't assume that any compression will take place (worst case),
1880 * so the compressed buffer has to be the same size as the uncompressed
1881 * one. It also must reside (along with the line length buffer) in
1884 * We need to enable/disable FBC on a global basis.
1886 static void intel_update_fbc(struct drm_device *dev)
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 struct drm_crtc *crtc = NULL, *tmp_crtc;
1890 struct intel_crtc *intel_crtc;
1891 struct drm_framebuffer *fb;
1892 struct intel_framebuffer *intel_fb;
1893 struct drm_i915_gem_object *obj;
1896 DRM_DEBUG_KMS("\n");
1898 if (!i915_powersave)
1901 if (!I915_HAS_FBC(dev))
1905 * If FBC is already on, we just have to verify that we can
1906 * keep it that way...
1907 * Need to disable if:
1908 * - more than one pipe is active
1909 * - changing FBC params (stride, fence, mode)
1910 * - new fb is too large to fit in compressed buffer
1911 * - going to an unsupported config (interlace, pixel multiply, etc.)
1913 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1914 if (tmp_crtc->enabled && tmp_crtc->fb) {
1916 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1917 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1924 if (!crtc || crtc->fb == NULL) {
1925 DRM_DEBUG_KMS("no output, disabling\n");
1926 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1930 intel_crtc = to_intel_crtc(crtc);
1932 intel_fb = to_intel_framebuffer(fb);
1933 obj = intel_fb->obj;
1935 enable_fbc = i915_enable_fbc;
1936 if (enable_fbc < 0) {
1937 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1939 if (INTEL_INFO(dev)->gen <= 6)
1943 DRM_DEBUG_KMS("fbc disabled per module param\n");
1944 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1947 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1948 DRM_DEBUG_KMS("framebuffer too large, disabling "
1950 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1953 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1954 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1955 DRM_DEBUG_KMS("mode incompatible with compression, "
1957 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1960 if ((crtc->mode.hdisplay > 2048) ||
1961 (crtc->mode.vdisplay > 1536)) {
1962 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1963 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1966 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1967 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1968 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1972 /* The use of a CPU fence is mandatory in order to detect writes
1973 * by the CPU to the scanout and trigger updates to the FBC.
1975 if (obj->tiling_mode != I915_TILING_X ||
1976 obj->fence_reg == I915_FENCE_REG_NONE) {
1977 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1978 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1982 /* If the kernel debugger is active, always disable compression */
1983 if (in_dbg_master())
1986 /* If the scanout has not changed, don't modify the FBC settings.
1987 * Note that we make the fundamental assumption that the fb->obj
1988 * cannot be unpinned (and have its GTT offset and fence revoked)
1989 * without first being decoupled from the scanout and FBC disabled.
1991 if (dev_priv->cfb_plane == intel_crtc->plane &&
1992 dev_priv->cfb_fb == fb->base.id &&
1993 dev_priv->cfb_y == crtc->y)
1996 if (intel_fbc_enabled(dev)) {
1997 /* We update FBC along two paths, after changing fb/crtc
1998 * configuration (modeswitching) and after page-flipping
1999 * finishes. For the latter, we know that not only did
2000 * we disable the FBC at the start of the page-flip
2001 * sequence, but also more than one vblank has passed.
2003 * For the former case of modeswitching, it is possible
2004 * to switch between two FBC valid configurations
2005 * instantaneously so we do need to disable the FBC
2006 * before we can modify its control registers. We also
2007 * have to wait for the next vblank for that to take
2008 * effect. However, since we delay enabling FBC we can
2009 * assume that a vblank has passed since disabling and
2010 * that we can safely alter the registers in the deferred
2013 * In the scenario that we go from a valid to invalid
2014 * and then back to valid FBC configuration we have
2015 * no strict enforcement that a vblank occurred since
2016 * disabling the FBC. However, along all current pipe
2017 * disabling paths we do need to wait for a vblank at
2018 * some point. And we wait before enabling FBC anyway.
2020 DRM_DEBUG_KMS("disabling active FBC for update\n");
2021 intel_disable_fbc(dev);
2024 intel_enable_fbc(crtc, 500);
2028 /* Multiple disables should be harmless */
2029 if (intel_fbc_enabled(dev)) {
2030 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2031 intel_disable_fbc(dev);
2036 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2037 struct drm_i915_gem_object *obj,
2038 struct intel_ring_buffer *pipelined)
2040 struct drm_i915_private *dev_priv = dev->dev_private;
2044 switch (obj->tiling_mode) {
2045 case I915_TILING_NONE:
2046 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2047 alignment = 128 * 1024;
2048 else if (INTEL_INFO(dev)->gen >= 4)
2049 alignment = 4 * 1024;
2051 alignment = 64 * 1024;
2054 /* pin() will align the object as required by fence */
2058 /* FIXME: Is this true? */
2059 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2065 dev_priv->mm.interruptible = false;
2066 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2068 goto err_interruptible;
2070 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2071 * fence, whereas 965+ only requires a fence if using
2072 * framebuffer compression. For simplicity, we always install
2073 * a fence as the cost is not that onerous.
2075 if (obj->tiling_mode != I915_TILING_NONE) {
2076 ret = i915_gem_object_get_fence(obj, pipelined);
2080 i915_gem_object_pin_fence(obj);
2083 dev_priv->mm.interruptible = true;
2087 i915_gem_object_unpin(obj);
2089 dev_priv->mm.interruptible = true;
2093 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2095 i915_gem_object_unpin_fence(obj);
2096 i915_gem_object_unpin(obj);
2099 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2102 struct drm_device *dev = crtc->dev;
2103 struct drm_i915_private *dev_priv = dev->dev_private;
2104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2105 struct intel_framebuffer *intel_fb;
2106 struct drm_i915_gem_object *obj;
2107 int plane = intel_crtc->plane;
2108 unsigned long Start, Offset;
2117 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2121 intel_fb = to_intel_framebuffer(fb);
2122 obj = intel_fb->obj;
2124 reg = DSPCNTR(plane);
2125 dspcntr = I915_READ(reg);
2126 /* Mask out pixel format bits in case we change it */
2127 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2128 switch (fb->bits_per_pixel) {
2130 dspcntr |= DISPPLANE_8BPP;
2133 if (fb->depth == 15)
2134 dspcntr |= DISPPLANE_15_16BPP;
2136 dspcntr |= DISPPLANE_16BPP;
2140 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2143 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2146 if (INTEL_INFO(dev)->gen >= 4) {
2147 if (obj->tiling_mode != I915_TILING_NONE)
2148 dspcntr |= DISPPLANE_TILED;
2150 dspcntr &= ~DISPPLANE_TILED;
2153 I915_WRITE(reg, dspcntr);
2155 Start = obj->gtt_offset;
2156 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2158 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2159 Start, Offset, x, y, fb->pitches[0]);
2160 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2161 if (INTEL_INFO(dev)->gen >= 4) {
2162 I915_WRITE(DSPSURF(plane), Start);
2163 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164 I915_WRITE(DSPADDR(plane), Offset);
2166 I915_WRITE(DSPADDR(plane), Start + Offset);
2172 static int ironlake_update_plane(struct drm_crtc *crtc,
2173 struct drm_framebuffer *fb, int x, int y)
2175 struct drm_device *dev = crtc->dev;
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2178 struct intel_framebuffer *intel_fb;
2179 struct drm_i915_gem_object *obj;
2180 int plane = intel_crtc->plane;
2181 unsigned long Start, Offset;
2191 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2195 intel_fb = to_intel_framebuffer(fb);
2196 obj = intel_fb->obj;
2198 reg = DSPCNTR(plane);
2199 dspcntr = I915_READ(reg);
2200 /* Mask out pixel format bits in case we change it */
2201 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2202 switch (fb->bits_per_pixel) {
2204 dspcntr |= DISPPLANE_8BPP;
2207 if (fb->depth != 16)
2210 dspcntr |= DISPPLANE_16BPP;
2214 if (fb->depth == 24)
2215 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2216 else if (fb->depth == 30)
2217 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2222 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2226 if (obj->tiling_mode != I915_TILING_NONE)
2227 dspcntr |= DISPPLANE_TILED;
2229 dspcntr &= ~DISPPLANE_TILED;
2232 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2234 I915_WRITE(reg, dspcntr);
2236 Start = obj->gtt_offset;
2237 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2239 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2240 Start, Offset, x, y, fb->pitches[0]);
2241 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2242 I915_WRITE(DSPSURF(plane), Start);
2243 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2244 I915_WRITE(DSPADDR(plane), Offset);
2250 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2252 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2253 int x, int y, enum mode_set_atomic state)
2255 struct drm_device *dev = crtc->dev;
2256 struct drm_i915_private *dev_priv = dev->dev_private;
2259 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2263 intel_update_fbc(dev);
2264 intel_increase_pllclock(crtc);
2270 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2271 struct drm_framebuffer *old_fb)
2273 struct drm_device *dev = crtc->dev;
2274 struct drm_i915_master_private *master_priv;
2275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2280 DRM_ERROR("No FB bound\n");
2284 switch (intel_crtc->plane) {
2289 if (IS_IVYBRIDGE(dev))
2291 /* fall through otherwise */
2293 DRM_ERROR("no plane for crtc\n");
2297 mutex_lock(&dev->struct_mutex);
2298 ret = intel_pin_and_fence_fb_obj(dev,
2299 to_intel_framebuffer(crtc->fb)->obj,
2302 mutex_unlock(&dev->struct_mutex);
2303 DRM_ERROR("pin & fence failed\n");
2308 struct drm_i915_private *dev_priv = dev->dev_private;
2309 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2311 wait_event(dev_priv->pending_flip_queue,
2312 atomic_read(&dev_priv->mm.wedged) ||
2313 atomic_read(&obj->pending_flip) == 0);
2315 /* Big Hammer, we also need to ensure that any pending
2316 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2317 * current scanout is retired before unpinning the old
2320 * This should only fail upon a hung GPU, in which case we
2321 * can safely continue.
2323 ret = i915_gem_object_finish_gpu(obj);
2327 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2328 LEAVE_ATOMIC_MODE_SET);
2330 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2331 mutex_unlock(&dev->struct_mutex);
2332 DRM_ERROR("failed to update base address\n");
2337 intel_wait_for_vblank(dev, intel_crtc->pipe);
2338 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2341 mutex_unlock(&dev->struct_mutex);
2343 if (!dev->primary->master)
2346 master_priv = dev->primary->master->driver_priv;
2347 if (!master_priv->sarea_priv)
2350 if (intel_crtc->pipe) {
2351 master_priv->sarea_priv->pipeB_x = x;
2352 master_priv->sarea_priv->pipeB_y = y;
2354 master_priv->sarea_priv->pipeA_x = x;
2355 master_priv->sarea_priv->pipeA_y = y;
2361 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2363 struct drm_device *dev = crtc->dev;
2364 struct drm_i915_private *dev_priv = dev->dev_private;
2367 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2368 dpa_ctl = I915_READ(DP_A);
2369 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2371 if (clock < 200000) {
2373 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2374 /* workaround for 160Mhz:
2375 1) program 0x4600c bits 15:0 = 0x8124
2376 2) program 0x46010 bit 0 = 1
2377 3) program 0x46034 bit 24 = 1
2378 4) program 0x64000 bit 14 = 1
2380 temp = I915_READ(0x4600c);
2382 I915_WRITE(0x4600c, temp | 0x8124);
2384 temp = I915_READ(0x46010);
2385 I915_WRITE(0x46010, temp | 1);
2387 temp = I915_READ(0x46034);
2388 I915_WRITE(0x46034, temp | (1 << 24));
2390 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2392 I915_WRITE(DP_A, dpa_ctl);
2398 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
2406 /* enable normal train */
2407 reg = FDI_TX_CTL(pipe);
2408 temp = I915_READ(reg);
2409 if (IS_IVYBRIDGE(dev)) {
2410 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2411 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2413 temp &= ~FDI_LINK_TRAIN_NONE;
2414 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2416 I915_WRITE(reg, temp);
2418 reg = FDI_RX_CTL(pipe);
2419 temp = I915_READ(reg);
2420 if (HAS_PCH_CPT(dev)) {
2421 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2422 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_NONE;
2427 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2429 /* wait one idle pattern time */
2433 /* IVB wants error correction enabled */
2434 if (IS_IVYBRIDGE(dev))
2435 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2436 FDI_FE_ERRC_ENABLE);
2439 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2441 struct drm_i915_private *dev_priv = dev->dev_private;
2442 u32 flags = I915_READ(SOUTH_CHICKEN1);
2444 flags |= FDI_PHASE_SYNC_OVR(pipe);
2445 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2446 flags |= FDI_PHASE_SYNC_EN(pipe);
2447 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2448 POSTING_READ(SOUTH_CHICKEN1);
2451 /* The FDI link training functions for ILK/Ibexpeak. */
2452 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2454 struct drm_device *dev = crtc->dev;
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2457 int pipe = intel_crtc->pipe;
2458 int plane = intel_crtc->plane;
2459 u32 reg, temp, tries;
2461 /* FDI needs bits from pipe & plane first */
2462 assert_pipe_enabled(dev_priv, pipe);
2463 assert_plane_enabled(dev_priv, plane);
2465 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2467 reg = FDI_RX_IMR(pipe);
2468 temp = I915_READ(reg);
2469 temp &= ~FDI_RX_SYMBOL_LOCK;
2470 temp &= ~FDI_RX_BIT_LOCK;
2471 I915_WRITE(reg, temp);
2475 /* enable CPU FDI TX and PCH FDI RX */
2476 reg = FDI_TX_CTL(pipe);
2477 temp = I915_READ(reg);
2479 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2480 temp &= ~FDI_LINK_TRAIN_NONE;
2481 temp |= FDI_LINK_TRAIN_PATTERN_1;
2482 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2484 reg = FDI_RX_CTL(pipe);
2485 temp = I915_READ(reg);
2486 temp &= ~FDI_LINK_TRAIN_NONE;
2487 temp |= FDI_LINK_TRAIN_PATTERN_1;
2488 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2493 /* Ironlake workaround, enable clock pointer after FDI enable*/
2494 if (HAS_PCH_IBX(dev)) {
2495 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2496 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2497 FDI_RX_PHASE_SYNC_POINTER_EN);
2500 reg = FDI_RX_IIR(pipe);
2501 for (tries = 0; tries < 5; tries++) {
2502 temp = I915_READ(reg);
2503 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2505 if ((temp & FDI_RX_BIT_LOCK)) {
2506 DRM_DEBUG_KMS("FDI train 1 done.\n");
2507 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2512 DRM_ERROR("FDI train 1 fail!\n");
2515 reg = FDI_TX_CTL(pipe);
2516 temp = I915_READ(reg);
2517 temp &= ~FDI_LINK_TRAIN_NONE;
2518 temp |= FDI_LINK_TRAIN_PATTERN_2;
2519 I915_WRITE(reg, temp);
2521 reg = FDI_RX_CTL(pipe);
2522 temp = I915_READ(reg);
2523 temp &= ~FDI_LINK_TRAIN_NONE;
2524 temp |= FDI_LINK_TRAIN_PATTERN_2;
2525 I915_WRITE(reg, temp);
2530 reg = FDI_RX_IIR(pipe);
2531 for (tries = 0; tries < 5; tries++) {
2532 temp = I915_READ(reg);
2533 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2535 if (temp & FDI_RX_SYMBOL_LOCK) {
2536 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2537 DRM_DEBUG_KMS("FDI train 2 done.\n");
2542 DRM_ERROR("FDI train 2 fail!\n");
2544 DRM_DEBUG_KMS("FDI train done\n");
2548 static const int snb_b_fdi_train_param[] = {
2549 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2550 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2551 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2552 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2555 /* The FDI link training functions for SNB/Cougarpoint. */
2556 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2558 struct drm_device *dev = crtc->dev;
2559 struct drm_i915_private *dev_priv = dev->dev_private;
2560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2561 int pipe = intel_crtc->pipe;
2562 u32 reg, temp, i, retry;
2564 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2566 reg = FDI_RX_IMR(pipe);
2567 temp = I915_READ(reg);
2568 temp &= ~FDI_RX_SYMBOL_LOCK;
2569 temp &= ~FDI_RX_BIT_LOCK;
2570 I915_WRITE(reg, temp);
2575 /* enable CPU FDI TX and PCH FDI RX */
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
2579 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2580 temp &= ~FDI_LINK_TRAIN_NONE;
2581 temp |= FDI_LINK_TRAIN_PATTERN_1;
2582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2584 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2585 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2587 reg = FDI_RX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 if (HAS_PCH_CPT(dev)) {
2590 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2593 temp &= ~FDI_LINK_TRAIN_NONE;
2594 temp |= FDI_LINK_TRAIN_PATTERN_1;
2596 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2601 if (HAS_PCH_CPT(dev))
2602 cpt_phase_pointer_enable(dev, pipe);
2604 for (i = 0; i < 4; i++) {
2605 reg = FDI_TX_CTL(pipe);
2606 temp = I915_READ(reg);
2607 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2608 temp |= snb_b_fdi_train_param[i];
2609 I915_WRITE(reg, temp);
2614 for (retry = 0; retry < 5; retry++) {
2615 reg = FDI_RX_IIR(pipe);
2616 temp = I915_READ(reg);
2617 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2618 if (temp & FDI_RX_BIT_LOCK) {
2619 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2620 DRM_DEBUG_KMS("FDI train 1 done.\n");
2629 DRM_ERROR("FDI train 1 fail!\n");
2632 reg = FDI_TX_CTL(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~FDI_LINK_TRAIN_NONE;
2635 temp |= FDI_LINK_TRAIN_PATTERN_2;
2637 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2641 I915_WRITE(reg, temp);
2643 reg = FDI_RX_CTL(pipe);
2644 temp = I915_READ(reg);
2645 if (HAS_PCH_CPT(dev)) {
2646 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2647 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2649 temp &= ~FDI_LINK_TRAIN_NONE;
2650 temp |= FDI_LINK_TRAIN_PATTERN_2;
2652 I915_WRITE(reg, temp);
2657 for (i = 0; i < 4; i++) {
2658 reg = FDI_TX_CTL(pipe);
2659 temp = I915_READ(reg);
2660 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2661 temp |= snb_b_fdi_train_param[i];
2662 I915_WRITE(reg, temp);
2667 for (retry = 0; retry < 5; retry++) {
2668 reg = FDI_RX_IIR(pipe);
2669 temp = I915_READ(reg);
2670 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2671 if (temp & FDI_RX_SYMBOL_LOCK) {
2672 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2673 DRM_DEBUG_KMS("FDI train 2 done.\n");
2682 DRM_ERROR("FDI train 2 fail!\n");
2684 DRM_DEBUG_KMS("FDI train done.\n");
2687 /* Manual link training for Ivy Bridge A0 parts */
2688 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2690 struct drm_device *dev = crtc->dev;
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2693 int pipe = intel_crtc->pipe;
2696 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2698 reg = FDI_RX_IMR(pipe);
2699 temp = I915_READ(reg);
2700 temp &= ~FDI_RX_SYMBOL_LOCK;
2701 temp &= ~FDI_RX_BIT_LOCK;
2702 I915_WRITE(reg, temp);
2707 /* enable CPU FDI TX and PCH FDI RX */
2708 reg = FDI_TX_CTL(pipe);
2709 temp = I915_READ(reg);
2711 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2712 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2713 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2714 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2715 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2716 temp |= FDI_COMPOSITE_SYNC;
2717 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~FDI_LINK_TRAIN_AUTO;
2722 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2723 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2724 temp |= FDI_COMPOSITE_SYNC;
2725 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2730 if (HAS_PCH_CPT(dev))
2731 cpt_phase_pointer_enable(dev, pipe);
2733 for (i = 0; i < 4; i++) {
2734 reg = FDI_TX_CTL(pipe);
2735 temp = I915_READ(reg);
2736 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2737 temp |= snb_b_fdi_train_param[i];
2738 I915_WRITE(reg, temp);
2743 reg = FDI_RX_IIR(pipe);
2744 temp = I915_READ(reg);
2745 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2747 if (temp & FDI_RX_BIT_LOCK ||
2748 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2749 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2750 DRM_DEBUG_KMS("FDI train 1 done.\n");
2755 DRM_ERROR("FDI train 1 fail!\n");
2758 reg = FDI_TX_CTL(pipe);
2759 temp = I915_READ(reg);
2760 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2761 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2762 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2763 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2764 I915_WRITE(reg, temp);
2766 reg = FDI_RX_CTL(pipe);
2767 temp = I915_READ(reg);
2768 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2769 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2770 I915_WRITE(reg, temp);
2775 for (i = 0; i < 4; i++) {
2776 reg = FDI_TX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779 temp |= snb_b_fdi_train_param[i];
2780 I915_WRITE(reg, temp);
2785 reg = FDI_RX_IIR(pipe);
2786 temp = I915_READ(reg);
2787 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2789 if (temp & FDI_RX_SYMBOL_LOCK) {
2790 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2791 DRM_DEBUG_KMS("FDI train 2 done.\n");
2796 DRM_ERROR("FDI train 2 fail!\n");
2798 DRM_DEBUG_KMS("FDI train done.\n");
2801 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2803 struct drm_device *dev = crtc->dev;
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2806 int pipe = intel_crtc->pipe;
2809 /* Write the TU size bits so error detection works */
2810 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2811 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2813 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~((0x7 << 19) | (0x7 << 16));
2817 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2818 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2824 /* Switch from Rawclk to PCDclk */
2825 temp = I915_READ(reg);
2826 I915_WRITE(reg, temp | FDI_PCDCLK);
2831 /* Enable CPU FDI TX PLL, always on for Ironlake */
2832 reg = FDI_TX_CTL(pipe);
2833 temp = I915_READ(reg);
2834 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2835 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2842 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2844 struct drm_i915_private *dev_priv = dev->dev_private;
2845 u32 flags = I915_READ(SOUTH_CHICKEN1);
2847 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2848 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2849 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2850 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2851 POSTING_READ(SOUTH_CHICKEN1);
2853 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2855 struct drm_device *dev = crtc->dev;
2856 struct drm_i915_private *dev_priv = dev->dev_private;
2857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2858 int pipe = intel_crtc->pipe;
2861 /* disable CPU FDI tx and PCH FDI rx */
2862 reg = FDI_TX_CTL(pipe);
2863 temp = I915_READ(reg);
2864 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2867 reg = FDI_RX_CTL(pipe);
2868 temp = I915_READ(reg);
2869 temp &= ~(0x7 << 16);
2870 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2871 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2876 /* Ironlake workaround, disable clock pointer after downing FDI */
2877 if (HAS_PCH_IBX(dev)) {
2878 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2879 I915_WRITE(FDI_RX_CHICKEN(pipe),
2880 I915_READ(FDI_RX_CHICKEN(pipe) &
2881 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2882 } else if (HAS_PCH_CPT(dev)) {
2883 cpt_phase_pointer_disable(dev, pipe);
2886 /* still set train pattern 1 */
2887 reg = FDI_TX_CTL(pipe);
2888 temp = I915_READ(reg);
2889 temp &= ~FDI_LINK_TRAIN_NONE;
2890 temp |= FDI_LINK_TRAIN_PATTERN_1;
2891 I915_WRITE(reg, temp);
2893 reg = FDI_RX_CTL(pipe);
2894 temp = I915_READ(reg);
2895 if (HAS_PCH_CPT(dev)) {
2896 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2897 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2899 temp &= ~FDI_LINK_TRAIN_NONE;
2900 temp |= FDI_LINK_TRAIN_PATTERN_1;
2902 /* BPC in FDI rx is consistent with that in PIPECONF */
2903 temp &= ~(0x07 << 16);
2904 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2905 I915_WRITE(reg, temp);
2912 * When we disable a pipe, we need to clear any pending scanline wait events
2913 * to avoid hanging the ring, which we assume we are waiting on.
2915 static void intel_clear_scanline_wait(struct drm_device *dev)
2917 struct drm_i915_private *dev_priv = dev->dev_private;
2918 struct intel_ring_buffer *ring;
2922 /* Can't break the hang on i8xx */
2925 ring = LP_RING(dev_priv);
2926 tmp = I915_READ_CTL(ring);
2927 if (tmp & RING_WAIT)
2928 I915_WRITE_CTL(ring, tmp);
2931 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2933 struct drm_i915_gem_object *obj;
2934 struct drm_i915_private *dev_priv;
2936 if (crtc->fb == NULL)
2939 obj = to_intel_framebuffer(crtc->fb)->obj;
2940 dev_priv = crtc->dev->dev_private;
2941 wait_event(dev_priv->pending_flip_queue,
2942 atomic_read(&obj->pending_flip) == 0);
2945 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2947 struct drm_device *dev = crtc->dev;
2948 struct drm_mode_config *mode_config = &dev->mode_config;
2949 struct intel_encoder *encoder;
2952 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2953 * must be driven by its own crtc; no sharing is possible.
2955 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2956 if (encoder->base.crtc != crtc)
2959 switch (encoder->type) {
2960 case INTEL_OUTPUT_EDP:
2961 if (!intel_encoder_is_pch_edp(&encoder->base))
2971 * Enable PCH resources required for PCH ports:
2973 * - FDI training & RX/TX
2974 * - update transcoder timings
2975 * - DP transcoding bits
2978 static void ironlake_pch_enable(struct drm_crtc *crtc)
2980 struct drm_device *dev = crtc->dev;
2981 struct drm_i915_private *dev_priv = dev->dev_private;
2982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2983 int pipe = intel_crtc->pipe;
2984 u32 reg, temp, transc_sel;
2986 /* For PCH output, training FDI link */
2987 dev_priv->display.fdi_link_train(crtc);
2989 intel_enable_pch_pll(dev_priv, pipe);
2991 if (HAS_PCH_CPT(dev)) {
2992 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2995 /* Be sure PCH DPLL SEL is set */
2996 temp = I915_READ(PCH_DPLL_SEL);
2998 temp &= ~(TRANSA_DPLLB_SEL);
2999 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3000 } else if (pipe == 1) {
3001 temp &= ~(TRANSB_DPLLB_SEL);
3002 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3003 } else if (pipe == 2) {
3004 temp &= ~(TRANSC_DPLLB_SEL);
3005 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
3007 I915_WRITE(PCH_DPLL_SEL, temp);
3010 /* set transcoder timing, panel must allow it */
3011 assert_panel_unlocked(dev_priv, pipe);
3012 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3013 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3014 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3016 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3017 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3018 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3019 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3021 intel_fdi_normal_train(crtc);
3023 /* For PCH DP, enable TRANS_DP_CTL */
3024 if (HAS_PCH_CPT(dev) &&
3025 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3026 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3027 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3028 reg = TRANS_DP_CTL(pipe);
3029 temp = I915_READ(reg);
3030 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3031 TRANS_DP_SYNC_MASK |
3033 temp |= (TRANS_DP_OUTPUT_ENABLE |
3034 TRANS_DP_ENH_FRAMING);
3035 temp |= bpc << 9; /* same format but at 11:9 */
3037 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3038 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3039 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3040 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3042 switch (intel_trans_dp_port_sel(crtc)) {
3044 temp |= TRANS_DP_PORT_SEL_B;
3047 temp |= TRANS_DP_PORT_SEL_C;
3050 temp |= TRANS_DP_PORT_SEL_D;
3053 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3054 temp |= TRANS_DP_PORT_SEL_B;
3058 I915_WRITE(reg, temp);
3061 intel_enable_transcoder(dev_priv, pipe);
3064 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3066 struct drm_i915_private *dev_priv = dev->dev_private;
3067 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3070 temp = I915_READ(dslreg);
3072 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3073 /* Without this, mode sets may fail silently on FDI */
3074 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3076 I915_WRITE(tc2reg, 0);
3077 if (wait_for(I915_READ(dslreg) != temp, 5))
3078 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3082 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3084 struct drm_device *dev = crtc->dev;
3085 struct drm_i915_private *dev_priv = dev->dev_private;
3086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087 int pipe = intel_crtc->pipe;
3088 int plane = intel_crtc->plane;
3092 if (intel_crtc->active)
3095 intel_crtc->active = true;
3096 intel_update_watermarks(dev);
3098 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3099 temp = I915_READ(PCH_LVDS);
3100 if ((temp & LVDS_PORT_EN) == 0)
3101 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3104 is_pch_port = intel_crtc_driving_pch(crtc);
3107 ironlake_fdi_pll_enable(crtc);
3109 ironlake_fdi_disable(crtc);
3111 /* Enable panel fitting for LVDS */
3112 if (dev_priv->pch_pf_size &&
3113 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3114 /* Force use of hard-coded filter coefficients
3115 * as some pre-programmed values are broken,
3118 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3119 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3120 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3124 * On ILK+ LUT must be loaded before the pipe is running but with
3127 intel_crtc_load_lut(crtc);
3129 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3130 intel_enable_plane(dev_priv, plane, pipe);
3133 ironlake_pch_enable(crtc);
3135 mutex_lock(&dev->struct_mutex);
3136 intel_update_fbc(dev);
3137 mutex_unlock(&dev->struct_mutex);
3139 intel_crtc_update_cursor(crtc, true);
3142 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3144 struct drm_device *dev = crtc->dev;
3145 struct drm_i915_private *dev_priv = dev->dev_private;
3146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3147 int pipe = intel_crtc->pipe;
3148 int plane = intel_crtc->plane;
3151 if (!intel_crtc->active)
3154 intel_crtc_wait_for_pending_flips(crtc);
3155 drm_vblank_off(dev, pipe);
3156 intel_crtc_update_cursor(crtc, false);
3158 intel_disable_plane(dev_priv, plane, pipe);
3160 if (dev_priv->cfb_plane == plane)
3161 intel_disable_fbc(dev);
3163 intel_disable_pipe(dev_priv, pipe);
3166 I915_WRITE(PF_CTL(pipe), 0);
3167 I915_WRITE(PF_WIN_SZ(pipe), 0);
3169 ironlake_fdi_disable(crtc);
3171 /* This is a horrible layering violation; we should be doing this in
3172 * the connector/encoder ->prepare instead, but we don't always have
3173 * enough information there about the config to know whether it will
3174 * actually be necessary or just cause undesired flicker.
3176 intel_disable_pch_ports(dev_priv, pipe);
3178 intel_disable_transcoder(dev_priv, pipe);
3180 if (HAS_PCH_CPT(dev)) {
3181 /* disable TRANS_DP_CTL */
3182 reg = TRANS_DP_CTL(pipe);
3183 temp = I915_READ(reg);
3184 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3185 temp |= TRANS_DP_PORT_SEL_NONE;
3186 I915_WRITE(reg, temp);
3188 /* disable DPLL_SEL */
3189 temp = I915_READ(PCH_DPLL_SEL);
3192 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3195 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3198 /* C shares PLL A or B */
3199 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3204 I915_WRITE(PCH_DPLL_SEL, temp);
3207 /* disable PCH DPLL */
3208 if (!intel_crtc->no_pll)
3209 intel_disable_pch_pll(dev_priv, pipe);
3211 /* Switch from PCDclk to Rawclk */
3212 reg = FDI_RX_CTL(pipe);
3213 temp = I915_READ(reg);
3214 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3216 /* Disable CPU FDI TX PLL */
3217 reg = FDI_TX_CTL(pipe);
3218 temp = I915_READ(reg);
3219 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3224 reg = FDI_RX_CTL(pipe);
3225 temp = I915_READ(reg);
3226 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3228 /* Wait for the clocks to turn off. */
3232 intel_crtc->active = false;
3233 intel_update_watermarks(dev);
3235 mutex_lock(&dev->struct_mutex);
3236 intel_update_fbc(dev);
3237 intel_clear_scanline_wait(dev);
3238 mutex_unlock(&dev->struct_mutex);
3241 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3244 int pipe = intel_crtc->pipe;
3245 int plane = intel_crtc->plane;
3247 /* XXX: When our outputs are all unaware of DPMS modes other than off
3248 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3251 case DRM_MODE_DPMS_ON:
3252 case DRM_MODE_DPMS_STANDBY:
3253 case DRM_MODE_DPMS_SUSPEND:
3254 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3255 ironlake_crtc_enable(crtc);
3258 case DRM_MODE_DPMS_OFF:
3259 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3260 ironlake_crtc_disable(crtc);
3265 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3267 if (!enable && intel_crtc->overlay) {
3268 struct drm_device *dev = intel_crtc->base.dev;
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3271 mutex_lock(&dev->struct_mutex);
3272 dev_priv->mm.interruptible = false;
3273 (void) intel_overlay_switch_off(intel_crtc->overlay);
3274 dev_priv->mm.interruptible = true;
3275 mutex_unlock(&dev->struct_mutex);
3278 /* Let userspace switch the overlay on again. In most cases userspace
3279 * has to recompute where to put it anyway.
3283 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3285 struct drm_device *dev = crtc->dev;
3286 struct drm_i915_private *dev_priv = dev->dev_private;
3287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3288 int pipe = intel_crtc->pipe;
3289 int plane = intel_crtc->plane;
3291 if (intel_crtc->active)
3294 intel_crtc->active = true;
3295 intel_update_watermarks(dev);
3297 intel_enable_pll(dev_priv, pipe);
3298 intel_enable_pipe(dev_priv, pipe, false);
3299 intel_enable_plane(dev_priv, plane, pipe);
3301 intel_crtc_load_lut(crtc);
3302 intel_update_fbc(dev);
3304 /* Give the overlay scaler a chance to enable if it's on this pipe */
3305 intel_crtc_dpms_overlay(intel_crtc, true);
3306 intel_crtc_update_cursor(crtc, true);
3309 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3311 struct drm_device *dev = crtc->dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3314 int pipe = intel_crtc->pipe;
3315 int plane = intel_crtc->plane;
3317 if (!intel_crtc->active)
3320 /* Give the overlay scaler a chance to disable if it's on this pipe */
3321 intel_crtc_wait_for_pending_flips(crtc);
3322 drm_vblank_off(dev, pipe);
3323 intel_crtc_dpms_overlay(intel_crtc, false);
3324 intel_crtc_update_cursor(crtc, false);
3326 if (dev_priv->cfb_plane == plane)
3327 intel_disable_fbc(dev);
3329 intel_disable_plane(dev_priv, plane, pipe);
3330 intel_disable_pipe(dev_priv, pipe);
3331 intel_disable_pll(dev_priv, pipe);
3333 intel_crtc->active = false;
3334 intel_update_fbc(dev);
3335 intel_update_watermarks(dev);
3336 intel_clear_scanline_wait(dev);
3339 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3341 /* XXX: When our outputs are all unaware of DPMS modes other than off
3342 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3345 case DRM_MODE_DPMS_ON:
3346 case DRM_MODE_DPMS_STANDBY:
3347 case DRM_MODE_DPMS_SUSPEND:
3348 i9xx_crtc_enable(crtc);
3350 case DRM_MODE_DPMS_OFF:
3351 i9xx_crtc_disable(crtc);
3357 * Sets the power management mode of the pipe and plane.
3359 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3361 struct drm_device *dev = crtc->dev;
3362 struct drm_i915_private *dev_priv = dev->dev_private;
3363 struct drm_i915_master_private *master_priv;
3364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365 int pipe = intel_crtc->pipe;
3368 if (intel_crtc->dpms_mode == mode)
3371 intel_crtc->dpms_mode = mode;
3373 dev_priv->display.dpms(crtc, mode);
3375 if (!dev->primary->master)
3378 master_priv = dev->primary->master->driver_priv;
3379 if (!master_priv->sarea_priv)
3382 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3386 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3387 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3390 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3391 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3394 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3399 static void intel_crtc_disable(struct drm_crtc *crtc)
3401 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3402 struct drm_device *dev = crtc->dev;
3404 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3405 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3406 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3409 mutex_lock(&dev->struct_mutex);
3410 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3411 mutex_unlock(&dev->struct_mutex);
3415 /* Prepare for a mode set.
3417 * Note we could be a lot smarter here. We need to figure out which outputs
3418 * will be enabled, which disabled (in short, how the config will changes)
3419 * and perform the minimum necessary steps to accomplish that, e.g. updating
3420 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3421 * panel fitting is in the proper state, etc.
3423 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3425 i9xx_crtc_disable(crtc);
3428 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3430 i9xx_crtc_enable(crtc);
3433 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3435 ironlake_crtc_disable(crtc);
3438 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3440 ironlake_crtc_enable(crtc);
3443 void intel_encoder_prepare(struct drm_encoder *encoder)
3445 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3446 /* lvds has its own version of prepare see intel_lvds_prepare */
3447 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3450 void intel_encoder_commit(struct drm_encoder *encoder)
3452 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3453 struct drm_device *dev = encoder->dev;
3454 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3455 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3457 /* lvds has its own version of commit see intel_lvds_commit */
3458 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3460 if (HAS_PCH_CPT(dev))
3461 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3464 void intel_encoder_destroy(struct drm_encoder *encoder)
3466 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3468 drm_encoder_cleanup(encoder);
3469 kfree(intel_encoder);
3472 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3473 struct drm_display_mode *mode,
3474 struct drm_display_mode *adjusted_mode)
3476 struct drm_device *dev = crtc->dev;
3478 if (HAS_PCH_SPLIT(dev)) {
3479 /* FDI link clock is fixed at 2.7G */
3480 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3484 /* All interlaced capable intel hw wants timings in frames. */
3485 drm_mode_set_crtcinfo(adjusted_mode, 0);
3490 static int i945_get_display_clock_speed(struct drm_device *dev)
3495 static int i915_get_display_clock_speed(struct drm_device *dev)
3500 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3505 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3509 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3511 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3514 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3515 case GC_DISPLAY_CLOCK_333_MHZ:
3518 case GC_DISPLAY_CLOCK_190_200_MHZ:
3524 static int i865_get_display_clock_speed(struct drm_device *dev)
3529 static int i855_get_display_clock_speed(struct drm_device *dev)
3532 /* Assume that the hardware is in the high speed state. This
3533 * should be the default.
3535 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3536 case GC_CLOCK_133_200:
3537 case GC_CLOCK_100_200:
3539 case GC_CLOCK_166_250:
3541 case GC_CLOCK_100_133:
3545 /* Shouldn't happen */
3549 static int i830_get_display_clock_speed(struct drm_device *dev)
3563 fdi_reduce_ratio(u32 *num, u32 *den)
3565 while (*num > 0xffffff || *den > 0xffffff) {
3572 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3573 int link_clock, struct fdi_m_n *m_n)
3575 m_n->tu = 64; /* default size */
3577 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3578 m_n->gmch_m = bits_per_pixel * pixel_clock;
3579 m_n->gmch_n = link_clock * nlanes * 8;
3580 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3582 m_n->link_m = pixel_clock;
3583 m_n->link_n = link_clock;
3584 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3588 struct intel_watermark_params {
3589 unsigned long fifo_size;
3590 unsigned long max_wm;
3591 unsigned long default_wm;
3592 unsigned long guard_size;
3593 unsigned long cacheline_size;
3596 /* Pineview has different values for various configs */
3597 static const struct intel_watermark_params pineview_display_wm = {
3598 PINEVIEW_DISPLAY_FIFO,
3602 PINEVIEW_FIFO_LINE_SIZE
3604 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3605 PINEVIEW_DISPLAY_FIFO,
3607 PINEVIEW_DFT_HPLLOFF_WM,
3609 PINEVIEW_FIFO_LINE_SIZE
3611 static const struct intel_watermark_params pineview_cursor_wm = {
3612 PINEVIEW_CURSOR_FIFO,
3613 PINEVIEW_CURSOR_MAX_WM,
3614 PINEVIEW_CURSOR_DFT_WM,
3615 PINEVIEW_CURSOR_GUARD_WM,
3616 PINEVIEW_FIFO_LINE_SIZE,
3618 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3619 PINEVIEW_CURSOR_FIFO,
3620 PINEVIEW_CURSOR_MAX_WM,
3621 PINEVIEW_CURSOR_DFT_WM,
3622 PINEVIEW_CURSOR_GUARD_WM,
3623 PINEVIEW_FIFO_LINE_SIZE
3625 static const struct intel_watermark_params g4x_wm_info = {
3632 static const struct intel_watermark_params g4x_cursor_wm_info = {
3639 static const struct intel_watermark_params i965_cursor_wm_info = {
3644 I915_FIFO_LINE_SIZE,
3646 static const struct intel_watermark_params i945_wm_info = {
3653 static const struct intel_watermark_params i915_wm_info = {
3660 static const struct intel_watermark_params i855_wm_info = {
3667 static const struct intel_watermark_params i830_wm_info = {
3675 static const struct intel_watermark_params ironlake_display_wm_info = {
3682 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3689 static const struct intel_watermark_params ironlake_display_srwm_info = {
3690 ILK_DISPLAY_SR_FIFO,
3691 ILK_DISPLAY_MAX_SRWM,
3692 ILK_DISPLAY_DFT_SRWM,
3696 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3698 ILK_CURSOR_MAX_SRWM,
3699 ILK_CURSOR_DFT_SRWM,
3704 static const struct intel_watermark_params sandybridge_display_wm_info = {
3711 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3718 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3719 SNB_DISPLAY_SR_FIFO,
3720 SNB_DISPLAY_MAX_SRWM,
3721 SNB_DISPLAY_DFT_SRWM,
3725 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3727 SNB_CURSOR_MAX_SRWM,
3728 SNB_CURSOR_DFT_SRWM,
3735 * intel_calculate_wm - calculate watermark level
3736 * @clock_in_khz: pixel clock
3737 * @wm: chip FIFO params
3738 * @pixel_size: display pixel size
3739 * @latency_ns: memory latency for the platform
3741 * Calculate the watermark level (the level at which the display plane will
3742 * start fetching from memory again). Each chip has a different display
3743 * FIFO size and allocation, so the caller needs to figure that out and pass
3744 * in the correct intel_watermark_params structure.
3746 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3747 * on the pixel size. When it reaches the watermark level, it'll start
3748 * fetching FIFO line sized based chunks from memory until the FIFO fills
3749 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3750 * will occur, and a display engine hang could result.
3752 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3753 const struct intel_watermark_params *wm,
3756 unsigned long latency_ns)
3758 long entries_required, wm_size;
3761 * Note: we need to make sure we don't overflow for various clock &
3763 * clocks go from a few thousand to several hundred thousand.
3764 * latency is usually a few thousand
3766 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3768 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3770 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3772 wm_size = fifo_size - (entries_required + wm->guard_size);
3774 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3776 /* Don't promote wm_size to unsigned... */
3777 if (wm_size > (long)wm->max_wm)
3778 wm_size = wm->max_wm;
3780 wm_size = wm->default_wm;
3784 struct cxsr_latency {
3787 unsigned long fsb_freq;
3788 unsigned long mem_freq;
3789 unsigned long display_sr;
3790 unsigned long display_hpll_disable;
3791 unsigned long cursor_sr;
3792 unsigned long cursor_hpll_disable;
3795 static const struct cxsr_latency cxsr_latency_table[] = {
3796 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3797 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3798 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3799 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3800 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3802 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3803 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3804 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3805 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3806 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3808 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3809 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3810 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3811 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3812 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3814 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3815 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3816 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3817 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3818 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3820 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3821 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3822 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3823 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3824 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3826 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3827 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3828 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3829 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3830 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3833 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3838 const struct cxsr_latency *latency;
3841 if (fsb == 0 || mem == 0)
3844 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3845 latency = &cxsr_latency_table[i];
3846 if (is_desktop == latency->is_desktop &&
3847 is_ddr3 == latency->is_ddr3 &&
3848 fsb == latency->fsb_freq && mem == latency->mem_freq)
3852 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3857 static void pineview_disable_cxsr(struct drm_device *dev)
3859 struct drm_i915_private *dev_priv = dev->dev_private;
3861 /* deactivate cxsr */
3862 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3866 * Latency for FIFO fetches is dependent on several factors:
3867 * - memory configuration (speed, channels)
3869 * - current MCH state
3870 * It can be fairly high in some situations, so here we assume a fairly
3871 * pessimal value. It's a tradeoff between extra memory fetches (if we
3872 * set this value too high, the FIFO will fetch frequently to stay full)
3873 * and power consumption (set it too low to save power and we might see
3874 * FIFO underruns and display "flicker").
3876 * A value of 5us seems to be a good balance; safe for very low end
3877 * platforms but not overly aggressive on lower latency configs.
3879 static const int latency_ns = 5000;
3881 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3883 struct drm_i915_private *dev_priv = dev->dev_private;
3884 uint32_t dsparb = I915_READ(DSPARB);
3887 size = dsparb & 0x7f;
3889 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3891 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3892 plane ? "B" : "A", size);
3897 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3899 struct drm_i915_private *dev_priv = dev->dev_private;
3900 uint32_t dsparb = I915_READ(DSPARB);
3903 size = dsparb & 0x1ff;
3905 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3906 size >>= 1; /* Convert to cachelines */
3908 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3909 plane ? "B" : "A", size);
3914 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3917 uint32_t dsparb = I915_READ(DSPARB);
3920 size = dsparb & 0x7f;
3921 size >>= 2; /* Convert to cachelines */
3923 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3930 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3932 struct drm_i915_private *dev_priv = dev->dev_private;
3933 uint32_t dsparb = I915_READ(DSPARB);
3936 size = dsparb & 0x7f;
3937 size >>= 1; /* Convert to cachelines */
3939 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3940 plane ? "B" : "A", size);
3945 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3947 struct drm_crtc *crtc, *enabled = NULL;
3949 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3950 if (crtc->enabled && crtc->fb) {
3960 static void pineview_update_wm(struct drm_device *dev)
3962 struct drm_i915_private *dev_priv = dev->dev_private;
3963 struct drm_crtc *crtc;
3964 const struct cxsr_latency *latency;
3968 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3969 dev_priv->fsb_freq, dev_priv->mem_freq);
3971 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3972 pineview_disable_cxsr(dev);
3976 crtc = single_enabled_crtc(dev);
3978 int clock = crtc->mode.clock;
3979 int pixel_size = crtc->fb->bits_per_pixel / 8;
3982 wm = intel_calculate_wm(clock, &pineview_display_wm,
3983 pineview_display_wm.fifo_size,
3984 pixel_size, latency->display_sr);
3985 reg = I915_READ(DSPFW1);
3986 reg &= ~DSPFW_SR_MASK;
3987 reg |= wm << DSPFW_SR_SHIFT;
3988 I915_WRITE(DSPFW1, reg);
3989 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3992 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3993 pineview_display_wm.fifo_size,
3994 pixel_size, latency->cursor_sr);
3995 reg = I915_READ(DSPFW3);
3996 reg &= ~DSPFW_CURSOR_SR_MASK;
3997 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3998 I915_WRITE(DSPFW3, reg);
4000 /* Display HPLL off SR */
4001 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4002 pineview_display_hplloff_wm.fifo_size,
4003 pixel_size, latency->display_hpll_disable);
4004 reg = I915_READ(DSPFW3);
4005 reg &= ~DSPFW_HPLL_SR_MASK;
4006 reg |= wm & DSPFW_HPLL_SR_MASK;
4007 I915_WRITE(DSPFW3, reg);
4009 /* cursor HPLL off SR */
4010 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4011 pineview_display_hplloff_wm.fifo_size,
4012 pixel_size, latency->cursor_hpll_disable);
4013 reg = I915_READ(DSPFW3);
4014 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4015 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4016 I915_WRITE(DSPFW3, reg);
4017 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4021 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4022 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4024 pineview_disable_cxsr(dev);
4025 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4029 static bool g4x_compute_wm0(struct drm_device *dev,
4031 const struct intel_watermark_params *display,
4032 int display_latency_ns,
4033 const struct intel_watermark_params *cursor,
4034 int cursor_latency_ns,
4038 struct drm_crtc *crtc;
4039 int htotal, hdisplay, clock, pixel_size;
4040 int line_time_us, line_count;
4041 int entries, tlb_miss;
4043 crtc = intel_get_crtc_for_plane(dev, plane);
4044 if (crtc->fb == NULL || !crtc->enabled) {
4045 *cursor_wm = cursor->guard_size;
4046 *plane_wm = display->guard_size;
4050 htotal = crtc->mode.htotal;
4051 hdisplay = crtc->mode.hdisplay;
4052 clock = crtc->mode.clock;
4053 pixel_size = crtc->fb->bits_per_pixel / 8;
4055 /* Use the small buffer method to calculate plane watermark */
4056 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4057 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4059 entries += tlb_miss;
4060 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4061 *plane_wm = entries + display->guard_size;
4062 if (*plane_wm > (int)display->max_wm)
4063 *plane_wm = display->max_wm;
4065 /* Use the large buffer method to calculate cursor watermark */
4066 line_time_us = ((htotal * 1000) / clock);
4067 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4068 entries = line_count * 64 * pixel_size;
4069 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4071 entries += tlb_miss;
4072 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4073 *cursor_wm = entries + cursor->guard_size;
4074 if (*cursor_wm > (int)cursor->max_wm)
4075 *cursor_wm = (int)cursor->max_wm;
4081 * Check the wm result.
4083 * If any calculated watermark values is larger than the maximum value that
4084 * can be programmed into the associated watermark register, that watermark
4087 static bool g4x_check_srwm(struct drm_device *dev,
4088 int display_wm, int cursor_wm,
4089 const struct intel_watermark_params *display,
4090 const struct intel_watermark_params *cursor)
4092 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4093 display_wm, cursor_wm);
4095 if (display_wm > display->max_wm) {
4096 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4097 display_wm, display->max_wm);
4101 if (cursor_wm > cursor->max_wm) {
4102 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4103 cursor_wm, cursor->max_wm);
4107 if (!(display_wm || cursor_wm)) {
4108 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4115 static bool g4x_compute_srwm(struct drm_device *dev,
4118 const struct intel_watermark_params *display,
4119 const struct intel_watermark_params *cursor,
4120 int *display_wm, int *cursor_wm)
4122 struct drm_crtc *crtc;
4123 int hdisplay, htotal, pixel_size, clock;
4124 unsigned long line_time_us;
4125 int line_count, line_size;
4130 *display_wm = *cursor_wm = 0;
4134 crtc = intel_get_crtc_for_plane(dev, plane);
4135 hdisplay = crtc->mode.hdisplay;
4136 htotal = crtc->mode.htotal;
4137 clock = crtc->mode.clock;
4138 pixel_size = crtc->fb->bits_per_pixel / 8;
4140 line_time_us = (htotal * 1000) / clock;
4141 line_count = (latency_ns / line_time_us + 1000) / 1000;
4142 line_size = hdisplay * pixel_size;
4144 /* Use the minimum of the small and large buffer method for primary */
4145 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4146 large = line_count * line_size;
4148 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4149 *display_wm = entries + display->guard_size;
4151 /* calculate the self-refresh watermark for display cursor */
4152 entries = line_count * pixel_size * 64;
4153 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4154 *cursor_wm = entries + cursor->guard_size;
4156 return g4x_check_srwm(dev,
4157 *display_wm, *cursor_wm,
4161 #define single_plane_enabled(mask) is_power_of_2(mask)
4163 static void g4x_update_wm(struct drm_device *dev)
4165 static const int sr_latency_ns = 12000;
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4168 int plane_sr, cursor_sr;
4169 unsigned int enabled = 0;
4171 if (g4x_compute_wm0(dev, 0,
4172 &g4x_wm_info, latency_ns,
4173 &g4x_cursor_wm_info, latency_ns,
4174 &planea_wm, &cursora_wm))
4177 if (g4x_compute_wm0(dev, 1,
4178 &g4x_wm_info, latency_ns,
4179 &g4x_cursor_wm_info, latency_ns,
4180 &planeb_wm, &cursorb_wm))
4183 plane_sr = cursor_sr = 0;
4184 if (single_plane_enabled(enabled) &&
4185 g4x_compute_srwm(dev, ffs(enabled) - 1,
4188 &g4x_cursor_wm_info,
4189 &plane_sr, &cursor_sr))
4190 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4192 I915_WRITE(FW_BLC_SELF,
4193 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4195 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4196 planea_wm, cursora_wm,
4197 planeb_wm, cursorb_wm,
4198 plane_sr, cursor_sr);
4201 (plane_sr << DSPFW_SR_SHIFT) |
4202 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4203 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4206 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4207 (cursora_wm << DSPFW_CURSORA_SHIFT));
4208 /* HPLL off in SR has some issues on G4x... disable it */
4210 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4211 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4214 static void i965_update_wm(struct drm_device *dev)
4216 struct drm_i915_private *dev_priv = dev->dev_private;
4217 struct drm_crtc *crtc;
4221 /* Calc sr entries for one plane configs */
4222 crtc = single_enabled_crtc(dev);
4224 /* self-refresh has much higher latency */
4225 static const int sr_latency_ns = 12000;
4226 int clock = crtc->mode.clock;
4227 int htotal = crtc->mode.htotal;
4228 int hdisplay = crtc->mode.hdisplay;
4229 int pixel_size = crtc->fb->bits_per_pixel / 8;
4230 unsigned long line_time_us;
4233 line_time_us = ((htotal * 1000) / clock);
4235 /* Use ns/us then divide to preserve precision */
4236 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4237 pixel_size * hdisplay;
4238 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4239 srwm = I965_FIFO_SIZE - entries;
4243 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4246 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4248 entries = DIV_ROUND_UP(entries,
4249 i965_cursor_wm_info.cacheline_size);
4250 cursor_sr = i965_cursor_wm_info.fifo_size -
4251 (entries + i965_cursor_wm_info.guard_size);
4253 if (cursor_sr > i965_cursor_wm_info.max_wm)
4254 cursor_sr = i965_cursor_wm_info.max_wm;
4256 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4257 "cursor %d\n", srwm, cursor_sr);
4259 if (IS_CRESTLINE(dev))
4260 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4262 /* Turn off self refresh if both pipes are enabled */
4263 if (IS_CRESTLINE(dev))
4264 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4268 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4271 /* 965 has limitations... */
4272 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4273 (8 << 16) | (8 << 8) | (8 << 0));
4274 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4275 /* update cursor SR watermark */
4276 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4279 static void i9xx_update_wm(struct drm_device *dev)
4281 struct drm_i915_private *dev_priv = dev->dev_private;
4282 const struct intel_watermark_params *wm_info;
4287 int planea_wm, planeb_wm;
4288 struct drm_crtc *crtc, *enabled = NULL;
4291 wm_info = &i945_wm_info;
4292 else if (!IS_GEN2(dev))
4293 wm_info = &i915_wm_info;
4295 wm_info = &i855_wm_info;
4297 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4298 crtc = intel_get_crtc_for_plane(dev, 0);
4299 if (crtc->enabled && crtc->fb) {
4300 planea_wm = intel_calculate_wm(crtc->mode.clock,
4302 crtc->fb->bits_per_pixel / 8,
4306 planea_wm = fifo_size - wm_info->guard_size;
4308 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4309 crtc = intel_get_crtc_for_plane(dev, 1);
4310 if (crtc->enabled && crtc->fb) {
4311 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4313 crtc->fb->bits_per_pixel / 8,
4315 if (enabled == NULL)
4320 planeb_wm = fifo_size - wm_info->guard_size;
4322 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4325 * Overlay gets an aggressive default since video jitter is bad.
4329 /* Play safe and disable self-refresh before adjusting watermarks. */
4330 if (IS_I945G(dev) || IS_I945GM(dev))
4331 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4332 else if (IS_I915GM(dev))
4333 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4335 /* Calc sr entries for one plane configs */
4336 if (HAS_FW_BLC(dev) && enabled) {
4337 /* self-refresh has much higher latency */
4338 static const int sr_latency_ns = 6000;
4339 int clock = enabled->mode.clock;
4340 int htotal = enabled->mode.htotal;
4341 int hdisplay = enabled->mode.hdisplay;
4342 int pixel_size = enabled->fb->bits_per_pixel / 8;
4343 unsigned long line_time_us;
4346 line_time_us = (htotal * 1000) / clock;
4348 /* Use ns/us then divide to preserve precision */
4349 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4350 pixel_size * hdisplay;
4351 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4352 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4353 srwm = wm_info->fifo_size - entries;
4357 if (IS_I945G(dev) || IS_I945GM(dev))
4358 I915_WRITE(FW_BLC_SELF,
4359 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4360 else if (IS_I915GM(dev))
4361 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4364 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4365 planea_wm, planeb_wm, cwm, srwm);
4367 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4368 fwater_hi = (cwm & 0x1f);
4370 /* Set request length to 8 cachelines per fetch */
4371 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4372 fwater_hi = fwater_hi | (1 << 8);
4374 I915_WRITE(FW_BLC, fwater_lo);
4375 I915_WRITE(FW_BLC2, fwater_hi);
4377 if (HAS_FW_BLC(dev)) {
4379 if (IS_I945G(dev) || IS_I945GM(dev))
4380 I915_WRITE(FW_BLC_SELF,
4381 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4382 else if (IS_I915GM(dev))
4383 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4384 DRM_DEBUG_KMS("memory self refresh enabled\n");
4386 DRM_DEBUG_KMS("memory self refresh disabled\n");
4390 static void i830_update_wm(struct drm_device *dev)
4392 struct drm_i915_private *dev_priv = dev->dev_private;
4393 struct drm_crtc *crtc;
4397 crtc = single_enabled_crtc(dev);
4401 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4402 dev_priv->display.get_fifo_size(dev, 0),
4403 crtc->fb->bits_per_pixel / 8,
4405 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4406 fwater_lo |= (3<<8) | planea_wm;
4408 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4410 I915_WRITE(FW_BLC, fwater_lo);
4413 #define ILK_LP0_PLANE_LATENCY 700
4414 #define ILK_LP0_CURSOR_LATENCY 1300
4417 * Check the wm result.
4419 * If any calculated watermark values is larger than the maximum value that
4420 * can be programmed into the associated watermark register, that watermark
4423 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4424 int fbc_wm, int display_wm, int cursor_wm,
4425 const struct intel_watermark_params *display,
4426 const struct intel_watermark_params *cursor)
4428 struct drm_i915_private *dev_priv = dev->dev_private;
4430 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4431 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4433 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4434 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4435 fbc_wm, SNB_FBC_MAX_SRWM, level);
4437 /* fbc has it's own way to disable FBC WM */
4438 I915_WRITE(DISP_ARB_CTL,
4439 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4443 if (display_wm > display->max_wm) {
4444 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4445 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4449 if (cursor_wm > cursor->max_wm) {
4450 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4451 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4455 if (!(fbc_wm || display_wm || cursor_wm)) {
4456 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4464 * Compute watermark values of WM[1-3],
4466 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4468 const struct intel_watermark_params *display,
4469 const struct intel_watermark_params *cursor,
4470 int *fbc_wm, int *display_wm, int *cursor_wm)
4472 struct drm_crtc *crtc;
4473 unsigned long line_time_us;
4474 int hdisplay, htotal, pixel_size, clock;
4475 int line_count, line_size;
4480 *fbc_wm = *display_wm = *cursor_wm = 0;
4484 crtc = intel_get_crtc_for_plane(dev, plane);
4485 hdisplay = crtc->mode.hdisplay;
4486 htotal = crtc->mode.htotal;
4487 clock = crtc->mode.clock;
4488 pixel_size = crtc->fb->bits_per_pixel / 8;
4490 line_time_us = (htotal * 1000) / clock;
4491 line_count = (latency_ns / line_time_us + 1000) / 1000;
4492 line_size = hdisplay * pixel_size;
4494 /* Use the minimum of the small and large buffer method for primary */
4495 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4496 large = line_count * line_size;
4498 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4499 *display_wm = entries + display->guard_size;
4503 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4505 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4507 /* calculate the self-refresh watermark for display cursor */
4508 entries = line_count * pixel_size * 64;
4509 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4510 *cursor_wm = entries + cursor->guard_size;
4512 return ironlake_check_srwm(dev, level,
4513 *fbc_wm, *display_wm, *cursor_wm,
4517 static void ironlake_update_wm(struct drm_device *dev)
4519 struct drm_i915_private *dev_priv = dev->dev_private;
4520 int fbc_wm, plane_wm, cursor_wm;
4521 unsigned int enabled;
4524 if (g4x_compute_wm0(dev, 0,
4525 &ironlake_display_wm_info,
4526 ILK_LP0_PLANE_LATENCY,
4527 &ironlake_cursor_wm_info,
4528 ILK_LP0_CURSOR_LATENCY,
4529 &plane_wm, &cursor_wm)) {
4530 I915_WRITE(WM0_PIPEA_ILK,
4531 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4532 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4533 " plane %d, " "cursor: %d\n",
4534 plane_wm, cursor_wm);
4538 if (g4x_compute_wm0(dev, 1,
4539 &ironlake_display_wm_info,
4540 ILK_LP0_PLANE_LATENCY,
4541 &ironlake_cursor_wm_info,
4542 ILK_LP0_CURSOR_LATENCY,
4543 &plane_wm, &cursor_wm)) {
4544 I915_WRITE(WM0_PIPEB_ILK,
4545 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4546 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4547 " plane %d, cursor: %d\n",
4548 plane_wm, cursor_wm);
4553 * Calculate and update the self-refresh watermark only when one
4554 * display plane is used.
4556 I915_WRITE(WM3_LP_ILK, 0);
4557 I915_WRITE(WM2_LP_ILK, 0);
4558 I915_WRITE(WM1_LP_ILK, 0);
4560 if (!single_plane_enabled(enabled))
4562 enabled = ffs(enabled) - 1;
4565 if (!ironlake_compute_srwm(dev, 1, enabled,
4566 ILK_READ_WM1_LATENCY() * 500,
4567 &ironlake_display_srwm_info,
4568 &ironlake_cursor_srwm_info,
4569 &fbc_wm, &plane_wm, &cursor_wm))
4572 I915_WRITE(WM1_LP_ILK,
4574 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4575 (fbc_wm << WM1_LP_FBC_SHIFT) |
4576 (plane_wm << WM1_LP_SR_SHIFT) |
4580 if (!ironlake_compute_srwm(dev, 2, enabled,
4581 ILK_READ_WM2_LATENCY() * 500,
4582 &ironlake_display_srwm_info,
4583 &ironlake_cursor_srwm_info,
4584 &fbc_wm, &plane_wm, &cursor_wm))
4587 I915_WRITE(WM2_LP_ILK,
4589 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4590 (fbc_wm << WM1_LP_FBC_SHIFT) |
4591 (plane_wm << WM1_LP_SR_SHIFT) |
4595 * WM3 is unsupported on ILK, probably because we don't have latency
4596 * data for that power state
4600 void sandybridge_update_wm(struct drm_device *dev)
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4605 int fbc_wm, plane_wm, cursor_wm;
4606 unsigned int enabled;
4609 if (g4x_compute_wm0(dev, 0,
4610 &sandybridge_display_wm_info, latency,
4611 &sandybridge_cursor_wm_info, latency,
4612 &plane_wm, &cursor_wm)) {
4613 val = I915_READ(WM0_PIPEA_ILK);
4614 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4615 I915_WRITE(WM0_PIPEA_ILK, val |
4616 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4617 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4618 " plane %d, " "cursor: %d\n",
4619 plane_wm, cursor_wm);
4623 if (g4x_compute_wm0(dev, 1,
4624 &sandybridge_display_wm_info, latency,
4625 &sandybridge_cursor_wm_info, latency,
4626 &plane_wm, &cursor_wm)) {
4627 val = I915_READ(WM0_PIPEB_ILK);
4628 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4629 I915_WRITE(WM0_PIPEB_ILK, val |
4630 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4631 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4632 " plane %d, cursor: %d\n",
4633 plane_wm, cursor_wm);
4637 /* IVB has 3 pipes */
4638 if (IS_IVYBRIDGE(dev) &&
4639 g4x_compute_wm0(dev, 2,
4640 &sandybridge_display_wm_info, latency,
4641 &sandybridge_cursor_wm_info, latency,
4642 &plane_wm, &cursor_wm)) {
4643 val = I915_READ(WM0_PIPEC_IVB);
4644 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4645 I915_WRITE(WM0_PIPEC_IVB, val |
4646 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4647 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4648 " plane %d, cursor: %d\n",
4649 plane_wm, cursor_wm);
4654 * Calculate and update the self-refresh watermark only when one
4655 * display plane is used.
4657 * SNB support 3 levels of watermark.
4659 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4660 * and disabled in the descending order
4663 I915_WRITE(WM3_LP_ILK, 0);
4664 I915_WRITE(WM2_LP_ILK, 0);
4665 I915_WRITE(WM1_LP_ILK, 0);
4667 if (!single_plane_enabled(enabled) ||
4668 dev_priv->sprite_scaling_enabled)
4670 enabled = ffs(enabled) - 1;
4673 if (!ironlake_compute_srwm(dev, 1, enabled,
4674 SNB_READ_WM1_LATENCY() * 500,
4675 &sandybridge_display_srwm_info,
4676 &sandybridge_cursor_srwm_info,
4677 &fbc_wm, &plane_wm, &cursor_wm))
4680 I915_WRITE(WM1_LP_ILK,
4682 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4683 (fbc_wm << WM1_LP_FBC_SHIFT) |
4684 (plane_wm << WM1_LP_SR_SHIFT) |
4688 if (!ironlake_compute_srwm(dev, 2, enabled,
4689 SNB_READ_WM2_LATENCY() * 500,
4690 &sandybridge_display_srwm_info,
4691 &sandybridge_cursor_srwm_info,
4692 &fbc_wm, &plane_wm, &cursor_wm))
4695 I915_WRITE(WM2_LP_ILK,
4697 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4698 (fbc_wm << WM1_LP_FBC_SHIFT) |
4699 (plane_wm << WM1_LP_SR_SHIFT) |
4703 if (!ironlake_compute_srwm(dev, 3, enabled,
4704 SNB_READ_WM3_LATENCY() * 500,
4705 &sandybridge_display_srwm_info,
4706 &sandybridge_cursor_srwm_info,
4707 &fbc_wm, &plane_wm, &cursor_wm))
4710 I915_WRITE(WM3_LP_ILK,
4712 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4713 (fbc_wm << WM1_LP_FBC_SHIFT) |
4714 (plane_wm << WM1_LP_SR_SHIFT) |
4719 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4720 uint32_t sprite_width, int pixel_size,
4721 const struct intel_watermark_params *display,
4722 int display_latency_ns, int *sprite_wm)
4724 struct drm_crtc *crtc;
4726 int entries, tlb_miss;
4728 crtc = intel_get_crtc_for_plane(dev, plane);
4729 if (crtc->fb == NULL || !crtc->enabled) {
4730 *sprite_wm = display->guard_size;
4734 clock = crtc->mode.clock;
4736 /* Use the small buffer method to calculate the sprite watermark */
4737 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4738 tlb_miss = display->fifo_size*display->cacheline_size -
4741 entries += tlb_miss;
4742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4743 *sprite_wm = entries + display->guard_size;
4744 if (*sprite_wm > (int)display->max_wm)
4745 *sprite_wm = display->max_wm;
4751 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4752 uint32_t sprite_width, int pixel_size,
4753 const struct intel_watermark_params *display,
4754 int latency_ns, int *sprite_wm)
4756 struct drm_crtc *crtc;
4757 unsigned long line_time_us;
4759 int line_count, line_size;
4768 crtc = intel_get_crtc_for_plane(dev, plane);
4769 clock = crtc->mode.clock;
4771 line_time_us = (sprite_width * 1000) / clock;
4772 line_count = (latency_ns / line_time_us + 1000) / 1000;
4773 line_size = sprite_width * pixel_size;
4775 /* Use the minimum of the small and large buffer method for primary */
4776 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4777 large = line_count * line_size;
4779 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4780 *sprite_wm = entries + display->guard_size;
4782 return *sprite_wm > 0x3ff ? false : true;
4785 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4786 uint32_t sprite_width, int pixel_size)
4788 struct drm_i915_private *dev_priv = dev->dev_private;
4789 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4796 reg = WM0_PIPEA_ILK;
4799 reg = WM0_PIPEB_ILK;
4802 reg = WM0_PIPEC_IVB;
4805 return; /* bad pipe */
4808 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4809 &sandybridge_display_wm_info,
4810 latency, &sprite_wm);
4812 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4817 val = I915_READ(reg);
4818 val &= ~WM0_PIPE_SPRITE_MASK;
4819 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4820 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4823 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4825 &sandybridge_display_srwm_info,
4826 SNB_READ_WM1_LATENCY() * 500,
4829 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4833 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4835 /* Only IVB has two more LP watermarks for sprite */
4836 if (!IS_IVYBRIDGE(dev))
4839 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4841 &sandybridge_display_srwm_info,
4842 SNB_READ_WM2_LATENCY() * 500,
4845 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4849 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4851 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4853 &sandybridge_display_srwm_info,
4854 SNB_READ_WM3_LATENCY() * 500,
4857 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4861 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4865 * intel_update_watermarks - update FIFO watermark values based on current modes
4867 * Calculate watermark values for the various WM regs based on current mode
4868 * and plane configuration.
4870 * There are several cases to deal with here:
4871 * - normal (i.e. non-self-refresh)
4872 * - self-refresh (SR) mode
4873 * - lines are large relative to FIFO size (buffer can hold up to 2)
4874 * - lines are small relative to FIFO size (buffer can hold more than 2
4875 * lines), so need to account for TLB latency
4877 * The normal calculation is:
4878 * watermark = dotclock * bytes per pixel * latency
4879 * where latency is platform & configuration dependent (we assume pessimal
4882 * The SR calculation is:
4883 * watermark = (trunc(latency/line time)+1) * surface width *
4886 * line time = htotal / dotclock
4887 * surface width = hdisplay for normal plane and 64 for cursor
4888 * and latency is assumed to be high, as above.
4890 * The final value programmed to the register should always be rounded up,
4891 * and include an extra 2 entries to account for clock crossings.
4893 * We don't use the sprite, so we can ignore that. And on Crestline we have
4894 * to set the non-SR watermarks to 8.
4896 static void intel_update_watermarks(struct drm_device *dev)
4898 struct drm_i915_private *dev_priv = dev->dev_private;
4900 if (dev_priv->display.update_wm)
4901 dev_priv->display.update_wm(dev);
4904 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4905 uint32_t sprite_width, int pixel_size)
4907 struct drm_i915_private *dev_priv = dev->dev_private;
4909 if (dev_priv->display.update_sprite_wm)
4910 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4914 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4916 if (i915_panel_use_ssc >= 0)
4917 return i915_panel_use_ssc != 0;
4918 return dev_priv->lvds_use_ssc
4919 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4923 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4924 * @crtc: CRTC structure
4925 * @mode: requested mode
4927 * A pipe may be connected to one or more outputs. Based on the depth of the
4928 * attached framebuffer, choose a good color depth to use on the pipe.
4930 * If possible, match the pipe depth to the fb depth. In some cases, this
4931 * isn't ideal, because the connected output supports a lesser or restricted
4932 * set of depths. Resolve that here:
4933 * LVDS typically supports only 6bpc, so clamp down in that case
4934 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4935 * Displays may support a restricted set as well, check EDID and clamp as
4937 * DP may want to dither down to 6bpc to fit larger modes
4940 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4941 * true if they don't match).
4943 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4944 unsigned int *pipe_bpp,
4945 struct drm_display_mode *mode)
4947 struct drm_device *dev = crtc->dev;
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 struct drm_encoder *encoder;
4950 struct drm_connector *connector;
4951 unsigned int display_bpc = UINT_MAX, bpc;
4953 /* Walk the encoders & connectors on this crtc, get min bpc */
4954 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4955 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4957 if (encoder->crtc != crtc)
4960 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4961 unsigned int lvds_bpc;
4963 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4969 if (lvds_bpc < display_bpc) {
4970 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4971 display_bpc = lvds_bpc;
4976 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4977 /* Use VBT settings if we have an eDP panel */
4978 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4980 if (edp_bpc < display_bpc) {
4981 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4982 display_bpc = edp_bpc;
4987 /* Not one of the known troublemakers, check the EDID */
4988 list_for_each_entry(connector, &dev->mode_config.connector_list,
4990 if (connector->encoder != encoder)
4993 /* Don't use an invalid EDID bpc value */
4994 if (connector->display_info.bpc &&
4995 connector->display_info.bpc < display_bpc) {
4996 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4997 display_bpc = connector->display_info.bpc;
5002 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5003 * through, clamp it down. (Note: >12bpc will be caught below.)
5005 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5006 if (display_bpc > 8 && display_bpc < 12) {
5007 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5010 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5016 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5017 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5022 * We could just drive the pipe at the highest bpc all the time and
5023 * enable dithering as needed, but that costs bandwidth. So choose
5024 * the minimum value that expresses the full color range of the fb but
5025 * also stays within the max display bpc discovered above.
5028 switch (crtc->fb->depth) {
5030 bpc = 8; /* since we go through a colormap */
5034 bpc = 6; /* min is 18bpp */
5046 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5047 bpc = min((unsigned int)8, display_bpc);
5051 display_bpc = min(display_bpc, bpc);
5053 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5056 *pipe_bpp = display_bpc * 3;
5058 return display_bpc != bpc;
5061 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5063 struct drm_device *dev = crtc->dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5067 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5068 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5069 refclk = dev_priv->lvds_ssc_freq * 1000;
5070 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5072 } else if (!IS_GEN2(dev)) {
5081 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5082 intel_clock_t *clock)
5084 /* SDVO TV has fixed PLL values depend on its clock range,
5085 this mirrors vbios setting. */
5086 if (adjusted_mode->clock >= 100000
5087 && adjusted_mode->clock < 140500) {
5093 } else if (adjusted_mode->clock >= 140500
5094 && adjusted_mode->clock <= 200000) {
5103 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5104 intel_clock_t *clock,
5105 intel_clock_t *reduced_clock)
5107 struct drm_device *dev = crtc->dev;
5108 struct drm_i915_private *dev_priv = dev->dev_private;
5109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5110 int pipe = intel_crtc->pipe;
5113 if (IS_PINEVIEW(dev)) {
5114 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5116 fp2 = (1 << reduced_clock->n) << 16 |
5117 reduced_clock->m1 << 8 | reduced_clock->m2;
5119 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5121 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5125 I915_WRITE(FP0(pipe), fp);
5127 intel_crtc->lowfreq_avail = false;
5128 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5129 reduced_clock && i915_powersave) {
5130 I915_WRITE(FP1(pipe), fp2);
5131 intel_crtc->lowfreq_avail = true;
5133 I915_WRITE(FP1(pipe), fp);
5137 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
5138 struct drm_display_mode *adjusted_mode)
5140 struct drm_device *dev = crtc->dev;
5141 struct drm_i915_private *dev_priv = dev->dev_private;
5142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5143 int pipe = intel_crtc->pipe;
5144 u32 temp, lvds_sync = 0;
5146 temp = I915_READ(LVDS);
5147 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5149 temp |= LVDS_PIPEB_SELECT;
5151 temp &= ~LVDS_PIPEB_SELECT;
5153 /* set the corresponsding LVDS_BORDER bit */
5154 temp |= dev_priv->lvds_border_bits;
5155 /* Set the B0-B3 data pairs corresponding to whether we're going to
5156 * set the DPLLs for dual-channel mode or not.
5159 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5161 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5163 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5164 * appropriately here, but we need to look more thoroughly into how
5165 * panels behave in the two modes.
5167 /* set the dithering flag on LVDS as needed */
5168 if (INTEL_INFO(dev)->gen >= 4) {
5169 if (dev_priv->lvds_dither)
5170 temp |= LVDS_ENABLE_DITHER;
5172 temp &= ~LVDS_ENABLE_DITHER;
5174 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5175 lvds_sync |= LVDS_HSYNC_POLARITY;
5176 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5177 lvds_sync |= LVDS_VSYNC_POLARITY;
5178 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5180 char flags[2] = "-+";
5181 DRM_INFO("Changing LVDS panel from "
5182 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5183 flags[!(temp & LVDS_HSYNC_POLARITY)],
5184 flags[!(temp & LVDS_VSYNC_POLARITY)],
5185 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5186 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5187 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5190 I915_WRITE(LVDS, temp);
5193 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5194 struct drm_display_mode *mode,
5195 struct drm_display_mode *adjusted_mode,
5197 struct drm_framebuffer *old_fb)
5199 struct drm_device *dev = crtc->dev;
5200 struct drm_i915_private *dev_priv = dev->dev_private;
5201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5202 int pipe = intel_crtc->pipe;
5203 int plane = intel_crtc->plane;
5204 int refclk, num_connectors = 0;
5205 intel_clock_t clock, reduced_clock;
5206 u32 dpll, dspcntr, pipeconf, vsyncshift;
5207 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5208 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5209 struct drm_mode_config *mode_config = &dev->mode_config;
5210 struct intel_encoder *encoder;
5211 const intel_limit_t *limit;
5215 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5216 if (encoder->base.crtc != crtc)
5219 switch (encoder->type) {
5220 case INTEL_OUTPUT_LVDS:
5223 case INTEL_OUTPUT_SDVO:
5224 case INTEL_OUTPUT_HDMI:
5226 if (encoder->needs_tv_clock)
5229 case INTEL_OUTPUT_DVO:
5232 case INTEL_OUTPUT_TVOUT:
5235 case INTEL_OUTPUT_ANALOG:
5238 case INTEL_OUTPUT_DISPLAYPORT:
5246 refclk = i9xx_get_refclk(crtc, num_connectors);
5249 * Returns a set of divisors for the desired target clock with the given
5250 * refclk, or FALSE. The returned values represent the clock equation:
5251 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5253 limit = intel_limit(crtc, refclk);
5254 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5257 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5261 /* Ensure that the cursor is valid for the new mode before changing... */
5262 intel_crtc_update_cursor(crtc, true);
5264 if (is_lvds && dev_priv->lvds_downclock_avail) {
5266 * Ensure we match the reduced clock's P to the target clock.
5267 * If the clocks don't match, we can't switch the display clock
5268 * by using the FP0/FP1. In such case we will disable the LVDS
5269 * downclock feature.
5271 has_reduced_clock = limit->find_pll(limit, crtc,
5272 dev_priv->lvds_downclock,
5278 if (is_sdvo && is_tv)
5279 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5281 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5282 &reduced_clock : NULL);
5284 dpll = DPLL_VGA_MODE_DIS;
5286 if (!IS_GEN2(dev)) {
5288 dpll |= DPLLB_MODE_LVDS;
5290 dpll |= DPLLB_MODE_DAC_SERIAL;
5292 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5293 if (pixel_multiplier > 1) {
5294 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5295 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5297 dpll |= DPLL_DVO_HIGH_SPEED;
5300 dpll |= DPLL_DVO_HIGH_SPEED;
5302 /* compute bitmask from p1 value */
5303 if (IS_PINEVIEW(dev))
5304 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5306 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5307 if (IS_G4X(dev) && has_reduced_clock)
5308 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5312 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5315 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5318 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5321 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5324 if (INTEL_INFO(dev)->gen >= 4)
5325 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5328 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5331 dpll |= PLL_P1_DIVIDE_BY_TWO;
5333 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5335 dpll |= PLL_P2_DIVIDE_BY_4;
5339 if (is_sdvo && is_tv)
5340 dpll |= PLL_REF_INPUT_TVCLKINBC;
5342 /* XXX: just matching BIOS for now */
5343 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5345 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5346 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5348 dpll |= PLL_REF_INPUT_DREFCLK;
5350 /* setup pipeconf */
5351 pipeconf = I915_READ(PIPECONF(pipe));
5353 /* Set up the display plane register */
5354 dspcntr = DISPPLANE_GAMMA_ENABLE;
5357 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5359 dspcntr |= DISPPLANE_SEL_PIPE_B;
5361 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5362 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5365 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5369 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5370 pipeconf |= PIPECONF_DOUBLE_WIDE;
5372 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5375 /* default to 8bpc */
5376 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5378 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5379 pipeconf |= PIPECONF_BPP_6 |
5380 PIPECONF_DITHER_EN |
5381 PIPECONF_DITHER_TYPE_SP;
5385 dpll |= DPLL_VCO_ENABLE;
5387 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5388 drm_mode_debug_printmodeline(mode);
5390 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5392 POSTING_READ(DPLL(pipe));
5395 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5396 * This is an exception to the general rule that mode_set doesn't turn
5399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5400 intel_update_lvds(crtc, &clock, adjusted_mode);
5403 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5406 I915_WRITE(DPLL(pipe), dpll);
5408 /* Wait for the clocks to stabilize. */
5409 POSTING_READ(DPLL(pipe));
5412 if (INTEL_INFO(dev)->gen >= 4) {
5415 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5417 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5421 I915_WRITE(DPLL_MD(pipe), temp);
5423 /* The pixel multiplier can only be updated once the
5424 * DPLL is enabled and the clocks are stable.
5426 * So write it again.
5428 I915_WRITE(DPLL(pipe), dpll);
5431 if (HAS_PIPE_CXSR(dev)) {
5432 if (intel_crtc->lowfreq_avail) {
5433 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5434 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5436 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5437 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5441 pipeconf &= ~PIPECONF_INTERLACE_MASK;
5442 if (!IS_GEN2(dev) &&
5443 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5444 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5445 /* the chip adds 2 halflines automatically */
5446 adjusted_mode->crtc_vtotal -= 1;
5447 adjusted_mode->crtc_vblank_end -= 1;
5448 vsyncshift = adjusted_mode->crtc_hsync_start
5449 - adjusted_mode->crtc_htotal/2;
5451 pipeconf |= PIPECONF_PROGRESSIVE;
5456 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5458 I915_WRITE(HTOTAL(pipe),
5459 (adjusted_mode->crtc_hdisplay - 1) |
5460 ((adjusted_mode->crtc_htotal - 1) << 16));
5461 I915_WRITE(HBLANK(pipe),
5462 (adjusted_mode->crtc_hblank_start - 1) |
5463 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5464 I915_WRITE(HSYNC(pipe),
5465 (adjusted_mode->crtc_hsync_start - 1) |
5466 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5468 I915_WRITE(VTOTAL(pipe),
5469 (adjusted_mode->crtc_vdisplay - 1) |
5470 ((adjusted_mode->crtc_vtotal - 1) << 16));
5471 I915_WRITE(VBLANK(pipe),
5472 (adjusted_mode->crtc_vblank_start - 1) |
5473 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5474 I915_WRITE(VSYNC(pipe),
5475 (adjusted_mode->crtc_vsync_start - 1) |
5476 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5478 /* pipesrc and dspsize control the size that is scaled from,
5479 * which should always be the user's requested size.
5481 I915_WRITE(DSPSIZE(plane),
5482 ((mode->vdisplay - 1) << 16) |
5483 (mode->hdisplay - 1));
5484 I915_WRITE(DSPPOS(plane), 0);
5485 I915_WRITE(PIPESRC(pipe),
5486 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5488 I915_WRITE(PIPECONF(pipe), pipeconf);
5489 POSTING_READ(PIPECONF(pipe));
5490 intel_enable_pipe(dev_priv, pipe, false);
5492 intel_wait_for_vblank(dev, pipe);
5494 I915_WRITE(DSPCNTR(plane), dspcntr);
5495 POSTING_READ(DSPCNTR(plane));
5496 intel_enable_plane(dev_priv, plane, pipe);
5498 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5500 intel_update_watermarks(dev);
5506 * Initialize reference clocks when the driver loads
5508 void ironlake_init_pch_refclk(struct drm_device *dev)
5510 struct drm_i915_private *dev_priv = dev->dev_private;
5511 struct drm_mode_config *mode_config = &dev->mode_config;
5512 struct intel_encoder *encoder;
5514 bool has_lvds = false;
5515 bool has_cpu_edp = false;
5516 bool has_pch_edp = false;
5517 bool has_panel = false;
5518 bool has_ck505 = false;
5519 bool can_ssc = false;
5521 /* We need to take the global config into account */
5522 list_for_each_entry(encoder, &mode_config->encoder_list,
5524 switch (encoder->type) {
5525 case INTEL_OUTPUT_LVDS:
5529 case INTEL_OUTPUT_EDP:
5531 if (intel_encoder_is_pch_edp(&encoder->base))
5539 if (HAS_PCH_IBX(dev)) {
5540 has_ck505 = dev_priv->display_clock_mode;
5541 can_ssc = has_ck505;
5547 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5548 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5551 /* Ironlake: try to setup display ref clock before DPLL
5552 * enabling. This is only under driver's control after
5553 * PCH B stepping, previous chipset stepping should be
5554 * ignoring this setting.
5556 temp = I915_READ(PCH_DREF_CONTROL);
5557 /* Always enable nonspread source */
5558 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5561 temp |= DREF_NONSPREAD_CK505_ENABLE;
5563 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5566 temp &= ~DREF_SSC_SOURCE_MASK;
5567 temp |= DREF_SSC_SOURCE_ENABLE;
5569 /* SSC must be turned on before enabling the CPU output */
5570 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5571 DRM_DEBUG_KMS("Using SSC on panel\n");
5572 temp |= DREF_SSC1_ENABLE;
5575 /* Get SSC going before enabling the outputs */
5576 I915_WRITE(PCH_DREF_CONTROL, temp);
5577 POSTING_READ(PCH_DREF_CONTROL);
5580 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5582 /* Enable CPU source on CPU attached eDP */
5584 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5585 DRM_DEBUG_KMS("Using SSC on eDP\n");
5586 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5589 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5591 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5593 I915_WRITE(PCH_DREF_CONTROL, temp);
5594 POSTING_READ(PCH_DREF_CONTROL);
5597 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5599 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5601 /* Turn off CPU output */
5602 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5604 I915_WRITE(PCH_DREF_CONTROL, temp);
5605 POSTING_READ(PCH_DREF_CONTROL);
5608 /* Turn off the SSC source */
5609 temp &= ~DREF_SSC_SOURCE_MASK;
5610 temp |= DREF_SSC_SOURCE_DISABLE;
5613 temp &= ~ DREF_SSC1_ENABLE;
5615 I915_WRITE(PCH_DREF_CONTROL, temp);
5616 POSTING_READ(PCH_DREF_CONTROL);
5621 static int ironlake_get_refclk(struct drm_crtc *crtc)
5623 struct drm_device *dev = crtc->dev;
5624 struct drm_i915_private *dev_priv = dev->dev_private;
5625 struct intel_encoder *encoder;
5626 struct drm_mode_config *mode_config = &dev->mode_config;
5627 struct intel_encoder *edp_encoder = NULL;
5628 int num_connectors = 0;
5629 bool is_lvds = false;
5631 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5632 if (encoder->base.crtc != crtc)
5635 switch (encoder->type) {
5636 case INTEL_OUTPUT_LVDS:
5639 case INTEL_OUTPUT_EDP:
5640 edp_encoder = encoder;
5646 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5647 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5648 dev_priv->lvds_ssc_freq);
5649 return dev_priv->lvds_ssc_freq * 1000;
5655 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5656 struct drm_display_mode *mode,
5657 struct drm_display_mode *adjusted_mode,
5659 struct drm_framebuffer *old_fb)
5661 struct drm_device *dev = crtc->dev;
5662 struct drm_i915_private *dev_priv = dev->dev_private;
5663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5664 int pipe = intel_crtc->pipe;
5665 int plane = intel_crtc->plane;
5666 int refclk, num_connectors = 0;
5667 intel_clock_t clock, reduced_clock;
5668 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5669 bool ok, has_reduced_clock = false, is_sdvo = false;
5670 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5671 struct intel_encoder *has_edp_encoder = NULL;
5672 struct drm_mode_config *mode_config = &dev->mode_config;
5673 struct intel_encoder *encoder;
5674 const intel_limit_t *limit;
5676 struct fdi_m_n m_n = {0};
5679 int target_clock, pixel_multiplier, lane, link_bw, factor;
5680 unsigned int pipe_bpp;
5683 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5684 if (encoder->base.crtc != crtc)
5687 switch (encoder->type) {
5688 case INTEL_OUTPUT_LVDS:
5691 case INTEL_OUTPUT_SDVO:
5692 case INTEL_OUTPUT_HDMI:
5694 if (encoder->needs_tv_clock)
5697 case INTEL_OUTPUT_TVOUT:
5700 case INTEL_OUTPUT_ANALOG:
5703 case INTEL_OUTPUT_DISPLAYPORT:
5706 case INTEL_OUTPUT_EDP:
5707 has_edp_encoder = encoder;
5714 refclk = ironlake_get_refclk(crtc);
5717 * Returns a set of divisors for the desired target clock with the given
5718 * refclk, or FALSE. The returned values represent the clock equation:
5719 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5721 limit = intel_limit(crtc, refclk);
5722 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5725 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5729 /* Ensure that the cursor is valid for the new mode before changing... */
5730 intel_crtc_update_cursor(crtc, true);
5732 if (is_lvds && dev_priv->lvds_downclock_avail) {
5734 * Ensure we match the reduced clock's P to the target clock.
5735 * If the clocks don't match, we can't switch the display clock
5736 * by using the FP0/FP1. In such case we will disable the LVDS
5737 * downclock feature.
5739 has_reduced_clock = limit->find_pll(limit, crtc,
5740 dev_priv->lvds_downclock,
5745 /* SDVO TV has fixed PLL values depend on its clock range,
5746 this mirrors vbios setting. */
5747 if (is_sdvo && is_tv) {
5748 if (adjusted_mode->clock >= 100000
5749 && adjusted_mode->clock < 140500) {
5755 } else if (adjusted_mode->clock >= 140500
5756 && adjusted_mode->clock <= 200000) {
5766 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5768 /* CPU eDP doesn't require FDI link, so just set DP M/N
5769 according to current link config */
5770 if (has_edp_encoder &&
5771 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5772 target_clock = mode->clock;
5773 intel_edp_link_config(has_edp_encoder,
5776 /* [e]DP over FDI requires target mode clock
5777 instead of link clock */
5778 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5779 target_clock = mode->clock;
5781 target_clock = adjusted_mode->clock;
5783 /* FDI is a binary signal running at ~2.7GHz, encoding
5784 * each output octet as 10 bits. The actual frequency
5785 * is stored as a divider into a 100MHz clock, and the
5786 * mode pixel clock is stored in units of 1KHz.
5787 * Hence the bw of each lane in terms of the mode signal
5790 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5793 /* determine panel color depth */
5794 temp = I915_READ(PIPECONF(pipe));
5795 temp &= ~PIPE_BPC_MASK;
5796 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5811 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5818 intel_crtc->bpp = pipe_bpp;
5819 I915_WRITE(PIPECONF(pipe), temp);
5823 * Account for spread spectrum to avoid
5824 * oversubscribing the link. Max center spread
5825 * is 2.5%; use 5% for safety's sake.
5827 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5828 lane = bps / (link_bw * 8) + 1;
5831 intel_crtc->fdi_lanes = lane;
5833 if (pixel_multiplier > 1)
5834 link_bw *= pixel_multiplier;
5835 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5838 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5839 if (has_reduced_clock)
5840 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5843 /* Enable autotuning of the PLL clock (if permissible) */
5846 if ((intel_panel_use_ssc(dev_priv) &&
5847 dev_priv->lvds_ssc_freq == 100) ||
5848 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5850 } else if (is_sdvo && is_tv)
5853 if (clock.m < factor * clock.n)
5859 dpll |= DPLLB_MODE_LVDS;
5861 dpll |= DPLLB_MODE_DAC_SERIAL;
5863 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5864 if (pixel_multiplier > 1) {
5865 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5867 dpll |= DPLL_DVO_HIGH_SPEED;
5869 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5870 dpll |= DPLL_DVO_HIGH_SPEED;
5872 /* compute bitmask from p1 value */
5873 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5875 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5879 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5882 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5885 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5888 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5892 if (is_sdvo && is_tv)
5893 dpll |= PLL_REF_INPUT_TVCLKINBC;
5895 /* XXX: just matching BIOS for now */
5896 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5898 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5899 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5901 dpll |= PLL_REF_INPUT_DREFCLK;
5903 /* setup pipeconf */
5904 pipeconf = I915_READ(PIPECONF(pipe));
5906 /* Set up the display plane register */
5907 dspcntr = DISPPLANE_GAMMA_ENABLE;
5909 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5910 drm_mode_debug_printmodeline(mode);
5912 /* PCH eDP needs FDI, but CPU eDP does not */
5913 if (!intel_crtc->no_pll) {
5914 if (!has_edp_encoder ||
5915 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5916 I915_WRITE(PCH_FP0(pipe), fp);
5917 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5919 POSTING_READ(PCH_DPLL(pipe));
5923 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5924 fp == I915_READ(PCH_FP0(0))) {
5925 intel_crtc->use_pll_a = true;
5926 DRM_DEBUG_KMS("using pipe a dpll\n");
5927 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5928 fp == I915_READ(PCH_FP0(1))) {
5929 intel_crtc->use_pll_a = false;
5930 DRM_DEBUG_KMS("using pipe b dpll\n");
5932 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5937 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5938 * This is an exception to the general rule that mode_set doesn't turn
5942 temp = I915_READ(PCH_LVDS);
5943 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5944 if (HAS_PCH_CPT(dev)) {
5945 temp &= ~PORT_TRANS_SEL_MASK;
5946 temp |= PORT_TRANS_SEL_CPT(pipe);
5949 temp |= LVDS_PIPEB_SELECT;
5951 temp &= ~LVDS_PIPEB_SELECT;
5954 /* set the corresponsding LVDS_BORDER bit */
5955 temp |= dev_priv->lvds_border_bits;
5956 /* Set the B0-B3 data pairs corresponding to whether we're going to
5957 * set the DPLLs for dual-channel mode or not.
5960 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5962 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5964 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5965 * appropriately here, but we need to look more thoroughly into how
5966 * panels behave in the two modes.
5968 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5969 lvds_sync |= LVDS_HSYNC_POLARITY;
5970 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5971 lvds_sync |= LVDS_VSYNC_POLARITY;
5972 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5974 char flags[2] = "-+";
5975 DRM_INFO("Changing LVDS panel from "
5976 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5977 flags[!(temp & LVDS_HSYNC_POLARITY)],
5978 flags[!(temp & LVDS_VSYNC_POLARITY)],
5979 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5980 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5981 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5984 I915_WRITE(PCH_LVDS, temp);
5987 pipeconf &= ~PIPECONF_DITHER_EN;
5988 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5989 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5990 pipeconf |= PIPECONF_DITHER_EN;
5991 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5993 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5994 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5996 /* For non-DP output, clear any trans DP clock recovery setting.*/
5997 I915_WRITE(TRANSDATA_M1(pipe), 0);
5998 I915_WRITE(TRANSDATA_N1(pipe), 0);
5999 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
6000 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
6003 if (!intel_crtc->no_pll &&
6004 (!has_edp_encoder ||
6005 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
6006 I915_WRITE(PCH_DPLL(pipe), dpll);
6008 /* Wait for the clocks to stabilize. */
6009 POSTING_READ(PCH_DPLL(pipe));
6012 /* The pixel multiplier can only be updated once the
6013 * DPLL is enabled and the clocks are stable.
6015 * So write it again.
6017 I915_WRITE(PCH_DPLL(pipe), dpll);
6020 intel_crtc->lowfreq_avail = false;
6021 if (!intel_crtc->no_pll) {
6022 if (is_lvds && has_reduced_clock && i915_powersave) {
6023 I915_WRITE(PCH_FP1(pipe), fp2);
6024 intel_crtc->lowfreq_avail = true;
6025 if (HAS_PIPE_CXSR(dev)) {
6026 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6027 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6030 I915_WRITE(PCH_FP1(pipe), fp);
6031 if (HAS_PIPE_CXSR(dev)) {
6032 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6033 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6038 pipeconf &= ~PIPECONF_INTERLACE_MASK;
6039 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6040 pipeconf |= PIPECONF_INTERLACED_ILK;
6041 /* the chip adds 2 halflines automatically */
6042 adjusted_mode->crtc_vtotal -= 1;
6043 adjusted_mode->crtc_vblank_end -= 1;
6044 I915_WRITE(VSYNCSHIFT(pipe),
6045 adjusted_mode->crtc_hsync_start
6046 - adjusted_mode->crtc_htotal/2);
6048 pipeconf |= PIPECONF_PROGRESSIVE;
6049 I915_WRITE(VSYNCSHIFT(pipe), 0);
6052 I915_WRITE(HTOTAL(pipe),
6053 (adjusted_mode->crtc_hdisplay - 1) |
6054 ((adjusted_mode->crtc_htotal - 1) << 16));
6055 I915_WRITE(HBLANK(pipe),
6056 (adjusted_mode->crtc_hblank_start - 1) |
6057 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6058 I915_WRITE(HSYNC(pipe),
6059 (adjusted_mode->crtc_hsync_start - 1) |
6060 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6062 I915_WRITE(VTOTAL(pipe),
6063 (adjusted_mode->crtc_vdisplay - 1) |
6064 ((adjusted_mode->crtc_vtotal - 1) << 16));
6065 I915_WRITE(VBLANK(pipe),
6066 (adjusted_mode->crtc_vblank_start - 1) |
6067 ((adjusted_mode->crtc_vblank_end - 1) << 16));
6068 I915_WRITE(VSYNC(pipe),
6069 (adjusted_mode->crtc_vsync_start - 1) |
6070 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6072 /* pipesrc controls the size that is scaled from, which should
6073 * always be the user's requested size.
6075 I915_WRITE(PIPESRC(pipe),
6076 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6078 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6079 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6080 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6081 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6083 if (has_edp_encoder &&
6084 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6085 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6088 I915_WRITE(PIPECONF(pipe), pipeconf);
6089 POSTING_READ(PIPECONF(pipe));
6091 intel_wait_for_vblank(dev, pipe);
6093 I915_WRITE(DSPCNTR(plane), dspcntr);
6094 POSTING_READ(DSPCNTR(plane));
6096 ret = intel_pipe_set_base(crtc, x, y, old_fb);
6098 intel_update_watermarks(dev);
6103 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6104 struct drm_display_mode *mode,
6105 struct drm_display_mode *adjusted_mode,
6107 struct drm_framebuffer *old_fb)
6109 struct drm_device *dev = crtc->dev;
6110 struct drm_i915_private *dev_priv = dev->dev_private;
6111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6112 int pipe = intel_crtc->pipe;
6115 drm_vblank_pre_modeset(dev, pipe);
6117 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6119 drm_vblank_post_modeset(dev, pipe);
6122 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6124 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6129 static bool intel_eld_uptodate(struct drm_connector *connector,
6130 int reg_eldv, uint32_t bits_eldv,
6131 int reg_elda, uint32_t bits_elda,
6134 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6135 uint8_t *eld = connector->eld;
6138 i = I915_READ(reg_eldv);
6147 i = I915_READ(reg_elda);
6149 I915_WRITE(reg_elda, i);
6151 for (i = 0; i < eld[2]; i++)
6152 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6158 static void g4x_write_eld(struct drm_connector *connector,
6159 struct drm_crtc *crtc)
6161 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6162 uint8_t *eld = connector->eld;
6167 i = I915_READ(G4X_AUD_VID_DID);
6169 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6170 eldv = G4X_ELDV_DEVCL_DEVBLC;
6172 eldv = G4X_ELDV_DEVCTG;
6174 if (intel_eld_uptodate(connector,
6175 G4X_AUD_CNTL_ST, eldv,
6176 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6177 G4X_HDMIW_HDMIEDID))
6180 i = I915_READ(G4X_AUD_CNTL_ST);
6181 i &= ~(eldv | G4X_ELD_ADDR);
6182 len = (i >> 9) & 0x1f; /* ELD buffer size */
6183 I915_WRITE(G4X_AUD_CNTL_ST, i);
6188 len = min_t(uint8_t, eld[2], len);
6189 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6190 for (i = 0; i < len; i++)
6191 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6193 i = I915_READ(G4X_AUD_CNTL_ST);
6195 I915_WRITE(G4X_AUD_CNTL_ST, i);
6198 static void ironlake_write_eld(struct drm_connector *connector,
6199 struct drm_crtc *crtc)
6201 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6202 uint8_t *eld = connector->eld;
6211 if (HAS_PCH_IBX(connector->dev)) {
6212 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6213 aud_config = IBX_AUD_CONFIG_A;
6214 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6215 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6217 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6218 aud_config = CPT_AUD_CONFIG_A;
6219 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6220 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6223 i = to_intel_crtc(crtc)->pipe;
6224 hdmiw_hdmiedid += i * 0x100;
6225 aud_cntl_st += i * 0x100;
6226 aud_config += i * 0x100;
6228 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6230 i = I915_READ(aud_cntl_st);
6231 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6233 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6234 /* operate blindly on all ports */
6235 eldv = IBX_ELD_VALIDB;
6236 eldv |= IBX_ELD_VALIDB << 4;
6237 eldv |= IBX_ELD_VALIDB << 8;
6239 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6240 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6243 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6244 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6245 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6246 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6248 I915_WRITE(aud_config, 0);
6250 if (intel_eld_uptodate(connector,
6251 aud_cntrl_st2, eldv,
6252 aud_cntl_st, IBX_ELD_ADDRESS,
6256 i = I915_READ(aud_cntrl_st2);
6258 I915_WRITE(aud_cntrl_st2, i);
6263 i = I915_READ(aud_cntl_st);
6264 i &= ~IBX_ELD_ADDRESS;
6265 I915_WRITE(aud_cntl_st, i);
6267 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6268 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6269 for (i = 0; i < len; i++)
6270 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6272 i = I915_READ(aud_cntrl_st2);
6274 I915_WRITE(aud_cntrl_st2, i);
6277 void intel_write_eld(struct drm_encoder *encoder,
6278 struct drm_display_mode *mode)
6280 struct drm_crtc *crtc = encoder->crtc;
6281 struct drm_connector *connector;
6282 struct drm_device *dev = encoder->dev;
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6285 connector = drm_select_eld(encoder, mode);
6289 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6291 drm_get_connector_name(connector),
6292 connector->encoder->base.id,
6293 drm_get_encoder_name(connector->encoder));
6295 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6297 if (dev_priv->display.write_eld)
6298 dev_priv->display.write_eld(connector, crtc);
6301 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6302 void intel_crtc_load_lut(struct drm_crtc *crtc)
6304 struct drm_device *dev = crtc->dev;
6305 struct drm_i915_private *dev_priv = dev->dev_private;
6306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6307 int palreg = PALETTE(intel_crtc->pipe);
6310 /* The clocks have to be on to load the palette. */
6314 /* use legacy palette for Ironlake */
6315 if (HAS_PCH_SPLIT(dev))
6316 palreg = LGC_PALETTE(intel_crtc->pipe);
6318 for (i = 0; i < 256; i++) {
6319 I915_WRITE(palreg + 4 * i,
6320 (intel_crtc->lut_r[i] << 16) |
6321 (intel_crtc->lut_g[i] << 8) |
6322 intel_crtc->lut_b[i]);
6326 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6328 struct drm_device *dev = crtc->dev;
6329 struct drm_i915_private *dev_priv = dev->dev_private;
6330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6331 bool visible = base != 0;
6334 if (intel_crtc->cursor_visible == visible)
6337 cntl = I915_READ(_CURACNTR);
6339 /* On these chipsets we can only modify the base whilst
6340 * the cursor is disabled.
6342 I915_WRITE(_CURABASE, base);
6344 cntl &= ~(CURSOR_FORMAT_MASK);
6345 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6346 cntl |= CURSOR_ENABLE |
6347 CURSOR_GAMMA_ENABLE |
6350 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6351 I915_WRITE(_CURACNTR, cntl);
6353 intel_crtc->cursor_visible = visible;
6356 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6358 struct drm_device *dev = crtc->dev;
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361 int pipe = intel_crtc->pipe;
6362 bool visible = base != 0;
6364 if (intel_crtc->cursor_visible != visible) {
6365 uint32_t cntl = I915_READ(CURCNTR(pipe));
6367 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6368 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6369 cntl |= pipe << 28; /* Connect to correct pipe */
6371 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6372 cntl |= CURSOR_MODE_DISABLE;
6374 I915_WRITE(CURCNTR(pipe), cntl);
6376 intel_crtc->cursor_visible = visible;
6378 /* and commit changes on next vblank */
6379 I915_WRITE(CURBASE(pipe), base);
6382 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6384 struct drm_device *dev = crtc->dev;
6385 struct drm_i915_private *dev_priv = dev->dev_private;
6386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6387 int pipe = intel_crtc->pipe;
6388 bool visible = base != 0;
6390 if (intel_crtc->cursor_visible != visible) {
6391 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6393 cntl &= ~CURSOR_MODE;
6394 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6396 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6397 cntl |= CURSOR_MODE_DISABLE;
6399 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6401 intel_crtc->cursor_visible = visible;
6403 /* and commit changes on next vblank */
6404 I915_WRITE(CURBASE_IVB(pipe), base);
6407 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6408 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6411 struct drm_device *dev = crtc->dev;
6412 struct drm_i915_private *dev_priv = dev->dev_private;
6413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6414 int pipe = intel_crtc->pipe;
6415 int x = intel_crtc->cursor_x;
6416 int y = intel_crtc->cursor_y;
6422 if (on && crtc->enabled && crtc->fb) {
6423 base = intel_crtc->cursor_addr;
6424 if (x > (int) crtc->fb->width)
6427 if (y > (int) crtc->fb->height)
6433 if (x + intel_crtc->cursor_width < 0)
6436 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6439 pos |= x << CURSOR_X_SHIFT;
6442 if (y + intel_crtc->cursor_height < 0)
6445 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6448 pos |= y << CURSOR_Y_SHIFT;
6450 visible = base != 0;
6451 if (!visible && !intel_crtc->cursor_visible)
6454 if (IS_IVYBRIDGE(dev)) {
6455 I915_WRITE(CURPOS_IVB(pipe), pos);
6456 ivb_update_cursor(crtc, base);
6458 I915_WRITE(CURPOS(pipe), pos);
6459 if (IS_845G(dev) || IS_I865G(dev))
6460 i845_update_cursor(crtc, base);
6462 i9xx_update_cursor(crtc, base);
6466 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6469 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6470 struct drm_file *file,
6472 uint32_t width, uint32_t height)
6474 struct drm_device *dev = crtc->dev;
6475 struct drm_i915_private *dev_priv = dev->dev_private;
6476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6477 struct drm_i915_gem_object *obj;
6481 DRM_DEBUG_KMS("\n");
6483 /* if we want to turn off the cursor ignore width and height */
6485 DRM_DEBUG_KMS("cursor off\n");
6488 mutex_lock(&dev->struct_mutex);
6492 /* Currently we only support 64x64 cursors */
6493 if (width != 64 || height != 64) {
6494 DRM_ERROR("we currently only support 64x64 cursors\n");
6498 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6499 if (&obj->base == NULL)
6502 if (obj->base.size < width * height * 4) {
6503 DRM_ERROR("buffer is to small\n");
6508 /* we only need to pin inside GTT if cursor is non-phy */
6509 mutex_lock(&dev->struct_mutex);
6510 if (!dev_priv->info->cursor_needs_physical) {
6511 if (obj->tiling_mode) {
6512 DRM_ERROR("cursor cannot be tiled\n");
6517 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6519 DRM_ERROR("failed to move cursor bo into the GTT\n");
6523 ret = i915_gem_object_put_fence(obj);
6525 DRM_ERROR("failed to release fence for cursor");
6529 addr = obj->gtt_offset;
6531 int align = IS_I830(dev) ? 16 * 1024 : 256;
6532 ret = i915_gem_attach_phys_object(dev, obj,
6533 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6536 DRM_ERROR("failed to attach phys object\n");
6539 addr = obj->phys_obj->handle->busaddr;
6543 I915_WRITE(CURSIZE, (height << 12) | width);
6546 if (intel_crtc->cursor_bo) {
6547 if (dev_priv->info->cursor_needs_physical) {
6548 if (intel_crtc->cursor_bo != obj)
6549 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6551 i915_gem_object_unpin(intel_crtc->cursor_bo);
6552 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6555 mutex_unlock(&dev->struct_mutex);
6557 intel_crtc->cursor_addr = addr;
6558 intel_crtc->cursor_bo = obj;
6559 intel_crtc->cursor_width = width;
6560 intel_crtc->cursor_height = height;
6562 intel_crtc_update_cursor(crtc, true);
6566 i915_gem_object_unpin(obj);
6568 mutex_unlock(&dev->struct_mutex);
6570 drm_gem_object_unreference_unlocked(&obj->base);
6574 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6578 intel_crtc->cursor_x = x;
6579 intel_crtc->cursor_y = y;
6581 intel_crtc_update_cursor(crtc, true);
6586 /** Sets the color ramps on behalf of RandR */
6587 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6588 u16 blue, int regno)
6590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6592 intel_crtc->lut_r[regno] = red >> 8;
6593 intel_crtc->lut_g[regno] = green >> 8;
6594 intel_crtc->lut_b[regno] = blue >> 8;
6597 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6598 u16 *blue, int regno)
6600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6602 *red = intel_crtc->lut_r[regno] << 8;
6603 *green = intel_crtc->lut_g[regno] << 8;
6604 *blue = intel_crtc->lut_b[regno] << 8;
6607 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6608 u16 *blue, uint32_t start, uint32_t size)
6610 int end = (start + size > 256) ? 256 : start + size, i;
6611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6613 for (i = start; i < end; i++) {
6614 intel_crtc->lut_r[i] = red[i] >> 8;
6615 intel_crtc->lut_g[i] = green[i] >> 8;
6616 intel_crtc->lut_b[i] = blue[i] >> 8;
6619 intel_crtc_load_lut(crtc);
6623 * Get a pipe with a simple mode set on it for doing load-based monitor
6626 * It will be up to the load-detect code to adjust the pipe as appropriate for
6627 * its requirements. The pipe will be connected to no other encoders.
6629 * Currently this code will only succeed if there is a pipe with no encoders
6630 * configured for it. In the future, it could choose to temporarily disable
6631 * some outputs to free up a pipe for its use.
6633 * \return crtc, or NULL if no pipes are available.
6636 /* VESA 640x480x72Hz mode to set on the pipe */
6637 static struct drm_display_mode load_detect_mode = {
6638 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6639 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6642 static struct drm_framebuffer *
6643 intel_framebuffer_create(struct drm_device *dev,
6644 struct drm_mode_fb_cmd2 *mode_cmd,
6645 struct drm_i915_gem_object *obj)
6647 struct intel_framebuffer *intel_fb;
6650 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6652 drm_gem_object_unreference_unlocked(&obj->base);
6653 return ERR_PTR(-ENOMEM);
6656 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6658 drm_gem_object_unreference_unlocked(&obj->base);
6660 return ERR_PTR(ret);
6663 return &intel_fb->base;
6667 intel_framebuffer_pitch_for_width(int width, int bpp)
6669 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6670 return ALIGN(pitch, 64);
6674 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6676 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6677 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6680 static struct drm_framebuffer *
6681 intel_framebuffer_create_for_mode(struct drm_device *dev,
6682 struct drm_display_mode *mode,
6685 struct drm_i915_gem_object *obj;
6686 struct drm_mode_fb_cmd2 mode_cmd;
6688 obj = i915_gem_alloc_object(dev,
6689 intel_framebuffer_size_for_mode(mode, bpp));
6691 return ERR_PTR(-ENOMEM);
6693 mode_cmd.width = mode->hdisplay;
6694 mode_cmd.height = mode->vdisplay;
6695 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6697 mode_cmd.pixel_format = 0;
6699 return intel_framebuffer_create(dev, &mode_cmd, obj);
6702 static struct drm_framebuffer *
6703 mode_fits_in_fbdev(struct drm_device *dev,
6704 struct drm_display_mode *mode)
6706 struct drm_i915_private *dev_priv = dev->dev_private;
6707 struct drm_i915_gem_object *obj;
6708 struct drm_framebuffer *fb;
6710 if (dev_priv->fbdev == NULL)
6713 obj = dev_priv->fbdev->ifb.obj;
6717 fb = &dev_priv->fbdev->ifb.base;
6718 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6719 fb->bits_per_pixel))
6722 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6728 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6729 struct drm_connector *connector,
6730 struct drm_display_mode *mode,
6731 struct intel_load_detect_pipe *old)
6733 struct intel_crtc *intel_crtc;
6734 struct drm_crtc *possible_crtc;
6735 struct drm_encoder *encoder = &intel_encoder->base;
6736 struct drm_crtc *crtc = NULL;
6737 struct drm_device *dev = encoder->dev;
6738 struct drm_framebuffer *old_fb;
6741 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6742 connector->base.id, drm_get_connector_name(connector),
6743 encoder->base.id, drm_get_encoder_name(encoder));
6746 * Algorithm gets a little messy:
6748 * - if the connector already has an assigned crtc, use it (but make
6749 * sure it's on first)
6751 * - try to find the first unused crtc that can drive this connector,
6752 * and use that if we find one
6755 /* See if we already have a CRTC for this connector */
6756 if (encoder->crtc) {
6757 crtc = encoder->crtc;
6759 intel_crtc = to_intel_crtc(crtc);
6760 old->dpms_mode = intel_crtc->dpms_mode;
6761 old->load_detect_temp = false;
6763 /* Make sure the crtc and connector are running */
6764 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6765 struct drm_encoder_helper_funcs *encoder_funcs;
6766 struct drm_crtc_helper_funcs *crtc_funcs;
6768 crtc_funcs = crtc->helper_private;
6769 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6771 encoder_funcs = encoder->helper_private;
6772 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6778 /* Find an unused one (if possible) */
6779 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6781 if (!(encoder->possible_crtcs & (1 << i)))
6783 if (!possible_crtc->enabled) {
6784 crtc = possible_crtc;
6790 * If we didn't find an unused CRTC, don't use any.
6793 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6797 encoder->crtc = crtc;
6798 connector->encoder = encoder;
6800 intel_crtc = to_intel_crtc(crtc);
6801 old->dpms_mode = intel_crtc->dpms_mode;
6802 old->load_detect_temp = true;
6803 old->release_fb = NULL;
6806 mode = &load_detect_mode;
6810 /* We need a framebuffer large enough to accommodate all accesses
6811 * that the plane may generate whilst we perform load detection.
6812 * We can not rely on the fbcon either being present (we get called
6813 * during its initialisation to detect all boot displays, or it may
6814 * not even exist) or that it is large enough to satisfy the
6817 crtc->fb = mode_fits_in_fbdev(dev, mode);
6818 if (crtc->fb == NULL) {
6819 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6820 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6821 old->release_fb = crtc->fb;
6823 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6824 if (IS_ERR(crtc->fb)) {
6825 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6830 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6831 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6832 if (old->release_fb)
6833 old->release_fb->funcs->destroy(old->release_fb);
6838 /* let the connector get through one full cycle before testing */
6839 intel_wait_for_vblank(dev, intel_crtc->pipe);
6844 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6845 struct drm_connector *connector,
6846 struct intel_load_detect_pipe *old)
6848 struct drm_encoder *encoder = &intel_encoder->base;
6849 struct drm_device *dev = encoder->dev;
6850 struct drm_crtc *crtc = encoder->crtc;
6851 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6852 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6855 connector->base.id, drm_get_connector_name(connector),
6856 encoder->base.id, drm_get_encoder_name(encoder));
6858 if (old->load_detect_temp) {
6859 connector->encoder = NULL;
6860 drm_helper_disable_unused_functions(dev);
6862 if (old->release_fb)
6863 old->release_fb->funcs->destroy(old->release_fb);
6868 /* Switch crtc and encoder back off if necessary */
6869 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6870 encoder_funcs->dpms(encoder, old->dpms_mode);
6871 crtc_funcs->dpms(crtc, old->dpms_mode);
6875 /* Returns the clock of the currently programmed mode of the given pipe. */
6876 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6878 struct drm_i915_private *dev_priv = dev->dev_private;
6879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6880 int pipe = intel_crtc->pipe;
6881 u32 dpll = I915_READ(DPLL(pipe));
6883 intel_clock_t clock;
6885 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6886 fp = I915_READ(FP0(pipe));
6888 fp = I915_READ(FP1(pipe));
6890 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6891 if (IS_PINEVIEW(dev)) {
6892 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6893 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6895 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6896 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6899 if (!IS_GEN2(dev)) {
6900 if (IS_PINEVIEW(dev))
6901 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6902 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6904 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6905 DPLL_FPA01_P1_POST_DIV_SHIFT);
6907 switch (dpll & DPLL_MODE_MASK) {
6908 case DPLLB_MODE_DAC_SERIAL:
6909 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6912 case DPLLB_MODE_LVDS:
6913 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6917 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6918 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6922 /* XXX: Handle the 100Mhz refclk */
6923 intel_clock(dev, 96000, &clock);
6925 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6928 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6929 DPLL_FPA01_P1_POST_DIV_SHIFT);
6932 if ((dpll & PLL_REF_INPUT_MASK) ==
6933 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6934 /* XXX: might not be 66MHz */
6935 intel_clock(dev, 66000, &clock);
6937 intel_clock(dev, 48000, &clock);
6939 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6942 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6943 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6945 if (dpll & PLL_P2_DIVIDE_BY_4)
6950 intel_clock(dev, 48000, &clock);
6954 /* XXX: It would be nice to validate the clocks, but we can't reuse
6955 * i830PllIsValid() because it relies on the xf86_config connector
6956 * configuration being accurate, which it isn't necessarily.
6962 /** Returns the currently programmed mode of the given pipe. */
6963 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6964 struct drm_crtc *crtc)
6966 struct drm_i915_private *dev_priv = dev->dev_private;
6967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6968 int pipe = intel_crtc->pipe;
6969 struct drm_display_mode *mode;
6970 int htot = I915_READ(HTOTAL(pipe));
6971 int hsync = I915_READ(HSYNC(pipe));
6972 int vtot = I915_READ(VTOTAL(pipe));
6973 int vsync = I915_READ(VSYNC(pipe));
6975 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6979 mode->clock = intel_crtc_clock_get(dev, crtc);
6980 mode->hdisplay = (htot & 0xffff) + 1;
6981 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6982 mode->hsync_start = (hsync & 0xffff) + 1;
6983 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6984 mode->vdisplay = (vtot & 0xffff) + 1;
6985 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6986 mode->vsync_start = (vsync & 0xffff) + 1;
6987 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6989 drm_mode_set_name(mode);
6990 drm_mode_set_crtcinfo(mode, 0);
6995 #define GPU_IDLE_TIMEOUT 500 /* ms */
6997 /* When this timer fires, we've been idle for awhile */
6998 static void intel_gpu_idle_timer(unsigned long arg)
7000 struct drm_device *dev = (struct drm_device *)arg;
7001 drm_i915_private_t *dev_priv = dev->dev_private;
7003 if (!list_empty(&dev_priv->mm.active_list)) {
7004 /* Still processing requests, so just re-arm the timer. */
7005 mod_timer(&dev_priv->idle_timer, jiffies +
7006 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7010 dev_priv->busy = false;
7011 queue_work(dev_priv->wq, &dev_priv->idle_work);
7014 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
7016 static void intel_crtc_idle_timer(unsigned long arg)
7018 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
7019 struct drm_crtc *crtc = &intel_crtc->base;
7020 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
7021 struct intel_framebuffer *intel_fb;
7023 intel_fb = to_intel_framebuffer(crtc->fb);
7024 if (intel_fb && intel_fb->obj->active) {
7025 /* The framebuffer is still being accessed by the GPU. */
7026 mod_timer(&intel_crtc->idle_timer, jiffies +
7027 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7031 intel_crtc->busy = false;
7032 queue_work(dev_priv->wq, &dev_priv->idle_work);
7035 static void intel_increase_pllclock(struct drm_crtc *crtc)
7037 struct drm_device *dev = crtc->dev;
7038 drm_i915_private_t *dev_priv = dev->dev_private;
7039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7040 int pipe = intel_crtc->pipe;
7041 int dpll_reg = DPLL(pipe);
7044 if (HAS_PCH_SPLIT(dev))
7047 if (!dev_priv->lvds_downclock_avail)
7050 dpll = I915_READ(dpll_reg);
7051 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7052 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7054 assert_panel_unlocked(dev_priv, pipe);
7056 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7057 I915_WRITE(dpll_reg, dpll);
7058 intel_wait_for_vblank(dev, pipe);
7060 dpll = I915_READ(dpll_reg);
7061 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7062 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7065 /* Schedule downclock */
7066 mod_timer(&intel_crtc->idle_timer, jiffies +
7067 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7070 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7072 struct drm_device *dev = crtc->dev;
7073 drm_i915_private_t *dev_priv = dev->dev_private;
7074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7075 int pipe = intel_crtc->pipe;
7076 int dpll_reg = DPLL(pipe);
7077 int dpll = I915_READ(dpll_reg);
7079 if (HAS_PCH_SPLIT(dev))
7082 if (!dev_priv->lvds_downclock_avail)
7086 * Since this is called by a timer, we should never get here in
7089 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7090 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7092 assert_panel_unlocked(dev_priv, pipe);
7094 dpll |= DISPLAY_RATE_SELECT_FPA1;
7095 I915_WRITE(dpll_reg, dpll);
7096 intel_wait_for_vblank(dev, pipe);
7097 dpll = I915_READ(dpll_reg);
7098 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7099 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7105 * intel_idle_update - adjust clocks for idleness
7106 * @work: work struct
7108 * Either the GPU or display (or both) went idle. Check the busy status
7109 * here and adjust the CRTC and GPU clocks as necessary.
7111 static void intel_idle_update(struct work_struct *work)
7113 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7115 struct drm_device *dev = dev_priv->dev;
7116 struct drm_crtc *crtc;
7117 struct intel_crtc *intel_crtc;
7119 if (!i915_powersave)
7122 mutex_lock(&dev->struct_mutex);
7124 i915_update_gfx_val(dev_priv);
7126 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7127 /* Skip inactive CRTCs */
7131 intel_crtc = to_intel_crtc(crtc);
7132 if (!intel_crtc->busy)
7133 intel_decrease_pllclock(crtc);
7137 mutex_unlock(&dev->struct_mutex);
7141 * intel_mark_busy - mark the GPU and possibly the display busy
7143 * @obj: object we're operating on
7145 * Callers can use this function to indicate that the GPU is busy processing
7146 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7147 * buffer), we'll also mark the display as busy, so we know to increase its
7150 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7152 drm_i915_private_t *dev_priv = dev->dev_private;
7153 struct drm_crtc *crtc = NULL;
7154 struct intel_framebuffer *intel_fb;
7155 struct intel_crtc *intel_crtc;
7157 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7160 if (!dev_priv->busy)
7161 dev_priv->busy = true;
7163 mod_timer(&dev_priv->idle_timer, jiffies +
7164 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7166 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7170 intel_crtc = to_intel_crtc(crtc);
7171 intel_fb = to_intel_framebuffer(crtc->fb);
7172 if (intel_fb->obj == obj) {
7173 if (!intel_crtc->busy) {
7174 /* Non-busy -> busy, upclock */
7175 intel_increase_pllclock(crtc);
7176 intel_crtc->busy = true;
7178 /* Busy -> busy, put off timer */
7179 mod_timer(&intel_crtc->idle_timer, jiffies +
7180 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7186 static void intel_crtc_destroy(struct drm_crtc *crtc)
7188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7189 struct drm_device *dev = crtc->dev;
7190 struct intel_unpin_work *work;
7191 unsigned long flags;
7193 spin_lock_irqsave(&dev->event_lock, flags);
7194 work = intel_crtc->unpin_work;
7195 intel_crtc->unpin_work = NULL;
7196 spin_unlock_irqrestore(&dev->event_lock, flags);
7199 cancel_work_sync(&work->work);
7203 drm_crtc_cleanup(crtc);
7208 static void intel_unpin_work_fn(struct work_struct *__work)
7210 struct intel_unpin_work *work =
7211 container_of(__work, struct intel_unpin_work, work);
7213 mutex_lock(&work->dev->struct_mutex);
7214 intel_unpin_fb_obj(work->old_fb_obj);
7215 drm_gem_object_unreference(&work->pending_flip_obj->base);
7216 drm_gem_object_unreference(&work->old_fb_obj->base);
7218 intel_update_fbc(work->dev);
7219 mutex_unlock(&work->dev->struct_mutex);
7223 static void do_intel_finish_page_flip(struct drm_device *dev,
7224 struct drm_crtc *crtc)
7226 drm_i915_private_t *dev_priv = dev->dev_private;
7227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7228 struct intel_unpin_work *work;
7229 struct drm_i915_gem_object *obj;
7230 struct drm_pending_vblank_event *e;
7231 struct timeval tnow, tvbl;
7232 unsigned long flags;
7234 /* Ignore early vblank irqs */
7235 if (intel_crtc == NULL)
7238 do_gettimeofday(&tnow);
7240 spin_lock_irqsave(&dev->event_lock, flags);
7241 work = intel_crtc->unpin_work;
7242 if (work == NULL || !work->pending) {
7243 spin_unlock_irqrestore(&dev->event_lock, flags);
7247 intel_crtc->unpin_work = NULL;
7251 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7253 /* Called before vblank count and timestamps have
7254 * been updated for the vblank interval of flip
7255 * completion? Need to increment vblank count and
7256 * add one videorefresh duration to returned timestamp
7257 * to account for this. We assume this happened if we
7258 * get called over 0.9 frame durations after the last
7259 * timestamped vblank.
7261 * This calculation can not be used with vrefresh rates
7262 * below 5Hz (10Hz to be on the safe side) without
7263 * promoting to 64 integers.
7265 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7266 9 * crtc->framedur_ns) {
7267 e->event.sequence++;
7268 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7272 e->event.tv_sec = tvbl.tv_sec;
7273 e->event.tv_usec = tvbl.tv_usec;
7275 list_add_tail(&e->base.link,
7276 &e->base.file_priv->event_list);
7277 wake_up_interruptible(&e->base.file_priv->event_wait);
7280 drm_vblank_put(dev, intel_crtc->pipe);
7282 spin_unlock_irqrestore(&dev->event_lock, flags);
7284 obj = work->old_fb_obj;
7286 atomic_clear_mask(1 << intel_crtc->plane,
7287 &obj->pending_flip.counter);
7288 if (atomic_read(&obj->pending_flip) == 0)
7289 wake_up(&dev_priv->pending_flip_queue);
7291 schedule_work(&work->work);
7293 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7296 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7298 drm_i915_private_t *dev_priv = dev->dev_private;
7299 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7301 do_intel_finish_page_flip(dev, crtc);
7304 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7306 drm_i915_private_t *dev_priv = dev->dev_private;
7307 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7309 do_intel_finish_page_flip(dev, crtc);
7312 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7314 drm_i915_private_t *dev_priv = dev->dev_private;
7315 struct intel_crtc *intel_crtc =
7316 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7317 unsigned long flags;
7319 spin_lock_irqsave(&dev->event_lock, flags);
7320 if (intel_crtc->unpin_work) {
7321 if ((++intel_crtc->unpin_work->pending) > 1)
7322 DRM_ERROR("Prepared flip multiple times\n");
7324 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7326 spin_unlock_irqrestore(&dev->event_lock, flags);
7329 static int intel_gen2_queue_flip(struct drm_device *dev,
7330 struct drm_crtc *crtc,
7331 struct drm_framebuffer *fb,
7332 struct drm_i915_gem_object *obj)
7334 struct drm_i915_private *dev_priv = dev->dev_private;
7335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7336 unsigned long offset;
7340 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7344 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7345 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7347 ret = BEGIN_LP_RING(6);
7351 /* Can't queue multiple flips, so wait for the previous
7352 * one to finish before executing the next.
7354 if (intel_crtc->plane)
7355 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7357 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7358 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7360 OUT_RING(MI_DISPLAY_FLIP |
7361 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7362 OUT_RING(fb->pitches[0]);
7363 OUT_RING(obj->gtt_offset + offset);
7364 OUT_RING(0); /* aux display base address, unused */
7370 static int intel_gen3_queue_flip(struct drm_device *dev,
7371 struct drm_crtc *crtc,
7372 struct drm_framebuffer *fb,
7373 struct drm_i915_gem_object *obj)
7375 struct drm_i915_private *dev_priv = dev->dev_private;
7376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7377 unsigned long offset;
7381 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7385 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7386 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7388 ret = BEGIN_LP_RING(6);
7392 if (intel_crtc->plane)
7393 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7395 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7396 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7398 OUT_RING(MI_DISPLAY_FLIP_I915 |
7399 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7400 OUT_RING(fb->pitches[0]);
7401 OUT_RING(obj->gtt_offset + offset);
7409 static int intel_gen4_queue_flip(struct drm_device *dev,
7410 struct drm_crtc *crtc,
7411 struct drm_framebuffer *fb,
7412 struct drm_i915_gem_object *obj)
7414 struct drm_i915_private *dev_priv = dev->dev_private;
7415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7416 uint32_t pf, pipesrc;
7419 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7423 ret = BEGIN_LP_RING(4);
7427 /* i965+ uses the linear or tiled offsets from the
7428 * Display Registers (which do not change across a page-flip)
7429 * so we need only reprogram the base address.
7431 OUT_RING(MI_DISPLAY_FLIP |
7432 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7433 OUT_RING(fb->pitches[0]);
7434 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7436 /* XXX Enabling the panel-fitter across page-flip is so far
7437 * untested on non-native modes, so ignore it for now.
7438 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7441 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7442 OUT_RING(pf | pipesrc);
7448 static int intel_gen6_queue_flip(struct drm_device *dev,
7449 struct drm_crtc *crtc,
7450 struct drm_framebuffer *fb,
7451 struct drm_i915_gem_object *obj)
7453 struct drm_i915_private *dev_priv = dev->dev_private;
7454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7455 uint32_t pf, pipesrc;
7458 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7462 ret = BEGIN_LP_RING(4);
7466 OUT_RING(MI_DISPLAY_FLIP |
7467 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7468 OUT_RING(fb->pitches[0] | obj->tiling_mode);
7469 OUT_RING(obj->gtt_offset);
7471 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7472 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7473 OUT_RING(pf | pipesrc);
7480 * On gen7 we currently use the blit ring because (in early silicon at least)
7481 * the render ring doesn't give us interrpts for page flip completion, which
7482 * means clients will hang after the first flip is queued. Fortunately the
7483 * blit ring generates interrupts properly, so use it instead.
7485 static int intel_gen7_queue_flip(struct drm_device *dev,
7486 struct drm_crtc *crtc,
7487 struct drm_framebuffer *fb,
7488 struct drm_i915_gem_object *obj)
7490 struct drm_i915_private *dev_priv = dev->dev_private;
7491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7492 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7495 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7499 ret = intel_ring_begin(ring, 4);
7503 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7504 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7505 intel_ring_emit(ring, (obj->gtt_offset));
7506 intel_ring_emit(ring, (MI_NOOP));
7507 intel_ring_advance(ring);
7512 static int intel_default_queue_flip(struct drm_device *dev,
7513 struct drm_crtc *crtc,
7514 struct drm_framebuffer *fb,
7515 struct drm_i915_gem_object *obj)
7520 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7521 struct drm_framebuffer *fb,
7522 struct drm_pending_vblank_event *event)
7524 struct drm_device *dev = crtc->dev;
7525 struct drm_i915_private *dev_priv = dev->dev_private;
7526 struct intel_framebuffer *intel_fb;
7527 struct drm_i915_gem_object *obj;
7528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7529 struct intel_unpin_work *work;
7530 unsigned long flags;
7533 work = kzalloc(sizeof *work, GFP_KERNEL);
7537 work->event = event;
7538 work->dev = crtc->dev;
7539 intel_fb = to_intel_framebuffer(crtc->fb);
7540 work->old_fb_obj = intel_fb->obj;
7541 INIT_WORK(&work->work, intel_unpin_work_fn);
7543 ret = drm_vblank_get(dev, intel_crtc->pipe);
7547 /* We borrow the event spin lock for protecting unpin_work */
7548 spin_lock_irqsave(&dev->event_lock, flags);
7549 if (intel_crtc->unpin_work) {
7550 spin_unlock_irqrestore(&dev->event_lock, flags);
7552 drm_vblank_put(dev, intel_crtc->pipe);
7554 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7557 intel_crtc->unpin_work = work;
7558 spin_unlock_irqrestore(&dev->event_lock, flags);
7560 intel_fb = to_intel_framebuffer(fb);
7561 obj = intel_fb->obj;
7563 mutex_lock(&dev->struct_mutex);
7565 /* Reference the objects for the scheduled work. */
7566 drm_gem_object_reference(&work->old_fb_obj->base);
7567 drm_gem_object_reference(&obj->base);
7571 work->pending_flip_obj = obj;
7573 work->enable_stall_check = true;
7575 /* Block clients from rendering to the new back buffer until
7576 * the flip occurs and the object is no longer visible.
7578 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7580 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7582 goto cleanup_pending;
7584 intel_disable_fbc(dev);
7585 mutex_unlock(&dev->struct_mutex);
7587 trace_i915_flip_request(intel_crtc->plane, obj);
7592 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7593 drm_gem_object_unreference(&work->old_fb_obj->base);
7594 drm_gem_object_unreference(&obj->base);
7595 mutex_unlock(&dev->struct_mutex);
7597 spin_lock_irqsave(&dev->event_lock, flags);
7598 intel_crtc->unpin_work = NULL;
7599 spin_unlock_irqrestore(&dev->event_lock, flags);
7601 drm_vblank_put(dev, intel_crtc->pipe);
7608 static void intel_sanitize_modesetting(struct drm_device *dev,
7609 int pipe, int plane)
7611 struct drm_i915_private *dev_priv = dev->dev_private;
7614 if (HAS_PCH_SPLIT(dev))
7617 /* Who knows what state these registers were left in by the BIOS or
7620 * If we leave the registers in a conflicting state (e.g. with the
7621 * display plane reading from the other pipe than the one we intend
7622 * to use) then when we attempt to teardown the active mode, we will
7623 * not disable the pipes and planes in the correct order -- leaving
7624 * a plane reading from a disabled pipe and possibly leading to
7625 * undefined behaviour.
7628 reg = DSPCNTR(plane);
7629 val = I915_READ(reg);
7631 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7633 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7636 /* This display plane is active and attached to the other CPU pipe. */
7639 /* Disable the plane and wait for it to stop reading from the pipe. */
7640 intel_disable_plane(dev_priv, plane, pipe);
7641 intel_disable_pipe(dev_priv, pipe);
7644 static void intel_crtc_reset(struct drm_crtc *crtc)
7646 struct drm_device *dev = crtc->dev;
7647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7649 /* Reset flags back to the 'unknown' status so that they
7650 * will be correctly set on the initial modeset.
7652 intel_crtc->dpms_mode = -1;
7654 /* We need to fix up any BIOS configuration that conflicts with
7657 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7660 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7661 .dpms = intel_crtc_dpms,
7662 .mode_fixup = intel_crtc_mode_fixup,
7663 .mode_set = intel_crtc_mode_set,
7664 .mode_set_base = intel_pipe_set_base,
7665 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7666 .load_lut = intel_crtc_load_lut,
7667 .disable = intel_crtc_disable,
7670 static const struct drm_crtc_funcs intel_crtc_funcs = {
7671 .reset = intel_crtc_reset,
7672 .cursor_set = intel_crtc_cursor_set,
7673 .cursor_move = intel_crtc_cursor_move,
7674 .gamma_set = intel_crtc_gamma_set,
7675 .set_config = drm_crtc_helper_set_config,
7676 .destroy = intel_crtc_destroy,
7677 .page_flip = intel_crtc_page_flip,
7680 static void intel_crtc_init(struct drm_device *dev, int pipe)
7682 drm_i915_private_t *dev_priv = dev->dev_private;
7683 struct intel_crtc *intel_crtc;
7686 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7687 if (intel_crtc == NULL)
7690 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7692 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7693 for (i = 0; i < 256; i++) {
7694 intel_crtc->lut_r[i] = i;
7695 intel_crtc->lut_g[i] = i;
7696 intel_crtc->lut_b[i] = i;
7699 /* Swap pipes & planes for FBC on pre-965 */
7700 intel_crtc->pipe = pipe;
7701 intel_crtc->plane = pipe;
7702 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7703 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7704 intel_crtc->plane = !pipe;
7707 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7708 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7709 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7710 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7712 intel_crtc_reset(&intel_crtc->base);
7713 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7714 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7716 if (HAS_PCH_SPLIT(dev)) {
7717 if (pipe == 2 && IS_IVYBRIDGE(dev))
7718 intel_crtc->no_pll = true;
7719 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7720 intel_helper_funcs.commit = ironlake_crtc_commit;
7722 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7723 intel_helper_funcs.commit = i9xx_crtc_commit;
7726 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7728 intel_crtc->busy = false;
7730 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7731 (unsigned long)intel_crtc);
7734 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7735 struct drm_file *file)
7737 drm_i915_private_t *dev_priv = dev->dev_private;
7738 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7739 struct drm_mode_object *drmmode_obj;
7740 struct intel_crtc *crtc;
7743 DRM_ERROR("called with no initialization\n");
7747 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7748 DRM_MODE_OBJECT_CRTC);
7751 DRM_ERROR("no such CRTC id\n");
7755 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7756 pipe_from_crtc_id->pipe = crtc->pipe;
7761 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7763 struct intel_encoder *encoder;
7767 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7768 if (type_mask & encoder->clone_mask)
7769 index_mask |= (1 << entry);
7776 static bool has_edp_a(struct drm_device *dev)
7778 struct drm_i915_private *dev_priv = dev->dev_private;
7780 if (!IS_MOBILE(dev))
7783 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7787 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7793 static void intel_setup_outputs(struct drm_device *dev)
7795 struct drm_i915_private *dev_priv = dev->dev_private;
7796 struct intel_encoder *encoder;
7797 bool dpd_is_edp = false;
7800 has_lvds = intel_lvds_init(dev);
7801 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7802 /* disable the panel fitter on everything but LVDS */
7803 I915_WRITE(PFIT_CONTROL, 0);
7806 if (HAS_PCH_SPLIT(dev)) {
7807 dpd_is_edp = intel_dpd_is_edp(dev);
7810 intel_dp_init(dev, DP_A);
7812 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7813 intel_dp_init(dev, PCH_DP_D);
7816 intel_crt_init(dev);
7818 if (HAS_PCH_SPLIT(dev)) {
7821 if (I915_READ(HDMIB) & PORT_DETECTED) {
7822 /* PCH SDVOB multiplex with HDMIB */
7823 found = intel_sdvo_init(dev, PCH_SDVOB, true);
7825 intel_hdmi_init(dev, HDMIB);
7826 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7827 intel_dp_init(dev, PCH_DP_B);
7830 if (I915_READ(HDMIC) & PORT_DETECTED)
7831 intel_hdmi_init(dev, HDMIC);
7833 if (I915_READ(HDMID) & PORT_DETECTED)
7834 intel_hdmi_init(dev, HDMID);
7836 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7837 intel_dp_init(dev, PCH_DP_C);
7839 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7840 intel_dp_init(dev, PCH_DP_D);
7842 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7845 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7846 DRM_DEBUG_KMS("probing SDVOB\n");
7847 found = intel_sdvo_init(dev, SDVOB, true);
7848 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7849 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7850 intel_hdmi_init(dev, SDVOB);
7853 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7854 DRM_DEBUG_KMS("probing DP_B\n");
7855 intel_dp_init(dev, DP_B);
7859 /* Before G4X SDVOC doesn't have its own detect register */
7861 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7862 DRM_DEBUG_KMS("probing SDVOC\n");
7863 found = intel_sdvo_init(dev, SDVOC, false);
7866 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7868 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7869 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7870 intel_hdmi_init(dev, SDVOC);
7872 if (SUPPORTS_INTEGRATED_DP(dev)) {
7873 DRM_DEBUG_KMS("probing DP_C\n");
7874 intel_dp_init(dev, DP_C);
7878 if (SUPPORTS_INTEGRATED_DP(dev) &&
7879 (I915_READ(DP_D) & DP_DETECTED)) {
7880 DRM_DEBUG_KMS("probing DP_D\n");
7881 intel_dp_init(dev, DP_D);
7883 } else if (IS_GEN2(dev))
7884 intel_dvo_init(dev);
7886 if (SUPPORTS_TV(dev))
7889 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7890 encoder->base.possible_crtcs = encoder->crtc_mask;
7891 encoder->base.possible_clones =
7892 intel_encoder_clones(dev, encoder->clone_mask);
7895 /* disable all the possible outputs/crtcs before entering KMS mode */
7896 drm_helper_disable_unused_functions(dev);
7898 if (HAS_PCH_SPLIT(dev))
7899 ironlake_init_pch_refclk(dev);
7902 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7904 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7906 drm_framebuffer_cleanup(fb);
7907 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7912 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7913 struct drm_file *file,
7914 unsigned int *handle)
7916 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7917 struct drm_i915_gem_object *obj = intel_fb->obj;
7919 return drm_gem_handle_create(file, &obj->base, handle);
7922 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7923 .destroy = intel_user_framebuffer_destroy,
7924 .create_handle = intel_user_framebuffer_create_handle,
7927 int intel_framebuffer_init(struct drm_device *dev,
7928 struct intel_framebuffer *intel_fb,
7929 struct drm_mode_fb_cmd2 *mode_cmd,
7930 struct drm_i915_gem_object *obj)
7934 if (obj->tiling_mode == I915_TILING_Y)
7937 if (mode_cmd->pitches[0] & 63)
7940 switch (mode_cmd->pixel_format) {
7941 case DRM_FORMAT_RGB332:
7942 case DRM_FORMAT_RGB565:
7943 case DRM_FORMAT_XRGB8888:
7944 case DRM_FORMAT_ARGB8888:
7945 case DRM_FORMAT_XRGB2101010:
7946 case DRM_FORMAT_ARGB2101010:
7947 /* RGB formats are common across chipsets */
7949 case DRM_FORMAT_YUYV:
7950 case DRM_FORMAT_UYVY:
7951 case DRM_FORMAT_YVYU:
7952 case DRM_FORMAT_VYUY:
7955 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7956 mode_cmd->pixel_format);
7960 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7962 DRM_ERROR("framebuffer init failed %d\n", ret);
7966 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7967 intel_fb->obj = obj;
7971 static struct drm_framebuffer *
7972 intel_user_framebuffer_create(struct drm_device *dev,
7973 struct drm_file *filp,
7974 struct drm_mode_fb_cmd2 *mode_cmd)
7976 struct drm_i915_gem_object *obj;
7978 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7979 mode_cmd->handles[0]));
7980 if (&obj->base == NULL)
7981 return ERR_PTR(-ENOENT);
7983 return intel_framebuffer_create(dev, mode_cmd, obj);
7986 static const struct drm_mode_config_funcs intel_mode_funcs = {
7987 .fb_create = intel_user_framebuffer_create,
7988 .output_poll_changed = intel_fb_output_poll_changed,
7991 static struct drm_i915_gem_object *
7992 intel_alloc_context_page(struct drm_device *dev)
7994 struct drm_i915_gem_object *ctx;
7997 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7999 ctx = i915_gem_alloc_object(dev, 4096);
8001 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8005 ret = i915_gem_object_pin(ctx, 4096, true);
8007 DRM_ERROR("failed to pin power context: %d\n", ret);
8011 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
8013 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8020 i915_gem_object_unpin(ctx);
8022 drm_gem_object_unreference(&ctx->base);
8023 mutex_unlock(&dev->struct_mutex);
8027 bool ironlake_set_drps(struct drm_device *dev, u8 val)
8029 struct drm_i915_private *dev_priv = dev->dev_private;
8032 rgvswctl = I915_READ16(MEMSWCTL);
8033 if (rgvswctl & MEMCTL_CMD_STS) {
8034 DRM_DEBUG("gpu busy, RCS change rejected\n");
8035 return false; /* still busy with another command */
8038 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8039 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8040 I915_WRITE16(MEMSWCTL, rgvswctl);
8041 POSTING_READ16(MEMSWCTL);
8043 rgvswctl |= MEMCTL_CMD_STS;
8044 I915_WRITE16(MEMSWCTL, rgvswctl);
8049 void ironlake_enable_drps(struct drm_device *dev)
8051 struct drm_i915_private *dev_priv = dev->dev_private;
8052 u32 rgvmodectl = I915_READ(MEMMODECTL);
8053 u8 fmax, fmin, fstart, vstart;
8055 /* Enable temp reporting */
8056 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8057 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8059 /* 100ms RC evaluation intervals */
8060 I915_WRITE(RCUPEI, 100000);
8061 I915_WRITE(RCDNEI, 100000);
8063 /* Set max/min thresholds to 90ms and 80ms respectively */
8064 I915_WRITE(RCBMAXAVG, 90000);
8065 I915_WRITE(RCBMINAVG, 80000);
8067 I915_WRITE(MEMIHYST, 1);
8069 /* Set up min, max, and cur for interrupt handling */
8070 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8071 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8072 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8073 MEMMODE_FSTART_SHIFT;
8075 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8078 dev_priv->fmax = fmax; /* IPS callback will increase this */
8079 dev_priv->fstart = fstart;
8081 dev_priv->max_delay = fstart;
8082 dev_priv->min_delay = fmin;
8083 dev_priv->cur_delay = fstart;
8085 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8086 fmax, fmin, fstart);
8088 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8091 * Interrupts will be enabled in ironlake_irq_postinstall
8094 I915_WRITE(VIDSTART, vstart);
8095 POSTING_READ(VIDSTART);
8097 rgvmodectl |= MEMMODE_SWMODE_EN;
8098 I915_WRITE(MEMMODECTL, rgvmodectl);
8100 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8101 DRM_ERROR("stuck trying to change perf mode\n");
8104 ironlake_set_drps(dev, fstart);
8106 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8108 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8109 dev_priv->last_count2 = I915_READ(0x112f4);
8110 getrawmonotonic(&dev_priv->last_time2);
8113 void ironlake_disable_drps(struct drm_device *dev)
8115 struct drm_i915_private *dev_priv = dev->dev_private;
8116 u16 rgvswctl = I915_READ16(MEMSWCTL);
8118 /* Ack interrupts, disable EFC interrupt */
8119 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8120 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8121 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8122 I915_WRITE(DEIIR, DE_PCU_EVENT);
8123 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8125 /* Go back to the starting frequency */
8126 ironlake_set_drps(dev, dev_priv->fstart);
8128 rgvswctl |= MEMCTL_CMD_STS;
8129 I915_WRITE(MEMSWCTL, rgvswctl);
8134 void gen6_set_rps(struct drm_device *dev, u8 val)
8136 struct drm_i915_private *dev_priv = dev->dev_private;
8139 swreq = (val & 0x3ff) << 25;
8140 I915_WRITE(GEN6_RPNSWREQ, swreq);
8143 void gen6_disable_rps(struct drm_device *dev)
8145 struct drm_i915_private *dev_priv = dev->dev_private;
8147 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8148 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8149 I915_WRITE(GEN6_PMIER, 0);
8150 /* Complete PM interrupt masking here doesn't race with the rps work
8151 * item again unmasking PM interrupts because that is using a different
8152 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8153 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8155 spin_lock_irq(&dev_priv->rps_lock);
8156 dev_priv->pm_iir = 0;
8157 spin_unlock_irq(&dev_priv->rps_lock);
8159 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8162 static unsigned long intel_pxfreq(u32 vidfreq)
8165 int div = (vidfreq & 0x3f0000) >> 16;
8166 int post = (vidfreq & 0x3000) >> 12;
8167 int pre = (vidfreq & 0x7);
8172 freq = ((div * 133333) / ((1<<post) * pre));
8177 void intel_init_emon(struct drm_device *dev)
8179 struct drm_i915_private *dev_priv = dev->dev_private;
8184 /* Disable to program */
8188 /* Program energy weights for various events */
8189 I915_WRITE(SDEW, 0x15040d00);
8190 I915_WRITE(CSIEW0, 0x007f0000);
8191 I915_WRITE(CSIEW1, 0x1e220004);
8192 I915_WRITE(CSIEW2, 0x04000004);
8194 for (i = 0; i < 5; i++)
8195 I915_WRITE(PEW + (i * 4), 0);
8196 for (i = 0; i < 3; i++)
8197 I915_WRITE(DEW + (i * 4), 0);
8199 /* Program P-state weights to account for frequency power adjustment */
8200 for (i = 0; i < 16; i++) {
8201 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8202 unsigned long freq = intel_pxfreq(pxvidfreq);
8203 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8208 val *= (freq / 1000);
8210 val /= (127*127*900);
8212 DRM_ERROR("bad pxval: %ld\n", val);
8215 /* Render standby states get 0 weight */
8219 for (i = 0; i < 4; i++) {
8220 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8221 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8222 I915_WRITE(PXW + (i * 4), val);
8225 /* Adjust magic regs to magic values (more experimental results) */
8226 I915_WRITE(OGW0, 0);
8227 I915_WRITE(OGW1, 0);
8228 I915_WRITE(EG0, 0x00007f00);
8229 I915_WRITE(EG1, 0x0000000e);
8230 I915_WRITE(EG2, 0x000e0000);
8231 I915_WRITE(EG3, 0x68000300);
8232 I915_WRITE(EG4, 0x42000000);
8233 I915_WRITE(EG5, 0x00140031);
8237 for (i = 0; i < 8; i++)
8238 I915_WRITE(PXWL + (i * 4), 0);
8240 /* Enable PMON + select events */
8241 I915_WRITE(ECR, 0x80000019);
8243 lcfuse = I915_READ(LCFUSE02);
8245 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8248 static bool intel_enable_rc6(struct drm_device *dev)
8251 * Respect the kernel parameter if it is set
8253 if (i915_enable_rc6 >= 0)
8254 return i915_enable_rc6;
8257 * Disable RC6 on Ironlake
8259 if (INTEL_INFO(dev)->gen == 5)
8263 * Disable rc6 on Sandybridge
8265 if (INTEL_INFO(dev)->gen == 6) {
8266 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8269 DRM_DEBUG_DRIVER("RC6 enabled\n");
8273 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8275 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8276 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8277 u32 pcu_mbox, rc6_mask = 0;
8279 int cur_freq, min_freq, max_freq;
8282 /* Here begins a magic sequence of register writes to enable
8283 * auto-downclocking.
8285 * Perhaps there might be some value in exposing these to
8288 I915_WRITE(GEN6_RC_STATE, 0);
8289 mutex_lock(&dev_priv->dev->struct_mutex);
8291 /* Clear the DBG now so we don't confuse earlier errors */
8292 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8293 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8294 I915_WRITE(GTFIFODBG, gtfifodbg);
8297 gen6_gt_force_wake_get(dev_priv);
8299 /* disable the counters and set deterministic thresholds */
8300 I915_WRITE(GEN6_RC_CONTROL, 0);
8302 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8303 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8304 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8305 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8306 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8308 for (i = 0; i < I915_NUM_RINGS; i++)
8309 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8311 I915_WRITE(GEN6_RC_SLEEP, 0);
8312 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8313 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8314 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8315 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8317 if (intel_enable_rc6(dev_priv->dev))
8318 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8319 GEN6_RC_CTL_RC6_ENABLE;
8321 I915_WRITE(GEN6_RC_CONTROL,
8323 GEN6_RC_CTL_EI_MODE(1) |
8324 GEN6_RC_CTL_HW_ENABLE);
8326 I915_WRITE(GEN6_RPNSWREQ,
8327 GEN6_FREQUENCY(10) |
8329 GEN6_AGGRESSIVE_TURBO);
8330 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8331 GEN6_FREQUENCY(12));
8333 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8334 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8337 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8338 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8339 I915_WRITE(GEN6_RP_UP_EI, 100000);
8340 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8341 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8342 I915_WRITE(GEN6_RP_CONTROL,
8343 GEN6_RP_MEDIA_TURBO |
8344 GEN6_RP_MEDIA_HW_MODE |
8345 GEN6_RP_MEDIA_IS_GFX |
8347 GEN6_RP_UP_BUSY_AVG |
8348 GEN6_RP_DOWN_IDLE_CONT);
8350 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8352 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8354 I915_WRITE(GEN6_PCODE_DATA, 0);
8355 I915_WRITE(GEN6_PCODE_MAILBOX,
8357 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8358 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8360 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8362 min_freq = (rp_state_cap & 0xff0000) >> 16;
8363 max_freq = rp_state_cap & 0xff;
8364 cur_freq = (gt_perf_status & 0xff00) >> 8;
8366 /* Check for overclock support */
8367 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8369 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8370 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8371 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8372 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8374 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8375 if (pcu_mbox & (1<<31)) { /* OC supported */
8376 max_freq = pcu_mbox & 0xff;
8377 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8380 /* In units of 100MHz */
8381 dev_priv->max_delay = max_freq;
8382 dev_priv->min_delay = min_freq;
8383 dev_priv->cur_delay = cur_freq;
8385 /* requires MSI enabled */
8386 I915_WRITE(GEN6_PMIER,
8387 GEN6_PM_MBOX_EVENT |
8388 GEN6_PM_THERMAL_EVENT |
8389 GEN6_PM_RP_DOWN_TIMEOUT |
8390 GEN6_PM_RP_UP_THRESHOLD |
8391 GEN6_PM_RP_DOWN_THRESHOLD |
8392 GEN6_PM_RP_UP_EI_EXPIRED |
8393 GEN6_PM_RP_DOWN_EI_EXPIRED);
8394 spin_lock_irq(&dev_priv->rps_lock);
8395 WARN_ON(dev_priv->pm_iir != 0);
8396 I915_WRITE(GEN6_PMIMR, 0);
8397 spin_unlock_irq(&dev_priv->rps_lock);
8398 /* enable all PM interrupts */
8399 I915_WRITE(GEN6_PMINTRMSK, 0);
8401 gen6_gt_force_wake_put(dev_priv);
8402 mutex_unlock(&dev_priv->dev->struct_mutex);
8405 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8408 int gpu_freq, ia_freq, max_ia_freq;
8409 int scaling_factor = 180;
8411 max_ia_freq = cpufreq_quick_get_max(0);
8413 * Default to measured freq if none found, PCU will ensure we don't go
8417 max_ia_freq = tsc_khz;
8419 /* Convert from kHz to MHz */
8420 max_ia_freq /= 1000;
8422 mutex_lock(&dev_priv->dev->struct_mutex);
8425 * For each potential GPU frequency, load a ring frequency we'd like
8426 * to use for memory access. We do this by specifying the IA frequency
8427 * the PCU should use as a reference to determine the ring frequency.
8429 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8431 int diff = dev_priv->max_delay - gpu_freq;
8434 * For GPU frequencies less than 750MHz, just use the lowest
8437 if (gpu_freq < min_freq)
8440 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8441 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8443 I915_WRITE(GEN6_PCODE_DATA,
8444 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8446 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8447 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8448 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8449 GEN6_PCODE_READY) == 0, 10)) {
8450 DRM_ERROR("pcode write of freq table timed out\n");
8455 mutex_unlock(&dev_priv->dev->struct_mutex);
8458 static void ironlake_init_clock_gating(struct drm_device *dev)
8460 struct drm_i915_private *dev_priv = dev->dev_private;
8461 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8463 /* Required for FBC */
8464 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8465 DPFCRUNIT_CLOCK_GATE_DISABLE |
8466 DPFDUNIT_CLOCK_GATE_DISABLE;
8467 /* Required for CxSR */
8468 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8470 I915_WRITE(PCH_3DCGDIS0,
8471 MARIUNIT_CLOCK_GATE_DISABLE |
8472 SVSMUNIT_CLOCK_GATE_DISABLE);
8473 I915_WRITE(PCH_3DCGDIS1,
8474 VFMUNIT_CLOCK_GATE_DISABLE);
8476 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8479 * According to the spec the following bits should be set in
8480 * order to enable memory self-refresh
8481 * The bit 22/21 of 0x42004
8482 * The bit 5 of 0x42020
8483 * The bit 15 of 0x45000
8485 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8486 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8487 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8488 I915_WRITE(ILK_DSPCLK_GATE,
8489 (I915_READ(ILK_DSPCLK_GATE) |
8490 ILK_DPARB_CLK_GATE));
8491 I915_WRITE(DISP_ARB_CTL,
8492 (I915_READ(DISP_ARB_CTL) |
8494 I915_WRITE(WM3_LP_ILK, 0);
8495 I915_WRITE(WM2_LP_ILK, 0);
8496 I915_WRITE(WM1_LP_ILK, 0);
8499 * Based on the document from hardware guys the following bits
8500 * should be set unconditionally in order to enable FBC.
8501 * The bit 22 of 0x42000
8502 * The bit 22 of 0x42004
8503 * The bit 7,8,9 of 0x42020.
8505 if (IS_IRONLAKE_M(dev)) {
8506 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8507 I915_READ(ILK_DISPLAY_CHICKEN1) |
8509 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8510 I915_READ(ILK_DISPLAY_CHICKEN2) |
8512 I915_WRITE(ILK_DSPCLK_GATE,
8513 I915_READ(ILK_DSPCLK_GATE) |
8519 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8520 I915_READ(ILK_DISPLAY_CHICKEN2) |
8521 ILK_ELPIN_409_SELECT);
8522 I915_WRITE(_3D_CHICKEN2,
8523 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8524 _3D_CHICKEN2_WM_READ_PIPELINED);
8527 static void gen6_init_clock_gating(struct drm_device *dev)
8529 struct drm_i915_private *dev_priv = dev->dev_private;
8531 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8533 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8535 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8536 I915_READ(ILK_DISPLAY_CHICKEN2) |
8537 ILK_ELPIN_409_SELECT);
8539 I915_WRITE(WM3_LP_ILK, 0);
8540 I915_WRITE(WM2_LP_ILK, 0);
8541 I915_WRITE(WM1_LP_ILK, 0);
8543 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8544 * gating disable must be set. Failure to set it results in
8545 * flickering pixels due to Z write ordering failures after
8546 * some amount of runtime in the Mesa "fire" demo, and Unigine
8547 * Sanctuary and Tropics, and apparently anything else with
8548 * alpha test or pixel discard.
8550 * According to the spec, bit 11 (RCCUNIT) must also be set,
8551 * but we didn't debug actual testcases to find it out.
8553 I915_WRITE(GEN6_UCGCTL2,
8554 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8555 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8558 * According to the spec the following bits should be
8559 * set in order to enable memory self-refresh and fbc:
8560 * The bit21 and bit22 of 0x42000
8561 * The bit21 and bit22 of 0x42004
8562 * The bit5 and bit7 of 0x42020
8563 * The bit14 of 0x70180
8564 * The bit14 of 0x71180
8566 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8567 I915_READ(ILK_DISPLAY_CHICKEN1) |
8568 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8569 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8570 I915_READ(ILK_DISPLAY_CHICKEN2) |
8571 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8572 I915_WRITE(ILK_DSPCLK_GATE,
8573 I915_READ(ILK_DSPCLK_GATE) |
8574 ILK_DPARB_CLK_GATE |
8577 for_each_pipe(pipe) {
8578 I915_WRITE(DSPCNTR(pipe),
8579 I915_READ(DSPCNTR(pipe)) |
8580 DISPPLANE_TRICKLE_FEED_DISABLE);
8581 intel_flush_display_plane(dev_priv, pipe);
8585 static void ivybridge_init_clock_gating(struct drm_device *dev)
8587 struct drm_i915_private *dev_priv = dev->dev_private;
8589 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8591 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8593 I915_WRITE(WM3_LP_ILK, 0);
8594 I915_WRITE(WM2_LP_ILK, 0);
8595 I915_WRITE(WM1_LP_ILK, 0);
8597 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8599 I915_WRITE(IVB_CHICKEN3,
8600 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8601 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8603 for_each_pipe(pipe) {
8604 I915_WRITE(DSPCNTR(pipe),
8605 I915_READ(DSPCNTR(pipe)) |
8606 DISPPLANE_TRICKLE_FEED_DISABLE);
8607 intel_flush_display_plane(dev_priv, pipe);
8611 static void g4x_init_clock_gating(struct drm_device *dev)
8613 struct drm_i915_private *dev_priv = dev->dev_private;
8614 uint32_t dspclk_gate;
8616 I915_WRITE(RENCLK_GATE_D1, 0);
8617 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8618 GS_UNIT_CLOCK_GATE_DISABLE |
8619 CL_UNIT_CLOCK_GATE_DISABLE);
8620 I915_WRITE(RAMCLK_GATE_D, 0);
8621 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8622 OVRUNIT_CLOCK_GATE_DISABLE |
8623 OVCUNIT_CLOCK_GATE_DISABLE;
8625 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8626 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8629 static void crestline_init_clock_gating(struct drm_device *dev)
8631 struct drm_i915_private *dev_priv = dev->dev_private;
8633 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8634 I915_WRITE(RENCLK_GATE_D2, 0);
8635 I915_WRITE(DSPCLK_GATE_D, 0);
8636 I915_WRITE(RAMCLK_GATE_D, 0);
8637 I915_WRITE16(DEUC, 0);
8640 static void broadwater_init_clock_gating(struct drm_device *dev)
8642 struct drm_i915_private *dev_priv = dev->dev_private;
8644 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8645 I965_RCC_CLOCK_GATE_DISABLE |
8646 I965_RCPB_CLOCK_GATE_DISABLE |
8647 I965_ISC_CLOCK_GATE_DISABLE |
8648 I965_FBC_CLOCK_GATE_DISABLE);
8649 I915_WRITE(RENCLK_GATE_D2, 0);
8652 static void gen3_init_clock_gating(struct drm_device *dev)
8654 struct drm_i915_private *dev_priv = dev->dev_private;
8655 u32 dstate = I915_READ(D_STATE);
8657 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8658 DSTATE_DOT_CLOCK_GATING;
8659 I915_WRITE(D_STATE, dstate);
8662 static void i85x_init_clock_gating(struct drm_device *dev)
8664 struct drm_i915_private *dev_priv = dev->dev_private;
8666 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8669 static void i830_init_clock_gating(struct drm_device *dev)
8671 struct drm_i915_private *dev_priv = dev->dev_private;
8673 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8676 static void ibx_init_clock_gating(struct drm_device *dev)
8678 struct drm_i915_private *dev_priv = dev->dev_private;
8681 * On Ibex Peak and Cougar Point, we need to disable clock
8682 * gating for the panel power sequencer or it will fail to
8683 * start up when no ports are active.
8685 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8688 static void cpt_init_clock_gating(struct drm_device *dev)
8690 struct drm_i915_private *dev_priv = dev->dev_private;
8694 * On Ibex Peak and Cougar Point, we need to disable clock
8695 * gating for the panel power sequencer or it will fail to
8696 * start up when no ports are active.
8698 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8699 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8700 DPLS_EDP_PPS_FIX_DIS);
8701 /* Without this, mode sets may fail silently on FDI */
8703 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8706 static void ironlake_teardown_rc6(struct drm_device *dev)
8708 struct drm_i915_private *dev_priv = dev->dev_private;
8710 if (dev_priv->renderctx) {
8711 i915_gem_object_unpin(dev_priv->renderctx);
8712 drm_gem_object_unreference(&dev_priv->renderctx->base);
8713 dev_priv->renderctx = NULL;
8716 if (dev_priv->pwrctx) {
8717 i915_gem_object_unpin(dev_priv->pwrctx);
8718 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8719 dev_priv->pwrctx = NULL;
8723 static void ironlake_disable_rc6(struct drm_device *dev)
8725 struct drm_i915_private *dev_priv = dev->dev_private;
8727 if (I915_READ(PWRCTXA)) {
8728 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8729 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8730 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8733 I915_WRITE(PWRCTXA, 0);
8734 POSTING_READ(PWRCTXA);
8736 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8737 POSTING_READ(RSTDBYCTL);
8740 ironlake_teardown_rc6(dev);
8743 static int ironlake_setup_rc6(struct drm_device *dev)
8745 struct drm_i915_private *dev_priv = dev->dev_private;
8747 if (dev_priv->renderctx == NULL)
8748 dev_priv->renderctx = intel_alloc_context_page(dev);
8749 if (!dev_priv->renderctx)
8752 if (dev_priv->pwrctx == NULL)
8753 dev_priv->pwrctx = intel_alloc_context_page(dev);
8754 if (!dev_priv->pwrctx) {
8755 ironlake_teardown_rc6(dev);
8762 void ironlake_enable_rc6(struct drm_device *dev)
8764 struct drm_i915_private *dev_priv = dev->dev_private;
8767 /* rc6 disabled by default due to repeated reports of hanging during
8770 if (!intel_enable_rc6(dev))
8773 mutex_lock(&dev->struct_mutex);
8774 ret = ironlake_setup_rc6(dev);
8776 mutex_unlock(&dev->struct_mutex);
8781 * GPU can automatically power down the render unit if given a page
8784 ret = BEGIN_LP_RING(6);
8786 ironlake_teardown_rc6(dev);
8787 mutex_unlock(&dev->struct_mutex);
8791 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8792 OUT_RING(MI_SET_CONTEXT);
8793 OUT_RING(dev_priv->renderctx->gtt_offset |
8795 MI_SAVE_EXT_STATE_EN |
8796 MI_RESTORE_EXT_STATE_EN |
8797 MI_RESTORE_INHIBIT);
8798 OUT_RING(MI_SUSPEND_FLUSH);
8804 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8805 * does an implicit flush, combined with MI_FLUSH above, it should be
8806 * safe to assume that renderctx is valid
8808 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8810 DRM_ERROR("failed to enable ironlake power power savings\n");
8811 ironlake_teardown_rc6(dev);
8812 mutex_unlock(&dev->struct_mutex);
8816 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8817 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8818 mutex_unlock(&dev->struct_mutex);
8821 void intel_init_clock_gating(struct drm_device *dev)
8823 struct drm_i915_private *dev_priv = dev->dev_private;
8825 dev_priv->display.init_clock_gating(dev);
8827 if (dev_priv->display.init_pch_clock_gating)
8828 dev_priv->display.init_pch_clock_gating(dev);
8831 /* Set up chip specific display functions */
8832 static void intel_init_display(struct drm_device *dev)
8834 struct drm_i915_private *dev_priv = dev->dev_private;
8836 /* We always want a DPMS function */
8837 if (HAS_PCH_SPLIT(dev)) {
8838 dev_priv->display.dpms = ironlake_crtc_dpms;
8839 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8840 dev_priv->display.update_plane = ironlake_update_plane;
8842 dev_priv->display.dpms = i9xx_crtc_dpms;
8843 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8844 dev_priv->display.update_plane = i9xx_update_plane;
8847 if (I915_HAS_FBC(dev)) {
8848 if (HAS_PCH_SPLIT(dev)) {
8849 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8850 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8851 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8852 } else if (IS_GM45(dev)) {
8853 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8854 dev_priv->display.enable_fbc = g4x_enable_fbc;
8855 dev_priv->display.disable_fbc = g4x_disable_fbc;
8856 } else if (IS_CRESTLINE(dev)) {
8857 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8858 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8859 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8861 /* 855GM needs testing */
8864 /* Returns the core display clock speed */
8865 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8866 dev_priv->display.get_display_clock_speed =
8867 i945_get_display_clock_speed;
8868 else if (IS_I915G(dev))
8869 dev_priv->display.get_display_clock_speed =
8870 i915_get_display_clock_speed;
8871 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8872 dev_priv->display.get_display_clock_speed =
8873 i9xx_misc_get_display_clock_speed;
8874 else if (IS_I915GM(dev))
8875 dev_priv->display.get_display_clock_speed =
8876 i915gm_get_display_clock_speed;
8877 else if (IS_I865G(dev))
8878 dev_priv->display.get_display_clock_speed =
8879 i865_get_display_clock_speed;
8880 else if (IS_I85X(dev))
8881 dev_priv->display.get_display_clock_speed =
8882 i855_get_display_clock_speed;
8884 dev_priv->display.get_display_clock_speed =
8885 i830_get_display_clock_speed;
8887 /* For FIFO watermark updates */
8888 if (HAS_PCH_SPLIT(dev)) {
8889 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8890 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8892 /* IVB configs may use multi-threaded forcewake */
8893 if (IS_IVYBRIDGE(dev)) {
8896 /* A small trick here - if the bios hasn't configured MT forcewake,
8897 * and if the device is in RC6, then force_wake_mt_get will not wake
8898 * the device and the ECOBUS read will return zero. Which will be
8899 * (correctly) interpreted by the test below as MT forcewake being
8902 mutex_lock(&dev->struct_mutex);
8903 __gen6_gt_force_wake_mt_get(dev_priv);
8904 ecobus = I915_READ_NOTRACE(ECOBUS);
8905 __gen6_gt_force_wake_mt_put(dev_priv);
8906 mutex_unlock(&dev->struct_mutex);
8908 if (ecobus & FORCEWAKE_MT_ENABLE) {
8909 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8910 dev_priv->display.force_wake_get =
8911 __gen6_gt_force_wake_mt_get;
8912 dev_priv->display.force_wake_put =
8913 __gen6_gt_force_wake_mt_put;
8917 if (HAS_PCH_IBX(dev))
8918 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8919 else if (HAS_PCH_CPT(dev))
8920 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8923 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8924 dev_priv->display.update_wm = ironlake_update_wm;
8926 DRM_DEBUG_KMS("Failed to get proper latency. "
8928 dev_priv->display.update_wm = NULL;
8930 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8931 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8932 dev_priv->display.write_eld = ironlake_write_eld;
8933 } else if (IS_GEN6(dev)) {
8934 if (SNB_READ_WM0_LATENCY()) {
8935 dev_priv->display.update_wm = sandybridge_update_wm;
8936 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8938 DRM_DEBUG_KMS("Failed to read display plane latency. "
8940 dev_priv->display.update_wm = NULL;
8942 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8943 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8944 dev_priv->display.write_eld = ironlake_write_eld;
8945 } else if (IS_IVYBRIDGE(dev)) {
8946 /* FIXME: detect B0+ stepping and use auto training */
8947 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8948 if (SNB_READ_WM0_LATENCY()) {
8949 dev_priv->display.update_wm = sandybridge_update_wm;
8950 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8952 DRM_DEBUG_KMS("Failed to read display plane latency. "
8954 dev_priv->display.update_wm = NULL;
8956 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8957 dev_priv->display.write_eld = ironlake_write_eld;
8959 dev_priv->display.update_wm = NULL;
8960 } else if (IS_PINEVIEW(dev)) {
8961 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8964 dev_priv->mem_freq)) {
8965 DRM_INFO("failed to find known CxSR latency "
8966 "(found ddr%s fsb freq %d, mem freq %d), "
8968 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8969 dev_priv->fsb_freq, dev_priv->mem_freq);
8970 /* Disable CxSR and never update its watermark again */
8971 pineview_disable_cxsr(dev);
8972 dev_priv->display.update_wm = NULL;
8974 dev_priv->display.update_wm = pineview_update_wm;
8975 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8976 } else if (IS_G4X(dev)) {
8977 dev_priv->display.write_eld = g4x_write_eld;
8978 dev_priv->display.update_wm = g4x_update_wm;
8979 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8980 } else if (IS_GEN4(dev)) {
8981 dev_priv->display.update_wm = i965_update_wm;
8982 if (IS_CRESTLINE(dev))
8983 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8984 else if (IS_BROADWATER(dev))
8985 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8986 } else if (IS_GEN3(dev)) {
8987 dev_priv->display.update_wm = i9xx_update_wm;
8988 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8989 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8990 } else if (IS_I865G(dev)) {
8991 dev_priv->display.update_wm = i830_update_wm;
8992 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8993 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8994 } else if (IS_I85X(dev)) {
8995 dev_priv->display.update_wm = i9xx_update_wm;
8996 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8997 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8999 dev_priv->display.update_wm = i830_update_wm;
9000 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9002 dev_priv->display.get_fifo_size = i845_get_fifo_size;
9004 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9007 /* Default just returns -ENODEV to indicate unsupported */
9008 dev_priv->display.queue_flip = intel_default_queue_flip;
9010 switch (INTEL_INFO(dev)->gen) {
9012 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9016 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9021 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9025 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9028 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9034 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9035 * resume, or other times. This quirk makes sure that's the case for
9038 static void quirk_pipea_force(struct drm_device *dev)
9040 struct drm_i915_private *dev_priv = dev->dev_private;
9042 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9043 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9047 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9049 static void quirk_ssc_force_disable(struct drm_device *dev)
9051 struct drm_i915_private *dev_priv = dev->dev_private;
9052 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9056 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9059 static void quirk_invert_brightness(struct drm_device *dev)
9061 struct drm_i915_private *dev_priv = dev->dev_private;
9062 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9065 struct intel_quirk {
9067 int subsystem_vendor;
9068 int subsystem_device;
9069 void (*hook)(struct drm_device *dev);
9072 struct intel_quirk intel_quirks[] = {
9073 /* HP Mini needs pipe A force quirk (LP: #322104) */
9074 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9076 /* Thinkpad R31 needs pipe A force quirk */
9077 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9078 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9079 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9081 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9082 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9083 /* ThinkPad X40 needs pipe A force quirk */
9085 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9086 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9088 /* 855 & before need to leave pipe A & dpll A up */
9089 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9090 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9092 /* Lenovo U160 cannot use SSC on LVDS */
9093 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9095 /* Sony Vaio Y cannot use SSC on LVDS */
9096 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9098 /* Acer Aspire 5734Z must invert backlight brightness */
9099 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9102 static void intel_init_quirks(struct drm_device *dev)
9104 struct pci_dev *d = dev->pdev;
9107 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9108 struct intel_quirk *q = &intel_quirks[i];
9110 if (d->device == q->device &&
9111 (d->subsystem_vendor == q->subsystem_vendor ||
9112 q->subsystem_vendor == PCI_ANY_ID) &&
9113 (d->subsystem_device == q->subsystem_device ||
9114 q->subsystem_device == PCI_ANY_ID))
9119 /* Disable the VGA plane that we never use */
9120 static void i915_disable_vga(struct drm_device *dev)
9122 struct drm_i915_private *dev_priv = dev->dev_private;
9126 if (HAS_PCH_SPLIT(dev))
9127 vga_reg = CPU_VGACNTRL;
9131 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9132 outb(1, VGA_SR_INDEX);
9133 sr1 = inb(VGA_SR_DATA);
9134 outb(sr1 | 1<<5, VGA_SR_DATA);
9135 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9138 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9139 POSTING_READ(vga_reg);
9142 void intel_modeset_init(struct drm_device *dev)
9144 struct drm_i915_private *dev_priv = dev->dev_private;
9147 drm_mode_config_init(dev);
9149 dev->mode_config.min_width = 0;
9150 dev->mode_config.min_height = 0;
9152 dev->mode_config.preferred_depth = 24;
9153 dev->mode_config.prefer_shadow = 1;
9155 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9157 intel_init_quirks(dev);
9159 intel_init_display(dev);
9162 dev->mode_config.max_width = 2048;
9163 dev->mode_config.max_height = 2048;
9164 } else if (IS_GEN3(dev)) {
9165 dev->mode_config.max_width = 4096;
9166 dev->mode_config.max_height = 4096;
9168 dev->mode_config.max_width = 8192;
9169 dev->mode_config.max_height = 8192;
9171 dev->mode_config.fb_base = dev->agp->base;
9173 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9174 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9176 for (i = 0; i < dev_priv->num_pipe; i++) {
9177 intel_crtc_init(dev, i);
9178 ret = intel_plane_init(dev, i);
9180 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9183 /* Just disable it once at startup */
9184 i915_disable_vga(dev);
9185 intel_setup_outputs(dev);
9187 intel_init_clock_gating(dev);
9189 if (IS_IRONLAKE_M(dev)) {
9190 ironlake_enable_drps(dev);
9191 intel_init_emon(dev);
9194 if (IS_GEN6(dev) || IS_GEN7(dev)) {
9195 gen6_enable_rps(dev_priv);
9196 gen6_update_ring_freq(dev_priv);
9199 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9200 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9201 (unsigned long)dev);
9204 void intel_modeset_gem_init(struct drm_device *dev)
9206 if (IS_IRONLAKE_M(dev))
9207 ironlake_enable_rc6(dev);
9209 intel_setup_overlay(dev);
9212 void intel_modeset_cleanup(struct drm_device *dev)
9214 struct drm_i915_private *dev_priv = dev->dev_private;
9215 struct drm_crtc *crtc;
9216 struct intel_crtc *intel_crtc;
9218 drm_kms_helper_poll_fini(dev);
9219 mutex_lock(&dev->struct_mutex);
9221 intel_unregister_dsm_handler();
9224 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9225 /* Skip inactive CRTCs */
9229 intel_crtc = to_intel_crtc(crtc);
9230 intel_increase_pllclock(crtc);
9233 intel_disable_fbc(dev);
9235 if (IS_IRONLAKE_M(dev))
9236 ironlake_disable_drps(dev);
9237 if (IS_GEN6(dev) || IS_GEN7(dev))
9238 gen6_disable_rps(dev);
9240 if (IS_IRONLAKE_M(dev))
9241 ironlake_disable_rc6(dev);
9243 mutex_unlock(&dev->struct_mutex);
9245 /* Disable the irq before mode object teardown, for the irq might
9246 * enqueue unpin/hotplug work. */
9247 drm_irq_uninstall(dev);
9248 cancel_work_sync(&dev_priv->hotplug_work);
9249 cancel_work_sync(&dev_priv->rps_work);
9251 /* flush any delayed tasks or pending work */
9252 flush_scheduled_work();
9254 /* Shut off idle work before the crtcs get freed. */
9255 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9256 intel_crtc = to_intel_crtc(crtc);
9257 del_timer_sync(&intel_crtc->idle_timer);
9259 del_timer_sync(&dev_priv->idle_timer);
9260 cancel_work_sync(&dev_priv->idle_work);
9262 drm_mode_config_cleanup(dev);
9266 * Return which encoder is currently attached for connector.
9268 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9270 return &intel_attached_encoder(connector)->base;
9273 void intel_connector_attach_encoder(struct intel_connector *connector,
9274 struct intel_encoder *encoder)
9276 connector->encoder = encoder;
9277 drm_mode_connector_attach_encoder(&connector->base,
9282 * set vga decode state - true == enable VGA decode
9284 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9286 struct drm_i915_private *dev_priv = dev->dev_private;
9289 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9291 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9293 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9294 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9298 #ifdef CONFIG_DEBUG_FS
9299 #include <linux/seq_file.h>
9301 struct intel_display_error_state {
9302 struct intel_cursor_error_state {
9309 struct intel_pipe_error_state {
9321 struct intel_plane_error_state {
9332 struct intel_display_error_state *
9333 intel_display_capture_error_state(struct drm_device *dev)
9335 drm_i915_private_t *dev_priv = dev->dev_private;
9336 struct intel_display_error_state *error;
9339 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9343 for (i = 0; i < 2; i++) {
9344 error->cursor[i].control = I915_READ(CURCNTR(i));
9345 error->cursor[i].position = I915_READ(CURPOS(i));
9346 error->cursor[i].base = I915_READ(CURBASE(i));
9348 error->plane[i].control = I915_READ(DSPCNTR(i));
9349 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9350 error->plane[i].size = I915_READ(DSPSIZE(i));
9351 error->plane[i].pos = I915_READ(DSPPOS(i));
9352 error->plane[i].addr = I915_READ(DSPADDR(i));
9353 if (INTEL_INFO(dev)->gen >= 4) {
9354 error->plane[i].surface = I915_READ(DSPSURF(i));
9355 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9358 error->pipe[i].conf = I915_READ(PIPECONF(i));
9359 error->pipe[i].source = I915_READ(PIPESRC(i));
9360 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9361 error->pipe[i].hblank = I915_READ(HBLANK(i));
9362 error->pipe[i].hsync = I915_READ(HSYNC(i));
9363 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9364 error->pipe[i].vblank = I915_READ(VBLANK(i));
9365 error->pipe[i].vsync = I915_READ(VSYNC(i));
9372 intel_display_print_error_state(struct seq_file *m,
9373 struct drm_device *dev,
9374 struct intel_display_error_state *error)
9378 for (i = 0; i < 2; i++) {
9379 seq_printf(m, "Pipe [%d]:\n", i);
9380 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9381 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9382 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9383 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9384 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9385 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9386 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9387 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9389 seq_printf(m, "Plane [%d]:\n", i);
9390 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9391 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9392 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9393 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9394 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9395 if (INTEL_INFO(dev)->gen >= 4) {
9396 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9397 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9400 seq_printf(m, "Cursor [%d]:\n", i);
9401 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9402 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9403 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);