drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats supported by all gen */
  49 #define COMMON_PRIMARY_FORMATS \
  50         DRM_FORMAT_C8, \
  51         DRM_FORMAT_RGB565, \
  52         DRM_FORMAT_XRGB8888, \
  53         DRM_FORMAT_ARGB8888
  54
  55 /* Primary plane formats for gen <= 3 */
  56 static const uint32_t intel_primary_formats_gen2[] = {
  57         COMMON_PRIMARY_FORMATS,
  58         DRM_FORMAT_XRGB1555,
  59         DRM_FORMAT_ARGB1555,
  60 };
  61
  62 /* Primary plane formats for gen >= 4 */
  63 static const uint32_t intel_primary_formats_gen4[] = {
  64         COMMON_PRIMARY_FORMATS, \
  65         DRM_FORMAT_XBGR8888,
  66         DRM_FORMAT_ABGR8888,
  67         DRM_FORMAT_XRGB2101010,
  68         DRM_FORMAT_ARGB2101010,
  69         DRM_FORMAT_XBGR2101010,
  70         DRM_FORMAT_ABGR2101010,
  71 };
  72
  73 /* Cursor formats */
  74 static const uint32_t intel_cursor_formats[] = {
  75         DRM_FORMAT_ARGB8888,
  76 };
  77
  78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  79
  80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  81                                 struct intel_crtc_state *pipe_config);
  82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  83                                    struct intel_crtc_state *pipe_config);
  84
  85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  86                           int x, int y, struct drm_framebuffer *old_fb);
  87 static int intel_framebuffer_init(struct drm_device *dev,
  88                                   struct intel_framebuffer *ifb,
  89                                   struct drm_mode_fb_cmd2 *mode_cmd,
  90                                   struct drm_i915_gem_object *obj);
  91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  94                                          struct intel_link_m_n *m_n,
  95                                          struct intel_link_m_n *m2_n2);
  96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  99 static void vlv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_state *pipe_config);
 101 static void chv_prepare_pll(struct intel_crtc *crtc,
 102                             const struct intel_crtc_state *pipe_config);
 103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 105
 106 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 107 {
 108         if (!connector->mst_port)
 109                 return connector->encoder;
 110         else
 111                 return &connector->mst_port->mst_encoders[pipe]->base;
 112 }
 113
 114 typedef struct {
 115         int     min, max;
 116 } intel_range_t;
 117
 118 typedef struct {
 119         int     dot_limit;
 120         int     p2_slow, p2_fast;
 121 } intel_p2_t;
 122
 123 typedef struct intel_limit intel_limit_t;
 124 struct intel_limit {
 125         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 126         intel_p2_t          p2;
 127 };
 128
 129 int
 130 intel_pch_rawclk(struct drm_device *dev)
 131 {
 132         struct drm_i915_private *dev_priv = dev->dev_private;
 133
 134         WARN_ON(!HAS_PCH_SPLIT(dev));
 135
 136         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 137 }
 138
 139 static inline u32 /* units of 100MHz */
 140 intel_fdi_link_freq(struct drm_device *dev)
 141 {
 142         if (IS_GEN5(dev)) {
 143                 struct drm_i915_private *dev_priv = dev->dev_private;
 144                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 145         } else
 146                 return 27;
 147 }
 148
 149 static const intel_limit_t intel_limits_i8xx_dac = {
 150         .dot = { .min = 25000, .max = 350000 },
 151         .vco = { .min = 908000, .max = 1512000 },
 152         .n = { .min = 2, .max = 16 },
 153         .m = { .min = 96, .max = 140 },
 154         .m1 = { .min = 18, .max = 26 },
 155         .m2 = { .min = 6, .max = 16 },
 156         .p = { .min = 4, .max = 128 },
 157         .p1 = { .min = 2, .max = 33 },
 158         .p2 = { .dot_limit = 165000,
 159                 .p2_slow = 4, .p2_fast = 2 },
 160 };
 161
 162 static const intel_limit_t intel_limits_i8xx_dvo = {
 163         .dot = { .min = 25000, .max = 350000 },
 164         .vco = { .min = 908000, .max = 1512000 },
 165         .n = { .min = 2, .max = 16 },
 166         .m = { .min = 96, .max = 140 },
 167         .m1 = { .min = 18, .max = 26 },
 168         .m2 = { .min = 6, .max = 16 },
 169         .p = { .min = 4, .max = 128 },
 170         .p1 = { .min = 2, .max = 33 },
 171         .p2 = { .dot_limit = 165000,
 172                 .p2_slow = 4, .p2_fast = 4 },
 173 };
 174
 175 static const intel_limit_t intel_limits_i8xx_lvds = {
 176         .dot = { .min = 25000, .max = 350000 },
 177         .vco = { .min = 908000, .max = 1512000 },
 178         .n = { .min = 2, .max = 16 },
 179         .m = { .min = 96, .max = 140 },
 180         .m1 = { .min = 18, .max = 26 },
 181         .m2 = { .min = 6, .max = 16 },
 182         .p = { .min = 4, .max = 128 },
 183         .p1 = { .min = 1, .max = 6 },
 184         .p2 = { .dot_limit = 165000,
 185                 .p2_slow = 14, .p2_fast = 7 },
 186 };
 187
 188 static const intel_limit_t intel_limits_i9xx_sdvo = {
 189         .dot = { .min = 20000, .max = 400000 },
 190         .vco = { .min = 1400000, .max = 2800000 },
 191         .n = { .min = 1, .max = 6 },
 192         .m = { .min = 70, .max = 120 },
 193         .m1 = { .min = 8, .max = 18 },
 194         .m2 = { .min = 3, .max = 7 },
 195         .p = { .min = 5, .max = 80 },
 196         .p1 = { .min = 1, .max = 8 },
 197         .p2 = { .dot_limit = 200000,
 198                 .p2_slow = 10, .p2_fast = 5 },
 199 };
 200
 201 static const intel_limit_t intel_limits_i9xx_lvds = {
 202         .dot = { .min = 20000, .max = 400000 },
 203         .vco = { .min = 1400000, .max = 2800000 },
 204         .n = { .min = 1, .max = 6 },
 205         .m = { .min = 70, .max = 120 },
 206         .m1 = { .min = 8, .max = 18 },
 207         .m2 = { .min = 3, .max = 7 },
 208         .p = { .min = 7, .max = 98 },
 209         .p1 = { .min = 1, .max = 8 },
 210         .p2 = { .dot_limit = 112000,
 211                 .p2_slow = 14, .p2_fast = 7 },
 212 };
 213
 214
 215 static const intel_limit_t intel_limits_g4x_sdvo = {
 216         .dot = { .min = 25000, .max = 270000 },
 217         .vco = { .min = 1750000, .max = 3500000},
 218         .n = { .min = 1, .max = 4 },
 219         .m = { .min = 104, .max = 138 },
 220         .m1 = { .min = 17, .max = 23 },
 221         .m2 = { .min = 5, .max = 11 },
 222         .p = { .min = 10, .max = 30 },
 223         .p1 = { .min = 1, .max = 3},
 224         .p2 = { .dot_limit = 270000,
 225                 .p2_slow = 10,
 226                 .p2_fast = 10
 227         },
 228 };
 229
 230 static const intel_limit_t intel_limits_g4x_hdmi = {
 231         .dot = { .min = 22000, .max = 400000 },
 232         .vco = { .min = 1750000, .max = 3500000},
 233         .n = { .min = 1, .max = 4 },
 234         .m = { .min = 104, .max = 138 },
 235         .m1 = { .min = 16, .max = 23 },
 236         .m2 = { .min = 5, .max = 11 },
 237         .p = { .min = 5, .max = 80 },
 238         .p1 = { .min = 1, .max = 8},
 239         .p2 = { .dot_limit = 165000,
 240                 .p2_slow = 10, .p2_fast = 5 },
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 244         .dot = { .min = 20000, .max = 115000 },
 245         .vco = { .min = 1750000, .max = 3500000 },
 246         .n = { .min = 1, .max = 3 },
 247         .m = { .min = 104, .max = 138 },
 248         .m1 = { .min = 17, .max = 23 },
 249         .m2 = { .min = 5, .max = 11 },
 250         .p = { .min = 28, .max = 112 },
 251         .p1 = { .min = 2, .max = 8 },
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 14, .p2_fast = 14
 254         },
 255 };
 256
 257 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 258         .dot = { .min = 80000, .max = 224000 },
 259         .vco = { .min = 1750000, .max = 3500000 },
 260         .n = { .min = 1, .max = 3 },
 261         .m = { .min = 104, .max = 138 },
 262         .m1 = { .min = 17, .max = 23 },
 263         .m2 = { .min = 5, .max = 11 },
 264         .p = { .min = 14, .max = 42 },
 265         .p1 = { .min = 2, .max = 6 },
 266         .p2 = { .dot_limit = 0,
 267                 .p2_slow = 7, .p2_fast = 7
 268         },
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_sdvo = {
 272         .dot = { .min = 20000, .max = 400000},
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         /* Pineview's Ncounter is a ring counter */
 275         .n = { .min = 3, .max = 6 },
 276         .m = { .min = 2, .max = 256 },
 277         /* Pineview only has one combined m divider, which we treat as m2. */
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 200000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284 };
 285
 286 static const intel_limit_t intel_limits_pineview_lvds = {
 287         .dot = { .min = 20000, .max = 400000 },
 288         .vco = { .min = 1700000, .max = 3500000 },
 289         .n = { .min = 3, .max = 6 },
 290         .m = { .min = 2, .max = 256 },
 291         .m1 = { .min = 0, .max = 0 },
 292         .m2 = { .min = 0, .max = 254 },
 293         .p = { .min = 7, .max = 112 },
 294         .p1 = { .min = 1, .max = 8 },
 295         .p2 = { .dot_limit = 112000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 /* Ironlake / Sandybridge
 300  *
 301  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 302  * the range value for them is (actual_value - 2).
 303  */
 304 static const intel_limit_t intel_limits_ironlake_dac = {
 305         .dot = { .min = 25000, .max = 350000 },
 306         .vco = { .min = 1760000, .max = 3510000 },
 307         .n = { .min = 1, .max = 5 },
 308         .m = { .min = 79, .max = 127 },
 309         .m1 = { .min = 12, .max = 22 },
 310         .m2 = { .min = 5, .max = 9 },
 311         .p = { .min = 5, .max = 80 },
 312         .p1 = { .min = 1, .max = 8 },
 313         .p2 = { .dot_limit = 225000,
 314                 .p2_slow = 10, .p2_fast = 5 },
 315 };
 316
 317 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 318         .dot = { .min = 25000, .max = 350000 },
 319         .vco = { .min = 1760000, .max = 3510000 },
 320         .n = { .min = 1, .max = 3 },
 321         .m = { .min = 79, .max = 118 },
 322         .m1 = { .min = 12, .max = 22 },
 323         .m2 = { .min = 5, .max = 9 },
 324         .p = { .min = 28, .max = 112 },
 325         .p1 = { .min = 2, .max = 8 },
 326         .p2 = { .dot_limit = 225000,
 327                 .p2_slow = 14, .p2_fast = 14 },
 328 };
 329
 330 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 331         .dot = { .min = 25000, .max = 350000 },
 332         .vco = { .min = 1760000, .max = 3510000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 79, .max = 127 },
 335         .m1 = { .min = 12, .max = 22 },
 336         .m2 = { .min = 5, .max = 9 },
 337         .p = { .min = 14, .max = 56 },
 338         .p1 = { .min = 2, .max = 8 },
 339         .p2 = { .dot_limit = 225000,
 340                 .p2_slow = 7, .p2_fast = 7 },
 341 };
 342
 343 /* LVDS 100mhz refclk limits. */
 344 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 345         .dot = { .min = 25000, .max = 350000 },
 346         .vco = { .min = 1760000, .max = 3510000 },
 347         .n = { .min = 1, .max = 2 },
 348         .m = { .min = 79, .max = 126 },
 349         .m1 = { .min = 12, .max = 22 },
 350         .m2 = { .min = 5, .max = 9 },
 351         .p = { .min = 28, .max = 112 },
 352         .p1 = { .min = 2, .max = 8 },
 353         .p2 = { .dot_limit = 225000,
 354                 .p2_slow = 14, .p2_fast = 14 },
 355 };
 356
 357 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 358         .dot = { .min = 25000, .max = 350000 },
 359         .vco = { .min = 1760000, .max = 3510000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 79, .max = 126 },
 362         .m1 = { .min = 12, .max = 22 },
 363         .m2 = { .min = 5, .max = 9 },
 364         .p = { .min = 14, .max = 42 },
 365         .p1 = { .min = 2, .max = 6 },
 366         .p2 = { .dot_limit = 225000,
 367                 .p2_slow = 7, .p2_fast = 7 },
 368 };
 369
 370 static const intel_limit_t intel_limits_vlv = {
 371          /*
 372           * These are the data rate limits (measured in fast clocks)
 373           * since those are the strictest limits we have. The fast
 374           * clock and actual rate limits are more relaxed, so checking
 375           * them would make no difference.
 376           */
 377         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 378         .vco = { .min = 4000000, .max = 6000000 },
 379         .n = { .min = 1, .max = 7 },
 380         .m1 = { .min = 2, .max = 3 },
 381         .m2 = { .min = 11, .max = 156 },
 382         .p1 = { .min = 2, .max = 3 },
 383         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 384 };
 385
 386 static const intel_limit_t intel_limits_chv = {
 387         /*
 388          * These are the data rate limits (measured in fast clocks)
 389          * since those are the strictest limits we have.  The fast
 390          * clock and actual rate limits are more relaxed, so checking
 391          * them would make no difference.
 392          */
 393         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 394         .vco = { .min = 4800000, .max = 6480000 },
 395         .n = { .min = 1, .max = 1 },
 396         .m1 = { .min = 2, .max = 2 },
 397         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 398         .p1 = { .min = 2, .max = 4 },
 399         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 400 };
 401
 402 static void vlv_clock(int refclk, intel_clock_t *clock)
 403 {
 404         clock->m = clock->m1 * clock->m2;
 405         clock->p = clock->p1 * clock->p2;
 406         if (WARN_ON(clock->n == 0 || clock->p == 0))
 407                 return;
 408         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 409         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 410 }
 411
 412 /**
 413  * Returns whether any output on the specified pipe is of the specified type
 414  */
 415 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 416 {
 417         struct drm_device *dev = crtc->base.dev;
 418         struct intel_encoder *encoder;
 419
 420         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 421                 if (encoder->type == type)
 422                         return true;
 423
 424         return false;
 425 }
 426
 427 /**
 428  * Returns whether any output on the specified pipe will have the specified
 429  * type after a staged modeset is complete, i.e., the same as
 430  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 431  * encoder->crtc.
 432  */
 433 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 434 {
 435         struct drm_device *dev = crtc->base.dev;
 436         struct intel_encoder *encoder;
 437
 438         for_each_intel_encoder(dev, encoder)
 439                 if (encoder->new_crtc == crtc && encoder->type == type)
 440                         return true;
 441
 442         return false;
 443 }
 444
 445 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 446                                                 int refclk)
 447 {
 448         struct drm_device *dev = crtc->base.dev;
 449         const intel_limit_t *limit;
 450
 451         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 452                 if (intel_is_dual_link_lvds(dev)) {
 453                         if (refclk == 100000)
 454                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 455                         else
 456                                 limit = &intel_limits_ironlake_dual_lvds;
 457                 } else {
 458                         if (refclk == 100000)
 459                                 limit = &intel_limits_ironlake_single_lvds_100m;
 460                         else
 461                                 limit = &intel_limits_ironlake_single_lvds;
 462                 }
 463         } else
 464                 limit = &intel_limits_ironlake_dac;
 465
 466         return limit;
 467 }
 468
 469 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 470 {
 471         struct drm_device *dev = crtc->base.dev;
 472         const intel_limit_t *limit;
 473
 474         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 475                 if (intel_is_dual_link_lvds(dev))
 476                         limit = &intel_limits_g4x_dual_channel_lvds;
 477                 else
 478                         limit = &intel_limits_g4x_single_channel_lvds;
 479         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 480                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 481                 limit = &intel_limits_g4x_hdmi;
 482         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 483                 limit = &intel_limits_g4x_sdvo;
 484         } else /* The option is for other outputs */
 485                 limit = &intel_limits_i9xx_sdvo;
 486
 487         return limit;
 488 }
 489
 490 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 491 {
 492         struct drm_device *dev = crtc->base.dev;
 493         const intel_limit_t *limit;
 494
 495         if (HAS_PCH_SPLIT(dev))
 496                 limit = intel_ironlake_limit(crtc, refclk);
 497         else if (IS_G4X(dev)) {
 498                 limit = intel_g4x_limit(crtc);
 499         } else if (IS_PINEVIEW(dev)) {
 500                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 501                         limit = &intel_limits_pineview_lvds;
 502                 else
 503                         limit = &intel_limits_pineview_sdvo;
 504         } else if (IS_CHERRYVIEW(dev)) {
 505                 limit = &intel_limits_chv;
 506         } else if (IS_VALLEYVIEW(dev)) {
 507                 limit = &intel_limits_vlv;
 508         } else if (!IS_GEN2(dev)) {
 509                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 510                         limit = &intel_limits_i9xx_lvds;
 511                 else
 512                         limit = &intel_limits_i9xx_sdvo;
 513         } else {
 514                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 515                         limit = &intel_limits_i8xx_lvds;
 516                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 517                         limit = &intel_limits_i8xx_dvo;
 518                 else
 519                         limit = &intel_limits_i8xx_dac;
 520         }
 521         return limit;
 522 }
 523
 524 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 525 static void pineview_clock(int refclk, intel_clock_t *clock)
 526 {
 527         clock->m = clock->m2 + 2;
 528         clock->p = clock->p1 * clock->p2;
 529         if (WARN_ON(clock->n == 0 || clock->p == 0))
 530                 return;
 531         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 533 }
 534
 535 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 536 {
 537         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 538 }
 539
 540 static void i9xx_clock(int refclk, intel_clock_t *clock)
 541 {
 542         clock->m = i9xx_dpll_compute_m(clock);
 543         clock->p = clock->p1 * clock->p2;
 544         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 545                 return;
 546         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 547         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 548 }
 549
 550 static void chv_clock(int refclk, intel_clock_t *clock)
 551 {
 552         clock->m = clock->m1 * clock->m2;
 553         clock->p = clock->p1 * clock->p2;
 554         if (WARN_ON(clock->n == 0 || clock->p == 0))
 555                 return;
 556         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 557                         clock->n << 22);
 558         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 559 }
 560
 561 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 562 /**
 563  * Returns whether the given set of divisors are valid for a given refclk with
 564  * the given connectors.
 565  */
 566
 567 static bool intel_PLL_is_valid(struct drm_device *dev,
 568                                const intel_limit_t *limit,
 569                                const intel_clock_t *clock)
 570 {
 571         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 572                 INTELPllInvalid("n out of range\n");
 573         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 574                 INTELPllInvalid("p1 out of range\n");
 575         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 576                 INTELPllInvalid("m2 out of range\n");
 577         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 578                 INTELPllInvalid("m1 out of range\n");
 579
 580         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 581                 if (clock->m1 <= clock->m2)
 582                         INTELPllInvalid("m1 <= m2\n");
 583
 584         if (!IS_VALLEYVIEW(dev)) {
 585                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 586                         INTELPllInvalid("p out of range\n");
 587                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 588                         INTELPllInvalid("m out of range\n");
 589         }
 590
 591         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 592                 INTELPllInvalid("vco out of range\n");
 593         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 594          * connector, etc., rather than just a single range.
 595          */
 596         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 597                 INTELPllInvalid("dot out of range\n");
 598
 599         return true;
 600 }
 601
 602 static bool
 603 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 604                     int target, int refclk, intel_clock_t *match_clock,
 605                     intel_clock_t *best_clock)
 606 {
 607         struct drm_device *dev = crtc->base.dev;
 608         intel_clock_t clock;
 609         int err = target;
 610
 611         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 612                 /*
 613                  * For LVDS just rely on its current settings for dual-channel.
 614                  * We haven't figured out how to reliably set up different
 615                  * single/dual channel state, if we even can.
 616                  */
 617                 if (intel_is_dual_link_lvds(dev))
 618                         clock.p2 = limit->p2.p2_fast;
 619                 else
 620                         clock.p2 = limit->p2.p2_slow;
 621         } else {
 622                 if (target < limit->p2.dot_limit)
 623                         clock.p2 = limit->p2.p2_slow;
 624                 else
 625                         clock.p2 = limit->p2.p2_fast;
 626         }
 627
 628         memset(best_clock, 0, sizeof(*best_clock));
 629
 630         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 631              clock.m1++) {
 632                 for (clock.m2 = limit->m2.min;
 633                      clock.m2 <= limit->m2.max; clock.m2++) {
 634                         if (clock.m2 >= clock.m1)
 635                                 break;
 636                         for (clock.n = limit->n.min;
 637                              clock.n <= limit->n.max; clock.n++) {
 638                                 for (clock.p1 = limit->p1.min;
 639                                         clock.p1 <= limit->p1.max; clock.p1++) {
 640                                         int this_err;
 641
 642                                         i9xx_clock(refclk, &clock);
 643                                         if (!intel_PLL_is_valid(dev, limit,
 644                                                                 &clock))
 645                                                 continue;
 646                                         if (match_clock &&
 647                                             clock.p != match_clock->p)
 648                                                 continue;
 649
 650                                         this_err = abs(clock.dot - target);
 651                                         if (this_err < err) {
 652                                                 *best_clock = clock;
 653                                                 err = this_err;
 654                                         }
 655                                 }
 656                         }
 657                 }
 658         }
 659
 660         return (err != target);
 661 }
 662
 663 static bool
 664 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 665                    int target, int refclk, intel_clock_t *match_clock,
 666                    intel_clock_t *best_clock)
 667 {
 668         struct drm_device *dev = crtc->base.dev;
 669         intel_clock_t clock;
 670         int err = target;
 671
 672         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 673                 /*
 674                  * For LVDS just rely on its current settings for dual-channel.
 675                  * We haven't figured out how to reliably set up different
 676                  * single/dual channel state, if we even can.
 677                  */
 678                 if (intel_is_dual_link_lvds(dev))
 679                         clock.p2 = limit->p2.p2_fast;
 680                 else
 681                         clock.p2 = limit->p2.p2_slow;
 682         } else {
 683                 if (target < limit->p2.dot_limit)
 684                         clock.p2 = limit->p2.p2_slow;
 685                 else
 686                         clock.p2 = limit->p2.p2_fast;
 687         }
 688
 689         memset(best_clock, 0, sizeof(*best_clock));
 690
 691         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 692              clock.m1++) {
 693                 for (clock.m2 = limit->m2.min;
 694                      clock.m2 <= limit->m2.max; clock.m2++) {
 695                         for (clock.n = limit->n.min;
 696                              clock.n <= limit->n.max; clock.n++) {
 697                                 for (clock.p1 = limit->p1.min;
 698                                         clock.p1 <= limit->p1.max; clock.p1++) {
 699                                         int this_err;
 700
 701                                         pineview_clock(refclk, &clock);
 702                                         if (!intel_PLL_is_valid(dev, limit,
 703                                                                 &clock))
 704                                                 continue;
 705                                         if (match_clock &&
 706                                             clock.p != match_clock->p)
 707                                                 continue;
 708
 709                                         this_err = abs(clock.dot - target);
 710                                         if (this_err < err) {
 711                                                 *best_clock = clock;
 712                                                 err = this_err;
 713                                         }
 714                                 }
 715                         }
 716                 }
 717         }
 718
 719         return (err != target);
 720 }
 721
 722 static bool
 723 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 724                    int target, int refclk, intel_clock_t *match_clock,
 725                    intel_clock_t *best_clock)
 726 {
 727         struct drm_device *dev = crtc->base.dev;
 728         intel_clock_t clock;
 729         int max_n;
 730         bool found;
 731         /* approximately equals target * 0.00585 */
 732         int err_most = (target >> 8) + (target >> 9);
 733         found = false;
 734
 735         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 736                 if (intel_is_dual_link_lvds(dev))
 737                         clock.p2 = limit->p2.p2_fast;
 738                 else
 739                         clock.p2 = limit->p2.p2_slow;
 740         } else {
 741                 if (target < limit->p2.dot_limit)
 742                         clock.p2 = limit->p2.p2_slow;
 743                 else
 744                         clock.p2 = limit->p2.p2_fast;
 745         }
 746
 747         memset(best_clock, 0, sizeof(*best_clock));
 748         max_n = limit->n.max;
 749         /* based on hardware requirement, prefer smaller n to precision */
 750         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 751                 /* based on hardware requirement, prefere larger m1,m2 */
 752                 for (clock.m1 = limit->m1.max;
 753                      clock.m1 >= limit->m1.min; clock.m1--) {
 754                         for (clock.m2 = limit->m2.max;
 755                              clock.m2 >= limit->m2.min; clock.m2--) {
 756                                 for (clock.p1 = limit->p1.max;
 757                                      clock.p1 >= limit->p1.min; clock.p1--) {
 758                                         int this_err;
 759
 760                                         i9xx_clock(refclk, &clock);
 761                                         if (!intel_PLL_is_valid(dev, limit,
 762                                                                 &clock))
 763                                                 continue;
 764
 765                                         this_err = abs(clock.dot - target);
 766                                         if (this_err < err_most) {
 767                                                 *best_clock = clock;
 768                                                 err_most = this_err;
 769                                                 max_n = clock.n;
 770                                                 found = true;
 771                                         }
 772                                 }
 773                         }
 774                 }
 775         }
 776         return found;
 777 }
 778
 779 /*
 780  * Check if the calculated PLL configuration is more optimal compared to the
 781  * best configuration and error found so far. Return the calculated error.
 782  */
 783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 784                                const intel_clock_t *calculated_clock,
 785                                const intel_clock_t *best_clock,
 786                                unsigned int best_error_ppm,
 787                                unsigned int *error_ppm)
 788 {
 789         /*
 790          * For CHV ignore the error and consider only the P value.
 791          * Prefer a bigger P value based on HW requirements.
 792          */
 793         if (IS_CHERRYVIEW(dev)) {
 794                 *error_ppm = 0;
 795
 796                 return calculated_clock->p > best_clock->p;
 797         }
 798
 799         if (WARN_ON_ONCE(!target_freq))
 800                 return false;
 801
 802         *error_ppm = div_u64(1000000ULL *
 803                                 abs(target_freq - calculated_clock->dot),
 804                              target_freq);
 805         /*
 806          * Prefer a better P value over a better (smaller) error if the error
 807          * is small. Ensure this preference for future configurations too by
 808          * setting the error to 0.
 809          */
 810         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 811                 *error_ppm = 0;
 812
 813                 return true;
 814         }
 815
 816         return *error_ppm + 10 < best_error_ppm;
 817 }
 818
 819 static bool
 820 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 821                    int target, int refclk, intel_clock_t *match_clock,
 822                    intel_clock_t *best_clock)
 823 {
 824         struct drm_device *dev = crtc->base.dev;
 825         intel_clock_t clock;
 826         unsigned int bestppm = 1000000;
 827         /* min update 19.2 MHz */
 828         int max_n = min(limit->n.max, refclk / 19200);
 829         bool found = false;
 830
 831         target *= 5; /* fast clock */
 832
 833         memset(best_clock, 0, sizeof(*best_clock));
 834
 835         /* based on hardware requirement, prefer smaller n to precision */
 836         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 837                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 838                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 839                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 840                                 clock.p = clock.p1 * clock.p2;
 841                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 842                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 843                                         unsigned int ppm;
 844
 845                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 846                                                                      refclk * clock.m1);
 847
 848                                         vlv_clock(refclk, &clock);
 849
 850                                         if (!intel_PLL_is_valid(dev, limit,
 851                                                                 &clock))
 852                                                 continue;
 853
 854                                         if (!vlv_PLL_is_optimal(dev, target,
 855                                                                 &clock,
 856                                                                 best_clock,
 857                                                                 bestppm, &ppm))
 858                                                 continue;
 859
 860                                         *best_clock = clock;
 861                                         bestppm = ppm;
 862                                         found = true;
 863                                 }
 864                         }
 865                 }
 866         }
 867
 868         return found;
 869 }
 870
 871 static bool
 872 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 873                    int target, int refclk, intel_clock_t *match_clock,
 874                    intel_clock_t *best_clock)
 875 {
 876         struct drm_device *dev = crtc->base.dev;
 877         unsigned int best_error_ppm;
 878         intel_clock_t clock;
 879         uint64_t m2;
 880         int found = false;
 881
 882         memset(best_clock, 0, sizeof(*best_clock));
 883         best_error_ppm = 1000000;
 884
 885         /*
 886          * Based on hardware doc, the n always set to 1, and m1 always
 887          * set to 2.  If requires to support 200Mhz refclk, we need to
 888          * revisit this because n may not 1 anymore.
 889          */
 890         clock.n = 1, clock.m1 = 2;
 891         target *= 5;    /* fast clock */
 892
 893         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 894                 for (clock.p2 = limit->p2.p2_fast;
 895                                 clock.p2 >= limit->p2.p2_slow;
 896                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 897                         unsigned int error_ppm;
 898
 899                         clock.p = clock.p1 * clock.p2;
 900
 901                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 902                                         clock.n) << 22, refclk * clock.m1);
 903
 904                         if (m2 > INT_MAX/clock.m1)
 905                                 continue;
 906
 907                         clock.m2 = m2;
 908
 909                         chv_clock(refclk, &clock);
 910
 911                         if (!intel_PLL_is_valid(dev, limit, &clock))
 912                                 continue;
 913
 914                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 915                                                 best_error_ppm, &error_ppm))
 916                                 continue;
 917
 918                         *best_clock = clock;
 919                         best_error_ppm = error_ppm;
 920                         found = true;
 921                 }
 922         }
 923
 924         return found;
 925 }
 926
 927 bool intel_crtc_active(struct drm_crtc *crtc)
 928 {
 929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 930
 931         /* Be paranoid as we can arrive here with only partial
 932          * state retrieved from the hardware during setup.
 933          *
 934          * We can ditch the adjusted_mode.crtc_clock check as soon
 935          * as Haswell has gained clock readout/fastboot support.
 936          *
 937          * We can ditch the crtc->primary->fb check as soon as we can
 938          * properly reconstruct framebuffers.
 939          *
 940          * FIXME: The intel_crtc->active here should be switched to
 941          * crtc->state->active once we have proper CRTC states wired up
 942          * for atomic.
 943          */
 944         return intel_crtc->active && crtc->primary->state->fb &&
 945                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 946 }
 947
 948 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 949                                              enum pipe pipe)
 950 {
 951         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 953
 954         return intel_crtc->config->cpu_transcoder;
 955 }
 956
 957 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 958 {
 959         struct drm_i915_private *dev_priv = dev->dev_private;
 960         u32 reg = PIPEDSL(pipe);
 961         u32 line1, line2;
 962         u32 line_mask;
 963
 964         if (IS_GEN2(dev))
 965                 line_mask = DSL_LINEMASK_GEN2;
 966         else
 967                 line_mask = DSL_LINEMASK_GEN3;
 968
 969         line1 = I915_READ(reg) & line_mask;
 970         mdelay(5);
 971         line2 = I915_READ(reg) & line_mask;
 972
 973         return line1 == line2;
 974 }
 975
 976 /*
 977  * intel_wait_for_pipe_off - wait for pipe to turn off
 978  * @crtc: crtc whose pipe to wait for
 979  *
 980  * After disabling a pipe, we can't wait for vblank in the usual way,
 981  * spinning on the vblank interrupt status bit, since we won't actually
 982  * see an interrupt when the pipe is disabled.
 983  *
 984  * On Gen4 and above:
 985  *   wait for the pipe register state bit to turn off
 986  *
 987  * Otherwise:
 988  *   wait for the display line value to settle (it usually
 989  *   ends up stopping at the start of the next frame).
 990  *
 991  */
 992 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 993 {
 994         struct drm_device *dev = crtc->base.dev;
 995         struct drm_i915_private *dev_priv = dev->dev_private;
 996         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
 997         enum pipe pipe = crtc->pipe;
 998
 999         if (INTEL_INFO(dev)->gen >= 4) {
1000                 int reg = PIPECONF(cpu_transcoder);
1001
1002                 /* Wait for the Pipe State to go off */
1003                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1004                              100))
1005                         WARN(1, "pipe_off wait timed out\n");
1006         } else {
1007                 /* Wait for the display line to settle */
1008                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1009                         WARN(1, "pipe_off wait timed out\n");
1010         }
1011 }
1012
1013 /*
1014  * ibx_digital_port_connected - is the specified port connected?
1015  * @dev_priv: i915 private structure
1016  * @port: the port to test
1017  *
1018  * Returns true if @port is connected, false otherwise.
1019  */
1020 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1021                                 struct intel_digital_port *port)
1022 {
1023         u32 bit;
1024
1025         if (HAS_PCH_IBX(dev_priv->dev)) {
1026                 switch (port->port) {
1027                 case PORT_B:
1028                         bit = SDE_PORTB_HOTPLUG;
1029                         break;
1030                 case PORT_C:
1031                         bit = SDE_PORTC_HOTPLUG;
1032                         break;
1033                 case PORT_D:
1034                         bit = SDE_PORTD_HOTPLUG;
1035                         break;
1036                 default:
1037                         return true;
1038                 }
1039         } else {
1040                 switch (port->port) {
1041                 case PORT_B:
1042                         bit = SDE_PORTB_HOTPLUG_CPT;
1043                         break;
1044                 case PORT_C:
1045                         bit = SDE_PORTC_HOTPLUG_CPT;
1046                         break;
1047                 case PORT_D:
1048                         bit = SDE_PORTD_HOTPLUG_CPT;
1049                         break;
1050                 default:
1051                         return true;
1052                 }
1053         }
1054
1055         return I915_READ(SDEISR) & bit;
1056 }
1057
1058 static const char *state_string(bool enabled)
1059 {
1060         return enabled ? "on" : "off";
1061 }
1062
1063 /* Only for pre-ILK configs */
1064 void assert_pll(struct drm_i915_private *dev_priv,
1065                 enum pipe pipe, bool state)
1066 {
1067         int reg;
1068         u32 val;
1069         bool cur_state;
1070
1071         reg = DPLL(pipe);
1072         val = I915_READ(reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         I915_STATE_WARN(cur_state != state,
1075              "PLL state assertion failure (expected %s, current %s)\n",
1076              state_string(state), state_string(cur_state));
1077 }
1078
1079 /* XXX: the dsi pll is shared between MIPI DSI ports */
1080 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1081 {
1082         u32 val;
1083         bool cur_state;
1084
1085         mutex_lock(&dev_priv->dpio_lock);
1086         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1087         mutex_unlock(&dev_priv->dpio_lock);
1088
1089         cur_state = val & DSI_PLL_VCO_EN;
1090         I915_STATE_WARN(cur_state != state,
1091              "DSI PLL state assertion failure (expected %s, current %s)\n",
1092              state_string(state), state_string(cur_state));
1093 }
1094 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1095 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1096
1097 struct intel_shared_dpll *
1098 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1099 {
1100         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1101
1102         if (crtc->config->shared_dpll < 0)
1103                 return NULL;
1104
1105         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1106 }
1107
1108 /* For ILK+ */
1109 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1110                         struct intel_shared_dpll *pll,
1111                         bool state)
1112 {
1113         bool cur_state;
1114         struct intel_dpll_hw_state hw_state;
1115
1116         if (WARN (!pll,
1117                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1118                 return;
1119
1120         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1121         I915_STATE_WARN(cur_state != state,
1122              "%s assertion failure (expected %s, current %s)\n",
1123              pll->name, state_string(state), state_string(cur_state));
1124 }
1125
1126 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1127                           enum pipe pipe, bool state)
1128 {
1129         int reg;
1130         u32 val;
1131         bool cur_state;
1132         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1133                                                                       pipe);
1134
1135         if (HAS_DDI(dev_priv->dev)) {
1136                 /* DDI does not have a specific FDI_TX register */
1137                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1138                 val = I915_READ(reg);
1139                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1140         } else {
1141                 reg = FDI_TX_CTL(pipe);
1142                 val = I915_READ(reg);
1143                 cur_state = !!(val & FDI_TX_ENABLE);
1144         }
1145         I915_STATE_WARN(cur_state != state,
1146              "FDI TX state assertion failure (expected %s, current %s)\n",
1147              state_string(state), state_string(cur_state));
1148 }
1149 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1150 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1151
1152 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1153                           enum pipe pipe, bool state)
1154 {
1155         int reg;
1156         u32 val;
1157         bool cur_state;
1158
1159         reg = FDI_RX_CTL(pipe);
1160         val = I915_READ(reg);
1161         cur_state = !!(val & FDI_RX_ENABLE);
1162         I915_STATE_WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (HAS_DDI(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189                        enum pipe pipe, bool state)
1190 {
1191         int reg;
1192         u32 val;
1193         bool cur_state;
1194
1195         reg = FDI_RX_CTL(pipe);
1196         val = I915_READ(reg);
1197         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1198         I915_STATE_WARN(cur_state != state,
1199              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1200              state_string(state), state_string(cur_state));
1201 }
1202
1203 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                            enum pipe pipe)
1205 {
1206         struct drm_device *dev = dev_priv->dev;
1207         int pp_reg;
1208         u32 val;
1209         enum pipe panel_pipe = PIPE_A;
1210         bool locked = true;
1211
1212         if (WARN_ON(HAS_DDI(dev)))
1213                 return;
1214
1215         if (HAS_PCH_SPLIT(dev)) {
1216                 u32 port_sel;
1217
1218                 pp_reg = PCH_PP_CONTROL;
1219                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1220
1221                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1222                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1223                         panel_pipe = PIPE_B;
1224                 /* XXX: else fix for eDP */
1225         } else if (IS_VALLEYVIEW(dev)) {
1226                 /* presumably write lock depends on pipe, not port select */
1227                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1228                 panel_pipe = pipe;
1229         } else {
1230                 pp_reg = PP_CONTROL;
1231                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1232                         panel_pipe = PIPE_B;
1233         }
1234
1235         val = I915_READ(pp_reg);
1236         if (!(val & PANEL_POWER_ON) ||
1237             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1238                 locked = false;
1239
1240         I915_STATE_WARN(panel_pipe == pipe && locked,
1241              "panel assertion failure, pipe %c regs locked\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static void assert_cursor(struct drm_i915_private *dev_priv,
1246                           enum pipe pipe, bool state)
1247 {
1248         struct drm_device *dev = dev_priv->dev;
1249         bool cur_state;
1250
1251         if (IS_845G(dev) || IS_I865G(dev))
1252                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1253         else
1254                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1255
1256         I915_STATE_WARN(cur_state != state,
1257              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1258              pipe_name(pipe), state_string(state), state_string(cur_state));
1259 }
1260 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1261 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1262
1263 void assert_pipe(struct drm_i915_private *dev_priv,
1264                  enum pipe pipe, bool state)
1265 {
1266         int reg;
1267         u32 val;
1268         bool cur_state;
1269         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1270                                                                       pipe);
1271
1272         /* if we need the pipe quirk it must be always on */
1273         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1274             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1275                 state = true;
1276
1277         if (!intel_display_power_is_enabled(dev_priv,
1278                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1279                 cur_state = false;
1280         } else {
1281                 reg = PIPECONF(cpu_transcoder);
1282                 val = I915_READ(reg);
1283                 cur_state = !!(val & PIPECONF_ENABLE);
1284         }
1285
1286         I915_STATE_WARN(cur_state != state,
1287              "pipe %c assertion failure (expected %s, current %s)\n",
1288              pipe_name(pipe), state_string(state), state_string(cur_state));
1289 }
1290
1291 static void assert_plane(struct drm_i915_private *dev_priv,
1292                          enum plane plane, bool state)
1293 {
1294         int reg;
1295         u32 val;
1296         bool cur_state;
1297
1298         reg = DSPCNTR(plane);
1299         val = I915_READ(reg);
1300         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1301         I915_STATE_WARN(cur_state != state,
1302              "plane %c assertion failure (expected %s, current %s)\n",
1303              plane_name(plane), state_string(state), state_string(cur_state));
1304 }
1305
1306 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1307 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1308
1309 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1310                                    enum pipe pipe)
1311 {
1312         struct drm_device *dev = dev_priv->dev;
1313         int reg, i;
1314         u32 val;
1315         int cur_pipe;
1316
1317         /* Primary planes are fixed to pipes on gen4+ */
1318         if (INTEL_INFO(dev)->gen >= 4) {
1319                 reg = DSPCNTR(pipe);
1320                 val = I915_READ(reg);
1321                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1322                      "plane %c assertion failure, should be disabled but not\n",
1323                      plane_name(pipe));
1324                 return;
1325         }
1326
1327         /* Need to check both planes against the pipe */
1328         for_each_pipe(dev_priv, i) {
1329                 reg = DSPCNTR(i);
1330                 val = I915_READ(reg);
1331                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1332                         DISPPLANE_SEL_PIPE_SHIFT;
1333                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1334                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1335                      plane_name(i), pipe_name(pipe));
1336         }
1337 }
1338
1339 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1340                                     enum pipe pipe)
1341 {
1342         struct drm_device *dev = dev_priv->dev;
1343         int reg, sprite;
1344         u32 val;
1345
1346         if (INTEL_INFO(dev)->gen >= 9) {
1347                 for_each_sprite(dev_priv, pipe, sprite) {
1348                         val = I915_READ(PLANE_CTL(pipe, sprite));
1349                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1350                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1351                              sprite, pipe_name(pipe));
1352                 }
1353         } else if (IS_VALLEYVIEW(dev)) {
1354                 for_each_sprite(dev_priv, pipe, sprite) {
1355                         reg = SPCNTR(pipe, sprite);
1356                         val = I915_READ(reg);
1357                         I915_STATE_WARN(val & SP_ENABLE,
1358                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1359                              sprite_name(pipe, sprite), pipe_name(pipe));
1360                 }
1361         } else if (INTEL_INFO(dev)->gen >= 7) {
1362                 reg = SPRCTL(pipe);
1363                 val = I915_READ(reg);
1364                 I915_STATE_WARN(val & SPRITE_ENABLE,
1365                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1366                      plane_name(pipe), pipe_name(pipe));
1367         } else if (INTEL_INFO(dev)->gen >= 5) {
1368                 reg = DVSCNTR(pipe);
1369                 val = I915_READ(reg);
1370                 I915_STATE_WARN(val & DVS_ENABLE,
1371                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1372                      plane_name(pipe), pipe_name(pipe));
1373         }
1374 }
1375
1376 static void assert_vblank_disabled(struct drm_crtc *crtc)
1377 {
1378         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1379                 drm_crtc_vblank_put(crtc);
1380 }
1381
1382 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1383 {
1384         u32 val;
1385         bool enabled;
1386
1387         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1388
1389         val = I915_READ(PCH_DREF_CONTROL);
1390         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1391                             DREF_SUPERSPREAD_SOURCE_MASK));
1392         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1393 }
1394
1395 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1396                                            enum pipe pipe)
1397 {
1398         int reg;
1399         u32 val;
1400         bool enabled;
1401
1402         reg = PCH_TRANSCONF(pipe);
1403         val = I915_READ(reg);
1404         enabled = !!(val & TRANS_ENABLE);
1405         I915_STATE_WARN(enabled,
1406              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1407              pipe_name(pipe));
1408 }
1409
1410 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1411                             enum pipe pipe, u32 port_sel, u32 val)
1412 {
1413         if ((val & DP_PORT_EN) == 0)
1414                 return false;
1415
1416         if (HAS_PCH_CPT(dev_priv->dev)) {
1417                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1418                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1419                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1420                         return false;
1421         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1422                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1423                         return false;
1424         } else {
1425                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1426                         return false;
1427         }
1428         return true;
1429 }
1430
1431 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1432                               enum pipe pipe, u32 val)
1433 {
1434         if ((val & SDVO_ENABLE) == 0)
1435                 return false;
1436
1437         if (HAS_PCH_CPT(dev_priv->dev)) {
1438                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1439                         return false;
1440         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1441                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1442                         return false;
1443         } else {
1444                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1445                         return false;
1446         }
1447         return true;
1448 }
1449
1450 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1451                               enum pipe pipe, u32 val)
1452 {
1453         if ((val & LVDS_PORT_EN) == 0)
1454                 return false;
1455
1456         if (HAS_PCH_CPT(dev_priv->dev)) {
1457                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458                         return false;
1459         } else {
1460                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1461                         return false;
1462         }
1463         return true;
1464 }
1465
1466 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1467                               enum pipe pipe, u32 val)
1468 {
1469         if ((val & ADPA_DAC_ENABLE) == 0)
1470                 return false;
1471         if (HAS_PCH_CPT(dev_priv->dev)) {
1472                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1473                         return false;
1474         } else {
1475                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1476                         return false;
1477         }
1478         return true;
1479 }
1480
1481 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1482                                    enum pipe pipe, int reg, u32 port_sel)
1483 {
1484         u32 val = I915_READ(reg);
1485         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1486              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1487              reg, pipe_name(pipe));
1488
1489         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1490              && (val & DP_PIPEB_SELECT),
1491              "IBX PCH dp port still using transcoder B\n");
1492 }
1493
1494 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1495                                      enum pipe pipe, int reg)
1496 {
1497         u32 val = I915_READ(reg);
1498         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1499              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1500              reg, pipe_name(pipe));
1501
1502         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1503              && (val & SDVO_PIPE_B_SELECT),
1504              "IBX PCH hdmi port still using transcoder B\n");
1505 }
1506
1507 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1508                                       enum pipe pipe)
1509 {
1510         int reg;
1511         u32 val;
1512
1513         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1514         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1515         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1516
1517         reg = PCH_ADPA;
1518         val = I915_READ(reg);
1519         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520              "PCH VGA enabled on transcoder %c, should be disabled\n",
1521              pipe_name(pipe));
1522
1523         reg = PCH_LVDS;
1524         val = I915_READ(reg);
1525         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1526              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1527              pipe_name(pipe));
1528
1529         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1530         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1531         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1532 }
1533
1534 static void intel_init_dpio(struct drm_device *dev)
1535 {
1536         struct drm_i915_private *dev_priv = dev->dev_private;
1537
1538         if (!IS_VALLEYVIEW(dev))
1539                 return;
1540
1541         /*
1542          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1543          * CHV x1 PHY (DP/HDMI D)
1544          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1545          */
1546         if (IS_CHERRYVIEW(dev)) {
1547                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1548                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1549         } else {
1550                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1551         }
1552 }
1553
1554 static void vlv_enable_pll(struct intel_crtc *crtc,
1555                            const struct intel_crtc_state *pipe_config)
1556 {
1557         struct drm_device *dev = crtc->base.dev;
1558         struct drm_i915_private *dev_priv = dev->dev_private;
1559         int reg = DPLL(crtc->pipe);
1560         u32 dpll = pipe_config->dpll_hw_state.dpll;
1561
1562         assert_pipe_disabled(dev_priv, crtc->pipe);
1563
1564         /* No really, not for ILK+ */
1565         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1566
1567         /* PLL is protected by panel, make sure we can write it */
1568         if (IS_MOBILE(dev_priv->dev))
1569                 assert_panel_unlocked(dev_priv, crtc->pipe);
1570
1571         I915_WRITE(reg, dpll);
1572         POSTING_READ(reg);
1573         udelay(150);
1574
1575         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1577
1578         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1579         POSTING_READ(DPLL_MD(crtc->pipe));
1580
1581         /* We do this three times for luck */
1582         I915_WRITE(reg, dpll);
1583         POSTING_READ(reg);
1584         udelay(150); /* wait for warmup */
1585         I915_WRITE(reg, dpll);
1586         POSTING_READ(reg);
1587         udelay(150); /* wait for warmup */
1588         I915_WRITE(reg, dpll);
1589         POSTING_READ(reg);
1590         udelay(150); /* wait for warmup */
1591 }
1592
1593 static void chv_enable_pll(struct intel_crtc *crtc,
1594                            const struct intel_crtc_state *pipe_config)
1595 {
1596         struct drm_device *dev = crtc->base.dev;
1597         struct drm_i915_private *dev_priv = dev->dev_private;
1598         int pipe = crtc->pipe;
1599         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1600         u32 tmp;
1601
1602         assert_pipe_disabled(dev_priv, crtc->pipe);
1603
1604         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1605
1606         mutex_lock(&dev_priv->dpio_lock);
1607
1608         /* Enable back the 10bit clock to display controller */
1609         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610         tmp |= DPIO_DCLKP_EN;
1611         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1612
1613         /*
1614          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1615          */
1616         udelay(1);
1617
1618         /* Enable PLL */
1619         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1620
1621         /* Check PLL is locked */
1622         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1623                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1624
1625         /* not sure when this should be written */
1626         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1627         POSTING_READ(DPLL_MD(pipe));
1628
1629         mutex_unlock(&dev_priv->dpio_lock);
1630 }
1631
1632 static int intel_num_dvo_pipes(struct drm_device *dev)
1633 {
1634         struct intel_crtc *crtc;
1635         int count = 0;
1636
1637         for_each_intel_crtc(dev, crtc)
1638                 count += crtc->active &&
1639                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1640
1641         return count;
1642 }
1643
1644 static void i9xx_enable_pll(struct intel_crtc *crtc)
1645 {
1646         struct drm_device *dev = crtc->base.dev;
1647         struct drm_i915_private *dev_priv = dev->dev_private;
1648         int reg = DPLL(crtc->pipe);
1649         u32 dpll = crtc->config->dpll_hw_state.dpll;
1650
1651         assert_pipe_disabled(dev_priv, crtc->pipe);
1652
1653         /* No really, not for ILK+ */
1654         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1655
1656         /* PLL is protected by panel, make sure we can write it */
1657         if (IS_MOBILE(dev) && !IS_I830(dev))
1658                 assert_panel_unlocked(dev_priv, crtc->pipe);
1659
1660         /* Enable DVO 2x clock on both PLLs if necessary */
1661         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1662                 /*
1663                  * It appears to be important that we don't enable this
1664                  * for the current pipe before otherwise configuring the
1665                  * PLL. No idea how this should be handled if multiple
1666                  * DVO outputs are enabled simultaneosly.
1667                  */
1668                 dpll |= DPLL_DVO_2X_MODE;
1669                 I915_WRITE(DPLL(!crtc->pipe),
1670                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1671         }
1672
1673         /* Wait for the clocks to stabilize. */
1674         POSTING_READ(reg);
1675         udelay(150);
1676
1677         if (INTEL_INFO(dev)->gen >= 4) {
1678                 I915_WRITE(DPLL_MD(crtc->pipe),
1679                            crtc->config->dpll_hw_state.dpll_md);
1680         } else {
1681                 /* The pixel multiplier can only be updated once the
1682                  * DPLL is enabled and the clocks are stable.
1683                  *
1684                  * So write it again.
1685                  */
1686                 I915_WRITE(reg, dpll);
1687         }
1688
1689         /* We do this three times for luck */
1690         I915_WRITE(reg, dpll);
1691         POSTING_READ(reg);
1692         udelay(150); /* wait for warmup */
1693         I915_WRITE(reg, dpll);
1694         POSTING_READ(reg);
1695         udelay(150); /* wait for warmup */
1696         I915_WRITE(reg, dpll);
1697         POSTING_READ(reg);
1698         udelay(150); /* wait for warmup */
1699 }
1700
1701 /**
1702  * i9xx_disable_pll - disable a PLL
1703  * @dev_priv: i915 private structure
1704  * @pipe: pipe PLL to disable
1705  *
1706  * Disable the PLL for @pipe, making sure the pipe is off first.
1707  *
1708  * Note!  This is for pre-ILK only.
1709  */
1710 static void i9xx_disable_pll(struct intel_crtc *crtc)
1711 {
1712         struct drm_device *dev = crtc->base.dev;
1713         struct drm_i915_private *dev_priv = dev->dev_private;
1714         enum pipe pipe = crtc->pipe;
1715
1716         /* Disable DVO 2x clock on both PLLs if necessary */
1717         if (IS_I830(dev) &&
1718             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1719             intel_num_dvo_pipes(dev) == 1) {
1720                 I915_WRITE(DPLL(PIPE_B),
1721                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1722                 I915_WRITE(DPLL(PIPE_A),
1723                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1724         }
1725
1726         /* Don't disable pipe or pipe PLLs if needed */
1727         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1728             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1729                 return;
1730
1731         /* Make sure the pipe isn't still relying on us */
1732         assert_pipe_disabled(dev_priv, pipe);
1733
1734         I915_WRITE(DPLL(pipe), 0);
1735         POSTING_READ(DPLL(pipe));
1736 }
1737
1738 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1739 {
1740         u32 val = 0;
1741
1742         /* Make sure the pipe isn't still relying on us */
1743         assert_pipe_disabled(dev_priv, pipe);
1744
1745         /*
1746          * Leave integrated clock source and reference clock enabled for pipe B.
1747          * The latter is needed for VGA hotplug / manual detection.
1748          */
1749         if (pipe == PIPE_B)
1750                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1751         I915_WRITE(DPLL(pipe), val);
1752         POSTING_READ(DPLL(pipe));
1753
1754 }
1755
1756 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1757 {
1758         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1759         u32 val;
1760
1761         /* Make sure the pipe isn't still relying on us */
1762         assert_pipe_disabled(dev_priv, pipe);
1763
1764         /* Set PLL en = 0 */
1765         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1766         if (pipe != PIPE_A)
1767                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1768         I915_WRITE(DPLL(pipe), val);
1769         POSTING_READ(DPLL(pipe));
1770
1771         mutex_lock(&dev_priv->dpio_lock);
1772
1773         /* Disable 10bit clock to display controller */
1774         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1775         val &= ~DPIO_DCLKP_EN;
1776         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1777
1778         /* disable left/right clock distribution */
1779         if (pipe != PIPE_B) {
1780                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1781                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1782                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1783         } else {
1784                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1785                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1786                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1787         }
1788
1789         mutex_unlock(&dev_priv->dpio_lock);
1790 }
1791
1792 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1793                 struct intel_digital_port *dport)
1794 {
1795         u32 port_mask;
1796         int dpll_reg;
1797
1798         switch (dport->port) {
1799         case PORT_B:
1800                 port_mask = DPLL_PORTB_READY_MASK;
1801                 dpll_reg = DPLL(0);
1802                 break;
1803         case PORT_C:
1804                 port_mask = DPLL_PORTC_READY_MASK;
1805                 dpll_reg = DPLL(0);
1806                 break;
1807         case PORT_D:
1808                 port_mask = DPLL_PORTD_READY_MASK;
1809                 dpll_reg = DPIO_PHY_STATUS;
1810                 break;
1811         default:
1812                 BUG();
1813         }
1814
1815         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1816                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1817                      port_name(dport->port), I915_READ(dpll_reg));
1818 }
1819
1820 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1821 {
1822         struct drm_device *dev = crtc->base.dev;
1823         struct drm_i915_private *dev_priv = dev->dev_private;
1824         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1825
1826         if (WARN_ON(pll == NULL))
1827                 return;
1828
1829         WARN_ON(!pll->config.crtc_mask);
1830         if (pll->active == 0) {
1831                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1832                 WARN_ON(pll->on);
1833                 assert_shared_dpll_disabled(dev_priv, pll);
1834
1835                 pll->mode_set(dev_priv, pll);
1836         }
1837 }
1838
1839 /**
1840  * intel_enable_shared_dpll - enable PCH PLL
1841  * @dev_priv: i915 private structure
1842  * @pipe: pipe PLL to enable
1843  *
1844  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1845  * drives the transcoder clock.
1846  */
1847 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1848 {
1849         struct drm_device *dev = crtc->base.dev;
1850         struct drm_i915_private *dev_priv = dev->dev_private;
1851         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1852
1853         if (WARN_ON(pll == NULL))
1854                 return;
1855
1856         if (WARN_ON(pll->config.crtc_mask == 0))
1857                 return;
1858
1859         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1860                       pll->name, pll->active, pll->on,
1861                       crtc->base.base.id);
1862
1863         if (pll->active++) {
1864                 WARN_ON(!pll->on);
1865                 assert_shared_dpll_enabled(dev_priv, pll);
1866                 return;
1867         }
1868         WARN_ON(pll->on);
1869
1870         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1871
1872         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1873         pll->enable(dev_priv, pll);
1874         pll->on = true;
1875 }
1876
1877 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1878 {
1879         struct drm_device *dev = crtc->base.dev;
1880         struct drm_i915_private *dev_priv = dev->dev_private;
1881         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1882
1883         /* PCH only available on ILK+ */
1884         BUG_ON(INTEL_INFO(dev)->gen < 5);
1885         if (WARN_ON(pll == NULL))
1886                return;
1887
1888         if (WARN_ON(pll->config.crtc_mask == 0))
1889                 return;
1890
1891         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1892                       pll->name, pll->active, pll->on,
1893                       crtc->base.base.id);
1894
1895         if (WARN_ON(pll->active == 0)) {
1896                 assert_shared_dpll_disabled(dev_priv, pll);
1897                 return;
1898         }
1899
1900         assert_shared_dpll_enabled(dev_priv, pll);
1901         WARN_ON(!pll->on);
1902         if (--pll->active)
1903                 return;
1904
1905         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1906         pll->disable(dev_priv, pll);
1907         pll->on = false;
1908
1909         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1910 }
1911
1912 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1913                                            enum pipe pipe)
1914 {
1915         struct drm_device *dev = dev_priv->dev;
1916         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1918         uint32_t reg, val, pipeconf_val;
1919
1920         /* PCH only available on ILK+ */
1921         BUG_ON(!HAS_PCH_SPLIT(dev));
1922
1923         /* Make sure PCH DPLL is enabled */
1924         assert_shared_dpll_enabled(dev_priv,
1925                                    intel_crtc_to_shared_dpll(intel_crtc));
1926
1927         /* FDI must be feeding us bits for PCH ports */
1928         assert_fdi_tx_enabled(dev_priv, pipe);
1929         assert_fdi_rx_enabled(dev_priv, pipe);
1930
1931         if (HAS_PCH_CPT(dev)) {
1932                 /* Workaround: Set the timing override bit before enabling the
1933                  * pch transcoder. */
1934                 reg = TRANS_CHICKEN2(pipe);
1935                 val = I915_READ(reg);
1936                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1937                 I915_WRITE(reg, val);
1938         }
1939
1940         reg = PCH_TRANSCONF(pipe);
1941         val = I915_READ(reg);
1942         pipeconf_val = I915_READ(PIPECONF(pipe));
1943
1944         if (HAS_PCH_IBX(dev_priv->dev)) {
1945                 /*
1946                  * make the BPC in transcoder be consistent with
1947                  * that in pipeconf reg.
1948                  */
1949                 val &= ~PIPECONF_BPC_MASK;
1950                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1951         }
1952
1953         val &= ~TRANS_INTERLACE_MASK;
1954         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1955                 if (HAS_PCH_IBX(dev_priv->dev) &&
1956                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1957                         val |= TRANS_LEGACY_INTERLACED_ILK;
1958                 else
1959                         val |= TRANS_INTERLACED;
1960         else
1961                 val |= TRANS_PROGRESSIVE;
1962
1963         I915_WRITE(reg, val | TRANS_ENABLE);
1964         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1965                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1966 }
1967
1968 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969                                       enum transcoder cpu_transcoder)
1970 {
1971         u32 val, pipeconf_val;
1972
1973         /* PCH only available on ILK+ */
1974         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1975
1976         /* FDI must be feeding us bits for PCH ports */
1977         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1978         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1979
1980         /* Workaround: set timing override bit. */
1981         val = I915_READ(_TRANSA_CHICKEN2);
1982         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1983         I915_WRITE(_TRANSA_CHICKEN2, val);
1984
1985         val = TRANS_ENABLE;
1986         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1987
1988         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1989             PIPECONF_INTERLACED_ILK)
1990                 val |= TRANS_INTERLACED;
1991         else
1992                 val |= TRANS_PROGRESSIVE;
1993
1994         I915_WRITE(LPT_TRANSCONF, val);
1995         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1996                 DRM_ERROR("Failed to enable PCH transcoder\n");
1997 }
1998
1999 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2000                                             enum pipe pipe)
2001 {
2002         struct drm_device *dev = dev_priv->dev;
2003         uint32_t reg, val;
2004
2005         /* FDI relies on the transcoder */
2006         assert_fdi_tx_disabled(dev_priv, pipe);
2007         assert_fdi_rx_disabled(dev_priv, pipe);
2008
2009         /* Ports must be off as well */
2010         assert_pch_ports_disabled(dev_priv, pipe);
2011
2012         reg = PCH_TRANSCONF(pipe);
2013         val = I915_READ(reg);
2014         val &= ~TRANS_ENABLE;
2015         I915_WRITE(reg, val);
2016         /* wait for PCH transcoder off, transcoder state */
2017         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2018                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2019
2020         if (!HAS_PCH_IBX(dev)) {
2021                 /* Workaround: Clear the timing override chicken bit again. */
2022                 reg = TRANS_CHICKEN2(pipe);
2023                 val = I915_READ(reg);
2024                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2025                 I915_WRITE(reg, val);
2026         }
2027 }
2028
2029 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2030 {
2031         u32 val;
2032
2033         val = I915_READ(LPT_TRANSCONF);
2034         val &= ~TRANS_ENABLE;
2035         I915_WRITE(LPT_TRANSCONF, val);
2036         /* wait for PCH transcoder off, transcoder state */
2037         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2038                 DRM_ERROR("Failed to disable PCH transcoder\n");
2039
2040         /* Workaround: clear timing override bit. */
2041         val = I915_READ(_TRANSA_CHICKEN2);
2042         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2043         I915_WRITE(_TRANSA_CHICKEN2, val);
2044 }
2045
2046 /**
2047  * intel_enable_pipe - enable a pipe, asserting requirements
2048  * @crtc: crtc responsible for the pipe
2049  *
2050  * Enable @crtc's pipe, making sure that various hardware specific requirements
2051  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2052  */
2053 static void intel_enable_pipe(struct intel_crtc *crtc)
2054 {
2055         struct drm_device *dev = crtc->base.dev;
2056         struct drm_i915_private *dev_priv = dev->dev_private;
2057         enum pipe pipe = crtc->pipe;
2058         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2059                                                                       pipe);
2060         enum pipe pch_transcoder;
2061         int reg;
2062         u32 val;
2063
2064         assert_planes_disabled(dev_priv, pipe);
2065         assert_cursor_disabled(dev_priv, pipe);
2066         assert_sprites_disabled(dev_priv, pipe);
2067
2068         if (HAS_PCH_LPT(dev_priv->dev))
2069                 pch_transcoder = TRANSCODER_A;
2070         else
2071                 pch_transcoder = pipe;
2072
2073         /*
2074          * A pipe without a PLL won't actually be able to drive bits from
2075          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2076          * need the check.
2077          */
2078         if (!HAS_PCH_SPLIT(dev_priv->dev))
2079                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2080                         assert_dsi_pll_enabled(dev_priv);
2081                 else
2082                         assert_pll_enabled(dev_priv, pipe);
2083         else {
2084                 if (crtc->config->has_pch_encoder) {
2085                         /* if driving the PCH, we need FDI enabled */
2086                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2087                         assert_fdi_tx_pll_enabled(dev_priv,
2088                                                   (enum pipe) cpu_transcoder);
2089                 }
2090                 /* FIXME: assert CPU port conditions for SNB+ */
2091         }
2092
2093         reg = PIPECONF(cpu_transcoder);
2094         val = I915_READ(reg);
2095         if (val & PIPECONF_ENABLE) {
2096                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2097                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2098                 return;
2099         }
2100
2101         I915_WRITE(reg, val | PIPECONF_ENABLE);
2102         POSTING_READ(reg);
2103 }
2104
2105 /**
2106  * intel_disable_pipe - disable a pipe, asserting requirements
2107  * @crtc: crtc whose pipes is to be disabled
2108  *
2109  * Disable the pipe of @crtc, making sure that various hardware
2110  * specific requirements are met, if applicable, e.g. plane
2111  * disabled, panel fitter off, etc.
2112  *
2113  * Will wait until the pipe has shut down before returning.
2114  */
2115 static void intel_disable_pipe(struct intel_crtc *crtc)
2116 {
2117         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2118         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2119         enum pipe pipe = crtc->pipe;
2120         int reg;
2121         u32 val;
2122
2123         /*
2124          * Make sure planes won't keep trying to pump pixels to us,
2125          * or we might hang the display.
2126          */
2127         assert_planes_disabled(dev_priv, pipe);
2128         assert_cursor_disabled(dev_priv, pipe);
2129         assert_sprites_disabled(dev_priv, pipe);
2130
2131         reg = PIPECONF(cpu_transcoder);
2132         val = I915_READ(reg);
2133         if ((val & PIPECONF_ENABLE) == 0)
2134                 return;
2135
2136         /*
2137          * Double wide has implications for planes
2138          * so best keep it disabled when not needed.
2139          */
2140         if (crtc->config->double_wide)
2141                 val &= ~PIPECONF_DOUBLE_WIDE;
2142
2143         /* Don't disable pipe or pipe PLLs if needed */
2144         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2145             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2146                 val &= ~PIPECONF_ENABLE;
2147
2148         I915_WRITE(reg, val);
2149         if ((val & PIPECONF_ENABLE) == 0)
2150                 intel_wait_for_pipe_off(crtc);
2151 }
2152
2153 /*
2154  * Plane regs are double buffered, going from enabled->disabled needs a
2155  * trigger in order to latch.  The display address reg provides this.
2156  */
2157 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2158                                enum plane plane)
2159 {
2160         struct drm_device *dev = dev_priv->dev;
2161         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2162
2163         I915_WRITE(reg, I915_READ(reg));
2164         POSTING_READ(reg);
2165 }
2166
2167 /**
2168  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2169  * @plane:  plane to be enabled
2170  * @crtc: crtc for the plane
2171  *
2172  * Enable @plane on @crtc, making sure that the pipe is running first.
2173  */
2174 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2175                                           struct drm_crtc *crtc)
2176 {
2177         struct drm_device *dev = plane->dev;
2178         struct drm_i915_private *dev_priv = dev->dev_private;
2179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180
2181         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2182         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2183
2184         if (intel_crtc->primary_enabled)
2185                 return;
2186
2187         intel_crtc->primary_enabled = true;
2188
2189         dev_priv->display.update_primary_plane(crtc, plane->fb,
2190                                                crtc->x, crtc->y);
2191
2192         /*
2193          * BDW signals flip done immediately if the plane
2194          * is disabled, even if the plane enable is already
2195          * armed to occur at the next vblank :(
2196          */
2197         if (IS_BROADWELL(dev))
2198                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2199 }
2200
2201 /**
2202  * intel_disable_primary_hw_plane - disable the primary hardware plane
2203  * @plane: plane to be disabled
2204  * @crtc: crtc for the plane
2205  *
2206  * Disable @plane on @crtc, making sure that the pipe is running first.
2207  */
2208 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2209                                            struct drm_crtc *crtc)
2210 {
2211         struct drm_device *dev = plane->dev;
2212         struct drm_i915_private *dev_priv = dev->dev_private;
2213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214
2215         if (WARN_ON(!intel_crtc->active))
2216                 return;
2217
2218         if (!intel_crtc->primary_enabled)
2219                 return;
2220
2221         intel_crtc->primary_enabled = false;
2222
2223         dev_priv->display.update_primary_plane(crtc, plane->fb,
2224                                                crtc->x, crtc->y);
2225 }
2226
2227 static bool need_vtd_wa(struct drm_device *dev)
2228 {
2229 #ifdef CONFIG_INTEL_IOMMU
2230         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2231                 return true;
2232 #endif
2233         return false;
2234 }
2235
2236 unsigned int
2237 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2238                   uint64_t fb_format_modifier)
2239 {
2240         unsigned int tile_height;
2241         uint32_t pixel_bytes;
2242
2243         switch (fb_format_modifier) {
2244         case DRM_FORMAT_MOD_NONE:
2245                 tile_height = 1;
2246                 break;
2247         case I915_FORMAT_MOD_X_TILED:
2248                 tile_height = IS_GEN2(dev) ? 16 : 8;
2249                 break;
2250         case I915_FORMAT_MOD_Y_TILED:
2251                 tile_height = 32;
2252                 break;
2253         case I915_FORMAT_MOD_Yf_TILED:
2254                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2255                 switch (pixel_bytes) {
2256                 default:
2257                 case 1:
2258                         tile_height = 64;
2259                         break;
2260                 case 2:
2261                 case 4:
2262                         tile_height = 32;
2263                         break;
2264                 case 8:
2265                         tile_height = 16;
2266                         break;
2267                 case 16:
2268                         WARN_ONCE(1,
2269                                   "128-bit pixels are not supported for display!");
2270                         tile_height = 16;
2271                         break;
2272                 }
2273                 break;
2274         default:
2275                 MISSING_CASE(fb_format_modifier);
2276                 tile_height = 1;
2277                 break;
2278         }
2279
2280         return tile_height;
2281 }
2282
2283 unsigned int
2284 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2285                       uint32_t pixel_format, uint64_t fb_format_modifier)
2286 {
2287         return ALIGN(height, intel_tile_height(dev, pixel_format,
2288                                                fb_format_modifier));
2289 }
2290
2291 static int
2292 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2293                         const struct drm_plane_state *plane_state)
2294 {
2295         struct intel_rotation_info *info = &view->rotation_info;
2296         static const struct i915_ggtt_view rotated_view =
2297                                 { .type = I915_GGTT_VIEW_ROTATED };
2298
2299         *view = i915_ggtt_view_normal;
2300
2301         if (!plane_state)
2302                 return 0;
2303
2304         if (!intel_rotation_90_or_270(plane_state->rotation))
2305                 return 0;
2306
2307         *view = rotated_view;
2308
2309         info->height = fb->height;
2310         info->pixel_format = fb->pixel_format;
2311         info->pitch = fb->pitches[0];
2312         info->fb_modifier = fb->modifier[0];
2313
2314         if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2315               info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2316                 DRM_DEBUG_KMS(
2317                               "Y or Yf tiling is needed for 90/270 rotation!\n");
2318                 return -EINVAL;
2319         }
2320
2321         return 0;
2322 }
2323
2324 int
2325 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2326                            struct drm_framebuffer *fb,
2327                            const struct drm_plane_state *plane_state,
2328                            struct intel_engine_cs *pipelined)
2329 {
2330         struct drm_device *dev = fb->dev;
2331         struct drm_i915_private *dev_priv = dev->dev_private;
2332         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2333         struct i915_ggtt_view view;
2334         u32 alignment;
2335         int ret;
2336
2337         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2338
2339         switch (fb->modifier[0]) {
2340         case DRM_FORMAT_MOD_NONE:
2341                 if (INTEL_INFO(dev)->gen >= 9)
2342                         alignment = 256 * 1024;
2343                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2344                         alignment = 128 * 1024;
2345                 else if (INTEL_INFO(dev)->gen >= 4)
2346                         alignment = 4 * 1024;
2347                 else
2348                         alignment = 64 * 1024;
2349                 break;
2350         case I915_FORMAT_MOD_X_TILED:
2351                 if (INTEL_INFO(dev)->gen >= 9)
2352                         alignment = 256 * 1024;
2353                 else {
2354                         /* pin() will align the object as required by fence */
2355                         alignment = 0;
2356                 }
2357                 break;
2358         case I915_FORMAT_MOD_Y_TILED:
2359         case I915_FORMAT_MOD_Yf_TILED:
2360                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2361                           "Y tiling bo slipped through, driver bug!\n"))
2362                         return -EINVAL;
2363                 alignment = 1 * 1024 * 1024;
2364                 break;
2365         default:
2366                 MISSING_CASE(fb->modifier[0]);
2367                 return -EINVAL;
2368         }
2369
2370         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2371         if (ret)
2372                 return ret;
2373
2374         /* Note that the w/a also requires 64 PTE of padding following the
2375          * bo. We currently fill all unused PTE with the shadow page and so
2376          * we should always have valid PTE following the scanout preventing
2377          * the VT-d warning.
2378          */
2379         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2380                 alignment = 256 * 1024;
2381
2382         /*
2383          * Global gtt pte registers are special registers which actually forward
2384          * writes to a chunk of system memory. Which means that there is no risk
2385          * that the register values disappear as soon as we call
2386          * intel_runtime_pm_put(), so it is correct to wrap only the
2387          * pin/unpin/fence and not more.
2388          */
2389         intel_runtime_pm_get(dev_priv);
2390
2391         dev_priv->mm.interruptible = false;
2392         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2393                                                    &view);
2394         if (ret)
2395                 goto err_interruptible;
2396
2397         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2398          * fence, whereas 965+ only requires a fence if using
2399          * framebuffer compression.  For simplicity, we always install
2400          * a fence as the cost is not that onerous.
2401          */
2402         ret = i915_gem_object_get_fence(obj);
2403         if (ret)
2404                 goto err_unpin;
2405
2406         i915_gem_object_pin_fence(obj);
2407
2408         dev_priv->mm.interruptible = true;
2409         intel_runtime_pm_put(dev_priv);
2410         return 0;
2411
2412 err_unpin:
2413         i915_gem_object_unpin_from_display_plane(obj, &view);
2414 err_interruptible:
2415         dev_priv->mm.interruptible = true;
2416         intel_runtime_pm_put(dev_priv);
2417         return ret;
2418 }
2419
2420 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2421                                const struct drm_plane_state *plane_state)
2422 {
2423         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2424         struct i915_ggtt_view view;
2425         int ret;
2426
2427         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2428
2429         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2430         WARN_ONCE(ret, "Couldn't get view from plane state!");
2431
2432         i915_gem_object_unpin_fence(obj);
2433         i915_gem_object_unpin_from_display_plane(obj, &view);
2434 }
2435
2436 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2437  * is assumed to be a power-of-two. */
2438 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2439                                              unsigned int tiling_mode,
2440                                              unsigned int cpp,
2441                                              unsigned int pitch)
2442 {
2443         if (tiling_mode != I915_TILING_NONE) {
2444                 unsigned int tile_rows, tiles;
2445
2446                 tile_rows = *y / 8;
2447                 *y %= 8;
2448
2449                 tiles = *x / (512/cpp);
2450                 *x %= 512/cpp;
2451
2452                 return tile_rows * pitch * 8 + tiles * 4096;
2453         } else {
2454                 unsigned int offset;
2455
2456                 offset = *y * pitch + *x * cpp;
2457                 *y = 0;
2458                 *x = (offset & 4095) / cpp;
2459                 return offset & -4096;
2460         }
2461 }
2462
2463 static int i9xx_format_to_fourcc(int format)
2464 {
2465         switch (format) {
2466         case DISPPLANE_8BPP:
2467                 return DRM_FORMAT_C8;
2468         case DISPPLANE_BGRX555:
2469                 return DRM_FORMAT_XRGB1555;
2470         case DISPPLANE_BGRX565:
2471                 return DRM_FORMAT_RGB565;
2472         default:
2473         case DISPPLANE_BGRX888:
2474                 return DRM_FORMAT_XRGB8888;
2475         case DISPPLANE_RGBX888:
2476                 return DRM_FORMAT_XBGR8888;
2477         case DISPPLANE_BGRX101010:
2478                 return DRM_FORMAT_XRGB2101010;
2479         case DISPPLANE_RGBX101010:
2480                 return DRM_FORMAT_XBGR2101010;
2481         }
2482 }
2483
2484 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2485 {
2486         switch (format) {
2487         case PLANE_CTL_FORMAT_RGB_565:
2488                 return DRM_FORMAT_RGB565;
2489         default:
2490         case PLANE_CTL_FORMAT_XRGB_8888:
2491                 if (rgb_order) {
2492                         if (alpha)
2493                                 return DRM_FORMAT_ABGR8888;
2494                         else
2495                                 return DRM_FORMAT_XBGR8888;
2496                 } else {
2497                         if (alpha)
2498                                 return DRM_FORMAT_ARGB8888;
2499                         else
2500                                 return DRM_FORMAT_XRGB8888;
2501                 }
2502         case PLANE_CTL_FORMAT_XRGB_2101010:
2503                 if (rgb_order)
2504                         return DRM_FORMAT_XBGR2101010;
2505                 else
2506                         return DRM_FORMAT_XRGB2101010;
2507         }
2508 }
2509
2510 static bool
2511 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2512                               struct intel_initial_plane_config *plane_config)
2513 {
2514         struct drm_device *dev = crtc->base.dev;
2515         struct drm_i915_gem_object *obj = NULL;
2516         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2517         struct drm_framebuffer *fb = &plane_config->fb->base;
2518         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2519         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2520                                     PAGE_SIZE);
2521
2522         size_aligned -= base_aligned;
2523
2524         if (plane_config->size == 0)
2525                 return false;
2526
2527         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2528                                                              base_aligned,
2529                                                              base_aligned,
2530                                                              size_aligned);
2531         if (!obj)
2532                 return false;
2533
2534         obj->tiling_mode = plane_config->tiling;
2535         if (obj->tiling_mode == I915_TILING_X)
2536                 obj->stride = fb->pitches[0];
2537
2538         mode_cmd.pixel_format = fb->pixel_format;
2539         mode_cmd.width = fb->width;
2540         mode_cmd.height = fb->height;
2541         mode_cmd.pitches[0] = fb->pitches[0];
2542         mode_cmd.modifier[0] = fb->modifier[0];
2543         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2544
2545         mutex_lock(&dev->struct_mutex);
2546         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2547                                    &mode_cmd, obj)) {
2548                 DRM_DEBUG_KMS("intel fb init failed\n");
2549                 goto out_unref_obj;
2550         }
2551         mutex_unlock(&dev->struct_mutex);
2552
2553         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2554         return true;
2555
2556 out_unref_obj:
2557         drm_gem_object_unreference(&obj->base);
2558         mutex_unlock(&dev->struct_mutex);
2559         return false;
2560 }
2561
2562 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2563 static void
2564 update_state_fb(struct drm_plane *plane)
2565 {
2566         if (plane->fb == plane->state->fb)
2567                 return;
2568
2569         if (plane->state->fb)
2570                 drm_framebuffer_unreference(plane->state->fb);
2571         plane->state->fb = plane->fb;
2572         if (plane->state->fb)
2573                 drm_framebuffer_reference(plane->state->fb);
2574 }
2575
2576 static void
2577 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2578                              struct intel_initial_plane_config *plane_config)
2579 {
2580         struct drm_device *dev = intel_crtc->base.dev;
2581         struct drm_i915_private *dev_priv = dev->dev_private;
2582         struct drm_crtc *c;
2583         struct intel_crtc *i;
2584         struct drm_i915_gem_object *obj;
2585         struct drm_plane *primary = intel_crtc->base.primary;
2586         struct drm_framebuffer *fb;
2587
2588         if (!plane_config->fb)
2589                 return;
2590
2591         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2592                 fb = &plane_config->fb->base;
2593                 goto valid_fb;
2594         }
2595
2596         kfree(plane_config->fb);
2597
2598         /*
2599          * Failed to alloc the obj, check to see if we should share
2600          * an fb with another CRTC instead
2601          */
2602         for_each_crtc(dev, c) {
2603                 i = to_intel_crtc(c);
2604
2605                 if (c == &intel_crtc->base)
2606                         continue;
2607
2608                 if (!i->active)
2609                         continue;
2610
2611                 fb = c->primary->fb;
2612                 if (!fb)
2613                         continue;
2614
2615                 obj = intel_fb_obj(fb);
2616                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2617                         drm_framebuffer_reference(fb);
2618                         goto valid_fb;
2619                 }
2620         }
2621
2622         return;
2623
2624 valid_fb:
2625         obj = intel_fb_obj(fb);
2626         if (obj->tiling_mode != I915_TILING_NONE)
2627                 dev_priv->preserve_bios_swizzle = true;
2628
2629         primary->fb = fb;
2630         primary->state->crtc = &intel_crtc->base;
2631         primary->crtc = &intel_crtc->base;
2632         update_state_fb(primary);
2633         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2634 }
2635
2636 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2637                                       struct drm_framebuffer *fb,
2638                                       int x, int y)
2639 {
2640         struct drm_device *dev = crtc->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643         struct drm_i915_gem_object *obj;
2644         int plane = intel_crtc->plane;
2645         unsigned long linear_offset;
2646         u32 dspcntr;
2647         u32 reg = DSPCNTR(plane);
2648         int pixel_size;
2649
2650         if (!intel_crtc->primary_enabled) {
2651                 I915_WRITE(reg, 0);
2652                 if (INTEL_INFO(dev)->gen >= 4)
2653                         I915_WRITE(DSPSURF(plane), 0);
2654                 else
2655                         I915_WRITE(DSPADDR(plane), 0);
2656                 POSTING_READ(reg);
2657                 return;
2658         }
2659
2660         obj = intel_fb_obj(fb);
2661         if (WARN_ON(obj == NULL))
2662                 return;
2663
2664         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2665
2666         dspcntr = DISPPLANE_GAMMA_ENABLE;
2667
2668         dspcntr |= DISPLAY_PLANE_ENABLE;
2669
2670         if (INTEL_INFO(dev)->gen < 4) {
2671                 if (intel_crtc->pipe == PIPE_B)
2672                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2673
2674                 /* pipesrc and dspsize control the size that is scaled from,
2675                  * which should always be the user's requested size.
2676                  */
2677                 I915_WRITE(DSPSIZE(plane),
2678                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2679                            (intel_crtc->config->pipe_src_w - 1));
2680                 I915_WRITE(DSPPOS(plane), 0);
2681         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2682                 I915_WRITE(PRIMSIZE(plane),
2683                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2684                            (intel_crtc->config->pipe_src_w - 1));
2685                 I915_WRITE(PRIMPOS(plane), 0);
2686                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2687         }
2688
2689         switch (fb->pixel_format) {
2690         case DRM_FORMAT_C8:
2691                 dspcntr |= DISPPLANE_8BPP;
2692                 break;
2693         case DRM_FORMAT_XRGB1555:
2694         case DRM_FORMAT_ARGB1555:
2695                 dspcntr |= DISPPLANE_BGRX555;
2696                 break;
2697         case DRM_FORMAT_RGB565:
2698                 dspcntr |= DISPPLANE_BGRX565;
2699                 break;
2700         case DRM_FORMAT_XRGB8888:
2701         case DRM_FORMAT_ARGB8888:
2702                 dspcntr |= DISPPLANE_BGRX888;
2703                 break;
2704         case DRM_FORMAT_XBGR8888:
2705         case DRM_FORMAT_ABGR8888:
2706                 dspcntr |= DISPPLANE_RGBX888;
2707                 break;
2708         case DRM_FORMAT_XRGB2101010:
2709         case DRM_FORMAT_ARGB2101010:
2710                 dspcntr |= DISPPLANE_BGRX101010;
2711                 break;
2712         case DRM_FORMAT_XBGR2101010:
2713         case DRM_FORMAT_ABGR2101010:
2714                 dspcntr |= DISPPLANE_RGBX101010;
2715                 break;
2716         default:
2717                 BUG();
2718         }
2719
2720         if (INTEL_INFO(dev)->gen >= 4 &&
2721             obj->tiling_mode != I915_TILING_NONE)
2722                 dspcntr |= DISPPLANE_TILED;
2723
2724         if (IS_G4X(dev))
2725                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2726
2727         linear_offset = y * fb->pitches[0] + x * pixel_size;
2728
2729         if (INTEL_INFO(dev)->gen >= 4) {
2730                 intel_crtc->dspaddr_offset =
2731                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2732                                                        pixel_size,
2733                                                        fb->pitches[0]);
2734                 linear_offset -= intel_crtc->dspaddr_offset;
2735         } else {
2736                 intel_crtc->dspaddr_offset = linear_offset;
2737         }
2738
2739         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2740                 dspcntr |= DISPPLANE_ROTATE_180;
2741
2742                 x += (intel_crtc->config->pipe_src_w - 1);
2743                 y += (intel_crtc->config->pipe_src_h - 1);
2744
2745                 /* Finding the last pixel of the last line of the display
2746                 data and adding to linear_offset*/
2747                 linear_offset +=
2748                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2749                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2750         }
2751
2752         I915_WRITE(reg, dspcntr);
2753
2754         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2755         if (INTEL_INFO(dev)->gen >= 4) {
2756                 I915_WRITE(DSPSURF(plane),
2757                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2758                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2759                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2760         } else
2761                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2762         POSTING_READ(reg);
2763 }
2764
2765 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2766                                           struct drm_framebuffer *fb,
2767                                           int x, int y)
2768 {
2769         struct drm_device *dev = crtc->dev;
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2772         struct drm_i915_gem_object *obj;
2773         int plane = intel_crtc->plane;
2774         unsigned long linear_offset;
2775         u32 dspcntr;
2776         u32 reg = DSPCNTR(plane);
2777         int pixel_size;
2778
2779         if (!intel_crtc->primary_enabled) {
2780                 I915_WRITE(reg, 0);
2781                 I915_WRITE(DSPSURF(plane), 0);
2782                 POSTING_READ(reg);
2783                 return;
2784         }
2785
2786         obj = intel_fb_obj(fb);
2787         if (WARN_ON(obj == NULL))
2788                 return;
2789
2790         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2791
2792         dspcntr = DISPPLANE_GAMMA_ENABLE;
2793
2794         dspcntr |= DISPLAY_PLANE_ENABLE;
2795
2796         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2797                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2798
2799         switch (fb->pixel_format) {
2800         case DRM_FORMAT_C8:
2801                 dspcntr |= DISPPLANE_8BPP;
2802                 break;
2803         case DRM_FORMAT_RGB565:
2804                 dspcntr |= DISPPLANE_BGRX565;
2805                 break;
2806         case DRM_FORMAT_XRGB8888:
2807         case DRM_FORMAT_ARGB8888:
2808                 dspcntr |= DISPPLANE_BGRX888;
2809                 break;
2810         case DRM_FORMAT_XBGR8888:
2811         case DRM_FORMAT_ABGR8888:
2812                 dspcntr |= DISPPLANE_RGBX888;
2813                 break;
2814         case DRM_FORMAT_XRGB2101010:
2815         case DRM_FORMAT_ARGB2101010:
2816                 dspcntr |= DISPPLANE_BGRX101010;
2817                 break;
2818         case DRM_FORMAT_XBGR2101010:
2819         case DRM_FORMAT_ABGR2101010:
2820                 dspcntr |= DISPPLANE_RGBX101010;
2821                 break;
2822         default:
2823                 BUG();
2824         }
2825
2826         if (obj->tiling_mode != I915_TILING_NONE)
2827                 dspcntr |= DISPPLANE_TILED;
2828
2829         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2830                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2831
2832         linear_offset = y * fb->pitches[0] + x * pixel_size;
2833         intel_crtc->dspaddr_offset =
2834                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2835                                                pixel_size,
2836                                                fb->pitches[0]);
2837         linear_offset -= intel_crtc->dspaddr_offset;
2838         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2839                 dspcntr |= DISPPLANE_ROTATE_180;
2840
2841                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2842                         x += (intel_crtc->config->pipe_src_w - 1);
2843                         y += (intel_crtc->config->pipe_src_h - 1);
2844
2845                         /* Finding the last pixel of the last line of the display
2846                         data and adding to linear_offset*/
2847                         linear_offset +=
2848                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2849                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2850                 }
2851         }
2852
2853         I915_WRITE(reg, dspcntr);
2854
2855         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2856         I915_WRITE(DSPSURF(plane),
2857                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2858         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2859                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2860         } else {
2861                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2862                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2863         }
2864         POSTING_READ(reg);
2865 }
2866
2867 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2868                               uint32_t pixel_format)
2869 {
2870         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2871
2872         /*
2873          * The stride is either expressed as a multiple of 64 bytes
2874          * chunks for linear buffers or in number of tiles for tiled
2875          * buffers.
2876          */
2877         switch (fb_modifier) {
2878         case DRM_FORMAT_MOD_NONE:
2879                 return 64;
2880         case I915_FORMAT_MOD_X_TILED:
2881                 if (INTEL_INFO(dev)->gen == 2)
2882                         return 128;
2883                 return 512;
2884         case I915_FORMAT_MOD_Y_TILED:
2885                 /* No need to check for old gens and Y tiling since this is
2886                  * about the display engine and those will be blocked before
2887                  * we get here.
2888                  */
2889                 return 128;
2890         case I915_FORMAT_MOD_Yf_TILED:
2891                 if (bits_per_pixel == 8)
2892                         return 64;
2893                 else
2894                         return 128;
2895         default:
2896                 MISSING_CASE(fb_modifier);
2897                 return 64;
2898         }
2899 }
2900
2901 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2902                                      struct drm_i915_gem_object *obj)
2903 {
2904         enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
2905
2906         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2907                 view = I915_GGTT_VIEW_ROTATED;
2908
2909         return i915_gem_obj_ggtt_offset_view(obj, view);
2910 }
2911
2912 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2913                                          struct drm_framebuffer *fb,
2914                                          int x, int y)
2915 {
2916         struct drm_device *dev = crtc->dev;
2917         struct drm_i915_private *dev_priv = dev->dev_private;
2918         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2919         struct drm_i915_gem_object *obj;
2920         int pipe = intel_crtc->pipe;
2921         u32 plane_ctl, stride_div;
2922         unsigned long surf_addr;
2923
2924         if (!intel_crtc->primary_enabled) {
2925                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2926                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2927                 POSTING_READ(PLANE_CTL(pipe, 0));
2928                 return;
2929         }
2930
2931         plane_ctl = PLANE_CTL_ENABLE |
2932                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2933                     PLANE_CTL_PIPE_CSC_ENABLE;
2934
2935         switch (fb->pixel_format) {
2936         case DRM_FORMAT_RGB565:
2937                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2938                 break;
2939         case DRM_FORMAT_XRGB8888:
2940                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2941                 break;
2942         case DRM_FORMAT_ARGB8888:
2943                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2944                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2945                 break;
2946         case DRM_FORMAT_XBGR8888:
2947                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2948                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2949                 break;
2950         case DRM_FORMAT_ABGR8888:
2951                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2952                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2953                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2954                 break;
2955         case DRM_FORMAT_XRGB2101010:
2956                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2957                 break;
2958         case DRM_FORMAT_XBGR2101010:
2959                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2960                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2961                 break;
2962         default:
2963                 BUG();
2964         }
2965
2966         switch (fb->modifier[0]) {
2967         case DRM_FORMAT_MOD_NONE:
2968                 break;
2969         case I915_FORMAT_MOD_X_TILED:
2970                 plane_ctl |= PLANE_CTL_TILED_X;
2971                 break;
2972         case I915_FORMAT_MOD_Y_TILED:
2973                 plane_ctl |= PLANE_CTL_TILED_Y;
2974                 break;
2975         case I915_FORMAT_MOD_Yf_TILED:
2976                 plane_ctl |= PLANE_CTL_TILED_YF;
2977                 break;
2978         default:
2979                 MISSING_CASE(fb->modifier[0]);
2980         }
2981
2982         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2983         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2984                 plane_ctl |= PLANE_CTL_ROTATE_180;
2985
2986         obj = intel_fb_obj(fb);
2987         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2988                                                fb->pixel_format);
2989         surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
2990
2991         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2992         I915_WRITE(PLANE_POS(pipe, 0), 0);
2993         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2994         I915_WRITE(PLANE_SIZE(pipe, 0),
2995                    (intel_crtc->config->pipe_src_h - 1) << 16 |
2996                    (intel_crtc->config->pipe_src_w - 1));
2997         I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2998         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
2999
3000         POSTING_READ(PLANE_SURF(pipe, 0));
3001 }
3002
3003 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3004 static int
3005 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3006                            int x, int y, enum mode_set_atomic state)
3007 {
3008         struct drm_device *dev = crtc->dev;
3009         struct drm_i915_private *dev_priv = dev->dev_private;
3010
3011         if (dev_priv->display.disable_fbc)
3012                 dev_priv->display.disable_fbc(dev);
3013
3014         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3015
3016         return 0;
3017 }
3018
3019 static void intel_complete_page_flips(struct drm_device *dev)
3020 {
3021         struct drm_crtc *crtc;
3022
3023         for_each_crtc(dev, crtc) {
3024                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3025                 enum plane plane = intel_crtc->plane;
3026
3027                 intel_prepare_page_flip(dev, plane);
3028                 intel_finish_page_flip_plane(dev, plane);
3029         }
3030 }
3031
3032 static void intel_update_primary_planes(struct drm_device *dev)
3033 {
3034         struct drm_i915_private *dev_priv = dev->dev_private;
3035         struct drm_crtc *crtc;
3036
3037         for_each_crtc(dev, crtc) {
3038                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039
3040                 drm_modeset_lock(&crtc->mutex, NULL);
3041                 /*
3042                  * FIXME: Once we have proper support for primary planes (and
3043                  * disabling them without disabling the entire crtc) allow again
3044                  * a NULL crtc->primary->fb.
3045                  */
3046                 if (intel_crtc->active && crtc->primary->fb)
3047                         dev_priv->display.update_primary_plane(crtc,
3048                                                                crtc->primary->fb,
3049                                                                crtc->x,
3050                                                                crtc->y);
3051                 drm_modeset_unlock(&crtc->mutex);
3052         }
3053 }
3054
3055 void intel_prepare_reset(struct drm_device *dev)
3056 {
3057         struct drm_i915_private *dev_priv = to_i915(dev);
3058         struct intel_crtc *crtc;
3059
3060         /* no reset support for gen2 */
3061         if (IS_GEN2(dev))
3062                 return;
3063
3064         /* reset doesn't touch the display */
3065         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3066                 return;
3067
3068         drm_modeset_lock_all(dev);
3069
3070         /*
3071          * Disabling the crtcs gracefully seems nicer. Also the
3072          * g33 docs say we should at least disable all the planes.
3073          */
3074         for_each_intel_crtc(dev, crtc) {
3075                 if (crtc->active)
3076                         dev_priv->display.crtc_disable(&crtc->base);
3077         }
3078 }
3079
3080 void intel_finish_reset(struct drm_device *dev)
3081 {
3082         struct drm_i915_private *dev_priv = to_i915(dev);
3083
3084         /*
3085          * Flips in the rings will be nuked by the reset,
3086          * so complete all pending flips so that user space
3087          * will get its events and not get stuck.
3088          */
3089         intel_complete_page_flips(dev);
3090
3091         /* no reset support for gen2 */
3092         if (IS_GEN2(dev))
3093                 return;
3094
3095         /* reset doesn't touch the display */
3096         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3097                 /*
3098                  * Flips in the rings have been nuked by the reset,
3099                  * so update the base address of all primary
3100                  * planes to the the last fb to make sure we're
3101                  * showing the correct fb after a reset.
3102                  */
3103                 intel_update_primary_planes(dev);
3104                 return;
3105         }
3106
3107         /*
3108          * The display has been reset as well,
3109          * so need a full re-initialization.
3110          */
3111         intel_runtime_pm_disable_interrupts(dev_priv);
3112         intel_runtime_pm_enable_interrupts(dev_priv);
3113
3114         intel_modeset_init_hw(dev);
3115
3116         spin_lock_irq(&dev_priv->irq_lock);
3117         if (dev_priv->display.hpd_irq_setup)
3118                 dev_priv->display.hpd_irq_setup(dev);
3119         spin_unlock_irq(&dev_priv->irq_lock);
3120
3121         intel_modeset_setup_hw_state(dev, true);
3122
3123         intel_hpd_init(dev_priv);
3124
3125         drm_modeset_unlock_all(dev);
3126 }
3127
3128 static int
3129 intel_finish_fb(struct drm_framebuffer *old_fb)
3130 {
3131         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3132         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3133         bool was_interruptible = dev_priv->mm.interruptible;
3134         int ret;
3135
3136         /* Big Hammer, we also need to ensure that any pending
3137          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3138          * current scanout is retired before unpinning the old
3139          * framebuffer.
3140          *
3141          * This should only fail upon a hung GPU, in which case we
3142          * can safely continue.
3143          */
3144         dev_priv->mm.interruptible = false;
3145         ret = i915_gem_object_finish_gpu(obj);
3146         dev_priv->mm.interruptible = was_interruptible;
3147
3148         return ret;
3149 }
3150
3151 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3152 {
3153         struct drm_device *dev = crtc->dev;
3154         struct drm_i915_private *dev_priv = dev->dev_private;
3155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3156         bool pending;
3157
3158         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3159             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3160                 return false;
3161
3162         spin_lock_irq(&dev->event_lock);
3163         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3164         spin_unlock_irq(&dev->event_lock);
3165
3166         return pending;
3167 }
3168
3169 static void intel_update_pipe_size(struct intel_crtc *crtc)
3170 {
3171         struct drm_device *dev = crtc->base.dev;
3172         struct drm_i915_private *dev_priv = dev->dev_private;
3173         const struct drm_display_mode *adjusted_mode;
3174
3175         if (!i915.fastboot)
3176                 return;
3177
3178         /*
3179          * Update pipe size and adjust fitter if needed: the reason for this is
3180          * that in compute_mode_changes we check the native mode (not the pfit
3181          * mode) to see if we can flip rather than do a full mode set. In the
3182          * fastboot case, we'll flip, but if we don't update the pipesrc and
3183          * pfit state, we'll end up with a big fb scanned out into the wrong
3184          * sized surface.
3185          *
3186          * To fix this properly, we need to hoist the checks up into
3187          * compute_mode_changes (or above), check the actual pfit state and
3188          * whether the platform allows pfit disable with pipe active, and only
3189          * then update the pipesrc and pfit state, even on the flip path.
3190          */
3191
3192         adjusted_mode = &crtc->config->base.adjusted_mode;
3193
3194         I915_WRITE(PIPESRC(crtc->pipe),
3195                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3196                    (adjusted_mode->crtc_vdisplay - 1));
3197         if (!crtc->config->pch_pfit.enabled &&
3198             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3199              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3200                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3201                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3202                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3203         }
3204         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3205         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3206 }
3207
3208 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3209 {
3210         struct drm_device *dev = crtc->dev;
3211         struct drm_i915_private *dev_priv = dev->dev_private;
3212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3213         int pipe = intel_crtc->pipe;
3214         u32 reg, temp;
3215
3216         /* enable normal train */
3217         reg = FDI_TX_CTL(pipe);
3218         temp = I915_READ(reg);
3219         if (IS_IVYBRIDGE(dev)) {
3220                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3221                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3222         } else {
3223                 temp &= ~FDI_LINK_TRAIN_NONE;
3224                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3225         }
3226         I915_WRITE(reg, temp);
3227
3228         reg = FDI_RX_CTL(pipe);
3229         temp = I915_READ(reg);
3230         if (HAS_PCH_CPT(dev)) {
3231                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3232                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3233         } else {
3234                 temp &= ~FDI_LINK_TRAIN_NONE;
3235                 temp |= FDI_LINK_TRAIN_NONE;
3236         }
3237         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3238
3239         /* wait one idle pattern time */
3240         POSTING_READ(reg);
3241         udelay(1000);
3242
3243         /* IVB wants error correction enabled */
3244         if (IS_IVYBRIDGE(dev))
3245                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3246                            FDI_FE_ERRC_ENABLE);
3247 }
3248
3249 /* The FDI link training functions for ILK/Ibexpeak. */
3250 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3251 {
3252         struct drm_device *dev = crtc->dev;
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3255         int pipe = intel_crtc->pipe;
3256         u32 reg, temp, tries;
3257
3258         /* FDI needs bits from pipe first */
3259         assert_pipe_enabled(dev_priv, pipe);
3260
3261         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3262            for train result */
3263         reg = FDI_RX_IMR(pipe);
3264         temp = I915_READ(reg);
3265         temp &= ~FDI_RX_SYMBOL_LOCK;
3266         temp &= ~FDI_RX_BIT_LOCK;
3267         I915_WRITE(reg, temp);
3268         I915_READ(reg);
3269         udelay(150);
3270
3271         /* enable CPU FDI TX and PCH FDI RX */
3272         reg = FDI_TX_CTL(pipe);
3273         temp = I915_READ(reg);
3274         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3275         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3276         temp &= ~FDI_LINK_TRAIN_NONE;
3277         temp |= FDI_LINK_TRAIN_PATTERN_1;
3278         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3279
3280         reg = FDI_RX_CTL(pipe);
3281         temp = I915_READ(reg);
3282         temp &= ~FDI_LINK_TRAIN_NONE;
3283         temp |= FDI_LINK_TRAIN_PATTERN_1;
3284         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3285
3286         POSTING_READ(reg);
3287         udelay(150);
3288
3289         /* Ironlake workaround, enable clock pointer after FDI enable*/
3290         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3291         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3292                    FDI_RX_PHASE_SYNC_POINTER_EN);
3293
3294         reg = FDI_RX_IIR(pipe);
3295         for (tries = 0; tries < 5; tries++) {
3296                 temp = I915_READ(reg);
3297                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3298
3299                 if ((temp & FDI_RX_BIT_LOCK)) {
3300                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3301                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3302                         break;
3303                 }
3304         }
3305         if (tries == 5)
3306                 DRM_ERROR("FDI train 1 fail!\n");
3307
3308         /* Train 2 */
3309         reg = FDI_TX_CTL(pipe);
3310         temp = I915_READ(reg);
3311         temp &= ~FDI_LINK_TRAIN_NONE;
3312         temp |= FDI_LINK_TRAIN_PATTERN_2;
3313         I915_WRITE(reg, temp);
3314
3315         reg = FDI_RX_CTL(pipe);
3316         temp = I915_READ(reg);
3317         temp &= ~FDI_LINK_TRAIN_NONE;
3318         temp |= FDI_LINK_TRAIN_PATTERN_2;
3319         I915_WRITE(reg, temp);
3320
3321         POSTING_READ(reg);
3322         udelay(150);
3323
3324         reg = FDI_RX_IIR(pipe);
3325         for (tries = 0; tries < 5; tries++) {
3326                 temp = I915_READ(reg);
3327                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3328
3329                 if (temp & FDI_RX_SYMBOL_LOCK) {
3330                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3331                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3332                         break;
3333                 }
3334         }
3335         if (tries == 5)
3336                 DRM_ERROR("FDI train 2 fail!\n");
3337
3338         DRM_DEBUG_KMS("FDI train done\n");
3339
3340 }
3341
3342 static const int snb_b_fdi_train_param[] = {
3343         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3344         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3345         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3346         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3347 };
3348
3349 /* The FDI link training functions for SNB/Cougarpoint. */
3350 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3351 {
3352         struct drm_device *dev = crtc->dev;
3353         struct drm_i915_private *dev_priv = dev->dev_private;
3354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355         int pipe = intel_crtc->pipe;
3356         u32 reg, temp, i, retry;
3357
3358         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3359            for train result */
3360         reg = FDI_RX_IMR(pipe);
3361         temp = I915_READ(reg);
3362         temp &= ~FDI_RX_SYMBOL_LOCK;
3363         temp &= ~FDI_RX_BIT_LOCK;
3364         I915_WRITE(reg, temp);
3365
3366         POSTING_READ(reg);
3367         udelay(150);
3368
3369         /* enable CPU FDI TX and PCH FDI RX */
3370         reg = FDI_TX_CTL(pipe);
3371         temp = I915_READ(reg);
3372         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3373         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3374         temp &= ~FDI_LINK_TRAIN_NONE;
3375         temp |= FDI_LINK_TRAIN_PATTERN_1;
3376         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3377         /* SNB-B */
3378         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3379         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3380
3381         I915_WRITE(FDI_RX_MISC(pipe),
3382                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3383
3384         reg = FDI_RX_CTL(pipe);
3385         temp = I915_READ(reg);
3386         if (HAS_PCH_CPT(dev)) {
3387                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3388                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3389         } else {
3390                 temp &= ~FDI_LINK_TRAIN_NONE;
3391                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3392         }
3393         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3394
3395         POSTING_READ(reg);
3396         udelay(150);
3397
3398         for (i = 0; i < 4; i++) {
3399                 reg = FDI_TX_CTL(pipe);
3400                 temp = I915_READ(reg);
3401                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3402                 temp |= snb_b_fdi_train_param[i];
3403                 I915_WRITE(reg, temp);
3404
3405                 POSTING_READ(reg);
3406                 udelay(500);
3407
3408                 for (retry = 0; retry < 5; retry++) {
3409                         reg = FDI_RX_IIR(pipe);
3410                         temp = I915_READ(reg);
3411                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3412                         if (temp & FDI_RX_BIT_LOCK) {
3413                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3414                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3415                                 break;
3416                         }
3417                         udelay(50);
3418                 }
3419                 if (retry < 5)
3420                         break;
3421         }
3422         if (i == 4)
3423                 DRM_ERROR("FDI train 1 fail!\n");
3424
3425         /* Train 2 */
3426         reg = FDI_TX_CTL(pipe);
3427         temp = I915_READ(reg);
3428         temp &= ~FDI_LINK_TRAIN_NONE;
3429         temp |= FDI_LINK_TRAIN_PATTERN_2;
3430         if (IS_GEN6(dev)) {
3431                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3432                 /* SNB-B */
3433                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3434         }
3435         I915_WRITE(reg, temp);
3436
3437         reg = FDI_RX_CTL(pipe);
3438         temp = I915_READ(reg);
3439         if (HAS_PCH_CPT(dev)) {
3440                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3441                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3442         } else {
3443                 temp &= ~FDI_LINK_TRAIN_NONE;
3444                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3445         }
3446         I915_WRITE(reg, temp);
3447
3448         POSTING_READ(reg);
3449         udelay(150);
3450
3451         for (i = 0; i < 4; i++) {
3452                 reg = FDI_TX_CTL(pipe);
3453                 temp = I915_READ(reg);
3454                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3455                 temp |= snb_b_fdi_train_param[i];
3456                 I915_WRITE(reg, temp);
3457
3458                 POSTING_READ(reg);
3459                 udelay(500);
3460
3461                 for (retry = 0; retry < 5; retry++) {
3462                         reg = FDI_RX_IIR(pipe);
3463                         temp = I915_READ(reg);
3464                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3465                         if (temp & FDI_RX_SYMBOL_LOCK) {
3466                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3467                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3468                                 break;
3469                         }
3470                         udelay(50);
3471                 }
3472                 if (retry < 5)
3473                         break;
3474         }
3475         if (i == 4)
3476                 DRM_ERROR("FDI train 2 fail!\n");
3477
3478         DRM_DEBUG_KMS("FDI train done.\n");
3479 }
3480
3481 /* Manual link training for Ivy Bridge A0 parts */
3482 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3483 {
3484         struct drm_device *dev = crtc->dev;
3485         struct drm_i915_private *dev_priv = dev->dev_private;
3486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3487         int pipe = intel_crtc->pipe;
3488         u32 reg, temp, i, j;
3489
3490         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3491            for train result */
3492         reg = FDI_RX_IMR(pipe);
3493         temp = I915_READ(reg);
3494         temp &= ~FDI_RX_SYMBOL_LOCK;
3495         temp &= ~FDI_RX_BIT_LOCK;
3496         I915_WRITE(reg, temp);
3497
3498         POSTING_READ(reg);
3499         udelay(150);
3500
3501         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3502                       I915_READ(FDI_RX_IIR(pipe)));
3503
3504         /* Try each vswing and preemphasis setting twice before moving on */
3505         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3506                 /* disable first in case we need to retry */
3507                 reg = FDI_TX_CTL(pipe);
3508                 temp = I915_READ(reg);
3509                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3510                 temp &= ~FDI_TX_ENABLE;
3511                 I915_WRITE(reg, temp);
3512
3513                 reg = FDI_RX_CTL(pipe);
3514                 temp = I915_READ(reg);
3515                 temp &= ~FDI_LINK_TRAIN_AUTO;
3516                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3517                 temp &= ~FDI_RX_ENABLE;
3518                 I915_WRITE(reg, temp);
3519
3520                 /* enable CPU FDI TX and PCH FDI RX */
3521                 reg = FDI_TX_CTL(pipe);
3522                 temp = I915_READ(reg);
3523                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3524                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3525                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3526                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3527                 temp |= snb_b_fdi_train_param[j/2];
3528                 temp |= FDI_COMPOSITE_SYNC;
3529                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3530
3531                 I915_WRITE(FDI_RX_MISC(pipe),
3532                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3533
3534                 reg = FDI_RX_CTL(pipe);
3535                 temp = I915_READ(reg);
3536                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3537                 temp |= FDI_COMPOSITE_SYNC;
3538                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3539
3540                 POSTING_READ(reg);
3541                 udelay(1); /* should be 0.5us */
3542
3543                 for (i = 0; i < 4; i++) {
3544                         reg = FDI_RX_IIR(pipe);
3545                         temp = I915_READ(reg);
3546                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3547
3548                         if (temp & FDI_RX_BIT_LOCK ||
3549                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3550                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3551                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3552                                               i);
3553                                 break;
3554                         }
3555                         udelay(1); /* should be 0.5us */
3556                 }
3557                 if (i == 4) {
3558                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3559                         continue;
3560                 }
3561
3562                 /* Train 2 */
3563                 reg = FDI_TX_CTL(pipe);
3564                 temp = I915_READ(reg);
3565                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3566                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3567                 I915_WRITE(reg, temp);
3568
3569                 reg = FDI_RX_CTL(pipe);
3570                 temp = I915_READ(reg);
3571                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3572                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3573                 I915_WRITE(reg, temp);
3574
3575                 POSTING_READ(reg);
3576                 udelay(2); /* should be 1.5us */
3577
3578                 for (i = 0; i < 4; i++) {
3579                         reg = FDI_RX_IIR(pipe);
3580                         temp = I915_READ(reg);
3581                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3582
3583                         if (temp & FDI_RX_SYMBOL_LOCK ||
3584                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3585                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3586                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3587                                               i);
3588                                 goto train_done;
3589                         }
3590                         udelay(2); /* should be 1.5us */
3591                 }
3592                 if (i == 4)
3593                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3594         }
3595
3596 train_done:
3597         DRM_DEBUG_KMS("FDI train done.\n");
3598 }
3599
3600 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3601 {
3602         struct drm_device *dev = intel_crtc->base.dev;
3603         struct drm_i915_private *dev_priv = dev->dev_private;
3604         int pipe = intel_crtc->pipe;
3605         u32 reg, temp;
3606
3607
3608         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3609         reg = FDI_RX_CTL(pipe);
3610         temp = I915_READ(reg);
3611         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3612         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3613         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3614         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3615
3616         POSTING_READ(reg);
3617         udelay(200);
3618
3619         /* Switch from Rawclk to PCDclk */
3620         temp = I915_READ(reg);
3621         I915_WRITE(reg, temp | FDI_PCDCLK);
3622
3623         POSTING_READ(reg);
3624         udelay(200);
3625
3626         /* Enable CPU FDI TX PLL, always on for Ironlake */
3627         reg = FDI_TX_CTL(pipe);
3628         temp = I915_READ(reg);
3629         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3630                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3631
3632                 POSTING_READ(reg);
3633                 udelay(100);
3634         }
3635 }
3636
3637 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3638 {
3639         struct drm_device *dev = intel_crtc->base.dev;
3640         struct drm_i915_private *dev_priv = dev->dev_private;
3641         int pipe = intel_crtc->pipe;
3642         u32 reg, temp;
3643
3644         /* Switch from PCDclk to Rawclk */
3645         reg = FDI_RX_CTL(pipe);
3646         temp = I915_READ(reg);
3647         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3648
3649         /* Disable CPU FDI TX PLL */
3650         reg = FDI_TX_CTL(pipe);
3651         temp = I915_READ(reg);
3652         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3653
3654         POSTING_READ(reg);
3655         udelay(100);
3656
3657         reg = FDI_RX_CTL(pipe);
3658         temp = I915_READ(reg);
3659         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3660
3661         /* Wait for the clocks to turn off. */
3662         POSTING_READ(reg);
3663         udelay(100);
3664 }
3665
3666 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3667 {
3668         struct drm_device *dev = crtc->dev;
3669         struct drm_i915_private *dev_priv = dev->dev_private;
3670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3671         int pipe = intel_crtc->pipe;
3672         u32 reg, temp;
3673
3674         /* disable CPU FDI tx and PCH FDI rx */
3675         reg = FDI_TX_CTL(pipe);
3676         temp = I915_READ(reg);
3677         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3678         POSTING_READ(reg);
3679
3680         reg = FDI_RX_CTL(pipe);
3681         temp = I915_READ(reg);
3682         temp &= ~(0x7 << 16);
3683         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3684         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3685
3686         POSTING_READ(reg);
3687         udelay(100);
3688
3689         /* Ironlake workaround, disable clock pointer after downing FDI */
3690         if (HAS_PCH_IBX(dev))
3691                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3692
3693         /* still set train pattern 1 */
3694         reg = FDI_TX_CTL(pipe);
3695         temp = I915_READ(reg);
3696         temp &= ~FDI_LINK_TRAIN_NONE;
3697         temp |= FDI_LINK_TRAIN_PATTERN_1;
3698         I915_WRITE(reg, temp);
3699
3700         reg = FDI_RX_CTL(pipe);
3701         temp = I915_READ(reg);
3702         if (HAS_PCH_CPT(dev)) {
3703                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3704                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3705         } else {
3706                 temp &= ~FDI_LINK_TRAIN_NONE;
3707                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3708         }
3709         /* BPC in FDI rx is consistent with that in PIPECONF */
3710         temp &= ~(0x07 << 16);
3711         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3712         I915_WRITE(reg, temp);
3713
3714         POSTING_READ(reg);
3715         udelay(100);
3716 }
3717
3718 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3719 {
3720         struct intel_crtc *crtc;
3721
3722         /* Note that we don't need to be called with mode_config.lock here
3723          * as our list of CRTC objects is static for the lifetime of the
3724          * device and so cannot disappear as we iterate. Similarly, we can
3725          * happily treat the predicates as racy, atomic checks as userspace
3726          * cannot claim and pin a new fb without at least acquring the
3727          * struct_mutex and so serialising with us.
3728          */
3729         for_each_intel_crtc(dev, crtc) {
3730                 if (atomic_read(&crtc->unpin_work_count) == 0)
3731                         continue;
3732
3733                 if (crtc->unpin_work)
3734                         intel_wait_for_vblank(dev, crtc->pipe);
3735
3736                 return true;
3737         }
3738
3739         return false;
3740 }
3741
3742 static void page_flip_completed(struct intel_crtc *intel_crtc)
3743 {
3744         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3745         struct intel_unpin_work *work = intel_crtc->unpin_work;
3746
3747         /* ensure that the unpin work is consistent wrt ->pending. */
3748         smp_rmb();
3749         intel_crtc->unpin_work = NULL;
3750
3751         if (work->event)
3752                 drm_send_vblank_event(intel_crtc->base.dev,
3753                                       intel_crtc->pipe,
3754                                       work->event);
3755
3756         drm_crtc_vblank_put(&intel_crtc->base);
3757
3758         wake_up_all(&dev_priv->pending_flip_queue);
3759         queue_work(dev_priv->wq, &work->work);
3760
3761         trace_i915_flip_complete(intel_crtc->plane,
3762                                  work->pending_flip_obj);
3763 }
3764
3765 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3766 {
3767         struct drm_device *dev = crtc->dev;
3768         struct drm_i915_private *dev_priv = dev->dev_private;
3769
3770         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3771         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3772                                        !intel_crtc_has_pending_flip(crtc),
3773                                        60*HZ) == 0)) {
3774                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3775
3776                 spin_lock_irq(&dev->event_lock);
3777                 if (intel_crtc->unpin_work) {
3778                         WARN_ONCE(1, "Removing stuck page flip\n");
3779                         page_flip_completed(intel_crtc);
3780                 }
3781                 spin_unlock_irq(&dev->event_lock);
3782         }
3783
3784         if (crtc->primary->fb) {
3785                 mutex_lock(&dev->struct_mutex);
3786                 intel_finish_fb(crtc->primary->fb);
3787                 mutex_unlock(&dev->struct_mutex);
3788         }
3789 }
3790
3791 /* Program iCLKIP clock to the desired frequency */
3792 static void lpt_program_iclkip(struct drm_crtc *crtc)
3793 {
3794         struct drm_device *dev = crtc->dev;
3795         struct drm_i915_private *dev_priv = dev->dev_private;
3796         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3797         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3798         u32 temp;
3799
3800         mutex_lock(&dev_priv->dpio_lock);
3801
3802         /* It is necessary to ungate the pixclk gate prior to programming
3803          * the divisors, and gate it back when it is done.
3804          */
3805         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3806
3807         /* Disable SSCCTL */
3808         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3809                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3810                                 SBI_SSCCTL_DISABLE,
3811                         SBI_ICLK);
3812
3813         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3814         if (clock == 20000) {
3815                 auxdiv = 1;
3816                 divsel = 0x41;
3817                 phaseinc = 0x20;
3818         } else {
3819                 /* The iCLK virtual clock root frequency is in MHz,
3820                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3821                  * divisors, it is necessary to divide one by another, so we
3822                  * convert the virtual clock precision to KHz here for higher
3823                  * precision.
3824                  */
3825                 u32 iclk_virtual_root_freq = 172800 * 1000;
3826                 u32 iclk_pi_range = 64;
3827                 u32 desired_divisor, msb_divisor_value, pi_value;
3828
3829                 desired_divisor = (iclk_virtual_root_freq / clock);
3830                 msb_divisor_value = desired_divisor / iclk_pi_range;
3831                 pi_value = desired_divisor % iclk_pi_range;
3832
3833                 auxdiv = 0;
3834                 divsel = msb_divisor_value - 2;
3835                 phaseinc = pi_value;
3836         }
3837
3838         /* This should not happen with any sane values */
3839         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3840                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3841         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3842                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3843
3844         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3845                         clock,
3846                         auxdiv,
3847                         divsel,
3848                         phasedir,
3849                         phaseinc);
3850
3851         /* Program SSCDIVINTPHASE6 */
3852         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3853         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3854         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3855         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3856         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3857         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3858         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3859         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3860
3861         /* Program SSCAUXDIV */
3862         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3863         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3864         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3865         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3866
3867         /* Enable modulator and associated divider */
3868         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3869         temp &= ~SBI_SSCCTL_DISABLE;
3870         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3871
3872         /* Wait for initialization time */
3873         udelay(24);
3874
3875         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3876
3877         mutex_unlock(&dev_priv->dpio_lock);
3878 }
3879
3880 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3881                                                 enum pipe pch_transcoder)
3882 {
3883         struct drm_device *dev = crtc->base.dev;
3884         struct drm_i915_private *dev_priv = dev->dev_private;
3885         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3886
3887         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3888                    I915_READ(HTOTAL(cpu_transcoder)));
3889         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3890                    I915_READ(HBLANK(cpu_transcoder)));
3891         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3892                    I915_READ(HSYNC(cpu_transcoder)));
3893
3894         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3895                    I915_READ(VTOTAL(cpu_transcoder)));
3896         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3897                    I915_READ(VBLANK(cpu_transcoder)));
3898         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3899                    I915_READ(VSYNC(cpu_transcoder)));
3900         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3901                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3902 }
3903
3904 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3905 {
3906         struct drm_i915_private *dev_priv = dev->dev_private;
3907         uint32_t temp;
3908
3909         temp = I915_READ(SOUTH_CHICKEN1);
3910         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3911                 return;
3912
3913         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3914         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3915
3916         temp &= ~FDI_BC_BIFURCATION_SELECT;
3917         if (enable)
3918                 temp |= FDI_BC_BIFURCATION_SELECT;
3919
3920         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3921         I915_WRITE(SOUTH_CHICKEN1, temp);
3922         POSTING_READ(SOUTH_CHICKEN1);
3923 }
3924
3925 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3926 {
3927         struct drm_device *dev = intel_crtc->base.dev;
3928
3929         switch (intel_crtc->pipe) {
3930         case PIPE_A:
3931                 break;
3932         case PIPE_B:
3933                 if (intel_crtc->config->fdi_lanes > 2)
3934                         cpt_set_fdi_bc_bifurcation(dev, false);
3935                 else
3936                         cpt_set_fdi_bc_bifurcation(dev, true);
3937
3938                 break;
3939         case PIPE_C:
3940                 cpt_set_fdi_bc_bifurcation(dev, true);
3941
3942                 break;
3943         default:
3944                 BUG();
3945         }
3946 }
3947
3948 /*
3949  * Enable PCH resources required for PCH ports:
3950  *   - PCH PLLs
3951  *   - FDI training & RX/TX
3952  *   - update transcoder timings
3953  *   - DP transcoding bits
3954  *   - transcoder
3955  */
3956 static void ironlake_pch_enable(struct drm_crtc *crtc)
3957 {
3958         struct drm_device *dev = crtc->dev;
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3961         int pipe = intel_crtc->pipe;
3962         u32 reg, temp;
3963
3964         assert_pch_transcoder_disabled(dev_priv, pipe);
3965
3966         if (IS_IVYBRIDGE(dev))
3967                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3968
3969         /* Write the TU size bits before fdi link training, so that error
3970          * detection works. */
3971         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3972                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3973
3974         /* For PCH output, training FDI link */
3975         dev_priv->display.fdi_link_train(crtc);
3976
3977         /* We need to program the right clock selection before writing the pixel
3978          * mutliplier into the DPLL. */
3979         if (HAS_PCH_CPT(dev)) {
3980                 u32 sel;
3981
3982                 temp = I915_READ(PCH_DPLL_SEL);
3983                 temp |= TRANS_DPLL_ENABLE(pipe);
3984                 sel = TRANS_DPLLB_SEL(pipe);
3985                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3986                         temp |= sel;
3987                 else
3988                         temp &= ~sel;
3989                 I915_WRITE(PCH_DPLL_SEL, temp);
3990         }
3991
3992         /* XXX: pch pll's can be enabled any time before we enable the PCH
3993          * transcoder, and we actually should do this to not upset any PCH
3994          * transcoder that already use the clock when we share it.
3995          *
3996          * Note that enable_shared_dpll tries to do the right thing, but
3997          * get_shared_dpll unconditionally resets the pll - we need that to have
3998          * the right LVDS enable sequence. */
3999         intel_enable_shared_dpll(intel_crtc);
4000
4001         /* set transcoder timing, panel must allow it */
4002         assert_panel_unlocked(dev_priv, pipe);
4003         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4004
4005         intel_fdi_normal_train(crtc);
4006
4007         /* For PCH DP, enable TRANS_DP_CTL */
4008         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4009                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4010                 reg = TRANS_DP_CTL(pipe);
4011                 temp = I915_READ(reg);
4012                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4013                           TRANS_DP_SYNC_MASK |
4014                           TRANS_DP_BPC_MASK);
4015                 temp |= (TRANS_DP_OUTPUT_ENABLE |
4016                          TRANS_DP_ENH_FRAMING);
4017                 temp |= bpc << 9; /* same format but at 11:9 */
4018
4019                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4020                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4021                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4022                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4023
4024                 switch (intel_trans_dp_port_sel(crtc)) {
4025                 case PCH_DP_B:
4026                         temp |= TRANS_DP_PORT_SEL_B;
4027                         break;
4028                 case PCH_DP_C:
4029                         temp |= TRANS_DP_PORT_SEL_C;
4030                         break;
4031                 case PCH_DP_D:
4032                         temp |= TRANS_DP_PORT_SEL_D;
4033                         break;
4034                 default:
4035                         BUG();
4036                 }
4037
4038                 I915_WRITE(reg, temp);
4039         }
4040
4041         ironlake_enable_pch_transcoder(dev_priv, pipe);
4042 }
4043
4044 static void lpt_pch_enable(struct drm_crtc *crtc)
4045 {
4046         struct drm_device *dev = crtc->dev;
4047         struct drm_i915_private *dev_priv = dev->dev_private;
4048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4049         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4050
4051         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4052
4053         lpt_program_iclkip(crtc);
4054
4055         /* Set transcoder timing. */
4056         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4057
4058         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4059 }
4060
4061 void intel_put_shared_dpll(struct intel_crtc *crtc)
4062 {
4063         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4064
4065         if (pll == NULL)
4066                 return;
4067
4068         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4069                 WARN(1, "bad %s crtc mask\n", pll->name);
4070                 return;
4071         }
4072
4073         pll->config.crtc_mask &= ~(1 << crtc->pipe);
4074         if (pll->config.crtc_mask == 0) {
4075                 WARN_ON(pll->on);
4076                 WARN_ON(pll->active);
4077         }
4078
4079         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4080 }
4081
4082 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4083                                                 struct intel_crtc_state *crtc_state)
4084 {
4085         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4086         struct intel_shared_dpll *pll;
4087         enum intel_dpll_id i;
4088
4089         if (HAS_PCH_IBX(dev_priv->dev)) {
4090                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4091                 i = (enum intel_dpll_id) crtc->pipe;
4092                 pll = &dev_priv->shared_dplls[i];
4093
4094                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4095                               crtc->base.base.id, pll->name);
4096
4097                 WARN_ON(pll->new_config->crtc_mask);
4098
4099                 goto found;
4100         }
4101
4102         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4103                 pll = &dev_priv->shared_dplls[i];
4104
4105                 /* Only want to check enabled timings first */
4106                 if (pll->new_config->crtc_mask == 0)
4107                         continue;
4108
4109                 if (memcmp(&crtc_state->dpll_hw_state,
4110                            &pll->new_config->hw_state,
4111                            sizeof(pll->new_config->hw_state)) == 0) {
4112                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4113                                       crtc->base.base.id, pll->name,
4114                                       pll->new_config->crtc_mask,
4115                                       pll->active);
4116                         goto found;
4117                 }
4118         }
4119
4120         /* Ok no matching timings, maybe there's a free one? */
4121         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4122                 pll = &dev_priv->shared_dplls[i];
4123                 if (pll->new_config->crtc_mask == 0) {
4124                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4125                                       crtc->base.base.id, pll->name);
4126                         goto found;
4127                 }
4128         }
4129
4130         return NULL;
4131
4132 found:
4133         if (pll->new_config->crtc_mask == 0)
4134                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4135
4136         crtc_state->shared_dpll = i;
4137         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4138                          pipe_name(crtc->pipe));
4139
4140         pll->new_config->crtc_mask |= 1 << crtc->pipe;
4141
4142         return pll;
4143 }
4144
4145 /**
4146  * intel_shared_dpll_start_config - start a new PLL staged config
4147  * @dev_priv: DRM device
4148  * @clear_pipes: mask of pipes that will have their PLLs freed
4149  *
4150  * Starts a new PLL staged config, copying the current config but
4151  * releasing the references of pipes specified in clear_pipes.
4152  */
4153 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4154                                           unsigned clear_pipes)
4155 {
4156         struct intel_shared_dpll *pll;
4157         enum intel_dpll_id i;
4158
4159         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4160                 pll = &dev_priv->shared_dplls[i];
4161
4162                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4163                                           GFP_KERNEL);
4164                 if (!pll->new_config)
4165                         goto cleanup;
4166
4167                 pll->new_config->crtc_mask &= ~clear_pipes;
4168         }
4169
4170         return 0;
4171
4172 cleanup:
4173         while (--i >= 0) {
4174                 pll = &dev_priv->shared_dplls[i];
4175                 kfree(pll->new_config);
4176                 pll->new_config = NULL;
4177         }
4178
4179         return -ENOMEM;
4180 }
4181
4182 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4183 {
4184         struct intel_shared_dpll *pll;
4185         enum intel_dpll_id i;
4186
4187         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4188                 pll = &dev_priv->shared_dplls[i];
4189
4190                 WARN_ON(pll->new_config == &pll->config);
4191
4192                 pll->config = *pll->new_config;
4193                 kfree(pll->new_config);
4194                 pll->new_config = NULL;
4195         }
4196 }
4197
4198 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4199 {
4200         struct intel_shared_dpll *pll;
4201         enum intel_dpll_id i;
4202
4203         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4204                 pll = &dev_priv->shared_dplls[i];
4205
4206                 WARN_ON(pll->new_config == &pll->config);
4207
4208                 kfree(pll->new_config);
4209                 pll->new_config = NULL;
4210         }
4211 }
4212
4213 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4214 {
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         int dslreg = PIPEDSL(pipe);
4217         u32 temp;
4218
4219         temp = I915_READ(dslreg);
4220         udelay(500);
4221         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4222                 if (wait_for(I915_READ(dslreg) != temp, 5))
4223                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4224         }
4225 }
4226
4227 static void skylake_pfit_enable(struct intel_crtc *crtc)
4228 {
4229         struct drm_device *dev = crtc->base.dev;
4230         struct drm_i915_private *dev_priv = dev->dev_private;
4231         int pipe = crtc->pipe;
4232
4233         if (crtc->config->pch_pfit.enabled) {
4234                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4235                 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4236                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4237         }
4238 }
4239
4240 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4241 {
4242         struct drm_device *dev = crtc->base.dev;
4243         struct drm_i915_private *dev_priv = dev->dev_private;
4244         int pipe = crtc->pipe;
4245
4246         if (crtc->config->pch_pfit.enabled) {
4247                 /* Force use of hard-coded filter coefficients
4248                  * as some pre-programmed values are broken,
4249                  * e.g. x201.
4250                  */
4251                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4252                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4253                                                  PF_PIPE_SEL_IVB(pipe));
4254                 else
4255                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4256                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4257                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4258         }
4259 }
4260
4261 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4262 {
4263         struct drm_device *dev = crtc->dev;
4264         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4265         struct drm_plane *plane;
4266         struct intel_plane *intel_plane;
4267
4268         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4269                 intel_plane = to_intel_plane(plane);
4270                 if (intel_plane->pipe == pipe)
4271                         intel_plane_restore(&intel_plane->base);
4272         }
4273 }
4274
4275 /*
4276  * Disable a plane internally without actually modifying the plane's state.
4277  * This will allow us to easily restore the plane later by just reprogramming
4278  * its state.
4279  */
4280 static void disable_plane_internal(struct drm_plane *plane)
4281 {
4282         struct intel_plane *intel_plane = to_intel_plane(plane);
4283         struct drm_plane_state *state =
4284                 plane->funcs->atomic_duplicate_state(plane);
4285         struct intel_plane_state *intel_state = to_intel_plane_state(state);
4286
4287         intel_state->visible = false;
4288         intel_plane->commit_plane(plane, intel_state);
4289
4290         intel_plane_destroy_state(plane, state);
4291 }
4292
4293 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4294 {
4295         struct drm_device *dev = crtc->dev;
4296         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4297         struct drm_plane *plane;
4298         struct intel_plane *intel_plane;
4299
4300         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4301                 intel_plane = to_intel_plane(plane);
4302                 if (plane->fb && intel_plane->pipe == pipe)
4303                         disable_plane_internal(plane);
4304         }
4305 }
4306
4307 void hsw_enable_ips(struct intel_crtc *crtc)
4308 {
4309         struct drm_device *dev = crtc->base.dev;
4310         struct drm_i915_private *dev_priv = dev->dev_private;
4311
4312         if (!crtc->config->ips_enabled)
4313                 return;
4314
4315         /* We can only enable IPS after we enable a plane and wait for a vblank */
4316         intel_wait_for_vblank(dev, crtc->pipe);
4317
4318         assert_plane_enabled(dev_priv, crtc->plane);
4319         if (IS_BROADWELL(dev)) {
4320                 mutex_lock(&dev_priv->rps.hw_lock);
4321                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4322                 mutex_unlock(&dev_priv->rps.hw_lock);
4323                 /* Quoting Art Runyan: "its not safe to expect any particular
4324                  * value in IPS_CTL bit 31 after enabling IPS through the
4325                  * mailbox." Moreover, the mailbox may return a bogus state,
4326                  * so we need to just enable it and continue on.
4327                  */
4328         } else {
4329                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4330                 /* The bit only becomes 1 in the next vblank, so this wait here
4331                  * is essentially intel_wait_for_vblank. If we don't have this
4332                  * and don't wait for vblanks until the end of crtc_enable, then
4333                  * the HW state readout code will complain that the expected
4334                  * IPS_CTL value is not the one we read. */
4335                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4336                         DRM_ERROR("Timed out waiting for IPS enable\n");
4337         }
4338 }
4339
4340 void hsw_disable_ips(struct intel_crtc *crtc)
4341 {
4342         struct drm_device *dev = crtc->base.dev;
4343         struct drm_i915_private *dev_priv = dev->dev_private;
4344
4345         if (!crtc->config->ips_enabled)
4346                 return;
4347
4348         assert_plane_enabled(dev_priv, crtc->plane);
4349         if (IS_BROADWELL(dev)) {
4350                 mutex_lock(&dev_priv->rps.hw_lock);
4351                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4352                 mutex_unlock(&dev_priv->rps.hw_lock);
4353                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4354                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4355                         DRM_ERROR("Timed out waiting for IPS disable\n");
4356         } else {
4357                 I915_WRITE(IPS_CTL, 0);
4358                 POSTING_READ(IPS_CTL);
4359         }
4360
4361         /* We need to wait for a vblank before we can disable the plane. */
4362         intel_wait_for_vblank(dev, crtc->pipe);
4363 }
4364
4365 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4366 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4367 {
4368         struct drm_device *dev = crtc->dev;
4369         struct drm_i915_private *dev_priv = dev->dev_private;
4370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4371         enum pipe pipe = intel_crtc->pipe;
4372         int palreg = PALETTE(pipe);
4373         int i;
4374         bool reenable_ips = false;
4375
4376         /* The clocks have to be on to load the palette. */
4377         if (!crtc->state->enable || !intel_crtc->active)
4378                 return;
4379
4380         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4381                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4382                         assert_dsi_pll_enabled(dev_priv);
4383                 else
4384                         assert_pll_enabled(dev_priv, pipe);
4385         }
4386
4387         /* use legacy palette for Ironlake */
4388         if (!HAS_GMCH_DISPLAY(dev))
4389                 palreg = LGC_PALETTE(pipe);
4390
4391         /* Workaround : Do not read or write the pipe palette/gamma data while
4392          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4393          */
4394         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4395             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4396              GAMMA_MODE_MODE_SPLIT)) {
4397                 hsw_disable_ips(intel_crtc);
4398                 reenable_ips = true;
4399         }
4400
4401         for (i = 0; i < 256; i++) {
4402                 I915_WRITE(palreg + 4 * i,
4403                            (intel_crtc->lut_r[i] << 16) |
4404                            (intel_crtc->lut_g[i] << 8) |
4405                            intel_crtc->lut_b[i]);
4406         }
4407
4408         if (reenable_ips)
4409                 hsw_enable_ips(intel_crtc);
4410 }
4411
4412 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4413 {
4414         if (!enable && intel_crtc->overlay) {
4415                 struct drm_device *dev = intel_crtc->base.dev;
4416                 struct drm_i915_private *dev_priv = dev->dev_private;
4417
4418                 mutex_lock(&dev->struct_mutex);
4419                 dev_priv->mm.interruptible = false;
4420                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4421                 dev_priv->mm.interruptible = true;
4422                 mutex_unlock(&dev->struct_mutex);
4423         }
4424
4425         /* Let userspace switch the overlay on again. In most cases userspace
4426          * has to recompute where to put it anyway.
4427          */
4428 }
4429
4430 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4431 {
4432         struct drm_device *dev = crtc->dev;
4433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4434         int pipe = intel_crtc->pipe;
4435
4436         intel_enable_primary_hw_plane(crtc->primary, crtc);
4437         intel_enable_sprite_planes(crtc);
4438         intel_crtc_update_cursor(crtc, true);
4439         intel_crtc_dpms_overlay(intel_crtc, true);
4440
4441         hsw_enable_ips(intel_crtc);
4442
4443         mutex_lock(&dev->struct_mutex);
4444         intel_fbc_update(dev);
4445         mutex_unlock(&dev->struct_mutex);
4446
4447         /*
4448          * FIXME: Once we grow proper nuclear flip support out of this we need
4449          * to compute the mask of flip planes precisely. For the time being
4450          * consider this a flip from a NULL plane.
4451          */
4452         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4453 }
4454
4455 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4456 {
4457         struct drm_device *dev = crtc->dev;
4458         struct drm_i915_private *dev_priv = dev->dev_private;
4459         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4460         int pipe = intel_crtc->pipe;
4461
4462         intel_crtc_wait_for_pending_flips(crtc);
4463
4464         if (dev_priv->fbc.crtc == intel_crtc)
4465                 intel_fbc_disable(dev);
4466
4467         hsw_disable_ips(intel_crtc);
4468
4469         intel_crtc_dpms_overlay(intel_crtc, false);
4470         intel_crtc_update_cursor(crtc, false);
4471         intel_disable_sprite_planes(crtc);
4472         intel_disable_primary_hw_plane(crtc->primary, crtc);
4473
4474         /*
4475          * FIXME: Once we grow proper nuclear flip support out of this we need
4476          * to compute the mask of flip planes precisely. For the time being
4477          * consider this a flip to a NULL plane.
4478          */
4479         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4480 }
4481
4482 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4483 {
4484         struct drm_device *dev = crtc->dev;
4485         struct drm_i915_private *dev_priv = dev->dev_private;
4486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4487         struct intel_encoder *encoder;
4488         int pipe = intel_crtc->pipe;
4489
4490         WARN_ON(!crtc->state->enable);
4491
4492         if (intel_crtc->active)
4493                 return;
4494
4495         if (intel_crtc->config->has_pch_encoder)
4496                 intel_prepare_shared_dpll(intel_crtc);
4497
4498         if (intel_crtc->config->has_dp_encoder)
4499                 intel_dp_set_m_n(intel_crtc, M1_N1);
4500
4501         intel_set_pipe_timings(intel_crtc);
4502
4503         if (intel_crtc->config->has_pch_encoder) {
4504                 intel_cpu_transcoder_set_m_n(intel_crtc,
4505                                      &intel_crtc->config->fdi_m_n, NULL);
4506         }
4507
4508         ironlake_set_pipeconf(crtc);
4509
4510         intel_crtc->active = true;
4511
4512         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4513         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4514
4515         for_each_encoder_on_crtc(dev, crtc, encoder)
4516                 if (encoder->pre_enable)
4517                         encoder->pre_enable(encoder);
4518
4519         if (intel_crtc->config->has_pch_encoder) {
4520                 /* Note: FDI PLL enabling _must_ be done before we enable the
4521                  * cpu pipes, hence this is separate from all the other fdi/pch
4522                  * enabling. */
4523                 ironlake_fdi_pll_enable(intel_crtc);
4524         } else {
4525                 assert_fdi_tx_disabled(dev_priv, pipe);
4526                 assert_fdi_rx_disabled(dev_priv, pipe);
4527         }
4528
4529         ironlake_pfit_enable(intel_crtc);
4530
4531         /*
4532          * On ILK+ LUT must be loaded before the pipe is running but with
4533          * clocks enabled
4534          */
4535         intel_crtc_load_lut(crtc);
4536
4537         intel_update_watermarks(crtc);
4538         intel_enable_pipe(intel_crtc);
4539
4540         if (intel_crtc->config->has_pch_encoder)
4541                 ironlake_pch_enable(crtc);
4542
4543         assert_vblank_disabled(crtc);
4544         drm_crtc_vblank_on(crtc);
4545
4546         for_each_encoder_on_crtc(dev, crtc, encoder)
4547                 encoder->enable(encoder);
4548
4549         if (HAS_PCH_CPT(dev))
4550                 cpt_verify_modeset(dev, intel_crtc->pipe);
4551
4552         intel_crtc_enable_planes(crtc);
4553 }
4554
4555 /* IPS only exists on ULT machines and is tied to pipe A. */
4556 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4557 {
4558         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4559 }
4560
4561 /*
4562  * This implements the workaround described in the "notes" section of the mode
4563  * set sequence documentation. When going from no pipes or single pipe to
4564  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4565  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4566  */
4567 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4568 {
4569         struct drm_device *dev = crtc->base.dev;
4570         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4571
4572         /* We want to get the other_active_crtc only if there's only 1 other
4573          * active crtc. */
4574         for_each_intel_crtc(dev, crtc_it) {
4575                 if (!crtc_it->active || crtc_it == crtc)
4576                         continue;
4577
4578                 if (other_active_crtc)
4579                         return;
4580
4581                 other_active_crtc = crtc_it;
4582         }
4583         if (!other_active_crtc)
4584                 return;
4585
4586         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4587         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4588 }
4589
4590 static void haswell_crtc_enable(struct drm_crtc *crtc)
4591 {
4592         struct drm_device *dev = crtc->dev;
4593         struct drm_i915_private *dev_priv = dev->dev_private;
4594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4595         struct intel_encoder *encoder;
4596         int pipe = intel_crtc->pipe;
4597
4598         WARN_ON(!crtc->state->enable);
4599
4600         if (intel_crtc->active)
4601                 return;
4602
4603         if (intel_crtc_to_shared_dpll(intel_crtc))
4604                 intel_enable_shared_dpll(intel_crtc);
4605
4606         if (intel_crtc->config->has_dp_encoder)
4607                 intel_dp_set_m_n(intel_crtc, M1_N1);
4608
4609         intel_set_pipe_timings(intel_crtc);
4610
4611         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4612                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4613                            intel_crtc->config->pixel_multiplier - 1);
4614         }
4615
4616         if (intel_crtc->config->has_pch_encoder) {
4617                 intel_cpu_transcoder_set_m_n(intel_crtc,
4618                                      &intel_crtc->config->fdi_m_n, NULL);
4619         }
4620
4621         haswell_set_pipeconf(crtc);
4622
4623         intel_set_pipe_csc(crtc);
4624
4625         intel_crtc->active = true;
4626
4627         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4628         for_each_encoder_on_crtc(dev, crtc, encoder)
4629                 if (encoder->pre_enable)
4630                         encoder->pre_enable(encoder);
4631
4632         if (intel_crtc->config->has_pch_encoder) {
4633                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4634                                                       true);
4635                 dev_priv->display.fdi_link_train(crtc);
4636         }
4637
4638         intel_ddi_enable_pipe_clock(intel_crtc);
4639
4640         if (IS_SKYLAKE(dev))
4641                 skylake_pfit_enable(intel_crtc);
4642         else
4643                 ironlake_pfit_enable(intel_crtc);
4644
4645         /*
4646          * On ILK+ LUT must be loaded before the pipe is running but with
4647          * clocks enabled
4648          */
4649         intel_crtc_load_lut(crtc);
4650
4651         intel_ddi_set_pipe_settings(crtc);
4652         intel_ddi_enable_transcoder_func(crtc);
4653
4654         intel_update_watermarks(crtc);
4655         intel_enable_pipe(intel_crtc);
4656
4657         if (intel_crtc->config->has_pch_encoder)
4658                 lpt_pch_enable(crtc);
4659
4660         if (intel_crtc->config->dp_encoder_is_mst)
4661                 intel_ddi_set_vc_payload_alloc(crtc, true);
4662
4663         assert_vblank_disabled(crtc);
4664         drm_crtc_vblank_on(crtc);
4665
4666         for_each_encoder_on_crtc(dev, crtc, encoder) {
4667                 encoder->enable(encoder);
4668                 intel_opregion_notify_encoder(encoder, true);
4669         }
4670
4671         /* If we change the relative order between pipe/planes enabling, we need
4672          * to change the workaround. */
4673         haswell_mode_set_planes_workaround(intel_crtc);
4674         intel_crtc_enable_planes(crtc);
4675 }
4676
4677 static void skylake_pfit_disable(struct intel_crtc *crtc)
4678 {
4679         struct drm_device *dev = crtc->base.dev;
4680         struct drm_i915_private *dev_priv = dev->dev_private;
4681         int pipe = crtc->pipe;
4682
4683         /* To avoid upsetting the power well on haswell only disable the pfit if
4684          * it's in use. The hw state code will make sure we get this right. */
4685         if (crtc->config->pch_pfit.enabled) {
4686                 I915_WRITE(PS_CTL(pipe), 0);
4687                 I915_WRITE(PS_WIN_POS(pipe), 0);
4688                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4689         }
4690 }
4691
4692 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4693 {
4694         struct drm_device *dev = crtc->base.dev;
4695         struct drm_i915_private *dev_priv = dev->dev_private;
4696         int pipe = crtc->pipe;
4697
4698         /* To avoid upsetting the power well on haswell only disable the pfit if
4699          * it's in use. The hw state code will make sure we get this right. */
4700         if (crtc->config->pch_pfit.enabled) {
4701                 I915_WRITE(PF_CTL(pipe), 0);
4702                 I915_WRITE(PF_WIN_POS(pipe), 0);
4703                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4704         }
4705 }
4706
4707 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4708 {
4709         struct drm_device *dev = crtc->dev;
4710         struct drm_i915_private *dev_priv = dev->dev_private;
4711         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712         struct intel_encoder *encoder;
4713         int pipe = intel_crtc->pipe;
4714         u32 reg, temp;
4715
4716         if (!intel_crtc->active)
4717                 return;
4718
4719         intel_crtc_disable_planes(crtc);
4720
4721         for_each_encoder_on_crtc(dev, crtc, encoder)
4722                 encoder->disable(encoder);
4723
4724         drm_crtc_vblank_off(crtc);
4725         assert_vblank_disabled(crtc);
4726
4727         if (intel_crtc->config->has_pch_encoder)
4728                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4729
4730         intel_disable_pipe(intel_crtc);
4731
4732         ironlake_pfit_disable(intel_crtc);
4733
4734         for_each_encoder_on_crtc(dev, crtc, encoder)
4735                 if (encoder->post_disable)
4736                         encoder->post_disable(encoder);
4737
4738         if (intel_crtc->config->has_pch_encoder) {
4739                 ironlake_fdi_disable(crtc);
4740
4741                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4742
4743                 if (HAS_PCH_CPT(dev)) {
4744                         /* disable TRANS_DP_CTL */
4745                         reg = TRANS_DP_CTL(pipe);
4746                         temp = I915_READ(reg);
4747                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4748                                   TRANS_DP_PORT_SEL_MASK);
4749                         temp |= TRANS_DP_PORT_SEL_NONE;
4750                         I915_WRITE(reg, temp);
4751
4752                         /* disable DPLL_SEL */
4753                         temp = I915_READ(PCH_DPLL_SEL);
4754                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4755                         I915_WRITE(PCH_DPLL_SEL, temp);
4756                 }
4757
4758                 /* disable PCH DPLL */
4759                 intel_disable_shared_dpll(intel_crtc);
4760
4761                 ironlake_fdi_pll_disable(intel_crtc);
4762         }
4763
4764         intel_crtc->active = false;
4765         intel_update_watermarks(crtc);
4766
4767         mutex_lock(&dev->struct_mutex);
4768         intel_fbc_update(dev);
4769         mutex_unlock(&dev->struct_mutex);
4770 }
4771
4772 static void haswell_crtc_disable(struct drm_crtc *crtc)
4773 {
4774         struct drm_device *dev = crtc->dev;
4775         struct drm_i915_private *dev_priv = dev->dev_private;
4776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4777         struct intel_encoder *encoder;
4778         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4779
4780         if (!intel_crtc->active)
4781                 return;
4782
4783         intel_crtc_disable_planes(crtc);
4784
4785         for_each_encoder_on_crtc(dev, crtc, encoder) {
4786                 intel_opregion_notify_encoder(encoder, false);
4787                 encoder->disable(encoder);
4788         }
4789
4790         drm_crtc_vblank_off(crtc);
4791         assert_vblank_disabled(crtc);
4792
4793         if (intel_crtc->config->has_pch_encoder)
4794                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4795                                                       false);
4796         intel_disable_pipe(intel_crtc);
4797
4798         if (intel_crtc->config->dp_encoder_is_mst)
4799                 intel_ddi_set_vc_payload_alloc(crtc, false);
4800
4801         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4802
4803         if (IS_SKYLAKE(dev))
4804                 skylake_pfit_disable(intel_crtc);
4805         else
4806                 ironlake_pfit_disable(intel_crtc);
4807
4808         intel_ddi_disable_pipe_clock(intel_crtc);
4809
4810         if (intel_crtc->config->has_pch_encoder) {
4811                 lpt_disable_pch_transcoder(dev_priv);
4812                 intel_ddi_fdi_disable(crtc);
4813         }
4814
4815         for_each_encoder_on_crtc(dev, crtc, encoder)
4816                 if (encoder->post_disable)
4817                         encoder->post_disable(encoder);
4818
4819         intel_crtc->active = false;
4820         intel_update_watermarks(crtc);
4821
4822         mutex_lock(&dev->struct_mutex);
4823         intel_fbc_update(dev);
4824         mutex_unlock(&dev->struct_mutex);
4825
4826         if (intel_crtc_to_shared_dpll(intel_crtc))
4827                 intel_disable_shared_dpll(intel_crtc);
4828 }
4829
4830 static void ironlake_crtc_off(struct drm_crtc *crtc)
4831 {
4832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4833         intel_put_shared_dpll(intel_crtc);
4834 }
4835
4836
4837 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4838 {
4839         struct drm_device *dev = crtc->base.dev;
4840         struct drm_i915_private *dev_priv = dev->dev_private;
4841         struct intel_crtc_state *pipe_config = crtc->config;
4842
4843         if (!pipe_config->gmch_pfit.control)
4844                 return;
4845
4846         /*
4847          * The panel fitter should only be adjusted whilst the pipe is disabled,
4848          * according to register description and PRM.
4849          */
4850         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4851         assert_pipe_disabled(dev_priv, crtc->pipe);
4852
4853         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4854         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4855
4856         /* Border color in case we don't scale up to the full screen. Black by
4857          * default, change to something else for debugging. */
4858         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4859 }
4860
4861 static enum intel_display_power_domain port_to_power_domain(enum port port)
4862 {
4863         switch (port) {
4864         case PORT_A:
4865                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4866         case PORT_B:
4867                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4868         case PORT_C:
4869                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4870         case PORT_D:
4871                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4872         default:
4873                 WARN_ON_ONCE(1);
4874                 return POWER_DOMAIN_PORT_OTHER;
4875         }
4876 }
4877
4878 #define for_each_power_domain(domain, mask)                             \
4879         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4880                 if ((1 << (domain)) & (mask))
4881
4882 enum intel_display_power_domain
4883 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4884 {
4885         struct drm_device *dev = intel_encoder->base.dev;
4886         struct intel_digital_port *intel_dig_port;
4887
4888         switch (intel_encoder->type) {
4889         case INTEL_OUTPUT_UNKNOWN:
4890                 /* Only DDI platforms should ever use this output type */
4891                 WARN_ON_ONCE(!HAS_DDI(dev));
4892         case INTEL_OUTPUT_DISPLAYPORT:
4893         case INTEL_OUTPUT_HDMI:
4894         case INTEL_OUTPUT_EDP:
4895                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4896                 return port_to_power_domain(intel_dig_port->port);
4897         case INTEL_OUTPUT_DP_MST:
4898                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4899                 return port_to_power_domain(intel_dig_port->port);
4900         case INTEL_OUTPUT_ANALOG:
4901                 return POWER_DOMAIN_PORT_CRT;
4902         case INTEL_OUTPUT_DSI:
4903                 return POWER_DOMAIN_PORT_DSI;
4904         default:
4905                 return POWER_DOMAIN_PORT_OTHER;
4906         }
4907 }
4908
4909 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4910 {
4911         struct drm_device *dev = crtc->dev;
4912         struct intel_encoder *intel_encoder;
4913         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4914         enum pipe pipe = intel_crtc->pipe;
4915         unsigned long mask;
4916         enum transcoder transcoder;
4917
4918         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4919
4920         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4921         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4922         if (intel_crtc->config->pch_pfit.enabled ||
4923             intel_crtc->config->pch_pfit.force_thru)
4924                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4925
4926         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4927                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4928
4929         return mask;
4930 }
4931
4932 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4933 {
4934         struct drm_i915_private *dev_priv = dev->dev_private;
4935         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4936         struct intel_crtc *crtc;
4937
4938         /*
4939          * First get all needed power domains, then put all unneeded, to avoid
4940          * any unnecessary toggling of the power wells.
4941          */
4942         for_each_intel_crtc(dev, crtc) {
4943                 enum intel_display_power_domain domain;
4944
4945                 if (!crtc->base.state->enable)
4946                         continue;
4947
4948                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4949
4950                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4951                         intel_display_power_get(dev_priv, domain);
4952         }
4953
4954         if (dev_priv->display.modeset_global_resources)
4955                 dev_priv->display.modeset_global_resources(dev);
4956
4957         for_each_intel_crtc(dev, crtc) {
4958                 enum intel_display_power_domain domain;
4959
4960                 for_each_power_domain(domain, crtc->enabled_power_domains)
4961                         intel_display_power_put(dev_priv, domain);
4962
4963                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4964         }
4965
4966         intel_display_set_init_power(dev_priv, false);
4967 }
4968
4969 /* returns HPLL frequency in kHz */
4970 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4971 {
4972         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4973
4974         /* Obtain SKU information */
4975         mutex_lock(&dev_priv->dpio_lock);
4976         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4977                 CCK_FUSE_HPLL_FREQ_MASK;
4978         mutex_unlock(&dev_priv->dpio_lock);
4979
4980         return vco_freq[hpll_freq] * 1000;
4981 }
4982
4983 static void vlv_update_cdclk(struct drm_device *dev)
4984 {
4985         struct drm_i915_private *dev_priv = dev->dev_private;
4986
4987         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4988         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4989                          dev_priv->vlv_cdclk_freq);
4990
4991         /*
4992          * Program the gmbus_freq based on the cdclk frequency.
4993          * BSpec erroneously claims we should aim for 4MHz, but
4994          * in fact 1MHz is the correct frequency.
4995          */
4996         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4997 }
4998
4999 /* Adjust CDclk dividers to allow high res or save power if possible */
5000 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5001 {
5002         struct drm_i915_private *dev_priv = dev->dev_private;
5003         u32 val, cmd;
5004
5005         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5006
5007         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5008                 cmd = 2;
5009         else if (cdclk == 266667)
5010                 cmd = 1;
5011         else
5012                 cmd = 0;
5013
5014         mutex_lock(&dev_priv->rps.hw_lock);
5015         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5016         val &= ~DSPFREQGUAR_MASK;
5017         val |= (cmd << DSPFREQGUAR_SHIFT);
5018         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5019         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5020                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5021                      50)) {
5022                 DRM_ERROR("timed out waiting for CDclk change\n");
5023         }
5024         mutex_unlock(&dev_priv->rps.hw_lock);
5025
5026         if (cdclk == 400000) {
5027                 u32 divider;
5028
5029                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5030
5031                 mutex_lock(&dev_priv->dpio_lock);
5032                 /* adjust cdclk divider */
5033                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5034                 val &= ~DISPLAY_FREQUENCY_VALUES;
5035                 val |= divider;
5036                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5037
5038                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5039                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5040                              50))
5041                         DRM_ERROR("timed out waiting for CDclk change\n");
5042                 mutex_unlock(&dev_priv->dpio_lock);
5043         }
5044
5045         mutex_lock(&dev_priv->dpio_lock);
5046         /* adjust self-refresh exit latency value */
5047         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5048         val &= ~0x7f;
5049
5050         /*
5051          * For high bandwidth configs, we set a higher latency in the bunit
5052          * so that the core display fetch happens in time to avoid underruns.
5053          */
5054         if (cdclk == 400000)
5055                 val |= 4500 / 250; /* 4.5 usec */
5056         else
5057                 val |= 3000 / 250; /* 3.0 usec */
5058         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5059         mutex_unlock(&dev_priv->dpio_lock);
5060
5061         vlv_update_cdclk(dev);
5062 }
5063
5064 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5065 {
5066         struct drm_i915_private *dev_priv = dev->dev_private;
5067         u32 val, cmd;
5068
5069         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5070
5071         switch (cdclk) {
5072         case 333333:
5073         case 320000:
5074         case 266667:
5075         case 200000:
5076                 break;
5077         default:
5078                 MISSING_CASE(cdclk);
5079                 return;
5080         }
5081
5082         /*
5083          * Specs are full of misinformation, but testing on actual
5084          * hardware has shown that we just need to write the desired
5085          * CCK divider into the Punit register.
5086          */
5087         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5088
5089         mutex_lock(&dev_priv->rps.hw_lock);
5090         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5091         val &= ~DSPFREQGUAR_MASK_CHV;
5092         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5093         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5094         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5095                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5096                      50)) {
5097                 DRM_ERROR("timed out waiting for CDclk change\n");
5098         }
5099         mutex_unlock(&dev_priv->rps.hw_lock);
5100
5101         vlv_update_cdclk(dev);
5102 }
5103
5104 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5105                                  int max_pixclk)
5106 {
5107         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5108         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5109
5110         /*
5111          * Really only a few cases to deal with, as only 4 CDclks are supported:
5112          *   200MHz
5113          *   267MHz
5114          *   320/333MHz (depends on HPLL freq)
5115          *   400MHz (VLV only)
5116          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5117          * of the lower bin and adjust if needed.
5118          *
5119          * We seem to get an unstable or solid color picture at 200MHz.
5120          * Not sure what's wrong. For now use 200MHz only when all pipes
5121          * are off.
5122          */
5123         if (!IS_CHERRYVIEW(dev_priv) &&
5124             max_pixclk > freq_320*limit/100)
5125                 return 400000;
5126         else if (max_pixclk > 266667*limit/100)
5127                 return freq_320;
5128         else if (max_pixclk > 0)
5129                 return 266667;
5130         else
5131                 return 200000;
5132 }
5133
5134 /* compute the max pixel clock for new configuration */
5135 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5136 {
5137         struct drm_device *dev = dev_priv->dev;
5138         struct intel_crtc *intel_crtc;
5139         int max_pixclk = 0;
5140
5141         for_each_intel_crtc(dev, intel_crtc) {
5142                 if (intel_crtc->new_enabled)
5143                         max_pixclk = max(max_pixclk,
5144                                          intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5145         }
5146
5147         return max_pixclk;
5148 }
5149
5150 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5151                                             unsigned *prepare_pipes)
5152 {
5153         struct drm_i915_private *dev_priv = dev->dev_private;
5154         struct intel_crtc *intel_crtc;
5155         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5156
5157         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5158             dev_priv->vlv_cdclk_freq)
5159                 return;
5160
5161         /* disable/enable all currently active pipes while we change cdclk */
5162         for_each_intel_crtc(dev, intel_crtc)
5163                 if (intel_crtc->base.state->enable)
5164                         *prepare_pipes |= (1 << intel_crtc->pipe);
5165 }
5166
5167 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5168 {
5169         unsigned int credits, default_credits;
5170
5171         if (IS_CHERRYVIEW(dev_priv))
5172                 default_credits = PFI_CREDIT(12);
5173         else
5174                 default_credits = PFI_CREDIT(8);
5175
5176         if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5177                 /* CHV suggested value is 31 or 63 */
5178                 if (IS_CHERRYVIEW(dev_priv))
5179                         credits = PFI_CREDIT_31;
5180                 else
5181                         credits = PFI_CREDIT(15);
5182         } else {
5183                 credits = default_credits;
5184         }
5185
5186         /*
5187          * WA - write default credits before re-programming
5188          * FIXME: should we also set the resend bit here?
5189          */
5190         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5191                    default_credits);
5192
5193         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5194                    credits | PFI_CREDIT_RESEND);
5195
5196         /*
5197          * FIXME is this guaranteed to clear
5198          * immediately or should we poll for it?
5199          */
5200         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5201 }
5202
5203 static void valleyview_modeset_global_resources(struct drm_device *dev)
5204 {
5205         struct drm_i915_private *dev_priv = dev->dev_private;
5206         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5207         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5208
5209         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5210                 /*
5211                  * FIXME: We can end up here with all power domains off, yet
5212                  * with a CDCLK frequency other than the minimum. To account
5213                  * for this take the PIPE-A power domain, which covers the HW
5214                  * blocks needed for the following programming. This can be
5215                  * removed once it's guaranteed that we get here either with
5216                  * the minimum CDCLK set, or the required power domains
5217                  * enabled.
5218                  */
5219                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5220
5221                 if (IS_CHERRYVIEW(dev))
5222                         cherryview_set_cdclk(dev, req_cdclk);
5223                 else
5224                         valleyview_set_cdclk(dev, req_cdclk);
5225
5226                 vlv_program_pfi_credits(dev_priv);
5227
5228                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5229         }
5230 }
5231
5232 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5233 {
5234         struct drm_device *dev = crtc->dev;
5235         struct drm_i915_private *dev_priv = to_i915(dev);
5236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237         struct intel_encoder *encoder;
5238         int pipe = intel_crtc->pipe;
5239         bool is_dsi;
5240
5241         WARN_ON(!crtc->state->enable);
5242
5243         if (intel_crtc->active)
5244                 return;
5245
5246         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5247
5248         if (!is_dsi) {
5249                 if (IS_CHERRYVIEW(dev))
5250                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5251                 else
5252                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5253         }
5254
5255         if (intel_crtc->config->has_dp_encoder)
5256                 intel_dp_set_m_n(intel_crtc, M1_N1);
5257
5258         intel_set_pipe_timings(intel_crtc);
5259
5260         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5261                 struct drm_i915_private *dev_priv = dev->dev_private;
5262
5263                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5264                 I915_WRITE(CHV_CANVAS(pipe), 0);
5265         }
5266
5267         i9xx_set_pipeconf(intel_crtc);
5268
5269         intel_crtc->active = true;
5270
5271         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5272
5273         for_each_encoder_on_crtc(dev, crtc, encoder)
5274                 if (encoder->pre_pll_enable)
5275                         encoder->pre_pll_enable(encoder);
5276
5277         if (!is_dsi) {
5278                 if (IS_CHERRYVIEW(dev))
5279                         chv_enable_pll(intel_crtc, intel_crtc->config);
5280                 else
5281                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5282         }
5283
5284         for_each_encoder_on_crtc(dev, crtc, encoder)
5285                 if (encoder->pre_enable)
5286                         encoder->pre_enable(encoder);
5287
5288         i9xx_pfit_enable(intel_crtc);
5289
5290         intel_crtc_load_lut(crtc);
5291
5292         intel_update_watermarks(crtc);
5293         intel_enable_pipe(intel_crtc);
5294
5295         assert_vblank_disabled(crtc);
5296         drm_crtc_vblank_on(crtc);
5297
5298         for_each_encoder_on_crtc(dev, crtc, encoder)
5299                 encoder->enable(encoder);
5300
5301         intel_crtc_enable_planes(crtc);
5302
5303         /* Underruns don't raise interrupts, so check manually. */
5304         i9xx_check_fifo_underruns(dev_priv);
5305 }
5306
5307 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5308 {
5309         struct drm_device *dev = crtc->base.dev;
5310         struct drm_i915_private *dev_priv = dev->dev_private;
5311
5312         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5313         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5314 }
5315
5316 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5317 {
5318         struct drm_device *dev = crtc->dev;
5319         struct drm_i915_private *dev_priv = to_i915(dev);
5320         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5321         struct intel_encoder *encoder;
5322         int pipe = intel_crtc->pipe;
5323
5324         WARN_ON(!crtc->state->enable);
5325
5326         if (intel_crtc->active)
5327                 return;
5328
5329         i9xx_set_pll_dividers(intel_crtc);
5330
5331         if (intel_crtc->config->has_dp_encoder)
5332                 intel_dp_set_m_n(intel_crtc, M1_N1);
5333
5334         intel_set_pipe_timings(intel_crtc);
5335
5336         i9xx_set_pipeconf(intel_crtc);
5337
5338         intel_crtc->active = true;
5339
5340         if (!IS_GEN2(dev))
5341                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5342
5343         for_each_encoder_on_crtc(dev, crtc, encoder)
5344                 if (encoder->pre_enable)
5345                         encoder->pre_enable(encoder);
5346
5347         i9xx_enable_pll(intel_crtc);
5348
5349         i9xx_pfit_enable(intel_crtc);
5350
5351         intel_crtc_load_lut(crtc);
5352
5353         intel_update_watermarks(crtc);
5354         intel_enable_pipe(intel_crtc);
5355
5356         assert_vblank_disabled(crtc);
5357         drm_crtc_vblank_on(crtc);
5358
5359         for_each_encoder_on_crtc(dev, crtc, encoder)
5360                 encoder->enable(encoder);
5361
5362         intel_crtc_enable_planes(crtc);
5363
5364         /*
5365          * Gen2 reports pipe underruns whenever all planes are disabled.
5366          * So don't enable underrun reporting before at least some planes
5367          * are enabled.
5368          * FIXME: Need to fix the logic to work when we turn off all planes
5369          * but leave the pipe running.
5370          */
5371         if (IS_GEN2(dev))
5372                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5373
5374         /* Underruns don't raise interrupts, so check manually. */
5375         i9xx_check_fifo_underruns(dev_priv);
5376 }
5377
5378 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5379 {
5380         struct drm_device *dev = crtc->base.dev;
5381         struct drm_i915_private *dev_priv = dev->dev_private;
5382
5383         if (!crtc->config->gmch_pfit.control)
5384                 return;
5385
5386         assert_pipe_disabled(dev_priv, crtc->pipe);
5387
5388         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5389                          I915_READ(PFIT_CONTROL));
5390         I915_WRITE(PFIT_CONTROL, 0);
5391 }
5392
5393 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5394 {
5395         struct drm_device *dev = crtc->dev;
5396         struct drm_i915_private *dev_priv = dev->dev_private;
5397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5398         struct intel_encoder *encoder;
5399         int pipe = intel_crtc->pipe;
5400
5401         if (!intel_crtc->active)
5402                 return;
5403
5404         /*
5405          * Gen2 reports pipe underruns whenever all planes are disabled.
5406          * So diasble underrun reporting before all the planes get disabled.
5407          * FIXME: Need to fix the logic to work when we turn off all planes
5408          * but leave the pipe running.
5409          */
5410         if (IS_GEN2(dev))
5411                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5412
5413         /*
5414          * Vblank time updates from the shadow to live plane control register
5415          * are blocked if the memory self-refresh mode is active at that
5416          * moment. So to make sure the plane gets truly disabled, disable
5417          * first the self-refresh mode. The self-refresh enable bit in turn
5418          * will be checked/applied by the HW only at the next frame start
5419          * event which is after the vblank start event, so we need to have a
5420          * wait-for-vblank between disabling the plane and the pipe.
5421          */
5422         intel_set_memory_cxsr(dev_priv, false);
5423         intel_crtc_disable_planes(crtc);
5424
5425         /*
5426          * On gen2 planes are double buffered but the pipe isn't, so we must
5427          * wait for planes to fully turn off before disabling the pipe.
5428          * We also need to wait on all gmch platforms because of the
5429          * self-refresh mode constraint explained above.
5430          */
5431         intel_wait_for_vblank(dev, pipe);
5432
5433         for_each_encoder_on_crtc(dev, crtc, encoder)
5434                 encoder->disable(encoder);
5435
5436         drm_crtc_vblank_off(crtc);
5437         assert_vblank_disabled(crtc);
5438
5439         intel_disable_pipe(intel_crtc);
5440
5441         i9xx_pfit_disable(intel_crtc);
5442
5443         for_each_encoder_on_crtc(dev, crtc, encoder)
5444                 if (encoder->post_disable)
5445                         encoder->post_disable(encoder);
5446
5447         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5448                 if (IS_CHERRYVIEW(dev))
5449                         chv_disable_pll(dev_priv, pipe);
5450                 else if (IS_VALLEYVIEW(dev))
5451                         vlv_disable_pll(dev_priv, pipe);
5452                 else
5453                         i9xx_disable_pll(intel_crtc);
5454         }
5455
5456         if (!IS_GEN2(dev))
5457                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5458
5459         intel_crtc->active = false;
5460         intel_update_watermarks(crtc);
5461
5462         mutex_lock(&dev->struct_mutex);
5463         intel_fbc_update(dev);
5464         mutex_unlock(&dev->struct_mutex);
5465 }
5466
5467 static void i9xx_crtc_off(struct drm_crtc *crtc)
5468 {
5469 }
5470
5471 /* Master function to enable/disable CRTC and corresponding power wells */
5472 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5473 {
5474         struct drm_device *dev = crtc->dev;
5475         struct drm_i915_private *dev_priv = dev->dev_private;
5476         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5477         enum intel_display_power_domain domain;
5478         unsigned long domains;
5479
5480         if (enable) {
5481                 if (!intel_crtc->active) {
5482                         domains = get_crtc_power_domains(crtc);
5483                         for_each_power_domain(domain, domains)
5484                                 intel_display_power_get(dev_priv, domain);
5485                         intel_crtc->enabled_power_domains = domains;
5486
5487                         dev_priv->display.crtc_enable(crtc);
5488                 }
5489         } else {
5490                 if (intel_crtc->active) {
5491                         dev_priv->display.crtc_disable(crtc);
5492
5493                         domains = intel_crtc->enabled_power_domains;
5494                         for_each_power_domain(domain, domains)
5495                                 intel_display_power_put(dev_priv, domain);
5496                         intel_crtc->enabled_power_domains = 0;
5497                 }
5498         }
5499 }
5500
5501 /**
5502  * Sets the power management mode of the pipe and plane.
5503  */
5504 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5505 {
5506         struct drm_device *dev = crtc->dev;
5507         struct intel_encoder *intel_encoder;
5508         bool enable = false;
5509
5510         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5511                 enable |= intel_encoder->connectors_active;
5512
5513         intel_crtc_control(crtc, enable);
5514 }
5515
5516 static void intel_crtc_disable(struct drm_crtc *crtc)
5517 {
5518         struct drm_device *dev = crtc->dev;
5519         struct drm_connector *connector;
5520         struct drm_i915_private *dev_priv = dev->dev_private;
5521
5522         /* crtc should still be enabled when we disable it. */
5523         WARN_ON(!crtc->state->enable);
5524
5525         dev_priv->display.crtc_disable(crtc);
5526         dev_priv->display.off(crtc);
5527
5528         crtc->primary->funcs->disable_plane(crtc->primary);
5529
5530         /* Update computed state. */
5531         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5532                 if (!connector->encoder || !connector->encoder->crtc)
5533                         continue;
5534
5535                 if (connector->encoder->crtc != crtc)
5536                         continue;
5537
5538                 connector->dpms = DRM_MODE_DPMS_OFF;
5539                 to_intel_encoder(connector->encoder)->connectors_active = false;
5540         }
5541 }
5542
5543 void intel_encoder_destroy(struct drm_encoder *encoder)
5544 {
5545         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5546
5547         drm_encoder_cleanup(encoder);
5548         kfree(intel_encoder);
5549 }
5550
5551 /* Simple dpms helper for encoders with just one connector, no cloning and only
5552  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5553  * state of the entire output pipe. */
5554 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5555 {
5556         if (mode == DRM_MODE_DPMS_ON) {
5557                 encoder->connectors_active = true;
5558
5559                 intel_crtc_update_dpms(encoder->base.crtc);
5560         } else {
5561                 encoder->connectors_active = false;
5562
5563                 intel_crtc_update_dpms(encoder->base.crtc);
5564         }
5565 }
5566
5567 /* Cross check the actual hw state with our own modeset state tracking (and it's
5568  * internal consistency). */
5569 static void intel_connector_check_state(struct intel_connector *connector)
5570 {
5571         if (connector->get_hw_state(connector)) {
5572                 struct intel_encoder *encoder = connector->encoder;
5573                 struct drm_crtc *crtc;
5574                 bool encoder_enabled;
5575                 enum pipe pipe;
5576
5577                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5578                               connector->base.base.id,
5579                               connector->base.name);
5580
5581                 /* there is no real hw state for MST connectors */
5582                 if (connector->mst_port)
5583                         return;
5584
5585                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5586                      "wrong connector dpms state\n");
5587                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5588                      "active connector not linked to encoder\n");
5589
5590                 if (encoder) {
5591                         I915_STATE_WARN(!encoder->connectors_active,
5592                              "encoder->connectors_active not set\n");
5593
5594                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5595                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5596                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
5597                                 return;
5598
5599                         crtc = encoder->base.crtc;
5600
5601                         I915_STATE_WARN(!crtc->state->enable,
5602                                         "crtc not enabled\n");
5603                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5604                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5605                              "encoder active on the wrong pipe\n");
5606                 }
5607         }
5608 }
5609
5610 /* Even simpler default implementation, if there's really no special case to
5611  * consider. */
5612 void intel_connector_dpms(struct drm_connector *connector, int mode)
5613 {
5614         /* All the simple cases only support two dpms states. */
5615         if (mode != DRM_MODE_DPMS_ON)
5616                 mode = DRM_MODE_DPMS_OFF;
5617
5618         if (mode == connector->dpms)
5619                 return;
5620
5621         connector->dpms = mode;
5622
5623         /* Only need to change hw state when actually enabled */
5624         if (connector->encoder)
5625                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5626
5627         intel_modeset_check_state(connector->dev);
5628 }
5629
5630 /* Simple connector->get_hw_state implementation for encoders that support only
5631  * one connector and no cloning and hence the encoder state determines the state
5632  * of the connector. */
5633 bool intel_connector_get_hw_state(struct intel_connector *connector)
5634 {
5635         enum pipe pipe = 0;
5636         struct intel_encoder *encoder = connector->encoder;
5637
5638         return encoder->get_hw_state(encoder, &pipe);
5639 }
5640
5641 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5642 {
5643         struct intel_crtc *crtc =
5644                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5645
5646         if (crtc->base.state->enable &&
5647             crtc->config->has_pch_encoder)
5648                 return crtc->config->fdi_lanes;
5649
5650         return 0;
5651 }
5652
5653 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5654                                      struct intel_crtc_state *pipe_config)
5655 {
5656         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5657                       pipe_name(pipe), pipe_config->fdi_lanes);
5658         if (pipe_config->fdi_lanes > 4) {
5659                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5660                               pipe_name(pipe), pipe_config->fdi_lanes);
5661                 return false;
5662         }
5663
5664         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5665                 if (pipe_config->fdi_lanes > 2) {
5666                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5667                                       pipe_config->fdi_lanes);
5668                         return false;
5669                 } else {
5670                         return true;
5671                 }
5672         }
5673
5674         if (INTEL_INFO(dev)->num_pipes == 2)
5675                 return true;
5676
5677         /* Ivybridge 3 pipe is really complicated */
5678         switch (pipe) {
5679         case PIPE_A:
5680                 return true;
5681         case PIPE_B:
5682                 if (pipe_config->fdi_lanes > 2 &&
5683                     pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5684                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5685                                       pipe_name(pipe), pipe_config->fdi_lanes);
5686                         return false;
5687                 }
5688                 return true;
5689         case PIPE_C:
5690                 if (pipe_config->fdi_lanes > 2) {
5691                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5692                                       pipe_name(pipe), pipe_config->fdi_lanes);
5693                         return false;
5694                 }
5695                 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5696                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5697                         return false;
5698                 }
5699                 return true;
5700         default:
5701                 BUG();
5702         }
5703 }
5704
5705 #define RETRY 1
5706 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5707                                        struct intel_crtc_state *pipe_config)
5708 {
5709         struct drm_device *dev = intel_crtc->base.dev;
5710         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5711         int lane, link_bw, fdi_dotclock;
5712         bool setup_ok, needs_recompute = false;
5713
5714 retry:
5715         /* FDI is a binary signal running at ~2.7GHz, encoding
5716          * each output octet as 10 bits. The actual frequency
5717          * is stored as a divider into a 100MHz clock, and the
5718          * mode pixel clock is stored in units of 1KHz.
5719          * Hence the bw of each lane in terms of the mode signal
5720          * is:
5721          */
5722         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5723
5724         fdi_dotclock = adjusted_mode->crtc_clock;
5725
5726         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5727                                            pipe_config->pipe_bpp);
5728
5729         pipe_config->fdi_lanes = lane;
5730
5731         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5732                                link_bw, &pipe_config->fdi_m_n);
5733
5734         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5735                                             intel_crtc->pipe, pipe_config);
5736         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5737                 pipe_config->pipe_bpp -= 2*3;
5738                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5739                               pipe_config->pipe_bpp);
5740                 needs_recompute = true;
5741                 pipe_config->bw_constrained = true;
5742
5743                 goto retry;
5744         }
5745
5746         if (needs_recompute)
5747                 return RETRY;
5748
5749         return setup_ok ? 0 : -EINVAL;
5750 }
5751
5752 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5753                                    struct intel_crtc_state *pipe_config)
5754 {
5755         pipe_config->ips_enabled = i915.enable_ips &&
5756                                    hsw_crtc_supports_ips(crtc) &&
5757                                    pipe_config->pipe_bpp <= 24;
5758 }
5759
5760 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5761                                      struct intel_crtc_state *pipe_config)
5762 {
5763         struct drm_device *dev = crtc->base.dev;
5764         struct drm_i915_private *dev_priv = dev->dev_private;
5765         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5766
5767         /* FIXME should check pixel clock limits on all platforms */
5768         if (INTEL_INFO(dev)->gen < 4) {
5769                 int clock_limit =
5770                         dev_priv->display.get_display_clock_speed(dev);
5771
5772                 /*
5773                  * Enable pixel doubling when the dot clock
5774                  * is > 90% of the (display) core speed.
5775                  *
5776                  * GDG double wide on either pipe,
5777                  * otherwise pipe A only.
5778                  */
5779                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5780                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5781                         clock_limit *= 2;
5782                         pipe_config->double_wide = true;
5783                 }
5784
5785                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5786                         return -EINVAL;
5787         }
5788
5789         /*
5790          * Pipe horizontal size must be even in:
5791          * - DVO ganged mode
5792          * - LVDS dual channel mode
5793          * - Double wide pipe
5794          */
5795         if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5796              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5797                 pipe_config->pipe_src_w &= ~1;
5798
5799         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5800          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5801          */
5802         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5803                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5804                 return -EINVAL;
5805
5806         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5807                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5808         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5809                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5810                  * for lvds. */
5811                 pipe_config->pipe_bpp = 8*3;
5812         }
5813
5814         if (HAS_IPS(dev))
5815                 hsw_compute_ips_config(crtc, pipe_config);
5816
5817         if (pipe_config->has_pch_encoder)
5818                 return ironlake_fdi_compute_config(crtc, pipe_config);
5819
5820         return 0;
5821 }
5822
5823 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5824 {
5825         struct drm_i915_private *dev_priv = dev->dev_private;
5826         u32 val;
5827         int divider;
5828
5829         if (dev_priv->hpll_freq == 0)
5830                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5831
5832         mutex_lock(&dev_priv->dpio_lock);
5833         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5834         mutex_unlock(&dev_priv->dpio_lock);
5835
5836         divider = val & DISPLAY_FREQUENCY_VALUES;
5837
5838         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5839              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5840              "cdclk change in progress\n");
5841
5842         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5843 }
5844
5845 static int i945_get_display_clock_speed(struct drm_device *dev)
5846 {
5847         return 400000;
5848 }
5849
5850 static int i915_get_display_clock_speed(struct drm_device *dev)
5851 {
5852         return 333000;
5853 }
5854
5855 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5856 {
5857         return 200000;
5858 }
5859
5860 static int pnv_get_display_clock_speed(struct drm_device *dev)
5861 {
5862         u16 gcfgc = 0;
5863
5864         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5865
5866         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5867         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5868                 return 267000;
5869         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5870                 return 333000;
5871         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5872                 return 444000;
5873         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5874                 return 200000;
5875         default:
5876                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5877         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5878                 return 133000;
5879         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5880                 return 167000;
5881         }
5882 }
5883
5884 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5885 {
5886         u16 gcfgc = 0;
5887
5888         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5889
5890         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5891                 return 133000;
5892         else {
5893                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5894                 case GC_DISPLAY_CLOCK_333_MHZ:
5895                         return 333000;
5896                 default:
5897                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5898                         return 190000;
5899                 }
5900         }
5901 }
5902
5903 static int i865_get_display_clock_speed(struct drm_device *dev)
5904 {
5905         return 266000;
5906 }
5907
5908 static int i855_get_display_clock_speed(struct drm_device *dev)
5909 {
5910         u16 hpllcc = 0;
5911         /* Assume that the hardware is in the high speed state.  This
5912          * should be the default.
5913          */
5914         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5915         case GC_CLOCK_133_200:
5916         case GC_CLOCK_100_200:
5917                 return 200000;
5918         case GC_CLOCK_166_250:
5919                 return 250000;
5920         case GC_CLOCK_100_133:
5921                 return 133000;
5922         }
5923
5924         /* Shouldn't happen */
5925         return 0;
5926 }
5927
5928 static int i830_get_display_clock_speed(struct drm_device *dev)
5929 {
5930         return 133000;
5931 }
5932
5933 static void
5934 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5935 {
5936         while (*num > DATA_LINK_M_N_MASK ||
5937                *den > DATA_LINK_M_N_MASK) {
5938                 *num >>= 1;
5939                 *den >>= 1;
5940         }
5941 }
5942
5943 static void compute_m_n(unsigned int m, unsigned int n,
5944                         uint32_t *ret_m, uint32_t *ret_n)
5945 {
5946         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5947         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5948         intel_reduce_m_n_ratio(ret_m, ret_n);
5949 }
5950
5951 void
5952 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5953                        int pixel_clock, int link_clock,
5954                        struct intel_link_m_n *m_n)
5955 {
5956         m_n->tu = 64;
5957
5958         compute_m_n(bits_per_pixel * pixel_clock,
5959                     link_clock * nlanes * 8,
5960                     &m_n->gmch_m, &m_n->gmch_n);
5961
5962         compute_m_n(pixel_clock, link_clock,
5963                     &m_n->link_m, &m_n->link_n);
5964 }
5965
5966 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5967 {
5968         if (i915.panel_use_ssc >= 0)
5969                 return i915.panel_use_ssc != 0;
5970         return dev_priv->vbt.lvds_use_ssc
5971                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5972 }
5973
5974 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5975 {
5976         struct drm_device *dev = crtc->base.dev;
5977         struct drm_i915_private *dev_priv = dev->dev_private;
5978         int refclk;
5979
5980         if (IS_VALLEYVIEW(dev)) {
5981                 refclk = 100000;
5982         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5983             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5984                 refclk = dev_priv->vbt.lvds_ssc_freq;
5985                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5986         } else if (!IS_GEN2(dev)) {
5987                 refclk = 96000;
5988         } else {
5989                 refclk = 48000;
5990         }
5991
5992         return refclk;
5993 }
5994
5995 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5996 {
5997         return (1 << dpll->n) << 16 | dpll->m2;
5998 }
5999
6000 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6001 {
6002         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6003 }
6004
6005 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6006                                      struct intel_crtc_state *crtc_state,
6007                                      intel_clock_t *reduced_clock)
6008 {
6009         struct drm_device *dev = crtc->base.dev;
6010         u32 fp, fp2 = 0;
6011
6012         if (IS_PINEVIEW(dev)) {
6013                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6014                 if (reduced_clock)
6015                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6016         } else {
6017                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6018                 if (reduced_clock)
6019                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6020         }
6021
6022         crtc_state->dpll_hw_state.fp0 = fp;
6023
6024         crtc->lowfreq_avail = false;
6025         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6026             reduced_clock) {
6027                 crtc_state->dpll_hw_state.fp1 = fp2;
6028                 crtc->lowfreq_avail = true;
6029         } else {
6030                 crtc_state->dpll_hw_state.fp1 = fp;
6031         }
6032 }
6033
6034 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6035                 pipe)
6036 {
6037         u32 reg_val;
6038
6039         /*
6040          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6041          * and set it to a reasonable value instead.
6042          */
6043         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6044         reg_val &= 0xffffff00;
6045         reg_val |= 0x00000030;
6046         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6047
6048         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6049         reg_val &= 0x8cffffff;
6050         reg_val = 0x8c000000;
6051         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6052
6053         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6054         reg_val &= 0xffffff00;
6055         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6056
6057         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6058         reg_val &= 0x00ffffff;
6059         reg_val |= 0xb0000000;
6060         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6061 }
6062
6063 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6064                                          struct intel_link_m_n *m_n)
6065 {
6066         struct drm_device *dev = crtc->base.dev;
6067         struct drm_i915_private *dev_priv = dev->dev_private;
6068         int pipe = crtc->pipe;
6069
6070         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6071         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6072         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6073         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6074 }
6075
6076 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6077                                          struct intel_link_m_n *m_n,
6078                                          struct intel_link_m_n *m2_n2)
6079 {
6080         struct drm_device *dev = crtc->base.dev;
6081         struct drm_i915_private *dev_priv = dev->dev_private;
6082         int pipe = crtc->pipe;
6083         enum transcoder transcoder = crtc->config->cpu_transcoder;
6084
6085         if (INTEL_INFO(dev)->gen >= 5) {
6086                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6087                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6088                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6089                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6090                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6091                  * for gen < 8) and if DRRS is supported (to make sure the
6092                  * registers are not unnecessarily accessed).
6093                  */
6094                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6095                         crtc->config->has_drrs) {
6096                         I915_WRITE(PIPE_DATA_M2(transcoder),
6097                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6098                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6099                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6100                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6101                 }
6102         } else {
6103                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6104                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6105                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6106                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6107         }
6108 }
6109
6110 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6111 {
6112         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6113
6114         if (m_n == M1_N1) {
6115                 dp_m_n = &crtc->config->dp_m_n;
6116                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6117         } else if (m_n == M2_N2) {
6118
6119                 /*
6120                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6121                  * needs to be programmed into M1_N1.
6122                  */
6123                 dp_m_n = &crtc->config->dp_m2_n2;
6124         } else {
6125                 DRM_ERROR("Unsupported divider value\n");
6126                 return;
6127         }
6128
6129         if (crtc->config->has_pch_encoder)
6130                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6131         else
6132                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6133 }
6134
6135 static void vlv_update_pll(struct intel_crtc *crtc,
6136                            struct intel_crtc_state *pipe_config)
6137 {
6138         u32 dpll, dpll_md;
6139
6140         /*
6141          * Enable DPIO clock input. We should never disable the reference
6142          * clock for pipe B, since VGA hotplug / manual detection depends
6143          * on it.
6144          */
6145         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6146                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6147         /* We should never disable this, set it here for state tracking */
6148         if (crtc->pipe == PIPE_B)
6149                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6150         dpll |= DPLL_VCO_ENABLE;
6151         pipe_config->dpll_hw_state.dpll = dpll;
6152
6153         dpll_md = (pipe_config->pixel_multiplier - 1)
6154                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6155         pipe_config->dpll_hw_state.dpll_md = dpll_md;
6156 }
6157
6158 static void vlv_prepare_pll(struct intel_crtc *crtc,
6159                             const struct intel_crtc_state *pipe_config)
6160 {
6161         struct drm_device *dev = crtc->base.dev;
6162         struct drm_i915_private *dev_priv = dev->dev_private;
6163         int pipe = crtc->pipe;
6164         u32 mdiv;
6165         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6166         u32 coreclk, reg_val;
6167
6168         mutex_lock(&dev_priv->dpio_lock);
6169
6170         bestn = pipe_config->dpll.n;
6171         bestm1 = pipe_config->dpll.m1;
6172         bestm2 = pipe_config->dpll.m2;
6173         bestp1 = pipe_config->dpll.p1;
6174         bestp2 = pipe_config->dpll.p2;
6175
6176         /* See eDP HDMI DPIO driver vbios notes doc */
6177
6178         /* PLL B needs special handling */
6179         if (pipe == PIPE_B)
6180                 vlv_pllb_recal_opamp(dev_priv, pipe);
6181
6182         /* Set up Tx target for periodic Rcomp update */
6183         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6184
6185         /* Disable target IRef on PLL */
6186         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6187         reg_val &= 0x00ffffff;
6188         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6189
6190         /* Disable fast lock */
6191         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6192
6193         /* Set idtafcrecal before PLL is enabled */
6194         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6195         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6196         mdiv |= ((bestn << DPIO_N_SHIFT));
6197         mdiv |= (1 << DPIO_K_SHIFT);
6198
6199         /*
6200          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6201          * but we don't support that).
6202          * Note: don't use the DAC post divider as it seems unstable.
6203          */
6204         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6205         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6206
6207         mdiv |= DPIO_ENABLE_CALIBRATION;
6208         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6209
6210         /* Set HBR and RBR LPF coefficients */
6211         if (pipe_config->port_clock == 162000 ||
6212             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6213             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6214                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6215                                  0x009f0003);
6216         else
6217                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6218                                  0x00d0000f);
6219
6220         if (pipe_config->has_dp_encoder) {
6221                 /* Use SSC source */
6222                 if (pipe == PIPE_A)
6223                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6224                                          0x0df40000);
6225                 else
6226                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6227                                          0x0df70000);
6228         } else { /* HDMI or VGA */
6229                 /* Use bend source */
6230                 if (pipe == PIPE_A)
6231                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6232                                          0x0df70000);
6233                 else
6234                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6235                                          0x0df40000);
6236         }
6237
6238         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6239         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6240         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6241             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6242                 coreclk |= 0x01000000;
6243         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6244
6245         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6246         mutex_unlock(&dev_priv->dpio_lock);
6247 }
6248
6249 static void chv_update_pll(struct intel_crtc *crtc,
6250                            struct intel_crtc_state *pipe_config)
6251 {
6252         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6253                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6254                 DPLL_VCO_ENABLE;
6255         if (crtc->pipe != PIPE_A)
6256                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6257
6258         pipe_config->dpll_hw_state.dpll_md =
6259                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6260 }
6261
6262 static void chv_prepare_pll(struct intel_crtc *crtc,
6263                             const struct intel_crtc_state *pipe_config)
6264 {
6265         struct drm_device *dev = crtc->base.dev;
6266         struct drm_i915_private *dev_priv = dev->dev_private;
6267         int pipe = crtc->pipe;
6268         int dpll_reg = DPLL(crtc->pipe);
6269         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6270         u32 loopfilter, tribuf_calcntr;
6271         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6272         u32 dpio_val;
6273         int vco;
6274
6275         bestn = pipe_config->dpll.n;
6276         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6277         bestm1 = pipe_config->dpll.m1;
6278         bestm2 = pipe_config->dpll.m2 >> 22;
6279         bestp1 = pipe_config->dpll.p1;
6280         bestp2 = pipe_config->dpll.p2;
6281         vco = pipe_config->dpll.vco;
6282         dpio_val = 0;
6283         loopfilter = 0;
6284
6285         /*
6286          * Enable Refclk and SSC
6287          */
6288         I915_WRITE(dpll_reg,
6289                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6290
6291         mutex_lock(&dev_priv->dpio_lock);
6292
6293         /* p1 and p2 divider */
6294         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6295                         5 << DPIO_CHV_S1_DIV_SHIFT |
6296                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6297                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6298                         1 << DPIO_CHV_K_DIV_SHIFT);
6299
6300         /* Feedback post-divider - m2 */
6301         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6302
6303         /* Feedback refclk divider - n and m1 */
6304         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6305                         DPIO_CHV_M1_DIV_BY_2 |
6306                         1 << DPIO_CHV_N_DIV_SHIFT);
6307
6308         /* M2 fraction division */
6309         if (bestm2_frac)
6310                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6311
6312         /* M2 fraction division enable */
6313         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6314         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6315         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6316         if (bestm2_frac)
6317                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6318         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6319
6320         /* Program digital lock detect threshold */
6321         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6322         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6323                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6324         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6325         if (!bestm2_frac)
6326                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6327         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6328
6329         /* Loop filter */
6330         if (vco == 5400000) {
6331                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6332                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6333                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6334                 tribuf_calcntr = 0x9;
6335         } else if (vco <= 6200000) {
6336                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6337                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6338                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6339                 tribuf_calcntr = 0x9;
6340         } else if (vco <= 6480000) {
6341                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6342                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6343                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6344                 tribuf_calcntr = 0x8;
6345         } else {
6346                 /* Not supported. Apply the same limits as in the max case */
6347                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6348                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6349                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6350                 tribuf_calcntr = 0;
6351         }
6352         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6353
6354         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6355         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6356         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6357         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6358
6359         /* AFC Recal */
6360         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6361                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6362                         DPIO_AFC_RECAL);
6363
6364         mutex_unlock(&dev_priv->dpio_lock);
6365 }
6366
6367 /**
6368  * vlv_force_pll_on - forcibly enable just the PLL
6369  * @dev_priv: i915 private structure
6370  * @pipe: pipe PLL to enable
6371  * @dpll: PLL configuration
6372  *
6373  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6374  * in cases where we need the PLL enabled even when @pipe is not going to
6375  * be enabled.
6376  */
6377 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6378                       const struct dpll *dpll)
6379 {
6380         struct intel_crtc *crtc =
6381                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6382         struct intel_crtc_state pipe_config = {
6383                 .pixel_multiplier = 1,
6384                 .dpll = *dpll,
6385         };
6386
6387         if (IS_CHERRYVIEW(dev)) {
6388                 chv_update_pll(crtc, &pipe_config);
6389                 chv_prepare_pll(crtc, &pipe_config);
6390                 chv_enable_pll(crtc, &pipe_config);
6391         } else {
6392                 vlv_update_pll(crtc, &pipe_config);
6393                 vlv_prepare_pll(crtc, &pipe_config);
6394                 vlv_enable_pll(crtc, &pipe_config);
6395         }
6396 }
6397
6398 /**
6399  * vlv_force_pll_off - forcibly disable just the PLL
6400  * @dev_priv: i915 private structure
6401  * @pipe: pipe PLL to disable
6402  *
6403  * Disable the PLL for @pipe. To be used in cases where we need
6404  * the PLL enabled even when @pipe is not going to be enabled.
6405  */
6406 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6407 {
6408         if (IS_CHERRYVIEW(dev))
6409                 chv_disable_pll(to_i915(dev), pipe);
6410         else
6411                 vlv_disable_pll(to_i915(dev), pipe);
6412 }
6413
6414 static void i9xx_update_pll(struct intel_crtc *crtc,
6415                             struct intel_crtc_state *crtc_state,
6416                             intel_clock_t *reduced_clock,
6417                             int num_connectors)
6418 {
6419         struct drm_device *dev = crtc->base.dev;
6420         struct drm_i915_private *dev_priv = dev->dev_private;
6421         u32 dpll;
6422         bool is_sdvo;
6423         struct dpll *clock = &crtc_state->dpll;
6424
6425         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6426
6427         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6428                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6429
6430         dpll = DPLL_VGA_MODE_DIS;
6431
6432         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6433                 dpll |= DPLLB_MODE_LVDS;
6434         else
6435                 dpll |= DPLLB_MODE_DAC_SERIAL;
6436
6437         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6438                 dpll |= (crtc_state->pixel_multiplier - 1)
6439                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6440         }
6441
6442         if (is_sdvo)
6443                 dpll |= DPLL_SDVO_HIGH_SPEED;
6444
6445         if (crtc_state->has_dp_encoder)
6446                 dpll |= DPLL_SDVO_HIGH_SPEED;
6447
6448         /* compute bitmask from p1 value */
6449         if (IS_PINEVIEW(dev))
6450                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6451         else {
6452                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6453                 if (IS_G4X(dev) && reduced_clock)
6454                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6455         }
6456         switch (clock->p2) {
6457         case 5:
6458                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6459                 break;
6460         case 7:
6461                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6462                 break;
6463         case 10:
6464                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6465                 break;
6466         case 14:
6467                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6468                 break;
6469         }
6470         if (INTEL_INFO(dev)->gen >= 4)
6471                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6472
6473         if (crtc_state->sdvo_tv_clock)
6474                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6475         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6476                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6477                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6478         else
6479                 dpll |= PLL_REF_INPUT_DREFCLK;
6480
6481         dpll |= DPLL_VCO_ENABLE;
6482         crtc_state->dpll_hw_state.dpll = dpll;
6483
6484         if (INTEL_INFO(dev)->gen >= 4) {
6485                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6486                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6487                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6488         }
6489 }
6490
6491 static void i8xx_update_pll(struct intel_crtc *crtc,
6492                             struct intel_crtc_state *crtc_state,
6493                             intel_clock_t *reduced_clock,
6494                             int num_connectors)
6495 {
6496         struct drm_device *dev = crtc->base.dev;
6497         struct drm_i915_private *dev_priv = dev->dev_private;
6498         u32 dpll;
6499         struct dpll *clock = &crtc_state->dpll;
6500
6501         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6502
6503         dpll = DPLL_VGA_MODE_DIS;
6504
6505         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6506                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6507         } else {
6508                 if (clock->p1 == 2)
6509                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6510                 else
6511                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6512                 if (clock->p2 == 4)
6513                         dpll |= PLL_P2_DIVIDE_BY_4;
6514         }
6515
6516         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6517                 dpll |= DPLL_DVO_2X_MODE;
6518
6519         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6520                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6521                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6522         else
6523                 dpll |= PLL_REF_INPUT_DREFCLK;
6524
6525         dpll |= DPLL_VCO_ENABLE;
6526         crtc_state->dpll_hw_state.dpll = dpll;
6527 }
6528
6529 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6530 {
6531         struct drm_device *dev = intel_crtc->base.dev;
6532         struct drm_i915_private *dev_priv = dev->dev_private;
6533         enum pipe pipe = intel_crtc->pipe;
6534         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6535         struct drm_display_mode *adjusted_mode =
6536                 &intel_crtc->config->base.adjusted_mode;
6537         uint32_t crtc_vtotal, crtc_vblank_end;
6538         int vsyncshift = 0;
6539
6540         /* We need to be careful not to changed the adjusted mode, for otherwise
6541          * the hw state checker will get angry at the mismatch. */
6542         crtc_vtotal = adjusted_mode->crtc_vtotal;
6543         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6544
6545         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6546                 /* the chip adds 2 halflines automatically */
6547                 crtc_vtotal -= 1;
6548                 crtc_vblank_end -= 1;
6549
6550                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6551                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6552                 else
6553                         vsyncshift = adjusted_mode->crtc_hsync_start -
6554                                 adjusted_mode->crtc_htotal / 2;
6555                 if (vsyncshift < 0)
6556                         vsyncshift += adjusted_mode->crtc_htotal;
6557         }
6558
6559         if (INTEL_INFO(dev)->gen > 3)
6560                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6561
6562         I915_WRITE(HTOTAL(cpu_transcoder),
6563                    (adjusted_mode->crtc_hdisplay - 1) |
6564                    ((adjusted_mode->crtc_htotal - 1) << 16));
6565         I915_WRITE(HBLANK(cpu_transcoder),
6566                    (adjusted_mode->crtc_hblank_start - 1) |
6567                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6568         I915_WRITE(HSYNC(cpu_transcoder),
6569                    (adjusted_mode->crtc_hsync_start - 1) |
6570                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6571
6572         I915_WRITE(VTOTAL(cpu_transcoder),
6573                    (adjusted_mode->crtc_vdisplay - 1) |
6574                    ((crtc_vtotal - 1) << 16));
6575         I915_WRITE(VBLANK(cpu_transcoder),
6576                    (adjusted_mode->crtc_vblank_start - 1) |
6577                    ((crtc_vblank_end - 1) << 16));
6578         I915_WRITE(VSYNC(cpu_transcoder),
6579                    (adjusted_mode->crtc_vsync_start - 1) |
6580                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6581
6582         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6583          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6584          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6585          * bits. */
6586         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6587             (pipe == PIPE_B || pipe == PIPE_C))
6588                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6589
6590         /* pipesrc controls the size that is scaled from, which should
6591          * always be the user's requested size.
6592          */
6593         I915_WRITE(PIPESRC(pipe),
6594                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6595                    (intel_crtc->config->pipe_src_h - 1));
6596 }
6597
6598 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6599                                    struct intel_crtc_state *pipe_config)
6600 {
6601         struct drm_device *dev = crtc->base.dev;
6602         struct drm_i915_private *dev_priv = dev->dev_private;
6603         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6604         uint32_t tmp;
6605
6606         tmp = I915_READ(HTOTAL(cpu_transcoder));
6607         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6608         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6609         tmp = I915_READ(HBLANK(cpu_transcoder));
6610         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6611         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6612         tmp = I915_READ(HSYNC(cpu_transcoder));
6613         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6614         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6615
6616         tmp = I915_READ(VTOTAL(cpu_transcoder));
6617         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6618         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6619         tmp = I915_READ(VBLANK(cpu_transcoder));
6620         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6621         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6622         tmp = I915_READ(VSYNC(cpu_transcoder));
6623         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6624         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6625
6626         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6627                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6628                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6629                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6630         }
6631
6632         tmp = I915_READ(PIPESRC(crtc->pipe));
6633         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6634         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6635
6636         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6637         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6638 }
6639
6640 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6641                                  struct intel_crtc_state *pipe_config)
6642 {
6643         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6644         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6645         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6646         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6647
6648         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6649         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6650         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6651         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6652
6653         mode->flags = pipe_config->base.adjusted_mode.flags;
6654
6655         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6656         mode->flags |= pipe_config->base.adjusted_mode.flags;
6657 }
6658
6659 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6660 {
6661         struct drm_device *dev = intel_crtc->base.dev;
6662         struct drm_i915_private *dev_priv = dev->dev_private;
6663         uint32_t pipeconf;
6664
6665         pipeconf = 0;
6666
6667         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6668             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6669                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6670
6671         if (intel_crtc->config->double_wide)
6672                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6673
6674         /* only g4x and later have fancy bpc/dither controls */
6675         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6676                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6677                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6678                         pipeconf |= PIPECONF_DITHER_EN |
6679                                     PIPECONF_DITHER_TYPE_SP;
6680
6681                 switch (intel_crtc->config->pipe_bpp) {
6682                 case 18:
6683                         pipeconf |= PIPECONF_6BPC;
6684                         break;
6685                 case 24:
6686                         pipeconf |= PIPECONF_8BPC;
6687                         break;
6688                 case 30:
6689                         pipeconf |= PIPECONF_10BPC;
6690                         break;
6691                 default:
6692                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6693                         BUG();
6694                 }
6695         }
6696
6697         if (HAS_PIPE_CXSR(dev)) {
6698                 if (intel_crtc->lowfreq_avail) {
6699                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6700                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6701                 } else {
6702                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6703                 }
6704         }
6705
6706         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6707                 if (INTEL_INFO(dev)->gen < 4 ||
6708                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6709                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6710                 else
6711                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6712         } else
6713                 pipeconf |= PIPECONF_PROGRESSIVE;
6714
6715         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6716                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6717
6718         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6719         POSTING_READ(PIPECONF(intel_crtc->pipe));
6720 }
6721
6722 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6723                                    struct intel_crtc_state *crtc_state)
6724 {
6725         struct drm_device *dev = crtc->base.dev;
6726         struct drm_i915_private *dev_priv = dev->dev_private;
6727         int refclk, num_connectors = 0;
6728         intel_clock_t clock, reduced_clock;
6729         bool ok, has_reduced_clock = false;
6730         bool is_lvds = false, is_dsi = false;
6731         struct intel_encoder *encoder;
6732         const intel_limit_t *limit;
6733
6734         for_each_intel_encoder(dev, encoder) {
6735                 if (encoder->new_crtc != crtc)
6736                         continue;
6737
6738                 switch (encoder->type) {
6739                 case INTEL_OUTPUT_LVDS:
6740                         is_lvds = true;
6741                         break;
6742                 case INTEL_OUTPUT_DSI:
6743                         is_dsi = true;
6744                         break;
6745                 default:
6746                         break;
6747                 }
6748
6749                 num_connectors++;
6750         }
6751
6752         if (is_dsi)
6753                 return 0;
6754
6755         if (!crtc_state->clock_set) {
6756                 refclk = i9xx_get_refclk(crtc, num_connectors);
6757
6758                 /*
6759                  * Returns a set of divisors for the desired target clock with
6760                  * the given refclk, or FALSE.  The returned values represent
6761                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6762                  * 2) / p1 / p2.
6763                  */
6764                 limit = intel_limit(crtc, refclk);
6765                 ok = dev_priv->display.find_dpll(limit, crtc,
6766                                                  crtc_state->port_clock,
6767                                                  refclk, NULL, &clock);
6768                 if (!ok) {
6769                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6770                         return -EINVAL;
6771                 }
6772
6773                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6774                         /*
6775                          * Ensure we match the reduced clock's P to the target
6776                          * clock.  If the clocks don't match, we can't switch
6777                          * the display clock by using the FP0/FP1. In such case
6778                          * we will disable the LVDS downclock feature.
6779                          */
6780                         has_reduced_clock =
6781                                 dev_priv->display.find_dpll(limit, crtc,
6782                                                             dev_priv->lvds_downclock,
6783                                                             refclk, &clock,
6784                                                             &reduced_clock);
6785                 }
6786                 /* Compat-code for transition, will disappear. */
6787                 crtc_state->dpll.n = clock.n;
6788                 crtc_state->dpll.m1 = clock.m1;
6789                 crtc_state->dpll.m2 = clock.m2;
6790                 crtc_state->dpll.p1 = clock.p1;
6791                 crtc_state->dpll.p2 = clock.p2;
6792         }
6793
6794         if (IS_GEN2(dev)) {
6795                 i8xx_update_pll(crtc, crtc_state,
6796                                 has_reduced_clock ? &reduced_clock : NULL,
6797                                 num_connectors);
6798         } else if (IS_CHERRYVIEW(dev)) {
6799                 chv_update_pll(crtc, crtc_state);
6800         } else if (IS_VALLEYVIEW(dev)) {
6801                 vlv_update_pll(crtc, crtc_state);
6802         } else {
6803                 i9xx_update_pll(crtc, crtc_state,
6804                                 has_reduced_clock ? &reduced_clock : NULL,
6805                                 num_connectors);
6806         }
6807
6808         return 0;
6809 }
6810
6811 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6812                                  struct intel_crtc_state *pipe_config)
6813 {
6814         struct drm_device *dev = crtc->base.dev;
6815         struct drm_i915_private *dev_priv = dev->dev_private;
6816         uint32_t tmp;
6817
6818         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6819                 return;
6820
6821         tmp = I915_READ(PFIT_CONTROL);
6822         if (!(tmp & PFIT_ENABLE))
6823                 return;
6824
6825         /* Check whether the pfit is attached to our pipe. */
6826         if (INTEL_INFO(dev)->gen < 4) {
6827                 if (crtc->pipe != PIPE_B)
6828                         return;
6829         } else {
6830                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6831                         return;
6832         }
6833
6834         pipe_config->gmch_pfit.control = tmp;
6835         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6836         if (INTEL_INFO(dev)->gen < 5)
6837                 pipe_config->gmch_pfit.lvds_border_bits =
6838                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6839 }
6840
6841 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6842                                struct intel_crtc_state *pipe_config)
6843 {
6844         struct drm_device *dev = crtc->base.dev;
6845         struct drm_i915_private *dev_priv = dev->dev_private;
6846         int pipe = pipe_config->cpu_transcoder;
6847         intel_clock_t clock;
6848         u32 mdiv;
6849         int refclk = 100000;
6850
6851         /* In case of MIPI DPLL will not even be used */
6852         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6853                 return;
6854
6855         mutex_lock(&dev_priv->dpio_lock);
6856         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6857         mutex_unlock(&dev_priv->dpio_lock);
6858
6859         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6860         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6861         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6862         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6863         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6864
6865         vlv_clock(refclk, &clock);
6866
6867         /* clock.dot is the fast clock */
6868         pipe_config->port_clock = clock.dot / 5;
6869 }
6870
6871 static void
6872 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6873                               struct intel_initial_plane_config *plane_config)
6874 {
6875         struct drm_device *dev = crtc->base.dev;
6876         struct drm_i915_private *dev_priv = dev->dev_private;
6877         u32 val, base, offset;
6878         int pipe = crtc->pipe, plane = crtc->plane;
6879         int fourcc, pixel_format;
6880         unsigned int aligned_height;
6881         struct drm_framebuffer *fb;
6882         struct intel_framebuffer *intel_fb;
6883
6884         val = I915_READ(DSPCNTR(plane));
6885         if (!(val & DISPLAY_PLANE_ENABLE))
6886                 return;
6887
6888         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6889         if (!intel_fb) {
6890                 DRM_DEBUG_KMS("failed to alloc fb\n");
6891                 return;
6892         }
6893
6894         fb = &intel_fb->base;
6895
6896         if (INTEL_INFO(dev)->gen >= 4) {
6897                 if (val & DISPPLANE_TILED) {
6898                         plane_config->tiling = I915_TILING_X;
6899                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6900                 }
6901         }
6902
6903         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6904         fourcc = i9xx_format_to_fourcc(pixel_format);
6905         fb->pixel_format = fourcc;
6906         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6907
6908         if (INTEL_INFO(dev)->gen >= 4) {
6909                 if (plane_config->tiling)
6910                         offset = I915_READ(DSPTILEOFF(plane));
6911                 else
6912                         offset = I915_READ(DSPLINOFF(plane));
6913                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6914         } else {
6915                 base = I915_READ(DSPADDR(plane));
6916         }
6917         plane_config->base = base;
6918
6919         val = I915_READ(PIPESRC(pipe));
6920         fb->width = ((val >> 16) & 0xfff) + 1;
6921         fb->height = ((val >> 0) & 0xfff) + 1;
6922
6923         val = I915_READ(DSPSTRIDE(pipe));
6924         fb->pitches[0] = val & 0xffffffc0;
6925
6926         aligned_height = intel_fb_align_height(dev, fb->height,
6927                                                fb->pixel_format,
6928                                                fb->modifier[0]);
6929
6930         plane_config->size = fb->pitches[0] * aligned_height;
6931
6932         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6933                       pipe_name(pipe), plane, fb->width, fb->height,
6934                       fb->bits_per_pixel, base, fb->pitches[0],
6935                       plane_config->size);
6936
6937         plane_config->fb = intel_fb;
6938 }
6939
6940 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6941                                struct intel_crtc_state *pipe_config)
6942 {
6943         struct drm_device *dev = crtc->base.dev;
6944         struct drm_i915_private *dev_priv = dev->dev_private;
6945         int pipe = pipe_config->cpu_transcoder;
6946         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6947         intel_clock_t clock;
6948         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6949         int refclk = 100000;
6950
6951         mutex_lock(&dev_priv->dpio_lock);
6952         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6953         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6954         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6955         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6956         mutex_unlock(&dev_priv->dpio_lock);
6957
6958         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6959         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6960         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6961         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6962         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6963
6964         chv_clock(refclk, &clock);
6965
6966         /* clock.dot is the fast clock */
6967         pipe_config->port_clock = clock.dot / 5;
6968 }
6969
6970 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6971                                  struct intel_crtc_state *pipe_config)
6972 {
6973         struct drm_device *dev = crtc->base.dev;
6974         struct drm_i915_private *dev_priv = dev->dev_private;
6975         uint32_t tmp;
6976
6977         if (!intel_display_power_is_enabled(dev_priv,
6978                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6979                 return false;
6980
6981         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6982         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6983
6984         tmp = I915_READ(PIPECONF(crtc->pipe));
6985         if (!(tmp & PIPECONF_ENABLE))
6986                 return false;
6987
6988         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6989                 switch (tmp & PIPECONF_BPC_MASK) {
6990                 case PIPECONF_6BPC:
6991                         pipe_config->pipe_bpp = 18;
6992                         break;
6993                 case PIPECONF_8BPC:
6994                         pipe_config->pipe_bpp = 24;
6995                         break;
6996                 case PIPECONF_10BPC:
6997                         pipe_config->pipe_bpp = 30;
6998                         break;
6999                 default:
7000                         break;
7001                 }
7002         }
7003
7004         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7005                 pipe_config->limited_color_range = true;
7006
7007         if (INTEL_INFO(dev)->gen < 4)
7008                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7009
7010         intel_get_pipe_timings(crtc, pipe_config);
7011
7012         i9xx_get_pfit_config(crtc, pipe_config);
7013
7014         if (INTEL_INFO(dev)->gen >= 4) {
7015                 tmp = I915_READ(DPLL_MD(crtc->pipe));
7016                 pipe_config->pixel_multiplier =
7017                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7018                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7019                 pipe_config->dpll_hw_state.dpll_md = tmp;
7020         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7021                 tmp = I915_READ(DPLL(crtc->pipe));
7022                 pipe_config->pixel_multiplier =
7023                         ((tmp & SDVO_MULTIPLIER_MASK)
7024                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7025         } else {
7026                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7027                  * port and will be fixed up in the encoder->get_config
7028                  * function. */
7029                 pipe_config->pixel_multiplier = 1;
7030         }
7031         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7032         if (!IS_VALLEYVIEW(dev)) {
7033                 /*
7034                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7035                  * on 830. Filter it out here so that we don't
7036                  * report errors due to that.
7037                  */
7038                 if (IS_I830(dev))
7039                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7040
7041                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7042                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7043         } else {
7044                 /* Mask out read-only status bits. */
7045                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7046                                                      DPLL_PORTC_READY_MASK |
7047                                                      DPLL_PORTB_READY_MASK);
7048         }
7049
7050         if (IS_CHERRYVIEW(dev))
7051                 chv_crtc_clock_get(crtc, pipe_config);
7052         else if (IS_VALLEYVIEW(dev))
7053                 vlv_crtc_clock_get(crtc, pipe_config);
7054         else
7055                 i9xx_crtc_clock_get(crtc, pipe_config);
7056
7057         return true;
7058 }
7059
7060 static void ironlake_init_pch_refclk(struct drm_device *dev)
7061 {
7062         struct drm_i915_private *dev_priv = dev->dev_private;
7063         struct intel_encoder *encoder;
7064         u32 val, final;
7065         bool has_lvds = false;
7066         bool has_cpu_edp = false;
7067         bool has_panel = false;
7068         bool has_ck505 = false;
7069         bool can_ssc = false;
7070
7071         /* We need to take the global config into account */
7072         for_each_intel_encoder(dev, encoder) {
7073                 switch (encoder->type) {
7074                 case INTEL_OUTPUT_LVDS:
7075                         has_panel = true;
7076                         has_lvds = true;
7077                         break;
7078                 case INTEL_OUTPUT_EDP:
7079                         has_panel = true;
7080                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7081                                 has_cpu_edp = true;
7082                         break;
7083                 default:
7084                         break;
7085                 }
7086         }
7087
7088         if (HAS_PCH_IBX(dev)) {
7089                 has_ck505 = dev_priv->vbt.display_clock_mode;
7090                 can_ssc = has_ck505;
7091         } else {
7092                 has_ck505 = false;
7093                 can_ssc = true;
7094         }
7095
7096         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7097                       has_panel, has_lvds, has_ck505);
7098
7099         /* Ironlake: try to setup display ref clock before DPLL
7100          * enabling. This is only under driver's control after
7101          * PCH B stepping, previous chipset stepping should be
7102          * ignoring this setting.
7103          */
7104         val = I915_READ(PCH_DREF_CONTROL);
7105
7106         /* As we must carefully and slowly disable/enable each source in turn,
7107          * compute the final state we want first and check if we need to
7108          * make any changes at all.
7109          */
7110         final = val;
7111         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7112         if (has_ck505)
7113                 final |= DREF_NONSPREAD_CK505_ENABLE;
7114         else
7115                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7116
7117         final &= ~DREF_SSC_SOURCE_MASK;
7118         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7119         final &= ~DREF_SSC1_ENABLE;
7120
7121         if (has_panel) {
7122                 final |= DREF_SSC_SOURCE_ENABLE;
7123
7124                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7125                         final |= DREF_SSC1_ENABLE;
7126
7127                 if (has_cpu_edp) {
7128                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7129                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7130                         else
7131                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7132                 } else
7133                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7134         } else {
7135                 final |= DREF_SSC_SOURCE_DISABLE;
7136                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7137         }
7138
7139         if (final == val)
7140                 return;
7141
7142         /* Always enable nonspread source */
7143         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7144
7145         if (has_ck505)
7146                 val |= DREF_NONSPREAD_CK505_ENABLE;
7147         else
7148                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7149
7150         if (has_panel) {
7151                 val &= ~DREF_SSC_SOURCE_MASK;
7152                 val |= DREF_SSC_SOURCE_ENABLE;
7153
7154                 /* SSC must be turned on before enabling the CPU output  */
7155                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7156                         DRM_DEBUG_KMS("Using SSC on panel\n");
7157                         val |= DREF_SSC1_ENABLE;
7158                 } else
7159                         val &= ~DREF_SSC1_ENABLE;
7160
7161                 /* Get SSC going before enabling the outputs */
7162                 I915_WRITE(PCH_DREF_CONTROL, val);
7163                 POSTING_READ(PCH_DREF_CONTROL);
7164                 udelay(200);
7165
7166                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7167
7168                 /* Enable CPU source on CPU attached eDP */
7169                 if (has_cpu_edp) {
7170                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7171                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7172                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7173                         } else
7174                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7175                 } else
7176                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7177
7178                 I915_WRITE(PCH_DREF_CONTROL, val);
7179                 POSTING_READ(PCH_DREF_CONTROL);
7180                 udelay(200);
7181         } else {
7182                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7183
7184                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7185
7186                 /* Turn off CPU output */
7187                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7188
7189                 I915_WRITE(PCH_DREF_CONTROL, val);
7190                 POSTING_READ(PCH_DREF_CONTROL);
7191                 udelay(200);
7192
7193                 /* Turn off the SSC source */
7194                 val &= ~DREF_SSC_SOURCE_MASK;
7195                 val |= DREF_SSC_SOURCE_DISABLE;
7196
7197                 /* Turn off SSC1 */
7198                 val &= ~DREF_SSC1_ENABLE;
7199
7200                 I915_WRITE(PCH_DREF_CONTROL, val);
7201                 POSTING_READ(PCH_DREF_CONTROL);
7202                 udelay(200);
7203         }
7204
7205         BUG_ON(val != final);
7206 }
7207
7208 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7209 {
7210         uint32_t tmp;
7211
7212         tmp = I915_READ(SOUTH_CHICKEN2);
7213         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7214         I915_WRITE(SOUTH_CHICKEN2, tmp);
7215
7216         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7217                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7218                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7219
7220         tmp = I915_READ(SOUTH_CHICKEN2);
7221         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7222         I915_WRITE(SOUTH_CHICKEN2, tmp);
7223
7224         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7225                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7226                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7227 }
7228
7229 /* WaMPhyProgramming:hsw */
7230 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7231 {
7232         uint32_t tmp;
7233
7234         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7235         tmp &= ~(0xFF << 24);
7236         tmp |= (0x12 << 24);
7237         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7238
7239         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7240         tmp |= (1 << 11);
7241         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7242
7243         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7244         tmp |= (1 << 11);
7245         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7246
7247         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7248         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7249         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7250
7251         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7252         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7253         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7254
7255         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7256         tmp &= ~(7 << 13);
7257         tmp |= (5 << 13);
7258         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7259
7260         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7261         tmp &= ~(7 << 13);
7262         tmp |= (5 << 13);
7263         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7264
7265         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7266         tmp &= ~0xFF;
7267         tmp |= 0x1C;
7268         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7269
7270         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7271         tmp &= ~0xFF;
7272         tmp |= 0x1C;
7273         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7274
7275         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7276         tmp &= ~(0xFF << 16);
7277         tmp |= (0x1C << 16);
7278         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7279
7280         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7281         tmp &= ~(0xFF << 16);
7282         tmp |= (0x1C << 16);
7283         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7284
7285         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7286         tmp |= (1 << 27);
7287         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7288
7289         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7290         tmp |= (1 << 27);
7291         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7292
7293         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7294         tmp &= ~(0xF << 28);
7295         tmp |= (4 << 28);
7296         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7297
7298         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7299         tmp &= ~(0xF << 28);
7300         tmp |= (4 << 28);
7301         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7302 }
7303
7304 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7305  * Programming" based on the parameters passed:
7306  * - Sequence to enable CLKOUT_DP
7307  * - Sequence to enable CLKOUT_DP without spread
7308  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7309  */
7310 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7311                                  bool with_fdi)
7312 {
7313         struct drm_i915_private *dev_priv = dev->dev_private;
7314         uint32_t reg, tmp;
7315
7316         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7317                 with_spread = true;
7318         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7319                  with_fdi, "LP PCH doesn't have FDI\n"))
7320                 with_fdi = false;
7321
7322         mutex_lock(&dev_priv->dpio_lock);
7323
7324         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7325         tmp &= ~SBI_SSCCTL_DISABLE;
7326         tmp |= SBI_SSCCTL_PATHALT;
7327         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7328
7329         udelay(24);
7330
7331         if (with_spread) {
7332                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7333                 tmp &= ~SBI_SSCCTL_PATHALT;
7334                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7335
7336                 if (with_fdi) {
7337                         lpt_reset_fdi_mphy(dev_priv);
7338                         lpt_program_fdi_mphy(dev_priv);
7339                 }
7340         }
7341
7342         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7343                SBI_GEN0 : SBI_DBUFF0;
7344         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7345         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7346         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7347
7348         mutex_unlock(&dev_priv->dpio_lock);
7349 }
7350
7351 /* Sequence to disable CLKOUT_DP */
7352 static void lpt_disable_clkout_dp(struct drm_device *dev)
7353 {
7354         struct drm_i915_private *dev_priv = dev->dev_private;
7355         uint32_t reg, tmp;
7356
7357         mutex_lock(&dev_priv->dpio_lock);
7358
7359         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7360                SBI_GEN0 : SBI_DBUFF0;
7361         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7362         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7363         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7364
7365         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7366         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7367                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7368                         tmp |= SBI_SSCCTL_PATHALT;
7369                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7370                         udelay(32);
7371                 }
7372                 tmp |= SBI_SSCCTL_DISABLE;
7373                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7374         }
7375
7376         mutex_unlock(&dev_priv->dpio_lock);
7377 }
7378
7379 static void lpt_init_pch_refclk(struct drm_device *dev)
7380 {
7381         struct intel_encoder *encoder;
7382         bool has_vga = false;
7383
7384         for_each_intel_encoder(dev, encoder) {
7385                 switch (encoder->type) {
7386                 case INTEL_OUTPUT_ANALOG:
7387                         has_vga = true;
7388                         break;
7389                 default:
7390                         break;
7391                 }
7392         }
7393
7394         if (has_vga)
7395                 lpt_enable_clkout_dp(dev, true, true);
7396         else
7397                 lpt_disable_clkout_dp(dev);
7398 }
7399
7400 /*
7401  * Initialize reference clocks when the driver loads
7402  */
7403 void intel_init_pch_refclk(struct drm_device *dev)
7404 {
7405         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7406                 ironlake_init_pch_refclk(dev);
7407         else if (HAS_PCH_LPT(dev))
7408                 lpt_init_pch_refclk(dev);
7409 }
7410
7411 static int ironlake_get_refclk(struct drm_crtc *crtc)
7412 {
7413         struct drm_device *dev = crtc->dev;
7414         struct drm_i915_private *dev_priv = dev->dev_private;
7415         struct intel_encoder *encoder;
7416         int num_connectors = 0;
7417         bool is_lvds = false;
7418
7419         for_each_intel_encoder(dev, encoder) {
7420                 if (encoder->new_crtc != to_intel_crtc(crtc))
7421                         continue;
7422
7423                 switch (encoder->type) {
7424                 case INTEL_OUTPUT_LVDS:
7425                         is_lvds = true;
7426                         break;
7427                 default:
7428                         break;
7429                 }
7430                 num_connectors++;
7431         }
7432
7433         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7434                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7435                               dev_priv->vbt.lvds_ssc_freq);
7436                 return dev_priv->vbt.lvds_ssc_freq;
7437         }
7438
7439         return 120000;
7440 }
7441
7442 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7443 {
7444         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7445         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7446         int pipe = intel_crtc->pipe;
7447         uint32_t val;
7448
7449         val = 0;
7450
7451         switch (intel_crtc->config->pipe_bpp) {
7452         case 18:
7453                 val |= PIPECONF_6BPC;
7454                 break;
7455         case 24:
7456                 val |= PIPECONF_8BPC;
7457                 break;
7458         case 30:
7459                 val |= PIPECONF_10BPC;
7460                 break;
7461         case 36:
7462                 val |= PIPECONF_12BPC;
7463                 break;
7464         default:
7465                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7466                 BUG();
7467         }
7468
7469         if (intel_crtc->config->dither)
7470                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7471
7472         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7473                 val |= PIPECONF_INTERLACED_ILK;
7474         else
7475                 val |= PIPECONF_PROGRESSIVE;
7476
7477         if (intel_crtc->config->limited_color_range)
7478                 val |= PIPECONF_COLOR_RANGE_SELECT;
7479
7480         I915_WRITE(PIPECONF(pipe), val);
7481         POSTING_READ(PIPECONF(pipe));
7482 }
7483
7484 /*
7485  * Set up the pipe CSC unit.
7486  *
7487  * Currently only full range RGB to limited range RGB conversion
7488  * is supported, but eventually this should handle various
7489  * RGB<->YCbCr scenarios as well.
7490  */
7491 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7492 {
7493         struct drm_device *dev = crtc->dev;
7494         struct drm_i915_private *dev_priv = dev->dev_private;
7495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7496         int pipe = intel_crtc->pipe;
7497         uint16_t coeff = 0x7800; /* 1.0 */
7498
7499         /*
7500          * TODO: Check what kind of values actually come out of the pipe
7501          * with these coeff/postoff values and adjust to get the best
7502          * accuracy. Perhaps we even need to take the bpc value into
7503          * consideration.
7504          */
7505
7506         if (intel_crtc->config->limited_color_range)
7507                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7508
7509         /*
7510          * GY/GU and RY/RU should be the other way around according
7511          * to BSpec, but reality doesn't agree. Just set them up in
7512          * a way that results in the correct picture.
7513          */
7514         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7515         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7516
7517         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7518         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7519
7520         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7521         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7522
7523         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7524         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7525         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7526
7527         if (INTEL_INFO(dev)->gen > 6) {
7528                 uint16_t postoff = 0;
7529
7530                 if (intel_crtc->config->limited_color_range)
7531                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7532
7533                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7534                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7535                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7536
7537                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7538         } else {
7539                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7540
7541                 if (intel_crtc->config->limited_color_range)
7542                         mode |= CSC_BLACK_SCREEN_OFFSET;
7543
7544                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7545         }
7546 }
7547
7548 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7549 {
7550         struct drm_device *dev = crtc->dev;
7551         struct drm_i915_private *dev_priv = dev->dev_private;
7552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7553         enum pipe pipe = intel_crtc->pipe;
7554         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7555         uint32_t val;
7556
7557         val = 0;
7558
7559         if (IS_HASWELL(dev) && intel_crtc->config->dither)
7560                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7561
7562         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7563                 val |= PIPECONF_INTERLACED_ILK;
7564         else
7565                 val |= PIPECONF_PROGRESSIVE;
7566
7567         I915_WRITE(PIPECONF(cpu_transcoder), val);
7568         POSTING_READ(PIPECONF(cpu_transcoder));
7569
7570         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7571         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7572
7573         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7574                 val = 0;
7575
7576                 switch (intel_crtc->config->pipe_bpp) {
7577                 case 18:
7578                         val |= PIPEMISC_DITHER_6_BPC;
7579                         break;
7580                 case 24:
7581                         val |= PIPEMISC_DITHER_8_BPC;
7582                         break;
7583                 case 30:
7584                         val |= PIPEMISC_DITHER_10_BPC;
7585                         break;
7586                 case 36:
7587                         val |= PIPEMISC_DITHER_12_BPC;
7588                         break;
7589                 default:
7590                         /* Case prevented by pipe_config_set_bpp. */
7591                         BUG();
7592                 }
7593
7594                 if (intel_crtc->config->dither)
7595                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7596
7597                 I915_WRITE(PIPEMISC(pipe), val);
7598         }
7599 }
7600
7601 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7602                                     struct intel_crtc_state *crtc_state,
7603                                     intel_clock_t *clock,
7604                                     bool *has_reduced_clock,
7605                                     intel_clock_t *reduced_clock)
7606 {
7607         struct drm_device *dev = crtc->dev;
7608         struct drm_i915_private *dev_priv = dev->dev_private;
7609         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7610         int refclk;
7611         const intel_limit_t *limit;
7612         bool ret, is_lvds = false;
7613
7614         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7615
7616         refclk = ironlake_get_refclk(crtc);
7617
7618         /*
7619          * Returns a set of divisors for the desired target clock with the given
7620          * refclk, or FALSE.  The returned values represent the clock equation:
7621          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7622          */
7623         limit = intel_limit(intel_crtc, refclk);
7624         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7625                                           crtc_state->port_clock,
7626                                           refclk, NULL, clock);
7627         if (!ret)
7628                 return false;
7629
7630         if (is_lvds && dev_priv->lvds_downclock_avail) {
7631                 /*
7632                  * Ensure we match the reduced clock's P to the target clock.
7633                  * If the clocks don't match, we can't switch the display clock
7634                  * by using the FP0/FP1. In such case we will disable the LVDS
7635                  * downclock feature.
7636                 */
7637                 *has_reduced_clock =
7638                         dev_priv->display.find_dpll(limit, intel_crtc,
7639                                                     dev_priv->lvds_downclock,
7640                                                     refclk, clock,
7641                                                     reduced_clock);
7642         }
7643
7644         return true;
7645 }
7646
7647 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7648 {
7649         /*
7650          * Account for spread spectrum to avoid
7651          * oversubscribing the link. Max center spread
7652          * is 2.5%; use 5% for safety's sake.
7653          */
7654         u32 bps = target_clock * bpp * 21 / 20;
7655         return DIV_ROUND_UP(bps, link_bw * 8);
7656 }
7657
7658 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7659 {
7660         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7661 }
7662
7663 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7664                                       struct intel_crtc_state *crtc_state,
7665                                       u32 *fp,
7666                                       intel_clock_t *reduced_clock, u32 *fp2)
7667 {
7668         struct drm_crtc *crtc = &intel_crtc->base;
7669         struct drm_device *dev = crtc->dev;
7670         struct drm_i915_private *dev_priv = dev->dev_private;
7671         struct intel_encoder *intel_encoder;
7672         uint32_t dpll;
7673         int factor, num_connectors = 0;
7674         bool is_lvds = false, is_sdvo = false;
7675
7676         for_each_intel_encoder(dev, intel_encoder) {
7677                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7678                         continue;
7679
7680                 switch (intel_encoder->type) {
7681                 case INTEL_OUTPUT_LVDS:
7682                         is_lvds = true;
7683                         break;
7684                 case INTEL_OUTPUT_SDVO:
7685                 case INTEL_OUTPUT_HDMI:
7686                         is_sdvo = true;
7687                         break;
7688                 default:
7689                         break;
7690                 }
7691
7692                 num_connectors++;
7693         }
7694
7695         /* Enable autotuning of the PLL clock (if permissible) */
7696         factor = 21;
7697         if (is_lvds) {
7698                 if ((intel_panel_use_ssc(dev_priv) &&
7699                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7700                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7701                         factor = 25;
7702         } else if (crtc_state->sdvo_tv_clock)
7703                 factor = 20;
7704
7705         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7706                 *fp |= FP_CB_TUNE;
7707
7708         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7709                 *fp2 |= FP_CB_TUNE;
7710
7711         dpll = 0;
7712
7713         if (is_lvds)
7714                 dpll |= DPLLB_MODE_LVDS;
7715         else
7716                 dpll |= DPLLB_MODE_DAC_SERIAL;
7717
7718         dpll |= (crtc_state->pixel_multiplier - 1)
7719                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7720
7721         if (is_sdvo)
7722                 dpll |= DPLL_SDVO_HIGH_SPEED;
7723         if (crtc_state->has_dp_encoder)
7724                 dpll |= DPLL_SDVO_HIGH_SPEED;
7725
7726         /* compute bitmask from p1 value */
7727         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7728         /* also FPA1 */
7729         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7730
7731         switch (crtc_state->dpll.p2) {
7732         case 5:
7733                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7734                 break;
7735         case 7:
7736                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7737                 break;
7738         case 10:
7739                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7740                 break;
7741         case 14:
7742                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7743                 break;
7744         }
7745
7746         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7747                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7748         else
7749                 dpll |= PLL_REF_INPUT_DREFCLK;
7750
7751         return dpll | DPLL_VCO_ENABLE;
7752 }
7753
7754 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7755                                        struct intel_crtc_state *crtc_state)
7756 {
7757         struct drm_device *dev = crtc->base.dev;
7758         intel_clock_t clock, reduced_clock;
7759         u32 dpll = 0, fp = 0, fp2 = 0;
7760         bool ok, has_reduced_clock = false;
7761         bool is_lvds = false;
7762         struct intel_shared_dpll *pll;
7763
7764         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7765
7766         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7767              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7768
7769         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7770                                      &has_reduced_clock, &reduced_clock);
7771         if (!ok && !crtc_state->clock_set) {
7772                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7773                 return -EINVAL;
7774         }
7775         /* Compat-code for transition, will disappear. */
7776         if (!crtc_state->clock_set) {
7777                 crtc_state->dpll.n = clock.n;
7778                 crtc_state->dpll.m1 = clock.m1;
7779                 crtc_state->dpll.m2 = clock.m2;
7780                 crtc_state->dpll.p1 = clock.p1;
7781                 crtc_state->dpll.p2 = clock.p2;
7782         }
7783
7784         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7785         if (crtc_state->has_pch_encoder) {
7786                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7787                 if (has_reduced_clock)
7788                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7789
7790                 dpll = ironlake_compute_dpll(crtc, crtc_state,
7791                                              &fp, &reduced_clock,
7792                                              has_reduced_clock ? &fp2 : NULL);
7793
7794                 crtc_state->dpll_hw_state.dpll = dpll;
7795                 crtc_state->dpll_hw_state.fp0 = fp;
7796                 if (has_reduced_clock)
7797                         crtc_state->dpll_hw_state.fp1 = fp2;
7798                 else
7799                         crtc_state->dpll_hw_state.fp1 = fp;
7800
7801                 pll = intel_get_shared_dpll(crtc, crtc_state);
7802                 if (pll == NULL) {
7803                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7804                                          pipe_name(crtc->pipe));
7805                         return -EINVAL;
7806                 }
7807         }
7808
7809         if (is_lvds && has_reduced_clock)
7810                 crtc->lowfreq_avail = true;
7811         else
7812                 crtc->lowfreq_avail = false;
7813
7814         return 0;
7815 }
7816
7817 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7818                                          struct intel_link_m_n *m_n)
7819 {
7820         struct drm_device *dev = crtc->base.dev;
7821         struct drm_i915_private *dev_priv = dev->dev_private;
7822         enum pipe pipe = crtc->pipe;
7823
7824         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7825         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7826         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7827                 & ~TU_SIZE_MASK;
7828         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7829         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7830                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7831 }
7832
7833 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7834                                          enum transcoder transcoder,
7835                                          struct intel_link_m_n *m_n,
7836                                          struct intel_link_m_n *m2_n2)
7837 {
7838         struct drm_device *dev = crtc->base.dev;
7839         struct drm_i915_private *dev_priv = dev->dev_private;
7840         enum pipe pipe = crtc->pipe;
7841
7842         if (INTEL_INFO(dev)->gen >= 5) {
7843                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7844                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7845                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7846                         & ~TU_SIZE_MASK;
7847                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7848                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7849                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7850                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7851                  * gen < 8) and if DRRS is supported (to make sure the
7852                  * registers are not unnecessarily read).
7853                  */
7854                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7855                         crtc->config->has_drrs) {
7856                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7857                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7858                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7859                                         & ~TU_SIZE_MASK;
7860                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7861                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7862                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7863                 }
7864         } else {
7865                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7866                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7867                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7868                         & ~TU_SIZE_MASK;
7869                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7870                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7871                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7872         }
7873 }
7874
7875 void intel_dp_get_m_n(struct intel_crtc *crtc,
7876                       struct intel_crtc_state *pipe_config)
7877 {
7878         if (pipe_config->has_pch_encoder)
7879                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7880         else
7881                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7882                                              &pipe_config->dp_m_n,
7883                                              &pipe_config->dp_m2_n2);
7884 }
7885
7886 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7887                                         struct intel_crtc_state *pipe_config)
7888 {
7889         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7890                                      &pipe_config->fdi_m_n, NULL);
7891 }
7892
7893 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7894                                     struct intel_crtc_state *pipe_config)
7895 {
7896         struct drm_device *dev = crtc->base.dev;
7897         struct drm_i915_private *dev_priv = dev->dev_private;
7898         uint32_t tmp;
7899
7900         tmp = I915_READ(PS_CTL(crtc->pipe));
7901
7902         if (tmp & PS_ENABLE) {
7903                 pipe_config->pch_pfit.enabled = true;
7904                 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7905                 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7906         }
7907 }
7908
7909 static void
7910 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7911                                  struct intel_initial_plane_config *plane_config)
7912 {
7913         struct drm_device *dev = crtc->base.dev;
7914         struct drm_i915_private *dev_priv = dev->dev_private;
7915         u32 val, base, offset, stride_mult, tiling;
7916         int pipe = crtc->pipe;
7917         int fourcc, pixel_format;
7918         unsigned int aligned_height;
7919         struct drm_framebuffer *fb;
7920         struct intel_framebuffer *intel_fb;
7921
7922         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7923         if (!intel_fb) {
7924                 DRM_DEBUG_KMS("failed to alloc fb\n");
7925                 return;
7926         }
7927
7928         fb = &intel_fb->base;
7929
7930         val = I915_READ(PLANE_CTL(pipe, 0));
7931         if (!(val & PLANE_CTL_ENABLE))
7932                 goto error;
7933
7934         pixel_format = val & PLANE_CTL_FORMAT_MASK;
7935         fourcc = skl_format_to_fourcc(pixel_format,
7936                                       val & PLANE_CTL_ORDER_RGBX,
7937                                       val & PLANE_CTL_ALPHA_MASK);
7938         fb->pixel_format = fourcc;
7939         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7940
7941         tiling = val & PLANE_CTL_TILED_MASK;
7942         switch (tiling) {
7943         case PLANE_CTL_TILED_LINEAR:
7944                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7945                 break;
7946         case PLANE_CTL_TILED_X:
7947                 plane_config->tiling = I915_TILING_X;
7948                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7949                 break;
7950         case PLANE_CTL_TILED_Y:
7951                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7952                 break;
7953         case PLANE_CTL_TILED_YF:
7954                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7955                 break;
7956         default:
7957                 MISSING_CASE(tiling);
7958                 goto error;
7959         }
7960
7961         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7962         plane_config->base = base;
7963
7964         offset = I915_READ(PLANE_OFFSET(pipe, 0));
7965
7966         val = I915_READ(PLANE_SIZE(pipe, 0));
7967         fb->height = ((val >> 16) & 0xfff) + 1;
7968         fb->width = ((val >> 0) & 0x1fff) + 1;
7969
7970         val = I915_READ(PLANE_STRIDE(pipe, 0));
7971         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7972                                                 fb->pixel_format);
7973         fb->pitches[0] = (val & 0x3ff) * stride_mult;
7974
7975         aligned_height = intel_fb_align_height(dev, fb->height,
7976                                                fb->pixel_format,
7977                                                fb->modifier[0]);
7978
7979         plane_config->size = fb->pitches[0] * aligned_height;
7980
7981         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7982                       pipe_name(pipe), fb->width, fb->height,
7983                       fb->bits_per_pixel, base, fb->pitches[0],
7984                       plane_config->size);
7985
7986         plane_config->fb = intel_fb;
7987         return;
7988
7989 error:
7990         kfree(fb);
7991 }
7992
7993 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7994                                      struct intel_crtc_state *pipe_config)
7995 {
7996         struct drm_device *dev = crtc->base.dev;
7997         struct drm_i915_private *dev_priv = dev->dev_private;
7998         uint32_t tmp;
7999
8000         tmp = I915_READ(PF_CTL(crtc->pipe));
8001
8002         if (tmp & PF_ENABLE) {
8003                 pipe_config->pch_pfit.enabled = true;
8004                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8005                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8006
8007                 /* We currently do not free assignements of panel fitters on
8008                  * ivb/hsw (since we don't use the higher upscaling modes which
8009                  * differentiates them) so just WARN about this case for now. */
8010                 if (IS_GEN7(dev)) {
8011                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8012                                 PF_PIPE_SEL_IVB(crtc->pipe));
8013                 }
8014         }
8015 }
8016
8017 static void
8018 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8019                                   struct intel_initial_plane_config *plane_config)
8020 {
8021         struct drm_device *dev = crtc->base.dev;
8022         struct drm_i915_private *dev_priv = dev->dev_private;
8023         u32 val, base, offset;
8024         int pipe = crtc->pipe;
8025         int fourcc, pixel_format;
8026         unsigned int aligned_height;
8027         struct drm_framebuffer *fb;
8028         struct intel_framebuffer *intel_fb;
8029
8030         val = I915_READ(DSPCNTR(pipe));
8031         if (!(val & DISPLAY_PLANE_ENABLE))
8032                 return;
8033
8034         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8035         if (!intel_fb) {
8036                 DRM_DEBUG_KMS("failed to alloc fb\n");
8037                 return;
8038         }
8039
8040         fb = &intel_fb->base;
8041
8042         if (INTEL_INFO(dev)->gen >= 4) {
8043                 if (val & DISPPLANE_TILED) {
8044                         plane_config->tiling = I915_TILING_X;
8045                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8046                 }
8047         }
8048
8049         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8050         fourcc = i9xx_format_to_fourcc(pixel_format);
8051         fb->pixel_format = fourcc;
8052         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8053
8054         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8055         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8056                 offset = I915_READ(DSPOFFSET(pipe));
8057         } else {
8058                 if (plane_config->tiling)
8059                         offset = I915_READ(DSPTILEOFF(pipe));
8060                 else
8061                         offset = I915_READ(DSPLINOFF(pipe));
8062         }
8063         plane_config->base = base;
8064
8065         val = I915_READ(PIPESRC(pipe));
8066         fb->width = ((val >> 16) & 0xfff) + 1;
8067         fb->height = ((val >> 0) & 0xfff) + 1;
8068
8069         val = I915_READ(DSPSTRIDE(pipe));
8070         fb->pitches[0] = val & 0xffffffc0;
8071
8072         aligned_height = intel_fb_align_height(dev, fb->height,
8073                                                fb->pixel_format,
8074                                                fb->modifier[0]);
8075
8076         plane_config->size = fb->pitches[0] * aligned_height;
8077
8078         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8079                       pipe_name(pipe), fb->width, fb->height,
8080                       fb->bits_per_pixel, base, fb->pitches[0],
8081                       plane_config->size);
8082
8083         plane_config->fb = intel_fb;
8084 }
8085
8086 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8087                                      struct intel_crtc_state *pipe_config)
8088 {
8089         struct drm_device *dev = crtc->base.dev;
8090         struct drm_i915_private *dev_priv = dev->dev_private;
8091         uint32_t tmp;
8092
8093         if (!intel_display_power_is_enabled(dev_priv,
8094                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8095                 return false;
8096
8097         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8098         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8099
8100         tmp = I915_READ(PIPECONF(crtc->pipe));
8101         if (!(tmp & PIPECONF_ENABLE))
8102                 return false;
8103
8104         switch (tmp & PIPECONF_BPC_MASK) {
8105         case PIPECONF_6BPC:
8106                 pipe_config->pipe_bpp = 18;
8107                 break;
8108         case PIPECONF_8BPC:
8109                 pipe_config->pipe_bpp = 24;
8110                 break;
8111         case PIPECONF_10BPC:
8112                 pipe_config->pipe_bpp = 30;
8113                 break;
8114         case PIPECONF_12BPC:
8115                 pipe_config->pipe_bpp = 36;
8116                 break;
8117         default:
8118                 break;
8119         }
8120
8121         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8122                 pipe_config->limited_color_range = true;
8123
8124         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8125                 struct intel_shared_dpll *pll;
8126
8127                 pipe_config->has_pch_encoder = true;
8128
8129                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8130                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8131                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8132
8133                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8134
8135                 if (HAS_PCH_IBX(dev_priv->dev)) {
8136                         pipe_config->shared_dpll =
8137                                 (enum intel_dpll_id) crtc->pipe;
8138                 } else {
8139                         tmp = I915_READ(PCH_DPLL_SEL);
8140                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8141                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8142                         else
8143                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8144                 }
8145
8146                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8147
8148                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8149                                            &pipe_config->dpll_hw_state));
8150
8151                 tmp = pipe_config->dpll_hw_state.dpll;
8152                 pipe_config->pixel_multiplier =
8153                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8154                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8155
8156                 ironlake_pch_clock_get(crtc, pipe_config);
8157         } else {
8158                 pipe_config->pixel_multiplier = 1;
8159         }
8160
8161         intel_get_pipe_timings(crtc, pipe_config);
8162
8163         ironlake_get_pfit_config(crtc, pipe_config);
8164
8165         return true;
8166 }
8167
8168 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8169 {
8170         struct drm_device *dev = dev_priv->dev;
8171         struct intel_crtc *crtc;
8172
8173         for_each_intel_crtc(dev, crtc)
8174                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8175                      pipe_name(crtc->pipe));
8176
8177         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8178         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8179         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8180         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8181         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8182         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8183              "CPU PWM1 enabled\n");
8184         if (IS_HASWELL(dev))
8185                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8186                      "CPU PWM2 enabled\n");
8187         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8188              "PCH PWM1 enabled\n");
8189         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8190              "Utility pin enabled\n");
8191         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8192
8193         /*
8194          * In theory we can still leave IRQs enabled, as long as only the HPD
8195          * interrupts remain enabled. We used to check for that, but since it's
8196          * gen-specific and since we only disable LCPLL after we fully disable
8197          * the interrupts, the check below should be enough.
8198          */
8199         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8200 }
8201
8202 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8203 {
8204         struct drm_device *dev = dev_priv->dev;
8205
8206         if (IS_HASWELL(dev))
8207                 return I915_READ(D_COMP_HSW);
8208         else
8209                 return I915_READ(D_COMP_BDW);
8210 }
8211
8212 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8213 {
8214         struct drm_device *dev = dev_priv->dev;
8215
8216         if (IS_HASWELL(dev)) {
8217                 mutex_lock(&dev_priv->rps.hw_lock);
8218                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8219                                             val))
8220                         DRM_ERROR("Failed to write to D_COMP\n");
8221                 mutex_unlock(&dev_priv->rps.hw_lock);
8222         } else {
8223                 I915_WRITE(D_COMP_BDW, val);
8224                 POSTING_READ(D_COMP_BDW);
8225         }
8226 }
8227
8228 /*
8229  * This function implements pieces of two sequences from BSpec:
8230  * - Sequence for display software to disable LCPLL
8231  * - Sequence for display software to allow package C8+
8232  * The steps implemented here are just the steps that actually touch the LCPLL
8233  * register. Callers should take care of disabling all the display engine
8234  * functions, doing the mode unset, fixing interrupts, etc.
8235  */
8236 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8237                               bool switch_to_fclk, bool allow_power_down)
8238 {
8239         uint32_t val;
8240
8241         assert_can_disable_lcpll(dev_priv);
8242
8243         val = I915_READ(LCPLL_CTL);
8244
8245         if (switch_to_fclk) {
8246                 val |= LCPLL_CD_SOURCE_FCLK;
8247                 I915_WRITE(LCPLL_CTL, val);
8248
8249                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8250                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
8251                         DRM_ERROR("Switching to FCLK failed\n");
8252
8253                 val = I915_READ(LCPLL_CTL);
8254         }
8255
8256         val |= LCPLL_PLL_DISABLE;
8257         I915_WRITE(LCPLL_CTL, val);
8258         POSTING_READ(LCPLL_CTL);
8259
8260         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8261                 DRM_ERROR("LCPLL still locked\n");
8262
8263         val = hsw_read_dcomp(dev_priv);
8264         val |= D_COMP_COMP_DISABLE;
8265         hsw_write_dcomp(dev_priv, val);
8266         ndelay(100);
8267
8268         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8269                      1))
8270                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8271
8272         if (allow_power_down) {
8273                 val = I915_READ(LCPLL_CTL);
8274                 val |= LCPLL_POWER_DOWN_ALLOW;
8275                 I915_WRITE(LCPLL_CTL, val);
8276                 POSTING_READ(LCPLL_CTL);
8277         }
8278 }
8279
8280 /*
8281  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8282  * source.
8283  */
8284 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8285 {
8286         uint32_t val;
8287
8288         val = I915_READ(LCPLL_CTL);
8289
8290         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8291                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8292                 return;
8293
8294         /*
8295          * Make sure we're not on PC8 state before disabling PC8, otherwise
8296          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8297          */
8298         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8299
8300         if (val & LCPLL_POWER_DOWN_ALLOW) {
8301                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8302                 I915_WRITE(LCPLL_CTL, val);
8303                 POSTING_READ(LCPLL_CTL);
8304         }
8305
8306         val = hsw_read_dcomp(dev_priv);
8307         val |= D_COMP_COMP_FORCE;
8308         val &= ~D_COMP_COMP_DISABLE;
8309         hsw_write_dcomp(dev_priv, val);
8310
8311         val = I915_READ(LCPLL_CTL);
8312         val &= ~LCPLL_PLL_DISABLE;
8313         I915_WRITE(LCPLL_CTL, val);
8314
8315         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8316                 DRM_ERROR("LCPLL not locked yet\n");
8317
8318         if (val & LCPLL_CD_SOURCE_FCLK) {
8319                 val = I915_READ(LCPLL_CTL);
8320                 val &= ~LCPLL_CD_SOURCE_FCLK;
8321                 I915_WRITE(LCPLL_CTL, val);
8322
8323                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8324                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8325                         DRM_ERROR("Switching back to LCPLL failed\n");
8326         }
8327
8328         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8329 }
8330
8331 /*
8332  * Package states C8 and deeper are really deep PC states that can only be
8333  * reached when all the devices on the system allow it, so even if the graphics
8334  * device allows PC8+, it doesn't mean the system will actually get to these
8335  * states. Our driver only allows PC8+ when going into runtime PM.
8336  *
8337  * The requirements for PC8+ are that all the outputs are disabled, the power
8338  * well is disabled and most interrupts are disabled, and these are also
8339  * requirements for runtime PM. When these conditions are met, we manually do
8340  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8341  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8342  * hang the machine.
8343  *
8344  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8345  * the state of some registers, so when we come back from PC8+ we need to
8346  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8347  * need to take care of the registers kept by RC6. Notice that this happens even
8348  * if we don't put the device in PCI D3 state (which is what currently happens
8349  * because of the runtime PM support).
8350  *
8351  * For more, read "Display Sequences for Package C8" on the hardware
8352  * documentation.
8353  */
8354 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8355 {
8356         struct drm_device *dev = dev_priv->dev;
8357         uint32_t val;
8358
8359         DRM_DEBUG_KMS("Enabling package C8+\n");
8360
8361         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8362                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8363                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8364                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8365         }
8366
8367         lpt_disable_clkout_dp(dev);
8368         hsw_disable_lcpll(dev_priv, true, true);
8369 }
8370
8371 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8372 {
8373         struct drm_device *dev = dev_priv->dev;
8374         uint32_t val;
8375
8376         DRM_DEBUG_KMS("Disabling package C8+\n");
8377
8378         hsw_restore_lcpll(dev_priv);
8379         lpt_init_pch_refclk(dev);
8380
8381         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8382                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8383                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8384                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8385         }
8386
8387         intel_prepare_ddi(dev);
8388 }
8389
8390 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8391                                       struct intel_crtc_state *crtc_state)
8392 {
8393         if (!intel_ddi_pll_select(crtc, crtc_state))
8394                 return -EINVAL;
8395
8396         crtc->lowfreq_avail = false;
8397
8398         return 0;
8399 }
8400
8401 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8402                                 enum port port,
8403                                 struct intel_crtc_state *pipe_config)
8404 {
8405         u32 temp, dpll_ctl1;
8406
8407         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8408         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8409
8410         switch (pipe_config->ddi_pll_sel) {
8411         case SKL_DPLL0:
8412                 /*
8413                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8414                  * of the shared DPLL framework and thus needs to be read out
8415                  * separately
8416                  */
8417                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8418                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8419                 break;
8420         case SKL_DPLL1:
8421                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8422                 break;
8423         case SKL_DPLL2:
8424                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8425                 break;
8426         case SKL_DPLL3:
8427                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8428                 break;
8429         }
8430 }
8431
8432 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8433                                 enum port port,
8434                                 struct intel_crtc_state *pipe_config)
8435 {
8436         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8437
8438         switch (pipe_config->ddi_pll_sel) {
8439         case PORT_CLK_SEL_WRPLL1:
8440                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8441                 break;
8442         case PORT_CLK_SEL_WRPLL2:
8443                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8444                 break;
8445         }
8446 }
8447
8448 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8449                                        struct intel_crtc_state *pipe_config)
8450 {
8451         struct drm_device *dev = crtc->base.dev;
8452         struct drm_i915_private *dev_priv = dev->dev_private;
8453         struct intel_shared_dpll *pll;
8454         enum port port;
8455         uint32_t tmp;
8456
8457         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8458
8459         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8460
8461         if (IS_SKYLAKE(dev))
8462                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8463         else
8464                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8465
8466         if (pipe_config->shared_dpll >= 0) {
8467                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8468
8469                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8470                                            &pipe_config->dpll_hw_state));
8471         }
8472
8473         /*
8474          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8475          * DDI E. So just check whether this pipe is wired to DDI E and whether
8476          * the PCH transcoder is on.
8477          */
8478         if (INTEL_INFO(dev)->gen < 9 &&
8479             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8480                 pipe_config->has_pch_encoder = true;
8481
8482                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8483                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8484                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8485
8486                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8487         }
8488 }
8489
8490 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8491                                     struct intel_crtc_state *pipe_config)
8492 {
8493         struct drm_device *dev = crtc->base.dev;
8494         struct drm_i915_private *dev_priv = dev->dev_private;
8495         enum intel_display_power_domain pfit_domain;
8496         uint32_t tmp;
8497
8498         if (!intel_display_power_is_enabled(dev_priv,
8499                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8500                 return false;
8501
8502         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8503         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8504
8505         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8506         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8507                 enum pipe trans_edp_pipe;
8508                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8509                 default:
8510                         WARN(1, "unknown pipe linked to edp transcoder\n");
8511                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8512                 case TRANS_DDI_EDP_INPUT_A_ON:
8513                         trans_edp_pipe = PIPE_A;
8514                         break;
8515                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8516                         trans_edp_pipe = PIPE_B;
8517                         break;
8518                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8519                         trans_edp_pipe = PIPE_C;
8520                         break;
8521                 }
8522
8523                 if (trans_edp_pipe == crtc->pipe)
8524                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8525         }
8526
8527         if (!intel_display_power_is_enabled(dev_priv,
8528                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8529                 return false;
8530
8531         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8532         if (!(tmp & PIPECONF_ENABLE))
8533                 return false;
8534
8535         haswell_get_ddi_port_state(crtc, pipe_config);
8536
8537         intel_get_pipe_timings(crtc, pipe_config);
8538
8539         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8540         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8541                 if (IS_SKYLAKE(dev))
8542                         skylake_get_pfit_config(crtc, pipe_config);
8543                 else
8544                         ironlake_get_pfit_config(crtc, pipe_config);
8545         }
8546
8547         if (IS_HASWELL(dev))
8548                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8549                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8550
8551         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8552                 pipe_config->pixel_multiplier =
8553                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8554         } else {
8555                 pipe_config->pixel_multiplier = 1;
8556         }
8557
8558         return true;
8559 }
8560
8561 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8562 {
8563         struct drm_device *dev = crtc->dev;
8564         struct drm_i915_private *dev_priv = dev->dev_private;
8565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8566         uint32_t cntl = 0, size = 0;
8567
8568         if (base) {
8569                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8570                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8571                 unsigned int stride = roundup_pow_of_two(width) * 4;
8572
8573                 switch (stride) {
8574                 default:
8575                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8576                                   width, stride);
8577                         stride = 256;
8578                         /* fallthrough */
8579                 case 256:
8580                 case 512:
8581                 case 1024:
8582                 case 2048:
8583                         break;
8584                 }
8585
8586                 cntl |= CURSOR_ENABLE |
8587                         CURSOR_GAMMA_ENABLE |
8588                         CURSOR_FORMAT_ARGB |
8589                         CURSOR_STRIDE(stride);
8590
8591                 size = (height << 12) | width;
8592         }
8593
8594         if (intel_crtc->cursor_cntl != 0 &&
8595             (intel_crtc->cursor_base != base ||
8596              intel_crtc->cursor_size != size ||
8597              intel_crtc->cursor_cntl != cntl)) {
8598                 /* On these chipsets we can only modify the base/size/stride
8599                  * whilst the cursor is disabled.
8600                  */
8601                 I915_WRITE(_CURACNTR, 0);
8602                 POSTING_READ(_CURACNTR);
8603                 intel_crtc->cursor_cntl = 0;
8604         }
8605
8606         if (intel_crtc->cursor_base != base) {
8607                 I915_WRITE(_CURABASE, base);
8608                 intel_crtc->cursor_base = base;
8609         }
8610
8611         if (intel_crtc->cursor_size != size) {
8612                 I915_WRITE(CURSIZE, size);
8613                 intel_crtc->cursor_size = size;
8614         }
8615
8616         if (intel_crtc->cursor_cntl != cntl) {
8617                 I915_WRITE(_CURACNTR, cntl);
8618                 POSTING_READ(_CURACNTR);
8619                 intel_crtc->cursor_cntl = cntl;
8620         }
8621 }
8622
8623 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8624 {
8625         struct drm_device *dev = crtc->dev;
8626         struct drm_i915_private *dev_priv = dev->dev_private;
8627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8628         int pipe = intel_crtc->pipe;
8629         uint32_t cntl;
8630
8631         cntl = 0;
8632         if (base) {
8633                 cntl = MCURSOR_GAMMA_ENABLE;
8634                 switch (intel_crtc->base.cursor->state->crtc_w) {
8635                         case 64:
8636                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8637                                 break;
8638                         case 128:
8639                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8640                                 break;
8641                         case 256:
8642                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8643                                 break;
8644                         default:
8645                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8646                                 return;
8647                 }
8648                 cntl |= pipe << 28; /* Connect to correct pipe */
8649
8650                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8651                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8652         }
8653
8654         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8655                 cntl |= CURSOR_ROTATE_180;
8656
8657         if (intel_crtc->cursor_cntl != cntl) {
8658                 I915_WRITE(CURCNTR(pipe), cntl);
8659                 POSTING_READ(CURCNTR(pipe));
8660                 intel_crtc->cursor_cntl = cntl;
8661         }
8662
8663         /* and commit changes on next vblank */
8664         I915_WRITE(CURBASE(pipe), base);
8665         POSTING_READ(CURBASE(pipe));
8666
8667         intel_crtc->cursor_base = base;
8668 }
8669
8670 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8671 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8672                                      bool on)
8673 {
8674         struct drm_device *dev = crtc->dev;
8675         struct drm_i915_private *dev_priv = dev->dev_private;
8676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8677         int pipe = intel_crtc->pipe;
8678         int x = crtc->cursor_x;
8679         int y = crtc->cursor_y;
8680         u32 base = 0, pos = 0;
8681
8682         if (on)
8683                 base = intel_crtc->cursor_addr;
8684
8685         if (x >= intel_crtc->config->pipe_src_w)
8686                 base = 0;
8687
8688         if (y >= intel_crtc->config->pipe_src_h)
8689                 base = 0;
8690
8691         if (x < 0) {
8692                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8693                         base = 0;
8694
8695                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8696                 x = -x;
8697         }
8698         pos |= x << CURSOR_X_SHIFT;
8699
8700         if (y < 0) {
8701                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8702                         base = 0;
8703
8704                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8705                 y = -y;
8706         }
8707         pos |= y << CURSOR_Y_SHIFT;
8708
8709         if (base == 0 && intel_crtc->cursor_base == 0)
8710                 return;
8711
8712         I915_WRITE(CURPOS(pipe), pos);
8713
8714         /* ILK+ do this automagically */
8715         if (HAS_GMCH_DISPLAY(dev) &&
8716             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8717                 base += (intel_crtc->base.cursor->state->crtc_h *
8718                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8719         }
8720
8721         if (IS_845G(dev) || IS_I865G(dev))
8722                 i845_update_cursor(crtc, base);
8723         else
8724                 i9xx_update_cursor(crtc, base);
8725 }
8726
8727 static bool cursor_size_ok(struct drm_device *dev,
8728                            uint32_t width, uint32_t height)
8729 {
8730         if (width == 0 || height == 0)
8731                 return false;
8732
8733         /*
8734          * 845g/865g are special in that they are only limited by
8735          * the width of their cursors, the height is arbitrary up to
8736          * the precision of the register. Everything else requires
8737          * square cursors, limited to a few power-of-two sizes.
8738          */
8739         if (IS_845G(dev) || IS_I865G(dev)) {
8740                 if ((width & 63) != 0)
8741                         return false;
8742
8743                 if (width > (IS_845G(dev) ? 64 : 512))
8744                         return false;
8745
8746                 if (height > 1023)
8747                         return false;
8748         } else {
8749                 switch (width | height) {
8750                 case 256:
8751                 case 128:
8752                         if (IS_GEN2(dev))
8753                                 return false;
8754                 case 64:
8755                         break;
8756                 default:
8757                         return false;
8758                 }
8759         }
8760
8761         return true;
8762 }
8763
8764 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8765                                  u16 *blue, uint32_t start, uint32_t size)
8766 {
8767         int end = (start + size > 256) ? 256 : start + size, i;
8768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8769
8770         for (i = start; i < end; i++) {
8771                 intel_crtc->lut_r[i] = red[i] >> 8;
8772                 intel_crtc->lut_g[i] = green[i] >> 8;
8773                 intel_crtc->lut_b[i] = blue[i] >> 8;
8774         }
8775
8776         intel_crtc_load_lut(crtc);
8777 }
8778
8779 /* VESA 640x480x72Hz mode to set on the pipe */
8780 static struct drm_display_mode load_detect_mode = {
8781         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8782                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8783 };
8784
8785 struct drm_framebuffer *
8786 __intel_framebuffer_create(struct drm_device *dev,
8787                            struct drm_mode_fb_cmd2 *mode_cmd,
8788                            struct drm_i915_gem_object *obj)
8789 {
8790         struct intel_framebuffer *intel_fb;
8791         int ret;
8792
8793         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8794         if (!intel_fb) {
8795                 drm_gem_object_unreference(&obj->base);
8796                 return ERR_PTR(-ENOMEM);
8797         }
8798
8799         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8800         if (ret)
8801                 goto err;
8802
8803         return &intel_fb->base;
8804 err:
8805         drm_gem_object_unreference(&obj->base);
8806         kfree(intel_fb);
8807
8808         return ERR_PTR(ret);
8809 }
8810
8811 static struct drm_framebuffer *
8812 intel_framebuffer_create(struct drm_device *dev,
8813                          struct drm_mode_fb_cmd2 *mode_cmd,
8814                          struct drm_i915_gem_object *obj)
8815 {
8816         struct drm_framebuffer *fb;
8817         int ret;
8818
8819         ret = i915_mutex_lock_interruptible(dev);
8820         if (ret)
8821                 return ERR_PTR(ret);
8822         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8823         mutex_unlock(&dev->struct_mutex);
8824
8825         return fb;
8826 }
8827
8828 static u32
8829 intel_framebuffer_pitch_for_width(int width, int bpp)
8830 {
8831         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8832         return ALIGN(pitch, 64);
8833 }
8834
8835 static u32
8836 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8837 {
8838         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8839         return PAGE_ALIGN(pitch * mode->vdisplay);
8840 }
8841
8842 static struct drm_framebuffer *
8843 intel_framebuffer_create_for_mode(struct drm_device *dev,
8844                                   struct drm_display_mode *mode,
8845                                   int depth, int bpp)
8846 {
8847         struct drm_i915_gem_object *obj;
8848         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8849
8850         obj = i915_gem_alloc_object(dev,
8851                                     intel_framebuffer_size_for_mode(mode, bpp));
8852         if (obj == NULL)
8853                 return ERR_PTR(-ENOMEM);
8854
8855         mode_cmd.width = mode->hdisplay;
8856         mode_cmd.height = mode->vdisplay;
8857         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8858                                                                 bpp);
8859         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8860
8861         return intel_framebuffer_create(dev, &mode_cmd, obj);
8862 }
8863
8864 static struct drm_framebuffer *
8865 mode_fits_in_fbdev(struct drm_device *dev,
8866                    struct drm_display_mode *mode)
8867 {
8868 #ifdef CONFIG_DRM_I915_FBDEV
8869         struct drm_i915_private *dev_priv = dev->dev_private;
8870         struct drm_i915_gem_object *obj;
8871         struct drm_framebuffer *fb;
8872
8873         if (!dev_priv->fbdev)
8874                 return NULL;
8875
8876         if (!dev_priv->fbdev->fb)
8877                 return NULL;
8878
8879         obj = dev_priv->fbdev->fb->obj;
8880         BUG_ON(!obj);
8881
8882         fb = &dev_priv->fbdev->fb->base;
8883         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8884                                                                fb->bits_per_pixel))
8885                 return NULL;
8886
8887         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8888                 return NULL;
8889
8890         return fb;
8891 #else
8892         return NULL;
8893 #endif
8894 }
8895
8896 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8897                                 struct drm_display_mode *mode,
8898                                 struct intel_load_detect_pipe *old,
8899                                 struct drm_modeset_acquire_ctx *ctx)
8900 {
8901         struct intel_crtc *intel_crtc;
8902         struct intel_encoder *intel_encoder =
8903                 intel_attached_encoder(connector);
8904         struct drm_crtc *possible_crtc;
8905         struct drm_encoder *encoder = &intel_encoder->base;
8906         struct drm_crtc *crtc = NULL;
8907         struct drm_device *dev = encoder->dev;
8908         struct drm_framebuffer *fb;
8909         struct drm_mode_config *config = &dev->mode_config;
8910         int ret, i = -1;
8911
8912         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8913                       connector->base.id, connector->name,
8914                       encoder->base.id, encoder->name);
8915
8916 retry:
8917         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8918         if (ret)
8919                 goto fail_unlock;
8920
8921         /*
8922          * Algorithm gets a little messy:
8923          *
8924          *   - if the connector already has an assigned crtc, use it (but make
8925          *     sure it's on first)
8926          *
8927          *   - try to find the first unused crtc that can drive this connector,
8928          *     and use that if we find one
8929          */
8930
8931         /* See if we already have a CRTC for this connector */
8932         if (encoder->crtc) {
8933                 crtc = encoder->crtc;
8934
8935                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8936                 if (ret)
8937                         goto fail_unlock;
8938                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8939                 if (ret)
8940                         goto fail_unlock;
8941
8942                 old->dpms_mode = connector->dpms;
8943                 old->load_detect_temp = false;
8944
8945                 /* Make sure the crtc and connector are running */
8946                 if (connector->dpms != DRM_MODE_DPMS_ON)
8947                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8948
8949                 return true;
8950         }
8951
8952         /* Find an unused one (if possible) */
8953         for_each_crtc(dev, possible_crtc) {
8954                 i++;
8955                 if (!(encoder->possible_crtcs & (1 << i)))
8956                         continue;
8957                 if (possible_crtc->state->enable)
8958                         continue;
8959                 /* This can occur when applying the pipe A quirk on resume. */
8960                 if (to_intel_crtc(possible_crtc)->new_enabled)
8961                         continue;
8962
8963                 crtc = possible_crtc;
8964                 break;
8965         }
8966
8967         /*
8968          * If we didn't find an unused CRTC, don't use any.
8969          */
8970         if (!crtc) {
8971                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8972                 goto fail_unlock;
8973         }
8974
8975         ret = drm_modeset_lock(&crtc->mutex, ctx);
8976         if (ret)
8977                 goto fail_unlock;
8978         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8979         if (ret)
8980                 goto fail_unlock;
8981         intel_encoder->new_crtc = to_intel_crtc(crtc);
8982         to_intel_connector(connector)->new_encoder = intel_encoder;
8983
8984         intel_crtc = to_intel_crtc(crtc);
8985         intel_crtc->new_enabled = true;
8986         intel_crtc->new_config = intel_crtc->config;
8987         old->dpms_mode = connector->dpms;
8988         old->load_detect_temp = true;
8989         old->release_fb = NULL;
8990
8991         if (!mode)
8992                 mode = &load_detect_mode;
8993
8994         /* We need a framebuffer large enough to accommodate all accesses
8995          * that the plane may generate whilst we perform load detection.
8996          * We can not rely on the fbcon either being present (we get called
8997          * during its initialisation to detect all boot displays, or it may
8998          * not even exist) or that it is large enough to satisfy the
8999          * requested mode.
9000          */
9001         fb = mode_fits_in_fbdev(dev, mode);
9002         if (fb == NULL) {
9003                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9004                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9005                 old->release_fb = fb;
9006         } else
9007                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9008         if (IS_ERR(fb)) {
9009                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9010                 goto fail;
9011         }
9012
9013         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
9014                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9015                 if (old->release_fb)
9016                         old->release_fb->funcs->destroy(old->release_fb);
9017                 goto fail;
9018         }
9019         crtc->primary->crtc = crtc;
9020
9021         /* let the connector get through one full cycle before testing */
9022         intel_wait_for_vblank(dev, intel_crtc->pipe);
9023         return true;
9024
9025  fail:
9026         intel_crtc->new_enabled = crtc->state->enable;
9027         if (intel_crtc->new_enabled)
9028                 intel_crtc->new_config = intel_crtc->config;
9029         else
9030                 intel_crtc->new_config = NULL;
9031 fail_unlock:
9032         if (ret == -EDEADLK) {
9033                 drm_modeset_backoff(ctx);
9034                 goto retry;
9035         }
9036
9037         return false;
9038 }
9039
9040 void intel_release_load_detect_pipe(struct drm_connector *connector,
9041                                     struct intel_load_detect_pipe *old,
9042                                     struct drm_modeset_acquire_ctx *ctx)
9043 {
9044         struct intel_encoder *intel_encoder =
9045                 intel_attached_encoder(connector);
9046         struct drm_encoder *encoder = &intel_encoder->base;
9047         struct drm_crtc *crtc = encoder->crtc;
9048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9049
9050         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9051                       connector->base.id, connector->name,
9052                       encoder->base.id, encoder->name);
9053
9054         if (old->load_detect_temp) {
9055                 to_intel_connector(connector)->new_encoder = NULL;
9056                 intel_encoder->new_crtc = NULL;
9057                 intel_crtc->new_enabled = false;
9058                 intel_crtc->new_config = NULL;
9059                 intel_set_mode(crtc, NULL, 0, 0, NULL);
9060
9061                 if (old->release_fb) {
9062                         drm_framebuffer_unregister_private(old->release_fb);
9063                         drm_framebuffer_unreference(old->release_fb);
9064                 }
9065
9066                 return;
9067         }
9068
9069         /* Switch crtc and encoder back off if necessary */
9070         if (old->dpms_mode != DRM_MODE_DPMS_ON)
9071                 connector->funcs->dpms(connector, old->dpms_mode);
9072 }
9073
9074 static int i9xx_pll_refclk(struct drm_device *dev,
9075                            const struct intel_crtc_state *pipe_config)
9076 {
9077         struct drm_i915_private *dev_priv = dev->dev_private;
9078         u32 dpll = pipe_config->dpll_hw_state.dpll;
9079
9080         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9081                 return dev_priv->vbt.lvds_ssc_freq;
9082         else if (HAS_PCH_SPLIT(dev))
9083                 return 120000;
9084         else if (!IS_GEN2(dev))
9085                 return 96000;
9086         else
9087                 return 48000;
9088 }
9089
9090 /* Returns the clock of the currently programmed mode of the given pipe. */
9091 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9092                                 struct intel_crtc_state *pipe_config)
9093 {
9094         struct drm_device *dev = crtc->base.dev;
9095         struct drm_i915_private *dev_priv = dev->dev_private;
9096         int pipe = pipe_config->cpu_transcoder;
9097         u32 dpll = pipe_config->dpll_hw_state.dpll;
9098         u32 fp;
9099         intel_clock_t clock;
9100         int refclk = i9xx_pll_refclk(dev, pipe_config);
9101
9102         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9103                 fp = pipe_config->dpll_hw_state.fp0;
9104         else
9105                 fp = pipe_config->dpll_hw_state.fp1;
9106
9107         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9108         if (IS_PINEVIEW(dev)) {
9109                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9110                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9111         } else {
9112                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9113                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9114         }
9115
9116         if (!IS_GEN2(dev)) {
9117                 if (IS_PINEVIEW(dev))
9118                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9119                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9120                 else
9121                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9122                                DPLL_FPA01_P1_POST_DIV_SHIFT);
9123
9124                 switch (dpll & DPLL_MODE_MASK) {
9125                 case DPLLB_MODE_DAC_SERIAL:
9126                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9127                                 5 : 10;
9128                         break;
9129                 case DPLLB_MODE_LVDS:
9130                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9131                                 7 : 14;
9132                         break;
9133                 default:
9134                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9135                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9136                         return;
9137                 }
9138
9139                 if (IS_PINEVIEW(dev))
9140                         pineview_clock(refclk, &clock);
9141                 else
9142                         i9xx_clock(refclk, &clock);
9143         } else {
9144                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9145                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9146
9147                 if (is_lvds) {
9148                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9149                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9150
9151                         if (lvds & LVDS_CLKB_POWER_UP)
9152                                 clock.p2 = 7;
9153                         else
9154                                 clock.p2 = 14;
9155                 } else {
9156                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9157                                 clock.p1 = 2;
9158                         else {
9159                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9160                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9161                         }
9162                         if (dpll & PLL_P2_DIVIDE_BY_4)
9163                                 clock.p2 = 4;
9164                         else
9165                                 clock.p2 = 2;
9166                 }
9167
9168                 i9xx_clock(refclk, &clock);
9169         }
9170
9171         /*
9172          * This value includes pixel_multiplier. We will use
9173          * port_clock to compute adjusted_mode.crtc_clock in the
9174          * encoder's get_config() function.
9175          */
9176         pipe_config->port_clock = clock.dot;
9177 }
9178
9179 int intel_dotclock_calculate(int link_freq,
9180                              const struct intel_link_m_n *m_n)
9181 {
9182         /*
9183          * The calculation for the data clock is:
9184          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9185          * But we want to avoid losing precison if possible, so:
9186          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9187          *
9188          * and the link clock is simpler:
9189          * link_clock = (m * link_clock) / n
9190          */
9191
9192         if (!m_n->link_n)
9193                 return 0;
9194
9195         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9196 }
9197
9198 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9199                                    struct intel_crtc_state *pipe_config)
9200 {
9201         struct drm_device *dev = crtc->base.dev;
9202
9203         /* read out port_clock from the DPLL */
9204         i9xx_crtc_clock_get(crtc, pipe_config);
9205
9206         /*
9207          * This value does not include pixel_multiplier.
9208          * We will check that port_clock and adjusted_mode.crtc_clock
9209          * agree once we know their relationship in the encoder's
9210          * get_config() function.
9211          */
9212         pipe_config->base.adjusted_mode.crtc_clock =
9213                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9214                                          &pipe_config->fdi_m_n);
9215 }
9216
9217 /** Returns the currently programmed mode of the given pipe. */
9218 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9219                                              struct drm_crtc *crtc)
9220 {
9221         struct drm_i915_private *dev_priv = dev->dev_private;
9222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9223         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9224         struct drm_display_mode *mode;
9225         struct intel_crtc_state pipe_config;
9226         int htot = I915_READ(HTOTAL(cpu_transcoder));
9227         int hsync = I915_READ(HSYNC(cpu_transcoder));
9228         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9229         int vsync = I915_READ(VSYNC(cpu_transcoder));
9230         enum pipe pipe = intel_crtc->pipe;
9231
9232         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9233         if (!mode)
9234                 return NULL;
9235
9236         /*
9237          * Construct a pipe_config sufficient for getting the clock info
9238          * back out of crtc_clock_get.
9239          *
9240          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9241          * to use a real value here instead.
9242          */
9243         pipe_config.cpu_transcoder = (enum transcoder) pipe;
9244         pipe_config.pixel_multiplier = 1;
9245         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9246         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9247         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9248         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9249
9250         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9251         mode->hdisplay = (htot & 0xffff) + 1;
9252         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9253         mode->hsync_start = (hsync & 0xffff) + 1;
9254         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9255         mode->vdisplay = (vtot & 0xffff) + 1;
9256         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9257         mode->vsync_start = (vsync & 0xffff) + 1;
9258         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9259
9260         drm_mode_set_name(mode);
9261
9262         return mode;
9263 }
9264
9265 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9266 {
9267         struct drm_device *dev = crtc->dev;
9268         struct drm_i915_private *dev_priv = dev->dev_private;
9269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9270
9271         if (!HAS_GMCH_DISPLAY(dev))
9272                 return;
9273
9274         if (!dev_priv->lvds_downclock_avail)
9275                 return;
9276
9277         /*
9278          * Since this is called by a timer, we should never get here in
9279          * the manual case.
9280          */
9281         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9282                 int pipe = intel_crtc->pipe;
9283                 int dpll_reg = DPLL(pipe);
9284                 int dpll;
9285
9286                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9287
9288                 assert_panel_unlocked(dev_priv, pipe);
9289
9290                 dpll = I915_READ(dpll_reg);
9291                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9292                 I915_WRITE(dpll_reg, dpll);
9293                 intel_wait_for_vblank(dev, pipe);
9294                 dpll = I915_READ(dpll_reg);
9295                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9296                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9297         }
9298
9299 }
9300
9301 void intel_mark_busy(struct drm_device *dev)
9302 {
9303         struct drm_i915_private *dev_priv = dev->dev_private;
9304
9305         if (dev_priv->mm.busy)
9306                 return;
9307
9308         intel_runtime_pm_get(dev_priv);
9309         i915_update_gfx_val(dev_priv);
9310         if (INTEL_INFO(dev)->gen >= 6)
9311                 gen6_rps_busy(dev_priv);
9312         dev_priv->mm.busy = true;
9313 }
9314
9315 void intel_mark_idle(struct drm_device *dev)
9316 {
9317         struct drm_i915_private *dev_priv = dev->dev_private;
9318         struct drm_crtc *crtc;
9319
9320         if (!dev_priv->mm.busy)
9321                 return;
9322
9323         dev_priv->mm.busy = false;
9324
9325         for_each_crtc(dev, crtc) {
9326                 if (!crtc->primary->fb)
9327                         continue;
9328
9329                 intel_decrease_pllclock(crtc);
9330         }
9331
9332         if (INTEL_INFO(dev)->gen >= 6)
9333                 gen6_rps_idle(dev->dev_private);
9334
9335         intel_runtime_pm_put(dev_priv);
9336 }
9337
9338 static void intel_crtc_set_state(struct intel_crtc *crtc,
9339                                  struct intel_crtc_state *crtc_state)
9340 {
9341         kfree(crtc->config);
9342         crtc->config = crtc_state;
9343         crtc->base.state = &crtc_state->base;
9344 }
9345
9346 static void intel_crtc_destroy(struct drm_crtc *crtc)
9347 {
9348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9349         struct drm_device *dev = crtc->dev;
9350         struct intel_unpin_work *work;
9351
9352         spin_lock_irq(&dev->event_lock);
9353         work = intel_crtc->unpin_work;
9354         intel_crtc->unpin_work = NULL;
9355         spin_unlock_irq(&dev->event_lock);
9356
9357         if (work) {
9358                 cancel_work_sync(&work->work);
9359                 kfree(work);
9360         }
9361
9362         intel_crtc_set_state(intel_crtc, NULL);
9363         drm_crtc_cleanup(crtc);
9364
9365         kfree(intel_crtc);
9366 }
9367
9368 static void intel_unpin_work_fn(struct work_struct *__work)
9369 {
9370         struct intel_unpin_work *work =
9371                 container_of(__work, struct intel_unpin_work, work);
9372         struct drm_device *dev = work->crtc->dev;
9373         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9374
9375         mutex_lock(&dev->struct_mutex);
9376         intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
9377         drm_gem_object_unreference(&work->pending_flip_obj->base);
9378
9379         intel_fbc_update(dev);
9380
9381         if (work->flip_queued_req)
9382                 i915_gem_request_assign(&work->flip_queued_req, NULL);
9383         mutex_unlock(&dev->struct_mutex);
9384
9385         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9386         drm_framebuffer_unreference(work->old_fb);
9387
9388         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9389         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9390
9391         kfree(work);
9392 }
9393
9394 static void do_intel_finish_page_flip(struct drm_device *dev,
9395                                       struct drm_crtc *crtc)
9396 {
9397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9398         struct intel_unpin_work *work;
9399         unsigned long flags;
9400
9401         /* Ignore early vblank irqs */
9402         if (intel_crtc == NULL)
9403                 return;
9404
9405         /*
9406          * This is called both by irq handlers and the reset code (to complete
9407          * lost pageflips) so needs the full irqsave spinlocks.
9408          */
9409         spin_lock_irqsave(&dev->event_lock, flags);
9410         work = intel_crtc->unpin_work;
9411
9412         /* Ensure we don't miss a work->pending update ... */
9413         smp_rmb();
9414
9415         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9416                 spin_unlock_irqrestore(&dev->event_lock, flags);
9417                 return;
9418         }
9419
9420         page_flip_completed(intel_crtc);
9421
9422         spin_unlock_irqrestore(&dev->event_lock, flags);
9423 }
9424
9425 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9426 {
9427         struct drm_i915_private *dev_priv = dev->dev_private;
9428         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9429
9430         do_intel_finish_page_flip(dev, crtc);
9431 }
9432
9433 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9434 {
9435         struct drm_i915_private *dev_priv = dev->dev_private;
9436         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9437
9438         do_intel_finish_page_flip(dev, crtc);
9439 }
9440
9441 /* Is 'a' after or equal to 'b'? */
9442 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9443 {
9444         return !((a - b) & 0x80000000);
9445 }
9446
9447 static bool page_flip_finished(struct intel_crtc *crtc)
9448 {
9449         struct drm_device *dev = crtc->base.dev;
9450         struct drm_i915_private *dev_priv = dev->dev_private;
9451
9452         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9453             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9454                 return true;
9455
9456         /*
9457          * The relevant registers doen't exist on pre-ctg.
9458          * As the flip done interrupt doesn't trigger for mmio
9459          * flips on gmch platforms, a flip count check isn't
9460          * really needed there. But since ctg has the registers,
9461          * include it in the check anyway.
9462          */
9463         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9464                 return true;
9465
9466         /*
9467          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9468          * used the same base address. In that case the mmio flip might
9469          * have completed, but the CS hasn't even executed the flip yet.
9470          *
9471          * A flip count check isn't enough as the CS might have updated
9472          * the base address just after start of vblank, but before we
9473          * managed to process the interrupt. This means we'd complete the
9474          * CS flip too soon.
9475          *
9476          * Combining both checks should get us a good enough result. It may
9477          * still happen that the CS flip has been executed, but has not
9478          * yet actually completed. But in case the base address is the same
9479          * anyway, we don't really care.
9480          */
9481         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9482                 crtc->unpin_work->gtt_offset &&
9483                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9484                                     crtc->unpin_work->flip_count);
9485 }
9486
9487 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9488 {
9489         struct drm_i915_private *dev_priv = dev->dev_private;
9490         struct intel_crtc *intel_crtc =
9491                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9492         unsigned long flags;
9493
9494
9495         /*
9496          * This is called both by irq handlers and the reset code (to complete
9497          * lost pageflips) so needs the full irqsave spinlocks.
9498          *
9499          * NB: An MMIO update of the plane base pointer will also
9500          * generate a page-flip completion irq, i.e. every modeset
9501          * is also accompanied by a spurious intel_prepare_page_flip().
9502          */
9503         spin_lock_irqsave(&dev->event_lock, flags);
9504         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9505                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9506         spin_unlock_irqrestore(&dev->event_lock, flags);
9507 }
9508
9509 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9510 {
9511         /* Ensure that the work item is consistent when activating it ... */
9512         smp_wmb();
9513         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9514         /* and that it is marked active as soon as the irq could fire. */
9515         smp_wmb();
9516 }
9517
9518 static int intel_gen2_queue_flip(struct drm_device *dev,
9519                                  struct drm_crtc *crtc,
9520                                  struct drm_framebuffer *fb,
9521                                  struct drm_i915_gem_object *obj,
9522                                  struct intel_engine_cs *ring,
9523                                  uint32_t flags)
9524 {
9525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9526         u32 flip_mask;
9527         int ret;
9528
9529         ret = intel_ring_begin(ring, 6);
9530         if (ret)
9531                 return ret;
9532
9533         /* Can't queue multiple flips, so wait for the previous
9534          * one to finish before executing the next.
9535          */
9536         if (intel_crtc->plane)
9537                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9538         else
9539                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9540         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9541         intel_ring_emit(ring, MI_NOOP);
9542         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9543                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9544         intel_ring_emit(ring, fb->pitches[0]);
9545         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9546         intel_ring_emit(ring, 0); /* aux display base address, unused */
9547
9548         intel_mark_page_flip_active(intel_crtc);
9549         __intel_ring_advance(ring);
9550         return 0;
9551 }
9552
9553 static int intel_gen3_queue_flip(struct drm_device *dev,
9554                                  struct drm_crtc *crtc,
9555                                  struct drm_framebuffer *fb,
9556                                  struct drm_i915_gem_object *obj,
9557                                  struct intel_engine_cs *ring,
9558                                  uint32_t flags)
9559 {
9560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9561         u32 flip_mask;
9562         int ret;
9563
9564         ret = intel_ring_begin(ring, 6);
9565         if (ret)
9566                 return ret;
9567
9568         if (intel_crtc->plane)
9569                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9570         else
9571                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9572         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9573         intel_ring_emit(ring, MI_NOOP);
9574         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9575                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9576         intel_ring_emit(ring, fb->pitches[0]);
9577         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9578         intel_ring_emit(ring, MI_NOOP);
9579
9580         intel_mark_page_flip_active(intel_crtc);
9581         __intel_ring_advance(ring);
9582         return 0;
9583 }
9584
9585 static int intel_gen4_queue_flip(struct drm_device *dev,
9586                                  struct drm_crtc *crtc,
9587                                  struct drm_framebuffer *fb,
9588                                  struct drm_i915_gem_object *obj,
9589                                  struct intel_engine_cs *ring,
9590                                  uint32_t flags)
9591 {
9592         struct drm_i915_private *dev_priv = dev->dev_private;
9593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9594         uint32_t pf, pipesrc;
9595         int ret;
9596
9597         ret = intel_ring_begin(ring, 4);
9598         if (ret)
9599                 return ret;
9600
9601         /* i965+ uses the linear or tiled offsets from the
9602          * Display Registers (which do not change across a page-flip)
9603          * so we need only reprogram the base address.
9604          */
9605         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9606                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9607         intel_ring_emit(ring, fb->pitches[0]);
9608         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9609                         obj->tiling_mode);
9610
9611         /* XXX Enabling the panel-fitter across page-flip is so far
9612          * untested on non-native modes, so ignore it for now.
9613          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9614          */
9615         pf = 0;
9616         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9617         intel_ring_emit(ring, pf | pipesrc);
9618
9619         intel_mark_page_flip_active(intel_crtc);
9620         __intel_ring_advance(ring);
9621         return 0;
9622 }
9623
9624 static int intel_gen6_queue_flip(struct drm_device *dev,
9625                                  struct drm_crtc *crtc,
9626                                  struct drm_framebuffer *fb,
9627                                  struct drm_i915_gem_object *obj,
9628                                  struct intel_engine_cs *ring,
9629                                  uint32_t flags)
9630 {
9631         struct drm_i915_private *dev_priv = dev->dev_private;
9632         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9633         uint32_t pf, pipesrc;
9634         int ret;
9635
9636         ret = intel_ring_begin(ring, 4);
9637         if (ret)
9638                 return ret;
9639
9640         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9641                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9642         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9643         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9644
9645         /* Contrary to the suggestions in the documentation,
9646          * "Enable Panel Fitter" does not seem to be required when page
9647          * flipping with a non-native mode, and worse causes a normal
9648          * modeset to fail.
9649          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9650          */
9651         pf = 0;
9652         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9653         intel_ring_emit(ring, pf | pipesrc);
9654
9655         intel_mark_page_flip_active(intel_crtc);
9656         __intel_ring_advance(ring);
9657         return 0;
9658 }
9659
9660 static int intel_gen7_queue_flip(struct drm_device *dev,
9661                                  struct drm_crtc *crtc,
9662                                  struct drm_framebuffer *fb,
9663                                  struct drm_i915_gem_object *obj,
9664                                  struct intel_engine_cs *ring,
9665                                  uint32_t flags)
9666 {
9667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9668         uint32_t plane_bit = 0;
9669         int len, ret;
9670
9671         switch (intel_crtc->plane) {
9672         case PLANE_A:
9673                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9674                 break;
9675         case PLANE_B:
9676                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9677                 break;
9678         case PLANE_C:
9679                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9680                 break;
9681         default:
9682                 WARN_ONCE(1, "unknown plane in flip command\n");
9683                 return -ENODEV;
9684         }
9685
9686         len = 4;
9687         if (ring->id == RCS) {
9688                 len += 6;
9689                 /*
9690                  * On Gen 8, SRM is now taking an extra dword to accommodate
9691                  * 48bits addresses, and we need a NOOP for the batch size to
9692                  * stay even.
9693                  */
9694                 if (IS_GEN8(dev))
9695                         len += 2;
9696         }
9697
9698         /*
9699          * BSpec MI_DISPLAY_FLIP for IVB:
9700          * "The full packet must be contained within the same cache line."
9701          *
9702          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9703          * cacheline, if we ever start emitting more commands before
9704          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9705          * then do the cacheline alignment, and finally emit the
9706          * MI_DISPLAY_FLIP.
9707          */
9708         ret = intel_ring_cacheline_align(ring);
9709         if (ret)
9710                 return ret;
9711
9712         ret = intel_ring_begin(ring, len);
9713         if (ret)
9714                 return ret;
9715
9716         /* Unmask the flip-done completion message. Note that the bspec says that
9717          * we should do this for both the BCS and RCS, and that we must not unmask
9718          * more than one flip event at any time (or ensure that one flip message
9719          * can be sent by waiting for flip-done prior to queueing new flips).
9720          * Experimentation says that BCS works despite DERRMR masking all
9721          * flip-done completion events and that unmasking all planes at once
9722          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9723          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9724          */
9725         if (ring->id == RCS) {
9726                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9727                 intel_ring_emit(ring, DERRMR);
9728                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9729                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9730                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9731                 if (IS_GEN8(dev))
9732                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9733                                               MI_SRM_LRM_GLOBAL_GTT);
9734                 else
9735                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9736                                               MI_SRM_LRM_GLOBAL_GTT);
9737                 intel_ring_emit(ring, DERRMR);
9738                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9739                 if (IS_GEN8(dev)) {
9740                         intel_ring_emit(ring, 0);
9741                         intel_ring_emit(ring, MI_NOOP);
9742                 }
9743         }
9744
9745         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9746         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9747         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9748         intel_ring_emit(ring, (MI_NOOP));
9749
9750         intel_mark_page_flip_active(intel_crtc);
9751         __intel_ring_advance(ring);
9752         return 0;
9753 }
9754
9755 static bool use_mmio_flip(struct intel_engine_cs *ring,
9756                           struct drm_i915_gem_object *obj)
9757 {
9758         /*
9759          * This is not being used for older platforms, because
9760          * non-availability of flip done interrupt forces us to use
9761          * CS flips. Older platforms derive flip done using some clever
9762          * tricks involving the flip_pending status bits and vblank irqs.
9763          * So using MMIO flips there would disrupt this mechanism.
9764          */
9765
9766         if (ring == NULL)
9767                 return true;
9768
9769         if (INTEL_INFO(ring->dev)->gen < 5)
9770                 return false;
9771
9772         if (i915.use_mmio_flip < 0)
9773                 return false;
9774         else if (i915.use_mmio_flip > 0)
9775                 return true;
9776         else if (i915.enable_execlists)
9777                 return true;
9778         else
9779                 return ring != i915_gem_request_get_ring(obj->last_read_req);
9780 }
9781
9782 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9783 {
9784         struct drm_device *dev = intel_crtc->base.dev;
9785         struct drm_i915_private *dev_priv = dev->dev_private;
9786         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9787         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9788         struct drm_i915_gem_object *obj = intel_fb->obj;
9789         const enum pipe pipe = intel_crtc->pipe;
9790         u32 ctl, stride;
9791
9792         ctl = I915_READ(PLANE_CTL(pipe, 0));
9793         ctl &= ~PLANE_CTL_TILED_MASK;
9794         if (obj->tiling_mode == I915_TILING_X)
9795                 ctl |= PLANE_CTL_TILED_X;
9796
9797         /*
9798          * The stride is either expressed as a multiple of 64 bytes chunks for
9799          * linear buffers or in number of tiles for tiled buffers.
9800          */
9801         stride = fb->pitches[0] >> 6;
9802         if (obj->tiling_mode == I915_TILING_X)
9803                 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9804
9805         /*
9806          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9807          * PLANE_SURF updates, the update is then guaranteed to be atomic.
9808          */
9809         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9810         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9811
9812         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9813         POSTING_READ(PLANE_SURF(pipe, 0));
9814 }
9815
9816 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9817 {
9818         struct drm_device *dev = intel_crtc->base.dev;
9819         struct drm_i915_private *dev_priv = dev->dev_private;
9820         struct intel_framebuffer *intel_fb =
9821                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9822         struct drm_i915_gem_object *obj = intel_fb->obj;
9823         u32 dspcntr;
9824         u32 reg;
9825
9826         reg = DSPCNTR(intel_crtc->plane);
9827         dspcntr = I915_READ(reg);
9828
9829         if (obj->tiling_mode != I915_TILING_NONE)
9830                 dspcntr |= DISPPLANE_TILED;
9831         else
9832                 dspcntr &= ~DISPPLANE_TILED;
9833
9834         I915_WRITE(reg, dspcntr);
9835
9836         I915_WRITE(DSPSURF(intel_crtc->plane),
9837                    intel_crtc->unpin_work->gtt_offset);
9838         POSTING_READ(DSPSURF(intel_crtc->plane));
9839
9840 }
9841
9842 /*
9843  * XXX: This is the temporary way to update the plane registers until we get
9844  * around to using the usual plane update functions for MMIO flips
9845  */
9846 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9847 {
9848         struct drm_device *dev = intel_crtc->base.dev;
9849         bool atomic_update;
9850         u32 start_vbl_count;
9851
9852         intel_mark_page_flip_active(intel_crtc);
9853
9854         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9855
9856         if (INTEL_INFO(dev)->gen >= 9)
9857                 skl_do_mmio_flip(intel_crtc);
9858         else
9859                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9860                 ilk_do_mmio_flip(intel_crtc);
9861
9862         if (atomic_update)
9863                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9864 }
9865
9866 static void intel_mmio_flip_work_func(struct work_struct *work)
9867 {
9868         struct intel_crtc *crtc =
9869                 container_of(work, struct intel_crtc, mmio_flip.work);
9870         struct intel_mmio_flip *mmio_flip;
9871
9872         mmio_flip = &crtc->mmio_flip;
9873         if (mmio_flip->req)
9874                 WARN_ON(__i915_wait_request(mmio_flip->req,
9875                                             crtc->reset_counter,
9876                                             false, NULL, NULL) != 0);
9877
9878         intel_do_mmio_flip(crtc);
9879         if (mmio_flip->req) {
9880                 mutex_lock(&crtc->base.dev->struct_mutex);
9881                 i915_gem_request_assign(&mmio_flip->req, NULL);
9882                 mutex_unlock(&crtc->base.dev->struct_mutex);
9883         }
9884 }
9885
9886 static int intel_queue_mmio_flip(struct drm_device *dev,
9887                                  struct drm_crtc *crtc,
9888                                  struct drm_framebuffer *fb,
9889                                  struct drm_i915_gem_object *obj,
9890                                  struct intel_engine_cs *ring,
9891                                  uint32_t flags)
9892 {
9893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9894
9895         i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9896                                 obj->last_write_req);
9897
9898         schedule_work(&intel_crtc->mmio_flip.work);
9899
9900         return 0;
9901 }
9902
9903 static int intel_default_queue_flip(struct drm_device *dev,
9904                                     struct drm_crtc *crtc,
9905                                     struct drm_framebuffer *fb,
9906                                     struct drm_i915_gem_object *obj,
9907                                     struct intel_engine_cs *ring,
9908                                     uint32_t flags)
9909 {
9910         return -ENODEV;
9911 }
9912
9913 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9914                                          struct drm_crtc *crtc)
9915 {
9916         struct drm_i915_private *dev_priv = dev->dev_private;
9917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9918         struct intel_unpin_work *work = intel_crtc->unpin_work;
9919         u32 addr;
9920
9921         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9922                 return true;
9923
9924         if (!work->enable_stall_check)
9925                 return false;
9926
9927         if (work->flip_ready_vblank == 0) {
9928                 if (work->flip_queued_req &&
9929                     !i915_gem_request_completed(work->flip_queued_req, true))
9930                         return false;
9931
9932                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9933         }
9934
9935         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9936                 return false;
9937
9938         /* Potential stall - if we see that the flip has happened,
9939          * assume a missed interrupt. */
9940         if (INTEL_INFO(dev)->gen >= 4)
9941                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9942         else
9943                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9944
9945         /* There is a potential issue here with a false positive after a flip
9946          * to the same address. We could address this by checking for a
9947          * non-incrementing frame counter.
9948          */
9949         return addr == work->gtt_offset;
9950 }
9951
9952 void intel_check_page_flip(struct drm_device *dev, int pipe)
9953 {
9954         struct drm_i915_private *dev_priv = dev->dev_private;
9955         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9957
9958         WARN_ON(!in_interrupt());
9959
9960         if (crtc == NULL)
9961                 return;
9962
9963         spin_lock(&dev->event_lock);
9964         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9965                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9966                          intel_crtc->unpin_work->flip_queued_vblank,
9967                          drm_vblank_count(dev, pipe));
9968                 page_flip_completed(intel_crtc);
9969         }
9970         spin_unlock(&dev->event_lock);
9971 }
9972
9973 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9974                                 struct drm_framebuffer *fb,
9975                                 struct drm_pending_vblank_event *event,
9976                                 uint32_t page_flip_flags)
9977 {
9978         struct drm_device *dev = crtc->dev;
9979         struct drm_i915_private *dev_priv = dev->dev_private;
9980         struct drm_framebuffer *old_fb = crtc->primary->fb;
9981         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9983         struct drm_plane *primary = crtc->primary;
9984         enum pipe pipe = intel_crtc->pipe;
9985         struct intel_unpin_work *work;
9986         struct intel_engine_cs *ring;
9987         int ret;
9988
9989         /*
9990          * drm_mode_page_flip_ioctl() should already catch this, but double
9991          * check to be safe.  In the future we may enable pageflipping from
9992          * a disabled primary plane.
9993          */
9994         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9995                 return -EBUSY;
9996
9997         /* Can't change pixel format via MI display flips. */
9998         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9999                 return -EINVAL;
10000
10001         /*
10002          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10003          * Note that pitch changes could also affect these register.
10004          */
10005         if (INTEL_INFO(dev)->gen > 3 &&
10006             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10007              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10008                 return -EINVAL;
10009
10010         if (i915_terminally_wedged(&dev_priv->gpu_error))
10011                 goto out_hang;
10012
10013         work = kzalloc(sizeof(*work), GFP_KERNEL);
10014         if (work == NULL)
10015                 return -ENOMEM;
10016
10017         work->event = event;
10018         work->crtc = crtc;
10019         work->old_fb = old_fb;
10020         INIT_WORK(&work->work, intel_unpin_work_fn);
10021
10022         ret = drm_crtc_vblank_get(crtc);
10023         if (ret)
10024                 goto free_work;
10025
10026         /* We borrow the event spin lock for protecting unpin_work */
10027         spin_lock_irq(&dev->event_lock);
10028         if (intel_crtc->unpin_work) {
10029                 /* Before declaring the flip queue wedged, check if
10030                  * the hardware completed the operation behind our backs.
10031                  */
10032                 if (__intel_pageflip_stall_check(dev, crtc)) {
10033                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10034                         page_flip_completed(intel_crtc);
10035                 } else {
10036                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10037                         spin_unlock_irq(&dev->event_lock);
10038
10039                         drm_crtc_vblank_put(crtc);
10040                         kfree(work);
10041                         return -EBUSY;
10042                 }
10043         }
10044         intel_crtc->unpin_work = work;
10045         spin_unlock_irq(&dev->event_lock);
10046
10047         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10048                 flush_workqueue(dev_priv->wq);
10049
10050         /* Reference the objects for the scheduled work. */
10051         drm_framebuffer_reference(work->old_fb);
10052         drm_gem_object_reference(&obj->base);
10053
10054         crtc->primary->fb = fb;
10055         update_state_fb(crtc->primary);
10056
10057         work->pending_flip_obj = obj;
10058
10059         ret = i915_mutex_lock_interruptible(dev);
10060         if (ret)
10061                 goto cleanup;
10062
10063         atomic_inc(&intel_crtc->unpin_work_count);
10064         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10065
10066         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10067                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10068
10069         if (IS_VALLEYVIEW(dev)) {
10070                 ring = &dev_priv->ring[BCS];
10071                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10072                         /* vlv: DISPLAY_FLIP fails to change tiling */
10073                         ring = NULL;
10074         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10075                 ring = &dev_priv->ring[BCS];
10076         } else if (INTEL_INFO(dev)->gen >= 7) {
10077                 ring = i915_gem_request_get_ring(obj->last_read_req);
10078                 if (ring == NULL || ring->id != RCS)
10079                         ring = &dev_priv->ring[BCS];
10080         } else {
10081                 ring = &dev_priv->ring[RCS];
10082         }
10083
10084         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10085                                          crtc->primary->state, ring);
10086         if (ret)
10087                 goto cleanup_pending;
10088
10089         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10090                                                   + intel_crtc->dspaddr_offset;
10091
10092         if (use_mmio_flip(ring, obj)) {
10093                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10094                                             page_flip_flags);
10095                 if (ret)
10096                         goto cleanup_unpin;
10097
10098                 i915_gem_request_assign(&work->flip_queued_req,
10099                                         obj->last_write_req);
10100         } else {
10101                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10102                                                    page_flip_flags);
10103                 if (ret)
10104                         goto cleanup_unpin;
10105
10106                 i915_gem_request_assign(&work->flip_queued_req,
10107                                         intel_ring_get_request(ring));
10108         }
10109
10110         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10111         work->enable_stall_check = true;
10112
10113         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10114                           INTEL_FRONTBUFFER_PRIMARY(pipe));
10115
10116         intel_fbc_disable(dev);
10117         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10118         mutex_unlock(&dev->struct_mutex);
10119
10120         trace_i915_flip_request(intel_crtc->plane, obj);
10121
10122         return 0;
10123
10124 cleanup_unpin:
10125         intel_unpin_fb_obj(fb, crtc->primary->state);
10126 cleanup_pending:
10127         atomic_dec(&intel_crtc->unpin_work_count);
10128         mutex_unlock(&dev->struct_mutex);
10129 cleanup:
10130         crtc->primary->fb = old_fb;
10131         update_state_fb(crtc->primary);
10132
10133         drm_gem_object_unreference_unlocked(&obj->base);
10134         drm_framebuffer_unreference(work->old_fb);
10135
10136         spin_lock_irq(&dev->event_lock);
10137         intel_crtc->unpin_work = NULL;
10138         spin_unlock_irq(&dev->event_lock);
10139
10140         drm_crtc_vblank_put(crtc);
10141 free_work:
10142         kfree(work);
10143
10144         if (ret == -EIO) {
10145 out_hang:
10146                 ret = intel_plane_restore(primary);
10147                 if (ret == 0 && event) {
10148                         spin_lock_irq(&dev->event_lock);
10149                         drm_send_vblank_event(dev, pipe, event);
10150                         spin_unlock_irq(&dev->event_lock);
10151                 }
10152         }
10153         return ret;
10154 }
10155
10156 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10157         .mode_set_base_atomic = intel_pipe_set_base_atomic,
10158         .load_lut = intel_crtc_load_lut,
10159         .atomic_begin = intel_begin_crtc_commit,
10160         .atomic_flush = intel_finish_crtc_commit,
10161 };
10162
10163 /**
10164  * intel_modeset_update_staged_output_state
10165  *
10166  * Updates the staged output configuration state, e.g. after we've read out the
10167  * current hw state.
10168  */
10169 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10170 {
10171         struct intel_crtc *crtc;
10172         struct intel_encoder *encoder;
10173         struct intel_connector *connector;
10174
10175         for_each_intel_connector(dev, connector) {
10176                 connector->new_encoder =
10177                         to_intel_encoder(connector->base.encoder);
10178         }
10179
10180         for_each_intel_encoder(dev, encoder) {
10181                 encoder->new_crtc =
10182                         to_intel_crtc(encoder->base.crtc);
10183         }
10184
10185         for_each_intel_crtc(dev, crtc) {
10186                 crtc->new_enabled = crtc->base.state->enable;
10187
10188                 if (crtc->new_enabled)
10189                         crtc->new_config = crtc->config;
10190                 else
10191                         crtc->new_config = NULL;
10192         }
10193 }
10194
10195 /**
10196  * intel_modeset_commit_output_state
10197  *
10198  * This function copies the stage display pipe configuration to the real one.
10199  */
10200 static void intel_modeset_commit_output_state(struct drm_device *dev)
10201 {
10202         struct intel_crtc *crtc;
10203         struct intel_encoder *encoder;
10204         struct intel_connector *connector;
10205
10206         for_each_intel_connector(dev, connector) {
10207                 connector->base.encoder = &connector->new_encoder->base;
10208         }
10209
10210         for_each_intel_encoder(dev, encoder) {
10211                 encoder->base.crtc = &encoder->new_crtc->base;
10212         }
10213
10214         for_each_intel_crtc(dev, crtc) {
10215                 crtc->base.state->enable = crtc->new_enabled;
10216                 crtc->base.enabled = crtc->new_enabled;
10217         }
10218 }
10219
10220 static void
10221 connected_sink_compute_bpp(struct intel_connector *connector,
10222                            struct intel_crtc_state *pipe_config)
10223 {
10224         int bpp = pipe_config->pipe_bpp;
10225
10226         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10227                 connector->base.base.id,
10228                 connector->base.name);
10229
10230         /* Don't use an invalid EDID bpc value */
10231         if (connector->base.display_info.bpc &&
10232             connector->base.display_info.bpc * 3 < bpp) {
10233                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10234                               bpp, connector->base.display_info.bpc*3);
10235                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10236         }
10237
10238         /* Clamp bpp to 8 on screens without EDID 1.4 */
10239         if (connector->base.display_info.bpc == 0 && bpp > 24) {
10240                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10241                               bpp);
10242                 pipe_config->pipe_bpp = 24;
10243         }
10244 }
10245
10246 static int
10247 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10248                           struct drm_framebuffer *fb,
10249                           struct intel_crtc_state *pipe_config)
10250 {
10251         struct drm_device *dev = crtc->base.dev;
10252         struct intel_connector *connector;
10253         int bpp;
10254
10255         switch (fb->pixel_format) {
10256         case DRM_FORMAT_C8:
10257                 bpp = 8*3; /* since we go through a colormap */
10258                 break;
10259         case DRM_FORMAT_XRGB1555:
10260         case DRM_FORMAT_ARGB1555:
10261                 /* checked in intel_framebuffer_init already */
10262                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10263                         return -EINVAL;
10264         case DRM_FORMAT_RGB565:
10265                 bpp = 6*3; /* min is 18bpp */
10266                 break;
10267         case DRM_FORMAT_XBGR8888:
10268         case DRM_FORMAT_ABGR8888:
10269                 /* checked in intel_framebuffer_init already */
10270                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10271                         return -EINVAL;
10272         case DRM_FORMAT_XRGB8888:
10273         case DRM_FORMAT_ARGB8888:
10274                 bpp = 8*3;
10275                 break;
10276         case DRM_FORMAT_XRGB2101010:
10277         case DRM_FORMAT_ARGB2101010:
10278         case DRM_FORMAT_XBGR2101010:
10279         case DRM_FORMAT_ABGR2101010:
10280                 /* checked in intel_framebuffer_init already */
10281                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10282                         return -EINVAL;
10283                 bpp = 10*3;
10284                 break;
10285         /* TODO: gen4+ supports 16 bpc floating point, too. */
10286         default:
10287                 DRM_DEBUG_KMS("unsupported depth\n");
10288                 return -EINVAL;
10289         }
10290
10291         pipe_config->pipe_bpp = bpp;
10292
10293         /* Clamp display bpp to EDID value */
10294         for_each_intel_connector(dev, connector) {
10295                 if (!connector->new_encoder ||
10296                     connector->new_encoder->new_crtc != crtc)
10297                         continue;
10298
10299                 connected_sink_compute_bpp(connector, pipe_config);
10300         }
10301
10302         return bpp;
10303 }
10304
10305 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10306 {
10307         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10308                         "type: 0x%x flags: 0x%x\n",
10309                 mode->crtc_clock,
10310                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10311                 mode->crtc_hsync_end, mode->crtc_htotal,
10312                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10313                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10314 }
10315
10316 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10317                                    struct intel_crtc_state *pipe_config,
10318                                    const char *context)
10319 {
10320         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10321                       context, pipe_name(crtc->pipe));
10322
10323         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10324         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10325                       pipe_config->pipe_bpp, pipe_config->dither);
10326         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10327                       pipe_config->has_pch_encoder,
10328                       pipe_config->fdi_lanes,
10329                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10330                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10331                       pipe_config->fdi_m_n.tu);
10332         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10333                       pipe_config->has_dp_encoder,
10334                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10335                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10336                       pipe_config->dp_m_n.tu);
10337
10338         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10339                       pipe_config->has_dp_encoder,
10340                       pipe_config->dp_m2_n2.gmch_m,
10341                       pipe_config->dp_m2_n2.gmch_n,
10342                       pipe_config->dp_m2_n2.link_m,
10343                       pipe_config->dp_m2_n2.link_n,
10344                       pipe_config->dp_m2_n2.tu);
10345
10346         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10347                       pipe_config->has_audio,
10348                       pipe_config->has_infoframe);
10349
10350         DRM_DEBUG_KMS("requested mode:\n");
10351         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10352         DRM_DEBUG_KMS("adjusted mode:\n");
10353         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10354         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10355         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10356         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10357                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10358         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10359                       pipe_config->gmch_pfit.control,
10360                       pipe_config->gmch_pfit.pgm_ratios,
10361                       pipe_config->gmch_pfit.lvds_border_bits);
10362         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10363                       pipe_config->pch_pfit.pos,
10364                       pipe_config->pch_pfit.size,
10365                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10366         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10367         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10368 }
10369
10370 static bool encoders_cloneable(const struct intel_encoder *a,
10371                                const struct intel_encoder *b)
10372 {
10373         /* masks could be asymmetric, so check both ways */
10374         return a == b || (a->cloneable & (1 << b->type) &&
10375                           b->cloneable & (1 << a->type));
10376 }
10377
10378 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10379                                          struct intel_encoder *encoder)
10380 {
10381         struct drm_device *dev = crtc->base.dev;
10382         struct intel_encoder *source_encoder;
10383
10384         for_each_intel_encoder(dev, source_encoder) {
10385                 if (source_encoder->new_crtc != crtc)
10386                         continue;
10387
10388                 if (!encoders_cloneable(encoder, source_encoder))
10389                         return false;
10390         }
10391
10392         return true;
10393 }
10394
10395 static bool check_encoder_cloning(struct intel_crtc *crtc)
10396 {
10397         struct drm_device *dev = crtc->base.dev;
10398         struct intel_encoder *encoder;
10399
10400         for_each_intel_encoder(dev, encoder) {
10401                 if (encoder->new_crtc != crtc)
10402                         continue;
10403
10404                 if (!check_single_encoder_cloning(crtc, encoder))
10405                         return false;
10406         }
10407
10408         return true;
10409 }
10410
10411 static bool check_digital_port_conflicts(struct drm_device *dev)
10412 {
10413         struct intel_connector *connector;
10414         unsigned int used_ports = 0;
10415
10416         /*
10417          * Walk the connector list instead of the encoder
10418          * list to detect the problem on ddi platforms
10419          * where there's just one encoder per digital port.
10420          */
10421         for_each_intel_connector(dev, connector) {
10422                 struct intel_encoder *encoder = connector->new_encoder;
10423
10424                 if (!encoder)
10425                         continue;
10426
10427                 WARN_ON(!encoder->new_crtc);
10428
10429                 switch (encoder->type) {
10430                         unsigned int port_mask;
10431                 case INTEL_OUTPUT_UNKNOWN:
10432                         if (WARN_ON(!HAS_DDI(dev)))
10433                                 break;
10434                 case INTEL_OUTPUT_DISPLAYPORT:
10435                 case INTEL_OUTPUT_HDMI:
10436                 case INTEL_OUTPUT_EDP:
10437                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10438
10439                         /* the same port mustn't appear more than once */
10440                         if (used_ports & port_mask)
10441                                 return false;
10442
10443                         used_ports |= port_mask;
10444                 default:
10445                         break;
10446                 }
10447         }
10448
10449         return true;
10450 }
10451
10452 static struct intel_crtc_state *
10453 intel_modeset_pipe_config(struct drm_crtc *crtc,
10454                           struct drm_framebuffer *fb,
10455                           struct drm_display_mode *mode)
10456 {
10457         struct drm_device *dev = crtc->dev;
10458         struct intel_encoder *encoder;
10459         struct intel_crtc_state *pipe_config;
10460         int plane_bpp, ret = -EINVAL;
10461         bool retry = true;
10462
10463         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10464                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10465                 return ERR_PTR(-EINVAL);
10466         }
10467
10468         if (!check_digital_port_conflicts(dev)) {
10469                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10470                 return ERR_PTR(-EINVAL);
10471         }
10472
10473         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10474         if (!pipe_config)
10475                 return ERR_PTR(-ENOMEM);
10476
10477         pipe_config->base.crtc = crtc;
10478         drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10479         drm_mode_copy(&pipe_config->base.mode, mode);
10480
10481         pipe_config->cpu_transcoder =
10482                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10483         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10484
10485         /*
10486          * Sanitize sync polarity flags based on requested ones. If neither
10487          * positive or negative polarity is requested, treat this as meaning
10488          * negative polarity.
10489          */
10490         if (!(pipe_config->base.adjusted_mode.flags &
10491               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10492                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10493
10494         if (!(pipe_config->base.adjusted_mode.flags &
10495               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10496                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10497
10498         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10499          * plane pixel format and any sink constraints into account. Returns the
10500          * source plane bpp so that dithering can be selected on mismatches
10501          * after encoders and crtc also have had their say. */
10502         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10503                                               fb, pipe_config);
10504         if (plane_bpp < 0)
10505                 goto fail;
10506
10507         /*
10508          * Determine the real pipe dimensions. Note that stereo modes can
10509          * increase the actual pipe size due to the frame doubling and
10510          * insertion of additional space for blanks between the frame. This
10511          * is stored in the crtc timings. We use the requested mode to do this
10512          * computation to clearly distinguish it from the adjusted mode, which
10513          * can be changed by the connectors in the below retry loop.
10514          */
10515         drm_crtc_get_hv_timing(&pipe_config->base.mode,
10516                                &pipe_config->pipe_src_w,
10517                                &pipe_config->pipe_src_h);
10518
10519 encoder_retry:
10520         /* Ensure the port clock defaults are reset when retrying. */
10521         pipe_config->port_clock = 0;
10522         pipe_config->pixel_multiplier = 1;
10523
10524         /* Fill in default crtc timings, allow encoders to overwrite them. */
10525         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10526                               CRTC_STEREO_DOUBLE);
10527
10528         /* Pass our mode to the connectors and the CRTC to give them a chance to
10529          * adjust it according to limitations or connector properties, and also
10530          * a chance to reject the mode entirely.
10531          */
10532         for_each_intel_encoder(dev, encoder) {
10533
10534                 if (&encoder->new_crtc->base != crtc)
10535                         continue;
10536
10537                 if (!(encoder->compute_config(encoder, pipe_config))) {
10538                         DRM_DEBUG_KMS("Encoder config failure\n");
10539                         goto fail;
10540                 }
10541         }
10542
10543         /* Set default port clock if not overwritten by the encoder. Needs to be
10544          * done afterwards in case the encoder adjusts the mode. */
10545         if (!pipe_config->port_clock)
10546                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10547                         * pipe_config->pixel_multiplier;
10548
10549         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10550         if (ret < 0) {
10551                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10552                 goto fail;
10553         }
10554
10555         if (ret == RETRY) {
10556                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10557                         ret = -EINVAL;
10558                         goto fail;
10559                 }
10560
10561                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10562                 retry = false;
10563                 goto encoder_retry;
10564         }
10565
10566         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10567         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10568                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10569
10570         return pipe_config;
10571 fail:
10572         kfree(pipe_config);
10573         return ERR_PTR(ret);
10574 }
10575
10576 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10577  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10578 static void
10579 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10580                              unsigned *prepare_pipes, unsigned *disable_pipes)
10581 {
10582         struct intel_crtc *intel_crtc;
10583         struct drm_device *dev = crtc->dev;
10584         struct intel_encoder *encoder;
10585         struct intel_connector *connector;
10586         struct drm_crtc *tmp_crtc;
10587
10588         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10589
10590         /* Check which crtcs have changed outputs connected to them, these need
10591          * to be part of the prepare_pipes mask. We don't (yet) support global
10592          * modeset across multiple crtcs, so modeset_pipes will only have one
10593          * bit set at most. */
10594         for_each_intel_connector(dev, connector) {
10595                 if (connector->base.encoder == &connector->new_encoder->base)
10596                         continue;
10597
10598                 if (connector->base.encoder) {
10599                         tmp_crtc = connector->base.encoder->crtc;
10600
10601                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10602                 }
10603
10604                 if (connector->new_encoder)
10605                         *prepare_pipes |=
10606                                 1 << connector->new_encoder->new_crtc->pipe;
10607         }
10608
10609         for_each_intel_encoder(dev, encoder) {
10610                 if (encoder->base.crtc == &encoder->new_crtc->base)
10611                         continue;
10612
10613                 if (encoder->base.crtc) {
10614                         tmp_crtc = encoder->base.crtc;
10615
10616                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10617                 }
10618
10619                 if (encoder->new_crtc)
10620                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10621         }
10622
10623         /* Check for pipes that will be enabled/disabled ... */
10624         for_each_intel_crtc(dev, intel_crtc) {
10625                 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10626                         continue;
10627
10628                 if (!intel_crtc->new_enabled)
10629                         *disable_pipes |= 1 << intel_crtc->pipe;
10630                 else
10631                         *prepare_pipes |= 1 << intel_crtc->pipe;
10632         }
10633
10634
10635         /* set_mode is also used to update properties on life display pipes. */
10636         intel_crtc = to_intel_crtc(crtc);
10637         if (intel_crtc->new_enabled)
10638                 *prepare_pipes |= 1 << intel_crtc->pipe;
10639
10640         /*
10641          * For simplicity do a full modeset on any pipe where the output routing
10642          * changed. We could be more clever, but that would require us to be
10643          * more careful with calling the relevant encoder->mode_set functions.
10644          */
10645         if (*prepare_pipes)
10646                 *modeset_pipes = *prepare_pipes;
10647
10648         /* ... and mask these out. */
10649         *modeset_pipes &= ~(*disable_pipes);
10650         *prepare_pipes &= ~(*disable_pipes);
10651
10652         /*
10653          * HACK: We don't (yet) fully support global modesets. intel_set_config
10654          * obies this rule, but the modeset restore mode of
10655          * intel_modeset_setup_hw_state does not.
10656          */
10657         *modeset_pipes &= 1 << intel_crtc->pipe;
10658         *prepare_pipes &= 1 << intel_crtc->pipe;
10659
10660         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10661                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10662 }
10663
10664 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10665 {
10666         struct drm_encoder *encoder;
10667         struct drm_device *dev = crtc->dev;
10668
10669         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10670                 if (encoder->crtc == crtc)
10671                         return true;
10672
10673         return false;
10674 }
10675
10676 static void
10677 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10678 {
10679         struct drm_i915_private *dev_priv = dev->dev_private;
10680         struct intel_encoder *intel_encoder;
10681         struct intel_crtc *intel_crtc;
10682         struct drm_connector *connector;
10683
10684         intel_shared_dpll_commit(dev_priv);
10685
10686         for_each_intel_encoder(dev, intel_encoder) {
10687                 if (!intel_encoder->base.crtc)
10688                         continue;
10689
10690                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10691
10692                 if (prepare_pipes & (1 << intel_crtc->pipe))
10693                         intel_encoder->connectors_active = false;
10694         }
10695
10696         intel_modeset_commit_output_state(dev);
10697
10698         /* Double check state. */
10699         for_each_intel_crtc(dev, intel_crtc) {
10700                 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10701                 WARN_ON(intel_crtc->new_config &&
10702                         intel_crtc->new_config != intel_crtc->config);
10703                 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10704         }
10705
10706         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10707                 if (!connector->encoder || !connector->encoder->crtc)
10708                         continue;
10709
10710                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10711
10712                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10713                         struct drm_property *dpms_property =
10714                                 dev->mode_config.dpms_property;
10715
10716                         connector->dpms = DRM_MODE_DPMS_ON;
10717                         drm_object_property_set_value(&connector->base,
10718                                                          dpms_property,
10719                                                          DRM_MODE_DPMS_ON);
10720
10721                         intel_encoder = to_intel_encoder(connector->encoder);
10722                         intel_encoder->connectors_active = true;
10723                 }
10724         }
10725
10726 }
10727
10728 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10729 {
10730         int diff;
10731
10732         if (clock1 == clock2)
10733                 return true;
10734
10735         if (!clock1 || !clock2)
10736                 return false;
10737
10738         diff = abs(clock1 - clock2);
10739
10740         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10741                 return true;
10742
10743         return false;
10744 }
10745
10746 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10747         list_for_each_entry((intel_crtc), \
10748                             &(dev)->mode_config.crtc_list, \
10749                             base.head) \
10750                 if (mask & (1 <<(intel_crtc)->pipe))
10751
10752 static bool
10753 intel_pipe_config_compare(struct drm_device *dev,
10754                           struct intel_crtc_state *current_config,
10755                           struct intel_crtc_state *pipe_config)
10756 {
10757 #define PIPE_CONF_CHECK_X(name) \
10758         if (current_config->name != pipe_config->name) { \
10759                 DRM_ERROR("mismatch in " #name " " \
10760                           "(expected 0x%08x, found 0x%08x)\n", \
10761                           current_config->name, \
10762                           pipe_config->name); \
10763                 return false; \
10764         }
10765
10766 #define PIPE_CONF_CHECK_I(name) \
10767         if (current_config->name != pipe_config->name) { \
10768                 DRM_ERROR("mismatch in " #name " " \
10769                           "(expected %i, found %i)\n", \
10770                           current_config->name, \
10771                           pipe_config->name); \
10772                 return false; \
10773         }
10774
10775 /* This is required for BDW+ where there is only one set of registers for
10776  * switching between high and low RR.
10777  * This macro can be used whenever a comparison has to be made between one
10778  * hw state and multiple sw state variables.
10779  */
10780 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10781         if ((current_config->name != pipe_config->name) && \
10782                 (current_config->alt_name != pipe_config->name)) { \
10783                         DRM_ERROR("mismatch in " #name " " \
10784                                   "(expected %i or %i, found %i)\n", \
10785                                   current_config->name, \
10786                                   current_config->alt_name, \
10787                                   pipe_config->name); \
10788                         return false; \
10789         }
10790
10791 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10792         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10793                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10794                           "(expected %i, found %i)\n", \
10795                           current_config->name & (mask), \
10796                           pipe_config->name & (mask)); \
10797                 return false; \
10798         }
10799
10800 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10801         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10802                 DRM_ERROR("mismatch in " #name " " \
10803                           "(expected %i, found %i)\n", \
10804                           current_config->name, \
10805                           pipe_config->name); \
10806                 return false; \
10807         }
10808
10809 #define PIPE_CONF_QUIRK(quirk)  \
10810         ((current_config->quirks | pipe_config->quirks) & (quirk))
10811
10812         PIPE_CONF_CHECK_I(cpu_transcoder);
10813
10814         PIPE_CONF_CHECK_I(has_pch_encoder);
10815         PIPE_CONF_CHECK_I(fdi_lanes);
10816         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10817         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10818         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10819         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10820         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10821
10822         PIPE_CONF_CHECK_I(has_dp_encoder);
10823
10824         if (INTEL_INFO(dev)->gen < 8) {
10825                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10826                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10827                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10828                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10829                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10830
10831                 if (current_config->has_drrs) {
10832                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10833                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10834                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10835                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10836                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10837                 }
10838         } else {
10839                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10840                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10841                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10842                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10843                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10844         }
10845
10846         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10847         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10848         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10849         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10850         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10851         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10852
10853         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10854         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10855         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10856         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10857         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10858         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10859
10860         PIPE_CONF_CHECK_I(pixel_multiplier);
10861         PIPE_CONF_CHECK_I(has_hdmi_sink);
10862         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10863             IS_VALLEYVIEW(dev))
10864                 PIPE_CONF_CHECK_I(limited_color_range);
10865         PIPE_CONF_CHECK_I(has_infoframe);
10866
10867         PIPE_CONF_CHECK_I(has_audio);
10868
10869         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10870                               DRM_MODE_FLAG_INTERLACE);
10871
10872         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10873                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10874                                       DRM_MODE_FLAG_PHSYNC);
10875                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10876                                       DRM_MODE_FLAG_NHSYNC);
10877                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10878                                       DRM_MODE_FLAG_PVSYNC);
10879                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10880                                       DRM_MODE_FLAG_NVSYNC);
10881         }
10882
10883         PIPE_CONF_CHECK_I(pipe_src_w);
10884         PIPE_CONF_CHECK_I(pipe_src_h);
10885
10886         /*
10887          * FIXME: BIOS likes to set up a cloned config with lvds+external
10888          * screen. Since we don't yet re-compute the pipe config when moving
10889          * just the lvds port away to another pipe the sw tracking won't match.
10890          *
10891          * Proper atomic modesets with recomputed global state will fix this.
10892          * Until then just don't check gmch state for inherited modes.
10893          */
10894         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10895                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10896                 /* pfit ratios are autocomputed by the hw on gen4+ */
10897                 if (INTEL_INFO(dev)->gen < 4)
10898                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10899                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10900         }
10901
10902         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10903         if (current_config->pch_pfit.enabled) {
10904                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10905                 PIPE_CONF_CHECK_I(pch_pfit.size);
10906         }
10907
10908         /* BDW+ don't expose a synchronous way to read the state */
10909         if (IS_HASWELL(dev))
10910                 PIPE_CONF_CHECK_I(ips_enabled);
10911
10912         PIPE_CONF_CHECK_I(double_wide);
10913
10914         PIPE_CONF_CHECK_X(ddi_pll_sel);
10915
10916         PIPE_CONF_CHECK_I(shared_dpll);
10917         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10918         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10919         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10920         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10921         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10922         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10923         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10924         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10925
10926         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10927                 PIPE_CONF_CHECK_I(pipe_bpp);
10928
10929         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10930         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10931
10932 #undef PIPE_CONF_CHECK_X
10933 #undef PIPE_CONF_CHECK_I
10934 #undef PIPE_CONF_CHECK_I_ALT
10935 #undef PIPE_CONF_CHECK_FLAGS
10936 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10937 #undef PIPE_CONF_QUIRK
10938
10939         return true;
10940 }
10941
10942 static void check_wm_state(struct drm_device *dev)
10943 {
10944         struct drm_i915_private *dev_priv = dev->dev_private;
10945         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10946         struct intel_crtc *intel_crtc;
10947         int plane;
10948
10949         if (INTEL_INFO(dev)->gen < 9)
10950                 return;
10951
10952         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10953         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10954
10955         for_each_intel_crtc(dev, intel_crtc) {
10956                 struct skl_ddb_entry *hw_entry, *sw_entry;
10957                 const enum pipe pipe = intel_crtc->pipe;
10958
10959                 if (!intel_crtc->active)
10960                         continue;
10961
10962                 /* planes */
10963                 for_each_plane(dev_priv, pipe, plane) {
10964                         hw_entry = &hw_ddb.plane[pipe][plane];
10965                         sw_entry = &sw_ddb->plane[pipe][plane];
10966
10967                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10968                                 continue;
10969
10970                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10971                                   "(expected (%u,%u), found (%u,%u))\n",
10972                                   pipe_name(pipe), plane + 1,
10973                                   sw_entry->start, sw_entry->end,
10974                                   hw_entry->start, hw_entry->end);
10975                 }
10976
10977                 /* cursor */
10978                 hw_entry = &hw_ddb.cursor[pipe];
10979                 sw_entry = &sw_ddb->cursor[pipe];
10980
10981                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10982                         continue;
10983
10984                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10985                           "(expected (%u,%u), found (%u,%u))\n",
10986                           pipe_name(pipe),
10987                           sw_entry->start, sw_entry->end,
10988                           hw_entry->start, hw_entry->end);
10989         }
10990 }
10991
10992 static void
10993 check_connector_state(struct drm_device *dev)
10994 {
10995         struct intel_connector *connector;
10996
10997         for_each_intel_connector(dev, connector) {
10998                 /* This also checks the encoder/connector hw state with the
10999                  * ->get_hw_state callbacks. */
11000                 intel_connector_check_state(connector);
11001
11002                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11003                      "connector's staged encoder doesn't match current encoder\n");
11004         }
11005 }
11006
11007 static void
11008 check_encoder_state(struct drm_device *dev)
11009 {
11010         struct intel_encoder *encoder;
11011         struct intel_connector *connector;
11012
11013         for_each_intel_encoder(dev, encoder) {
11014                 bool enabled = false;
11015                 bool active = false;
11016                 enum pipe pipe, tracked_pipe;
11017
11018                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11019                               encoder->base.base.id,
11020                               encoder->base.name);
11021
11022                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11023                      "encoder's stage crtc doesn't match current crtc\n");
11024                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11025                      "encoder's active_connectors set, but no crtc\n");
11026
11027                 for_each_intel_connector(dev, connector) {
11028                         if (connector->base.encoder != &encoder->base)
11029                                 continue;
11030                         enabled = true;
11031                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11032                                 active = true;
11033                 }
11034                 /*
11035                  * for MST connectors if we unplug the connector is gone
11036                  * away but the encoder is still connected to a crtc
11037                  * until a modeset happens in response to the hotplug.
11038                  */
11039                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11040                         continue;
11041
11042                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11043                      "encoder's enabled state mismatch "
11044                      "(expected %i, found %i)\n",
11045                      !!encoder->base.crtc, enabled);
11046                 I915_STATE_WARN(active && !encoder->base.crtc,
11047                      "active encoder with no crtc\n");
11048
11049                 I915_STATE_WARN(encoder->connectors_active != active,
11050                      "encoder's computed active state doesn't match tracked active state "
11051                      "(expected %i, found %i)\n", active, encoder->connectors_active);
11052
11053                 active = encoder->get_hw_state(encoder, &pipe);
11054                 I915_STATE_WARN(active != encoder->connectors_active,
11055                      "encoder's hw state doesn't match sw tracking "
11056                      "(expected %i, found %i)\n",
11057                      encoder->connectors_active, active);
11058
11059                 if (!encoder->base.crtc)
11060                         continue;
11061
11062                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11063                 I915_STATE_WARN(active && pipe != tracked_pipe,
11064                      "active encoder's pipe doesn't match"
11065                      "(expected %i, found %i)\n",
11066                      tracked_pipe, pipe);
11067
11068         }
11069 }
11070
11071 static void
11072 check_crtc_state(struct drm_device *dev)
11073 {
11074         struct drm_i915_private *dev_priv = dev->dev_private;
11075         struct intel_crtc *crtc;
11076         struct intel_encoder *encoder;
11077         struct intel_crtc_state pipe_config;
11078
11079         for_each_intel_crtc(dev, crtc) {
11080                 bool enabled = false;
11081                 bool active = false;
11082
11083                 memset(&pipe_config, 0, sizeof(pipe_config));
11084
11085                 DRM_DEBUG_KMS("[CRTC:%d]\n",
11086                               crtc->base.base.id);
11087
11088                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11089                      "active crtc, but not enabled in sw tracking\n");
11090
11091                 for_each_intel_encoder(dev, encoder) {
11092                         if (encoder->base.crtc != &crtc->base)
11093                                 continue;
11094                         enabled = true;
11095                         if (encoder->connectors_active)
11096                                 active = true;
11097                 }
11098
11099                 I915_STATE_WARN(active != crtc->active,
11100                      "crtc's computed active state doesn't match tracked active state "
11101                      "(expected %i, found %i)\n", active, crtc->active);
11102                 I915_STATE_WARN(enabled != crtc->base.state->enable,
11103                      "crtc's computed enabled state doesn't match tracked enabled state "
11104                      "(expected %i, found %i)\n", enabled,
11105                                 crtc->base.state->enable);
11106
11107                 active = dev_priv->display.get_pipe_config(crtc,
11108                                                            &pipe_config);
11109
11110                 /* hw state is inconsistent with the pipe quirk */
11111                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11112                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11113                         active = crtc->active;
11114
11115                 for_each_intel_encoder(dev, encoder) {
11116                         enum pipe pipe;
11117                         if (encoder->base.crtc != &crtc->base)
11118                                 continue;
11119                         if (encoder->get_hw_state(encoder, &pipe))
11120                                 encoder->get_config(encoder, &pipe_config);
11121                 }
11122
11123                 I915_STATE_WARN(crtc->active != active,
11124                      "crtc active state doesn't match with hw state "
11125                      "(expected %i, found %i)\n", crtc->active, active);
11126
11127                 if (active &&
11128                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11129                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
11130                         intel_dump_pipe_config(crtc, &pipe_config,
11131                                                "[hw state]");
11132                         intel_dump_pipe_config(crtc, crtc->config,
11133                                                "[sw state]");
11134                 }
11135         }
11136 }
11137
11138 static void
11139 check_shared_dpll_state(struct drm_device *dev)
11140 {
11141         struct drm_i915_private *dev_priv = dev->dev_private;
11142         struct intel_crtc *crtc;
11143         struct intel_dpll_hw_state dpll_hw_state;
11144         int i;
11145
11146         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11147                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11148                 int enabled_crtcs = 0, active_crtcs = 0;
11149                 bool active;
11150
11151                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11152
11153                 DRM_DEBUG_KMS("%s\n", pll->name);
11154
11155                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11156
11157                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11158                      "more active pll users than references: %i vs %i\n",
11159                      pll->active, hweight32(pll->config.crtc_mask));
11160                 I915_STATE_WARN(pll->active && !pll->on,
11161                      "pll in active use but not on in sw tracking\n");
11162                 I915_STATE_WARN(pll->on && !pll->active,
11163                      "pll in on but not on in use in sw tracking\n");
11164                 I915_STATE_WARN(pll->on != active,
11165                      "pll on state mismatch (expected %i, found %i)\n",
11166                      pll->on, active);
11167
11168                 for_each_intel_crtc(dev, crtc) {
11169                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11170                                 enabled_crtcs++;
11171                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11172                                 active_crtcs++;
11173                 }
11174                 I915_STATE_WARN(pll->active != active_crtcs,
11175                      "pll active crtcs mismatch (expected %i, found %i)\n",
11176                      pll->active, active_crtcs);
11177                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11178                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
11179                      hweight32(pll->config.crtc_mask), enabled_crtcs);
11180
11181                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11182                                        sizeof(dpll_hw_state)),
11183                      "pll hw state mismatch\n");
11184         }
11185 }
11186
11187 void
11188 intel_modeset_check_state(struct drm_device *dev)
11189 {
11190         check_wm_state(dev);
11191         check_connector_state(dev);
11192         check_encoder_state(dev);
11193         check_crtc_state(dev);
11194         check_shared_dpll_state(dev);
11195 }
11196
11197 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11198                                      int dotclock)
11199 {
11200         /*
11201          * FDI already provided one idea for the dotclock.
11202          * Yell if the encoder disagrees.
11203          */
11204         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11205              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11206              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11207 }
11208
11209 static void update_scanline_offset(struct intel_crtc *crtc)
11210 {
11211         struct drm_device *dev = crtc->base.dev;
11212
11213         /*
11214          * The scanline counter increments at the leading edge of hsync.
11215          *
11216          * On most platforms it starts counting from vtotal-1 on the
11217          * first active line. That means the scanline counter value is
11218          * always one less than what we would expect. Ie. just after
11219          * start of vblank, which also occurs at start of hsync (on the
11220          * last active line), the scanline counter will read vblank_start-1.
11221          *
11222          * On gen2 the scanline counter starts counting from 1 instead
11223          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11224          * to keep the value positive), instead of adding one.
11225          *
11226          * On HSW+ the behaviour of the scanline counter depends on the output
11227          * type. For DP ports it behaves like most other platforms, but on HDMI
11228          * there's an extra 1 line difference. So we need to add two instead of
11229          * one to the value.
11230          */
11231         if (IS_GEN2(dev)) {
11232                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11233                 int vtotal;
11234
11235                 vtotal = mode->crtc_vtotal;
11236                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11237                         vtotal /= 2;
11238
11239                 crtc->scanline_offset = vtotal - 1;
11240         } else if (HAS_DDI(dev) &&
11241                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11242                 crtc->scanline_offset = 2;
11243         } else
11244                 crtc->scanline_offset = 1;
11245 }
11246
11247 static struct intel_crtc_state *
11248 intel_modeset_compute_config(struct drm_crtc *crtc,
11249                              struct drm_display_mode *mode,
11250                              struct drm_framebuffer *fb,
11251                              unsigned *modeset_pipes,
11252                              unsigned *prepare_pipes,
11253                              unsigned *disable_pipes)
11254 {
11255         struct intel_crtc_state *pipe_config = NULL;
11256
11257         intel_modeset_affected_pipes(crtc, modeset_pipes,
11258                                      prepare_pipes, disable_pipes);
11259
11260         if ((*modeset_pipes) == 0)
11261                 goto out;
11262
11263         /*
11264          * Note this needs changes when we start tracking multiple modes
11265          * and crtcs.  At that point we'll need to compute the whole config
11266          * (i.e. one pipe_config for each crtc) rather than just the one
11267          * for this crtc.
11268          */
11269         pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11270         if (IS_ERR(pipe_config)) {
11271                 goto out;
11272         }
11273         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11274                                "[modeset]");
11275
11276 out:
11277         return pipe_config;
11278 }
11279
11280 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11281                                        unsigned modeset_pipes,
11282                                        unsigned disable_pipes)
11283 {
11284         struct drm_i915_private *dev_priv = to_i915(dev);
11285         unsigned clear_pipes = modeset_pipes | disable_pipes;
11286         struct intel_crtc *intel_crtc;
11287         int ret = 0;
11288
11289         if (!dev_priv->display.crtc_compute_clock)
11290                 return 0;
11291
11292         ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11293         if (ret)
11294                 goto done;
11295
11296         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11297                 struct intel_crtc_state *state = intel_crtc->new_config;
11298                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11299                                                            state);
11300                 if (ret) {
11301                         intel_shared_dpll_abort_config(dev_priv);
11302                         goto done;
11303                 }
11304         }
11305
11306 done:
11307         return ret;
11308 }
11309
11310 static int __intel_set_mode(struct drm_crtc *crtc,
11311                             struct drm_display_mode *mode,
11312                             int x, int y, struct drm_framebuffer *fb,
11313                             struct intel_crtc_state *pipe_config,
11314                             unsigned modeset_pipes,
11315                             unsigned prepare_pipes,
11316                             unsigned disable_pipes)
11317 {
11318         struct drm_device *dev = crtc->dev;
11319         struct drm_i915_private *dev_priv = dev->dev_private;
11320         struct drm_display_mode *saved_mode;
11321         struct intel_crtc *intel_crtc;
11322         int ret = 0;
11323
11324         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11325         if (!saved_mode)
11326                 return -ENOMEM;
11327
11328         *saved_mode = crtc->mode;
11329
11330         if (modeset_pipes)
11331                 to_intel_crtc(crtc)->new_config = pipe_config;
11332
11333         /*
11334          * See if the config requires any additional preparation, e.g.
11335          * to adjust global state with pipes off.  We need to do this
11336          * here so we can get the modeset_pipe updated config for the new
11337          * mode set on this crtc.  For other crtcs we need to use the
11338          * adjusted_mode bits in the crtc directly.
11339          */
11340         if (IS_VALLEYVIEW(dev)) {
11341                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11342
11343                 /* may have added more to prepare_pipes than we should */
11344                 prepare_pipes &= ~disable_pipes;
11345         }
11346
11347         ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11348         if (ret)
11349                 goto done;
11350
11351         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11352                 intel_crtc_disable(&intel_crtc->base);
11353
11354         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11355                 if (intel_crtc->base.state->enable)
11356                         dev_priv->display.crtc_disable(&intel_crtc->base);
11357         }
11358
11359         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11360          * to set it here already despite that we pass it down the callchain.
11361          *
11362          * Note we'll need to fix this up when we start tracking multiple
11363          * pipes; here we assume a single modeset_pipe and only track the
11364          * single crtc and mode.
11365          */
11366         if (modeset_pipes) {
11367                 crtc->mode = *mode;
11368                 /* mode_set/enable/disable functions rely on a correct pipe
11369                  * config. */
11370                 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11371
11372                 /*
11373                  * Calculate and store various constants which
11374                  * are later needed by vblank and swap-completion
11375                  * timestamping. They are derived from true hwmode.
11376                  */
11377                 drm_calc_timestamping_constants(crtc,
11378                                                 &pipe_config->base.adjusted_mode);
11379         }
11380
11381         /* Only after disabling all output pipelines that will be changed can we
11382          * update the the output configuration. */
11383         intel_modeset_update_state(dev, prepare_pipes);
11384
11385         modeset_update_crtc_power_domains(dev);
11386
11387         /* Set up the DPLL and any encoders state that needs to adjust or depend
11388          * on the DPLL.
11389          */
11390         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11391                 struct drm_plane *primary = intel_crtc->base.primary;
11392                 int vdisplay, hdisplay;
11393
11394                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11395                 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11396                                                    fb, 0, 0,
11397                                                    hdisplay, vdisplay,
11398                                                    x << 16, y << 16,
11399                                                    hdisplay << 16, vdisplay << 16);
11400         }
11401
11402         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11403         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11404                 update_scanline_offset(intel_crtc);
11405
11406                 dev_priv->display.crtc_enable(&intel_crtc->base);
11407         }
11408
11409         /* FIXME: add subpixel order */
11410 done:
11411         if (ret && crtc->state->enable)
11412                 crtc->mode = *saved_mode;
11413
11414         kfree(saved_mode);
11415         return ret;
11416 }
11417
11418 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11419                                 struct drm_display_mode *mode,
11420                                 int x, int y, struct drm_framebuffer *fb,
11421                                 struct intel_crtc_state *pipe_config,
11422                                 unsigned modeset_pipes,
11423                                 unsigned prepare_pipes,
11424                                 unsigned disable_pipes)
11425 {
11426         int ret;
11427
11428         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11429                                prepare_pipes, disable_pipes);
11430
11431         if (ret == 0)
11432                 intel_modeset_check_state(crtc->dev);
11433
11434         return ret;
11435 }
11436
11437 static int intel_set_mode(struct drm_crtc *crtc,
11438                           struct drm_display_mode *mode,
11439                           int x, int y, struct drm_framebuffer *fb)
11440 {
11441         struct intel_crtc_state *pipe_config;
11442         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11443
11444         pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11445                                                    &modeset_pipes,
11446                                                    &prepare_pipes,
11447                                                    &disable_pipes);
11448
11449         if (IS_ERR(pipe_config))
11450                 return PTR_ERR(pipe_config);
11451
11452         return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11453                                     modeset_pipes, prepare_pipes,
11454                                     disable_pipes);
11455 }
11456
11457 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11458 {
11459         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11460 }
11461
11462 #undef for_each_intel_crtc_masked
11463
11464 static void intel_set_config_free(struct intel_set_config *config)
11465 {
11466         if (!config)
11467                 return;
11468
11469         kfree(config->save_connector_encoders);
11470         kfree(config->save_encoder_crtcs);
11471         kfree(config->save_crtc_enabled);
11472         kfree(config);
11473 }
11474
11475 static int intel_set_config_save_state(struct drm_device *dev,
11476                                        struct intel_set_config *config)
11477 {
11478         struct drm_crtc *crtc;
11479         struct drm_encoder *encoder;
11480         struct drm_connector *connector;
11481         int count;
11482
11483         config->save_crtc_enabled =
11484                 kcalloc(dev->mode_config.num_crtc,
11485                         sizeof(bool), GFP_KERNEL);
11486         if (!config->save_crtc_enabled)
11487                 return -ENOMEM;
11488
11489         config->save_encoder_crtcs =
11490                 kcalloc(dev->mode_config.num_encoder,
11491                         sizeof(struct drm_crtc *), GFP_KERNEL);
11492         if (!config->save_encoder_crtcs)
11493                 return -ENOMEM;
11494
11495         config->save_connector_encoders =
11496                 kcalloc(dev->mode_config.num_connector,
11497                         sizeof(struct drm_encoder *), GFP_KERNEL);
11498         if (!config->save_connector_encoders)
11499                 return -ENOMEM;
11500
11501         /* Copy data. Note that driver private data is not affected.
11502          * Should anything bad happen only the expected state is
11503          * restored, not the drivers personal bookkeeping.
11504          */
11505         count = 0;
11506         for_each_crtc(dev, crtc) {
11507                 config->save_crtc_enabled[count++] = crtc->state->enable;
11508         }
11509
11510         count = 0;
11511         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11512                 config->save_encoder_crtcs[count++] = encoder->crtc;
11513         }
11514
11515         count = 0;
11516         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11517                 config->save_connector_encoders[count++] = connector->encoder;
11518         }
11519
11520         return 0;
11521 }
11522
11523 static void intel_set_config_restore_state(struct drm_device *dev,
11524                                            struct intel_set_config *config)
11525 {
11526         struct intel_crtc *crtc;
11527         struct intel_encoder *encoder;
11528         struct intel_connector *connector;
11529         int count;
11530
11531         count = 0;
11532         for_each_intel_crtc(dev, crtc) {
11533                 crtc->new_enabled = config->save_crtc_enabled[count++];
11534
11535                 if (crtc->new_enabled)
11536                         crtc->new_config = crtc->config;
11537                 else
11538                         crtc->new_config = NULL;
11539         }
11540
11541         count = 0;
11542         for_each_intel_encoder(dev, encoder) {
11543                 encoder->new_crtc =
11544                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11545         }
11546
11547         count = 0;
11548         for_each_intel_connector(dev, connector) {
11549                 connector->new_encoder =
11550                         to_intel_encoder(config->save_connector_encoders[count++]);
11551         }
11552 }
11553
11554 static bool
11555 is_crtc_connector_off(struct drm_mode_set *set)
11556 {
11557         int i;
11558
11559         if (set->num_connectors == 0)
11560                 return false;
11561
11562         if (WARN_ON(set->connectors == NULL))
11563                 return false;
11564
11565         for (i = 0; i < set->num_connectors; i++)
11566                 if (set->connectors[i]->encoder &&
11567                     set->connectors[i]->encoder->crtc == set->crtc &&
11568                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11569                         return true;
11570
11571         return false;
11572 }
11573
11574 static void
11575 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11576                                       struct intel_set_config *config)
11577 {
11578
11579         /* We should be able to check here if the fb has the same properties
11580          * and then just flip_or_move it */
11581         if (is_crtc_connector_off(set)) {
11582                 config->mode_changed = true;
11583         } else if (set->crtc->primary->fb != set->fb) {
11584                 /*
11585                  * If we have no fb, we can only flip as long as the crtc is
11586                  * active, otherwise we need a full mode set.  The crtc may
11587                  * be active if we've only disabled the primary plane, or
11588                  * in fastboot situations.
11589                  */
11590                 if (set->crtc->primary->fb == NULL) {
11591                         struct intel_crtc *intel_crtc =
11592                                 to_intel_crtc(set->crtc);
11593
11594                         if (intel_crtc->active) {
11595                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11596                                 config->fb_changed = true;
11597                         } else {
11598                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11599                                 config->mode_changed = true;
11600                         }
11601                 } else if (set->fb == NULL) {
11602                         config->mode_changed = true;
11603                 } else if (set->fb->pixel_format !=
11604                            set->crtc->primary->fb->pixel_format) {
11605                         config->mode_changed = true;
11606                 } else {
11607                         config->fb_changed = true;
11608                 }
11609         }
11610
11611         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11612                 config->fb_changed = true;
11613
11614         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11615                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11616                 drm_mode_debug_printmodeline(&set->crtc->mode);
11617                 drm_mode_debug_printmodeline(set->mode);
11618                 config->mode_changed = true;
11619         }
11620
11621         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11622                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11623 }
11624
11625 static int
11626 intel_modeset_stage_output_state(struct drm_device *dev,
11627                                  struct drm_mode_set *set,
11628                                  struct intel_set_config *config)
11629 {
11630         struct intel_connector *connector;
11631         struct intel_encoder *encoder;
11632         struct intel_crtc *crtc;
11633         int ro;
11634
11635         /* The upper layers ensure that we either disable a crtc or have a list
11636          * of connectors. For paranoia, double-check this. */
11637         WARN_ON(!set->fb && (set->num_connectors != 0));
11638         WARN_ON(set->fb && (set->num_connectors == 0));
11639
11640         for_each_intel_connector(dev, connector) {
11641                 /* Otherwise traverse passed in connector list and get encoders
11642                  * for them. */
11643                 for (ro = 0; ro < set->num_connectors; ro++) {
11644                         if (set->connectors[ro] == &connector->base) {
11645                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11646                                 break;
11647                         }
11648                 }
11649
11650                 /* If we disable the crtc, disable all its connectors. Also, if
11651                  * the connector is on the changing crtc but not on the new
11652                  * connector list, disable it. */
11653                 if ((!set->fb || ro == set->num_connectors) &&
11654                     connector->base.encoder &&
11655                     connector->base.encoder->crtc == set->crtc) {
11656                         connector->new_encoder = NULL;
11657
11658                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11659                                 connector->base.base.id,
11660                                 connector->base.name);
11661                 }
11662
11663
11664                 if (&connector->new_encoder->base != connector->base.encoder) {
11665                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11666                                       connector->base.base.id,
11667                                       connector->base.name);
11668                         config->mode_changed = true;
11669                 }
11670         }
11671         /* connector->new_encoder is now updated for all connectors. */
11672
11673         /* Update crtc of enabled connectors. */
11674         for_each_intel_connector(dev, connector) {
11675                 struct drm_crtc *new_crtc;
11676
11677                 if (!connector->new_encoder)
11678                         continue;
11679
11680                 new_crtc = connector->new_encoder->base.crtc;
11681
11682                 for (ro = 0; ro < set->num_connectors; ro++) {
11683                         if (set->connectors[ro] == &connector->base)
11684                                 new_crtc = set->crtc;
11685                 }
11686
11687                 /* Make sure the new CRTC will work with the encoder */
11688                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11689                                          new_crtc)) {
11690                         return -EINVAL;
11691                 }
11692                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11693
11694                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11695                         connector->base.base.id,
11696                         connector->base.name,
11697                         new_crtc->base.id);
11698         }
11699
11700         /* Check for any encoders that needs to be disabled. */
11701         for_each_intel_encoder(dev, encoder) {
11702                 int num_connectors = 0;
11703                 for_each_intel_connector(dev, connector) {
11704                         if (connector->new_encoder == encoder) {
11705                                 WARN_ON(!connector->new_encoder->new_crtc);
11706                                 num_connectors++;
11707                         }
11708                 }
11709
11710                 if (num_connectors == 0)
11711                         encoder->new_crtc = NULL;
11712                 else if (num_connectors > 1)
11713                         return -EINVAL;
11714
11715                 /* Only now check for crtc changes so we don't miss encoders
11716                  * that will be disabled. */
11717                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11718                         DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11719                                       encoder->base.base.id,
11720                                       encoder->base.name);
11721                         config->mode_changed = true;
11722                 }
11723         }
11724         /* Now we've also updated encoder->new_crtc for all encoders. */
11725         for_each_intel_connector(dev, connector) {
11726                 if (connector->new_encoder)
11727                         if (connector->new_encoder != connector->encoder)
11728                                 connector->encoder = connector->new_encoder;
11729         }
11730         for_each_intel_crtc(dev, crtc) {
11731                 crtc->new_enabled = false;
11732
11733                 for_each_intel_encoder(dev, encoder) {
11734                         if (encoder->new_crtc == crtc) {
11735                                 crtc->new_enabled = true;
11736                                 break;
11737                         }
11738                 }
11739
11740                 if (crtc->new_enabled != crtc->base.state->enable) {
11741                         DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11742                                       crtc->base.base.id,
11743                                       crtc->new_enabled ? "en" : "dis");
11744                         config->mode_changed = true;
11745                 }
11746
11747                 if (crtc->new_enabled)
11748                         crtc->new_config = crtc->config;
11749                 else
11750                         crtc->new_config = NULL;
11751         }
11752
11753         return 0;
11754 }
11755
11756 static void disable_crtc_nofb(struct intel_crtc *crtc)
11757 {
11758         struct drm_device *dev = crtc->base.dev;
11759         struct intel_encoder *encoder;
11760         struct intel_connector *connector;
11761
11762         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11763                       pipe_name(crtc->pipe));
11764
11765         for_each_intel_connector(dev, connector) {
11766                 if (connector->new_encoder &&
11767                     connector->new_encoder->new_crtc == crtc)
11768                         connector->new_encoder = NULL;
11769         }
11770
11771         for_each_intel_encoder(dev, encoder) {
11772                 if (encoder->new_crtc == crtc)
11773                         encoder->new_crtc = NULL;
11774         }
11775
11776         crtc->new_enabled = false;
11777         crtc->new_config = NULL;
11778 }
11779
11780 static int intel_crtc_set_config(struct drm_mode_set *set)
11781 {
11782         struct drm_device *dev;
11783         struct drm_mode_set save_set;
11784         struct intel_set_config *config;
11785         struct intel_crtc_state *pipe_config;
11786         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11787         int ret;
11788
11789         BUG_ON(!set);
11790         BUG_ON(!set->crtc);
11791         BUG_ON(!set->crtc->helper_private);
11792
11793         /* Enforce sane interface api - has been abused by the fb helper. */
11794         BUG_ON(!set->mode && set->fb);
11795         BUG_ON(set->fb && set->num_connectors == 0);
11796
11797         if (set->fb) {
11798                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11799                                 set->crtc->base.id, set->fb->base.id,
11800                                 (int)set->num_connectors, set->x, set->y);
11801         } else {
11802                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11803         }
11804
11805         dev = set->crtc->dev;
11806
11807         ret = -ENOMEM;
11808         config = kzalloc(sizeof(*config), GFP_KERNEL);
11809         if (!config)
11810                 goto out_config;
11811
11812         ret = intel_set_config_save_state(dev, config);
11813         if (ret)
11814                 goto out_config;
11815
11816         save_set.crtc = set->crtc;
11817         save_set.mode = &set->crtc->mode;
11818         save_set.x = set->crtc->x;
11819         save_set.y = set->crtc->y;
11820         save_set.fb = set->crtc->primary->fb;
11821
11822         /* Compute whether we need a full modeset, only an fb base update or no
11823          * change at all. In the future we might also check whether only the
11824          * mode changed, e.g. for LVDS where we only change the panel fitter in
11825          * such cases. */
11826         intel_set_config_compute_mode_changes(set, config);
11827
11828         ret = intel_modeset_stage_output_state(dev, set, config);
11829         if (ret)
11830                 goto fail;
11831
11832         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11833                                                    set->fb,
11834                                                    &modeset_pipes,
11835                                                    &prepare_pipes,
11836                                                    &disable_pipes);
11837         if (IS_ERR(pipe_config)) {
11838                 ret = PTR_ERR(pipe_config);
11839                 goto fail;
11840         } else if (pipe_config) {
11841                 if (pipe_config->has_audio !=
11842                     to_intel_crtc(set->crtc)->config->has_audio)
11843                         config->mode_changed = true;
11844
11845                 /*
11846                  * Note we have an issue here with infoframes: current code
11847                  * only updates them on the full mode set path per hw
11848                  * requirements.  So here we should be checking for any
11849                  * required changes and forcing a mode set.
11850                  */
11851         }
11852
11853         /* set_mode will free it in the mode_changed case */
11854         if (!config->mode_changed)
11855                 kfree(pipe_config);
11856
11857         intel_update_pipe_size(to_intel_crtc(set->crtc));
11858
11859         if (config->mode_changed) {
11860                 ret = intel_set_mode_pipes(set->crtc, set->mode,
11861                                            set->x, set->y, set->fb, pipe_config,
11862                                            modeset_pipes, prepare_pipes,
11863                                            disable_pipes);
11864         } else if (config->fb_changed) {
11865                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11866                 struct drm_plane *primary = set->crtc->primary;
11867                 int vdisplay, hdisplay;
11868
11869                 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11870                 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11871                                                    0, 0, hdisplay, vdisplay,
11872                                                    set->x << 16, set->y << 16,
11873                                                    hdisplay << 16, vdisplay << 16);
11874
11875                 /*
11876                  * We need to make sure the primary plane is re-enabled if it
11877                  * has previously been turned off.
11878                  */
11879                 if (!intel_crtc->primary_enabled && ret == 0) {
11880                         WARN_ON(!intel_crtc->active);
11881                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11882                 }
11883
11884                 /*
11885                  * In the fastboot case this may be our only check of the
11886                  * state after boot.  It would be better to only do it on
11887                  * the first update, but we don't have a nice way of doing that
11888                  * (and really, set_config isn't used much for high freq page
11889                  * flipping, so increasing its cost here shouldn't be a big
11890                  * deal).
11891                  */
11892                 if (i915.fastboot && ret == 0)
11893                         intel_modeset_check_state(set->crtc->dev);
11894         }
11895
11896         if (ret) {
11897                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11898                               set->crtc->base.id, ret);
11899 fail:
11900                 intel_set_config_restore_state(dev, config);
11901
11902                 /*
11903                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11904                  * force the pipe off to avoid oopsing in the modeset code
11905                  * due to fb==NULL. This should only happen during boot since
11906                  * we don't yet reconstruct the FB from the hardware state.
11907                  */
11908                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11909                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11910
11911                 /* Try to restore the config */
11912                 if (config->mode_changed &&
11913                     intel_set_mode(save_set.crtc, save_set.mode,
11914                                    save_set.x, save_set.y, save_set.fb))
11915                         DRM_ERROR("failed to restore config after modeset failure\n");
11916         }
11917
11918 out_config:
11919         intel_set_config_free(config);
11920         return ret;
11921 }
11922
11923 static const struct drm_crtc_funcs intel_crtc_funcs = {
11924         .gamma_set = intel_crtc_gamma_set,
11925         .set_config = intel_crtc_set_config,
11926         .destroy = intel_crtc_destroy,
11927         .page_flip = intel_crtc_page_flip,
11928         .atomic_duplicate_state = intel_crtc_duplicate_state,
11929         .atomic_destroy_state = intel_crtc_destroy_state,
11930 };
11931
11932 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11933                                       struct intel_shared_dpll *pll,
11934                                       struct intel_dpll_hw_state *hw_state)
11935 {
11936         uint32_t val;
11937
11938         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11939                 return false;
11940
11941         val = I915_READ(PCH_DPLL(pll->id));
11942         hw_state->dpll = val;
11943         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11944         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11945
11946         return val & DPLL_VCO_ENABLE;
11947 }
11948
11949 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11950                                   struct intel_shared_dpll *pll)
11951 {
11952         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11953         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11954 }
11955
11956 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11957                                 struct intel_shared_dpll *pll)
11958 {
11959         /* PCH refclock must be enabled first */
11960         ibx_assert_pch_refclk_enabled(dev_priv);
11961
11962         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11963
11964         /* Wait for the clocks to stabilize. */
11965         POSTING_READ(PCH_DPLL(pll->id));
11966         udelay(150);
11967
11968         /* The pixel multiplier can only be updated once the
11969          * DPLL is enabled and the clocks are stable.
11970          *
11971          * So write it again.
11972          */
11973         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11974         POSTING_READ(PCH_DPLL(pll->id));
11975         udelay(200);
11976 }
11977
11978 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11979                                  struct intel_shared_dpll *pll)
11980 {
11981         struct drm_device *dev = dev_priv->dev;
11982         struct intel_crtc *crtc;
11983
11984         /* Make sure no transcoder isn't still depending on us. */
11985         for_each_intel_crtc(dev, crtc) {
11986                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11987                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11988         }
11989
11990         I915_WRITE(PCH_DPLL(pll->id), 0);
11991         POSTING_READ(PCH_DPLL(pll->id));
11992         udelay(200);
11993 }
11994
11995 static char *ibx_pch_dpll_names[] = {
11996         "PCH DPLL A",
11997         "PCH DPLL B",
11998 };
11999
12000 static void ibx_pch_dpll_init(struct drm_device *dev)
12001 {
12002         struct drm_i915_private *dev_priv = dev->dev_private;
12003         int i;
12004
12005         dev_priv->num_shared_dpll = 2;
12006
12007         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12008                 dev_priv->shared_dplls[i].id = i;
12009                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12010                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12011                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12012                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12013                 dev_priv->shared_dplls[i].get_hw_state =
12014                         ibx_pch_dpll_get_hw_state;
12015         }
12016 }
12017
12018 static void intel_shared_dpll_init(struct drm_device *dev)
12019 {
12020         struct drm_i915_private *dev_priv = dev->dev_private;
12021
12022         if (HAS_DDI(dev))
12023                 intel_ddi_pll_init(dev);
12024         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12025                 ibx_pch_dpll_init(dev);
12026         else
12027                 dev_priv->num_shared_dpll = 0;
12028
12029         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12030 }
12031
12032 /**
12033  * intel_wm_need_update - Check whether watermarks need updating
12034  * @plane: drm plane
12035  * @state: new plane state
12036  *
12037  * Check current plane state versus the new one to determine whether
12038  * watermarks need to be recalculated.
12039  *
12040  * Returns true or false.
12041  */
12042 bool intel_wm_need_update(struct drm_plane *plane,
12043                           struct drm_plane_state *state)
12044 {
12045         /* Update watermarks on tiling changes. */
12046         if (!plane->state->fb || !state->fb ||
12047             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12048             plane->state->rotation != state->rotation)
12049                 return true;
12050
12051         return false;
12052 }
12053
12054 /**
12055  * intel_prepare_plane_fb - Prepare fb for usage on plane
12056  * @plane: drm plane to prepare for
12057  * @fb: framebuffer to prepare for presentation
12058  *
12059  * Prepares a framebuffer for usage on a display plane.  Generally this
12060  * involves pinning the underlying object and updating the frontbuffer tracking
12061  * bits.  Some older platforms need special physical address handling for
12062  * cursor planes.
12063  *
12064  * Returns 0 on success, negative error code on failure.
12065  */
12066 int
12067 intel_prepare_plane_fb(struct drm_plane *plane,
12068                        struct drm_framebuffer *fb,
12069                        const struct drm_plane_state *new_state)
12070 {
12071         struct drm_device *dev = plane->dev;
12072         struct intel_plane *intel_plane = to_intel_plane(plane);
12073         enum pipe pipe = intel_plane->pipe;
12074         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12075         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12076         unsigned frontbuffer_bits = 0;
12077         int ret = 0;
12078
12079         if (!obj)
12080                 return 0;
12081
12082         switch (plane->type) {
12083         case DRM_PLANE_TYPE_PRIMARY:
12084                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12085                 break;
12086         case DRM_PLANE_TYPE_CURSOR:
12087                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12088                 break;
12089         case DRM_PLANE_TYPE_OVERLAY:
12090                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12091                 break;
12092         }
12093
12094         mutex_lock(&dev->struct_mutex);
12095
12096         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12097             INTEL_INFO(dev)->cursor_needs_physical) {
12098                 int align = IS_I830(dev) ? 16 * 1024 : 256;
12099                 ret = i915_gem_object_attach_phys(obj, align);
12100                 if (ret)
12101                         DRM_DEBUG_KMS("failed to attach phys object\n");
12102         } else {
12103                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12104         }
12105
12106         if (ret == 0)
12107                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12108
12109         mutex_unlock(&dev->struct_mutex);
12110
12111         return ret;
12112 }
12113
12114 /**
12115  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12116  * @plane: drm plane to clean up for
12117  * @fb: old framebuffer that was on plane
12118  *
12119  * Cleans up a framebuffer that has just been removed from a plane.
12120  */
12121 void
12122 intel_cleanup_plane_fb(struct drm_plane *plane,
12123                        struct drm_framebuffer *fb,
12124                        const struct drm_plane_state *old_state)
12125 {
12126         struct drm_device *dev = plane->dev;
12127         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12128
12129         if (WARN_ON(!obj))
12130                 return;
12131
12132         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12133             !INTEL_INFO(dev)->cursor_needs_physical) {
12134                 mutex_lock(&dev->struct_mutex);
12135                 intel_unpin_fb_obj(fb, old_state);
12136                 mutex_unlock(&dev->struct_mutex);
12137         }
12138 }
12139
12140 static int
12141 intel_check_primary_plane(struct drm_plane *plane,
12142                           struct intel_plane_state *state)
12143 {
12144         struct drm_device *dev = plane->dev;
12145         struct drm_i915_private *dev_priv = dev->dev_private;
12146         struct drm_crtc *crtc = state->base.crtc;
12147         struct intel_crtc *intel_crtc;
12148         struct drm_framebuffer *fb = state->base.fb;
12149         struct drm_rect *dest = &state->dst;
12150         struct drm_rect *src = &state->src;
12151         const struct drm_rect *clip = &state->clip;
12152         int ret;
12153
12154         crtc = crtc ? crtc : plane->crtc;
12155         intel_crtc = to_intel_crtc(crtc);
12156
12157         ret = drm_plane_helper_check_update(plane, crtc, fb,
12158                                             src, dest, clip,
12159                                             DRM_PLANE_HELPER_NO_SCALING,
12160                                             DRM_PLANE_HELPER_NO_SCALING,
12161                                             false, true, &state->visible);
12162         if (ret)
12163                 return ret;
12164
12165         if (intel_crtc->active) {
12166                 intel_crtc->atomic.wait_for_flips = true;
12167
12168                 /*
12169                  * FBC does not work on some platforms for rotated
12170                  * planes, so disable it when rotation is not 0 and
12171                  * update it when rotation is set back to 0.
12172                  *
12173                  * FIXME: This is redundant with the fbc update done in
12174                  * the primary plane enable function except that that
12175                  * one is done too late. We eventually need to unify
12176                  * this.
12177                  */
12178                 if (intel_crtc->primary_enabled &&
12179                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12180                     dev_priv->fbc.crtc == intel_crtc &&
12181                     state->base.rotation != BIT(DRM_ROTATE_0)) {
12182                         intel_crtc->atomic.disable_fbc = true;
12183                 }
12184
12185                 if (state->visible) {
12186                         /*
12187                          * BDW signals flip done immediately if the plane
12188                          * is disabled, even if the plane enable is already
12189                          * armed to occur at the next vblank :(
12190                          */
12191                         if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12192                                 intel_crtc->atomic.wait_vblank = true;
12193                 }
12194
12195                 intel_crtc->atomic.fb_bits |=
12196                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12197
12198                 intel_crtc->atomic.update_fbc = true;
12199
12200                 if (intel_wm_need_update(plane, &state->base))
12201                         intel_crtc->atomic.update_wm = true;
12202         }
12203
12204         return 0;
12205 }
12206
12207 static void
12208 intel_commit_primary_plane(struct drm_plane *plane,
12209                            struct intel_plane_state *state)
12210 {
12211         struct drm_crtc *crtc = state->base.crtc;
12212         struct drm_framebuffer *fb = state->base.fb;
12213         struct drm_device *dev = plane->dev;
12214         struct drm_i915_private *dev_priv = dev->dev_private;
12215         struct intel_crtc *intel_crtc;
12216         struct drm_rect *src = &state->src;
12217
12218         crtc = crtc ? crtc : plane->crtc;
12219         intel_crtc = to_intel_crtc(crtc);
12220
12221         plane->fb = fb;
12222         crtc->x = src->x1 >> 16;
12223         crtc->y = src->y1 >> 16;
12224
12225         if (intel_crtc->active) {
12226                 if (state->visible) {
12227                         /* FIXME: kill this fastboot hack */
12228                         intel_update_pipe_size(intel_crtc);
12229
12230                         intel_crtc->primary_enabled = true;
12231
12232                         dev_priv->display.update_primary_plane(crtc, plane->fb,
12233                                         crtc->x, crtc->y);
12234                 } else {
12235                         /*
12236                          * If clipping results in a non-visible primary plane,
12237                          * we'll disable the primary plane.  Note that this is
12238                          * a bit different than what happens if userspace
12239                          * explicitly disables the plane by passing fb=0
12240                          * because plane->fb still gets set and pinned.
12241                          */
12242                         intel_disable_primary_hw_plane(plane, crtc);
12243                 }
12244         }
12245 }
12246
12247 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12248 {
12249         struct drm_device *dev = crtc->dev;
12250         struct drm_i915_private *dev_priv = dev->dev_private;
12251         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12252         struct intel_plane *intel_plane;
12253         struct drm_plane *p;
12254         unsigned fb_bits = 0;
12255
12256         /* Track fb's for any planes being disabled */
12257         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12258                 intel_plane = to_intel_plane(p);
12259
12260                 if (intel_crtc->atomic.disabled_planes &
12261                     (1 << drm_plane_index(p))) {
12262                         switch (p->type) {
12263                         case DRM_PLANE_TYPE_PRIMARY:
12264                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12265                                 break;
12266                         case DRM_PLANE_TYPE_CURSOR:
12267                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12268                                 break;
12269                         case DRM_PLANE_TYPE_OVERLAY:
12270                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12271                                 break;
12272                         }
12273
12274                         mutex_lock(&dev->struct_mutex);
12275                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12276                         mutex_unlock(&dev->struct_mutex);
12277                 }
12278         }
12279
12280         if (intel_crtc->atomic.wait_for_flips)
12281                 intel_crtc_wait_for_pending_flips(crtc);
12282
12283         if (intel_crtc->atomic.disable_fbc)
12284                 intel_fbc_disable(dev);
12285
12286         if (intel_crtc->atomic.pre_disable_primary)
12287                 intel_pre_disable_primary(crtc);
12288
12289         if (intel_crtc->atomic.update_wm)
12290                 intel_update_watermarks(crtc);
12291
12292         intel_runtime_pm_get(dev_priv);
12293
12294         /* Perform vblank evasion around commit operation */
12295         if (intel_crtc->active)
12296                 intel_crtc->atomic.evade =
12297                         intel_pipe_update_start(intel_crtc,
12298                                                 &intel_crtc->atomic.start_vbl_count);
12299 }
12300
12301 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12302 {
12303         struct drm_device *dev = crtc->dev;
12304         struct drm_i915_private *dev_priv = dev->dev_private;
12305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12306         struct drm_plane *p;
12307
12308         if (intel_crtc->atomic.evade)
12309                 intel_pipe_update_end(intel_crtc,
12310                                       intel_crtc->atomic.start_vbl_count);
12311
12312         intel_runtime_pm_put(dev_priv);
12313
12314         if (intel_crtc->atomic.wait_vblank)
12315                 intel_wait_for_vblank(dev, intel_crtc->pipe);
12316
12317         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12318
12319         if (intel_crtc->atomic.update_fbc) {
12320                 mutex_lock(&dev->struct_mutex);
12321                 intel_fbc_update(dev);
12322                 mutex_unlock(&dev->struct_mutex);
12323         }
12324
12325         if (intel_crtc->atomic.post_enable_primary)
12326                 intel_post_enable_primary(crtc);
12327
12328         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12329                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12330                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12331                                                        false, false);
12332
12333         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12334 }
12335
12336 /**
12337  * intel_plane_destroy - destroy a plane
12338  * @plane: plane to destroy
12339  *
12340  * Common destruction function for all types of planes (primary, cursor,
12341  * sprite).
12342  */
12343 void intel_plane_destroy(struct drm_plane *plane)
12344 {
12345         struct intel_plane *intel_plane = to_intel_plane(plane);
12346         drm_plane_cleanup(plane);
12347         kfree(intel_plane);
12348 }
12349
12350 const struct drm_plane_funcs intel_plane_funcs = {
12351         .update_plane = drm_plane_helper_update,
12352         .disable_plane = drm_plane_helper_disable,
12353         .destroy = intel_plane_destroy,
12354         .set_property = drm_atomic_helper_plane_set_property,
12355         .atomic_get_property = intel_plane_atomic_get_property,
12356         .atomic_set_property = intel_plane_atomic_set_property,
12357         .atomic_duplicate_state = intel_plane_duplicate_state,
12358         .atomic_destroy_state = intel_plane_destroy_state,
12359
12360 };
12361
12362 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12363                                                     int pipe)
12364 {
12365         struct intel_plane *primary;
12366         struct intel_plane_state *state;
12367         const uint32_t *intel_primary_formats;
12368         int num_formats;
12369
12370         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12371         if (primary == NULL)
12372                 return NULL;
12373
12374         state = intel_create_plane_state(&primary->base);
12375         if (!state) {
12376                 kfree(primary);
12377                 return NULL;
12378         }
12379         primary->base.state = &state->base;
12380
12381         primary->can_scale = false;
12382         primary->max_downscale = 1;
12383         primary->pipe = pipe;
12384         primary->plane = pipe;
12385         primary->check_plane = intel_check_primary_plane;
12386         primary->commit_plane = intel_commit_primary_plane;
12387         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12388                 primary->plane = !pipe;
12389
12390         if (INTEL_INFO(dev)->gen <= 3) {
12391                 intel_primary_formats = intel_primary_formats_gen2;
12392                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12393         } else {
12394                 intel_primary_formats = intel_primary_formats_gen4;
12395                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12396         }
12397
12398         drm_universal_plane_init(dev, &primary->base, 0,
12399                                  &intel_plane_funcs,
12400                                  intel_primary_formats, num_formats,
12401                                  DRM_PLANE_TYPE_PRIMARY);
12402
12403         if (INTEL_INFO(dev)->gen >= 4) {
12404                 if (!dev->mode_config.rotation_property)
12405                         dev->mode_config.rotation_property =
12406                                 drm_mode_create_rotation_property(dev,
12407                                                         BIT(DRM_ROTATE_0) |
12408                                                         BIT(DRM_ROTATE_180));
12409                 if (dev->mode_config.rotation_property)
12410                         drm_object_attach_property(&primary->base.base,
12411                                 dev->mode_config.rotation_property,
12412                                 state->base.rotation);
12413         }
12414
12415         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12416
12417         return &primary->base;
12418 }
12419
12420 static int
12421 intel_check_cursor_plane(struct drm_plane *plane,
12422                          struct intel_plane_state *state)
12423 {
12424         struct drm_crtc *crtc = state->base.crtc;
12425         struct drm_device *dev = plane->dev;
12426         struct drm_framebuffer *fb = state->base.fb;
12427         struct drm_rect *dest = &state->dst;
12428         struct drm_rect *src = &state->src;
12429         const struct drm_rect *clip = &state->clip;
12430         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12431         struct intel_crtc *intel_crtc;
12432         unsigned stride;
12433         int ret;
12434
12435         crtc = crtc ? crtc : plane->crtc;
12436         intel_crtc = to_intel_crtc(crtc);
12437
12438         ret = drm_plane_helper_check_update(plane, crtc, fb,
12439                                             src, dest, clip,
12440                                             DRM_PLANE_HELPER_NO_SCALING,
12441                                             DRM_PLANE_HELPER_NO_SCALING,
12442                                             true, true, &state->visible);
12443         if (ret)
12444                 return ret;
12445
12446
12447         /* if we want to turn off the cursor ignore width and height */
12448         if (!obj)
12449                 goto finish;
12450
12451         /* Check for which cursor types we support */
12452         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12453                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12454                           state->base.crtc_w, state->base.crtc_h);
12455                 return -EINVAL;
12456         }
12457
12458         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12459         if (obj->base.size < stride * state->base.crtc_h) {
12460                 DRM_DEBUG_KMS("buffer is too small\n");
12461                 return -ENOMEM;
12462         }
12463
12464         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12465                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12466                 ret = -EINVAL;
12467         }
12468
12469 finish:
12470         if (intel_crtc->active) {
12471                 if (plane->state->crtc_w != state->base.crtc_w)
12472                         intel_crtc->atomic.update_wm = true;
12473
12474                 intel_crtc->atomic.fb_bits |=
12475                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12476         }
12477
12478         return ret;
12479 }
12480
12481 static void
12482 intel_commit_cursor_plane(struct drm_plane *plane,
12483                           struct intel_plane_state *state)
12484 {
12485         struct drm_crtc *crtc = state->base.crtc;
12486         struct drm_device *dev = plane->dev;
12487         struct intel_crtc *intel_crtc;
12488         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12489         uint32_t addr;
12490
12491         crtc = crtc ? crtc : plane->crtc;
12492         intel_crtc = to_intel_crtc(crtc);
12493
12494         plane->fb = state->base.fb;
12495         crtc->cursor_x = state->base.crtc_x;
12496         crtc->cursor_y = state->base.crtc_y;
12497
12498         if (intel_crtc->cursor_bo == obj)
12499                 goto update;
12500
12501         if (!obj)
12502                 addr = 0;
12503         else if (!INTEL_INFO(dev)->cursor_needs_physical)
12504                 addr = i915_gem_obj_ggtt_offset(obj);
12505         else
12506                 addr = obj->phys_handle->busaddr;
12507
12508         intel_crtc->cursor_addr = addr;
12509         intel_crtc->cursor_bo = obj;
12510 update:
12511
12512         if (intel_crtc->active)
12513                 intel_crtc_update_cursor(crtc, state->visible);
12514 }
12515
12516 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12517                                                    int pipe)
12518 {
12519         struct intel_plane *cursor;
12520         struct intel_plane_state *state;
12521
12522         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12523         if (cursor == NULL)
12524                 return NULL;
12525
12526         state = intel_create_plane_state(&cursor->base);
12527         if (!state) {
12528                 kfree(cursor);
12529                 return NULL;
12530         }
12531         cursor->base.state = &state->base;
12532
12533         cursor->can_scale = false;
12534         cursor->max_downscale = 1;
12535         cursor->pipe = pipe;
12536         cursor->plane = pipe;
12537         cursor->check_plane = intel_check_cursor_plane;
12538         cursor->commit_plane = intel_commit_cursor_plane;
12539
12540         drm_universal_plane_init(dev, &cursor->base, 0,
12541                                  &intel_plane_funcs,
12542                                  intel_cursor_formats,
12543                                  ARRAY_SIZE(intel_cursor_formats),
12544                                  DRM_PLANE_TYPE_CURSOR);
12545
12546         if (INTEL_INFO(dev)->gen >= 4) {
12547                 if (!dev->mode_config.rotation_property)
12548                         dev->mode_config.rotation_property =
12549                                 drm_mode_create_rotation_property(dev,
12550                                                         BIT(DRM_ROTATE_0) |
12551                                                         BIT(DRM_ROTATE_180));
12552                 if (dev->mode_config.rotation_property)
12553                         drm_object_attach_property(&cursor->base.base,
12554                                 dev->mode_config.rotation_property,
12555                                 state->base.rotation);
12556         }
12557
12558         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12559
12560         return &cursor->base;
12561 }
12562
12563 static void intel_crtc_init(struct drm_device *dev, int pipe)
12564 {
12565         struct drm_i915_private *dev_priv = dev->dev_private;
12566         struct intel_crtc *intel_crtc;
12567         struct intel_crtc_state *crtc_state = NULL;
12568         struct drm_plane *primary = NULL;
12569         struct drm_plane *cursor = NULL;
12570         int i, ret;
12571
12572         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12573         if (intel_crtc == NULL)
12574                 return;
12575
12576         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12577         if (!crtc_state)
12578                 goto fail;
12579         intel_crtc_set_state(intel_crtc, crtc_state);
12580         crtc_state->base.crtc = &intel_crtc->base;
12581
12582         primary = intel_primary_plane_create(dev, pipe);
12583         if (!primary)
12584                 goto fail;
12585
12586         cursor = intel_cursor_plane_create(dev, pipe);
12587         if (!cursor)
12588                 goto fail;
12589
12590         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12591                                         cursor, &intel_crtc_funcs);
12592         if (ret)
12593                 goto fail;
12594
12595         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12596         for (i = 0; i < 256; i++) {
12597                 intel_crtc->lut_r[i] = i;
12598                 intel_crtc->lut_g[i] = i;
12599                 intel_crtc->lut_b[i] = i;
12600         }
12601
12602         /*
12603          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12604          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12605          */
12606         intel_crtc->pipe = pipe;
12607         intel_crtc->plane = pipe;
12608         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12609                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12610                 intel_crtc->plane = !pipe;
12611         }
12612
12613         intel_crtc->cursor_base = ~0;
12614         intel_crtc->cursor_cntl = ~0;
12615         intel_crtc->cursor_size = ~0;
12616
12617         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12618                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12619         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12620         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12621
12622         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12623
12624         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12625
12626         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12627         return;
12628
12629 fail:
12630         if (primary)
12631                 drm_plane_cleanup(primary);
12632         if (cursor)
12633                 drm_plane_cleanup(cursor);
12634         kfree(crtc_state);
12635         kfree(intel_crtc);
12636 }
12637
12638 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12639 {
12640         struct drm_encoder *encoder = connector->base.encoder;
12641         struct drm_device *dev = connector->base.dev;
12642
12643         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12644
12645         if (!encoder || WARN_ON(!encoder->crtc))
12646                 return INVALID_PIPE;
12647
12648         return to_intel_crtc(encoder->crtc)->pipe;
12649 }
12650
12651 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12652                                 struct drm_file *file)
12653 {
12654         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12655         struct drm_crtc *drmmode_crtc;
12656         struct intel_crtc *crtc;
12657
12658         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12659
12660         if (!drmmode_crtc) {
12661                 DRM_ERROR("no such CRTC id\n");
12662                 return -ENOENT;
12663         }
12664
12665         crtc = to_intel_crtc(drmmode_crtc);
12666         pipe_from_crtc_id->pipe = crtc->pipe;
12667
12668         return 0;
12669 }
12670
12671 static int intel_encoder_clones(struct intel_encoder *encoder)
12672 {
12673         struct drm_device *dev = encoder->base.dev;
12674         struct intel_encoder *source_encoder;
12675         int index_mask = 0;
12676         int entry = 0;
12677
12678         for_each_intel_encoder(dev, source_encoder) {
12679                 if (encoders_cloneable(encoder, source_encoder))
12680                         index_mask |= (1 << entry);
12681
12682                 entry++;
12683         }
12684
12685         return index_mask;
12686 }
12687
12688 static bool has_edp_a(struct drm_device *dev)
12689 {
12690         struct drm_i915_private *dev_priv = dev->dev_private;
12691
12692         if (!IS_MOBILE(dev))
12693                 return false;
12694
12695         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12696                 return false;
12697
12698         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12699                 return false;
12700
12701         return true;
12702 }
12703
12704 static bool intel_crt_present(struct drm_device *dev)
12705 {
12706         struct drm_i915_private *dev_priv = dev->dev_private;
12707
12708         if (INTEL_INFO(dev)->gen >= 9)
12709                 return false;
12710
12711         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12712                 return false;
12713
12714         if (IS_CHERRYVIEW(dev))
12715                 return false;
12716
12717         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12718                 return false;
12719
12720         return true;
12721 }
12722
12723 static void intel_setup_outputs(struct drm_device *dev)
12724 {
12725         struct drm_i915_private *dev_priv = dev->dev_private;
12726         struct intel_encoder *encoder;
12727         struct drm_connector *connector;
12728         bool dpd_is_edp = false;
12729
12730         intel_lvds_init(dev);
12731
12732         if (intel_crt_present(dev))
12733                 intel_crt_init(dev);
12734
12735         if (HAS_DDI(dev)) {
12736                 int found;
12737
12738                 /*
12739                  * Haswell uses DDI functions to detect digital outputs.
12740                  * On SKL pre-D0 the strap isn't connected, so we assume
12741                  * it's there.
12742                  */
12743                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12744                 /* WaIgnoreDDIAStrap: skl */
12745                 if (found ||
12746                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12747                         intel_ddi_init(dev, PORT_A);
12748
12749                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12750                  * register */
12751                 found = I915_READ(SFUSE_STRAP);
12752
12753                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12754                         intel_ddi_init(dev, PORT_B);
12755                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12756                         intel_ddi_init(dev, PORT_C);
12757                 if (found & SFUSE_STRAP_DDID_DETECTED)
12758                         intel_ddi_init(dev, PORT_D);
12759         } else if (HAS_PCH_SPLIT(dev)) {
12760                 int found;
12761                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12762
12763                 if (has_edp_a(dev))
12764                         intel_dp_init(dev, DP_A, PORT_A);
12765
12766                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12767                         /* PCH SDVOB multiplex with HDMIB */
12768                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12769                         if (!found)
12770                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12771                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12772                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12773                 }
12774
12775                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12776                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12777
12778                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12779                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12780
12781                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12782                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12783
12784                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12785                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12786         } else if (IS_VALLEYVIEW(dev)) {
12787                 /*
12788                  * The DP_DETECTED bit is the latched state of the DDC
12789                  * SDA pin at boot. However since eDP doesn't require DDC
12790                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12791                  * eDP ports may have been muxed to an alternate function.
12792                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12793                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12794                  * detect eDP ports.
12795                  */
12796                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12797                     !intel_dp_is_edp(dev, PORT_B))
12798                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12799                                         PORT_B);
12800                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12801                     intel_dp_is_edp(dev, PORT_B))
12802                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12803
12804                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12805                     !intel_dp_is_edp(dev, PORT_C))
12806                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12807                                         PORT_C);
12808                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12809                     intel_dp_is_edp(dev, PORT_C))
12810                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12811
12812                 if (IS_CHERRYVIEW(dev)) {
12813                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12814                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12815                                                 PORT_D);
12816                         /* eDP not supported on port D, so don't check VBT */
12817                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12818                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12819                 }
12820
12821                 intel_dsi_init(dev);
12822         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12823                 bool found = false;
12824
12825                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12826                         DRM_DEBUG_KMS("probing SDVOB\n");
12827                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12828                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12829                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12830                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12831                         }
12832
12833                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12834                                 intel_dp_init(dev, DP_B, PORT_B);
12835                 }
12836
12837                 /* Before G4X SDVOC doesn't have its own detect register */
12838
12839                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12840                         DRM_DEBUG_KMS("probing SDVOC\n");
12841                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12842                 }
12843
12844                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12845
12846                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12847                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12848                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12849                         }
12850                         if (SUPPORTS_INTEGRATED_DP(dev))
12851                                 intel_dp_init(dev, DP_C, PORT_C);
12852                 }
12853
12854                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12855                     (I915_READ(DP_D) & DP_DETECTED))
12856                         intel_dp_init(dev, DP_D, PORT_D);
12857         } else if (IS_GEN2(dev))
12858                 intel_dvo_init(dev);
12859
12860         if (SUPPORTS_TV(dev))
12861                 intel_tv_init(dev);
12862
12863         /*
12864          * FIXME:  We don't have full atomic support yet, but we want to be
12865          * able to enable/test plane updates via the atomic interface in the
12866          * meantime.  However as soon as we flip DRIVER_ATOMIC on, the DRM core
12867          * will take some atomic codepaths to lookup properties during
12868          * drmModeGetConnector() that unconditionally dereference
12869          * connector->state.
12870          *
12871          * We create a dummy connector state here for each connector to ensure
12872          * the DRM core doesn't try to dereference a NULL connector->state.
12873          * The actual connector properties will never be updated or contain
12874          * useful information, but since we're doing this specifically for
12875          * testing/debug of the plane operations (and only when a specific
12876          * kernel module option is given), that shouldn't really matter.
12877          *
12878          * Once atomic support for crtc's + connectors lands, this loop should
12879          * be removed since we'll be setting up real connector state, which
12880          * will contain Intel-specific properties.
12881          */
12882         if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12883                 list_for_each_entry(connector,
12884                                     &dev->mode_config.connector_list,
12885                                     head) {
12886                         if (!WARN_ON(connector->state)) {
12887                                 connector->state =
12888                                         kzalloc(sizeof(*connector->state),
12889                                                 GFP_KERNEL);
12890                         }
12891                 }
12892         }
12893
12894         intel_psr_init(dev);
12895
12896         for_each_intel_encoder(dev, encoder) {
12897                 encoder->base.possible_crtcs = encoder->crtc_mask;
12898                 encoder->base.possible_clones =
12899                         intel_encoder_clones(encoder);
12900         }
12901
12902         intel_init_pch_refclk(dev);
12903
12904         drm_helper_move_panel_connectors_to_head(dev);
12905 }
12906
12907 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12908 {
12909         struct drm_device *dev = fb->dev;
12910         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12911
12912         drm_framebuffer_cleanup(fb);
12913         mutex_lock(&dev->struct_mutex);
12914         WARN_ON(!intel_fb->obj->framebuffer_references--);
12915         drm_gem_object_unreference(&intel_fb->obj->base);
12916         mutex_unlock(&dev->struct_mutex);
12917         kfree(intel_fb);
12918 }
12919
12920 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12921                                                 struct drm_file *file,
12922                                                 unsigned int *handle)
12923 {
12924         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12925         struct drm_i915_gem_object *obj = intel_fb->obj;
12926
12927         return drm_gem_handle_create(file, &obj->base, handle);
12928 }
12929
12930 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12931         .destroy = intel_user_framebuffer_destroy,
12932         .create_handle = intel_user_framebuffer_create_handle,
12933 };
12934
12935 static
12936 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12937                          uint32_t pixel_format)
12938 {
12939         u32 gen = INTEL_INFO(dev)->gen;
12940
12941         if (gen >= 9) {
12942                 /* "The stride in bytes must not exceed the of the size of 8K
12943                  *  pixels and 32K bytes."
12944                  */
12945                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12946         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12947                 return 32*1024;
12948         } else if (gen >= 4) {
12949                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12950                         return 16*1024;
12951                 else
12952                         return 32*1024;
12953         } else if (gen >= 3) {
12954                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12955                         return 8*1024;
12956                 else
12957                         return 16*1024;
12958         } else {
12959                 /* XXX DSPC is limited to 4k tiled */
12960                 return 8*1024;
12961         }
12962 }
12963
12964 static int intel_framebuffer_init(struct drm_device *dev,
12965                                   struct intel_framebuffer *intel_fb,
12966                                   struct drm_mode_fb_cmd2 *mode_cmd,
12967                                   struct drm_i915_gem_object *obj)
12968 {
12969         unsigned int aligned_height;
12970         int ret;
12971         u32 pitch_limit, stride_alignment;
12972
12973         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12974
12975         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12976                 /* Enforce that fb modifier and tiling mode match, but only for
12977                  * X-tiled. This is needed for FBC. */
12978                 if (!!(obj->tiling_mode == I915_TILING_X) !=
12979                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12980                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12981                         return -EINVAL;
12982                 }
12983         } else {
12984                 if (obj->tiling_mode == I915_TILING_X)
12985                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12986                 else if (obj->tiling_mode == I915_TILING_Y) {
12987                         DRM_DEBUG("No Y tiling for legacy addfb\n");
12988                         return -EINVAL;
12989                 }
12990         }
12991
12992         /* Passed in modifier sanity checking. */
12993         switch (mode_cmd->modifier[0]) {
12994         case I915_FORMAT_MOD_Y_TILED:
12995         case I915_FORMAT_MOD_Yf_TILED:
12996                 if (INTEL_INFO(dev)->gen < 9) {
12997                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12998                                   mode_cmd->modifier[0]);
12999                         return -EINVAL;
13000                 }
13001         case DRM_FORMAT_MOD_NONE:
13002         case I915_FORMAT_MOD_X_TILED:
13003                 break;
13004         default:
13005                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13006                           mode_cmd->modifier[0]);
13007                 return -EINVAL;
13008         }
13009
13010         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13011                                                      mode_cmd->pixel_format);
13012         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13013                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13014                           mode_cmd->pitches[0], stride_alignment);
13015                 return -EINVAL;
13016         }
13017
13018         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13019                                            mode_cmd->pixel_format);
13020         if (mode_cmd->pitches[0] > pitch_limit) {
13021                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13022                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13023                           "tiled" : "linear",
13024                           mode_cmd->pitches[0], pitch_limit);
13025                 return -EINVAL;
13026         }
13027
13028         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13029             mode_cmd->pitches[0] != obj->stride) {
13030                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13031                           mode_cmd->pitches[0], obj->stride);
13032                 return -EINVAL;
13033         }
13034
13035         /* Reject formats not supported by any plane early. */
13036         switch (mode_cmd->pixel_format) {
13037         case DRM_FORMAT_C8:
13038         case DRM_FORMAT_RGB565:
13039         case DRM_FORMAT_XRGB8888:
13040         case DRM_FORMAT_ARGB8888:
13041                 break;
13042         case DRM_FORMAT_XRGB1555:
13043         case DRM_FORMAT_ARGB1555:
13044                 if (INTEL_INFO(dev)->gen > 3) {
13045                         DRM_DEBUG("unsupported pixel format: %s\n",
13046                                   drm_get_format_name(mode_cmd->pixel_format));
13047                         return -EINVAL;
13048                 }
13049                 break;
13050         case DRM_FORMAT_XBGR8888:
13051         case DRM_FORMAT_ABGR8888:
13052         case DRM_FORMAT_XRGB2101010:
13053         case DRM_FORMAT_ARGB2101010:
13054         case DRM_FORMAT_XBGR2101010:
13055         case DRM_FORMAT_ABGR2101010:
13056                 if (INTEL_INFO(dev)->gen < 4) {
13057                         DRM_DEBUG("unsupported pixel format: %s\n",
13058                                   drm_get_format_name(mode_cmd->pixel_format));
13059                         return -EINVAL;
13060                 }
13061                 break;
13062         case DRM_FORMAT_YUYV:
13063         case DRM_FORMAT_UYVY:
13064         case DRM_FORMAT_YVYU:
13065         case DRM_FORMAT_VYUY:
13066                 if (INTEL_INFO(dev)->gen < 5) {
13067                         DRM_DEBUG("unsupported pixel format: %s\n",
13068                                   drm_get_format_name(mode_cmd->pixel_format));
13069                         return -EINVAL;
13070                 }
13071                 break;
13072         default:
13073                 DRM_DEBUG("unsupported pixel format: %s\n",
13074                           drm_get_format_name(mode_cmd->pixel_format));
13075                 return -EINVAL;
13076         }
13077
13078         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13079         if (mode_cmd->offsets[0] != 0)
13080                 return -EINVAL;
13081
13082         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13083                                                mode_cmd->pixel_format,
13084                                                mode_cmd->modifier[0]);
13085         /* FIXME drm helper for size checks (especially planar formats)? */
13086         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13087                 return -EINVAL;
13088
13089         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13090         intel_fb->obj = obj;
13091         intel_fb->obj->framebuffer_references++;
13092
13093         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13094         if (ret) {
13095                 DRM_ERROR("framebuffer init failed %d\n", ret);
13096                 return ret;
13097         }
13098
13099         return 0;
13100 }
13101
13102 static struct drm_framebuffer *
13103 intel_user_framebuffer_create(struct drm_device *dev,
13104                               struct drm_file *filp,
13105                               struct drm_mode_fb_cmd2 *mode_cmd)
13106 {
13107         struct drm_i915_gem_object *obj;
13108
13109         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13110                                                 mode_cmd->handles[0]));
13111         if (&obj->base == NULL)
13112                 return ERR_PTR(-ENOENT);
13113
13114         return intel_framebuffer_create(dev, mode_cmd, obj);
13115 }
13116
13117 #ifndef CONFIG_DRM_I915_FBDEV
13118 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13119 {
13120 }
13121 #endif
13122
13123 static const struct drm_mode_config_funcs intel_mode_funcs = {
13124         .fb_create = intel_user_framebuffer_create,
13125         .output_poll_changed = intel_fbdev_output_poll_changed,
13126         .atomic_check = intel_atomic_check,
13127         .atomic_commit = intel_atomic_commit,
13128 };
13129
13130 /* Set up chip specific display functions */
13131 static void intel_init_display(struct drm_device *dev)
13132 {
13133         struct drm_i915_private *dev_priv = dev->dev_private;
13134
13135         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13136                 dev_priv->display.find_dpll = g4x_find_best_dpll;
13137         else if (IS_CHERRYVIEW(dev))
13138                 dev_priv->display.find_dpll = chv_find_best_dpll;
13139         else if (IS_VALLEYVIEW(dev))
13140                 dev_priv->display.find_dpll = vlv_find_best_dpll;
13141         else if (IS_PINEVIEW(dev))
13142                 dev_priv->display.find_dpll = pnv_find_best_dpll;
13143         else
13144                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13145
13146         if (INTEL_INFO(dev)->gen >= 9) {
13147                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13148                 dev_priv->display.get_initial_plane_config =
13149                         skylake_get_initial_plane_config;
13150                 dev_priv->display.crtc_compute_clock =
13151                         haswell_crtc_compute_clock;
13152                 dev_priv->display.crtc_enable = haswell_crtc_enable;
13153                 dev_priv->display.crtc_disable = haswell_crtc_disable;
13154                 dev_priv->display.off = ironlake_crtc_off;
13155                 dev_priv->display.update_primary_plane =
13156                         skylake_update_primary_plane;
13157         } else if (HAS_DDI(dev)) {
13158                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13159                 dev_priv->display.get_initial_plane_config =
13160                         ironlake_get_initial_plane_config;
13161                 dev_priv->display.crtc_compute_clock =
13162                         haswell_crtc_compute_clock;
13163                 dev_priv->display.crtc_enable = haswell_crtc_enable;
13164                 dev_priv->display.crtc_disable = haswell_crtc_disable;
13165                 dev_priv->display.off = ironlake_crtc_off;
13166                 dev_priv->display.update_primary_plane =
13167                         ironlake_update_primary_plane;
13168         } else if (HAS_PCH_SPLIT(dev)) {
13169                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13170                 dev_priv->display.get_initial_plane_config =
13171                         ironlake_get_initial_plane_config;
13172                 dev_priv->display.crtc_compute_clock =
13173                         ironlake_crtc_compute_clock;
13174                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13175                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13176                 dev_priv->display.off = ironlake_crtc_off;
13177                 dev_priv->display.update_primary_plane =
13178                         ironlake_update_primary_plane;
13179         } else if (IS_VALLEYVIEW(dev)) {
13180                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13181                 dev_priv->display.get_initial_plane_config =
13182                         i9xx_get_initial_plane_config;
13183                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13184                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13185                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13186                 dev_priv->display.off = i9xx_crtc_off;
13187                 dev_priv->display.update_primary_plane =
13188                         i9xx_update_primary_plane;
13189         } else {
13190                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13191                 dev_priv->display.get_initial_plane_config =
13192                         i9xx_get_initial_plane_config;
13193                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13194                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13195                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13196                 dev_priv->display.off = i9xx_crtc_off;
13197                 dev_priv->display.update_primary_plane =
13198                         i9xx_update_primary_plane;
13199         }
13200
13201         /* Returns the core display clock speed */
13202         if (IS_VALLEYVIEW(dev))
13203                 dev_priv->display.get_display_clock_speed =
13204                         valleyview_get_display_clock_speed;
13205         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13206                 dev_priv->display.get_display_clock_speed =
13207                         i945_get_display_clock_speed;
13208         else if (IS_I915G(dev))
13209                 dev_priv->display.get_display_clock_speed =
13210                         i915_get_display_clock_speed;
13211         else if (IS_I945GM(dev) || IS_845G(dev))
13212                 dev_priv->display.get_display_clock_speed =
13213                         i9xx_misc_get_display_clock_speed;
13214         else if (IS_PINEVIEW(dev))
13215                 dev_priv->display.get_display_clock_speed =
13216                         pnv_get_display_clock_speed;
13217         else if (IS_I915GM(dev))
13218                 dev_priv->display.get_display_clock_speed =
13219                         i915gm_get_display_clock_speed;
13220         else if (IS_I865G(dev))
13221                 dev_priv->display.get_display_clock_speed =
13222                         i865_get_display_clock_speed;
13223         else if (IS_I85X(dev))
13224                 dev_priv->display.get_display_clock_speed =
13225                         i855_get_display_clock_speed;
13226         else /* 852, 830 */
13227                 dev_priv->display.get_display_clock_speed =
13228                         i830_get_display_clock_speed;
13229
13230         if (IS_GEN5(dev)) {
13231                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13232         } else if (IS_GEN6(dev)) {
13233                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13234         } else if (IS_IVYBRIDGE(dev)) {
13235                 /* FIXME: detect B0+ stepping and use auto training */
13236                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13237         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13238                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13239         } else if (IS_VALLEYVIEW(dev)) {
13240                 dev_priv->display.modeset_global_resources =
13241                         valleyview_modeset_global_resources;
13242         }
13243
13244         switch (INTEL_INFO(dev)->gen) {
13245         case 2:
13246                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13247                 break;
13248
13249         case 3:
13250                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13251                 break;
13252
13253         case 4:
13254         case 5:
13255                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13256                 break;
13257
13258         case 6:
13259                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13260                 break;
13261         case 7:
13262         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13263                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13264                 break;
13265         case 9:
13266                 /* Drop through - unsupported since execlist only. */
13267         default:
13268                 /* Default just returns -ENODEV to indicate unsupported */
13269                 dev_priv->display.queue_flip = intel_default_queue_flip;
13270         }
13271
13272         intel_panel_init_backlight_funcs(dev);
13273
13274         mutex_init(&dev_priv->pps_mutex);
13275 }
13276
13277 /*
13278  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13279  * resume, or other times.  This quirk makes sure that's the case for
13280  * affected systems.
13281  */
13282 static void quirk_pipea_force(struct drm_device *dev)
13283 {
13284         struct drm_i915_private *dev_priv = dev->dev_private;
13285
13286         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13287         DRM_INFO("applying pipe a force quirk\n");
13288 }
13289
13290 static void quirk_pipeb_force(struct drm_device *dev)
13291 {
13292         struct drm_i915_private *dev_priv = dev->dev_private;
13293
13294         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13295         DRM_INFO("applying pipe b force quirk\n");
13296 }
13297
13298 /*
13299  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13300  */
13301 static void quirk_ssc_force_disable(struct drm_device *dev)
13302 {
13303         struct drm_i915_private *dev_priv = dev->dev_private;
13304         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13305         DRM_INFO("applying lvds SSC disable quirk\n");
13306 }
13307
13308 /*
13309  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13310  * brightness value
13311  */
13312 static void quirk_invert_brightness(struct drm_device *dev)
13313 {
13314         struct drm_i915_private *dev_priv = dev->dev_private;
13315         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13316         DRM_INFO("applying inverted panel brightness quirk\n");
13317 }
13318
13319 /* Some VBT's incorrectly indicate no backlight is present */
13320 static void quirk_backlight_present(struct drm_device *dev)
13321 {
13322         struct drm_i915_private *dev_priv = dev->dev_private;
13323         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13324         DRM_INFO("applying backlight present quirk\n");
13325 }
13326
13327 struct intel_quirk {
13328         int device;
13329         int subsystem_vendor;
13330         int subsystem_device;
13331         void (*hook)(struct drm_device *dev);
13332 };
13333
13334 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13335 struct intel_dmi_quirk {
13336         void (*hook)(struct drm_device *dev);
13337         const struct dmi_system_id (*dmi_id_list)[];
13338 };
13339
13340 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13341 {
13342         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13343         return 1;
13344 }
13345
13346 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13347         {
13348                 .dmi_id_list = &(const struct dmi_system_id[]) {
13349                         {
13350                                 .callback = intel_dmi_reverse_brightness,
13351                                 .ident = "NCR Corporation",
13352                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13353                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
13354                                 },
13355                         },
13356                         { }  /* terminating entry */
13357                 },
13358                 .hook = quirk_invert_brightness,
13359         },
13360 };
13361
13362 static struct intel_quirk intel_quirks[] = {
13363         /* HP Mini needs pipe A force quirk (LP: #322104) */
13364         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13365
13366         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13367         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13368
13369         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13370         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13371
13372         /* 830 needs to leave pipe A & dpll A up */
13373         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13374
13375         /* 830 needs to leave pipe B & dpll B up */
13376         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13377
13378         /* Lenovo U160 cannot use SSC on LVDS */
13379         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13380
13381         /* Sony Vaio Y cannot use SSC on LVDS */
13382         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13383
13384         /* Acer Aspire 5734Z must invert backlight brightness */
13385         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13386
13387         /* Acer/eMachines G725 */
13388         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13389
13390         /* Acer/eMachines e725 */
13391         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13392
13393         /* Acer/Packard Bell NCL20 */
13394         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13395
13396         /* Acer Aspire 4736Z */
13397         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13398
13399         /* Acer Aspire 5336 */
13400         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13401
13402         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13403         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13404
13405         /* Acer C720 Chromebook (Core i3 4005U) */
13406         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13407
13408         /* Apple Macbook 2,1 (Core 2 T7400) */
13409         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13410
13411         /* Toshiba CB35 Chromebook (Celeron 2955U) */
13412         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13413
13414         /* HP Chromebook 14 (Celeron 2955U) */
13415         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13416
13417         /* Dell Chromebook 11 */
13418         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13419 };
13420
13421 static void intel_init_quirks(struct drm_device *dev)
13422 {
13423         struct pci_dev *d = dev->pdev;
13424         int i;
13425
13426         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13427                 struct intel_quirk *q = &intel_quirks[i];
13428
13429                 if (d->device == q->device &&
13430                     (d->subsystem_vendor == q->subsystem_vendor ||
13431                      q->subsystem_vendor == PCI_ANY_ID) &&
13432                     (d->subsystem_device == q->subsystem_device ||
13433                      q->subsystem_device == PCI_ANY_ID))
13434                         q->hook(dev);
13435         }
13436         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13437                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13438                         intel_dmi_quirks[i].hook(dev);
13439         }
13440 }
13441
13442 /* Disable the VGA plane that we never use */
13443 static void i915_disable_vga(struct drm_device *dev)
13444 {
13445         struct drm_i915_private *dev_priv = dev->dev_private;
13446         u8 sr1;
13447         u32 vga_reg = i915_vgacntrl_reg(dev);
13448
13449         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13450         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13451         outb(SR01, VGA_SR_INDEX);
13452         sr1 = inb(VGA_SR_DATA);
13453         outb(sr1 | 1<<5, VGA_SR_DATA);
13454         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13455         udelay(300);
13456
13457         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13458         POSTING_READ(vga_reg);
13459 }
13460
13461 void intel_modeset_init_hw(struct drm_device *dev)
13462 {
13463         intel_prepare_ddi(dev);
13464
13465         if (IS_VALLEYVIEW(dev))
13466                 vlv_update_cdclk(dev);
13467
13468         intel_init_clock_gating(dev);
13469
13470         intel_enable_gt_powersave(dev);
13471 }
13472
13473 void intel_modeset_init(struct drm_device *dev)
13474 {
13475         struct drm_i915_private *dev_priv = dev->dev_private;
13476         int sprite, ret;
13477         enum pipe pipe;
13478         struct intel_crtc *crtc;
13479
13480         drm_mode_config_init(dev);
13481
13482         dev->mode_config.min_width = 0;
13483         dev->mode_config.min_height = 0;
13484
13485         dev->mode_config.preferred_depth = 24;
13486         dev->mode_config.prefer_shadow = 1;
13487
13488         dev->mode_config.allow_fb_modifiers = true;
13489
13490         dev->mode_config.funcs = &intel_mode_funcs;
13491
13492         intel_init_quirks(dev);
13493
13494         intel_init_pm(dev);
13495
13496         if (INTEL_INFO(dev)->num_pipes == 0)
13497                 return;
13498
13499         intel_init_display(dev);
13500         intel_init_audio(dev);
13501
13502         if (IS_GEN2(dev)) {
13503                 dev->mode_config.max_width = 2048;
13504                 dev->mode_config.max_height = 2048;
13505         } else if (IS_GEN3(dev)) {
13506                 dev->mode_config.max_width = 4096;
13507                 dev->mode_config.max_height = 4096;
13508         } else {
13509                 dev->mode_config.max_width = 8192;
13510                 dev->mode_config.max_height = 8192;
13511         }
13512
13513         if (IS_845G(dev) || IS_I865G(dev)) {
13514                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13515                 dev->mode_config.cursor_height = 1023;
13516         } else if (IS_GEN2(dev)) {
13517                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13518                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13519         } else {
13520                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13521                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13522         }
13523
13524         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13525
13526         DRM_DEBUG_KMS("%d display pipe%s available.\n",
13527                       INTEL_INFO(dev)->num_pipes,
13528                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13529
13530         for_each_pipe(dev_priv, pipe) {
13531                 intel_crtc_init(dev, pipe);
13532                 for_each_sprite(dev_priv, pipe, sprite) {
13533                         ret = intel_plane_init(dev, pipe, sprite);
13534                         if (ret)
13535                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13536                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13537                 }
13538         }
13539
13540         intel_init_dpio(dev);
13541
13542         intel_shared_dpll_init(dev);
13543
13544         /* Just disable it once at startup */
13545         i915_disable_vga(dev);
13546         intel_setup_outputs(dev);
13547
13548         /* Just in case the BIOS is doing something questionable. */
13549         intel_fbc_disable(dev);
13550
13551         drm_modeset_lock_all(dev);
13552         intel_modeset_setup_hw_state(dev, false);
13553         drm_modeset_unlock_all(dev);
13554
13555         for_each_intel_crtc(dev, crtc) {
13556                 if (!crtc->active)
13557                         continue;
13558
13559                 /*
13560                  * Note that reserving the BIOS fb up front prevents us
13561                  * from stuffing other stolen allocations like the ring
13562                  * on top.  This prevents some ugliness at boot time, and
13563                  * can even allow for smooth boot transitions if the BIOS
13564                  * fb is large enough for the active pipe configuration.
13565                  */
13566                 if (dev_priv->display.get_initial_plane_config) {
13567                         dev_priv->display.get_initial_plane_config(crtc,
13568                                                            &crtc->plane_config);
13569                         /*
13570                          * If the fb is shared between multiple heads, we'll
13571                          * just get the first one.
13572                          */
13573                         intel_find_initial_plane_obj(crtc, &crtc->plane_config);
13574                 }
13575         }
13576 }
13577
13578 static void intel_enable_pipe_a(struct drm_device *dev)
13579 {
13580         struct intel_connector *connector;
13581         struct drm_connector *crt = NULL;
13582         struct intel_load_detect_pipe load_detect_temp;
13583         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13584
13585         /* We can't just switch on the pipe A, we need to set things up with a
13586          * proper mode and output configuration. As a gross hack, enable pipe A
13587          * by enabling the load detect pipe once. */
13588         for_each_intel_connector(dev, connector) {
13589                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13590                         crt = &connector->base;
13591                         break;
13592                 }
13593         }
13594
13595         if (!crt)
13596                 return;
13597
13598         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13599                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
13600 }
13601
13602 static bool
13603 intel_check_plane_mapping(struct intel_crtc *crtc)
13604 {
13605         struct drm_device *dev = crtc->base.dev;
13606         struct drm_i915_private *dev_priv = dev->dev_private;
13607         u32 reg, val;
13608
13609         if (INTEL_INFO(dev)->num_pipes == 1)
13610                 return true;
13611
13612         reg = DSPCNTR(!crtc->plane);
13613         val = I915_READ(reg);
13614
13615         if ((val & DISPLAY_PLANE_ENABLE) &&
13616             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13617                 return false;
13618
13619         return true;
13620 }
13621
13622 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13623 {
13624         struct drm_device *dev = crtc->base.dev;
13625         struct drm_i915_private *dev_priv = dev->dev_private;
13626         u32 reg;
13627
13628         /* Clear any frame start delays used for debugging left by the BIOS */
13629         reg = PIPECONF(crtc->config->cpu_transcoder);
13630         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13631
13632         /* restore vblank interrupts to correct state */
13633         drm_crtc_vblank_reset(&crtc->base);
13634         if (crtc->active) {
13635                 update_scanline_offset(crtc);
13636                 drm_crtc_vblank_on(&crtc->base);
13637         }
13638
13639         /* We need to sanitize the plane -> pipe mapping first because this will
13640          * disable the crtc (and hence change the state) if it is wrong. Note
13641          * that gen4+ has a fixed plane -> pipe mapping.  */
13642         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13643                 struct intel_connector *connector;
13644                 bool plane;
13645
13646                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13647                               crtc->base.base.id);
13648
13649                 /* Pipe has the wrong plane attached and the plane is active.
13650                  * Temporarily change the plane mapping and disable everything
13651                  * ...  */
13652                 plane = crtc->plane;
13653                 crtc->plane = !plane;
13654                 crtc->primary_enabled = true;
13655                 dev_priv->display.crtc_disable(&crtc->base);
13656                 crtc->plane = plane;
13657
13658                 /* ... and break all links. */
13659                 for_each_intel_connector(dev, connector) {
13660                         if (connector->encoder->base.crtc != &crtc->base)
13661                                 continue;
13662
13663                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13664                         connector->base.encoder = NULL;
13665                 }
13666                 /* multiple connectors may have the same encoder:
13667                  *  handle them and break crtc link separately */
13668                 for_each_intel_connector(dev, connector)
13669                         if (connector->encoder->base.crtc == &crtc->base) {
13670                                 connector->encoder->base.crtc = NULL;
13671                                 connector->encoder->connectors_active = false;
13672                         }
13673
13674                 WARN_ON(crtc->active);
13675                 crtc->base.state->enable = false;
13676                 crtc->base.enabled = false;
13677         }
13678
13679         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13680             crtc->pipe == PIPE_A && !crtc->active) {
13681                 /* BIOS forgot to enable pipe A, this mostly happens after
13682                  * resume. Force-enable the pipe to fix this, the update_dpms
13683                  * call below we restore the pipe to the right state, but leave
13684                  * the required bits on. */
13685                 intel_enable_pipe_a(dev);
13686         }
13687
13688         /* Adjust the state of the output pipe according to whether we
13689          * have active connectors/encoders. */
13690         intel_crtc_update_dpms(&crtc->base);
13691
13692         if (crtc->active != crtc->base.state->enable) {
13693                 struct intel_encoder *encoder;
13694
13695                 /* This can happen either due to bugs in the get_hw_state
13696                  * functions or because the pipe is force-enabled due to the
13697                  * pipe A quirk. */
13698                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13699                               crtc->base.base.id,
13700                               crtc->base.state->enable ? "enabled" : "disabled",
13701                               crtc->active ? "enabled" : "disabled");
13702
13703                 crtc->base.state->enable = crtc->active;
13704                 crtc->base.enabled = crtc->active;
13705
13706                 /* Because we only establish the connector -> encoder ->
13707                  * crtc links if something is active, this means the
13708                  * crtc is now deactivated. Break the links. connector
13709                  * -> encoder links are only establish when things are
13710                  *  actually up, hence no need to break them. */
13711                 WARN_ON(crtc->active);
13712
13713                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13714                         WARN_ON(encoder->connectors_active);
13715                         encoder->base.crtc = NULL;
13716                 }
13717         }
13718
13719         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13720                 /*
13721                  * We start out with underrun reporting disabled to avoid races.
13722                  * For correct bookkeeping mark this on active crtcs.
13723                  *
13724                  * Also on gmch platforms we dont have any hardware bits to
13725                  * disable the underrun reporting. Which means we need to start
13726                  * out with underrun reporting disabled also on inactive pipes,
13727                  * since otherwise we'll complain about the garbage we read when
13728                  * e.g. coming up after runtime pm.
13729                  *
13730                  * No protection against concurrent access is required - at
13731                  * worst a fifo underrun happens which also sets this to false.
13732                  */
13733                 crtc->cpu_fifo_underrun_disabled = true;
13734                 crtc->pch_fifo_underrun_disabled = true;
13735         }
13736 }
13737
13738 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13739 {
13740         struct intel_connector *connector;
13741         struct drm_device *dev = encoder->base.dev;
13742
13743         /* We need to check both for a crtc link (meaning that the
13744          * encoder is active and trying to read from a pipe) and the
13745          * pipe itself being active. */
13746         bool has_active_crtc = encoder->base.crtc &&
13747                 to_intel_crtc(encoder->base.crtc)->active;
13748
13749         if (encoder->connectors_active && !has_active_crtc) {
13750                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13751                               encoder->base.base.id,
13752                               encoder->base.name);
13753
13754                 /* Connector is active, but has no active pipe. This is
13755                  * fallout from our resume register restoring. Disable
13756                  * the encoder manually again. */
13757                 if (encoder->base.crtc) {
13758                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13759                                       encoder->base.base.id,
13760                                       encoder->base.name);
13761                         encoder->disable(encoder);
13762                         if (encoder->post_disable)
13763                                 encoder->post_disable(encoder);
13764                 }
13765                 encoder->base.crtc = NULL;
13766                 encoder->connectors_active = false;
13767
13768                 /* Inconsistent output/port/pipe state happens presumably due to
13769                  * a bug in one of the get_hw_state functions. Or someplace else
13770                  * in our code, like the register restore mess on resume. Clamp
13771                  * things to off as a safer default. */
13772                 for_each_intel_connector(dev, connector) {
13773                         if (connector->encoder != encoder)
13774                                 continue;
13775                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13776                         connector->base.encoder = NULL;
13777                 }
13778         }
13779         /* Enabled encoders without active connectors will be fixed in
13780          * the crtc fixup. */
13781 }
13782
13783 void i915_redisable_vga_power_on(struct drm_device *dev)
13784 {
13785         struct drm_i915_private *dev_priv = dev->dev_private;
13786         u32 vga_reg = i915_vgacntrl_reg(dev);
13787
13788         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13789                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13790                 i915_disable_vga(dev);
13791         }
13792 }
13793
13794 void i915_redisable_vga(struct drm_device *dev)
13795 {
13796         struct drm_i915_private *dev_priv = dev->dev_private;
13797
13798         /* This function can be called both from intel_modeset_setup_hw_state or
13799          * at a very early point in our resume sequence, where the power well
13800          * structures are not yet restored. Since this function is at a very
13801          * paranoid "someone might have enabled VGA while we were not looking"
13802          * level, just check if the power well is enabled instead of trying to
13803          * follow the "don't touch the power well if we don't need it" policy
13804          * the rest of the driver uses. */
13805         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13806                 return;
13807
13808         i915_redisable_vga_power_on(dev);
13809 }
13810
13811 static bool primary_get_hw_state(struct intel_crtc *crtc)
13812 {
13813         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13814
13815         if (!crtc->active)
13816                 return false;
13817
13818         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13819 }
13820
13821 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13822 {
13823         struct drm_i915_private *dev_priv = dev->dev_private;
13824         enum pipe pipe;
13825         struct intel_crtc *crtc;
13826         struct intel_encoder *encoder;
13827         struct intel_connector *connector;
13828         int i;
13829
13830         for_each_intel_crtc(dev, crtc) {
13831                 memset(crtc->config, 0, sizeof(*crtc->config));
13832
13833                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13834
13835                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13836                                                                  crtc->config);
13837
13838                 crtc->base.state->enable = crtc->active;
13839                 crtc->base.enabled = crtc->active;
13840                 crtc->primary_enabled = primary_get_hw_state(crtc);
13841
13842                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13843                               crtc->base.base.id,
13844                               crtc->active ? "enabled" : "disabled");
13845         }
13846
13847         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13848                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13849
13850                 pll->on = pll->get_hw_state(dev_priv, pll,
13851                                             &pll->config.hw_state);
13852                 pll->active = 0;
13853                 pll->config.crtc_mask = 0;
13854                 for_each_intel_crtc(dev, crtc) {
13855                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13856                                 pll->active++;
13857                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13858                         }
13859                 }
13860
13861                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13862                               pll->name, pll->config.crtc_mask, pll->on);
13863
13864                 if (pll->config.crtc_mask)
13865                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13866         }
13867
13868         for_each_intel_encoder(dev, encoder) {
13869                 pipe = 0;
13870
13871                 if (encoder->get_hw_state(encoder, &pipe)) {
13872                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13873                         encoder->base.crtc = &crtc->base;
13874                         encoder->get_config(encoder, crtc->config);
13875                 } else {
13876                         encoder->base.crtc = NULL;
13877                 }
13878
13879                 encoder->connectors_active = false;
13880                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13881                               encoder->base.base.id,
13882                               encoder->base.name,
13883                               encoder->base.crtc ? "enabled" : "disabled",
13884                               pipe_name(pipe));
13885         }
13886
13887         for_each_intel_connector(dev, connector) {
13888                 if (connector->get_hw_state(connector)) {
13889                         connector->base.dpms = DRM_MODE_DPMS_ON;
13890                         connector->encoder->connectors_active = true;
13891                         connector->base.encoder = &connector->encoder->base;
13892                 } else {
13893                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13894                         connector->base.encoder = NULL;
13895                 }
13896                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13897                               connector->base.base.id,
13898                               connector->base.name,
13899                               connector->base.encoder ? "enabled" : "disabled");
13900         }
13901 }
13902
13903 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13904  * and i915 state tracking structures. */
13905 void intel_modeset_setup_hw_state(struct drm_device *dev,
13906                                   bool force_restore)
13907 {
13908         struct drm_i915_private *dev_priv = dev->dev_private;
13909         enum pipe pipe;
13910         struct intel_crtc *crtc;
13911         struct intel_encoder *encoder;
13912         int i;
13913
13914         intel_modeset_readout_hw_state(dev);
13915
13916         /*
13917          * Now that we have the config, copy it to each CRTC struct
13918          * Note that this could go away if we move to using crtc_config
13919          * checking everywhere.
13920          */
13921         for_each_intel_crtc(dev, crtc) {
13922                 if (crtc->active && i915.fastboot) {
13923                         intel_mode_from_pipe_config(&crtc->base.mode,
13924                                                     crtc->config);
13925                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13926                                       crtc->base.base.id);
13927                         drm_mode_debug_printmodeline(&crtc->base.mode);
13928                 }
13929         }
13930
13931         /* HW state is read out, now we need to sanitize this mess. */
13932         for_each_intel_encoder(dev, encoder) {
13933                 intel_sanitize_encoder(encoder);
13934         }
13935
13936         for_each_pipe(dev_priv, pipe) {
13937                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13938                 intel_sanitize_crtc(crtc);
13939                 intel_dump_pipe_config(crtc, crtc->config,
13940                                        "[setup_hw_state]");
13941         }
13942
13943         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13944                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13945
13946                 if (!pll->on || pll->active)
13947                         continue;
13948
13949                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13950
13951                 pll->disable(dev_priv, pll);
13952                 pll->on = false;
13953         }
13954
13955         if (IS_GEN9(dev))
13956                 skl_wm_get_hw_state(dev);
13957         else if (HAS_PCH_SPLIT(dev))
13958                 ilk_wm_get_hw_state(dev);
13959
13960         if (force_restore) {
13961                 i915_redisable_vga(dev);
13962
13963                 /*
13964                  * We need to use raw interfaces for restoring state to avoid
13965                  * checking (bogus) intermediate states.
13966                  */
13967                 for_each_pipe(dev_priv, pipe) {
13968                         struct drm_crtc *crtc =
13969                                 dev_priv->pipe_to_crtc_mapping[pipe];
13970
13971                         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13972                                        crtc->primary->fb);
13973                 }
13974         } else {
13975                 intel_modeset_update_staged_output_state(dev);
13976         }
13977
13978         intel_modeset_check_state(dev);
13979 }
13980
13981 void intel_modeset_gem_init(struct drm_device *dev)
13982 {
13983         struct drm_i915_private *dev_priv = dev->dev_private;
13984         struct drm_crtc *c;
13985         struct drm_i915_gem_object *obj;
13986
13987         mutex_lock(&dev->struct_mutex);
13988         intel_init_gt_powersave(dev);
13989         mutex_unlock(&dev->struct_mutex);
13990
13991         /*
13992          * There may be no VBT; and if the BIOS enabled SSC we can
13993          * just keep using it to avoid unnecessary flicker.  Whereas if the
13994          * BIOS isn't using it, don't assume it will work even if the VBT
13995          * indicates as much.
13996          */
13997         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13998                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13999                                                 DREF_SSC1_ENABLE);
14000
14001         intel_modeset_init_hw(dev);
14002
14003         intel_setup_overlay(dev);
14004
14005         /*
14006          * Make sure any fbs we allocated at startup are properly
14007          * pinned & fenced.  When we do the allocation it's too early
14008          * for this.
14009          */
14010         mutex_lock(&dev->struct_mutex);
14011         for_each_crtc(dev, c) {
14012                 obj = intel_fb_obj(c->primary->fb);
14013                 if (obj == NULL)
14014                         continue;
14015
14016                 if (intel_pin_and_fence_fb_obj(c->primary,
14017                                                c->primary->fb,
14018                                                c->primary->state,
14019                                                NULL)) {
14020                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
14021                                   to_intel_crtc(c)->pipe);
14022                         drm_framebuffer_unreference(c->primary->fb);
14023                         c->primary->fb = NULL;
14024                         update_state_fb(c->primary);
14025                 }
14026         }
14027         mutex_unlock(&dev->struct_mutex);
14028
14029         intel_backlight_register(dev);
14030 }
14031
14032 void intel_connector_unregister(struct intel_connector *intel_connector)
14033 {
14034         struct drm_connector *connector = &intel_connector->base;
14035
14036         intel_panel_destroy_backlight(connector);
14037         drm_connector_unregister(connector);
14038 }
14039
14040 void intel_modeset_cleanup(struct drm_device *dev)
14041 {
14042         struct drm_i915_private *dev_priv = dev->dev_private;
14043         struct drm_connector *connector;
14044
14045         intel_disable_gt_powersave(dev);
14046
14047         intel_backlight_unregister(dev);
14048
14049         /*
14050          * Interrupts and polling as the first thing to avoid creating havoc.
14051          * Too much stuff here (turning of connectors, ...) would
14052          * experience fancy races otherwise.
14053          */
14054         intel_irq_uninstall(dev_priv);
14055
14056         /*
14057          * Due to the hpd irq storm handling the hotplug work can re-arm the
14058          * poll handlers. Hence disable polling after hpd handling is shut down.
14059          */
14060         drm_kms_helper_poll_fini(dev);
14061
14062         mutex_lock(&dev->struct_mutex);
14063
14064         intel_unregister_dsm_handler();
14065
14066         intel_fbc_disable(dev);
14067
14068         mutex_unlock(&dev->struct_mutex);
14069
14070         /* flush any delayed tasks or pending work */
14071         flush_scheduled_work();
14072
14073         /* destroy the backlight and sysfs files before encoders/connectors */
14074         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
14075                 struct intel_connector *intel_connector;
14076
14077                 intel_connector = to_intel_connector(connector);
14078                 intel_connector->unregister(intel_connector);
14079         }
14080
14081         drm_mode_config_cleanup(dev);
14082
14083         intel_cleanup_overlay(dev);
14084
14085         mutex_lock(&dev->struct_mutex);
14086         intel_cleanup_gt_powersave(dev);
14087         mutex_unlock(&dev->struct_mutex);
14088 }
14089
14090 /*
14091  * Return which encoder is currently attached for connector.
14092  */
14093 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14094 {
14095         return &intel_attached_encoder(connector)->base;
14096 }
14097
14098 void intel_connector_attach_encoder(struct intel_connector *connector,
14099                                     struct intel_encoder *encoder)
14100 {
14101         connector->encoder = encoder;
14102         drm_mode_connector_attach_encoder(&connector->base,
14103                                           &encoder->base);
14104 }
14105
14106 /*
14107  * set vga decode state - true == enable VGA decode
14108  */
14109 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14110 {
14111         struct drm_i915_private *dev_priv = dev->dev_private;
14112         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14113         u16 gmch_ctrl;
14114
14115         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14116                 DRM_ERROR("failed to read control word\n");
14117                 return -EIO;
14118         }
14119
14120         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14121                 return 0;
14122
14123         if (state)
14124                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14125         else
14126                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14127
14128         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14129                 DRM_ERROR("failed to write control word\n");
14130                 return -EIO;
14131         }
14132
14133         return 0;
14134 }
14135
14136 struct intel_display_error_state {
14137
14138         u32 power_well_driver;
14139
14140         int num_transcoders;
14141
14142         struct intel_cursor_error_state {
14143                 u32 control;
14144                 u32 position;
14145                 u32 base;
14146                 u32 size;
14147         } cursor[I915_MAX_PIPES];
14148
14149         struct intel_pipe_error_state {
14150                 bool power_domain_on;
14151                 u32 source;
14152                 u32 stat;
14153         } pipe[I915_MAX_PIPES];
14154
14155         struct intel_plane_error_state {
14156                 u32 control;
14157                 u32 stride;
14158                 u32 size;
14159                 u32 pos;
14160                 u32 addr;
14161                 u32 surface;
14162                 u32 tile_offset;
14163         } plane[I915_MAX_PIPES];
14164
14165         struct intel_transcoder_error_state {
14166                 bool power_domain_on;
14167                 enum transcoder cpu_transcoder;
14168
14169                 u32 conf;
14170
14171                 u32 htotal;
14172                 u32 hblank;
14173                 u32 hsync;
14174                 u32 vtotal;
14175                 u32 vblank;
14176                 u32 vsync;
14177         } transcoder[4];
14178 };
14179
14180 struct intel_display_error_state *
14181 intel_display_capture_error_state(struct drm_device *dev)
14182 {
14183         struct drm_i915_private *dev_priv = dev->dev_private;
14184         struct intel_display_error_state *error;
14185         int transcoders[] = {
14186                 TRANSCODER_A,
14187                 TRANSCODER_B,
14188                 TRANSCODER_C,
14189                 TRANSCODER_EDP,
14190         };
14191         int i;
14192
14193         if (INTEL_INFO(dev)->num_pipes == 0)
14194                 return NULL;
14195
14196         error = kzalloc(sizeof(*error), GFP_ATOMIC);
14197         if (error == NULL)
14198                 return NULL;
14199
14200         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14201                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14202
14203         for_each_pipe(dev_priv, i) {
14204                 error->pipe[i].power_domain_on =
14205                         __intel_display_power_is_enabled(dev_priv,
14206                                                          POWER_DOMAIN_PIPE(i));
14207                 if (!error->pipe[i].power_domain_on)
14208                         continue;
14209
14210                 error->cursor[i].control = I915_READ(CURCNTR(i));
14211                 error->cursor[i].position = I915_READ(CURPOS(i));
14212                 error->cursor[i].base = I915_READ(CURBASE(i));
14213
14214                 error->plane[i].control = I915_READ(DSPCNTR(i));
14215                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14216                 if (INTEL_INFO(dev)->gen <= 3) {
14217                         error->plane[i].size = I915_READ(DSPSIZE(i));
14218                         error->plane[i].pos = I915_READ(DSPPOS(i));
14219                 }
14220                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14221                         error->plane[i].addr = I915_READ(DSPADDR(i));
14222                 if (INTEL_INFO(dev)->gen >= 4) {
14223                         error->plane[i].surface = I915_READ(DSPSURF(i));
14224                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14225                 }
14226
14227                 error->pipe[i].source = I915_READ(PIPESRC(i));
14228
14229                 if (HAS_GMCH_DISPLAY(dev))
14230                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
14231         }
14232
14233         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14234         if (HAS_DDI(dev_priv->dev))
14235                 error->num_transcoders++; /* Account for eDP. */
14236
14237         for (i = 0; i < error->num_transcoders; i++) {
14238                 enum transcoder cpu_transcoder = transcoders[i];
14239
14240                 error->transcoder[i].power_domain_on =
14241                         __intel_display_power_is_enabled(dev_priv,
14242                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14243                 if (!error->transcoder[i].power_domain_on)
14244                         continue;
14245
14246                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14247
14248                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14249                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14250                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14251                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14252                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14253                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14254                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14255         }
14256
14257         return error;
14258 }
14259
14260 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14261
14262 void
14263 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14264                                 struct drm_device *dev,
14265                                 struct intel_display_error_state *error)
14266 {
14267         struct drm_i915_private *dev_priv = dev->dev_private;
14268         int i;
14269
14270         if (!error)
14271                 return;
14272
14273         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14274         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14275                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14276                            error->power_well_driver);
14277         for_each_pipe(dev_priv, i) {
14278                 err_printf(m, "Pipe [%d]:\n", i);
14279                 err_printf(m, "  Power: %s\n",
14280                            error->pipe[i].power_domain_on ? "on" : "off");
14281                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
14282                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
14283
14284                 err_printf(m, "Plane [%d]:\n", i);
14285                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
14286                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
14287                 if (INTEL_INFO(dev)->gen <= 3) {
14288                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
14289                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
14290                 }
14291                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14292                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
14293                 if (INTEL_INFO(dev)->gen >= 4) {
14294                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
14295                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
14296                 }
14297
14298                 err_printf(m, "Cursor [%d]:\n", i);
14299                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
14300                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
14301                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
14302         }
14303
14304         for (i = 0; i < error->num_transcoders; i++) {
14305                 err_printf(m, "CPU transcoder: %c\n",
14306                            transcoder_name(error->transcoder[i].cpu_transcoder));
14307                 err_printf(m, "  Power: %s\n",
14308                            error->transcoder[i].power_domain_on ? "on" : "off");
14309                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
14310                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
14311                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
14312                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
14313                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
14314                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
14315                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
14316         }
14317 }
14318
14319 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14320 {
14321         struct intel_crtc *crtc;
14322
14323         for_each_intel_crtc(dev, crtc) {
14324                 struct intel_unpin_work *work;
14325
14326                 spin_lock_irq(&dev->event_lock);
14327
14328                 work = crtc->unpin_work;
14329
14330                 if (work && work->event &&
14331                     work->event->base.file_priv == file) {
14332                         kfree(work->event);
14333                         work->event = NULL;
14334                 }
14335
14336                 spin_unlock_irq(&dev->event_lock);
14337         }
14338 }