2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
66 static const uint32_t skl_primary_formats[] = {
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
78 static const uint32_t intel_cursor_formats[] = {
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
89 static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
101 static void vlv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void chv_prepare_pll(struct intel_crtc *crtc,
104 const struct intel_crtc_state *pipe_config);
105 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
106 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 int p2_slow, p2_fast;
122 typedef struct intel_limit intel_limit_t;
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
129 intel_pch_rawclk(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
133 WARN_ON(!HAS_PCH_SPLIT(dev));
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
369 static const intel_limit_t intel_limits_vlv = {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv = {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401 static const intel_limit_t intel_limits_bxt = {
402 /* FIXME: find real dot limits */
403 .dot = { .min = 0, .max = INT_MAX },
404 .vco = { .min = 4800000, .max = 6700000 },
405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 /* FIXME: find real m2 limits */
408 .m2 = { .min = 2 << 22, .max = 255 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 20 },
414 needs_modeset(struct drm_crtc_state *state)
416 return drm_atomic_crtc_needs_modeset(state);
420 * Returns whether any output on the specified pipe is of the specified type
422 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
424 struct drm_device *dev = crtc->base.dev;
425 struct intel_encoder *encoder;
427 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
428 if (encoder->type == type)
435 * Returns whether any output on the specified pipe will have the specified
436 * type after a staged modeset is complete, i.e., the same as
437 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
440 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
443 struct drm_atomic_state *state = crtc_state->base.state;
444 struct drm_connector *connector;
445 struct drm_connector_state *connector_state;
446 struct intel_encoder *encoder;
447 int i, num_connectors = 0;
449 for_each_connector_in_state(state, connector, connector_state, i) {
450 if (connector_state->crtc != crtc_state->base.crtc)
455 encoder = to_intel_encoder(connector_state->best_encoder);
456 if (encoder->type == type)
460 WARN_ON(num_connectors == 0);
465 static const intel_limit_t *
466 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
468 struct drm_device *dev = crtc_state->base.crtc->dev;
469 const intel_limit_t *limit;
471 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
472 if (intel_is_dual_link_lvds(dev)) {
473 if (refclk == 100000)
474 limit = &intel_limits_ironlake_dual_lvds_100m;
476 limit = &intel_limits_ironlake_dual_lvds;
478 if (refclk == 100000)
479 limit = &intel_limits_ironlake_single_lvds_100m;
481 limit = &intel_limits_ironlake_single_lvds;
484 limit = &intel_limits_ironlake_dac;
489 static const intel_limit_t *
490 intel_g4x_limit(struct intel_crtc_state *crtc_state)
492 struct drm_device *dev = crtc_state->base.crtc->dev;
493 const intel_limit_t *limit;
495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
496 if (intel_is_dual_link_lvds(dev))
497 limit = &intel_limits_g4x_dual_channel_lvds;
499 limit = &intel_limits_g4x_single_channel_lvds;
500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
502 limit = &intel_limits_g4x_hdmi;
503 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
504 limit = &intel_limits_g4x_sdvo;
505 } else /* The option is for other outputs */
506 limit = &intel_limits_i9xx_sdvo;
511 static const intel_limit_t *
512 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
514 struct drm_device *dev = crtc_state->base.crtc->dev;
515 const intel_limit_t *limit;
518 limit = &intel_limits_bxt;
519 else if (HAS_PCH_SPLIT(dev))
520 limit = intel_ironlake_limit(crtc_state, refclk);
521 else if (IS_G4X(dev)) {
522 limit = intel_g4x_limit(crtc_state);
523 } else if (IS_PINEVIEW(dev)) {
524 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
525 limit = &intel_limits_pineview_lvds;
527 limit = &intel_limits_pineview_sdvo;
528 } else if (IS_CHERRYVIEW(dev)) {
529 limit = &intel_limits_chv;
530 } else if (IS_VALLEYVIEW(dev)) {
531 limit = &intel_limits_vlv;
532 } else if (!IS_GEN2(dev)) {
533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
534 limit = &intel_limits_i9xx_lvds;
536 limit = &intel_limits_i9xx_sdvo;
538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
539 limit = &intel_limits_i8xx_lvds;
540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
541 limit = &intel_limits_i8xx_dvo;
543 limit = &intel_limits_i8xx_dac;
549 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
550 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
551 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
552 * The helpers' return value is the rate of the clock that is fed to the
553 * display engine's pipe which can be the above fast dot clock rate or a
554 * divided-down version of it.
556 /* m1 is reserved as 0 in Pineview, n is a ring counter */
557 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
559 clock->m = clock->m2 + 2;
560 clock->p = clock->p1 * clock->p2;
561 if (WARN_ON(clock->n == 0 || clock->p == 0))
563 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
564 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
569 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
574 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
576 clock->m = i9xx_dpll_compute_m(clock);
577 clock->p = clock->p1 * clock->p2;
578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
586 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
592 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
595 return clock->dot / 5;
598 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
600 clock->m = clock->m1 * clock->m2;
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n == 0 || clock->p == 0))
604 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
608 return clock->dot / 5;
611 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
613 * Returns whether the given set of divisors are valid for a given refclk with
614 * the given connectors.
617 static bool intel_PLL_is_valid(struct drm_device *dev,
618 const intel_limit_t *limit,
619 const intel_clock_t *clock)
621 if (clock->n < limit->n.min || limit->n.max < clock->n)
622 INTELPllInvalid("n out of range\n");
623 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
624 INTELPllInvalid("p1 out of range\n");
625 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
626 INTELPllInvalid("m2 out of range\n");
627 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
628 INTELPllInvalid("m1 out of range\n");
630 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
631 if (clock->m1 <= clock->m2)
632 INTELPllInvalid("m1 <= m2\n");
634 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
635 if (clock->p < limit->p.min || limit->p.max < clock->p)
636 INTELPllInvalid("p out of range\n");
637 if (clock->m < limit->m.min || limit->m.max < clock->m)
638 INTELPllInvalid("m out of range\n");
641 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
642 INTELPllInvalid("vco out of range\n");
643 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
644 * connector, etc., rather than just a single range.
646 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
647 INTELPllInvalid("dot out of range\n");
653 i9xx_select_p2_div(const intel_limit_t *limit,
654 const struct intel_crtc_state *crtc_state,
657 struct drm_device *dev = crtc_state->base.crtc->dev;
659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
661 * For LVDS just rely on its current settings for dual-channel.
662 * We haven't figured out how to reliably set up different
663 * single/dual channel state, if we even can.
665 if (intel_is_dual_link_lvds(dev))
666 return limit->p2.p2_fast;
668 return limit->p2.p2_slow;
670 if (target < limit->p2.dot_limit)
671 return limit->p2.p2_slow;
673 return limit->p2.p2_fast;
678 i9xx_find_best_dpll(const intel_limit_t *limit,
679 struct intel_crtc_state *crtc_state,
680 int target, int refclk, intel_clock_t *match_clock,
681 intel_clock_t *best_clock)
683 struct drm_device *dev = crtc_state->base.crtc->dev;
687 memset(best_clock, 0, sizeof(*best_clock));
689 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 if (clock.m2 >= clock.m1)
697 for (clock.n = limit->n.min;
698 clock.n <= limit->n.max; clock.n++) {
699 for (clock.p1 = limit->p1.min;
700 clock.p1 <= limit->p1.max; clock.p1++) {
703 i9xx_calc_dpll_params(refclk, &clock);
704 if (!intel_PLL_is_valid(dev, limit,
708 clock.p != match_clock->p)
711 this_err = abs(clock.dot - target);
712 if (this_err < err) {
721 return (err != target);
725 pnv_find_best_dpll(const intel_limit_t *limit,
726 struct intel_crtc_state *crtc_state,
727 int target, int refclk, intel_clock_t *match_clock,
728 intel_clock_t *best_clock)
730 struct drm_device *dev = crtc_state->base.crtc->dev;
734 memset(best_clock, 0, sizeof(*best_clock));
736 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
740 for (clock.m2 = limit->m2.min;
741 clock.m2 <= limit->m2.max; clock.m2++) {
742 for (clock.n = limit->n.min;
743 clock.n <= limit->n.max; clock.n++) {
744 for (clock.p1 = limit->p1.min;
745 clock.p1 <= limit->p1.max; clock.p1++) {
748 pnv_calc_dpll_params(refclk, &clock);
749 if (!intel_PLL_is_valid(dev, limit,
753 clock.p != match_clock->p)
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
766 return (err != target);
770 g4x_find_best_dpll(const intel_limit_t *limit,
771 struct intel_crtc_state *crtc_state,
772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
775 struct drm_device *dev = crtc_state->base.crtc->dev;
779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
782 memset(best_clock, 0, sizeof(*best_clock));
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
786 max_n = limit->n.max;
787 /* based on hardware requirement, prefer smaller n to precision */
788 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
789 /* based on hardware requirement, prefere larger m1,m2 */
790 for (clock.m1 = limit->m1.max;
791 clock.m1 >= limit->m1.min; clock.m1--) {
792 for (clock.m2 = limit->m2.max;
793 clock.m2 >= limit->m2.min; clock.m2--) {
794 for (clock.p1 = limit->p1.max;
795 clock.p1 >= limit->p1.min; clock.p1--) {
798 i9xx_calc_dpll_params(refclk, &clock);
799 if (!intel_PLL_is_valid(dev, limit,
803 this_err = abs(clock.dot - target);
804 if (this_err < err_most) {
818 * Check if the calculated PLL configuration is more optimal compared to the
819 * best configuration and error found so far. Return the calculated error.
821 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
822 const intel_clock_t *calculated_clock,
823 const intel_clock_t *best_clock,
824 unsigned int best_error_ppm,
825 unsigned int *error_ppm)
828 * For CHV ignore the error and consider only the P value.
829 * Prefer a bigger P value based on HW requirements.
831 if (IS_CHERRYVIEW(dev)) {
834 return calculated_clock->p > best_clock->p;
837 if (WARN_ON_ONCE(!target_freq))
840 *error_ppm = div_u64(1000000ULL *
841 abs(target_freq - calculated_clock->dot),
844 * Prefer a better P value over a better (smaller) error if the error
845 * is small. Ensure this preference for future configurations too by
846 * setting the error to 0.
848 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
854 return *error_ppm + 10 < best_error_ppm;
858 vlv_find_best_dpll(const intel_limit_t *limit,
859 struct intel_crtc_state *crtc_state,
860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
864 struct drm_device *dev = crtc->base.dev;
866 unsigned int bestppm = 1000000;
867 /* min update 19.2 MHz */
868 int max_n = min(limit->n.max, refclk / 19200);
871 target *= 5; /* fast clock */
873 memset(best_clock, 0, sizeof(*best_clock));
875 /* based on hardware requirement, prefer smaller n to precision */
876 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
877 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
878 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
879 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
880 clock.p = clock.p1 * clock.p2;
881 /* based on hardware requirement, prefer bigger m1,m2 values */
882 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
885 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
888 vlv_calc_dpll_params(refclk, &clock);
890 if (!intel_PLL_is_valid(dev, limit,
894 if (!vlv_PLL_is_optimal(dev, target,
912 chv_find_best_dpll(const intel_limit_t *limit,
913 struct intel_crtc_state *crtc_state,
914 int target, int refclk, intel_clock_t *match_clock,
915 intel_clock_t *best_clock)
917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
918 struct drm_device *dev = crtc->base.dev;
919 unsigned int best_error_ppm;
924 memset(best_clock, 0, sizeof(*best_clock));
925 best_error_ppm = 1000000;
928 * Based on hardware doc, the n always set to 1, and m1 always
929 * set to 2. If requires to support 200Mhz refclk, we need to
930 * revisit this because n may not 1 anymore.
932 clock.n = 1, clock.m1 = 2;
933 target *= 5; /* fast clock */
935 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
936 for (clock.p2 = limit->p2.p2_fast;
937 clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 unsigned int error_ppm;
941 clock.p = clock.p1 * clock.p2;
943 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
944 clock.n) << 22, refclk * clock.m1);
946 if (m2 > INT_MAX/clock.m1)
951 chv_calc_dpll_params(refclk, &clock);
953 if (!intel_PLL_is_valid(dev, limit, &clock))
956 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
957 best_error_ppm, &error_ppm))
961 best_error_ppm = error_ppm;
969 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
970 intel_clock_t *best_clock)
972 int refclk = i9xx_get_refclk(crtc_state, 0);
974 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
975 target_clock, refclk, NULL, best_clock);
978 bool intel_crtc_active(struct drm_crtc *crtc)
980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
982 /* Be paranoid as we can arrive here with only partial
983 * state retrieved from the hardware during setup.
985 * We can ditch the adjusted_mode.crtc_clock check as soon
986 * as Haswell has gained clock readout/fastboot support.
988 * We can ditch the crtc->primary->fb check as soon as we can
989 * properly reconstruct framebuffers.
991 * FIXME: The intel_crtc->active here should be switched to
992 * crtc->state->active once we have proper CRTC states wired up
995 return intel_crtc->active && crtc->primary->state->fb &&
996 intel_crtc->config->base.adjusted_mode.crtc_clock;
999 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1005 return intel_crtc->config->cpu_transcoder;
1008 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 reg = PIPEDSL(pipe);
1016 line_mask = DSL_LINEMASK_GEN2;
1018 line_mask = DSL_LINEMASK_GEN3;
1020 line1 = I915_READ(reg) & line_mask;
1022 line2 = I915_READ(reg) & line_mask;
1024 return line1 == line2;
1028 * intel_wait_for_pipe_off - wait for pipe to turn off
1029 * @crtc: crtc whose pipe to wait for
1031 * After disabling a pipe, we can't wait for vblank in the usual way,
1032 * spinning on the vblank interrupt status bit, since we won't actually
1033 * see an interrupt when the pipe is disabled.
1035 * On Gen4 and above:
1036 * wait for the pipe register state bit to turn off
1039 * wait for the display line value to settle (it usually
1040 * ends up stopping at the start of the next frame).
1043 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1045 struct drm_device *dev = crtc->base.dev;
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048 enum pipe pipe = crtc->pipe;
1050 if (INTEL_INFO(dev)->gen >= 4) {
1051 int reg = PIPECONF(cpu_transcoder);
1053 /* Wait for the Pipe State to go off */
1054 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1056 WARN(1, "pipe_off wait timed out\n");
1058 /* Wait for the display line to settle */
1059 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060 WARN(1, "pipe_off wait timed out\n");
1065 * ibx_digital_port_connected - is the specified port connected?
1066 * @dev_priv: i915 private structure
1067 * @port: the port to test
1069 * Returns true if @port is connected, false otherwise.
1071 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072 struct intel_digital_port *port)
1076 if (HAS_PCH_IBX(dev_priv->dev)) {
1077 switch (port->port) {
1079 bit = SDE_PORTB_HOTPLUG;
1082 bit = SDE_PORTC_HOTPLUG;
1085 bit = SDE_PORTD_HOTPLUG;
1091 switch (port->port) {
1093 bit = SDE_PORTB_HOTPLUG_CPT;
1096 bit = SDE_PORTC_HOTPLUG_CPT;
1099 bit = SDE_PORTD_HOTPLUG_CPT;
1106 return I915_READ(SDEISR) & bit;
1109 static const char *state_string(bool enabled)
1111 return enabled ? "on" : "off";
1114 /* Only for pre-ILK configs */
1115 void assert_pll(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1123 val = I915_READ(reg);
1124 cur_state = !!(val & DPLL_VCO_ENABLE);
1125 I915_STATE_WARN(cur_state != state,
1126 "PLL state assertion failure (expected %s, current %s)\n",
1127 state_string(state), state_string(cur_state));
1130 /* XXX: the dsi pll is shared between MIPI DSI ports */
1131 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1136 mutex_lock(&dev_priv->sb_lock);
1137 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1138 mutex_unlock(&dev_priv->sb_lock);
1140 cur_state = val & DSI_PLL_VCO_EN;
1141 I915_STATE_WARN(cur_state != state,
1142 "DSI PLL state assertion failure (expected %s, current %s)\n",
1143 state_string(state), state_string(cur_state));
1145 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1146 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1148 struct intel_shared_dpll *
1149 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1151 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1153 if (crtc->config->shared_dpll < 0)
1156 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1160 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1161 struct intel_shared_dpll *pll,
1165 struct intel_dpll_hw_state hw_state;
1168 "asserting DPLL %s with no DPLL\n", state_string(state)))
1171 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1172 I915_STATE_WARN(cur_state != state,
1173 "%s assertion failure (expected %s, current %s)\n",
1174 pll->name, state_string(state), state_string(cur_state));
1177 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1183 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1186 if (HAS_DDI(dev_priv->dev)) {
1187 /* DDI does not have a specific FDI_TX register */
1188 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1189 val = I915_READ(reg);
1190 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1192 reg = FDI_TX_CTL(pipe);
1193 val = I915_READ(reg);
1194 cur_state = !!(val & FDI_TX_ENABLE);
1196 I915_STATE_WARN(cur_state != state,
1197 "FDI TX state assertion failure (expected %s, current %s)\n",
1198 state_string(state), state_string(cur_state));
1200 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1201 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1203 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
1210 reg = FDI_RX_CTL(pipe);
1211 val = I915_READ(reg);
1212 cur_state = !!(val & FDI_RX_ENABLE);
1213 I915_STATE_WARN(cur_state != state,
1214 "FDI RX state assertion failure (expected %s, current %s)\n",
1215 state_string(state), state_string(cur_state));
1217 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1218 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1220 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1226 /* ILK FDI PLL is always enabled */
1227 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1230 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1231 if (HAS_DDI(dev_priv->dev))
1234 reg = FDI_TX_CTL(pipe);
1235 val = I915_READ(reg);
1236 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1239 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1246 reg = FDI_RX_CTL(pipe);
1247 val = I915_READ(reg);
1248 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1249 I915_STATE_WARN(cur_state != state,
1250 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1251 state_string(state), state_string(cur_state));
1254 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1257 struct drm_device *dev = dev_priv->dev;
1260 enum pipe panel_pipe = PIPE_A;
1263 if (WARN_ON(HAS_DDI(dev)))
1266 if (HAS_PCH_SPLIT(dev)) {
1269 pp_reg = PCH_PP_CONTROL;
1270 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1272 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1273 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1274 panel_pipe = PIPE_B;
1275 /* XXX: else fix for eDP */
1276 } else if (IS_VALLEYVIEW(dev)) {
1277 /* presumably write lock depends on pipe, not port select */
1278 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1281 pp_reg = PP_CONTROL;
1282 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1283 panel_pipe = PIPE_B;
1286 val = I915_READ(pp_reg);
1287 if (!(val & PANEL_POWER_ON) ||
1288 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1291 I915_STATE_WARN(panel_pipe == pipe && locked,
1292 "panel assertion failure, pipe %c regs locked\n",
1296 static void assert_cursor(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, bool state)
1299 struct drm_device *dev = dev_priv->dev;
1302 if (IS_845G(dev) || IS_I865G(dev))
1303 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1305 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1307 I915_STATE_WARN(cur_state != state,
1308 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1309 pipe_name(pipe), state_string(state), state_string(cur_state));
1311 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1312 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1314 void assert_pipe(struct drm_i915_private *dev_priv,
1315 enum pipe pipe, bool state)
1320 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1323 /* if we need the pipe quirk it must be always on */
1324 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1325 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1328 if (!intel_display_power_is_enabled(dev_priv,
1329 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1332 reg = PIPECONF(cpu_transcoder);
1333 val = I915_READ(reg);
1334 cur_state = !!(val & PIPECONF_ENABLE);
1337 I915_STATE_WARN(cur_state != state,
1338 "pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1342 static void assert_plane(struct drm_i915_private *dev_priv,
1343 enum plane plane, bool state)
1349 reg = DSPCNTR(plane);
1350 val = I915_READ(reg);
1351 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1352 I915_STATE_WARN(cur_state != state,
1353 "plane %c assertion failure (expected %s, current %s)\n",
1354 plane_name(plane), state_string(state), state_string(cur_state));
1357 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1358 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1360 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1363 struct drm_device *dev = dev_priv->dev;
1368 /* Primary planes are fixed to pipes on gen4+ */
1369 if (INTEL_INFO(dev)->gen >= 4) {
1370 reg = DSPCNTR(pipe);
1371 val = I915_READ(reg);
1372 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1373 "plane %c assertion failure, should be disabled but not\n",
1378 /* Need to check both planes against the pipe */
1379 for_each_pipe(dev_priv, i) {
1381 val = I915_READ(reg);
1382 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1383 DISPPLANE_SEL_PIPE_SHIFT;
1384 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1385 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1386 plane_name(i), pipe_name(pipe));
1390 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1393 struct drm_device *dev = dev_priv->dev;
1397 if (INTEL_INFO(dev)->gen >= 9) {
1398 for_each_sprite(dev_priv, pipe, sprite) {
1399 val = I915_READ(PLANE_CTL(pipe, sprite));
1400 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1401 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1402 sprite, pipe_name(pipe));
1404 } else if (IS_VALLEYVIEW(dev)) {
1405 for_each_sprite(dev_priv, pipe, sprite) {
1406 reg = SPCNTR(pipe, sprite);
1407 val = I915_READ(reg);
1408 I915_STATE_WARN(val & SP_ENABLE,
1409 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1410 sprite_name(pipe, sprite), pipe_name(pipe));
1412 } else if (INTEL_INFO(dev)->gen >= 7) {
1414 val = I915_READ(reg);
1415 I915_STATE_WARN(val & SPRITE_ENABLE,
1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417 plane_name(pipe), pipe_name(pipe));
1418 } else if (INTEL_INFO(dev)->gen >= 5) {
1419 reg = DVSCNTR(pipe);
1420 val = I915_READ(reg);
1421 I915_STATE_WARN(val & DVS_ENABLE,
1422 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1423 plane_name(pipe), pipe_name(pipe));
1427 static void assert_vblank_disabled(struct drm_crtc *crtc)
1429 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1430 drm_crtc_vblank_put(crtc);
1433 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1438 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1440 val = I915_READ(PCH_DREF_CONTROL);
1441 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1442 DREF_SUPERSPREAD_SOURCE_MASK));
1443 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1446 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1453 reg = PCH_TRANSCONF(pipe);
1454 val = I915_READ(reg);
1455 enabled = !!(val & TRANS_ENABLE);
1456 I915_STATE_WARN(enabled,
1457 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1462 enum pipe pipe, u32 port_sel, u32 val)
1464 if ((val & DP_PORT_EN) == 0)
1467 if (HAS_PCH_CPT(dev_priv->dev)) {
1468 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1469 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1470 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1472 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1473 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1476 if ((val & DP_PIPE_MASK) != (pipe << 30))
1482 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, u32 val)
1485 if ((val & SDVO_ENABLE) == 0)
1488 if (HAS_PCH_CPT(dev_priv->dev)) {
1489 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1491 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1495 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1501 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1502 enum pipe pipe, u32 val)
1504 if ((val & LVDS_PORT_EN) == 0)
1507 if (HAS_PCH_CPT(dev_priv->dev)) {
1508 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1511 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1517 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1518 enum pipe pipe, u32 val)
1520 if ((val & ADPA_DAC_ENABLE) == 0)
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1526 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1532 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, int reg, u32 port_sel)
1535 u32 val = I915_READ(reg);
1536 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1537 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1538 reg, pipe_name(pipe));
1540 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1541 && (val & DP_PIPEB_SELECT),
1542 "IBX PCH dp port still using transcoder B\n");
1545 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1546 enum pipe pipe, int reg)
1548 u32 val = I915_READ(reg);
1549 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1550 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1551 reg, pipe_name(pipe));
1553 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1554 && (val & SDVO_PIPE_B_SELECT),
1555 "IBX PCH hdmi port still using transcoder B\n");
1558 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1564 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1565 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1566 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1569 val = I915_READ(reg);
1570 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1571 "PCH VGA enabled on transcoder %c, should be disabled\n",
1575 val = I915_READ(reg);
1576 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1577 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1580 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1581 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1582 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1585 static void intel_init_dpio(struct drm_device *dev)
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1589 if (!IS_VALLEYVIEW(dev))
1593 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1594 * CHV x1 PHY (DP/HDMI D)
1595 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1597 if (IS_CHERRYVIEW(dev)) {
1598 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1599 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 static void vlv_enable_pll(struct intel_crtc *crtc,
1606 const struct intel_crtc_state *pipe_config)
1608 struct drm_device *dev = crtc->base.dev;
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 int reg = DPLL(crtc->pipe);
1611 u32 dpll = pipe_config->dpll_hw_state.dpll;
1613 assert_pipe_disabled(dev_priv, crtc->pipe);
1615 /* No really, not for ILK+ */
1616 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1618 /* PLL is protected by panel, make sure we can write it */
1619 if (IS_MOBILE(dev_priv->dev))
1620 assert_panel_unlocked(dev_priv, crtc->pipe);
1622 I915_WRITE(reg, dpll);
1626 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1627 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1629 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1630 POSTING_READ(DPLL_MD(crtc->pipe));
1632 /* We do this three times for luck */
1633 I915_WRITE(reg, dpll);
1635 udelay(150); /* wait for warmup */
1636 I915_WRITE(reg, dpll);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg, dpll);
1641 udelay(150); /* wait for warmup */
1644 static void chv_enable_pll(struct intel_crtc *crtc,
1645 const struct intel_crtc_state *pipe_config)
1647 struct drm_device *dev = crtc->base.dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 int pipe = crtc->pipe;
1650 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1653 assert_pipe_disabled(dev_priv, crtc->pipe);
1655 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1657 mutex_lock(&dev_priv->sb_lock);
1659 /* Enable back the 10bit clock to display controller */
1660 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1661 tmp |= DPIO_DCLKP_EN;
1662 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1664 mutex_unlock(&dev_priv->sb_lock);
1667 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1672 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1674 /* Check PLL is locked */
1675 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1676 DRM_ERROR("PLL %d failed to lock\n", pipe);
1678 /* not sure when this should be written */
1679 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1680 POSTING_READ(DPLL_MD(pipe));
1683 static int intel_num_dvo_pipes(struct drm_device *dev)
1685 struct intel_crtc *crtc;
1688 for_each_intel_crtc(dev, crtc)
1689 count += crtc->base.state->active &&
1690 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1695 static void i9xx_enable_pll(struct intel_crtc *crtc)
1697 struct drm_device *dev = crtc->base.dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699 int reg = DPLL(crtc->pipe);
1700 u32 dpll = crtc->config->dpll_hw_state.dpll;
1702 assert_pipe_disabled(dev_priv, crtc->pipe);
1704 /* No really, not for ILK+ */
1705 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1707 /* PLL is protected by panel, make sure we can write it */
1708 if (IS_MOBILE(dev) && !IS_I830(dev))
1709 assert_panel_unlocked(dev_priv, crtc->pipe);
1711 /* Enable DVO 2x clock on both PLLs if necessary */
1712 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1714 * It appears to be important that we don't enable this
1715 * for the current pipe before otherwise configuring the
1716 * PLL. No idea how this should be handled if multiple
1717 * DVO outputs are enabled simultaneosly.
1719 dpll |= DPLL_DVO_2X_MODE;
1720 I915_WRITE(DPLL(!crtc->pipe),
1721 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1724 /* Wait for the clocks to stabilize. */
1728 if (INTEL_INFO(dev)->gen >= 4) {
1729 I915_WRITE(DPLL_MD(crtc->pipe),
1730 crtc->config->dpll_hw_state.dpll_md);
1732 /* The pixel multiplier can only be updated once the
1733 * DPLL is enabled and the clocks are stable.
1735 * So write it again.
1737 I915_WRITE(reg, dpll);
1740 /* We do this three times for luck */
1741 I915_WRITE(reg, dpll);
1743 udelay(150); /* wait for warmup */
1744 I915_WRITE(reg, dpll);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1749 udelay(150); /* wait for warmup */
1753 * i9xx_disable_pll - disable a PLL
1754 * @dev_priv: i915 private structure
1755 * @pipe: pipe PLL to disable
1757 * Disable the PLL for @pipe, making sure the pipe is off first.
1759 * Note! This is for pre-ILK only.
1761 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 struct drm_device *dev = crtc->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 enum pipe pipe = crtc->pipe;
1767 /* Disable DVO 2x clock on both PLLs if necessary */
1769 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1770 !intel_num_dvo_pipes(dev)) {
1771 I915_WRITE(DPLL(PIPE_B),
1772 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773 I915_WRITE(DPLL(PIPE_A),
1774 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1777 /* Don't disable pipe or pipe PLLs if needed */
1778 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1782 /* Make sure the pipe isn't still relying on us */
1783 assert_pipe_disabled(dev_priv, pipe);
1785 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1786 POSTING_READ(DPLL(pipe));
1789 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 /* Make sure the pipe isn't still relying on us */
1794 assert_pipe_disabled(dev_priv, pipe);
1797 * Leave integrated clock source and reference clock enabled for pipe B.
1798 * The latter is needed for VGA hotplug / manual detection.
1800 val = DPLL_VGA_MODE_DIS;
1802 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1803 I915_WRITE(DPLL(pipe), val);
1804 POSTING_READ(DPLL(pipe));
1808 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1813 /* Make sure the pipe isn't still relying on us */
1814 assert_pipe_disabled(dev_priv, pipe);
1816 /* Set PLL en = 0 */
1817 val = DPLL_SSC_REF_CLK_CHV |
1818 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821 I915_WRITE(DPLL(pipe), val);
1822 POSTING_READ(DPLL(pipe));
1824 mutex_lock(&dev_priv->sb_lock);
1826 /* Disable 10bit clock to display controller */
1827 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828 val &= ~DPIO_DCLKP_EN;
1829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831 /* disable left/right clock distribution */
1832 if (pipe != PIPE_B) {
1833 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1837 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1842 mutex_unlock(&dev_priv->sb_lock);
1845 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1846 struct intel_digital_port *dport,
1847 unsigned int expected_mask)
1852 switch (dport->port) {
1854 port_mask = DPLL_PORTB_READY_MASK;
1858 port_mask = DPLL_PORTC_READY_MASK;
1860 expected_mask <<= 4;
1863 port_mask = DPLL_PORTD_READY_MASK;
1864 dpll_reg = DPIO_PHY_STATUS;
1870 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1875 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881 if (WARN_ON(pll == NULL))
1884 WARN_ON(!pll->config.crtc_mask);
1885 if (pll->active == 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888 assert_shared_dpll_disabled(dev_priv, pll);
1890 pll->mode_set(dev_priv, pll);
1895 * intel_enable_shared_dpll - enable PCH PLL
1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1902 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1904 struct drm_device *dev = crtc->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
1906 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1908 if (WARN_ON(pll == NULL))
1911 if (WARN_ON(pll->config.crtc_mask == 0))
1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1915 pll->name, pll->active, pll->on,
1916 crtc->base.base.id);
1918 if (pll->active++) {
1920 assert_shared_dpll_enabled(dev_priv, pll);
1925 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1928 pll->enable(dev_priv, pll);
1932 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1934 struct drm_device *dev = crtc->base.dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1938 /* PCH only available on ILK+ */
1939 if (INTEL_INFO(dev)->gen < 5)
1945 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1948 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1949 pll->name, pll->active, pll->on,
1950 crtc->base.base.id);
1952 if (WARN_ON(pll->active == 0)) {
1953 assert_shared_dpll_disabled(dev_priv, pll);
1957 assert_shared_dpll_enabled(dev_priv, pll);
1962 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1963 pll->disable(dev_priv, pll);
1966 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1969 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1972 struct drm_device *dev = dev_priv->dev;
1973 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1975 uint32_t reg, val, pipeconf_val;
1977 /* PCH only available on ILK+ */
1978 BUG_ON(!HAS_PCH_SPLIT(dev));
1980 /* Make sure PCH DPLL is enabled */
1981 assert_shared_dpll_enabled(dev_priv,
1982 intel_crtc_to_shared_dpll(intel_crtc));
1984 /* FDI must be feeding us bits for PCH ports */
1985 assert_fdi_tx_enabled(dev_priv, pipe);
1986 assert_fdi_rx_enabled(dev_priv, pipe);
1988 if (HAS_PCH_CPT(dev)) {
1989 /* Workaround: Set the timing override bit before enabling the
1990 * pch transcoder. */
1991 reg = TRANS_CHICKEN2(pipe);
1992 val = I915_READ(reg);
1993 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1994 I915_WRITE(reg, val);
1997 reg = PCH_TRANSCONF(pipe);
1998 val = I915_READ(reg);
1999 pipeconf_val = I915_READ(PIPECONF(pipe));
2001 if (HAS_PCH_IBX(dev_priv->dev)) {
2003 * Make the BPC in transcoder be consistent with
2004 * that in pipeconf reg. For HDMI we must use 8bpc
2005 * here for both 8bpc and 12bpc.
2007 val &= ~PIPECONF_BPC_MASK;
2008 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2009 val |= PIPECONF_8BPC;
2011 val |= pipeconf_val & PIPECONF_BPC_MASK;
2014 val &= ~TRANS_INTERLACE_MASK;
2015 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2016 if (HAS_PCH_IBX(dev_priv->dev) &&
2017 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2018 val |= TRANS_LEGACY_INTERLACED_ILK;
2020 val |= TRANS_INTERLACED;
2022 val |= TRANS_PROGRESSIVE;
2024 I915_WRITE(reg, val | TRANS_ENABLE);
2025 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2026 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2029 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2030 enum transcoder cpu_transcoder)
2032 u32 val, pipeconf_val;
2034 /* PCH only available on ILK+ */
2035 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2037 /* FDI must be feeding us bits for PCH ports */
2038 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2039 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2041 /* Workaround: set timing override bit. */
2042 val = I915_READ(_TRANSA_CHICKEN2);
2043 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2044 I915_WRITE(_TRANSA_CHICKEN2, val);
2047 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2049 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2050 PIPECONF_INTERLACED_ILK)
2051 val |= TRANS_INTERLACED;
2053 val |= TRANS_PROGRESSIVE;
2055 I915_WRITE(LPT_TRANSCONF, val);
2056 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2057 DRM_ERROR("Failed to enable PCH transcoder\n");
2060 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2063 struct drm_device *dev = dev_priv->dev;
2066 /* FDI relies on the transcoder */
2067 assert_fdi_tx_disabled(dev_priv, pipe);
2068 assert_fdi_rx_disabled(dev_priv, pipe);
2070 /* Ports must be off as well */
2071 assert_pch_ports_disabled(dev_priv, pipe);
2073 reg = PCH_TRANSCONF(pipe);
2074 val = I915_READ(reg);
2075 val &= ~TRANS_ENABLE;
2076 I915_WRITE(reg, val);
2077 /* wait for PCH transcoder off, transcoder state */
2078 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2079 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2081 if (!HAS_PCH_IBX(dev)) {
2082 /* Workaround: Clear the timing override chicken bit again. */
2083 reg = TRANS_CHICKEN2(pipe);
2084 val = I915_READ(reg);
2085 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2086 I915_WRITE(reg, val);
2090 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2094 val = I915_READ(LPT_TRANSCONF);
2095 val &= ~TRANS_ENABLE;
2096 I915_WRITE(LPT_TRANSCONF, val);
2097 /* wait for PCH transcoder off, transcoder state */
2098 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2099 DRM_ERROR("Failed to disable PCH transcoder\n");
2101 /* Workaround: clear timing override bit. */
2102 val = I915_READ(_TRANSA_CHICKEN2);
2103 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2104 I915_WRITE(_TRANSA_CHICKEN2, val);
2108 * intel_enable_pipe - enable a pipe, asserting requirements
2109 * @crtc: crtc responsible for the pipe
2111 * Enable @crtc's pipe, making sure that various hardware specific requirements
2112 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2114 static void intel_enable_pipe(struct intel_crtc *crtc)
2116 struct drm_device *dev = crtc->base.dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 enum pipe pipe = crtc->pipe;
2119 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2121 enum pipe pch_transcoder;
2125 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2127 assert_planes_disabled(dev_priv, pipe);
2128 assert_cursor_disabled(dev_priv, pipe);
2129 assert_sprites_disabled(dev_priv, pipe);
2131 if (HAS_PCH_LPT(dev_priv->dev))
2132 pch_transcoder = TRANSCODER_A;
2134 pch_transcoder = pipe;
2137 * A pipe without a PLL won't actually be able to drive bits from
2138 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2141 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2142 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2143 assert_dsi_pll_enabled(dev_priv);
2145 assert_pll_enabled(dev_priv, pipe);
2147 if (crtc->config->has_pch_encoder) {
2148 /* if driving the PCH, we need FDI enabled */
2149 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2150 assert_fdi_tx_pll_enabled(dev_priv,
2151 (enum pipe) cpu_transcoder);
2153 /* FIXME: assert CPU port conditions for SNB+ */
2156 reg = PIPECONF(cpu_transcoder);
2157 val = I915_READ(reg);
2158 if (val & PIPECONF_ENABLE) {
2159 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2160 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2164 I915_WRITE(reg, val | PIPECONF_ENABLE);
2169 * intel_disable_pipe - disable a pipe, asserting requirements
2170 * @crtc: crtc whose pipes is to be disabled
2172 * Disable the pipe of @crtc, making sure that various hardware
2173 * specific requirements are met, if applicable, e.g. plane
2174 * disabled, panel fitter off, etc.
2176 * Will wait until the pipe has shut down before returning.
2178 static void intel_disable_pipe(struct intel_crtc *crtc)
2180 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2181 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2182 enum pipe pipe = crtc->pipe;
2186 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2189 * Make sure planes won't keep trying to pump pixels to us,
2190 * or we might hang the display.
2192 assert_planes_disabled(dev_priv, pipe);
2193 assert_cursor_disabled(dev_priv, pipe);
2194 assert_sprites_disabled(dev_priv, pipe);
2196 reg = PIPECONF(cpu_transcoder);
2197 val = I915_READ(reg);
2198 if ((val & PIPECONF_ENABLE) == 0)
2202 * Double wide has implications for planes
2203 * so best keep it disabled when not needed.
2205 if (crtc->config->double_wide)
2206 val &= ~PIPECONF_DOUBLE_WIDE;
2208 /* Don't disable pipe or pipe PLLs if needed */
2209 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2210 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2211 val &= ~PIPECONF_ENABLE;
2213 I915_WRITE(reg, val);
2214 if ((val & PIPECONF_ENABLE) == 0)
2215 intel_wait_for_pipe_off(crtc);
2218 static bool need_vtd_wa(struct drm_device *dev)
2220 #ifdef CONFIG_INTEL_IOMMU
2221 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2228 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2229 uint64_t fb_format_modifier)
2231 unsigned int tile_height;
2232 uint32_t pixel_bytes;
2234 switch (fb_format_modifier) {
2235 case DRM_FORMAT_MOD_NONE:
2238 case I915_FORMAT_MOD_X_TILED:
2239 tile_height = IS_GEN2(dev) ? 16 : 8;
2241 case I915_FORMAT_MOD_Y_TILED:
2244 case I915_FORMAT_MOD_Yf_TILED:
2245 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2246 switch (pixel_bytes) {
2260 "128-bit pixels are not supported for display!");
2266 MISSING_CASE(fb_format_modifier);
2275 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2276 uint32_t pixel_format, uint64_t fb_format_modifier)
2278 return ALIGN(height, intel_tile_height(dev, pixel_format,
2279 fb_format_modifier));
2283 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2284 const struct drm_plane_state *plane_state)
2286 struct intel_rotation_info *info = &view->rotation_info;
2287 unsigned int tile_height, tile_pitch;
2289 *view = i915_ggtt_view_normal;
2294 if (!intel_rotation_90_or_270(plane_state->rotation))
2297 *view = i915_ggtt_view_rotated;
2299 info->height = fb->height;
2300 info->pixel_format = fb->pixel_format;
2301 info->pitch = fb->pitches[0];
2302 info->fb_modifier = fb->modifier[0];
2304 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2306 tile_pitch = PAGE_SIZE / tile_height;
2307 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2309 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2314 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2316 if (INTEL_INFO(dev_priv)->gen >= 9)
2318 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2319 IS_VALLEYVIEW(dev_priv))
2321 else if (INTEL_INFO(dev_priv)->gen >= 4)
2328 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2329 struct drm_framebuffer *fb,
2330 const struct drm_plane_state *plane_state,
2331 struct intel_engine_cs *pipelined,
2332 struct drm_i915_gem_request **pipelined_request)
2334 struct drm_device *dev = fb->dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337 struct i915_ggtt_view view;
2341 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2343 switch (fb->modifier[0]) {
2344 case DRM_FORMAT_MOD_NONE:
2345 alignment = intel_linear_alignment(dev_priv);
2347 case I915_FORMAT_MOD_X_TILED:
2348 if (INTEL_INFO(dev)->gen >= 9)
2349 alignment = 256 * 1024;
2351 /* pin() will align the object as required by fence */
2355 case I915_FORMAT_MOD_Y_TILED:
2356 case I915_FORMAT_MOD_Yf_TILED:
2357 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2358 "Y tiling bo slipped through, driver bug!\n"))
2360 alignment = 1 * 1024 * 1024;
2363 MISSING_CASE(fb->modifier[0]);
2367 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2371 /* Note that the w/a also requires 64 PTE of padding following the
2372 * bo. We currently fill all unused PTE with the shadow page and so
2373 * we should always have valid PTE following the scanout preventing
2376 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2377 alignment = 256 * 1024;
2380 * Global gtt pte registers are special registers which actually forward
2381 * writes to a chunk of system memory. Which means that there is no risk
2382 * that the register values disappear as soon as we call
2383 * intel_runtime_pm_put(), so it is correct to wrap only the
2384 * pin/unpin/fence and not more.
2386 intel_runtime_pm_get(dev_priv);
2388 dev_priv->mm.interruptible = false;
2389 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2390 pipelined_request, &view);
2392 goto err_interruptible;
2394 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2395 * fence, whereas 965+ only requires a fence if using
2396 * framebuffer compression. For simplicity, we always install
2397 * a fence as the cost is not that onerous.
2399 ret = i915_gem_object_get_fence(obj);
2403 i915_gem_object_pin_fence(obj);
2405 dev_priv->mm.interruptible = true;
2406 intel_runtime_pm_put(dev_priv);
2410 i915_gem_object_unpin_from_display_plane(obj, &view);
2412 dev_priv->mm.interruptible = true;
2413 intel_runtime_pm_put(dev_priv);
2417 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2418 const struct drm_plane_state *plane_state)
2420 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2421 struct i915_ggtt_view view;
2424 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2426 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2427 WARN_ONCE(ret, "Couldn't get view from plane state!");
2429 i915_gem_object_unpin_fence(obj);
2430 i915_gem_object_unpin_from_display_plane(obj, &view);
2433 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2434 * is assumed to be a power-of-two. */
2435 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2437 unsigned int tiling_mode,
2441 if (tiling_mode != I915_TILING_NONE) {
2442 unsigned int tile_rows, tiles;
2447 tiles = *x / (512/cpp);
2450 return tile_rows * pitch * 8 + tiles * 4096;
2452 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2453 unsigned int offset;
2455 offset = *y * pitch + *x * cpp;
2456 *y = (offset & alignment) / pitch;
2457 *x = ((offset & alignment) - *y * pitch) / cpp;
2458 return offset & ~alignment;
2462 static int i9xx_format_to_fourcc(int format)
2465 case DISPPLANE_8BPP:
2466 return DRM_FORMAT_C8;
2467 case DISPPLANE_BGRX555:
2468 return DRM_FORMAT_XRGB1555;
2469 case DISPPLANE_BGRX565:
2470 return DRM_FORMAT_RGB565;
2472 case DISPPLANE_BGRX888:
2473 return DRM_FORMAT_XRGB8888;
2474 case DISPPLANE_RGBX888:
2475 return DRM_FORMAT_XBGR8888;
2476 case DISPPLANE_BGRX101010:
2477 return DRM_FORMAT_XRGB2101010;
2478 case DISPPLANE_RGBX101010:
2479 return DRM_FORMAT_XBGR2101010;
2483 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2486 case PLANE_CTL_FORMAT_RGB_565:
2487 return DRM_FORMAT_RGB565;
2489 case PLANE_CTL_FORMAT_XRGB_8888:
2492 return DRM_FORMAT_ABGR8888;
2494 return DRM_FORMAT_XBGR8888;
2497 return DRM_FORMAT_ARGB8888;
2499 return DRM_FORMAT_XRGB8888;
2501 case PLANE_CTL_FORMAT_XRGB_2101010:
2503 return DRM_FORMAT_XBGR2101010;
2505 return DRM_FORMAT_XRGB2101010;
2510 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2511 struct intel_initial_plane_config *plane_config)
2513 struct drm_device *dev = crtc->base.dev;
2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2516 struct drm_framebuffer *fb = &plane_config->fb->base;
2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2521 size_aligned -= base_aligned;
2523 if (plane_config->size == 0)
2526 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2533 obj->tiling_mode = plane_config->tiling;
2534 if (obj->tiling_mode == I915_TILING_X)
2535 obj->stride = fb->pitches[0];
2537 mode_cmd.pixel_format = fb->pixel_format;
2538 mode_cmd.width = fb->width;
2539 mode_cmd.height = fb->height;
2540 mode_cmd.pitches[0] = fb->pitches[0];
2541 mode_cmd.modifier[0] = fb->modifier[0];
2542 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2544 mutex_lock(&dev->struct_mutex);
2545 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2547 DRM_DEBUG_KMS("intel fb init failed\n");
2550 mutex_unlock(&dev->struct_mutex);
2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2556 drm_gem_object_unreference(&obj->base);
2557 mutex_unlock(&dev->struct_mutex);
2561 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2563 update_state_fb(struct drm_plane *plane)
2565 if (plane->fb == plane->state->fb)
2568 if (plane->state->fb)
2569 drm_framebuffer_unreference(plane->state->fb);
2570 plane->state->fb = plane->fb;
2571 if (plane->state->fb)
2572 drm_framebuffer_reference(plane->state->fb);
2576 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2577 struct intel_initial_plane_config *plane_config)
2579 struct drm_device *dev = intel_crtc->base.dev;
2580 struct drm_i915_private *dev_priv = dev->dev_private;
2582 struct intel_crtc *i;
2583 struct drm_i915_gem_object *obj;
2584 struct drm_plane *primary = intel_crtc->base.primary;
2585 struct drm_plane_state *plane_state = primary->state;
2586 struct drm_framebuffer *fb;
2588 if (!plane_config->fb)
2591 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2592 fb = &plane_config->fb->base;
2596 kfree(plane_config->fb);
2599 * Failed to alloc the obj, check to see if we should share
2600 * an fb with another CRTC instead
2602 for_each_crtc(dev, c) {
2603 i = to_intel_crtc(c);
2605 if (c == &intel_crtc->base)
2611 fb = c->primary->fb;
2615 obj = intel_fb_obj(fb);
2616 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2617 drm_framebuffer_reference(fb);
2625 plane_state->src_x = plane_state->src_y = 0;
2626 plane_state->src_w = fb->width << 16;
2627 plane_state->src_h = fb->height << 16;
2629 plane_state->crtc_x = plane_state->src_y = 0;
2630 plane_state->crtc_w = fb->width;
2631 plane_state->crtc_h = fb->height;
2633 obj = intel_fb_obj(fb);
2634 if (obj->tiling_mode != I915_TILING_NONE)
2635 dev_priv->preserve_bios_swizzle = true;
2637 drm_framebuffer_reference(fb);
2638 primary->fb = primary->state->fb = fb;
2639 primary->crtc = primary->state->crtc = &intel_crtc->base;
2640 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2641 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2644 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2645 struct drm_framebuffer *fb,
2648 struct drm_device *dev = crtc->dev;
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651 struct drm_plane *primary = crtc->primary;
2652 bool visible = to_intel_plane_state(primary->state)->visible;
2653 struct drm_i915_gem_object *obj;
2654 int plane = intel_crtc->plane;
2655 unsigned long linear_offset;
2657 u32 reg = DSPCNTR(plane);
2660 if (!visible || !fb) {
2662 if (INTEL_INFO(dev)->gen >= 4)
2663 I915_WRITE(DSPSURF(plane), 0);
2665 I915_WRITE(DSPADDR(plane), 0);
2670 obj = intel_fb_obj(fb);
2671 if (WARN_ON(obj == NULL))
2674 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2676 dspcntr = DISPPLANE_GAMMA_ENABLE;
2678 dspcntr |= DISPLAY_PLANE_ENABLE;
2680 if (INTEL_INFO(dev)->gen < 4) {
2681 if (intel_crtc->pipe == PIPE_B)
2682 dspcntr |= DISPPLANE_SEL_PIPE_B;
2684 /* pipesrc and dspsize control the size that is scaled from,
2685 * which should always be the user's requested size.
2687 I915_WRITE(DSPSIZE(plane),
2688 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2689 (intel_crtc->config->pipe_src_w - 1));
2690 I915_WRITE(DSPPOS(plane), 0);
2691 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2692 I915_WRITE(PRIMSIZE(plane),
2693 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694 (intel_crtc->config->pipe_src_w - 1));
2695 I915_WRITE(PRIMPOS(plane), 0);
2696 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2699 switch (fb->pixel_format) {
2701 dspcntr |= DISPPLANE_8BPP;
2703 case DRM_FORMAT_XRGB1555:
2704 dspcntr |= DISPPLANE_BGRX555;
2706 case DRM_FORMAT_RGB565:
2707 dspcntr |= DISPPLANE_BGRX565;
2709 case DRM_FORMAT_XRGB8888:
2710 dspcntr |= DISPPLANE_BGRX888;
2712 case DRM_FORMAT_XBGR8888:
2713 dspcntr |= DISPPLANE_RGBX888;
2715 case DRM_FORMAT_XRGB2101010:
2716 dspcntr |= DISPPLANE_BGRX101010;
2718 case DRM_FORMAT_XBGR2101010:
2719 dspcntr |= DISPPLANE_RGBX101010;
2725 if (INTEL_INFO(dev)->gen >= 4 &&
2726 obj->tiling_mode != I915_TILING_NONE)
2727 dspcntr |= DISPPLANE_TILED;
2730 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2732 linear_offset = y * fb->pitches[0] + x * pixel_size;
2734 if (INTEL_INFO(dev)->gen >= 4) {
2735 intel_crtc->dspaddr_offset =
2736 intel_gen4_compute_page_offset(dev_priv,
2737 &x, &y, obj->tiling_mode,
2740 linear_offset -= intel_crtc->dspaddr_offset;
2742 intel_crtc->dspaddr_offset = linear_offset;
2745 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2746 dspcntr |= DISPPLANE_ROTATE_180;
2748 x += (intel_crtc->config->pipe_src_w - 1);
2749 y += (intel_crtc->config->pipe_src_h - 1);
2751 /* Finding the last pixel of the last line of the display
2752 data and adding to linear_offset*/
2754 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2755 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2758 I915_WRITE(reg, dspcntr);
2760 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2761 if (INTEL_INFO(dev)->gen >= 4) {
2762 I915_WRITE(DSPSURF(plane),
2763 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2764 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2765 I915_WRITE(DSPLINOFF(plane), linear_offset);
2767 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2771 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2772 struct drm_framebuffer *fb,
2775 struct drm_device *dev = crtc->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778 struct drm_plane *primary = crtc->primary;
2779 bool visible = to_intel_plane_state(primary->state)->visible;
2780 struct drm_i915_gem_object *obj;
2781 int plane = intel_crtc->plane;
2782 unsigned long linear_offset;
2784 u32 reg = DSPCNTR(plane);
2787 if (!visible || !fb) {
2789 I915_WRITE(DSPSURF(plane), 0);
2794 obj = intel_fb_obj(fb);
2795 if (WARN_ON(obj == NULL))
2798 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2800 dspcntr = DISPPLANE_GAMMA_ENABLE;
2802 dspcntr |= DISPLAY_PLANE_ENABLE;
2804 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2805 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2807 switch (fb->pixel_format) {
2809 dspcntr |= DISPPLANE_8BPP;
2811 case DRM_FORMAT_RGB565:
2812 dspcntr |= DISPPLANE_BGRX565;
2814 case DRM_FORMAT_XRGB8888:
2815 dspcntr |= DISPPLANE_BGRX888;
2817 case DRM_FORMAT_XBGR8888:
2818 dspcntr |= DISPPLANE_RGBX888;
2820 case DRM_FORMAT_XRGB2101010:
2821 dspcntr |= DISPPLANE_BGRX101010;
2823 case DRM_FORMAT_XBGR2101010:
2824 dspcntr |= DISPPLANE_RGBX101010;
2830 if (obj->tiling_mode != I915_TILING_NONE)
2831 dspcntr |= DISPPLANE_TILED;
2833 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2834 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2836 linear_offset = y * fb->pitches[0] + x * pixel_size;
2837 intel_crtc->dspaddr_offset =
2838 intel_gen4_compute_page_offset(dev_priv,
2839 &x, &y, obj->tiling_mode,
2842 linear_offset -= intel_crtc->dspaddr_offset;
2843 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2844 dspcntr |= DISPPLANE_ROTATE_180;
2846 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2847 x += (intel_crtc->config->pipe_src_w - 1);
2848 y += (intel_crtc->config->pipe_src_h - 1);
2850 /* Finding the last pixel of the last line of the display
2851 data and adding to linear_offset*/
2853 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2854 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2858 I915_WRITE(reg, dspcntr);
2860 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2861 I915_WRITE(DSPSURF(plane),
2862 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2863 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2864 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2866 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2867 I915_WRITE(DSPLINOFF(plane), linear_offset);
2872 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2873 uint32_t pixel_format)
2875 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2878 * The stride is either expressed as a multiple of 64 bytes
2879 * chunks for linear buffers or in number of tiles for tiled
2882 switch (fb_modifier) {
2883 case DRM_FORMAT_MOD_NONE:
2885 case I915_FORMAT_MOD_X_TILED:
2886 if (INTEL_INFO(dev)->gen == 2)
2889 case I915_FORMAT_MOD_Y_TILED:
2890 /* No need to check for old gens and Y tiling since this is
2891 * about the display engine and those will be blocked before
2895 case I915_FORMAT_MOD_Yf_TILED:
2896 if (bits_per_pixel == 8)
2901 MISSING_CASE(fb_modifier);
2906 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2907 struct drm_i915_gem_object *obj)
2909 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2911 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2912 view = &i915_ggtt_view_rotated;
2914 return i915_gem_obj_ggtt_offset_view(obj, view);
2917 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2919 struct drm_device *dev = intel_crtc->base.dev;
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2922 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2923 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2924 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2925 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2926 intel_crtc->base.base.id, intel_crtc->pipe, id);
2930 * This function detaches (aka. unbinds) unused scalers in hardware
2932 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2934 struct intel_crtc_scaler_state *scaler_state;
2937 scaler_state = &intel_crtc->config->scaler_state;
2939 /* loop through and disable scalers that aren't in use */
2940 for (i = 0; i < intel_crtc->num_scalers; i++) {
2941 if (!scaler_state->scalers[i].in_use)
2942 skl_detach_scaler(intel_crtc, i);
2946 u32 skl_plane_ctl_format(uint32_t pixel_format)
2948 switch (pixel_format) {
2950 return PLANE_CTL_FORMAT_INDEXED;
2951 case DRM_FORMAT_RGB565:
2952 return PLANE_CTL_FORMAT_RGB_565;
2953 case DRM_FORMAT_XBGR8888:
2954 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2955 case DRM_FORMAT_XRGB8888:
2956 return PLANE_CTL_FORMAT_XRGB_8888;
2958 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2959 * to be already pre-multiplied. We need to add a knob (or a different
2960 * DRM_FORMAT) for user-space to configure that.
2962 case DRM_FORMAT_ABGR8888:
2963 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2964 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2965 case DRM_FORMAT_ARGB8888:
2966 return PLANE_CTL_FORMAT_XRGB_8888 |
2967 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2968 case DRM_FORMAT_XRGB2101010:
2969 return PLANE_CTL_FORMAT_XRGB_2101010;
2970 case DRM_FORMAT_XBGR2101010:
2971 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2972 case DRM_FORMAT_YUYV:
2973 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2974 case DRM_FORMAT_YVYU:
2975 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2976 case DRM_FORMAT_UYVY:
2977 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2978 case DRM_FORMAT_VYUY:
2979 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2981 MISSING_CASE(pixel_format);
2987 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2989 switch (fb_modifier) {
2990 case DRM_FORMAT_MOD_NONE:
2992 case I915_FORMAT_MOD_X_TILED:
2993 return PLANE_CTL_TILED_X;
2994 case I915_FORMAT_MOD_Y_TILED:
2995 return PLANE_CTL_TILED_Y;
2996 case I915_FORMAT_MOD_Yf_TILED:
2997 return PLANE_CTL_TILED_YF;
2999 MISSING_CASE(fb_modifier);
3005 u32 skl_plane_ctl_rotation(unsigned int rotation)
3008 case BIT(DRM_ROTATE_0):
3011 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3012 * while i915 HW rotation is clockwise, thats why this swapping.
3014 case BIT(DRM_ROTATE_90):
3015 return PLANE_CTL_ROTATE_270;
3016 case BIT(DRM_ROTATE_180):
3017 return PLANE_CTL_ROTATE_180;
3018 case BIT(DRM_ROTATE_270):
3019 return PLANE_CTL_ROTATE_90;
3021 MISSING_CASE(rotation);
3027 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3028 struct drm_framebuffer *fb,
3031 struct drm_device *dev = crtc->dev;
3032 struct drm_i915_private *dev_priv = dev->dev_private;
3033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3034 struct drm_plane *plane = crtc->primary;
3035 bool visible = to_intel_plane_state(plane->state)->visible;
3036 struct drm_i915_gem_object *obj;
3037 int pipe = intel_crtc->pipe;
3038 u32 plane_ctl, stride_div, stride;
3039 u32 tile_height, plane_offset, plane_size;
3040 unsigned int rotation;
3041 int x_offset, y_offset;
3042 unsigned long surf_addr;
3043 struct intel_crtc_state *crtc_state = intel_crtc->config;
3044 struct intel_plane_state *plane_state;
3045 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3046 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3049 plane_state = to_intel_plane_state(plane->state);
3051 if (!visible || !fb) {
3052 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3053 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3054 POSTING_READ(PLANE_CTL(pipe, 0));
3058 plane_ctl = PLANE_CTL_ENABLE |
3059 PLANE_CTL_PIPE_GAMMA_ENABLE |
3060 PLANE_CTL_PIPE_CSC_ENABLE;
3062 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3063 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3064 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3066 rotation = plane->state->rotation;
3067 plane_ctl |= skl_plane_ctl_rotation(rotation);
3069 obj = intel_fb_obj(fb);
3070 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3072 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3075 * FIXME: intel_plane_state->src, dst aren't set when transitional
3076 * update_plane helpers are called from legacy paths.
3077 * Once full atomic crtc is available, below check can be avoided.
3079 if (drm_rect_width(&plane_state->src)) {
3080 scaler_id = plane_state->scaler_id;
3081 src_x = plane_state->src.x1 >> 16;
3082 src_y = plane_state->src.y1 >> 16;
3083 src_w = drm_rect_width(&plane_state->src) >> 16;
3084 src_h = drm_rect_height(&plane_state->src) >> 16;
3085 dst_x = plane_state->dst.x1;
3086 dst_y = plane_state->dst.y1;
3087 dst_w = drm_rect_width(&plane_state->dst);
3088 dst_h = drm_rect_height(&plane_state->dst);
3090 WARN_ON(x != src_x || y != src_y);
3092 src_w = intel_crtc->config->pipe_src_w;
3093 src_h = intel_crtc->config->pipe_src_h;
3096 if (intel_rotation_90_or_270(rotation)) {
3097 /* stride = Surface height in tiles */
3098 tile_height = intel_tile_height(dev, fb->pixel_format,
3100 stride = DIV_ROUND_UP(fb->height, tile_height);
3101 x_offset = stride * tile_height - y - src_h;
3103 plane_size = (src_w - 1) << 16 | (src_h - 1);
3105 stride = fb->pitches[0] / stride_div;
3108 plane_size = (src_h - 1) << 16 | (src_w - 1);
3110 plane_offset = y_offset << 16 | x_offset;
3112 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3113 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3114 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3115 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3117 if (scaler_id >= 0) {
3118 uint32_t ps_ctrl = 0;
3120 WARN_ON(!dst_w || !dst_h);
3121 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3122 crtc_state->scaler_state.scalers[scaler_id].mode;
3123 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3124 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3125 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3126 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3127 I915_WRITE(PLANE_POS(pipe, 0), 0);
3129 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3132 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3134 POSTING_READ(PLANE_SURF(pipe, 0));
3137 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3139 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3140 int x, int y, enum mode_set_atomic state)
3142 struct drm_device *dev = crtc->dev;
3143 struct drm_i915_private *dev_priv = dev->dev_private;
3145 if (dev_priv->fbc.disable_fbc)
3146 dev_priv->fbc.disable_fbc(dev_priv);
3148 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3153 static void intel_complete_page_flips(struct drm_device *dev)
3155 struct drm_crtc *crtc;
3157 for_each_crtc(dev, crtc) {
3158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3159 enum plane plane = intel_crtc->plane;
3161 intel_prepare_page_flip(dev, plane);
3162 intel_finish_page_flip_plane(dev, plane);
3166 static void intel_update_primary_planes(struct drm_device *dev)
3168 struct drm_i915_private *dev_priv = dev->dev_private;
3169 struct drm_crtc *crtc;
3171 for_each_crtc(dev, crtc) {
3172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3174 drm_modeset_lock(&crtc->mutex, NULL);
3176 * FIXME: Once we have proper support for primary planes (and
3177 * disabling them without disabling the entire crtc) allow again
3178 * a NULL crtc->primary->fb.
3180 if (intel_crtc->active && crtc->primary->fb)
3181 dev_priv->display.update_primary_plane(crtc,
3185 drm_modeset_unlock(&crtc->mutex);
3189 void intel_prepare_reset(struct drm_device *dev)
3191 /* no reset support for gen2 */
3195 /* reset doesn't touch the display */
3196 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3199 drm_modeset_lock_all(dev);
3201 * Disabling the crtcs gracefully seems nicer. Also the
3202 * g33 docs say we should at least disable all the planes.
3204 intel_display_suspend(dev);
3207 void intel_finish_reset(struct drm_device *dev)
3209 struct drm_i915_private *dev_priv = to_i915(dev);
3212 * Flips in the rings will be nuked by the reset,
3213 * so complete all pending flips so that user space
3214 * will get its events and not get stuck.
3216 intel_complete_page_flips(dev);
3218 /* no reset support for gen2 */
3222 /* reset doesn't touch the display */
3223 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3225 * Flips in the rings have been nuked by the reset,
3226 * so update the base address of all primary
3227 * planes to the the last fb to make sure we're
3228 * showing the correct fb after a reset.
3230 intel_update_primary_planes(dev);
3235 * The display has been reset as well,
3236 * so need a full re-initialization.
3238 intel_runtime_pm_disable_interrupts(dev_priv);
3239 intel_runtime_pm_enable_interrupts(dev_priv);
3241 intel_modeset_init_hw(dev);
3243 spin_lock_irq(&dev_priv->irq_lock);
3244 if (dev_priv->display.hpd_irq_setup)
3245 dev_priv->display.hpd_irq_setup(dev);
3246 spin_unlock_irq(&dev_priv->irq_lock);
3248 intel_display_resume(dev);
3250 intel_hpd_init(dev_priv);
3252 drm_modeset_unlock_all(dev);
3256 intel_finish_fb(struct drm_framebuffer *old_fb)
3258 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3259 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3260 bool was_interruptible = dev_priv->mm.interruptible;
3263 /* Big Hammer, we also need to ensure that any pending
3264 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3265 * current scanout is retired before unpinning the old
3266 * framebuffer. Note that we rely on userspace rendering
3267 * into the buffer attached to the pipe they are waiting
3268 * on. If not, userspace generates a GPU hang with IPEHR
3269 * point to the MI_WAIT_FOR_EVENT.
3271 * This should only fail upon a hung GPU, in which case we
3272 * can safely continue.
3274 dev_priv->mm.interruptible = false;
3275 ret = i915_gem_object_wait_rendering(obj, true);
3276 dev_priv->mm.interruptible = was_interruptible;
3281 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3283 struct drm_device *dev = crtc->dev;
3284 struct drm_i915_private *dev_priv = dev->dev_private;
3285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3288 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3289 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3292 spin_lock_irq(&dev->event_lock);
3293 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3294 spin_unlock_irq(&dev->event_lock);
3299 static void intel_update_pipe_size(struct intel_crtc *crtc)
3301 struct drm_device *dev = crtc->base.dev;
3302 struct drm_i915_private *dev_priv = dev->dev_private;
3303 const struct drm_display_mode *adjusted_mode;
3309 * Update pipe size and adjust fitter if needed: the reason for this is
3310 * that in compute_mode_changes we check the native mode (not the pfit
3311 * mode) to see if we can flip rather than do a full mode set. In the
3312 * fastboot case, we'll flip, but if we don't update the pipesrc and
3313 * pfit state, we'll end up with a big fb scanned out into the wrong
3316 * To fix this properly, we need to hoist the checks up into
3317 * compute_mode_changes (or above), check the actual pfit state and
3318 * whether the platform allows pfit disable with pipe active, and only
3319 * then update the pipesrc and pfit state, even on the flip path.
3322 adjusted_mode = &crtc->config->base.adjusted_mode;
3324 I915_WRITE(PIPESRC(crtc->pipe),
3325 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3326 (adjusted_mode->crtc_vdisplay - 1));
3327 if (!crtc->config->pch_pfit.enabled &&
3328 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3329 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3330 I915_WRITE(PF_CTL(crtc->pipe), 0);
3331 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3332 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3334 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3335 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3338 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3340 struct drm_device *dev = crtc->dev;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3343 int pipe = intel_crtc->pipe;
3346 /* enable normal train */
3347 reg = FDI_TX_CTL(pipe);
3348 temp = I915_READ(reg);
3349 if (IS_IVYBRIDGE(dev)) {
3350 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3351 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3353 temp &= ~FDI_LINK_TRAIN_NONE;
3354 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3356 I915_WRITE(reg, temp);
3358 reg = FDI_RX_CTL(pipe);
3359 temp = I915_READ(reg);
3360 if (HAS_PCH_CPT(dev)) {
3361 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3362 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3364 temp &= ~FDI_LINK_TRAIN_NONE;
3365 temp |= FDI_LINK_TRAIN_NONE;
3367 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3369 /* wait one idle pattern time */
3373 /* IVB wants error correction enabled */
3374 if (IS_IVYBRIDGE(dev))
3375 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3376 FDI_FE_ERRC_ENABLE);
3379 /* The FDI link training functions for ILK/Ibexpeak. */
3380 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3382 struct drm_device *dev = crtc->dev;
3383 struct drm_i915_private *dev_priv = dev->dev_private;
3384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3385 int pipe = intel_crtc->pipe;
3386 u32 reg, temp, tries;
3388 /* FDI needs bits from pipe first */
3389 assert_pipe_enabled(dev_priv, pipe);
3391 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3393 reg = FDI_RX_IMR(pipe);
3394 temp = I915_READ(reg);
3395 temp &= ~FDI_RX_SYMBOL_LOCK;
3396 temp &= ~FDI_RX_BIT_LOCK;
3397 I915_WRITE(reg, temp);
3401 /* enable CPU FDI TX and PCH FDI RX */
3402 reg = FDI_TX_CTL(pipe);
3403 temp = I915_READ(reg);
3404 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3405 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3406 temp &= ~FDI_LINK_TRAIN_NONE;
3407 temp |= FDI_LINK_TRAIN_PATTERN_1;
3408 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3410 reg = FDI_RX_CTL(pipe);
3411 temp = I915_READ(reg);
3412 temp &= ~FDI_LINK_TRAIN_NONE;
3413 temp |= FDI_LINK_TRAIN_PATTERN_1;
3414 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3419 /* Ironlake workaround, enable clock pointer after FDI enable*/
3420 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3421 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3422 FDI_RX_PHASE_SYNC_POINTER_EN);
3424 reg = FDI_RX_IIR(pipe);
3425 for (tries = 0; tries < 5; tries++) {
3426 temp = I915_READ(reg);
3427 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3429 if ((temp & FDI_RX_BIT_LOCK)) {
3430 DRM_DEBUG_KMS("FDI train 1 done.\n");
3431 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3436 DRM_ERROR("FDI train 1 fail!\n");
3439 reg = FDI_TX_CTL(pipe);
3440 temp = I915_READ(reg);
3441 temp &= ~FDI_LINK_TRAIN_NONE;
3442 temp |= FDI_LINK_TRAIN_PATTERN_2;
3443 I915_WRITE(reg, temp);
3445 reg = FDI_RX_CTL(pipe);
3446 temp = I915_READ(reg);
3447 temp &= ~FDI_LINK_TRAIN_NONE;
3448 temp |= FDI_LINK_TRAIN_PATTERN_2;
3449 I915_WRITE(reg, temp);
3454 reg = FDI_RX_IIR(pipe);
3455 for (tries = 0; tries < 5; tries++) {
3456 temp = I915_READ(reg);
3457 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3459 if (temp & FDI_RX_SYMBOL_LOCK) {
3460 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3461 DRM_DEBUG_KMS("FDI train 2 done.\n");
3466 DRM_ERROR("FDI train 2 fail!\n");
3468 DRM_DEBUG_KMS("FDI train done\n");
3472 static const int snb_b_fdi_train_param[] = {
3473 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3474 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3475 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3476 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3479 /* The FDI link training functions for SNB/Cougarpoint. */
3480 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3482 struct drm_device *dev = crtc->dev;
3483 struct drm_i915_private *dev_priv = dev->dev_private;
3484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3485 int pipe = intel_crtc->pipe;
3486 u32 reg, temp, i, retry;
3488 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3490 reg = FDI_RX_IMR(pipe);
3491 temp = I915_READ(reg);
3492 temp &= ~FDI_RX_SYMBOL_LOCK;
3493 temp &= ~FDI_RX_BIT_LOCK;
3494 I915_WRITE(reg, temp);
3499 /* enable CPU FDI TX and PCH FDI RX */
3500 reg = FDI_TX_CTL(pipe);
3501 temp = I915_READ(reg);
3502 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3503 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3504 temp &= ~FDI_LINK_TRAIN_NONE;
3505 temp |= FDI_LINK_TRAIN_PATTERN_1;
3506 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3508 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3509 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3511 I915_WRITE(FDI_RX_MISC(pipe),
3512 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3514 reg = FDI_RX_CTL(pipe);
3515 temp = I915_READ(reg);
3516 if (HAS_PCH_CPT(dev)) {
3517 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3518 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3520 temp &= ~FDI_LINK_TRAIN_NONE;
3521 temp |= FDI_LINK_TRAIN_PATTERN_1;
3523 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3528 for (i = 0; i < 4; i++) {
3529 reg = FDI_TX_CTL(pipe);
3530 temp = I915_READ(reg);
3531 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3532 temp |= snb_b_fdi_train_param[i];
3533 I915_WRITE(reg, temp);
3538 for (retry = 0; retry < 5; retry++) {
3539 reg = FDI_RX_IIR(pipe);
3540 temp = I915_READ(reg);
3541 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3542 if (temp & FDI_RX_BIT_LOCK) {
3543 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3544 DRM_DEBUG_KMS("FDI train 1 done.\n");
3553 DRM_ERROR("FDI train 1 fail!\n");
3556 reg = FDI_TX_CTL(pipe);
3557 temp = I915_READ(reg);
3558 temp &= ~FDI_LINK_TRAIN_NONE;
3559 temp |= FDI_LINK_TRAIN_PATTERN_2;
3561 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3563 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3565 I915_WRITE(reg, temp);
3567 reg = FDI_RX_CTL(pipe);
3568 temp = I915_READ(reg);
3569 if (HAS_PCH_CPT(dev)) {
3570 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3573 temp &= ~FDI_LINK_TRAIN_NONE;
3574 temp |= FDI_LINK_TRAIN_PATTERN_2;
3576 I915_WRITE(reg, temp);
3581 for (i = 0; i < 4; i++) {
3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
3584 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3585 temp |= snb_b_fdi_train_param[i];
3586 I915_WRITE(reg, temp);
3591 for (retry = 0; retry < 5; retry++) {
3592 reg = FDI_RX_IIR(pipe);
3593 temp = I915_READ(reg);
3594 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3595 if (temp & FDI_RX_SYMBOL_LOCK) {
3596 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3597 DRM_DEBUG_KMS("FDI train 2 done.\n");
3606 DRM_ERROR("FDI train 2 fail!\n");
3608 DRM_DEBUG_KMS("FDI train done.\n");
3611 /* Manual link training for Ivy Bridge A0 parts */
3612 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3614 struct drm_device *dev = crtc->dev;
3615 struct drm_i915_private *dev_priv = dev->dev_private;
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617 int pipe = intel_crtc->pipe;
3618 u32 reg, temp, i, j;
3620 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3622 reg = FDI_RX_IMR(pipe);
3623 temp = I915_READ(reg);
3624 temp &= ~FDI_RX_SYMBOL_LOCK;
3625 temp &= ~FDI_RX_BIT_LOCK;
3626 I915_WRITE(reg, temp);
3631 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3632 I915_READ(FDI_RX_IIR(pipe)));
3634 /* Try each vswing and preemphasis setting twice before moving on */
3635 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3636 /* disable first in case we need to retry */
3637 reg = FDI_TX_CTL(pipe);
3638 temp = I915_READ(reg);
3639 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3640 temp &= ~FDI_TX_ENABLE;
3641 I915_WRITE(reg, temp);
3643 reg = FDI_RX_CTL(pipe);
3644 temp = I915_READ(reg);
3645 temp &= ~FDI_LINK_TRAIN_AUTO;
3646 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3647 temp &= ~FDI_RX_ENABLE;
3648 I915_WRITE(reg, temp);
3650 /* enable CPU FDI TX and PCH FDI RX */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3654 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3655 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3656 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3657 temp |= snb_b_fdi_train_param[j/2];
3658 temp |= FDI_COMPOSITE_SYNC;
3659 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3661 I915_WRITE(FDI_RX_MISC(pipe),
3662 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3664 reg = FDI_RX_CTL(pipe);
3665 temp = I915_READ(reg);
3666 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3667 temp |= FDI_COMPOSITE_SYNC;
3668 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3671 udelay(1); /* should be 0.5us */
3673 for (i = 0; i < 4; i++) {
3674 reg = FDI_RX_IIR(pipe);
3675 temp = I915_READ(reg);
3676 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3678 if (temp & FDI_RX_BIT_LOCK ||
3679 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3680 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3681 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3685 udelay(1); /* should be 0.5us */
3688 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3693 reg = FDI_TX_CTL(pipe);
3694 temp = I915_READ(reg);
3695 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3696 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3697 I915_WRITE(reg, temp);
3699 reg = FDI_RX_CTL(pipe);
3700 temp = I915_READ(reg);
3701 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3702 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3703 I915_WRITE(reg, temp);
3706 udelay(2); /* should be 1.5us */
3708 for (i = 0; i < 4; i++) {
3709 reg = FDI_RX_IIR(pipe);
3710 temp = I915_READ(reg);
3711 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3713 if (temp & FDI_RX_SYMBOL_LOCK ||
3714 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3715 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3716 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3720 udelay(2); /* should be 1.5us */
3723 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3727 DRM_DEBUG_KMS("FDI train done.\n");
3730 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3732 struct drm_device *dev = intel_crtc->base.dev;
3733 struct drm_i915_private *dev_priv = dev->dev_private;
3734 int pipe = intel_crtc->pipe;
3738 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3739 reg = FDI_RX_CTL(pipe);
3740 temp = I915_READ(reg);
3741 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3742 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3743 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3744 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3749 /* Switch from Rawclk to PCDclk */
3750 temp = I915_READ(reg);
3751 I915_WRITE(reg, temp | FDI_PCDCLK);
3756 /* Enable CPU FDI TX PLL, always on for Ironlake */
3757 reg = FDI_TX_CTL(pipe);
3758 temp = I915_READ(reg);
3759 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3760 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3767 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3769 struct drm_device *dev = intel_crtc->base.dev;
3770 struct drm_i915_private *dev_priv = dev->dev_private;
3771 int pipe = intel_crtc->pipe;
3774 /* Switch from PCDclk to Rawclk */
3775 reg = FDI_RX_CTL(pipe);
3776 temp = I915_READ(reg);
3777 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3779 /* Disable CPU FDI TX PLL */
3780 reg = FDI_TX_CTL(pipe);
3781 temp = I915_READ(reg);
3782 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3787 reg = FDI_RX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3791 /* Wait for the clocks to turn off. */
3796 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3798 struct drm_device *dev = crtc->dev;
3799 struct drm_i915_private *dev_priv = dev->dev_private;
3800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3801 int pipe = intel_crtc->pipe;
3804 /* disable CPU FDI tx and PCH FDI rx */
3805 reg = FDI_TX_CTL(pipe);
3806 temp = I915_READ(reg);
3807 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3810 reg = FDI_RX_CTL(pipe);
3811 temp = I915_READ(reg);
3812 temp &= ~(0x7 << 16);
3813 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3814 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3819 /* Ironlake workaround, disable clock pointer after downing FDI */
3820 if (HAS_PCH_IBX(dev))
3821 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3823 /* still set train pattern 1 */
3824 reg = FDI_TX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 temp &= ~FDI_LINK_TRAIN_NONE;
3827 temp |= FDI_LINK_TRAIN_PATTERN_1;
3828 I915_WRITE(reg, temp);
3830 reg = FDI_RX_CTL(pipe);
3831 temp = I915_READ(reg);
3832 if (HAS_PCH_CPT(dev)) {
3833 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3834 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3836 temp &= ~FDI_LINK_TRAIN_NONE;
3837 temp |= FDI_LINK_TRAIN_PATTERN_1;
3839 /* BPC in FDI rx is consistent with that in PIPECONF */
3840 temp &= ~(0x07 << 16);
3841 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3842 I915_WRITE(reg, temp);
3848 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3850 struct intel_crtc *crtc;
3852 /* Note that we don't need to be called with mode_config.lock here
3853 * as our list of CRTC objects is static for the lifetime of the
3854 * device and so cannot disappear as we iterate. Similarly, we can
3855 * happily treat the predicates as racy, atomic checks as userspace
3856 * cannot claim and pin a new fb without at least acquring the
3857 * struct_mutex and so serialising with us.
3859 for_each_intel_crtc(dev, crtc) {
3860 if (atomic_read(&crtc->unpin_work_count) == 0)
3863 if (crtc->unpin_work)
3864 intel_wait_for_vblank(dev, crtc->pipe);
3872 static void page_flip_completed(struct intel_crtc *intel_crtc)
3874 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3875 struct intel_unpin_work *work = intel_crtc->unpin_work;
3877 /* ensure that the unpin work is consistent wrt ->pending. */
3879 intel_crtc->unpin_work = NULL;
3882 drm_send_vblank_event(intel_crtc->base.dev,
3886 drm_crtc_vblank_put(&intel_crtc->base);
3888 wake_up_all(&dev_priv->pending_flip_queue);
3889 queue_work(dev_priv->wq, &work->work);
3891 trace_i915_flip_complete(intel_crtc->plane,
3892 work->pending_flip_obj);
3895 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3897 struct drm_device *dev = crtc->dev;
3898 struct drm_i915_private *dev_priv = dev->dev_private;
3900 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3901 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3902 !intel_crtc_has_pending_flip(crtc),
3904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3906 spin_lock_irq(&dev->event_lock);
3907 if (intel_crtc->unpin_work) {
3908 WARN_ONCE(1, "Removing stuck page flip\n");
3909 page_flip_completed(intel_crtc);
3911 spin_unlock_irq(&dev->event_lock);
3914 if (crtc->primary->fb) {
3915 mutex_lock(&dev->struct_mutex);
3916 intel_finish_fb(crtc->primary->fb);
3917 mutex_unlock(&dev->struct_mutex);
3921 /* Program iCLKIP clock to the desired frequency */
3922 static void lpt_program_iclkip(struct drm_crtc *crtc)
3924 struct drm_device *dev = crtc->dev;
3925 struct drm_i915_private *dev_priv = dev->dev_private;
3926 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3927 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3930 mutex_lock(&dev_priv->sb_lock);
3932 /* It is necessary to ungate the pixclk gate prior to programming
3933 * the divisors, and gate it back when it is done.
3935 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3937 /* Disable SSCCTL */
3938 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3939 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3943 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3944 if (clock == 20000) {
3949 /* The iCLK virtual clock root frequency is in MHz,
3950 * but the adjusted_mode->crtc_clock in in KHz. To get the
3951 * divisors, it is necessary to divide one by another, so we
3952 * convert the virtual clock precision to KHz here for higher
3955 u32 iclk_virtual_root_freq = 172800 * 1000;
3956 u32 iclk_pi_range = 64;
3957 u32 desired_divisor, msb_divisor_value, pi_value;
3959 desired_divisor = (iclk_virtual_root_freq / clock);
3960 msb_divisor_value = desired_divisor / iclk_pi_range;
3961 pi_value = desired_divisor % iclk_pi_range;
3964 divsel = msb_divisor_value - 2;
3965 phaseinc = pi_value;
3968 /* This should not happen with any sane values */
3969 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3970 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3971 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3972 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3974 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3981 /* Program SSCDIVINTPHASE6 */
3982 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3983 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3984 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3985 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3986 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3987 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3988 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3989 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3991 /* Program SSCAUXDIV */
3992 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3993 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3994 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3995 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3997 /* Enable modulator and associated divider */
3998 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3999 temp &= ~SBI_SSCCTL_DISABLE;
4000 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4002 /* Wait for initialization time */
4005 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4007 mutex_unlock(&dev_priv->sb_lock);
4010 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4011 enum pipe pch_transcoder)
4013 struct drm_device *dev = crtc->base.dev;
4014 struct drm_i915_private *dev_priv = dev->dev_private;
4015 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4017 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4018 I915_READ(HTOTAL(cpu_transcoder)));
4019 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4020 I915_READ(HBLANK(cpu_transcoder)));
4021 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4022 I915_READ(HSYNC(cpu_transcoder)));
4024 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4025 I915_READ(VTOTAL(cpu_transcoder)));
4026 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4027 I915_READ(VBLANK(cpu_transcoder)));
4028 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4029 I915_READ(VSYNC(cpu_transcoder)));
4030 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4031 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4034 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4036 struct drm_i915_private *dev_priv = dev->dev_private;
4039 temp = I915_READ(SOUTH_CHICKEN1);
4040 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4043 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4044 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4046 temp &= ~FDI_BC_BIFURCATION_SELECT;
4048 temp |= FDI_BC_BIFURCATION_SELECT;
4050 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4051 I915_WRITE(SOUTH_CHICKEN1, temp);
4052 POSTING_READ(SOUTH_CHICKEN1);
4055 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4057 struct drm_device *dev = intel_crtc->base.dev;
4059 switch (intel_crtc->pipe) {
4063 if (intel_crtc->config->fdi_lanes > 2)
4064 cpt_set_fdi_bc_bifurcation(dev, false);
4066 cpt_set_fdi_bc_bifurcation(dev, true);
4070 cpt_set_fdi_bc_bifurcation(dev, true);
4079 * Enable PCH resources required for PCH ports:
4081 * - FDI training & RX/TX
4082 * - update transcoder timings
4083 * - DP transcoding bits
4086 static void ironlake_pch_enable(struct drm_crtc *crtc)
4088 struct drm_device *dev = crtc->dev;
4089 struct drm_i915_private *dev_priv = dev->dev_private;
4090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4091 int pipe = intel_crtc->pipe;
4094 assert_pch_transcoder_disabled(dev_priv, pipe);
4096 if (IS_IVYBRIDGE(dev))
4097 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4099 /* Write the TU size bits before fdi link training, so that error
4100 * detection works. */
4101 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4102 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4104 /* For PCH output, training FDI link */
4105 dev_priv->display.fdi_link_train(crtc);
4107 /* We need to program the right clock selection before writing the pixel
4108 * mutliplier into the DPLL. */
4109 if (HAS_PCH_CPT(dev)) {
4112 temp = I915_READ(PCH_DPLL_SEL);
4113 temp |= TRANS_DPLL_ENABLE(pipe);
4114 sel = TRANS_DPLLB_SEL(pipe);
4115 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4119 I915_WRITE(PCH_DPLL_SEL, temp);
4122 /* XXX: pch pll's can be enabled any time before we enable the PCH
4123 * transcoder, and we actually should do this to not upset any PCH
4124 * transcoder that already use the clock when we share it.
4126 * Note that enable_shared_dpll tries to do the right thing, but
4127 * get_shared_dpll unconditionally resets the pll - we need that to have
4128 * the right LVDS enable sequence. */
4129 intel_enable_shared_dpll(intel_crtc);
4131 /* set transcoder timing, panel must allow it */
4132 assert_panel_unlocked(dev_priv, pipe);
4133 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4135 intel_fdi_normal_train(crtc);
4137 /* For PCH DP, enable TRANS_DP_CTL */
4138 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4139 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4140 reg = TRANS_DP_CTL(pipe);
4141 temp = I915_READ(reg);
4142 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4143 TRANS_DP_SYNC_MASK |
4145 temp |= TRANS_DP_OUTPUT_ENABLE;
4146 temp |= bpc << 9; /* same format but at 11:9 */
4148 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4149 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4150 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4151 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4153 switch (intel_trans_dp_port_sel(crtc)) {
4155 temp |= TRANS_DP_PORT_SEL_B;
4158 temp |= TRANS_DP_PORT_SEL_C;
4161 temp |= TRANS_DP_PORT_SEL_D;
4167 I915_WRITE(reg, temp);
4170 ironlake_enable_pch_transcoder(dev_priv, pipe);
4173 static void lpt_pch_enable(struct drm_crtc *crtc)
4175 struct drm_device *dev = crtc->dev;
4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4180 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4182 lpt_program_iclkip(crtc);
4184 /* Set transcoder timing. */
4185 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4187 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4190 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4191 struct intel_crtc_state *crtc_state)
4193 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4194 struct intel_shared_dpll *pll;
4195 struct intel_shared_dpll_config *shared_dpll;
4196 enum intel_dpll_id i;
4198 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4200 if (HAS_PCH_IBX(dev_priv->dev)) {
4201 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4202 i = (enum intel_dpll_id) crtc->pipe;
4203 pll = &dev_priv->shared_dplls[i];
4205 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4206 crtc->base.base.id, pll->name);
4208 WARN_ON(shared_dpll[i].crtc_mask);
4213 if (IS_BROXTON(dev_priv->dev)) {
4214 /* PLL is attached to port in bxt */
4215 struct intel_encoder *encoder;
4216 struct intel_digital_port *intel_dig_port;
4218 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4219 if (WARN_ON(!encoder))
4222 intel_dig_port = enc_to_dig_port(&encoder->base);
4223 /* 1:1 mapping between ports and PLLs */
4224 i = (enum intel_dpll_id)intel_dig_port->port;
4225 pll = &dev_priv->shared_dplls[i];
4226 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4227 crtc->base.base.id, pll->name);
4228 WARN_ON(shared_dpll[i].crtc_mask);
4233 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4234 pll = &dev_priv->shared_dplls[i];
4236 /* Only want to check enabled timings first */
4237 if (shared_dpll[i].crtc_mask == 0)
4240 if (memcmp(&crtc_state->dpll_hw_state,
4241 &shared_dpll[i].hw_state,
4242 sizeof(crtc_state->dpll_hw_state)) == 0) {
4243 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4244 crtc->base.base.id, pll->name,
4245 shared_dpll[i].crtc_mask,
4251 /* Ok no matching timings, maybe there's a free one? */
4252 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4253 pll = &dev_priv->shared_dplls[i];
4254 if (shared_dpll[i].crtc_mask == 0) {
4255 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4256 crtc->base.base.id, pll->name);
4264 if (shared_dpll[i].crtc_mask == 0)
4265 shared_dpll[i].hw_state =
4266 crtc_state->dpll_hw_state;
4268 crtc_state->shared_dpll = i;
4269 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4270 pipe_name(crtc->pipe));
4272 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4277 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4279 struct drm_i915_private *dev_priv = to_i915(state->dev);
4280 struct intel_shared_dpll_config *shared_dpll;
4281 struct intel_shared_dpll *pll;
4282 enum intel_dpll_id i;
4284 if (!to_intel_atomic_state(state)->dpll_set)
4287 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4288 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4289 pll = &dev_priv->shared_dplls[i];
4290 pll->config = shared_dpll[i];
4294 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4296 struct drm_i915_private *dev_priv = dev->dev_private;
4297 int dslreg = PIPEDSL(pipe);
4300 temp = I915_READ(dslreg);
4302 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4303 if (wait_for(I915_READ(dslreg) != temp, 5))
4304 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4309 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4310 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4311 int src_w, int src_h, int dst_w, int dst_h)
4313 struct intel_crtc_scaler_state *scaler_state =
4314 &crtc_state->scaler_state;
4315 struct intel_crtc *intel_crtc =
4316 to_intel_crtc(crtc_state->base.crtc);
4319 need_scaling = intel_rotation_90_or_270(rotation) ?
4320 (src_h != dst_w || src_w != dst_h):
4321 (src_w != dst_w || src_h != dst_h);
4324 * if plane is being disabled or scaler is no more required or force detach
4325 * - free scaler binded to this plane/crtc
4326 * - in order to do this, update crtc->scaler_usage
4328 * Here scaler state in crtc_state is set free so that
4329 * scaler can be assigned to other user. Actual register
4330 * update to free the scaler is done in plane/panel-fit programming.
4331 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4333 if (force_detach || !need_scaling) {
4334 if (*scaler_id >= 0) {
4335 scaler_state->scaler_users &= ~(1 << scaler_user);
4336 scaler_state->scalers[*scaler_id].in_use = 0;
4338 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4339 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4340 intel_crtc->pipe, scaler_user, *scaler_id,
4341 scaler_state->scaler_users);
4348 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4349 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4351 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4352 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4353 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4354 "size is out of scaler range\n",
4355 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4359 /* mark this plane as a scaler user in crtc_state */
4360 scaler_state->scaler_users |= (1 << scaler_user);
4361 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4362 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4363 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4364 scaler_state->scaler_users);
4370 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4372 * @state: crtc's scaler state
4375 * 0 - scaler_usage updated successfully
4376 * error - requested scaling cannot be supported or other error condition
4378 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4380 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4381 struct drm_display_mode *adjusted_mode =
4382 &state->base.adjusted_mode;
4384 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4385 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4387 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4388 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4389 state->pipe_src_w, state->pipe_src_h,
4390 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4394 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4396 * @state: crtc's scaler state
4397 * @plane_state: atomic plane state to update
4400 * 0 - scaler_usage updated successfully
4401 * error - requested scaling cannot be supported or other error condition
4403 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4404 struct intel_plane_state *plane_state)
4407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4408 struct intel_plane *intel_plane =
4409 to_intel_plane(plane_state->base.plane);
4410 struct drm_framebuffer *fb = plane_state->base.fb;
4413 bool force_detach = !fb || !plane_state->visible;
4415 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4416 intel_plane->base.base.id, intel_crtc->pipe,
4417 drm_plane_index(&intel_plane->base));
4419 ret = skl_update_scaler(crtc_state, force_detach,
4420 drm_plane_index(&intel_plane->base),
4421 &plane_state->scaler_id,
4422 plane_state->base.rotation,
4423 drm_rect_width(&plane_state->src) >> 16,
4424 drm_rect_height(&plane_state->src) >> 16,
4425 drm_rect_width(&plane_state->dst),
4426 drm_rect_height(&plane_state->dst));
4428 if (ret || plane_state->scaler_id < 0)
4431 /* check colorkey */
4432 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4433 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4434 intel_plane->base.base.id);
4438 /* Check src format */
4439 switch (fb->pixel_format) {
4440 case DRM_FORMAT_RGB565:
4441 case DRM_FORMAT_XBGR8888:
4442 case DRM_FORMAT_XRGB8888:
4443 case DRM_FORMAT_ABGR8888:
4444 case DRM_FORMAT_ARGB8888:
4445 case DRM_FORMAT_XRGB2101010:
4446 case DRM_FORMAT_XBGR2101010:
4447 case DRM_FORMAT_YUYV:
4448 case DRM_FORMAT_YVYU:
4449 case DRM_FORMAT_UYVY:
4450 case DRM_FORMAT_VYUY:
4453 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4454 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4461 static void skylake_scaler_disable(struct intel_crtc *crtc)
4465 for (i = 0; i < crtc->num_scalers; i++)
4466 skl_detach_scaler(crtc, i);
4469 static void skylake_pfit_enable(struct intel_crtc *crtc)
4471 struct drm_device *dev = crtc->base.dev;
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 int pipe = crtc->pipe;
4474 struct intel_crtc_scaler_state *scaler_state =
4475 &crtc->config->scaler_state;
4477 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4479 if (crtc->config->pch_pfit.enabled) {
4482 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4483 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4487 id = scaler_state->scaler_id;
4488 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4489 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4490 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4491 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4493 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4497 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4499 struct drm_device *dev = crtc->base.dev;
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501 int pipe = crtc->pipe;
4503 if (crtc->config->pch_pfit.enabled) {
4504 /* Force use of hard-coded filter coefficients
4505 * as some pre-programmed values are broken,
4508 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4509 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4510 PF_PIPE_SEL_IVB(pipe));
4512 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4513 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4514 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4518 void hsw_enable_ips(struct intel_crtc *crtc)
4520 struct drm_device *dev = crtc->base.dev;
4521 struct drm_i915_private *dev_priv = dev->dev_private;
4523 if (!crtc->config->ips_enabled)
4526 /* We can only enable IPS after we enable a plane and wait for a vblank */
4527 intel_wait_for_vblank(dev, crtc->pipe);
4529 assert_plane_enabled(dev_priv, crtc->plane);
4530 if (IS_BROADWELL(dev)) {
4531 mutex_lock(&dev_priv->rps.hw_lock);
4532 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4533 mutex_unlock(&dev_priv->rps.hw_lock);
4534 /* Quoting Art Runyan: "its not safe to expect any particular
4535 * value in IPS_CTL bit 31 after enabling IPS through the
4536 * mailbox." Moreover, the mailbox may return a bogus state,
4537 * so we need to just enable it and continue on.
4540 I915_WRITE(IPS_CTL, IPS_ENABLE);
4541 /* The bit only becomes 1 in the next vblank, so this wait here
4542 * is essentially intel_wait_for_vblank. If we don't have this
4543 * and don't wait for vblanks until the end of crtc_enable, then
4544 * the HW state readout code will complain that the expected
4545 * IPS_CTL value is not the one we read. */
4546 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4547 DRM_ERROR("Timed out waiting for IPS enable\n");
4551 void hsw_disable_ips(struct intel_crtc *crtc)
4553 struct drm_device *dev = crtc->base.dev;
4554 struct drm_i915_private *dev_priv = dev->dev_private;
4556 if (!crtc->config->ips_enabled)
4559 assert_plane_enabled(dev_priv, crtc->plane);
4560 if (IS_BROADWELL(dev)) {
4561 mutex_lock(&dev_priv->rps.hw_lock);
4562 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4563 mutex_unlock(&dev_priv->rps.hw_lock);
4564 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4565 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4566 DRM_ERROR("Timed out waiting for IPS disable\n");
4568 I915_WRITE(IPS_CTL, 0);
4569 POSTING_READ(IPS_CTL);
4572 /* We need to wait for a vblank before we can disable the plane. */
4573 intel_wait_for_vblank(dev, crtc->pipe);
4576 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4577 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4579 struct drm_device *dev = crtc->dev;
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4582 enum pipe pipe = intel_crtc->pipe;
4583 int palreg = PALETTE(pipe);
4585 bool reenable_ips = false;
4587 /* The clocks have to be on to load the palette. */
4588 if (!crtc->state->active)
4591 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4592 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4593 assert_dsi_pll_enabled(dev_priv);
4595 assert_pll_enabled(dev_priv, pipe);
4598 /* use legacy palette for Ironlake */
4599 if (!HAS_GMCH_DISPLAY(dev))
4600 palreg = LGC_PALETTE(pipe);
4602 /* Workaround : Do not read or write the pipe palette/gamma data while
4603 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4605 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4606 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4607 GAMMA_MODE_MODE_SPLIT)) {
4608 hsw_disable_ips(intel_crtc);
4609 reenable_ips = true;
4612 for (i = 0; i < 256; i++) {
4613 I915_WRITE(palreg + 4 * i,
4614 (intel_crtc->lut_r[i] << 16) |
4615 (intel_crtc->lut_g[i] << 8) |
4616 intel_crtc->lut_b[i]);
4620 hsw_enable_ips(intel_crtc);
4623 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4625 if (intel_crtc->overlay) {
4626 struct drm_device *dev = intel_crtc->base.dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4629 mutex_lock(&dev->struct_mutex);
4630 dev_priv->mm.interruptible = false;
4631 (void) intel_overlay_switch_off(intel_crtc->overlay);
4632 dev_priv->mm.interruptible = true;
4633 mutex_unlock(&dev->struct_mutex);
4636 /* Let userspace switch the overlay on again. In most cases userspace
4637 * has to recompute where to put it anyway.
4642 * intel_post_enable_primary - Perform operations after enabling primary plane
4643 * @crtc: the CRTC whose primary plane was just enabled
4645 * Performs potentially sleeping operations that must be done after the primary
4646 * plane is enabled, such as updating FBC and IPS. Note that this may be
4647 * called due to an explicit primary plane update, or due to an implicit
4648 * re-enable that is caused when a sprite plane is updated to no longer
4649 * completely hide the primary plane.
4652 intel_post_enable_primary(struct drm_crtc *crtc)
4654 struct drm_device *dev = crtc->dev;
4655 struct drm_i915_private *dev_priv = dev->dev_private;
4656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4657 int pipe = intel_crtc->pipe;
4660 * BDW signals flip done immediately if the plane
4661 * is disabled, even if the plane enable is already
4662 * armed to occur at the next vblank :(
4664 if (IS_BROADWELL(dev))
4665 intel_wait_for_vblank(dev, pipe);
4668 * FIXME IPS should be fine as long as one plane is
4669 * enabled, but in practice it seems to have problems
4670 * when going from primary only to sprite only and vice
4673 hsw_enable_ips(intel_crtc);
4676 * Gen2 reports pipe underruns whenever all planes are disabled.
4677 * So don't enable underrun reporting before at least some planes
4679 * FIXME: Need to fix the logic to work when we turn off all planes
4680 * but leave the pipe running.
4683 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4685 /* Underruns don't raise interrupts, so check manually. */
4686 if (HAS_GMCH_DISPLAY(dev))
4687 i9xx_check_fifo_underruns(dev_priv);
4691 * intel_pre_disable_primary - Perform operations before disabling primary plane
4692 * @crtc: the CRTC whose primary plane is to be disabled
4694 * Performs potentially sleeping operations that must be done before the
4695 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4696 * be called due to an explicit primary plane update, or due to an implicit
4697 * disable that is caused when a sprite plane completely hides the primary
4701 intel_pre_disable_primary(struct drm_crtc *crtc)
4703 struct drm_device *dev = crtc->dev;
4704 struct drm_i915_private *dev_priv = dev->dev_private;
4705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4706 int pipe = intel_crtc->pipe;
4709 * Gen2 reports pipe underruns whenever all planes are disabled.
4710 * So diasble underrun reporting before all the planes get disabled.
4711 * FIXME: Need to fix the logic to work when we turn off all planes
4712 * but leave the pipe running.
4715 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4718 * Vblank time updates from the shadow to live plane control register
4719 * are blocked if the memory self-refresh mode is active at that
4720 * moment. So to make sure the plane gets truly disabled, disable
4721 * first the self-refresh mode. The self-refresh enable bit in turn
4722 * will be checked/applied by the HW only at the next frame start
4723 * event which is after the vblank start event, so we need to have a
4724 * wait-for-vblank between disabling the plane and the pipe.
4726 if (HAS_GMCH_DISPLAY(dev)) {
4727 intel_set_memory_cxsr(dev_priv, false);
4728 dev_priv->wm.vlv.cxsr = false;
4729 intel_wait_for_vblank(dev, pipe);
4733 * FIXME IPS should be fine as long as one plane is
4734 * enabled, but in practice it seems to have problems
4735 * when going from primary only to sprite only and vice
4738 hsw_disable_ips(intel_crtc);
4741 static void intel_post_plane_update(struct intel_crtc *crtc)
4743 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4744 struct drm_device *dev = crtc->base.dev;
4745 struct drm_i915_private *dev_priv = dev->dev_private;
4746 struct drm_plane *plane;
4748 if (atomic->wait_vblank)
4749 intel_wait_for_vblank(dev, crtc->pipe);
4751 intel_frontbuffer_flip(dev, atomic->fb_bits);
4753 if (atomic->disable_cxsr)
4754 crtc->wm.cxsr_allowed = true;
4756 if (crtc->atomic.update_wm_post)
4757 intel_update_watermarks(&crtc->base);
4759 if (atomic->update_fbc)
4760 intel_fbc_update(dev_priv);
4762 if (atomic->post_enable_primary)
4763 intel_post_enable_primary(&crtc->base);
4765 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4766 intel_update_sprite_watermarks(plane, &crtc->base,
4767 0, 0, 0, false, false);
4769 memset(atomic, 0, sizeof(*atomic));
4772 static void intel_pre_plane_update(struct intel_crtc *crtc)
4774 struct drm_device *dev = crtc->base.dev;
4775 struct drm_i915_private *dev_priv = dev->dev_private;
4776 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4777 struct drm_plane *p;
4779 /* Track fb's for any planes being disabled */
4780 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4781 struct intel_plane *plane = to_intel_plane(p);
4783 mutex_lock(&dev->struct_mutex);
4784 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4785 plane->frontbuffer_bit);
4786 mutex_unlock(&dev->struct_mutex);
4789 if (atomic->wait_for_flips)
4790 intel_crtc_wait_for_pending_flips(&crtc->base);
4792 if (atomic->disable_fbc)
4793 intel_fbc_disable_crtc(crtc);
4795 if (crtc->atomic.disable_ips)
4796 hsw_disable_ips(crtc);
4798 if (atomic->pre_disable_primary)
4799 intel_pre_disable_primary(&crtc->base);
4801 if (atomic->disable_cxsr) {
4802 crtc->wm.cxsr_allowed = false;
4803 intel_set_memory_cxsr(dev_priv, false);
4807 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4809 struct drm_device *dev = crtc->dev;
4810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4811 struct drm_plane *p;
4812 int pipe = intel_crtc->pipe;
4814 intel_crtc_dpms_overlay_disable(intel_crtc);
4816 drm_for_each_plane_mask(p, dev, plane_mask)
4817 to_intel_plane(p)->disable_plane(p, crtc);
4820 * FIXME: Once we grow proper nuclear flip support out of this we need
4821 * to compute the mask of flip planes precisely. For the time being
4822 * consider this a flip to a NULL plane.
4824 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4827 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4829 struct drm_device *dev = crtc->dev;
4830 struct drm_i915_private *dev_priv = dev->dev_private;
4831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4832 struct intel_encoder *encoder;
4833 int pipe = intel_crtc->pipe;
4835 if (WARN_ON(intel_crtc->active))
4838 if (intel_crtc->config->has_pch_encoder)
4839 intel_prepare_shared_dpll(intel_crtc);
4841 if (intel_crtc->config->has_dp_encoder)
4842 intel_dp_set_m_n(intel_crtc, M1_N1);
4844 intel_set_pipe_timings(intel_crtc);
4846 if (intel_crtc->config->has_pch_encoder) {
4847 intel_cpu_transcoder_set_m_n(intel_crtc,
4848 &intel_crtc->config->fdi_m_n, NULL);
4851 ironlake_set_pipeconf(crtc);
4853 intel_crtc->active = true;
4855 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4856 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4858 for_each_encoder_on_crtc(dev, crtc, encoder)
4859 if (encoder->pre_enable)
4860 encoder->pre_enable(encoder);
4862 if (intel_crtc->config->has_pch_encoder) {
4863 /* Note: FDI PLL enabling _must_ be done before we enable the
4864 * cpu pipes, hence this is separate from all the other fdi/pch
4866 ironlake_fdi_pll_enable(intel_crtc);
4868 assert_fdi_tx_disabled(dev_priv, pipe);
4869 assert_fdi_rx_disabled(dev_priv, pipe);
4872 ironlake_pfit_enable(intel_crtc);
4875 * On ILK+ LUT must be loaded before the pipe is running but with
4878 intel_crtc_load_lut(crtc);
4880 intel_update_watermarks(crtc);
4881 intel_enable_pipe(intel_crtc);
4883 if (intel_crtc->config->has_pch_encoder)
4884 ironlake_pch_enable(crtc);
4886 assert_vblank_disabled(crtc);
4887 drm_crtc_vblank_on(crtc);
4889 for_each_encoder_on_crtc(dev, crtc, encoder)
4890 encoder->enable(encoder);
4892 if (HAS_PCH_CPT(dev))
4893 cpt_verify_modeset(dev, intel_crtc->pipe);
4896 /* IPS only exists on ULT machines and is tied to pipe A. */
4897 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4899 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4902 static void haswell_crtc_enable(struct drm_crtc *crtc)
4904 struct drm_device *dev = crtc->dev;
4905 struct drm_i915_private *dev_priv = dev->dev_private;
4906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4907 struct intel_encoder *encoder;
4908 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4909 struct intel_crtc_state *pipe_config =
4910 to_intel_crtc_state(crtc->state);
4912 if (WARN_ON(intel_crtc->active))
4915 if (intel_crtc_to_shared_dpll(intel_crtc))
4916 intel_enable_shared_dpll(intel_crtc);
4918 if (intel_crtc->config->has_dp_encoder)
4919 intel_dp_set_m_n(intel_crtc, M1_N1);
4921 intel_set_pipe_timings(intel_crtc);
4923 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4924 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4925 intel_crtc->config->pixel_multiplier - 1);
4928 if (intel_crtc->config->has_pch_encoder) {
4929 intel_cpu_transcoder_set_m_n(intel_crtc,
4930 &intel_crtc->config->fdi_m_n, NULL);
4933 haswell_set_pipeconf(crtc);
4935 intel_set_pipe_csc(crtc);
4937 intel_crtc->active = true;
4939 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4940 for_each_encoder_on_crtc(dev, crtc, encoder)
4941 if (encoder->pre_enable)
4942 encoder->pre_enable(encoder);
4944 if (intel_crtc->config->has_pch_encoder) {
4945 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4947 dev_priv->display.fdi_link_train(crtc);
4950 intel_ddi_enable_pipe_clock(intel_crtc);
4952 if (INTEL_INFO(dev)->gen == 9)
4953 skylake_pfit_enable(intel_crtc);
4954 else if (INTEL_INFO(dev)->gen < 9)
4955 ironlake_pfit_enable(intel_crtc);
4957 MISSING_CASE(INTEL_INFO(dev)->gen);
4960 * On ILK+ LUT must be loaded before the pipe is running but with
4963 intel_crtc_load_lut(crtc);
4965 intel_ddi_set_pipe_settings(crtc);
4966 intel_ddi_enable_transcoder_func(crtc);
4968 intel_update_watermarks(crtc);
4969 intel_enable_pipe(intel_crtc);
4971 if (intel_crtc->config->has_pch_encoder)
4972 lpt_pch_enable(crtc);
4974 if (intel_crtc->config->dp_encoder_is_mst)
4975 intel_ddi_set_vc_payload_alloc(crtc, true);
4977 assert_vblank_disabled(crtc);
4978 drm_crtc_vblank_on(crtc);
4980 for_each_encoder_on_crtc(dev, crtc, encoder) {
4981 encoder->enable(encoder);
4982 intel_opregion_notify_encoder(encoder, true);
4985 /* If we change the relative order between pipe/planes enabling, we need
4986 * to change the workaround. */
4987 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4988 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4989 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4990 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4994 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4996 struct drm_device *dev = crtc->base.dev;
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 int pipe = crtc->pipe;
5000 /* To avoid upsetting the power well on haswell only disable the pfit if
5001 * it's in use. The hw state code will make sure we get this right. */
5002 if (crtc->config->pch_pfit.enabled) {
5003 I915_WRITE(PF_CTL(pipe), 0);
5004 I915_WRITE(PF_WIN_POS(pipe), 0);
5005 I915_WRITE(PF_WIN_SZ(pipe), 0);
5009 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5011 struct drm_device *dev = crtc->dev;
5012 struct drm_i915_private *dev_priv = dev->dev_private;
5013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5014 struct intel_encoder *encoder;
5015 int pipe = intel_crtc->pipe;
5018 for_each_encoder_on_crtc(dev, crtc, encoder)
5019 encoder->disable(encoder);
5021 drm_crtc_vblank_off(crtc);
5022 assert_vblank_disabled(crtc);
5024 if (intel_crtc->config->has_pch_encoder)
5025 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5027 intel_disable_pipe(intel_crtc);
5029 ironlake_pfit_disable(intel_crtc);
5031 if (intel_crtc->config->has_pch_encoder)
5032 ironlake_fdi_disable(crtc);
5034 for_each_encoder_on_crtc(dev, crtc, encoder)
5035 if (encoder->post_disable)
5036 encoder->post_disable(encoder);
5038 if (intel_crtc->config->has_pch_encoder) {
5039 ironlake_disable_pch_transcoder(dev_priv, pipe);
5041 if (HAS_PCH_CPT(dev)) {
5042 /* disable TRANS_DP_CTL */
5043 reg = TRANS_DP_CTL(pipe);
5044 temp = I915_READ(reg);
5045 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5046 TRANS_DP_PORT_SEL_MASK);
5047 temp |= TRANS_DP_PORT_SEL_NONE;
5048 I915_WRITE(reg, temp);
5050 /* disable DPLL_SEL */
5051 temp = I915_READ(PCH_DPLL_SEL);
5052 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5053 I915_WRITE(PCH_DPLL_SEL, temp);
5056 ironlake_fdi_pll_disable(intel_crtc);
5059 intel_crtc->active = false;
5060 intel_update_watermarks(crtc);
5063 static void haswell_crtc_disable(struct drm_crtc *crtc)
5065 struct drm_device *dev = crtc->dev;
5066 struct drm_i915_private *dev_priv = dev->dev_private;
5067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5068 struct intel_encoder *encoder;
5069 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5071 for_each_encoder_on_crtc(dev, crtc, encoder) {
5072 intel_opregion_notify_encoder(encoder, false);
5073 encoder->disable(encoder);
5076 drm_crtc_vblank_off(crtc);
5077 assert_vblank_disabled(crtc);
5079 if (intel_crtc->config->has_pch_encoder)
5080 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5082 intel_disable_pipe(intel_crtc);
5084 if (intel_crtc->config->dp_encoder_is_mst)
5085 intel_ddi_set_vc_payload_alloc(crtc, false);
5087 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5089 if (INTEL_INFO(dev)->gen == 9)
5090 skylake_scaler_disable(intel_crtc);
5091 else if (INTEL_INFO(dev)->gen < 9)
5092 ironlake_pfit_disable(intel_crtc);
5094 MISSING_CASE(INTEL_INFO(dev)->gen);
5096 intel_ddi_disable_pipe_clock(intel_crtc);
5098 if (intel_crtc->config->has_pch_encoder) {
5099 lpt_disable_pch_transcoder(dev_priv);
5100 intel_ddi_fdi_disable(crtc);
5103 for_each_encoder_on_crtc(dev, crtc, encoder)
5104 if (encoder->post_disable)
5105 encoder->post_disable(encoder);
5107 intel_crtc->active = false;
5108 intel_update_watermarks(crtc);
5111 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5113 struct drm_device *dev = crtc->base.dev;
5114 struct drm_i915_private *dev_priv = dev->dev_private;
5115 struct intel_crtc_state *pipe_config = crtc->config;
5117 if (!pipe_config->gmch_pfit.control)
5121 * The panel fitter should only be adjusted whilst the pipe is disabled,
5122 * according to register description and PRM.
5124 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5125 assert_pipe_disabled(dev_priv, crtc->pipe);
5127 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5128 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5130 /* Border color in case we don't scale up to the full screen. Black by
5131 * default, change to something else for debugging. */
5132 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5135 static enum intel_display_power_domain port_to_power_domain(enum port port)
5139 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5141 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5143 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5145 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5148 return POWER_DOMAIN_PORT_OTHER;
5152 #define for_each_power_domain(domain, mask) \
5153 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5154 if ((1 << (domain)) & (mask))
5156 enum intel_display_power_domain
5157 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5159 struct drm_device *dev = intel_encoder->base.dev;
5160 struct intel_digital_port *intel_dig_port;
5162 switch (intel_encoder->type) {
5163 case INTEL_OUTPUT_UNKNOWN:
5164 /* Only DDI platforms should ever use this output type */
5165 WARN_ON_ONCE(!HAS_DDI(dev));
5166 case INTEL_OUTPUT_DISPLAYPORT:
5167 case INTEL_OUTPUT_HDMI:
5168 case INTEL_OUTPUT_EDP:
5169 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5170 return port_to_power_domain(intel_dig_port->port);
5171 case INTEL_OUTPUT_DP_MST:
5172 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5173 return port_to_power_domain(intel_dig_port->port);
5174 case INTEL_OUTPUT_ANALOG:
5175 return POWER_DOMAIN_PORT_CRT;
5176 case INTEL_OUTPUT_DSI:
5177 return POWER_DOMAIN_PORT_DSI;
5179 return POWER_DOMAIN_PORT_OTHER;
5183 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5185 struct drm_device *dev = crtc->dev;
5186 struct intel_encoder *intel_encoder;
5187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5188 enum pipe pipe = intel_crtc->pipe;
5190 enum transcoder transcoder;
5192 if (!crtc->state->active)
5195 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5197 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5198 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5199 if (intel_crtc->config->pch_pfit.enabled ||
5200 intel_crtc->config->pch_pfit.force_thru)
5201 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5203 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5204 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5209 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5211 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5213 enum intel_display_power_domain domain;
5214 unsigned long domains, new_domains, old_domains;
5216 old_domains = intel_crtc->enabled_power_domains;
5217 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5219 domains = new_domains & ~old_domains;
5221 for_each_power_domain(domain, domains)
5222 intel_display_power_get(dev_priv, domain);
5224 return old_domains & ~new_domains;
5227 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5228 unsigned long domains)
5230 enum intel_display_power_domain domain;
5232 for_each_power_domain(domain, domains)
5233 intel_display_power_put(dev_priv, domain);
5236 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5238 struct drm_device *dev = state->dev;
5239 struct drm_i915_private *dev_priv = dev->dev_private;
5240 unsigned long put_domains[I915_MAX_PIPES] = {};
5241 struct drm_crtc_state *crtc_state;
5242 struct drm_crtc *crtc;
5245 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5246 if (needs_modeset(crtc->state))
5247 put_domains[to_intel_crtc(crtc)->pipe] =
5248 modeset_get_crtc_power_domains(crtc);
5251 if (dev_priv->display.modeset_commit_cdclk) {
5252 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5254 if (cdclk != dev_priv->cdclk_freq &&
5255 !WARN_ON(!state->allow_modeset))
5256 dev_priv->display.modeset_commit_cdclk(state);
5259 for (i = 0; i < I915_MAX_PIPES; i++)
5261 modeset_put_power_domains(dev_priv, put_domains[i]);
5264 static void intel_update_max_cdclk(struct drm_device *dev)
5266 struct drm_i915_private *dev_priv = dev->dev_private;
5268 if (IS_SKYLAKE(dev)) {
5269 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5271 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5272 dev_priv->max_cdclk_freq = 675000;
5273 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5274 dev_priv->max_cdclk_freq = 540000;
5275 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5276 dev_priv->max_cdclk_freq = 450000;
5278 dev_priv->max_cdclk_freq = 337500;
5279 } else if (IS_BROADWELL(dev)) {
5281 * FIXME with extra cooling we can allow
5282 * 540 MHz for ULX and 675 Mhz for ULT.
5283 * How can we know if extra cooling is
5284 * available? PCI ID, VTB, something else?
5286 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5287 dev_priv->max_cdclk_freq = 450000;
5288 else if (IS_BDW_ULX(dev))
5289 dev_priv->max_cdclk_freq = 450000;
5290 else if (IS_BDW_ULT(dev))
5291 dev_priv->max_cdclk_freq = 540000;
5293 dev_priv->max_cdclk_freq = 675000;
5294 } else if (IS_CHERRYVIEW(dev)) {
5295 dev_priv->max_cdclk_freq = 320000;
5296 } else if (IS_VALLEYVIEW(dev)) {
5297 dev_priv->max_cdclk_freq = 400000;
5299 /* otherwise assume cdclk is fixed */
5300 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5303 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5304 dev_priv->max_cdclk_freq);
5307 static void intel_update_cdclk(struct drm_device *dev)
5309 struct drm_i915_private *dev_priv = dev->dev_private;
5311 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5312 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5313 dev_priv->cdclk_freq);
5316 * Program the gmbus_freq based on the cdclk frequency.
5317 * BSpec erroneously claims we should aim for 4MHz, but
5318 * in fact 1MHz is the correct frequency.
5320 if (IS_VALLEYVIEW(dev)) {
5322 * Program the gmbus_freq based on the cdclk frequency.
5323 * BSpec erroneously claims we should aim for 4MHz, but
5324 * in fact 1MHz is the correct frequency.
5326 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5329 if (dev_priv->max_cdclk_freq == 0)
5330 intel_update_max_cdclk(dev);
5333 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5335 struct drm_i915_private *dev_priv = dev->dev_private;
5338 uint32_t current_freq;
5341 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5342 switch (frequency) {
5344 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5345 ratio = BXT_DE_PLL_RATIO(60);
5348 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5349 ratio = BXT_DE_PLL_RATIO(60);
5352 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5353 ratio = BXT_DE_PLL_RATIO(60);
5356 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5357 ratio = BXT_DE_PLL_RATIO(60);
5360 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5361 ratio = BXT_DE_PLL_RATIO(65);
5365 * Bypass frequency with DE PLL disabled. Init ratio, divider
5366 * to suppress GCC warning.
5372 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5377 mutex_lock(&dev_priv->rps.hw_lock);
5378 /* Inform power controller of upcoming frequency change */
5379 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5381 mutex_unlock(&dev_priv->rps.hw_lock);
5384 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5389 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5390 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5391 current_freq = current_freq * 500 + 1000;
5394 * DE PLL has to be disabled when
5395 * - setting to 19.2MHz (bypass, PLL isn't used)
5396 * - before setting to 624MHz (PLL needs toggling)
5397 * - before setting to any frequency from 624MHz (PLL needs toggling)
5399 if (frequency == 19200 || frequency == 624000 ||
5400 current_freq == 624000) {
5401 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5403 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5405 DRM_ERROR("timout waiting for DE PLL unlock\n");
5408 if (frequency != 19200) {
5411 val = I915_READ(BXT_DE_PLL_CTL);
5412 val &= ~BXT_DE_PLL_RATIO_MASK;
5414 I915_WRITE(BXT_DE_PLL_CTL, val);
5416 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5418 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5419 DRM_ERROR("timeout waiting for DE PLL lock\n");
5421 val = I915_READ(CDCLK_CTL);
5422 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5425 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5428 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5429 if (frequency >= 500000)
5430 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5432 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5433 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5434 val |= (frequency - 1000) / 500;
5435 I915_WRITE(CDCLK_CTL, val);
5438 mutex_lock(&dev_priv->rps.hw_lock);
5439 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5440 DIV_ROUND_UP(frequency, 25000));
5441 mutex_unlock(&dev_priv->rps.hw_lock);
5444 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5449 intel_update_cdclk(dev);
5452 void broxton_init_cdclk(struct drm_device *dev)
5454 struct drm_i915_private *dev_priv = dev->dev_private;
5458 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5459 * or else the reset will hang because there is no PCH to respond.
5460 * Move the handshake programming to initialization sequence.
5461 * Previously was left up to BIOS.
5463 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5464 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5465 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5467 /* Enable PG1 for cdclk */
5468 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5470 /* check if cd clock is enabled */
5471 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5472 DRM_DEBUG_KMS("Display already initialized\n");
5478 * - The initial CDCLK needs to be read from VBT.
5479 * Need to make this change after VBT has changes for BXT.
5480 * - check if setting the max (or any) cdclk freq is really necessary
5481 * here, it belongs to modeset time
5483 broxton_set_cdclk(dev, 624000);
5485 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5486 POSTING_READ(DBUF_CTL);
5490 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5491 DRM_ERROR("DBuf power enable timeout!\n");
5494 void broxton_uninit_cdclk(struct drm_device *dev)
5496 struct drm_i915_private *dev_priv = dev->dev_private;
5498 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5499 POSTING_READ(DBUF_CTL);
5503 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5504 DRM_ERROR("DBuf power disable timeout!\n");
5506 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5507 broxton_set_cdclk(dev, 19200);
5509 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5512 static const struct skl_cdclk_entry {
5515 } skl_cdclk_frequencies[] = {
5516 { .freq = 308570, .vco = 8640 },
5517 { .freq = 337500, .vco = 8100 },
5518 { .freq = 432000, .vco = 8640 },
5519 { .freq = 450000, .vco = 8100 },
5520 { .freq = 540000, .vco = 8100 },
5521 { .freq = 617140, .vco = 8640 },
5522 { .freq = 675000, .vco = 8100 },
5525 static unsigned int skl_cdclk_decimal(unsigned int freq)
5527 return (freq - 1000) / 500;
5530 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5534 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5535 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5537 if (e->freq == freq)
5545 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5547 unsigned int min_freq;
5550 /* select the minimum CDCLK before enabling DPLL 0 */
5551 val = I915_READ(CDCLK_CTL);
5552 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5553 val |= CDCLK_FREQ_337_308;
5555 if (required_vco == 8640)
5560 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5562 I915_WRITE(CDCLK_CTL, val);
5563 POSTING_READ(CDCLK_CTL);
5566 * We always enable DPLL0 with the lowest link rate possible, but still
5567 * taking into account the VCO required to operate the eDP panel at the
5568 * desired frequency. The usual DP link rates operate with a VCO of
5569 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5570 * The modeset code is responsible for the selection of the exact link
5571 * rate later on, with the constraint of choosing a frequency that
5572 * works with required_vco.
5574 val = I915_READ(DPLL_CTRL1);
5576 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5577 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5578 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5579 if (required_vco == 8640)
5580 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5583 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5586 I915_WRITE(DPLL_CTRL1, val);
5587 POSTING_READ(DPLL_CTRL1);
5589 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5591 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5592 DRM_ERROR("DPLL0 not locked\n");
5595 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5600 /* inform PCU we want to change CDCLK */
5601 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5602 mutex_lock(&dev_priv->rps.hw_lock);
5603 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5604 mutex_unlock(&dev_priv->rps.hw_lock);
5606 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5609 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5613 for (i = 0; i < 15; i++) {
5614 if (skl_cdclk_pcu_ready(dev_priv))
5622 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5624 struct drm_device *dev = dev_priv->dev;
5625 u32 freq_select, pcu_ack;
5627 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5629 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5630 DRM_ERROR("failed to inform PCU about cdclk change\n");
5638 freq_select = CDCLK_FREQ_450_432;
5642 freq_select = CDCLK_FREQ_540;
5648 freq_select = CDCLK_FREQ_337_308;
5653 freq_select = CDCLK_FREQ_675_617;
5658 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5659 POSTING_READ(CDCLK_CTL);
5661 /* inform PCU of the change */
5662 mutex_lock(&dev_priv->rps.hw_lock);
5663 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5664 mutex_unlock(&dev_priv->rps.hw_lock);
5666 intel_update_cdclk(dev);
5669 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5671 /* disable DBUF power */
5672 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5673 POSTING_READ(DBUF_CTL);
5677 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5678 DRM_ERROR("DBuf power disable timeout\n");
5681 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5682 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5683 DRM_ERROR("Couldn't disable DPLL0\n");
5685 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5688 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5691 unsigned int required_vco;
5693 /* enable PCH reset handshake */
5694 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5695 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5697 /* enable PG1 and Misc I/O */
5698 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5700 /* DPLL0 already enabed !? */
5701 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5702 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5707 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5708 skl_dpll0_enable(dev_priv, required_vco);
5710 /* set CDCLK to the frequency the BIOS chose */
5711 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5713 /* enable DBUF power */
5714 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5715 POSTING_READ(DBUF_CTL);
5719 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5720 DRM_ERROR("DBuf power enable timeout\n");
5723 /* returns HPLL frequency in kHz */
5724 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5726 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5728 /* Obtain SKU information */
5729 mutex_lock(&dev_priv->sb_lock);
5730 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5731 CCK_FUSE_HPLL_FREQ_MASK;
5732 mutex_unlock(&dev_priv->sb_lock);
5734 return vco_freq[hpll_freq] * 1000;
5737 /* Adjust CDclk dividers to allow high res or save power if possible */
5738 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5740 struct drm_i915_private *dev_priv = dev->dev_private;
5743 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5744 != dev_priv->cdclk_freq);
5746 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5748 else if (cdclk == 266667)
5753 mutex_lock(&dev_priv->rps.hw_lock);
5754 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5755 val &= ~DSPFREQGUAR_MASK;
5756 val |= (cmd << DSPFREQGUAR_SHIFT);
5757 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5758 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5759 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5761 DRM_ERROR("timed out waiting for CDclk change\n");
5763 mutex_unlock(&dev_priv->rps.hw_lock);
5765 mutex_lock(&dev_priv->sb_lock);
5767 if (cdclk == 400000) {
5770 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5772 /* adjust cdclk divider */
5773 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5774 val &= ~DISPLAY_FREQUENCY_VALUES;
5776 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5778 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5779 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5781 DRM_ERROR("timed out waiting for CDclk change\n");
5784 /* adjust self-refresh exit latency value */
5785 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5789 * For high bandwidth configs, we set a higher latency in the bunit
5790 * so that the core display fetch happens in time to avoid underruns.
5792 if (cdclk == 400000)
5793 val |= 4500 / 250; /* 4.5 usec */
5795 val |= 3000 / 250; /* 3.0 usec */
5796 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5798 mutex_unlock(&dev_priv->sb_lock);
5800 intel_update_cdclk(dev);
5803 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5805 struct drm_i915_private *dev_priv = dev->dev_private;
5808 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5809 != dev_priv->cdclk_freq);
5818 MISSING_CASE(cdclk);
5823 * Specs are full of misinformation, but testing on actual
5824 * hardware has shown that we just need to write the desired
5825 * CCK divider into the Punit register.
5827 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5829 mutex_lock(&dev_priv->rps.hw_lock);
5830 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5831 val &= ~DSPFREQGUAR_MASK_CHV;
5832 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5833 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5834 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5835 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5837 DRM_ERROR("timed out waiting for CDclk change\n");
5839 mutex_unlock(&dev_priv->rps.hw_lock);
5841 intel_update_cdclk(dev);
5844 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5847 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5848 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5851 * Really only a few cases to deal with, as only 4 CDclks are supported:
5854 * 320/333MHz (depends on HPLL freq)
5856 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5857 * of the lower bin and adjust if needed.
5859 * We seem to get an unstable or solid color picture at 200MHz.
5860 * Not sure what's wrong. For now use 200MHz only when all pipes
5863 if (!IS_CHERRYVIEW(dev_priv) &&
5864 max_pixclk > freq_320*limit/100)
5866 else if (max_pixclk > 266667*limit/100)
5868 else if (max_pixclk > 0)
5874 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5879 * - remove the guardband, it's not needed on BXT
5880 * - set 19.2MHz bypass frequency if there are no active pipes
5882 if (max_pixclk > 576000*9/10)
5884 else if (max_pixclk > 384000*9/10)
5886 else if (max_pixclk > 288000*9/10)
5888 else if (max_pixclk > 144000*9/10)
5894 /* Compute the max pixel clock for new configuration. Uses atomic state if
5895 * that's non-NULL, look at current state otherwise. */
5896 static int intel_mode_max_pixclk(struct drm_device *dev,
5897 struct drm_atomic_state *state)
5899 struct intel_crtc *intel_crtc;
5900 struct intel_crtc_state *crtc_state;
5903 for_each_intel_crtc(dev, intel_crtc) {
5904 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5905 if (IS_ERR(crtc_state))
5906 return PTR_ERR(crtc_state);
5908 if (!crtc_state->base.enable)
5911 max_pixclk = max(max_pixclk,
5912 crtc_state->base.adjusted_mode.crtc_clock);
5918 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5920 struct drm_device *dev = state->dev;
5921 struct drm_i915_private *dev_priv = dev->dev_private;
5922 int max_pixclk = intel_mode_max_pixclk(dev, state);
5927 to_intel_atomic_state(state)->cdclk =
5928 valleyview_calc_cdclk(dev_priv, max_pixclk);
5933 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5935 struct drm_device *dev = state->dev;
5936 struct drm_i915_private *dev_priv = dev->dev_private;
5937 int max_pixclk = intel_mode_max_pixclk(dev, state);
5942 to_intel_atomic_state(state)->cdclk =
5943 broxton_calc_cdclk(dev_priv, max_pixclk);
5948 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5950 unsigned int credits, default_credits;
5952 if (IS_CHERRYVIEW(dev_priv))
5953 default_credits = PFI_CREDIT(12);
5955 default_credits = PFI_CREDIT(8);
5957 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5958 /* CHV suggested value is 31 or 63 */
5959 if (IS_CHERRYVIEW(dev_priv))
5960 credits = PFI_CREDIT_63;
5962 credits = PFI_CREDIT(15);
5964 credits = default_credits;
5968 * WA - write default credits before re-programming
5969 * FIXME: should we also set the resend bit here?
5971 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5974 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5975 credits | PFI_CREDIT_RESEND);
5978 * FIXME is this guaranteed to clear
5979 * immediately or should we poll for it?
5981 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5984 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5986 struct drm_device *dev = old_state->dev;
5987 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5988 struct drm_i915_private *dev_priv = dev->dev_private;
5991 * FIXME: We can end up here with all power domains off, yet
5992 * with a CDCLK frequency other than the minimum. To account
5993 * for this take the PIPE-A power domain, which covers the HW
5994 * blocks needed for the following programming. This can be
5995 * removed once it's guaranteed that we get here either with
5996 * the minimum CDCLK set, or the required power domains
5999 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6001 if (IS_CHERRYVIEW(dev))
6002 cherryview_set_cdclk(dev, req_cdclk);
6004 valleyview_set_cdclk(dev, req_cdclk);
6006 vlv_program_pfi_credits(dev_priv);
6008 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6011 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6013 struct drm_device *dev = crtc->dev;
6014 struct drm_i915_private *dev_priv = to_i915(dev);
6015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6016 struct intel_encoder *encoder;
6017 int pipe = intel_crtc->pipe;
6020 if (WARN_ON(intel_crtc->active))
6023 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6026 if (IS_CHERRYVIEW(dev))
6027 chv_prepare_pll(intel_crtc, intel_crtc->config);
6029 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6032 if (intel_crtc->config->has_dp_encoder)
6033 intel_dp_set_m_n(intel_crtc, M1_N1);
6035 intel_set_pipe_timings(intel_crtc);
6037 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6038 struct drm_i915_private *dev_priv = dev->dev_private;
6040 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6041 I915_WRITE(CHV_CANVAS(pipe), 0);
6044 i9xx_set_pipeconf(intel_crtc);
6046 intel_crtc->active = true;
6048 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6050 for_each_encoder_on_crtc(dev, crtc, encoder)
6051 if (encoder->pre_pll_enable)
6052 encoder->pre_pll_enable(encoder);
6055 if (IS_CHERRYVIEW(dev))
6056 chv_enable_pll(intel_crtc, intel_crtc->config);
6058 vlv_enable_pll(intel_crtc, intel_crtc->config);
6061 for_each_encoder_on_crtc(dev, crtc, encoder)
6062 if (encoder->pre_enable)
6063 encoder->pre_enable(encoder);
6065 i9xx_pfit_enable(intel_crtc);
6067 intel_crtc_load_lut(crtc);
6069 intel_enable_pipe(intel_crtc);
6071 assert_vblank_disabled(crtc);
6072 drm_crtc_vblank_on(crtc);
6074 for_each_encoder_on_crtc(dev, crtc, encoder)
6075 encoder->enable(encoder);
6078 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6080 struct drm_device *dev = crtc->base.dev;
6081 struct drm_i915_private *dev_priv = dev->dev_private;
6083 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6084 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6087 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6089 struct drm_device *dev = crtc->dev;
6090 struct drm_i915_private *dev_priv = to_i915(dev);
6091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6092 struct intel_encoder *encoder;
6093 int pipe = intel_crtc->pipe;
6095 if (WARN_ON(intel_crtc->active))
6098 i9xx_set_pll_dividers(intel_crtc);
6100 if (intel_crtc->config->has_dp_encoder)
6101 intel_dp_set_m_n(intel_crtc, M1_N1);
6103 intel_set_pipe_timings(intel_crtc);
6105 i9xx_set_pipeconf(intel_crtc);
6107 intel_crtc->active = true;
6110 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6112 for_each_encoder_on_crtc(dev, crtc, encoder)
6113 if (encoder->pre_enable)
6114 encoder->pre_enable(encoder);
6116 i9xx_enable_pll(intel_crtc);
6118 i9xx_pfit_enable(intel_crtc);
6120 intel_crtc_load_lut(crtc);
6122 intel_update_watermarks(crtc);
6123 intel_enable_pipe(intel_crtc);
6125 assert_vblank_disabled(crtc);
6126 drm_crtc_vblank_on(crtc);
6128 for_each_encoder_on_crtc(dev, crtc, encoder)
6129 encoder->enable(encoder);
6132 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6134 struct drm_device *dev = crtc->base.dev;
6135 struct drm_i915_private *dev_priv = dev->dev_private;
6137 if (!crtc->config->gmch_pfit.control)
6140 assert_pipe_disabled(dev_priv, crtc->pipe);
6142 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6143 I915_READ(PFIT_CONTROL));
6144 I915_WRITE(PFIT_CONTROL, 0);
6147 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6149 struct drm_device *dev = crtc->dev;
6150 struct drm_i915_private *dev_priv = dev->dev_private;
6151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152 struct intel_encoder *encoder;
6153 int pipe = intel_crtc->pipe;
6156 * On gen2 planes are double buffered but the pipe isn't, so we must
6157 * wait for planes to fully turn off before disabling the pipe.
6158 * We also need to wait on all gmch platforms because of the
6159 * self-refresh mode constraint explained above.
6161 intel_wait_for_vblank(dev, pipe);
6163 for_each_encoder_on_crtc(dev, crtc, encoder)
6164 encoder->disable(encoder);
6166 drm_crtc_vblank_off(crtc);
6167 assert_vblank_disabled(crtc);
6169 intel_disable_pipe(intel_crtc);
6171 i9xx_pfit_disable(intel_crtc);
6173 for_each_encoder_on_crtc(dev, crtc, encoder)
6174 if (encoder->post_disable)
6175 encoder->post_disable(encoder);
6177 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6178 if (IS_CHERRYVIEW(dev))
6179 chv_disable_pll(dev_priv, pipe);
6180 else if (IS_VALLEYVIEW(dev))
6181 vlv_disable_pll(dev_priv, pipe);
6183 i9xx_disable_pll(intel_crtc);
6187 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6189 intel_crtc->active = false;
6190 intel_update_watermarks(crtc);
6193 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6196 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6197 enum intel_display_power_domain domain;
6198 unsigned long domains;
6200 if (!intel_crtc->active)
6203 if (to_intel_plane_state(crtc->primary->state)->visible) {
6204 intel_crtc_wait_for_pending_flips(crtc);
6205 intel_pre_disable_primary(crtc);
6208 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6209 dev_priv->display.crtc_disable(crtc);
6210 intel_disable_shared_dpll(intel_crtc);
6212 domains = intel_crtc->enabled_power_domains;
6213 for_each_power_domain(domain, domains)
6214 intel_display_power_put(dev_priv, domain);
6215 intel_crtc->enabled_power_domains = 0;
6219 * turn all crtc's off, but do not adjust state
6220 * This has to be paired with a call to intel_modeset_setup_hw_state.
6222 int intel_display_suspend(struct drm_device *dev)
6224 struct drm_mode_config *config = &dev->mode_config;
6225 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6226 struct drm_atomic_state *state;
6227 struct drm_crtc *crtc;
6228 unsigned crtc_mask = 0;
6234 lockdep_assert_held(&ctx->ww_ctx);
6235 state = drm_atomic_state_alloc(dev);
6236 if (WARN_ON(!state))
6239 state->acquire_ctx = ctx;
6240 state->allow_modeset = true;
6242 for_each_crtc(dev, crtc) {
6243 struct drm_crtc_state *crtc_state =
6244 drm_atomic_get_crtc_state(state, crtc);
6246 ret = PTR_ERR_OR_ZERO(crtc_state);
6250 if (!crtc_state->active)
6253 crtc_state->active = false;
6254 crtc_mask |= 1 << drm_crtc_index(crtc);
6258 ret = drm_atomic_commit(state);
6261 for_each_crtc(dev, crtc)
6262 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6263 crtc->state->active = true;
6271 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6272 drm_atomic_state_free(state);
6276 /* Master function to enable/disable CRTC and corresponding power wells */
6277 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6279 struct drm_device *dev = crtc->dev;
6280 struct drm_mode_config *config = &dev->mode_config;
6281 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6283 struct intel_crtc_state *pipe_config;
6284 struct drm_atomic_state *state;
6287 if (enable == intel_crtc->active)
6290 if (enable && !crtc->state->enable)
6293 /* this function should be called with drm_modeset_lock_all for now */
6296 lockdep_assert_held(&ctx->ww_ctx);
6298 state = drm_atomic_state_alloc(dev);
6299 if (WARN_ON(!state))
6302 state->acquire_ctx = ctx;
6303 state->allow_modeset = true;
6305 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6306 if (IS_ERR(pipe_config)) {
6307 ret = PTR_ERR(pipe_config);
6310 pipe_config->base.active = enable;
6312 ret = drm_atomic_commit(state);
6317 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6318 drm_atomic_state_free(state);
6323 * Sets the power management mode of the pipe and plane.
6325 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6327 struct drm_device *dev = crtc->dev;
6328 struct intel_encoder *intel_encoder;
6329 bool enable = false;
6331 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6332 enable |= intel_encoder->connectors_active;
6334 intel_crtc_control(crtc, enable);
6337 void intel_encoder_destroy(struct drm_encoder *encoder)
6339 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6341 drm_encoder_cleanup(encoder);
6342 kfree(intel_encoder);
6345 /* Simple dpms helper for encoders with just one connector, no cloning and only
6346 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6347 * state of the entire output pipe. */
6348 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6350 if (mode == DRM_MODE_DPMS_ON) {
6351 encoder->connectors_active = true;
6353 intel_crtc_update_dpms(encoder->base.crtc);
6355 encoder->connectors_active = false;
6357 intel_crtc_update_dpms(encoder->base.crtc);
6361 /* Cross check the actual hw state with our own modeset state tracking (and it's
6362 * internal consistency). */
6363 static void intel_connector_check_state(struct intel_connector *connector)
6365 if (connector->get_hw_state(connector)) {
6366 struct intel_encoder *encoder = connector->encoder;
6367 struct drm_crtc *crtc;
6368 bool encoder_enabled;
6371 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6372 connector->base.base.id,
6373 connector->base.name);
6375 /* there is no real hw state for MST connectors */
6376 if (connector->mst_port)
6379 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6380 "wrong connector dpms state\n");
6381 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6382 "active connector not linked to encoder\n");
6385 I915_STATE_WARN(!encoder->connectors_active,
6386 "encoder->connectors_active not set\n");
6388 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6389 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6390 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6393 crtc = encoder->base.crtc;
6395 I915_STATE_WARN(!crtc->state->enable,
6396 "crtc not enabled\n");
6397 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6398 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6399 "encoder active on the wrong pipe\n");
6404 int intel_connector_init(struct intel_connector *connector)
6406 struct drm_connector_state *connector_state;
6408 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6409 if (!connector_state)
6412 connector->base.state = connector_state;
6416 struct intel_connector *intel_connector_alloc(void)
6418 struct intel_connector *connector;
6420 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6424 if (intel_connector_init(connector) < 0) {
6432 /* Even simpler default implementation, if there's really no special case to
6434 int intel_connector_dpms(struct drm_connector *connector, int mode)
6436 /* All the simple cases only support two dpms states. */
6437 if (mode != DRM_MODE_DPMS_ON)
6438 mode = DRM_MODE_DPMS_OFF;
6440 if (mode == connector->dpms)
6443 connector->dpms = mode;
6445 /* Only need to change hw state when actually enabled */
6446 if (connector->encoder)
6447 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6449 intel_modeset_check_state(connector->dev);
6454 /* Simple connector->get_hw_state implementation for encoders that support only
6455 * one connector and no cloning and hence the encoder state determines the state
6456 * of the connector. */
6457 bool intel_connector_get_hw_state(struct intel_connector *connector)
6460 struct intel_encoder *encoder = connector->encoder;
6462 return encoder->get_hw_state(encoder, &pipe);
6465 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6467 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6468 return crtc_state->fdi_lanes;
6473 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6474 struct intel_crtc_state *pipe_config)
6476 struct drm_atomic_state *state = pipe_config->base.state;
6477 struct intel_crtc *other_crtc;
6478 struct intel_crtc_state *other_crtc_state;
6480 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6481 pipe_name(pipe), pipe_config->fdi_lanes);
6482 if (pipe_config->fdi_lanes > 4) {
6483 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6484 pipe_name(pipe), pipe_config->fdi_lanes);
6488 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6489 if (pipe_config->fdi_lanes > 2) {
6490 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6491 pipe_config->fdi_lanes);
6498 if (INTEL_INFO(dev)->num_pipes == 2)
6501 /* Ivybridge 3 pipe is really complicated */
6506 if (pipe_config->fdi_lanes <= 2)
6509 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6511 intel_atomic_get_crtc_state(state, other_crtc);
6512 if (IS_ERR(other_crtc_state))
6513 return PTR_ERR(other_crtc_state);
6515 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6516 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6517 pipe_name(pipe), pipe_config->fdi_lanes);
6522 if (pipe_config->fdi_lanes > 2) {
6523 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6524 pipe_name(pipe), pipe_config->fdi_lanes);
6528 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6530 intel_atomic_get_crtc_state(state, other_crtc);
6531 if (IS_ERR(other_crtc_state))
6532 return PTR_ERR(other_crtc_state);
6534 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6535 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6545 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6546 struct intel_crtc_state *pipe_config)
6548 struct drm_device *dev = intel_crtc->base.dev;
6549 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6550 int lane, link_bw, fdi_dotclock, ret;
6551 bool needs_recompute = false;
6554 /* FDI is a binary signal running at ~2.7GHz, encoding
6555 * each output octet as 10 bits. The actual frequency
6556 * is stored as a divider into a 100MHz clock, and the
6557 * mode pixel clock is stored in units of 1KHz.
6558 * Hence the bw of each lane in terms of the mode signal
6561 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6563 fdi_dotclock = adjusted_mode->crtc_clock;
6565 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6566 pipe_config->pipe_bpp);
6568 pipe_config->fdi_lanes = lane;
6570 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6571 link_bw, &pipe_config->fdi_m_n);
6573 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6574 intel_crtc->pipe, pipe_config);
6575 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6576 pipe_config->pipe_bpp -= 2*3;
6577 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6578 pipe_config->pipe_bpp);
6579 needs_recompute = true;
6580 pipe_config->bw_constrained = true;
6585 if (needs_recompute)
6591 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6592 struct intel_crtc_state *pipe_config)
6594 if (pipe_config->pipe_bpp > 24)
6597 /* HSW can handle pixel rate up to cdclk? */
6598 if (IS_HASWELL(dev_priv->dev))
6602 * We compare against max which means we must take
6603 * the increased cdclk requirement into account when
6604 * calculating the new cdclk.
6606 * Should measure whether using a lower cdclk w/o IPS
6608 return ilk_pipe_pixel_rate(pipe_config) <=
6609 dev_priv->max_cdclk_freq * 95 / 100;
6612 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6613 struct intel_crtc_state *pipe_config)
6615 struct drm_device *dev = crtc->base.dev;
6616 struct drm_i915_private *dev_priv = dev->dev_private;
6618 pipe_config->ips_enabled = i915.enable_ips &&
6619 hsw_crtc_supports_ips(crtc) &&
6620 pipe_config_supports_ips(dev_priv, pipe_config);
6623 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6624 struct intel_crtc_state *pipe_config)
6626 struct drm_device *dev = crtc->base.dev;
6627 struct drm_i915_private *dev_priv = dev->dev_private;
6628 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6630 /* FIXME should check pixel clock limits on all platforms */
6631 if (INTEL_INFO(dev)->gen < 4) {
6632 int clock_limit = dev_priv->max_cdclk_freq;
6635 * Enable pixel doubling when the dot clock
6636 * is > 90% of the (display) core speed.
6638 * GDG double wide on either pipe,
6639 * otherwise pipe A only.
6641 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6642 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6644 pipe_config->double_wide = true;
6647 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6652 * Pipe horizontal size must be even in:
6654 * - LVDS dual channel mode
6655 * - Double wide pipe
6657 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6658 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6659 pipe_config->pipe_src_w &= ~1;
6661 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6662 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6664 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6665 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6669 hsw_compute_ips_config(crtc, pipe_config);
6671 if (pipe_config->has_pch_encoder)
6672 return ironlake_fdi_compute_config(crtc, pipe_config);
6677 static int skylake_get_display_clock_speed(struct drm_device *dev)
6679 struct drm_i915_private *dev_priv = to_i915(dev);
6680 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6681 uint32_t cdctl = I915_READ(CDCLK_CTL);
6684 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6685 return 24000; /* 24MHz is the cd freq with NSSC ref */
6687 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6690 linkrate = (I915_READ(DPLL_CTRL1) &
6691 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6693 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6694 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6696 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6697 case CDCLK_FREQ_450_432:
6699 case CDCLK_FREQ_337_308:
6701 case CDCLK_FREQ_675_617:
6704 WARN(1, "Unknown cd freq selection\n");
6708 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6709 case CDCLK_FREQ_450_432:
6711 case CDCLK_FREQ_337_308:
6713 case CDCLK_FREQ_675_617:
6716 WARN(1, "Unknown cd freq selection\n");
6720 /* error case, do as if DPLL0 isn't enabled */
6724 static int broxton_get_display_clock_speed(struct drm_device *dev)
6726 struct drm_i915_private *dev_priv = to_i915(dev);
6727 uint32_t cdctl = I915_READ(CDCLK_CTL);
6728 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6729 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6732 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6735 cdclk = 19200 * pll_ratio / 2;
6737 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6738 case BXT_CDCLK_CD2X_DIV_SEL_1:
6739 return cdclk; /* 576MHz or 624MHz */
6740 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6741 return cdclk * 2 / 3; /* 384MHz */
6742 case BXT_CDCLK_CD2X_DIV_SEL_2:
6743 return cdclk / 2; /* 288MHz */
6744 case BXT_CDCLK_CD2X_DIV_SEL_4:
6745 return cdclk / 4; /* 144MHz */
6748 /* error case, do as if DE PLL isn't enabled */
6752 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6754 struct drm_i915_private *dev_priv = dev->dev_private;
6755 uint32_t lcpll = I915_READ(LCPLL_CTL);
6756 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6758 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6760 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6762 else if (freq == LCPLL_CLK_FREQ_450)
6764 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6766 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6772 static int haswell_get_display_clock_speed(struct drm_device *dev)
6774 struct drm_i915_private *dev_priv = dev->dev_private;
6775 uint32_t lcpll = I915_READ(LCPLL_CTL);
6776 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6778 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6780 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6782 else if (freq == LCPLL_CLK_FREQ_450)
6784 else if (IS_HSW_ULT(dev))
6790 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6792 struct drm_i915_private *dev_priv = dev->dev_private;
6796 if (dev_priv->hpll_freq == 0)
6797 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6799 mutex_lock(&dev_priv->sb_lock);
6800 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6801 mutex_unlock(&dev_priv->sb_lock);
6803 divider = val & DISPLAY_FREQUENCY_VALUES;
6805 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6806 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6807 "cdclk change in progress\n");
6809 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6812 static int ilk_get_display_clock_speed(struct drm_device *dev)
6817 static int i945_get_display_clock_speed(struct drm_device *dev)
6822 static int i915_get_display_clock_speed(struct drm_device *dev)
6827 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6832 static int pnv_get_display_clock_speed(struct drm_device *dev)
6836 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6838 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6839 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6841 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6843 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6845 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6848 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6849 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6851 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6856 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6860 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6862 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6865 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6866 case GC_DISPLAY_CLOCK_333_MHZ:
6869 case GC_DISPLAY_CLOCK_190_200_MHZ:
6875 static int i865_get_display_clock_speed(struct drm_device *dev)
6880 static int i85x_get_display_clock_speed(struct drm_device *dev)
6885 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6886 * encoding is different :(
6887 * FIXME is this the right way to detect 852GM/852GMV?
6889 if (dev->pdev->revision == 0x1)
6892 pci_bus_read_config_word(dev->pdev->bus,
6893 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6895 /* Assume that the hardware is in the high speed state. This
6896 * should be the default.
6898 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6899 case GC_CLOCK_133_200:
6900 case GC_CLOCK_133_200_2:
6901 case GC_CLOCK_100_200:
6903 case GC_CLOCK_166_250:
6905 case GC_CLOCK_100_133:
6907 case GC_CLOCK_133_266:
6908 case GC_CLOCK_133_266_2:
6909 case GC_CLOCK_166_266:
6913 /* Shouldn't happen */
6917 static int i830_get_display_clock_speed(struct drm_device *dev)
6922 static unsigned int intel_hpll_vco(struct drm_device *dev)
6924 struct drm_i915_private *dev_priv = dev->dev_private;
6925 static const unsigned int blb_vco[8] = {
6932 static const unsigned int pnv_vco[8] = {
6939 static const unsigned int cl_vco[8] = {
6948 static const unsigned int elk_vco[8] = {
6954 static const unsigned int ctg_vco[8] = {
6962 const unsigned int *vco_table;
6966 /* FIXME other chipsets? */
6968 vco_table = ctg_vco;
6969 else if (IS_G4X(dev))
6970 vco_table = elk_vco;
6971 else if (IS_CRESTLINE(dev))
6973 else if (IS_PINEVIEW(dev))
6974 vco_table = pnv_vco;
6975 else if (IS_G33(dev))
6976 vco_table = blb_vco;
6980 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6982 vco = vco_table[tmp & 0x7];
6984 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6986 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6991 static int gm45_get_display_clock_speed(struct drm_device *dev)
6993 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6996 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6998 cdclk_sel = (tmp >> 12) & 0x1;
7004 return cdclk_sel ? 333333 : 222222;
7006 return cdclk_sel ? 320000 : 228571;
7008 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7013 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7015 static const uint8_t div_3200[] = { 16, 10, 8 };
7016 static const uint8_t div_4000[] = { 20, 12, 10 };
7017 static const uint8_t div_5333[] = { 24, 16, 14 };
7018 const uint8_t *div_table;
7019 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7022 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7024 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7026 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7031 div_table = div_3200;
7034 div_table = div_4000;
7037 div_table = div_5333;
7043 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7046 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7050 static int g33_get_display_clock_speed(struct drm_device *dev)
7052 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7053 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7054 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7055 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7056 const uint8_t *div_table;
7057 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7060 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7062 cdclk_sel = (tmp >> 4) & 0x7;
7064 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7069 div_table = div_3200;
7072 div_table = div_4000;
7075 div_table = div_4800;
7078 div_table = div_5333;
7084 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7087 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7092 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7094 while (*num > DATA_LINK_M_N_MASK ||
7095 *den > DATA_LINK_M_N_MASK) {
7101 static void compute_m_n(unsigned int m, unsigned int n,
7102 uint32_t *ret_m, uint32_t *ret_n)
7104 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7105 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7106 intel_reduce_m_n_ratio(ret_m, ret_n);
7110 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7111 int pixel_clock, int link_clock,
7112 struct intel_link_m_n *m_n)
7116 compute_m_n(bits_per_pixel * pixel_clock,
7117 link_clock * nlanes * 8,
7118 &m_n->gmch_m, &m_n->gmch_n);
7120 compute_m_n(pixel_clock, link_clock,
7121 &m_n->link_m, &m_n->link_n);
7124 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7126 if (i915.panel_use_ssc >= 0)
7127 return i915.panel_use_ssc != 0;
7128 return dev_priv->vbt.lvds_use_ssc
7129 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7132 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7135 struct drm_device *dev = crtc_state->base.crtc->dev;
7136 struct drm_i915_private *dev_priv = dev->dev_private;
7139 WARN_ON(!crtc_state->base.state);
7141 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7143 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7144 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7145 refclk = dev_priv->vbt.lvds_ssc_freq;
7146 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7147 } else if (!IS_GEN2(dev)) {
7156 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7158 return (1 << dpll->n) << 16 | dpll->m2;
7161 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7163 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7166 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7167 struct intel_crtc_state *crtc_state,
7168 intel_clock_t *reduced_clock)
7170 struct drm_device *dev = crtc->base.dev;
7173 if (IS_PINEVIEW(dev)) {
7174 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7176 fp2 = pnv_dpll_compute_fp(reduced_clock);
7178 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7180 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7183 crtc_state->dpll_hw_state.fp0 = fp;
7185 crtc->lowfreq_avail = false;
7186 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7188 crtc_state->dpll_hw_state.fp1 = fp2;
7189 crtc->lowfreq_avail = true;
7191 crtc_state->dpll_hw_state.fp1 = fp;
7195 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7201 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7202 * and set it to a reasonable value instead.
7204 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7205 reg_val &= 0xffffff00;
7206 reg_val |= 0x00000030;
7207 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7209 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7210 reg_val &= 0x8cffffff;
7211 reg_val = 0x8c000000;
7212 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7214 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7215 reg_val &= 0xffffff00;
7216 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7218 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7219 reg_val &= 0x00ffffff;
7220 reg_val |= 0xb0000000;
7221 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7224 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7225 struct intel_link_m_n *m_n)
7227 struct drm_device *dev = crtc->base.dev;
7228 struct drm_i915_private *dev_priv = dev->dev_private;
7229 int pipe = crtc->pipe;
7231 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7232 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7233 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7234 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7237 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7238 struct intel_link_m_n *m_n,
7239 struct intel_link_m_n *m2_n2)
7241 struct drm_device *dev = crtc->base.dev;
7242 struct drm_i915_private *dev_priv = dev->dev_private;
7243 int pipe = crtc->pipe;
7244 enum transcoder transcoder = crtc->config->cpu_transcoder;
7246 if (INTEL_INFO(dev)->gen >= 5) {
7247 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7248 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7249 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7250 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7251 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7252 * for gen < 8) and if DRRS is supported (to make sure the
7253 * registers are not unnecessarily accessed).
7255 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7256 crtc->config->has_drrs) {
7257 I915_WRITE(PIPE_DATA_M2(transcoder),
7258 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7259 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7260 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7261 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7264 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7265 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7266 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7267 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7271 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7273 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7276 dp_m_n = &crtc->config->dp_m_n;
7277 dp_m2_n2 = &crtc->config->dp_m2_n2;
7278 } else if (m_n == M2_N2) {
7281 * M2_N2 registers are not supported. Hence m2_n2 divider value
7282 * needs to be programmed into M1_N1.
7284 dp_m_n = &crtc->config->dp_m2_n2;
7286 DRM_ERROR("Unsupported divider value\n");
7290 if (crtc->config->has_pch_encoder)
7291 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7293 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7296 static void vlv_compute_dpll(struct intel_crtc *crtc,
7297 struct intel_crtc_state *pipe_config)
7302 * Enable DPIO clock input. We should never disable the reference
7303 * clock for pipe B, since VGA hotplug / manual detection depends
7306 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7307 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7308 /* We should never disable this, set it here for state tracking */
7309 if (crtc->pipe == PIPE_B)
7310 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7311 dpll |= DPLL_VCO_ENABLE;
7312 pipe_config->dpll_hw_state.dpll = dpll;
7314 dpll_md = (pipe_config->pixel_multiplier - 1)
7315 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7316 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7319 static void vlv_prepare_pll(struct intel_crtc *crtc,
7320 const struct intel_crtc_state *pipe_config)
7322 struct drm_device *dev = crtc->base.dev;
7323 struct drm_i915_private *dev_priv = dev->dev_private;
7324 int pipe = crtc->pipe;
7326 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7327 u32 coreclk, reg_val;
7329 mutex_lock(&dev_priv->sb_lock);
7331 bestn = pipe_config->dpll.n;
7332 bestm1 = pipe_config->dpll.m1;
7333 bestm2 = pipe_config->dpll.m2;
7334 bestp1 = pipe_config->dpll.p1;
7335 bestp2 = pipe_config->dpll.p2;
7337 /* See eDP HDMI DPIO driver vbios notes doc */
7339 /* PLL B needs special handling */
7341 vlv_pllb_recal_opamp(dev_priv, pipe);
7343 /* Set up Tx target for periodic Rcomp update */
7344 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7346 /* Disable target IRef on PLL */
7347 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7348 reg_val &= 0x00ffffff;
7349 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7351 /* Disable fast lock */
7352 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7354 /* Set idtafcrecal before PLL is enabled */
7355 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7356 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7357 mdiv |= ((bestn << DPIO_N_SHIFT));
7358 mdiv |= (1 << DPIO_K_SHIFT);
7361 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7362 * but we don't support that).
7363 * Note: don't use the DAC post divider as it seems unstable.
7365 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7366 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7368 mdiv |= DPIO_ENABLE_CALIBRATION;
7369 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7371 /* Set HBR and RBR LPF coefficients */
7372 if (pipe_config->port_clock == 162000 ||
7373 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7374 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7375 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7378 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7381 if (pipe_config->has_dp_encoder) {
7382 /* Use SSC source */
7384 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7387 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7389 } else { /* HDMI or VGA */
7390 /* Use bend source */
7392 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7395 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7399 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7400 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7402 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7403 coreclk |= 0x01000000;
7404 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7406 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7407 mutex_unlock(&dev_priv->sb_lock);
7410 static void chv_compute_dpll(struct intel_crtc *crtc,
7411 struct intel_crtc_state *pipe_config)
7413 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7414 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7416 if (crtc->pipe != PIPE_A)
7417 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7419 pipe_config->dpll_hw_state.dpll_md =
7420 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7423 static void chv_prepare_pll(struct intel_crtc *crtc,
7424 const struct intel_crtc_state *pipe_config)
7426 struct drm_device *dev = crtc->base.dev;
7427 struct drm_i915_private *dev_priv = dev->dev_private;
7428 int pipe = crtc->pipe;
7429 int dpll_reg = DPLL(crtc->pipe);
7430 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7431 u32 loopfilter, tribuf_calcntr;
7432 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7436 bestn = pipe_config->dpll.n;
7437 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7438 bestm1 = pipe_config->dpll.m1;
7439 bestm2 = pipe_config->dpll.m2 >> 22;
7440 bestp1 = pipe_config->dpll.p1;
7441 bestp2 = pipe_config->dpll.p2;
7442 vco = pipe_config->dpll.vco;
7447 * Enable Refclk and SSC
7449 I915_WRITE(dpll_reg,
7450 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7452 mutex_lock(&dev_priv->sb_lock);
7454 /* p1 and p2 divider */
7455 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7456 5 << DPIO_CHV_S1_DIV_SHIFT |
7457 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7458 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7459 1 << DPIO_CHV_K_DIV_SHIFT);
7461 /* Feedback post-divider - m2 */
7462 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7464 /* Feedback refclk divider - n and m1 */
7465 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7466 DPIO_CHV_M1_DIV_BY_2 |
7467 1 << DPIO_CHV_N_DIV_SHIFT);
7469 /* M2 fraction division */
7471 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7473 /* M2 fraction division enable */
7474 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7475 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7476 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7478 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7479 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7481 /* Program digital lock detect threshold */
7482 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7483 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7484 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7485 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7487 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7488 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7491 if (vco == 5400000) {
7492 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7493 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7494 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7495 tribuf_calcntr = 0x9;
7496 } else if (vco <= 6200000) {
7497 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7498 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7499 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7500 tribuf_calcntr = 0x9;
7501 } else if (vco <= 6480000) {
7502 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7503 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7504 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7505 tribuf_calcntr = 0x8;
7507 /* Not supported. Apply the same limits as in the max case */
7508 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7509 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7510 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7513 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7515 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7516 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7517 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7518 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7521 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7522 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7525 mutex_unlock(&dev_priv->sb_lock);
7529 * vlv_force_pll_on - forcibly enable just the PLL
7530 * @dev_priv: i915 private structure
7531 * @pipe: pipe PLL to enable
7532 * @dpll: PLL configuration
7534 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7535 * in cases where we need the PLL enabled even when @pipe is not going to
7538 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7539 const struct dpll *dpll)
7541 struct intel_crtc *crtc =
7542 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7543 struct intel_crtc_state pipe_config = {
7544 .base.crtc = &crtc->base,
7545 .pixel_multiplier = 1,
7549 if (IS_CHERRYVIEW(dev)) {
7550 chv_compute_dpll(crtc, &pipe_config);
7551 chv_prepare_pll(crtc, &pipe_config);
7552 chv_enable_pll(crtc, &pipe_config);
7554 vlv_compute_dpll(crtc, &pipe_config);
7555 vlv_prepare_pll(crtc, &pipe_config);
7556 vlv_enable_pll(crtc, &pipe_config);
7561 * vlv_force_pll_off - forcibly disable just the PLL
7562 * @dev_priv: i915 private structure
7563 * @pipe: pipe PLL to disable
7565 * Disable the PLL for @pipe. To be used in cases where we need
7566 * the PLL enabled even when @pipe is not going to be enabled.
7568 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7570 if (IS_CHERRYVIEW(dev))
7571 chv_disable_pll(to_i915(dev), pipe);
7573 vlv_disable_pll(to_i915(dev), pipe);
7576 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7577 struct intel_crtc_state *crtc_state,
7578 intel_clock_t *reduced_clock,
7581 struct drm_device *dev = crtc->base.dev;
7582 struct drm_i915_private *dev_priv = dev->dev_private;
7585 struct dpll *clock = &crtc_state->dpll;
7587 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7589 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7590 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7592 dpll = DPLL_VGA_MODE_DIS;
7594 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7595 dpll |= DPLLB_MODE_LVDS;
7597 dpll |= DPLLB_MODE_DAC_SERIAL;
7599 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7600 dpll |= (crtc_state->pixel_multiplier - 1)
7601 << SDVO_MULTIPLIER_SHIFT_HIRES;
7605 dpll |= DPLL_SDVO_HIGH_SPEED;
7607 if (crtc_state->has_dp_encoder)
7608 dpll |= DPLL_SDVO_HIGH_SPEED;
7610 /* compute bitmask from p1 value */
7611 if (IS_PINEVIEW(dev))
7612 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7614 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7615 if (IS_G4X(dev) && reduced_clock)
7616 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7618 switch (clock->p2) {
7620 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7623 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7626 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7629 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7632 if (INTEL_INFO(dev)->gen >= 4)
7633 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7635 if (crtc_state->sdvo_tv_clock)
7636 dpll |= PLL_REF_INPUT_TVCLKINBC;
7637 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7638 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7639 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7641 dpll |= PLL_REF_INPUT_DREFCLK;
7643 dpll |= DPLL_VCO_ENABLE;
7644 crtc_state->dpll_hw_state.dpll = dpll;
7646 if (INTEL_INFO(dev)->gen >= 4) {
7647 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7648 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7649 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7653 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7654 struct intel_crtc_state *crtc_state,
7655 intel_clock_t *reduced_clock,
7658 struct drm_device *dev = crtc->base.dev;
7659 struct drm_i915_private *dev_priv = dev->dev_private;
7661 struct dpll *clock = &crtc_state->dpll;
7663 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7665 dpll = DPLL_VGA_MODE_DIS;
7667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7668 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7671 dpll |= PLL_P1_DIVIDE_BY_TWO;
7673 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7675 dpll |= PLL_P2_DIVIDE_BY_4;
7678 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7679 dpll |= DPLL_DVO_2X_MODE;
7681 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7682 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7683 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7685 dpll |= PLL_REF_INPUT_DREFCLK;
7687 dpll |= DPLL_VCO_ENABLE;
7688 crtc_state->dpll_hw_state.dpll = dpll;
7691 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7693 struct drm_device *dev = intel_crtc->base.dev;
7694 struct drm_i915_private *dev_priv = dev->dev_private;
7695 enum pipe pipe = intel_crtc->pipe;
7696 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7697 struct drm_display_mode *adjusted_mode =
7698 &intel_crtc->config->base.adjusted_mode;
7699 uint32_t crtc_vtotal, crtc_vblank_end;
7702 /* We need to be careful not to changed the adjusted mode, for otherwise
7703 * the hw state checker will get angry at the mismatch. */
7704 crtc_vtotal = adjusted_mode->crtc_vtotal;
7705 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7707 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7708 /* the chip adds 2 halflines automatically */
7710 crtc_vblank_end -= 1;
7712 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7713 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7715 vsyncshift = adjusted_mode->crtc_hsync_start -
7716 adjusted_mode->crtc_htotal / 2;
7718 vsyncshift += adjusted_mode->crtc_htotal;
7721 if (INTEL_INFO(dev)->gen > 3)
7722 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7724 I915_WRITE(HTOTAL(cpu_transcoder),
7725 (adjusted_mode->crtc_hdisplay - 1) |
7726 ((adjusted_mode->crtc_htotal - 1) << 16));
7727 I915_WRITE(HBLANK(cpu_transcoder),
7728 (adjusted_mode->crtc_hblank_start - 1) |
7729 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7730 I915_WRITE(HSYNC(cpu_transcoder),
7731 (adjusted_mode->crtc_hsync_start - 1) |
7732 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7734 I915_WRITE(VTOTAL(cpu_transcoder),
7735 (adjusted_mode->crtc_vdisplay - 1) |
7736 ((crtc_vtotal - 1) << 16));
7737 I915_WRITE(VBLANK(cpu_transcoder),
7738 (adjusted_mode->crtc_vblank_start - 1) |
7739 ((crtc_vblank_end - 1) << 16));
7740 I915_WRITE(VSYNC(cpu_transcoder),
7741 (adjusted_mode->crtc_vsync_start - 1) |
7742 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7744 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7745 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7746 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7748 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7749 (pipe == PIPE_B || pipe == PIPE_C))
7750 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7752 /* pipesrc controls the size that is scaled from, which should
7753 * always be the user's requested size.
7755 I915_WRITE(PIPESRC(pipe),
7756 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7757 (intel_crtc->config->pipe_src_h - 1));
7760 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7761 struct intel_crtc_state *pipe_config)
7763 struct drm_device *dev = crtc->base.dev;
7764 struct drm_i915_private *dev_priv = dev->dev_private;
7765 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7768 tmp = I915_READ(HTOTAL(cpu_transcoder));
7769 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7770 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7771 tmp = I915_READ(HBLANK(cpu_transcoder));
7772 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7773 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7774 tmp = I915_READ(HSYNC(cpu_transcoder));
7775 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7776 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7778 tmp = I915_READ(VTOTAL(cpu_transcoder));
7779 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7780 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7781 tmp = I915_READ(VBLANK(cpu_transcoder));
7782 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7783 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7784 tmp = I915_READ(VSYNC(cpu_transcoder));
7785 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7786 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7788 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7789 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7790 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7791 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7794 tmp = I915_READ(PIPESRC(crtc->pipe));
7795 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7796 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7798 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7799 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7802 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7803 struct intel_crtc_state *pipe_config)
7805 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7806 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7807 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7808 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7810 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7811 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7812 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7813 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7815 mode->flags = pipe_config->base.adjusted_mode.flags;
7816 mode->type = DRM_MODE_TYPE_DRIVER;
7818 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7819 mode->flags |= pipe_config->base.adjusted_mode.flags;
7821 mode->hsync = drm_mode_hsync(mode);
7822 mode->vrefresh = drm_mode_vrefresh(mode);
7823 drm_mode_set_name(mode);
7826 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7828 struct drm_device *dev = intel_crtc->base.dev;
7829 struct drm_i915_private *dev_priv = dev->dev_private;
7834 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7835 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7836 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7838 if (intel_crtc->config->double_wide)
7839 pipeconf |= PIPECONF_DOUBLE_WIDE;
7841 /* only g4x and later have fancy bpc/dither controls */
7842 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7843 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7844 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7845 pipeconf |= PIPECONF_DITHER_EN |
7846 PIPECONF_DITHER_TYPE_SP;
7848 switch (intel_crtc->config->pipe_bpp) {
7850 pipeconf |= PIPECONF_6BPC;
7853 pipeconf |= PIPECONF_8BPC;
7856 pipeconf |= PIPECONF_10BPC;
7859 /* Case prevented by intel_choose_pipe_bpp_dither. */
7864 if (HAS_PIPE_CXSR(dev)) {
7865 if (intel_crtc->lowfreq_avail) {
7866 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7867 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7869 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7873 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7874 if (INTEL_INFO(dev)->gen < 4 ||
7875 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7876 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7878 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7880 pipeconf |= PIPECONF_PROGRESSIVE;
7882 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7883 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7885 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7886 POSTING_READ(PIPECONF(intel_crtc->pipe));
7889 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7890 struct intel_crtc_state *crtc_state)
7892 struct drm_device *dev = crtc->base.dev;
7893 struct drm_i915_private *dev_priv = dev->dev_private;
7894 int refclk, num_connectors = 0;
7895 intel_clock_t clock;
7897 bool is_dsi = false;
7898 struct intel_encoder *encoder;
7899 const intel_limit_t *limit;
7900 struct drm_atomic_state *state = crtc_state->base.state;
7901 struct drm_connector *connector;
7902 struct drm_connector_state *connector_state;
7905 memset(&crtc_state->dpll_hw_state, 0,
7906 sizeof(crtc_state->dpll_hw_state));
7908 for_each_connector_in_state(state, connector, connector_state, i) {
7909 if (connector_state->crtc != &crtc->base)
7912 encoder = to_intel_encoder(connector_state->best_encoder);
7914 switch (encoder->type) {
7915 case INTEL_OUTPUT_DSI:
7928 if (!crtc_state->clock_set) {
7929 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7932 * Returns a set of divisors for the desired target clock with
7933 * the given refclk, or FALSE. The returned values represent
7934 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7937 limit = intel_limit(crtc_state, refclk);
7938 ok = dev_priv->display.find_dpll(limit, crtc_state,
7939 crtc_state->port_clock,
7940 refclk, NULL, &clock);
7942 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7946 /* Compat-code for transition, will disappear. */
7947 crtc_state->dpll.n = clock.n;
7948 crtc_state->dpll.m1 = clock.m1;
7949 crtc_state->dpll.m2 = clock.m2;
7950 crtc_state->dpll.p1 = clock.p1;
7951 crtc_state->dpll.p2 = clock.p2;
7955 i8xx_compute_dpll(crtc, crtc_state, NULL,
7957 } else if (IS_CHERRYVIEW(dev)) {
7958 chv_compute_dpll(crtc, crtc_state);
7959 } else if (IS_VALLEYVIEW(dev)) {
7960 vlv_compute_dpll(crtc, crtc_state);
7962 i9xx_compute_dpll(crtc, crtc_state, NULL,
7969 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7970 struct intel_crtc_state *pipe_config)
7972 struct drm_device *dev = crtc->base.dev;
7973 struct drm_i915_private *dev_priv = dev->dev_private;
7976 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7979 tmp = I915_READ(PFIT_CONTROL);
7980 if (!(tmp & PFIT_ENABLE))
7983 /* Check whether the pfit is attached to our pipe. */
7984 if (INTEL_INFO(dev)->gen < 4) {
7985 if (crtc->pipe != PIPE_B)
7988 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7992 pipe_config->gmch_pfit.control = tmp;
7993 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7994 if (INTEL_INFO(dev)->gen < 5)
7995 pipe_config->gmch_pfit.lvds_border_bits =
7996 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7999 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8000 struct intel_crtc_state *pipe_config)
8002 struct drm_device *dev = crtc->base.dev;
8003 struct drm_i915_private *dev_priv = dev->dev_private;
8004 int pipe = pipe_config->cpu_transcoder;
8005 intel_clock_t clock;
8007 int refclk = 100000;
8009 /* In case of MIPI DPLL will not even be used */
8010 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8013 mutex_lock(&dev_priv->sb_lock);
8014 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8015 mutex_unlock(&dev_priv->sb_lock);
8017 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8018 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8019 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8020 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8021 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8023 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8027 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8028 struct intel_initial_plane_config *plane_config)
8030 struct drm_device *dev = crtc->base.dev;
8031 struct drm_i915_private *dev_priv = dev->dev_private;
8032 u32 val, base, offset;
8033 int pipe = crtc->pipe, plane = crtc->plane;
8034 int fourcc, pixel_format;
8035 unsigned int aligned_height;
8036 struct drm_framebuffer *fb;
8037 struct intel_framebuffer *intel_fb;
8039 val = I915_READ(DSPCNTR(plane));
8040 if (!(val & DISPLAY_PLANE_ENABLE))
8043 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8045 DRM_DEBUG_KMS("failed to alloc fb\n");
8049 fb = &intel_fb->base;
8051 if (INTEL_INFO(dev)->gen >= 4) {
8052 if (val & DISPPLANE_TILED) {
8053 plane_config->tiling = I915_TILING_X;
8054 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8058 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8059 fourcc = i9xx_format_to_fourcc(pixel_format);
8060 fb->pixel_format = fourcc;
8061 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8063 if (INTEL_INFO(dev)->gen >= 4) {
8064 if (plane_config->tiling)
8065 offset = I915_READ(DSPTILEOFF(plane));
8067 offset = I915_READ(DSPLINOFF(plane));
8068 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8070 base = I915_READ(DSPADDR(plane));
8072 plane_config->base = base;
8074 val = I915_READ(PIPESRC(pipe));
8075 fb->width = ((val >> 16) & 0xfff) + 1;
8076 fb->height = ((val >> 0) & 0xfff) + 1;
8078 val = I915_READ(DSPSTRIDE(pipe));
8079 fb->pitches[0] = val & 0xffffffc0;
8081 aligned_height = intel_fb_align_height(dev, fb->height,
8085 plane_config->size = fb->pitches[0] * aligned_height;
8087 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8088 pipe_name(pipe), plane, fb->width, fb->height,
8089 fb->bits_per_pixel, base, fb->pitches[0],
8090 plane_config->size);
8092 plane_config->fb = intel_fb;
8095 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8096 struct intel_crtc_state *pipe_config)
8098 struct drm_device *dev = crtc->base.dev;
8099 struct drm_i915_private *dev_priv = dev->dev_private;
8100 int pipe = pipe_config->cpu_transcoder;
8101 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8102 intel_clock_t clock;
8103 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8104 int refclk = 100000;
8106 mutex_lock(&dev_priv->sb_lock);
8107 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8108 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8109 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8110 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8111 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8112 mutex_unlock(&dev_priv->sb_lock);
8114 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8115 clock.m2 = (pll_dw0 & 0xff) << 22;
8116 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8117 clock.m2 |= pll_dw2 & 0x3fffff;
8118 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8119 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8120 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8122 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8125 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8126 struct intel_crtc_state *pipe_config)
8128 struct drm_device *dev = crtc->base.dev;
8129 struct drm_i915_private *dev_priv = dev->dev_private;
8132 if (!intel_display_power_is_enabled(dev_priv,
8133 POWER_DOMAIN_PIPE(crtc->pipe)))
8136 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8137 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8139 tmp = I915_READ(PIPECONF(crtc->pipe));
8140 if (!(tmp & PIPECONF_ENABLE))
8143 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8144 switch (tmp & PIPECONF_BPC_MASK) {
8146 pipe_config->pipe_bpp = 18;
8149 pipe_config->pipe_bpp = 24;
8151 case PIPECONF_10BPC:
8152 pipe_config->pipe_bpp = 30;
8159 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8160 pipe_config->limited_color_range = true;
8162 if (INTEL_INFO(dev)->gen < 4)
8163 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8165 intel_get_pipe_timings(crtc, pipe_config);
8167 i9xx_get_pfit_config(crtc, pipe_config);
8169 if (INTEL_INFO(dev)->gen >= 4) {
8170 tmp = I915_READ(DPLL_MD(crtc->pipe));
8171 pipe_config->pixel_multiplier =
8172 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8173 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8174 pipe_config->dpll_hw_state.dpll_md = tmp;
8175 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8176 tmp = I915_READ(DPLL(crtc->pipe));
8177 pipe_config->pixel_multiplier =
8178 ((tmp & SDVO_MULTIPLIER_MASK)
8179 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8181 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8182 * port and will be fixed up in the encoder->get_config
8184 pipe_config->pixel_multiplier = 1;
8186 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8187 if (!IS_VALLEYVIEW(dev)) {
8189 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8190 * on 830. Filter it out here so that we don't
8191 * report errors due to that.
8194 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8196 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8197 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8199 /* Mask out read-only status bits. */
8200 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8201 DPLL_PORTC_READY_MASK |
8202 DPLL_PORTB_READY_MASK);
8205 if (IS_CHERRYVIEW(dev))
8206 chv_crtc_clock_get(crtc, pipe_config);
8207 else if (IS_VALLEYVIEW(dev))
8208 vlv_crtc_clock_get(crtc, pipe_config);
8210 i9xx_crtc_clock_get(crtc, pipe_config);
8215 static void ironlake_init_pch_refclk(struct drm_device *dev)
8217 struct drm_i915_private *dev_priv = dev->dev_private;
8218 struct intel_encoder *encoder;
8220 bool has_lvds = false;
8221 bool has_cpu_edp = false;
8222 bool has_panel = false;
8223 bool has_ck505 = false;
8224 bool can_ssc = false;
8226 /* We need to take the global config into account */
8227 for_each_intel_encoder(dev, encoder) {
8228 switch (encoder->type) {
8229 case INTEL_OUTPUT_LVDS:
8233 case INTEL_OUTPUT_EDP:
8235 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8243 if (HAS_PCH_IBX(dev)) {
8244 has_ck505 = dev_priv->vbt.display_clock_mode;
8245 can_ssc = has_ck505;
8251 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8252 has_panel, has_lvds, has_ck505);
8254 /* Ironlake: try to setup display ref clock before DPLL
8255 * enabling. This is only under driver's control after
8256 * PCH B stepping, previous chipset stepping should be
8257 * ignoring this setting.
8259 val = I915_READ(PCH_DREF_CONTROL);
8261 /* As we must carefully and slowly disable/enable each source in turn,
8262 * compute the final state we want first and check if we need to
8263 * make any changes at all.
8266 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8268 final |= DREF_NONSPREAD_CK505_ENABLE;
8270 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8272 final &= ~DREF_SSC_SOURCE_MASK;
8273 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8274 final &= ~DREF_SSC1_ENABLE;
8277 final |= DREF_SSC_SOURCE_ENABLE;
8279 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8280 final |= DREF_SSC1_ENABLE;
8283 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8284 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8286 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8288 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8290 final |= DREF_SSC_SOURCE_DISABLE;
8291 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8297 /* Always enable nonspread source */
8298 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8301 val |= DREF_NONSPREAD_CK505_ENABLE;
8303 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8306 val &= ~DREF_SSC_SOURCE_MASK;
8307 val |= DREF_SSC_SOURCE_ENABLE;
8309 /* SSC must be turned on before enabling the CPU output */
8310 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8311 DRM_DEBUG_KMS("Using SSC on panel\n");
8312 val |= DREF_SSC1_ENABLE;
8314 val &= ~DREF_SSC1_ENABLE;
8316 /* Get SSC going before enabling the outputs */
8317 I915_WRITE(PCH_DREF_CONTROL, val);
8318 POSTING_READ(PCH_DREF_CONTROL);
8321 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8323 /* Enable CPU source on CPU attached eDP */
8325 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8326 DRM_DEBUG_KMS("Using SSC on eDP\n");
8327 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8329 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8331 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8333 I915_WRITE(PCH_DREF_CONTROL, val);
8334 POSTING_READ(PCH_DREF_CONTROL);
8337 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8339 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8341 /* Turn off CPU output */
8342 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8344 I915_WRITE(PCH_DREF_CONTROL, val);
8345 POSTING_READ(PCH_DREF_CONTROL);
8348 /* Turn off the SSC source */
8349 val &= ~DREF_SSC_SOURCE_MASK;
8350 val |= DREF_SSC_SOURCE_DISABLE;
8353 val &= ~DREF_SSC1_ENABLE;
8355 I915_WRITE(PCH_DREF_CONTROL, val);
8356 POSTING_READ(PCH_DREF_CONTROL);
8360 BUG_ON(val != final);
8363 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8367 tmp = I915_READ(SOUTH_CHICKEN2);
8368 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8369 I915_WRITE(SOUTH_CHICKEN2, tmp);
8371 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8372 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8373 DRM_ERROR("FDI mPHY reset assert timeout\n");
8375 tmp = I915_READ(SOUTH_CHICKEN2);
8376 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8377 I915_WRITE(SOUTH_CHICKEN2, tmp);
8379 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8380 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8381 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8384 /* WaMPhyProgramming:hsw */
8385 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8389 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8390 tmp &= ~(0xFF << 24);
8391 tmp |= (0x12 << 24);
8392 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8394 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8396 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8398 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8400 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8402 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8403 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8404 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8406 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8407 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8408 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8410 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8413 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8415 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8418 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8420 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8423 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8425 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8428 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8430 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8431 tmp &= ~(0xFF << 16);
8432 tmp |= (0x1C << 16);
8433 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8435 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8436 tmp &= ~(0xFF << 16);
8437 tmp |= (0x1C << 16);
8438 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8440 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8442 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8444 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8446 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8448 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8449 tmp &= ~(0xF << 28);
8451 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8453 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8454 tmp &= ~(0xF << 28);
8456 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8459 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8460 * Programming" based on the parameters passed:
8461 * - Sequence to enable CLKOUT_DP
8462 * - Sequence to enable CLKOUT_DP without spread
8463 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8465 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8468 struct drm_i915_private *dev_priv = dev->dev_private;
8471 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8473 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8474 with_fdi, "LP PCH doesn't have FDI\n"))
8477 mutex_lock(&dev_priv->sb_lock);
8479 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8480 tmp &= ~SBI_SSCCTL_DISABLE;
8481 tmp |= SBI_SSCCTL_PATHALT;
8482 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8487 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8488 tmp &= ~SBI_SSCCTL_PATHALT;
8489 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8492 lpt_reset_fdi_mphy(dev_priv);
8493 lpt_program_fdi_mphy(dev_priv);
8497 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8498 SBI_GEN0 : SBI_DBUFF0;
8499 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8500 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8501 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8503 mutex_unlock(&dev_priv->sb_lock);
8506 /* Sequence to disable CLKOUT_DP */
8507 static void lpt_disable_clkout_dp(struct drm_device *dev)
8509 struct drm_i915_private *dev_priv = dev->dev_private;
8512 mutex_lock(&dev_priv->sb_lock);
8514 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8515 SBI_GEN0 : SBI_DBUFF0;
8516 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8517 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8518 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8520 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8521 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8522 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8523 tmp |= SBI_SSCCTL_PATHALT;
8524 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8527 tmp |= SBI_SSCCTL_DISABLE;
8528 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8531 mutex_unlock(&dev_priv->sb_lock);
8534 static void lpt_init_pch_refclk(struct drm_device *dev)
8536 struct intel_encoder *encoder;
8537 bool has_vga = false;
8539 for_each_intel_encoder(dev, encoder) {
8540 switch (encoder->type) {
8541 case INTEL_OUTPUT_ANALOG:
8550 lpt_enable_clkout_dp(dev, true, true);
8552 lpt_disable_clkout_dp(dev);
8556 * Initialize reference clocks when the driver loads
8558 void intel_init_pch_refclk(struct drm_device *dev)
8560 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8561 ironlake_init_pch_refclk(dev);
8562 else if (HAS_PCH_LPT(dev))
8563 lpt_init_pch_refclk(dev);
8566 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8568 struct drm_device *dev = crtc_state->base.crtc->dev;
8569 struct drm_i915_private *dev_priv = dev->dev_private;
8570 struct drm_atomic_state *state = crtc_state->base.state;
8571 struct drm_connector *connector;
8572 struct drm_connector_state *connector_state;
8573 struct intel_encoder *encoder;
8574 int num_connectors = 0, i;
8575 bool is_lvds = false;
8577 for_each_connector_in_state(state, connector, connector_state, i) {
8578 if (connector_state->crtc != crtc_state->base.crtc)
8581 encoder = to_intel_encoder(connector_state->best_encoder);
8583 switch (encoder->type) {
8584 case INTEL_OUTPUT_LVDS:
8593 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8594 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8595 dev_priv->vbt.lvds_ssc_freq);
8596 return dev_priv->vbt.lvds_ssc_freq;
8602 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8604 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8606 int pipe = intel_crtc->pipe;
8611 switch (intel_crtc->config->pipe_bpp) {
8613 val |= PIPECONF_6BPC;
8616 val |= PIPECONF_8BPC;
8619 val |= PIPECONF_10BPC;
8622 val |= PIPECONF_12BPC;
8625 /* Case prevented by intel_choose_pipe_bpp_dither. */
8629 if (intel_crtc->config->dither)
8630 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8632 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8633 val |= PIPECONF_INTERLACED_ILK;
8635 val |= PIPECONF_PROGRESSIVE;
8637 if (intel_crtc->config->limited_color_range)
8638 val |= PIPECONF_COLOR_RANGE_SELECT;
8640 I915_WRITE(PIPECONF(pipe), val);
8641 POSTING_READ(PIPECONF(pipe));
8645 * Set up the pipe CSC unit.
8647 * Currently only full range RGB to limited range RGB conversion
8648 * is supported, but eventually this should handle various
8649 * RGB<->YCbCr scenarios as well.
8651 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8653 struct drm_device *dev = crtc->dev;
8654 struct drm_i915_private *dev_priv = dev->dev_private;
8655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8656 int pipe = intel_crtc->pipe;
8657 uint16_t coeff = 0x7800; /* 1.0 */
8660 * TODO: Check what kind of values actually come out of the pipe
8661 * with these coeff/postoff values and adjust to get the best
8662 * accuracy. Perhaps we even need to take the bpc value into
8666 if (intel_crtc->config->limited_color_range)
8667 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8670 * GY/GU and RY/RU should be the other way around according
8671 * to BSpec, but reality doesn't agree. Just set them up in
8672 * a way that results in the correct picture.
8674 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8675 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8677 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8678 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8680 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8681 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8683 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8684 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8685 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8687 if (INTEL_INFO(dev)->gen > 6) {
8688 uint16_t postoff = 0;
8690 if (intel_crtc->config->limited_color_range)
8691 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8693 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8694 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8695 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8697 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8699 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8701 if (intel_crtc->config->limited_color_range)
8702 mode |= CSC_BLACK_SCREEN_OFFSET;
8704 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8708 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8710 struct drm_device *dev = crtc->dev;
8711 struct drm_i915_private *dev_priv = dev->dev_private;
8712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8713 enum pipe pipe = intel_crtc->pipe;
8714 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8719 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8720 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8722 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8723 val |= PIPECONF_INTERLACED_ILK;
8725 val |= PIPECONF_PROGRESSIVE;
8727 I915_WRITE(PIPECONF(cpu_transcoder), val);
8728 POSTING_READ(PIPECONF(cpu_transcoder));
8730 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8731 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8733 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8736 switch (intel_crtc->config->pipe_bpp) {
8738 val |= PIPEMISC_DITHER_6_BPC;
8741 val |= PIPEMISC_DITHER_8_BPC;
8744 val |= PIPEMISC_DITHER_10_BPC;
8747 val |= PIPEMISC_DITHER_12_BPC;
8750 /* Case prevented by pipe_config_set_bpp. */
8754 if (intel_crtc->config->dither)
8755 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8757 I915_WRITE(PIPEMISC(pipe), val);
8761 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8762 struct intel_crtc_state *crtc_state,
8763 intel_clock_t *clock,
8764 bool *has_reduced_clock,
8765 intel_clock_t *reduced_clock)
8767 struct drm_device *dev = crtc->dev;
8768 struct drm_i915_private *dev_priv = dev->dev_private;
8770 const intel_limit_t *limit;
8773 refclk = ironlake_get_refclk(crtc_state);
8776 * Returns a set of divisors for the desired target clock with the given
8777 * refclk, or FALSE. The returned values represent the clock equation:
8778 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8780 limit = intel_limit(crtc_state, refclk);
8781 ret = dev_priv->display.find_dpll(limit, crtc_state,
8782 crtc_state->port_clock,
8783 refclk, NULL, clock);
8790 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8793 * Account for spread spectrum to avoid
8794 * oversubscribing the link. Max center spread
8795 * is 2.5%; use 5% for safety's sake.
8797 u32 bps = target_clock * bpp * 21 / 20;
8798 return DIV_ROUND_UP(bps, link_bw * 8);
8801 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8803 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8806 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8807 struct intel_crtc_state *crtc_state,
8809 intel_clock_t *reduced_clock, u32 *fp2)
8811 struct drm_crtc *crtc = &intel_crtc->base;
8812 struct drm_device *dev = crtc->dev;
8813 struct drm_i915_private *dev_priv = dev->dev_private;
8814 struct drm_atomic_state *state = crtc_state->base.state;
8815 struct drm_connector *connector;
8816 struct drm_connector_state *connector_state;
8817 struct intel_encoder *encoder;
8819 int factor, num_connectors = 0, i;
8820 bool is_lvds = false, is_sdvo = false;
8822 for_each_connector_in_state(state, connector, connector_state, i) {
8823 if (connector_state->crtc != crtc_state->base.crtc)
8826 encoder = to_intel_encoder(connector_state->best_encoder);
8828 switch (encoder->type) {
8829 case INTEL_OUTPUT_LVDS:
8832 case INTEL_OUTPUT_SDVO:
8833 case INTEL_OUTPUT_HDMI:
8843 /* Enable autotuning of the PLL clock (if permissible) */
8846 if ((intel_panel_use_ssc(dev_priv) &&
8847 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8848 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8850 } else if (crtc_state->sdvo_tv_clock)
8853 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8856 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8862 dpll |= DPLLB_MODE_LVDS;
8864 dpll |= DPLLB_MODE_DAC_SERIAL;
8866 dpll |= (crtc_state->pixel_multiplier - 1)
8867 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8870 dpll |= DPLL_SDVO_HIGH_SPEED;
8871 if (crtc_state->has_dp_encoder)
8872 dpll |= DPLL_SDVO_HIGH_SPEED;
8874 /* compute bitmask from p1 value */
8875 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8877 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8879 switch (crtc_state->dpll.p2) {
8881 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8884 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8887 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8890 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8894 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8895 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8897 dpll |= PLL_REF_INPUT_DREFCLK;
8899 return dpll | DPLL_VCO_ENABLE;
8902 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8903 struct intel_crtc_state *crtc_state)
8905 struct drm_device *dev = crtc->base.dev;
8906 intel_clock_t clock, reduced_clock;
8907 u32 dpll = 0, fp = 0, fp2 = 0;
8908 bool ok, has_reduced_clock = false;
8909 bool is_lvds = false;
8910 struct intel_shared_dpll *pll;
8912 memset(&crtc_state->dpll_hw_state, 0,
8913 sizeof(crtc_state->dpll_hw_state));
8915 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8917 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8918 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8920 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8921 &has_reduced_clock, &reduced_clock);
8922 if (!ok && !crtc_state->clock_set) {
8923 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8926 /* Compat-code for transition, will disappear. */
8927 if (!crtc_state->clock_set) {
8928 crtc_state->dpll.n = clock.n;
8929 crtc_state->dpll.m1 = clock.m1;
8930 crtc_state->dpll.m2 = clock.m2;
8931 crtc_state->dpll.p1 = clock.p1;
8932 crtc_state->dpll.p2 = clock.p2;
8935 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8936 if (crtc_state->has_pch_encoder) {
8937 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8938 if (has_reduced_clock)
8939 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8941 dpll = ironlake_compute_dpll(crtc, crtc_state,
8942 &fp, &reduced_clock,
8943 has_reduced_clock ? &fp2 : NULL);
8945 crtc_state->dpll_hw_state.dpll = dpll;
8946 crtc_state->dpll_hw_state.fp0 = fp;
8947 if (has_reduced_clock)
8948 crtc_state->dpll_hw_state.fp1 = fp2;
8950 crtc_state->dpll_hw_state.fp1 = fp;
8952 pll = intel_get_shared_dpll(crtc, crtc_state);
8954 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8955 pipe_name(crtc->pipe));
8960 if (is_lvds && has_reduced_clock)
8961 crtc->lowfreq_avail = true;
8963 crtc->lowfreq_avail = false;
8968 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8969 struct intel_link_m_n *m_n)
8971 struct drm_device *dev = crtc->base.dev;
8972 struct drm_i915_private *dev_priv = dev->dev_private;
8973 enum pipe pipe = crtc->pipe;
8975 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8976 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8977 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8979 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8980 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8981 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8984 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8985 enum transcoder transcoder,
8986 struct intel_link_m_n *m_n,
8987 struct intel_link_m_n *m2_n2)
8989 struct drm_device *dev = crtc->base.dev;
8990 struct drm_i915_private *dev_priv = dev->dev_private;
8991 enum pipe pipe = crtc->pipe;
8993 if (INTEL_INFO(dev)->gen >= 5) {
8994 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8995 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8996 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8998 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8999 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9000 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9001 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9002 * gen < 8) and if DRRS is supported (to make sure the
9003 * registers are not unnecessarily read).
9005 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9006 crtc->config->has_drrs) {
9007 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9008 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9009 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9011 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9012 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9013 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9016 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9017 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9018 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9020 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9021 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9022 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9026 void intel_dp_get_m_n(struct intel_crtc *crtc,
9027 struct intel_crtc_state *pipe_config)
9029 if (pipe_config->has_pch_encoder)
9030 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9032 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9033 &pipe_config->dp_m_n,
9034 &pipe_config->dp_m2_n2);
9037 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9038 struct intel_crtc_state *pipe_config)
9040 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9041 &pipe_config->fdi_m_n, NULL);
9044 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9045 struct intel_crtc_state *pipe_config)
9047 struct drm_device *dev = crtc->base.dev;
9048 struct drm_i915_private *dev_priv = dev->dev_private;
9049 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9050 uint32_t ps_ctrl = 0;
9054 /* find scaler attached to this pipe */
9055 for (i = 0; i < crtc->num_scalers; i++) {
9056 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9057 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9059 pipe_config->pch_pfit.enabled = true;
9060 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9061 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9066 scaler_state->scaler_id = id;
9068 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9070 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9075 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9076 struct intel_initial_plane_config *plane_config)
9078 struct drm_device *dev = crtc->base.dev;
9079 struct drm_i915_private *dev_priv = dev->dev_private;
9080 u32 val, base, offset, stride_mult, tiling;
9081 int pipe = crtc->pipe;
9082 int fourcc, pixel_format;
9083 unsigned int aligned_height;
9084 struct drm_framebuffer *fb;
9085 struct intel_framebuffer *intel_fb;
9087 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9089 DRM_DEBUG_KMS("failed to alloc fb\n");
9093 fb = &intel_fb->base;
9095 val = I915_READ(PLANE_CTL(pipe, 0));
9096 if (!(val & PLANE_CTL_ENABLE))
9099 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9100 fourcc = skl_format_to_fourcc(pixel_format,
9101 val & PLANE_CTL_ORDER_RGBX,
9102 val & PLANE_CTL_ALPHA_MASK);
9103 fb->pixel_format = fourcc;
9104 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9106 tiling = val & PLANE_CTL_TILED_MASK;
9108 case PLANE_CTL_TILED_LINEAR:
9109 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9111 case PLANE_CTL_TILED_X:
9112 plane_config->tiling = I915_TILING_X;
9113 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9115 case PLANE_CTL_TILED_Y:
9116 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9118 case PLANE_CTL_TILED_YF:
9119 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9122 MISSING_CASE(tiling);
9126 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9127 plane_config->base = base;
9129 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9131 val = I915_READ(PLANE_SIZE(pipe, 0));
9132 fb->height = ((val >> 16) & 0xfff) + 1;
9133 fb->width = ((val >> 0) & 0x1fff) + 1;
9135 val = I915_READ(PLANE_STRIDE(pipe, 0));
9136 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9138 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9140 aligned_height = intel_fb_align_height(dev, fb->height,
9144 plane_config->size = fb->pitches[0] * aligned_height;
9146 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9147 pipe_name(pipe), fb->width, fb->height,
9148 fb->bits_per_pixel, base, fb->pitches[0],
9149 plane_config->size);
9151 plane_config->fb = intel_fb;
9158 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9159 struct intel_crtc_state *pipe_config)
9161 struct drm_device *dev = crtc->base.dev;
9162 struct drm_i915_private *dev_priv = dev->dev_private;
9165 tmp = I915_READ(PF_CTL(crtc->pipe));
9167 if (tmp & PF_ENABLE) {
9168 pipe_config->pch_pfit.enabled = true;
9169 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9170 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9172 /* We currently do not free assignements of panel fitters on
9173 * ivb/hsw (since we don't use the higher upscaling modes which
9174 * differentiates them) so just WARN about this case for now. */
9176 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9177 PF_PIPE_SEL_IVB(crtc->pipe));
9183 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9184 struct intel_initial_plane_config *plane_config)
9186 struct drm_device *dev = crtc->base.dev;
9187 struct drm_i915_private *dev_priv = dev->dev_private;
9188 u32 val, base, offset;
9189 int pipe = crtc->pipe;
9190 int fourcc, pixel_format;
9191 unsigned int aligned_height;
9192 struct drm_framebuffer *fb;
9193 struct intel_framebuffer *intel_fb;
9195 val = I915_READ(DSPCNTR(pipe));
9196 if (!(val & DISPLAY_PLANE_ENABLE))
9199 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9201 DRM_DEBUG_KMS("failed to alloc fb\n");
9205 fb = &intel_fb->base;
9207 if (INTEL_INFO(dev)->gen >= 4) {
9208 if (val & DISPPLANE_TILED) {
9209 plane_config->tiling = I915_TILING_X;
9210 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9214 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9215 fourcc = i9xx_format_to_fourcc(pixel_format);
9216 fb->pixel_format = fourcc;
9217 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9219 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9220 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9221 offset = I915_READ(DSPOFFSET(pipe));
9223 if (plane_config->tiling)
9224 offset = I915_READ(DSPTILEOFF(pipe));
9226 offset = I915_READ(DSPLINOFF(pipe));
9228 plane_config->base = base;
9230 val = I915_READ(PIPESRC(pipe));
9231 fb->width = ((val >> 16) & 0xfff) + 1;
9232 fb->height = ((val >> 0) & 0xfff) + 1;
9234 val = I915_READ(DSPSTRIDE(pipe));
9235 fb->pitches[0] = val & 0xffffffc0;
9237 aligned_height = intel_fb_align_height(dev, fb->height,
9241 plane_config->size = fb->pitches[0] * aligned_height;
9243 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9244 pipe_name(pipe), fb->width, fb->height,
9245 fb->bits_per_pixel, base, fb->pitches[0],
9246 plane_config->size);
9248 plane_config->fb = intel_fb;
9251 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9252 struct intel_crtc_state *pipe_config)
9254 struct drm_device *dev = crtc->base.dev;
9255 struct drm_i915_private *dev_priv = dev->dev_private;
9258 if (!intel_display_power_is_enabled(dev_priv,
9259 POWER_DOMAIN_PIPE(crtc->pipe)))
9262 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9263 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9265 tmp = I915_READ(PIPECONF(crtc->pipe));
9266 if (!(tmp & PIPECONF_ENABLE))
9269 switch (tmp & PIPECONF_BPC_MASK) {
9271 pipe_config->pipe_bpp = 18;
9274 pipe_config->pipe_bpp = 24;
9276 case PIPECONF_10BPC:
9277 pipe_config->pipe_bpp = 30;
9279 case PIPECONF_12BPC:
9280 pipe_config->pipe_bpp = 36;
9286 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9287 pipe_config->limited_color_range = true;
9289 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9290 struct intel_shared_dpll *pll;
9292 pipe_config->has_pch_encoder = true;
9294 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9295 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9296 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9298 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9300 if (HAS_PCH_IBX(dev_priv->dev)) {
9301 pipe_config->shared_dpll =
9302 (enum intel_dpll_id) crtc->pipe;
9304 tmp = I915_READ(PCH_DPLL_SEL);
9305 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9306 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9308 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9311 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9313 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9314 &pipe_config->dpll_hw_state));
9316 tmp = pipe_config->dpll_hw_state.dpll;
9317 pipe_config->pixel_multiplier =
9318 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9319 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9321 ironlake_pch_clock_get(crtc, pipe_config);
9323 pipe_config->pixel_multiplier = 1;
9326 intel_get_pipe_timings(crtc, pipe_config);
9328 ironlake_get_pfit_config(crtc, pipe_config);
9333 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9335 struct drm_device *dev = dev_priv->dev;
9336 struct intel_crtc *crtc;
9338 for_each_intel_crtc(dev, crtc)
9339 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9340 pipe_name(crtc->pipe));
9342 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9343 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9344 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9345 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9346 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9347 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9348 "CPU PWM1 enabled\n");
9349 if (IS_HASWELL(dev))
9350 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9351 "CPU PWM2 enabled\n");
9352 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9353 "PCH PWM1 enabled\n");
9354 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9355 "Utility pin enabled\n");
9356 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9359 * In theory we can still leave IRQs enabled, as long as only the HPD
9360 * interrupts remain enabled. We used to check for that, but since it's
9361 * gen-specific and since we only disable LCPLL after we fully disable
9362 * the interrupts, the check below should be enough.
9364 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9367 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9369 struct drm_device *dev = dev_priv->dev;
9371 if (IS_HASWELL(dev))
9372 return I915_READ(D_COMP_HSW);
9374 return I915_READ(D_COMP_BDW);
9377 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9379 struct drm_device *dev = dev_priv->dev;
9381 if (IS_HASWELL(dev)) {
9382 mutex_lock(&dev_priv->rps.hw_lock);
9383 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9385 DRM_ERROR("Failed to write to D_COMP\n");
9386 mutex_unlock(&dev_priv->rps.hw_lock);
9388 I915_WRITE(D_COMP_BDW, val);
9389 POSTING_READ(D_COMP_BDW);
9394 * This function implements pieces of two sequences from BSpec:
9395 * - Sequence for display software to disable LCPLL
9396 * - Sequence for display software to allow package C8+
9397 * The steps implemented here are just the steps that actually touch the LCPLL
9398 * register. Callers should take care of disabling all the display engine
9399 * functions, doing the mode unset, fixing interrupts, etc.
9401 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9402 bool switch_to_fclk, bool allow_power_down)
9406 assert_can_disable_lcpll(dev_priv);
9408 val = I915_READ(LCPLL_CTL);
9410 if (switch_to_fclk) {
9411 val |= LCPLL_CD_SOURCE_FCLK;
9412 I915_WRITE(LCPLL_CTL, val);
9414 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9415 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9416 DRM_ERROR("Switching to FCLK failed\n");
9418 val = I915_READ(LCPLL_CTL);
9421 val |= LCPLL_PLL_DISABLE;
9422 I915_WRITE(LCPLL_CTL, val);
9423 POSTING_READ(LCPLL_CTL);
9425 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9426 DRM_ERROR("LCPLL still locked\n");
9428 val = hsw_read_dcomp(dev_priv);
9429 val |= D_COMP_COMP_DISABLE;
9430 hsw_write_dcomp(dev_priv, val);
9433 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9435 DRM_ERROR("D_COMP RCOMP still in progress\n");
9437 if (allow_power_down) {
9438 val = I915_READ(LCPLL_CTL);
9439 val |= LCPLL_POWER_DOWN_ALLOW;
9440 I915_WRITE(LCPLL_CTL, val);
9441 POSTING_READ(LCPLL_CTL);
9446 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9449 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9453 val = I915_READ(LCPLL_CTL);
9455 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9456 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9460 * Make sure we're not on PC8 state before disabling PC8, otherwise
9461 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9463 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9465 if (val & LCPLL_POWER_DOWN_ALLOW) {
9466 val &= ~LCPLL_POWER_DOWN_ALLOW;
9467 I915_WRITE(LCPLL_CTL, val);
9468 POSTING_READ(LCPLL_CTL);
9471 val = hsw_read_dcomp(dev_priv);
9472 val |= D_COMP_COMP_FORCE;
9473 val &= ~D_COMP_COMP_DISABLE;
9474 hsw_write_dcomp(dev_priv, val);
9476 val = I915_READ(LCPLL_CTL);
9477 val &= ~LCPLL_PLL_DISABLE;
9478 I915_WRITE(LCPLL_CTL, val);
9480 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9481 DRM_ERROR("LCPLL not locked yet\n");
9483 if (val & LCPLL_CD_SOURCE_FCLK) {
9484 val = I915_READ(LCPLL_CTL);
9485 val &= ~LCPLL_CD_SOURCE_FCLK;
9486 I915_WRITE(LCPLL_CTL, val);
9488 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9489 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9490 DRM_ERROR("Switching back to LCPLL failed\n");
9493 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9494 intel_update_cdclk(dev_priv->dev);
9498 * Package states C8 and deeper are really deep PC states that can only be
9499 * reached when all the devices on the system allow it, so even if the graphics
9500 * device allows PC8+, it doesn't mean the system will actually get to these
9501 * states. Our driver only allows PC8+ when going into runtime PM.
9503 * The requirements for PC8+ are that all the outputs are disabled, the power
9504 * well is disabled and most interrupts are disabled, and these are also
9505 * requirements for runtime PM. When these conditions are met, we manually do
9506 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9507 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9510 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9511 * the state of some registers, so when we come back from PC8+ we need to
9512 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9513 * need to take care of the registers kept by RC6. Notice that this happens even
9514 * if we don't put the device in PCI D3 state (which is what currently happens
9515 * because of the runtime PM support).
9517 * For more, read "Display Sequences for Package C8" on the hardware
9520 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9522 struct drm_device *dev = dev_priv->dev;
9525 DRM_DEBUG_KMS("Enabling package C8+\n");
9527 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9528 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9529 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9530 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9533 lpt_disable_clkout_dp(dev);
9534 hsw_disable_lcpll(dev_priv, true, true);
9537 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9539 struct drm_device *dev = dev_priv->dev;
9542 DRM_DEBUG_KMS("Disabling package C8+\n");
9544 hsw_restore_lcpll(dev_priv);
9545 lpt_init_pch_refclk(dev);
9547 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9548 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9549 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9550 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9553 intel_prepare_ddi(dev);
9556 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9558 struct drm_device *dev = old_state->dev;
9559 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9561 broxton_set_cdclk(dev, req_cdclk);
9564 /* compute the max rate for new configuration */
9565 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9567 struct intel_crtc *intel_crtc;
9568 struct intel_crtc_state *crtc_state;
9569 int max_pixel_rate = 0;
9571 for_each_intel_crtc(state->dev, intel_crtc) {
9574 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9575 if (IS_ERR(crtc_state))
9576 return PTR_ERR(crtc_state);
9578 if (!crtc_state->base.enable)
9581 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9583 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9584 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9585 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9587 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9590 return max_pixel_rate;
9593 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9595 struct drm_i915_private *dev_priv = dev->dev_private;
9599 if (WARN((I915_READ(LCPLL_CTL) &
9600 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9601 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9602 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9603 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9604 "trying to change cdclk frequency with cdclk not enabled\n"))
9607 mutex_lock(&dev_priv->rps.hw_lock);
9608 ret = sandybridge_pcode_write(dev_priv,
9609 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9610 mutex_unlock(&dev_priv->rps.hw_lock);
9612 DRM_ERROR("failed to inform pcode about cdclk change\n");
9616 val = I915_READ(LCPLL_CTL);
9617 val |= LCPLL_CD_SOURCE_FCLK;
9618 I915_WRITE(LCPLL_CTL, val);
9620 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9621 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9622 DRM_ERROR("Switching to FCLK failed\n");
9624 val = I915_READ(LCPLL_CTL);
9625 val &= ~LCPLL_CLK_FREQ_MASK;
9629 val |= LCPLL_CLK_FREQ_450;
9633 val |= LCPLL_CLK_FREQ_54O_BDW;
9637 val |= LCPLL_CLK_FREQ_337_5_BDW;
9641 val |= LCPLL_CLK_FREQ_675_BDW;
9645 WARN(1, "invalid cdclk frequency\n");
9649 I915_WRITE(LCPLL_CTL, val);
9651 val = I915_READ(LCPLL_CTL);
9652 val &= ~LCPLL_CD_SOURCE_FCLK;
9653 I915_WRITE(LCPLL_CTL, val);
9655 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9656 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9657 DRM_ERROR("Switching back to LCPLL failed\n");
9659 mutex_lock(&dev_priv->rps.hw_lock);
9660 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9661 mutex_unlock(&dev_priv->rps.hw_lock);
9663 intel_update_cdclk(dev);
9665 WARN(cdclk != dev_priv->cdclk_freq,
9666 "cdclk requested %d kHz but got %d kHz\n",
9667 cdclk, dev_priv->cdclk_freq);
9670 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9672 struct drm_i915_private *dev_priv = to_i915(state->dev);
9673 int max_pixclk = ilk_max_pixel_rate(state);
9677 * FIXME should also account for plane ratio
9678 * once 64bpp pixel formats are supported.
9680 if (max_pixclk > 540000)
9682 else if (max_pixclk > 450000)
9684 else if (max_pixclk > 337500)
9690 * FIXME move the cdclk caclulation to
9691 * compute_config() so we can fail gracegully.
9693 if (cdclk > dev_priv->max_cdclk_freq) {
9694 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9695 cdclk, dev_priv->max_cdclk_freq);
9696 cdclk = dev_priv->max_cdclk_freq;
9699 to_intel_atomic_state(state)->cdclk = cdclk;
9704 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9706 struct drm_device *dev = old_state->dev;
9707 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9709 broadwell_set_cdclk(dev, req_cdclk);
9712 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9713 struct intel_crtc_state *crtc_state)
9715 if (!intel_ddi_pll_select(crtc, crtc_state))
9718 crtc->lowfreq_avail = false;
9723 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9725 struct intel_crtc_state *pipe_config)
9729 pipe_config->ddi_pll_sel = SKL_DPLL0;
9730 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9733 pipe_config->ddi_pll_sel = SKL_DPLL1;
9734 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9737 pipe_config->ddi_pll_sel = SKL_DPLL2;
9738 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9741 DRM_ERROR("Incorrect port type\n");
9745 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9747 struct intel_crtc_state *pipe_config)
9749 u32 temp, dpll_ctl1;
9751 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9752 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9754 switch (pipe_config->ddi_pll_sel) {
9757 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9758 * of the shared DPLL framework and thus needs to be read out
9761 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9762 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9765 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9768 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9771 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9776 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9778 struct intel_crtc_state *pipe_config)
9780 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9782 switch (pipe_config->ddi_pll_sel) {
9783 case PORT_CLK_SEL_WRPLL1:
9784 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9786 case PORT_CLK_SEL_WRPLL2:
9787 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9792 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9793 struct intel_crtc_state *pipe_config)
9795 struct drm_device *dev = crtc->base.dev;
9796 struct drm_i915_private *dev_priv = dev->dev_private;
9797 struct intel_shared_dpll *pll;
9801 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9803 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9805 if (IS_SKYLAKE(dev))
9806 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9807 else if (IS_BROXTON(dev))
9808 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9810 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9812 if (pipe_config->shared_dpll >= 0) {
9813 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9815 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9816 &pipe_config->dpll_hw_state));
9820 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9821 * DDI E. So just check whether this pipe is wired to DDI E and whether
9822 * the PCH transcoder is on.
9824 if (INTEL_INFO(dev)->gen < 9 &&
9825 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9826 pipe_config->has_pch_encoder = true;
9828 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9829 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9830 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9832 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9836 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9837 struct intel_crtc_state *pipe_config)
9839 struct drm_device *dev = crtc->base.dev;
9840 struct drm_i915_private *dev_priv = dev->dev_private;
9841 enum intel_display_power_domain pfit_domain;
9844 if (!intel_display_power_is_enabled(dev_priv,
9845 POWER_DOMAIN_PIPE(crtc->pipe)))
9848 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9849 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9851 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9852 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9853 enum pipe trans_edp_pipe;
9854 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9856 WARN(1, "unknown pipe linked to edp transcoder\n");
9857 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9858 case TRANS_DDI_EDP_INPUT_A_ON:
9859 trans_edp_pipe = PIPE_A;
9861 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9862 trans_edp_pipe = PIPE_B;
9864 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9865 trans_edp_pipe = PIPE_C;
9869 if (trans_edp_pipe == crtc->pipe)
9870 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9873 if (!intel_display_power_is_enabled(dev_priv,
9874 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9877 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9878 if (!(tmp & PIPECONF_ENABLE))
9881 haswell_get_ddi_port_state(crtc, pipe_config);
9883 intel_get_pipe_timings(crtc, pipe_config);
9885 if (INTEL_INFO(dev)->gen >= 9) {
9886 skl_init_scalers(dev, crtc, pipe_config);
9889 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9891 if (INTEL_INFO(dev)->gen >= 9) {
9892 pipe_config->scaler_state.scaler_id = -1;
9893 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9896 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9897 if (INTEL_INFO(dev)->gen == 9)
9898 skylake_get_pfit_config(crtc, pipe_config);
9899 else if (INTEL_INFO(dev)->gen < 9)
9900 ironlake_get_pfit_config(crtc, pipe_config);
9902 MISSING_CASE(INTEL_INFO(dev)->gen);
9905 if (IS_HASWELL(dev))
9906 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9907 (I915_READ(IPS_CTL) & IPS_ENABLE);
9909 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9910 pipe_config->pixel_multiplier =
9911 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9913 pipe_config->pixel_multiplier = 1;
9919 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9921 struct drm_device *dev = crtc->dev;
9922 struct drm_i915_private *dev_priv = dev->dev_private;
9923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9924 uint32_t cntl = 0, size = 0;
9927 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9928 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9929 unsigned int stride = roundup_pow_of_two(width) * 4;
9933 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9944 cntl |= CURSOR_ENABLE |
9945 CURSOR_GAMMA_ENABLE |
9946 CURSOR_FORMAT_ARGB |
9947 CURSOR_STRIDE(stride);
9949 size = (height << 12) | width;
9952 if (intel_crtc->cursor_cntl != 0 &&
9953 (intel_crtc->cursor_base != base ||
9954 intel_crtc->cursor_size != size ||
9955 intel_crtc->cursor_cntl != cntl)) {
9956 /* On these chipsets we can only modify the base/size/stride
9957 * whilst the cursor is disabled.
9959 I915_WRITE(_CURACNTR, 0);
9960 POSTING_READ(_CURACNTR);
9961 intel_crtc->cursor_cntl = 0;
9964 if (intel_crtc->cursor_base != base) {
9965 I915_WRITE(_CURABASE, base);
9966 intel_crtc->cursor_base = base;
9969 if (intel_crtc->cursor_size != size) {
9970 I915_WRITE(CURSIZE, size);
9971 intel_crtc->cursor_size = size;
9974 if (intel_crtc->cursor_cntl != cntl) {
9975 I915_WRITE(_CURACNTR, cntl);
9976 POSTING_READ(_CURACNTR);
9977 intel_crtc->cursor_cntl = cntl;
9981 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9983 struct drm_device *dev = crtc->dev;
9984 struct drm_i915_private *dev_priv = dev->dev_private;
9985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9986 int pipe = intel_crtc->pipe;
9991 cntl = MCURSOR_GAMMA_ENABLE;
9992 switch (intel_crtc->base.cursor->state->crtc_w) {
9994 cntl |= CURSOR_MODE_64_ARGB_AX;
9997 cntl |= CURSOR_MODE_128_ARGB_AX;
10000 cntl |= CURSOR_MODE_256_ARGB_AX;
10003 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10006 cntl |= pipe << 28; /* Connect to correct pipe */
10008 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10009 cntl |= CURSOR_PIPE_CSC_ENABLE;
10012 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10013 cntl |= CURSOR_ROTATE_180;
10015 if (intel_crtc->cursor_cntl != cntl) {
10016 I915_WRITE(CURCNTR(pipe), cntl);
10017 POSTING_READ(CURCNTR(pipe));
10018 intel_crtc->cursor_cntl = cntl;
10021 /* and commit changes on next vblank */
10022 I915_WRITE(CURBASE(pipe), base);
10023 POSTING_READ(CURBASE(pipe));
10025 intel_crtc->cursor_base = base;
10028 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10029 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10032 struct drm_device *dev = crtc->dev;
10033 struct drm_i915_private *dev_priv = dev->dev_private;
10034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10035 int pipe = intel_crtc->pipe;
10036 int x = crtc->cursor_x;
10037 int y = crtc->cursor_y;
10038 u32 base = 0, pos = 0;
10041 base = intel_crtc->cursor_addr;
10043 if (x >= intel_crtc->config->pipe_src_w)
10046 if (y >= intel_crtc->config->pipe_src_h)
10050 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10053 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10056 pos |= x << CURSOR_X_SHIFT;
10059 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10062 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10065 pos |= y << CURSOR_Y_SHIFT;
10067 if (base == 0 && intel_crtc->cursor_base == 0)
10070 I915_WRITE(CURPOS(pipe), pos);
10072 /* ILK+ do this automagically */
10073 if (HAS_GMCH_DISPLAY(dev) &&
10074 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10075 base += (intel_crtc->base.cursor->state->crtc_h *
10076 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10079 if (IS_845G(dev) || IS_I865G(dev))
10080 i845_update_cursor(crtc, base);
10082 i9xx_update_cursor(crtc, base);
10085 static bool cursor_size_ok(struct drm_device *dev,
10086 uint32_t width, uint32_t height)
10088 if (width == 0 || height == 0)
10092 * 845g/865g are special in that they are only limited by
10093 * the width of their cursors, the height is arbitrary up to
10094 * the precision of the register. Everything else requires
10095 * square cursors, limited to a few power-of-two sizes.
10097 if (IS_845G(dev) || IS_I865G(dev)) {
10098 if ((width & 63) != 0)
10101 if (width > (IS_845G(dev) ? 64 : 512))
10107 switch (width | height) {
10122 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10123 u16 *blue, uint32_t start, uint32_t size)
10125 int end = (start + size > 256) ? 256 : start + size, i;
10126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10128 for (i = start; i < end; i++) {
10129 intel_crtc->lut_r[i] = red[i] >> 8;
10130 intel_crtc->lut_g[i] = green[i] >> 8;
10131 intel_crtc->lut_b[i] = blue[i] >> 8;
10134 intel_crtc_load_lut(crtc);
10137 /* VESA 640x480x72Hz mode to set on the pipe */
10138 static struct drm_display_mode load_detect_mode = {
10139 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10140 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10143 struct drm_framebuffer *
10144 __intel_framebuffer_create(struct drm_device *dev,
10145 struct drm_mode_fb_cmd2 *mode_cmd,
10146 struct drm_i915_gem_object *obj)
10148 struct intel_framebuffer *intel_fb;
10151 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10153 drm_gem_object_unreference(&obj->base);
10154 return ERR_PTR(-ENOMEM);
10157 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10161 return &intel_fb->base;
10163 drm_gem_object_unreference(&obj->base);
10166 return ERR_PTR(ret);
10169 static struct drm_framebuffer *
10170 intel_framebuffer_create(struct drm_device *dev,
10171 struct drm_mode_fb_cmd2 *mode_cmd,
10172 struct drm_i915_gem_object *obj)
10174 struct drm_framebuffer *fb;
10177 ret = i915_mutex_lock_interruptible(dev);
10179 return ERR_PTR(ret);
10180 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10181 mutex_unlock(&dev->struct_mutex);
10187 intel_framebuffer_pitch_for_width(int width, int bpp)
10189 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10190 return ALIGN(pitch, 64);
10194 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10196 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10197 return PAGE_ALIGN(pitch * mode->vdisplay);
10200 static struct drm_framebuffer *
10201 intel_framebuffer_create_for_mode(struct drm_device *dev,
10202 struct drm_display_mode *mode,
10203 int depth, int bpp)
10205 struct drm_i915_gem_object *obj;
10206 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10208 obj = i915_gem_alloc_object(dev,
10209 intel_framebuffer_size_for_mode(mode, bpp));
10211 return ERR_PTR(-ENOMEM);
10213 mode_cmd.width = mode->hdisplay;
10214 mode_cmd.height = mode->vdisplay;
10215 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10217 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10219 return intel_framebuffer_create(dev, &mode_cmd, obj);
10222 static struct drm_framebuffer *
10223 mode_fits_in_fbdev(struct drm_device *dev,
10224 struct drm_display_mode *mode)
10226 #ifdef CONFIG_DRM_I915_FBDEV
10227 struct drm_i915_private *dev_priv = dev->dev_private;
10228 struct drm_i915_gem_object *obj;
10229 struct drm_framebuffer *fb;
10231 if (!dev_priv->fbdev)
10234 if (!dev_priv->fbdev->fb)
10237 obj = dev_priv->fbdev->fb->obj;
10240 fb = &dev_priv->fbdev->fb->base;
10241 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10242 fb->bits_per_pixel))
10245 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10254 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10255 struct drm_crtc *crtc,
10256 struct drm_display_mode *mode,
10257 struct drm_framebuffer *fb,
10260 struct drm_plane_state *plane_state;
10261 int hdisplay, vdisplay;
10264 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10265 if (IS_ERR(plane_state))
10266 return PTR_ERR(plane_state);
10269 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10271 hdisplay = vdisplay = 0;
10273 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10276 drm_atomic_set_fb_for_plane(plane_state, fb);
10277 plane_state->crtc_x = 0;
10278 plane_state->crtc_y = 0;
10279 plane_state->crtc_w = hdisplay;
10280 plane_state->crtc_h = vdisplay;
10281 plane_state->src_x = x << 16;
10282 plane_state->src_y = y << 16;
10283 plane_state->src_w = hdisplay << 16;
10284 plane_state->src_h = vdisplay << 16;
10289 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10290 struct drm_display_mode *mode,
10291 struct intel_load_detect_pipe *old,
10292 struct drm_modeset_acquire_ctx *ctx)
10294 struct intel_crtc *intel_crtc;
10295 struct intel_encoder *intel_encoder =
10296 intel_attached_encoder(connector);
10297 struct drm_crtc *possible_crtc;
10298 struct drm_encoder *encoder = &intel_encoder->base;
10299 struct drm_crtc *crtc = NULL;
10300 struct drm_device *dev = encoder->dev;
10301 struct drm_framebuffer *fb;
10302 struct drm_mode_config *config = &dev->mode_config;
10303 struct drm_atomic_state *state = NULL;
10304 struct drm_connector_state *connector_state;
10305 struct intel_crtc_state *crtc_state;
10308 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10309 connector->base.id, connector->name,
10310 encoder->base.id, encoder->name);
10313 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10318 * Algorithm gets a little messy:
10320 * - if the connector already has an assigned crtc, use it (but make
10321 * sure it's on first)
10323 * - try to find the first unused crtc that can drive this connector,
10324 * and use that if we find one
10327 /* See if we already have a CRTC for this connector */
10328 if (encoder->crtc) {
10329 crtc = encoder->crtc;
10331 ret = drm_modeset_lock(&crtc->mutex, ctx);
10334 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10338 old->dpms_mode = connector->dpms;
10339 old->load_detect_temp = false;
10341 /* Make sure the crtc and connector are running */
10342 if (connector->dpms != DRM_MODE_DPMS_ON)
10343 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10348 /* Find an unused one (if possible) */
10349 for_each_crtc(dev, possible_crtc) {
10351 if (!(encoder->possible_crtcs & (1 << i)))
10353 if (possible_crtc->state->enable)
10356 crtc = possible_crtc;
10361 * If we didn't find an unused CRTC, don't use any.
10364 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10368 ret = drm_modeset_lock(&crtc->mutex, ctx);
10371 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10375 intel_crtc = to_intel_crtc(crtc);
10376 old->dpms_mode = connector->dpms;
10377 old->load_detect_temp = true;
10378 old->release_fb = NULL;
10380 state = drm_atomic_state_alloc(dev);
10384 state->acquire_ctx = ctx;
10386 connector_state = drm_atomic_get_connector_state(state, connector);
10387 if (IS_ERR(connector_state)) {
10388 ret = PTR_ERR(connector_state);
10392 connector_state->crtc = crtc;
10393 connector_state->best_encoder = &intel_encoder->base;
10395 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10396 if (IS_ERR(crtc_state)) {
10397 ret = PTR_ERR(crtc_state);
10401 crtc_state->base.active = crtc_state->base.enable = true;
10404 mode = &load_detect_mode;
10406 /* We need a framebuffer large enough to accommodate all accesses
10407 * that the plane may generate whilst we perform load detection.
10408 * We can not rely on the fbcon either being present (we get called
10409 * during its initialisation to detect all boot displays, or it may
10410 * not even exist) or that it is large enough to satisfy the
10413 fb = mode_fits_in_fbdev(dev, mode);
10415 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10416 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10417 old->release_fb = fb;
10419 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10421 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10425 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10429 drm_mode_copy(&crtc_state->base.mode, mode);
10431 if (drm_atomic_commit(state)) {
10432 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10433 if (old->release_fb)
10434 old->release_fb->funcs->destroy(old->release_fb);
10437 crtc->primary->crtc = crtc;
10439 /* let the connector get through one full cycle before testing */
10440 intel_wait_for_vblank(dev, intel_crtc->pipe);
10444 drm_atomic_state_free(state);
10447 if (ret == -EDEADLK) {
10448 drm_modeset_backoff(ctx);
10455 void intel_release_load_detect_pipe(struct drm_connector *connector,
10456 struct intel_load_detect_pipe *old,
10457 struct drm_modeset_acquire_ctx *ctx)
10459 struct drm_device *dev = connector->dev;
10460 struct intel_encoder *intel_encoder =
10461 intel_attached_encoder(connector);
10462 struct drm_encoder *encoder = &intel_encoder->base;
10463 struct drm_crtc *crtc = encoder->crtc;
10464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10465 struct drm_atomic_state *state;
10466 struct drm_connector_state *connector_state;
10467 struct intel_crtc_state *crtc_state;
10470 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10471 connector->base.id, connector->name,
10472 encoder->base.id, encoder->name);
10474 if (old->load_detect_temp) {
10475 state = drm_atomic_state_alloc(dev);
10479 state->acquire_ctx = ctx;
10481 connector_state = drm_atomic_get_connector_state(state, connector);
10482 if (IS_ERR(connector_state))
10485 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10486 if (IS_ERR(crtc_state))
10489 connector_state->best_encoder = NULL;
10490 connector_state->crtc = NULL;
10492 crtc_state->base.enable = crtc_state->base.active = false;
10494 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10499 ret = drm_atomic_commit(state);
10503 if (old->release_fb) {
10504 drm_framebuffer_unregister_private(old->release_fb);
10505 drm_framebuffer_unreference(old->release_fb);
10511 /* Switch crtc and encoder back off if necessary */
10512 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10513 connector->funcs->dpms(connector, old->dpms_mode);
10517 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10518 drm_atomic_state_free(state);
10521 static int i9xx_pll_refclk(struct drm_device *dev,
10522 const struct intel_crtc_state *pipe_config)
10524 struct drm_i915_private *dev_priv = dev->dev_private;
10525 u32 dpll = pipe_config->dpll_hw_state.dpll;
10527 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10528 return dev_priv->vbt.lvds_ssc_freq;
10529 else if (HAS_PCH_SPLIT(dev))
10531 else if (!IS_GEN2(dev))
10537 /* Returns the clock of the currently programmed mode of the given pipe. */
10538 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10539 struct intel_crtc_state *pipe_config)
10541 struct drm_device *dev = crtc->base.dev;
10542 struct drm_i915_private *dev_priv = dev->dev_private;
10543 int pipe = pipe_config->cpu_transcoder;
10544 u32 dpll = pipe_config->dpll_hw_state.dpll;
10546 intel_clock_t clock;
10548 int refclk = i9xx_pll_refclk(dev, pipe_config);
10550 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10551 fp = pipe_config->dpll_hw_state.fp0;
10553 fp = pipe_config->dpll_hw_state.fp1;
10555 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10556 if (IS_PINEVIEW(dev)) {
10557 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10558 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10560 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10561 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10564 if (!IS_GEN2(dev)) {
10565 if (IS_PINEVIEW(dev))
10566 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10567 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10569 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10570 DPLL_FPA01_P1_POST_DIV_SHIFT);
10572 switch (dpll & DPLL_MODE_MASK) {
10573 case DPLLB_MODE_DAC_SERIAL:
10574 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10577 case DPLLB_MODE_LVDS:
10578 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10582 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10583 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10587 if (IS_PINEVIEW(dev))
10588 port_clock = pnv_calc_dpll_params(refclk, &clock);
10590 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10592 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10593 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10596 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10597 DPLL_FPA01_P1_POST_DIV_SHIFT);
10599 if (lvds & LVDS_CLKB_POWER_UP)
10604 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10607 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10608 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10610 if (dpll & PLL_P2_DIVIDE_BY_4)
10616 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10620 * This value includes pixel_multiplier. We will use
10621 * port_clock to compute adjusted_mode.crtc_clock in the
10622 * encoder's get_config() function.
10624 pipe_config->port_clock = port_clock;
10627 int intel_dotclock_calculate(int link_freq,
10628 const struct intel_link_m_n *m_n)
10631 * The calculation for the data clock is:
10632 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10633 * But we want to avoid losing precison if possible, so:
10634 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10636 * and the link clock is simpler:
10637 * link_clock = (m * link_clock) / n
10643 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10646 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10647 struct intel_crtc_state *pipe_config)
10649 struct drm_device *dev = crtc->base.dev;
10651 /* read out port_clock from the DPLL */
10652 i9xx_crtc_clock_get(crtc, pipe_config);
10655 * This value does not include pixel_multiplier.
10656 * We will check that port_clock and adjusted_mode.crtc_clock
10657 * agree once we know their relationship in the encoder's
10658 * get_config() function.
10660 pipe_config->base.adjusted_mode.crtc_clock =
10661 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10662 &pipe_config->fdi_m_n);
10665 /** Returns the currently programmed mode of the given pipe. */
10666 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10667 struct drm_crtc *crtc)
10669 struct drm_i915_private *dev_priv = dev->dev_private;
10670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10671 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10672 struct drm_display_mode *mode;
10673 struct intel_crtc_state pipe_config;
10674 int htot = I915_READ(HTOTAL(cpu_transcoder));
10675 int hsync = I915_READ(HSYNC(cpu_transcoder));
10676 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10677 int vsync = I915_READ(VSYNC(cpu_transcoder));
10678 enum pipe pipe = intel_crtc->pipe;
10680 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10685 * Construct a pipe_config sufficient for getting the clock info
10686 * back out of crtc_clock_get.
10688 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10689 * to use a real value here instead.
10691 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10692 pipe_config.pixel_multiplier = 1;
10693 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10694 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10695 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10696 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10698 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10699 mode->hdisplay = (htot & 0xffff) + 1;
10700 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10701 mode->hsync_start = (hsync & 0xffff) + 1;
10702 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10703 mode->vdisplay = (vtot & 0xffff) + 1;
10704 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10705 mode->vsync_start = (vsync & 0xffff) + 1;
10706 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10708 drm_mode_set_name(mode);
10713 void intel_mark_busy(struct drm_device *dev)
10715 struct drm_i915_private *dev_priv = dev->dev_private;
10717 if (dev_priv->mm.busy)
10720 intel_runtime_pm_get(dev_priv);
10721 i915_update_gfx_val(dev_priv);
10722 if (INTEL_INFO(dev)->gen >= 6)
10723 gen6_rps_busy(dev_priv);
10724 dev_priv->mm.busy = true;
10727 void intel_mark_idle(struct drm_device *dev)
10729 struct drm_i915_private *dev_priv = dev->dev_private;
10731 if (!dev_priv->mm.busy)
10734 dev_priv->mm.busy = false;
10736 if (INTEL_INFO(dev)->gen >= 6)
10737 gen6_rps_idle(dev->dev_private);
10739 intel_runtime_pm_put(dev_priv);
10742 static void intel_crtc_destroy(struct drm_crtc *crtc)
10744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10745 struct drm_device *dev = crtc->dev;
10746 struct intel_unpin_work *work;
10748 spin_lock_irq(&dev->event_lock);
10749 work = intel_crtc->unpin_work;
10750 intel_crtc->unpin_work = NULL;
10751 spin_unlock_irq(&dev->event_lock);
10754 cancel_work_sync(&work->work);
10758 drm_crtc_cleanup(crtc);
10763 static void intel_unpin_work_fn(struct work_struct *__work)
10765 struct intel_unpin_work *work =
10766 container_of(__work, struct intel_unpin_work, work);
10767 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10768 struct drm_device *dev = crtc->base.dev;
10769 struct drm_plane *primary = crtc->base.primary;
10771 mutex_lock(&dev->struct_mutex);
10772 intel_unpin_fb_obj(work->old_fb, primary->state);
10773 drm_gem_object_unreference(&work->pending_flip_obj->base);
10775 if (work->flip_queued_req)
10776 i915_gem_request_assign(&work->flip_queued_req, NULL);
10777 mutex_unlock(&dev->struct_mutex);
10779 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10780 drm_framebuffer_unreference(work->old_fb);
10782 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10783 atomic_dec(&crtc->unpin_work_count);
10788 static void do_intel_finish_page_flip(struct drm_device *dev,
10789 struct drm_crtc *crtc)
10791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10792 struct intel_unpin_work *work;
10793 unsigned long flags;
10795 /* Ignore early vblank irqs */
10796 if (intel_crtc == NULL)
10800 * This is called both by irq handlers and the reset code (to complete
10801 * lost pageflips) so needs the full irqsave spinlocks.
10803 spin_lock_irqsave(&dev->event_lock, flags);
10804 work = intel_crtc->unpin_work;
10806 /* Ensure we don't miss a work->pending update ... */
10809 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10810 spin_unlock_irqrestore(&dev->event_lock, flags);
10814 page_flip_completed(intel_crtc);
10816 spin_unlock_irqrestore(&dev->event_lock, flags);
10819 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10821 struct drm_i915_private *dev_priv = dev->dev_private;
10822 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10824 do_intel_finish_page_flip(dev, crtc);
10827 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10829 struct drm_i915_private *dev_priv = dev->dev_private;
10830 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10832 do_intel_finish_page_flip(dev, crtc);
10835 /* Is 'a' after or equal to 'b'? */
10836 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10838 return !((a - b) & 0x80000000);
10841 static bool page_flip_finished(struct intel_crtc *crtc)
10843 struct drm_device *dev = crtc->base.dev;
10844 struct drm_i915_private *dev_priv = dev->dev_private;
10846 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10847 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10851 * The relevant registers doen't exist on pre-ctg.
10852 * As the flip done interrupt doesn't trigger for mmio
10853 * flips on gmch platforms, a flip count check isn't
10854 * really needed there. But since ctg has the registers,
10855 * include it in the check anyway.
10857 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10861 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10862 * used the same base address. In that case the mmio flip might
10863 * have completed, but the CS hasn't even executed the flip yet.
10865 * A flip count check isn't enough as the CS might have updated
10866 * the base address just after start of vblank, but before we
10867 * managed to process the interrupt. This means we'd complete the
10868 * CS flip too soon.
10870 * Combining both checks should get us a good enough result. It may
10871 * still happen that the CS flip has been executed, but has not
10872 * yet actually completed. But in case the base address is the same
10873 * anyway, we don't really care.
10875 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10876 crtc->unpin_work->gtt_offset &&
10877 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10878 crtc->unpin_work->flip_count);
10881 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10883 struct drm_i915_private *dev_priv = dev->dev_private;
10884 struct intel_crtc *intel_crtc =
10885 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10886 unsigned long flags;
10890 * This is called both by irq handlers and the reset code (to complete
10891 * lost pageflips) so needs the full irqsave spinlocks.
10893 * NB: An MMIO update of the plane base pointer will also
10894 * generate a page-flip completion irq, i.e. every modeset
10895 * is also accompanied by a spurious intel_prepare_page_flip().
10897 spin_lock_irqsave(&dev->event_lock, flags);
10898 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10899 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10900 spin_unlock_irqrestore(&dev->event_lock, flags);
10903 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10905 /* Ensure that the work item is consistent when activating it ... */
10907 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10908 /* and that it is marked active as soon as the irq could fire. */
10912 static int intel_gen2_queue_flip(struct drm_device *dev,
10913 struct drm_crtc *crtc,
10914 struct drm_framebuffer *fb,
10915 struct drm_i915_gem_object *obj,
10916 struct drm_i915_gem_request *req,
10919 struct intel_engine_cs *ring = req->ring;
10920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10924 ret = intel_ring_begin(req, 6);
10928 /* Can't queue multiple flips, so wait for the previous
10929 * one to finish before executing the next.
10931 if (intel_crtc->plane)
10932 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10934 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10935 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10936 intel_ring_emit(ring, MI_NOOP);
10937 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10938 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10939 intel_ring_emit(ring, fb->pitches[0]);
10940 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10941 intel_ring_emit(ring, 0); /* aux display base address, unused */
10943 intel_mark_page_flip_active(intel_crtc);
10947 static int intel_gen3_queue_flip(struct drm_device *dev,
10948 struct drm_crtc *crtc,
10949 struct drm_framebuffer *fb,
10950 struct drm_i915_gem_object *obj,
10951 struct drm_i915_gem_request *req,
10954 struct intel_engine_cs *ring = req->ring;
10955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10959 ret = intel_ring_begin(req, 6);
10963 if (intel_crtc->plane)
10964 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10966 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10967 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10968 intel_ring_emit(ring, MI_NOOP);
10969 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10970 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10971 intel_ring_emit(ring, fb->pitches[0]);
10972 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10973 intel_ring_emit(ring, MI_NOOP);
10975 intel_mark_page_flip_active(intel_crtc);
10979 static int intel_gen4_queue_flip(struct drm_device *dev,
10980 struct drm_crtc *crtc,
10981 struct drm_framebuffer *fb,
10982 struct drm_i915_gem_object *obj,
10983 struct drm_i915_gem_request *req,
10986 struct intel_engine_cs *ring = req->ring;
10987 struct drm_i915_private *dev_priv = dev->dev_private;
10988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10989 uint32_t pf, pipesrc;
10992 ret = intel_ring_begin(req, 4);
10996 /* i965+ uses the linear or tiled offsets from the
10997 * Display Registers (which do not change across a page-flip)
10998 * so we need only reprogram the base address.
11000 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11001 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11002 intel_ring_emit(ring, fb->pitches[0]);
11003 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11006 /* XXX Enabling the panel-fitter across page-flip is so far
11007 * untested on non-native modes, so ignore it for now.
11008 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11011 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11012 intel_ring_emit(ring, pf | pipesrc);
11014 intel_mark_page_flip_active(intel_crtc);
11018 static int intel_gen6_queue_flip(struct drm_device *dev,
11019 struct drm_crtc *crtc,
11020 struct drm_framebuffer *fb,
11021 struct drm_i915_gem_object *obj,
11022 struct drm_i915_gem_request *req,
11025 struct intel_engine_cs *ring = req->ring;
11026 struct drm_i915_private *dev_priv = dev->dev_private;
11027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11028 uint32_t pf, pipesrc;
11031 ret = intel_ring_begin(req, 4);
11035 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11036 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11037 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11038 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11040 /* Contrary to the suggestions in the documentation,
11041 * "Enable Panel Fitter" does not seem to be required when page
11042 * flipping with a non-native mode, and worse causes a normal
11044 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11047 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11048 intel_ring_emit(ring, pf | pipesrc);
11050 intel_mark_page_flip_active(intel_crtc);
11054 static int intel_gen7_queue_flip(struct drm_device *dev,
11055 struct drm_crtc *crtc,
11056 struct drm_framebuffer *fb,
11057 struct drm_i915_gem_object *obj,
11058 struct drm_i915_gem_request *req,
11061 struct intel_engine_cs *ring = req->ring;
11062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11063 uint32_t plane_bit = 0;
11066 switch (intel_crtc->plane) {
11068 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11071 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11074 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11077 WARN_ONCE(1, "unknown plane in flip command\n");
11082 if (ring->id == RCS) {
11085 * On Gen 8, SRM is now taking an extra dword to accommodate
11086 * 48bits addresses, and we need a NOOP for the batch size to
11094 * BSpec MI_DISPLAY_FLIP for IVB:
11095 * "The full packet must be contained within the same cache line."
11097 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11098 * cacheline, if we ever start emitting more commands before
11099 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11100 * then do the cacheline alignment, and finally emit the
11103 ret = intel_ring_cacheline_align(req);
11107 ret = intel_ring_begin(req, len);
11111 /* Unmask the flip-done completion message. Note that the bspec says that
11112 * we should do this for both the BCS and RCS, and that we must not unmask
11113 * more than one flip event at any time (or ensure that one flip message
11114 * can be sent by waiting for flip-done prior to queueing new flips).
11115 * Experimentation says that BCS works despite DERRMR masking all
11116 * flip-done completion events and that unmasking all planes at once
11117 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11118 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11120 if (ring->id == RCS) {
11121 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11122 intel_ring_emit(ring, DERRMR);
11123 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11124 DERRMR_PIPEB_PRI_FLIP_DONE |
11125 DERRMR_PIPEC_PRI_FLIP_DONE));
11127 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11128 MI_SRM_LRM_GLOBAL_GTT);
11130 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11131 MI_SRM_LRM_GLOBAL_GTT);
11132 intel_ring_emit(ring, DERRMR);
11133 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11134 if (IS_GEN8(dev)) {
11135 intel_ring_emit(ring, 0);
11136 intel_ring_emit(ring, MI_NOOP);
11140 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11141 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11142 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11143 intel_ring_emit(ring, (MI_NOOP));
11145 intel_mark_page_flip_active(intel_crtc);
11149 static bool use_mmio_flip(struct intel_engine_cs *ring,
11150 struct drm_i915_gem_object *obj)
11153 * This is not being used for older platforms, because
11154 * non-availability of flip done interrupt forces us to use
11155 * CS flips. Older platforms derive flip done using some clever
11156 * tricks involving the flip_pending status bits and vblank irqs.
11157 * So using MMIO flips there would disrupt this mechanism.
11163 if (INTEL_INFO(ring->dev)->gen < 5)
11166 if (i915.use_mmio_flip < 0)
11168 else if (i915.use_mmio_flip > 0)
11170 else if (i915.enable_execlists)
11173 return ring != i915_gem_request_get_ring(obj->last_write_req);
11176 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11178 struct drm_device *dev = intel_crtc->base.dev;
11179 struct drm_i915_private *dev_priv = dev->dev_private;
11180 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11181 const enum pipe pipe = intel_crtc->pipe;
11184 ctl = I915_READ(PLANE_CTL(pipe, 0));
11185 ctl &= ~PLANE_CTL_TILED_MASK;
11186 switch (fb->modifier[0]) {
11187 case DRM_FORMAT_MOD_NONE:
11189 case I915_FORMAT_MOD_X_TILED:
11190 ctl |= PLANE_CTL_TILED_X;
11192 case I915_FORMAT_MOD_Y_TILED:
11193 ctl |= PLANE_CTL_TILED_Y;
11195 case I915_FORMAT_MOD_Yf_TILED:
11196 ctl |= PLANE_CTL_TILED_YF;
11199 MISSING_CASE(fb->modifier[0]);
11203 * The stride is either expressed as a multiple of 64 bytes chunks for
11204 * linear buffers or in number of tiles for tiled buffers.
11206 stride = fb->pitches[0] /
11207 intel_fb_stride_alignment(dev, fb->modifier[0],
11211 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11212 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11214 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11215 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11217 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11218 POSTING_READ(PLANE_SURF(pipe, 0));
11221 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11223 struct drm_device *dev = intel_crtc->base.dev;
11224 struct drm_i915_private *dev_priv = dev->dev_private;
11225 struct intel_framebuffer *intel_fb =
11226 to_intel_framebuffer(intel_crtc->base.primary->fb);
11227 struct drm_i915_gem_object *obj = intel_fb->obj;
11231 reg = DSPCNTR(intel_crtc->plane);
11232 dspcntr = I915_READ(reg);
11234 if (obj->tiling_mode != I915_TILING_NONE)
11235 dspcntr |= DISPPLANE_TILED;
11237 dspcntr &= ~DISPPLANE_TILED;
11239 I915_WRITE(reg, dspcntr);
11241 I915_WRITE(DSPSURF(intel_crtc->plane),
11242 intel_crtc->unpin_work->gtt_offset);
11243 POSTING_READ(DSPSURF(intel_crtc->plane));
11248 * XXX: This is the temporary way to update the plane registers until we get
11249 * around to using the usual plane update functions for MMIO flips
11251 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11253 struct drm_device *dev = intel_crtc->base.dev;
11254 u32 start_vbl_count;
11256 intel_mark_page_flip_active(intel_crtc);
11258 intel_pipe_update_start(intel_crtc, &start_vbl_count);
11260 if (INTEL_INFO(dev)->gen >= 9)
11261 skl_do_mmio_flip(intel_crtc);
11263 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11264 ilk_do_mmio_flip(intel_crtc);
11266 intel_pipe_update_end(intel_crtc, start_vbl_count);
11269 static void intel_mmio_flip_work_func(struct work_struct *work)
11271 struct intel_mmio_flip *mmio_flip =
11272 container_of(work, struct intel_mmio_flip, work);
11274 if (mmio_flip->req)
11275 WARN_ON(__i915_wait_request(mmio_flip->req,
11276 mmio_flip->crtc->reset_counter,
11278 &mmio_flip->i915->rps.mmioflips));
11280 intel_do_mmio_flip(mmio_flip->crtc);
11282 i915_gem_request_unreference__unlocked(mmio_flip->req);
11286 static int intel_queue_mmio_flip(struct drm_device *dev,
11287 struct drm_crtc *crtc,
11288 struct drm_framebuffer *fb,
11289 struct drm_i915_gem_object *obj,
11290 struct intel_engine_cs *ring,
11293 struct intel_mmio_flip *mmio_flip;
11295 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11296 if (mmio_flip == NULL)
11299 mmio_flip->i915 = to_i915(dev);
11300 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11301 mmio_flip->crtc = to_intel_crtc(crtc);
11303 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11304 schedule_work(&mmio_flip->work);
11309 static int intel_default_queue_flip(struct drm_device *dev,
11310 struct drm_crtc *crtc,
11311 struct drm_framebuffer *fb,
11312 struct drm_i915_gem_object *obj,
11313 struct drm_i915_gem_request *req,
11319 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11320 struct drm_crtc *crtc)
11322 struct drm_i915_private *dev_priv = dev->dev_private;
11323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11324 struct intel_unpin_work *work = intel_crtc->unpin_work;
11327 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11330 if (!work->enable_stall_check)
11333 if (work->flip_ready_vblank == 0) {
11334 if (work->flip_queued_req &&
11335 !i915_gem_request_completed(work->flip_queued_req, true))
11338 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11341 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11344 /* Potential stall - if we see that the flip has happened,
11345 * assume a missed interrupt. */
11346 if (INTEL_INFO(dev)->gen >= 4)
11347 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11349 addr = I915_READ(DSPADDR(intel_crtc->plane));
11351 /* There is a potential issue here with a false positive after a flip
11352 * to the same address. We could address this by checking for a
11353 * non-incrementing frame counter.
11355 return addr == work->gtt_offset;
11358 void intel_check_page_flip(struct drm_device *dev, int pipe)
11360 struct drm_i915_private *dev_priv = dev->dev_private;
11361 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11363 struct intel_unpin_work *work;
11365 WARN_ON(!in_interrupt());
11370 spin_lock(&dev->event_lock);
11371 work = intel_crtc->unpin_work;
11372 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11373 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11374 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11375 page_flip_completed(intel_crtc);
11378 if (work != NULL &&
11379 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11380 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11381 spin_unlock(&dev->event_lock);
11384 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11385 struct drm_framebuffer *fb,
11386 struct drm_pending_vblank_event *event,
11387 uint32_t page_flip_flags)
11389 struct drm_device *dev = crtc->dev;
11390 struct drm_i915_private *dev_priv = dev->dev_private;
11391 struct drm_framebuffer *old_fb = crtc->primary->fb;
11392 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11394 struct drm_plane *primary = crtc->primary;
11395 enum pipe pipe = intel_crtc->pipe;
11396 struct intel_unpin_work *work;
11397 struct intel_engine_cs *ring;
11399 struct drm_i915_gem_request *request = NULL;
11403 * drm_mode_page_flip_ioctl() should already catch this, but double
11404 * check to be safe. In the future we may enable pageflipping from
11405 * a disabled primary plane.
11407 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11410 /* Can't change pixel format via MI display flips. */
11411 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11415 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11416 * Note that pitch changes could also affect these register.
11418 if (INTEL_INFO(dev)->gen > 3 &&
11419 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11420 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11423 if (i915_terminally_wedged(&dev_priv->gpu_error))
11426 work = kzalloc(sizeof(*work), GFP_KERNEL);
11430 work->event = event;
11432 work->old_fb = old_fb;
11433 INIT_WORK(&work->work, intel_unpin_work_fn);
11435 ret = drm_crtc_vblank_get(crtc);
11439 /* We borrow the event spin lock for protecting unpin_work */
11440 spin_lock_irq(&dev->event_lock);
11441 if (intel_crtc->unpin_work) {
11442 /* Before declaring the flip queue wedged, check if
11443 * the hardware completed the operation behind our backs.
11445 if (__intel_pageflip_stall_check(dev, crtc)) {
11446 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11447 page_flip_completed(intel_crtc);
11449 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11450 spin_unlock_irq(&dev->event_lock);
11452 drm_crtc_vblank_put(crtc);
11457 intel_crtc->unpin_work = work;
11458 spin_unlock_irq(&dev->event_lock);
11460 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11461 flush_workqueue(dev_priv->wq);
11463 /* Reference the objects for the scheduled work. */
11464 drm_framebuffer_reference(work->old_fb);
11465 drm_gem_object_reference(&obj->base);
11467 crtc->primary->fb = fb;
11468 update_state_fb(crtc->primary);
11470 work->pending_flip_obj = obj;
11472 ret = i915_mutex_lock_interruptible(dev);
11476 atomic_inc(&intel_crtc->unpin_work_count);
11477 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11479 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11480 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11482 if (IS_VALLEYVIEW(dev)) {
11483 ring = &dev_priv->ring[BCS];
11484 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11485 /* vlv: DISPLAY_FLIP fails to change tiling */
11487 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11488 ring = &dev_priv->ring[BCS];
11489 } else if (INTEL_INFO(dev)->gen >= 7) {
11490 ring = i915_gem_request_get_ring(obj->last_write_req);
11491 if (ring == NULL || ring->id != RCS)
11492 ring = &dev_priv->ring[BCS];
11494 ring = &dev_priv->ring[RCS];
11497 mmio_flip = use_mmio_flip(ring, obj);
11499 /* When using CS flips, we want to emit semaphores between rings.
11500 * However, when using mmio flips we will create a task to do the
11501 * synchronisation, so all we want here is to pin the framebuffer
11502 * into the display plane and skip any waits.
11504 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11505 crtc->primary->state,
11506 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11508 goto cleanup_pending;
11510 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11511 + intel_crtc->dspaddr_offset;
11514 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11517 goto cleanup_unpin;
11519 i915_gem_request_assign(&work->flip_queued_req,
11520 obj->last_write_req);
11523 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11525 goto cleanup_unpin;
11528 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11531 goto cleanup_unpin;
11533 i915_gem_request_assign(&work->flip_queued_req, request);
11537 i915_add_request_no_flush(request);
11539 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11540 work->enable_stall_check = true;
11542 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11543 to_intel_plane(primary)->frontbuffer_bit);
11544 mutex_unlock(&dev->struct_mutex);
11546 intel_fbc_disable_crtc(intel_crtc);
11547 intel_frontbuffer_flip_prepare(dev,
11548 to_intel_plane(primary)->frontbuffer_bit);
11550 trace_i915_flip_request(intel_crtc->plane, obj);
11555 intel_unpin_fb_obj(fb, crtc->primary->state);
11558 i915_gem_request_cancel(request);
11559 atomic_dec(&intel_crtc->unpin_work_count);
11560 mutex_unlock(&dev->struct_mutex);
11562 crtc->primary->fb = old_fb;
11563 update_state_fb(crtc->primary);
11565 drm_gem_object_unreference_unlocked(&obj->base);
11566 drm_framebuffer_unreference(work->old_fb);
11568 spin_lock_irq(&dev->event_lock);
11569 intel_crtc->unpin_work = NULL;
11570 spin_unlock_irq(&dev->event_lock);
11572 drm_crtc_vblank_put(crtc);
11577 struct drm_atomic_state *state;
11578 struct drm_plane_state *plane_state;
11581 state = drm_atomic_state_alloc(dev);
11584 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11587 plane_state = drm_atomic_get_plane_state(state, primary);
11588 ret = PTR_ERR_OR_ZERO(plane_state);
11590 drm_atomic_set_fb_for_plane(plane_state, fb);
11592 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11594 ret = drm_atomic_commit(state);
11597 if (ret == -EDEADLK) {
11598 drm_modeset_backoff(state->acquire_ctx);
11599 drm_atomic_state_clear(state);
11604 drm_atomic_state_free(state);
11606 if (ret == 0 && event) {
11607 spin_lock_irq(&dev->event_lock);
11608 drm_send_vblank_event(dev, pipe, event);
11609 spin_unlock_irq(&dev->event_lock);
11617 * intel_wm_need_update - Check whether watermarks need updating
11618 * @plane: drm plane
11619 * @state: new plane state
11621 * Check current plane state versus the new one to determine whether
11622 * watermarks need to be recalculated.
11624 * Returns true or false.
11626 static bool intel_wm_need_update(struct drm_plane *plane,
11627 struct drm_plane_state *state)
11629 /* Update watermarks on tiling changes. */
11630 if (!plane->state->fb || !state->fb ||
11631 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11632 plane->state->rotation != state->rotation)
11635 if (plane->state->crtc_w != state->crtc_w)
11641 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11642 struct drm_plane_state *plane_state)
11644 struct drm_crtc *crtc = crtc_state->crtc;
11645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11646 struct drm_plane *plane = plane_state->plane;
11647 struct drm_device *dev = crtc->dev;
11648 struct drm_i915_private *dev_priv = dev->dev_private;
11649 struct intel_plane_state *old_plane_state =
11650 to_intel_plane_state(plane->state);
11651 int idx = intel_crtc->base.base.id, ret;
11652 int i = drm_plane_index(plane);
11653 bool mode_changed = needs_modeset(crtc_state);
11654 bool was_crtc_enabled = crtc->state->active;
11655 bool is_crtc_enabled = crtc_state->active;
11657 bool turn_off, turn_on, visible, was_visible;
11658 struct drm_framebuffer *fb = plane_state->fb;
11660 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11661 plane->type != DRM_PLANE_TYPE_CURSOR) {
11662 ret = skl_update_scaler_plane(
11663 to_intel_crtc_state(crtc_state),
11664 to_intel_plane_state(plane_state));
11670 * Disabling a plane is always okay; we just need to update
11671 * fb tracking in a special way since cleanup_fb() won't
11672 * get called by the plane helpers.
11674 if (old_plane_state->base.fb && !fb)
11675 intel_crtc->atomic.disabled_planes |= 1 << i;
11677 was_visible = old_plane_state->visible;
11678 visible = to_intel_plane_state(plane_state)->visible;
11680 if (!was_crtc_enabled && WARN_ON(was_visible))
11681 was_visible = false;
11683 if (!is_crtc_enabled && WARN_ON(visible))
11686 if (!was_visible && !visible)
11689 turn_off = was_visible && (!visible || mode_changed);
11690 turn_on = visible && (!was_visible || mode_changed);
11692 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11693 plane->base.id, fb ? fb->base.id : -1);
11695 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11696 plane->base.id, was_visible, visible,
11697 turn_off, turn_on, mode_changed);
11700 intel_crtc->atomic.update_wm_pre = true;
11701 /* must disable cxsr around plane enable/disable */
11702 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11703 intel_crtc->atomic.disable_cxsr = true;
11704 /* to potentially re-enable cxsr */
11705 intel_crtc->atomic.wait_vblank = true;
11706 intel_crtc->atomic.update_wm_post = true;
11708 } else if (turn_off) {
11709 intel_crtc->atomic.update_wm_post = true;
11710 /* must disable cxsr around plane enable/disable */
11711 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11712 if (is_crtc_enabled)
11713 intel_crtc->atomic.wait_vblank = true;
11714 intel_crtc->atomic.disable_cxsr = true;
11716 } else if (intel_wm_need_update(plane, plane_state)) {
11717 intel_crtc->atomic.update_wm_pre = true;
11721 intel_crtc->atomic.fb_bits |=
11722 to_intel_plane(plane)->frontbuffer_bit;
11724 switch (plane->type) {
11725 case DRM_PLANE_TYPE_PRIMARY:
11726 intel_crtc->atomic.wait_for_flips = true;
11727 intel_crtc->atomic.pre_disable_primary = turn_off;
11728 intel_crtc->atomic.post_enable_primary = turn_on;
11732 * FIXME: Actually if we will still have any other
11733 * plane enabled on the pipe we could let IPS enabled
11734 * still, but for now lets consider that when we make
11735 * primary invisible by setting DSPCNTR to 0 on
11736 * update_primary_plane function IPS needs to be
11739 intel_crtc->atomic.disable_ips = true;
11741 intel_crtc->atomic.disable_fbc = true;
11745 * FBC does not work on some platforms for rotated
11746 * planes, so disable it when rotation is not 0 and
11747 * update it when rotation is set back to 0.
11749 * FIXME: This is redundant with the fbc update done in
11750 * the primary plane enable function except that that
11751 * one is done too late. We eventually need to unify
11756 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11757 dev_priv->fbc.crtc == intel_crtc &&
11758 plane_state->rotation != BIT(DRM_ROTATE_0))
11759 intel_crtc->atomic.disable_fbc = true;
11762 * BDW signals flip done immediately if the plane
11763 * is disabled, even if the plane enable is already
11764 * armed to occur at the next vblank :(
11766 if (turn_on && IS_BROADWELL(dev))
11767 intel_crtc->atomic.wait_vblank = true;
11769 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11771 case DRM_PLANE_TYPE_CURSOR:
11773 case DRM_PLANE_TYPE_OVERLAY:
11774 if (turn_off && !mode_changed) {
11775 intel_crtc->atomic.wait_vblank = true;
11776 intel_crtc->atomic.update_sprite_watermarks |=
11783 static bool encoders_cloneable(const struct intel_encoder *a,
11784 const struct intel_encoder *b)
11786 /* masks could be asymmetric, so check both ways */
11787 return a == b || (a->cloneable & (1 << b->type) &&
11788 b->cloneable & (1 << a->type));
11791 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11792 struct intel_crtc *crtc,
11793 struct intel_encoder *encoder)
11795 struct intel_encoder *source_encoder;
11796 struct drm_connector *connector;
11797 struct drm_connector_state *connector_state;
11800 for_each_connector_in_state(state, connector, connector_state, i) {
11801 if (connector_state->crtc != &crtc->base)
11805 to_intel_encoder(connector_state->best_encoder);
11806 if (!encoders_cloneable(encoder, source_encoder))
11813 static bool check_encoder_cloning(struct drm_atomic_state *state,
11814 struct intel_crtc *crtc)
11816 struct intel_encoder *encoder;
11817 struct drm_connector *connector;
11818 struct drm_connector_state *connector_state;
11821 for_each_connector_in_state(state, connector, connector_state, i) {
11822 if (connector_state->crtc != &crtc->base)
11825 encoder = to_intel_encoder(connector_state->best_encoder);
11826 if (!check_single_encoder_cloning(state, crtc, encoder))
11833 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11834 struct drm_crtc_state *crtc_state)
11836 struct drm_device *dev = crtc->dev;
11837 struct drm_i915_private *dev_priv = dev->dev_private;
11838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11839 struct intel_crtc_state *pipe_config =
11840 to_intel_crtc_state(crtc_state);
11841 struct drm_atomic_state *state = crtc_state->state;
11842 int ret, idx = crtc->base.id;
11843 bool mode_changed = needs_modeset(crtc_state);
11845 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11846 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11850 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11851 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11852 idx, crtc->state->active, intel_crtc->active);
11854 if (mode_changed && !crtc_state->active)
11855 intel_crtc->atomic.update_wm_post = true;
11857 if (mode_changed && crtc_state->enable &&
11858 dev_priv->display.crtc_compute_clock &&
11859 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11860 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11867 if (INTEL_INFO(dev)->gen >= 9) {
11869 ret = skl_update_scaler_crtc(pipe_config);
11872 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11879 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11880 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11881 .load_lut = intel_crtc_load_lut,
11882 .atomic_begin = intel_begin_crtc_commit,
11883 .atomic_flush = intel_finish_crtc_commit,
11884 .atomic_check = intel_crtc_atomic_check,
11887 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11889 struct intel_connector *connector;
11891 for_each_intel_connector(dev, connector) {
11892 if (connector->base.encoder) {
11893 connector->base.state->best_encoder =
11894 connector->base.encoder;
11895 connector->base.state->crtc =
11896 connector->base.encoder->crtc;
11898 connector->base.state->best_encoder = NULL;
11899 connector->base.state->crtc = NULL;
11905 connected_sink_compute_bpp(struct intel_connector *connector,
11906 struct intel_crtc_state *pipe_config)
11908 int bpp = pipe_config->pipe_bpp;
11910 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11911 connector->base.base.id,
11912 connector->base.name);
11914 /* Don't use an invalid EDID bpc value */
11915 if (connector->base.display_info.bpc &&
11916 connector->base.display_info.bpc * 3 < bpp) {
11917 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11918 bpp, connector->base.display_info.bpc*3);
11919 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11922 /* Clamp bpp to 8 on screens without EDID 1.4 */
11923 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11924 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11926 pipe_config->pipe_bpp = 24;
11931 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11932 struct intel_crtc_state *pipe_config)
11934 struct drm_device *dev = crtc->base.dev;
11935 struct drm_atomic_state *state;
11936 struct drm_connector *connector;
11937 struct drm_connector_state *connector_state;
11940 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11942 else if (INTEL_INFO(dev)->gen >= 5)
11948 pipe_config->pipe_bpp = bpp;
11950 state = pipe_config->base.state;
11952 /* Clamp display bpp to EDID value */
11953 for_each_connector_in_state(state, connector, connector_state, i) {
11954 if (connector_state->crtc != &crtc->base)
11957 connected_sink_compute_bpp(to_intel_connector(connector),
11964 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11966 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11967 "type: 0x%x flags: 0x%x\n",
11969 mode->crtc_hdisplay, mode->crtc_hsync_start,
11970 mode->crtc_hsync_end, mode->crtc_htotal,
11971 mode->crtc_vdisplay, mode->crtc_vsync_start,
11972 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11975 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11976 struct intel_crtc_state *pipe_config,
11977 const char *context)
11979 struct drm_device *dev = crtc->base.dev;
11980 struct drm_plane *plane;
11981 struct intel_plane *intel_plane;
11982 struct intel_plane_state *state;
11983 struct drm_framebuffer *fb;
11985 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11986 context, pipe_config, pipe_name(crtc->pipe));
11988 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11989 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11990 pipe_config->pipe_bpp, pipe_config->dither);
11991 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11992 pipe_config->has_pch_encoder,
11993 pipe_config->fdi_lanes,
11994 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11995 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11996 pipe_config->fdi_m_n.tu);
11997 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11998 pipe_config->has_dp_encoder,
11999 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12000 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12001 pipe_config->dp_m_n.tu);
12003 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12004 pipe_config->has_dp_encoder,
12005 pipe_config->dp_m2_n2.gmch_m,
12006 pipe_config->dp_m2_n2.gmch_n,
12007 pipe_config->dp_m2_n2.link_m,
12008 pipe_config->dp_m2_n2.link_n,
12009 pipe_config->dp_m2_n2.tu);
12011 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12012 pipe_config->has_audio,
12013 pipe_config->has_infoframe);
12015 DRM_DEBUG_KMS("requested mode:\n");
12016 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12017 DRM_DEBUG_KMS("adjusted mode:\n");
12018 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12019 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12020 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12021 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12022 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12023 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12025 pipe_config->scaler_state.scaler_users,
12026 pipe_config->scaler_state.scaler_id);
12027 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12028 pipe_config->gmch_pfit.control,
12029 pipe_config->gmch_pfit.pgm_ratios,
12030 pipe_config->gmch_pfit.lvds_border_bits);
12031 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12032 pipe_config->pch_pfit.pos,
12033 pipe_config->pch_pfit.size,
12034 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12035 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12036 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12038 if (IS_BROXTON(dev)) {
12039 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12040 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12041 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12042 pipe_config->ddi_pll_sel,
12043 pipe_config->dpll_hw_state.ebb0,
12044 pipe_config->dpll_hw_state.ebb4,
12045 pipe_config->dpll_hw_state.pll0,
12046 pipe_config->dpll_hw_state.pll1,
12047 pipe_config->dpll_hw_state.pll2,
12048 pipe_config->dpll_hw_state.pll3,
12049 pipe_config->dpll_hw_state.pll6,
12050 pipe_config->dpll_hw_state.pll8,
12051 pipe_config->dpll_hw_state.pll9,
12052 pipe_config->dpll_hw_state.pll10,
12053 pipe_config->dpll_hw_state.pcsdw12);
12054 } else if (IS_SKYLAKE(dev)) {
12055 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12056 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12057 pipe_config->ddi_pll_sel,
12058 pipe_config->dpll_hw_state.ctrl1,
12059 pipe_config->dpll_hw_state.cfgcr1,
12060 pipe_config->dpll_hw_state.cfgcr2);
12061 } else if (HAS_DDI(dev)) {
12062 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12063 pipe_config->ddi_pll_sel,
12064 pipe_config->dpll_hw_state.wrpll);
12066 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12067 "fp0: 0x%x, fp1: 0x%x\n",
12068 pipe_config->dpll_hw_state.dpll,
12069 pipe_config->dpll_hw_state.dpll_md,
12070 pipe_config->dpll_hw_state.fp0,
12071 pipe_config->dpll_hw_state.fp1);
12074 DRM_DEBUG_KMS("planes on this crtc\n");
12075 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12076 intel_plane = to_intel_plane(plane);
12077 if (intel_plane->pipe != crtc->pipe)
12080 state = to_intel_plane_state(plane->state);
12081 fb = state->base.fb;
12083 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12084 "disabled, scaler_id = %d\n",
12085 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12086 plane->base.id, intel_plane->pipe,
12087 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12088 drm_plane_index(plane), state->scaler_id);
12092 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12093 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12094 plane->base.id, intel_plane->pipe,
12095 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12096 drm_plane_index(plane));
12097 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12098 fb->base.id, fb->width, fb->height, fb->pixel_format);
12099 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12101 state->src.x1 >> 16, state->src.y1 >> 16,
12102 drm_rect_width(&state->src) >> 16,
12103 drm_rect_height(&state->src) >> 16,
12104 state->dst.x1, state->dst.y1,
12105 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12109 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12111 struct drm_device *dev = state->dev;
12112 struct intel_encoder *encoder;
12113 struct drm_connector *connector;
12114 struct drm_connector_state *connector_state;
12115 unsigned int used_ports = 0;
12119 * Walk the connector list instead of the encoder
12120 * list to detect the problem on ddi platforms
12121 * where there's just one encoder per digital port.
12123 for_each_connector_in_state(state, connector, connector_state, i) {
12124 if (!connector_state->best_encoder)
12127 encoder = to_intel_encoder(connector_state->best_encoder);
12129 WARN_ON(!connector_state->crtc);
12131 switch (encoder->type) {
12132 unsigned int port_mask;
12133 case INTEL_OUTPUT_UNKNOWN:
12134 if (WARN_ON(!HAS_DDI(dev)))
12136 case INTEL_OUTPUT_DISPLAYPORT:
12137 case INTEL_OUTPUT_HDMI:
12138 case INTEL_OUTPUT_EDP:
12139 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12141 /* the same port mustn't appear more than once */
12142 if (used_ports & port_mask)
12145 used_ports |= port_mask;
12155 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12157 struct drm_crtc_state tmp_state;
12158 struct intel_crtc_scaler_state scaler_state;
12159 struct intel_dpll_hw_state dpll_hw_state;
12160 enum intel_dpll_id shared_dpll;
12161 uint32_t ddi_pll_sel;
12163 /* FIXME: before the switch to atomic started, a new pipe_config was
12164 * kzalloc'd. Code that depends on any field being zero should be
12165 * fixed, so that the crtc_state can be safely duplicated. For now,
12166 * only fields that are know to not cause problems are preserved. */
12168 tmp_state = crtc_state->base;
12169 scaler_state = crtc_state->scaler_state;
12170 shared_dpll = crtc_state->shared_dpll;
12171 dpll_hw_state = crtc_state->dpll_hw_state;
12172 ddi_pll_sel = crtc_state->ddi_pll_sel;
12174 memset(crtc_state, 0, sizeof *crtc_state);
12176 crtc_state->base = tmp_state;
12177 crtc_state->scaler_state = scaler_state;
12178 crtc_state->shared_dpll = shared_dpll;
12179 crtc_state->dpll_hw_state = dpll_hw_state;
12180 crtc_state->ddi_pll_sel = ddi_pll_sel;
12184 intel_modeset_pipe_config(struct drm_crtc *crtc,
12185 struct intel_crtc_state *pipe_config)
12187 struct drm_atomic_state *state = pipe_config->base.state;
12188 struct intel_encoder *encoder;
12189 struct drm_connector *connector;
12190 struct drm_connector_state *connector_state;
12191 int base_bpp, ret = -EINVAL;
12195 clear_intel_crtc_state(pipe_config);
12197 pipe_config->cpu_transcoder =
12198 (enum transcoder) to_intel_crtc(crtc)->pipe;
12201 * Sanitize sync polarity flags based on requested ones. If neither
12202 * positive or negative polarity is requested, treat this as meaning
12203 * negative polarity.
12205 if (!(pipe_config->base.adjusted_mode.flags &
12206 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12207 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12209 if (!(pipe_config->base.adjusted_mode.flags &
12210 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12211 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12213 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12214 * plane pixel format and any sink constraints into account. Returns the
12215 * source plane bpp so that dithering can be selected on mismatches
12216 * after encoders and crtc also have had their say. */
12217 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12223 * Determine the real pipe dimensions. Note that stereo modes can
12224 * increase the actual pipe size due to the frame doubling and
12225 * insertion of additional space for blanks between the frame. This
12226 * is stored in the crtc timings. We use the requested mode to do this
12227 * computation to clearly distinguish it from the adjusted mode, which
12228 * can be changed by the connectors in the below retry loop.
12230 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12231 &pipe_config->pipe_src_w,
12232 &pipe_config->pipe_src_h);
12235 /* Ensure the port clock defaults are reset when retrying. */
12236 pipe_config->port_clock = 0;
12237 pipe_config->pixel_multiplier = 1;
12239 /* Fill in default crtc timings, allow encoders to overwrite them. */
12240 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12241 CRTC_STEREO_DOUBLE);
12243 /* Pass our mode to the connectors and the CRTC to give them a chance to
12244 * adjust it according to limitations or connector properties, and also
12245 * a chance to reject the mode entirely.
12247 for_each_connector_in_state(state, connector, connector_state, i) {
12248 if (connector_state->crtc != crtc)
12251 encoder = to_intel_encoder(connector_state->best_encoder);
12253 if (!(encoder->compute_config(encoder, pipe_config))) {
12254 DRM_DEBUG_KMS("Encoder config failure\n");
12259 /* Set default port clock if not overwritten by the encoder. Needs to be
12260 * done afterwards in case the encoder adjusts the mode. */
12261 if (!pipe_config->port_clock)
12262 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12263 * pipe_config->pixel_multiplier;
12265 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12267 DRM_DEBUG_KMS("CRTC fixup failed\n");
12271 if (ret == RETRY) {
12272 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12277 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12279 goto encoder_retry;
12282 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12283 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12284 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12290 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12292 struct drm_encoder *encoder;
12293 struct drm_device *dev = crtc->dev;
12295 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12296 if (encoder->crtc == crtc)
12303 intel_modeset_update_state(struct drm_atomic_state *state)
12305 struct drm_device *dev = state->dev;
12306 struct intel_encoder *intel_encoder;
12307 struct drm_crtc *crtc;
12308 struct drm_crtc_state *crtc_state;
12309 struct drm_connector *connector;
12312 intel_shared_dpll_commit(state);
12314 for_each_intel_encoder(dev, intel_encoder) {
12315 if (!intel_encoder->base.crtc)
12318 crtc = intel_encoder->base.crtc;
12319 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12320 if (!crtc_state || !needs_modeset(crtc->state))
12323 intel_encoder->connectors_active = false;
12326 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12328 /* Double check state. */
12329 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12330 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12332 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12334 /* Update hwmode for vblank functions */
12335 if (crtc->state->active)
12336 crtc->hwmode = crtc->state->adjusted_mode;
12338 crtc->hwmode.crtc_clock = 0;
12341 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12342 if (!connector->encoder || !connector->encoder->crtc)
12345 crtc = connector->encoder->crtc;
12346 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12347 if (!crtc_state || !needs_modeset(crtc->state))
12350 if (crtc->state->active) {
12351 intel_encoder = to_intel_encoder(connector->encoder);
12352 intel_encoder->connectors_active = true;
12357 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12361 if (clock1 == clock2)
12364 if (!clock1 || !clock2)
12367 diff = abs(clock1 - clock2);
12369 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12375 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12376 list_for_each_entry((intel_crtc), \
12377 &(dev)->mode_config.crtc_list, \
12379 if (mask & (1 <<(intel_crtc)->pipe))
12383 intel_compare_m_n(unsigned int m, unsigned int n,
12384 unsigned int m2, unsigned int n2,
12387 if (m == m2 && n == n2)
12390 if (exact || !m || !n || !m2 || !n2)
12393 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12400 } else if (m < m2) {
12407 return m == m2 && n == n2;
12411 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12412 struct intel_link_m_n *m2_n2,
12415 if (m_n->tu == m2_n2->tu &&
12416 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12417 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12418 intel_compare_m_n(m_n->link_m, m_n->link_n,
12419 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12430 intel_pipe_config_compare(struct drm_device *dev,
12431 struct intel_crtc_state *current_config,
12432 struct intel_crtc_state *pipe_config,
12437 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12440 DRM_ERROR(fmt, ##__VA_ARGS__); \
12442 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12445 #define PIPE_CONF_CHECK_X(name) \
12446 if (current_config->name != pipe_config->name) { \
12447 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12448 "(expected 0x%08x, found 0x%08x)\n", \
12449 current_config->name, \
12450 pipe_config->name); \
12454 #define PIPE_CONF_CHECK_I(name) \
12455 if (current_config->name != pipe_config->name) { \
12456 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12457 "(expected %i, found %i)\n", \
12458 current_config->name, \
12459 pipe_config->name); \
12463 #define PIPE_CONF_CHECK_M_N(name) \
12464 if (!intel_compare_link_m_n(¤t_config->name, \
12465 &pipe_config->name,\
12467 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12468 "(expected tu %i gmch %i/%i link %i/%i, " \
12469 "found tu %i, gmch %i/%i link %i/%i)\n", \
12470 current_config->name.tu, \
12471 current_config->name.gmch_m, \
12472 current_config->name.gmch_n, \
12473 current_config->name.link_m, \
12474 current_config->name.link_n, \
12475 pipe_config->name.tu, \
12476 pipe_config->name.gmch_m, \
12477 pipe_config->name.gmch_n, \
12478 pipe_config->name.link_m, \
12479 pipe_config->name.link_n); \
12483 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12484 if (!intel_compare_link_m_n(¤t_config->name, \
12485 &pipe_config->name, adjust) && \
12486 !intel_compare_link_m_n(¤t_config->alt_name, \
12487 &pipe_config->name, adjust)) { \
12488 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12489 "(expected tu %i gmch %i/%i link %i/%i, " \
12490 "or tu %i gmch %i/%i link %i/%i, " \
12491 "found tu %i, gmch %i/%i link %i/%i)\n", \
12492 current_config->name.tu, \
12493 current_config->name.gmch_m, \
12494 current_config->name.gmch_n, \
12495 current_config->name.link_m, \
12496 current_config->name.link_n, \
12497 current_config->alt_name.tu, \
12498 current_config->alt_name.gmch_m, \
12499 current_config->alt_name.gmch_n, \
12500 current_config->alt_name.link_m, \
12501 current_config->alt_name.link_n, \
12502 pipe_config->name.tu, \
12503 pipe_config->name.gmch_m, \
12504 pipe_config->name.gmch_n, \
12505 pipe_config->name.link_m, \
12506 pipe_config->name.link_n); \
12510 /* This is required for BDW+ where there is only one set of registers for
12511 * switching between high and low RR.
12512 * This macro can be used whenever a comparison has to be made between one
12513 * hw state and multiple sw state variables.
12515 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12516 if ((current_config->name != pipe_config->name) && \
12517 (current_config->alt_name != pipe_config->name)) { \
12518 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12519 "(expected %i or %i, found %i)\n", \
12520 current_config->name, \
12521 current_config->alt_name, \
12522 pipe_config->name); \
12526 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12527 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12528 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12529 "(expected %i, found %i)\n", \
12530 current_config->name & (mask), \
12531 pipe_config->name & (mask)); \
12535 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12536 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12537 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12538 "(expected %i, found %i)\n", \
12539 current_config->name, \
12540 pipe_config->name); \
12544 #define PIPE_CONF_QUIRK(quirk) \
12545 ((current_config->quirks | pipe_config->quirks) & (quirk))
12547 PIPE_CONF_CHECK_I(cpu_transcoder);
12549 PIPE_CONF_CHECK_I(has_pch_encoder);
12550 PIPE_CONF_CHECK_I(fdi_lanes);
12551 PIPE_CONF_CHECK_M_N(fdi_m_n);
12553 PIPE_CONF_CHECK_I(has_dp_encoder);
12555 if (INTEL_INFO(dev)->gen < 8) {
12556 PIPE_CONF_CHECK_M_N(dp_m_n);
12558 PIPE_CONF_CHECK_I(has_drrs);
12559 if (current_config->has_drrs)
12560 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12562 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12564 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12565 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12566 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12567 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12568 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12569 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12571 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12572 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12573 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12574 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12575 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12576 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12578 PIPE_CONF_CHECK_I(pixel_multiplier);
12579 PIPE_CONF_CHECK_I(has_hdmi_sink);
12580 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12581 IS_VALLEYVIEW(dev))
12582 PIPE_CONF_CHECK_I(limited_color_range);
12583 PIPE_CONF_CHECK_I(has_infoframe);
12585 PIPE_CONF_CHECK_I(has_audio);
12587 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12588 DRM_MODE_FLAG_INTERLACE);
12590 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12591 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12592 DRM_MODE_FLAG_PHSYNC);
12593 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12594 DRM_MODE_FLAG_NHSYNC);
12595 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12596 DRM_MODE_FLAG_PVSYNC);
12597 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12598 DRM_MODE_FLAG_NVSYNC);
12601 PIPE_CONF_CHECK_I(pipe_src_w);
12602 PIPE_CONF_CHECK_I(pipe_src_h);
12604 PIPE_CONF_CHECK_I(gmch_pfit.control);
12605 /* pfit ratios are autocomputed by the hw on gen4+ */
12606 if (INTEL_INFO(dev)->gen < 4)
12607 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12608 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12610 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12611 if (current_config->pch_pfit.enabled) {
12612 PIPE_CONF_CHECK_I(pch_pfit.pos);
12613 PIPE_CONF_CHECK_I(pch_pfit.size);
12616 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12618 /* BDW+ don't expose a synchronous way to read the state */
12619 if (IS_HASWELL(dev))
12620 PIPE_CONF_CHECK_I(ips_enabled);
12622 PIPE_CONF_CHECK_I(double_wide);
12624 PIPE_CONF_CHECK_X(ddi_pll_sel);
12626 PIPE_CONF_CHECK_I(shared_dpll);
12627 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12628 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12629 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12630 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12631 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12632 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12633 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12634 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12636 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12637 PIPE_CONF_CHECK_I(pipe_bpp);
12639 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12640 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12642 #undef PIPE_CONF_CHECK_X
12643 #undef PIPE_CONF_CHECK_I
12644 #undef PIPE_CONF_CHECK_I_ALT
12645 #undef PIPE_CONF_CHECK_FLAGS
12646 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12647 #undef PIPE_CONF_QUIRK
12648 #undef INTEL_ERR_OR_DBG_KMS
12653 static void check_wm_state(struct drm_device *dev)
12655 struct drm_i915_private *dev_priv = dev->dev_private;
12656 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12657 struct intel_crtc *intel_crtc;
12660 if (INTEL_INFO(dev)->gen < 9)
12663 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12664 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12666 for_each_intel_crtc(dev, intel_crtc) {
12667 struct skl_ddb_entry *hw_entry, *sw_entry;
12668 const enum pipe pipe = intel_crtc->pipe;
12670 if (!intel_crtc->active)
12674 for_each_plane(dev_priv, pipe, plane) {
12675 hw_entry = &hw_ddb.plane[pipe][plane];
12676 sw_entry = &sw_ddb->plane[pipe][plane];
12678 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12681 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12682 "(expected (%u,%u), found (%u,%u))\n",
12683 pipe_name(pipe), plane + 1,
12684 sw_entry->start, sw_entry->end,
12685 hw_entry->start, hw_entry->end);
12689 hw_entry = &hw_ddb.cursor[pipe];
12690 sw_entry = &sw_ddb->cursor[pipe];
12692 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12695 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12696 "(expected (%u,%u), found (%u,%u))\n",
12698 sw_entry->start, sw_entry->end,
12699 hw_entry->start, hw_entry->end);
12704 check_connector_state(struct drm_device *dev)
12706 struct intel_connector *connector;
12708 for_each_intel_connector(dev, connector) {
12709 struct drm_encoder *encoder = connector->base.encoder;
12710 struct drm_connector_state *state = connector->base.state;
12712 /* This also checks the encoder/connector hw state with the
12713 * ->get_hw_state callbacks. */
12714 intel_connector_check_state(connector);
12716 I915_STATE_WARN(state->best_encoder != encoder,
12717 "connector's staged encoder doesn't match current encoder\n");
12722 check_encoder_state(struct drm_device *dev)
12724 struct intel_encoder *encoder;
12725 struct intel_connector *connector;
12727 for_each_intel_encoder(dev, encoder) {
12728 bool enabled = false;
12729 bool active = false;
12730 enum pipe pipe, tracked_pipe;
12732 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12733 encoder->base.base.id,
12734 encoder->base.name);
12736 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12737 "encoder's active_connectors set, but no crtc\n");
12739 for_each_intel_connector(dev, connector) {
12740 if (connector->base.encoder != &encoder->base)
12743 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12746 I915_STATE_WARN(connector->base.state->crtc !=
12747 encoder->base.crtc,
12748 "connector's crtc doesn't match encoder crtc\n");
12751 * for MST connectors if we unplug the connector is gone
12752 * away but the encoder is still connected to a crtc
12753 * until a modeset happens in response to the hotplug.
12755 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12758 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12759 "encoder's enabled state mismatch "
12760 "(expected %i, found %i)\n",
12761 !!encoder->base.crtc, enabled);
12762 I915_STATE_WARN(active && !encoder->base.crtc,
12763 "active encoder with no crtc\n");
12765 I915_STATE_WARN(encoder->connectors_active != active,
12766 "encoder's computed active state doesn't match tracked active state "
12767 "(expected %i, found %i)\n", active, encoder->connectors_active);
12769 active = encoder->get_hw_state(encoder, &pipe);
12770 I915_STATE_WARN(active != encoder->connectors_active,
12771 "encoder's hw state doesn't match sw tracking "
12772 "(expected %i, found %i)\n",
12773 encoder->connectors_active, active);
12775 if (!encoder->base.crtc)
12778 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12779 I915_STATE_WARN(active && pipe != tracked_pipe,
12780 "active encoder's pipe doesn't match"
12781 "(expected %i, found %i)\n",
12782 tracked_pipe, pipe);
12788 check_crtc_state(struct drm_device *dev)
12790 struct drm_i915_private *dev_priv = dev->dev_private;
12791 struct intel_crtc *crtc;
12792 struct intel_encoder *encoder;
12793 struct intel_crtc_state pipe_config;
12795 for_each_intel_crtc(dev, crtc) {
12796 bool enabled = false;
12797 bool active = false;
12799 memset(&pipe_config, 0, sizeof(pipe_config));
12801 DRM_DEBUG_KMS("[CRTC:%d]\n",
12802 crtc->base.base.id);
12804 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12805 "active crtc, but not enabled in sw tracking\n");
12807 for_each_intel_encoder(dev, encoder) {
12808 if (encoder->base.crtc != &crtc->base)
12811 if (encoder->connectors_active)
12815 I915_STATE_WARN(active != crtc->active,
12816 "crtc's computed active state doesn't match tracked active state "
12817 "(expected %i, found %i)\n", active, crtc->active);
12818 I915_STATE_WARN(enabled != crtc->base.state->enable,
12819 "crtc's computed enabled state doesn't match tracked enabled state "
12820 "(expected %i, found %i)\n", enabled,
12821 crtc->base.state->enable);
12823 active = dev_priv->display.get_pipe_config(crtc,
12826 /* hw state is inconsistent with the pipe quirk */
12827 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12828 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12829 active = crtc->active;
12831 for_each_intel_encoder(dev, encoder) {
12833 if (encoder->base.crtc != &crtc->base)
12835 if (encoder->get_hw_state(encoder, &pipe))
12836 encoder->get_config(encoder, &pipe_config);
12839 I915_STATE_WARN(crtc->active != active,
12840 "crtc active state doesn't match with hw state "
12841 "(expected %i, found %i)\n", crtc->active, active);
12843 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12844 "transitional active state does not match atomic hw state "
12845 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12850 if (!intel_pipe_config_compare(dev, crtc->config,
12851 &pipe_config, false)) {
12852 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12853 intel_dump_pipe_config(crtc, &pipe_config,
12855 intel_dump_pipe_config(crtc, crtc->config,
12862 check_shared_dpll_state(struct drm_device *dev)
12864 struct drm_i915_private *dev_priv = dev->dev_private;
12865 struct intel_crtc *crtc;
12866 struct intel_dpll_hw_state dpll_hw_state;
12869 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12870 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12871 int enabled_crtcs = 0, active_crtcs = 0;
12874 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12876 DRM_DEBUG_KMS("%s\n", pll->name);
12878 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12880 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12881 "more active pll users than references: %i vs %i\n",
12882 pll->active, hweight32(pll->config.crtc_mask));
12883 I915_STATE_WARN(pll->active && !pll->on,
12884 "pll in active use but not on in sw tracking\n");
12885 I915_STATE_WARN(pll->on && !pll->active,
12886 "pll in on but not on in use in sw tracking\n");
12887 I915_STATE_WARN(pll->on != active,
12888 "pll on state mismatch (expected %i, found %i)\n",
12891 for_each_intel_crtc(dev, crtc) {
12892 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12894 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12897 I915_STATE_WARN(pll->active != active_crtcs,
12898 "pll active crtcs mismatch (expected %i, found %i)\n",
12899 pll->active, active_crtcs);
12900 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12901 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12902 hweight32(pll->config.crtc_mask), enabled_crtcs);
12904 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12905 sizeof(dpll_hw_state)),
12906 "pll hw state mismatch\n");
12911 intel_modeset_check_state(struct drm_device *dev)
12913 check_wm_state(dev);
12914 check_connector_state(dev);
12915 check_encoder_state(dev);
12916 check_crtc_state(dev);
12917 check_shared_dpll_state(dev);
12920 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12924 * FDI already provided one idea for the dotclock.
12925 * Yell if the encoder disagrees.
12927 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12928 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12929 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12932 static void update_scanline_offset(struct intel_crtc *crtc)
12934 struct drm_device *dev = crtc->base.dev;
12937 * The scanline counter increments at the leading edge of hsync.
12939 * On most platforms it starts counting from vtotal-1 on the
12940 * first active line. That means the scanline counter value is
12941 * always one less than what we would expect. Ie. just after
12942 * start of vblank, which also occurs at start of hsync (on the
12943 * last active line), the scanline counter will read vblank_start-1.
12945 * On gen2 the scanline counter starts counting from 1 instead
12946 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12947 * to keep the value positive), instead of adding one.
12949 * On HSW+ the behaviour of the scanline counter depends on the output
12950 * type. For DP ports it behaves like most other platforms, but on HDMI
12951 * there's an extra 1 line difference. So we need to add two instead of
12952 * one to the value.
12954 if (IS_GEN2(dev)) {
12955 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12958 vtotal = mode->crtc_vtotal;
12959 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12962 crtc->scanline_offset = vtotal - 1;
12963 } else if (HAS_DDI(dev) &&
12964 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12965 crtc->scanline_offset = 2;
12967 crtc->scanline_offset = 1;
12970 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12972 struct drm_device *dev = state->dev;
12973 struct drm_i915_private *dev_priv = to_i915(dev);
12974 struct intel_shared_dpll_config *shared_dpll = NULL;
12975 struct intel_crtc *intel_crtc;
12976 struct intel_crtc_state *intel_crtc_state;
12977 struct drm_crtc *crtc;
12978 struct drm_crtc_state *crtc_state;
12981 if (!dev_priv->display.crtc_compute_clock)
12984 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12987 intel_crtc = to_intel_crtc(crtc);
12988 intel_crtc_state = to_intel_crtc_state(crtc_state);
12989 dpll = intel_crtc_state->shared_dpll;
12991 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12994 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12997 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12999 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13004 * This implements the workaround described in the "notes" section of the mode
13005 * set sequence documentation. When going from no pipes or single pipe to
13006 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13007 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13009 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13011 struct drm_crtc_state *crtc_state;
13012 struct intel_crtc *intel_crtc;
13013 struct drm_crtc *crtc;
13014 struct intel_crtc_state *first_crtc_state = NULL;
13015 struct intel_crtc_state *other_crtc_state = NULL;
13016 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13019 /* look at all crtc's that are going to be enabled in during modeset */
13020 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13021 intel_crtc = to_intel_crtc(crtc);
13023 if (!crtc_state->active || !needs_modeset(crtc_state))
13026 if (first_crtc_state) {
13027 other_crtc_state = to_intel_crtc_state(crtc_state);
13030 first_crtc_state = to_intel_crtc_state(crtc_state);
13031 first_pipe = intel_crtc->pipe;
13035 /* No workaround needed? */
13036 if (!first_crtc_state)
13039 /* w/a possibly needed, check how many crtc's are already enabled. */
13040 for_each_intel_crtc(state->dev, intel_crtc) {
13041 struct intel_crtc_state *pipe_config;
13043 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13044 if (IS_ERR(pipe_config))
13045 return PTR_ERR(pipe_config);
13047 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13049 if (!pipe_config->base.active ||
13050 needs_modeset(&pipe_config->base))
13053 /* 2 or more enabled crtcs means no need for w/a */
13054 if (enabled_pipe != INVALID_PIPE)
13057 enabled_pipe = intel_crtc->pipe;
13060 if (enabled_pipe != INVALID_PIPE)
13061 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13062 else if (other_crtc_state)
13063 other_crtc_state->hsw_workaround_pipe = first_pipe;
13068 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13070 struct drm_crtc *crtc;
13071 struct drm_crtc_state *crtc_state;
13074 /* add all active pipes to the state */
13075 for_each_crtc(state->dev, crtc) {
13076 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13077 if (IS_ERR(crtc_state))
13078 return PTR_ERR(crtc_state);
13080 if (!crtc_state->active || needs_modeset(crtc_state))
13083 crtc_state->mode_changed = true;
13085 ret = drm_atomic_add_affected_connectors(state, crtc);
13089 ret = drm_atomic_add_affected_planes(state, crtc);
13098 static int intel_modeset_checks(struct drm_atomic_state *state)
13100 struct drm_device *dev = state->dev;
13101 struct drm_i915_private *dev_priv = dev->dev_private;
13104 if (!check_digital_port_conflicts(state)) {
13105 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13110 * See if the config requires any additional preparation, e.g.
13111 * to adjust global state with pipes off. We need to do this
13112 * here so we can get the modeset_pipe updated config for the new
13113 * mode set on this crtc. For other crtcs we need to use the
13114 * adjusted_mode bits in the crtc directly.
13116 if (dev_priv->display.modeset_calc_cdclk) {
13117 unsigned int cdclk;
13119 ret = dev_priv->display.modeset_calc_cdclk(state);
13121 cdclk = to_intel_atomic_state(state)->cdclk;
13122 if (!ret && cdclk != dev_priv->cdclk_freq)
13123 ret = intel_modeset_all_pipes(state);
13128 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13130 intel_modeset_clear_plls(state);
13132 if (IS_HASWELL(dev))
13133 return haswell_mode_set_planes_workaround(state);
13139 * intel_atomic_check - validate state object
13141 * @state: state to validate
13143 static int intel_atomic_check(struct drm_device *dev,
13144 struct drm_atomic_state *state)
13146 struct drm_crtc *crtc;
13147 struct drm_crtc_state *crtc_state;
13149 bool any_ms = false;
13151 ret = drm_atomic_helper_check_modeset(dev, state);
13155 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13156 struct intel_crtc_state *pipe_config =
13157 to_intel_crtc_state(crtc_state);
13159 /* Catch I915_MODE_FLAG_INHERITED */
13160 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13161 crtc_state->mode_changed = true;
13163 if (!crtc_state->enable) {
13164 if (needs_modeset(crtc_state))
13169 if (!needs_modeset(crtc_state))
13172 /* FIXME: For only active_changed we shouldn't need to do any
13173 * state recomputation at all. */
13175 ret = drm_atomic_add_affected_connectors(state, crtc);
13179 ret = intel_modeset_pipe_config(crtc, pipe_config);
13183 if (i915.fastboot &&
13184 intel_pipe_config_compare(state->dev,
13185 to_intel_crtc_state(crtc->state),
13186 pipe_config, true)) {
13187 crtc_state->mode_changed = false;
13190 if (needs_modeset(crtc_state)) {
13193 ret = drm_atomic_add_affected_planes(state, crtc);
13198 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13199 needs_modeset(crtc_state) ?
13200 "[modeset]" : "[fastset]");
13204 ret = intel_modeset_checks(state);
13209 to_intel_atomic_state(state)->cdclk =
13210 to_i915(state->dev)->cdclk_freq;
13212 return drm_atomic_helper_check_planes(state->dev, state);
13216 * intel_atomic_commit - commit validated state object
13218 * @state: the top-level driver state object
13219 * @async: asynchronous commit
13221 * This function commits a top-level state object that has been validated
13222 * with drm_atomic_helper_check().
13224 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13225 * we can only handle plane-related operations and do not yet support
13226 * asynchronous commit.
13229 * Zero for success or -errno.
13231 static int intel_atomic_commit(struct drm_device *dev,
13232 struct drm_atomic_state *state,
13235 struct drm_i915_private *dev_priv = dev->dev_private;
13236 struct drm_crtc *crtc;
13237 struct drm_crtc_state *crtc_state;
13240 bool any_ms = false;
13243 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13247 ret = drm_atomic_helper_prepare_planes(dev, state);
13251 drm_atomic_helper_swap_state(dev, state);
13253 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13256 if (!needs_modeset(crtc->state))
13260 intel_pre_plane_update(intel_crtc);
13262 if (crtc_state->active) {
13263 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13264 dev_priv->display.crtc_disable(crtc);
13265 intel_crtc->active = false;
13266 intel_disable_shared_dpll(intel_crtc);
13270 /* Only after disabling all output pipelines that will be changed can we
13271 * update the the output configuration. */
13272 intel_modeset_update_state(state);
13274 /* The state has been swaped above, so state actually contains the
13275 * old state now. */
13277 modeset_update_crtc_power_domains(state);
13279 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13280 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13282 bool modeset = needs_modeset(crtc->state);
13284 if (modeset && crtc->state->active) {
13285 update_scanline_offset(to_intel_crtc(crtc));
13286 dev_priv->display.crtc_enable(crtc);
13290 intel_pre_plane_update(intel_crtc);
13292 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13293 intel_post_plane_update(intel_crtc);
13296 /* FIXME: add subpixel order */
13298 drm_atomic_helper_wait_for_vblanks(dev, state);
13299 drm_atomic_helper_cleanup_planes(dev, state);
13300 drm_atomic_state_free(state);
13303 intel_modeset_check_state(dev);
13308 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13310 struct drm_device *dev = crtc->dev;
13311 struct drm_atomic_state *state;
13312 struct drm_crtc_state *crtc_state;
13315 state = drm_atomic_state_alloc(dev);
13317 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13322 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13325 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13326 ret = PTR_ERR_OR_ZERO(crtc_state);
13328 if (!crtc_state->active)
13331 crtc_state->mode_changed = true;
13332 ret = drm_atomic_commit(state);
13335 if (ret == -EDEADLK) {
13336 drm_atomic_state_clear(state);
13337 drm_modeset_backoff(state->acquire_ctx);
13343 drm_atomic_state_free(state);
13346 #undef for_each_intel_crtc_masked
13348 static const struct drm_crtc_funcs intel_crtc_funcs = {
13349 .gamma_set = intel_crtc_gamma_set,
13350 .set_config = drm_atomic_helper_set_config,
13351 .destroy = intel_crtc_destroy,
13352 .page_flip = intel_crtc_page_flip,
13353 .atomic_duplicate_state = intel_crtc_duplicate_state,
13354 .atomic_destroy_state = intel_crtc_destroy_state,
13357 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13358 struct intel_shared_dpll *pll,
13359 struct intel_dpll_hw_state *hw_state)
13363 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13366 val = I915_READ(PCH_DPLL(pll->id));
13367 hw_state->dpll = val;
13368 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13369 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13371 return val & DPLL_VCO_ENABLE;
13374 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13375 struct intel_shared_dpll *pll)
13377 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13378 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13381 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13382 struct intel_shared_dpll *pll)
13384 /* PCH refclock must be enabled first */
13385 ibx_assert_pch_refclk_enabled(dev_priv);
13387 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13389 /* Wait for the clocks to stabilize. */
13390 POSTING_READ(PCH_DPLL(pll->id));
13393 /* The pixel multiplier can only be updated once the
13394 * DPLL is enabled and the clocks are stable.
13396 * So write it again.
13398 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13399 POSTING_READ(PCH_DPLL(pll->id));
13403 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13404 struct intel_shared_dpll *pll)
13406 struct drm_device *dev = dev_priv->dev;
13407 struct intel_crtc *crtc;
13409 /* Make sure no transcoder isn't still depending on us. */
13410 for_each_intel_crtc(dev, crtc) {
13411 if (intel_crtc_to_shared_dpll(crtc) == pll)
13412 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13415 I915_WRITE(PCH_DPLL(pll->id), 0);
13416 POSTING_READ(PCH_DPLL(pll->id));
13420 static char *ibx_pch_dpll_names[] = {
13425 static void ibx_pch_dpll_init(struct drm_device *dev)
13427 struct drm_i915_private *dev_priv = dev->dev_private;
13430 dev_priv->num_shared_dpll = 2;
13432 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13433 dev_priv->shared_dplls[i].id = i;
13434 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13435 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13436 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13437 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13438 dev_priv->shared_dplls[i].get_hw_state =
13439 ibx_pch_dpll_get_hw_state;
13443 static void intel_shared_dpll_init(struct drm_device *dev)
13445 struct drm_i915_private *dev_priv = dev->dev_private;
13447 intel_update_cdclk(dev);
13450 intel_ddi_pll_init(dev);
13451 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13452 ibx_pch_dpll_init(dev);
13454 dev_priv->num_shared_dpll = 0;
13456 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13460 * intel_prepare_plane_fb - Prepare fb for usage on plane
13461 * @plane: drm plane to prepare for
13462 * @fb: framebuffer to prepare for presentation
13464 * Prepares a framebuffer for usage on a display plane. Generally this
13465 * involves pinning the underlying object and updating the frontbuffer tracking
13466 * bits. Some older platforms need special physical address handling for
13469 * Returns 0 on success, negative error code on failure.
13472 intel_prepare_plane_fb(struct drm_plane *plane,
13473 struct drm_framebuffer *fb,
13474 const struct drm_plane_state *new_state)
13476 struct drm_device *dev = plane->dev;
13477 struct intel_plane *intel_plane = to_intel_plane(plane);
13478 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13479 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13485 mutex_lock(&dev->struct_mutex);
13487 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13488 INTEL_INFO(dev)->cursor_needs_physical) {
13489 int align = IS_I830(dev) ? 16 * 1024 : 256;
13490 ret = i915_gem_object_attach_phys(obj, align);
13492 DRM_DEBUG_KMS("failed to attach phys object\n");
13494 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13498 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13500 mutex_unlock(&dev->struct_mutex);
13506 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13507 * @plane: drm plane to clean up for
13508 * @fb: old framebuffer that was on plane
13510 * Cleans up a framebuffer that has just been removed from a plane.
13513 intel_cleanup_plane_fb(struct drm_plane *plane,
13514 struct drm_framebuffer *fb,
13515 const struct drm_plane_state *old_state)
13517 struct drm_device *dev = plane->dev;
13518 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13523 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13524 !INTEL_INFO(dev)->cursor_needs_physical) {
13525 mutex_lock(&dev->struct_mutex);
13526 intel_unpin_fb_obj(fb, old_state);
13527 mutex_unlock(&dev->struct_mutex);
13532 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13535 struct drm_device *dev;
13536 struct drm_i915_private *dev_priv;
13537 int crtc_clock, cdclk;
13539 if (!intel_crtc || !crtc_state)
13540 return DRM_PLANE_HELPER_NO_SCALING;
13542 dev = intel_crtc->base.dev;
13543 dev_priv = dev->dev_private;
13544 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13545 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13547 if (!crtc_clock || !cdclk)
13548 return DRM_PLANE_HELPER_NO_SCALING;
13551 * skl max scale is lower of:
13552 * close to 3 but not 3, -1 is for that purpose
13556 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13562 intel_check_primary_plane(struct drm_plane *plane,
13563 struct intel_crtc_state *crtc_state,
13564 struct intel_plane_state *state)
13566 struct drm_crtc *crtc = state->base.crtc;
13567 struct drm_framebuffer *fb = state->base.fb;
13568 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13569 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13570 bool can_position = false;
13572 /* use scaler when colorkey is not required */
13573 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13574 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13576 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13577 can_position = true;
13580 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13581 &state->dst, &state->clip,
13582 min_scale, max_scale,
13583 can_position, true,
13588 intel_commit_primary_plane(struct drm_plane *plane,
13589 struct intel_plane_state *state)
13591 struct drm_crtc *crtc = state->base.crtc;
13592 struct drm_framebuffer *fb = state->base.fb;
13593 struct drm_device *dev = plane->dev;
13594 struct drm_i915_private *dev_priv = dev->dev_private;
13595 struct intel_crtc *intel_crtc;
13596 struct drm_rect *src = &state->src;
13598 crtc = crtc ? crtc : plane->crtc;
13599 intel_crtc = to_intel_crtc(crtc);
13602 crtc->x = src->x1 >> 16;
13603 crtc->y = src->y1 >> 16;
13605 if (!crtc->state->active)
13608 if (state->visible)
13609 /* FIXME: kill this fastboot hack */
13610 intel_update_pipe_size(intel_crtc);
13612 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13616 intel_disable_primary_plane(struct drm_plane *plane,
13617 struct drm_crtc *crtc)
13619 struct drm_device *dev = plane->dev;
13620 struct drm_i915_private *dev_priv = dev->dev_private;
13622 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13625 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13626 struct drm_crtc_state *old_crtc_state)
13628 struct drm_device *dev = crtc->dev;
13629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13631 if (intel_crtc->atomic.update_wm_pre)
13632 intel_update_watermarks(crtc);
13634 /* Perform vblank evasion around commit operation */
13635 if (crtc->state->active)
13636 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13638 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13639 skl_detach_scalers(intel_crtc);
13642 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13643 struct drm_crtc_state *old_crtc_state)
13645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13647 if (crtc->state->active)
13648 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13652 * intel_plane_destroy - destroy a plane
13653 * @plane: plane to destroy
13655 * Common destruction function for all types of planes (primary, cursor,
13658 void intel_plane_destroy(struct drm_plane *plane)
13660 struct intel_plane *intel_plane = to_intel_plane(plane);
13661 drm_plane_cleanup(plane);
13662 kfree(intel_plane);
13665 const struct drm_plane_funcs intel_plane_funcs = {
13666 .update_plane = drm_atomic_helper_update_plane,
13667 .disable_plane = drm_atomic_helper_disable_plane,
13668 .destroy = intel_plane_destroy,
13669 .set_property = drm_atomic_helper_plane_set_property,
13670 .atomic_get_property = intel_plane_atomic_get_property,
13671 .atomic_set_property = intel_plane_atomic_set_property,
13672 .atomic_duplicate_state = intel_plane_duplicate_state,
13673 .atomic_destroy_state = intel_plane_destroy_state,
13677 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13680 struct intel_plane *primary;
13681 struct intel_plane_state *state;
13682 const uint32_t *intel_primary_formats;
13685 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13686 if (primary == NULL)
13689 state = intel_create_plane_state(&primary->base);
13694 primary->base.state = &state->base;
13696 primary->can_scale = false;
13697 primary->max_downscale = 1;
13698 if (INTEL_INFO(dev)->gen >= 9) {
13699 primary->can_scale = true;
13700 state->scaler_id = -1;
13702 primary->pipe = pipe;
13703 primary->plane = pipe;
13704 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13705 primary->check_plane = intel_check_primary_plane;
13706 primary->commit_plane = intel_commit_primary_plane;
13707 primary->disable_plane = intel_disable_primary_plane;
13708 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13709 primary->plane = !pipe;
13711 if (INTEL_INFO(dev)->gen >= 9) {
13712 intel_primary_formats = skl_primary_formats;
13713 num_formats = ARRAY_SIZE(skl_primary_formats);
13714 } else if (INTEL_INFO(dev)->gen >= 4) {
13715 intel_primary_formats = i965_primary_formats;
13716 num_formats = ARRAY_SIZE(i965_primary_formats);
13718 intel_primary_formats = i8xx_primary_formats;
13719 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13722 drm_universal_plane_init(dev, &primary->base, 0,
13723 &intel_plane_funcs,
13724 intel_primary_formats, num_formats,
13725 DRM_PLANE_TYPE_PRIMARY);
13727 if (INTEL_INFO(dev)->gen >= 4)
13728 intel_create_rotation_property(dev, primary);
13730 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13732 return &primary->base;
13735 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13737 if (!dev->mode_config.rotation_property) {
13738 unsigned long flags = BIT(DRM_ROTATE_0) |
13739 BIT(DRM_ROTATE_180);
13741 if (INTEL_INFO(dev)->gen >= 9)
13742 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13744 dev->mode_config.rotation_property =
13745 drm_mode_create_rotation_property(dev, flags);
13747 if (dev->mode_config.rotation_property)
13748 drm_object_attach_property(&plane->base.base,
13749 dev->mode_config.rotation_property,
13750 plane->base.state->rotation);
13754 intel_check_cursor_plane(struct drm_plane *plane,
13755 struct intel_crtc_state *crtc_state,
13756 struct intel_plane_state *state)
13758 struct drm_crtc *crtc = crtc_state->base.crtc;
13759 struct drm_framebuffer *fb = state->base.fb;
13760 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13764 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13765 &state->dst, &state->clip,
13766 DRM_PLANE_HELPER_NO_SCALING,
13767 DRM_PLANE_HELPER_NO_SCALING,
13768 true, true, &state->visible);
13772 /* if we want to turn off the cursor ignore width and height */
13776 /* Check for which cursor types we support */
13777 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13778 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13779 state->base.crtc_w, state->base.crtc_h);
13783 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13784 if (obj->base.size < stride * state->base.crtc_h) {
13785 DRM_DEBUG_KMS("buffer is too small\n");
13789 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13790 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13798 intel_disable_cursor_plane(struct drm_plane *plane,
13799 struct drm_crtc *crtc)
13801 intel_crtc_update_cursor(crtc, false);
13805 intel_commit_cursor_plane(struct drm_plane *plane,
13806 struct intel_plane_state *state)
13808 struct drm_crtc *crtc = state->base.crtc;
13809 struct drm_device *dev = plane->dev;
13810 struct intel_crtc *intel_crtc;
13811 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13814 crtc = crtc ? crtc : plane->crtc;
13815 intel_crtc = to_intel_crtc(crtc);
13817 plane->fb = state->base.fb;
13818 crtc->cursor_x = state->base.crtc_x;
13819 crtc->cursor_y = state->base.crtc_y;
13821 if (intel_crtc->cursor_bo == obj)
13826 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13827 addr = i915_gem_obj_ggtt_offset(obj);
13829 addr = obj->phys_handle->busaddr;
13831 intel_crtc->cursor_addr = addr;
13832 intel_crtc->cursor_bo = obj;
13835 if (crtc->state->active)
13836 intel_crtc_update_cursor(crtc, state->visible);
13839 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13842 struct intel_plane *cursor;
13843 struct intel_plane_state *state;
13845 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13846 if (cursor == NULL)
13849 state = intel_create_plane_state(&cursor->base);
13854 cursor->base.state = &state->base;
13856 cursor->can_scale = false;
13857 cursor->max_downscale = 1;
13858 cursor->pipe = pipe;
13859 cursor->plane = pipe;
13860 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13861 cursor->check_plane = intel_check_cursor_plane;
13862 cursor->commit_plane = intel_commit_cursor_plane;
13863 cursor->disable_plane = intel_disable_cursor_plane;
13865 drm_universal_plane_init(dev, &cursor->base, 0,
13866 &intel_plane_funcs,
13867 intel_cursor_formats,
13868 ARRAY_SIZE(intel_cursor_formats),
13869 DRM_PLANE_TYPE_CURSOR);
13871 if (INTEL_INFO(dev)->gen >= 4) {
13872 if (!dev->mode_config.rotation_property)
13873 dev->mode_config.rotation_property =
13874 drm_mode_create_rotation_property(dev,
13875 BIT(DRM_ROTATE_0) |
13876 BIT(DRM_ROTATE_180));
13877 if (dev->mode_config.rotation_property)
13878 drm_object_attach_property(&cursor->base.base,
13879 dev->mode_config.rotation_property,
13880 state->base.rotation);
13883 if (INTEL_INFO(dev)->gen >=9)
13884 state->scaler_id = -1;
13886 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13888 return &cursor->base;
13891 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13892 struct intel_crtc_state *crtc_state)
13895 struct intel_scaler *intel_scaler;
13896 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13898 for (i = 0; i < intel_crtc->num_scalers; i++) {
13899 intel_scaler = &scaler_state->scalers[i];
13900 intel_scaler->in_use = 0;
13901 intel_scaler->mode = PS_SCALER_MODE_DYN;
13904 scaler_state->scaler_id = -1;
13907 static void intel_crtc_init(struct drm_device *dev, int pipe)
13909 struct drm_i915_private *dev_priv = dev->dev_private;
13910 struct intel_crtc *intel_crtc;
13911 struct intel_crtc_state *crtc_state = NULL;
13912 struct drm_plane *primary = NULL;
13913 struct drm_plane *cursor = NULL;
13916 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13917 if (intel_crtc == NULL)
13920 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13923 intel_crtc->config = crtc_state;
13924 intel_crtc->base.state = &crtc_state->base;
13925 crtc_state->base.crtc = &intel_crtc->base;
13927 /* initialize shared scalers */
13928 if (INTEL_INFO(dev)->gen >= 9) {
13929 if (pipe == PIPE_C)
13930 intel_crtc->num_scalers = 1;
13932 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13934 skl_init_scalers(dev, intel_crtc, crtc_state);
13937 primary = intel_primary_plane_create(dev, pipe);
13941 cursor = intel_cursor_plane_create(dev, pipe);
13945 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13946 cursor, &intel_crtc_funcs);
13950 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13951 for (i = 0; i < 256; i++) {
13952 intel_crtc->lut_r[i] = i;
13953 intel_crtc->lut_g[i] = i;
13954 intel_crtc->lut_b[i] = i;
13958 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13959 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13961 intel_crtc->pipe = pipe;
13962 intel_crtc->plane = pipe;
13963 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13964 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13965 intel_crtc->plane = !pipe;
13968 intel_crtc->cursor_base = ~0;
13969 intel_crtc->cursor_cntl = ~0;
13970 intel_crtc->cursor_size = ~0;
13972 intel_crtc->wm.cxsr_allowed = true;
13974 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13975 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13976 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13977 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13979 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13981 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13986 drm_plane_cleanup(primary);
13988 drm_plane_cleanup(cursor);
13993 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13995 struct drm_encoder *encoder = connector->base.encoder;
13996 struct drm_device *dev = connector->base.dev;
13998 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14000 if (!encoder || WARN_ON(!encoder->crtc))
14001 return INVALID_PIPE;
14003 return to_intel_crtc(encoder->crtc)->pipe;
14006 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14007 struct drm_file *file)
14009 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14010 struct drm_crtc *drmmode_crtc;
14011 struct intel_crtc *crtc;
14013 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14015 if (!drmmode_crtc) {
14016 DRM_ERROR("no such CRTC id\n");
14020 crtc = to_intel_crtc(drmmode_crtc);
14021 pipe_from_crtc_id->pipe = crtc->pipe;
14026 static int intel_encoder_clones(struct intel_encoder *encoder)
14028 struct drm_device *dev = encoder->base.dev;
14029 struct intel_encoder *source_encoder;
14030 int index_mask = 0;
14033 for_each_intel_encoder(dev, source_encoder) {
14034 if (encoders_cloneable(encoder, source_encoder))
14035 index_mask |= (1 << entry);
14043 static bool has_edp_a(struct drm_device *dev)
14045 struct drm_i915_private *dev_priv = dev->dev_private;
14047 if (!IS_MOBILE(dev))
14050 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14053 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14059 static bool intel_crt_present(struct drm_device *dev)
14061 struct drm_i915_private *dev_priv = dev->dev_private;
14063 if (INTEL_INFO(dev)->gen >= 9)
14066 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14069 if (IS_CHERRYVIEW(dev))
14072 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14078 static void intel_setup_outputs(struct drm_device *dev)
14080 struct drm_i915_private *dev_priv = dev->dev_private;
14081 struct intel_encoder *encoder;
14082 bool dpd_is_edp = false;
14084 intel_lvds_init(dev);
14086 if (intel_crt_present(dev))
14087 intel_crt_init(dev);
14089 if (IS_BROXTON(dev)) {
14091 * FIXME: Broxton doesn't support port detection via the
14092 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14093 * detect the ports.
14095 intel_ddi_init(dev, PORT_A);
14096 intel_ddi_init(dev, PORT_B);
14097 intel_ddi_init(dev, PORT_C);
14098 } else if (HAS_DDI(dev)) {
14102 * Haswell uses DDI functions to detect digital outputs.
14103 * On SKL pre-D0 the strap isn't connected, so we assume
14106 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14107 /* WaIgnoreDDIAStrap: skl */
14109 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14110 intel_ddi_init(dev, PORT_A);
14112 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14114 found = I915_READ(SFUSE_STRAP);
14116 if (found & SFUSE_STRAP_DDIB_DETECTED)
14117 intel_ddi_init(dev, PORT_B);
14118 if (found & SFUSE_STRAP_DDIC_DETECTED)
14119 intel_ddi_init(dev, PORT_C);
14120 if (found & SFUSE_STRAP_DDID_DETECTED)
14121 intel_ddi_init(dev, PORT_D);
14122 } else if (HAS_PCH_SPLIT(dev)) {
14124 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14126 if (has_edp_a(dev))
14127 intel_dp_init(dev, DP_A, PORT_A);
14129 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14130 /* PCH SDVOB multiplex with HDMIB */
14131 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14133 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14134 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14135 intel_dp_init(dev, PCH_DP_B, PORT_B);
14138 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14139 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14141 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14142 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14144 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14145 intel_dp_init(dev, PCH_DP_C, PORT_C);
14147 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14148 intel_dp_init(dev, PCH_DP_D, PORT_D);
14149 } else if (IS_VALLEYVIEW(dev)) {
14151 * The DP_DETECTED bit is the latched state of the DDC
14152 * SDA pin at boot. However since eDP doesn't require DDC
14153 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14154 * eDP ports may have been muxed to an alternate function.
14155 * Thus we can't rely on the DP_DETECTED bit alone to detect
14156 * eDP ports. Consult the VBT as well as DP_DETECTED to
14157 * detect eDP ports.
14159 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14160 !intel_dp_is_edp(dev, PORT_B))
14161 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14163 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14164 intel_dp_is_edp(dev, PORT_B))
14165 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14167 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14168 !intel_dp_is_edp(dev, PORT_C))
14169 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14171 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14172 intel_dp_is_edp(dev, PORT_C))
14173 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14175 if (IS_CHERRYVIEW(dev)) {
14176 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14177 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14179 /* eDP not supported on port D, so don't check VBT */
14180 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14181 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14184 intel_dsi_init(dev);
14185 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14186 bool found = false;
14188 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14189 DRM_DEBUG_KMS("probing SDVOB\n");
14190 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14191 if (!found && IS_G4X(dev)) {
14192 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14193 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14196 if (!found && IS_G4X(dev))
14197 intel_dp_init(dev, DP_B, PORT_B);
14200 /* Before G4X SDVOC doesn't have its own detect register */
14202 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14203 DRM_DEBUG_KMS("probing SDVOC\n");
14204 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14207 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14210 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14211 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14214 intel_dp_init(dev, DP_C, PORT_C);
14218 (I915_READ(DP_D) & DP_DETECTED))
14219 intel_dp_init(dev, DP_D, PORT_D);
14220 } else if (IS_GEN2(dev))
14221 intel_dvo_init(dev);
14223 if (SUPPORTS_TV(dev))
14224 intel_tv_init(dev);
14226 intel_psr_init(dev);
14228 for_each_intel_encoder(dev, encoder) {
14229 encoder->base.possible_crtcs = encoder->crtc_mask;
14230 encoder->base.possible_clones =
14231 intel_encoder_clones(encoder);
14234 intel_init_pch_refclk(dev);
14236 drm_helper_move_panel_connectors_to_head(dev);
14239 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14241 struct drm_device *dev = fb->dev;
14242 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14244 drm_framebuffer_cleanup(fb);
14245 mutex_lock(&dev->struct_mutex);
14246 WARN_ON(!intel_fb->obj->framebuffer_references--);
14247 drm_gem_object_unreference(&intel_fb->obj->base);
14248 mutex_unlock(&dev->struct_mutex);
14252 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14253 struct drm_file *file,
14254 unsigned int *handle)
14256 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14257 struct drm_i915_gem_object *obj = intel_fb->obj;
14259 return drm_gem_handle_create(file, &obj->base, handle);
14262 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14263 struct drm_file *file,
14264 unsigned flags, unsigned color,
14265 struct drm_clip_rect *clips,
14266 unsigned num_clips)
14268 struct drm_device *dev = fb->dev;
14269 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14270 struct drm_i915_gem_object *obj = intel_fb->obj;
14272 mutex_lock(&dev->struct_mutex);
14273 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14274 mutex_unlock(&dev->struct_mutex);
14279 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14280 .destroy = intel_user_framebuffer_destroy,
14281 .create_handle = intel_user_framebuffer_create_handle,
14282 .dirty = intel_user_framebuffer_dirty,
14286 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14287 uint32_t pixel_format)
14289 u32 gen = INTEL_INFO(dev)->gen;
14292 /* "The stride in bytes must not exceed the of the size of 8K
14293 * pixels and 32K bytes."
14295 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14296 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14298 } else if (gen >= 4) {
14299 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14303 } else if (gen >= 3) {
14304 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14309 /* XXX DSPC is limited to 4k tiled */
14314 static int intel_framebuffer_init(struct drm_device *dev,
14315 struct intel_framebuffer *intel_fb,
14316 struct drm_mode_fb_cmd2 *mode_cmd,
14317 struct drm_i915_gem_object *obj)
14319 unsigned int aligned_height;
14321 u32 pitch_limit, stride_alignment;
14323 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14325 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14326 /* Enforce that fb modifier and tiling mode match, but only for
14327 * X-tiled. This is needed for FBC. */
14328 if (!!(obj->tiling_mode == I915_TILING_X) !=
14329 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14330 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14334 if (obj->tiling_mode == I915_TILING_X)
14335 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14336 else if (obj->tiling_mode == I915_TILING_Y) {
14337 DRM_DEBUG("No Y tiling for legacy addfb\n");
14342 /* Passed in modifier sanity checking. */
14343 switch (mode_cmd->modifier[0]) {
14344 case I915_FORMAT_MOD_Y_TILED:
14345 case I915_FORMAT_MOD_Yf_TILED:
14346 if (INTEL_INFO(dev)->gen < 9) {
14347 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14348 mode_cmd->modifier[0]);
14351 case DRM_FORMAT_MOD_NONE:
14352 case I915_FORMAT_MOD_X_TILED:
14355 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14356 mode_cmd->modifier[0]);
14360 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14361 mode_cmd->pixel_format);
14362 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14363 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14364 mode_cmd->pitches[0], stride_alignment);
14368 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14369 mode_cmd->pixel_format);
14370 if (mode_cmd->pitches[0] > pitch_limit) {
14371 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14372 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14373 "tiled" : "linear",
14374 mode_cmd->pitches[0], pitch_limit);
14378 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14379 mode_cmd->pitches[0] != obj->stride) {
14380 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14381 mode_cmd->pitches[0], obj->stride);
14385 /* Reject formats not supported by any plane early. */
14386 switch (mode_cmd->pixel_format) {
14387 case DRM_FORMAT_C8:
14388 case DRM_FORMAT_RGB565:
14389 case DRM_FORMAT_XRGB8888:
14390 case DRM_FORMAT_ARGB8888:
14392 case DRM_FORMAT_XRGB1555:
14393 if (INTEL_INFO(dev)->gen > 3) {
14394 DRM_DEBUG("unsupported pixel format: %s\n",
14395 drm_get_format_name(mode_cmd->pixel_format));
14399 case DRM_FORMAT_ABGR8888:
14400 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14401 DRM_DEBUG("unsupported pixel format: %s\n",
14402 drm_get_format_name(mode_cmd->pixel_format));
14406 case DRM_FORMAT_XBGR8888:
14407 case DRM_FORMAT_XRGB2101010:
14408 case DRM_FORMAT_XBGR2101010:
14409 if (INTEL_INFO(dev)->gen < 4) {
14410 DRM_DEBUG("unsupported pixel format: %s\n",
14411 drm_get_format_name(mode_cmd->pixel_format));
14415 case DRM_FORMAT_ABGR2101010:
14416 if (!IS_VALLEYVIEW(dev)) {
14417 DRM_DEBUG("unsupported pixel format: %s\n",
14418 drm_get_format_name(mode_cmd->pixel_format));
14422 case DRM_FORMAT_YUYV:
14423 case DRM_FORMAT_UYVY:
14424 case DRM_FORMAT_YVYU:
14425 case DRM_FORMAT_VYUY:
14426 if (INTEL_INFO(dev)->gen < 5) {
14427 DRM_DEBUG("unsupported pixel format: %s\n",
14428 drm_get_format_name(mode_cmd->pixel_format));
14433 DRM_DEBUG("unsupported pixel format: %s\n",
14434 drm_get_format_name(mode_cmd->pixel_format));
14438 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14439 if (mode_cmd->offsets[0] != 0)
14442 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14443 mode_cmd->pixel_format,
14444 mode_cmd->modifier[0]);
14445 /* FIXME drm helper for size checks (especially planar formats)? */
14446 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14449 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14450 intel_fb->obj = obj;
14451 intel_fb->obj->framebuffer_references++;
14453 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14455 DRM_ERROR("framebuffer init failed %d\n", ret);
14462 static struct drm_framebuffer *
14463 intel_user_framebuffer_create(struct drm_device *dev,
14464 struct drm_file *filp,
14465 struct drm_mode_fb_cmd2 *mode_cmd)
14467 struct drm_i915_gem_object *obj;
14469 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14470 mode_cmd->handles[0]));
14471 if (&obj->base == NULL)
14472 return ERR_PTR(-ENOENT);
14474 return intel_framebuffer_create(dev, mode_cmd, obj);
14477 #ifndef CONFIG_DRM_I915_FBDEV
14478 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14483 static const struct drm_mode_config_funcs intel_mode_funcs = {
14484 .fb_create = intel_user_framebuffer_create,
14485 .output_poll_changed = intel_fbdev_output_poll_changed,
14486 .atomic_check = intel_atomic_check,
14487 .atomic_commit = intel_atomic_commit,
14488 .atomic_state_alloc = intel_atomic_state_alloc,
14489 .atomic_state_clear = intel_atomic_state_clear,
14492 /* Set up chip specific display functions */
14493 static void intel_init_display(struct drm_device *dev)
14495 struct drm_i915_private *dev_priv = dev->dev_private;
14497 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14498 dev_priv->display.find_dpll = g4x_find_best_dpll;
14499 else if (IS_CHERRYVIEW(dev))
14500 dev_priv->display.find_dpll = chv_find_best_dpll;
14501 else if (IS_VALLEYVIEW(dev))
14502 dev_priv->display.find_dpll = vlv_find_best_dpll;
14503 else if (IS_PINEVIEW(dev))
14504 dev_priv->display.find_dpll = pnv_find_best_dpll;
14506 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14508 if (INTEL_INFO(dev)->gen >= 9) {
14509 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14510 dev_priv->display.get_initial_plane_config =
14511 skylake_get_initial_plane_config;
14512 dev_priv->display.crtc_compute_clock =
14513 haswell_crtc_compute_clock;
14514 dev_priv->display.crtc_enable = haswell_crtc_enable;
14515 dev_priv->display.crtc_disable = haswell_crtc_disable;
14516 dev_priv->display.update_primary_plane =
14517 skylake_update_primary_plane;
14518 } else if (HAS_DDI(dev)) {
14519 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14520 dev_priv->display.get_initial_plane_config =
14521 ironlake_get_initial_plane_config;
14522 dev_priv->display.crtc_compute_clock =
14523 haswell_crtc_compute_clock;
14524 dev_priv->display.crtc_enable = haswell_crtc_enable;
14525 dev_priv->display.crtc_disable = haswell_crtc_disable;
14526 dev_priv->display.update_primary_plane =
14527 ironlake_update_primary_plane;
14528 } else if (HAS_PCH_SPLIT(dev)) {
14529 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14530 dev_priv->display.get_initial_plane_config =
14531 ironlake_get_initial_plane_config;
14532 dev_priv->display.crtc_compute_clock =
14533 ironlake_crtc_compute_clock;
14534 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14535 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14536 dev_priv->display.update_primary_plane =
14537 ironlake_update_primary_plane;
14538 } else if (IS_VALLEYVIEW(dev)) {
14539 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14540 dev_priv->display.get_initial_plane_config =
14541 i9xx_get_initial_plane_config;
14542 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14543 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14544 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14545 dev_priv->display.update_primary_plane =
14546 i9xx_update_primary_plane;
14548 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14549 dev_priv->display.get_initial_plane_config =
14550 i9xx_get_initial_plane_config;
14551 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14552 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14553 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14554 dev_priv->display.update_primary_plane =
14555 i9xx_update_primary_plane;
14558 /* Returns the core display clock speed */
14559 if (IS_SKYLAKE(dev))
14560 dev_priv->display.get_display_clock_speed =
14561 skylake_get_display_clock_speed;
14562 else if (IS_BROXTON(dev))
14563 dev_priv->display.get_display_clock_speed =
14564 broxton_get_display_clock_speed;
14565 else if (IS_BROADWELL(dev))
14566 dev_priv->display.get_display_clock_speed =
14567 broadwell_get_display_clock_speed;
14568 else if (IS_HASWELL(dev))
14569 dev_priv->display.get_display_clock_speed =
14570 haswell_get_display_clock_speed;
14571 else if (IS_VALLEYVIEW(dev))
14572 dev_priv->display.get_display_clock_speed =
14573 valleyview_get_display_clock_speed;
14574 else if (IS_GEN5(dev))
14575 dev_priv->display.get_display_clock_speed =
14576 ilk_get_display_clock_speed;
14577 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14578 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14579 dev_priv->display.get_display_clock_speed =
14580 i945_get_display_clock_speed;
14581 else if (IS_GM45(dev))
14582 dev_priv->display.get_display_clock_speed =
14583 gm45_get_display_clock_speed;
14584 else if (IS_CRESTLINE(dev))
14585 dev_priv->display.get_display_clock_speed =
14586 i965gm_get_display_clock_speed;
14587 else if (IS_PINEVIEW(dev))
14588 dev_priv->display.get_display_clock_speed =
14589 pnv_get_display_clock_speed;
14590 else if (IS_G33(dev) || IS_G4X(dev))
14591 dev_priv->display.get_display_clock_speed =
14592 g33_get_display_clock_speed;
14593 else if (IS_I915G(dev))
14594 dev_priv->display.get_display_clock_speed =
14595 i915_get_display_clock_speed;
14596 else if (IS_I945GM(dev) || IS_845G(dev))
14597 dev_priv->display.get_display_clock_speed =
14598 i9xx_misc_get_display_clock_speed;
14599 else if (IS_PINEVIEW(dev))
14600 dev_priv->display.get_display_clock_speed =
14601 pnv_get_display_clock_speed;
14602 else if (IS_I915GM(dev))
14603 dev_priv->display.get_display_clock_speed =
14604 i915gm_get_display_clock_speed;
14605 else if (IS_I865G(dev))
14606 dev_priv->display.get_display_clock_speed =
14607 i865_get_display_clock_speed;
14608 else if (IS_I85X(dev))
14609 dev_priv->display.get_display_clock_speed =
14610 i85x_get_display_clock_speed;
14612 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14613 dev_priv->display.get_display_clock_speed =
14614 i830_get_display_clock_speed;
14617 if (IS_GEN5(dev)) {
14618 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14619 } else if (IS_GEN6(dev)) {
14620 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14621 } else if (IS_IVYBRIDGE(dev)) {
14622 /* FIXME: detect B0+ stepping and use auto training */
14623 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14624 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14625 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14626 if (IS_BROADWELL(dev)) {
14627 dev_priv->display.modeset_commit_cdclk =
14628 broadwell_modeset_commit_cdclk;
14629 dev_priv->display.modeset_calc_cdclk =
14630 broadwell_modeset_calc_cdclk;
14632 } else if (IS_VALLEYVIEW(dev)) {
14633 dev_priv->display.modeset_commit_cdclk =
14634 valleyview_modeset_commit_cdclk;
14635 dev_priv->display.modeset_calc_cdclk =
14636 valleyview_modeset_calc_cdclk;
14637 } else if (IS_BROXTON(dev)) {
14638 dev_priv->display.modeset_commit_cdclk =
14639 broxton_modeset_commit_cdclk;
14640 dev_priv->display.modeset_calc_cdclk =
14641 broxton_modeset_calc_cdclk;
14644 switch (INTEL_INFO(dev)->gen) {
14646 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14650 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14655 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14659 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14662 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14663 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14666 /* Drop through - unsupported since execlist only. */
14668 /* Default just returns -ENODEV to indicate unsupported */
14669 dev_priv->display.queue_flip = intel_default_queue_flip;
14672 intel_panel_init_backlight_funcs(dev);
14674 mutex_init(&dev_priv->pps_mutex);
14678 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14679 * resume, or other times. This quirk makes sure that's the case for
14680 * affected systems.
14682 static void quirk_pipea_force(struct drm_device *dev)
14684 struct drm_i915_private *dev_priv = dev->dev_private;
14686 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14687 DRM_INFO("applying pipe a force quirk\n");
14690 static void quirk_pipeb_force(struct drm_device *dev)
14692 struct drm_i915_private *dev_priv = dev->dev_private;
14694 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14695 DRM_INFO("applying pipe b force quirk\n");
14699 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14701 static void quirk_ssc_force_disable(struct drm_device *dev)
14703 struct drm_i915_private *dev_priv = dev->dev_private;
14704 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14705 DRM_INFO("applying lvds SSC disable quirk\n");
14709 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14712 static void quirk_invert_brightness(struct drm_device *dev)
14714 struct drm_i915_private *dev_priv = dev->dev_private;
14715 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14716 DRM_INFO("applying inverted panel brightness quirk\n");
14719 /* Some VBT's incorrectly indicate no backlight is present */
14720 static void quirk_backlight_present(struct drm_device *dev)
14722 struct drm_i915_private *dev_priv = dev->dev_private;
14723 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14724 DRM_INFO("applying backlight present quirk\n");
14727 struct intel_quirk {
14729 int subsystem_vendor;
14730 int subsystem_device;
14731 void (*hook)(struct drm_device *dev);
14734 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14735 struct intel_dmi_quirk {
14736 void (*hook)(struct drm_device *dev);
14737 const struct dmi_system_id (*dmi_id_list)[];
14740 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14742 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14746 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14748 .dmi_id_list = &(const struct dmi_system_id[]) {
14750 .callback = intel_dmi_reverse_brightness,
14751 .ident = "NCR Corporation",
14752 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14753 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14756 { } /* terminating entry */
14758 .hook = quirk_invert_brightness,
14762 static struct intel_quirk intel_quirks[] = {
14763 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14764 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14766 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14767 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14769 /* 830 needs to leave pipe A & dpll A up */
14770 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14772 /* 830 needs to leave pipe B & dpll B up */
14773 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14775 /* Lenovo U160 cannot use SSC on LVDS */
14776 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14778 /* Sony Vaio Y cannot use SSC on LVDS */
14779 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14781 /* Acer Aspire 5734Z must invert backlight brightness */
14782 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14784 /* Acer/eMachines G725 */
14785 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14787 /* Acer/eMachines e725 */
14788 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14790 /* Acer/Packard Bell NCL20 */
14791 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14793 /* Acer Aspire 4736Z */
14794 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14796 /* Acer Aspire 5336 */
14797 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14799 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14800 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14802 /* Acer C720 Chromebook (Core i3 4005U) */
14803 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14805 /* Apple Macbook 2,1 (Core 2 T7400) */
14806 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14808 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14809 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14811 /* HP Chromebook 14 (Celeron 2955U) */
14812 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14814 /* Dell Chromebook 11 */
14815 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14818 static void intel_init_quirks(struct drm_device *dev)
14820 struct pci_dev *d = dev->pdev;
14823 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14824 struct intel_quirk *q = &intel_quirks[i];
14826 if (d->device == q->device &&
14827 (d->subsystem_vendor == q->subsystem_vendor ||
14828 q->subsystem_vendor == PCI_ANY_ID) &&
14829 (d->subsystem_device == q->subsystem_device ||
14830 q->subsystem_device == PCI_ANY_ID))
14833 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14834 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14835 intel_dmi_quirks[i].hook(dev);
14839 /* Disable the VGA plane that we never use */
14840 static void i915_disable_vga(struct drm_device *dev)
14842 struct drm_i915_private *dev_priv = dev->dev_private;
14844 u32 vga_reg = i915_vgacntrl_reg(dev);
14846 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14847 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14848 outb(SR01, VGA_SR_INDEX);
14849 sr1 = inb(VGA_SR_DATA);
14850 outb(sr1 | 1<<5, VGA_SR_DATA);
14851 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14854 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14855 POSTING_READ(vga_reg);
14858 void intel_modeset_init_hw(struct drm_device *dev)
14860 intel_update_cdclk(dev);
14861 intel_prepare_ddi(dev);
14862 intel_init_clock_gating(dev);
14863 intel_enable_gt_powersave(dev);
14866 void intel_modeset_init(struct drm_device *dev)
14868 struct drm_i915_private *dev_priv = dev->dev_private;
14871 struct intel_crtc *crtc;
14873 drm_mode_config_init(dev);
14875 dev->mode_config.min_width = 0;
14876 dev->mode_config.min_height = 0;
14878 dev->mode_config.preferred_depth = 24;
14879 dev->mode_config.prefer_shadow = 1;
14881 dev->mode_config.allow_fb_modifiers = true;
14883 dev->mode_config.funcs = &intel_mode_funcs;
14885 intel_init_quirks(dev);
14887 intel_init_pm(dev);
14889 if (INTEL_INFO(dev)->num_pipes == 0)
14892 intel_init_display(dev);
14893 intel_init_audio(dev);
14895 if (IS_GEN2(dev)) {
14896 dev->mode_config.max_width = 2048;
14897 dev->mode_config.max_height = 2048;
14898 } else if (IS_GEN3(dev)) {
14899 dev->mode_config.max_width = 4096;
14900 dev->mode_config.max_height = 4096;
14902 dev->mode_config.max_width = 8192;
14903 dev->mode_config.max_height = 8192;
14906 if (IS_845G(dev) || IS_I865G(dev)) {
14907 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14908 dev->mode_config.cursor_height = 1023;
14909 } else if (IS_GEN2(dev)) {
14910 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14911 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14913 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14914 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14917 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14919 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14920 INTEL_INFO(dev)->num_pipes,
14921 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14923 for_each_pipe(dev_priv, pipe) {
14924 intel_crtc_init(dev, pipe);
14925 for_each_sprite(dev_priv, pipe, sprite) {
14926 ret = intel_plane_init(dev, pipe, sprite);
14928 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14929 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14933 intel_init_dpio(dev);
14935 intel_shared_dpll_init(dev);
14937 /* Just disable it once at startup */
14938 i915_disable_vga(dev);
14939 intel_setup_outputs(dev);
14941 /* Just in case the BIOS is doing something questionable. */
14942 intel_fbc_disable(dev_priv);
14944 drm_modeset_lock_all(dev);
14945 intel_modeset_setup_hw_state(dev);
14946 drm_modeset_unlock_all(dev);
14948 for_each_intel_crtc(dev, crtc) {
14949 struct intel_initial_plane_config plane_config = {};
14955 * Note that reserving the BIOS fb up front prevents us
14956 * from stuffing other stolen allocations like the ring
14957 * on top. This prevents some ugliness at boot time, and
14958 * can even allow for smooth boot transitions if the BIOS
14959 * fb is large enough for the active pipe configuration.
14961 dev_priv->display.get_initial_plane_config(crtc,
14965 * If the fb is shared between multiple heads, we'll
14966 * just get the first one.
14968 intel_find_initial_plane_obj(crtc, &plane_config);
14972 static void intel_enable_pipe_a(struct drm_device *dev)
14974 struct intel_connector *connector;
14975 struct drm_connector *crt = NULL;
14976 struct intel_load_detect_pipe load_detect_temp;
14977 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14979 /* We can't just switch on the pipe A, we need to set things up with a
14980 * proper mode and output configuration. As a gross hack, enable pipe A
14981 * by enabling the load detect pipe once. */
14982 for_each_intel_connector(dev, connector) {
14983 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14984 crt = &connector->base;
14992 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14993 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14997 intel_check_plane_mapping(struct intel_crtc *crtc)
14999 struct drm_device *dev = crtc->base.dev;
15000 struct drm_i915_private *dev_priv = dev->dev_private;
15003 if (INTEL_INFO(dev)->num_pipes == 1)
15006 reg = DSPCNTR(!crtc->plane);
15007 val = I915_READ(reg);
15009 if ((val & DISPLAY_PLANE_ENABLE) &&
15010 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15016 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15018 struct drm_device *dev = crtc->base.dev;
15019 struct drm_i915_private *dev_priv = dev->dev_private;
15020 struct intel_encoder *encoder;
15024 /* Clear any frame start delays used for debugging left by the BIOS */
15025 reg = PIPECONF(crtc->config->cpu_transcoder);
15026 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15028 /* restore vblank interrupts to correct state */
15029 drm_crtc_vblank_reset(&crtc->base);
15030 if (crtc->active) {
15031 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15032 update_scanline_offset(crtc);
15033 drm_crtc_vblank_on(&crtc->base);
15036 /* We need to sanitize the plane -> pipe mapping first because this will
15037 * disable the crtc (and hence change the state) if it is wrong. Note
15038 * that gen4+ has a fixed plane -> pipe mapping. */
15039 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15042 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15043 crtc->base.base.id);
15045 /* Pipe has the wrong plane attached and the plane is active.
15046 * Temporarily change the plane mapping and disable everything
15048 plane = crtc->plane;
15049 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15050 crtc->plane = !plane;
15051 intel_crtc_disable_noatomic(&crtc->base);
15052 crtc->plane = plane;
15055 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15056 crtc->pipe == PIPE_A && !crtc->active) {
15057 /* BIOS forgot to enable pipe A, this mostly happens after
15058 * resume. Force-enable the pipe to fix this, the update_dpms
15059 * call below we restore the pipe to the right state, but leave
15060 * the required bits on. */
15061 intel_enable_pipe_a(dev);
15064 /* Adjust the state of the output pipe according to whether we
15065 * have active connectors/encoders. */
15067 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15068 enable |= encoder->connectors_active;
15071 intel_crtc_disable_noatomic(&crtc->base);
15073 if (crtc->active != crtc->base.state->active) {
15075 /* This can happen either due to bugs in the get_hw_state
15076 * functions or because of calls to intel_crtc_disable_noatomic,
15077 * or because the pipe is force-enabled due to the
15079 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15080 crtc->base.base.id,
15081 crtc->base.state->enable ? "enabled" : "disabled",
15082 crtc->active ? "enabled" : "disabled");
15084 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15085 crtc->base.state->active = crtc->active;
15086 crtc->base.enabled = crtc->active;
15088 /* Because we only establish the connector -> encoder ->
15089 * crtc links if something is active, this means the
15090 * crtc is now deactivated. Break the links. connector
15091 * -> encoder links are only establish when things are
15092 * actually up, hence no need to break them. */
15093 WARN_ON(crtc->active);
15095 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15096 WARN_ON(encoder->connectors_active);
15097 encoder->base.crtc = NULL;
15101 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15103 * We start out with underrun reporting disabled to avoid races.
15104 * For correct bookkeeping mark this on active crtcs.
15106 * Also on gmch platforms we dont have any hardware bits to
15107 * disable the underrun reporting. Which means we need to start
15108 * out with underrun reporting disabled also on inactive pipes,
15109 * since otherwise we'll complain about the garbage we read when
15110 * e.g. coming up after runtime pm.
15112 * No protection against concurrent access is required - at
15113 * worst a fifo underrun happens which also sets this to false.
15115 crtc->cpu_fifo_underrun_disabled = true;
15116 crtc->pch_fifo_underrun_disabled = true;
15120 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15122 struct intel_connector *connector;
15123 struct drm_device *dev = encoder->base.dev;
15125 /* We need to check both for a crtc link (meaning that the
15126 * encoder is active and trying to read from a pipe) and the
15127 * pipe itself being active. */
15128 bool has_active_crtc = encoder->base.crtc &&
15129 to_intel_crtc(encoder->base.crtc)->active;
15131 if (encoder->connectors_active && !has_active_crtc) {
15132 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15133 encoder->base.base.id,
15134 encoder->base.name);
15136 /* Connector is active, but has no active pipe. This is
15137 * fallout from our resume register restoring. Disable
15138 * the encoder manually again. */
15139 if (encoder->base.crtc) {
15140 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15141 encoder->base.base.id,
15142 encoder->base.name);
15143 encoder->disable(encoder);
15144 if (encoder->post_disable)
15145 encoder->post_disable(encoder);
15147 encoder->base.crtc = NULL;
15148 encoder->connectors_active = false;
15150 /* Inconsistent output/port/pipe state happens presumably due to
15151 * a bug in one of the get_hw_state functions. Or someplace else
15152 * in our code, like the register restore mess on resume. Clamp
15153 * things to off as a safer default. */
15154 for_each_intel_connector(dev, connector) {
15155 if (connector->encoder != encoder)
15157 connector->base.dpms = DRM_MODE_DPMS_OFF;
15158 connector->base.encoder = NULL;
15161 /* Enabled encoders without active connectors will be fixed in
15162 * the crtc fixup. */
15165 void i915_redisable_vga_power_on(struct drm_device *dev)
15167 struct drm_i915_private *dev_priv = dev->dev_private;
15168 u32 vga_reg = i915_vgacntrl_reg(dev);
15170 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15171 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15172 i915_disable_vga(dev);
15176 void i915_redisable_vga(struct drm_device *dev)
15178 struct drm_i915_private *dev_priv = dev->dev_private;
15180 /* This function can be called both from intel_modeset_setup_hw_state or
15181 * at a very early point in our resume sequence, where the power well
15182 * structures are not yet restored. Since this function is at a very
15183 * paranoid "someone might have enabled VGA while we were not looking"
15184 * level, just check if the power well is enabled instead of trying to
15185 * follow the "don't touch the power well if we don't need it" policy
15186 * the rest of the driver uses. */
15187 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15190 i915_redisable_vga_power_on(dev);
15193 static bool primary_get_hw_state(struct intel_crtc *crtc)
15195 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15197 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15200 static void readout_plane_state(struct intel_crtc *crtc,
15201 struct intel_crtc_state *crtc_state)
15203 struct intel_plane *p;
15204 struct intel_plane_state *plane_state;
15205 bool active = crtc_state->base.active;
15207 for_each_intel_plane(crtc->base.dev, p) {
15208 if (crtc->pipe != p->pipe)
15211 plane_state = to_intel_plane_state(p->base.state);
15213 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15214 plane_state->visible = primary_get_hw_state(crtc);
15217 p->disable_plane(&p->base, &crtc->base);
15219 plane_state->visible = false;
15224 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15226 struct drm_i915_private *dev_priv = dev->dev_private;
15228 struct intel_crtc *crtc;
15229 struct intel_encoder *encoder;
15230 struct intel_connector *connector;
15233 for_each_intel_crtc(dev, crtc) {
15234 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15235 memset(crtc->config, 0, sizeof(*crtc->config));
15236 crtc->config->base.crtc = &crtc->base;
15238 crtc->active = dev_priv->display.get_pipe_config(crtc,
15241 crtc->base.state->active = crtc->active;
15242 crtc->base.enabled = crtc->active;
15244 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15245 if (crtc->base.state->active) {
15246 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15247 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15248 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15251 * The initial mode needs to be set in order to keep
15252 * the atomic core happy. It wants a valid mode if the
15253 * crtc's enabled, so we do the above call.
15255 * At this point some state updated by the connectors
15256 * in their ->detect() callback has not run yet, so
15257 * no recalculation can be done yet.
15259 * Even if we could do a recalculation and modeset
15260 * right now it would cause a double modeset if
15261 * fbdev or userspace chooses a different initial mode.
15263 * If that happens, someone indicated they wanted a
15264 * mode change, which means it's safe to do a full
15267 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15270 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15271 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15273 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15274 crtc->base.base.id,
15275 crtc->active ? "enabled" : "disabled");
15278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15279 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15281 pll->on = pll->get_hw_state(dev_priv, pll,
15282 &pll->config.hw_state);
15284 pll->config.crtc_mask = 0;
15285 for_each_intel_crtc(dev, crtc) {
15286 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15288 pll->config.crtc_mask |= 1 << crtc->pipe;
15292 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15293 pll->name, pll->config.crtc_mask, pll->on);
15295 if (pll->config.crtc_mask)
15296 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15299 for_each_intel_encoder(dev, encoder) {
15302 if (encoder->get_hw_state(encoder, &pipe)) {
15303 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15304 encoder->base.crtc = &crtc->base;
15305 encoder->get_config(encoder, crtc->config);
15307 encoder->base.crtc = NULL;
15310 encoder->connectors_active = false;
15311 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15312 encoder->base.base.id,
15313 encoder->base.name,
15314 encoder->base.crtc ? "enabled" : "disabled",
15318 for_each_intel_connector(dev, connector) {
15319 if (connector->get_hw_state(connector)) {
15320 connector->base.dpms = DRM_MODE_DPMS_ON;
15321 connector->encoder->connectors_active = true;
15322 connector->base.encoder = &connector->encoder->base;
15324 connector->base.dpms = DRM_MODE_DPMS_OFF;
15325 connector->base.encoder = NULL;
15327 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15328 connector->base.base.id,
15329 connector->base.name,
15330 connector->base.encoder ? "enabled" : "disabled");
15334 /* Scan out the current hw modeset state,
15335 * and sanitizes it to the current state
15338 intel_modeset_setup_hw_state(struct drm_device *dev)
15340 struct drm_i915_private *dev_priv = dev->dev_private;
15342 struct intel_crtc *crtc;
15343 struct intel_encoder *encoder;
15346 intel_modeset_readout_hw_state(dev);
15348 /* HW state is read out, now we need to sanitize this mess. */
15349 for_each_intel_encoder(dev, encoder) {
15350 intel_sanitize_encoder(encoder);
15353 for_each_pipe(dev_priv, pipe) {
15354 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15355 intel_sanitize_crtc(crtc);
15356 intel_dump_pipe_config(crtc, crtc->config,
15357 "[setup_hw_state]");
15360 intel_modeset_update_connector_atomic_state(dev);
15362 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15363 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15365 if (!pll->on || pll->active)
15368 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15370 pll->disable(dev_priv, pll);
15374 if (IS_VALLEYVIEW(dev))
15375 vlv_wm_get_hw_state(dev);
15376 else if (IS_GEN9(dev))
15377 skl_wm_get_hw_state(dev);
15378 else if (HAS_PCH_SPLIT(dev))
15379 ilk_wm_get_hw_state(dev);
15381 for_each_intel_crtc(dev, crtc) {
15382 unsigned long put_domains;
15384 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15385 if (WARN_ON(put_domains))
15386 modeset_put_power_domains(dev_priv, put_domains);
15388 intel_display_set_init_power(dev_priv, false);
15391 void intel_display_resume(struct drm_device *dev)
15393 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15394 struct intel_connector *conn;
15395 struct intel_plane *plane;
15396 struct drm_crtc *crtc;
15402 state->acquire_ctx = dev->mode_config.acquire_ctx;
15404 /* preserve complete old state, including dpll */
15405 intel_atomic_get_shared_dpll_state(state);
15407 for_each_crtc(dev, crtc) {
15408 struct drm_crtc_state *crtc_state =
15409 drm_atomic_get_crtc_state(state, crtc);
15411 ret = PTR_ERR_OR_ZERO(crtc_state);
15415 /* force a restore */
15416 crtc_state->mode_changed = true;
15419 for_each_intel_plane(dev, plane) {
15420 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15425 for_each_intel_connector(dev, conn) {
15426 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15431 intel_modeset_setup_hw_state(dev);
15433 i915_redisable_vga(dev);
15434 ret = drm_atomic_commit(state);
15439 DRM_ERROR("Restoring old state failed with %i\n", ret);
15440 drm_atomic_state_free(state);
15443 void intel_modeset_gem_init(struct drm_device *dev)
15445 struct drm_i915_private *dev_priv = dev->dev_private;
15446 struct drm_crtc *c;
15447 struct drm_i915_gem_object *obj;
15450 mutex_lock(&dev->struct_mutex);
15451 intel_init_gt_powersave(dev);
15452 mutex_unlock(&dev->struct_mutex);
15455 * There may be no VBT; and if the BIOS enabled SSC we can
15456 * just keep using it to avoid unnecessary flicker. Whereas if the
15457 * BIOS isn't using it, don't assume it will work even if the VBT
15458 * indicates as much.
15460 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15461 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15464 intel_modeset_init_hw(dev);
15466 intel_setup_overlay(dev);
15469 * Make sure any fbs we allocated at startup are properly
15470 * pinned & fenced. When we do the allocation it's too early
15473 for_each_crtc(dev, c) {
15474 obj = intel_fb_obj(c->primary->fb);
15478 mutex_lock(&dev->struct_mutex);
15479 ret = intel_pin_and_fence_fb_obj(c->primary,
15483 mutex_unlock(&dev->struct_mutex);
15485 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15486 to_intel_crtc(c)->pipe);
15487 drm_framebuffer_unreference(c->primary->fb);
15488 c->primary->fb = NULL;
15489 c->primary->crtc = c->primary->state->crtc = NULL;
15490 update_state_fb(c->primary);
15491 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15495 intel_backlight_register(dev);
15498 void intel_connector_unregister(struct intel_connector *intel_connector)
15500 struct drm_connector *connector = &intel_connector->base;
15502 intel_panel_destroy_backlight(connector);
15503 drm_connector_unregister(connector);
15506 void intel_modeset_cleanup(struct drm_device *dev)
15508 struct drm_i915_private *dev_priv = dev->dev_private;
15509 struct drm_connector *connector;
15511 intel_disable_gt_powersave(dev);
15513 intel_backlight_unregister(dev);
15516 * Interrupts and polling as the first thing to avoid creating havoc.
15517 * Too much stuff here (turning of connectors, ...) would
15518 * experience fancy races otherwise.
15520 intel_irq_uninstall(dev_priv);
15523 * Due to the hpd irq storm handling the hotplug work can re-arm the
15524 * poll handlers. Hence disable polling after hpd handling is shut down.
15526 drm_kms_helper_poll_fini(dev);
15528 intel_unregister_dsm_handler();
15530 intel_fbc_disable(dev_priv);
15532 /* flush any delayed tasks or pending work */
15533 flush_scheduled_work();
15535 /* destroy the backlight and sysfs files before encoders/connectors */
15536 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15537 struct intel_connector *intel_connector;
15539 intel_connector = to_intel_connector(connector);
15540 intel_connector->unregister(intel_connector);
15543 drm_mode_config_cleanup(dev);
15545 intel_cleanup_overlay(dev);
15547 mutex_lock(&dev->struct_mutex);
15548 intel_cleanup_gt_powersave(dev);
15549 mutex_unlock(&dev->struct_mutex);
15553 * Return which encoder is currently attached for connector.
15555 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15557 return &intel_attached_encoder(connector)->base;
15560 void intel_connector_attach_encoder(struct intel_connector *connector,
15561 struct intel_encoder *encoder)
15563 connector->encoder = encoder;
15564 drm_mode_connector_attach_encoder(&connector->base,
15569 * set vga decode state - true == enable VGA decode
15571 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15573 struct drm_i915_private *dev_priv = dev->dev_private;
15574 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15577 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15578 DRM_ERROR("failed to read control word\n");
15582 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15586 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15588 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15590 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15591 DRM_ERROR("failed to write control word\n");
15598 struct intel_display_error_state {
15600 u32 power_well_driver;
15602 int num_transcoders;
15604 struct intel_cursor_error_state {
15609 } cursor[I915_MAX_PIPES];
15611 struct intel_pipe_error_state {
15612 bool power_domain_on;
15615 } pipe[I915_MAX_PIPES];
15617 struct intel_plane_error_state {
15625 } plane[I915_MAX_PIPES];
15627 struct intel_transcoder_error_state {
15628 bool power_domain_on;
15629 enum transcoder cpu_transcoder;
15642 struct intel_display_error_state *
15643 intel_display_capture_error_state(struct drm_device *dev)
15645 struct drm_i915_private *dev_priv = dev->dev_private;
15646 struct intel_display_error_state *error;
15647 int transcoders[] = {
15655 if (INTEL_INFO(dev)->num_pipes == 0)
15658 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15662 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15663 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15665 for_each_pipe(dev_priv, i) {
15666 error->pipe[i].power_domain_on =
15667 __intel_display_power_is_enabled(dev_priv,
15668 POWER_DOMAIN_PIPE(i));
15669 if (!error->pipe[i].power_domain_on)
15672 error->cursor[i].control = I915_READ(CURCNTR(i));
15673 error->cursor[i].position = I915_READ(CURPOS(i));
15674 error->cursor[i].base = I915_READ(CURBASE(i));
15676 error->plane[i].control = I915_READ(DSPCNTR(i));
15677 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15678 if (INTEL_INFO(dev)->gen <= 3) {
15679 error->plane[i].size = I915_READ(DSPSIZE(i));
15680 error->plane[i].pos = I915_READ(DSPPOS(i));
15682 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15683 error->plane[i].addr = I915_READ(DSPADDR(i));
15684 if (INTEL_INFO(dev)->gen >= 4) {
15685 error->plane[i].surface = I915_READ(DSPSURF(i));
15686 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15689 error->pipe[i].source = I915_READ(PIPESRC(i));
15691 if (HAS_GMCH_DISPLAY(dev))
15692 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15695 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15696 if (HAS_DDI(dev_priv->dev))
15697 error->num_transcoders++; /* Account for eDP. */
15699 for (i = 0; i < error->num_transcoders; i++) {
15700 enum transcoder cpu_transcoder = transcoders[i];
15702 error->transcoder[i].power_domain_on =
15703 __intel_display_power_is_enabled(dev_priv,
15704 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15705 if (!error->transcoder[i].power_domain_on)
15708 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15710 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15711 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15712 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15713 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15714 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15715 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15716 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15722 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15725 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15726 struct drm_device *dev,
15727 struct intel_display_error_state *error)
15729 struct drm_i915_private *dev_priv = dev->dev_private;
15735 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15736 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15737 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15738 error->power_well_driver);
15739 for_each_pipe(dev_priv, i) {
15740 err_printf(m, "Pipe [%d]:\n", i);
15741 err_printf(m, " Power: %s\n",
15742 error->pipe[i].power_domain_on ? "on" : "off");
15743 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15744 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15746 err_printf(m, "Plane [%d]:\n", i);
15747 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15748 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15749 if (INTEL_INFO(dev)->gen <= 3) {
15750 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15751 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15753 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15754 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15755 if (INTEL_INFO(dev)->gen >= 4) {
15756 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15757 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15760 err_printf(m, "Cursor [%d]:\n", i);
15761 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15762 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15763 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15766 for (i = 0; i < error->num_transcoders; i++) {
15767 err_printf(m, "CPU transcoder: %c\n",
15768 transcoder_name(error->transcoder[i].cpu_transcoder));
15769 err_printf(m, " Power: %s\n",
15770 error->transcoder[i].power_domain_on ? "on" : "off");
15771 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15772 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15773 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15774 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15775 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15776 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15777 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15781 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15783 struct intel_crtc *crtc;
15785 for_each_intel_crtc(dev, crtc) {
15786 struct intel_unpin_work *work;
15788 spin_lock_irq(&dev->event_lock);
15790 work = crtc->unpin_work;
15792 if (work && work->event &&
15793 work->event->base.file_priv == file) {
15794 kfree(work->event);
15795 work->event = NULL;
15798 spin_unlock_irq(&dev->event_lock);