drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_set_mode(struct drm_atomic_state *state);
  90 static int intel_framebuffer_init(struct drm_device *dev,
  91                                   struct intel_framebuffer *ifb,
  92                                   struct drm_mode_fb_cmd2 *mode_cmd,
  93                                   struct drm_i915_gem_object *obj);
  94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  97                                          struct intel_link_m_n *m_n,
  98                                          struct intel_link_m_n *m2_n2);
  99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 102 static void vlv_prepare_pll(struct intel_crtc *crtc,
 103                             const struct intel_crtc_state *pipe_config);
 104 static void chv_prepare_pll(struct intel_crtc *crtc,
 105                             const struct intel_crtc_state *pipe_config);
 106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 109         struct intel_crtc_state *crtc_state);
 110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 111                            int num_connectors);
 112
 113 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 114 {
 115         if (!connector->mst_port)
 116                 return connector->encoder;
 117         else
 118                 return &connector->mst_port->mst_encoders[pipe]->base;
 119 }
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 int
 137 intel_pch_rawclk(struct drm_device *dev)
 138 {
 139         struct drm_i915_private *dev_priv = dev->dev_private;
 140
 141         WARN_ON(!HAS_PCH_SPLIT(dev));
 142
 143         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 144 }
 145
 146 static inline u32 /* units of 100MHz */
 147 intel_fdi_link_freq(struct drm_device *dev)
 148 {
 149         if (IS_GEN5(dev)) {
 150                 struct drm_i915_private *dev_priv = dev->dev_private;
 151                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 152         } else
 153                 return 27;
 154 }
 155
 156 static const intel_limit_t intel_limits_i8xx_dac = {
 157         .dot = { .min = 25000, .max = 350000 },
 158         .vco = { .min = 908000, .max = 1512000 },
 159         .n = { .min = 2, .max = 16 },
 160         .m = { .min = 96, .max = 140 },
 161         .m1 = { .min = 18, .max = 26 },
 162         .m2 = { .min = 6, .max = 16 },
 163         .p = { .min = 4, .max = 128 },
 164         .p1 = { .min = 2, .max = 33 },
 165         .p2 = { .dot_limit = 165000,
 166                 .p2_slow = 4, .p2_fast = 2 },
 167 };
 168
 169 static const intel_limit_t intel_limits_i8xx_dvo = {
 170         .dot = { .min = 25000, .max = 350000 },
 171         .vco = { .min = 908000, .max = 1512000 },
 172         .n = { .min = 2, .max = 16 },
 173         .m = { .min = 96, .max = 140 },
 174         .m1 = { .min = 18, .max = 26 },
 175         .m2 = { .min = 6, .max = 16 },
 176         .p = { .min = 4, .max = 128 },
 177         .p1 = { .min = 2, .max = 33 },
 178         .p2 = { .dot_limit = 165000,
 179                 .p2_slow = 4, .p2_fast = 4 },
 180 };
 181
 182 static const intel_limit_t intel_limits_i8xx_lvds = {
 183         .dot = { .min = 25000, .max = 350000 },
 184         .vco = { .min = 908000, .max = 1512000 },
 185         .n = { .min = 2, .max = 16 },
 186         .m = { .min = 96, .max = 140 },
 187         .m1 = { .min = 18, .max = 26 },
 188         .m2 = { .min = 6, .max = 16 },
 189         .p = { .min = 4, .max = 128 },
 190         .p1 = { .min = 1, .max = 6 },
 191         .p2 = { .dot_limit = 165000,
 192                 .p2_slow = 14, .p2_fast = 7 },
 193 };
 194
 195 static const intel_limit_t intel_limits_i9xx_sdvo = {
 196         .dot = { .min = 20000, .max = 400000 },
 197         .vco = { .min = 1400000, .max = 2800000 },
 198         .n = { .min = 1, .max = 6 },
 199         .m = { .min = 70, .max = 120 },
 200         .m1 = { .min = 8, .max = 18 },
 201         .m2 = { .min = 3, .max = 7 },
 202         .p = { .min = 5, .max = 80 },
 203         .p1 = { .min = 1, .max = 8 },
 204         .p2 = { .dot_limit = 200000,
 205                 .p2_slow = 10, .p2_fast = 5 },
 206 };
 207
 208 static const intel_limit_t intel_limits_i9xx_lvds = {
 209         .dot = { .min = 20000, .max = 400000 },
 210         .vco = { .min = 1400000, .max = 2800000 },
 211         .n = { .min = 1, .max = 6 },
 212         .m = { .min = 70, .max = 120 },
 213         .m1 = { .min = 8, .max = 18 },
 214         .m2 = { .min = 3, .max = 7 },
 215         .p = { .min = 7, .max = 98 },
 216         .p1 = { .min = 1, .max = 8 },
 217         .p2 = { .dot_limit = 112000,
 218                 .p2_slow = 14, .p2_fast = 7 },
 219 };
 220
 221
 222 static const intel_limit_t intel_limits_g4x_sdvo = {
 223         .dot = { .min = 25000, .max = 270000 },
 224         .vco = { .min = 1750000, .max = 3500000},
 225         .n = { .min = 1, .max = 4 },
 226         .m = { .min = 104, .max = 138 },
 227         .m1 = { .min = 17, .max = 23 },
 228         .m2 = { .min = 5, .max = 11 },
 229         .p = { .min = 10, .max = 30 },
 230         .p1 = { .min = 1, .max = 3},
 231         .p2 = { .dot_limit = 270000,
 232                 .p2_slow = 10,
 233                 .p2_fast = 10
 234         },
 235 };
 236
 237 static const intel_limit_t intel_limits_g4x_hdmi = {
 238         .dot = { .min = 22000, .max = 400000 },
 239         .vco = { .min = 1750000, .max = 3500000},
 240         .n = { .min = 1, .max = 4 },
 241         .m = { .min = 104, .max = 138 },
 242         .m1 = { .min = 16, .max = 23 },
 243         .m2 = { .min = 5, .max = 11 },
 244         .p = { .min = 5, .max = 80 },
 245         .p1 = { .min = 1, .max = 8},
 246         .p2 = { .dot_limit = 165000,
 247                 .p2_slow = 10, .p2_fast = 5 },
 248 };
 249
 250 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 251         .dot = { .min = 20000, .max = 115000 },
 252         .vco = { .min = 1750000, .max = 3500000 },
 253         .n = { .min = 1, .max = 3 },
 254         .m = { .min = 104, .max = 138 },
 255         .m1 = { .min = 17, .max = 23 },
 256         .m2 = { .min = 5, .max = 11 },
 257         .p = { .min = 28, .max = 112 },
 258         .p1 = { .min = 2, .max = 8 },
 259         .p2 = { .dot_limit = 0,
 260                 .p2_slow = 14, .p2_fast = 14
 261         },
 262 };
 263
 264 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 265         .dot = { .min = 80000, .max = 224000 },
 266         .vco = { .min = 1750000, .max = 3500000 },
 267         .n = { .min = 1, .max = 3 },
 268         .m = { .min = 104, .max = 138 },
 269         .m1 = { .min = 17, .max = 23 },
 270         .m2 = { .min = 5, .max = 11 },
 271         .p = { .min = 14, .max = 42 },
 272         .p1 = { .min = 2, .max = 6 },
 273         .p2 = { .dot_limit = 0,
 274                 .p2_slow = 7, .p2_fast = 7
 275         },
 276 };
 277
 278 static const intel_limit_t intel_limits_pineview_sdvo = {
 279         .dot = { .min = 20000, .max = 400000},
 280         .vco = { .min = 1700000, .max = 3500000 },
 281         /* Pineview's Ncounter is a ring counter */
 282         .n = { .min = 3, .max = 6 },
 283         .m = { .min = 2, .max = 256 },
 284         /* Pineview only has one combined m divider, which we treat as m2. */
 285         .m1 = { .min = 0, .max = 0 },
 286         .m2 = { .min = 0, .max = 254 },
 287         .p = { .min = 5, .max = 80 },
 288         .p1 = { .min = 1, .max = 8 },
 289         .p2 = { .dot_limit = 200000,
 290                 .p2_slow = 10, .p2_fast = 5 },
 291 };
 292
 293 static const intel_limit_t intel_limits_pineview_lvds = {
 294         .dot = { .min = 20000, .max = 400000 },
 295         .vco = { .min = 1700000, .max = 3500000 },
 296         .n = { .min = 3, .max = 6 },
 297         .m = { .min = 2, .max = 256 },
 298         .m1 = { .min = 0, .max = 0 },
 299         .m2 = { .min = 0, .max = 254 },
 300         .p = { .min = 7, .max = 112 },
 301         .p1 = { .min = 1, .max = 8 },
 302         .p2 = { .dot_limit = 112000,
 303                 .p2_slow = 14, .p2_fast = 14 },
 304 };
 305
 306 /* Ironlake / Sandybridge
 307  *
 308  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 309  * the range value for them is (actual_value - 2).
 310  */
 311 static const intel_limit_t intel_limits_ironlake_dac = {
 312         .dot = { .min = 25000, .max = 350000 },
 313         .vco = { .min = 1760000, .max = 3510000 },
 314         .n = { .min = 1, .max = 5 },
 315         .m = { .min = 79, .max = 127 },
 316         .m1 = { .min = 12, .max = 22 },
 317         .m2 = { .min = 5, .max = 9 },
 318         .p = { .min = 5, .max = 80 },
 319         .p1 = { .min = 1, .max = 8 },
 320         .p2 = { .dot_limit = 225000,
 321                 .p2_slow = 10, .p2_fast = 5 },
 322 };
 323
 324 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 325         .dot = { .min = 25000, .max = 350000 },
 326         .vco = { .min = 1760000, .max = 3510000 },
 327         .n = { .min = 1, .max = 3 },
 328         .m = { .min = 79, .max = 118 },
 329         .m1 = { .min = 12, .max = 22 },
 330         .m2 = { .min = 5, .max = 9 },
 331         .p = { .min = 28, .max = 112 },
 332         .p1 = { .min = 2, .max = 8 },
 333         .p2 = { .dot_limit = 225000,
 334                 .p2_slow = 14, .p2_fast = 14 },
 335 };
 336
 337 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 338         .dot = { .min = 25000, .max = 350000 },
 339         .vco = { .min = 1760000, .max = 3510000 },
 340         .n = { .min = 1, .max = 3 },
 341         .m = { .min = 79, .max = 127 },
 342         .m1 = { .min = 12, .max = 22 },
 343         .m2 = { .min = 5, .max = 9 },
 344         .p = { .min = 14, .max = 56 },
 345         .p1 = { .min = 2, .max = 8 },
 346         .p2 = { .dot_limit = 225000,
 347                 .p2_slow = 7, .p2_fast = 7 },
 348 };
 349
 350 /* LVDS 100mhz refclk limits. */
 351 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 352         .dot = { .min = 25000, .max = 350000 },
 353         .vco = { .min = 1760000, .max = 3510000 },
 354         .n = { .min = 1, .max = 2 },
 355         .m = { .min = 79, .max = 126 },
 356         .m1 = { .min = 12, .max = 22 },
 357         .m2 = { .min = 5, .max = 9 },
 358         .p = { .min = 28, .max = 112 },
 359         .p1 = { .min = 2, .max = 8 },
 360         .p2 = { .dot_limit = 225000,
 361                 .p2_slow = 14, .p2_fast = 14 },
 362 };
 363
 364 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 365         .dot = { .min = 25000, .max = 350000 },
 366         .vco = { .min = 1760000, .max = 3510000 },
 367         .n = { .min = 1, .max = 3 },
 368         .m = { .min = 79, .max = 126 },
 369         .m1 = { .min = 12, .max = 22 },
 370         .m2 = { .min = 5, .max = 9 },
 371         .p = { .min = 14, .max = 42 },
 372         .p1 = { .min = 2, .max = 6 },
 373         .p2 = { .dot_limit = 225000,
 374                 .p2_slow = 7, .p2_fast = 7 },
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv = {
 378          /*
 379           * These are the data rate limits (measured in fast clocks)
 380           * since those are the strictest limits we have. The fast
 381           * clock and actual rate limits are more relaxed, so checking
 382           * them would make no difference.
 383           */
 384         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 385         .vco = { .min = 4000000, .max = 6000000 },
 386         .n = { .min = 1, .max = 7 },
 387         .m1 = { .min = 2, .max = 3 },
 388         .m2 = { .min = 11, .max = 156 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 391 };
 392
 393 static const intel_limit_t intel_limits_chv = {
 394         /*
 395          * These are the data rate limits (measured in fast clocks)
 396          * since those are the strictest limits we have.  The fast
 397          * clock and actual rate limits are more relaxed, so checking
 398          * them would make no difference.
 399          */
 400         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 401         .vco = { .min = 4800000, .max = 6480000 },
 402         .n = { .min = 1, .max = 1 },
 403         .m1 = { .min = 2, .max = 2 },
 404         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 405         .p1 = { .min = 2, .max = 4 },
 406         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 407 };
 408
 409 static const intel_limit_t intel_limits_bxt = {
 410         /* FIXME: find real dot limits */
 411         .dot = { .min = 0, .max = INT_MAX },
 412         .vco = { .min = 4800000, .max = 6700000 },
 413         .n = { .min = 1, .max = 1 },
 414         .m1 = { .min = 2, .max = 2 },
 415         /* FIXME: find real m2 limits */
 416         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 417         .p1 = { .min = 2, .max = 4 },
 418         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 419 };
 420
 421 static bool
 422 needs_modeset(struct drm_crtc_state *state)
 423 {
 424         return state->mode_changed || state->active_changed;
 425 }
 426
 427 /**
 428  * Returns whether any output on the specified pipe is of the specified type
 429  */
 430 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 431 {
 432         struct drm_device *dev = crtc->base.dev;
 433         struct intel_encoder *encoder;
 434
 435         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 436                 if (encoder->type == type)
 437                         return true;
 438
 439         return false;
 440 }
 441
 442 /**
 443  * Returns whether any output on the specified pipe will have the specified
 444  * type after a staged modeset is complete, i.e., the same as
 445  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 446  * encoder->crtc.
 447  */
 448 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 449                                       int type)
 450 {
 451         struct drm_atomic_state *state = crtc_state->base.state;
 452         struct drm_connector *connector;
 453         struct drm_connector_state *connector_state;
 454         struct intel_encoder *encoder;
 455         int i, num_connectors = 0;
 456
 457         for_each_connector_in_state(state, connector, connector_state, i) {
 458                 if (connector_state->crtc != crtc_state->base.crtc)
 459                         continue;
 460
 461                 num_connectors++;
 462
 463                 encoder = to_intel_encoder(connector_state->best_encoder);
 464                 if (encoder->type == type)
 465                         return true;
 466         }
 467
 468         WARN_ON(num_connectors == 0);
 469
 470         return false;
 471 }
 472
 473 static const intel_limit_t *
 474 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 475 {
 476         struct drm_device *dev = crtc_state->base.crtc->dev;
 477         const intel_limit_t *limit;
 478
 479         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 480                 if (intel_is_dual_link_lvds(dev)) {
 481                         if (refclk == 100000)
 482                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 483                         else
 484                                 limit = &intel_limits_ironlake_dual_lvds;
 485                 } else {
 486                         if (refclk == 100000)
 487                                 limit = &intel_limits_ironlake_single_lvds_100m;
 488                         else
 489                                 limit = &intel_limits_ironlake_single_lvds;
 490                 }
 491         } else
 492                 limit = &intel_limits_ironlake_dac;
 493
 494         return limit;
 495 }
 496
 497 static const intel_limit_t *
 498 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 499 {
 500         struct drm_device *dev = crtc_state->base.crtc->dev;
 501         const intel_limit_t *limit;
 502
 503         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 504                 if (intel_is_dual_link_lvds(dev))
 505                         limit = &intel_limits_g4x_dual_channel_lvds;
 506                 else
 507                         limit = &intel_limits_g4x_single_channel_lvds;
 508         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 509                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 510                 limit = &intel_limits_g4x_hdmi;
 511         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 512                 limit = &intel_limits_g4x_sdvo;
 513         } else /* The option is for other outputs */
 514                 limit = &intel_limits_i9xx_sdvo;
 515
 516         return limit;
 517 }
 518
 519 static const intel_limit_t *
 520 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 521 {
 522         struct drm_device *dev = crtc_state->base.crtc->dev;
 523         const intel_limit_t *limit;
 524
 525         if (IS_BROXTON(dev))
 526                 limit = &intel_limits_bxt;
 527         else if (HAS_PCH_SPLIT(dev))
 528                 limit = intel_ironlake_limit(crtc_state, refclk);
 529         else if (IS_G4X(dev)) {
 530                 limit = intel_g4x_limit(crtc_state);
 531         } else if (IS_PINEVIEW(dev)) {
 532                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 533                         limit = &intel_limits_pineview_lvds;
 534                 else
 535                         limit = &intel_limits_pineview_sdvo;
 536         } else if (IS_CHERRYVIEW(dev)) {
 537                 limit = &intel_limits_chv;
 538         } else if (IS_VALLEYVIEW(dev)) {
 539                 limit = &intel_limits_vlv;
 540         } else if (!IS_GEN2(dev)) {
 541                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 542                         limit = &intel_limits_i9xx_lvds;
 543                 else
 544                         limit = &intel_limits_i9xx_sdvo;
 545         } else {
 546                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 547                         limit = &intel_limits_i8xx_lvds;
 548                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 549                         limit = &intel_limits_i8xx_dvo;
 550                 else
 551                         limit = &intel_limits_i8xx_dac;
 552         }
 553         return limit;
 554 }
 555
 556 /*
 557  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 558  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 559  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 560  * The helpers' return value is the rate of the clock that is fed to the
 561  * display engine's pipe which can be the above fast dot clock rate or a
 562  * divided-down version of it.
 563  */
 564 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 565 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 566 {
 567         clock->m = clock->m2 + 2;
 568         clock->p = clock->p1 * clock->p2;
 569         if (WARN_ON(clock->n == 0 || clock->p == 0))
 570                 return 0;
 571         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 572         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 573
 574         return clock->dot;
 575 }
 576
 577 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 578 {
 579         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 580 }
 581
 582 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 583 {
 584         clock->m = i9xx_dpll_compute_m(clock);
 585         clock->p = clock->p1 * clock->p2;
 586         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 587                 return 0;
 588         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 589         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 590
 591         return clock->dot;
 592 }
 593
 594 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 595 {
 596         clock->m = clock->m1 * clock->m2;
 597         clock->p = clock->p1 * clock->p2;
 598         if (WARN_ON(clock->n == 0 || clock->p == 0))
 599                 return 0;
 600         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 601         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 602
 603         return clock->dot / 5;
 604 }
 605
 606 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 607 {
 608         clock->m = clock->m1 * clock->m2;
 609         clock->p = clock->p1 * clock->p2;
 610         if (WARN_ON(clock->n == 0 || clock->p == 0))
 611                 return 0;
 612         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 613                         clock->n << 22);
 614         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 615
 616         return clock->dot / 5;
 617 }
 618
 619 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 620 /**
 621  * Returns whether the given set of divisors are valid for a given refclk with
 622  * the given connectors.
 623  */
 624
 625 static bool intel_PLL_is_valid(struct drm_device *dev,
 626                                const intel_limit_t *limit,
 627                                const intel_clock_t *clock)
 628 {
 629         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 630                 INTELPllInvalid("n out of range\n");
 631         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 632                 INTELPllInvalid("p1 out of range\n");
 633         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 634                 INTELPllInvalid("m2 out of range\n");
 635         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 636                 INTELPllInvalid("m1 out of range\n");
 637
 638         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 639                 if (clock->m1 <= clock->m2)
 640                         INTELPllInvalid("m1 <= m2\n");
 641
 642         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 643                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 644                         INTELPllInvalid("p out of range\n");
 645                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 646                         INTELPllInvalid("m out of range\n");
 647         }
 648
 649         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 650                 INTELPllInvalid("vco out of range\n");
 651         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 652          * connector, etc., rather than just a single range.
 653          */
 654         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 655                 INTELPllInvalid("dot out of range\n");
 656
 657         return true;
 658 }
 659
 660 static int
 661 i9xx_select_p2_div(const intel_limit_t *limit,
 662                    const struct intel_crtc_state *crtc_state,
 663                    int target)
 664 {
 665         struct drm_device *dev = crtc_state->base.crtc->dev;
 666
 667         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 668                 /*
 669                  * For LVDS just rely on its current settings for dual-channel.
 670                  * We haven't figured out how to reliably set up different
 671                  * single/dual channel state, if we even can.
 672                  */
 673                 if (intel_is_dual_link_lvds(dev))
 674                         return limit->p2.p2_fast;
 675                 else
 676                         return limit->p2.p2_slow;
 677         } else {
 678                 if (target < limit->p2.dot_limit)
 679                         return limit->p2.p2_slow;
 680                 else
 681                         return limit->p2.p2_fast;
 682         }
 683 }
 684
 685 static bool
 686 i9xx_find_best_dpll(const intel_limit_t *limit,
 687                     struct intel_crtc_state *crtc_state,
 688                     int target, int refclk, intel_clock_t *match_clock,
 689                     intel_clock_t *best_clock)
 690 {
 691         struct drm_device *dev = crtc_state->base.crtc->dev;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         memset(best_clock, 0, sizeof(*best_clock));
 696
 697         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 698
 699         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 700              clock.m1++) {
 701                 for (clock.m2 = limit->m2.min;
 702                      clock.m2 <= limit->m2.max; clock.m2++) {
 703                         if (clock.m2 >= clock.m1)
 704                                 break;
 705                         for (clock.n = limit->n.min;
 706                              clock.n <= limit->n.max; clock.n++) {
 707                                 for (clock.p1 = limit->p1.min;
 708                                         clock.p1 <= limit->p1.max; clock.p1++) {
 709                                         int this_err;
 710
 711                                         i9xx_calc_dpll_params(refclk, &clock);
 712                                         if (!intel_PLL_is_valid(dev, limit,
 713                                                                 &clock))
 714                                                 continue;
 715                                         if (match_clock &&
 716                                             clock.p != match_clock->p)
 717                                                 continue;
 718
 719                                         this_err = abs(clock.dot - target);
 720                                         if (this_err < err) {
 721                                                 *best_clock = clock;
 722                                                 err = this_err;
 723                                         }
 724                                 }
 725                         }
 726                 }
 727         }
 728
 729         return (err != target);
 730 }
 731
 732 static bool
 733 pnv_find_best_dpll(const intel_limit_t *limit,
 734                    struct intel_crtc_state *crtc_state,
 735                    int target, int refclk, intel_clock_t *match_clock,
 736                    intel_clock_t *best_clock)
 737 {
 738         struct drm_device *dev = crtc_state->base.crtc->dev;
 739         intel_clock_t clock;
 740         int err = target;
 741
 742         memset(best_clock, 0, sizeof(*best_clock));
 743
 744         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 745
 746         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 747              clock.m1++) {
 748                 for (clock.m2 = limit->m2.min;
 749                      clock.m2 <= limit->m2.max; clock.m2++) {
 750                         for (clock.n = limit->n.min;
 751                              clock.n <= limit->n.max; clock.n++) {
 752                                 for (clock.p1 = limit->p1.min;
 753                                         clock.p1 <= limit->p1.max; clock.p1++) {
 754                                         int this_err;
 755
 756                                         pnv_calc_dpll_params(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760                                         if (match_clock &&
 761                                             clock.p != match_clock->p)
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err) {
 766                                                 *best_clock = clock;
 767                                                 err = this_err;
 768                                         }
 769                                 }
 770                         }
 771                 }
 772         }
 773
 774         return (err != target);
 775 }
 776
 777 static bool
 778 g4x_find_best_dpll(const intel_limit_t *limit,
 779                    struct intel_crtc_state *crtc_state,
 780                    int target, int refclk, intel_clock_t *match_clock,
 781                    intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc_state->base.crtc->dev;
 784         intel_clock_t clock;
 785         int max_n;
 786         bool found = false;
 787         /* approximately equals target * 0.00585 */
 788         int err_most = (target >> 8) + (target >> 9);
 789
 790         memset(best_clock, 0, sizeof(*best_clock));
 791
 792         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 793
 794         max_n = limit->n.max;
 795         /* based on hardware requirement, prefer smaller n to precision */
 796         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 797                 /* based on hardware requirement, prefere larger m1,m2 */
 798                 for (clock.m1 = limit->m1.max;
 799                      clock.m1 >= limit->m1.min; clock.m1--) {
 800                         for (clock.m2 = limit->m2.max;
 801                              clock.m2 >= limit->m2.min; clock.m2--) {
 802                                 for (clock.p1 = limit->p1.max;
 803                                      clock.p1 >= limit->p1.min; clock.p1--) {
 804                                         int this_err;
 805
 806                                         i9xx_calc_dpll_params(refclk, &clock);
 807                                         if (!intel_PLL_is_valid(dev, limit,
 808                                                                 &clock))
 809                                                 continue;
 810
 811                                         this_err = abs(clock.dot - target);
 812                                         if (this_err < err_most) {
 813                                                 *best_clock = clock;
 814                                                 err_most = this_err;
 815                                                 max_n = clock.n;
 816                                                 found = true;
 817                                         }
 818                                 }
 819                         }
 820                 }
 821         }
 822         return found;
 823 }
 824
 825 /*
 826  * Check if the calculated PLL configuration is more optimal compared to the
 827  * best configuration and error found so far. Return the calculated error.
 828  */
 829 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 830                                const intel_clock_t *calculated_clock,
 831                                const intel_clock_t *best_clock,
 832                                unsigned int best_error_ppm,
 833                                unsigned int *error_ppm)
 834 {
 835         /*
 836          * For CHV ignore the error and consider only the P value.
 837          * Prefer a bigger P value based on HW requirements.
 838          */
 839         if (IS_CHERRYVIEW(dev)) {
 840                 *error_ppm = 0;
 841
 842                 return calculated_clock->p > best_clock->p;
 843         }
 844
 845         if (WARN_ON_ONCE(!target_freq))
 846                 return false;
 847
 848         *error_ppm = div_u64(1000000ULL *
 849                                 abs(target_freq - calculated_clock->dot),
 850                              target_freq);
 851         /*
 852          * Prefer a better P value over a better (smaller) error if the error
 853          * is small. Ensure this preference for future configurations too by
 854          * setting the error to 0.
 855          */
 856         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 857                 *error_ppm = 0;
 858
 859                 return true;
 860         }
 861
 862         return *error_ppm + 10 < best_error_ppm;
 863 }
 864
 865 static bool
 866 vlv_find_best_dpll(const intel_limit_t *limit,
 867                    struct intel_crtc_state *crtc_state,
 868                    int target, int refclk, intel_clock_t *match_clock,
 869                    intel_clock_t *best_clock)
 870 {
 871         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 872         struct drm_device *dev = crtc->base.dev;
 873         intel_clock_t clock;
 874         unsigned int bestppm = 1000000;
 875         /* min update 19.2 MHz */
 876         int max_n = min(limit->n.max, refclk / 19200);
 877         bool found = false;
 878
 879         target *= 5; /* fast clock */
 880
 881         memset(best_clock, 0, sizeof(*best_clock));
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 885                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 886                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 887                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 888                                 clock.p = clock.p1 * clock.p2;
 889                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 890                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 891                                         unsigned int ppm;
 892
 893                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 894                                                                      refclk * clock.m1);
 895
 896                                         vlv_calc_dpll_params(refclk, &clock);
 897
 898                                         if (!intel_PLL_is_valid(dev, limit,
 899                                                                 &clock))
 900                                                 continue;
 901
 902                                         if (!vlv_PLL_is_optimal(dev, target,
 903                                                                 &clock,
 904                                                                 best_clock,
 905                                                                 bestppm, &ppm))
 906                                                 continue;
 907
 908                                         *best_clock = clock;
 909                                         bestppm = ppm;
 910                                         found = true;
 911                                 }
 912                         }
 913                 }
 914         }
 915
 916         return found;
 917 }
 918
 919 static bool
 920 chv_find_best_dpll(const intel_limit_t *limit,
 921                    struct intel_crtc_state *crtc_state,
 922                    int target, int refclk, intel_clock_t *match_clock,
 923                    intel_clock_t *best_clock)
 924 {
 925         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 926         struct drm_device *dev = crtc->base.dev;
 927         unsigned int best_error_ppm;
 928         intel_clock_t clock;
 929         uint64_t m2;
 930         int found = false;
 931
 932         memset(best_clock, 0, sizeof(*best_clock));
 933         best_error_ppm = 1000000;
 934
 935         /*
 936          * Based on hardware doc, the n always set to 1, and m1 always
 937          * set to 2.  If requires to support 200Mhz refclk, we need to
 938          * revisit this because n may not 1 anymore.
 939          */
 940         clock.n = 1, clock.m1 = 2;
 941         target *= 5;    /* fast clock */
 942
 943         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 944                 for (clock.p2 = limit->p2.p2_fast;
 945                                 clock.p2 >= limit->p2.p2_slow;
 946                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 947                         unsigned int error_ppm;
 948
 949                         clock.p = clock.p1 * clock.p2;
 950
 951                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 952                                         clock.n) << 22, refclk * clock.m1);
 953
 954                         if (m2 > INT_MAX/clock.m1)
 955                                 continue;
 956
 957                         clock.m2 = m2;
 958
 959                         chv_calc_dpll_params(refclk, &clock);
 960
 961                         if (!intel_PLL_is_valid(dev, limit, &clock))
 962                                 continue;
 963
 964                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 965                                                 best_error_ppm, &error_ppm))
 966                                 continue;
 967
 968                         *best_clock = clock;
 969                         best_error_ppm = error_ppm;
 970                         found = true;
 971                 }
 972         }
 973
 974         return found;
 975 }
 976
 977 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 978                         intel_clock_t *best_clock)
 979 {
 980         int refclk = i9xx_get_refclk(crtc_state, 0);
 981
 982         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 983                                   target_clock, refclk, NULL, best_clock);
 984 }
 985
 986 bool intel_crtc_active(struct drm_crtc *crtc)
 987 {
 988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 989
 990         /* Be paranoid as we can arrive here with only partial
 991          * state retrieved from the hardware during setup.
 992          *
 993          * We can ditch the adjusted_mode.crtc_clock check as soon
 994          * as Haswell has gained clock readout/fastboot support.
 995          *
 996          * We can ditch the crtc->primary->fb check as soon as we can
 997          * properly reconstruct framebuffers.
 998          *
 999          * FIXME: The intel_crtc->active here should be switched to
1000          * crtc->state->active once we have proper CRTC states wired up
1001          * for atomic.
1002          */
1003         return intel_crtc->active && crtc->primary->state->fb &&
1004                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1005 }
1006
1007 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1008                                              enum pipe pipe)
1009 {
1010         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1012
1013         return intel_crtc->config->cpu_transcoder;
1014 }
1015
1016 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1017 {
1018         struct drm_i915_private *dev_priv = dev->dev_private;
1019         u32 reg = PIPEDSL(pipe);
1020         u32 line1, line2;
1021         u32 line_mask;
1022
1023         if (IS_GEN2(dev))
1024                 line_mask = DSL_LINEMASK_GEN2;
1025         else
1026                 line_mask = DSL_LINEMASK_GEN3;
1027
1028         line1 = I915_READ(reg) & line_mask;
1029         msleep(5);
1030         line2 = I915_READ(reg) & line_mask;
1031
1032         return line1 == line2;
1033 }
1034
1035 /*
1036  * intel_wait_for_pipe_off - wait for pipe to turn off
1037  * @crtc: crtc whose pipe to wait for
1038  *
1039  * After disabling a pipe, we can't wait for vblank in the usual way,
1040  * spinning on the vblank interrupt status bit, since we won't actually
1041  * see an interrupt when the pipe is disabled.
1042  *
1043  * On Gen4 and above:
1044  *   wait for the pipe register state bit to turn off
1045  *
1046  * Otherwise:
1047  *   wait for the display line value to settle (it usually
1048  *   ends up stopping at the start of the next frame).
1049  *
1050  */
1051 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1052 {
1053         struct drm_device *dev = crtc->base.dev;
1054         struct drm_i915_private *dev_priv = dev->dev_private;
1055         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1056         enum pipe pipe = crtc->pipe;
1057
1058         if (INTEL_INFO(dev)->gen >= 4) {
1059                 int reg = PIPECONF(cpu_transcoder);
1060
1061                 /* Wait for the Pipe State to go off */
1062                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1063                              100))
1064                         WARN(1, "pipe_off wait timed out\n");
1065         } else {
1066                 /* Wait for the display line to settle */
1067                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1068                         WARN(1, "pipe_off wait timed out\n");
1069         }
1070 }
1071
1072 /*
1073  * ibx_digital_port_connected - is the specified port connected?
1074  * @dev_priv: i915 private structure
1075  * @port: the port to test
1076  *
1077  * Returns true if @port is connected, false otherwise.
1078  */
1079 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1080                                 struct intel_digital_port *port)
1081 {
1082         u32 bit;
1083
1084         if (HAS_PCH_IBX(dev_priv->dev)) {
1085                 switch (port->port) {
1086                 case PORT_B:
1087                         bit = SDE_PORTB_HOTPLUG;
1088                         break;
1089                 case PORT_C:
1090                         bit = SDE_PORTC_HOTPLUG;
1091                         break;
1092                 case PORT_D:
1093                         bit = SDE_PORTD_HOTPLUG;
1094                         break;
1095                 default:
1096                         return true;
1097                 }
1098         } else {
1099                 switch (port->port) {
1100                 case PORT_B:
1101                         bit = SDE_PORTB_HOTPLUG_CPT;
1102                         break;
1103                 case PORT_C:
1104                         bit = SDE_PORTC_HOTPLUG_CPT;
1105                         break;
1106                 case PORT_D:
1107                         bit = SDE_PORTD_HOTPLUG_CPT;
1108                         break;
1109                 default:
1110                         return true;
1111                 }
1112         }
1113
1114         return I915_READ(SDEISR) & bit;
1115 }
1116
1117 static const char *state_string(bool enabled)
1118 {
1119         return enabled ? "on" : "off";
1120 }
1121
1122 /* Only for pre-ILK configs */
1123 void assert_pll(struct drm_i915_private *dev_priv,
1124                 enum pipe pipe, bool state)
1125 {
1126         int reg;
1127         u32 val;
1128         bool cur_state;
1129
1130         reg = DPLL(pipe);
1131         val = I915_READ(reg);
1132         cur_state = !!(val & DPLL_VCO_ENABLE);
1133         I915_STATE_WARN(cur_state != state,
1134              "PLL state assertion failure (expected %s, current %s)\n",
1135              state_string(state), state_string(cur_state));
1136 }
1137
1138 /* XXX: the dsi pll is shared between MIPI DSI ports */
1139 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1140 {
1141         u32 val;
1142         bool cur_state;
1143
1144         mutex_lock(&dev_priv->sb_lock);
1145         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1146         mutex_unlock(&dev_priv->sb_lock);
1147
1148         cur_state = val & DSI_PLL_VCO_EN;
1149         I915_STATE_WARN(cur_state != state,
1150              "DSI PLL state assertion failure (expected %s, current %s)\n",
1151              state_string(state), state_string(cur_state));
1152 }
1153 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1154 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1155
1156 struct intel_shared_dpll *
1157 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1158 {
1159         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1160
1161         if (crtc->config->shared_dpll < 0)
1162                 return NULL;
1163
1164         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1165 }
1166
1167 /* For ILK+ */
1168 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1169                         struct intel_shared_dpll *pll,
1170                         bool state)
1171 {
1172         bool cur_state;
1173         struct intel_dpll_hw_state hw_state;
1174
1175         if (WARN (!pll,
1176                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1177                 return;
1178
1179         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1180         I915_STATE_WARN(cur_state != state,
1181              "%s assertion failure (expected %s, current %s)\n",
1182              pll->name, state_string(state), state_string(cur_state));
1183 }
1184
1185 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1186                           enum pipe pipe, bool state)
1187 {
1188         int reg;
1189         u32 val;
1190         bool cur_state;
1191         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192                                                                       pipe);
1193
1194         if (HAS_DDI(dev_priv->dev)) {
1195                 /* DDI does not have a specific FDI_TX register */
1196                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1197                 val = I915_READ(reg);
1198                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1199         } else {
1200                 reg = FDI_TX_CTL(pipe);
1201                 val = I915_READ(reg);
1202                 cur_state = !!(val & FDI_TX_ENABLE);
1203         }
1204         I915_STATE_WARN(cur_state != state,
1205              "FDI TX state assertion failure (expected %s, current %s)\n",
1206              state_string(state), state_string(cur_state));
1207 }
1208 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1209 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1210
1211 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1212                           enum pipe pipe, bool state)
1213 {
1214         int reg;
1215         u32 val;
1216         bool cur_state;
1217
1218         reg = FDI_RX_CTL(pipe);
1219         val = I915_READ(reg);
1220         cur_state = !!(val & FDI_RX_ENABLE);
1221         I915_STATE_WARN(cur_state != state,
1222              "FDI RX state assertion failure (expected %s, current %s)\n",
1223              state_string(state), state_string(cur_state));
1224 }
1225 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1226 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1227
1228 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1229                                       enum pipe pipe)
1230 {
1231         int reg;
1232         u32 val;
1233
1234         /* ILK FDI PLL is always enabled */
1235         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1236                 return;
1237
1238         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1239         if (HAS_DDI(dev_priv->dev))
1240                 return;
1241
1242         reg = FDI_TX_CTL(pipe);
1243         val = I915_READ(reg);
1244         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1245 }
1246
1247 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1248                        enum pipe pipe, bool state)
1249 {
1250         int reg;
1251         u32 val;
1252         bool cur_state;
1253
1254         reg = FDI_RX_CTL(pipe);
1255         val = I915_READ(reg);
1256         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1257         I915_STATE_WARN(cur_state != state,
1258              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1259              state_string(state), state_string(cur_state));
1260 }
1261
1262 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1263                            enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int pp_reg;
1267         u32 val;
1268         enum pipe panel_pipe = PIPE_A;
1269         bool locked = true;
1270
1271         if (WARN_ON(HAS_DDI(dev)))
1272                 return;
1273
1274         if (HAS_PCH_SPLIT(dev)) {
1275                 u32 port_sel;
1276
1277                 pp_reg = PCH_PP_CONTROL;
1278                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1279
1280                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1281                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1282                         panel_pipe = PIPE_B;
1283                 /* XXX: else fix for eDP */
1284         } else if (IS_VALLEYVIEW(dev)) {
1285                 /* presumably write lock depends on pipe, not port select */
1286                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1287                 panel_pipe = pipe;
1288         } else {
1289                 pp_reg = PP_CONTROL;
1290                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1291                         panel_pipe = PIPE_B;
1292         }
1293
1294         val = I915_READ(pp_reg);
1295         if (!(val & PANEL_POWER_ON) ||
1296             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1297                 locked = false;
1298
1299         I915_STATE_WARN(panel_pipe == pipe && locked,
1300              "panel assertion failure, pipe %c regs locked\n",
1301              pipe_name(pipe));
1302 }
1303
1304 static void assert_cursor(struct drm_i915_private *dev_priv,
1305                           enum pipe pipe, bool state)
1306 {
1307         struct drm_device *dev = dev_priv->dev;
1308         bool cur_state;
1309
1310         if (IS_845G(dev) || IS_I865G(dev))
1311                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1312         else
1313                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1314
1315         I915_STATE_WARN(cur_state != state,
1316              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1317              pipe_name(pipe), state_string(state), state_string(cur_state));
1318 }
1319 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1320 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1321
1322 void assert_pipe(struct drm_i915_private *dev_priv,
1323                  enum pipe pipe, bool state)
1324 {
1325         int reg;
1326         u32 val;
1327         bool cur_state;
1328         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1329                                                                       pipe);
1330
1331         /* if we need the pipe quirk it must be always on */
1332         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1333             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1334                 state = true;
1335
1336         if (!intel_display_power_is_enabled(dev_priv,
1337                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1338                 cur_state = false;
1339         } else {
1340                 reg = PIPECONF(cpu_transcoder);
1341                 val = I915_READ(reg);
1342                 cur_state = !!(val & PIPECONF_ENABLE);
1343         }
1344
1345         I915_STATE_WARN(cur_state != state,
1346              "pipe %c assertion failure (expected %s, current %s)\n",
1347              pipe_name(pipe), state_string(state), state_string(cur_state));
1348 }
1349
1350 static void assert_plane(struct drm_i915_private *dev_priv,
1351                          enum plane plane, bool state)
1352 {
1353         int reg;
1354         u32 val;
1355         bool cur_state;
1356
1357         reg = DSPCNTR(plane);
1358         val = I915_READ(reg);
1359         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1360         I915_STATE_WARN(cur_state != state,
1361              "plane %c assertion failure (expected %s, current %s)\n",
1362              plane_name(plane), state_string(state), state_string(cur_state));
1363 }
1364
1365 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1366 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1367
1368 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1369                                    enum pipe pipe)
1370 {
1371         struct drm_device *dev = dev_priv->dev;
1372         int reg, i;
1373         u32 val;
1374         int cur_pipe;
1375
1376         /* Primary planes are fixed to pipes on gen4+ */
1377         if (INTEL_INFO(dev)->gen >= 4) {
1378                 reg = DSPCNTR(pipe);
1379                 val = I915_READ(reg);
1380                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1381                      "plane %c assertion failure, should be disabled but not\n",
1382                      plane_name(pipe));
1383                 return;
1384         }
1385
1386         /* Need to check both planes against the pipe */
1387         for_each_pipe(dev_priv, i) {
1388                 reg = DSPCNTR(i);
1389                 val = I915_READ(reg);
1390                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1391                         DISPPLANE_SEL_PIPE_SHIFT;
1392                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1393                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1394                      plane_name(i), pipe_name(pipe));
1395         }
1396 }
1397
1398 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1399                                     enum pipe pipe)
1400 {
1401         struct drm_device *dev = dev_priv->dev;
1402         int reg, sprite;
1403         u32 val;
1404
1405         if (INTEL_INFO(dev)->gen >= 9) {
1406                 for_each_sprite(dev_priv, pipe, sprite) {
1407                         val = I915_READ(PLANE_CTL(pipe, sprite));
1408                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1409                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1410                              sprite, pipe_name(pipe));
1411                 }
1412         } else if (IS_VALLEYVIEW(dev)) {
1413                 for_each_sprite(dev_priv, pipe, sprite) {
1414                         reg = SPCNTR(pipe, sprite);
1415                         val = I915_READ(reg);
1416                         I915_STATE_WARN(val & SP_ENABLE,
1417                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1418                              sprite_name(pipe, sprite), pipe_name(pipe));
1419                 }
1420         } else if (INTEL_INFO(dev)->gen >= 7) {
1421                 reg = SPRCTL(pipe);
1422                 val = I915_READ(reg);
1423                 I915_STATE_WARN(val & SPRITE_ENABLE,
1424                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425                      plane_name(pipe), pipe_name(pipe));
1426         } else if (INTEL_INFO(dev)->gen >= 5) {
1427                 reg = DVSCNTR(pipe);
1428                 val = I915_READ(reg);
1429                 I915_STATE_WARN(val & DVS_ENABLE,
1430                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431                      plane_name(pipe), pipe_name(pipe));
1432         }
1433 }
1434
1435 static void assert_vblank_disabled(struct drm_crtc *crtc)
1436 {
1437         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1438                 drm_crtc_vblank_put(crtc);
1439 }
1440
1441 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1442 {
1443         u32 val;
1444         bool enabled;
1445
1446         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1447
1448         val = I915_READ(PCH_DREF_CONTROL);
1449         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1450                             DREF_SUPERSPREAD_SOURCE_MASK));
1451         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1452 }
1453
1454 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1455                                            enum pipe pipe)
1456 {
1457         int reg;
1458         u32 val;
1459         bool enabled;
1460
1461         reg = PCH_TRANSCONF(pipe);
1462         val = I915_READ(reg);
1463         enabled = !!(val & TRANS_ENABLE);
1464         I915_STATE_WARN(enabled,
1465              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1466              pipe_name(pipe));
1467 }
1468
1469 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1470                             enum pipe pipe, u32 port_sel, u32 val)
1471 {
1472         if ((val & DP_PORT_EN) == 0)
1473                 return false;
1474
1475         if (HAS_PCH_CPT(dev_priv->dev)) {
1476                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1477                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1478                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1479                         return false;
1480         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1481                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1482                         return false;
1483         } else {
1484                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1485                         return false;
1486         }
1487         return true;
1488 }
1489
1490 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1491                               enum pipe pipe, u32 val)
1492 {
1493         if ((val & SDVO_ENABLE) == 0)
1494                 return false;
1495
1496         if (HAS_PCH_CPT(dev_priv->dev)) {
1497                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1498                         return false;
1499         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1500                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1501                         return false;
1502         } else {
1503                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1504                         return false;
1505         }
1506         return true;
1507 }
1508
1509 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1510                               enum pipe pipe, u32 val)
1511 {
1512         if ((val & LVDS_PORT_EN) == 0)
1513                 return false;
1514
1515         if (HAS_PCH_CPT(dev_priv->dev)) {
1516                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1517                         return false;
1518         } else {
1519                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1520                         return false;
1521         }
1522         return true;
1523 }
1524
1525 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1526                               enum pipe pipe, u32 val)
1527 {
1528         if ((val & ADPA_DAC_ENABLE) == 0)
1529                 return false;
1530         if (HAS_PCH_CPT(dev_priv->dev)) {
1531                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1532                         return false;
1533         } else {
1534                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1535                         return false;
1536         }
1537         return true;
1538 }
1539
1540 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1541                                    enum pipe pipe, int reg, u32 port_sel)
1542 {
1543         u32 val = I915_READ(reg);
1544         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1545              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1546              reg, pipe_name(pipe));
1547
1548         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1549              && (val & DP_PIPEB_SELECT),
1550              "IBX PCH dp port still using transcoder B\n");
1551 }
1552
1553 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1554                                      enum pipe pipe, int reg)
1555 {
1556         u32 val = I915_READ(reg);
1557         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1558              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1559              reg, pipe_name(pipe));
1560
1561         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1562              && (val & SDVO_PIPE_B_SELECT),
1563              "IBX PCH hdmi port still using transcoder B\n");
1564 }
1565
1566 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1567                                       enum pipe pipe)
1568 {
1569         int reg;
1570         u32 val;
1571
1572         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1573         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1574         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1575
1576         reg = PCH_ADPA;
1577         val = I915_READ(reg);
1578         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1579              "PCH VGA enabled on transcoder %c, should be disabled\n",
1580              pipe_name(pipe));
1581
1582         reg = PCH_LVDS;
1583         val = I915_READ(reg);
1584         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1585              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1586              pipe_name(pipe));
1587
1588         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1591 }
1592
1593 static void intel_init_dpio(struct drm_device *dev)
1594 {
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597         if (!IS_VALLEYVIEW(dev))
1598                 return;
1599
1600         /*
1601          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1602          * CHV x1 PHY (DP/HDMI D)
1603          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1604          */
1605         if (IS_CHERRYVIEW(dev)) {
1606                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1607                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1608         } else {
1609                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1610         }
1611 }
1612
1613 static void vlv_enable_pll(struct intel_crtc *crtc,
1614                            const struct intel_crtc_state *pipe_config)
1615 {
1616         struct drm_device *dev = crtc->base.dev;
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618         int reg = DPLL(crtc->pipe);
1619         u32 dpll = pipe_config->dpll_hw_state.dpll;
1620
1621         assert_pipe_disabled(dev_priv, crtc->pipe);
1622
1623         /* No really, not for ILK+ */
1624         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1625
1626         /* PLL is protected by panel, make sure we can write it */
1627         if (IS_MOBILE(dev_priv->dev))
1628                 assert_panel_unlocked(dev_priv, crtc->pipe);
1629
1630         I915_WRITE(reg, dpll);
1631         POSTING_READ(reg);
1632         udelay(150);
1633
1634         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1636
1637         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1638         POSTING_READ(DPLL_MD(crtc->pipe));
1639
1640         /* We do this three times for luck */
1641         I915_WRITE(reg, dpll);
1642         POSTING_READ(reg);
1643         udelay(150); /* wait for warmup */
1644         I915_WRITE(reg, dpll);
1645         POSTING_READ(reg);
1646         udelay(150); /* wait for warmup */
1647         I915_WRITE(reg, dpll);
1648         POSTING_READ(reg);
1649         udelay(150); /* wait for warmup */
1650 }
1651
1652 static void chv_enable_pll(struct intel_crtc *crtc,
1653                            const struct intel_crtc_state *pipe_config)
1654 {
1655         struct drm_device *dev = crtc->base.dev;
1656         struct drm_i915_private *dev_priv = dev->dev_private;
1657         int pipe = crtc->pipe;
1658         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1659         u32 tmp;
1660
1661         assert_pipe_disabled(dev_priv, crtc->pipe);
1662
1663         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1664
1665         mutex_lock(&dev_priv->sb_lock);
1666
1667         /* Enable back the 10bit clock to display controller */
1668         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1669         tmp |= DPIO_DCLKP_EN;
1670         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1671
1672         mutex_unlock(&dev_priv->sb_lock);
1673
1674         /*
1675          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1676          */
1677         udelay(1);
1678
1679         /* Enable PLL */
1680         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1681
1682         /* Check PLL is locked */
1683         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1684                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1685
1686         /* not sure when this should be written */
1687         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1688         POSTING_READ(DPLL_MD(pipe));
1689 }
1690
1691 static int intel_num_dvo_pipes(struct drm_device *dev)
1692 {
1693         struct intel_crtc *crtc;
1694         int count = 0;
1695
1696         for_each_intel_crtc(dev, crtc)
1697                 count += crtc->base.state->active &&
1698                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1699
1700         return count;
1701 }
1702
1703 static void i9xx_enable_pll(struct intel_crtc *crtc)
1704 {
1705         struct drm_device *dev = crtc->base.dev;
1706         struct drm_i915_private *dev_priv = dev->dev_private;
1707         int reg = DPLL(crtc->pipe);
1708         u32 dpll = crtc->config->dpll_hw_state.dpll;
1709
1710         assert_pipe_disabled(dev_priv, crtc->pipe);
1711
1712         /* No really, not for ILK+ */
1713         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1714
1715         /* PLL is protected by panel, make sure we can write it */
1716         if (IS_MOBILE(dev) && !IS_I830(dev))
1717                 assert_panel_unlocked(dev_priv, crtc->pipe);
1718
1719         /* Enable DVO 2x clock on both PLLs if necessary */
1720         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1721                 /*
1722                  * It appears to be important that we don't enable this
1723                  * for the current pipe before otherwise configuring the
1724                  * PLL. No idea how this should be handled if multiple
1725                  * DVO outputs are enabled simultaneosly.
1726                  */
1727                 dpll |= DPLL_DVO_2X_MODE;
1728                 I915_WRITE(DPLL(!crtc->pipe),
1729                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1730         }
1731
1732         /* Wait for the clocks to stabilize. */
1733         POSTING_READ(reg);
1734         udelay(150);
1735
1736         if (INTEL_INFO(dev)->gen >= 4) {
1737                 I915_WRITE(DPLL_MD(crtc->pipe),
1738                            crtc->config->dpll_hw_state.dpll_md);
1739         } else {
1740                 /* The pixel multiplier can only be updated once the
1741                  * DPLL is enabled and the clocks are stable.
1742                  *
1743                  * So write it again.
1744                  */
1745                 I915_WRITE(reg, dpll);
1746         }
1747
1748         /* We do this three times for luck */
1749         I915_WRITE(reg, dpll);
1750         POSTING_READ(reg);
1751         udelay(150); /* wait for warmup */
1752         I915_WRITE(reg, dpll);
1753         POSTING_READ(reg);
1754         udelay(150); /* wait for warmup */
1755         I915_WRITE(reg, dpll);
1756         POSTING_READ(reg);
1757         udelay(150); /* wait for warmup */
1758 }
1759
1760 /**
1761  * i9xx_disable_pll - disable a PLL
1762  * @dev_priv: i915 private structure
1763  * @pipe: pipe PLL to disable
1764  *
1765  * Disable the PLL for @pipe, making sure the pipe is off first.
1766  *
1767  * Note!  This is for pre-ILK only.
1768  */
1769 static void i9xx_disable_pll(struct intel_crtc *crtc)
1770 {
1771         struct drm_device *dev = crtc->base.dev;
1772         struct drm_i915_private *dev_priv = dev->dev_private;
1773         enum pipe pipe = crtc->pipe;
1774
1775         /* Disable DVO 2x clock on both PLLs if necessary */
1776         if (IS_I830(dev) &&
1777             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1778             !intel_num_dvo_pipes(dev)) {
1779                 I915_WRITE(DPLL(PIPE_B),
1780                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1781                 I915_WRITE(DPLL(PIPE_A),
1782                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1783         }
1784
1785         /* Don't disable pipe or pipe PLLs if needed */
1786         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1787             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1788                 return;
1789
1790         /* Make sure the pipe isn't still relying on us */
1791         assert_pipe_disabled(dev_priv, pipe);
1792
1793         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1794         POSTING_READ(DPLL(pipe));
1795 }
1796
1797 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1798 {
1799         u32 val;
1800
1801         /* Make sure the pipe isn't still relying on us */
1802         assert_pipe_disabled(dev_priv, pipe);
1803
1804         /*
1805          * Leave integrated clock source and reference clock enabled for pipe B.
1806          * The latter is needed for VGA hotplug / manual detection.
1807          */
1808         val = DPLL_VGA_MODE_DIS;
1809         if (pipe == PIPE_B)
1810                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1811         I915_WRITE(DPLL(pipe), val);
1812         POSTING_READ(DPLL(pipe));
1813
1814 }
1815
1816 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1817 {
1818         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1819         u32 val;
1820
1821         /* Make sure the pipe isn't still relying on us */
1822         assert_pipe_disabled(dev_priv, pipe);
1823
1824         /* Set PLL en = 0 */
1825         val = DPLL_SSC_REF_CLK_CHV |
1826                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1827         if (pipe != PIPE_A)
1828                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1829         I915_WRITE(DPLL(pipe), val);
1830         POSTING_READ(DPLL(pipe));
1831
1832         mutex_lock(&dev_priv->sb_lock);
1833
1834         /* Disable 10bit clock to display controller */
1835         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1836         val &= ~DPIO_DCLKP_EN;
1837         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1838
1839         /* disable left/right clock distribution */
1840         if (pipe != PIPE_B) {
1841                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1842                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1843                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1844         } else {
1845                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1846                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1847                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1848         }
1849
1850         mutex_unlock(&dev_priv->sb_lock);
1851 }
1852
1853 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1854                          struct intel_digital_port *dport,
1855                          unsigned int expected_mask)
1856 {
1857         u32 port_mask;
1858         int dpll_reg;
1859
1860         switch (dport->port) {
1861         case PORT_B:
1862                 port_mask = DPLL_PORTB_READY_MASK;
1863                 dpll_reg = DPLL(0);
1864                 break;
1865         case PORT_C:
1866                 port_mask = DPLL_PORTC_READY_MASK;
1867                 dpll_reg = DPLL(0);
1868                 expected_mask <<= 4;
1869                 break;
1870         case PORT_D:
1871                 port_mask = DPLL_PORTD_READY_MASK;
1872                 dpll_reg = DPIO_PHY_STATUS;
1873                 break;
1874         default:
1875                 BUG();
1876         }
1877
1878         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1879                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1880                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1881 }
1882
1883 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1884 {
1885         struct drm_device *dev = crtc->base.dev;
1886         struct drm_i915_private *dev_priv = dev->dev_private;
1887         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
1889         if (WARN_ON(pll == NULL))
1890                 return;
1891
1892         WARN_ON(!pll->config.crtc_mask);
1893         if (pll->active == 0) {
1894                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1895                 WARN_ON(pll->on);
1896                 assert_shared_dpll_disabled(dev_priv, pll);
1897
1898                 pll->mode_set(dev_priv, pll);
1899         }
1900 }
1901
1902 /**
1903  * intel_enable_shared_dpll - enable PCH PLL
1904  * @dev_priv: i915 private structure
1905  * @pipe: pipe PLL to enable
1906  *
1907  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1908  * drives the transcoder clock.
1909  */
1910 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1911 {
1912         struct drm_device *dev = crtc->base.dev;
1913         struct drm_i915_private *dev_priv = dev->dev_private;
1914         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1915
1916         if (WARN_ON(pll == NULL))
1917                 return;
1918
1919         if (WARN_ON(pll->config.crtc_mask == 0))
1920                 return;
1921
1922         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1923                       pll->name, pll->active, pll->on,
1924                       crtc->base.base.id);
1925
1926         if (pll->active++) {
1927                 WARN_ON(!pll->on);
1928                 assert_shared_dpll_enabled(dev_priv, pll);
1929                 return;
1930         }
1931         WARN_ON(pll->on);
1932
1933         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1934
1935         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1936         pll->enable(dev_priv, pll);
1937         pll->on = true;
1938 }
1939
1940 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1941 {
1942         struct drm_device *dev = crtc->base.dev;
1943         struct drm_i915_private *dev_priv = dev->dev_private;
1944         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1945
1946         /* PCH only available on ILK+ */
1947         BUG_ON(INTEL_INFO(dev)->gen < 5);
1948         if (pll == NULL)
1949                 return;
1950
1951         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1952                 return;
1953
1954         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1955                       pll->name, pll->active, pll->on,
1956                       crtc->base.base.id);
1957
1958         if (WARN_ON(pll->active == 0)) {
1959                 assert_shared_dpll_disabled(dev_priv, pll);
1960                 return;
1961         }
1962
1963         assert_shared_dpll_enabled(dev_priv, pll);
1964         WARN_ON(!pll->on);
1965         if (--pll->active)
1966                 return;
1967
1968         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1969         pll->disable(dev_priv, pll);
1970         pll->on = false;
1971
1972         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1973 }
1974
1975 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1976                                            enum pipe pipe)
1977 {
1978         struct drm_device *dev = dev_priv->dev;
1979         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1981         uint32_t reg, val, pipeconf_val;
1982
1983         /* PCH only available on ILK+ */
1984         BUG_ON(!HAS_PCH_SPLIT(dev));
1985
1986         /* Make sure PCH DPLL is enabled */
1987         assert_shared_dpll_enabled(dev_priv,
1988                                    intel_crtc_to_shared_dpll(intel_crtc));
1989
1990         /* FDI must be feeding us bits for PCH ports */
1991         assert_fdi_tx_enabled(dev_priv, pipe);
1992         assert_fdi_rx_enabled(dev_priv, pipe);
1993
1994         if (HAS_PCH_CPT(dev)) {
1995                 /* Workaround: Set the timing override bit before enabling the
1996                  * pch transcoder. */
1997                 reg = TRANS_CHICKEN2(pipe);
1998                 val = I915_READ(reg);
1999                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2000                 I915_WRITE(reg, val);
2001         }
2002
2003         reg = PCH_TRANSCONF(pipe);
2004         val = I915_READ(reg);
2005         pipeconf_val = I915_READ(PIPECONF(pipe));
2006
2007         if (HAS_PCH_IBX(dev_priv->dev)) {
2008                 /*
2009                  * Make the BPC in transcoder be consistent with
2010                  * that in pipeconf reg. For HDMI we must use 8bpc
2011                  * here for both 8bpc and 12bpc.
2012                  */
2013                 val &= ~PIPECONF_BPC_MASK;
2014                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2015                         val |= PIPECONF_8BPC;
2016                 else
2017                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2018         }
2019
2020         val &= ~TRANS_INTERLACE_MASK;
2021         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2022                 if (HAS_PCH_IBX(dev_priv->dev) &&
2023                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2024                         val |= TRANS_LEGACY_INTERLACED_ILK;
2025                 else
2026                         val |= TRANS_INTERLACED;
2027         else
2028                 val |= TRANS_PROGRESSIVE;
2029
2030         I915_WRITE(reg, val | TRANS_ENABLE);
2031         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2032                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2033 }
2034
2035 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2036                                       enum transcoder cpu_transcoder)
2037 {
2038         u32 val, pipeconf_val;
2039
2040         /* PCH only available on ILK+ */
2041         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2042
2043         /* FDI must be feeding us bits for PCH ports */
2044         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2045         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2046
2047         /* Workaround: set timing override bit. */
2048         val = I915_READ(_TRANSA_CHICKEN2);
2049         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2050         I915_WRITE(_TRANSA_CHICKEN2, val);
2051
2052         val = TRANS_ENABLE;
2053         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2054
2055         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2056             PIPECONF_INTERLACED_ILK)
2057                 val |= TRANS_INTERLACED;
2058         else
2059                 val |= TRANS_PROGRESSIVE;
2060
2061         I915_WRITE(LPT_TRANSCONF, val);
2062         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2063                 DRM_ERROR("Failed to enable PCH transcoder\n");
2064 }
2065
2066 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2067                                             enum pipe pipe)
2068 {
2069         struct drm_device *dev = dev_priv->dev;
2070         uint32_t reg, val;
2071
2072         /* FDI relies on the transcoder */
2073         assert_fdi_tx_disabled(dev_priv, pipe);
2074         assert_fdi_rx_disabled(dev_priv, pipe);
2075
2076         /* Ports must be off as well */
2077         assert_pch_ports_disabled(dev_priv, pipe);
2078
2079         reg = PCH_TRANSCONF(pipe);
2080         val = I915_READ(reg);
2081         val &= ~TRANS_ENABLE;
2082         I915_WRITE(reg, val);
2083         /* wait for PCH transcoder off, transcoder state */
2084         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2085                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2086
2087         if (!HAS_PCH_IBX(dev)) {
2088                 /* Workaround: Clear the timing override chicken bit again. */
2089                 reg = TRANS_CHICKEN2(pipe);
2090                 val = I915_READ(reg);
2091                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2092                 I915_WRITE(reg, val);
2093         }
2094 }
2095
2096 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2097 {
2098         u32 val;
2099
2100         val = I915_READ(LPT_TRANSCONF);
2101         val &= ~TRANS_ENABLE;
2102         I915_WRITE(LPT_TRANSCONF, val);
2103         /* wait for PCH transcoder off, transcoder state */
2104         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2105                 DRM_ERROR("Failed to disable PCH transcoder\n");
2106
2107         /* Workaround: clear timing override bit. */
2108         val = I915_READ(_TRANSA_CHICKEN2);
2109         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2110         I915_WRITE(_TRANSA_CHICKEN2, val);
2111 }
2112
2113 /**
2114  * intel_enable_pipe - enable a pipe, asserting requirements
2115  * @crtc: crtc responsible for the pipe
2116  *
2117  * Enable @crtc's pipe, making sure that various hardware specific requirements
2118  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2119  */
2120 static void intel_enable_pipe(struct intel_crtc *crtc)
2121 {
2122         struct drm_device *dev = crtc->base.dev;
2123         struct drm_i915_private *dev_priv = dev->dev_private;
2124         enum pipe pipe = crtc->pipe;
2125         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2126                                                                       pipe);
2127         enum pipe pch_transcoder;
2128         int reg;
2129         u32 val;
2130
2131         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2132
2133         assert_planes_disabled(dev_priv, pipe);
2134         assert_cursor_disabled(dev_priv, pipe);
2135         assert_sprites_disabled(dev_priv, pipe);
2136
2137         if (HAS_PCH_LPT(dev_priv->dev))
2138                 pch_transcoder = TRANSCODER_A;
2139         else
2140                 pch_transcoder = pipe;
2141
2142         /*
2143          * A pipe without a PLL won't actually be able to drive bits from
2144          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2145          * need the check.
2146          */
2147         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2148                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2149                         assert_dsi_pll_enabled(dev_priv);
2150                 else
2151                         assert_pll_enabled(dev_priv, pipe);
2152         else {
2153                 if (crtc->config->has_pch_encoder) {
2154                         /* if driving the PCH, we need FDI enabled */
2155                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2156                         assert_fdi_tx_pll_enabled(dev_priv,
2157                                                   (enum pipe) cpu_transcoder);
2158                 }
2159                 /* FIXME: assert CPU port conditions for SNB+ */
2160         }
2161
2162         reg = PIPECONF(cpu_transcoder);
2163         val = I915_READ(reg);
2164         if (val & PIPECONF_ENABLE) {
2165                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2166                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2167                 return;
2168         }
2169
2170         I915_WRITE(reg, val | PIPECONF_ENABLE);
2171         POSTING_READ(reg);
2172 }
2173
2174 /**
2175  * intel_disable_pipe - disable a pipe, asserting requirements
2176  * @crtc: crtc whose pipes is to be disabled
2177  *
2178  * Disable the pipe of @crtc, making sure that various hardware
2179  * specific requirements are met, if applicable, e.g. plane
2180  * disabled, panel fitter off, etc.
2181  *
2182  * Will wait until the pipe has shut down before returning.
2183  */
2184 static void intel_disable_pipe(struct intel_crtc *crtc)
2185 {
2186         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2187         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2188         enum pipe pipe = crtc->pipe;
2189         int reg;
2190         u32 val;
2191
2192         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2193
2194         /*
2195          * Make sure planes won't keep trying to pump pixels to us,
2196          * or we might hang the display.
2197          */
2198         assert_planes_disabled(dev_priv, pipe);
2199         assert_cursor_disabled(dev_priv, pipe);
2200         assert_sprites_disabled(dev_priv, pipe);
2201
2202         reg = PIPECONF(cpu_transcoder);
2203         val = I915_READ(reg);
2204         if ((val & PIPECONF_ENABLE) == 0)
2205                 return;
2206
2207         /*
2208          * Double wide has implications for planes
2209          * so best keep it disabled when not needed.
2210          */
2211         if (crtc->config->double_wide)
2212                 val &= ~PIPECONF_DOUBLE_WIDE;
2213
2214         /* Don't disable pipe or pipe PLLs if needed */
2215         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2216             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2217                 val &= ~PIPECONF_ENABLE;
2218
2219         I915_WRITE(reg, val);
2220         if ((val & PIPECONF_ENABLE) == 0)
2221                 intel_wait_for_pipe_off(crtc);
2222 }
2223
2224 static bool need_vtd_wa(struct drm_device *dev)
2225 {
2226 #ifdef CONFIG_INTEL_IOMMU
2227         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2228                 return true;
2229 #endif
2230         return false;
2231 }
2232
2233 unsigned int
2234 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2235                   uint64_t fb_format_modifier)
2236 {
2237         unsigned int tile_height;
2238         uint32_t pixel_bytes;
2239
2240         switch (fb_format_modifier) {
2241         case DRM_FORMAT_MOD_NONE:
2242                 tile_height = 1;
2243                 break;
2244         case I915_FORMAT_MOD_X_TILED:
2245                 tile_height = IS_GEN2(dev) ? 16 : 8;
2246                 break;
2247         case I915_FORMAT_MOD_Y_TILED:
2248                 tile_height = 32;
2249                 break;
2250         case I915_FORMAT_MOD_Yf_TILED:
2251                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2252                 switch (pixel_bytes) {
2253                 default:
2254                 case 1:
2255                         tile_height = 64;
2256                         break;
2257                 case 2:
2258                 case 4:
2259                         tile_height = 32;
2260                         break;
2261                 case 8:
2262                         tile_height = 16;
2263                         break;
2264                 case 16:
2265                         WARN_ONCE(1,
2266                                   "128-bit pixels are not supported for display!");
2267                         tile_height = 16;
2268                         break;
2269                 }
2270                 break;
2271         default:
2272                 MISSING_CASE(fb_format_modifier);
2273                 tile_height = 1;
2274                 break;
2275         }
2276
2277         return tile_height;
2278 }
2279
2280 unsigned int
2281 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2282                       uint32_t pixel_format, uint64_t fb_format_modifier)
2283 {
2284         return ALIGN(height, intel_tile_height(dev, pixel_format,
2285                                                fb_format_modifier));
2286 }
2287
2288 static int
2289 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2290                         const struct drm_plane_state *plane_state)
2291 {
2292         struct intel_rotation_info *info = &view->rotation_info;
2293         unsigned int tile_height, tile_pitch;
2294
2295         *view = i915_ggtt_view_normal;
2296
2297         if (!plane_state)
2298                 return 0;
2299
2300         if (!intel_rotation_90_or_270(plane_state->rotation))
2301                 return 0;
2302
2303         *view = i915_ggtt_view_rotated;
2304
2305         info->height = fb->height;
2306         info->pixel_format = fb->pixel_format;
2307         info->pitch = fb->pitches[0];
2308         info->fb_modifier = fb->modifier[0];
2309
2310         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2311                                         fb->modifier[0]);
2312         tile_pitch = PAGE_SIZE / tile_height;
2313         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2314         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2315         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2316
2317         return 0;
2318 }
2319
2320 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2321 {
2322         if (INTEL_INFO(dev_priv)->gen >= 9)
2323                 return 256 * 1024;
2324         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2325                  IS_VALLEYVIEW(dev_priv))
2326                 return 128 * 1024;
2327         else if (INTEL_INFO(dev_priv)->gen >= 4)
2328                 return 4 * 1024;
2329         else
2330                 return 0;
2331 }
2332
2333 int
2334 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2335                            struct drm_framebuffer *fb,
2336                            const struct drm_plane_state *plane_state,
2337                            struct intel_engine_cs *pipelined,
2338                            struct drm_i915_gem_request **pipelined_request)
2339 {
2340         struct drm_device *dev = fb->dev;
2341         struct drm_i915_private *dev_priv = dev->dev_private;
2342         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2343         struct i915_ggtt_view view;
2344         u32 alignment;
2345         int ret;
2346
2347         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2348
2349         switch (fb->modifier[0]) {
2350         case DRM_FORMAT_MOD_NONE:
2351                 alignment = intel_linear_alignment(dev_priv);
2352                 break;
2353         case I915_FORMAT_MOD_X_TILED:
2354                 if (INTEL_INFO(dev)->gen >= 9)
2355                         alignment = 256 * 1024;
2356                 else {
2357                         /* pin() will align the object as required by fence */
2358                         alignment = 0;
2359                 }
2360                 break;
2361         case I915_FORMAT_MOD_Y_TILED:
2362         case I915_FORMAT_MOD_Yf_TILED:
2363                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2364                           "Y tiling bo slipped through, driver bug!\n"))
2365                         return -EINVAL;
2366                 alignment = 1 * 1024 * 1024;
2367                 break;
2368         default:
2369                 MISSING_CASE(fb->modifier[0]);
2370                 return -EINVAL;
2371         }
2372
2373         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2374         if (ret)
2375                 return ret;
2376
2377         /* Note that the w/a also requires 64 PTE of padding following the
2378          * bo. We currently fill all unused PTE with the shadow page and so
2379          * we should always have valid PTE following the scanout preventing
2380          * the VT-d warning.
2381          */
2382         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2383                 alignment = 256 * 1024;
2384
2385         /*
2386          * Global gtt pte registers are special registers which actually forward
2387          * writes to a chunk of system memory. Which means that there is no risk
2388          * that the register values disappear as soon as we call
2389          * intel_runtime_pm_put(), so it is correct to wrap only the
2390          * pin/unpin/fence and not more.
2391          */
2392         intel_runtime_pm_get(dev_priv);
2393
2394         dev_priv->mm.interruptible = false;
2395         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2396                                                    pipelined_request, &view);
2397         if (ret)
2398                 goto err_interruptible;
2399
2400         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2401          * fence, whereas 965+ only requires a fence if using
2402          * framebuffer compression.  For simplicity, we always install
2403          * a fence as the cost is not that onerous.
2404          */
2405         ret = i915_gem_object_get_fence(obj);
2406         if (ret)
2407                 goto err_unpin;
2408
2409         i915_gem_object_pin_fence(obj);
2410
2411         dev_priv->mm.interruptible = true;
2412         intel_runtime_pm_put(dev_priv);
2413         return 0;
2414
2415 err_unpin:
2416         i915_gem_object_unpin_from_display_plane(obj, &view);
2417 err_interruptible:
2418         dev_priv->mm.interruptible = true;
2419         intel_runtime_pm_put(dev_priv);
2420         return ret;
2421 }
2422
2423 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2424                                const struct drm_plane_state *plane_state)
2425 {
2426         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2427         struct i915_ggtt_view view;
2428         int ret;
2429
2430         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2431
2432         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2433         WARN_ONCE(ret, "Couldn't get view from plane state!");
2434
2435         i915_gem_object_unpin_fence(obj);
2436         i915_gem_object_unpin_from_display_plane(obj, &view);
2437 }
2438
2439 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2440  * is assumed to be a power-of-two. */
2441 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2442                                              int *x, int *y,
2443                                              unsigned int tiling_mode,
2444                                              unsigned int cpp,
2445                                              unsigned int pitch)
2446 {
2447         if (tiling_mode != I915_TILING_NONE) {
2448                 unsigned int tile_rows, tiles;
2449
2450                 tile_rows = *y / 8;
2451                 *y %= 8;
2452
2453                 tiles = *x / (512/cpp);
2454                 *x %= 512/cpp;
2455
2456                 return tile_rows * pitch * 8 + tiles * 4096;
2457         } else {
2458                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2459                 unsigned int offset;
2460
2461                 offset = *y * pitch + *x * cpp;
2462                 *y = (offset & alignment) / pitch;
2463                 *x = ((offset & alignment) - *y * pitch) / cpp;
2464                 return offset & ~alignment;
2465         }
2466 }
2467
2468 static int i9xx_format_to_fourcc(int format)
2469 {
2470         switch (format) {
2471         case DISPPLANE_8BPP:
2472                 return DRM_FORMAT_C8;
2473         case DISPPLANE_BGRX555:
2474                 return DRM_FORMAT_XRGB1555;
2475         case DISPPLANE_BGRX565:
2476                 return DRM_FORMAT_RGB565;
2477         default:
2478         case DISPPLANE_BGRX888:
2479                 return DRM_FORMAT_XRGB8888;
2480         case DISPPLANE_RGBX888:
2481                 return DRM_FORMAT_XBGR8888;
2482         case DISPPLANE_BGRX101010:
2483                 return DRM_FORMAT_XRGB2101010;
2484         case DISPPLANE_RGBX101010:
2485                 return DRM_FORMAT_XBGR2101010;
2486         }
2487 }
2488
2489 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2490 {
2491         switch (format) {
2492         case PLANE_CTL_FORMAT_RGB_565:
2493                 return DRM_FORMAT_RGB565;
2494         default:
2495         case PLANE_CTL_FORMAT_XRGB_8888:
2496                 if (rgb_order) {
2497                         if (alpha)
2498                                 return DRM_FORMAT_ABGR8888;
2499                         else
2500                                 return DRM_FORMAT_XBGR8888;
2501                 } else {
2502                         if (alpha)
2503                                 return DRM_FORMAT_ARGB8888;
2504                         else
2505                                 return DRM_FORMAT_XRGB8888;
2506                 }
2507         case PLANE_CTL_FORMAT_XRGB_2101010:
2508                 if (rgb_order)
2509                         return DRM_FORMAT_XBGR2101010;
2510                 else
2511                         return DRM_FORMAT_XRGB2101010;
2512         }
2513 }
2514
2515 static bool
2516 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2517                               struct intel_initial_plane_config *plane_config)
2518 {
2519         struct drm_device *dev = crtc->base.dev;
2520         struct drm_i915_gem_object *obj = NULL;
2521         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2522         struct drm_framebuffer *fb = &plane_config->fb->base;
2523         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2524         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2525                                     PAGE_SIZE);
2526
2527         size_aligned -= base_aligned;
2528
2529         if (plane_config->size == 0)
2530                 return false;
2531
2532         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2533                                                              base_aligned,
2534                                                              base_aligned,
2535                                                              size_aligned);
2536         if (!obj)
2537                 return false;
2538
2539         obj->tiling_mode = plane_config->tiling;
2540         if (obj->tiling_mode == I915_TILING_X)
2541                 obj->stride = fb->pitches[0];
2542
2543         mode_cmd.pixel_format = fb->pixel_format;
2544         mode_cmd.width = fb->width;
2545         mode_cmd.height = fb->height;
2546         mode_cmd.pitches[0] = fb->pitches[0];
2547         mode_cmd.modifier[0] = fb->modifier[0];
2548         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2549
2550         mutex_lock(&dev->struct_mutex);
2551         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2552                                    &mode_cmd, obj)) {
2553                 DRM_DEBUG_KMS("intel fb init failed\n");
2554                 goto out_unref_obj;
2555         }
2556         mutex_unlock(&dev->struct_mutex);
2557
2558         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2559         return true;
2560
2561 out_unref_obj:
2562         drm_gem_object_unreference(&obj->base);
2563         mutex_unlock(&dev->struct_mutex);
2564         return false;
2565 }
2566
2567 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2568 static void
2569 update_state_fb(struct drm_plane *plane)
2570 {
2571         if (plane->fb == plane->state->fb)
2572                 return;
2573
2574         if (plane->state->fb)
2575                 drm_framebuffer_unreference(plane->state->fb);
2576         plane->state->fb = plane->fb;
2577         if (plane->state->fb)
2578                 drm_framebuffer_reference(plane->state->fb);
2579 }
2580
2581 static void
2582 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2583                              struct intel_initial_plane_config *plane_config)
2584 {
2585         struct drm_device *dev = intel_crtc->base.dev;
2586         struct drm_i915_private *dev_priv = dev->dev_private;
2587         struct drm_crtc *c;
2588         struct intel_crtc *i;
2589         struct drm_i915_gem_object *obj;
2590         struct drm_plane *primary = intel_crtc->base.primary;
2591         struct drm_framebuffer *fb;
2592
2593         if (!plane_config->fb)
2594                 return;
2595
2596         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2597                 fb = &plane_config->fb->base;
2598                 goto valid_fb;
2599         }
2600
2601         kfree(plane_config->fb);
2602
2603         /*
2604          * Failed to alloc the obj, check to see if we should share
2605          * an fb with another CRTC instead
2606          */
2607         for_each_crtc(dev, c) {
2608                 i = to_intel_crtc(c);
2609
2610                 if (c == &intel_crtc->base)
2611                         continue;
2612
2613                 if (!i->active)
2614                         continue;
2615
2616                 fb = c->primary->fb;
2617                 if (!fb)
2618                         continue;
2619
2620                 obj = intel_fb_obj(fb);
2621                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2622                         drm_framebuffer_reference(fb);
2623                         goto valid_fb;
2624                 }
2625         }
2626
2627         return;
2628
2629 valid_fb:
2630         obj = intel_fb_obj(fb);
2631         if (obj->tiling_mode != I915_TILING_NONE)
2632                 dev_priv->preserve_bios_swizzle = true;
2633
2634         primary->fb = fb;
2635         primary->crtc = primary->state->crtc = &intel_crtc->base;
2636         update_state_fb(primary);
2637         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2638         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2639 }
2640
2641 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2642                                       struct drm_framebuffer *fb,
2643                                       int x, int y)
2644 {
2645         struct drm_device *dev = crtc->dev;
2646         struct drm_i915_private *dev_priv = dev->dev_private;
2647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2648         struct drm_plane *primary = crtc->primary;
2649         bool visible = to_intel_plane_state(primary->state)->visible;
2650         struct drm_i915_gem_object *obj;
2651         int plane = intel_crtc->plane;
2652         unsigned long linear_offset;
2653         u32 dspcntr;
2654         u32 reg = DSPCNTR(plane);
2655         int pixel_size;
2656
2657         if (!visible || !fb) {
2658                 I915_WRITE(reg, 0);
2659                 if (INTEL_INFO(dev)->gen >= 4)
2660                         I915_WRITE(DSPSURF(plane), 0);
2661                 else
2662                         I915_WRITE(DSPADDR(plane), 0);
2663                 POSTING_READ(reg);
2664                 return;
2665         }
2666
2667         obj = intel_fb_obj(fb);
2668         if (WARN_ON(obj == NULL))
2669                 return;
2670
2671         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2672
2673         dspcntr = DISPPLANE_GAMMA_ENABLE;
2674
2675         dspcntr |= DISPLAY_PLANE_ENABLE;
2676
2677         if (INTEL_INFO(dev)->gen < 4) {
2678                 if (intel_crtc->pipe == PIPE_B)
2679                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2680
2681                 /* pipesrc and dspsize control the size that is scaled from,
2682                  * which should always be the user's requested size.
2683                  */
2684                 I915_WRITE(DSPSIZE(plane),
2685                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2686                            (intel_crtc->config->pipe_src_w - 1));
2687                 I915_WRITE(DSPPOS(plane), 0);
2688         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2689                 I915_WRITE(PRIMSIZE(plane),
2690                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2691                            (intel_crtc->config->pipe_src_w - 1));
2692                 I915_WRITE(PRIMPOS(plane), 0);
2693                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2694         }
2695
2696         switch (fb->pixel_format) {
2697         case DRM_FORMAT_C8:
2698                 dspcntr |= DISPPLANE_8BPP;
2699                 break;
2700         case DRM_FORMAT_XRGB1555:
2701                 dspcntr |= DISPPLANE_BGRX555;
2702                 break;
2703         case DRM_FORMAT_RGB565:
2704                 dspcntr |= DISPPLANE_BGRX565;
2705                 break;
2706         case DRM_FORMAT_XRGB8888:
2707                 dspcntr |= DISPPLANE_BGRX888;
2708                 break;
2709         case DRM_FORMAT_XBGR8888:
2710                 dspcntr |= DISPPLANE_RGBX888;
2711                 break;
2712         case DRM_FORMAT_XRGB2101010:
2713                 dspcntr |= DISPPLANE_BGRX101010;
2714                 break;
2715         case DRM_FORMAT_XBGR2101010:
2716                 dspcntr |= DISPPLANE_RGBX101010;
2717                 break;
2718         default:
2719                 BUG();
2720         }
2721
2722         if (INTEL_INFO(dev)->gen >= 4 &&
2723             obj->tiling_mode != I915_TILING_NONE)
2724                 dspcntr |= DISPPLANE_TILED;
2725
2726         if (IS_G4X(dev))
2727                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2728
2729         linear_offset = y * fb->pitches[0] + x * pixel_size;
2730
2731         if (INTEL_INFO(dev)->gen >= 4) {
2732                 intel_crtc->dspaddr_offset =
2733                         intel_gen4_compute_page_offset(dev_priv,
2734                                                        &x, &y, obj->tiling_mode,
2735                                                        pixel_size,
2736                                                        fb->pitches[0]);
2737                 linear_offset -= intel_crtc->dspaddr_offset;
2738         } else {
2739                 intel_crtc->dspaddr_offset = linear_offset;
2740         }
2741
2742         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2743                 dspcntr |= DISPPLANE_ROTATE_180;
2744
2745                 x += (intel_crtc->config->pipe_src_w - 1);
2746                 y += (intel_crtc->config->pipe_src_h - 1);
2747
2748                 /* Finding the last pixel of the last line of the display
2749                 data and adding to linear_offset*/
2750                 linear_offset +=
2751                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2752                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2753         }
2754
2755         I915_WRITE(reg, dspcntr);
2756
2757         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2758         if (INTEL_INFO(dev)->gen >= 4) {
2759                 I915_WRITE(DSPSURF(plane),
2760                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2761                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2762                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2763         } else
2764                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2765         POSTING_READ(reg);
2766 }
2767
2768 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2769                                           struct drm_framebuffer *fb,
2770                                           int x, int y)
2771 {
2772         struct drm_device *dev = crtc->dev;
2773         struct drm_i915_private *dev_priv = dev->dev_private;
2774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2775         struct drm_plane *primary = crtc->primary;
2776         bool visible = to_intel_plane_state(primary->state)->visible;
2777         struct drm_i915_gem_object *obj;
2778         int plane = intel_crtc->plane;
2779         unsigned long linear_offset;
2780         u32 dspcntr;
2781         u32 reg = DSPCNTR(plane);
2782         int pixel_size;
2783
2784         if (!visible || !fb) {
2785                 I915_WRITE(reg, 0);
2786                 I915_WRITE(DSPSURF(plane), 0);
2787                 POSTING_READ(reg);
2788                 return;
2789         }
2790
2791         obj = intel_fb_obj(fb);
2792         if (WARN_ON(obj == NULL))
2793                 return;
2794
2795         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2796
2797         dspcntr = DISPPLANE_GAMMA_ENABLE;
2798
2799         dspcntr |= DISPLAY_PLANE_ENABLE;
2800
2801         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2802                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2803
2804         switch (fb->pixel_format) {
2805         case DRM_FORMAT_C8:
2806                 dspcntr |= DISPPLANE_8BPP;
2807                 break;
2808         case DRM_FORMAT_RGB565:
2809                 dspcntr |= DISPPLANE_BGRX565;
2810                 break;
2811         case DRM_FORMAT_XRGB8888:
2812                 dspcntr |= DISPPLANE_BGRX888;
2813                 break;
2814         case DRM_FORMAT_XBGR8888:
2815                 dspcntr |= DISPPLANE_RGBX888;
2816                 break;
2817         case DRM_FORMAT_XRGB2101010:
2818                 dspcntr |= DISPPLANE_BGRX101010;
2819                 break;
2820         case DRM_FORMAT_XBGR2101010:
2821                 dspcntr |= DISPPLANE_RGBX101010;
2822                 break;
2823         default:
2824                 BUG();
2825         }
2826
2827         if (obj->tiling_mode != I915_TILING_NONE)
2828                 dspcntr |= DISPPLANE_TILED;
2829
2830         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2831                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2832
2833         linear_offset = y * fb->pitches[0] + x * pixel_size;
2834         intel_crtc->dspaddr_offset =
2835                 intel_gen4_compute_page_offset(dev_priv,
2836                                                &x, &y, obj->tiling_mode,
2837                                                pixel_size,
2838                                                fb->pitches[0]);
2839         linear_offset -= intel_crtc->dspaddr_offset;
2840         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2841                 dspcntr |= DISPPLANE_ROTATE_180;
2842
2843                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2844                         x += (intel_crtc->config->pipe_src_w - 1);
2845                         y += (intel_crtc->config->pipe_src_h - 1);
2846
2847                         /* Finding the last pixel of the last line of the display
2848                         data and adding to linear_offset*/
2849                         linear_offset +=
2850                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2851                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2852                 }
2853         }
2854
2855         I915_WRITE(reg, dspcntr);
2856
2857         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2858         I915_WRITE(DSPSURF(plane),
2859                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2860         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2861                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2862         } else {
2863                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2864                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2865         }
2866         POSTING_READ(reg);
2867 }
2868
2869 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2870                               uint32_t pixel_format)
2871 {
2872         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2873
2874         /*
2875          * The stride is either expressed as a multiple of 64 bytes
2876          * chunks for linear buffers or in number of tiles for tiled
2877          * buffers.
2878          */
2879         switch (fb_modifier) {
2880         case DRM_FORMAT_MOD_NONE:
2881                 return 64;
2882         case I915_FORMAT_MOD_X_TILED:
2883                 if (INTEL_INFO(dev)->gen == 2)
2884                         return 128;
2885                 return 512;
2886         case I915_FORMAT_MOD_Y_TILED:
2887                 /* No need to check for old gens and Y tiling since this is
2888                  * about the display engine and those will be blocked before
2889                  * we get here.
2890                  */
2891                 return 128;
2892         case I915_FORMAT_MOD_Yf_TILED:
2893                 if (bits_per_pixel == 8)
2894                         return 64;
2895                 else
2896                         return 128;
2897         default:
2898                 MISSING_CASE(fb_modifier);
2899                 return 64;
2900         }
2901 }
2902
2903 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2904                                      struct drm_i915_gem_object *obj)
2905 {
2906         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2907
2908         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2909                 view = &i915_ggtt_view_rotated;
2910
2911         return i915_gem_obj_ggtt_offset_view(obj, view);
2912 }
2913
2914 /*
2915  * This function detaches (aka. unbinds) unused scalers in hardware
2916  */
2917 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2918 {
2919         struct drm_device *dev;
2920         struct drm_i915_private *dev_priv;
2921         struct intel_crtc_scaler_state *scaler_state;
2922         int i;
2923
2924         dev = intel_crtc->base.dev;
2925         dev_priv = dev->dev_private;
2926         scaler_state = &intel_crtc->config->scaler_state;
2927
2928         /* loop through and disable scalers that aren't in use */
2929         for (i = 0; i < intel_crtc->num_scalers; i++) {
2930                 if (!scaler_state->scalers[i].in_use) {
2931                         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2932                         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2933                         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2934                         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2935                                 intel_crtc->base.base.id, intel_crtc->pipe, i);
2936                 }
2937         }
2938 }
2939
2940 u32 skl_plane_ctl_format(uint32_t pixel_format)
2941 {
2942         switch (pixel_format) {
2943         case DRM_FORMAT_C8:
2944                 return PLANE_CTL_FORMAT_INDEXED;
2945         case DRM_FORMAT_RGB565:
2946                 return PLANE_CTL_FORMAT_RGB_565;
2947         case DRM_FORMAT_XBGR8888:
2948                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2949         case DRM_FORMAT_XRGB8888:
2950                 return PLANE_CTL_FORMAT_XRGB_8888;
2951         /*
2952          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2953          * to be already pre-multiplied. We need to add a knob (or a different
2954          * DRM_FORMAT) for user-space to configure that.
2955          */
2956         case DRM_FORMAT_ABGR8888:
2957                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2958                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2959         case DRM_FORMAT_ARGB8888:
2960                 return PLANE_CTL_FORMAT_XRGB_8888 |
2961                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2962         case DRM_FORMAT_XRGB2101010:
2963                 return PLANE_CTL_FORMAT_XRGB_2101010;
2964         case DRM_FORMAT_XBGR2101010:
2965                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2966         case DRM_FORMAT_YUYV:
2967                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2968         case DRM_FORMAT_YVYU:
2969                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2970         case DRM_FORMAT_UYVY:
2971                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2972         case DRM_FORMAT_VYUY:
2973                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2974         default:
2975                 MISSING_CASE(pixel_format);
2976         }
2977
2978         return 0;
2979 }
2980
2981 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2982 {
2983         switch (fb_modifier) {
2984         case DRM_FORMAT_MOD_NONE:
2985                 break;
2986         case I915_FORMAT_MOD_X_TILED:
2987                 return PLANE_CTL_TILED_X;
2988         case I915_FORMAT_MOD_Y_TILED:
2989                 return PLANE_CTL_TILED_Y;
2990         case I915_FORMAT_MOD_Yf_TILED:
2991                 return PLANE_CTL_TILED_YF;
2992         default:
2993                 MISSING_CASE(fb_modifier);
2994         }
2995
2996         return 0;
2997 }
2998
2999 u32 skl_plane_ctl_rotation(unsigned int rotation)
3000 {
3001         switch (rotation) {
3002         case BIT(DRM_ROTATE_0):
3003                 break;
3004         /*
3005          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3006          * while i915 HW rotation is clockwise, thats why this swapping.
3007          */
3008         case BIT(DRM_ROTATE_90):
3009                 return PLANE_CTL_ROTATE_270;
3010         case BIT(DRM_ROTATE_180):
3011                 return PLANE_CTL_ROTATE_180;
3012         case BIT(DRM_ROTATE_270):
3013                 return PLANE_CTL_ROTATE_90;
3014         default:
3015                 MISSING_CASE(rotation);
3016         }
3017
3018         return 0;
3019 }
3020
3021 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3022                                          struct drm_framebuffer *fb,
3023                                          int x, int y)
3024 {
3025         struct drm_device *dev = crtc->dev;
3026         struct drm_i915_private *dev_priv = dev->dev_private;
3027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3028         struct drm_plane *plane = crtc->primary;
3029         bool visible = to_intel_plane_state(plane->state)->visible;
3030         struct drm_i915_gem_object *obj;
3031         int pipe = intel_crtc->pipe;
3032         u32 plane_ctl, stride_div, stride;
3033         u32 tile_height, plane_offset, plane_size;
3034         unsigned int rotation;
3035         int x_offset, y_offset;
3036         unsigned long surf_addr;
3037         struct intel_crtc_state *crtc_state = intel_crtc->config;
3038         struct intel_plane_state *plane_state;
3039         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3040         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3041         int scaler_id = -1;
3042
3043         plane_state = to_intel_plane_state(plane->state);
3044
3045         if (!visible || !fb) {
3046                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3047                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3048                 POSTING_READ(PLANE_CTL(pipe, 0));
3049                 return;
3050         }
3051
3052         plane_ctl = PLANE_CTL_ENABLE |
3053                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3054                     PLANE_CTL_PIPE_CSC_ENABLE;
3055
3056         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3057         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3058         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3059
3060         rotation = plane->state->rotation;
3061         plane_ctl |= skl_plane_ctl_rotation(rotation);
3062
3063         obj = intel_fb_obj(fb);
3064         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3065                                                fb->pixel_format);
3066         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3067
3068         /*
3069          * FIXME: intel_plane_state->src, dst aren't set when transitional
3070          * update_plane helpers are called from legacy paths.
3071          * Once full atomic crtc is available, below check can be avoided.
3072          */
3073         if (drm_rect_width(&plane_state->src)) {
3074                 scaler_id = plane_state->scaler_id;
3075                 src_x = plane_state->src.x1 >> 16;
3076                 src_y = plane_state->src.y1 >> 16;
3077                 src_w = drm_rect_width(&plane_state->src) >> 16;
3078                 src_h = drm_rect_height(&plane_state->src) >> 16;
3079                 dst_x = plane_state->dst.x1;
3080                 dst_y = plane_state->dst.y1;
3081                 dst_w = drm_rect_width(&plane_state->dst);
3082                 dst_h = drm_rect_height(&plane_state->dst);
3083
3084                 WARN_ON(x != src_x || y != src_y);
3085         } else {
3086                 src_w = intel_crtc->config->pipe_src_w;
3087                 src_h = intel_crtc->config->pipe_src_h;
3088         }
3089
3090         if (intel_rotation_90_or_270(rotation)) {
3091                 /* stride = Surface height in tiles */
3092                 tile_height = intel_tile_height(dev, fb->pixel_format,
3093                                                 fb->modifier[0]);
3094                 stride = DIV_ROUND_UP(fb->height, tile_height);
3095                 x_offset = stride * tile_height - y - src_h;
3096                 y_offset = x;
3097                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3098         } else {
3099                 stride = fb->pitches[0] / stride_div;
3100                 x_offset = x;
3101                 y_offset = y;
3102                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3103         }
3104         plane_offset = y_offset << 16 | x_offset;
3105
3106         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3107         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3108         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3109         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3110
3111         if (scaler_id >= 0) {
3112                 uint32_t ps_ctrl = 0;
3113
3114                 WARN_ON(!dst_w || !dst_h);
3115                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3116                         crtc_state->scaler_state.scalers[scaler_id].mode;
3117                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3118                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3119                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3120                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3121                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3122         } else {
3123                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3124         }
3125
3126         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3127
3128         POSTING_READ(PLANE_SURF(pipe, 0));
3129 }
3130
3131 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3132 static int
3133 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3134                            int x, int y, enum mode_set_atomic state)
3135 {
3136         struct drm_device *dev = crtc->dev;
3137         struct drm_i915_private *dev_priv = dev->dev_private;
3138
3139         if (dev_priv->fbc.disable_fbc)
3140                 dev_priv->fbc.disable_fbc(dev_priv);
3141
3142         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3143
3144         return 0;
3145 }
3146
3147 static void intel_complete_page_flips(struct drm_device *dev)
3148 {
3149         struct drm_crtc *crtc;
3150
3151         for_each_crtc(dev, crtc) {
3152                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3153                 enum plane plane = intel_crtc->plane;
3154
3155                 intel_prepare_page_flip(dev, plane);
3156                 intel_finish_page_flip_plane(dev, plane);
3157         }
3158 }
3159
3160 static void intel_update_primary_planes(struct drm_device *dev)
3161 {
3162         struct drm_i915_private *dev_priv = dev->dev_private;
3163         struct drm_crtc *crtc;
3164
3165         for_each_crtc(dev, crtc) {
3166                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167
3168                 drm_modeset_lock(&crtc->mutex, NULL);
3169                 /*
3170                  * FIXME: Once we have proper support for primary planes (and
3171                  * disabling them without disabling the entire crtc) allow again
3172                  * a NULL crtc->primary->fb.
3173                  */
3174                 if (intel_crtc->active && crtc->primary->fb)
3175                         dev_priv->display.update_primary_plane(crtc,
3176                                                                crtc->primary->fb,
3177                                                                crtc->x,
3178                                                                crtc->y);
3179                 drm_modeset_unlock(&crtc->mutex);
3180         }
3181 }
3182
3183 void intel_prepare_reset(struct drm_device *dev)
3184 {
3185         /* no reset support for gen2 */
3186         if (IS_GEN2(dev))
3187                 return;
3188
3189         /* reset doesn't touch the display */
3190         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3191                 return;
3192
3193         drm_modeset_lock_all(dev);
3194         /*
3195          * Disabling the crtcs gracefully seems nicer. Also the
3196          * g33 docs say we should at least disable all the planes.
3197          */
3198         intel_display_suspend(dev);
3199 }
3200
3201 void intel_finish_reset(struct drm_device *dev)
3202 {
3203         struct drm_i915_private *dev_priv = to_i915(dev);
3204
3205         /*
3206          * Flips in the rings will be nuked by the reset,
3207          * so complete all pending flips so that user space
3208          * will get its events and not get stuck.
3209          */
3210         intel_complete_page_flips(dev);
3211
3212         /* no reset support for gen2 */
3213         if (IS_GEN2(dev))
3214                 return;
3215
3216         /* reset doesn't touch the display */
3217         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3218                 /*
3219                  * Flips in the rings have been nuked by the reset,
3220                  * so update the base address of all primary
3221                  * planes to the the last fb to make sure we're
3222                  * showing the correct fb after a reset.
3223                  */
3224                 intel_update_primary_planes(dev);
3225                 return;
3226         }
3227
3228         /*
3229          * The display has been reset as well,
3230          * so need a full re-initialization.
3231          */
3232         intel_runtime_pm_disable_interrupts(dev_priv);
3233         intel_runtime_pm_enable_interrupts(dev_priv);
3234
3235         intel_modeset_init_hw(dev);
3236
3237         spin_lock_irq(&dev_priv->irq_lock);
3238         if (dev_priv->display.hpd_irq_setup)
3239                 dev_priv->display.hpd_irq_setup(dev);
3240         spin_unlock_irq(&dev_priv->irq_lock);
3241
3242         intel_modeset_setup_hw_state(dev, true);
3243
3244         intel_hpd_init(dev_priv);
3245
3246         drm_modeset_unlock_all(dev);
3247 }
3248
3249 static void
3250 intel_finish_fb(struct drm_framebuffer *old_fb)
3251 {
3252         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3253         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3254         bool was_interruptible = dev_priv->mm.interruptible;
3255         int ret;
3256
3257         /* Big Hammer, we also need to ensure that any pending
3258          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3259          * current scanout is retired before unpinning the old
3260          * framebuffer. Note that we rely on userspace rendering
3261          * into the buffer attached to the pipe they are waiting
3262          * on. If not, userspace generates a GPU hang with IPEHR
3263          * point to the MI_WAIT_FOR_EVENT.
3264          *
3265          * This should only fail upon a hung GPU, in which case we
3266          * can safely continue.
3267          */
3268         dev_priv->mm.interruptible = false;
3269         ret = i915_gem_object_wait_rendering(obj, true);
3270         dev_priv->mm.interruptible = was_interruptible;
3271
3272         WARN_ON(ret);
3273 }
3274
3275 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3276 {
3277         struct drm_device *dev = crtc->dev;
3278         struct drm_i915_private *dev_priv = dev->dev_private;
3279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3280         bool pending;
3281
3282         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3283             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3284                 return false;
3285
3286         spin_lock_irq(&dev->event_lock);
3287         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3288         spin_unlock_irq(&dev->event_lock);
3289
3290         return pending;
3291 }
3292
3293 static void intel_update_pipe_size(struct intel_crtc *crtc)
3294 {
3295         struct drm_device *dev = crtc->base.dev;
3296         struct drm_i915_private *dev_priv = dev->dev_private;
3297         const struct drm_display_mode *adjusted_mode;
3298
3299         if (!i915.fastboot)
3300                 return;
3301
3302         /*
3303          * Update pipe size and adjust fitter if needed: the reason for this is
3304          * that in compute_mode_changes we check the native mode (not the pfit
3305          * mode) to see if we can flip rather than do a full mode set. In the
3306          * fastboot case, we'll flip, but if we don't update the pipesrc and
3307          * pfit state, we'll end up with a big fb scanned out into the wrong
3308          * sized surface.
3309          *
3310          * To fix this properly, we need to hoist the checks up into
3311          * compute_mode_changes (or above), check the actual pfit state and
3312          * whether the platform allows pfit disable with pipe active, and only
3313          * then update the pipesrc and pfit state, even on the flip path.
3314          */
3315
3316         adjusted_mode = &crtc->config->base.adjusted_mode;
3317
3318         I915_WRITE(PIPESRC(crtc->pipe),
3319                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3320                    (adjusted_mode->crtc_vdisplay - 1));
3321         if (!crtc->config->pch_pfit.enabled &&
3322             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3323              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3324                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3325                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3326                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3327         }
3328         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3329         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3330 }
3331
3332 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3333 {
3334         struct drm_device *dev = crtc->dev;
3335         struct drm_i915_private *dev_priv = dev->dev_private;
3336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337         int pipe = intel_crtc->pipe;
3338         u32 reg, temp;
3339
3340         /* enable normal train */
3341         reg = FDI_TX_CTL(pipe);
3342         temp = I915_READ(reg);
3343         if (IS_IVYBRIDGE(dev)) {
3344                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3345                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3346         } else {
3347                 temp &= ~FDI_LINK_TRAIN_NONE;
3348                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3349         }
3350         I915_WRITE(reg, temp);
3351
3352         reg = FDI_RX_CTL(pipe);
3353         temp = I915_READ(reg);
3354         if (HAS_PCH_CPT(dev)) {
3355                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3357         } else {
3358                 temp &= ~FDI_LINK_TRAIN_NONE;
3359                 temp |= FDI_LINK_TRAIN_NONE;
3360         }
3361         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3362
3363         /* wait one idle pattern time */
3364         POSTING_READ(reg);
3365         udelay(1000);
3366
3367         /* IVB wants error correction enabled */
3368         if (IS_IVYBRIDGE(dev))
3369                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3370                            FDI_FE_ERRC_ENABLE);
3371 }
3372
3373 /* The FDI link training functions for ILK/Ibexpeak. */
3374 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3375 {
3376         struct drm_device *dev = crtc->dev;
3377         struct drm_i915_private *dev_priv = dev->dev_private;
3378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3379         int pipe = intel_crtc->pipe;
3380         u32 reg, temp, tries;
3381
3382         /* FDI needs bits from pipe first */
3383         assert_pipe_enabled(dev_priv, pipe);
3384
3385         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3386            for train result */
3387         reg = FDI_RX_IMR(pipe);
3388         temp = I915_READ(reg);
3389         temp &= ~FDI_RX_SYMBOL_LOCK;
3390         temp &= ~FDI_RX_BIT_LOCK;
3391         I915_WRITE(reg, temp);
3392         I915_READ(reg);
3393         udelay(150);
3394
3395         /* enable CPU FDI TX and PCH FDI RX */
3396         reg = FDI_TX_CTL(pipe);
3397         temp = I915_READ(reg);
3398         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3399         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3400         temp &= ~FDI_LINK_TRAIN_NONE;
3401         temp |= FDI_LINK_TRAIN_PATTERN_1;
3402         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3403
3404         reg = FDI_RX_CTL(pipe);
3405         temp = I915_READ(reg);
3406         temp &= ~FDI_LINK_TRAIN_NONE;
3407         temp |= FDI_LINK_TRAIN_PATTERN_1;
3408         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3409
3410         POSTING_READ(reg);
3411         udelay(150);
3412
3413         /* Ironlake workaround, enable clock pointer after FDI enable*/
3414         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3415         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3416                    FDI_RX_PHASE_SYNC_POINTER_EN);
3417
3418         reg = FDI_RX_IIR(pipe);
3419         for (tries = 0; tries < 5; tries++) {
3420                 temp = I915_READ(reg);
3421                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3422
3423                 if ((temp & FDI_RX_BIT_LOCK)) {
3424                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3425                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3426                         break;
3427                 }
3428         }
3429         if (tries == 5)
3430                 DRM_ERROR("FDI train 1 fail!\n");
3431
3432         /* Train 2 */
3433         reg = FDI_TX_CTL(pipe);
3434         temp = I915_READ(reg);
3435         temp &= ~FDI_LINK_TRAIN_NONE;
3436         temp |= FDI_LINK_TRAIN_PATTERN_2;
3437         I915_WRITE(reg, temp);
3438
3439         reg = FDI_RX_CTL(pipe);
3440         temp = I915_READ(reg);
3441         temp &= ~FDI_LINK_TRAIN_NONE;
3442         temp |= FDI_LINK_TRAIN_PATTERN_2;
3443         I915_WRITE(reg, temp);
3444
3445         POSTING_READ(reg);
3446         udelay(150);
3447
3448         reg = FDI_RX_IIR(pipe);
3449         for (tries = 0; tries < 5; tries++) {
3450                 temp = I915_READ(reg);
3451                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3452
3453                 if (temp & FDI_RX_SYMBOL_LOCK) {
3454                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3455                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3456                         break;
3457                 }
3458         }
3459         if (tries == 5)
3460                 DRM_ERROR("FDI train 2 fail!\n");
3461
3462         DRM_DEBUG_KMS("FDI train done\n");
3463
3464 }
3465
3466 static const int snb_b_fdi_train_param[] = {
3467         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3468         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3469         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3470         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3471 };
3472
3473 /* The FDI link training functions for SNB/Cougarpoint. */
3474 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3475 {
3476         struct drm_device *dev = crtc->dev;
3477         struct drm_i915_private *dev_priv = dev->dev_private;
3478         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3479         int pipe = intel_crtc->pipe;
3480         u32 reg, temp, i, retry;
3481
3482         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3483            for train result */
3484         reg = FDI_RX_IMR(pipe);
3485         temp = I915_READ(reg);
3486         temp &= ~FDI_RX_SYMBOL_LOCK;
3487         temp &= ~FDI_RX_BIT_LOCK;
3488         I915_WRITE(reg, temp);
3489
3490         POSTING_READ(reg);
3491         udelay(150);
3492
3493         /* enable CPU FDI TX and PCH FDI RX */
3494         reg = FDI_TX_CTL(pipe);
3495         temp = I915_READ(reg);
3496         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3497         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3498         temp &= ~FDI_LINK_TRAIN_NONE;
3499         temp |= FDI_LINK_TRAIN_PATTERN_1;
3500         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3501         /* SNB-B */
3502         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3503         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3504
3505         I915_WRITE(FDI_RX_MISC(pipe),
3506                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3507
3508         reg = FDI_RX_CTL(pipe);
3509         temp = I915_READ(reg);
3510         if (HAS_PCH_CPT(dev)) {
3511                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3512                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3513         } else {
3514                 temp &= ~FDI_LINK_TRAIN_NONE;
3515                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3516         }
3517         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3518
3519         POSTING_READ(reg);
3520         udelay(150);
3521
3522         for (i = 0; i < 4; i++) {
3523                 reg = FDI_TX_CTL(pipe);
3524                 temp = I915_READ(reg);
3525                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3526                 temp |= snb_b_fdi_train_param[i];
3527                 I915_WRITE(reg, temp);
3528
3529                 POSTING_READ(reg);
3530                 udelay(500);
3531
3532                 for (retry = 0; retry < 5; retry++) {
3533                         reg = FDI_RX_IIR(pipe);
3534                         temp = I915_READ(reg);
3535                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3536                         if (temp & FDI_RX_BIT_LOCK) {
3537                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3538                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3539                                 break;
3540                         }
3541                         udelay(50);
3542                 }
3543                 if (retry < 5)
3544                         break;
3545         }
3546         if (i == 4)
3547                 DRM_ERROR("FDI train 1 fail!\n");
3548
3549         /* Train 2 */
3550         reg = FDI_TX_CTL(pipe);
3551         temp = I915_READ(reg);
3552         temp &= ~FDI_LINK_TRAIN_NONE;
3553         temp |= FDI_LINK_TRAIN_PATTERN_2;
3554         if (IS_GEN6(dev)) {
3555                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3556                 /* SNB-B */
3557                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3558         }
3559         I915_WRITE(reg, temp);
3560
3561         reg = FDI_RX_CTL(pipe);
3562         temp = I915_READ(reg);
3563         if (HAS_PCH_CPT(dev)) {
3564                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3565                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3566         } else {
3567                 temp &= ~FDI_LINK_TRAIN_NONE;
3568                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3569         }
3570         I915_WRITE(reg, temp);
3571
3572         POSTING_READ(reg);
3573         udelay(150);
3574
3575         for (i = 0; i < 4; i++) {
3576                 reg = FDI_TX_CTL(pipe);
3577                 temp = I915_READ(reg);
3578                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3579                 temp |= snb_b_fdi_train_param[i];
3580                 I915_WRITE(reg, temp);
3581
3582                 POSTING_READ(reg);
3583                 udelay(500);
3584
3585                 for (retry = 0; retry < 5; retry++) {
3586                         reg = FDI_RX_IIR(pipe);
3587                         temp = I915_READ(reg);
3588                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3589                         if (temp & FDI_RX_SYMBOL_LOCK) {
3590                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3591                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3592                                 break;
3593                         }
3594                         udelay(50);
3595                 }
3596                 if (retry < 5)
3597                         break;
3598         }
3599         if (i == 4)
3600                 DRM_ERROR("FDI train 2 fail!\n");
3601
3602         DRM_DEBUG_KMS("FDI train done.\n");
3603 }
3604
3605 /* Manual link training for Ivy Bridge A0 parts */
3606 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3607 {
3608         struct drm_device *dev = crtc->dev;
3609         struct drm_i915_private *dev_priv = dev->dev_private;
3610         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3611         int pipe = intel_crtc->pipe;
3612         u32 reg, temp, i, j;
3613
3614         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3615            for train result */
3616         reg = FDI_RX_IMR(pipe);
3617         temp = I915_READ(reg);
3618         temp &= ~FDI_RX_SYMBOL_LOCK;
3619         temp &= ~FDI_RX_BIT_LOCK;
3620         I915_WRITE(reg, temp);
3621
3622         POSTING_READ(reg);
3623         udelay(150);
3624
3625         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3626                       I915_READ(FDI_RX_IIR(pipe)));
3627
3628         /* Try each vswing and preemphasis setting twice before moving on */
3629         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3630                 /* disable first in case we need to retry */
3631                 reg = FDI_TX_CTL(pipe);
3632                 temp = I915_READ(reg);
3633                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3634                 temp &= ~FDI_TX_ENABLE;
3635                 I915_WRITE(reg, temp);
3636
3637                 reg = FDI_RX_CTL(pipe);
3638                 temp = I915_READ(reg);
3639                 temp &= ~FDI_LINK_TRAIN_AUTO;
3640                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3641                 temp &= ~FDI_RX_ENABLE;
3642                 I915_WRITE(reg, temp);
3643
3644                 /* enable CPU FDI TX and PCH FDI RX */
3645                 reg = FDI_TX_CTL(pipe);
3646                 temp = I915_READ(reg);
3647                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3648                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3649                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3650                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3651                 temp |= snb_b_fdi_train_param[j/2];
3652                 temp |= FDI_COMPOSITE_SYNC;
3653                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3654
3655                 I915_WRITE(FDI_RX_MISC(pipe),
3656                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3657
3658                 reg = FDI_RX_CTL(pipe);
3659                 temp = I915_READ(reg);
3660                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3661                 temp |= FDI_COMPOSITE_SYNC;
3662                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3663
3664                 POSTING_READ(reg);
3665                 udelay(1); /* should be 0.5us */
3666
3667                 for (i = 0; i < 4; i++) {
3668                         reg = FDI_RX_IIR(pipe);
3669                         temp = I915_READ(reg);
3670                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3671
3672                         if (temp & FDI_RX_BIT_LOCK ||
3673                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3674                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3675                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3676                                               i);
3677                                 break;
3678                         }
3679                         udelay(1); /* should be 0.5us */
3680                 }
3681                 if (i == 4) {
3682                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3683                         continue;
3684                 }
3685
3686                 /* Train 2 */
3687                 reg = FDI_TX_CTL(pipe);
3688                 temp = I915_READ(reg);
3689                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3690                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3691                 I915_WRITE(reg, temp);
3692
3693                 reg = FDI_RX_CTL(pipe);
3694                 temp = I915_READ(reg);
3695                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3696                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3697                 I915_WRITE(reg, temp);
3698
3699                 POSTING_READ(reg);
3700                 udelay(2); /* should be 1.5us */
3701
3702                 for (i = 0; i < 4; i++) {
3703                         reg = FDI_RX_IIR(pipe);
3704                         temp = I915_READ(reg);
3705                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3706
3707                         if (temp & FDI_RX_SYMBOL_LOCK ||
3708                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3709                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3710                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3711                                               i);
3712                                 goto train_done;
3713                         }
3714                         udelay(2); /* should be 1.5us */
3715                 }
3716                 if (i == 4)
3717                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3718         }
3719
3720 train_done:
3721         DRM_DEBUG_KMS("FDI train done.\n");
3722 }
3723
3724 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3725 {
3726         struct drm_device *dev = intel_crtc->base.dev;
3727         struct drm_i915_private *dev_priv = dev->dev_private;
3728         int pipe = intel_crtc->pipe;
3729         u32 reg, temp;
3730
3731
3732         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3733         reg = FDI_RX_CTL(pipe);
3734         temp = I915_READ(reg);
3735         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3736         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3737         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3738         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3739
3740         POSTING_READ(reg);
3741         udelay(200);
3742
3743         /* Switch from Rawclk to PCDclk */
3744         temp = I915_READ(reg);
3745         I915_WRITE(reg, temp | FDI_PCDCLK);
3746
3747         POSTING_READ(reg);
3748         udelay(200);
3749
3750         /* Enable CPU FDI TX PLL, always on for Ironlake */
3751         reg = FDI_TX_CTL(pipe);
3752         temp = I915_READ(reg);
3753         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3754                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3755
3756                 POSTING_READ(reg);
3757                 udelay(100);
3758         }
3759 }
3760
3761 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3762 {
3763         struct drm_device *dev = intel_crtc->base.dev;
3764         struct drm_i915_private *dev_priv = dev->dev_private;
3765         int pipe = intel_crtc->pipe;
3766         u32 reg, temp;
3767
3768         /* Switch from PCDclk to Rawclk */
3769         reg = FDI_RX_CTL(pipe);
3770         temp = I915_READ(reg);
3771         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3772
3773         /* Disable CPU FDI TX PLL */
3774         reg = FDI_TX_CTL(pipe);
3775         temp = I915_READ(reg);
3776         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3777
3778         POSTING_READ(reg);
3779         udelay(100);
3780
3781         reg = FDI_RX_CTL(pipe);
3782         temp = I915_READ(reg);
3783         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3784
3785         /* Wait for the clocks to turn off. */
3786         POSTING_READ(reg);
3787         udelay(100);
3788 }
3789
3790 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3791 {
3792         struct drm_device *dev = crtc->dev;
3793         struct drm_i915_private *dev_priv = dev->dev_private;
3794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3795         int pipe = intel_crtc->pipe;
3796         u32 reg, temp;
3797
3798         /* disable CPU FDI tx and PCH FDI rx */
3799         reg = FDI_TX_CTL(pipe);
3800         temp = I915_READ(reg);
3801         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3802         POSTING_READ(reg);
3803
3804         reg = FDI_RX_CTL(pipe);
3805         temp = I915_READ(reg);
3806         temp &= ~(0x7 << 16);
3807         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3808         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3809
3810         POSTING_READ(reg);
3811         udelay(100);
3812
3813         /* Ironlake workaround, disable clock pointer after downing FDI */
3814         if (HAS_PCH_IBX(dev))
3815                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3816
3817         /* still set train pattern 1 */
3818         reg = FDI_TX_CTL(pipe);
3819         temp = I915_READ(reg);
3820         temp &= ~FDI_LINK_TRAIN_NONE;
3821         temp |= FDI_LINK_TRAIN_PATTERN_1;
3822         I915_WRITE(reg, temp);
3823
3824         reg = FDI_RX_CTL(pipe);
3825         temp = I915_READ(reg);
3826         if (HAS_PCH_CPT(dev)) {
3827                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3828                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3829         } else {
3830                 temp &= ~FDI_LINK_TRAIN_NONE;
3831                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3832         }
3833         /* BPC in FDI rx is consistent with that in PIPECONF */
3834         temp &= ~(0x07 << 16);
3835         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3836         I915_WRITE(reg, temp);
3837
3838         POSTING_READ(reg);
3839         udelay(100);
3840 }
3841
3842 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3843 {
3844         struct intel_crtc *crtc;
3845
3846         /* Note that we don't need to be called with mode_config.lock here
3847          * as our list of CRTC objects is static for the lifetime of the
3848          * device and so cannot disappear as we iterate. Similarly, we can
3849          * happily treat the predicates as racy, atomic checks as userspace
3850          * cannot claim and pin a new fb without at least acquring the
3851          * struct_mutex and so serialising with us.
3852          */
3853         for_each_intel_crtc(dev, crtc) {
3854                 if (atomic_read(&crtc->unpin_work_count) == 0)
3855                         continue;
3856
3857                 if (crtc->unpin_work)
3858                         intel_wait_for_vblank(dev, crtc->pipe);
3859
3860                 return true;
3861         }
3862
3863         return false;
3864 }
3865
3866 static void page_flip_completed(struct intel_crtc *intel_crtc)
3867 {
3868         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3869         struct intel_unpin_work *work = intel_crtc->unpin_work;
3870
3871         /* ensure that the unpin work is consistent wrt ->pending. */
3872         smp_rmb();
3873         intel_crtc->unpin_work = NULL;
3874
3875         if (work->event)
3876                 drm_send_vblank_event(intel_crtc->base.dev,
3877                                       intel_crtc->pipe,
3878                                       work->event);
3879
3880         drm_crtc_vblank_put(&intel_crtc->base);
3881
3882         wake_up_all(&dev_priv->pending_flip_queue);
3883         queue_work(dev_priv->wq, &work->work);
3884
3885         trace_i915_flip_complete(intel_crtc->plane,
3886                                  work->pending_flip_obj);
3887 }
3888
3889 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3890 {
3891         struct drm_device *dev = crtc->dev;
3892         struct drm_i915_private *dev_priv = dev->dev_private;
3893
3894         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3895         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3896                                        !intel_crtc_has_pending_flip(crtc),
3897                                        60*HZ) == 0)) {
3898                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3899
3900                 spin_lock_irq(&dev->event_lock);
3901                 if (intel_crtc->unpin_work) {
3902                         WARN_ONCE(1, "Removing stuck page flip\n");
3903                         page_flip_completed(intel_crtc);
3904                 }
3905                 spin_unlock_irq(&dev->event_lock);
3906         }
3907
3908         if (crtc->primary->fb) {
3909                 mutex_lock(&dev->struct_mutex);
3910                 intel_finish_fb(crtc->primary->fb);
3911                 mutex_unlock(&dev->struct_mutex);
3912         }
3913 }
3914
3915 /* Program iCLKIP clock to the desired frequency */
3916 static void lpt_program_iclkip(struct drm_crtc *crtc)
3917 {
3918         struct drm_device *dev = crtc->dev;
3919         struct drm_i915_private *dev_priv = dev->dev_private;
3920         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3921         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3922         u32 temp;
3923
3924         mutex_lock(&dev_priv->sb_lock);
3925
3926         /* It is necessary to ungate the pixclk gate prior to programming
3927          * the divisors, and gate it back when it is done.
3928          */
3929         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3930
3931         /* Disable SSCCTL */
3932         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3933                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3934                                 SBI_SSCCTL_DISABLE,
3935                         SBI_ICLK);
3936
3937         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3938         if (clock == 20000) {
3939                 auxdiv = 1;
3940                 divsel = 0x41;
3941                 phaseinc = 0x20;
3942         } else {
3943                 /* The iCLK virtual clock root frequency is in MHz,
3944                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3945                  * divisors, it is necessary to divide one by another, so we
3946                  * convert the virtual clock precision to KHz here for higher
3947                  * precision.
3948                  */
3949                 u32 iclk_virtual_root_freq = 172800 * 1000;
3950                 u32 iclk_pi_range = 64;
3951                 u32 desired_divisor, msb_divisor_value, pi_value;
3952
3953                 desired_divisor = (iclk_virtual_root_freq / clock);
3954                 msb_divisor_value = desired_divisor / iclk_pi_range;
3955                 pi_value = desired_divisor % iclk_pi_range;
3956
3957                 auxdiv = 0;
3958                 divsel = msb_divisor_value - 2;
3959                 phaseinc = pi_value;
3960         }
3961
3962         /* This should not happen with any sane values */
3963         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3964                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3965         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3966                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3967
3968         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3969                         clock,
3970                         auxdiv,
3971                         divsel,
3972                         phasedir,
3973                         phaseinc);
3974
3975         /* Program SSCDIVINTPHASE6 */
3976         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3977         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3978         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3979         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3980         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3981         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3982         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3983         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3984
3985         /* Program SSCAUXDIV */
3986         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3987         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3988         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3989         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3990
3991         /* Enable modulator and associated divider */
3992         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3993         temp &= ~SBI_SSCCTL_DISABLE;
3994         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3995
3996         /* Wait for initialization time */
3997         udelay(24);
3998
3999         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4000
4001         mutex_unlock(&dev_priv->sb_lock);
4002 }
4003
4004 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4005                                                 enum pipe pch_transcoder)
4006 {
4007         struct drm_device *dev = crtc->base.dev;
4008         struct drm_i915_private *dev_priv = dev->dev_private;
4009         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4010
4011         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4012                    I915_READ(HTOTAL(cpu_transcoder)));
4013         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4014                    I915_READ(HBLANK(cpu_transcoder)));
4015         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4016                    I915_READ(HSYNC(cpu_transcoder)));
4017
4018         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4019                    I915_READ(VTOTAL(cpu_transcoder)));
4020         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4021                    I915_READ(VBLANK(cpu_transcoder)));
4022         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4023                    I915_READ(VSYNC(cpu_transcoder)));
4024         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4025                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4026 }
4027
4028 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4029 {
4030         struct drm_i915_private *dev_priv = dev->dev_private;
4031         uint32_t temp;
4032
4033         temp = I915_READ(SOUTH_CHICKEN1);
4034         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4035                 return;
4036
4037         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4038         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4039
4040         temp &= ~FDI_BC_BIFURCATION_SELECT;
4041         if (enable)
4042                 temp |= FDI_BC_BIFURCATION_SELECT;
4043
4044         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4045         I915_WRITE(SOUTH_CHICKEN1, temp);
4046         POSTING_READ(SOUTH_CHICKEN1);
4047 }
4048
4049 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4050 {
4051         struct drm_device *dev = intel_crtc->base.dev;
4052
4053         switch (intel_crtc->pipe) {
4054         case PIPE_A:
4055                 break;
4056         case PIPE_B:
4057                 if (intel_crtc->config->fdi_lanes > 2)
4058                         cpt_set_fdi_bc_bifurcation(dev, false);
4059                 else
4060                         cpt_set_fdi_bc_bifurcation(dev, true);
4061
4062                 break;
4063         case PIPE_C:
4064                 cpt_set_fdi_bc_bifurcation(dev, true);
4065
4066                 break;
4067         default:
4068                 BUG();
4069         }
4070 }
4071
4072 /*
4073  * Enable PCH resources required for PCH ports:
4074  *   - PCH PLLs
4075  *   - FDI training & RX/TX
4076  *   - update transcoder timings
4077  *   - DP transcoding bits
4078  *   - transcoder
4079  */
4080 static void ironlake_pch_enable(struct drm_crtc *crtc)
4081 {
4082         struct drm_device *dev = crtc->dev;
4083         struct drm_i915_private *dev_priv = dev->dev_private;
4084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4085         int pipe = intel_crtc->pipe;
4086         u32 reg, temp;
4087
4088         assert_pch_transcoder_disabled(dev_priv, pipe);
4089
4090         if (IS_IVYBRIDGE(dev))
4091                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4092
4093         /* Write the TU size bits before fdi link training, so that error
4094          * detection works. */
4095         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4096                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4097
4098         /* For PCH output, training FDI link */
4099         dev_priv->display.fdi_link_train(crtc);
4100
4101         /* We need to program the right clock selection before writing the pixel
4102          * mutliplier into the DPLL. */
4103         if (HAS_PCH_CPT(dev)) {
4104                 u32 sel;
4105
4106                 temp = I915_READ(PCH_DPLL_SEL);
4107                 temp |= TRANS_DPLL_ENABLE(pipe);
4108                 sel = TRANS_DPLLB_SEL(pipe);
4109                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4110                         temp |= sel;
4111                 else
4112                         temp &= ~sel;
4113                 I915_WRITE(PCH_DPLL_SEL, temp);
4114         }
4115
4116         /* XXX: pch pll's can be enabled any time before we enable the PCH
4117          * transcoder, and we actually should do this to not upset any PCH
4118          * transcoder that already use the clock when we share it.
4119          *
4120          * Note that enable_shared_dpll tries to do the right thing, but
4121          * get_shared_dpll unconditionally resets the pll - we need that to have
4122          * the right LVDS enable sequence. */
4123         intel_enable_shared_dpll(intel_crtc);
4124
4125         /* set transcoder timing, panel must allow it */
4126         assert_panel_unlocked(dev_priv, pipe);
4127         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4128
4129         intel_fdi_normal_train(crtc);
4130
4131         /* For PCH DP, enable TRANS_DP_CTL */
4132         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4133                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4134                 reg = TRANS_DP_CTL(pipe);
4135                 temp = I915_READ(reg);
4136                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4137                           TRANS_DP_SYNC_MASK |
4138                           TRANS_DP_BPC_MASK);
4139                 temp |= TRANS_DP_OUTPUT_ENABLE;
4140                 temp |= bpc << 9; /* same format but at 11:9 */
4141
4142                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4143                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4144                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4145                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4146
4147                 switch (intel_trans_dp_port_sel(crtc)) {
4148                 case PCH_DP_B:
4149                         temp |= TRANS_DP_PORT_SEL_B;
4150                         break;
4151                 case PCH_DP_C:
4152                         temp |= TRANS_DP_PORT_SEL_C;
4153                         break;
4154                 case PCH_DP_D:
4155                         temp |= TRANS_DP_PORT_SEL_D;
4156                         break;
4157                 default:
4158                         BUG();
4159                 }
4160
4161                 I915_WRITE(reg, temp);
4162         }
4163
4164         ironlake_enable_pch_transcoder(dev_priv, pipe);
4165 }
4166
4167 static void lpt_pch_enable(struct drm_crtc *crtc)
4168 {
4169         struct drm_device *dev = crtc->dev;
4170         struct drm_i915_private *dev_priv = dev->dev_private;
4171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4172         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4173
4174         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4175
4176         lpt_program_iclkip(crtc);
4177
4178         /* Set transcoder timing. */
4179         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4180
4181         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4182 }
4183
4184 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4185                                                 struct intel_crtc_state *crtc_state)
4186 {
4187         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4188         struct intel_shared_dpll *pll;
4189         struct intel_shared_dpll_config *shared_dpll;
4190         enum intel_dpll_id i;
4191
4192         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4193
4194         if (HAS_PCH_IBX(dev_priv->dev)) {
4195                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4196                 i = (enum intel_dpll_id) crtc->pipe;
4197                 pll = &dev_priv->shared_dplls[i];
4198
4199                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4200                               crtc->base.base.id, pll->name);
4201
4202                 WARN_ON(shared_dpll[i].crtc_mask);
4203
4204                 goto found;
4205         }
4206
4207         if (IS_BROXTON(dev_priv->dev)) {
4208                 /* PLL is attached to port in bxt */
4209                 struct intel_encoder *encoder;
4210                 struct intel_digital_port *intel_dig_port;
4211
4212                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4213                 if (WARN_ON(!encoder))
4214                         return NULL;
4215
4216                 intel_dig_port = enc_to_dig_port(&encoder->base);
4217                 /* 1:1 mapping between ports and PLLs */
4218                 i = (enum intel_dpll_id)intel_dig_port->port;
4219                 pll = &dev_priv->shared_dplls[i];
4220                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4221                         crtc->base.base.id, pll->name);
4222                 WARN_ON(shared_dpll[i].crtc_mask);
4223
4224                 goto found;
4225         }
4226
4227         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4228                 pll = &dev_priv->shared_dplls[i];
4229
4230                 /* Only want to check enabled timings first */
4231                 if (shared_dpll[i].crtc_mask == 0)
4232                         continue;
4233
4234                 if (memcmp(&crtc_state->dpll_hw_state,
4235                            &shared_dpll[i].hw_state,
4236                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4237                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4238                                       crtc->base.base.id, pll->name,
4239                                       shared_dpll[i].crtc_mask,
4240                                       pll->active);
4241                         goto found;
4242                 }
4243         }
4244
4245         /* Ok no matching timings, maybe there's a free one? */
4246         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4247                 pll = &dev_priv->shared_dplls[i];
4248                 if (shared_dpll[i].crtc_mask == 0) {
4249                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4250                                       crtc->base.base.id, pll->name);
4251                         goto found;
4252                 }
4253         }
4254
4255         return NULL;
4256
4257 found:
4258         if (shared_dpll[i].crtc_mask == 0)
4259                 shared_dpll[i].hw_state =
4260                         crtc_state->dpll_hw_state;
4261
4262         crtc_state->shared_dpll = i;
4263         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4264                          pipe_name(crtc->pipe));
4265
4266         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4267
4268         return pll;
4269 }
4270
4271 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4272 {
4273         struct drm_i915_private *dev_priv = to_i915(state->dev);
4274         struct intel_shared_dpll_config *shared_dpll;
4275         struct intel_shared_dpll *pll;
4276         enum intel_dpll_id i;
4277
4278         if (!to_intel_atomic_state(state)->dpll_set)
4279                 return;
4280
4281         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4282         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283                 pll = &dev_priv->shared_dplls[i];
4284                 pll->config = shared_dpll[i];
4285         }
4286 }
4287
4288 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4289 {
4290         struct drm_i915_private *dev_priv = dev->dev_private;
4291         int dslreg = PIPEDSL(pipe);
4292         u32 temp;
4293
4294         temp = I915_READ(dslreg);
4295         udelay(500);
4296         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4297                 if (wait_for(I915_READ(dslreg) != temp, 5))
4298                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4299         }
4300 }
4301
4302 static int
4303 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4304                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4305                   int src_w, int src_h, int dst_w, int dst_h)
4306 {
4307         struct intel_crtc_scaler_state *scaler_state =
4308                 &crtc_state->scaler_state;
4309         struct intel_crtc *intel_crtc =
4310                 to_intel_crtc(crtc_state->base.crtc);
4311         int need_scaling;
4312
4313         need_scaling = intel_rotation_90_or_270(rotation) ?
4314                 (src_h != dst_w || src_w != dst_h):
4315                 (src_w != dst_w || src_h != dst_h);
4316
4317         /*
4318          * if plane is being disabled or scaler is no more required or force detach
4319          *  - free scaler binded to this plane/crtc
4320          *  - in order to do this, update crtc->scaler_usage
4321          *
4322          * Here scaler state in crtc_state is set free so that
4323          * scaler can be assigned to other user. Actual register
4324          * update to free the scaler is done in plane/panel-fit programming.
4325          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4326          */
4327         if (force_detach || !need_scaling) {
4328                 if (*scaler_id >= 0) {
4329                         scaler_state->scaler_users &= ~(1 << scaler_user);
4330                         scaler_state->scalers[*scaler_id].in_use = 0;
4331
4332                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4333                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4334                                 intel_crtc->pipe, scaler_user, *scaler_id,
4335                                 scaler_state->scaler_users);
4336                         *scaler_id = -1;
4337                 }
4338                 return 0;
4339         }
4340
4341         /* range checks */
4342         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4343                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4344
4345                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4346                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4347                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4348                         "size is out of scaler range\n",
4349                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4350                 return -EINVAL;
4351         }
4352
4353         /* mark this plane as a scaler user in crtc_state */
4354         scaler_state->scaler_users |= (1 << scaler_user);
4355         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4356                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4357                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4358                 scaler_state->scaler_users);
4359
4360         return 0;
4361 }
4362
4363 /**
4364  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4365  *
4366  * @state: crtc's scaler state
4367  * @force_detach: whether to forcibly disable scaler
4368  *
4369  * Return
4370  *     0 - scaler_usage updated successfully
4371  *    error - requested scaling cannot be supported or other error condition
4372  */
4373 int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4374 {
4375         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4376         struct drm_display_mode *adjusted_mode =
4377                 &state->base.adjusted_mode;
4378
4379         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4380                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4381
4382         return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4383                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4384                 state->pipe_src_w, state->pipe_src_h,
4385                 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4386 }
4387
4388 /**
4389  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4390  *
4391  * @state: crtc's scaler state
4392  * @plane_state: atomic plane state to update
4393  *
4394  * Return
4395  *     0 - scaler_usage updated successfully
4396  *    error - requested scaling cannot be supported or other error condition
4397  */
4398 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4399                                    struct intel_plane_state *plane_state)
4400 {
4401
4402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4403         struct intel_plane *intel_plane =
4404                 to_intel_plane(plane_state->base.plane);
4405         struct drm_framebuffer *fb = plane_state->base.fb;
4406         int ret;
4407
4408         bool force_detach = !fb || !plane_state->visible;
4409
4410         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4411                       intel_plane->base.base.id, intel_crtc->pipe,
4412                       drm_plane_index(&intel_plane->base));
4413
4414         ret = skl_update_scaler(crtc_state, force_detach,
4415                                 drm_plane_index(&intel_plane->base),
4416                                 &plane_state->scaler_id,
4417                                 plane_state->base.rotation,
4418                                 drm_rect_width(&plane_state->src) >> 16,
4419                                 drm_rect_height(&plane_state->src) >> 16,
4420                                 drm_rect_width(&plane_state->dst),
4421                                 drm_rect_height(&plane_state->dst));
4422
4423         if (ret || plane_state->scaler_id < 0)
4424                 return ret;
4425
4426         /* check colorkey */
4427         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4428                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4429                               intel_plane->base.base.id);
4430                 return -EINVAL;
4431         }
4432
4433         /* Check src format */
4434         switch (fb->pixel_format) {
4435         case DRM_FORMAT_RGB565:
4436         case DRM_FORMAT_XBGR8888:
4437         case DRM_FORMAT_XRGB8888:
4438         case DRM_FORMAT_ABGR8888:
4439         case DRM_FORMAT_ARGB8888:
4440         case DRM_FORMAT_XRGB2101010:
4441         case DRM_FORMAT_XBGR2101010:
4442         case DRM_FORMAT_YUYV:
4443         case DRM_FORMAT_YVYU:
4444         case DRM_FORMAT_UYVY:
4445         case DRM_FORMAT_VYUY:
4446                 break;
4447         default:
4448                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4449                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4450                 return -EINVAL;
4451         }
4452
4453         return 0;
4454 }
4455
4456 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4457 {
4458         struct drm_device *dev = crtc->base.dev;
4459         struct drm_i915_private *dev_priv = dev->dev_private;
4460         int pipe = crtc->pipe;
4461         struct intel_crtc_scaler_state *scaler_state =
4462                 &crtc->config->scaler_state;
4463
4464         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4465
4466         /* To update pfit, first update scaler state */
4467         skl_update_scaler_crtc(crtc->config, !enable);
4468         intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4469         skl_detach_scalers(crtc);
4470         if (!enable)
4471                 return;
4472
4473         if (crtc->config->pch_pfit.enabled) {
4474                 int id;
4475
4476                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4477                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4478                         return;
4479                 }
4480
4481                 id = scaler_state->scaler_id;
4482                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4483                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4484                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4485                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4486
4487                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4488         }
4489 }
4490
4491 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4492 {
4493         struct drm_device *dev = crtc->base.dev;
4494         struct drm_i915_private *dev_priv = dev->dev_private;
4495         int pipe = crtc->pipe;
4496
4497         if (crtc->config->pch_pfit.enabled) {
4498                 /* Force use of hard-coded filter coefficients
4499                  * as some pre-programmed values are broken,
4500                  * e.g. x201.
4501                  */
4502                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4503                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4504                                                  PF_PIPE_SEL_IVB(pipe));
4505                 else
4506                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4507                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4508                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4509         }
4510 }
4511
4512 void hsw_enable_ips(struct intel_crtc *crtc)
4513 {
4514         struct drm_device *dev = crtc->base.dev;
4515         struct drm_i915_private *dev_priv = dev->dev_private;
4516
4517         if (!crtc->config->ips_enabled)
4518                 return;
4519
4520         /* We can only enable IPS after we enable a plane and wait for a vblank */
4521         intel_wait_for_vblank(dev, crtc->pipe);
4522
4523         assert_plane_enabled(dev_priv, crtc->plane);
4524         if (IS_BROADWELL(dev)) {
4525                 mutex_lock(&dev_priv->rps.hw_lock);
4526                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4527                 mutex_unlock(&dev_priv->rps.hw_lock);
4528                 /* Quoting Art Runyan: "its not safe to expect any particular
4529                  * value in IPS_CTL bit 31 after enabling IPS through the
4530                  * mailbox." Moreover, the mailbox may return a bogus state,
4531                  * so we need to just enable it and continue on.
4532                  */
4533         } else {
4534                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4535                 /* The bit only becomes 1 in the next vblank, so this wait here
4536                  * is essentially intel_wait_for_vblank. If we don't have this
4537                  * and don't wait for vblanks until the end of crtc_enable, then
4538                  * the HW state readout code will complain that the expected
4539                  * IPS_CTL value is not the one we read. */
4540                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4541                         DRM_ERROR("Timed out waiting for IPS enable\n");
4542         }
4543 }
4544
4545 void hsw_disable_ips(struct intel_crtc *crtc)
4546 {
4547         struct drm_device *dev = crtc->base.dev;
4548         struct drm_i915_private *dev_priv = dev->dev_private;
4549
4550         if (!crtc->config->ips_enabled)
4551                 return;
4552
4553         assert_plane_enabled(dev_priv, crtc->plane);
4554         if (IS_BROADWELL(dev)) {
4555                 mutex_lock(&dev_priv->rps.hw_lock);
4556                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4557                 mutex_unlock(&dev_priv->rps.hw_lock);
4558                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4559                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4560                         DRM_ERROR("Timed out waiting for IPS disable\n");
4561         } else {
4562                 I915_WRITE(IPS_CTL, 0);
4563                 POSTING_READ(IPS_CTL);
4564         }
4565
4566         /* We need to wait for a vblank before we can disable the plane. */
4567         intel_wait_for_vblank(dev, crtc->pipe);
4568 }
4569
4570 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4571 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4572 {
4573         struct drm_device *dev = crtc->dev;
4574         struct drm_i915_private *dev_priv = dev->dev_private;
4575         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4576         enum pipe pipe = intel_crtc->pipe;
4577         int palreg = PALETTE(pipe);
4578         int i;
4579         bool reenable_ips = false;
4580
4581         /* The clocks have to be on to load the palette. */
4582         if (!crtc->state->active)
4583                 return;
4584
4585         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4586                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4587                         assert_dsi_pll_enabled(dev_priv);
4588                 else
4589                         assert_pll_enabled(dev_priv, pipe);
4590         }
4591
4592         /* use legacy palette for Ironlake */
4593         if (!HAS_GMCH_DISPLAY(dev))
4594                 palreg = LGC_PALETTE(pipe);
4595
4596         /* Workaround : Do not read or write the pipe palette/gamma data while
4597          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4598          */
4599         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4600             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4601              GAMMA_MODE_MODE_SPLIT)) {
4602                 hsw_disable_ips(intel_crtc);
4603                 reenable_ips = true;
4604         }
4605
4606         for (i = 0; i < 256; i++) {
4607                 I915_WRITE(palreg + 4 * i,
4608                            (intel_crtc->lut_r[i] << 16) |
4609                            (intel_crtc->lut_g[i] << 8) |
4610                            intel_crtc->lut_b[i]);
4611         }
4612
4613         if (reenable_ips)
4614                 hsw_enable_ips(intel_crtc);
4615 }
4616
4617 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4618 {
4619         if (intel_crtc->overlay) {
4620                 struct drm_device *dev = intel_crtc->base.dev;
4621                 struct drm_i915_private *dev_priv = dev->dev_private;
4622
4623                 mutex_lock(&dev->struct_mutex);
4624                 dev_priv->mm.interruptible = false;
4625                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4626                 dev_priv->mm.interruptible = true;
4627                 mutex_unlock(&dev->struct_mutex);
4628         }
4629
4630         /* Let userspace switch the overlay on again. In most cases userspace
4631          * has to recompute where to put it anyway.
4632          */
4633 }
4634
4635 /**
4636  * intel_post_enable_primary - Perform operations after enabling primary plane
4637  * @crtc: the CRTC whose primary plane was just enabled
4638  *
4639  * Performs potentially sleeping operations that must be done after the primary
4640  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4641  * called due to an explicit primary plane update, or due to an implicit
4642  * re-enable that is caused when a sprite plane is updated to no longer
4643  * completely hide the primary plane.
4644  */
4645 static void
4646 intel_post_enable_primary(struct drm_crtc *crtc)
4647 {
4648         struct drm_device *dev = crtc->dev;
4649         struct drm_i915_private *dev_priv = dev->dev_private;
4650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4651         int pipe = intel_crtc->pipe;
4652
4653         /*
4654          * BDW signals flip done immediately if the plane
4655          * is disabled, even if the plane enable is already
4656          * armed to occur at the next vblank :(
4657          */
4658         if (IS_BROADWELL(dev))
4659                 intel_wait_for_vblank(dev, pipe);
4660
4661         /*
4662          * FIXME IPS should be fine as long as one plane is
4663          * enabled, but in practice it seems to have problems
4664          * when going from primary only to sprite only and vice
4665          * versa.
4666          */
4667         hsw_enable_ips(intel_crtc);
4668
4669         /*
4670          * Gen2 reports pipe underruns whenever all planes are disabled.
4671          * So don't enable underrun reporting before at least some planes
4672          * are enabled.
4673          * FIXME: Need to fix the logic to work when we turn off all planes
4674          * but leave the pipe running.
4675          */
4676         if (IS_GEN2(dev))
4677                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4678
4679         /* Underruns don't raise interrupts, so check manually. */
4680         if (HAS_GMCH_DISPLAY(dev))
4681                 i9xx_check_fifo_underruns(dev_priv);
4682 }
4683
4684 /**
4685  * intel_pre_disable_primary - Perform operations before disabling primary plane
4686  * @crtc: the CRTC whose primary plane is to be disabled
4687  *
4688  * Performs potentially sleeping operations that must be done before the
4689  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4690  * be called due to an explicit primary plane update, or due to an implicit
4691  * disable that is caused when a sprite plane completely hides the primary
4692  * plane.
4693  */
4694 static void
4695 intel_pre_disable_primary(struct drm_crtc *crtc)
4696 {
4697         struct drm_device *dev = crtc->dev;
4698         struct drm_i915_private *dev_priv = dev->dev_private;
4699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4700         int pipe = intel_crtc->pipe;
4701
4702         /*
4703          * Gen2 reports pipe underruns whenever all planes are disabled.
4704          * So diasble underrun reporting before all the planes get disabled.
4705          * FIXME: Need to fix the logic to work when we turn off all planes
4706          * but leave the pipe running.
4707          */
4708         if (IS_GEN2(dev))
4709                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4710
4711         /*
4712          * Vblank time updates from the shadow to live plane control register
4713          * are blocked if the memory self-refresh mode is active at that
4714          * moment. So to make sure the plane gets truly disabled, disable
4715          * first the self-refresh mode. The self-refresh enable bit in turn
4716          * will be checked/applied by the HW only at the next frame start
4717          * event which is after the vblank start event, so we need to have a
4718          * wait-for-vblank between disabling the plane and the pipe.
4719          */
4720         if (HAS_GMCH_DISPLAY(dev)) {
4721                 intel_set_memory_cxsr(dev_priv, false);
4722                 dev_priv->wm.vlv.cxsr = false;
4723                 intel_wait_for_vblank(dev, pipe);
4724         }
4725
4726         /*
4727          * FIXME IPS should be fine as long as one plane is
4728          * enabled, but in practice it seems to have problems
4729          * when going from primary only to sprite only and vice
4730          * versa.
4731          */
4732         hsw_disable_ips(intel_crtc);
4733 }
4734
4735 static void intel_post_plane_update(struct intel_crtc *crtc)
4736 {
4737         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4738         struct drm_device *dev = crtc->base.dev;
4739         struct drm_i915_private *dev_priv = dev->dev_private;
4740         struct drm_plane *plane;
4741
4742         if (atomic->wait_vblank)
4743                 intel_wait_for_vblank(dev, crtc->pipe);
4744
4745         intel_frontbuffer_flip(dev, atomic->fb_bits);
4746
4747         if (atomic->disable_cxsr)
4748                 crtc->wm.cxsr_allowed = true;
4749
4750         if (crtc->atomic.update_wm_post)
4751                 intel_update_watermarks(&crtc->base);
4752
4753         if (atomic->update_fbc)
4754                 intel_fbc_update(dev_priv);
4755
4756         if (atomic->post_enable_primary)
4757                 intel_post_enable_primary(&crtc->base);
4758
4759         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4760                 intel_update_sprite_watermarks(plane, &crtc->base,
4761                                                0, 0, 0, false, false);
4762
4763         memset(atomic, 0, sizeof(*atomic));
4764 }
4765
4766 static void intel_pre_plane_update(struct intel_crtc *crtc)
4767 {
4768         struct drm_device *dev = crtc->base.dev;
4769         struct drm_i915_private *dev_priv = dev->dev_private;
4770         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4771         struct drm_plane *p;
4772
4773         /* Track fb's for any planes being disabled */
4774         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4775                 struct intel_plane *plane = to_intel_plane(p);
4776
4777                 mutex_lock(&dev->struct_mutex);
4778                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4779                                   plane->frontbuffer_bit);
4780                 mutex_unlock(&dev->struct_mutex);
4781         }
4782
4783         if (atomic->wait_for_flips)
4784                 intel_crtc_wait_for_pending_flips(&crtc->base);
4785
4786         if (atomic->disable_fbc)
4787                 intel_fbc_disable_crtc(crtc);
4788
4789         if (crtc->atomic.disable_ips)
4790                 hsw_disable_ips(crtc);
4791
4792         if (atomic->pre_disable_primary)
4793                 intel_pre_disable_primary(&crtc->base);
4794
4795         if (atomic->disable_cxsr) {
4796                 crtc->wm.cxsr_allowed = false;
4797                 intel_set_memory_cxsr(dev_priv, false);
4798         }
4799 }
4800
4801 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4802 {
4803         struct drm_device *dev = crtc->dev;
4804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4805         struct drm_plane *p;
4806         int pipe = intel_crtc->pipe;
4807
4808         intel_crtc_dpms_overlay_disable(intel_crtc);
4809
4810         drm_for_each_plane_mask(p, dev, plane_mask)
4811                 to_intel_plane(p)->disable_plane(p, crtc);
4812
4813         /*
4814          * FIXME: Once we grow proper nuclear flip support out of this we need
4815          * to compute the mask of flip planes precisely. For the time being
4816          * consider this a flip to a NULL plane.
4817          */
4818         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4819 }
4820
4821 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4822 {
4823         struct drm_device *dev = crtc->dev;
4824         struct drm_i915_private *dev_priv = dev->dev_private;
4825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4826         struct intel_encoder *encoder;
4827         int pipe = intel_crtc->pipe;
4828
4829         if (WARN_ON(intel_crtc->active))
4830                 return;
4831
4832         if (intel_crtc->config->has_pch_encoder)
4833                 intel_prepare_shared_dpll(intel_crtc);
4834
4835         if (intel_crtc->config->has_dp_encoder)
4836                 intel_dp_set_m_n(intel_crtc, M1_N1);
4837
4838         intel_set_pipe_timings(intel_crtc);
4839
4840         if (intel_crtc->config->has_pch_encoder) {
4841                 intel_cpu_transcoder_set_m_n(intel_crtc,
4842                                      &intel_crtc->config->fdi_m_n, NULL);
4843         }
4844
4845         ironlake_set_pipeconf(crtc);
4846
4847         intel_crtc->active = true;
4848
4849         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4850         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4851
4852         for_each_encoder_on_crtc(dev, crtc, encoder)
4853                 if (encoder->pre_enable)
4854                         encoder->pre_enable(encoder);
4855
4856         if (intel_crtc->config->has_pch_encoder) {
4857                 /* Note: FDI PLL enabling _must_ be done before we enable the
4858                  * cpu pipes, hence this is separate from all the other fdi/pch
4859                  * enabling. */
4860                 ironlake_fdi_pll_enable(intel_crtc);
4861         } else {
4862                 assert_fdi_tx_disabled(dev_priv, pipe);
4863                 assert_fdi_rx_disabled(dev_priv, pipe);
4864         }
4865
4866         ironlake_pfit_enable(intel_crtc);
4867
4868         /*
4869          * On ILK+ LUT must be loaded before the pipe is running but with
4870          * clocks enabled
4871          */
4872         intel_crtc_load_lut(crtc);
4873
4874         intel_update_watermarks(crtc);
4875         intel_enable_pipe(intel_crtc);
4876
4877         if (intel_crtc->config->has_pch_encoder)
4878                 ironlake_pch_enable(crtc);
4879
4880         assert_vblank_disabled(crtc);
4881         drm_crtc_vblank_on(crtc);
4882
4883         for_each_encoder_on_crtc(dev, crtc, encoder)
4884                 encoder->enable(encoder);
4885
4886         if (HAS_PCH_CPT(dev))
4887                 cpt_verify_modeset(dev, intel_crtc->pipe);
4888 }
4889
4890 /* IPS only exists on ULT machines and is tied to pipe A. */
4891 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4892 {
4893         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4894 }
4895
4896 static void haswell_crtc_enable(struct drm_crtc *crtc)
4897 {
4898         struct drm_device *dev = crtc->dev;
4899         struct drm_i915_private *dev_priv = dev->dev_private;
4900         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4901         struct intel_encoder *encoder;
4902         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4903         struct intel_crtc_state *pipe_config =
4904                 to_intel_crtc_state(crtc->state);
4905
4906         if (WARN_ON(intel_crtc->active))
4907                 return;
4908
4909         if (intel_crtc_to_shared_dpll(intel_crtc))
4910                 intel_enable_shared_dpll(intel_crtc);
4911
4912         if (intel_crtc->config->has_dp_encoder)
4913                 intel_dp_set_m_n(intel_crtc, M1_N1);
4914
4915         intel_set_pipe_timings(intel_crtc);
4916
4917         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4918                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4919                            intel_crtc->config->pixel_multiplier - 1);
4920         }
4921
4922         if (intel_crtc->config->has_pch_encoder) {
4923                 intel_cpu_transcoder_set_m_n(intel_crtc,
4924                                      &intel_crtc->config->fdi_m_n, NULL);
4925         }
4926
4927         haswell_set_pipeconf(crtc);
4928
4929         intel_set_pipe_csc(crtc);
4930
4931         intel_crtc->active = true;
4932
4933         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4934         for_each_encoder_on_crtc(dev, crtc, encoder)
4935                 if (encoder->pre_enable)
4936                         encoder->pre_enable(encoder);
4937
4938         if (intel_crtc->config->has_pch_encoder) {
4939                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4940                                                       true);
4941                 dev_priv->display.fdi_link_train(crtc);
4942         }
4943
4944         intel_ddi_enable_pipe_clock(intel_crtc);
4945
4946         if (INTEL_INFO(dev)->gen == 9)
4947                 skylake_pfit_update(intel_crtc, 1);
4948         else if (INTEL_INFO(dev)->gen < 9)
4949                 ironlake_pfit_enable(intel_crtc);
4950         else
4951                 MISSING_CASE(INTEL_INFO(dev)->gen);
4952
4953         /*
4954          * On ILK+ LUT must be loaded before the pipe is running but with
4955          * clocks enabled
4956          */
4957         intel_crtc_load_lut(crtc);
4958
4959         intel_ddi_set_pipe_settings(crtc);
4960         intel_ddi_enable_transcoder_func(crtc);
4961
4962         intel_update_watermarks(crtc);
4963         intel_enable_pipe(intel_crtc);
4964
4965         if (intel_crtc->config->has_pch_encoder)
4966                 lpt_pch_enable(crtc);
4967
4968         if (intel_crtc->config->dp_encoder_is_mst)
4969                 intel_ddi_set_vc_payload_alloc(crtc, true);
4970
4971         assert_vblank_disabled(crtc);
4972         drm_crtc_vblank_on(crtc);
4973
4974         for_each_encoder_on_crtc(dev, crtc, encoder) {
4975                 encoder->enable(encoder);
4976                 intel_opregion_notify_encoder(encoder, true);
4977         }
4978
4979         /* If we change the relative order between pipe/planes enabling, we need
4980          * to change the workaround. */
4981         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4982         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4983                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4984                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4985         }
4986 }
4987
4988 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4989 {
4990         struct drm_device *dev = crtc->base.dev;
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992         int pipe = crtc->pipe;
4993
4994         /* To avoid upsetting the power well on haswell only disable the pfit if
4995          * it's in use. The hw state code will make sure we get this right. */
4996         if (crtc->config->pch_pfit.enabled) {
4997                 I915_WRITE(PF_CTL(pipe), 0);
4998                 I915_WRITE(PF_WIN_POS(pipe), 0);
4999                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5000         }
5001 }
5002
5003 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5004 {
5005         struct drm_device *dev = crtc->dev;
5006         struct drm_i915_private *dev_priv = dev->dev_private;
5007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5008         struct intel_encoder *encoder;
5009         int pipe = intel_crtc->pipe;
5010         u32 reg, temp;
5011
5012         for_each_encoder_on_crtc(dev, crtc, encoder)
5013                 encoder->disable(encoder);
5014
5015         drm_crtc_vblank_off(crtc);
5016         assert_vblank_disabled(crtc);
5017
5018         if (intel_crtc->config->has_pch_encoder)
5019                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5020
5021         intel_disable_pipe(intel_crtc);
5022
5023         ironlake_pfit_disable(intel_crtc);
5024
5025         if (intel_crtc->config->has_pch_encoder)
5026                 ironlake_fdi_disable(crtc);
5027
5028         for_each_encoder_on_crtc(dev, crtc, encoder)
5029                 if (encoder->post_disable)
5030                         encoder->post_disable(encoder);
5031
5032         if (intel_crtc->config->has_pch_encoder) {
5033                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5034
5035                 if (HAS_PCH_CPT(dev)) {
5036                         /* disable TRANS_DP_CTL */
5037                         reg = TRANS_DP_CTL(pipe);
5038                         temp = I915_READ(reg);
5039                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5040                                   TRANS_DP_PORT_SEL_MASK);
5041                         temp |= TRANS_DP_PORT_SEL_NONE;
5042                         I915_WRITE(reg, temp);
5043
5044                         /* disable DPLL_SEL */
5045                         temp = I915_READ(PCH_DPLL_SEL);
5046                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5047                         I915_WRITE(PCH_DPLL_SEL, temp);
5048                 }
5049
5050                 ironlake_fdi_pll_disable(intel_crtc);
5051         }
5052
5053         intel_crtc->active = false;
5054         intel_update_watermarks(crtc);
5055 }
5056
5057 static void haswell_crtc_disable(struct drm_crtc *crtc)
5058 {
5059         struct drm_device *dev = crtc->dev;
5060         struct drm_i915_private *dev_priv = dev->dev_private;
5061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5062         struct intel_encoder *encoder;
5063         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5064
5065         for_each_encoder_on_crtc(dev, crtc, encoder) {
5066                 intel_opregion_notify_encoder(encoder, false);
5067                 encoder->disable(encoder);
5068         }
5069
5070         drm_crtc_vblank_off(crtc);
5071         assert_vblank_disabled(crtc);
5072
5073         if (intel_crtc->config->has_pch_encoder)
5074                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5075                                                       false);
5076         intel_disable_pipe(intel_crtc);
5077
5078         if (intel_crtc->config->dp_encoder_is_mst)
5079                 intel_ddi_set_vc_payload_alloc(crtc, false);
5080
5081         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5082
5083         if (INTEL_INFO(dev)->gen == 9)
5084                 skylake_pfit_update(intel_crtc, 0);
5085         else if (INTEL_INFO(dev)->gen < 9)
5086                 ironlake_pfit_disable(intel_crtc);
5087         else
5088                 MISSING_CASE(INTEL_INFO(dev)->gen);
5089
5090         intel_ddi_disable_pipe_clock(intel_crtc);
5091
5092         if (intel_crtc->config->has_pch_encoder) {
5093                 lpt_disable_pch_transcoder(dev_priv);
5094                 intel_ddi_fdi_disable(crtc);
5095         }
5096
5097         for_each_encoder_on_crtc(dev, crtc, encoder)
5098                 if (encoder->post_disable)
5099                         encoder->post_disable(encoder);
5100
5101         intel_crtc->active = false;
5102         intel_update_watermarks(crtc);
5103 }
5104
5105 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5106 {
5107         struct drm_device *dev = crtc->base.dev;
5108         struct drm_i915_private *dev_priv = dev->dev_private;
5109         struct intel_crtc_state *pipe_config = crtc->config;
5110
5111         if (!pipe_config->gmch_pfit.control)
5112                 return;
5113
5114         /*
5115          * The panel fitter should only be adjusted whilst the pipe is disabled,
5116          * according to register description and PRM.
5117          */
5118         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5119         assert_pipe_disabled(dev_priv, crtc->pipe);
5120
5121         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5122         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5123
5124         /* Border color in case we don't scale up to the full screen. Black by
5125          * default, change to something else for debugging. */
5126         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5127 }
5128
5129 static enum intel_display_power_domain port_to_power_domain(enum port port)
5130 {
5131         switch (port) {
5132         case PORT_A:
5133                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5134         case PORT_B:
5135                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5136         case PORT_C:
5137                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5138         case PORT_D:
5139                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5140         default:
5141                 WARN_ON_ONCE(1);
5142                 return POWER_DOMAIN_PORT_OTHER;
5143         }
5144 }
5145
5146 #define for_each_power_domain(domain, mask)                             \
5147         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5148                 if ((1 << (domain)) & (mask))
5149
5150 enum intel_display_power_domain
5151 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5152 {
5153         struct drm_device *dev = intel_encoder->base.dev;
5154         struct intel_digital_port *intel_dig_port;
5155
5156         switch (intel_encoder->type) {
5157         case INTEL_OUTPUT_UNKNOWN:
5158                 /* Only DDI platforms should ever use this output type */
5159                 WARN_ON_ONCE(!HAS_DDI(dev));
5160         case INTEL_OUTPUT_DISPLAYPORT:
5161         case INTEL_OUTPUT_HDMI:
5162         case INTEL_OUTPUT_EDP:
5163                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5164                 return port_to_power_domain(intel_dig_port->port);
5165         case INTEL_OUTPUT_DP_MST:
5166                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5167                 return port_to_power_domain(intel_dig_port->port);
5168         case INTEL_OUTPUT_ANALOG:
5169                 return POWER_DOMAIN_PORT_CRT;
5170         case INTEL_OUTPUT_DSI:
5171                 return POWER_DOMAIN_PORT_DSI;
5172         default:
5173                 return POWER_DOMAIN_PORT_OTHER;
5174         }
5175 }
5176
5177 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5178 {
5179         struct drm_device *dev = crtc->dev;
5180         struct intel_encoder *intel_encoder;
5181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5182         enum pipe pipe = intel_crtc->pipe;
5183         unsigned long mask;
5184         enum transcoder transcoder;
5185
5186         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5187
5188         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5189         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5190         if (intel_crtc->config->pch_pfit.enabled ||
5191             intel_crtc->config->pch_pfit.force_thru)
5192                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5193
5194         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5195                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5196
5197         return mask;
5198 }
5199
5200 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5201 {
5202         struct drm_device *dev = state->dev;
5203         struct drm_i915_private *dev_priv = dev->dev_private;
5204         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5205         struct intel_crtc *crtc;
5206
5207         /*
5208          * First get all needed power domains, then put all unneeded, to avoid
5209          * any unnecessary toggling of the power wells.
5210          */
5211         for_each_intel_crtc(dev, crtc) {
5212                 enum intel_display_power_domain domain;
5213
5214                 if (!crtc->base.state->enable)
5215                         continue;
5216
5217                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5218
5219                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5220                         intel_display_power_get(dev_priv, domain);
5221         }
5222
5223         if (dev_priv->display.modeset_commit_cdclk) {
5224                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5225
5226                 if (cdclk != dev_priv->cdclk_freq &&
5227                     !WARN_ON(!state->allow_modeset))
5228                         dev_priv->display.modeset_commit_cdclk(state);
5229         }
5230
5231         for_each_intel_crtc(dev, crtc) {
5232                 enum intel_display_power_domain domain;
5233
5234                 for_each_power_domain(domain, crtc->enabled_power_domains)
5235                         intel_display_power_put(dev_priv, domain);
5236
5237                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5238         }
5239
5240         intel_display_set_init_power(dev_priv, false);
5241 }
5242
5243 static void intel_update_max_cdclk(struct drm_device *dev)
5244 {
5245         struct drm_i915_private *dev_priv = dev->dev_private;
5246
5247         if (IS_SKYLAKE(dev)) {
5248                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5249
5250                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5251                         dev_priv->max_cdclk_freq = 675000;
5252                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5253                         dev_priv->max_cdclk_freq = 540000;
5254                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5255                         dev_priv->max_cdclk_freq = 450000;
5256                 else
5257                         dev_priv->max_cdclk_freq = 337500;
5258         } else if (IS_BROADWELL(dev))  {
5259                 /*
5260                  * FIXME with extra cooling we can allow
5261                  * 540 MHz for ULX and 675 Mhz for ULT.
5262                  * How can we know if extra cooling is
5263                  * available? PCI ID, VTB, something else?
5264                  */
5265                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5266                         dev_priv->max_cdclk_freq = 450000;
5267                 else if (IS_BDW_ULX(dev))
5268                         dev_priv->max_cdclk_freq = 450000;
5269                 else if (IS_BDW_ULT(dev))
5270                         dev_priv->max_cdclk_freq = 540000;
5271                 else
5272                         dev_priv->max_cdclk_freq = 675000;
5273         } else if (IS_CHERRYVIEW(dev)) {
5274                 dev_priv->max_cdclk_freq = 320000;
5275         } else if (IS_VALLEYVIEW(dev)) {
5276                 dev_priv->max_cdclk_freq = 400000;
5277         } else {
5278                 /* otherwise assume cdclk is fixed */
5279                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5280         }
5281
5282         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5283                          dev_priv->max_cdclk_freq);
5284 }
5285
5286 static void intel_update_cdclk(struct drm_device *dev)
5287 {
5288         struct drm_i915_private *dev_priv = dev->dev_private;
5289
5290         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5291         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5292                          dev_priv->cdclk_freq);
5293
5294         /*
5295          * Program the gmbus_freq based on the cdclk frequency.
5296          * BSpec erroneously claims we should aim for 4MHz, but
5297          * in fact 1MHz is the correct frequency.
5298          */
5299         if (IS_VALLEYVIEW(dev)) {
5300                 /*
5301                  * Program the gmbus_freq based on the cdclk frequency.
5302                  * BSpec erroneously claims we should aim for 4MHz, but
5303                  * in fact 1MHz is the correct frequency.
5304                  */
5305                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5306         }
5307
5308         if (dev_priv->max_cdclk_freq == 0)
5309                 intel_update_max_cdclk(dev);
5310 }
5311
5312 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5313 {
5314         struct drm_i915_private *dev_priv = dev->dev_private;
5315         uint32_t divider;
5316         uint32_t ratio;
5317         uint32_t current_freq;
5318         int ret;
5319
5320         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5321         switch (frequency) {
5322         case 144000:
5323                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5324                 ratio = BXT_DE_PLL_RATIO(60);
5325                 break;
5326         case 288000:
5327                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5328                 ratio = BXT_DE_PLL_RATIO(60);
5329                 break;
5330         case 384000:
5331                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5332                 ratio = BXT_DE_PLL_RATIO(60);
5333                 break;
5334         case 576000:
5335                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5336                 ratio = BXT_DE_PLL_RATIO(60);
5337                 break;
5338         case 624000:
5339                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5340                 ratio = BXT_DE_PLL_RATIO(65);
5341                 break;
5342         case 19200:
5343                 /*
5344                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5345                  * to suppress GCC warning.
5346                  */
5347                 ratio = 0;
5348                 divider = 0;
5349                 break;
5350         default:
5351                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5352
5353                 return;
5354         }
5355
5356         mutex_lock(&dev_priv->rps.hw_lock);
5357         /* Inform power controller of upcoming frequency change */
5358         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5359                                       0x80000000);
5360         mutex_unlock(&dev_priv->rps.hw_lock);
5361
5362         if (ret) {
5363                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5364                           ret, frequency);
5365                 return;
5366         }
5367
5368         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5369         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5370         current_freq = current_freq * 500 + 1000;
5371
5372         /*
5373          * DE PLL has to be disabled when
5374          * - setting to 19.2MHz (bypass, PLL isn't used)
5375          * - before setting to 624MHz (PLL needs toggling)
5376          * - before setting to any frequency from 624MHz (PLL needs toggling)
5377          */
5378         if (frequency == 19200 || frequency == 624000 ||
5379             current_freq == 624000) {
5380                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5381                 /* Timeout 200us */
5382                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5383                              1))
5384                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5385         }
5386
5387         if (frequency != 19200) {
5388                 uint32_t val;
5389
5390                 val = I915_READ(BXT_DE_PLL_CTL);
5391                 val &= ~BXT_DE_PLL_RATIO_MASK;
5392                 val |= ratio;
5393                 I915_WRITE(BXT_DE_PLL_CTL, val);
5394
5395                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5396                 /* Timeout 200us */
5397                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5398                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5399
5400                 val = I915_READ(CDCLK_CTL);
5401                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5402                 val |= divider;
5403                 /*
5404                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5405                  * enable otherwise.
5406                  */
5407                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5408                 if (frequency >= 500000)
5409                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5410
5411                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5412                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5413                 val |= (frequency - 1000) / 500;
5414                 I915_WRITE(CDCLK_CTL, val);
5415         }
5416
5417         mutex_lock(&dev_priv->rps.hw_lock);
5418         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5419                                       DIV_ROUND_UP(frequency, 25000));
5420         mutex_unlock(&dev_priv->rps.hw_lock);
5421
5422         if (ret) {
5423                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5424                           ret, frequency);
5425                 return;
5426         }
5427
5428         intel_update_cdclk(dev);
5429 }
5430
5431 void broxton_init_cdclk(struct drm_device *dev)
5432 {
5433         struct drm_i915_private *dev_priv = dev->dev_private;
5434         uint32_t val;
5435
5436         /*
5437          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5438          * or else the reset will hang because there is no PCH to respond.
5439          * Move the handshake programming to initialization sequence.
5440          * Previously was left up to BIOS.
5441          */
5442         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5443         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5444         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5445
5446         /* Enable PG1 for cdclk */
5447         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5448
5449         /* check if cd clock is enabled */
5450         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5451                 DRM_DEBUG_KMS("Display already initialized\n");
5452                 return;
5453         }
5454
5455         /*
5456          * FIXME:
5457          * - The initial CDCLK needs to be read from VBT.
5458          *   Need to make this change after VBT has changes for BXT.
5459          * - check if setting the max (or any) cdclk freq is really necessary
5460          *   here, it belongs to modeset time
5461          */
5462         broxton_set_cdclk(dev, 624000);
5463
5464         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5465         POSTING_READ(DBUF_CTL);
5466
5467         udelay(10);
5468
5469         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5470                 DRM_ERROR("DBuf power enable timeout!\n");
5471 }
5472
5473 void broxton_uninit_cdclk(struct drm_device *dev)
5474 {
5475         struct drm_i915_private *dev_priv = dev->dev_private;
5476
5477         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5478         POSTING_READ(DBUF_CTL);
5479
5480         udelay(10);
5481
5482         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5483                 DRM_ERROR("DBuf power disable timeout!\n");
5484
5485         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5486         broxton_set_cdclk(dev, 19200);
5487
5488         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5489 }
5490
5491 static const struct skl_cdclk_entry {
5492         unsigned int freq;
5493         unsigned int vco;
5494 } skl_cdclk_frequencies[] = {
5495         { .freq = 308570, .vco = 8640 },
5496         { .freq = 337500, .vco = 8100 },
5497         { .freq = 432000, .vco = 8640 },
5498         { .freq = 450000, .vco = 8100 },
5499         { .freq = 540000, .vco = 8100 },
5500         { .freq = 617140, .vco = 8640 },
5501         { .freq = 675000, .vco = 8100 },
5502 };
5503
5504 static unsigned int skl_cdclk_decimal(unsigned int freq)
5505 {
5506         return (freq - 1000) / 500;
5507 }
5508
5509 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5510 {
5511         unsigned int i;
5512
5513         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5514                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5515
5516                 if (e->freq == freq)
5517                         return e->vco;
5518         }
5519
5520         return 8100;
5521 }
5522
5523 static void
5524 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5525 {
5526         unsigned int min_freq;
5527         u32 val;
5528
5529         /* select the minimum CDCLK before enabling DPLL 0 */
5530         val = I915_READ(CDCLK_CTL);
5531         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5532         val |= CDCLK_FREQ_337_308;
5533
5534         if (required_vco == 8640)
5535                 min_freq = 308570;
5536         else
5537                 min_freq = 337500;
5538
5539         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5540
5541         I915_WRITE(CDCLK_CTL, val);
5542         POSTING_READ(CDCLK_CTL);
5543
5544         /*
5545          * We always enable DPLL0 with the lowest link rate possible, but still
5546          * taking into account the VCO required to operate the eDP panel at the
5547          * desired frequency. The usual DP link rates operate with a VCO of
5548          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5549          * The modeset code is responsible for the selection of the exact link
5550          * rate later on, with the constraint of choosing a frequency that
5551          * works with required_vco.
5552          */
5553         val = I915_READ(DPLL_CTRL1);
5554
5555         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5556                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5557         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5558         if (required_vco == 8640)
5559                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5560                                             SKL_DPLL0);
5561         else
5562                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5563                                             SKL_DPLL0);
5564
5565         I915_WRITE(DPLL_CTRL1, val);
5566         POSTING_READ(DPLL_CTRL1);
5567
5568         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5569
5570         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5571                 DRM_ERROR("DPLL0 not locked\n");
5572 }
5573
5574 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5575 {
5576         int ret;
5577         u32 val;
5578
5579         /* inform PCU we want to change CDCLK */
5580         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5581         mutex_lock(&dev_priv->rps.hw_lock);
5582         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5583         mutex_unlock(&dev_priv->rps.hw_lock);
5584
5585         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5586 }
5587
5588 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5589 {
5590         unsigned int i;
5591
5592         for (i = 0; i < 15; i++) {
5593                 if (skl_cdclk_pcu_ready(dev_priv))
5594                         return true;
5595                 udelay(10);
5596         }
5597
5598         return false;
5599 }
5600
5601 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5602 {
5603         struct drm_device *dev = dev_priv->dev;
5604         u32 freq_select, pcu_ack;
5605
5606         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5607
5608         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5609                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5610                 return;
5611         }
5612
5613         /* set CDCLK_CTL */
5614         switch(freq) {
5615         case 450000:
5616         case 432000:
5617                 freq_select = CDCLK_FREQ_450_432;
5618                 pcu_ack = 1;
5619                 break;
5620         case 540000:
5621                 freq_select = CDCLK_FREQ_540;
5622                 pcu_ack = 2;
5623                 break;
5624         case 308570:
5625         case 337500:
5626         default:
5627                 freq_select = CDCLK_FREQ_337_308;
5628                 pcu_ack = 0;
5629                 break;
5630         case 617140:
5631         case 675000:
5632                 freq_select = CDCLK_FREQ_675_617;
5633                 pcu_ack = 3;
5634                 break;
5635         }
5636
5637         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5638         POSTING_READ(CDCLK_CTL);
5639
5640         /* inform PCU of the change */
5641         mutex_lock(&dev_priv->rps.hw_lock);
5642         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5643         mutex_unlock(&dev_priv->rps.hw_lock);
5644
5645         intel_update_cdclk(dev);
5646 }
5647
5648 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5649 {
5650         /* disable DBUF power */
5651         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5652         POSTING_READ(DBUF_CTL);
5653
5654         udelay(10);
5655
5656         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5657                 DRM_ERROR("DBuf power disable timeout\n");
5658
5659         /* disable DPLL0 */
5660         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5661         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5662                 DRM_ERROR("Couldn't disable DPLL0\n");
5663
5664         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5665 }
5666
5667 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5668 {
5669         u32 val;
5670         unsigned int required_vco;
5671
5672         /* enable PCH reset handshake */
5673         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5674         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5675
5676         /* enable PG1 and Misc I/O */
5677         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5678
5679         /* DPLL0 already enabed !? */
5680         if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5681                 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5682                 return;
5683         }
5684
5685         /* enable DPLL0 */
5686         required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5687         skl_dpll0_enable(dev_priv, required_vco);
5688
5689         /* set CDCLK to the frequency the BIOS chose */
5690         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5691
5692         /* enable DBUF power */
5693         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5694         POSTING_READ(DBUF_CTL);
5695
5696         udelay(10);
5697
5698         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5699                 DRM_ERROR("DBuf power enable timeout\n");
5700 }
5701
5702 /* returns HPLL frequency in kHz */
5703 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5704 {
5705         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5706
5707         /* Obtain SKU information */
5708         mutex_lock(&dev_priv->sb_lock);
5709         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5710                 CCK_FUSE_HPLL_FREQ_MASK;
5711         mutex_unlock(&dev_priv->sb_lock);
5712
5713         return vco_freq[hpll_freq] * 1000;
5714 }
5715
5716 /* Adjust CDclk dividers to allow high res or save power if possible */
5717 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5718 {
5719         struct drm_i915_private *dev_priv = dev->dev_private;
5720         u32 val, cmd;
5721
5722         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5723                                         != dev_priv->cdclk_freq);
5724
5725         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5726                 cmd = 2;
5727         else if (cdclk == 266667)
5728                 cmd = 1;
5729         else
5730                 cmd = 0;
5731
5732         mutex_lock(&dev_priv->rps.hw_lock);
5733         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5734         val &= ~DSPFREQGUAR_MASK;
5735         val |= (cmd << DSPFREQGUAR_SHIFT);
5736         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5737         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5738                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5739                      50)) {
5740                 DRM_ERROR("timed out waiting for CDclk change\n");
5741         }
5742         mutex_unlock(&dev_priv->rps.hw_lock);
5743
5744         mutex_lock(&dev_priv->sb_lock);
5745
5746         if (cdclk == 400000) {
5747                 u32 divider;
5748
5749                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5750
5751                 /* adjust cdclk divider */
5752                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5753                 val &= ~DISPLAY_FREQUENCY_VALUES;
5754                 val |= divider;
5755                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5756
5757                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5758                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5759                              50))
5760                         DRM_ERROR("timed out waiting for CDclk change\n");
5761         }
5762
5763         /* adjust self-refresh exit latency value */
5764         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5765         val &= ~0x7f;
5766
5767         /*
5768          * For high bandwidth configs, we set a higher latency in the bunit
5769          * so that the core display fetch happens in time to avoid underruns.
5770          */
5771         if (cdclk == 400000)
5772                 val |= 4500 / 250; /* 4.5 usec */
5773         else
5774                 val |= 3000 / 250; /* 3.0 usec */
5775         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5776
5777         mutex_unlock(&dev_priv->sb_lock);
5778
5779         intel_update_cdclk(dev);
5780 }
5781
5782 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5783 {
5784         struct drm_i915_private *dev_priv = dev->dev_private;
5785         u32 val, cmd;
5786
5787         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5788                                                 != dev_priv->cdclk_freq);
5789
5790         switch (cdclk) {
5791         case 333333:
5792         case 320000:
5793         case 266667:
5794         case 200000:
5795                 break;
5796         default:
5797                 MISSING_CASE(cdclk);
5798                 return;
5799         }
5800
5801         /*
5802          * Specs are full of misinformation, but testing on actual
5803          * hardware has shown that we just need to write the desired
5804          * CCK divider into the Punit register.
5805          */
5806         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5807
5808         mutex_lock(&dev_priv->rps.hw_lock);
5809         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5810         val &= ~DSPFREQGUAR_MASK_CHV;
5811         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5812         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5813         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5814                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5815                      50)) {
5816                 DRM_ERROR("timed out waiting for CDclk change\n");
5817         }
5818         mutex_unlock(&dev_priv->rps.hw_lock);
5819
5820         intel_update_cdclk(dev);
5821 }
5822
5823 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5824                                  int max_pixclk)
5825 {
5826         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5827         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5828
5829         /*
5830          * Really only a few cases to deal with, as only 4 CDclks are supported:
5831          *   200MHz
5832          *   267MHz
5833          *   320/333MHz (depends on HPLL freq)
5834          *   400MHz (VLV only)
5835          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5836          * of the lower bin and adjust if needed.
5837          *
5838          * We seem to get an unstable or solid color picture at 200MHz.
5839          * Not sure what's wrong. For now use 200MHz only when all pipes
5840          * are off.
5841          */
5842         if (!IS_CHERRYVIEW(dev_priv) &&
5843             max_pixclk > freq_320*limit/100)
5844                 return 400000;
5845         else if (max_pixclk > 266667*limit/100)
5846                 return freq_320;
5847         else if (max_pixclk > 0)
5848                 return 266667;
5849         else
5850                 return 200000;
5851 }
5852
5853 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5854                               int max_pixclk)
5855 {
5856         /*
5857          * FIXME:
5858          * - remove the guardband, it's not needed on BXT
5859          * - set 19.2MHz bypass frequency if there are no active pipes
5860          */
5861         if (max_pixclk > 576000*9/10)
5862                 return 624000;
5863         else if (max_pixclk > 384000*9/10)
5864                 return 576000;
5865         else if (max_pixclk > 288000*9/10)
5866                 return 384000;
5867         else if (max_pixclk > 144000*9/10)
5868                 return 288000;
5869         else
5870                 return 144000;
5871 }
5872
5873 /* Compute the max pixel clock for new configuration. Uses atomic state if
5874  * that's non-NULL, look at current state otherwise. */
5875 static int intel_mode_max_pixclk(struct drm_device *dev,
5876                                  struct drm_atomic_state *state)
5877 {
5878         struct intel_crtc *intel_crtc;
5879         struct intel_crtc_state *crtc_state;
5880         int max_pixclk = 0;
5881
5882         for_each_intel_crtc(dev, intel_crtc) {
5883                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5884                 if (IS_ERR(crtc_state))
5885                         return PTR_ERR(crtc_state);
5886
5887                 if (!crtc_state->base.enable)
5888                         continue;
5889
5890                 max_pixclk = max(max_pixclk,
5891                                  crtc_state->base.adjusted_mode.crtc_clock);
5892         }
5893
5894         return max_pixclk;
5895 }
5896
5897 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5898 {
5899         struct drm_device *dev = state->dev;
5900         struct drm_i915_private *dev_priv = dev->dev_private;
5901         int max_pixclk = intel_mode_max_pixclk(dev, state);
5902
5903         if (max_pixclk < 0)
5904                 return max_pixclk;
5905
5906         to_intel_atomic_state(state)->cdclk =
5907                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5908
5909         return 0;
5910 }
5911
5912 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5913 {
5914         struct drm_device *dev = state->dev;
5915         struct drm_i915_private *dev_priv = dev->dev_private;
5916         int max_pixclk = intel_mode_max_pixclk(dev, state);
5917
5918         if (max_pixclk < 0)
5919                 return max_pixclk;
5920
5921         to_intel_atomic_state(state)->cdclk =
5922                 broxton_calc_cdclk(dev_priv, max_pixclk);
5923
5924         return 0;
5925 }
5926
5927 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5928 {
5929         unsigned int credits, default_credits;
5930
5931         if (IS_CHERRYVIEW(dev_priv))
5932                 default_credits = PFI_CREDIT(12);
5933         else
5934                 default_credits = PFI_CREDIT(8);
5935
5936         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5937                 /* CHV suggested value is 31 or 63 */
5938                 if (IS_CHERRYVIEW(dev_priv))
5939                         credits = PFI_CREDIT_63;
5940                 else
5941                         credits = PFI_CREDIT(15);
5942         } else {
5943                 credits = default_credits;
5944         }
5945
5946         /*
5947          * WA - write default credits before re-programming
5948          * FIXME: should we also set the resend bit here?
5949          */
5950         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5951                    default_credits);
5952
5953         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5954                    credits | PFI_CREDIT_RESEND);
5955
5956         /*
5957          * FIXME is this guaranteed to clear
5958          * immediately or should we poll for it?
5959          */
5960         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5961 }
5962
5963 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5964 {
5965         struct drm_device *dev = old_state->dev;
5966         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5967         struct drm_i915_private *dev_priv = dev->dev_private;
5968
5969         /*
5970          * FIXME: We can end up here with all power domains off, yet
5971          * with a CDCLK frequency other than the minimum. To account
5972          * for this take the PIPE-A power domain, which covers the HW
5973          * blocks needed for the following programming. This can be
5974          * removed once it's guaranteed that we get here either with
5975          * the minimum CDCLK set, or the required power domains
5976          * enabled.
5977          */
5978         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5979
5980         if (IS_CHERRYVIEW(dev))
5981                 cherryview_set_cdclk(dev, req_cdclk);
5982         else
5983                 valleyview_set_cdclk(dev, req_cdclk);
5984
5985         vlv_program_pfi_credits(dev_priv);
5986
5987         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5988 }
5989
5990 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5991 {
5992         struct drm_device *dev = crtc->dev;
5993         struct drm_i915_private *dev_priv = to_i915(dev);
5994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5995         struct intel_encoder *encoder;
5996         int pipe = intel_crtc->pipe;
5997         bool is_dsi;
5998
5999         if (WARN_ON(intel_crtc->active))
6000                 return;
6001
6002         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6003
6004         if (!is_dsi) {
6005                 if (IS_CHERRYVIEW(dev))
6006                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6007                 else
6008                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6009         }
6010
6011         if (intel_crtc->config->has_dp_encoder)
6012                 intel_dp_set_m_n(intel_crtc, M1_N1);
6013
6014         intel_set_pipe_timings(intel_crtc);
6015
6016         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6017                 struct drm_i915_private *dev_priv = dev->dev_private;
6018
6019                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6020                 I915_WRITE(CHV_CANVAS(pipe), 0);
6021         }
6022
6023         i9xx_set_pipeconf(intel_crtc);
6024
6025         intel_crtc->active = true;
6026
6027         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6028
6029         for_each_encoder_on_crtc(dev, crtc, encoder)
6030                 if (encoder->pre_pll_enable)
6031                         encoder->pre_pll_enable(encoder);
6032
6033         if (!is_dsi) {
6034                 if (IS_CHERRYVIEW(dev))
6035                         chv_enable_pll(intel_crtc, intel_crtc->config);
6036                 else
6037                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6038         }
6039
6040         for_each_encoder_on_crtc(dev, crtc, encoder)
6041                 if (encoder->pre_enable)
6042                         encoder->pre_enable(encoder);
6043
6044         i9xx_pfit_enable(intel_crtc);
6045
6046         intel_crtc_load_lut(crtc);
6047
6048         intel_enable_pipe(intel_crtc);
6049
6050         assert_vblank_disabled(crtc);
6051         drm_crtc_vblank_on(crtc);
6052
6053         for_each_encoder_on_crtc(dev, crtc, encoder)
6054                 encoder->enable(encoder);
6055 }
6056
6057 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6058 {
6059         struct drm_device *dev = crtc->base.dev;
6060         struct drm_i915_private *dev_priv = dev->dev_private;
6061
6062         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6063         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6064 }
6065
6066 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6067 {
6068         struct drm_device *dev = crtc->dev;
6069         struct drm_i915_private *dev_priv = to_i915(dev);
6070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6071         struct intel_encoder *encoder;
6072         int pipe = intel_crtc->pipe;
6073
6074         if (WARN_ON(intel_crtc->active))
6075                 return;
6076
6077         i9xx_set_pll_dividers(intel_crtc);
6078
6079         if (intel_crtc->config->has_dp_encoder)
6080                 intel_dp_set_m_n(intel_crtc, M1_N1);
6081
6082         intel_set_pipe_timings(intel_crtc);
6083
6084         i9xx_set_pipeconf(intel_crtc);
6085
6086         intel_crtc->active = true;
6087
6088         if (!IS_GEN2(dev))
6089                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6090
6091         for_each_encoder_on_crtc(dev, crtc, encoder)
6092                 if (encoder->pre_enable)
6093                         encoder->pre_enable(encoder);
6094
6095         i9xx_enable_pll(intel_crtc);
6096
6097         i9xx_pfit_enable(intel_crtc);
6098
6099         intel_crtc_load_lut(crtc);
6100
6101         intel_update_watermarks(crtc);
6102         intel_enable_pipe(intel_crtc);
6103
6104         assert_vblank_disabled(crtc);
6105         drm_crtc_vblank_on(crtc);
6106
6107         for_each_encoder_on_crtc(dev, crtc, encoder)
6108                 encoder->enable(encoder);
6109 }
6110
6111 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6112 {
6113         struct drm_device *dev = crtc->base.dev;
6114         struct drm_i915_private *dev_priv = dev->dev_private;
6115
6116         if (!crtc->config->gmch_pfit.control)
6117                 return;
6118
6119         assert_pipe_disabled(dev_priv, crtc->pipe);
6120
6121         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6122                          I915_READ(PFIT_CONTROL));
6123         I915_WRITE(PFIT_CONTROL, 0);
6124 }
6125
6126 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6127 {
6128         struct drm_device *dev = crtc->dev;
6129         struct drm_i915_private *dev_priv = dev->dev_private;
6130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6131         struct intel_encoder *encoder;
6132         int pipe = intel_crtc->pipe;
6133
6134         /*
6135          * On gen2 planes are double buffered but the pipe isn't, so we must
6136          * wait for planes to fully turn off before disabling the pipe.
6137          * We also need to wait on all gmch platforms because of the
6138          * self-refresh mode constraint explained above.
6139          */
6140         intel_wait_for_vblank(dev, pipe);
6141
6142         for_each_encoder_on_crtc(dev, crtc, encoder)
6143                 encoder->disable(encoder);
6144
6145         drm_crtc_vblank_off(crtc);
6146         assert_vblank_disabled(crtc);
6147
6148         intel_disable_pipe(intel_crtc);
6149
6150         i9xx_pfit_disable(intel_crtc);
6151
6152         for_each_encoder_on_crtc(dev, crtc, encoder)
6153                 if (encoder->post_disable)
6154                         encoder->post_disable(encoder);
6155
6156         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6157                 if (IS_CHERRYVIEW(dev))
6158                         chv_disable_pll(dev_priv, pipe);
6159                 else if (IS_VALLEYVIEW(dev))
6160                         vlv_disable_pll(dev_priv, pipe);
6161                 else
6162                         i9xx_disable_pll(intel_crtc);
6163         }
6164
6165         if (!IS_GEN2(dev))
6166                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6167
6168         intel_crtc->active = false;
6169         intel_update_watermarks(crtc);
6170 }
6171
6172 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6173 {
6174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6175         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6176         enum intel_display_power_domain domain;
6177         unsigned long domains;
6178
6179         if (!intel_crtc->active)
6180                 return;
6181
6182         if (to_intel_plane_state(crtc->primary->state)->visible) {
6183                 intel_crtc_wait_for_pending_flips(crtc);
6184                 intel_pre_disable_primary(crtc);
6185         }
6186
6187         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6188         dev_priv->display.crtc_disable(crtc);
6189
6190         domains = intel_crtc->enabled_power_domains;
6191         for_each_power_domain(domain, domains)
6192                 intel_display_power_put(dev_priv, domain);
6193         intel_crtc->enabled_power_domains = 0;
6194 }
6195
6196 /*
6197  * turn all crtc's off, but do not adjust state
6198  * This has to be paired with a call to intel_modeset_setup_hw_state.
6199  */
6200 void intel_display_suspend(struct drm_device *dev)
6201 {
6202         struct drm_crtc *crtc;
6203
6204         for_each_crtc(dev, crtc)
6205                 intel_crtc_disable_noatomic(crtc);
6206 }
6207
6208 /* Master function to enable/disable CRTC and corresponding power wells */
6209 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6210 {
6211         struct drm_device *dev = crtc->dev;
6212         struct drm_mode_config *config = &dev->mode_config;
6213         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6215         struct intel_crtc_state *pipe_config;
6216         struct drm_atomic_state *state;
6217         int ret;
6218
6219         if (enable == intel_crtc->active)
6220                 return 0;
6221
6222         if (enable && !crtc->state->enable)
6223                 return 0;
6224
6225         /* this function should be called with drm_modeset_lock_all for now */
6226         if (WARN_ON(!ctx))
6227                 return -EIO;
6228         lockdep_assert_held(&ctx->ww_ctx);
6229
6230         state = drm_atomic_state_alloc(dev);
6231         if (WARN_ON(!state))
6232                 return -ENOMEM;
6233
6234         state->acquire_ctx = ctx;
6235         state->allow_modeset = true;
6236
6237         pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6238         if (IS_ERR(pipe_config)) {
6239                 ret = PTR_ERR(pipe_config);
6240                 goto err;
6241         }
6242         pipe_config->base.active = enable;
6243
6244         ret = intel_set_mode(state);
6245         if (!ret)
6246                 return ret;
6247
6248 err:
6249         DRM_ERROR("Updating crtc active failed with %i\n", ret);
6250         drm_atomic_state_free(state);
6251         return ret;
6252 }
6253
6254 /**
6255  * Sets the power management mode of the pipe and plane.
6256  */
6257 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6258 {
6259         struct drm_device *dev = crtc->dev;
6260         struct intel_encoder *intel_encoder;
6261         bool enable = false;
6262
6263         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6264                 enable |= intel_encoder->connectors_active;
6265
6266         intel_crtc_control(crtc, enable);
6267 }
6268
6269 void intel_encoder_destroy(struct drm_encoder *encoder)
6270 {
6271         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6272
6273         drm_encoder_cleanup(encoder);
6274         kfree(intel_encoder);
6275 }
6276
6277 /* Simple dpms helper for encoders with just one connector, no cloning and only
6278  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6279  * state of the entire output pipe. */
6280 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6281 {
6282         if (mode == DRM_MODE_DPMS_ON) {
6283                 encoder->connectors_active = true;
6284
6285                 intel_crtc_update_dpms(encoder->base.crtc);
6286         } else {
6287                 encoder->connectors_active = false;
6288
6289                 intel_crtc_update_dpms(encoder->base.crtc);
6290         }
6291 }
6292
6293 /* Cross check the actual hw state with our own modeset state tracking (and it's
6294  * internal consistency). */
6295 static void intel_connector_check_state(struct intel_connector *connector)
6296 {
6297         if (connector->get_hw_state(connector)) {
6298                 struct intel_encoder *encoder = connector->encoder;
6299                 struct drm_crtc *crtc;
6300                 bool encoder_enabled;
6301                 enum pipe pipe;
6302
6303                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6304                               connector->base.base.id,
6305                               connector->base.name);
6306
6307                 /* there is no real hw state for MST connectors */
6308                 if (connector->mst_port)
6309                         return;
6310
6311                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6312                      "wrong connector dpms state\n");
6313                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6314                      "active connector not linked to encoder\n");
6315
6316                 if (encoder) {
6317                         I915_STATE_WARN(!encoder->connectors_active,
6318                              "encoder->connectors_active not set\n");
6319
6320                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6321                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6322                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
6323                                 return;
6324
6325                         crtc = encoder->base.crtc;
6326
6327                         I915_STATE_WARN(!crtc->state->enable,
6328                                         "crtc not enabled\n");
6329                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6330                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6331                              "encoder active on the wrong pipe\n");
6332                 }
6333         }
6334 }
6335
6336 int intel_connector_init(struct intel_connector *connector)
6337 {
6338         struct drm_connector_state *connector_state;
6339
6340         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6341         if (!connector_state)
6342                 return -ENOMEM;
6343
6344         connector->base.state = connector_state;
6345         return 0;
6346 }
6347
6348 struct intel_connector *intel_connector_alloc(void)
6349 {
6350         struct intel_connector *connector;
6351
6352         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6353         if (!connector)
6354                 return NULL;
6355
6356         if (intel_connector_init(connector) < 0) {
6357                 kfree(connector);
6358                 return NULL;
6359         }
6360
6361         return connector;
6362 }
6363
6364 /* Even simpler default implementation, if there's really no special case to
6365  * consider. */
6366 void intel_connector_dpms(struct drm_connector *connector, int mode)
6367 {
6368         /* All the simple cases only support two dpms states. */
6369         if (mode != DRM_MODE_DPMS_ON)
6370                 mode = DRM_MODE_DPMS_OFF;
6371
6372         if (mode == connector->dpms)
6373                 return;
6374
6375         connector->dpms = mode;
6376
6377         /* Only need to change hw state when actually enabled */
6378         if (connector->encoder)
6379                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6380
6381         intel_modeset_check_state(connector->dev);
6382 }
6383
6384 /* Simple connector->get_hw_state implementation for encoders that support only
6385  * one connector and no cloning and hence the encoder state determines the state
6386  * of the connector. */
6387 bool intel_connector_get_hw_state(struct intel_connector *connector)
6388 {
6389         enum pipe pipe = 0;
6390         struct intel_encoder *encoder = connector->encoder;
6391
6392         return encoder->get_hw_state(encoder, &pipe);
6393 }
6394
6395 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6396 {
6397         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6398                 return crtc_state->fdi_lanes;
6399
6400         return 0;
6401 }
6402
6403 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6404                                      struct intel_crtc_state *pipe_config)
6405 {
6406         struct drm_atomic_state *state = pipe_config->base.state;
6407         struct intel_crtc *other_crtc;
6408         struct intel_crtc_state *other_crtc_state;
6409
6410         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6411                       pipe_name(pipe), pipe_config->fdi_lanes);
6412         if (pipe_config->fdi_lanes > 4) {
6413                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6414                               pipe_name(pipe), pipe_config->fdi_lanes);
6415                 return -EINVAL;
6416         }
6417
6418         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6419                 if (pipe_config->fdi_lanes > 2) {
6420                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6421                                       pipe_config->fdi_lanes);
6422                         return -EINVAL;
6423                 } else {
6424                         return 0;
6425                 }
6426         }
6427
6428         if (INTEL_INFO(dev)->num_pipes == 2)
6429                 return 0;
6430
6431         /* Ivybridge 3 pipe is really complicated */
6432         switch (pipe) {
6433         case PIPE_A:
6434                 return 0;
6435         case PIPE_B:
6436                 if (pipe_config->fdi_lanes <= 2)
6437                         return 0;
6438
6439                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6440                 other_crtc_state =
6441                         intel_atomic_get_crtc_state(state, other_crtc);
6442                 if (IS_ERR(other_crtc_state))
6443                         return PTR_ERR(other_crtc_state);
6444
6445                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6446                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6447                                       pipe_name(pipe), pipe_config->fdi_lanes);
6448                         return -EINVAL;
6449                 }
6450                 return 0;
6451         case PIPE_C:
6452                 if (pipe_config->fdi_lanes > 2) {
6453                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6454                                       pipe_name(pipe), pipe_config->fdi_lanes);
6455                         return -EINVAL;
6456                 }
6457
6458                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6459                 other_crtc_state =
6460                         intel_atomic_get_crtc_state(state, other_crtc);
6461                 if (IS_ERR(other_crtc_state))
6462                         return PTR_ERR(other_crtc_state);
6463
6464                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6465                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6466                         return -EINVAL;
6467                 }
6468                 return 0;
6469         default:
6470                 BUG();
6471         }
6472 }
6473
6474 #define RETRY 1
6475 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6476                                        struct intel_crtc_state *pipe_config)
6477 {
6478         struct drm_device *dev = intel_crtc->base.dev;
6479         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6480         int lane, link_bw, fdi_dotclock, ret;
6481         bool needs_recompute = false;
6482
6483 retry:
6484         /* FDI is a binary signal running at ~2.7GHz, encoding
6485          * each output octet as 10 bits. The actual frequency
6486          * is stored as a divider into a 100MHz clock, and the
6487          * mode pixel clock is stored in units of 1KHz.
6488          * Hence the bw of each lane in terms of the mode signal
6489          * is:
6490          */
6491         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6492
6493         fdi_dotclock = adjusted_mode->crtc_clock;
6494
6495         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6496                                            pipe_config->pipe_bpp);
6497
6498         pipe_config->fdi_lanes = lane;
6499
6500         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6501                                link_bw, &pipe_config->fdi_m_n);
6502
6503         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6504                                        intel_crtc->pipe, pipe_config);
6505         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6506                 pipe_config->pipe_bpp -= 2*3;
6507                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6508                               pipe_config->pipe_bpp);
6509                 needs_recompute = true;
6510                 pipe_config->bw_constrained = true;
6511
6512                 goto retry;
6513         }
6514
6515         if (needs_recompute)
6516                 return RETRY;
6517
6518         return ret;
6519 }
6520
6521 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6522                                      struct intel_crtc_state *pipe_config)
6523 {
6524         if (pipe_config->pipe_bpp > 24)
6525                 return false;
6526
6527         /* HSW can handle pixel rate up to cdclk? */
6528         if (IS_HASWELL(dev_priv->dev))
6529                 return true;
6530
6531         /*
6532          * We compare against max which means we must take
6533          * the increased cdclk requirement into account when
6534          * calculating the new cdclk.
6535          *
6536          * Should measure whether using a lower cdclk w/o IPS
6537          */
6538         return ilk_pipe_pixel_rate(pipe_config) <=
6539                 dev_priv->max_cdclk_freq * 95 / 100;
6540 }
6541
6542 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6543                                    struct intel_crtc_state *pipe_config)
6544 {
6545         struct drm_device *dev = crtc->base.dev;
6546         struct drm_i915_private *dev_priv = dev->dev_private;
6547
6548         pipe_config->ips_enabled = i915.enable_ips &&
6549                 hsw_crtc_supports_ips(crtc) &&
6550                 pipe_config_supports_ips(dev_priv, pipe_config);
6551 }
6552
6553 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6554                                      struct intel_crtc_state *pipe_config)
6555 {
6556         struct drm_device *dev = crtc->base.dev;
6557         struct drm_i915_private *dev_priv = dev->dev_private;
6558         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6559
6560         /* FIXME should check pixel clock limits on all platforms */
6561         if (INTEL_INFO(dev)->gen < 4) {
6562                 int clock_limit = dev_priv->max_cdclk_freq;
6563
6564                 /*
6565                  * Enable pixel doubling when the dot clock
6566                  * is > 90% of the (display) core speed.
6567                  *
6568                  * GDG double wide on either pipe,
6569                  * otherwise pipe A only.
6570                  */
6571                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6572                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6573                         clock_limit *= 2;
6574                         pipe_config->double_wide = true;
6575                 }
6576
6577                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6578                         return -EINVAL;
6579         }
6580
6581         /*
6582          * Pipe horizontal size must be even in:
6583          * - DVO ganged mode
6584          * - LVDS dual channel mode
6585          * - Double wide pipe
6586          */
6587         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6588              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6589                 pipe_config->pipe_src_w &= ~1;
6590
6591         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6592          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6593          */
6594         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6595                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6596                 return -EINVAL;
6597
6598         if (HAS_IPS(dev))
6599                 hsw_compute_ips_config(crtc, pipe_config);
6600
6601         if (pipe_config->has_pch_encoder)
6602                 return ironlake_fdi_compute_config(crtc, pipe_config);
6603
6604         return 0;
6605 }
6606
6607 static int skylake_get_display_clock_speed(struct drm_device *dev)
6608 {
6609         struct drm_i915_private *dev_priv = to_i915(dev);
6610         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6611         uint32_t cdctl = I915_READ(CDCLK_CTL);
6612         uint32_t linkrate;
6613
6614         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6615                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6616
6617         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6618                 return 540000;
6619
6620         linkrate = (I915_READ(DPLL_CTRL1) &
6621                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6622
6623         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6624             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6625                 /* vco 8640 */
6626                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6627                 case CDCLK_FREQ_450_432:
6628                         return 432000;
6629                 case CDCLK_FREQ_337_308:
6630                         return 308570;
6631                 case CDCLK_FREQ_675_617:
6632                         return 617140;
6633                 default:
6634                         WARN(1, "Unknown cd freq selection\n");
6635                 }
6636         } else {
6637                 /* vco 8100 */
6638                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6639                 case CDCLK_FREQ_450_432:
6640                         return 450000;
6641                 case CDCLK_FREQ_337_308:
6642                         return 337500;
6643                 case CDCLK_FREQ_675_617:
6644                         return 675000;
6645                 default:
6646                         WARN(1, "Unknown cd freq selection\n");
6647                 }
6648         }
6649
6650         /* error case, do as if DPLL0 isn't enabled */
6651         return 24000;
6652 }
6653
6654 static int broxton_get_display_clock_speed(struct drm_device *dev)
6655 {
6656         struct drm_i915_private *dev_priv = to_i915(dev);
6657         uint32_t cdctl = I915_READ(CDCLK_CTL);
6658         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6659         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6660         int cdclk;
6661
6662         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6663                 return 19200;
6664
6665         cdclk = 19200 * pll_ratio / 2;
6666
6667         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6668         case BXT_CDCLK_CD2X_DIV_SEL_1:
6669                 return cdclk;  /* 576MHz or 624MHz */
6670         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6671                 return cdclk * 2 / 3; /* 384MHz */
6672         case BXT_CDCLK_CD2X_DIV_SEL_2:
6673                 return cdclk / 2; /* 288MHz */
6674         case BXT_CDCLK_CD2X_DIV_SEL_4:
6675                 return cdclk / 4; /* 144MHz */
6676         }
6677
6678         /* error case, do as if DE PLL isn't enabled */
6679         return 19200;
6680 }
6681
6682 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6683 {
6684         struct drm_i915_private *dev_priv = dev->dev_private;
6685         uint32_t lcpll = I915_READ(LCPLL_CTL);
6686         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6687
6688         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6689                 return 800000;
6690         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6691                 return 450000;
6692         else if (freq == LCPLL_CLK_FREQ_450)
6693                 return 450000;
6694         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6695                 return 540000;
6696         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6697                 return 337500;
6698         else
6699                 return 675000;
6700 }
6701
6702 static int haswell_get_display_clock_speed(struct drm_device *dev)
6703 {
6704         struct drm_i915_private *dev_priv = dev->dev_private;
6705         uint32_t lcpll = I915_READ(LCPLL_CTL);
6706         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6707
6708         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6709                 return 800000;
6710         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6711                 return 450000;
6712         else if (freq == LCPLL_CLK_FREQ_450)
6713                 return 450000;
6714         else if (IS_HSW_ULT(dev))
6715                 return 337500;
6716         else
6717                 return 540000;
6718 }
6719
6720 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6721 {
6722         struct drm_i915_private *dev_priv = dev->dev_private;
6723         u32 val;
6724         int divider;
6725
6726         if (dev_priv->hpll_freq == 0)
6727                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6728
6729         mutex_lock(&dev_priv->sb_lock);
6730         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6731         mutex_unlock(&dev_priv->sb_lock);
6732
6733         divider = val & DISPLAY_FREQUENCY_VALUES;
6734
6735         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6736              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6737              "cdclk change in progress\n");
6738
6739         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6740 }
6741
6742 static int ilk_get_display_clock_speed(struct drm_device *dev)
6743 {
6744         return 450000;
6745 }
6746
6747 static int i945_get_display_clock_speed(struct drm_device *dev)
6748 {
6749         return 400000;
6750 }
6751
6752 static int i915_get_display_clock_speed(struct drm_device *dev)
6753 {
6754         return 333333;
6755 }
6756
6757 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6758 {
6759         return 200000;
6760 }
6761
6762 static int pnv_get_display_clock_speed(struct drm_device *dev)
6763 {
6764         u16 gcfgc = 0;
6765
6766         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6767
6768         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6769         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6770                 return 266667;
6771         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6772                 return 333333;
6773         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6774                 return 444444;
6775         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6776                 return 200000;
6777         default:
6778                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6779         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6780                 return 133333;
6781         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6782                 return 166667;
6783         }
6784 }
6785
6786 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6787 {
6788         u16 gcfgc = 0;
6789
6790         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6791
6792         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6793                 return 133333;
6794         else {
6795                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6796                 case GC_DISPLAY_CLOCK_333_MHZ:
6797                         return 333333;
6798                 default:
6799                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6800                         return 190000;
6801                 }
6802         }
6803 }
6804
6805 static int i865_get_display_clock_speed(struct drm_device *dev)
6806 {
6807         return 266667;
6808 }
6809
6810 static int i85x_get_display_clock_speed(struct drm_device *dev)
6811 {
6812         u16 hpllcc = 0;
6813
6814         /*
6815          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6816          * encoding is different :(
6817          * FIXME is this the right way to detect 852GM/852GMV?
6818          */
6819         if (dev->pdev->revision == 0x1)
6820                 return 133333;
6821
6822         pci_bus_read_config_word(dev->pdev->bus,
6823                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6824
6825         /* Assume that the hardware is in the high speed state.  This
6826          * should be the default.
6827          */
6828         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6829         case GC_CLOCK_133_200:
6830         case GC_CLOCK_133_200_2:
6831         case GC_CLOCK_100_200:
6832                 return 200000;
6833         case GC_CLOCK_166_250:
6834                 return 250000;
6835         case GC_CLOCK_100_133:
6836                 return 133333;
6837         case GC_CLOCK_133_266:
6838         case GC_CLOCK_133_266_2:
6839         case GC_CLOCK_166_266:
6840                 return 266667;
6841         }
6842
6843         /* Shouldn't happen */
6844         return 0;
6845 }
6846
6847 static int i830_get_display_clock_speed(struct drm_device *dev)
6848 {
6849         return 133333;
6850 }
6851
6852 static unsigned int intel_hpll_vco(struct drm_device *dev)
6853 {
6854         struct drm_i915_private *dev_priv = dev->dev_private;
6855         static const unsigned int blb_vco[8] = {
6856                 [0] = 3200000,
6857                 [1] = 4000000,
6858                 [2] = 5333333,
6859                 [3] = 4800000,
6860                 [4] = 6400000,
6861         };
6862         static const unsigned int pnv_vco[8] = {
6863                 [0] = 3200000,
6864                 [1] = 4000000,
6865                 [2] = 5333333,
6866                 [3] = 4800000,
6867                 [4] = 2666667,
6868         };
6869         static const unsigned int cl_vco[8] = {
6870                 [0] = 3200000,
6871                 [1] = 4000000,
6872                 [2] = 5333333,
6873                 [3] = 6400000,
6874                 [4] = 3333333,
6875                 [5] = 3566667,
6876                 [6] = 4266667,
6877         };
6878         static const unsigned int elk_vco[8] = {
6879                 [0] = 3200000,
6880                 [1] = 4000000,
6881                 [2] = 5333333,
6882                 [3] = 4800000,
6883         };
6884         static const unsigned int ctg_vco[8] = {
6885                 [0] = 3200000,
6886                 [1] = 4000000,
6887                 [2] = 5333333,
6888                 [3] = 6400000,
6889                 [4] = 2666667,
6890                 [5] = 4266667,
6891         };
6892         const unsigned int *vco_table;
6893         unsigned int vco;
6894         uint8_t tmp = 0;
6895
6896         /* FIXME other chipsets? */
6897         if (IS_GM45(dev))
6898                 vco_table = ctg_vco;
6899         else if (IS_G4X(dev))
6900                 vco_table = elk_vco;
6901         else if (IS_CRESTLINE(dev))
6902                 vco_table = cl_vco;
6903         else if (IS_PINEVIEW(dev))
6904                 vco_table = pnv_vco;
6905         else if (IS_G33(dev))
6906                 vco_table = blb_vco;
6907         else
6908                 return 0;
6909
6910         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6911
6912         vco = vco_table[tmp & 0x7];
6913         if (vco == 0)
6914                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6915         else
6916                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6917
6918         return vco;
6919 }
6920
6921 static int gm45_get_display_clock_speed(struct drm_device *dev)
6922 {
6923         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6924         uint16_t tmp = 0;
6925
6926         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6927
6928         cdclk_sel = (tmp >> 12) & 0x1;
6929
6930         switch (vco) {
6931         case 2666667:
6932         case 4000000:
6933         case 5333333:
6934                 return cdclk_sel ? 333333 : 222222;
6935         case 3200000:
6936                 return cdclk_sel ? 320000 : 228571;
6937         default:
6938                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6939                 return 222222;
6940         }
6941 }
6942
6943 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6944 {
6945         static const uint8_t div_3200[] = { 16, 10,  8 };
6946         static const uint8_t div_4000[] = { 20, 12, 10 };
6947         static const uint8_t div_5333[] = { 24, 16, 14 };
6948         const uint8_t *div_table;
6949         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6950         uint16_t tmp = 0;
6951
6952         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6953
6954         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6955
6956         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6957                 goto fail;
6958
6959         switch (vco) {
6960         case 3200000:
6961                 div_table = div_3200;
6962                 break;
6963         case 4000000:
6964                 div_table = div_4000;
6965                 break;
6966         case 5333333:
6967                 div_table = div_5333;
6968                 break;
6969         default:
6970                 goto fail;
6971         }
6972
6973         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6974
6975 fail:
6976         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6977         return 200000;
6978 }
6979
6980 static int g33_get_display_clock_speed(struct drm_device *dev)
6981 {
6982         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6983         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6984         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6985         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6986         const uint8_t *div_table;
6987         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6988         uint16_t tmp = 0;
6989
6990         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6991
6992         cdclk_sel = (tmp >> 4) & 0x7;
6993
6994         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6995                 goto fail;
6996
6997         switch (vco) {
6998         case 3200000:
6999                 div_table = div_3200;
7000                 break;
7001         case 4000000:
7002                 div_table = div_4000;
7003                 break;
7004         case 4800000:
7005                 div_table = div_4800;
7006                 break;
7007         case 5333333:
7008                 div_table = div_5333;
7009                 break;
7010         default:
7011                 goto fail;
7012         }
7013
7014         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7015
7016 fail:
7017         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7018         return 190476;
7019 }
7020
7021 static void
7022 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7023 {
7024         while (*num > DATA_LINK_M_N_MASK ||
7025                *den > DATA_LINK_M_N_MASK) {
7026                 *num >>= 1;
7027                 *den >>= 1;
7028         }
7029 }
7030
7031 static void compute_m_n(unsigned int m, unsigned int n,
7032                         uint32_t *ret_m, uint32_t *ret_n)
7033 {
7034         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7035         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7036         intel_reduce_m_n_ratio(ret_m, ret_n);
7037 }
7038
7039 void
7040 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7041                        int pixel_clock, int link_clock,
7042                        struct intel_link_m_n *m_n)
7043 {
7044         m_n->tu = 64;
7045
7046         compute_m_n(bits_per_pixel * pixel_clock,
7047                     link_clock * nlanes * 8,
7048                     &m_n->gmch_m, &m_n->gmch_n);
7049
7050         compute_m_n(pixel_clock, link_clock,
7051                     &m_n->link_m, &m_n->link_n);
7052 }
7053
7054 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7055 {
7056         if (i915.panel_use_ssc >= 0)
7057                 return i915.panel_use_ssc != 0;
7058         return dev_priv->vbt.lvds_use_ssc
7059                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7060 }
7061
7062 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7063                            int num_connectors)
7064 {
7065         struct drm_device *dev = crtc_state->base.crtc->dev;
7066         struct drm_i915_private *dev_priv = dev->dev_private;
7067         int refclk;
7068
7069         WARN_ON(!crtc_state->base.state);
7070
7071         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7072                 refclk = 100000;
7073         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7074             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7075                 refclk = dev_priv->vbt.lvds_ssc_freq;
7076                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7077         } else if (!IS_GEN2(dev)) {
7078                 refclk = 96000;
7079         } else {
7080                 refclk = 48000;
7081         }
7082
7083         return refclk;
7084 }
7085
7086 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7087 {
7088         return (1 << dpll->n) << 16 | dpll->m2;
7089 }
7090
7091 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7092 {
7093         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7094 }
7095
7096 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7097                                      struct intel_crtc_state *crtc_state,
7098                                      intel_clock_t *reduced_clock)
7099 {
7100         struct drm_device *dev = crtc->base.dev;
7101         u32 fp, fp2 = 0;
7102
7103         if (IS_PINEVIEW(dev)) {
7104                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7105                 if (reduced_clock)
7106                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7107         } else {
7108                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7109                 if (reduced_clock)
7110                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7111         }
7112
7113         crtc_state->dpll_hw_state.fp0 = fp;
7114
7115         crtc->lowfreq_avail = false;
7116         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7117             reduced_clock) {
7118                 crtc_state->dpll_hw_state.fp1 = fp2;
7119                 crtc->lowfreq_avail = true;
7120         } else {
7121                 crtc_state->dpll_hw_state.fp1 = fp;
7122         }
7123 }
7124
7125 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7126                 pipe)
7127 {
7128         u32 reg_val;
7129
7130         /*
7131          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7132          * and set it to a reasonable value instead.
7133          */
7134         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7135         reg_val &= 0xffffff00;
7136         reg_val |= 0x00000030;
7137         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7138
7139         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7140         reg_val &= 0x8cffffff;
7141         reg_val = 0x8c000000;
7142         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7143
7144         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7145         reg_val &= 0xffffff00;
7146         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7147
7148         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7149         reg_val &= 0x00ffffff;
7150         reg_val |= 0xb0000000;
7151         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7152 }
7153
7154 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7155                                          struct intel_link_m_n *m_n)
7156 {
7157         struct drm_device *dev = crtc->base.dev;
7158         struct drm_i915_private *dev_priv = dev->dev_private;
7159         int pipe = crtc->pipe;
7160
7161         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7162         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7163         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7164         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7165 }
7166
7167 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7168                                          struct intel_link_m_n *m_n,
7169                                          struct intel_link_m_n *m2_n2)
7170 {
7171         struct drm_device *dev = crtc->base.dev;
7172         struct drm_i915_private *dev_priv = dev->dev_private;
7173         int pipe = crtc->pipe;
7174         enum transcoder transcoder = crtc->config->cpu_transcoder;
7175
7176         if (INTEL_INFO(dev)->gen >= 5) {
7177                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7178                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7179                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7180                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7181                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7182                  * for gen < 8) and if DRRS is supported (to make sure the
7183                  * registers are not unnecessarily accessed).
7184                  */
7185                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7186                         crtc->config->has_drrs) {
7187                         I915_WRITE(PIPE_DATA_M2(transcoder),
7188                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7189                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7190                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7191                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7192                 }
7193         } else {
7194                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7195                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7196                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7197                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7198         }
7199 }
7200
7201 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7202 {
7203         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7204
7205         if (m_n == M1_N1) {
7206                 dp_m_n = &crtc->config->dp_m_n;
7207                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7208         } else if (m_n == M2_N2) {
7209
7210                 /*
7211                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7212                  * needs to be programmed into M1_N1.
7213                  */
7214                 dp_m_n = &crtc->config->dp_m2_n2;
7215         } else {
7216                 DRM_ERROR("Unsupported divider value\n");
7217                 return;
7218         }
7219
7220         if (crtc->config->has_pch_encoder)
7221                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7222         else
7223                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7224 }
7225
7226 static void vlv_compute_dpll(struct intel_crtc *crtc,
7227                              struct intel_crtc_state *pipe_config)
7228 {
7229         u32 dpll, dpll_md;
7230
7231         /*
7232          * Enable DPIO clock input. We should never disable the reference
7233          * clock for pipe B, since VGA hotplug / manual detection depends
7234          * on it.
7235          */
7236         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7237                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7238         /* We should never disable this, set it here for state tracking */
7239         if (crtc->pipe == PIPE_B)
7240                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7241         dpll |= DPLL_VCO_ENABLE;
7242         pipe_config->dpll_hw_state.dpll = dpll;
7243
7244         dpll_md = (pipe_config->pixel_multiplier - 1)
7245                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7246         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7247 }
7248
7249 static void vlv_prepare_pll(struct intel_crtc *crtc,
7250                             const struct intel_crtc_state *pipe_config)
7251 {
7252         struct drm_device *dev = crtc->base.dev;
7253         struct drm_i915_private *dev_priv = dev->dev_private;
7254         int pipe = crtc->pipe;
7255         u32 mdiv;
7256         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7257         u32 coreclk, reg_val;
7258
7259         mutex_lock(&dev_priv->sb_lock);
7260
7261         bestn = pipe_config->dpll.n;
7262         bestm1 = pipe_config->dpll.m1;
7263         bestm2 = pipe_config->dpll.m2;
7264         bestp1 = pipe_config->dpll.p1;
7265         bestp2 = pipe_config->dpll.p2;
7266
7267         /* See eDP HDMI DPIO driver vbios notes doc */
7268
7269         /* PLL B needs special handling */
7270         if (pipe == PIPE_B)
7271                 vlv_pllb_recal_opamp(dev_priv, pipe);
7272
7273         /* Set up Tx target for periodic Rcomp update */
7274         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7275
7276         /* Disable target IRef on PLL */
7277         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7278         reg_val &= 0x00ffffff;
7279         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7280
7281         /* Disable fast lock */
7282         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7283
7284         /* Set idtafcrecal before PLL is enabled */
7285         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7286         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7287         mdiv |= ((bestn << DPIO_N_SHIFT));
7288         mdiv |= (1 << DPIO_K_SHIFT);
7289
7290         /*
7291          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7292          * but we don't support that).
7293          * Note: don't use the DAC post divider as it seems unstable.
7294          */
7295         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7296         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7297
7298         mdiv |= DPIO_ENABLE_CALIBRATION;
7299         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7300
7301         /* Set HBR and RBR LPF coefficients */
7302         if (pipe_config->port_clock == 162000 ||
7303             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7304             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7305                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7306                                  0x009f0003);
7307         else
7308                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7309                                  0x00d0000f);
7310
7311         if (pipe_config->has_dp_encoder) {
7312                 /* Use SSC source */
7313                 if (pipe == PIPE_A)
7314                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7315                                          0x0df40000);
7316                 else
7317                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7318                                          0x0df70000);
7319         } else { /* HDMI or VGA */
7320                 /* Use bend source */
7321                 if (pipe == PIPE_A)
7322                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7323                                          0x0df70000);
7324                 else
7325                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7326                                          0x0df40000);
7327         }
7328
7329         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7330         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7331         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7332             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7333                 coreclk |= 0x01000000;
7334         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7335
7336         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7337         mutex_unlock(&dev_priv->sb_lock);
7338 }
7339
7340 static void chv_compute_dpll(struct intel_crtc *crtc,
7341                              struct intel_crtc_state *pipe_config)
7342 {
7343         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7344                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7345                 DPLL_VCO_ENABLE;
7346         if (crtc->pipe != PIPE_A)
7347                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7348
7349         pipe_config->dpll_hw_state.dpll_md =
7350                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7351 }
7352
7353 static void chv_prepare_pll(struct intel_crtc *crtc,
7354                             const struct intel_crtc_state *pipe_config)
7355 {
7356         struct drm_device *dev = crtc->base.dev;
7357         struct drm_i915_private *dev_priv = dev->dev_private;
7358         int pipe = crtc->pipe;
7359         int dpll_reg = DPLL(crtc->pipe);
7360         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7361         u32 loopfilter, tribuf_calcntr;
7362         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7363         u32 dpio_val;
7364         int vco;
7365
7366         bestn = pipe_config->dpll.n;
7367         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7368         bestm1 = pipe_config->dpll.m1;
7369         bestm2 = pipe_config->dpll.m2 >> 22;
7370         bestp1 = pipe_config->dpll.p1;
7371         bestp2 = pipe_config->dpll.p2;
7372         vco = pipe_config->dpll.vco;
7373         dpio_val = 0;
7374         loopfilter = 0;
7375
7376         /*
7377          * Enable Refclk and SSC
7378          */
7379         I915_WRITE(dpll_reg,
7380                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7381
7382         mutex_lock(&dev_priv->sb_lock);
7383
7384         /* p1 and p2 divider */
7385         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7386                         5 << DPIO_CHV_S1_DIV_SHIFT |
7387                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7388                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7389                         1 << DPIO_CHV_K_DIV_SHIFT);
7390
7391         /* Feedback post-divider - m2 */
7392         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7393
7394         /* Feedback refclk divider - n and m1 */
7395         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7396                         DPIO_CHV_M1_DIV_BY_2 |
7397                         1 << DPIO_CHV_N_DIV_SHIFT);
7398
7399         /* M2 fraction division */
7400         if (bestm2_frac)
7401                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7402
7403         /* M2 fraction division enable */
7404         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7405         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7406         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7407         if (bestm2_frac)
7408                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7409         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7410
7411         /* Program digital lock detect threshold */
7412         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7413         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7414                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7415         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7416         if (!bestm2_frac)
7417                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7418         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7419
7420         /* Loop filter */
7421         if (vco == 5400000) {
7422                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7423                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7424                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7425                 tribuf_calcntr = 0x9;
7426         } else if (vco <= 6200000) {
7427                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7428                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7429                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7430                 tribuf_calcntr = 0x9;
7431         } else if (vco <= 6480000) {
7432                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7433                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7434                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7435                 tribuf_calcntr = 0x8;
7436         } else {
7437                 /* Not supported. Apply the same limits as in the max case */
7438                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7439                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7440                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7441                 tribuf_calcntr = 0;
7442         }
7443         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7444
7445         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7446         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7447         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7448         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7449
7450         /* AFC Recal */
7451         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7452                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7453                         DPIO_AFC_RECAL);
7454
7455         mutex_unlock(&dev_priv->sb_lock);
7456 }
7457
7458 /**
7459  * vlv_force_pll_on - forcibly enable just the PLL
7460  * @dev_priv: i915 private structure
7461  * @pipe: pipe PLL to enable
7462  * @dpll: PLL configuration
7463  *
7464  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7465  * in cases where we need the PLL enabled even when @pipe is not going to
7466  * be enabled.
7467  */
7468 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7469                       const struct dpll *dpll)
7470 {
7471         struct intel_crtc *crtc =
7472                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7473         struct intel_crtc_state pipe_config = {
7474                 .base.crtc = &crtc->base,
7475                 .pixel_multiplier = 1,
7476                 .dpll = *dpll,
7477         };
7478
7479         if (IS_CHERRYVIEW(dev)) {
7480                 chv_compute_dpll(crtc, &pipe_config);
7481                 chv_prepare_pll(crtc, &pipe_config);
7482                 chv_enable_pll(crtc, &pipe_config);
7483         } else {
7484                 vlv_compute_dpll(crtc, &pipe_config);
7485                 vlv_prepare_pll(crtc, &pipe_config);
7486                 vlv_enable_pll(crtc, &pipe_config);
7487         }
7488 }
7489
7490 /**
7491  * vlv_force_pll_off - forcibly disable just the PLL
7492  * @dev_priv: i915 private structure
7493  * @pipe: pipe PLL to disable
7494  *
7495  * Disable the PLL for @pipe. To be used in cases where we need
7496  * the PLL enabled even when @pipe is not going to be enabled.
7497  */
7498 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7499 {
7500         if (IS_CHERRYVIEW(dev))
7501                 chv_disable_pll(to_i915(dev), pipe);
7502         else
7503                 vlv_disable_pll(to_i915(dev), pipe);
7504 }
7505
7506 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7507                               struct intel_crtc_state *crtc_state,
7508                               intel_clock_t *reduced_clock,
7509                               int num_connectors)
7510 {
7511         struct drm_device *dev = crtc->base.dev;
7512         struct drm_i915_private *dev_priv = dev->dev_private;
7513         u32 dpll;
7514         bool is_sdvo;
7515         struct dpll *clock = &crtc_state->dpll;
7516
7517         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7518
7519         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7520                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7521
7522         dpll = DPLL_VGA_MODE_DIS;
7523
7524         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7525                 dpll |= DPLLB_MODE_LVDS;
7526         else
7527                 dpll |= DPLLB_MODE_DAC_SERIAL;
7528
7529         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7530                 dpll |= (crtc_state->pixel_multiplier - 1)
7531                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7532         }
7533
7534         if (is_sdvo)
7535                 dpll |= DPLL_SDVO_HIGH_SPEED;
7536
7537         if (crtc_state->has_dp_encoder)
7538                 dpll |= DPLL_SDVO_HIGH_SPEED;
7539
7540         /* compute bitmask from p1 value */
7541         if (IS_PINEVIEW(dev))
7542                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7543         else {
7544                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7545                 if (IS_G4X(dev) && reduced_clock)
7546                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7547         }
7548         switch (clock->p2) {
7549         case 5:
7550                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7551                 break;
7552         case 7:
7553                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7554                 break;
7555         case 10:
7556                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7557                 break;
7558         case 14:
7559                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7560                 break;
7561         }
7562         if (INTEL_INFO(dev)->gen >= 4)
7563                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7564
7565         if (crtc_state->sdvo_tv_clock)
7566                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7567         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7568                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7569                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7570         else
7571                 dpll |= PLL_REF_INPUT_DREFCLK;
7572
7573         dpll |= DPLL_VCO_ENABLE;
7574         crtc_state->dpll_hw_state.dpll = dpll;
7575
7576         if (INTEL_INFO(dev)->gen >= 4) {
7577                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7578                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7579                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7580         }
7581 }
7582
7583 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7584                               struct intel_crtc_state *crtc_state,
7585                               intel_clock_t *reduced_clock,
7586                               int num_connectors)
7587 {
7588         struct drm_device *dev = crtc->base.dev;
7589         struct drm_i915_private *dev_priv = dev->dev_private;
7590         u32 dpll;
7591         struct dpll *clock = &crtc_state->dpll;
7592
7593         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7594
7595         dpll = DPLL_VGA_MODE_DIS;
7596
7597         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7598                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7599         } else {
7600                 if (clock->p1 == 2)
7601                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7602                 else
7603                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7604                 if (clock->p2 == 4)
7605                         dpll |= PLL_P2_DIVIDE_BY_4;
7606         }
7607
7608         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7609                 dpll |= DPLL_DVO_2X_MODE;
7610
7611         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7612                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7613                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7614         else
7615                 dpll |= PLL_REF_INPUT_DREFCLK;
7616
7617         dpll |= DPLL_VCO_ENABLE;
7618         crtc_state->dpll_hw_state.dpll = dpll;
7619 }
7620
7621 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7622 {
7623         struct drm_device *dev = intel_crtc->base.dev;
7624         struct drm_i915_private *dev_priv = dev->dev_private;
7625         enum pipe pipe = intel_crtc->pipe;
7626         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7627         struct drm_display_mode *adjusted_mode =
7628                 &intel_crtc->config->base.adjusted_mode;
7629         uint32_t crtc_vtotal, crtc_vblank_end;
7630         int vsyncshift = 0;
7631
7632         /* We need to be careful not to changed the adjusted mode, for otherwise
7633          * the hw state checker will get angry at the mismatch. */
7634         crtc_vtotal = adjusted_mode->crtc_vtotal;
7635         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7636
7637         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7638                 /* the chip adds 2 halflines automatically */
7639                 crtc_vtotal -= 1;
7640                 crtc_vblank_end -= 1;
7641
7642                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7643                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7644                 else
7645                         vsyncshift = adjusted_mode->crtc_hsync_start -
7646                                 adjusted_mode->crtc_htotal / 2;
7647                 if (vsyncshift < 0)
7648                         vsyncshift += adjusted_mode->crtc_htotal;
7649         }
7650
7651         if (INTEL_INFO(dev)->gen > 3)
7652                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7653
7654         I915_WRITE(HTOTAL(cpu_transcoder),
7655                    (adjusted_mode->crtc_hdisplay - 1) |
7656                    ((adjusted_mode->crtc_htotal - 1) << 16));
7657         I915_WRITE(HBLANK(cpu_transcoder),
7658                    (adjusted_mode->crtc_hblank_start - 1) |
7659                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7660         I915_WRITE(HSYNC(cpu_transcoder),
7661                    (adjusted_mode->crtc_hsync_start - 1) |
7662                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7663
7664         I915_WRITE(VTOTAL(cpu_transcoder),
7665                    (adjusted_mode->crtc_vdisplay - 1) |
7666                    ((crtc_vtotal - 1) << 16));
7667         I915_WRITE(VBLANK(cpu_transcoder),
7668                    (adjusted_mode->crtc_vblank_start - 1) |
7669                    ((crtc_vblank_end - 1) << 16));
7670         I915_WRITE(VSYNC(cpu_transcoder),
7671                    (adjusted_mode->crtc_vsync_start - 1) |
7672                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7673
7674         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7675          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7676          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7677          * bits. */
7678         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7679             (pipe == PIPE_B || pipe == PIPE_C))
7680                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7681
7682         /* pipesrc controls the size that is scaled from, which should
7683          * always be the user's requested size.
7684          */
7685         I915_WRITE(PIPESRC(pipe),
7686                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7687                    (intel_crtc->config->pipe_src_h - 1));
7688 }
7689
7690 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7691                                    struct intel_crtc_state *pipe_config)
7692 {
7693         struct drm_device *dev = crtc->base.dev;
7694         struct drm_i915_private *dev_priv = dev->dev_private;
7695         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7696         uint32_t tmp;
7697
7698         tmp = I915_READ(HTOTAL(cpu_transcoder));
7699         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7700         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7701         tmp = I915_READ(HBLANK(cpu_transcoder));
7702         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7703         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7704         tmp = I915_READ(HSYNC(cpu_transcoder));
7705         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7706         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7707
7708         tmp = I915_READ(VTOTAL(cpu_transcoder));
7709         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7710         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7711         tmp = I915_READ(VBLANK(cpu_transcoder));
7712         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7713         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7714         tmp = I915_READ(VSYNC(cpu_transcoder));
7715         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7716         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7717
7718         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7719                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7720                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7721                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7722         }
7723
7724         tmp = I915_READ(PIPESRC(crtc->pipe));
7725         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7726         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7727
7728         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7729         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7730 }
7731
7732 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7733                                  struct intel_crtc_state *pipe_config)
7734 {
7735         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7736         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7737         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7738         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7739
7740         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7741         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7742         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7743         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7744
7745         mode->flags = pipe_config->base.adjusted_mode.flags;
7746
7747         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7748         mode->flags |= pipe_config->base.adjusted_mode.flags;
7749 }
7750
7751 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7752 {
7753         struct drm_device *dev = intel_crtc->base.dev;
7754         struct drm_i915_private *dev_priv = dev->dev_private;
7755         uint32_t pipeconf;
7756
7757         pipeconf = 0;
7758
7759         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7760             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7761                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7762
7763         if (intel_crtc->config->double_wide)
7764                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7765
7766         /* only g4x and later have fancy bpc/dither controls */
7767         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7768                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7769                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7770                         pipeconf |= PIPECONF_DITHER_EN |
7771                                     PIPECONF_DITHER_TYPE_SP;
7772
7773                 switch (intel_crtc->config->pipe_bpp) {
7774                 case 18:
7775                         pipeconf |= PIPECONF_6BPC;
7776                         break;
7777                 case 24:
7778                         pipeconf |= PIPECONF_8BPC;
7779                         break;
7780                 case 30:
7781                         pipeconf |= PIPECONF_10BPC;
7782                         break;
7783                 default:
7784                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7785                         BUG();
7786                 }
7787         }
7788
7789         if (HAS_PIPE_CXSR(dev)) {
7790                 if (intel_crtc->lowfreq_avail) {
7791                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7792                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7793                 } else {
7794                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7795                 }
7796         }
7797
7798         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7799                 if (INTEL_INFO(dev)->gen < 4 ||
7800                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7801                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7802                 else
7803                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7804         } else
7805                 pipeconf |= PIPECONF_PROGRESSIVE;
7806
7807         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7808                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7809
7810         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7811         POSTING_READ(PIPECONF(intel_crtc->pipe));
7812 }
7813
7814 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7815                                    struct intel_crtc_state *crtc_state)
7816 {
7817         struct drm_device *dev = crtc->base.dev;
7818         struct drm_i915_private *dev_priv = dev->dev_private;
7819         int refclk, num_connectors = 0;
7820         intel_clock_t clock;
7821         bool ok;
7822         bool is_dsi = false;
7823         struct intel_encoder *encoder;
7824         const intel_limit_t *limit;
7825         struct drm_atomic_state *state = crtc_state->base.state;
7826         struct drm_connector *connector;
7827         struct drm_connector_state *connector_state;
7828         int i;
7829
7830         memset(&crtc_state->dpll_hw_state, 0,
7831                sizeof(crtc_state->dpll_hw_state));
7832
7833         for_each_connector_in_state(state, connector, connector_state, i) {
7834                 if (connector_state->crtc != &crtc->base)
7835                         continue;
7836
7837                 encoder = to_intel_encoder(connector_state->best_encoder);
7838
7839                 switch (encoder->type) {
7840                 case INTEL_OUTPUT_DSI:
7841                         is_dsi = true;
7842                         break;
7843                 default:
7844                         break;
7845                 }
7846
7847                 num_connectors++;
7848         }
7849
7850         if (is_dsi)
7851                 return 0;
7852
7853         if (!crtc_state->clock_set) {
7854                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7855
7856                 /*
7857                  * Returns a set of divisors for the desired target clock with
7858                  * the given refclk, or FALSE.  The returned values represent
7859                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7860                  * 2) / p1 / p2.
7861                  */
7862                 limit = intel_limit(crtc_state, refclk);
7863                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7864                                                  crtc_state->port_clock,
7865                                                  refclk, NULL, &clock);
7866                 if (!ok) {
7867                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7868                         return -EINVAL;
7869                 }
7870
7871                 /* Compat-code for transition, will disappear. */
7872                 crtc_state->dpll.n = clock.n;
7873                 crtc_state->dpll.m1 = clock.m1;
7874                 crtc_state->dpll.m2 = clock.m2;
7875                 crtc_state->dpll.p1 = clock.p1;
7876                 crtc_state->dpll.p2 = clock.p2;
7877         }
7878
7879         if (IS_GEN2(dev)) {
7880                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7881                                   num_connectors);
7882         } else if (IS_CHERRYVIEW(dev)) {
7883                 chv_compute_dpll(crtc, crtc_state);
7884         } else if (IS_VALLEYVIEW(dev)) {
7885                 vlv_compute_dpll(crtc, crtc_state);
7886         } else {
7887                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7888                                   num_connectors);
7889         }
7890
7891         return 0;
7892 }
7893
7894 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7895                                  struct intel_crtc_state *pipe_config)
7896 {
7897         struct drm_device *dev = crtc->base.dev;
7898         struct drm_i915_private *dev_priv = dev->dev_private;
7899         uint32_t tmp;
7900
7901         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7902                 return;
7903
7904         tmp = I915_READ(PFIT_CONTROL);
7905         if (!(tmp & PFIT_ENABLE))
7906                 return;
7907
7908         /* Check whether the pfit is attached to our pipe. */
7909         if (INTEL_INFO(dev)->gen < 4) {
7910                 if (crtc->pipe != PIPE_B)
7911                         return;
7912         } else {
7913                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7914                         return;
7915         }
7916
7917         pipe_config->gmch_pfit.control = tmp;
7918         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7919         if (INTEL_INFO(dev)->gen < 5)
7920                 pipe_config->gmch_pfit.lvds_border_bits =
7921                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7922 }
7923
7924 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7925                                struct intel_crtc_state *pipe_config)
7926 {
7927         struct drm_device *dev = crtc->base.dev;
7928         struct drm_i915_private *dev_priv = dev->dev_private;
7929         int pipe = pipe_config->cpu_transcoder;
7930         intel_clock_t clock;
7931         u32 mdiv;
7932         int refclk = 100000;
7933
7934         /* In case of MIPI DPLL will not even be used */
7935         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7936                 return;
7937
7938         mutex_lock(&dev_priv->sb_lock);
7939         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7940         mutex_unlock(&dev_priv->sb_lock);
7941
7942         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7943         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7944         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7945         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7946         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7947
7948         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7949 }
7950
7951 static void
7952 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7953                               struct intel_initial_plane_config *plane_config)
7954 {
7955         struct drm_device *dev = crtc->base.dev;
7956         struct drm_i915_private *dev_priv = dev->dev_private;
7957         u32 val, base, offset;
7958         int pipe = crtc->pipe, plane = crtc->plane;
7959         int fourcc, pixel_format;
7960         unsigned int aligned_height;
7961         struct drm_framebuffer *fb;
7962         struct intel_framebuffer *intel_fb;
7963
7964         val = I915_READ(DSPCNTR(plane));
7965         if (!(val & DISPLAY_PLANE_ENABLE))
7966                 return;
7967
7968         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7969         if (!intel_fb) {
7970                 DRM_DEBUG_KMS("failed to alloc fb\n");
7971                 return;
7972         }
7973
7974         fb = &intel_fb->base;
7975
7976         if (INTEL_INFO(dev)->gen >= 4) {
7977                 if (val & DISPPLANE_TILED) {
7978                         plane_config->tiling = I915_TILING_X;
7979                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7980                 }
7981         }
7982
7983         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7984         fourcc = i9xx_format_to_fourcc(pixel_format);
7985         fb->pixel_format = fourcc;
7986         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7987
7988         if (INTEL_INFO(dev)->gen >= 4) {
7989                 if (plane_config->tiling)
7990                         offset = I915_READ(DSPTILEOFF(plane));
7991                 else
7992                         offset = I915_READ(DSPLINOFF(plane));
7993                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7994         } else {
7995                 base = I915_READ(DSPADDR(plane));
7996         }
7997         plane_config->base = base;
7998
7999         val = I915_READ(PIPESRC(pipe));
8000         fb->width = ((val >> 16) & 0xfff) + 1;
8001         fb->height = ((val >> 0) & 0xfff) + 1;
8002
8003         val = I915_READ(DSPSTRIDE(pipe));
8004         fb->pitches[0] = val & 0xffffffc0;
8005
8006         aligned_height = intel_fb_align_height(dev, fb->height,
8007                                                fb->pixel_format,
8008                                                fb->modifier[0]);
8009
8010         plane_config->size = fb->pitches[0] * aligned_height;
8011
8012         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8013                       pipe_name(pipe), plane, fb->width, fb->height,
8014                       fb->bits_per_pixel, base, fb->pitches[0],
8015                       plane_config->size);
8016
8017         plane_config->fb = intel_fb;
8018 }
8019
8020 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8021                                struct intel_crtc_state *pipe_config)
8022 {
8023         struct drm_device *dev = crtc->base.dev;
8024         struct drm_i915_private *dev_priv = dev->dev_private;
8025         int pipe = pipe_config->cpu_transcoder;
8026         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8027         intel_clock_t clock;
8028         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8029         int refclk = 100000;
8030
8031         mutex_lock(&dev_priv->sb_lock);
8032         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8033         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8034         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8035         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8036         mutex_unlock(&dev_priv->sb_lock);
8037
8038         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8039         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8040         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8041         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8042         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8043
8044         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8045 }
8046
8047 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8048                                  struct intel_crtc_state *pipe_config)
8049 {
8050         struct drm_device *dev = crtc->base.dev;
8051         struct drm_i915_private *dev_priv = dev->dev_private;
8052         uint32_t tmp;
8053
8054         if (!intel_display_power_is_enabled(dev_priv,
8055                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8056                 return false;
8057
8058         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8059         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8060
8061         tmp = I915_READ(PIPECONF(crtc->pipe));
8062         if (!(tmp & PIPECONF_ENABLE))
8063                 return false;
8064
8065         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8066                 switch (tmp & PIPECONF_BPC_MASK) {
8067                 case PIPECONF_6BPC:
8068                         pipe_config->pipe_bpp = 18;
8069                         break;
8070                 case PIPECONF_8BPC:
8071                         pipe_config->pipe_bpp = 24;
8072                         break;
8073                 case PIPECONF_10BPC:
8074                         pipe_config->pipe_bpp = 30;
8075                         break;
8076                 default:
8077                         break;
8078                 }
8079         }
8080
8081         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8082                 pipe_config->limited_color_range = true;
8083
8084         if (INTEL_INFO(dev)->gen < 4)
8085                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8086
8087         intel_get_pipe_timings(crtc, pipe_config);
8088
8089         i9xx_get_pfit_config(crtc, pipe_config);
8090
8091         if (INTEL_INFO(dev)->gen >= 4) {
8092                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8093                 pipe_config->pixel_multiplier =
8094                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8095                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8096                 pipe_config->dpll_hw_state.dpll_md = tmp;
8097         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8098                 tmp = I915_READ(DPLL(crtc->pipe));
8099                 pipe_config->pixel_multiplier =
8100                         ((tmp & SDVO_MULTIPLIER_MASK)
8101                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8102         } else {
8103                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8104                  * port and will be fixed up in the encoder->get_config
8105                  * function. */
8106                 pipe_config->pixel_multiplier = 1;
8107         }
8108         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8109         if (!IS_VALLEYVIEW(dev)) {
8110                 /*
8111                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8112                  * on 830. Filter it out here so that we don't
8113                  * report errors due to that.
8114                  */
8115                 if (IS_I830(dev))
8116                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8117
8118                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8119                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8120         } else {
8121                 /* Mask out read-only status bits. */
8122                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8123                                                      DPLL_PORTC_READY_MASK |
8124                                                      DPLL_PORTB_READY_MASK);
8125         }
8126
8127         if (IS_CHERRYVIEW(dev))
8128                 chv_crtc_clock_get(crtc, pipe_config);
8129         else if (IS_VALLEYVIEW(dev))
8130                 vlv_crtc_clock_get(crtc, pipe_config);
8131         else
8132                 i9xx_crtc_clock_get(crtc, pipe_config);
8133
8134         return true;
8135 }
8136
8137 static void ironlake_init_pch_refclk(struct drm_device *dev)
8138 {
8139         struct drm_i915_private *dev_priv = dev->dev_private;
8140         struct intel_encoder *encoder;
8141         u32 val, final;
8142         bool has_lvds = false;
8143         bool has_cpu_edp = false;
8144         bool has_panel = false;
8145         bool has_ck505 = false;
8146         bool can_ssc = false;
8147
8148         /* We need to take the global config into account */
8149         for_each_intel_encoder(dev, encoder) {
8150                 switch (encoder->type) {
8151                 case INTEL_OUTPUT_LVDS:
8152                         has_panel = true;
8153                         has_lvds = true;
8154                         break;
8155                 case INTEL_OUTPUT_EDP:
8156                         has_panel = true;
8157                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8158                                 has_cpu_edp = true;
8159                         break;
8160                 default:
8161                         break;
8162                 }
8163         }
8164
8165         if (HAS_PCH_IBX(dev)) {
8166                 has_ck505 = dev_priv->vbt.display_clock_mode;
8167                 can_ssc = has_ck505;
8168         } else {
8169                 has_ck505 = false;
8170                 can_ssc = true;
8171         }
8172
8173         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8174                       has_panel, has_lvds, has_ck505);
8175
8176         /* Ironlake: try to setup display ref clock before DPLL
8177          * enabling. This is only under driver's control after
8178          * PCH B stepping, previous chipset stepping should be
8179          * ignoring this setting.
8180          */
8181         val = I915_READ(PCH_DREF_CONTROL);
8182
8183         /* As we must carefully and slowly disable/enable each source in turn,
8184          * compute the final state we want first and check if we need to
8185          * make any changes at all.
8186          */
8187         final = val;
8188         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8189         if (has_ck505)
8190                 final |= DREF_NONSPREAD_CK505_ENABLE;
8191         else
8192                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8193
8194         final &= ~DREF_SSC_SOURCE_MASK;
8195         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8196         final &= ~DREF_SSC1_ENABLE;
8197
8198         if (has_panel) {
8199                 final |= DREF_SSC_SOURCE_ENABLE;
8200
8201                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8202                         final |= DREF_SSC1_ENABLE;
8203
8204                 if (has_cpu_edp) {
8205                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8206                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8207                         else
8208                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8209                 } else
8210                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8211         } else {
8212                 final |= DREF_SSC_SOURCE_DISABLE;
8213                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8214         }
8215
8216         if (final == val)
8217                 return;
8218
8219         /* Always enable nonspread source */
8220         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8221
8222         if (has_ck505)
8223                 val |= DREF_NONSPREAD_CK505_ENABLE;
8224         else
8225                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8226
8227         if (has_panel) {
8228                 val &= ~DREF_SSC_SOURCE_MASK;
8229                 val |= DREF_SSC_SOURCE_ENABLE;
8230
8231                 /* SSC must be turned on before enabling the CPU output  */
8232                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8233                         DRM_DEBUG_KMS("Using SSC on panel\n");
8234                         val |= DREF_SSC1_ENABLE;
8235                 } else
8236                         val &= ~DREF_SSC1_ENABLE;
8237
8238                 /* Get SSC going before enabling the outputs */
8239                 I915_WRITE(PCH_DREF_CONTROL, val);
8240                 POSTING_READ(PCH_DREF_CONTROL);
8241                 udelay(200);
8242
8243                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8244
8245                 /* Enable CPU source on CPU attached eDP */
8246                 if (has_cpu_edp) {
8247                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8248                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8249                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8250                         } else
8251                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8252                 } else
8253                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8254
8255                 I915_WRITE(PCH_DREF_CONTROL, val);
8256                 POSTING_READ(PCH_DREF_CONTROL);
8257                 udelay(200);
8258         } else {
8259                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8260
8261                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8262
8263                 /* Turn off CPU output */
8264                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8265
8266                 I915_WRITE(PCH_DREF_CONTROL, val);
8267                 POSTING_READ(PCH_DREF_CONTROL);
8268                 udelay(200);
8269
8270                 /* Turn off the SSC source */
8271                 val &= ~DREF_SSC_SOURCE_MASK;
8272                 val |= DREF_SSC_SOURCE_DISABLE;
8273
8274                 /* Turn off SSC1 */
8275                 val &= ~DREF_SSC1_ENABLE;
8276
8277                 I915_WRITE(PCH_DREF_CONTROL, val);
8278                 POSTING_READ(PCH_DREF_CONTROL);
8279                 udelay(200);
8280         }
8281
8282         BUG_ON(val != final);
8283 }
8284
8285 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8286 {
8287         uint32_t tmp;
8288
8289         tmp = I915_READ(SOUTH_CHICKEN2);
8290         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8291         I915_WRITE(SOUTH_CHICKEN2, tmp);
8292
8293         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8294                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8295                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8296
8297         tmp = I915_READ(SOUTH_CHICKEN2);
8298         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8299         I915_WRITE(SOUTH_CHICKEN2, tmp);
8300
8301         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8302                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8303                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8304 }
8305
8306 /* WaMPhyProgramming:hsw */
8307 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8308 {
8309         uint32_t tmp;
8310
8311         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8312         tmp &= ~(0xFF << 24);
8313         tmp |= (0x12 << 24);
8314         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8315
8316         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8317         tmp |= (1 << 11);
8318         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8319
8320         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8321         tmp |= (1 << 11);
8322         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8323
8324         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8325         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8326         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8327
8328         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8329         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8330         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8331
8332         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8333         tmp &= ~(7 << 13);
8334         tmp |= (5 << 13);
8335         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8336
8337         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8338         tmp &= ~(7 << 13);
8339         tmp |= (5 << 13);
8340         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8341
8342         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8343         tmp &= ~0xFF;
8344         tmp |= 0x1C;
8345         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8346
8347         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8348         tmp &= ~0xFF;
8349         tmp |= 0x1C;
8350         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8351
8352         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8353         tmp &= ~(0xFF << 16);
8354         tmp |= (0x1C << 16);
8355         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8356
8357         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8358         tmp &= ~(0xFF << 16);
8359         tmp |= (0x1C << 16);
8360         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8361
8362         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8363         tmp |= (1 << 27);
8364         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8365
8366         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8367         tmp |= (1 << 27);
8368         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8369
8370         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8371         tmp &= ~(0xF << 28);
8372         tmp |= (4 << 28);
8373         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8374
8375         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8376         tmp &= ~(0xF << 28);
8377         tmp |= (4 << 28);
8378         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8379 }
8380
8381 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8382  * Programming" based on the parameters passed:
8383  * - Sequence to enable CLKOUT_DP
8384  * - Sequence to enable CLKOUT_DP without spread
8385  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8386  */
8387 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8388                                  bool with_fdi)
8389 {
8390         struct drm_i915_private *dev_priv = dev->dev_private;
8391         uint32_t reg, tmp;
8392
8393         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8394                 with_spread = true;
8395         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8396                  with_fdi, "LP PCH doesn't have FDI\n"))
8397                 with_fdi = false;
8398
8399         mutex_lock(&dev_priv->sb_lock);
8400
8401         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8402         tmp &= ~SBI_SSCCTL_DISABLE;
8403         tmp |= SBI_SSCCTL_PATHALT;
8404         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8405
8406         udelay(24);
8407
8408         if (with_spread) {
8409                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8410                 tmp &= ~SBI_SSCCTL_PATHALT;
8411                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8412
8413                 if (with_fdi) {
8414                         lpt_reset_fdi_mphy(dev_priv);
8415                         lpt_program_fdi_mphy(dev_priv);
8416                 }
8417         }
8418
8419         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8420                SBI_GEN0 : SBI_DBUFF0;
8421         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8422         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8423         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8424
8425         mutex_unlock(&dev_priv->sb_lock);
8426 }
8427
8428 /* Sequence to disable CLKOUT_DP */
8429 static void lpt_disable_clkout_dp(struct drm_device *dev)
8430 {
8431         struct drm_i915_private *dev_priv = dev->dev_private;
8432         uint32_t reg, tmp;
8433
8434         mutex_lock(&dev_priv->sb_lock);
8435
8436         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8437                SBI_GEN0 : SBI_DBUFF0;
8438         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8439         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8440         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8441
8442         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8443         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8444                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8445                         tmp |= SBI_SSCCTL_PATHALT;
8446                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8447                         udelay(32);
8448                 }
8449                 tmp |= SBI_SSCCTL_DISABLE;
8450                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8451         }
8452
8453         mutex_unlock(&dev_priv->sb_lock);
8454 }
8455
8456 static void lpt_init_pch_refclk(struct drm_device *dev)
8457 {
8458         struct intel_encoder *encoder;
8459         bool has_vga = false;
8460
8461         for_each_intel_encoder(dev, encoder) {
8462                 switch (encoder->type) {
8463                 case INTEL_OUTPUT_ANALOG:
8464                         has_vga = true;
8465                         break;
8466                 default:
8467                         break;
8468                 }
8469         }
8470
8471         if (has_vga)
8472                 lpt_enable_clkout_dp(dev, true, true);
8473         else
8474                 lpt_disable_clkout_dp(dev);
8475 }
8476
8477 /*
8478  * Initialize reference clocks when the driver loads
8479  */
8480 void intel_init_pch_refclk(struct drm_device *dev)
8481 {
8482         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8483                 ironlake_init_pch_refclk(dev);
8484         else if (HAS_PCH_LPT(dev))
8485                 lpt_init_pch_refclk(dev);
8486 }
8487
8488 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8489 {
8490         struct drm_device *dev = crtc_state->base.crtc->dev;
8491         struct drm_i915_private *dev_priv = dev->dev_private;
8492         struct drm_atomic_state *state = crtc_state->base.state;
8493         struct drm_connector *connector;
8494         struct drm_connector_state *connector_state;
8495         struct intel_encoder *encoder;
8496         int num_connectors = 0, i;
8497         bool is_lvds = false;
8498
8499         for_each_connector_in_state(state, connector, connector_state, i) {
8500                 if (connector_state->crtc != crtc_state->base.crtc)
8501                         continue;
8502
8503                 encoder = to_intel_encoder(connector_state->best_encoder);
8504
8505                 switch (encoder->type) {
8506                 case INTEL_OUTPUT_LVDS:
8507                         is_lvds = true;
8508                         break;
8509                 default:
8510                         break;
8511                 }
8512                 num_connectors++;
8513         }
8514
8515         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8516                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8517                               dev_priv->vbt.lvds_ssc_freq);
8518                 return dev_priv->vbt.lvds_ssc_freq;
8519         }
8520
8521         return 120000;
8522 }
8523
8524 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8525 {
8526         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8528         int pipe = intel_crtc->pipe;
8529         uint32_t val;
8530
8531         val = 0;
8532
8533         switch (intel_crtc->config->pipe_bpp) {
8534         case 18:
8535                 val |= PIPECONF_6BPC;
8536                 break;
8537         case 24:
8538                 val |= PIPECONF_8BPC;
8539                 break;
8540         case 30:
8541                 val |= PIPECONF_10BPC;
8542                 break;
8543         case 36:
8544                 val |= PIPECONF_12BPC;
8545                 break;
8546         default:
8547                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8548                 BUG();
8549         }
8550
8551         if (intel_crtc->config->dither)
8552                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8553
8554         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8555                 val |= PIPECONF_INTERLACED_ILK;
8556         else
8557                 val |= PIPECONF_PROGRESSIVE;
8558
8559         if (intel_crtc->config->limited_color_range)
8560                 val |= PIPECONF_COLOR_RANGE_SELECT;
8561
8562         I915_WRITE(PIPECONF(pipe), val);
8563         POSTING_READ(PIPECONF(pipe));
8564 }
8565
8566 /*
8567  * Set up the pipe CSC unit.
8568  *
8569  * Currently only full range RGB to limited range RGB conversion
8570  * is supported, but eventually this should handle various
8571  * RGB<->YCbCr scenarios as well.
8572  */
8573 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8574 {
8575         struct drm_device *dev = crtc->dev;
8576         struct drm_i915_private *dev_priv = dev->dev_private;
8577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8578         int pipe = intel_crtc->pipe;
8579         uint16_t coeff = 0x7800; /* 1.0 */
8580
8581         /*
8582          * TODO: Check what kind of values actually come out of the pipe
8583          * with these coeff/postoff values and adjust to get the best
8584          * accuracy. Perhaps we even need to take the bpc value into
8585          * consideration.
8586          */
8587
8588         if (intel_crtc->config->limited_color_range)
8589                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8590
8591         /*
8592          * GY/GU and RY/RU should be the other way around according
8593          * to BSpec, but reality doesn't agree. Just set them up in
8594          * a way that results in the correct picture.
8595          */
8596         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8597         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8598
8599         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8600         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8601
8602         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8603         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8604
8605         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8606         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8607         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8608
8609         if (INTEL_INFO(dev)->gen > 6) {
8610                 uint16_t postoff = 0;
8611
8612                 if (intel_crtc->config->limited_color_range)
8613                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8614
8615                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8616                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8617                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8618
8619                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8620         } else {
8621                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8622
8623                 if (intel_crtc->config->limited_color_range)
8624                         mode |= CSC_BLACK_SCREEN_OFFSET;
8625
8626                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8627         }
8628 }
8629
8630 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8631 {
8632         struct drm_device *dev = crtc->dev;
8633         struct drm_i915_private *dev_priv = dev->dev_private;
8634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8635         enum pipe pipe = intel_crtc->pipe;
8636         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8637         uint32_t val;
8638
8639         val = 0;
8640
8641         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8642                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8643
8644         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8645                 val |= PIPECONF_INTERLACED_ILK;
8646         else
8647                 val |= PIPECONF_PROGRESSIVE;
8648
8649         I915_WRITE(PIPECONF(cpu_transcoder), val);
8650         POSTING_READ(PIPECONF(cpu_transcoder));
8651
8652         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8653         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8654
8655         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8656                 val = 0;
8657
8658                 switch (intel_crtc->config->pipe_bpp) {
8659                 case 18:
8660                         val |= PIPEMISC_DITHER_6_BPC;
8661                         break;
8662                 case 24:
8663                         val |= PIPEMISC_DITHER_8_BPC;
8664                         break;
8665                 case 30:
8666                         val |= PIPEMISC_DITHER_10_BPC;
8667                         break;
8668                 case 36:
8669                         val |= PIPEMISC_DITHER_12_BPC;
8670                         break;
8671                 default:
8672                         /* Case prevented by pipe_config_set_bpp. */
8673                         BUG();
8674                 }
8675
8676                 if (intel_crtc->config->dither)
8677                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8678
8679                 I915_WRITE(PIPEMISC(pipe), val);
8680         }
8681 }
8682
8683 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8684                                     struct intel_crtc_state *crtc_state,
8685                                     intel_clock_t *clock,
8686                                     bool *has_reduced_clock,
8687                                     intel_clock_t *reduced_clock)
8688 {
8689         struct drm_device *dev = crtc->dev;
8690         struct drm_i915_private *dev_priv = dev->dev_private;
8691         int refclk;
8692         const intel_limit_t *limit;
8693         bool ret;
8694
8695         refclk = ironlake_get_refclk(crtc_state);
8696
8697         /*
8698          * Returns a set of divisors for the desired target clock with the given
8699          * refclk, or FALSE.  The returned values represent the clock equation:
8700          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8701          */
8702         limit = intel_limit(crtc_state, refclk);
8703         ret = dev_priv->display.find_dpll(limit, crtc_state,
8704                                           crtc_state->port_clock,
8705                                           refclk, NULL, clock);
8706         if (!ret)
8707                 return false;
8708
8709         return true;
8710 }
8711
8712 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8713 {
8714         /*
8715          * Account for spread spectrum to avoid
8716          * oversubscribing the link. Max center spread
8717          * is 2.5%; use 5% for safety's sake.
8718          */
8719         u32 bps = target_clock * bpp * 21 / 20;
8720         return DIV_ROUND_UP(bps, link_bw * 8);
8721 }
8722
8723 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8724 {
8725         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8726 }
8727
8728 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8729                                       struct intel_crtc_state *crtc_state,
8730                                       u32 *fp,
8731                                       intel_clock_t *reduced_clock, u32 *fp2)
8732 {
8733         struct drm_crtc *crtc = &intel_crtc->base;
8734         struct drm_device *dev = crtc->dev;
8735         struct drm_i915_private *dev_priv = dev->dev_private;
8736         struct drm_atomic_state *state = crtc_state->base.state;
8737         struct drm_connector *connector;
8738         struct drm_connector_state *connector_state;
8739         struct intel_encoder *encoder;
8740         uint32_t dpll;
8741         int factor, num_connectors = 0, i;
8742         bool is_lvds = false, is_sdvo = false;
8743
8744         for_each_connector_in_state(state, connector, connector_state, i) {
8745                 if (connector_state->crtc != crtc_state->base.crtc)
8746                         continue;
8747
8748                 encoder = to_intel_encoder(connector_state->best_encoder);
8749
8750                 switch (encoder->type) {
8751                 case INTEL_OUTPUT_LVDS:
8752                         is_lvds = true;
8753                         break;
8754                 case INTEL_OUTPUT_SDVO:
8755                 case INTEL_OUTPUT_HDMI:
8756                         is_sdvo = true;
8757                         break;
8758                 default:
8759                         break;
8760                 }
8761
8762                 num_connectors++;
8763         }
8764
8765         /* Enable autotuning of the PLL clock (if permissible) */
8766         factor = 21;
8767         if (is_lvds) {
8768                 if ((intel_panel_use_ssc(dev_priv) &&
8769                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8770                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8771                         factor = 25;
8772         } else if (crtc_state->sdvo_tv_clock)
8773                 factor = 20;
8774
8775         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8776                 *fp |= FP_CB_TUNE;
8777
8778         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8779                 *fp2 |= FP_CB_TUNE;
8780
8781         dpll = 0;
8782
8783         if (is_lvds)
8784                 dpll |= DPLLB_MODE_LVDS;
8785         else
8786                 dpll |= DPLLB_MODE_DAC_SERIAL;
8787
8788         dpll |= (crtc_state->pixel_multiplier - 1)
8789                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8790
8791         if (is_sdvo)
8792                 dpll |= DPLL_SDVO_HIGH_SPEED;
8793         if (crtc_state->has_dp_encoder)
8794                 dpll |= DPLL_SDVO_HIGH_SPEED;
8795
8796         /* compute bitmask from p1 value */
8797         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8798         /* also FPA1 */
8799         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8800
8801         switch (crtc_state->dpll.p2) {
8802         case 5:
8803                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8804                 break;
8805         case 7:
8806                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8807                 break;
8808         case 10:
8809                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8810                 break;
8811         case 14:
8812                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8813                 break;
8814         }
8815
8816         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8817                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8818         else
8819                 dpll |= PLL_REF_INPUT_DREFCLK;
8820
8821         return dpll | DPLL_VCO_ENABLE;
8822 }
8823
8824 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8825                                        struct intel_crtc_state *crtc_state)
8826 {
8827         struct drm_device *dev = crtc->base.dev;
8828         intel_clock_t clock, reduced_clock;
8829         u32 dpll = 0, fp = 0, fp2 = 0;
8830         bool ok, has_reduced_clock = false;
8831         bool is_lvds = false;
8832         struct intel_shared_dpll *pll;
8833
8834         memset(&crtc_state->dpll_hw_state, 0,
8835                sizeof(crtc_state->dpll_hw_state));
8836
8837         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8838
8839         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8840              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8841
8842         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8843                                      &has_reduced_clock, &reduced_clock);
8844         if (!ok && !crtc_state->clock_set) {
8845                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8846                 return -EINVAL;
8847         }
8848         /* Compat-code for transition, will disappear. */
8849         if (!crtc_state->clock_set) {
8850                 crtc_state->dpll.n = clock.n;
8851                 crtc_state->dpll.m1 = clock.m1;
8852                 crtc_state->dpll.m2 = clock.m2;
8853                 crtc_state->dpll.p1 = clock.p1;
8854                 crtc_state->dpll.p2 = clock.p2;
8855         }
8856
8857         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8858         if (crtc_state->has_pch_encoder) {
8859                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8860                 if (has_reduced_clock)
8861                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8862
8863                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8864                                              &fp, &reduced_clock,
8865                                              has_reduced_clock ? &fp2 : NULL);
8866
8867                 crtc_state->dpll_hw_state.dpll = dpll;
8868                 crtc_state->dpll_hw_state.fp0 = fp;
8869                 if (has_reduced_clock)
8870                         crtc_state->dpll_hw_state.fp1 = fp2;
8871                 else
8872                         crtc_state->dpll_hw_state.fp1 = fp;
8873
8874                 pll = intel_get_shared_dpll(crtc, crtc_state);
8875                 if (pll == NULL) {
8876                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8877                                          pipe_name(crtc->pipe));
8878                         return -EINVAL;
8879                 }
8880         }
8881
8882         if (is_lvds && has_reduced_clock)
8883                 crtc->lowfreq_avail = true;
8884         else
8885                 crtc->lowfreq_avail = false;
8886
8887         return 0;
8888 }
8889
8890 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8891                                          struct intel_link_m_n *m_n)
8892 {
8893         struct drm_device *dev = crtc->base.dev;
8894         struct drm_i915_private *dev_priv = dev->dev_private;
8895         enum pipe pipe = crtc->pipe;
8896
8897         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8898         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8899         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8900                 & ~TU_SIZE_MASK;
8901         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8902         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8903                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8904 }
8905
8906 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8907                                          enum transcoder transcoder,
8908                                          struct intel_link_m_n *m_n,
8909                                          struct intel_link_m_n *m2_n2)
8910 {
8911         struct drm_device *dev = crtc->base.dev;
8912         struct drm_i915_private *dev_priv = dev->dev_private;
8913         enum pipe pipe = crtc->pipe;
8914
8915         if (INTEL_INFO(dev)->gen >= 5) {
8916                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8917                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8918                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8919                         & ~TU_SIZE_MASK;
8920                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8921                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8922                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8923                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8924                  * gen < 8) and if DRRS is supported (to make sure the
8925                  * registers are not unnecessarily read).
8926                  */
8927                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8928                         crtc->config->has_drrs) {
8929                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8930                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8931                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8932                                         & ~TU_SIZE_MASK;
8933                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8934                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8935                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8936                 }
8937         } else {
8938                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8939                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8940                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8941                         & ~TU_SIZE_MASK;
8942                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8943                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8944                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8945         }
8946 }
8947
8948 void intel_dp_get_m_n(struct intel_crtc *crtc,
8949                       struct intel_crtc_state *pipe_config)
8950 {
8951         if (pipe_config->has_pch_encoder)
8952                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8953         else
8954                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8955                                              &pipe_config->dp_m_n,
8956                                              &pipe_config->dp_m2_n2);
8957 }
8958
8959 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8960                                         struct intel_crtc_state *pipe_config)
8961 {
8962         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8963                                      &pipe_config->fdi_m_n, NULL);
8964 }
8965
8966 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8967                                     struct intel_crtc_state *pipe_config)
8968 {
8969         struct drm_device *dev = crtc->base.dev;
8970         struct drm_i915_private *dev_priv = dev->dev_private;
8971         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8972         uint32_t ps_ctrl = 0;
8973         int id = -1;
8974         int i;
8975
8976         /* find scaler attached to this pipe */
8977         for (i = 0; i < crtc->num_scalers; i++) {
8978                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8979                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8980                         id = i;
8981                         pipe_config->pch_pfit.enabled = true;
8982                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8983                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8984                         break;
8985                 }
8986         }
8987
8988         scaler_state->scaler_id = id;
8989         if (id >= 0) {
8990                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8991         } else {
8992                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8993         }
8994 }
8995
8996 static void
8997 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8998                                  struct intel_initial_plane_config *plane_config)
8999 {
9000         struct drm_device *dev = crtc->base.dev;
9001         struct drm_i915_private *dev_priv = dev->dev_private;
9002         u32 val, base, offset, stride_mult, tiling;
9003         int pipe = crtc->pipe;
9004         int fourcc, pixel_format;
9005         unsigned int aligned_height;
9006         struct drm_framebuffer *fb;
9007         struct intel_framebuffer *intel_fb;
9008
9009         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9010         if (!intel_fb) {
9011                 DRM_DEBUG_KMS("failed to alloc fb\n");
9012                 return;
9013         }
9014
9015         fb = &intel_fb->base;
9016
9017         val = I915_READ(PLANE_CTL(pipe, 0));
9018         if (!(val & PLANE_CTL_ENABLE))
9019                 goto error;
9020
9021         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9022         fourcc = skl_format_to_fourcc(pixel_format,
9023                                       val & PLANE_CTL_ORDER_RGBX,
9024                                       val & PLANE_CTL_ALPHA_MASK);
9025         fb->pixel_format = fourcc;
9026         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9027
9028         tiling = val & PLANE_CTL_TILED_MASK;
9029         switch (tiling) {
9030         case PLANE_CTL_TILED_LINEAR:
9031                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9032                 break;
9033         case PLANE_CTL_TILED_X:
9034                 plane_config->tiling = I915_TILING_X;
9035                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9036                 break;
9037         case PLANE_CTL_TILED_Y:
9038                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9039                 break;
9040         case PLANE_CTL_TILED_YF:
9041                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9042                 break;
9043         default:
9044                 MISSING_CASE(tiling);
9045                 goto error;
9046         }
9047
9048         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9049         plane_config->base = base;
9050
9051         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9052
9053         val = I915_READ(PLANE_SIZE(pipe, 0));
9054         fb->height = ((val >> 16) & 0xfff) + 1;
9055         fb->width = ((val >> 0) & 0x1fff) + 1;
9056
9057         val = I915_READ(PLANE_STRIDE(pipe, 0));
9058         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9059                                                 fb->pixel_format);
9060         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9061
9062         aligned_height = intel_fb_align_height(dev, fb->height,
9063                                                fb->pixel_format,
9064                                                fb->modifier[0]);
9065
9066         plane_config->size = fb->pitches[0] * aligned_height;
9067
9068         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9069                       pipe_name(pipe), fb->width, fb->height,
9070                       fb->bits_per_pixel, base, fb->pitches[0],
9071                       plane_config->size);
9072
9073         plane_config->fb = intel_fb;
9074         return;
9075
9076 error:
9077         kfree(fb);
9078 }
9079
9080 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9081                                      struct intel_crtc_state *pipe_config)
9082 {
9083         struct drm_device *dev = crtc->base.dev;
9084         struct drm_i915_private *dev_priv = dev->dev_private;
9085         uint32_t tmp;
9086
9087         tmp = I915_READ(PF_CTL(crtc->pipe));
9088
9089         if (tmp & PF_ENABLE) {
9090                 pipe_config->pch_pfit.enabled = true;
9091                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9092                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9093
9094                 /* We currently do not free assignements of panel fitters on
9095                  * ivb/hsw (since we don't use the higher upscaling modes which
9096                  * differentiates them) so just WARN about this case for now. */
9097                 if (IS_GEN7(dev)) {
9098                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9099                                 PF_PIPE_SEL_IVB(crtc->pipe));
9100                 }
9101         }
9102 }
9103
9104 static void
9105 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9106                                   struct intel_initial_plane_config *plane_config)
9107 {
9108         struct drm_device *dev = crtc->base.dev;
9109         struct drm_i915_private *dev_priv = dev->dev_private;
9110         u32 val, base, offset;
9111         int pipe = crtc->pipe;
9112         int fourcc, pixel_format;
9113         unsigned int aligned_height;
9114         struct drm_framebuffer *fb;
9115         struct intel_framebuffer *intel_fb;
9116
9117         val = I915_READ(DSPCNTR(pipe));
9118         if (!(val & DISPLAY_PLANE_ENABLE))
9119                 return;
9120
9121         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9122         if (!intel_fb) {
9123                 DRM_DEBUG_KMS("failed to alloc fb\n");
9124                 return;
9125         }
9126
9127         fb = &intel_fb->base;
9128
9129         if (INTEL_INFO(dev)->gen >= 4) {
9130                 if (val & DISPPLANE_TILED) {
9131                         plane_config->tiling = I915_TILING_X;
9132                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9133                 }
9134         }
9135
9136         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9137         fourcc = i9xx_format_to_fourcc(pixel_format);
9138         fb->pixel_format = fourcc;
9139         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9140
9141         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9142         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9143                 offset = I915_READ(DSPOFFSET(pipe));
9144         } else {
9145                 if (plane_config->tiling)
9146                         offset = I915_READ(DSPTILEOFF(pipe));
9147                 else
9148                         offset = I915_READ(DSPLINOFF(pipe));
9149         }
9150         plane_config->base = base;
9151
9152         val = I915_READ(PIPESRC(pipe));
9153         fb->width = ((val >> 16) & 0xfff) + 1;
9154         fb->height = ((val >> 0) & 0xfff) + 1;
9155
9156         val = I915_READ(DSPSTRIDE(pipe));
9157         fb->pitches[0] = val & 0xffffffc0;
9158
9159         aligned_height = intel_fb_align_height(dev, fb->height,
9160                                                fb->pixel_format,
9161                                                fb->modifier[0]);
9162
9163         plane_config->size = fb->pitches[0] * aligned_height;
9164
9165         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9166                       pipe_name(pipe), fb->width, fb->height,
9167                       fb->bits_per_pixel, base, fb->pitches[0],
9168                       plane_config->size);
9169
9170         plane_config->fb = intel_fb;
9171 }
9172
9173 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9174                                      struct intel_crtc_state *pipe_config)
9175 {
9176         struct drm_device *dev = crtc->base.dev;
9177         struct drm_i915_private *dev_priv = dev->dev_private;
9178         uint32_t tmp;
9179
9180         if (!intel_display_power_is_enabled(dev_priv,
9181                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9182                 return false;
9183
9184         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9185         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9186
9187         tmp = I915_READ(PIPECONF(crtc->pipe));
9188         if (!(tmp & PIPECONF_ENABLE))
9189                 return false;
9190
9191         switch (tmp & PIPECONF_BPC_MASK) {
9192         case PIPECONF_6BPC:
9193                 pipe_config->pipe_bpp = 18;
9194                 break;
9195         case PIPECONF_8BPC:
9196                 pipe_config->pipe_bpp = 24;
9197                 break;
9198         case PIPECONF_10BPC:
9199                 pipe_config->pipe_bpp = 30;
9200                 break;
9201         case PIPECONF_12BPC:
9202                 pipe_config->pipe_bpp = 36;
9203                 break;
9204         default:
9205                 break;
9206         }
9207
9208         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9209                 pipe_config->limited_color_range = true;
9210
9211         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9212                 struct intel_shared_dpll *pll;
9213
9214                 pipe_config->has_pch_encoder = true;
9215
9216                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9217                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9218                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9219
9220                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9221
9222                 if (HAS_PCH_IBX(dev_priv->dev)) {
9223                         pipe_config->shared_dpll =
9224                                 (enum intel_dpll_id) crtc->pipe;
9225                 } else {
9226                         tmp = I915_READ(PCH_DPLL_SEL);
9227                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9228                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9229                         else
9230                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9231                 }
9232
9233                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9234
9235                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9236                                            &pipe_config->dpll_hw_state));
9237
9238                 tmp = pipe_config->dpll_hw_state.dpll;
9239                 pipe_config->pixel_multiplier =
9240                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9241                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9242
9243                 ironlake_pch_clock_get(crtc, pipe_config);
9244         } else {
9245                 pipe_config->pixel_multiplier = 1;
9246         }
9247
9248         intel_get_pipe_timings(crtc, pipe_config);
9249
9250         ironlake_get_pfit_config(crtc, pipe_config);
9251
9252         return true;
9253 }
9254
9255 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9256 {
9257         struct drm_device *dev = dev_priv->dev;
9258         struct intel_crtc *crtc;
9259
9260         for_each_intel_crtc(dev, crtc)
9261                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9262                      pipe_name(crtc->pipe));
9263
9264         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9265         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9266         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9267         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9268         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9269         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9270              "CPU PWM1 enabled\n");
9271         if (IS_HASWELL(dev))
9272                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9273                      "CPU PWM2 enabled\n");
9274         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9275              "PCH PWM1 enabled\n");
9276         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9277              "Utility pin enabled\n");
9278         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9279
9280         /*
9281          * In theory we can still leave IRQs enabled, as long as only the HPD
9282          * interrupts remain enabled. We used to check for that, but since it's
9283          * gen-specific and since we only disable LCPLL after we fully disable
9284          * the interrupts, the check below should be enough.
9285          */
9286         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9287 }
9288
9289 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9290 {
9291         struct drm_device *dev = dev_priv->dev;
9292
9293         if (IS_HASWELL(dev))
9294                 return I915_READ(D_COMP_HSW);
9295         else
9296                 return I915_READ(D_COMP_BDW);
9297 }
9298
9299 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9300 {
9301         struct drm_device *dev = dev_priv->dev;
9302
9303         if (IS_HASWELL(dev)) {
9304                 mutex_lock(&dev_priv->rps.hw_lock);
9305                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9306                                             val))
9307                         DRM_ERROR("Failed to write to D_COMP\n");
9308                 mutex_unlock(&dev_priv->rps.hw_lock);
9309         } else {
9310                 I915_WRITE(D_COMP_BDW, val);
9311                 POSTING_READ(D_COMP_BDW);
9312         }
9313 }
9314
9315 /*
9316  * This function implements pieces of two sequences from BSpec:
9317  * - Sequence for display software to disable LCPLL
9318  * - Sequence for display software to allow package C8+
9319  * The steps implemented here are just the steps that actually touch the LCPLL
9320  * register. Callers should take care of disabling all the display engine
9321  * functions, doing the mode unset, fixing interrupts, etc.
9322  */
9323 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9324                               bool switch_to_fclk, bool allow_power_down)
9325 {
9326         uint32_t val;
9327
9328         assert_can_disable_lcpll(dev_priv);
9329
9330         val = I915_READ(LCPLL_CTL);
9331
9332         if (switch_to_fclk) {
9333                 val |= LCPLL_CD_SOURCE_FCLK;
9334                 I915_WRITE(LCPLL_CTL, val);
9335
9336                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9337                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9338                         DRM_ERROR("Switching to FCLK failed\n");
9339
9340                 val = I915_READ(LCPLL_CTL);
9341         }
9342
9343         val |= LCPLL_PLL_DISABLE;
9344         I915_WRITE(LCPLL_CTL, val);
9345         POSTING_READ(LCPLL_CTL);
9346
9347         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9348                 DRM_ERROR("LCPLL still locked\n");
9349
9350         val = hsw_read_dcomp(dev_priv);
9351         val |= D_COMP_COMP_DISABLE;
9352         hsw_write_dcomp(dev_priv, val);
9353         ndelay(100);
9354
9355         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9356                      1))
9357                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9358
9359         if (allow_power_down) {
9360                 val = I915_READ(LCPLL_CTL);
9361                 val |= LCPLL_POWER_DOWN_ALLOW;
9362                 I915_WRITE(LCPLL_CTL, val);
9363                 POSTING_READ(LCPLL_CTL);
9364         }
9365 }
9366
9367 /*
9368  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9369  * source.
9370  */
9371 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9372 {
9373         uint32_t val;
9374
9375         val = I915_READ(LCPLL_CTL);
9376
9377         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9378                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9379                 return;
9380
9381         /*
9382          * Make sure we're not on PC8 state before disabling PC8, otherwise
9383          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9384          */
9385         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9386
9387         if (val & LCPLL_POWER_DOWN_ALLOW) {
9388                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9389                 I915_WRITE(LCPLL_CTL, val);
9390                 POSTING_READ(LCPLL_CTL);
9391         }
9392
9393         val = hsw_read_dcomp(dev_priv);
9394         val |= D_COMP_COMP_FORCE;
9395         val &= ~D_COMP_COMP_DISABLE;
9396         hsw_write_dcomp(dev_priv, val);
9397
9398         val = I915_READ(LCPLL_CTL);
9399         val &= ~LCPLL_PLL_DISABLE;
9400         I915_WRITE(LCPLL_CTL, val);
9401
9402         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9403                 DRM_ERROR("LCPLL not locked yet\n");
9404
9405         if (val & LCPLL_CD_SOURCE_FCLK) {
9406                 val = I915_READ(LCPLL_CTL);
9407                 val &= ~LCPLL_CD_SOURCE_FCLK;
9408                 I915_WRITE(LCPLL_CTL, val);
9409
9410                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9411                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9412                         DRM_ERROR("Switching back to LCPLL failed\n");
9413         }
9414
9415         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9416         intel_update_cdclk(dev_priv->dev);
9417 }
9418
9419 /*
9420  * Package states C8 and deeper are really deep PC states that can only be
9421  * reached when all the devices on the system allow it, so even if the graphics
9422  * device allows PC8+, it doesn't mean the system will actually get to these
9423  * states. Our driver only allows PC8+ when going into runtime PM.
9424  *
9425  * The requirements for PC8+ are that all the outputs are disabled, the power
9426  * well is disabled and most interrupts are disabled, and these are also
9427  * requirements for runtime PM. When these conditions are met, we manually do
9428  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9429  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9430  * hang the machine.
9431  *
9432  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9433  * the state of some registers, so when we come back from PC8+ we need to
9434  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9435  * need to take care of the registers kept by RC6. Notice that this happens even
9436  * if we don't put the device in PCI D3 state (which is what currently happens
9437  * because of the runtime PM support).
9438  *
9439  * For more, read "Display Sequences for Package C8" on the hardware
9440  * documentation.
9441  */
9442 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9443 {
9444         struct drm_device *dev = dev_priv->dev;
9445         uint32_t val;
9446
9447         DRM_DEBUG_KMS("Enabling package C8+\n");
9448
9449         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9450                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9451                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9452                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9453         }
9454
9455         lpt_disable_clkout_dp(dev);
9456         hsw_disable_lcpll(dev_priv, true, true);
9457 }
9458
9459 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9460 {
9461         struct drm_device *dev = dev_priv->dev;
9462         uint32_t val;
9463
9464         DRM_DEBUG_KMS("Disabling package C8+\n");
9465
9466         hsw_restore_lcpll(dev_priv);
9467         lpt_init_pch_refclk(dev);
9468
9469         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9470                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9471                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9472                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9473         }
9474
9475         intel_prepare_ddi(dev);
9476 }
9477
9478 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9479 {
9480         struct drm_device *dev = old_state->dev;
9481         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9482
9483         broxton_set_cdclk(dev, req_cdclk);
9484 }
9485
9486 /* compute the max rate for new configuration */
9487 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9488 {
9489         struct intel_crtc *intel_crtc;
9490         struct intel_crtc_state *crtc_state;
9491         int max_pixel_rate = 0;
9492
9493         for_each_intel_crtc(state->dev, intel_crtc) {
9494                 int pixel_rate;
9495
9496                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9497                 if (IS_ERR(crtc_state))
9498                         return PTR_ERR(crtc_state);
9499
9500                 if (!crtc_state->base.enable)
9501                         continue;
9502
9503                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9504
9505                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9506                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9507                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9508
9509                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9510         }
9511
9512         return max_pixel_rate;
9513 }
9514
9515 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9516 {
9517         struct drm_i915_private *dev_priv = dev->dev_private;
9518         uint32_t val, data;
9519         int ret;
9520
9521         if (WARN((I915_READ(LCPLL_CTL) &
9522                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9523                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9524                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9525                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9526                  "trying to change cdclk frequency with cdclk not enabled\n"))
9527                 return;
9528
9529         mutex_lock(&dev_priv->rps.hw_lock);
9530         ret = sandybridge_pcode_write(dev_priv,
9531                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9532         mutex_unlock(&dev_priv->rps.hw_lock);
9533         if (ret) {
9534                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9535                 return;
9536         }
9537
9538         val = I915_READ(LCPLL_CTL);
9539         val |= LCPLL_CD_SOURCE_FCLK;
9540         I915_WRITE(LCPLL_CTL, val);
9541
9542         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9543                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9544                 DRM_ERROR("Switching to FCLK failed\n");
9545
9546         val = I915_READ(LCPLL_CTL);
9547         val &= ~LCPLL_CLK_FREQ_MASK;
9548
9549         switch (cdclk) {
9550         case 450000:
9551                 val |= LCPLL_CLK_FREQ_450;
9552                 data = 0;
9553                 break;
9554         case 540000:
9555                 val |= LCPLL_CLK_FREQ_54O_BDW;
9556                 data = 1;
9557                 break;
9558         case 337500:
9559                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9560                 data = 2;
9561                 break;
9562         case 675000:
9563                 val |= LCPLL_CLK_FREQ_675_BDW;
9564                 data = 3;
9565                 break;
9566         default:
9567                 WARN(1, "invalid cdclk frequency\n");
9568                 return;
9569         }
9570
9571         I915_WRITE(LCPLL_CTL, val);
9572
9573         val = I915_READ(LCPLL_CTL);
9574         val &= ~LCPLL_CD_SOURCE_FCLK;
9575         I915_WRITE(LCPLL_CTL, val);
9576
9577         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9578                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9579                 DRM_ERROR("Switching back to LCPLL failed\n");
9580
9581         mutex_lock(&dev_priv->rps.hw_lock);
9582         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9583         mutex_unlock(&dev_priv->rps.hw_lock);
9584
9585         intel_update_cdclk(dev);
9586
9587         WARN(cdclk != dev_priv->cdclk_freq,
9588              "cdclk requested %d kHz but got %d kHz\n",
9589              cdclk, dev_priv->cdclk_freq);
9590 }
9591
9592 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9593 {
9594         struct drm_i915_private *dev_priv = to_i915(state->dev);
9595         int max_pixclk = ilk_max_pixel_rate(state);
9596         int cdclk;
9597
9598         /*
9599          * FIXME should also account for plane ratio
9600          * once 64bpp pixel formats are supported.
9601          */
9602         if (max_pixclk > 540000)
9603                 cdclk = 675000;
9604         else if (max_pixclk > 450000)
9605                 cdclk = 540000;
9606         else if (max_pixclk > 337500)
9607                 cdclk = 450000;
9608         else
9609                 cdclk = 337500;
9610
9611         /*
9612          * FIXME move the cdclk caclulation to
9613          * compute_config() so we can fail gracegully.
9614          */
9615         if (cdclk > dev_priv->max_cdclk_freq) {
9616                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9617                           cdclk, dev_priv->max_cdclk_freq);
9618                 cdclk = dev_priv->max_cdclk_freq;
9619         }
9620
9621         to_intel_atomic_state(state)->cdclk = cdclk;
9622
9623         return 0;
9624 }
9625
9626 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9627 {
9628         struct drm_device *dev = old_state->dev;
9629         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9630
9631         broadwell_set_cdclk(dev, req_cdclk);
9632 }
9633
9634 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9635                                       struct intel_crtc_state *crtc_state)
9636 {
9637         if (!intel_ddi_pll_select(crtc, crtc_state))
9638                 return -EINVAL;
9639
9640         crtc->lowfreq_avail = false;
9641
9642         return 0;
9643 }
9644
9645 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9646                                 enum port port,
9647                                 struct intel_crtc_state *pipe_config)
9648 {
9649         switch (port) {
9650         case PORT_A:
9651                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9652                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9653                 break;
9654         case PORT_B:
9655                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9656                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9657                 break;
9658         case PORT_C:
9659                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9660                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9661                 break;
9662         default:
9663                 DRM_ERROR("Incorrect port type\n");
9664         }
9665 }
9666
9667 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9668                                 enum port port,
9669                                 struct intel_crtc_state *pipe_config)
9670 {
9671         u32 temp, dpll_ctl1;
9672
9673         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9674         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9675
9676         switch (pipe_config->ddi_pll_sel) {
9677         case SKL_DPLL0:
9678                 /*
9679                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9680                  * of the shared DPLL framework and thus needs to be read out
9681                  * separately
9682                  */
9683                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9684                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9685                 break;
9686         case SKL_DPLL1:
9687                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9688                 break;
9689         case SKL_DPLL2:
9690                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9691                 break;
9692         case SKL_DPLL3:
9693                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9694                 break;
9695         }
9696 }
9697
9698 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9699                                 enum port port,
9700                                 struct intel_crtc_state *pipe_config)
9701 {
9702         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9703
9704         switch (pipe_config->ddi_pll_sel) {
9705         case PORT_CLK_SEL_WRPLL1:
9706                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9707                 break;
9708         case PORT_CLK_SEL_WRPLL2:
9709                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9710                 break;
9711         }
9712 }
9713
9714 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9715                                        struct intel_crtc_state *pipe_config)
9716 {
9717         struct drm_device *dev = crtc->base.dev;
9718         struct drm_i915_private *dev_priv = dev->dev_private;
9719         struct intel_shared_dpll *pll;
9720         enum port port;
9721         uint32_t tmp;
9722
9723         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9724
9725         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9726
9727         if (IS_SKYLAKE(dev))
9728                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9729         else if (IS_BROXTON(dev))
9730                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9731         else
9732                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9733
9734         if (pipe_config->shared_dpll >= 0) {
9735                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9736
9737                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9738                                            &pipe_config->dpll_hw_state));
9739         }
9740
9741         /*
9742          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9743          * DDI E. So just check whether this pipe is wired to DDI E and whether
9744          * the PCH transcoder is on.
9745          */
9746         if (INTEL_INFO(dev)->gen < 9 &&
9747             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9748                 pipe_config->has_pch_encoder = true;
9749
9750                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9751                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9752                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9753
9754                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9755         }
9756 }
9757
9758 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9759                                     struct intel_crtc_state *pipe_config)
9760 {
9761         struct drm_device *dev = crtc->base.dev;
9762         struct drm_i915_private *dev_priv = dev->dev_private;
9763         enum intel_display_power_domain pfit_domain;
9764         uint32_t tmp;
9765
9766         if (!intel_display_power_is_enabled(dev_priv,
9767                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9768                 return false;
9769
9770         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9771         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9772
9773         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9774         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9775                 enum pipe trans_edp_pipe;
9776                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9777                 default:
9778                         WARN(1, "unknown pipe linked to edp transcoder\n");
9779                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9780                 case TRANS_DDI_EDP_INPUT_A_ON:
9781                         trans_edp_pipe = PIPE_A;
9782                         break;
9783                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9784                         trans_edp_pipe = PIPE_B;
9785                         break;
9786                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9787                         trans_edp_pipe = PIPE_C;
9788                         break;
9789                 }
9790
9791                 if (trans_edp_pipe == crtc->pipe)
9792                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9793         }
9794
9795         if (!intel_display_power_is_enabled(dev_priv,
9796                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9797                 return false;
9798
9799         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9800         if (!(tmp & PIPECONF_ENABLE))
9801                 return false;
9802
9803         haswell_get_ddi_port_state(crtc, pipe_config);
9804
9805         intel_get_pipe_timings(crtc, pipe_config);
9806
9807         if (INTEL_INFO(dev)->gen >= 9) {
9808                 skl_init_scalers(dev, crtc, pipe_config);
9809         }
9810
9811         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9812
9813         if (INTEL_INFO(dev)->gen >= 9) {
9814                 pipe_config->scaler_state.scaler_id = -1;
9815                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9816         }
9817
9818         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9819                 if (INTEL_INFO(dev)->gen == 9)
9820                         skylake_get_pfit_config(crtc, pipe_config);
9821                 else if (INTEL_INFO(dev)->gen < 9)
9822                         ironlake_get_pfit_config(crtc, pipe_config);
9823                 else
9824                         MISSING_CASE(INTEL_INFO(dev)->gen);
9825         }
9826
9827         if (IS_HASWELL(dev))
9828                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9829                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9830
9831         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9832                 pipe_config->pixel_multiplier =
9833                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9834         } else {
9835                 pipe_config->pixel_multiplier = 1;
9836         }
9837
9838         return true;
9839 }
9840
9841 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9842 {
9843         struct drm_device *dev = crtc->dev;
9844         struct drm_i915_private *dev_priv = dev->dev_private;
9845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9846         uint32_t cntl = 0, size = 0;
9847
9848         if (base) {
9849                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9850                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9851                 unsigned int stride = roundup_pow_of_two(width) * 4;
9852
9853                 switch (stride) {
9854                 default:
9855                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9856                                   width, stride);
9857                         stride = 256;
9858                         /* fallthrough */
9859                 case 256:
9860                 case 512:
9861                 case 1024:
9862                 case 2048:
9863                         break;
9864                 }
9865
9866                 cntl |= CURSOR_ENABLE |
9867                         CURSOR_GAMMA_ENABLE |
9868                         CURSOR_FORMAT_ARGB |
9869                         CURSOR_STRIDE(stride);
9870
9871                 size = (height << 12) | width;
9872         }
9873
9874         if (intel_crtc->cursor_cntl != 0 &&
9875             (intel_crtc->cursor_base != base ||
9876              intel_crtc->cursor_size != size ||
9877              intel_crtc->cursor_cntl != cntl)) {
9878                 /* On these chipsets we can only modify the base/size/stride
9879                  * whilst the cursor is disabled.
9880                  */
9881                 I915_WRITE(_CURACNTR, 0);
9882                 POSTING_READ(_CURACNTR);
9883                 intel_crtc->cursor_cntl = 0;
9884         }
9885
9886         if (intel_crtc->cursor_base != base) {
9887                 I915_WRITE(_CURABASE, base);
9888                 intel_crtc->cursor_base = base;
9889         }
9890
9891         if (intel_crtc->cursor_size != size) {
9892                 I915_WRITE(CURSIZE, size);
9893                 intel_crtc->cursor_size = size;
9894         }
9895
9896         if (intel_crtc->cursor_cntl != cntl) {
9897                 I915_WRITE(_CURACNTR, cntl);
9898                 POSTING_READ(_CURACNTR);
9899                 intel_crtc->cursor_cntl = cntl;
9900         }
9901 }
9902
9903 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9904 {
9905         struct drm_device *dev = crtc->dev;
9906         struct drm_i915_private *dev_priv = dev->dev_private;
9907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9908         int pipe = intel_crtc->pipe;
9909         uint32_t cntl;
9910
9911         cntl = 0;
9912         if (base) {
9913                 cntl = MCURSOR_GAMMA_ENABLE;
9914                 switch (intel_crtc->base.cursor->state->crtc_w) {
9915                         case 64:
9916                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9917                                 break;
9918                         case 128:
9919                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9920                                 break;
9921                         case 256:
9922                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9923                                 break;
9924                         default:
9925                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9926                                 return;
9927                 }
9928                 cntl |= pipe << 28; /* Connect to correct pipe */
9929
9930                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9931                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9932         }
9933
9934         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9935                 cntl |= CURSOR_ROTATE_180;
9936
9937         if (intel_crtc->cursor_cntl != cntl) {
9938                 I915_WRITE(CURCNTR(pipe), cntl);
9939                 POSTING_READ(CURCNTR(pipe));
9940                 intel_crtc->cursor_cntl = cntl;
9941         }
9942
9943         /* and commit changes on next vblank */
9944         I915_WRITE(CURBASE(pipe), base);
9945         POSTING_READ(CURBASE(pipe));
9946
9947         intel_crtc->cursor_base = base;
9948 }
9949
9950 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9951 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9952                                      bool on)
9953 {
9954         struct drm_device *dev = crtc->dev;
9955         struct drm_i915_private *dev_priv = dev->dev_private;
9956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9957         int pipe = intel_crtc->pipe;
9958         int x = crtc->cursor_x;
9959         int y = crtc->cursor_y;
9960         u32 base = 0, pos = 0;
9961
9962         if (on)
9963                 base = intel_crtc->cursor_addr;
9964
9965         if (x >= intel_crtc->config->pipe_src_w)
9966                 base = 0;
9967
9968         if (y >= intel_crtc->config->pipe_src_h)
9969                 base = 0;
9970
9971         if (x < 0) {
9972                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9973                         base = 0;
9974
9975                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9976                 x = -x;
9977         }
9978         pos |= x << CURSOR_X_SHIFT;
9979
9980         if (y < 0) {
9981                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9982                         base = 0;
9983
9984                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9985                 y = -y;
9986         }
9987         pos |= y << CURSOR_Y_SHIFT;
9988
9989         if (base == 0 && intel_crtc->cursor_base == 0)
9990                 return;
9991
9992         I915_WRITE(CURPOS(pipe), pos);
9993
9994         /* ILK+ do this automagically */
9995         if (HAS_GMCH_DISPLAY(dev) &&
9996             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9997                 base += (intel_crtc->base.cursor->state->crtc_h *
9998                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9999         }
10000
10001         if (IS_845G(dev) || IS_I865G(dev))
10002                 i845_update_cursor(crtc, base);
10003         else
10004                 i9xx_update_cursor(crtc, base);
10005 }
10006
10007 static bool cursor_size_ok(struct drm_device *dev,
10008                            uint32_t width, uint32_t height)
10009 {
10010         if (width == 0 || height == 0)
10011                 return false;
10012
10013         /*
10014          * 845g/865g are special in that they are only limited by
10015          * the width of their cursors, the height is arbitrary up to
10016          * the precision of the register. Everything else requires
10017          * square cursors, limited to a few power-of-two sizes.
10018          */
10019         if (IS_845G(dev) || IS_I865G(dev)) {
10020                 if ((width & 63) != 0)
10021                         return false;
10022
10023                 if (width > (IS_845G(dev) ? 64 : 512))
10024                         return false;
10025
10026                 if (height > 1023)
10027                         return false;
10028         } else {
10029                 switch (width | height) {
10030                 case 256:
10031                 case 128:
10032                         if (IS_GEN2(dev))
10033                                 return false;
10034                 case 64:
10035                         break;
10036                 default:
10037                         return false;
10038                 }
10039         }
10040
10041         return true;
10042 }
10043
10044 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10045                                  u16 *blue, uint32_t start, uint32_t size)
10046 {
10047         int end = (start + size > 256) ? 256 : start + size, i;
10048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10049
10050         for (i = start; i < end; i++) {
10051                 intel_crtc->lut_r[i] = red[i] >> 8;
10052                 intel_crtc->lut_g[i] = green[i] >> 8;
10053                 intel_crtc->lut_b[i] = blue[i] >> 8;
10054         }
10055
10056         intel_crtc_load_lut(crtc);
10057 }
10058
10059 /* VESA 640x480x72Hz mode to set on the pipe */
10060 static struct drm_display_mode load_detect_mode = {
10061         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10062                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10063 };
10064
10065 struct drm_framebuffer *
10066 __intel_framebuffer_create(struct drm_device *dev,
10067                            struct drm_mode_fb_cmd2 *mode_cmd,
10068                            struct drm_i915_gem_object *obj)
10069 {
10070         struct intel_framebuffer *intel_fb;
10071         int ret;
10072
10073         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10074         if (!intel_fb) {
10075                 drm_gem_object_unreference(&obj->base);
10076                 return ERR_PTR(-ENOMEM);
10077         }
10078
10079         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10080         if (ret)
10081                 goto err;
10082
10083         return &intel_fb->base;
10084 err:
10085         drm_gem_object_unreference(&obj->base);
10086         kfree(intel_fb);
10087
10088         return ERR_PTR(ret);
10089 }
10090
10091 static struct drm_framebuffer *
10092 intel_framebuffer_create(struct drm_device *dev,
10093                          struct drm_mode_fb_cmd2 *mode_cmd,
10094                          struct drm_i915_gem_object *obj)
10095 {
10096         struct drm_framebuffer *fb;
10097         int ret;
10098
10099         ret = i915_mutex_lock_interruptible(dev);
10100         if (ret)
10101                 return ERR_PTR(ret);
10102         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10103         mutex_unlock(&dev->struct_mutex);
10104
10105         return fb;
10106 }
10107
10108 static u32
10109 intel_framebuffer_pitch_for_width(int width, int bpp)
10110 {
10111         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10112         return ALIGN(pitch, 64);
10113 }
10114
10115 static u32
10116 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10117 {
10118         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10119         return PAGE_ALIGN(pitch * mode->vdisplay);
10120 }
10121
10122 static struct drm_framebuffer *
10123 intel_framebuffer_create_for_mode(struct drm_device *dev,
10124                                   struct drm_display_mode *mode,
10125                                   int depth, int bpp)
10126 {
10127         struct drm_i915_gem_object *obj;
10128         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10129
10130         obj = i915_gem_alloc_object(dev,
10131                                     intel_framebuffer_size_for_mode(mode, bpp));
10132         if (obj == NULL)
10133                 return ERR_PTR(-ENOMEM);
10134
10135         mode_cmd.width = mode->hdisplay;
10136         mode_cmd.height = mode->vdisplay;
10137         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10138                                                                 bpp);
10139         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10140
10141         return intel_framebuffer_create(dev, &mode_cmd, obj);
10142 }
10143
10144 static struct drm_framebuffer *
10145 mode_fits_in_fbdev(struct drm_device *dev,
10146                    struct drm_display_mode *mode)
10147 {
10148 #ifdef CONFIG_DRM_I915_FBDEV
10149         struct drm_i915_private *dev_priv = dev->dev_private;
10150         struct drm_i915_gem_object *obj;
10151         struct drm_framebuffer *fb;
10152
10153         if (!dev_priv->fbdev)
10154                 return NULL;
10155
10156         if (!dev_priv->fbdev->fb)
10157                 return NULL;
10158
10159         obj = dev_priv->fbdev->fb->obj;
10160         BUG_ON(!obj);
10161
10162         fb = &dev_priv->fbdev->fb->base;
10163         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10164                                                                fb->bits_per_pixel))
10165                 return NULL;
10166
10167         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10168                 return NULL;
10169
10170         return fb;
10171 #else
10172         return NULL;
10173 #endif
10174 }
10175
10176 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10177                                            struct drm_crtc *crtc,
10178                                            struct drm_display_mode *mode,
10179                                            struct drm_framebuffer *fb,
10180                                            int x, int y)
10181 {
10182         struct drm_plane_state *plane_state;
10183         int hdisplay, vdisplay;
10184         int ret;
10185
10186         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10187         if (IS_ERR(plane_state))
10188                 return PTR_ERR(plane_state);
10189
10190         if (mode)
10191                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10192         else
10193                 hdisplay = vdisplay = 0;
10194
10195         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10196         if (ret)
10197                 return ret;
10198         drm_atomic_set_fb_for_plane(plane_state, fb);
10199         plane_state->crtc_x = 0;
10200         plane_state->crtc_y = 0;
10201         plane_state->crtc_w = hdisplay;
10202         plane_state->crtc_h = vdisplay;
10203         plane_state->src_x = x << 16;
10204         plane_state->src_y = y << 16;
10205         plane_state->src_w = hdisplay << 16;
10206         plane_state->src_h = vdisplay << 16;
10207
10208         return 0;
10209 }
10210
10211 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10212                                 struct drm_display_mode *mode,
10213                                 struct intel_load_detect_pipe *old,
10214                                 struct drm_modeset_acquire_ctx *ctx)
10215 {
10216         struct intel_crtc *intel_crtc;
10217         struct intel_encoder *intel_encoder =
10218                 intel_attached_encoder(connector);
10219         struct drm_crtc *possible_crtc;
10220         struct drm_encoder *encoder = &intel_encoder->base;
10221         struct drm_crtc *crtc = NULL;
10222         struct drm_device *dev = encoder->dev;
10223         struct drm_framebuffer *fb;
10224         struct drm_mode_config *config = &dev->mode_config;
10225         struct drm_atomic_state *state = NULL;
10226         struct drm_connector_state *connector_state;
10227         struct intel_crtc_state *crtc_state;
10228         int ret, i = -1;
10229
10230         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10231                       connector->base.id, connector->name,
10232                       encoder->base.id, encoder->name);
10233
10234 retry:
10235         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10236         if (ret)
10237                 goto fail_unlock;
10238
10239         /*
10240          * Algorithm gets a little messy:
10241          *
10242          *   - if the connector already has an assigned crtc, use it (but make
10243          *     sure it's on first)
10244          *
10245          *   - try to find the first unused crtc that can drive this connector,
10246          *     and use that if we find one
10247          */
10248
10249         /* See if we already have a CRTC for this connector */
10250         if (encoder->crtc) {
10251                 crtc = encoder->crtc;
10252
10253                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10254                 if (ret)
10255                         goto fail_unlock;
10256                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10257                 if (ret)
10258                         goto fail_unlock;
10259
10260                 old->dpms_mode = connector->dpms;
10261                 old->load_detect_temp = false;
10262
10263                 /* Make sure the crtc and connector are running */
10264                 if (connector->dpms != DRM_MODE_DPMS_ON)
10265                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10266
10267                 return true;
10268         }
10269
10270         /* Find an unused one (if possible) */
10271         for_each_crtc(dev, possible_crtc) {
10272                 i++;
10273                 if (!(encoder->possible_crtcs & (1 << i)))
10274                         continue;
10275                 if (possible_crtc->state->enable)
10276                         continue;
10277                 /* This can occur when applying the pipe A quirk on resume. */
10278                 if (to_intel_crtc(possible_crtc)->new_enabled)
10279                         continue;
10280
10281                 crtc = possible_crtc;
10282                 break;
10283         }
10284
10285         /*
10286          * If we didn't find an unused CRTC, don't use any.
10287          */
10288         if (!crtc) {
10289                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10290                 goto fail_unlock;
10291         }
10292
10293         ret = drm_modeset_lock(&crtc->mutex, ctx);
10294         if (ret)
10295                 goto fail_unlock;
10296         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10297         if (ret)
10298                 goto fail_unlock;
10299         intel_encoder->new_crtc = to_intel_crtc(crtc);
10300         to_intel_connector(connector)->new_encoder = intel_encoder;
10301
10302         intel_crtc = to_intel_crtc(crtc);
10303         intel_crtc->new_enabled = true;
10304         old->dpms_mode = connector->dpms;
10305         old->load_detect_temp = true;
10306         old->release_fb = NULL;
10307
10308         state = drm_atomic_state_alloc(dev);
10309         if (!state)
10310                 return false;
10311
10312         state->acquire_ctx = ctx;
10313
10314         connector_state = drm_atomic_get_connector_state(state, connector);
10315         if (IS_ERR(connector_state)) {
10316                 ret = PTR_ERR(connector_state);
10317                 goto fail;
10318         }
10319
10320         connector_state->crtc = crtc;
10321         connector_state->best_encoder = &intel_encoder->base;
10322
10323         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10324         if (IS_ERR(crtc_state)) {
10325                 ret = PTR_ERR(crtc_state);
10326                 goto fail;
10327         }
10328
10329         crtc_state->base.active = crtc_state->base.enable = true;
10330
10331         if (!mode)
10332                 mode = &load_detect_mode;
10333
10334         /* We need a framebuffer large enough to accommodate all accesses
10335          * that the plane may generate whilst we perform load detection.
10336          * We can not rely on the fbcon either being present (we get called
10337          * during its initialisation to detect all boot displays, or it may
10338          * not even exist) or that it is large enough to satisfy the
10339          * requested mode.
10340          */
10341         fb = mode_fits_in_fbdev(dev, mode);
10342         if (fb == NULL) {
10343                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10344                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10345                 old->release_fb = fb;
10346         } else
10347                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10348         if (IS_ERR(fb)) {
10349                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10350                 goto fail;
10351         }
10352
10353         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10354         if (ret)
10355                 goto fail;
10356
10357         drm_mode_copy(&crtc_state->base.mode, mode);
10358
10359         if (intel_set_mode(state)) {
10360                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10361                 if (old->release_fb)
10362                         old->release_fb->funcs->destroy(old->release_fb);
10363                 goto fail;
10364         }
10365         crtc->primary->crtc = crtc;
10366
10367         /* let the connector get through one full cycle before testing */
10368         intel_wait_for_vblank(dev, intel_crtc->pipe);
10369         return true;
10370
10371  fail:
10372         intel_crtc->new_enabled = crtc->state->enable;
10373 fail_unlock:
10374         drm_atomic_state_free(state);
10375         state = NULL;
10376
10377         if (ret == -EDEADLK) {
10378                 drm_modeset_backoff(ctx);
10379                 goto retry;
10380         }
10381
10382         return false;
10383 }
10384
10385 void intel_release_load_detect_pipe(struct drm_connector *connector,
10386                                     struct intel_load_detect_pipe *old,
10387                                     struct drm_modeset_acquire_ctx *ctx)
10388 {
10389         struct drm_device *dev = connector->dev;
10390         struct intel_encoder *intel_encoder =
10391                 intel_attached_encoder(connector);
10392         struct drm_encoder *encoder = &intel_encoder->base;
10393         struct drm_crtc *crtc = encoder->crtc;
10394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10395         struct drm_atomic_state *state;
10396         struct drm_connector_state *connector_state;
10397         struct intel_crtc_state *crtc_state;
10398         int ret;
10399
10400         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10401                       connector->base.id, connector->name,
10402                       encoder->base.id, encoder->name);
10403
10404         if (old->load_detect_temp) {
10405                 state = drm_atomic_state_alloc(dev);
10406                 if (!state)
10407                         goto fail;
10408
10409                 state->acquire_ctx = ctx;
10410
10411                 connector_state = drm_atomic_get_connector_state(state, connector);
10412                 if (IS_ERR(connector_state))
10413                         goto fail;
10414
10415                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10416                 if (IS_ERR(crtc_state))
10417                         goto fail;
10418
10419                 to_intel_connector(connector)->new_encoder = NULL;
10420                 intel_encoder->new_crtc = NULL;
10421                 intel_crtc->new_enabled = false;
10422
10423                 connector_state->best_encoder = NULL;
10424                 connector_state->crtc = NULL;
10425
10426                 crtc_state->base.enable = crtc_state->base.active = false;
10427
10428                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10429                                                       0, 0);
10430                 if (ret)
10431                         goto fail;
10432
10433                 ret = intel_set_mode(state);
10434                 if (ret)
10435                         goto fail;
10436
10437                 if (old->release_fb) {
10438                         drm_framebuffer_unregister_private(old->release_fb);
10439                         drm_framebuffer_unreference(old->release_fb);
10440                 }
10441
10442                 return;
10443         }
10444
10445         /* Switch crtc and encoder back off if necessary */
10446         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10447                 connector->funcs->dpms(connector, old->dpms_mode);
10448
10449         return;
10450 fail:
10451         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10452         drm_atomic_state_free(state);
10453 }
10454
10455 static int i9xx_pll_refclk(struct drm_device *dev,
10456                            const struct intel_crtc_state *pipe_config)
10457 {
10458         struct drm_i915_private *dev_priv = dev->dev_private;
10459         u32 dpll = pipe_config->dpll_hw_state.dpll;
10460
10461         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10462                 return dev_priv->vbt.lvds_ssc_freq;
10463         else if (HAS_PCH_SPLIT(dev))
10464                 return 120000;
10465         else if (!IS_GEN2(dev))
10466                 return 96000;
10467         else
10468                 return 48000;
10469 }
10470
10471 /* Returns the clock of the currently programmed mode of the given pipe. */
10472 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10473                                 struct intel_crtc_state *pipe_config)
10474 {
10475         struct drm_device *dev = crtc->base.dev;
10476         struct drm_i915_private *dev_priv = dev->dev_private;
10477         int pipe = pipe_config->cpu_transcoder;
10478         u32 dpll = pipe_config->dpll_hw_state.dpll;
10479         u32 fp;
10480         intel_clock_t clock;
10481         int port_clock;
10482         int refclk = i9xx_pll_refclk(dev, pipe_config);
10483
10484         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10485                 fp = pipe_config->dpll_hw_state.fp0;
10486         else
10487                 fp = pipe_config->dpll_hw_state.fp1;
10488
10489         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10490         if (IS_PINEVIEW(dev)) {
10491                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10492                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10493         } else {
10494                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10495                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10496         }
10497
10498         if (!IS_GEN2(dev)) {
10499                 if (IS_PINEVIEW(dev))
10500                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10501                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10502                 else
10503                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10504                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10505
10506                 switch (dpll & DPLL_MODE_MASK) {
10507                 case DPLLB_MODE_DAC_SERIAL:
10508                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10509                                 5 : 10;
10510                         break;
10511                 case DPLLB_MODE_LVDS:
10512                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10513                                 7 : 14;
10514                         break;
10515                 default:
10516                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10517                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10518                         return;
10519                 }
10520
10521                 if (IS_PINEVIEW(dev))
10522                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10523                 else
10524                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10525         } else {
10526                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10527                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10528
10529                 if (is_lvds) {
10530                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10531                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10532
10533                         if (lvds & LVDS_CLKB_POWER_UP)
10534                                 clock.p2 = 7;
10535                         else
10536                                 clock.p2 = 14;
10537                 } else {
10538                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10539                                 clock.p1 = 2;
10540                         else {
10541                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10542                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10543                         }
10544                         if (dpll & PLL_P2_DIVIDE_BY_4)
10545                                 clock.p2 = 4;
10546                         else
10547                                 clock.p2 = 2;
10548                 }
10549
10550                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10551         }
10552
10553         /*
10554          * This value includes pixel_multiplier. We will use
10555          * port_clock to compute adjusted_mode.crtc_clock in the
10556          * encoder's get_config() function.
10557          */
10558         pipe_config->port_clock = port_clock;
10559 }
10560
10561 int intel_dotclock_calculate(int link_freq,
10562                              const struct intel_link_m_n *m_n)
10563 {
10564         /*
10565          * The calculation for the data clock is:
10566          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10567          * But we want to avoid losing precison if possible, so:
10568          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10569          *
10570          * and the link clock is simpler:
10571          * link_clock = (m * link_clock) / n
10572          */
10573
10574         if (!m_n->link_n)
10575                 return 0;
10576
10577         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10578 }
10579
10580 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10581                                    struct intel_crtc_state *pipe_config)
10582 {
10583         struct drm_device *dev = crtc->base.dev;
10584
10585         /* read out port_clock from the DPLL */
10586         i9xx_crtc_clock_get(crtc, pipe_config);
10587
10588         /*
10589          * This value does not include pixel_multiplier.
10590          * We will check that port_clock and adjusted_mode.crtc_clock
10591          * agree once we know their relationship in the encoder's
10592          * get_config() function.
10593          */
10594         pipe_config->base.adjusted_mode.crtc_clock =
10595                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10596                                          &pipe_config->fdi_m_n);
10597 }
10598
10599 /** Returns the currently programmed mode of the given pipe. */
10600 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10601                                              struct drm_crtc *crtc)
10602 {
10603         struct drm_i915_private *dev_priv = dev->dev_private;
10604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10605         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10606         struct drm_display_mode *mode;
10607         struct intel_crtc_state pipe_config;
10608         int htot = I915_READ(HTOTAL(cpu_transcoder));
10609         int hsync = I915_READ(HSYNC(cpu_transcoder));
10610         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10611         int vsync = I915_READ(VSYNC(cpu_transcoder));
10612         enum pipe pipe = intel_crtc->pipe;
10613
10614         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10615         if (!mode)
10616                 return NULL;
10617
10618         /*
10619          * Construct a pipe_config sufficient for getting the clock info
10620          * back out of crtc_clock_get.
10621          *
10622          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10623          * to use a real value here instead.
10624          */
10625         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10626         pipe_config.pixel_multiplier = 1;
10627         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10628         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10629         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10630         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10631
10632         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10633         mode->hdisplay = (htot & 0xffff) + 1;
10634         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10635         mode->hsync_start = (hsync & 0xffff) + 1;
10636         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10637         mode->vdisplay = (vtot & 0xffff) + 1;
10638         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10639         mode->vsync_start = (vsync & 0xffff) + 1;
10640         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10641
10642         drm_mode_set_name(mode);
10643
10644         return mode;
10645 }
10646
10647 void intel_mark_busy(struct drm_device *dev)
10648 {
10649         struct drm_i915_private *dev_priv = dev->dev_private;
10650
10651         if (dev_priv->mm.busy)
10652                 return;
10653
10654         intel_runtime_pm_get(dev_priv);
10655         i915_update_gfx_val(dev_priv);
10656         if (INTEL_INFO(dev)->gen >= 6)
10657                 gen6_rps_busy(dev_priv);
10658         dev_priv->mm.busy = true;
10659 }
10660
10661 void intel_mark_idle(struct drm_device *dev)
10662 {
10663         struct drm_i915_private *dev_priv = dev->dev_private;
10664
10665         if (!dev_priv->mm.busy)
10666                 return;
10667
10668         dev_priv->mm.busy = false;
10669
10670         if (INTEL_INFO(dev)->gen >= 6)
10671                 gen6_rps_idle(dev->dev_private);
10672
10673         intel_runtime_pm_put(dev_priv);
10674 }
10675
10676 static void intel_crtc_destroy(struct drm_crtc *crtc)
10677 {
10678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10679         struct drm_device *dev = crtc->dev;
10680         struct intel_unpin_work *work;
10681
10682         spin_lock_irq(&dev->event_lock);
10683         work = intel_crtc->unpin_work;
10684         intel_crtc->unpin_work = NULL;
10685         spin_unlock_irq(&dev->event_lock);
10686
10687         if (work) {
10688                 cancel_work_sync(&work->work);
10689                 kfree(work);
10690         }
10691
10692         drm_crtc_cleanup(crtc);
10693
10694         kfree(intel_crtc);
10695 }
10696
10697 static void intel_unpin_work_fn(struct work_struct *__work)
10698 {
10699         struct intel_unpin_work *work =
10700                 container_of(__work, struct intel_unpin_work, work);
10701         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10702         struct drm_device *dev = crtc->base.dev;
10703         struct drm_i915_private *dev_priv = dev->dev_private;
10704         struct drm_plane *primary = crtc->base.primary;
10705
10706         mutex_lock(&dev->struct_mutex);
10707         intel_unpin_fb_obj(work->old_fb, primary->state);
10708         drm_gem_object_unreference(&work->pending_flip_obj->base);
10709
10710         intel_fbc_update(dev_priv);
10711
10712         if (work->flip_queued_req)
10713                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10714         mutex_unlock(&dev->struct_mutex);
10715
10716         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10717         drm_framebuffer_unreference(work->old_fb);
10718
10719         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10720         atomic_dec(&crtc->unpin_work_count);
10721
10722         kfree(work);
10723 }
10724
10725 static void do_intel_finish_page_flip(struct drm_device *dev,
10726                                       struct drm_crtc *crtc)
10727 {
10728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10729         struct intel_unpin_work *work;
10730         unsigned long flags;
10731
10732         /* Ignore early vblank irqs */
10733         if (intel_crtc == NULL)
10734                 return;
10735
10736         /*
10737          * This is called both by irq handlers and the reset code (to complete
10738          * lost pageflips) so needs the full irqsave spinlocks.
10739          */
10740         spin_lock_irqsave(&dev->event_lock, flags);
10741         work = intel_crtc->unpin_work;
10742
10743         /* Ensure we don't miss a work->pending update ... */
10744         smp_rmb();
10745
10746         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10747                 spin_unlock_irqrestore(&dev->event_lock, flags);
10748                 return;
10749         }
10750
10751         page_flip_completed(intel_crtc);
10752
10753         spin_unlock_irqrestore(&dev->event_lock, flags);
10754 }
10755
10756 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10757 {
10758         struct drm_i915_private *dev_priv = dev->dev_private;
10759         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10760
10761         do_intel_finish_page_flip(dev, crtc);
10762 }
10763
10764 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10765 {
10766         struct drm_i915_private *dev_priv = dev->dev_private;
10767         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10768
10769         do_intel_finish_page_flip(dev, crtc);
10770 }
10771
10772 /* Is 'a' after or equal to 'b'? */
10773 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10774 {
10775         return !((a - b) & 0x80000000);
10776 }
10777
10778 static bool page_flip_finished(struct intel_crtc *crtc)
10779 {
10780         struct drm_device *dev = crtc->base.dev;
10781         struct drm_i915_private *dev_priv = dev->dev_private;
10782
10783         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10784             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10785                 return true;
10786
10787         /*
10788          * The relevant registers doen't exist on pre-ctg.
10789          * As the flip done interrupt doesn't trigger for mmio
10790          * flips on gmch platforms, a flip count check isn't
10791          * really needed there. But since ctg has the registers,
10792          * include it in the check anyway.
10793          */
10794         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10795                 return true;
10796
10797         /*
10798          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10799          * used the same base address. In that case the mmio flip might
10800          * have completed, but the CS hasn't even executed the flip yet.
10801          *
10802          * A flip count check isn't enough as the CS might have updated
10803          * the base address just after start of vblank, but before we
10804          * managed to process the interrupt. This means we'd complete the
10805          * CS flip too soon.
10806          *
10807          * Combining both checks should get us a good enough result. It may
10808          * still happen that the CS flip has been executed, but has not
10809          * yet actually completed. But in case the base address is the same
10810          * anyway, we don't really care.
10811          */
10812         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10813                 crtc->unpin_work->gtt_offset &&
10814                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10815                                     crtc->unpin_work->flip_count);
10816 }
10817
10818 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10819 {
10820         struct drm_i915_private *dev_priv = dev->dev_private;
10821         struct intel_crtc *intel_crtc =
10822                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10823         unsigned long flags;
10824
10825
10826         /*
10827          * This is called both by irq handlers and the reset code (to complete
10828          * lost pageflips) so needs the full irqsave spinlocks.
10829          *
10830          * NB: An MMIO update of the plane base pointer will also
10831          * generate a page-flip completion irq, i.e. every modeset
10832          * is also accompanied by a spurious intel_prepare_page_flip().
10833          */
10834         spin_lock_irqsave(&dev->event_lock, flags);
10835         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10836                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10837         spin_unlock_irqrestore(&dev->event_lock, flags);
10838 }
10839
10840 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10841 {
10842         /* Ensure that the work item is consistent when activating it ... */
10843         smp_wmb();
10844         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10845         /* and that it is marked active as soon as the irq could fire. */
10846         smp_wmb();
10847 }
10848
10849 static int intel_gen2_queue_flip(struct drm_device *dev,
10850                                  struct drm_crtc *crtc,
10851                                  struct drm_framebuffer *fb,
10852                                  struct drm_i915_gem_object *obj,
10853                                  struct drm_i915_gem_request *req,
10854                                  uint32_t flags)
10855 {
10856         struct intel_engine_cs *ring = req->ring;
10857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10858         u32 flip_mask;
10859         int ret;
10860
10861         ret = intel_ring_begin(req, 6);
10862         if (ret)
10863                 return ret;
10864
10865         /* Can't queue multiple flips, so wait for the previous
10866          * one to finish before executing the next.
10867          */
10868         if (intel_crtc->plane)
10869                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10870         else
10871                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10872         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10873         intel_ring_emit(ring, MI_NOOP);
10874         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10875                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10876         intel_ring_emit(ring, fb->pitches[0]);
10877         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10878         intel_ring_emit(ring, 0); /* aux display base address, unused */
10879
10880         intel_mark_page_flip_active(intel_crtc);
10881         return 0;
10882 }
10883
10884 static int intel_gen3_queue_flip(struct drm_device *dev,
10885                                  struct drm_crtc *crtc,
10886                                  struct drm_framebuffer *fb,
10887                                  struct drm_i915_gem_object *obj,
10888                                  struct drm_i915_gem_request *req,
10889                                  uint32_t flags)
10890 {
10891         struct intel_engine_cs *ring = req->ring;
10892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10893         u32 flip_mask;
10894         int ret;
10895
10896         ret = intel_ring_begin(req, 6);
10897         if (ret)
10898                 return ret;
10899
10900         if (intel_crtc->plane)
10901                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10902         else
10903                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10904         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10905         intel_ring_emit(ring, MI_NOOP);
10906         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10907                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10908         intel_ring_emit(ring, fb->pitches[0]);
10909         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10910         intel_ring_emit(ring, MI_NOOP);
10911
10912         intel_mark_page_flip_active(intel_crtc);
10913         return 0;
10914 }
10915
10916 static int intel_gen4_queue_flip(struct drm_device *dev,
10917                                  struct drm_crtc *crtc,
10918                                  struct drm_framebuffer *fb,
10919                                  struct drm_i915_gem_object *obj,
10920                                  struct drm_i915_gem_request *req,
10921                                  uint32_t flags)
10922 {
10923         struct intel_engine_cs *ring = req->ring;
10924         struct drm_i915_private *dev_priv = dev->dev_private;
10925         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10926         uint32_t pf, pipesrc;
10927         int ret;
10928
10929         ret = intel_ring_begin(req, 4);
10930         if (ret)
10931                 return ret;
10932
10933         /* i965+ uses the linear or tiled offsets from the
10934          * Display Registers (which do not change across a page-flip)
10935          * so we need only reprogram the base address.
10936          */
10937         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10938                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10939         intel_ring_emit(ring, fb->pitches[0]);
10940         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10941                         obj->tiling_mode);
10942
10943         /* XXX Enabling the panel-fitter across page-flip is so far
10944          * untested on non-native modes, so ignore it for now.
10945          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10946          */
10947         pf = 0;
10948         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10949         intel_ring_emit(ring, pf | pipesrc);
10950
10951         intel_mark_page_flip_active(intel_crtc);
10952         return 0;
10953 }
10954
10955 static int intel_gen6_queue_flip(struct drm_device *dev,
10956                                  struct drm_crtc *crtc,
10957                                  struct drm_framebuffer *fb,
10958                                  struct drm_i915_gem_object *obj,
10959                                  struct drm_i915_gem_request *req,
10960                                  uint32_t flags)
10961 {
10962         struct intel_engine_cs *ring = req->ring;
10963         struct drm_i915_private *dev_priv = dev->dev_private;
10964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10965         uint32_t pf, pipesrc;
10966         int ret;
10967
10968         ret = intel_ring_begin(req, 4);
10969         if (ret)
10970                 return ret;
10971
10972         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10973                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10974         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10975         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10976
10977         /* Contrary to the suggestions in the documentation,
10978          * "Enable Panel Fitter" does not seem to be required when page
10979          * flipping with a non-native mode, and worse causes a normal
10980          * modeset to fail.
10981          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10982          */
10983         pf = 0;
10984         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10985         intel_ring_emit(ring, pf | pipesrc);
10986
10987         intel_mark_page_flip_active(intel_crtc);
10988         return 0;
10989 }
10990
10991 static int intel_gen7_queue_flip(struct drm_device *dev,
10992                                  struct drm_crtc *crtc,
10993                                  struct drm_framebuffer *fb,
10994                                  struct drm_i915_gem_object *obj,
10995                                  struct drm_i915_gem_request *req,
10996                                  uint32_t flags)
10997 {
10998         struct intel_engine_cs *ring = req->ring;
10999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11000         uint32_t plane_bit = 0;
11001         int len, ret;
11002
11003         switch (intel_crtc->plane) {
11004         case PLANE_A:
11005                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11006                 break;
11007         case PLANE_B:
11008                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11009                 break;
11010         case PLANE_C:
11011                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11012                 break;
11013         default:
11014                 WARN_ONCE(1, "unknown plane in flip command\n");
11015                 return -ENODEV;
11016         }
11017
11018         len = 4;
11019         if (ring->id == RCS) {
11020                 len += 6;
11021                 /*
11022                  * On Gen 8, SRM is now taking an extra dword to accommodate
11023                  * 48bits addresses, and we need a NOOP for the batch size to
11024                  * stay even.
11025                  */
11026                 if (IS_GEN8(dev))
11027                         len += 2;
11028         }
11029
11030         /*
11031          * BSpec MI_DISPLAY_FLIP for IVB:
11032          * "The full packet must be contained within the same cache line."
11033          *
11034          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11035          * cacheline, if we ever start emitting more commands before
11036          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11037          * then do the cacheline alignment, and finally emit the
11038          * MI_DISPLAY_FLIP.
11039          */
11040         ret = intel_ring_cacheline_align(req);
11041         if (ret)
11042                 return ret;
11043
11044         ret = intel_ring_begin(req, len);
11045         if (ret)
11046                 return ret;
11047
11048         /* Unmask the flip-done completion message. Note that the bspec says that
11049          * we should do this for both the BCS and RCS, and that we must not unmask
11050          * more than one flip event at any time (or ensure that one flip message
11051          * can be sent by waiting for flip-done prior to queueing new flips).
11052          * Experimentation says that BCS works despite DERRMR masking all
11053          * flip-done completion events and that unmasking all planes at once
11054          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11055          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11056          */
11057         if (ring->id == RCS) {
11058                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11059                 intel_ring_emit(ring, DERRMR);
11060                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11061                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11062                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11063                 if (IS_GEN8(dev))
11064                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11065                                               MI_SRM_LRM_GLOBAL_GTT);
11066                 else
11067                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11068                                               MI_SRM_LRM_GLOBAL_GTT);
11069                 intel_ring_emit(ring, DERRMR);
11070                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11071                 if (IS_GEN8(dev)) {
11072                         intel_ring_emit(ring, 0);
11073                         intel_ring_emit(ring, MI_NOOP);
11074                 }
11075         }
11076
11077         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11078         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11079         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11080         intel_ring_emit(ring, (MI_NOOP));
11081
11082         intel_mark_page_flip_active(intel_crtc);
11083         return 0;
11084 }
11085
11086 static bool use_mmio_flip(struct intel_engine_cs *ring,
11087                           struct drm_i915_gem_object *obj)
11088 {
11089         /*
11090          * This is not being used for older platforms, because
11091          * non-availability of flip done interrupt forces us to use
11092          * CS flips. Older platforms derive flip done using some clever
11093          * tricks involving the flip_pending status bits and vblank irqs.
11094          * So using MMIO flips there would disrupt this mechanism.
11095          */
11096
11097         if (ring == NULL)
11098                 return true;
11099
11100         if (INTEL_INFO(ring->dev)->gen < 5)
11101                 return false;
11102
11103         if (i915.use_mmio_flip < 0)
11104                 return false;
11105         else if (i915.use_mmio_flip > 0)
11106                 return true;
11107         else if (i915.enable_execlists)
11108                 return true;
11109         else
11110                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11111 }
11112
11113 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11114 {
11115         struct drm_device *dev = intel_crtc->base.dev;
11116         struct drm_i915_private *dev_priv = dev->dev_private;
11117         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11118         const enum pipe pipe = intel_crtc->pipe;
11119         u32 ctl, stride;
11120
11121         ctl = I915_READ(PLANE_CTL(pipe, 0));
11122         ctl &= ~PLANE_CTL_TILED_MASK;
11123         switch (fb->modifier[0]) {
11124         case DRM_FORMAT_MOD_NONE:
11125                 break;
11126         case I915_FORMAT_MOD_X_TILED:
11127                 ctl |= PLANE_CTL_TILED_X;
11128                 break;
11129         case I915_FORMAT_MOD_Y_TILED:
11130                 ctl |= PLANE_CTL_TILED_Y;
11131                 break;
11132         case I915_FORMAT_MOD_Yf_TILED:
11133                 ctl |= PLANE_CTL_TILED_YF;
11134                 break;
11135         default:
11136                 MISSING_CASE(fb->modifier[0]);
11137         }
11138
11139         /*
11140          * The stride is either expressed as a multiple of 64 bytes chunks for
11141          * linear buffers or in number of tiles for tiled buffers.
11142          */
11143         stride = fb->pitches[0] /
11144                  intel_fb_stride_alignment(dev, fb->modifier[0],
11145                                            fb->pixel_format);
11146
11147         /*
11148          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11149          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11150          */
11151         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11152         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11153
11154         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11155         POSTING_READ(PLANE_SURF(pipe, 0));
11156 }
11157
11158 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11159 {
11160         struct drm_device *dev = intel_crtc->base.dev;
11161         struct drm_i915_private *dev_priv = dev->dev_private;
11162         struct intel_framebuffer *intel_fb =
11163                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11164         struct drm_i915_gem_object *obj = intel_fb->obj;
11165         u32 dspcntr;
11166         u32 reg;
11167
11168         reg = DSPCNTR(intel_crtc->plane);
11169         dspcntr = I915_READ(reg);
11170
11171         if (obj->tiling_mode != I915_TILING_NONE)
11172                 dspcntr |= DISPPLANE_TILED;
11173         else
11174                 dspcntr &= ~DISPPLANE_TILED;
11175
11176         I915_WRITE(reg, dspcntr);
11177
11178         I915_WRITE(DSPSURF(intel_crtc->plane),
11179                    intel_crtc->unpin_work->gtt_offset);
11180         POSTING_READ(DSPSURF(intel_crtc->plane));
11181
11182 }
11183
11184 /*
11185  * XXX: This is the temporary way to update the plane registers until we get
11186  * around to using the usual plane update functions for MMIO flips
11187  */
11188 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11189 {
11190         struct drm_device *dev = intel_crtc->base.dev;
11191         bool atomic_update;
11192         u32 start_vbl_count;
11193
11194         intel_mark_page_flip_active(intel_crtc);
11195
11196         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11197
11198         if (INTEL_INFO(dev)->gen >= 9)
11199                 skl_do_mmio_flip(intel_crtc);
11200         else
11201                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11202                 ilk_do_mmio_flip(intel_crtc);
11203
11204         if (atomic_update)
11205                 intel_pipe_update_end(intel_crtc, start_vbl_count);
11206 }
11207
11208 static void intel_mmio_flip_work_func(struct work_struct *work)
11209 {
11210         struct intel_mmio_flip *mmio_flip =
11211                 container_of(work, struct intel_mmio_flip, work);
11212
11213         if (mmio_flip->req)
11214                 WARN_ON(__i915_wait_request(mmio_flip->req,
11215                                             mmio_flip->crtc->reset_counter,
11216                                             false, NULL,
11217                                             &mmio_flip->i915->rps.mmioflips));
11218
11219         intel_do_mmio_flip(mmio_flip->crtc);
11220
11221         i915_gem_request_unreference__unlocked(mmio_flip->req);
11222         kfree(mmio_flip);
11223 }
11224
11225 static int intel_queue_mmio_flip(struct drm_device *dev,
11226                                  struct drm_crtc *crtc,
11227                                  struct drm_framebuffer *fb,
11228                                  struct drm_i915_gem_object *obj,
11229                                  struct intel_engine_cs *ring,
11230                                  uint32_t flags)
11231 {
11232         struct intel_mmio_flip *mmio_flip;
11233
11234         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11235         if (mmio_flip == NULL)
11236                 return -ENOMEM;
11237
11238         mmio_flip->i915 = to_i915(dev);
11239         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11240         mmio_flip->crtc = to_intel_crtc(crtc);
11241
11242         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11243         schedule_work(&mmio_flip->work);
11244
11245         return 0;
11246 }
11247
11248 static int intel_default_queue_flip(struct drm_device *dev,
11249                                     struct drm_crtc *crtc,
11250                                     struct drm_framebuffer *fb,
11251                                     struct drm_i915_gem_object *obj,
11252                                     struct drm_i915_gem_request *req,
11253                                     uint32_t flags)
11254 {
11255         return -ENODEV;
11256 }
11257
11258 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11259                                          struct drm_crtc *crtc)
11260 {
11261         struct drm_i915_private *dev_priv = dev->dev_private;
11262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11263         struct intel_unpin_work *work = intel_crtc->unpin_work;
11264         u32 addr;
11265
11266         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11267                 return true;
11268
11269         if (!work->enable_stall_check)
11270                 return false;
11271
11272         if (work->flip_ready_vblank == 0) {
11273                 if (work->flip_queued_req &&
11274                     !i915_gem_request_completed(work->flip_queued_req, true))
11275                         return false;
11276
11277                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11278         }
11279
11280         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11281                 return false;
11282
11283         /* Potential stall - if we see that the flip has happened,
11284          * assume a missed interrupt. */
11285         if (INTEL_INFO(dev)->gen >= 4)
11286                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11287         else
11288                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11289
11290         /* There is a potential issue here with a false positive after a flip
11291          * to the same address. We could address this by checking for a
11292          * non-incrementing frame counter.
11293          */
11294         return addr == work->gtt_offset;
11295 }
11296
11297 void intel_check_page_flip(struct drm_device *dev, int pipe)
11298 {
11299         struct drm_i915_private *dev_priv = dev->dev_private;
11300         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11301         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11302         struct intel_unpin_work *work;
11303
11304         WARN_ON(!in_interrupt());
11305
11306         if (crtc == NULL)
11307                 return;
11308
11309         spin_lock(&dev->event_lock);
11310         work = intel_crtc->unpin_work;
11311         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11312                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11313                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11314                 page_flip_completed(intel_crtc);
11315                 work = NULL;
11316         }
11317         if (work != NULL &&
11318             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11319                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11320         spin_unlock(&dev->event_lock);
11321 }
11322
11323 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11324                                 struct drm_framebuffer *fb,
11325                                 struct drm_pending_vblank_event *event,
11326                                 uint32_t page_flip_flags)
11327 {
11328         struct drm_device *dev = crtc->dev;
11329         struct drm_i915_private *dev_priv = dev->dev_private;
11330         struct drm_framebuffer *old_fb = crtc->primary->fb;
11331         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11333         struct drm_plane *primary = crtc->primary;
11334         enum pipe pipe = intel_crtc->pipe;
11335         struct intel_unpin_work *work;
11336         struct intel_engine_cs *ring;
11337         bool mmio_flip;
11338         struct drm_i915_gem_request *request = NULL;
11339         int ret;
11340
11341         /*
11342          * drm_mode_page_flip_ioctl() should already catch this, but double
11343          * check to be safe.  In the future we may enable pageflipping from
11344          * a disabled primary plane.
11345          */
11346         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11347                 return -EBUSY;
11348
11349         /* Can't change pixel format via MI display flips. */
11350         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11351                 return -EINVAL;
11352
11353         /*
11354          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11355          * Note that pitch changes could also affect these register.
11356          */
11357         if (INTEL_INFO(dev)->gen > 3 &&
11358             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11359              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11360                 return -EINVAL;
11361
11362         if (i915_terminally_wedged(&dev_priv->gpu_error))
11363                 goto out_hang;
11364
11365         work = kzalloc(sizeof(*work), GFP_KERNEL);
11366         if (work == NULL)
11367                 return -ENOMEM;
11368
11369         work->event = event;
11370         work->crtc = crtc;
11371         work->old_fb = old_fb;
11372         INIT_WORK(&work->work, intel_unpin_work_fn);
11373
11374         ret = drm_crtc_vblank_get(crtc);
11375         if (ret)
11376                 goto free_work;
11377
11378         /* We borrow the event spin lock for protecting unpin_work */
11379         spin_lock_irq(&dev->event_lock);
11380         if (intel_crtc->unpin_work) {
11381                 /* Before declaring the flip queue wedged, check if
11382                  * the hardware completed the operation behind our backs.
11383                  */
11384                 if (__intel_pageflip_stall_check(dev, crtc)) {
11385                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11386                         page_flip_completed(intel_crtc);
11387                 } else {
11388                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11389                         spin_unlock_irq(&dev->event_lock);
11390
11391                         drm_crtc_vblank_put(crtc);
11392                         kfree(work);
11393                         return -EBUSY;
11394                 }
11395         }
11396         intel_crtc->unpin_work = work;
11397         spin_unlock_irq(&dev->event_lock);
11398
11399         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11400                 flush_workqueue(dev_priv->wq);
11401
11402         /* Reference the objects for the scheduled work. */
11403         drm_framebuffer_reference(work->old_fb);
11404         drm_gem_object_reference(&obj->base);
11405
11406         crtc->primary->fb = fb;
11407         update_state_fb(crtc->primary);
11408
11409         work->pending_flip_obj = obj;
11410
11411         ret = i915_mutex_lock_interruptible(dev);
11412         if (ret)
11413                 goto cleanup;
11414
11415         atomic_inc(&intel_crtc->unpin_work_count);
11416         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11417
11418         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11419                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11420
11421         if (IS_VALLEYVIEW(dev)) {
11422                 ring = &dev_priv->ring[BCS];
11423                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11424                         /* vlv: DISPLAY_FLIP fails to change tiling */
11425                         ring = NULL;
11426         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11427                 ring = &dev_priv->ring[BCS];
11428         } else if (INTEL_INFO(dev)->gen >= 7) {
11429                 ring = i915_gem_request_get_ring(obj->last_write_req);
11430                 if (ring == NULL || ring->id != RCS)
11431                         ring = &dev_priv->ring[BCS];
11432         } else {
11433                 ring = &dev_priv->ring[RCS];
11434         }
11435
11436         mmio_flip = use_mmio_flip(ring, obj);
11437
11438         /* When using CS flips, we want to emit semaphores between rings.
11439          * However, when using mmio flips we will create a task to do the
11440          * synchronisation, so all we want here is to pin the framebuffer
11441          * into the display plane and skip any waits.
11442          */
11443         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11444                                          crtc->primary->state,
11445                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11446         if (ret)
11447                 goto cleanup_pending;
11448
11449         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11450                                                   + intel_crtc->dspaddr_offset;
11451
11452         if (mmio_flip) {
11453                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11454                                             page_flip_flags);
11455                 if (ret)
11456                         goto cleanup_unpin;
11457
11458                 i915_gem_request_assign(&work->flip_queued_req,
11459                                         obj->last_write_req);
11460         } else {
11461                 if (!request) {
11462                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11463                         if (ret)
11464                                 goto cleanup_unpin;
11465                 }
11466
11467                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11468                                                    page_flip_flags);
11469                 if (ret)
11470                         goto cleanup_unpin;
11471
11472                 i915_gem_request_assign(&work->flip_queued_req, request);
11473         }
11474
11475         if (request)
11476                 i915_add_request_no_flush(request);
11477
11478         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11479         work->enable_stall_check = true;
11480
11481         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11482                           to_intel_plane(primary)->frontbuffer_bit);
11483         mutex_unlock(&dev->struct_mutex);
11484
11485         intel_fbc_disable(dev_priv);
11486         intel_frontbuffer_flip_prepare(dev,
11487                                        to_intel_plane(primary)->frontbuffer_bit);
11488
11489         trace_i915_flip_request(intel_crtc->plane, obj);
11490
11491         return 0;
11492
11493 cleanup_unpin:
11494         intel_unpin_fb_obj(fb, crtc->primary->state);
11495 cleanup_pending:
11496         if (request)
11497                 i915_gem_request_cancel(request);
11498         atomic_dec(&intel_crtc->unpin_work_count);
11499         mutex_unlock(&dev->struct_mutex);
11500 cleanup:
11501         crtc->primary->fb = old_fb;
11502         update_state_fb(crtc->primary);
11503
11504         drm_gem_object_unreference_unlocked(&obj->base);
11505         drm_framebuffer_unreference(work->old_fb);
11506
11507         spin_lock_irq(&dev->event_lock);
11508         intel_crtc->unpin_work = NULL;
11509         spin_unlock_irq(&dev->event_lock);
11510
11511         drm_crtc_vblank_put(crtc);
11512 free_work:
11513         kfree(work);
11514
11515         if (ret == -EIO) {
11516                 struct drm_atomic_state *state;
11517                 struct drm_plane_state *plane_state;
11518
11519 out_hang:
11520                 state = drm_atomic_state_alloc(dev);
11521                 if (!state)
11522                         return -ENOMEM;
11523                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11524
11525 retry:
11526                 plane_state = drm_atomic_get_plane_state(state, primary);
11527                 ret = PTR_ERR_OR_ZERO(plane_state);
11528                 if (!ret) {
11529                         drm_atomic_set_fb_for_plane(plane_state, fb);
11530
11531                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11532                         if (!ret)
11533                                 ret = drm_atomic_commit(state);
11534                 }
11535
11536                 if (ret == -EDEADLK) {
11537                         drm_modeset_backoff(state->acquire_ctx);
11538                         drm_atomic_state_clear(state);
11539                         goto retry;
11540                 }
11541
11542                 if (ret)
11543                         drm_atomic_state_free(state);
11544
11545                 if (ret == 0 && event) {
11546                         spin_lock_irq(&dev->event_lock);
11547                         drm_send_vblank_event(dev, pipe, event);
11548                         spin_unlock_irq(&dev->event_lock);
11549                 }
11550         }
11551         return ret;
11552 }
11553
11554
11555 /**
11556  * intel_wm_need_update - Check whether watermarks need updating
11557  * @plane: drm plane
11558  * @state: new plane state
11559  *
11560  * Check current plane state versus the new one to determine whether
11561  * watermarks need to be recalculated.
11562  *
11563  * Returns true or false.
11564  */
11565 static bool intel_wm_need_update(struct drm_plane *plane,
11566                                  struct drm_plane_state *state)
11567 {
11568         /* Update watermarks on tiling changes. */
11569         if (!plane->state->fb || !state->fb ||
11570             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11571             plane->state->rotation != state->rotation)
11572                 return true;
11573
11574         if (plane->state->crtc_w != state->crtc_w)
11575                 return true;
11576
11577         return false;
11578 }
11579
11580 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11581                                     struct drm_plane_state *plane_state)
11582 {
11583         struct drm_crtc *crtc = crtc_state->crtc;
11584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11585         struct drm_plane *plane = plane_state->plane;
11586         struct drm_device *dev = crtc->dev;
11587         struct drm_i915_private *dev_priv = dev->dev_private;
11588         struct intel_plane_state *old_plane_state =
11589                 to_intel_plane_state(plane->state);
11590         int idx = intel_crtc->base.base.id, ret;
11591         int i = drm_plane_index(plane);
11592         bool mode_changed = needs_modeset(crtc_state);
11593         bool was_crtc_enabled = crtc->state->active;
11594         bool is_crtc_enabled = crtc_state->active;
11595
11596         bool turn_off, turn_on, visible, was_visible;
11597         struct drm_framebuffer *fb = plane_state->fb;
11598
11599         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11600             plane->type != DRM_PLANE_TYPE_CURSOR) {
11601                 ret = skl_update_scaler_plane(
11602                         to_intel_crtc_state(crtc_state),
11603                         to_intel_plane_state(plane_state));
11604                 if (ret)
11605                         return ret;
11606         }
11607
11608         /*
11609          * Disabling a plane is always okay; we just need to update
11610          * fb tracking in a special way since cleanup_fb() won't
11611          * get called by the plane helpers.
11612          */
11613         if (old_plane_state->base.fb && !fb)
11614                 intel_crtc->atomic.disabled_planes |= 1 << i;
11615
11616         was_visible = old_plane_state->visible;
11617         visible = to_intel_plane_state(plane_state)->visible;
11618
11619         if (!was_crtc_enabled && WARN_ON(was_visible))
11620                 was_visible = false;
11621
11622         if (!is_crtc_enabled && WARN_ON(visible))
11623                 visible = false;
11624
11625         if (!was_visible && !visible)
11626                 return 0;
11627
11628         turn_off = was_visible && (!visible || mode_changed);
11629         turn_on = visible && (!was_visible || mode_changed);
11630
11631         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11632                          plane->base.id, fb ? fb->base.id : -1);
11633
11634         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11635                          plane->base.id, was_visible, visible,
11636                          turn_off, turn_on, mode_changed);
11637
11638         if (turn_on) {
11639                 intel_crtc->atomic.update_wm_pre = true;
11640                 /* must disable cxsr around plane enable/disable */
11641                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11642                         intel_crtc->atomic.disable_cxsr = true;
11643                         /* to potentially re-enable cxsr */
11644                         intel_crtc->atomic.wait_vblank = true;
11645                         intel_crtc->atomic.update_wm_post = true;
11646                 }
11647         } else if (turn_off) {
11648                 intel_crtc->atomic.update_wm_post = true;
11649                 /* must disable cxsr around plane enable/disable */
11650                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11651                         if (is_crtc_enabled)
11652                                 intel_crtc->atomic.wait_vblank = true;
11653                         intel_crtc->atomic.disable_cxsr = true;
11654                 }
11655         } else if (intel_wm_need_update(plane, plane_state)) {
11656                 intel_crtc->atomic.update_wm_pre = true;
11657         }
11658
11659         if (visible)
11660                 intel_crtc->atomic.fb_bits |=
11661                         to_intel_plane(plane)->frontbuffer_bit;
11662
11663         switch (plane->type) {
11664         case DRM_PLANE_TYPE_PRIMARY:
11665                 intel_crtc->atomic.wait_for_flips = true;
11666                 intel_crtc->atomic.pre_disable_primary = turn_off;
11667                 intel_crtc->atomic.post_enable_primary = turn_on;
11668
11669                 if (turn_off) {
11670                         /*
11671                          * FIXME: Actually if we will still have any other
11672                          * plane enabled on the pipe we could let IPS enabled
11673                          * still, but for now lets consider that when we make
11674                          * primary invisible by setting DSPCNTR to 0 on
11675                          * update_primary_plane function IPS needs to be
11676                          * disable.
11677                          */
11678                         intel_crtc->atomic.disable_ips = true;
11679
11680                         intel_crtc->atomic.disable_fbc = true;
11681                 }
11682
11683                 /*
11684                  * FBC does not work on some platforms for rotated
11685                  * planes, so disable it when rotation is not 0 and
11686                  * update it when rotation is set back to 0.
11687                  *
11688                  * FIXME: This is redundant with the fbc update done in
11689                  * the primary plane enable function except that that
11690                  * one is done too late. We eventually need to unify
11691                  * this.
11692                  */
11693
11694                 if (visible &&
11695                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11696                     dev_priv->fbc.crtc == intel_crtc &&
11697                     plane_state->rotation != BIT(DRM_ROTATE_0))
11698                         intel_crtc->atomic.disable_fbc = true;
11699
11700                 /*
11701                  * BDW signals flip done immediately if the plane
11702                  * is disabled, even if the plane enable is already
11703                  * armed to occur at the next vblank :(
11704                  */
11705                 if (turn_on && IS_BROADWELL(dev))
11706                         intel_crtc->atomic.wait_vblank = true;
11707
11708                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11709                 break;
11710         case DRM_PLANE_TYPE_CURSOR:
11711                 break;
11712         case DRM_PLANE_TYPE_OVERLAY:
11713                 if (turn_off && !mode_changed) {
11714                         intel_crtc->atomic.wait_vblank = true;
11715                         intel_crtc->atomic.update_sprite_watermarks |=
11716                                 1 << i;
11717                 }
11718         }
11719         return 0;
11720 }
11721
11722 static bool encoders_cloneable(const struct intel_encoder *a,
11723                                const struct intel_encoder *b)
11724 {
11725         /* masks could be asymmetric, so check both ways */
11726         return a == b || (a->cloneable & (1 << b->type) &&
11727                           b->cloneable & (1 << a->type));
11728 }
11729
11730 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11731                                          struct intel_crtc *crtc,
11732                                          struct intel_encoder *encoder)
11733 {
11734         struct intel_encoder *source_encoder;
11735         struct drm_connector *connector;
11736         struct drm_connector_state *connector_state;
11737         int i;
11738
11739         for_each_connector_in_state(state, connector, connector_state, i) {
11740                 if (connector_state->crtc != &crtc->base)
11741                         continue;
11742
11743                 source_encoder =
11744                         to_intel_encoder(connector_state->best_encoder);
11745                 if (!encoders_cloneable(encoder, source_encoder))
11746                         return false;
11747         }
11748
11749         return true;
11750 }
11751
11752 static bool check_encoder_cloning(struct drm_atomic_state *state,
11753                                   struct intel_crtc *crtc)
11754 {
11755         struct intel_encoder *encoder;
11756         struct drm_connector *connector;
11757         struct drm_connector_state *connector_state;
11758         int i;
11759
11760         for_each_connector_in_state(state, connector, connector_state, i) {
11761                 if (connector_state->crtc != &crtc->base)
11762                         continue;
11763
11764                 encoder = to_intel_encoder(connector_state->best_encoder);
11765                 if (!check_single_encoder_cloning(state, crtc, encoder))
11766                         return false;
11767         }
11768
11769         return true;
11770 }
11771
11772 static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11773                                             struct drm_crtc_state *crtc_state)
11774 {
11775         struct intel_crtc_state *pipe_config =
11776                 to_intel_crtc_state(crtc_state);
11777         struct drm_plane *p;
11778         unsigned visible_mask = 0;
11779
11780         drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11781                 struct drm_plane_state *plane_state =
11782                         drm_atomic_get_existing_plane_state(crtc_state->state, p);
11783
11784                 if (WARN_ON(!plane_state))
11785                         continue;
11786
11787                 if (!plane_state->fb)
11788                         crtc_state->plane_mask &=
11789                                 ~(1 << drm_plane_index(p));
11790                 else if (to_intel_plane_state(plane_state)->visible)
11791                         visible_mask |= 1 << drm_plane_index(p);
11792         }
11793
11794         if (!visible_mask)
11795                 return;
11796
11797         pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11798 }
11799
11800 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11801                                    struct drm_crtc_state *crtc_state)
11802 {
11803         struct drm_device *dev = crtc->dev;
11804         struct drm_i915_private *dev_priv = dev->dev_private;
11805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11806         struct intel_crtc_state *pipe_config =
11807                 to_intel_crtc_state(crtc_state);
11808         struct drm_atomic_state *state = crtc_state->state;
11809         int ret, idx = crtc->base.id;
11810         bool mode_changed = needs_modeset(crtc_state);
11811
11812         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11813                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11814                 return -EINVAL;
11815         }
11816
11817         I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11818                 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11819                 idx, crtc->state->active, intel_crtc->active);
11820
11821         /* plane mask is fixed up after all initial planes are calculated */
11822         if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11823                 intel_crtc_check_initial_planes(crtc, crtc_state);
11824
11825         if (mode_changed && !crtc_state->active)
11826                 intel_crtc->atomic.update_wm_post = true;
11827
11828         if (mode_changed && crtc_state->enable &&
11829             dev_priv->display.crtc_compute_clock &&
11830             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11831                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11832                                                            pipe_config);
11833                 if (ret)
11834                         return ret;
11835         }
11836
11837         return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
11838 }
11839
11840 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11841         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11842         .load_lut = intel_crtc_load_lut,
11843         .atomic_begin = intel_begin_crtc_commit,
11844         .atomic_flush = intel_finish_crtc_commit,
11845         .atomic_check = intel_crtc_atomic_check,
11846 };
11847
11848 /**
11849  * intel_modeset_update_staged_output_state
11850  *
11851  * Updates the staged output configuration state, e.g. after we've read out the
11852  * current hw state.
11853  */
11854 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11855 {
11856         struct intel_crtc *crtc;
11857         struct intel_encoder *encoder;
11858         struct intel_connector *connector;
11859
11860         for_each_intel_connector(dev, connector) {
11861                 connector->new_encoder =
11862                         to_intel_encoder(connector->base.encoder);
11863         }
11864
11865         for_each_intel_encoder(dev, encoder) {
11866                 encoder->new_crtc =
11867                         to_intel_crtc(encoder->base.crtc);
11868         }
11869
11870         for_each_intel_crtc(dev, crtc) {
11871                 crtc->new_enabled = crtc->base.state->enable;
11872         }
11873 }
11874
11875 /* Transitional helper to copy current connector/encoder state to
11876  * connector->state. This is needed so that code that is partially
11877  * converted to atomic does the right thing.
11878  */
11879 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11880 {
11881         struct intel_connector *connector;
11882
11883         for_each_intel_connector(dev, connector) {
11884                 if (connector->base.encoder) {
11885                         connector->base.state->best_encoder =
11886                                 connector->base.encoder;
11887                         connector->base.state->crtc =
11888                                 connector->base.encoder->crtc;
11889                 } else {
11890                         connector->base.state->best_encoder = NULL;
11891                         connector->base.state->crtc = NULL;
11892                 }
11893         }
11894 }
11895
11896 static void
11897 connected_sink_compute_bpp(struct intel_connector *connector,
11898                            struct intel_crtc_state *pipe_config)
11899 {
11900         int bpp = pipe_config->pipe_bpp;
11901
11902         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11903                 connector->base.base.id,
11904                 connector->base.name);
11905
11906         /* Don't use an invalid EDID bpc value */
11907         if (connector->base.display_info.bpc &&
11908             connector->base.display_info.bpc * 3 < bpp) {
11909                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11910                               bpp, connector->base.display_info.bpc*3);
11911                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11912         }
11913
11914         /* Clamp bpp to 8 on screens without EDID 1.4 */
11915         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11916                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11917                               bpp);
11918                 pipe_config->pipe_bpp = 24;
11919         }
11920 }
11921
11922 static int
11923 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11924                           struct intel_crtc_state *pipe_config)
11925 {
11926         struct drm_device *dev = crtc->base.dev;
11927         struct drm_atomic_state *state;
11928         struct drm_connector *connector;
11929         struct drm_connector_state *connector_state;
11930         int bpp, i;
11931
11932         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11933                 bpp = 10*3;
11934         else if (INTEL_INFO(dev)->gen >= 5)
11935                 bpp = 12*3;
11936         else
11937                 bpp = 8*3;
11938
11939
11940         pipe_config->pipe_bpp = bpp;
11941
11942         state = pipe_config->base.state;
11943
11944         /* Clamp display bpp to EDID value */
11945         for_each_connector_in_state(state, connector, connector_state, i) {
11946                 if (connector_state->crtc != &crtc->base)
11947                         continue;
11948
11949                 connected_sink_compute_bpp(to_intel_connector(connector),
11950                                            pipe_config);
11951         }
11952
11953         return bpp;
11954 }
11955
11956 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11957 {
11958         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11959                         "type: 0x%x flags: 0x%x\n",
11960                 mode->crtc_clock,
11961                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11962                 mode->crtc_hsync_end, mode->crtc_htotal,
11963                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11964                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11965 }
11966
11967 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11968                                    struct intel_crtc_state *pipe_config,
11969                                    const char *context)
11970 {
11971         struct drm_device *dev = crtc->base.dev;
11972         struct drm_plane *plane;
11973         struct intel_plane *intel_plane;
11974         struct intel_plane_state *state;
11975         struct drm_framebuffer *fb;
11976
11977         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11978                       context, pipe_config, pipe_name(crtc->pipe));
11979
11980         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11981         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11982                       pipe_config->pipe_bpp, pipe_config->dither);
11983         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11984                       pipe_config->has_pch_encoder,
11985                       pipe_config->fdi_lanes,
11986                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11987                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11988                       pipe_config->fdi_m_n.tu);
11989         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11990                       pipe_config->has_dp_encoder,
11991                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11992                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11993                       pipe_config->dp_m_n.tu);
11994
11995         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11996                       pipe_config->has_dp_encoder,
11997                       pipe_config->dp_m2_n2.gmch_m,
11998                       pipe_config->dp_m2_n2.gmch_n,
11999                       pipe_config->dp_m2_n2.link_m,
12000                       pipe_config->dp_m2_n2.link_n,
12001                       pipe_config->dp_m2_n2.tu);
12002
12003         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12004                       pipe_config->has_audio,
12005                       pipe_config->has_infoframe);
12006
12007         DRM_DEBUG_KMS("requested mode:\n");
12008         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12009         DRM_DEBUG_KMS("adjusted mode:\n");
12010         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12011         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12012         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12013         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12014                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12015         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12016                       crtc->num_scalers,
12017                       pipe_config->scaler_state.scaler_users,
12018                       pipe_config->scaler_state.scaler_id);
12019         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12020                       pipe_config->gmch_pfit.control,
12021                       pipe_config->gmch_pfit.pgm_ratios,
12022                       pipe_config->gmch_pfit.lvds_border_bits);
12023         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12024                       pipe_config->pch_pfit.pos,
12025                       pipe_config->pch_pfit.size,
12026                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12027         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12028         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12029
12030         if (IS_BROXTON(dev)) {
12031                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12032                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12033                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12034                               pipe_config->ddi_pll_sel,
12035                               pipe_config->dpll_hw_state.ebb0,
12036                               pipe_config->dpll_hw_state.ebb4,
12037                               pipe_config->dpll_hw_state.pll0,
12038                               pipe_config->dpll_hw_state.pll1,
12039                               pipe_config->dpll_hw_state.pll2,
12040                               pipe_config->dpll_hw_state.pll3,
12041                               pipe_config->dpll_hw_state.pll6,
12042                               pipe_config->dpll_hw_state.pll8,
12043                               pipe_config->dpll_hw_state.pll9,
12044                               pipe_config->dpll_hw_state.pll10,
12045                               pipe_config->dpll_hw_state.pcsdw12);
12046         } else if (IS_SKYLAKE(dev)) {
12047                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12048                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12049                               pipe_config->ddi_pll_sel,
12050                               pipe_config->dpll_hw_state.ctrl1,
12051                               pipe_config->dpll_hw_state.cfgcr1,
12052                               pipe_config->dpll_hw_state.cfgcr2);
12053         } else if (HAS_DDI(dev)) {
12054                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12055                               pipe_config->ddi_pll_sel,
12056                               pipe_config->dpll_hw_state.wrpll);
12057         } else {
12058                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12059                               "fp0: 0x%x, fp1: 0x%x\n",
12060                               pipe_config->dpll_hw_state.dpll,
12061                               pipe_config->dpll_hw_state.dpll_md,
12062                               pipe_config->dpll_hw_state.fp0,
12063                               pipe_config->dpll_hw_state.fp1);
12064         }
12065
12066         DRM_DEBUG_KMS("planes on this crtc\n");
12067         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12068                 intel_plane = to_intel_plane(plane);
12069                 if (intel_plane->pipe != crtc->pipe)
12070                         continue;
12071
12072                 state = to_intel_plane_state(plane->state);
12073                 fb = state->base.fb;
12074                 if (!fb) {
12075                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12076                                 "disabled, scaler_id = %d\n",
12077                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12078                                 plane->base.id, intel_plane->pipe,
12079                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12080                                 drm_plane_index(plane), state->scaler_id);
12081                         continue;
12082                 }
12083
12084                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12085                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12086                         plane->base.id, intel_plane->pipe,
12087                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12088                         drm_plane_index(plane));
12089                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12090                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12091                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12092                         state->scaler_id,
12093                         state->src.x1 >> 16, state->src.y1 >> 16,
12094                         drm_rect_width(&state->src) >> 16,
12095                         drm_rect_height(&state->src) >> 16,
12096                         state->dst.x1, state->dst.y1,
12097                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12098         }
12099 }
12100
12101 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12102 {
12103         struct drm_device *dev = state->dev;
12104         struct intel_encoder *encoder;
12105         struct drm_connector *connector;
12106         struct drm_connector_state *connector_state;
12107         unsigned int used_ports = 0;
12108         int i;
12109
12110         /*
12111          * Walk the connector list instead of the encoder
12112          * list to detect the problem on ddi platforms
12113          * where there's just one encoder per digital port.
12114          */
12115         for_each_connector_in_state(state, connector, connector_state, i) {
12116                 if (!connector_state->best_encoder)
12117                         continue;
12118
12119                 encoder = to_intel_encoder(connector_state->best_encoder);
12120
12121                 WARN_ON(!connector_state->crtc);
12122
12123                 switch (encoder->type) {
12124                         unsigned int port_mask;
12125                 case INTEL_OUTPUT_UNKNOWN:
12126                         if (WARN_ON(!HAS_DDI(dev)))
12127                                 break;
12128                 case INTEL_OUTPUT_DISPLAYPORT:
12129                 case INTEL_OUTPUT_HDMI:
12130                 case INTEL_OUTPUT_EDP:
12131                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12132
12133                         /* the same port mustn't appear more than once */
12134                         if (used_ports & port_mask)
12135                                 return false;
12136
12137                         used_ports |= port_mask;
12138                 default:
12139                         break;
12140                 }
12141         }
12142
12143         return true;
12144 }
12145
12146 static void
12147 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12148 {
12149         struct drm_crtc_state tmp_state;
12150         struct intel_crtc_scaler_state scaler_state;
12151         struct intel_dpll_hw_state dpll_hw_state;
12152         enum intel_dpll_id shared_dpll;
12153         uint32_t ddi_pll_sel;
12154
12155         /* FIXME: before the switch to atomic started, a new pipe_config was
12156          * kzalloc'd. Code that depends on any field being zero should be
12157          * fixed, so that the crtc_state can be safely duplicated. For now,
12158          * only fields that are know to not cause problems are preserved. */
12159
12160         tmp_state = crtc_state->base;
12161         scaler_state = crtc_state->scaler_state;
12162         shared_dpll = crtc_state->shared_dpll;
12163         dpll_hw_state = crtc_state->dpll_hw_state;
12164         ddi_pll_sel = crtc_state->ddi_pll_sel;
12165
12166         memset(crtc_state, 0, sizeof *crtc_state);
12167
12168         crtc_state->base = tmp_state;
12169         crtc_state->scaler_state = scaler_state;
12170         crtc_state->shared_dpll = shared_dpll;
12171         crtc_state->dpll_hw_state = dpll_hw_state;
12172         crtc_state->ddi_pll_sel = ddi_pll_sel;
12173 }
12174
12175 static int
12176 intel_modeset_pipe_config(struct drm_crtc *crtc,
12177                           struct intel_crtc_state *pipe_config)
12178 {
12179         struct drm_atomic_state *state = pipe_config->base.state;
12180         struct intel_encoder *encoder;
12181         struct drm_connector *connector;
12182         struct drm_connector_state *connector_state;
12183         int base_bpp, ret = -EINVAL;
12184         int i;
12185         bool retry = true;
12186
12187         clear_intel_crtc_state(pipe_config);
12188
12189         pipe_config->cpu_transcoder =
12190                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12191
12192         /*
12193          * Sanitize sync polarity flags based on requested ones. If neither
12194          * positive or negative polarity is requested, treat this as meaning
12195          * negative polarity.
12196          */
12197         if (!(pipe_config->base.adjusted_mode.flags &
12198               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12199                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12200
12201         if (!(pipe_config->base.adjusted_mode.flags &
12202               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12203                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12204
12205         /* Compute a starting value for pipe_config->pipe_bpp taking the source
12206          * plane pixel format and any sink constraints into account. Returns the
12207          * source plane bpp so that dithering can be selected on mismatches
12208          * after encoders and crtc also have had their say. */
12209         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12210                                              pipe_config);
12211         if (base_bpp < 0)
12212                 goto fail;
12213
12214         /*
12215          * Determine the real pipe dimensions. Note that stereo modes can
12216          * increase the actual pipe size due to the frame doubling and
12217          * insertion of additional space for blanks between the frame. This
12218          * is stored in the crtc timings. We use the requested mode to do this
12219          * computation to clearly distinguish it from the adjusted mode, which
12220          * can be changed by the connectors in the below retry loop.
12221          */
12222         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12223                                &pipe_config->pipe_src_w,
12224                                &pipe_config->pipe_src_h);
12225
12226 encoder_retry:
12227         /* Ensure the port clock defaults are reset when retrying. */
12228         pipe_config->port_clock = 0;
12229         pipe_config->pixel_multiplier = 1;
12230
12231         /* Fill in default crtc timings, allow encoders to overwrite them. */
12232         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12233                               CRTC_STEREO_DOUBLE);
12234
12235         /* Pass our mode to the connectors and the CRTC to give them a chance to
12236          * adjust it according to limitations or connector properties, and also
12237          * a chance to reject the mode entirely.
12238          */
12239         for_each_connector_in_state(state, connector, connector_state, i) {
12240                 if (connector_state->crtc != crtc)
12241                         continue;
12242
12243                 encoder = to_intel_encoder(connector_state->best_encoder);
12244
12245                 if (!(encoder->compute_config(encoder, pipe_config))) {
12246                         DRM_DEBUG_KMS("Encoder config failure\n");
12247                         goto fail;
12248                 }
12249         }
12250
12251         /* Set default port clock if not overwritten by the encoder. Needs to be
12252          * done afterwards in case the encoder adjusts the mode. */
12253         if (!pipe_config->port_clock)
12254                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12255                         * pipe_config->pixel_multiplier;
12256
12257         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12258         if (ret < 0) {
12259                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12260                 goto fail;
12261         }
12262
12263         if (ret == RETRY) {
12264                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12265                         ret = -EINVAL;
12266                         goto fail;
12267                 }
12268
12269                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12270                 retry = false;
12271                 goto encoder_retry;
12272         }
12273
12274         pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12275         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12276                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12277
12278         /* Check if we need to force a modeset */
12279         if (pipe_config->has_audio !=
12280             to_intel_crtc_state(crtc->state)->has_audio) {
12281                 pipe_config->base.mode_changed = true;
12282                 ret = drm_atomic_add_affected_planes(state, crtc);
12283         }
12284
12285         /*
12286          * Note we have an issue here with infoframes: current code
12287          * only updates them on the full mode set path per hw
12288          * requirements.  So here we should be checking for any
12289          * required changes and forcing a mode set.
12290          */
12291 fail:
12292         return ret;
12293 }
12294
12295 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12296 {
12297         struct drm_encoder *encoder;
12298         struct drm_device *dev = crtc->dev;
12299
12300         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12301                 if (encoder->crtc == crtc)
12302                         return true;
12303
12304         return false;
12305 }
12306
12307 static void
12308 intel_modeset_update_state(struct drm_atomic_state *state)
12309 {
12310         struct drm_device *dev = state->dev;
12311         struct intel_encoder *intel_encoder;
12312         struct drm_crtc *crtc;
12313         struct drm_crtc_state *crtc_state;
12314         struct drm_connector *connector;
12315         int i;
12316
12317         intel_shared_dpll_commit(state);
12318
12319         for_each_intel_encoder(dev, intel_encoder) {
12320                 if (!intel_encoder->base.crtc)
12321                         continue;
12322
12323                 crtc = intel_encoder->base.crtc;
12324                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12325                 if (!crtc_state || !needs_modeset(crtc->state))
12326                         continue;
12327
12328                 intel_encoder->connectors_active = false;
12329         }
12330
12331         drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12332         intel_modeset_update_staged_output_state(state->dev);
12333
12334         /* Double check state. */
12335         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12336                 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12337
12338                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12339
12340                 /* Update hwmode for vblank functions */
12341                 if (crtc->state->active)
12342                         crtc->hwmode = crtc->state->adjusted_mode;
12343                 else
12344                         crtc->hwmode.crtc_clock = 0;
12345         }
12346
12347         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12348                 if (!connector->encoder || !connector->encoder->crtc)
12349                         continue;
12350
12351                 crtc = connector->encoder->crtc;
12352                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12353                 if (!crtc_state || !needs_modeset(crtc->state))
12354                         continue;
12355
12356                 if (crtc->state->active) {
12357                         struct drm_property *dpms_property =
12358                                 dev->mode_config.dpms_property;
12359
12360                         connector->dpms = DRM_MODE_DPMS_ON;
12361                         drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12362
12363                         intel_encoder = to_intel_encoder(connector->encoder);
12364                         intel_encoder->connectors_active = true;
12365                 } else
12366                         connector->dpms = DRM_MODE_DPMS_OFF;
12367         }
12368 }
12369
12370 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12371 {
12372         int diff;
12373
12374         if (clock1 == clock2)
12375                 return true;
12376
12377         if (!clock1 || !clock2)
12378                 return false;
12379
12380         diff = abs(clock1 - clock2);
12381
12382         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12383                 return true;
12384
12385         return false;
12386 }
12387
12388 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12389         list_for_each_entry((intel_crtc), \
12390                             &(dev)->mode_config.crtc_list, \
12391                             base.head) \
12392                 if (mask & (1 <<(intel_crtc)->pipe))
12393
12394 static bool
12395 intel_pipe_config_compare(struct drm_device *dev,
12396                           struct intel_crtc_state *current_config,
12397                           struct intel_crtc_state *pipe_config)
12398 {
12399 #define PIPE_CONF_CHECK_X(name) \
12400         if (current_config->name != pipe_config->name) { \
12401                 DRM_ERROR("mismatch in " #name " " \
12402                           "(expected 0x%08x, found 0x%08x)\n", \
12403                           current_config->name, \
12404                           pipe_config->name); \
12405                 return false; \
12406         }
12407
12408 #define PIPE_CONF_CHECK_I(name) \
12409         if (current_config->name != pipe_config->name) { \
12410                 DRM_ERROR("mismatch in " #name " " \
12411                           "(expected %i, found %i)\n", \
12412                           current_config->name, \
12413                           pipe_config->name); \
12414                 return false; \
12415         }
12416
12417 /* This is required for BDW+ where there is only one set of registers for
12418  * switching between high and low RR.
12419  * This macro can be used whenever a comparison has to be made between one
12420  * hw state and multiple sw state variables.
12421  */
12422 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12423         if ((current_config->name != pipe_config->name) && \
12424                 (current_config->alt_name != pipe_config->name)) { \
12425                         DRM_ERROR("mismatch in " #name " " \
12426                                   "(expected %i or %i, found %i)\n", \
12427                                   current_config->name, \
12428                                   current_config->alt_name, \
12429                                   pipe_config->name); \
12430                         return false; \
12431         }
12432
12433 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12434         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12435                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
12436                           "(expected %i, found %i)\n", \
12437                           current_config->name & (mask), \
12438                           pipe_config->name & (mask)); \
12439                 return false; \
12440         }
12441
12442 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12443         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12444                 DRM_ERROR("mismatch in " #name " " \
12445                           "(expected %i, found %i)\n", \
12446                           current_config->name, \
12447                           pipe_config->name); \
12448                 return false; \
12449         }
12450
12451 #define PIPE_CONF_QUIRK(quirk)  \
12452         ((current_config->quirks | pipe_config->quirks) & (quirk))
12453
12454         PIPE_CONF_CHECK_I(cpu_transcoder);
12455
12456         PIPE_CONF_CHECK_I(has_pch_encoder);
12457         PIPE_CONF_CHECK_I(fdi_lanes);
12458         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12459         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12460         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12461         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12462         PIPE_CONF_CHECK_I(fdi_m_n.tu);
12463
12464         PIPE_CONF_CHECK_I(has_dp_encoder);
12465
12466         if (INTEL_INFO(dev)->gen < 8) {
12467                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12468                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12469                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12470                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12471                 PIPE_CONF_CHECK_I(dp_m_n.tu);
12472
12473                 if (current_config->has_drrs) {
12474                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12475                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12476                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12477                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12478                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12479                 }
12480         } else {
12481                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12482                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12483                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12484                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12485                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12486         }
12487
12488         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12489         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12490         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12491         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12492         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12493         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12494
12495         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12496         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12497         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12498         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12499         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12500         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12501
12502         PIPE_CONF_CHECK_I(pixel_multiplier);
12503         PIPE_CONF_CHECK_I(has_hdmi_sink);
12504         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12505             IS_VALLEYVIEW(dev))
12506                 PIPE_CONF_CHECK_I(limited_color_range);
12507         PIPE_CONF_CHECK_I(has_infoframe);
12508
12509         PIPE_CONF_CHECK_I(has_audio);
12510
12511         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12512                               DRM_MODE_FLAG_INTERLACE);
12513
12514         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12515                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12516                                       DRM_MODE_FLAG_PHSYNC);
12517                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12518                                       DRM_MODE_FLAG_NHSYNC);
12519                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12520                                       DRM_MODE_FLAG_PVSYNC);
12521                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12522                                       DRM_MODE_FLAG_NVSYNC);
12523         }
12524
12525         PIPE_CONF_CHECK_I(pipe_src_w);
12526         PIPE_CONF_CHECK_I(pipe_src_h);
12527
12528         /*
12529          * FIXME: BIOS likes to set up a cloned config with lvds+external
12530          * screen. Since we don't yet re-compute the pipe config when moving
12531          * just the lvds port away to another pipe the sw tracking won't match.
12532          *
12533          * Proper atomic modesets with recomputed global state will fix this.
12534          * Until then just don't check gmch state for inherited modes.
12535          */
12536         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12537                 PIPE_CONF_CHECK_I(gmch_pfit.control);
12538                 /* pfit ratios are autocomputed by the hw on gen4+ */
12539                 if (INTEL_INFO(dev)->gen < 4)
12540                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12541                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12542         }
12543
12544         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12545         if (current_config->pch_pfit.enabled) {
12546                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12547                 PIPE_CONF_CHECK_I(pch_pfit.size);
12548         }
12549
12550         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12551
12552         /* BDW+ don't expose a synchronous way to read the state */
12553         if (IS_HASWELL(dev))
12554                 PIPE_CONF_CHECK_I(ips_enabled);
12555
12556         PIPE_CONF_CHECK_I(double_wide);
12557
12558         PIPE_CONF_CHECK_X(ddi_pll_sel);
12559
12560         PIPE_CONF_CHECK_I(shared_dpll);
12561         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12562         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12563         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12564         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12565         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12566         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12567         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12568         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12569
12570         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12571                 PIPE_CONF_CHECK_I(pipe_bpp);
12572
12573         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12574         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12575
12576 #undef PIPE_CONF_CHECK_X
12577 #undef PIPE_CONF_CHECK_I
12578 #undef PIPE_CONF_CHECK_I_ALT
12579 #undef PIPE_CONF_CHECK_FLAGS
12580 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12581 #undef PIPE_CONF_QUIRK
12582
12583         return true;
12584 }
12585
12586 static void check_wm_state(struct drm_device *dev)
12587 {
12588         struct drm_i915_private *dev_priv = dev->dev_private;
12589         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12590         struct intel_crtc *intel_crtc;
12591         int plane;
12592
12593         if (INTEL_INFO(dev)->gen < 9)
12594                 return;
12595
12596         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12597         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12598
12599         for_each_intel_crtc(dev, intel_crtc) {
12600                 struct skl_ddb_entry *hw_entry, *sw_entry;
12601                 const enum pipe pipe = intel_crtc->pipe;
12602
12603                 if (!intel_crtc->active)
12604                         continue;
12605
12606                 /* planes */
12607                 for_each_plane(dev_priv, pipe, plane) {
12608                         hw_entry = &hw_ddb.plane[pipe][plane];
12609                         sw_entry = &sw_ddb->plane[pipe][plane];
12610
12611                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12612                                 continue;
12613
12614                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12615                                   "(expected (%u,%u), found (%u,%u))\n",
12616                                   pipe_name(pipe), plane + 1,
12617                                   sw_entry->start, sw_entry->end,
12618                                   hw_entry->start, hw_entry->end);
12619                 }
12620
12621                 /* cursor */
12622                 hw_entry = &hw_ddb.cursor[pipe];
12623                 sw_entry = &sw_ddb->cursor[pipe];
12624
12625                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12626                         continue;
12627
12628                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12629                           "(expected (%u,%u), found (%u,%u))\n",
12630                           pipe_name(pipe),
12631                           sw_entry->start, sw_entry->end,
12632                           hw_entry->start, hw_entry->end);
12633         }
12634 }
12635
12636 static void
12637 check_connector_state(struct drm_device *dev)
12638 {
12639         struct intel_connector *connector;
12640
12641         for_each_intel_connector(dev, connector) {
12642                 /* This also checks the encoder/connector hw state with the
12643                  * ->get_hw_state callbacks. */
12644                 intel_connector_check_state(connector);
12645
12646                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12647                      "connector's staged encoder doesn't match current encoder\n");
12648         }
12649 }
12650
12651 static void
12652 check_encoder_state(struct drm_device *dev)
12653 {
12654         struct intel_encoder *encoder;
12655         struct intel_connector *connector;
12656
12657         for_each_intel_encoder(dev, encoder) {
12658                 bool enabled = false;
12659                 bool active = false;
12660                 enum pipe pipe, tracked_pipe;
12661
12662                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12663                               encoder->base.base.id,
12664                               encoder->base.name);
12665
12666                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12667                      "encoder's stage crtc doesn't match current crtc\n");
12668                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12669                      "encoder's active_connectors set, but no crtc\n");
12670
12671                 for_each_intel_connector(dev, connector) {
12672                         if (connector->base.encoder != &encoder->base)
12673                                 continue;
12674                         enabled = true;
12675                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12676                                 active = true;
12677                 }
12678                 /*
12679                  * for MST connectors if we unplug the connector is gone
12680                  * away but the encoder is still connected to a crtc
12681                  * until a modeset happens in response to the hotplug.
12682                  */
12683                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12684                         continue;
12685
12686                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12687                      "encoder's enabled state mismatch "
12688                      "(expected %i, found %i)\n",
12689                      !!encoder->base.crtc, enabled);
12690                 I915_STATE_WARN(active && !encoder->base.crtc,
12691                      "active encoder with no crtc\n");
12692
12693                 I915_STATE_WARN(encoder->connectors_active != active,
12694                      "encoder's computed active state doesn't match tracked active state "
12695                      "(expected %i, found %i)\n", active, encoder->connectors_active);
12696
12697                 active = encoder->get_hw_state(encoder, &pipe);
12698                 I915_STATE_WARN(active != encoder->connectors_active,
12699                      "encoder's hw state doesn't match sw tracking "
12700                      "(expected %i, found %i)\n",
12701                      encoder->connectors_active, active);
12702
12703                 if (!encoder->base.crtc)
12704                         continue;
12705
12706                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12707                 I915_STATE_WARN(active && pipe != tracked_pipe,
12708                      "active encoder's pipe doesn't match"
12709                      "(expected %i, found %i)\n",
12710                      tracked_pipe, pipe);
12711
12712         }
12713 }
12714
12715 static void
12716 check_crtc_state(struct drm_device *dev)
12717 {
12718         struct drm_i915_private *dev_priv = dev->dev_private;
12719         struct intel_crtc *crtc;
12720         struct intel_encoder *encoder;
12721         struct intel_crtc_state pipe_config;
12722
12723         for_each_intel_crtc(dev, crtc) {
12724                 bool enabled = false;
12725                 bool active = false;
12726
12727                 memset(&pipe_config, 0, sizeof(pipe_config));
12728
12729                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12730                               crtc->base.base.id);
12731
12732                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12733                      "active crtc, but not enabled in sw tracking\n");
12734
12735                 for_each_intel_encoder(dev, encoder) {
12736                         if (encoder->base.crtc != &crtc->base)
12737                                 continue;
12738                         enabled = true;
12739                         if (encoder->connectors_active)
12740                                 active = true;
12741                 }
12742
12743                 I915_STATE_WARN(active != crtc->active,
12744                      "crtc's computed active state doesn't match tracked active state "
12745                      "(expected %i, found %i)\n", active, crtc->active);
12746                 I915_STATE_WARN(enabled != crtc->base.state->enable,
12747                      "crtc's computed enabled state doesn't match tracked enabled state "
12748                      "(expected %i, found %i)\n", enabled,
12749                                 crtc->base.state->enable);
12750
12751                 active = dev_priv->display.get_pipe_config(crtc,
12752                                                            &pipe_config);
12753
12754                 /* hw state is inconsistent with the pipe quirk */
12755                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12756                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12757                         active = crtc->active;
12758
12759                 for_each_intel_encoder(dev, encoder) {
12760                         enum pipe pipe;
12761                         if (encoder->base.crtc != &crtc->base)
12762                                 continue;
12763                         if (encoder->get_hw_state(encoder, &pipe))
12764                                 encoder->get_config(encoder, &pipe_config);
12765                 }
12766
12767                 I915_STATE_WARN(crtc->active != active,
12768                      "crtc active state doesn't match with hw state "
12769                      "(expected %i, found %i)\n", crtc->active, active);
12770
12771                 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12772                      "transitional active state does not match atomic hw state "
12773                      "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12774
12775                 if (active &&
12776                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12777                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12778                         intel_dump_pipe_config(crtc, &pipe_config,
12779                                                "[hw state]");
12780                         intel_dump_pipe_config(crtc, crtc->config,
12781                                                "[sw state]");
12782                 }
12783         }
12784 }
12785
12786 static void
12787 check_shared_dpll_state(struct drm_device *dev)
12788 {
12789         struct drm_i915_private *dev_priv = dev->dev_private;
12790         struct intel_crtc *crtc;
12791         struct intel_dpll_hw_state dpll_hw_state;
12792         int i;
12793
12794         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12795                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12796                 int enabled_crtcs = 0, active_crtcs = 0;
12797                 bool active;
12798
12799                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12800
12801                 DRM_DEBUG_KMS("%s\n", pll->name);
12802
12803                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12804
12805                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12806                      "more active pll users than references: %i vs %i\n",
12807                      pll->active, hweight32(pll->config.crtc_mask));
12808                 I915_STATE_WARN(pll->active && !pll->on,
12809                      "pll in active use but not on in sw tracking\n");
12810                 I915_STATE_WARN(pll->on && !pll->active,
12811                      "pll in on but not on in use in sw tracking\n");
12812                 I915_STATE_WARN(pll->on != active,
12813                      "pll on state mismatch (expected %i, found %i)\n",
12814                      pll->on, active);
12815
12816                 for_each_intel_crtc(dev, crtc) {
12817                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12818                                 enabled_crtcs++;
12819                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12820                                 active_crtcs++;
12821                 }
12822                 I915_STATE_WARN(pll->active != active_crtcs,
12823                      "pll active crtcs mismatch (expected %i, found %i)\n",
12824                      pll->active, active_crtcs);
12825                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12826                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12827                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12828
12829                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12830                                        sizeof(dpll_hw_state)),
12831                      "pll hw state mismatch\n");
12832         }
12833 }
12834
12835 void
12836 intel_modeset_check_state(struct drm_device *dev)
12837 {
12838         check_wm_state(dev);
12839         check_connector_state(dev);
12840         check_encoder_state(dev);
12841         check_crtc_state(dev);
12842         check_shared_dpll_state(dev);
12843 }
12844
12845 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12846                                      int dotclock)
12847 {
12848         /*
12849          * FDI already provided one idea for the dotclock.
12850          * Yell if the encoder disagrees.
12851          */
12852         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12853              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12854              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12855 }
12856
12857 static void update_scanline_offset(struct intel_crtc *crtc)
12858 {
12859         struct drm_device *dev = crtc->base.dev;
12860
12861         /*
12862          * The scanline counter increments at the leading edge of hsync.
12863          *
12864          * On most platforms it starts counting from vtotal-1 on the
12865          * first active line. That means the scanline counter value is
12866          * always one less than what we would expect. Ie. just after
12867          * start of vblank, which also occurs at start of hsync (on the
12868          * last active line), the scanline counter will read vblank_start-1.
12869          *
12870          * On gen2 the scanline counter starts counting from 1 instead
12871          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12872          * to keep the value positive), instead of adding one.
12873          *
12874          * On HSW+ the behaviour of the scanline counter depends on the output
12875          * type. For DP ports it behaves like most other platforms, but on HDMI
12876          * there's an extra 1 line difference. So we need to add two instead of
12877          * one to the value.
12878          */
12879         if (IS_GEN2(dev)) {
12880                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12881                 int vtotal;
12882
12883                 vtotal = mode->crtc_vtotal;
12884                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12885                         vtotal /= 2;
12886
12887                 crtc->scanline_offset = vtotal - 1;
12888         } else if (HAS_DDI(dev) &&
12889                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12890                 crtc->scanline_offset = 2;
12891         } else
12892                 crtc->scanline_offset = 1;
12893 }
12894
12895 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12896 {
12897         struct drm_device *dev = state->dev;
12898         struct drm_i915_private *dev_priv = to_i915(dev);
12899         struct intel_shared_dpll_config *shared_dpll = NULL;
12900         struct intel_crtc *intel_crtc;
12901         struct intel_crtc_state *intel_crtc_state;
12902         struct drm_crtc *crtc;
12903         struct drm_crtc_state *crtc_state;
12904         int i;
12905
12906         if (!dev_priv->display.crtc_compute_clock)
12907                 return;
12908
12909         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12910                 int dpll;
12911
12912                 intel_crtc = to_intel_crtc(crtc);
12913                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12914                 dpll = intel_crtc_state->shared_dpll;
12915
12916                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12917                         continue;
12918
12919                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12920
12921                 if (!shared_dpll)
12922                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12923
12924                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12925         }
12926 }
12927
12928 /*
12929  * This implements the workaround described in the "notes" section of the mode
12930  * set sequence documentation. When going from no pipes or single pipe to
12931  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12932  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12933  */
12934 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12935 {
12936         struct drm_crtc_state *crtc_state;
12937         struct intel_crtc *intel_crtc;
12938         struct drm_crtc *crtc;
12939         struct intel_crtc_state *first_crtc_state = NULL;
12940         struct intel_crtc_state *other_crtc_state = NULL;
12941         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12942         int i;
12943
12944         /* look at all crtc's that are going to be enabled in during modeset */
12945         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12946                 intel_crtc = to_intel_crtc(crtc);
12947
12948                 if (!crtc_state->active || !needs_modeset(crtc_state))
12949                         continue;
12950
12951                 if (first_crtc_state) {
12952                         other_crtc_state = to_intel_crtc_state(crtc_state);
12953                         break;
12954                 } else {
12955                         first_crtc_state = to_intel_crtc_state(crtc_state);
12956                         first_pipe = intel_crtc->pipe;
12957                 }
12958         }
12959
12960         /* No workaround needed? */
12961         if (!first_crtc_state)
12962                 return 0;
12963
12964         /* w/a possibly needed, check how many crtc's are already enabled. */
12965         for_each_intel_crtc(state->dev, intel_crtc) {
12966                 struct intel_crtc_state *pipe_config;
12967
12968                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12969                 if (IS_ERR(pipe_config))
12970                         return PTR_ERR(pipe_config);
12971
12972                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12973
12974                 if (!pipe_config->base.active ||
12975                     needs_modeset(&pipe_config->base))
12976                         continue;
12977
12978                 /* 2 or more enabled crtcs means no need for w/a */
12979                 if (enabled_pipe != INVALID_PIPE)
12980                         return 0;
12981
12982                 enabled_pipe = intel_crtc->pipe;
12983         }
12984
12985         if (enabled_pipe != INVALID_PIPE)
12986                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12987         else if (other_crtc_state)
12988                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12989
12990         return 0;
12991 }
12992
12993 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12994 {
12995         struct drm_crtc *crtc;
12996         struct drm_crtc_state *crtc_state;
12997         int ret = 0;
12998
12999         /* add all active pipes to the state */
13000         for_each_crtc(state->dev, crtc) {
13001                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13002                 if (IS_ERR(crtc_state))
13003                         return PTR_ERR(crtc_state);
13004
13005                 if (!crtc_state->active || needs_modeset(crtc_state))
13006                         continue;
13007
13008                 crtc_state->mode_changed = true;
13009
13010                 ret = drm_atomic_add_affected_connectors(state, crtc);
13011                 if (ret)
13012                         break;
13013
13014                 ret = drm_atomic_add_affected_planes(state, crtc);
13015                 if (ret)
13016                         break;
13017         }
13018
13019         return ret;
13020 }
13021
13022
13023 /* Code that should eventually be part of atomic_check() */
13024 static int intel_modeset_checks(struct drm_atomic_state *state)
13025 {
13026         struct drm_device *dev = state->dev;
13027         struct drm_i915_private *dev_priv = dev->dev_private;
13028         int ret;
13029
13030         if (!check_digital_port_conflicts(state)) {
13031                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13032                 return -EINVAL;
13033         }
13034
13035         /*
13036          * See if the config requires any additional preparation, e.g.
13037          * to adjust global state with pipes off.  We need to do this
13038          * here so we can get the modeset_pipe updated config for the new
13039          * mode set on this crtc.  For other crtcs we need to use the
13040          * adjusted_mode bits in the crtc directly.
13041          */
13042         if (dev_priv->display.modeset_calc_cdclk) {
13043                 unsigned int cdclk;
13044
13045                 ret = dev_priv->display.modeset_calc_cdclk(state);
13046
13047                 cdclk = to_intel_atomic_state(state)->cdclk;
13048                 if (!ret && cdclk != dev_priv->cdclk_freq)
13049                         ret = intel_modeset_all_pipes(state);
13050
13051                 if (ret < 0)
13052                         return ret;
13053         } else
13054                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13055
13056         intel_modeset_clear_plls(state);
13057
13058         if (IS_HASWELL(dev))
13059                 return haswell_mode_set_planes_workaround(state);
13060
13061         return 0;
13062 }
13063
13064 static int
13065 intel_modeset_compute_config(struct drm_atomic_state *state)
13066 {
13067         struct drm_crtc *crtc;
13068         struct drm_crtc_state *crtc_state;
13069         int ret, i;
13070         bool any_ms = false;
13071
13072         ret = drm_atomic_helper_check_modeset(state->dev, state);
13073         if (ret)
13074                 return ret;
13075
13076         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13077                 if (!crtc_state->enable) {
13078                         if (needs_modeset(crtc_state))
13079                                 any_ms = true;
13080                         continue;
13081                 }
13082
13083                 if (to_intel_crtc_state(crtc_state)->quirks &
13084                     PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13085                         ret = drm_atomic_add_affected_planes(state, crtc);
13086                         if (ret)
13087                                 return ret;
13088
13089                         /*
13090                          * We ought to handle i915.fastboot here.
13091                          * If no modeset is required and the primary plane has
13092                          * a fb, update the members of crtc_state as needed,
13093                          * and run the necessary updates during vblank evasion.
13094                          */
13095                 }
13096
13097                 if (!needs_modeset(crtc_state)) {
13098                         ret = drm_atomic_add_affected_connectors(state, crtc);
13099                         if (ret)
13100                                 return ret;
13101                 }
13102
13103                 ret = intel_modeset_pipe_config(crtc,
13104                                         to_intel_crtc_state(crtc_state));
13105                 if (ret)
13106                         return ret;
13107
13108                 if (needs_modeset(crtc_state))
13109                         any_ms = true;
13110
13111                 intel_dump_pipe_config(to_intel_crtc(crtc),
13112                                        to_intel_crtc_state(crtc_state),
13113                                        "[modeset]");
13114         }
13115
13116         if (any_ms) {
13117                 ret = intel_modeset_checks(state);
13118
13119                 if (ret)
13120                         return ret;
13121         } else
13122                 to_intel_atomic_state(state)->cdclk =
13123                         to_i915(state->dev)->cdclk_freq;
13124
13125         return drm_atomic_helper_check_planes(state->dev, state);
13126 }
13127
13128 static int __intel_set_mode(struct drm_atomic_state *state)
13129 {
13130         struct drm_device *dev = state->dev;
13131         struct drm_i915_private *dev_priv = dev->dev_private;
13132         struct drm_crtc *crtc;
13133         struct drm_crtc_state *crtc_state;
13134         int ret = 0;
13135         int i;
13136         bool any_ms = false;
13137
13138         ret = drm_atomic_helper_prepare_planes(dev, state);
13139         if (ret)
13140                 return ret;
13141
13142         drm_atomic_helper_swap_state(dev, state);
13143
13144         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13145                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13146
13147                 if (!needs_modeset(crtc->state))
13148                         continue;
13149
13150                 any_ms = true;
13151                 intel_pre_plane_update(intel_crtc);
13152
13153                 if (crtc_state->active) {
13154                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13155                         dev_priv->display.crtc_disable(crtc);
13156                         intel_crtc->active = false;
13157                         intel_disable_shared_dpll(intel_crtc);
13158                 }
13159         }
13160
13161         /* Only after disabling all output pipelines that will be changed can we
13162          * update the the output configuration. */
13163         intel_modeset_update_state(state);
13164
13165         /* The state has been swaped above, so state actually contains the
13166          * old state now. */
13167         if (any_ms)
13168                 modeset_update_crtc_power_domains(state);
13169
13170         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13171         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13172                 if (needs_modeset(crtc->state) && crtc->state->active) {
13173                         update_scanline_offset(to_intel_crtc(crtc));
13174                         dev_priv->display.crtc_enable(crtc);
13175                 }
13176
13177                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13178         }
13179
13180         /* FIXME: add subpixel order */
13181
13182         drm_atomic_helper_cleanup_planes(dev, state);
13183
13184         drm_atomic_state_free(state);
13185
13186         return 0;
13187 }
13188
13189 static int intel_set_mode_checked(struct drm_atomic_state *state)
13190 {
13191         struct drm_device *dev = state->dev;
13192         int ret;
13193
13194         ret = __intel_set_mode(state);
13195         if (ret == 0)
13196                 intel_modeset_check_state(dev);
13197
13198         return ret;
13199 }
13200
13201 static int intel_set_mode(struct drm_atomic_state *state)
13202 {
13203         int ret;
13204
13205         ret = intel_modeset_compute_config(state);
13206         if (ret)
13207                 return ret;
13208
13209         return intel_set_mode_checked(state);
13210 }
13211
13212 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13213 {
13214         struct drm_device *dev = crtc->dev;
13215         struct drm_atomic_state *state;
13216         struct intel_encoder *encoder;
13217         struct intel_connector *connector;
13218         struct drm_connector_state *connector_state;
13219         struct intel_crtc_state *crtc_state;
13220         int ret;
13221
13222         state = drm_atomic_state_alloc(dev);
13223         if (!state) {
13224                 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13225                               crtc->base.id);
13226                 return;
13227         }
13228
13229         state->acquire_ctx = dev->mode_config.acquire_ctx;
13230
13231         /* The force restore path in the HW readout code relies on the staged
13232          * config still keeping the user requested config while the actual
13233          * state has been overwritten by the configuration read from HW. We
13234          * need to copy the staged config to the atomic state, otherwise the
13235          * mode set will just reapply the state the HW is already in. */
13236         for_each_intel_encoder(dev, encoder) {
13237                 if (&encoder->new_crtc->base != crtc)
13238                         continue;
13239
13240                 for_each_intel_connector(dev, connector) {
13241                         if (connector->new_encoder != encoder)
13242                                 continue;
13243
13244                         connector_state = drm_atomic_get_connector_state(state, &connector->base);
13245                         if (IS_ERR(connector_state)) {
13246                                 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13247                                               connector->base.base.id,
13248                                               connector->base.name,
13249                                               PTR_ERR(connector_state));
13250                                 continue;
13251                         }
13252
13253                         connector_state->crtc = crtc;
13254                         connector_state->best_encoder = &encoder->base;
13255                 }
13256         }
13257
13258         crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13259         if (IS_ERR(crtc_state)) {
13260                 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13261                               crtc->base.id, PTR_ERR(crtc_state));
13262                 drm_atomic_state_free(state);
13263                 return;
13264         }
13265
13266         crtc_state->base.active = crtc_state->base.enable =
13267                 to_intel_crtc(crtc)->new_enabled;
13268
13269         drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13270
13271         intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13272                                         crtc->primary->fb, crtc->x, crtc->y);
13273
13274         ret = intel_set_mode(state);
13275         if (ret)
13276                 drm_atomic_state_free(state);
13277 }
13278
13279 #undef for_each_intel_crtc_masked
13280
13281 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13282                                         struct drm_mode_set *set)
13283 {
13284         int ro;
13285
13286         for (ro = 0; ro < set->num_connectors; ro++)
13287                 if (set->connectors[ro] == &connector->base)
13288                         return true;
13289
13290         return false;
13291 }
13292
13293 static int
13294 intel_modeset_stage_output_state(struct drm_device *dev,
13295                                  struct drm_mode_set *set,
13296                                  struct drm_atomic_state *state)
13297 {
13298         struct intel_connector *connector;
13299         struct drm_connector *drm_connector;
13300         struct drm_connector_state *connector_state;
13301         struct drm_crtc *crtc;
13302         struct drm_crtc_state *crtc_state;
13303         int i, ret;
13304
13305         /* The upper layers ensure that we either disable a crtc or have a list
13306          * of connectors. For paranoia, double-check this. */
13307         WARN_ON(!set->fb && (set->num_connectors != 0));
13308         WARN_ON(set->fb && (set->num_connectors == 0));
13309
13310         for_each_intel_connector(dev, connector) {
13311                 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13312
13313                 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13314                         continue;
13315
13316                 connector_state =
13317                         drm_atomic_get_connector_state(state, &connector->base);
13318                 if (IS_ERR(connector_state))
13319                         return PTR_ERR(connector_state);
13320
13321                 if (in_mode_set) {
13322                         int pipe = to_intel_crtc(set->crtc)->pipe;
13323                         connector_state->best_encoder =
13324                                 &intel_find_encoder(connector, pipe)->base;
13325                 }
13326
13327                 if (connector->base.state->crtc != set->crtc)
13328                         continue;
13329
13330                 /* If we disable the crtc, disable all its connectors. Also, if
13331                  * the connector is on the changing crtc but not on the new
13332                  * connector list, disable it. */
13333                 if (!set->fb || !in_mode_set) {
13334                         connector_state->best_encoder = NULL;
13335
13336                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13337                                 connector->base.base.id,
13338                                 connector->base.name);
13339                 }
13340         }
13341         /* connector->new_encoder is now updated for all connectors. */
13342
13343         for_each_connector_in_state(state, drm_connector, connector_state, i) {
13344                 connector = to_intel_connector(drm_connector);
13345
13346                 if (!connector_state->best_encoder) {
13347                         ret = drm_atomic_set_crtc_for_connector(connector_state,
13348                                                                 NULL);
13349                         if (ret)
13350                                 return ret;
13351
13352                         continue;
13353                 }
13354
13355                 if (intel_connector_in_mode_set(connector, set)) {
13356                         struct drm_crtc *crtc = connector->base.state->crtc;
13357
13358                         /* If this connector was in a previous crtc, add it
13359                          * to the state. We might need to disable it. */
13360                         if (crtc) {
13361                                 crtc_state =
13362                                         drm_atomic_get_crtc_state(state, crtc);
13363                                 if (IS_ERR(crtc_state))
13364                                         return PTR_ERR(crtc_state);
13365                         }
13366
13367                         ret = drm_atomic_set_crtc_for_connector(connector_state,
13368                                                                 set->crtc);
13369                         if (ret)
13370                                 return ret;
13371                 }
13372
13373                 /* Make sure the new CRTC will work with the encoder */
13374                 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13375                                          connector_state->crtc)) {
13376                         return -EINVAL;
13377                 }
13378
13379                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13380                         connector->base.base.id,
13381                         connector->base.name,
13382                         connector_state->crtc->base.id);
13383
13384                 if (connector_state->best_encoder != &connector->encoder->base)
13385                         connector->encoder =
13386                                 to_intel_encoder(connector_state->best_encoder);
13387         }
13388
13389         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13390                 bool has_connectors;
13391
13392                 ret = drm_atomic_add_affected_connectors(state, crtc);
13393                 if (ret)
13394                         return ret;
13395
13396                 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13397                 if (has_connectors != crtc_state->enable)
13398                         crtc_state->enable =
13399                         crtc_state->active = has_connectors;
13400         }
13401
13402         ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13403                                               set->fb, set->x, set->y);
13404         if (ret)
13405                 return ret;
13406
13407         crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13408         if (IS_ERR(crtc_state))
13409                 return PTR_ERR(crtc_state);
13410
13411         ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13412         if (ret)
13413                 return ret;
13414
13415         if (set->num_connectors)
13416                 crtc_state->active = true;
13417
13418         return 0;
13419 }
13420
13421 static int intel_crtc_set_config(struct drm_mode_set *set)
13422 {
13423         struct drm_device *dev;
13424         struct drm_atomic_state *state = NULL;
13425         int ret;
13426
13427         BUG_ON(!set);
13428         BUG_ON(!set->crtc);
13429         BUG_ON(!set->crtc->helper_private);
13430
13431         /* Enforce sane interface api - has been abused by the fb helper. */
13432         BUG_ON(!set->mode && set->fb);
13433         BUG_ON(set->fb && set->num_connectors == 0);
13434
13435         if (set->fb) {
13436                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13437                                 set->crtc->base.id, set->fb->base.id,
13438                                 (int)set->num_connectors, set->x, set->y);
13439         } else {
13440                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13441         }
13442
13443         dev = set->crtc->dev;
13444
13445         state = drm_atomic_state_alloc(dev);
13446         if (!state)
13447                 return -ENOMEM;
13448
13449         state->acquire_ctx = dev->mode_config.acquire_ctx;
13450
13451         ret = intel_modeset_stage_output_state(dev, set, state);
13452         if (ret)
13453                 goto out;
13454
13455         ret = intel_modeset_compute_config(state);
13456         if (ret)
13457                 goto out;
13458
13459         intel_update_pipe_size(to_intel_crtc(set->crtc));
13460
13461         ret = intel_set_mode_checked(state);
13462         if (ret) {
13463                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13464                               set->crtc->base.id, ret);
13465         }
13466
13467 out:
13468         if (ret)
13469                 drm_atomic_state_free(state);
13470         return ret;
13471 }
13472
13473 static const struct drm_crtc_funcs intel_crtc_funcs = {
13474         .gamma_set = intel_crtc_gamma_set,
13475         .set_config = intel_crtc_set_config,
13476         .destroy = intel_crtc_destroy,
13477         .page_flip = intel_crtc_page_flip,
13478         .atomic_duplicate_state = intel_crtc_duplicate_state,
13479         .atomic_destroy_state = intel_crtc_destroy_state,
13480 };
13481
13482 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13483                                       struct intel_shared_dpll *pll,
13484                                       struct intel_dpll_hw_state *hw_state)
13485 {
13486         uint32_t val;
13487
13488         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13489                 return false;
13490
13491         val = I915_READ(PCH_DPLL(pll->id));
13492         hw_state->dpll = val;
13493         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13494         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13495
13496         return val & DPLL_VCO_ENABLE;
13497 }
13498
13499 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13500                                   struct intel_shared_dpll *pll)
13501 {
13502         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13503         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13504 }
13505
13506 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13507                                 struct intel_shared_dpll *pll)
13508 {
13509         /* PCH refclock must be enabled first */
13510         ibx_assert_pch_refclk_enabled(dev_priv);
13511
13512         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13513
13514         /* Wait for the clocks to stabilize. */
13515         POSTING_READ(PCH_DPLL(pll->id));
13516         udelay(150);
13517
13518         /* The pixel multiplier can only be updated once the
13519          * DPLL is enabled and the clocks are stable.
13520          *
13521          * So write it again.
13522          */
13523         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13524         POSTING_READ(PCH_DPLL(pll->id));
13525         udelay(200);
13526 }
13527
13528 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13529                                  struct intel_shared_dpll *pll)
13530 {
13531         struct drm_device *dev = dev_priv->dev;
13532         struct intel_crtc *crtc;
13533
13534         /* Make sure no transcoder isn't still depending on us. */
13535         for_each_intel_crtc(dev, crtc) {
13536                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13537                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13538         }
13539
13540         I915_WRITE(PCH_DPLL(pll->id), 0);
13541         POSTING_READ(PCH_DPLL(pll->id));
13542         udelay(200);
13543 }
13544
13545 static char *ibx_pch_dpll_names[] = {
13546         "PCH DPLL A",
13547         "PCH DPLL B",
13548 };
13549
13550 static void ibx_pch_dpll_init(struct drm_device *dev)
13551 {
13552         struct drm_i915_private *dev_priv = dev->dev_private;
13553         int i;
13554
13555         dev_priv->num_shared_dpll = 2;
13556
13557         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13558                 dev_priv->shared_dplls[i].id = i;
13559                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13560                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13561                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13562                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13563                 dev_priv->shared_dplls[i].get_hw_state =
13564                         ibx_pch_dpll_get_hw_state;
13565         }
13566 }
13567
13568 static void intel_shared_dpll_init(struct drm_device *dev)
13569 {
13570         struct drm_i915_private *dev_priv = dev->dev_private;
13571
13572         intel_update_cdclk(dev);
13573
13574         if (HAS_DDI(dev))
13575                 intel_ddi_pll_init(dev);
13576         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13577                 ibx_pch_dpll_init(dev);
13578         else
13579                 dev_priv->num_shared_dpll = 0;
13580
13581         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13582 }
13583
13584 /**
13585  * intel_prepare_plane_fb - Prepare fb for usage on plane
13586  * @plane: drm plane to prepare for
13587  * @fb: framebuffer to prepare for presentation
13588  *
13589  * Prepares a framebuffer for usage on a display plane.  Generally this
13590  * involves pinning the underlying object and updating the frontbuffer tracking
13591  * bits.  Some older platforms need special physical address handling for
13592  * cursor planes.
13593  *
13594  * Returns 0 on success, negative error code on failure.
13595  */
13596 int
13597 intel_prepare_plane_fb(struct drm_plane *plane,
13598                        struct drm_framebuffer *fb,
13599                        const struct drm_plane_state *new_state)
13600 {
13601         struct drm_device *dev = plane->dev;
13602         struct intel_plane *intel_plane = to_intel_plane(plane);
13603         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13604         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13605         int ret = 0;
13606
13607         if (!obj)
13608                 return 0;
13609
13610         mutex_lock(&dev->struct_mutex);
13611
13612         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13613             INTEL_INFO(dev)->cursor_needs_physical) {
13614                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13615                 ret = i915_gem_object_attach_phys(obj, align);
13616                 if (ret)
13617                         DRM_DEBUG_KMS("failed to attach phys object\n");
13618         } else {
13619                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13620         }
13621
13622         if (ret == 0)
13623                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13624
13625         mutex_unlock(&dev->struct_mutex);
13626
13627         return ret;
13628 }
13629
13630 /**
13631  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13632  * @plane: drm plane to clean up for
13633  * @fb: old framebuffer that was on plane
13634  *
13635  * Cleans up a framebuffer that has just been removed from a plane.
13636  */
13637 void
13638 intel_cleanup_plane_fb(struct drm_plane *plane,
13639                        struct drm_framebuffer *fb,
13640                        const struct drm_plane_state *old_state)
13641 {
13642         struct drm_device *dev = plane->dev;
13643         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13644
13645         if (WARN_ON(!obj))
13646                 return;
13647
13648         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13649             !INTEL_INFO(dev)->cursor_needs_physical) {
13650                 mutex_lock(&dev->struct_mutex);
13651                 intel_unpin_fb_obj(fb, old_state);
13652                 mutex_unlock(&dev->struct_mutex);
13653         }
13654 }
13655
13656 int
13657 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13658 {
13659         int max_scale;
13660         struct drm_device *dev;
13661         struct drm_i915_private *dev_priv;
13662         int crtc_clock, cdclk;
13663
13664         if (!intel_crtc || !crtc_state)
13665                 return DRM_PLANE_HELPER_NO_SCALING;
13666
13667         dev = intel_crtc->base.dev;
13668         dev_priv = dev->dev_private;
13669         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13670         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13671
13672         if (!crtc_clock || !cdclk)
13673                 return DRM_PLANE_HELPER_NO_SCALING;
13674
13675         /*
13676          * skl max scale is lower of:
13677          *    close to 3 but not 3, -1 is for that purpose
13678          *            or
13679          *    cdclk/crtc_clock
13680          */
13681         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13682
13683         return max_scale;
13684 }
13685
13686 static int
13687 intel_check_primary_plane(struct drm_plane *plane,
13688                           struct intel_crtc_state *crtc_state,
13689                           struct intel_plane_state *state)
13690 {
13691         struct drm_crtc *crtc = state->base.crtc;
13692         struct drm_framebuffer *fb = state->base.fb;
13693         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13694         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13695         bool can_position = false;
13696
13697         /* use scaler when colorkey is not required */
13698         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13699             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13700                 min_scale = 1;
13701                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13702                 can_position = true;
13703         }
13704
13705         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13706                                              &state->dst, &state->clip,
13707                                              min_scale, max_scale,
13708                                              can_position, true,
13709                                              &state->visible);
13710 }
13711
13712 static void
13713 intel_commit_primary_plane(struct drm_plane *plane,
13714                            struct intel_plane_state *state)
13715 {
13716         struct drm_crtc *crtc = state->base.crtc;
13717         struct drm_framebuffer *fb = state->base.fb;
13718         struct drm_device *dev = plane->dev;
13719         struct drm_i915_private *dev_priv = dev->dev_private;
13720         struct intel_crtc *intel_crtc;
13721         struct drm_rect *src = &state->src;
13722
13723         crtc = crtc ? crtc : plane->crtc;
13724         intel_crtc = to_intel_crtc(crtc);
13725
13726         plane->fb = fb;
13727         crtc->x = src->x1 >> 16;
13728         crtc->y = src->y1 >> 16;
13729
13730         if (!crtc->state->active)
13731                 return;
13732
13733         if (state->visible)
13734                 /* FIXME: kill this fastboot hack */
13735                 intel_update_pipe_size(intel_crtc);
13736
13737         dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13738 }
13739
13740 static void
13741 intel_disable_primary_plane(struct drm_plane *plane,
13742                             struct drm_crtc *crtc)
13743 {
13744         struct drm_device *dev = plane->dev;
13745         struct drm_i915_private *dev_priv = dev->dev_private;
13746
13747         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13748 }
13749
13750 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13751 {
13752         struct drm_device *dev = crtc->dev;
13753         struct drm_i915_private *dev_priv = dev->dev_private;
13754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13755
13756         if (!needs_modeset(crtc->state))
13757                 intel_pre_plane_update(intel_crtc);
13758
13759         if (intel_crtc->atomic.update_wm_pre)
13760                 intel_update_watermarks(crtc);
13761
13762         intel_runtime_pm_get(dev_priv);
13763
13764         /* Perform vblank evasion around commit operation */
13765         if (crtc->state->active)
13766                 intel_crtc->atomic.evade =
13767                         intel_pipe_update_start(intel_crtc,
13768                                                 &intel_crtc->atomic.start_vbl_count);
13769
13770         if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13771                 skl_detach_scalers(intel_crtc);
13772 }
13773
13774 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13775 {
13776         struct drm_device *dev = crtc->dev;
13777         struct drm_i915_private *dev_priv = dev->dev_private;
13778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13779
13780         if (intel_crtc->atomic.evade)
13781                 intel_pipe_update_end(intel_crtc,
13782                                       intel_crtc->atomic.start_vbl_count);
13783
13784         intel_runtime_pm_put(dev_priv);
13785
13786         intel_post_plane_update(intel_crtc);
13787 }
13788
13789 /**
13790  * intel_plane_destroy - destroy a plane
13791  * @plane: plane to destroy
13792  *
13793  * Common destruction function for all types of planes (primary, cursor,
13794  * sprite).
13795  */
13796 void intel_plane_destroy(struct drm_plane *plane)
13797 {
13798         struct intel_plane *intel_plane = to_intel_plane(plane);
13799         drm_plane_cleanup(plane);
13800         kfree(intel_plane);
13801 }
13802
13803 const struct drm_plane_funcs intel_plane_funcs = {
13804         .update_plane = drm_atomic_helper_update_plane,
13805         .disable_plane = drm_atomic_helper_disable_plane,
13806         .destroy = intel_plane_destroy,
13807         .set_property = drm_atomic_helper_plane_set_property,
13808         .atomic_get_property = intel_plane_atomic_get_property,
13809         .atomic_set_property = intel_plane_atomic_set_property,
13810         .atomic_duplicate_state = intel_plane_duplicate_state,
13811         .atomic_destroy_state = intel_plane_destroy_state,
13812
13813 };
13814
13815 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13816                                                     int pipe)
13817 {
13818         struct intel_plane *primary;
13819         struct intel_plane_state *state;
13820         const uint32_t *intel_primary_formats;
13821         int num_formats;
13822
13823         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13824         if (primary == NULL)
13825                 return NULL;
13826
13827         state = intel_create_plane_state(&primary->base);
13828         if (!state) {
13829                 kfree(primary);
13830                 return NULL;
13831         }
13832         primary->base.state = &state->base;
13833
13834         primary->can_scale = false;
13835         primary->max_downscale = 1;
13836         if (INTEL_INFO(dev)->gen >= 9) {
13837                 primary->can_scale = true;
13838                 state->scaler_id = -1;
13839         }
13840         primary->pipe = pipe;
13841         primary->plane = pipe;
13842         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13843         primary->check_plane = intel_check_primary_plane;
13844         primary->commit_plane = intel_commit_primary_plane;
13845         primary->disable_plane = intel_disable_primary_plane;
13846         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13847                 primary->plane = !pipe;
13848
13849         if (INTEL_INFO(dev)->gen >= 9) {
13850                 intel_primary_formats = skl_primary_formats;
13851                 num_formats = ARRAY_SIZE(skl_primary_formats);
13852         } else if (INTEL_INFO(dev)->gen >= 4) {
13853                 intel_primary_formats = i965_primary_formats;
13854                 num_formats = ARRAY_SIZE(i965_primary_formats);
13855         } else {
13856                 intel_primary_formats = i8xx_primary_formats;
13857                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13858         }
13859
13860         drm_universal_plane_init(dev, &primary->base, 0,
13861                                  &intel_plane_funcs,
13862                                  intel_primary_formats, num_formats,
13863                                  DRM_PLANE_TYPE_PRIMARY);
13864
13865         if (INTEL_INFO(dev)->gen >= 4)
13866                 intel_create_rotation_property(dev, primary);
13867
13868         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13869
13870         return &primary->base;
13871 }
13872
13873 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13874 {
13875         if (!dev->mode_config.rotation_property) {
13876                 unsigned long flags = BIT(DRM_ROTATE_0) |
13877                         BIT(DRM_ROTATE_180);
13878
13879                 if (INTEL_INFO(dev)->gen >= 9)
13880                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13881
13882                 dev->mode_config.rotation_property =
13883                         drm_mode_create_rotation_property(dev, flags);
13884         }
13885         if (dev->mode_config.rotation_property)
13886                 drm_object_attach_property(&plane->base.base,
13887                                 dev->mode_config.rotation_property,
13888                                 plane->base.state->rotation);
13889 }
13890
13891 static int
13892 intel_check_cursor_plane(struct drm_plane *plane,
13893                          struct intel_crtc_state *crtc_state,
13894                          struct intel_plane_state *state)
13895 {
13896         struct drm_crtc *crtc = crtc_state->base.crtc;
13897         struct drm_framebuffer *fb = state->base.fb;
13898         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13899         unsigned stride;
13900         int ret;
13901
13902         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13903                                             &state->dst, &state->clip,
13904                                             DRM_PLANE_HELPER_NO_SCALING,
13905                                             DRM_PLANE_HELPER_NO_SCALING,
13906                                             true, true, &state->visible);
13907         if (ret)
13908                 return ret;
13909
13910         /* if we want to turn off the cursor ignore width and height */
13911         if (!obj)
13912                 return 0;
13913
13914         /* Check for which cursor types we support */
13915         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13916                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13917                           state->base.crtc_w, state->base.crtc_h);
13918                 return -EINVAL;
13919         }
13920
13921         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13922         if (obj->base.size < stride * state->base.crtc_h) {
13923                 DRM_DEBUG_KMS("buffer is too small\n");
13924                 return -ENOMEM;
13925         }
13926
13927         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13928                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13929                 return -EINVAL;
13930         }
13931
13932         return 0;
13933 }
13934
13935 static void
13936 intel_disable_cursor_plane(struct drm_plane *plane,
13937                            struct drm_crtc *crtc)
13938 {
13939         intel_crtc_update_cursor(crtc, false);
13940 }
13941
13942 static void
13943 intel_commit_cursor_plane(struct drm_plane *plane,
13944                           struct intel_plane_state *state)
13945 {
13946         struct drm_crtc *crtc = state->base.crtc;
13947         struct drm_device *dev = plane->dev;
13948         struct intel_crtc *intel_crtc;
13949         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13950         uint32_t addr;
13951
13952         crtc = crtc ? crtc : plane->crtc;
13953         intel_crtc = to_intel_crtc(crtc);
13954
13955         plane->fb = state->base.fb;
13956         crtc->cursor_x = state->base.crtc_x;
13957         crtc->cursor_y = state->base.crtc_y;
13958
13959         if (intel_crtc->cursor_bo == obj)
13960                 goto update;
13961
13962         if (!obj)
13963                 addr = 0;
13964         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13965                 addr = i915_gem_obj_ggtt_offset(obj);
13966         else
13967                 addr = obj->phys_handle->busaddr;
13968
13969         intel_crtc->cursor_addr = addr;
13970         intel_crtc->cursor_bo = obj;
13971
13972 update:
13973         if (crtc->state->active)
13974                 intel_crtc_update_cursor(crtc, state->visible);
13975 }
13976
13977 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13978                                                    int pipe)
13979 {
13980         struct intel_plane *cursor;
13981         struct intel_plane_state *state;
13982
13983         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13984         if (cursor == NULL)
13985                 return NULL;
13986
13987         state = intel_create_plane_state(&cursor->base);
13988         if (!state) {
13989                 kfree(cursor);
13990                 return NULL;
13991         }
13992         cursor->base.state = &state->base;
13993
13994         cursor->can_scale = false;
13995         cursor->max_downscale = 1;
13996         cursor->pipe = pipe;
13997         cursor->plane = pipe;
13998         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13999         cursor->check_plane = intel_check_cursor_plane;
14000         cursor->commit_plane = intel_commit_cursor_plane;
14001         cursor->disable_plane = intel_disable_cursor_plane;
14002
14003         drm_universal_plane_init(dev, &cursor->base, 0,
14004                                  &intel_plane_funcs,
14005                                  intel_cursor_formats,
14006                                  ARRAY_SIZE(intel_cursor_formats),
14007                                  DRM_PLANE_TYPE_CURSOR);
14008
14009         if (INTEL_INFO(dev)->gen >= 4) {
14010                 if (!dev->mode_config.rotation_property)
14011                         dev->mode_config.rotation_property =
14012                                 drm_mode_create_rotation_property(dev,
14013                                                         BIT(DRM_ROTATE_0) |
14014                                                         BIT(DRM_ROTATE_180));
14015                 if (dev->mode_config.rotation_property)
14016                         drm_object_attach_property(&cursor->base.base,
14017                                 dev->mode_config.rotation_property,
14018                                 state->base.rotation);
14019         }
14020
14021         if (INTEL_INFO(dev)->gen >=9)
14022                 state->scaler_id = -1;
14023
14024         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14025
14026         return &cursor->base;
14027 }
14028
14029 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14030         struct intel_crtc_state *crtc_state)
14031 {
14032         int i;
14033         struct intel_scaler *intel_scaler;
14034         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14035
14036         for (i = 0; i < intel_crtc->num_scalers; i++) {
14037                 intel_scaler = &scaler_state->scalers[i];
14038                 intel_scaler->in_use = 0;
14039                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14040         }
14041
14042         scaler_state->scaler_id = -1;
14043 }
14044
14045 static void intel_crtc_init(struct drm_device *dev, int pipe)
14046 {
14047         struct drm_i915_private *dev_priv = dev->dev_private;
14048         struct intel_crtc *intel_crtc;
14049         struct intel_crtc_state *crtc_state = NULL;
14050         struct drm_plane *primary = NULL;
14051         struct drm_plane *cursor = NULL;
14052         int i, ret;
14053
14054         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14055         if (intel_crtc == NULL)
14056                 return;
14057
14058         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14059         if (!crtc_state)
14060                 goto fail;
14061         intel_crtc->config = crtc_state;
14062         intel_crtc->base.state = &crtc_state->base;
14063         crtc_state->base.crtc = &intel_crtc->base;
14064
14065         /* initialize shared scalers */
14066         if (INTEL_INFO(dev)->gen >= 9) {
14067                 if (pipe == PIPE_C)
14068                         intel_crtc->num_scalers = 1;
14069                 else
14070                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14071
14072                 skl_init_scalers(dev, intel_crtc, crtc_state);
14073         }
14074
14075         primary = intel_primary_plane_create(dev, pipe);
14076         if (!primary)
14077                 goto fail;
14078
14079         cursor = intel_cursor_plane_create(dev, pipe);
14080         if (!cursor)
14081                 goto fail;
14082
14083         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14084                                         cursor, &intel_crtc_funcs);
14085         if (ret)
14086                 goto fail;
14087
14088         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14089         for (i = 0; i < 256; i++) {
14090                 intel_crtc->lut_r[i] = i;
14091                 intel_crtc->lut_g[i] = i;
14092                 intel_crtc->lut_b[i] = i;
14093         }
14094
14095         /*
14096          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14097          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14098          */
14099         intel_crtc->pipe = pipe;
14100         intel_crtc->plane = pipe;
14101         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14102                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14103                 intel_crtc->plane = !pipe;
14104         }
14105
14106         intel_crtc->cursor_base = ~0;
14107         intel_crtc->cursor_cntl = ~0;
14108         intel_crtc->cursor_size = ~0;
14109
14110         intel_crtc->wm.cxsr_allowed = true;
14111
14112         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14113                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14114         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14115         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14116
14117         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14118
14119         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14120         return;
14121
14122 fail:
14123         if (primary)
14124                 drm_plane_cleanup(primary);
14125         if (cursor)
14126                 drm_plane_cleanup(cursor);
14127         kfree(crtc_state);
14128         kfree(intel_crtc);
14129 }
14130
14131 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14132 {
14133         struct drm_encoder *encoder = connector->base.encoder;
14134         struct drm_device *dev = connector->base.dev;
14135
14136         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14137
14138         if (!encoder || WARN_ON(!encoder->crtc))
14139                 return INVALID_PIPE;
14140
14141         return to_intel_crtc(encoder->crtc)->pipe;
14142 }
14143
14144 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14145                                 struct drm_file *file)
14146 {
14147         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14148         struct drm_crtc *drmmode_crtc;
14149         struct intel_crtc *crtc;
14150
14151         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14152
14153         if (!drmmode_crtc) {
14154                 DRM_ERROR("no such CRTC id\n");
14155                 return -ENOENT;
14156         }
14157
14158         crtc = to_intel_crtc(drmmode_crtc);
14159         pipe_from_crtc_id->pipe = crtc->pipe;
14160
14161         return 0;
14162 }
14163
14164 static int intel_encoder_clones(struct intel_encoder *encoder)
14165 {
14166         struct drm_device *dev = encoder->base.dev;
14167         struct intel_encoder *source_encoder;
14168         int index_mask = 0;
14169         int entry = 0;
14170
14171         for_each_intel_encoder(dev, source_encoder) {
14172                 if (encoders_cloneable(encoder, source_encoder))
14173                         index_mask |= (1 << entry);
14174
14175                 entry++;
14176         }
14177
14178         return index_mask;
14179 }
14180
14181 static bool has_edp_a(struct drm_device *dev)
14182 {
14183         struct drm_i915_private *dev_priv = dev->dev_private;
14184
14185         if (!IS_MOBILE(dev))
14186                 return false;
14187
14188         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14189                 return false;
14190
14191         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14192                 return false;
14193
14194         return true;
14195 }
14196
14197 static bool intel_crt_present(struct drm_device *dev)
14198 {
14199         struct drm_i915_private *dev_priv = dev->dev_private;
14200
14201         if (INTEL_INFO(dev)->gen >= 9)
14202                 return false;
14203
14204         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14205                 return false;
14206
14207         if (IS_CHERRYVIEW(dev))
14208                 return false;
14209
14210         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14211                 return false;
14212
14213         return true;
14214 }
14215
14216 static void intel_setup_outputs(struct drm_device *dev)
14217 {
14218         struct drm_i915_private *dev_priv = dev->dev_private;
14219         struct intel_encoder *encoder;
14220         bool dpd_is_edp = false;
14221
14222         intel_lvds_init(dev);
14223
14224         if (intel_crt_present(dev))
14225                 intel_crt_init(dev);
14226
14227         if (IS_BROXTON(dev)) {
14228                 /*
14229                  * FIXME: Broxton doesn't support port detection via the
14230                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14231                  * detect the ports.
14232                  */
14233                 intel_ddi_init(dev, PORT_A);
14234                 intel_ddi_init(dev, PORT_B);
14235                 intel_ddi_init(dev, PORT_C);
14236         } else if (HAS_DDI(dev)) {
14237                 int found;
14238
14239                 /*
14240                  * Haswell uses DDI functions to detect digital outputs.
14241                  * On SKL pre-D0 the strap isn't connected, so we assume
14242                  * it's there.
14243                  */
14244                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14245                 /* WaIgnoreDDIAStrap: skl */
14246                 if (found ||
14247                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14248                         intel_ddi_init(dev, PORT_A);
14249
14250                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14251                  * register */
14252                 found = I915_READ(SFUSE_STRAP);
14253
14254                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14255                         intel_ddi_init(dev, PORT_B);
14256                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14257                         intel_ddi_init(dev, PORT_C);
14258                 if (found & SFUSE_STRAP_DDID_DETECTED)
14259                         intel_ddi_init(dev, PORT_D);
14260         } else if (HAS_PCH_SPLIT(dev)) {
14261                 int found;
14262                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14263
14264                 if (has_edp_a(dev))
14265                         intel_dp_init(dev, DP_A, PORT_A);
14266
14267                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14268                         /* PCH SDVOB multiplex with HDMIB */
14269                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14270                         if (!found)
14271                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14272                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14273                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14274                 }
14275
14276                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14277                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14278
14279                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14280                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14281
14282                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14283                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14284
14285                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14286                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14287         } else if (IS_VALLEYVIEW(dev)) {
14288                 /*
14289                  * The DP_DETECTED bit is the latched state of the DDC
14290                  * SDA pin at boot. However since eDP doesn't require DDC
14291                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14292                  * eDP ports may have been muxed to an alternate function.
14293                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14294                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14295                  * detect eDP ports.
14296                  */
14297                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14298                     !intel_dp_is_edp(dev, PORT_B))
14299                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14300                                         PORT_B);
14301                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14302                     intel_dp_is_edp(dev, PORT_B))
14303                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14304
14305                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14306                     !intel_dp_is_edp(dev, PORT_C))
14307                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14308                                         PORT_C);
14309                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14310                     intel_dp_is_edp(dev, PORT_C))
14311                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14312
14313                 if (IS_CHERRYVIEW(dev)) {
14314                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14315                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14316                                                 PORT_D);
14317                         /* eDP not supported on port D, so don't check VBT */
14318                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14319                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14320                 }
14321
14322                 intel_dsi_init(dev);
14323         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14324                 bool found = false;
14325
14326                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14327                         DRM_DEBUG_KMS("probing SDVOB\n");
14328                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14329                         if (!found && IS_G4X(dev)) {
14330                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14331                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14332                         }
14333
14334                         if (!found && IS_G4X(dev))
14335                                 intel_dp_init(dev, DP_B, PORT_B);
14336                 }
14337
14338                 /* Before G4X SDVOC doesn't have its own detect register */
14339
14340                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14341                         DRM_DEBUG_KMS("probing SDVOC\n");
14342                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14343                 }
14344
14345                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14346
14347                         if (IS_G4X(dev)) {
14348                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14349                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14350                         }
14351                         if (IS_G4X(dev))
14352                                 intel_dp_init(dev, DP_C, PORT_C);
14353                 }
14354
14355                 if (IS_G4X(dev) &&
14356                     (I915_READ(DP_D) & DP_DETECTED))
14357                         intel_dp_init(dev, DP_D, PORT_D);
14358         } else if (IS_GEN2(dev))
14359                 intel_dvo_init(dev);
14360
14361         if (SUPPORTS_TV(dev))
14362                 intel_tv_init(dev);
14363
14364         intel_psr_init(dev);
14365
14366         for_each_intel_encoder(dev, encoder) {
14367                 encoder->base.possible_crtcs = encoder->crtc_mask;
14368                 encoder->base.possible_clones =
14369                         intel_encoder_clones(encoder);
14370         }
14371
14372         intel_init_pch_refclk(dev);
14373
14374         drm_helper_move_panel_connectors_to_head(dev);
14375 }
14376
14377 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14378 {
14379         struct drm_device *dev = fb->dev;
14380         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14381
14382         drm_framebuffer_cleanup(fb);
14383         mutex_lock(&dev->struct_mutex);
14384         WARN_ON(!intel_fb->obj->framebuffer_references--);
14385         drm_gem_object_unreference(&intel_fb->obj->base);
14386         mutex_unlock(&dev->struct_mutex);
14387         kfree(intel_fb);
14388 }
14389
14390 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14391                                                 struct drm_file *file,
14392                                                 unsigned int *handle)
14393 {
14394         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14395         struct drm_i915_gem_object *obj = intel_fb->obj;
14396
14397         return drm_gem_handle_create(file, &obj->base, handle);
14398 }
14399
14400 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14401                                         struct drm_file *file,
14402                                         unsigned flags, unsigned color,
14403                                         struct drm_clip_rect *clips,
14404                                         unsigned num_clips)
14405 {
14406         struct drm_device *dev = fb->dev;
14407         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14408         struct drm_i915_gem_object *obj = intel_fb->obj;
14409
14410         mutex_lock(&dev->struct_mutex);
14411         intel_fb_obj_flush(obj, false, ORIGIN_GTT);
14412         mutex_unlock(&dev->struct_mutex);
14413
14414         return 0;
14415 }
14416
14417 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14418         .destroy = intel_user_framebuffer_destroy,
14419         .create_handle = intel_user_framebuffer_create_handle,
14420         .dirty = intel_user_framebuffer_dirty,
14421 };
14422
14423 static
14424 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14425                          uint32_t pixel_format)
14426 {
14427         u32 gen = INTEL_INFO(dev)->gen;
14428
14429         if (gen >= 9) {
14430                 /* "The stride in bytes must not exceed the of the size of 8K
14431                  *  pixels and 32K bytes."
14432                  */
14433                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14434         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14435                 return 32*1024;
14436         } else if (gen >= 4) {
14437                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14438                         return 16*1024;
14439                 else
14440                         return 32*1024;
14441         } else if (gen >= 3) {
14442                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14443                         return 8*1024;
14444                 else
14445                         return 16*1024;
14446         } else {
14447                 /* XXX DSPC is limited to 4k tiled */
14448                 return 8*1024;
14449         }
14450 }
14451
14452 static int intel_framebuffer_init(struct drm_device *dev,
14453                                   struct intel_framebuffer *intel_fb,
14454                                   struct drm_mode_fb_cmd2 *mode_cmd,
14455                                   struct drm_i915_gem_object *obj)
14456 {
14457         unsigned int aligned_height;
14458         int ret;
14459         u32 pitch_limit, stride_alignment;
14460
14461         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14462
14463         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14464                 /* Enforce that fb modifier and tiling mode match, but only for
14465                  * X-tiled. This is needed for FBC. */
14466                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14467                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14468                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14469                         return -EINVAL;
14470                 }
14471         } else {
14472                 if (obj->tiling_mode == I915_TILING_X)
14473                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14474                 else if (obj->tiling_mode == I915_TILING_Y) {
14475                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14476                         return -EINVAL;
14477                 }
14478         }
14479
14480         /* Passed in modifier sanity checking. */
14481         switch (mode_cmd->modifier[0]) {
14482         case I915_FORMAT_MOD_Y_TILED:
14483         case I915_FORMAT_MOD_Yf_TILED:
14484                 if (INTEL_INFO(dev)->gen < 9) {
14485                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14486                                   mode_cmd->modifier[0]);
14487                         return -EINVAL;
14488                 }
14489         case DRM_FORMAT_MOD_NONE:
14490         case I915_FORMAT_MOD_X_TILED:
14491                 break;
14492         default:
14493                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14494                           mode_cmd->modifier[0]);
14495                 return -EINVAL;
14496         }
14497
14498         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14499                                                      mode_cmd->pixel_format);
14500         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14501                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14502                           mode_cmd->pitches[0], stride_alignment);
14503                 return -EINVAL;
14504         }
14505
14506         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14507                                            mode_cmd->pixel_format);
14508         if (mode_cmd->pitches[0] > pitch_limit) {
14509                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14510                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14511                           "tiled" : "linear",
14512                           mode_cmd->pitches[0], pitch_limit);
14513                 return -EINVAL;
14514         }
14515
14516         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14517             mode_cmd->pitches[0] != obj->stride) {
14518                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14519                           mode_cmd->pitches[0], obj->stride);
14520                 return -EINVAL;
14521         }
14522
14523         /* Reject formats not supported by any plane early. */
14524         switch (mode_cmd->pixel_format) {
14525         case DRM_FORMAT_C8:
14526         case DRM_FORMAT_RGB565:
14527         case DRM_FORMAT_XRGB8888:
14528         case DRM_FORMAT_ARGB8888:
14529                 break;
14530         case DRM_FORMAT_XRGB1555:
14531                 if (INTEL_INFO(dev)->gen > 3) {
14532                         DRM_DEBUG("unsupported pixel format: %s\n",
14533                                   drm_get_format_name(mode_cmd->pixel_format));
14534                         return -EINVAL;
14535                 }
14536                 break;
14537         case DRM_FORMAT_ABGR8888:
14538                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14539                         DRM_DEBUG("unsupported pixel format: %s\n",
14540                                   drm_get_format_name(mode_cmd->pixel_format));
14541                         return -EINVAL;
14542                 }
14543                 break;
14544         case DRM_FORMAT_XBGR8888:
14545         case DRM_FORMAT_XRGB2101010:
14546         case DRM_FORMAT_XBGR2101010:
14547                 if (INTEL_INFO(dev)->gen < 4) {
14548                         DRM_DEBUG("unsupported pixel format: %s\n",
14549                                   drm_get_format_name(mode_cmd->pixel_format));
14550                         return -EINVAL;
14551                 }
14552                 break;
14553         case DRM_FORMAT_ABGR2101010:
14554                 if (!IS_VALLEYVIEW(dev)) {
14555                         DRM_DEBUG("unsupported pixel format: %s\n",
14556                                   drm_get_format_name(mode_cmd->pixel_format));
14557                         return -EINVAL;
14558                 }
14559                 break;
14560         case DRM_FORMAT_YUYV:
14561         case DRM_FORMAT_UYVY:
14562         case DRM_FORMAT_YVYU:
14563         case DRM_FORMAT_VYUY:
14564                 if (INTEL_INFO(dev)->gen < 5) {
14565                         DRM_DEBUG("unsupported pixel format: %s\n",
14566                                   drm_get_format_name(mode_cmd->pixel_format));
14567                         return -EINVAL;
14568                 }
14569                 break;
14570         default:
14571                 DRM_DEBUG("unsupported pixel format: %s\n",
14572                           drm_get_format_name(mode_cmd->pixel_format));
14573                 return -EINVAL;
14574         }
14575
14576         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14577         if (mode_cmd->offsets[0] != 0)
14578                 return -EINVAL;
14579
14580         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14581                                                mode_cmd->pixel_format,
14582                                                mode_cmd->modifier[0]);
14583         /* FIXME drm helper for size checks (especially planar formats)? */
14584         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14585                 return -EINVAL;
14586
14587         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14588         intel_fb->obj = obj;
14589         intel_fb->obj->framebuffer_references++;
14590
14591         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14592         if (ret) {
14593                 DRM_ERROR("framebuffer init failed %d\n", ret);
14594                 return ret;
14595         }
14596
14597         return 0;
14598 }
14599
14600 static struct drm_framebuffer *
14601 intel_user_framebuffer_create(struct drm_device *dev,
14602                               struct drm_file *filp,
14603                               struct drm_mode_fb_cmd2 *mode_cmd)
14604 {
14605         struct drm_i915_gem_object *obj;
14606
14607         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14608                                                 mode_cmd->handles[0]));
14609         if (&obj->base == NULL)
14610                 return ERR_PTR(-ENOENT);
14611
14612         return intel_framebuffer_create(dev, mode_cmd, obj);
14613 }
14614
14615 #ifndef CONFIG_DRM_I915_FBDEV
14616 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14617 {
14618 }
14619 #endif
14620
14621 static const struct drm_mode_config_funcs intel_mode_funcs = {
14622         .fb_create = intel_user_framebuffer_create,
14623         .output_poll_changed = intel_fbdev_output_poll_changed,
14624         .atomic_check = intel_atomic_check,
14625         .atomic_commit = intel_atomic_commit,
14626         .atomic_state_alloc = intel_atomic_state_alloc,
14627         .atomic_state_clear = intel_atomic_state_clear,
14628 };
14629
14630 /* Set up chip specific display functions */
14631 static void intel_init_display(struct drm_device *dev)
14632 {
14633         struct drm_i915_private *dev_priv = dev->dev_private;
14634
14635         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14636                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14637         else if (IS_CHERRYVIEW(dev))
14638                 dev_priv->display.find_dpll = chv_find_best_dpll;
14639         else if (IS_VALLEYVIEW(dev))
14640                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14641         else if (IS_PINEVIEW(dev))
14642                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14643         else
14644                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14645
14646         if (INTEL_INFO(dev)->gen >= 9) {
14647                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14648                 dev_priv->display.get_initial_plane_config =
14649                         skylake_get_initial_plane_config;
14650                 dev_priv->display.crtc_compute_clock =
14651                         haswell_crtc_compute_clock;
14652                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14653                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14654                 dev_priv->display.update_primary_plane =
14655                         skylake_update_primary_plane;
14656         } else if (HAS_DDI(dev)) {
14657                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14658                 dev_priv->display.get_initial_plane_config =
14659                         ironlake_get_initial_plane_config;
14660                 dev_priv->display.crtc_compute_clock =
14661                         haswell_crtc_compute_clock;
14662                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14663                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14664                 dev_priv->display.update_primary_plane =
14665                         ironlake_update_primary_plane;
14666         } else if (HAS_PCH_SPLIT(dev)) {
14667                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14668                 dev_priv->display.get_initial_plane_config =
14669                         ironlake_get_initial_plane_config;
14670                 dev_priv->display.crtc_compute_clock =
14671                         ironlake_crtc_compute_clock;
14672                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14673                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14674                 dev_priv->display.update_primary_plane =
14675                         ironlake_update_primary_plane;
14676         } else if (IS_VALLEYVIEW(dev)) {
14677                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14678                 dev_priv->display.get_initial_plane_config =
14679                         i9xx_get_initial_plane_config;
14680                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14681                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14682                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14683                 dev_priv->display.update_primary_plane =
14684                         i9xx_update_primary_plane;
14685         } else {
14686                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14687                 dev_priv->display.get_initial_plane_config =
14688                         i9xx_get_initial_plane_config;
14689                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14690                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14691                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14692                 dev_priv->display.update_primary_plane =
14693                         i9xx_update_primary_plane;
14694         }
14695
14696         /* Returns the core display clock speed */
14697         if (IS_SKYLAKE(dev))
14698                 dev_priv->display.get_display_clock_speed =
14699                         skylake_get_display_clock_speed;
14700         else if (IS_BROXTON(dev))
14701                 dev_priv->display.get_display_clock_speed =
14702                         broxton_get_display_clock_speed;
14703         else if (IS_BROADWELL(dev))
14704                 dev_priv->display.get_display_clock_speed =
14705                         broadwell_get_display_clock_speed;
14706         else if (IS_HASWELL(dev))
14707                 dev_priv->display.get_display_clock_speed =
14708                         haswell_get_display_clock_speed;
14709         else if (IS_VALLEYVIEW(dev))
14710                 dev_priv->display.get_display_clock_speed =
14711                         valleyview_get_display_clock_speed;
14712         else if (IS_GEN5(dev))
14713                 dev_priv->display.get_display_clock_speed =
14714                         ilk_get_display_clock_speed;
14715         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14716                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14717                 dev_priv->display.get_display_clock_speed =
14718                         i945_get_display_clock_speed;
14719         else if (IS_GM45(dev))
14720                 dev_priv->display.get_display_clock_speed =
14721                         gm45_get_display_clock_speed;
14722         else if (IS_CRESTLINE(dev))
14723                 dev_priv->display.get_display_clock_speed =
14724                         i965gm_get_display_clock_speed;
14725         else if (IS_PINEVIEW(dev))
14726                 dev_priv->display.get_display_clock_speed =
14727                         pnv_get_display_clock_speed;
14728         else if (IS_G33(dev) || IS_G4X(dev))
14729                 dev_priv->display.get_display_clock_speed =
14730                         g33_get_display_clock_speed;
14731         else if (IS_I915G(dev))
14732                 dev_priv->display.get_display_clock_speed =
14733                         i915_get_display_clock_speed;
14734         else if (IS_I945GM(dev) || IS_845G(dev))
14735                 dev_priv->display.get_display_clock_speed =
14736                         i9xx_misc_get_display_clock_speed;
14737         else if (IS_PINEVIEW(dev))
14738                 dev_priv->display.get_display_clock_speed =
14739                         pnv_get_display_clock_speed;
14740         else if (IS_I915GM(dev))
14741                 dev_priv->display.get_display_clock_speed =
14742                         i915gm_get_display_clock_speed;
14743         else if (IS_I865G(dev))
14744                 dev_priv->display.get_display_clock_speed =
14745                         i865_get_display_clock_speed;
14746         else if (IS_I85X(dev))
14747                 dev_priv->display.get_display_clock_speed =
14748                         i85x_get_display_clock_speed;
14749         else { /* 830 */
14750                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14751                 dev_priv->display.get_display_clock_speed =
14752                         i830_get_display_clock_speed;
14753         }
14754
14755         if (IS_GEN5(dev)) {
14756                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14757         } else if (IS_GEN6(dev)) {
14758                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14759         } else if (IS_IVYBRIDGE(dev)) {
14760                 /* FIXME: detect B0+ stepping and use auto training */
14761                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14762         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14763                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14764                 if (IS_BROADWELL(dev)) {
14765                         dev_priv->display.modeset_commit_cdclk =
14766                                 broadwell_modeset_commit_cdclk;
14767                         dev_priv->display.modeset_calc_cdclk =
14768                                 broadwell_modeset_calc_cdclk;
14769                 }
14770         } else if (IS_VALLEYVIEW(dev)) {
14771                 dev_priv->display.modeset_commit_cdclk =
14772                         valleyview_modeset_commit_cdclk;
14773                 dev_priv->display.modeset_calc_cdclk =
14774                         valleyview_modeset_calc_cdclk;
14775         } else if (IS_BROXTON(dev)) {
14776                 dev_priv->display.modeset_commit_cdclk =
14777                         broxton_modeset_commit_cdclk;
14778                 dev_priv->display.modeset_calc_cdclk =
14779                         broxton_modeset_calc_cdclk;
14780         }
14781
14782         switch (INTEL_INFO(dev)->gen) {
14783         case 2:
14784                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14785                 break;
14786
14787         case 3:
14788                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14789                 break;
14790
14791         case 4:
14792         case 5:
14793                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14794                 break;
14795
14796         case 6:
14797                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14798                 break;
14799         case 7:
14800         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14801                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14802                 break;
14803         case 9:
14804                 /* Drop through - unsupported since execlist only. */
14805         default:
14806                 /* Default just returns -ENODEV to indicate unsupported */
14807                 dev_priv->display.queue_flip = intel_default_queue_flip;
14808         }
14809
14810         intel_panel_init_backlight_funcs(dev);
14811
14812         mutex_init(&dev_priv->pps_mutex);
14813 }
14814
14815 /*
14816  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14817  * resume, or other times.  This quirk makes sure that's the case for
14818  * affected systems.
14819  */
14820 static void quirk_pipea_force(struct drm_device *dev)
14821 {
14822         struct drm_i915_private *dev_priv = dev->dev_private;
14823
14824         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14825         DRM_INFO("applying pipe a force quirk\n");
14826 }
14827
14828 static void quirk_pipeb_force(struct drm_device *dev)
14829 {
14830         struct drm_i915_private *dev_priv = dev->dev_private;
14831
14832         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14833         DRM_INFO("applying pipe b force quirk\n");
14834 }
14835
14836 /*
14837  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14838  */
14839 static void quirk_ssc_force_disable(struct drm_device *dev)
14840 {
14841         struct drm_i915_private *dev_priv = dev->dev_private;
14842         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14843         DRM_INFO("applying lvds SSC disable quirk\n");
14844 }
14845
14846 /*
14847  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14848  * brightness value
14849  */
14850 static void quirk_invert_brightness(struct drm_device *dev)
14851 {
14852         struct drm_i915_private *dev_priv = dev->dev_private;
14853         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14854         DRM_INFO("applying inverted panel brightness quirk\n");
14855 }
14856
14857 /* Some VBT's incorrectly indicate no backlight is present */
14858 static void quirk_backlight_present(struct drm_device *dev)
14859 {
14860         struct drm_i915_private *dev_priv = dev->dev_private;
14861         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14862         DRM_INFO("applying backlight present quirk\n");
14863 }
14864
14865 struct intel_quirk {
14866         int device;
14867         int subsystem_vendor;
14868         int subsystem_device;
14869         void (*hook)(struct drm_device *dev);
14870 };
14871
14872 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14873 struct intel_dmi_quirk {
14874         void (*hook)(struct drm_device *dev);
14875         const struct dmi_system_id (*dmi_id_list)[];
14876 };
14877
14878 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14879 {
14880         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14881         return 1;
14882 }
14883
14884 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14885         {
14886                 .dmi_id_list = &(const struct dmi_system_id[]) {
14887                         {
14888                                 .callback = intel_dmi_reverse_brightness,
14889                                 .ident = "NCR Corporation",
14890                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14891                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14892                                 },
14893                         },
14894                         { }  /* terminating entry */
14895                 },
14896                 .hook = quirk_invert_brightness,
14897         },
14898 };
14899
14900 static struct intel_quirk intel_quirks[] = {
14901         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14902         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14903
14904         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14905         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14906
14907         /* 830 needs to leave pipe A & dpll A up */
14908         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14909
14910         /* 830 needs to leave pipe B & dpll B up */
14911         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14912
14913         /* Lenovo U160 cannot use SSC on LVDS */
14914         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14915
14916         /* Sony Vaio Y cannot use SSC on LVDS */
14917         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14918
14919         /* Acer Aspire 5734Z must invert backlight brightness */
14920         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14921
14922         /* Acer/eMachines G725 */
14923         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14924
14925         /* Acer/eMachines e725 */
14926         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14927
14928         /* Acer/Packard Bell NCL20 */
14929         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14930
14931         /* Acer Aspire 4736Z */
14932         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14933
14934         /* Acer Aspire 5336 */
14935         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14936
14937         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14938         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14939
14940         /* Acer C720 Chromebook (Core i3 4005U) */
14941         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14942
14943         /* Apple Macbook 2,1 (Core 2 T7400) */
14944         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14945
14946         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14947         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14948
14949         /* HP Chromebook 14 (Celeron 2955U) */
14950         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14951
14952         /* Dell Chromebook 11 */
14953         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14954 };
14955
14956 static void intel_init_quirks(struct drm_device *dev)
14957 {
14958         struct pci_dev *d = dev->pdev;
14959         int i;
14960
14961         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14962                 struct intel_quirk *q = &intel_quirks[i];
14963
14964                 if (d->device == q->device &&
14965                     (d->subsystem_vendor == q->subsystem_vendor ||
14966                      q->subsystem_vendor == PCI_ANY_ID) &&
14967                     (d->subsystem_device == q->subsystem_device ||
14968                      q->subsystem_device == PCI_ANY_ID))
14969                         q->hook(dev);
14970         }
14971         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14972                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14973                         intel_dmi_quirks[i].hook(dev);
14974         }
14975 }
14976
14977 /* Disable the VGA plane that we never use */
14978 static void i915_disable_vga(struct drm_device *dev)
14979 {
14980         struct drm_i915_private *dev_priv = dev->dev_private;
14981         u8 sr1;
14982         u32 vga_reg = i915_vgacntrl_reg(dev);
14983
14984         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14985         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14986         outb(SR01, VGA_SR_INDEX);
14987         sr1 = inb(VGA_SR_DATA);
14988         outb(sr1 | 1<<5, VGA_SR_DATA);
14989         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14990         udelay(300);
14991
14992         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14993         POSTING_READ(vga_reg);
14994 }
14995
14996 void intel_modeset_init_hw(struct drm_device *dev)
14997 {
14998         intel_update_cdclk(dev);
14999         intel_prepare_ddi(dev);
15000         intel_init_clock_gating(dev);
15001         intel_enable_gt_powersave(dev);
15002 }
15003
15004 void intel_modeset_init(struct drm_device *dev)
15005 {
15006         struct drm_i915_private *dev_priv = dev->dev_private;
15007         int sprite, ret;
15008         enum pipe pipe;
15009         struct intel_crtc *crtc;
15010
15011         drm_mode_config_init(dev);
15012
15013         dev->mode_config.min_width = 0;
15014         dev->mode_config.min_height = 0;
15015
15016         dev->mode_config.preferred_depth = 24;
15017         dev->mode_config.prefer_shadow = 1;
15018
15019         dev->mode_config.allow_fb_modifiers = true;
15020
15021         dev->mode_config.funcs = &intel_mode_funcs;
15022
15023         intel_init_quirks(dev);
15024
15025         intel_init_pm(dev);
15026
15027         if (INTEL_INFO(dev)->num_pipes == 0)
15028                 return;
15029
15030         intel_init_display(dev);
15031         intel_init_audio(dev);
15032
15033         if (IS_GEN2(dev)) {
15034                 dev->mode_config.max_width = 2048;
15035                 dev->mode_config.max_height = 2048;
15036         } else if (IS_GEN3(dev)) {
15037                 dev->mode_config.max_width = 4096;
15038                 dev->mode_config.max_height = 4096;
15039         } else {
15040                 dev->mode_config.max_width = 8192;
15041                 dev->mode_config.max_height = 8192;
15042         }
15043
15044         if (IS_845G(dev) || IS_I865G(dev)) {
15045                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15046                 dev->mode_config.cursor_height = 1023;
15047         } else if (IS_GEN2(dev)) {
15048                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15049                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15050         } else {
15051                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15052                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15053         }
15054
15055         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15056
15057         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15058                       INTEL_INFO(dev)->num_pipes,
15059                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15060
15061         for_each_pipe(dev_priv, pipe) {
15062                 intel_crtc_init(dev, pipe);
15063                 for_each_sprite(dev_priv, pipe, sprite) {
15064                         ret = intel_plane_init(dev, pipe, sprite);
15065                         if (ret)
15066                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15067                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15068                 }
15069         }
15070
15071         intel_init_dpio(dev);
15072
15073         intel_shared_dpll_init(dev);
15074
15075         /* Just disable it once at startup */
15076         i915_disable_vga(dev);
15077         intel_setup_outputs(dev);
15078
15079         /* Just in case the BIOS is doing something questionable. */
15080         intel_fbc_disable(dev_priv);
15081
15082         drm_modeset_lock_all(dev);
15083         intel_modeset_setup_hw_state(dev, false);
15084         drm_modeset_unlock_all(dev);
15085
15086         for_each_intel_crtc(dev, crtc) {
15087                 if (!crtc->active)
15088                         continue;
15089
15090                 /*
15091                  * Note that reserving the BIOS fb up front prevents us
15092                  * from stuffing other stolen allocations like the ring
15093                  * on top.  This prevents some ugliness at boot time, and
15094                  * can even allow for smooth boot transitions if the BIOS
15095                  * fb is large enough for the active pipe configuration.
15096                  */
15097                 if (dev_priv->display.get_initial_plane_config) {
15098                         dev_priv->display.get_initial_plane_config(crtc,
15099                                                            &crtc->plane_config);
15100                         /*
15101                          * If the fb is shared between multiple heads, we'll
15102                          * just get the first one.
15103                          */
15104                         intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15105                 }
15106         }
15107 }
15108
15109 static void intel_enable_pipe_a(struct drm_device *dev)
15110 {
15111         struct intel_connector *connector;
15112         struct drm_connector *crt = NULL;
15113         struct intel_load_detect_pipe load_detect_temp;
15114         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15115
15116         /* We can't just switch on the pipe A, we need to set things up with a
15117          * proper mode and output configuration. As a gross hack, enable pipe A
15118          * by enabling the load detect pipe once. */
15119         for_each_intel_connector(dev, connector) {
15120                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15121                         crt = &connector->base;
15122                         break;
15123                 }
15124         }
15125
15126         if (!crt)
15127                 return;
15128
15129         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15130                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15131 }
15132
15133 static bool
15134 intel_check_plane_mapping(struct intel_crtc *crtc)
15135 {
15136         struct drm_device *dev = crtc->base.dev;
15137         struct drm_i915_private *dev_priv = dev->dev_private;
15138         u32 reg, val;
15139
15140         if (INTEL_INFO(dev)->num_pipes == 1)
15141                 return true;
15142
15143         reg = DSPCNTR(!crtc->plane);
15144         val = I915_READ(reg);
15145
15146         if ((val & DISPLAY_PLANE_ENABLE) &&
15147             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15148                 return false;
15149
15150         return true;
15151 }
15152
15153 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15154 {
15155         struct drm_device *dev = crtc->base.dev;
15156         struct drm_i915_private *dev_priv = dev->dev_private;
15157         struct intel_encoder *encoder;
15158         u32 reg;
15159         bool enable;
15160
15161         /* Clear any frame start delays used for debugging left by the BIOS */
15162         reg = PIPECONF(crtc->config->cpu_transcoder);
15163         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15164
15165         /* restore vblank interrupts to correct state */
15166         drm_crtc_vblank_reset(&crtc->base);
15167         if (crtc->active) {
15168                 update_scanline_offset(crtc);
15169                 drm_crtc_vblank_on(&crtc->base);
15170         }
15171
15172         /* We need to sanitize the plane -> pipe mapping first because this will
15173          * disable the crtc (and hence change the state) if it is wrong. Note
15174          * that gen4+ has a fixed plane -> pipe mapping.  */
15175         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15176                 bool plane;
15177
15178                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15179                               crtc->base.base.id);
15180
15181                 /* Pipe has the wrong plane attached and the plane is active.
15182                  * Temporarily change the plane mapping and disable everything
15183                  * ...  */
15184                 plane = crtc->plane;
15185                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15186                 crtc->plane = !plane;
15187                 intel_crtc_disable_noatomic(&crtc->base);
15188                 crtc->plane = plane;
15189         }
15190
15191         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15192             crtc->pipe == PIPE_A && !crtc->active) {
15193                 /* BIOS forgot to enable pipe A, this mostly happens after
15194                  * resume. Force-enable the pipe to fix this, the update_dpms
15195                  * call below we restore the pipe to the right state, but leave
15196                  * the required bits on. */
15197                 intel_enable_pipe_a(dev);
15198         }
15199
15200         /* Adjust the state of the output pipe according to whether we
15201          * have active connectors/encoders. */
15202         enable = false;
15203         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15204                 enable |= encoder->connectors_active;
15205
15206         if (!enable)
15207                 intel_crtc_disable_noatomic(&crtc->base);
15208
15209         if (crtc->active != crtc->base.state->active) {
15210
15211                 /* This can happen either due to bugs in the get_hw_state
15212                  * functions or because of calls to intel_crtc_disable_noatomic,
15213                  * or because the pipe is force-enabled due to the
15214                  * pipe A quirk. */
15215                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15216                               crtc->base.base.id,
15217                               crtc->base.state->enable ? "enabled" : "disabled",
15218                               crtc->active ? "enabled" : "disabled");
15219
15220                 crtc->base.state->enable = crtc->active;
15221                 crtc->base.state->active = crtc->active;
15222                 crtc->base.enabled = crtc->active;
15223
15224                 /* Because we only establish the connector -> encoder ->
15225                  * crtc links if something is active, this means the
15226                  * crtc is now deactivated. Break the links. connector
15227                  * -> encoder links are only establish when things are
15228                  *  actually up, hence no need to break them. */
15229                 WARN_ON(crtc->active);
15230
15231                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15232                         WARN_ON(encoder->connectors_active);
15233                         encoder->base.crtc = NULL;
15234                 }
15235         }
15236
15237         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15238                 /*
15239                  * We start out with underrun reporting disabled to avoid races.
15240                  * For correct bookkeeping mark this on active crtcs.
15241                  *
15242                  * Also on gmch platforms we dont have any hardware bits to
15243                  * disable the underrun reporting. Which means we need to start
15244                  * out with underrun reporting disabled also on inactive pipes,
15245                  * since otherwise we'll complain about the garbage we read when
15246                  * e.g. coming up after runtime pm.
15247                  *
15248                  * No protection against concurrent access is required - at
15249                  * worst a fifo underrun happens which also sets this to false.
15250                  */
15251                 crtc->cpu_fifo_underrun_disabled = true;
15252                 crtc->pch_fifo_underrun_disabled = true;
15253         }
15254 }
15255
15256 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15257 {
15258         struct intel_connector *connector;
15259         struct drm_device *dev = encoder->base.dev;
15260
15261         /* We need to check both for a crtc link (meaning that the
15262          * encoder is active and trying to read from a pipe) and the
15263          * pipe itself being active. */
15264         bool has_active_crtc = encoder->base.crtc &&
15265                 to_intel_crtc(encoder->base.crtc)->active;
15266
15267         if (encoder->connectors_active && !has_active_crtc) {
15268                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15269                               encoder->base.base.id,
15270                               encoder->base.name);
15271
15272                 /* Connector is active, but has no active pipe. This is
15273                  * fallout from our resume register restoring. Disable
15274                  * the encoder manually again. */
15275                 if (encoder->base.crtc) {
15276                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15277                                       encoder->base.base.id,
15278                                       encoder->base.name);
15279                         encoder->disable(encoder);
15280                         if (encoder->post_disable)
15281                                 encoder->post_disable(encoder);
15282                 }
15283                 encoder->base.crtc = NULL;
15284                 encoder->connectors_active = false;
15285
15286                 /* Inconsistent output/port/pipe state happens presumably due to
15287                  * a bug in one of the get_hw_state functions. Or someplace else
15288                  * in our code, like the register restore mess on resume. Clamp
15289                  * things to off as a safer default. */
15290                 for_each_intel_connector(dev, connector) {
15291                         if (connector->encoder != encoder)
15292                                 continue;
15293                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15294                         connector->base.encoder = NULL;
15295                 }
15296         }
15297         /* Enabled encoders without active connectors will be fixed in
15298          * the crtc fixup. */
15299 }
15300
15301 void i915_redisable_vga_power_on(struct drm_device *dev)
15302 {
15303         struct drm_i915_private *dev_priv = dev->dev_private;
15304         u32 vga_reg = i915_vgacntrl_reg(dev);
15305
15306         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15307                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15308                 i915_disable_vga(dev);
15309         }
15310 }
15311
15312 void i915_redisable_vga(struct drm_device *dev)
15313 {
15314         struct drm_i915_private *dev_priv = dev->dev_private;
15315
15316         /* This function can be called both from intel_modeset_setup_hw_state or
15317          * at a very early point in our resume sequence, where the power well
15318          * structures are not yet restored. Since this function is at a very
15319          * paranoid "someone might have enabled VGA while we were not looking"
15320          * level, just check if the power well is enabled instead of trying to
15321          * follow the "don't touch the power well if we don't need it" policy
15322          * the rest of the driver uses. */
15323         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15324                 return;
15325
15326         i915_redisable_vga_power_on(dev);
15327 }
15328
15329 static bool primary_get_hw_state(struct intel_crtc *crtc)
15330 {
15331         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15332
15333         return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15334 }
15335
15336 static void readout_plane_state(struct intel_crtc *crtc,
15337                                 struct intel_crtc_state *crtc_state)
15338 {
15339         struct intel_plane *p;
15340         struct drm_plane_state *drm_plane_state;
15341         bool active = crtc_state->base.active;
15342
15343         if (active) {
15344                 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15345
15346                 /* apply to previous sw state too */
15347                 to_intel_crtc_state(crtc->base.state)->quirks |=
15348                         PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15349         }
15350
15351         for_each_intel_plane(crtc->base.dev, p) {
15352                 bool visible = active;
15353
15354                 if (crtc->pipe != p->pipe)
15355                         continue;
15356
15357                 drm_plane_state = p->base.state;
15358                 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15359                         visible = primary_get_hw_state(crtc);
15360                         to_intel_plane_state(drm_plane_state)->visible = visible;
15361                 } else {
15362                         /*
15363                          * unknown state, assume it's off to force a transition
15364                          * to on when calculating state changes.
15365                          */
15366                         to_intel_plane_state(drm_plane_state)->visible = false;
15367                 }
15368
15369                 if (visible) {
15370                         crtc_state->base.plane_mask |=
15371                                 1 << drm_plane_index(&p->base);
15372                 } else if (crtc_state->base.state) {
15373                         /* Make this unconditional for atomic hw readout. */
15374                         crtc_state->base.plane_mask &=
15375                                 ~(1 << drm_plane_index(&p->base));
15376                 }
15377         }
15378 }
15379
15380 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15381 {
15382         struct drm_i915_private *dev_priv = dev->dev_private;
15383         enum pipe pipe;
15384         struct intel_crtc *crtc;
15385         struct intel_encoder *encoder;
15386         struct intel_connector *connector;
15387         int i;
15388
15389         for_each_intel_crtc(dev, crtc) {
15390                 memset(crtc->config, 0, sizeof(*crtc->config));
15391                 crtc->config->base.crtc = &crtc->base;
15392
15393                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15394
15395                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15396                                                                  crtc->config);
15397
15398                 crtc->base.state->enable = crtc->active;
15399                 crtc->base.state->active = crtc->active;
15400                 crtc->base.enabled = crtc->active;
15401                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15402
15403                 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15404
15405                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15406                               crtc->base.base.id,
15407                               crtc->active ? "enabled" : "disabled");
15408         }
15409
15410         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15411                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15412
15413                 pll->on = pll->get_hw_state(dev_priv, pll,
15414                                             &pll->config.hw_state);
15415                 pll->active = 0;
15416                 pll->config.crtc_mask = 0;
15417                 for_each_intel_crtc(dev, crtc) {
15418                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15419                                 pll->active++;
15420                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15421                         }
15422                 }
15423
15424                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15425                               pll->name, pll->config.crtc_mask, pll->on);
15426
15427                 if (pll->config.crtc_mask)
15428                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15429         }
15430
15431         for_each_intel_encoder(dev, encoder) {
15432                 pipe = 0;
15433
15434                 if (encoder->get_hw_state(encoder, &pipe)) {
15435                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15436                         encoder->base.crtc = &crtc->base;
15437                         encoder->get_config(encoder, crtc->config);
15438                 } else {
15439                         encoder->base.crtc = NULL;
15440                 }
15441
15442                 encoder->connectors_active = false;
15443                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15444                               encoder->base.base.id,
15445                               encoder->base.name,
15446                               encoder->base.crtc ? "enabled" : "disabled",
15447                               pipe_name(pipe));
15448         }
15449
15450         for_each_intel_connector(dev, connector) {
15451                 if (connector->get_hw_state(connector)) {
15452                         connector->base.dpms = DRM_MODE_DPMS_ON;
15453                         connector->encoder->connectors_active = true;
15454                         connector->base.encoder = &connector->encoder->base;
15455                 } else {
15456                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15457                         connector->base.encoder = NULL;
15458                 }
15459                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15460                               connector->base.base.id,
15461                               connector->base.name,
15462                               connector->base.encoder ? "enabled" : "disabled");
15463         }
15464 }
15465
15466 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15467  * and i915 state tracking structures. */
15468 void intel_modeset_setup_hw_state(struct drm_device *dev,
15469                                   bool force_restore)
15470 {
15471         struct drm_i915_private *dev_priv = dev->dev_private;
15472         enum pipe pipe;
15473         struct intel_crtc *crtc;
15474         struct intel_encoder *encoder;
15475         int i;
15476
15477         intel_modeset_readout_hw_state(dev);
15478
15479         /*
15480          * Now that we have the config, copy it to each CRTC struct
15481          * Note that this could go away if we move to using crtc_config
15482          * checking everywhere.
15483          */
15484         for_each_intel_crtc(dev, crtc) {
15485                 if (crtc->active && i915.fastboot) {
15486                         intel_mode_from_pipe_config(&crtc->base.mode,
15487                                                     crtc->config);
15488                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15489                                       crtc->base.base.id);
15490                         drm_mode_debug_printmodeline(&crtc->base.mode);
15491                 }
15492         }
15493
15494         /* HW state is read out, now we need to sanitize this mess. */
15495         for_each_intel_encoder(dev, encoder) {
15496                 intel_sanitize_encoder(encoder);
15497         }
15498
15499         for_each_pipe(dev_priv, pipe) {
15500                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15501                 intel_sanitize_crtc(crtc);
15502                 intel_dump_pipe_config(crtc, crtc->config,
15503                                        "[setup_hw_state]");
15504         }
15505
15506         intel_modeset_update_connector_atomic_state(dev);
15507
15508         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15509                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15510
15511                 if (!pll->on || pll->active)
15512                         continue;
15513
15514                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15515
15516                 pll->disable(dev_priv, pll);
15517                 pll->on = false;
15518         }
15519
15520         if (IS_VALLEYVIEW(dev))
15521                 vlv_wm_get_hw_state(dev);
15522         else if (IS_GEN9(dev))
15523                 skl_wm_get_hw_state(dev);
15524         else if (HAS_PCH_SPLIT(dev))
15525                 ilk_wm_get_hw_state(dev);
15526
15527         if (force_restore) {
15528                 i915_redisable_vga(dev);
15529
15530                 /*
15531                  * We need to use raw interfaces for restoring state to avoid
15532                  * checking (bogus) intermediate states.
15533                  */
15534                 for_each_pipe(dev_priv, pipe) {
15535                         struct drm_crtc *crtc =
15536                                 dev_priv->pipe_to_crtc_mapping[pipe];
15537
15538                         intel_crtc_restore_mode(crtc);
15539                 }
15540         } else {
15541                 intel_modeset_update_staged_output_state(dev);
15542         }
15543
15544         intel_modeset_check_state(dev);
15545 }
15546
15547 void intel_modeset_gem_init(struct drm_device *dev)
15548 {
15549         struct drm_i915_private *dev_priv = dev->dev_private;
15550         struct drm_crtc *c;
15551         struct drm_i915_gem_object *obj;
15552         int ret;
15553
15554         mutex_lock(&dev->struct_mutex);
15555         intel_init_gt_powersave(dev);
15556         mutex_unlock(&dev->struct_mutex);
15557
15558         /*
15559          * There may be no VBT; and if the BIOS enabled SSC we can
15560          * just keep using it to avoid unnecessary flicker.  Whereas if the
15561          * BIOS isn't using it, don't assume it will work even if the VBT
15562          * indicates as much.
15563          */
15564         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15565                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15566                                                 DREF_SSC1_ENABLE);
15567
15568         intel_modeset_init_hw(dev);
15569
15570         intel_setup_overlay(dev);
15571
15572         /*
15573          * Make sure any fbs we allocated at startup are properly
15574          * pinned & fenced.  When we do the allocation it's too early
15575          * for this.
15576          */
15577         for_each_crtc(dev, c) {
15578                 obj = intel_fb_obj(c->primary->fb);
15579                 if (obj == NULL)
15580                         continue;
15581
15582                 mutex_lock(&dev->struct_mutex);
15583                 ret = intel_pin_and_fence_fb_obj(c->primary,
15584                                                  c->primary->fb,
15585                                                  c->primary->state,
15586                                                  NULL, NULL);
15587                 mutex_unlock(&dev->struct_mutex);
15588                 if (ret) {
15589                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15590                                   to_intel_crtc(c)->pipe);
15591                         drm_framebuffer_unreference(c->primary->fb);
15592                         c->primary->fb = NULL;
15593                         c->primary->crtc = c->primary->state->crtc = NULL;
15594                         update_state_fb(c->primary);
15595                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15596                 }
15597         }
15598
15599         intel_backlight_register(dev);
15600 }
15601
15602 void intel_connector_unregister(struct intel_connector *intel_connector)
15603 {
15604         struct drm_connector *connector = &intel_connector->base;
15605
15606         intel_panel_destroy_backlight(connector);
15607         drm_connector_unregister(connector);
15608 }
15609
15610 void intel_modeset_cleanup(struct drm_device *dev)
15611 {
15612         struct drm_i915_private *dev_priv = dev->dev_private;
15613         struct drm_connector *connector;
15614
15615         intel_disable_gt_powersave(dev);
15616
15617         intel_backlight_unregister(dev);
15618
15619         /*
15620          * Interrupts and polling as the first thing to avoid creating havoc.
15621          * Too much stuff here (turning of connectors, ...) would
15622          * experience fancy races otherwise.
15623          */
15624         intel_irq_uninstall(dev_priv);
15625
15626         /*
15627          * Due to the hpd irq storm handling the hotplug work can re-arm the
15628          * poll handlers. Hence disable polling after hpd handling is shut down.
15629          */
15630         drm_kms_helper_poll_fini(dev);
15631
15632         intel_unregister_dsm_handler();
15633
15634         intel_fbc_disable(dev_priv);
15635
15636         /* flush any delayed tasks or pending work */
15637         flush_scheduled_work();
15638
15639         /* destroy the backlight and sysfs files before encoders/connectors */
15640         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15641                 struct intel_connector *intel_connector;
15642
15643                 intel_connector = to_intel_connector(connector);
15644                 intel_connector->unregister(intel_connector);
15645         }
15646
15647         drm_mode_config_cleanup(dev);
15648
15649         intel_cleanup_overlay(dev);
15650
15651         mutex_lock(&dev->struct_mutex);
15652         intel_cleanup_gt_powersave(dev);
15653         mutex_unlock(&dev->struct_mutex);
15654 }
15655
15656 /*
15657  * Return which encoder is currently attached for connector.
15658  */
15659 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15660 {
15661         return &intel_attached_encoder(connector)->base;
15662 }
15663
15664 void intel_connector_attach_encoder(struct intel_connector *connector,
15665                                     struct intel_encoder *encoder)
15666 {
15667         connector->encoder = encoder;
15668         drm_mode_connector_attach_encoder(&connector->base,
15669                                           &encoder->base);
15670 }
15671
15672 /*
15673  * set vga decode state - true == enable VGA decode
15674  */
15675 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15676 {
15677         struct drm_i915_private *dev_priv = dev->dev_private;
15678         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15679         u16 gmch_ctrl;
15680
15681         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15682                 DRM_ERROR("failed to read control word\n");
15683                 return -EIO;
15684         }
15685
15686         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15687                 return 0;
15688
15689         if (state)
15690                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15691         else
15692                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15693
15694         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15695                 DRM_ERROR("failed to write control word\n");
15696                 return -EIO;
15697         }
15698
15699         return 0;
15700 }
15701
15702 struct intel_display_error_state {
15703
15704         u32 power_well_driver;
15705
15706         int num_transcoders;
15707
15708         struct intel_cursor_error_state {
15709                 u32 control;
15710                 u32 position;
15711                 u32 base;
15712                 u32 size;
15713         } cursor[I915_MAX_PIPES];
15714
15715         struct intel_pipe_error_state {
15716                 bool power_domain_on;
15717                 u32 source;
15718                 u32 stat;
15719         } pipe[I915_MAX_PIPES];
15720
15721         struct intel_plane_error_state {
15722                 u32 control;
15723                 u32 stride;
15724                 u32 size;
15725                 u32 pos;
15726                 u32 addr;
15727                 u32 surface;
15728                 u32 tile_offset;
15729         } plane[I915_MAX_PIPES];
15730
15731         struct intel_transcoder_error_state {
15732                 bool power_domain_on;
15733                 enum transcoder cpu_transcoder;
15734
15735                 u32 conf;
15736
15737                 u32 htotal;
15738                 u32 hblank;
15739                 u32 hsync;
15740                 u32 vtotal;
15741                 u32 vblank;
15742                 u32 vsync;
15743         } transcoder[4];
15744 };
15745
15746 struct intel_display_error_state *
15747 intel_display_capture_error_state(struct drm_device *dev)
15748 {
15749         struct drm_i915_private *dev_priv = dev->dev_private;
15750         struct intel_display_error_state *error;
15751         int transcoders[] = {
15752                 TRANSCODER_A,
15753                 TRANSCODER_B,
15754                 TRANSCODER_C,
15755                 TRANSCODER_EDP,
15756         };
15757         int i;
15758
15759         if (INTEL_INFO(dev)->num_pipes == 0)
15760                 return NULL;
15761
15762         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15763         if (error == NULL)
15764                 return NULL;
15765
15766         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15767                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15768
15769         for_each_pipe(dev_priv, i) {
15770                 error->pipe[i].power_domain_on =
15771                         __intel_display_power_is_enabled(dev_priv,
15772                                                          POWER_DOMAIN_PIPE(i));
15773                 if (!error->pipe[i].power_domain_on)
15774                         continue;
15775
15776                 error->cursor[i].control = I915_READ(CURCNTR(i));
15777                 error->cursor[i].position = I915_READ(CURPOS(i));
15778                 error->cursor[i].base = I915_READ(CURBASE(i));
15779
15780                 error->plane[i].control = I915_READ(DSPCNTR(i));
15781                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15782                 if (INTEL_INFO(dev)->gen <= 3) {
15783                         error->plane[i].size = I915_READ(DSPSIZE(i));
15784                         error->plane[i].pos = I915_READ(DSPPOS(i));
15785                 }
15786                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15787                         error->plane[i].addr = I915_READ(DSPADDR(i));
15788                 if (INTEL_INFO(dev)->gen >= 4) {
15789                         error->plane[i].surface = I915_READ(DSPSURF(i));
15790                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15791                 }
15792
15793                 error->pipe[i].source = I915_READ(PIPESRC(i));
15794
15795                 if (HAS_GMCH_DISPLAY(dev))
15796                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15797         }
15798
15799         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15800         if (HAS_DDI(dev_priv->dev))
15801                 error->num_transcoders++; /* Account for eDP. */
15802
15803         for (i = 0; i < error->num_transcoders; i++) {
15804                 enum transcoder cpu_transcoder = transcoders[i];
15805
15806                 error->transcoder[i].power_domain_on =
15807                         __intel_display_power_is_enabled(dev_priv,
15808                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15809                 if (!error->transcoder[i].power_domain_on)
15810                         continue;
15811
15812                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15813
15814                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15815                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15816                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15817                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15818                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15819                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15820                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15821         }
15822
15823         return error;
15824 }
15825
15826 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15827
15828 void
15829 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15830                                 struct drm_device *dev,
15831                                 struct intel_display_error_state *error)
15832 {
15833         struct drm_i915_private *dev_priv = dev->dev_private;
15834         int i;
15835
15836         if (!error)
15837                 return;
15838
15839         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15840         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15841                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15842                            error->power_well_driver);
15843         for_each_pipe(dev_priv, i) {
15844                 err_printf(m, "Pipe [%d]:\n", i);
15845                 err_printf(m, "  Power: %s\n",
15846                            error->pipe[i].power_domain_on ? "on" : "off");
15847                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15848                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15849
15850                 err_printf(m, "Plane [%d]:\n", i);
15851                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15852                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15853                 if (INTEL_INFO(dev)->gen <= 3) {
15854                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15855                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15856                 }
15857                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15858                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15859                 if (INTEL_INFO(dev)->gen >= 4) {
15860                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15861                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15862                 }
15863
15864                 err_printf(m, "Cursor [%d]:\n", i);
15865                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15866                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15867                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15868         }
15869
15870         for (i = 0; i < error->num_transcoders; i++) {
15871                 err_printf(m, "CPU transcoder: %c\n",
15872                            transcoder_name(error->transcoder[i].cpu_transcoder));
15873                 err_printf(m, "  Power: %s\n",
15874                            error->transcoder[i].power_domain_on ? "on" : "off");
15875                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15876                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15877                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15878                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15879                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15880                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15881                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15882         }
15883 }
15884
15885 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15886 {
15887         struct intel_crtc *crtc;
15888
15889         for_each_intel_crtc(dev, crtc) {
15890                 struct intel_unpin_work *work;
15891
15892                 spin_lock_irq(&dev->event_lock);
15893
15894                 work = crtc->unpin_work;
15895
15896                 if (work && work->event &&
15897                     work->event->base.file_priv == file) {
15898                         kfree(work->event);
15899                         work->event = NULL;
15900                 }
15901
15902                 spin_unlock_irq(&dev->event_lock);
15903         }
15904 }