drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75         DRM_FORMAT_YUYV,
  76         DRM_FORMAT_YVYU,
  77         DRM_FORMAT_UYVY,
  78         DRM_FORMAT_VYUY,
  79 };
  80
  81 /* Cursor formats */
  82 static const uint32_t intel_cursor_formats[] = {
  83         DRM_FORMAT_ARGB8888,
  84 };
  85
  86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119
 120 typedef struct {
 121         int     min, max;
 122 } intel_range_t;
 123
 124 typedef struct {
 125         int     dot_limit;
 126         int     p2_slow, p2_fast;
 127 } intel_p2_t;
 128
 129 typedef struct intel_limit intel_limit_t;
 130 struct intel_limit {
 131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 132         intel_p2_t          p2;
 133 };
 134
 135 int
 136 intel_pch_rawclk(struct drm_device *dev)
 137 {
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139
 140         WARN_ON(!HAS_PCH_SPLIT(dev));
 141
 142         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 143 }
 144
 145 /* hrawclock is 1/4 the FSB frequency */
 146 int intel_hrawclk(struct drm_device *dev)
 147 {
 148         struct drm_i915_private *dev_priv = dev->dev_private;
 149         uint32_t clkcfg;
 150
 151         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 152         if (IS_VALLEYVIEW(dev))
 153                 return 200;
 154
 155         clkcfg = I915_READ(CLKCFG);
 156         switch (clkcfg & CLKCFG_FSB_MASK) {
 157         case CLKCFG_FSB_400:
 158                 return 100;
 159         case CLKCFG_FSB_533:
 160                 return 133;
 161         case CLKCFG_FSB_667:
 162                 return 166;
 163         case CLKCFG_FSB_800:
 164                 return 200;
 165         case CLKCFG_FSB_1067:
 166                 return 266;
 167         case CLKCFG_FSB_1333:
 168                 return 333;
 169         /* these two are just a guess; one of them might be right */
 170         case CLKCFG_FSB_1600:
 171         case CLKCFG_FSB_1600_ALT:
 172                 return 400;
 173         default:
 174                 return 133;
 175         }
 176 }
 177
 178 static inline u32 /* units of 100MHz */
 179 intel_fdi_link_freq(struct drm_device *dev)
 180 {
 181         if (IS_GEN5(dev)) {
 182                 struct drm_i915_private *dev_priv = dev->dev_private;
 183                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 184         } else
 185                 return 27;
 186 }
 187
 188 static const intel_limit_t intel_limits_i8xx_dac = {
 189         .dot = { .min = 25000, .max = 350000 },
 190         .vco = { .min = 908000, .max = 1512000 },
 191         .n = { .min = 2, .max = 16 },
 192         .m = { .min = 96, .max = 140 },
 193         .m1 = { .min = 18, .max = 26 },
 194         .m2 = { .min = 6, .max = 16 },
 195         .p = { .min = 4, .max = 128 },
 196         .p1 = { .min = 2, .max = 33 },
 197         .p2 = { .dot_limit = 165000,
 198                 .p2_slow = 4, .p2_fast = 2 },
 199 };
 200
 201 static const intel_limit_t intel_limits_i8xx_dvo = {
 202         .dot = { .min = 25000, .max = 350000 },
 203         .vco = { .min = 908000, .max = 1512000 },
 204         .n = { .min = 2, .max = 16 },
 205         .m = { .min = 96, .max = 140 },
 206         .m1 = { .min = 18, .max = 26 },
 207         .m2 = { .min = 6, .max = 16 },
 208         .p = { .min = 4, .max = 128 },
 209         .p1 = { .min = 2, .max = 33 },
 210         .p2 = { .dot_limit = 165000,
 211                 .p2_slow = 4, .p2_fast = 4 },
 212 };
 213
 214 static const intel_limit_t intel_limits_i8xx_lvds = {
 215         .dot = { .min = 25000, .max = 350000 },
 216         .vco = { .min = 908000, .max = 1512000 },
 217         .n = { .min = 2, .max = 16 },
 218         .m = { .min = 96, .max = 140 },
 219         .m1 = { .min = 18, .max = 26 },
 220         .m2 = { .min = 6, .max = 16 },
 221         .p = { .min = 4, .max = 128 },
 222         .p1 = { .min = 1, .max = 6 },
 223         .p2 = { .dot_limit = 165000,
 224                 .p2_slow = 14, .p2_fast = 7 },
 225 };
 226
 227 static const intel_limit_t intel_limits_i9xx_sdvo = {
 228         .dot = { .min = 20000, .max = 400000 },
 229         .vco = { .min = 1400000, .max = 2800000 },
 230         .n = { .min = 1, .max = 6 },
 231         .m = { .min = 70, .max = 120 },
 232         .m1 = { .min = 8, .max = 18 },
 233         .m2 = { .min = 3, .max = 7 },
 234         .p = { .min = 5, .max = 80 },
 235         .p1 = { .min = 1, .max = 8 },
 236         .p2 = { .dot_limit = 200000,
 237                 .p2_slow = 10, .p2_fast = 5 },
 238 };
 239
 240 static const intel_limit_t intel_limits_i9xx_lvds = {
 241         .dot = { .min = 20000, .max = 400000 },
 242         .vco = { .min = 1400000, .max = 2800000 },
 243         .n = { .min = 1, .max = 6 },
 244         .m = { .min = 70, .max = 120 },
 245         .m1 = { .min = 8, .max = 18 },
 246         .m2 = { .min = 3, .max = 7 },
 247         .p = { .min = 7, .max = 98 },
 248         .p1 = { .min = 1, .max = 8 },
 249         .p2 = { .dot_limit = 112000,
 250                 .p2_slow = 14, .p2_fast = 7 },
 251 };
 252
 253
 254 static const intel_limit_t intel_limits_g4x_sdvo = {
 255         .dot = { .min = 25000, .max = 270000 },
 256         .vco = { .min = 1750000, .max = 3500000},
 257         .n = { .min = 1, .max = 4 },
 258         .m = { .min = 104, .max = 138 },
 259         .m1 = { .min = 17, .max = 23 },
 260         .m2 = { .min = 5, .max = 11 },
 261         .p = { .min = 10, .max = 30 },
 262         .p1 = { .min = 1, .max = 3},
 263         .p2 = { .dot_limit = 270000,
 264                 .p2_slow = 10,
 265                 .p2_fast = 10
 266         },
 267 };
 268
 269 static const intel_limit_t intel_limits_g4x_hdmi = {
 270         .dot = { .min = 22000, .max = 400000 },
 271         .vco = { .min = 1750000, .max = 3500000},
 272         .n = { .min = 1, .max = 4 },
 273         .m = { .min = 104, .max = 138 },
 274         .m1 = { .min = 16, .max = 23 },
 275         .m2 = { .min = 5, .max = 11 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8},
 278         .p2 = { .dot_limit = 165000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 283         .dot = { .min = 20000, .max = 115000 },
 284         .vco = { .min = 1750000, .max = 3500000 },
 285         .n = { .min = 1, .max = 3 },
 286         .m = { .min = 104, .max = 138 },
 287         .m1 = { .min = 17, .max = 23 },
 288         .m2 = { .min = 5, .max = 11 },
 289         .p = { .min = 28, .max = 112 },
 290         .p1 = { .min = 2, .max = 8 },
 291         .p2 = { .dot_limit = 0,
 292                 .p2_slow = 14, .p2_fast = 14
 293         },
 294 };
 295
 296 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 297         .dot = { .min = 80000, .max = 224000 },
 298         .vco = { .min = 1750000, .max = 3500000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 104, .max = 138 },
 301         .m1 = { .min = 17, .max = 23 },
 302         .m2 = { .min = 5, .max = 11 },
 303         .p = { .min = 14, .max = 42 },
 304         .p1 = { .min = 2, .max = 6 },
 305         .p2 = { .dot_limit = 0,
 306                 .p2_slow = 7, .p2_fast = 7
 307         },
 308 };
 309
 310 static const intel_limit_t intel_limits_pineview_sdvo = {
 311         .dot = { .min = 20000, .max = 400000},
 312         .vco = { .min = 1700000, .max = 3500000 },
 313         /* Pineview's Ncounter is a ring counter */
 314         .n = { .min = 3, .max = 6 },
 315         .m = { .min = 2, .max = 256 },
 316         /* Pineview only has one combined m divider, which we treat as m2. */
 317         .m1 = { .min = 0, .max = 0 },
 318         .m2 = { .min = 0, .max = 254 },
 319         .p = { .min = 5, .max = 80 },
 320         .p1 = { .min = 1, .max = 8 },
 321         .p2 = { .dot_limit = 200000,
 322                 .p2_slow = 10, .p2_fast = 5 },
 323 };
 324
 325 static const intel_limit_t intel_limits_pineview_lvds = {
 326         .dot = { .min = 20000, .max = 400000 },
 327         .vco = { .min = 1700000, .max = 3500000 },
 328         .n = { .min = 3, .max = 6 },
 329         .m = { .min = 2, .max = 256 },
 330         .m1 = { .min = 0, .max = 0 },
 331         .m2 = { .min = 0, .max = 254 },
 332         .p = { .min = 7, .max = 112 },
 333         .p1 = { .min = 1, .max = 8 },
 334         .p2 = { .dot_limit = 112000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336 };
 337
 338 /* Ironlake / Sandybridge
 339  *
 340  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 341  * the range value for them is (actual_value - 2).
 342  */
 343 static const intel_limit_t intel_limits_ironlake_dac = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 5 },
 347         .m = { .min = 79, .max = 127 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 5, .max = 80 },
 351         .p1 = { .min = 1, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 10, .p2_fast = 5 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 118 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 28, .max = 112 },
 364         .p1 = { .min = 2, .max = 8 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 14, .p2_fast = 14 },
 367 };
 368
 369 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 370         .dot = { .min = 25000, .max = 350000 },
 371         .vco = { .min = 1760000, .max = 3510000 },
 372         .n = { .min = 1, .max = 3 },
 373         .m = { .min = 79, .max = 127 },
 374         .m1 = { .min = 12, .max = 22 },
 375         .m2 = { .min = 5, .max = 9 },
 376         .p = { .min = 14, .max = 56 },
 377         .p1 = { .min = 2, .max = 8 },
 378         .p2 = { .dot_limit = 225000,
 379                 .p2_slow = 7, .p2_fast = 7 },
 380 };
 381
 382 /* LVDS 100mhz refclk limits. */
 383 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 384         .dot = { .min = 25000, .max = 350000 },
 385         .vco = { .min = 1760000, .max = 3510000 },
 386         .n = { .min = 1, .max = 2 },
 387         .m = { .min = 79, .max = 126 },
 388         .m1 = { .min = 12, .max = 22 },
 389         .m2 = { .min = 5, .max = 9 },
 390         .p = { .min = 28, .max = 112 },
 391         .p1 = { .min = 2, .max = 8 },
 392         .p2 = { .dot_limit = 225000,
 393                 .p2_slow = 14, .p2_fast = 14 },
 394 };
 395
 396 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 397         .dot = { .min = 25000, .max = 350000 },
 398         .vco = { .min = 1760000, .max = 3510000 },
 399         .n = { .min = 1, .max = 3 },
 400         .m = { .min = 79, .max = 126 },
 401         .m1 = { .min = 12, .max = 22 },
 402         .m2 = { .min = 5, .max = 9 },
 403         .p = { .min = 14, .max = 42 },
 404         .p1 = { .min = 2, .max = 6 },
 405         .p2 = { .dot_limit = 225000,
 406                 .p2_slow = 7, .p2_fast = 7 },
 407 };
 408
 409 static const intel_limit_t intel_limits_vlv = {
 410          /*
 411           * These are the data rate limits (measured in fast clocks)
 412           * since those are the strictest limits we have. The fast
 413           * clock and actual rate limits are more relaxed, so checking
 414           * them would make no difference.
 415           */
 416         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 417         .vco = { .min = 4000000, .max = 6000000 },
 418         .n = { .min = 1, .max = 7 },
 419         .m1 = { .min = 2, .max = 3 },
 420         .m2 = { .min = 11, .max = 156 },
 421         .p1 = { .min = 2, .max = 3 },
 422         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 423 };
 424
 425 static const intel_limit_t intel_limits_chv = {
 426         /*
 427          * These are the data rate limits (measured in fast clocks)
 428          * since those are the strictest limits we have.  The fast
 429          * clock and actual rate limits are more relaxed, so checking
 430          * them would make no difference.
 431          */
 432         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 433         .vco = { .min = 4800000, .max = 6480000 },
 434         .n = { .min = 1, .max = 1 },
 435         .m1 = { .min = 2, .max = 2 },
 436         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 437         .p1 = { .min = 2, .max = 4 },
 438         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 439 };
 440
 441 static const intel_limit_t intel_limits_bxt = {
 442         /* FIXME: find real dot limits */
 443         .dot = { .min = 0, .max = INT_MAX },
 444         .vco = { .min = 4800000, .max = 6700000 },
 445         .n = { .min = 1, .max = 1 },
 446         .m1 = { .min = 2, .max = 2 },
 447         /* FIXME: find real m2 limits */
 448         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 449         .p1 = { .min = 2, .max = 4 },
 450         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 451 };
 452
 453 static bool
 454 needs_modeset(struct drm_crtc_state *state)
 455 {
 456         return drm_atomic_crtc_needs_modeset(state);
 457 }
 458
 459 /**
 460  * Returns whether any output on the specified pipe is of the specified type
 461  */
 462 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 463 {
 464         struct drm_device *dev = crtc->base.dev;
 465         struct intel_encoder *encoder;
 466
 467         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 468                 if (encoder->type == type)
 469                         return true;
 470
 471         return false;
 472 }
 473
 474 /**
 475  * Returns whether any output on the specified pipe will have the specified
 476  * type after a staged modeset is complete, i.e., the same as
 477  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 478  * encoder->crtc.
 479  */
 480 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 481                                       int type)
 482 {
 483         struct drm_atomic_state *state = crtc_state->base.state;
 484         struct drm_connector *connector;
 485         struct drm_connector_state *connector_state;
 486         struct intel_encoder *encoder;
 487         int i, num_connectors = 0;
 488
 489         for_each_connector_in_state(state, connector, connector_state, i) {
 490                 if (connector_state->crtc != crtc_state->base.crtc)
 491                         continue;
 492
 493                 num_connectors++;
 494
 495                 encoder = to_intel_encoder(connector_state->best_encoder);
 496                 if (encoder->type == type)
 497                         return true;
 498         }
 499
 500         WARN_ON(num_connectors == 0);
 501
 502         return false;
 503 }
 504
 505 static const intel_limit_t *
 506 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 507 {
 508         struct drm_device *dev = crtc_state->base.crtc->dev;
 509         const intel_limit_t *limit;
 510
 511         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 512                 if (intel_is_dual_link_lvds(dev)) {
 513                         if (refclk == 100000)
 514                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 515                         else
 516                                 limit = &intel_limits_ironlake_dual_lvds;
 517                 } else {
 518                         if (refclk == 100000)
 519                                 limit = &intel_limits_ironlake_single_lvds_100m;
 520                         else
 521                                 limit = &intel_limits_ironlake_single_lvds;
 522                 }
 523         } else
 524                 limit = &intel_limits_ironlake_dac;
 525
 526         return limit;
 527 }
 528
 529 static const intel_limit_t *
 530 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 531 {
 532         struct drm_device *dev = crtc_state->base.crtc->dev;
 533         const intel_limit_t *limit;
 534
 535         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 536                 if (intel_is_dual_link_lvds(dev))
 537                         limit = &intel_limits_g4x_dual_channel_lvds;
 538                 else
 539                         limit = &intel_limits_g4x_single_channel_lvds;
 540         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 541                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 542                 limit = &intel_limits_g4x_hdmi;
 543         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 544                 limit = &intel_limits_g4x_sdvo;
 545         } else /* The option is for other outputs */
 546                 limit = &intel_limits_i9xx_sdvo;
 547
 548         return limit;
 549 }
 550
 551 static const intel_limit_t *
 552 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 553 {
 554         struct drm_device *dev = crtc_state->base.crtc->dev;
 555         const intel_limit_t *limit;
 556
 557         if (IS_BROXTON(dev))
 558                 limit = &intel_limits_bxt;
 559         else if (HAS_PCH_SPLIT(dev))
 560                 limit = intel_ironlake_limit(crtc_state, refclk);
 561         else if (IS_G4X(dev)) {
 562                 limit = intel_g4x_limit(crtc_state);
 563         } else if (IS_PINEVIEW(dev)) {
 564                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 565                         limit = &intel_limits_pineview_lvds;
 566                 else
 567                         limit = &intel_limits_pineview_sdvo;
 568         } else if (IS_CHERRYVIEW(dev)) {
 569                 limit = &intel_limits_chv;
 570         } else if (IS_VALLEYVIEW(dev)) {
 571                 limit = &intel_limits_vlv;
 572         } else if (!IS_GEN2(dev)) {
 573                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 574                         limit = &intel_limits_i9xx_lvds;
 575                 else
 576                         limit = &intel_limits_i9xx_sdvo;
 577         } else {
 578                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_i8xx_lvds;
 580                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 581                         limit = &intel_limits_i8xx_dvo;
 582                 else
 583                         limit = &intel_limits_i8xx_dac;
 584         }
 585         return limit;
 586 }
 587
 588 /*
 589  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 590  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 591  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 592  * The helpers' return value is the rate of the clock that is fed to the
 593  * display engine's pipe which can be the above fast dot clock rate or a
 594  * divided-down version of it.
 595  */
 596 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 597 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 598 {
 599         clock->m = clock->m2 + 2;
 600         clock->p = clock->p1 * clock->p2;
 601         if (WARN_ON(clock->n == 0 || clock->p == 0))
 602                 return 0;
 603         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 604         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 605
 606         return clock->dot;
 607 }
 608
 609 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 610 {
 611         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 612 }
 613
 614 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = i9xx_dpll_compute_m(clock);
 617         clock->p = clock->p1 * clock->p2;
 618         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 619                 return 0;
 620         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 621         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 622
 623         return clock->dot;
 624 }
 625
 626 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 627 {
 628         clock->m = clock->m1 * clock->m2;
 629         clock->p = clock->p1 * clock->p2;
 630         if (WARN_ON(clock->n == 0 || clock->p == 0))
 631                 return 0;
 632         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 633         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 634
 635         return clock->dot / 5;
 636 }
 637
 638 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 639 {
 640         clock->m = clock->m1 * clock->m2;
 641         clock->p = clock->p1 * clock->p2;
 642         if (WARN_ON(clock->n == 0 || clock->p == 0))
 643                 return 0;
 644         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 645                         clock->n << 22);
 646         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 647
 648         return clock->dot / 5;
 649 }
 650
 651 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 652 /**
 653  * Returns whether the given set of divisors are valid for a given refclk with
 654  * the given connectors.
 655  */
 656
 657 static bool intel_PLL_is_valid(struct drm_device *dev,
 658                                const intel_limit_t *limit,
 659                                const intel_clock_t *clock)
 660 {
 661         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 662                 INTELPllInvalid("n out of range\n");
 663         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 664                 INTELPllInvalid("p1 out of range\n");
 665         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 666                 INTELPllInvalid("m2 out of range\n");
 667         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 668                 INTELPllInvalid("m1 out of range\n");
 669
 670         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 671                 if (clock->m1 <= clock->m2)
 672                         INTELPllInvalid("m1 <= m2\n");
 673
 674         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 675                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 676                         INTELPllInvalid("p out of range\n");
 677                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 678                         INTELPllInvalid("m out of range\n");
 679         }
 680
 681         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 682                 INTELPllInvalid("vco out of range\n");
 683         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 684          * connector, etc., rather than just a single range.
 685          */
 686         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 687                 INTELPllInvalid("dot out of range\n");
 688
 689         return true;
 690 }
 691
 692 static int
 693 i9xx_select_p2_div(const intel_limit_t *limit,
 694                    const struct intel_crtc_state *crtc_state,
 695                    int target)
 696 {
 697         struct drm_device *dev = crtc_state->base.crtc->dev;
 698
 699         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 700                 /*
 701                  * For LVDS just rely on its current settings for dual-channel.
 702                  * We haven't figured out how to reliably set up different
 703                  * single/dual channel state, if we even can.
 704                  */
 705                 if (intel_is_dual_link_lvds(dev))
 706                         return limit->p2.p2_fast;
 707                 else
 708                         return limit->p2.p2_slow;
 709         } else {
 710                 if (target < limit->p2.dot_limit)
 711                         return limit->p2.p2_slow;
 712                 else
 713                         return limit->p2.p2_fast;
 714         }
 715 }
 716
 717 static bool
 718 i9xx_find_best_dpll(const intel_limit_t *limit,
 719                     struct intel_crtc_state *crtc_state,
 720                     int target, int refclk, intel_clock_t *match_clock,
 721                     intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc_state->base.crtc->dev;
 724         intel_clock_t clock;
 725         int err = target;
 726
 727         memset(best_clock, 0, sizeof(*best_clock));
 728
 729         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 730
 731         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 732              clock.m1++) {
 733                 for (clock.m2 = limit->m2.min;
 734                      clock.m2 <= limit->m2.max; clock.m2++) {
 735                         if (clock.m2 >= clock.m1)
 736                                 break;
 737                         for (clock.n = limit->n.min;
 738                              clock.n <= limit->n.max; clock.n++) {
 739                                 for (clock.p1 = limit->p1.min;
 740                                         clock.p1 <= limit->p1.max; clock.p1++) {
 741                                         int this_err;
 742
 743                                         i9xx_calc_dpll_params(refclk, &clock);
 744                                         if (!intel_PLL_is_valid(dev, limit,
 745                                                                 &clock))
 746                                                 continue;
 747                                         if (match_clock &&
 748                                             clock.p != match_clock->p)
 749                                                 continue;
 750
 751                                         this_err = abs(clock.dot - target);
 752                                         if (this_err < err) {
 753                                                 *best_clock = clock;
 754                                                 err = this_err;
 755                                         }
 756                                 }
 757                         }
 758                 }
 759         }
 760
 761         return (err != target);
 762 }
 763
 764 static bool
 765 pnv_find_best_dpll(const intel_limit_t *limit,
 766                    struct intel_crtc_state *crtc_state,
 767                    int target, int refclk, intel_clock_t *match_clock,
 768                    intel_clock_t *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->base.crtc->dev;
 771         intel_clock_t clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         for (clock.n = limit->n.min;
 783                              clock.n <= limit->n.max; clock.n++) {
 784                                 for (clock.p1 = limit->p1.min;
 785                                         clock.p1 <= limit->p1.max; clock.p1++) {
 786                                         int this_err;
 787
 788                                         pnv_calc_dpll_params(refclk, &clock);
 789                                         if (!intel_PLL_is_valid(dev, limit,
 790                                                                 &clock))
 791                                                 continue;
 792                                         if (match_clock &&
 793                                             clock.p != match_clock->p)
 794                                                 continue;
 795
 796                                         this_err = abs(clock.dot - target);
 797                                         if (this_err < err) {
 798                                                 *best_clock = clock;
 799                                                 err = this_err;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805
 806         return (err != target);
 807 }
 808
 809 static bool
 810 g4x_find_best_dpll(const intel_limit_t *limit,
 811                    struct intel_crtc_state *crtc_state,
 812                    int target, int refclk, intel_clock_t *match_clock,
 813                    intel_clock_t *best_clock)
 814 {
 815         struct drm_device *dev = crtc_state->base.crtc->dev;
 816         intel_clock_t clock;
 817         int max_n;
 818         bool found = false;
 819         /* approximately equals target * 0.00585 */
 820         int err_most = (target >> 8) + (target >> 9);
 821
 822         memset(best_clock, 0, sizeof(*best_clock));
 823
 824         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 825
 826         max_n = limit->n.max;
 827         /* based on hardware requirement, prefer smaller n to precision */
 828         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 829                 /* based on hardware requirement, prefere larger m1,m2 */
 830                 for (clock.m1 = limit->m1.max;
 831                      clock.m1 >= limit->m1.min; clock.m1--) {
 832                         for (clock.m2 = limit->m2.max;
 833                              clock.m2 >= limit->m2.min; clock.m2--) {
 834                                 for (clock.p1 = limit->p1.max;
 835                                      clock.p1 >= limit->p1.min; clock.p1--) {
 836                                         int this_err;
 837
 838                                         i9xx_calc_dpll_params(refclk, &clock);
 839                                         if (!intel_PLL_is_valid(dev, limit,
 840                                                                 &clock))
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err_most) {
 845                                                 *best_clock = clock;
 846                                                 err_most = this_err;
 847                                                 max_n = clock.n;
 848                                                 found = true;
 849                                         }
 850                                 }
 851                         }
 852                 }
 853         }
 854         return found;
 855 }
 856
 857 /*
 858  * Check if the calculated PLL configuration is more optimal compared to the
 859  * best configuration and error found so far. Return the calculated error.
 860  */
 861 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 862                                const intel_clock_t *calculated_clock,
 863                                const intel_clock_t *best_clock,
 864                                unsigned int best_error_ppm,
 865                                unsigned int *error_ppm)
 866 {
 867         /*
 868          * For CHV ignore the error and consider only the P value.
 869          * Prefer a bigger P value based on HW requirements.
 870          */
 871         if (IS_CHERRYVIEW(dev)) {
 872                 *error_ppm = 0;
 873
 874                 return calculated_clock->p > best_clock->p;
 875         }
 876
 877         if (WARN_ON_ONCE(!target_freq))
 878                 return false;
 879
 880         *error_ppm = div_u64(1000000ULL *
 881                                 abs(target_freq - calculated_clock->dot),
 882                              target_freq);
 883         /*
 884          * Prefer a better P value over a better (smaller) error if the error
 885          * is small. Ensure this preference for future configurations too by
 886          * setting the error to 0.
 887          */
 888         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 889                 *error_ppm = 0;
 890
 891                 return true;
 892         }
 893
 894         return *error_ppm + 10 < best_error_ppm;
 895 }
 896
 897 static bool
 898 vlv_find_best_dpll(const intel_limit_t *limit,
 899                    struct intel_crtc_state *crtc_state,
 900                    int target, int refclk, intel_clock_t *match_clock,
 901                    intel_clock_t *best_clock)
 902 {
 903         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 904         struct drm_device *dev = crtc->base.dev;
 905         intel_clock_t clock;
 906         unsigned int bestppm = 1000000;
 907         /* min update 19.2 MHz */
 908         int max_n = min(limit->n.max, refclk / 19200);
 909         bool found = false;
 910
 911         target *= 5; /* fast clock */
 912
 913         memset(best_clock, 0, sizeof(*best_clock));
 914
 915         /* based on hardware requirement, prefer smaller n to precision */
 916         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 917                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 918                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 919                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 920                                 clock.p = clock.p1 * clock.p2;
 921                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 922                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 923                                         unsigned int ppm;
 924
 925                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 926                                                                      refclk * clock.m1);
 927
 928                                         vlv_calc_dpll_params(refclk, &clock);
 929
 930                                         if (!intel_PLL_is_valid(dev, limit,
 931                                                                 &clock))
 932                                                 continue;
 933
 934                                         if (!vlv_PLL_is_optimal(dev, target,
 935                                                                 &clock,
 936                                                                 best_clock,
 937                                                                 bestppm, &ppm))
 938                                                 continue;
 939
 940                                         *best_clock = clock;
 941                                         bestppm = ppm;
 942                                         found = true;
 943                                 }
 944                         }
 945                 }
 946         }
 947
 948         return found;
 949 }
 950
 951 static bool
 952 chv_find_best_dpll(const intel_limit_t *limit,
 953                    struct intel_crtc_state *crtc_state,
 954                    int target, int refclk, intel_clock_t *match_clock,
 955                    intel_clock_t *best_clock)
 956 {
 957         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 958         struct drm_device *dev = crtc->base.dev;
 959         unsigned int best_error_ppm;
 960         intel_clock_t clock;
 961         uint64_t m2;
 962         int found = false;
 963
 964         memset(best_clock, 0, sizeof(*best_clock));
 965         best_error_ppm = 1000000;
 966
 967         /*
 968          * Based on hardware doc, the n always set to 1, and m1 always
 969          * set to 2.  If requires to support 200Mhz refclk, we need to
 970          * revisit this because n may not 1 anymore.
 971          */
 972         clock.n = 1, clock.m1 = 2;
 973         target *= 5;    /* fast clock */
 974
 975         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 976                 for (clock.p2 = limit->p2.p2_fast;
 977                                 clock.p2 >= limit->p2.p2_slow;
 978                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 979                         unsigned int error_ppm;
 980
 981                         clock.p = clock.p1 * clock.p2;
 982
 983                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 984                                         clock.n) << 22, refclk * clock.m1);
 985
 986                         if (m2 > INT_MAX/clock.m1)
 987                                 continue;
 988
 989                         clock.m2 = m2;
 990
 991                         chv_calc_dpll_params(refclk, &clock);
 992
 993                         if (!intel_PLL_is_valid(dev, limit, &clock))
 994                                 continue;
 995
 996                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 997                                                 best_error_ppm, &error_ppm))
 998                                 continue;
 999
1000                         *best_clock = clock;
1001                         best_error_ppm = error_ppm;
1002                         found = true;
1003                 }
1004         }
1005
1006         return found;
1007 }
1008
1009 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1010                         intel_clock_t *best_clock)
1011 {
1012         int refclk = i9xx_get_refclk(crtc_state, 0);
1013
1014         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1015                                   target_clock, refclk, NULL, best_clock);
1016 }
1017
1018 bool intel_crtc_active(struct drm_crtc *crtc)
1019 {
1020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1021
1022         /* Be paranoid as we can arrive here with only partial
1023          * state retrieved from the hardware during setup.
1024          *
1025          * We can ditch the adjusted_mode.crtc_clock check as soon
1026          * as Haswell has gained clock readout/fastboot support.
1027          *
1028          * We can ditch the crtc->primary->fb check as soon as we can
1029          * properly reconstruct framebuffers.
1030          *
1031          * FIXME: The intel_crtc->active here should be switched to
1032          * crtc->state->active once we have proper CRTC states wired up
1033          * for atomic.
1034          */
1035         return intel_crtc->active && crtc->primary->state->fb &&
1036                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1037 }
1038
1039 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1040                                              enum pipe pipe)
1041 {
1042         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1043         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1044
1045         return intel_crtc->config->cpu_transcoder;
1046 }
1047
1048 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1049 {
1050         struct drm_i915_private *dev_priv = dev->dev_private;
1051         u32 reg = PIPEDSL(pipe);
1052         u32 line1, line2;
1053         u32 line_mask;
1054
1055         if (IS_GEN2(dev))
1056                 line_mask = DSL_LINEMASK_GEN2;
1057         else
1058                 line_mask = DSL_LINEMASK_GEN3;
1059
1060         line1 = I915_READ(reg) & line_mask;
1061         msleep(5);
1062         line2 = I915_READ(reg) & line_mask;
1063
1064         return line1 == line2;
1065 }
1066
1067 /*
1068  * intel_wait_for_pipe_off - wait for pipe to turn off
1069  * @crtc: crtc whose pipe to wait for
1070  *
1071  * After disabling a pipe, we can't wait for vblank in the usual way,
1072  * spinning on the vblank interrupt status bit, since we won't actually
1073  * see an interrupt when the pipe is disabled.
1074  *
1075  * On Gen4 and above:
1076  *   wait for the pipe register state bit to turn off
1077  *
1078  * Otherwise:
1079  *   wait for the display line value to settle (it usually
1080  *   ends up stopping at the start of the next frame).
1081  *
1082  */
1083 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1084 {
1085         struct drm_device *dev = crtc->base.dev;
1086         struct drm_i915_private *dev_priv = dev->dev_private;
1087         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1088         enum pipe pipe = crtc->pipe;
1089
1090         if (INTEL_INFO(dev)->gen >= 4) {
1091                 int reg = PIPECONF(cpu_transcoder);
1092
1093                 /* Wait for the Pipe State to go off */
1094                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1095                              100))
1096                         WARN(1, "pipe_off wait timed out\n");
1097         } else {
1098                 /* Wait for the display line to settle */
1099                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1100                         WARN(1, "pipe_off wait timed out\n");
1101         }
1102 }
1103
1104 static const char *state_string(bool enabled)
1105 {
1106         return enabled ? "on" : "off";
1107 }
1108
1109 /* Only for pre-ILK configs */
1110 void assert_pll(struct drm_i915_private *dev_priv,
1111                 enum pipe pipe, bool state)
1112 {
1113         int reg;
1114         u32 val;
1115         bool cur_state;
1116
1117         reg = DPLL(pipe);
1118         val = I915_READ(reg);
1119         cur_state = !!(val & DPLL_VCO_ENABLE);
1120         I915_STATE_WARN(cur_state != state,
1121              "PLL state assertion failure (expected %s, current %s)\n",
1122              state_string(state), state_string(cur_state));
1123 }
1124
1125 /* XXX: the dsi pll is shared between MIPI DSI ports */
1126 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1127 {
1128         u32 val;
1129         bool cur_state;
1130
1131         mutex_lock(&dev_priv->sb_lock);
1132         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1133         mutex_unlock(&dev_priv->sb_lock);
1134
1135         cur_state = val & DSI_PLL_VCO_EN;
1136         I915_STATE_WARN(cur_state != state,
1137              "DSI PLL state assertion failure (expected %s, current %s)\n",
1138              state_string(state), state_string(cur_state));
1139 }
1140 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1141 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1142
1143 struct intel_shared_dpll *
1144 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1145 {
1146         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1147
1148         if (crtc->config->shared_dpll < 0)
1149                 return NULL;
1150
1151         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1152 }
1153
1154 /* For ILK+ */
1155 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1156                         struct intel_shared_dpll *pll,
1157                         bool state)
1158 {
1159         bool cur_state;
1160         struct intel_dpll_hw_state hw_state;
1161
1162         if (WARN (!pll,
1163                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1164                 return;
1165
1166         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1167         I915_STATE_WARN(cur_state != state,
1168              "%s assertion failure (expected %s, current %s)\n",
1169              pll->name, state_string(state), state_string(cur_state));
1170 }
1171
1172 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1173                           enum pipe pipe, bool state)
1174 {
1175         int reg;
1176         u32 val;
1177         bool cur_state;
1178         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1179                                                                       pipe);
1180
1181         if (HAS_DDI(dev_priv->dev)) {
1182                 /* DDI does not have a specific FDI_TX register */
1183                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1184                 val = I915_READ(reg);
1185                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1186         } else {
1187                 reg = FDI_TX_CTL(pipe);
1188                 val = I915_READ(reg);
1189                 cur_state = !!(val & FDI_TX_ENABLE);
1190         }
1191         I915_STATE_WARN(cur_state != state,
1192              "FDI TX state assertion failure (expected %s, current %s)\n",
1193              state_string(state), state_string(cur_state));
1194 }
1195 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1196 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1197
1198 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         int reg;
1202         u32 val;
1203         bool cur_state;
1204
1205         reg = FDI_RX_CTL(pipe);
1206         val = I915_READ(reg);
1207         cur_state = !!(val & FDI_RX_ENABLE);
1208         I915_STATE_WARN(cur_state != state,
1209              "FDI RX state assertion failure (expected %s, current %s)\n",
1210              state_string(state), state_string(cur_state));
1211 }
1212 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1213 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1214
1215 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1216                                       enum pipe pipe)
1217 {
1218         int reg;
1219         u32 val;
1220
1221         /* ILK FDI PLL is always enabled */
1222         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1223                 return;
1224
1225         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1226         if (HAS_DDI(dev_priv->dev))
1227                 return;
1228
1229         reg = FDI_TX_CTL(pipe);
1230         val = I915_READ(reg);
1231         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1232 }
1233
1234 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1235                        enum pipe pipe, bool state)
1236 {
1237         int reg;
1238         u32 val;
1239         bool cur_state;
1240
1241         reg = FDI_RX_CTL(pipe);
1242         val = I915_READ(reg);
1243         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1244         I915_STATE_WARN(cur_state != state,
1245              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1246              state_string(state), state_string(cur_state));
1247 }
1248
1249 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1250                            enum pipe pipe)
1251 {
1252         struct drm_device *dev = dev_priv->dev;
1253         int pp_reg;
1254         u32 val;
1255         enum pipe panel_pipe = PIPE_A;
1256         bool locked = true;
1257
1258         if (WARN_ON(HAS_DDI(dev)))
1259                 return;
1260
1261         if (HAS_PCH_SPLIT(dev)) {
1262                 u32 port_sel;
1263
1264                 pp_reg = PCH_PP_CONTROL;
1265                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1266
1267                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1268                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1269                         panel_pipe = PIPE_B;
1270                 /* XXX: else fix for eDP */
1271         } else if (IS_VALLEYVIEW(dev)) {
1272                 /* presumably write lock depends on pipe, not port select */
1273                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1274                 panel_pipe = pipe;
1275         } else {
1276                 pp_reg = PP_CONTROL;
1277                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1278                         panel_pipe = PIPE_B;
1279         }
1280
1281         val = I915_READ(pp_reg);
1282         if (!(val & PANEL_POWER_ON) ||
1283             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1284                 locked = false;
1285
1286         I915_STATE_WARN(panel_pipe == pipe && locked,
1287              "panel assertion failure, pipe %c regs locked\n",
1288              pipe_name(pipe));
1289 }
1290
1291 static void assert_cursor(struct drm_i915_private *dev_priv,
1292                           enum pipe pipe, bool state)
1293 {
1294         struct drm_device *dev = dev_priv->dev;
1295         bool cur_state;
1296
1297         if (IS_845G(dev) || IS_I865G(dev))
1298                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1299         else
1300                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1301
1302         I915_STATE_WARN(cur_state != state,
1303              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1304              pipe_name(pipe), state_string(state), state_string(cur_state));
1305 }
1306 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1307 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1308
1309 void assert_pipe(struct drm_i915_private *dev_priv,
1310                  enum pipe pipe, bool state)
1311 {
1312         int reg;
1313         u32 val;
1314         bool cur_state;
1315         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1316                                                                       pipe);
1317
1318         /* if we need the pipe quirk it must be always on */
1319         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1320             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1321                 state = true;
1322
1323         if (!intel_display_power_is_enabled(dev_priv,
1324                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1325                 cur_state = false;
1326         } else {
1327                 reg = PIPECONF(cpu_transcoder);
1328                 val = I915_READ(reg);
1329                 cur_state = !!(val & PIPECONF_ENABLE);
1330         }
1331
1332         I915_STATE_WARN(cur_state != state,
1333              "pipe %c assertion failure (expected %s, current %s)\n",
1334              pipe_name(pipe), state_string(state), state_string(cur_state));
1335 }
1336
1337 static void assert_plane(struct drm_i915_private *dev_priv,
1338                          enum plane plane, bool state)
1339 {
1340         int reg;
1341         u32 val;
1342         bool cur_state;
1343
1344         reg = DSPCNTR(plane);
1345         val = I915_READ(reg);
1346         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1347         I915_STATE_WARN(cur_state != state,
1348              "plane %c assertion failure (expected %s, current %s)\n",
1349              plane_name(plane), state_string(state), state_string(cur_state));
1350 }
1351
1352 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1353 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1354
1355 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1356                                    enum pipe pipe)
1357 {
1358         struct drm_device *dev = dev_priv->dev;
1359         int reg, i;
1360         u32 val;
1361         int cur_pipe;
1362
1363         /* Primary planes are fixed to pipes on gen4+ */
1364         if (INTEL_INFO(dev)->gen >= 4) {
1365                 reg = DSPCNTR(pipe);
1366                 val = I915_READ(reg);
1367                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1368                      "plane %c assertion failure, should be disabled but not\n",
1369                      plane_name(pipe));
1370                 return;
1371         }
1372
1373         /* Need to check both planes against the pipe */
1374         for_each_pipe(dev_priv, i) {
1375                 reg = DSPCNTR(i);
1376                 val = I915_READ(reg);
1377                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1378                         DISPPLANE_SEL_PIPE_SHIFT;
1379                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1380                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1381                      plane_name(i), pipe_name(pipe));
1382         }
1383 }
1384
1385 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1386                                     enum pipe pipe)
1387 {
1388         struct drm_device *dev = dev_priv->dev;
1389         int reg, sprite;
1390         u32 val;
1391
1392         if (INTEL_INFO(dev)->gen >= 9) {
1393                 for_each_sprite(dev_priv, pipe, sprite) {
1394                         val = I915_READ(PLANE_CTL(pipe, sprite));
1395                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1396                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1397                              sprite, pipe_name(pipe));
1398                 }
1399         } else if (IS_VALLEYVIEW(dev)) {
1400                 for_each_sprite(dev_priv, pipe, sprite) {
1401                         reg = SPCNTR(pipe, sprite);
1402                         val = I915_READ(reg);
1403                         I915_STATE_WARN(val & SP_ENABLE,
1404                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1405                              sprite_name(pipe, sprite), pipe_name(pipe));
1406                 }
1407         } else if (INTEL_INFO(dev)->gen >= 7) {
1408                 reg = SPRCTL(pipe);
1409                 val = I915_READ(reg);
1410                 I915_STATE_WARN(val & SPRITE_ENABLE,
1411                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1412                      plane_name(pipe), pipe_name(pipe));
1413         } else if (INTEL_INFO(dev)->gen >= 5) {
1414                 reg = DVSCNTR(pipe);
1415                 val = I915_READ(reg);
1416                 I915_STATE_WARN(val & DVS_ENABLE,
1417                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1418                      plane_name(pipe), pipe_name(pipe));
1419         }
1420 }
1421
1422 static void assert_vblank_disabled(struct drm_crtc *crtc)
1423 {
1424         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1425                 drm_crtc_vblank_put(crtc);
1426 }
1427
1428 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1429 {
1430         u32 val;
1431         bool enabled;
1432
1433         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1434
1435         val = I915_READ(PCH_DREF_CONTROL);
1436         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1437                             DREF_SUPERSPREAD_SOURCE_MASK));
1438         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1439 }
1440
1441 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1442                                            enum pipe pipe)
1443 {
1444         int reg;
1445         u32 val;
1446         bool enabled;
1447
1448         reg = PCH_TRANSCONF(pipe);
1449         val = I915_READ(reg);
1450         enabled = !!(val & TRANS_ENABLE);
1451         I915_STATE_WARN(enabled,
1452              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1453              pipe_name(pipe));
1454 }
1455
1456 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1457                             enum pipe pipe, u32 port_sel, u32 val)
1458 {
1459         if ((val & DP_PORT_EN) == 0)
1460                 return false;
1461
1462         if (HAS_PCH_CPT(dev_priv->dev)) {
1463                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1464                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1465                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1466                         return false;
1467         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1468                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1469                         return false;
1470         } else {
1471                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1472                         return false;
1473         }
1474         return true;
1475 }
1476
1477 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1478                               enum pipe pipe, u32 val)
1479 {
1480         if ((val & SDVO_ENABLE) == 0)
1481                 return false;
1482
1483         if (HAS_PCH_CPT(dev_priv->dev)) {
1484                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1485                         return false;
1486         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1487                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1488                         return false;
1489         } else {
1490                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1491                         return false;
1492         }
1493         return true;
1494 }
1495
1496 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1497                               enum pipe pipe, u32 val)
1498 {
1499         if ((val & LVDS_PORT_EN) == 0)
1500                 return false;
1501
1502         if (HAS_PCH_CPT(dev_priv->dev)) {
1503                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1504                         return false;
1505         } else {
1506                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1507                         return false;
1508         }
1509         return true;
1510 }
1511
1512 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1513                               enum pipe pipe, u32 val)
1514 {
1515         if ((val & ADPA_DAC_ENABLE) == 0)
1516                 return false;
1517         if (HAS_PCH_CPT(dev_priv->dev)) {
1518                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1519                         return false;
1520         } else {
1521                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1522                         return false;
1523         }
1524         return true;
1525 }
1526
1527 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1528                                    enum pipe pipe, int reg, u32 port_sel)
1529 {
1530         u32 val = I915_READ(reg);
1531         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1532              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1533              reg, pipe_name(pipe));
1534
1535         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1536              && (val & DP_PIPEB_SELECT),
1537              "IBX PCH dp port still using transcoder B\n");
1538 }
1539
1540 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1541                                      enum pipe pipe, int reg)
1542 {
1543         u32 val = I915_READ(reg);
1544         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1545              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1546              reg, pipe_name(pipe));
1547
1548         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1549              && (val & SDVO_PIPE_B_SELECT),
1550              "IBX PCH hdmi port still using transcoder B\n");
1551 }
1552
1553 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1554                                       enum pipe pipe)
1555 {
1556         int reg;
1557         u32 val;
1558
1559         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1560         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1561         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1562
1563         reg = PCH_ADPA;
1564         val = I915_READ(reg);
1565         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1566              "PCH VGA enabled on transcoder %c, should be disabled\n",
1567              pipe_name(pipe));
1568
1569         reg = PCH_LVDS;
1570         val = I915_READ(reg);
1571         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1572              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1573              pipe_name(pipe));
1574
1575         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1576         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1577         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1578 }
1579
1580 static void vlv_enable_pll(struct intel_crtc *crtc,
1581                            const struct intel_crtc_state *pipe_config)
1582 {
1583         struct drm_device *dev = crtc->base.dev;
1584         struct drm_i915_private *dev_priv = dev->dev_private;
1585         int reg = DPLL(crtc->pipe);
1586         u32 dpll = pipe_config->dpll_hw_state.dpll;
1587
1588         assert_pipe_disabled(dev_priv, crtc->pipe);
1589
1590         /* No really, not for ILK+ */
1591         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1592
1593         /* PLL is protected by panel, make sure we can write it */
1594         if (IS_MOBILE(dev_priv->dev))
1595                 assert_panel_unlocked(dev_priv, crtc->pipe);
1596
1597         I915_WRITE(reg, dpll);
1598         POSTING_READ(reg);
1599         udelay(150);
1600
1601         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1602                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1603
1604         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1605         POSTING_READ(DPLL_MD(crtc->pipe));
1606
1607         /* We do this three times for luck */
1608         I915_WRITE(reg, dpll);
1609         POSTING_READ(reg);
1610         udelay(150); /* wait for warmup */
1611         I915_WRITE(reg, dpll);
1612         POSTING_READ(reg);
1613         udelay(150); /* wait for warmup */
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150); /* wait for warmup */
1617 }
1618
1619 static void chv_enable_pll(struct intel_crtc *crtc,
1620                            const struct intel_crtc_state *pipe_config)
1621 {
1622         struct drm_device *dev = crtc->base.dev;
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624         int pipe = crtc->pipe;
1625         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1626         u32 tmp;
1627
1628         assert_pipe_disabled(dev_priv, crtc->pipe);
1629
1630         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1631
1632         mutex_lock(&dev_priv->sb_lock);
1633
1634         /* Enable back the 10bit clock to display controller */
1635         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1636         tmp |= DPIO_DCLKP_EN;
1637         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1638
1639         mutex_unlock(&dev_priv->sb_lock);
1640
1641         /*
1642          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1643          */
1644         udelay(1);
1645
1646         /* Enable PLL */
1647         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1648
1649         /* Check PLL is locked */
1650         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1651                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1652
1653         /* not sure when this should be written */
1654         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1655         POSTING_READ(DPLL_MD(pipe));
1656 }
1657
1658 static int intel_num_dvo_pipes(struct drm_device *dev)
1659 {
1660         struct intel_crtc *crtc;
1661         int count = 0;
1662
1663         for_each_intel_crtc(dev, crtc)
1664                 count += crtc->base.state->active &&
1665                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1666
1667         return count;
1668 }
1669
1670 static void i9xx_enable_pll(struct intel_crtc *crtc)
1671 {
1672         struct drm_device *dev = crtc->base.dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         int reg = DPLL(crtc->pipe);
1675         u32 dpll = crtc->config->dpll_hw_state.dpll;
1676
1677         assert_pipe_disabled(dev_priv, crtc->pipe);
1678
1679         /* No really, not for ILK+ */
1680         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1681
1682         /* PLL is protected by panel, make sure we can write it */
1683         if (IS_MOBILE(dev) && !IS_I830(dev))
1684                 assert_panel_unlocked(dev_priv, crtc->pipe);
1685
1686         /* Enable DVO 2x clock on both PLLs if necessary */
1687         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1688                 /*
1689                  * It appears to be important that we don't enable this
1690                  * for the current pipe before otherwise configuring the
1691                  * PLL. No idea how this should be handled if multiple
1692                  * DVO outputs are enabled simultaneosly.
1693                  */
1694                 dpll |= DPLL_DVO_2X_MODE;
1695                 I915_WRITE(DPLL(!crtc->pipe),
1696                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1697         }
1698
1699         /* Wait for the clocks to stabilize. */
1700         POSTING_READ(reg);
1701         udelay(150);
1702
1703         if (INTEL_INFO(dev)->gen >= 4) {
1704                 I915_WRITE(DPLL_MD(crtc->pipe),
1705                            crtc->config->dpll_hw_state.dpll_md);
1706         } else {
1707                 /* The pixel multiplier can only be updated once the
1708                  * DPLL is enabled and the clocks are stable.
1709                  *
1710                  * So write it again.
1711                  */
1712                 I915_WRITE(reg, dpll);
1713         }
1714
1715         /* We do this three times for luck */
1716         I915_WRITE(reg, dpll);
1717         POSTING_READ(reg);
1718         udelay(150); /* wait for warmup */
1719         I915_WRITE(reg, dpll);
1720         POSTING_READ(reg);
1721         udelay(150); /* wait for warmup */
1722         I915_WRITE(reg, dpll);
1723         POSTING_READ(reg);
1724         udelay(150); /* wait for warmup */
1725 }
1726
1727 /**
1728  * i9xx_disable_pll - disable a PLL
1729  * @dev_priv: i915 private structure
1730  * @pipe: pipe PLL to disable
1731  *
1732  * Disable the PLL for @pipe, making sure the pipe is off first.
1733  *
1734  * Note!  This is for pre-ILK only.
1735  */
1736 static void i9xx_disable_pll(struct intel_crtc *crtc)
1737 {
1738         struct drm_device *dev = crtc->base.dev;
1739         struct drm_i915_private *dev_priv = dev->dev_private;
1740         enum pipe pipe = crtc->pipe;
1741
1742         /* Disable DVO 2x clock on both PLLs if necessary */
1743         if (IS_I830(dev) &&
1744             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1745             !intel_num_dvo_pipes(dev)) {
1746                 I915_WRITE(DPLL(PIPE_B),
1747                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1748                 I915_WRITE(DPLL(PIPE_A),
1749                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1750         }
1751
1752         /* Don't disable pipe or pipe PLLs if needed */
1753         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1754             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1755                 return;
1756
1757         /* Make sure the pipe isn't still relying on us */
1758         assert_pipe_disabled(dev_priv, pipe);
1759
1760         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1761         POSTING_READ(DPLL(pipe));
1762 }
1763
1764 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1765 {
1766         u32 val;
1767
1768         /* Make sure the pipe isn't still relying on us */
1769         assert_pipe_disabled(dev_priv, pipe);
1770
1771         /*
1772          * Leave integrated clock source and reference clock enabled for pipe B.
1773          * The latter is needed for VGA hotplug / manual detection.
1774          */
1775         val = DPLL_VGA_MODE_DIS;
1776         if (pipe == PIPE_B)
1777                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1778         I915_WRITE(DPLL(pipe), val);
1779         POSTING_READ(DPLL(pipe));
1780
1781 }
1782
1783 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1784 {
1785         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1786         u32 val;
1787
1788         /* Make sure the pipe isn't still relying on us */
1789         assert_pipe_disabled(dev_priv, pipe);
1790
1791         /* Set PLL en = 0 */
1792         val = DPLL_SSC_REF_CLK_CHV |
1793                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1794         if (pipe != PIPE_A)
1795                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1796         I915_WRITE(DPLL(pipe), val);
1797         POSTING_READ(DPLL(pipe));
1798
1799         mutex_lock(&dev_priv->sb_lock);
1800
1801         /* Disable 10bit clock to display controller */
1802         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1803         val &= ~DPIO_DCLKP_EN;
1804         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1805
1806         mutex_unlock(&dev_priv->sb_lock);
1807 }
1808
1809 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1810                          struct intel_digital_port *dport,
1811                          unsigned int expected_mask)
1812 {
1813         u32 port_mask;
1814         int dpll_reg;
1815
1816         switch (dport->port) {
1817         case PORT_B:
1818                 port_mask = DPLL_PORTB_READY_MASK;
1819                 dpll_reg = DPLL(0);
1820                 break;
1821         case PORT_C:
1822                 port_mask = DPLL_PORTC_READY_MASK;
1823                 dpll_reg = DPLL(0);
1824                 expected_mask <<= 4;
1825                 break;
1826         case PORT_D:
1827                 port_mask = DPLL_PORTD_READY_MASK;
1828                 dpll_reg = DPIO_PHY_STATUS;
1829                 break;
1830         default:
1831                 BUG();
1832         }
1833
1834         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1835                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1836                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1837 }
1838
1839 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1840 {
1841         struct drm_device *dev = crtc->base.dev;
1842         struct drm_i915_private *dev_priv = dev->dev_private;
1843         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1844
1845         if (WARN_ON(pll == NULL))
1846                 return;
1847
1848         WARN_ON(!pll->config.crtc_mask);
1849         if (pll->active == 0) {
1850                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1851                 WARN_ON(pll->on);
1852                 assert_shared_dpll_disabled(dev_priv, pll);
1853
1854                 pll->mode_set(dev_priv, pll);
1855         }
1856 }
1857
1858 /**
1859  * intel_enable_shared_dpll - enable PCH PLL
1860  * @dev_priv: i915 private structure
1861  * @pipe: pipe PLL to enable
1862  *
1863  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1864  * drives the transcoder clock.
1865  */
1866 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1867 {
1868         struct drm_device *dev = crtc->base.dev;
1869         struct drm_i915_private *dev_priv = dev->dev_private;
1870         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1871
1872         if (WARN_ON(pll == NULL))
1873                 return;
1874
1875         if (WARN_ON(pll->config.crtc_mask == 0))
1876                 return;
1877
1878         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1879                       pll->name, pll->active, pll->on,
1880                       crtc->base.base.id);
1881
1882         if (pll->active++) {
1883                 WARN_ON(!pll->on);
1884                 assert_shared_dpll_enabled(dev_priv, pll);
1885                 return;
1886         }
1887         WARN_ON(pll->on);
1888
1889         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1890
1891         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1892         pll->enable(dev_priv, pll);
1893         pll->on = true;
1894 }
1895
1896 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1897 {
1898         struct drm_device *dev = crtc->base.dev;
1899         struct drm_i915_private *dev_priv = dev->dev_private;
1900         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1901
1902         /* PCH only available on ILK+ */
1903         if (INTEL_INFO(dev)->gen < 5)
1904                 return;
1905
1906         if (pll == NULL)
1907                 return;
1908
1909         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1910                 return;
1911
1912         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1913                       pll->name, pll->active, pll->on,
1914                       crtc->base.base.id);
1915
1916         if (WARN_ON(pll->active == 0)) {
1917                 assert_shared_dpll_disabled(dev_priv, pll);
1918                 return;
1919         }
1920
1921         assert_shared_dpll_enabled(dev_priv, pll);
1922         WARN_ON(!pll->on);
1923         if (--pll->active)
1924                 return;
1925
1926         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1927         pll->disable(dev_priv, pll);
1928         pll->on = false;
1929
1930         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1931 }
1932
1933 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1934                                            enum pipe pipe)
1935 {
1936         struct drm_device *dev = dev_priv->dev;
1937         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1939         uint32_t reg, val, pipeconf_val;
1940
1941         /* PCH only available on ILK+ */
1942         BUG_ON(!HAS_PCH_SPLIT(dev));
1943
1944         /* Make sure PCH DPLL is enabled */
1945         assert_shared_dpll_enabled(dev_priv,
1946                                    intel_crtc_to_shared_dpll(intel_crtc));
1947
1948         /* FDI must be feeding us bits for PCH ports */
1949         assert_fdi_tx_enabled(dev_priv, pipe);
1950         assert_fdi_rx_enabled(dev_priv, pipe);
1951
1952         if (HAS_PCH_CPT(dev)) {
1953                 /* Workaround: Set the timing override bit before enabling the
1954                  * pch transcoder. */
1955                 reg = TRANS_CHICKEN2(pipe);
1956                 val = I915_READ(reg);
1957                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1958                 I915_WRITE(reg, val);
1959         }
1960
1961         reg = PCH_TRANSCONF(pipe);
1962         val = I915_READ(reg);
1963         pipeconf_val = I915_READ(PIPECONF(pipe));
1964
1965         if (HAS_PCH_IBX(dev_priv->dev)) {
1966                 /*
1967                  * Make the BPC in transcoder be consistent with
1968                  * that in pipeconf reg. For HDMI we must use 8bpc
1969                  * here for both 8bpc and 12bpc.
1970                  */
1971                 val &= ~PIPECONF_BPC_MASK;
1972                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1973                         val |= PIPECONF_8BPC;
1974                 else
1975                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1976         }
1977
1978         val &= ~TRANS_INTERLACE_MASK;
1979         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1980                 if (HAS_PCH_IBX(dev_priv->dev) &&
1981                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1982                         val |= TRANS_LEGACY_INTERLACED_ILK;
1983                 else
1984                         val |= TRANS_INTERLACED;
1985         else
1986                 val |= TRANS_PROGRESSIVE;
1987
1988         I915_WRITE(reg, val | TRANS_ENABLE);
1989         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1990                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1991 }
1992
1993 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1994                                       enum transcoder cpu_transcoder)
1995 {
1996         u32 val, pipeconf_val;
1997
1998         /* PCH only available on ILK+ */
1999         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2000
2001         /* FDI must be feeding us bits for PCH ports */
2002         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2003         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2004
2005         /* Workaround: set timing override bit. */
2006         val = I915_READ(_TRANSA_CHICKEN2);
2007         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2008         I915_WRITE(_TRANSA_CHICKEN2, val);
2009
2010         val = TRANS_ENABLE;
2011         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2012
2013         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2014             PIPECONF_INTERLACED_ILK)
2015                 val |= TRANS_INTERLACED;
2016         else
2017                 val |= TRANS_PROGRESSIVE;
2018
2019         I915_WRITE(LPT_TRANSCONF, val);
2020         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2021                 DRM_ERROR("Failed to enable PCH transcoder\n");
2022 }
2023
2024 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2025                                             enum pipe pipe)
2026 {
2027         struct drm_device *dev = dev_priv->dev;
2028         uint32_t reg, val;
2029
2030         /* FDI relies on the transcoder */
2031         assert_fdi_tx_disabled(dev_priv, pipe);
2032         assert_fdi_rx_disabled(dev_priv, pipe);
2033
2034         /* Ports must be off as well */
2035         assert_pch_ports_disabled(dev_priv, pipe);
2036
2037         reg = PCH_TRANSCONF(pipe);
2038         val = I915_READ(reg);
2039         val &= ~TRANS_ENABLE;
2040         I915_WRITE(reg, val);
2041         /* wait for PCH transcoder off, transcoder state */
2042         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2043                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2044
2045         if (!HAS_PCH_IBX(dev)) {
2046                 /* Workaround: Clear the timing override chicken bit again. */
2047                 reg = TRANS_CHICKEN2(pipe);
2048                 val = I915_READ(reg);
2049                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2050                 I915_WRITE(reg, val);
2051         }
2052 }
2053
2054 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2055 {
2056         u32 val;
2057
2058         val = I915_READ(LPT_TRANSCONF);
2059         val &= ~TRANS_ENABLE;
2060         I915_WRITE(LPT_TRANSCONF, val);
2061         /* wait for PCH transcoder off, transcoder state */
2062         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2063                 DRM_ERROR("Failed to disable PCH transcoder\n");
2064
2065         /* Workaround: clear timing override bit. */
2066         val = I915_READ(_TRANSA_CHICKEN2);
2067         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2068         I915_WRITE(_TRANSA_CHICKEN2, val);
2069 }
2070
2071 /**
2072  * intel_enable_pipe - enable a pipe, asserting requirements
2073  * @crtc: crtc responsible for the pipe
2074  *
2075  * Enable @crtc's pipe, making sure that various hardware specific requirements
2076  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2077  */
2078 static void intel_enable_pipe(struct intel_crtc *crtc)
2079 {
2080         struct drm_device *dev = crtc->base.dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         enum pipe pipe = crtc->pipe;
2083         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2084                                                                       pipe);
2085         enum pipe pch_transcoder;
2086         int reg;
2087         u32 val;
2088
2089         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2090
2091         assert_planes_disabled(dev_priv, pipe);
2092         assert_cursor_disabled(dev_priv, pipe);
2093         assert_sprites_disabled(dev_priv, pipe);
2094
2095         if (HAS_PCH_LPT(dev_priv->dev))
2096                 pch_transcoder = TRANSCODER_A;
2097         else
2098                 pch_transcoder = pipe;
2099
2100         /*
2101          * A pipe without a PLL won't actually be able to drive bits from
2102          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2103          * need the check.
2104          */
2105         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2106                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2107                         assert_dsi_pll_enabled(dev_priv);
2108                 else
2109                         assert_pll_enabled(dev_priv, pipe);
2110         else {
2111                 if (crtc->config->has_pch_encoder) {
2112                         /* if driving the PCH, we need FDI enabled */
2113                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2114                         assert_fdi_tx_pll_enabled(dev_priv,
2115                                                   (enum pipe) cpu_transcoder);
2116                 }
2117                 /* FIXME: assert CPU port conditions for SNB+ */
2118         }
2119
2120         reg = PIPECONF(cpu_transcoder);
2121         val = I915_READ(reg);
2122         if (val & PIPECONF_ENABLE) {
2123                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2124                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2125                 return;
2126         }
2127
2128         I915_WRITE(reg, val | PIPECONF_ENABLE);
2129         POSTING_READ(reg);
2130 }
2131
2132 /**
2133  * intel_disable_pipe - disable a pipe, asserting requirements
2134  * @crtc: crtc whose pipes is to be disabled
2135  *
2136  * Disable the pipe of @crtc, making sure that various hardware
2137  * specific requirements are met, if applicable, e.g. plane
2138  * disabled, panel fitter off, etc.
2139  *
2140  * Will wait until the pipe has shut down before returning.
2141  */
2142 static void intel_disable_pipe(struct intel_crtc *crtc)
2143 {
2144         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2145         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2146         enum pipe pipe = crtc->pipe;
2147         int reg;
2148         u32 val;
2149
2150         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2151
2152         /*
2153          * Make sure planes won't keep trying to pump pixels to us,
2154          * or we might hang the display.
2155          */
2156         assert_planes_disabled(dev_priv, pipe);
2157         assert_cursor_disabled(dev_priv, pipe);
2158         assert_sprites_disabled(dev_priv, pipe);
2159
2160         reg = PIPECONF(cpu_transcoder);
2161         val = I915_READ(reg);
2162         if ((val & PIPECONF_ENABLE) == 0)
2163                 return;
2164
2165         /*
2166          * Double wide has implications for planes
2167          * so best keep it disabled when not needed.
2168          */
2169         if (crtc->config->double_wide)
2170                 val &= ~PIPECONF_DOUBLE_WIDE;
2171
2172         /* Don't disable pipe or pipe PLLs if needed */
2173         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2174             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2175                 val &= ~PIPECONF_ENABLE;
2176
2177         I915_WRITE(reg, val);
2178         if ((val & PIPECONF_ENABLE) == 0)
2179                 intel_wait_for_pipe_off(crtc);
2180 }
2181
2182 static bool need_vtd_wa(struct drm_device *dev)
2183 {
2184 #ifdef CONFIG_INTEL_IOMMU
2185         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2186                 return true;
2187 #endif
2188         return false;
2189 }
2190
2191 unsigned int
2192 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2193                   uint64_t fb_format_modifier, unsigned int plane)
2194 {
2195         unsigned int tile_height;
2196         uint32_t pixel_bytes;
2197
2198         switch (fb_format_modifier) {
2199         case DRM_FORMAT_MOD_NONE:
2200                 tile_height = 1;
2201                 break;
2202         case I915_FORMAT_MOD_X_TILED:
2203                 tile_height = IS_GEN2(dev) ? 16 : 8;
2204                 break;
2205         case I915_FORMAT_MOD_Y_TILED:
2206                 tile_height = 32;
2207                 break;
2208         case I915_FORMAT_MOD_Yf_TILED:
2209                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2210                 switch (pixel_bytes) {
2211                 default:
2212                 case 1:
2213                         tile_height = 64;
2214                         break;
2215                 case 2:
2216                 case 4:
2217                         tile_height = 32;
2218                         break;
2219                 case 8:
2220                         tile_height = 16;
2221                         break;
2222                 case 16:
2223                         WARN_ONCE(1,
2224                                   "128-bit pixels are not supported for display!");
2225                         tile_height = 16;
2226                         break;
2227                 }
2228                 break;
2229         default:
2230                 MISSING_CASE(fb_format_modifier);
2231                 tile_height = 1;
2232                 break;
2233         }
2234
2235         return tile_height;
2236 }
2237
2238 unsigned int
2239 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2240                       uint32_t pixel_format, uint64_t fb_format_modifier)
2241 {
2242         return ALIGN(height, intel_tile_height(dev, pixel_format,
2243                                                fb_format_modifier, 0));
2244 }
2245
2246 static int
2247 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2248                         const struct drm_plane_state *plane_state)
2249 {
2250         struct intel_rotation_info *info = &view->rotation_info;
2251         unsigned int tile_height, tile_pitch;
2252
2253         *view = i915_ggtt_view_normal;
2254
2255         if (!plane_state)
2256                 return 0;
2257
2258         if (!intel_rotation_90_or_270(plane_state->rotation))
2259                 return 0;
2260
2261         *view = i915_ggtt_view_rotated;
2262
2263         info->height = fb->height;
2264         info->pixel_format = fb->pixel_format;
2265         info->pitch = fb->pitches[0];
2266         info->uv_offset = fb->offsets[1];
2267         info->fb_modifier = fb->modifier[0];
2268
2269         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2270                                         fb->modifier[0], 0);
2271         tile_pitch = PAGE_SIZE / tile_height;
2272         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2273         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2274         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2275
2276         if (info->pixel_format == DRM_FORMAT_NV12) {
2277                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2278                                                 fb->modifier[0], 1);
2279                 tile_pitch = PAGE_SIZE / tile_height;
2280                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2281                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2282                                                      tile_height);
2283                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2284                                 PAGE_SIZE;
2285         }
2286
2287         return 0;
2288 }
2289
2290 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2291 {
2292         if (INTEL_INFO(dev_priv)->gen >= 9)
2293                 return 256 * 1024;
2294         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2295                  IS_VALLEYVIEW(dev_priv))
2296                 return 128 * 1024;
2297         else if (INTEL_INFO(dev_priv)->gen >= 4)
2298                 return 4 * 1024;
2299         else
2300                 return 0;
2301 }
2302
2303 int
2304 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2305                            struct drm_framebuffer *fb,
2306                            const struct drm_plane_state *plane_state,
2307                            struct intel_engine_cs *pipelined,
2308                            struct drm_i915_gem_request **pipelined_request)
2309 {
2310         struct drm_device *dev = fb->dev;
2311         struct drm_i915_private *dev_priv = dev->dev_private;
2312         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2313         struct i915_ggtt_view view;
2314         u32 alignment;
2315         int ret;
2316
2317         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2318
2319         switch (fb->modifier[0]) {
2320         case DRM_FORMAT_MOD_NONE:
2321                 alignment = intel_linear_alignment(dev_priv);
2322                 break;
2323         case I915_FORMAT_MOD_X_TILED:
2324                 if (INTEL_INFO(dev)->gen >= 9)
2325                         alignment = 256 * 1024;
2326                 else {
2327                         /* pin() will align the object as required by fence */
2328                         alignment = 0;
2329                 }
2330                 break;
2331         case I915_FORMAT_MOD_Y_TILED:
2332         case I915_FORMAT_MOD_Yf_TILED:
2333                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2334                           "Y tiling bo slipped through, driver bug!\n"))
2335                         return -EINVAL;
2336                 alignment = 1 * 1024 * 1024;
2337                 break;
2338         default:
2339                 MISSING_CASE(fb->modifier[0]);
2340                 return -EINVAL;
2341         }
2342
2343         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2344         if (ret)
2345                 return ret;
2346
2347         /* Note that the w/a also requires 64 PTE of padding following the
2348          * bo. We currently fill all unused PTE with the shadow page and so
2349          * we should always have valid PTE following the scanout preventing
2350          * the VT-d warning.
2351          */
2352         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2353                 alignment = 256 * 1024;
2354
2355         /*
2356          * Global gtt pte registers are special registers which actually forward
2357          * writes to a chunk of system memory. Which means that there is no risk
2358          * that the register values disappear as soon as we call
2359          * intel_runtime_pm_put(), so it is correct to wrap only the
2360          * pin/unpin/fence and not more.
2361          */
2362         intel_runtime_pm_get(dev_priv);
2363
2364         dev_priv->mm.interruptible = false;
2365         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2366                                                    pipelined_request, &view);
2367         if (ret)
2368                 goto err_interruptible;
2369
2370         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2371          * fence, whereas 965+ only requires a fence if using
2372          * framebuffer compression.  For simplicity, we always install
2373          * a fence as the cost is not that onerous.
2374          */
2375         ret = i915_gem_object_get_fence(obj);
2376         if (ret == -EDEADLK) {
2377                 /*
2378                  * -EDEADLK means there are no free fences
2379                  * no pending flips.
2380                  *
2381                  * This is propagated to atomic, but it uses
2382                  * -EDEADLK to force a locking recovery, so
2383                  * change the returned error to -EBUSY.
2384                  */
2385                 ret = -EBUSY;
2386                 goto err_unpin;
2387         } else if (ret)
2388                 goto err_unpin;
2389
2390         i915_gem_object_pin_fence(obj);
2391
2392         dev_priv->mm.interruptible = true;
2393         intel_runtime_pm_put(dev_priv);
2394         return 0;
2395
2396 err_unpin:
2397         i915_gem_object_unpin_from_display_plane(obj, &view);
2398 err_interruptible:
2399         dev_priv->mm.interruptible = true;
2400         intel_runtime_pm_put(dev_priv);
2401         return ret;
2402 }
2403
2404 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2405                                const struct drm_plane_state *plane_state)
2406 {
2407         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2408         struct i915_ggtt_view view;
2409         int ret;
2410
2411         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2412
2413         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2414         WARN_ONCE(ret, "Couldn't get view from plane state!");
2415
2416         i915_gem_object_unpin_fence(obj);
2417         i915_gem_object_unpin_from_display_plane(obj, &view);
2418 }
2419
2420 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2421  * is assumed to be a power-of-two. */
2422 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2423                                              int *x, int *y,
2424                                              unsigned int tiling_mode,
2425                                              unsigned int cpp,
2426                                              unsigned int pitch)
2427 {
2428         if (tiling_mode != I915_TILING_NONE) {
2429                 unsigned int tile_rows, tiles;
2430
2431                 tile_rows = *y / 8;
2432                 *y %= 8;
2433
2434                 tiles = *x / (512/cpp);
2435                 *x %= 512/cpp;
2436
2437                 return tile_rows * pitch * 8 + tiles * 4096;
2438         } else {
2439                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2440                 unsigned int offset;
2441
2442                 offset = *y * pitch + *x * cpp;
2443                 *y = (offset & alignment) / pitch;
2444                 *x = ((offset & alignment) - *y * pitch) / cpp;
2445                 return offset & ~alignment;
2446         }
2447 }
2448
2449 static int i9xx_format_to_fourcc(int format)
2450 {
2451         switch (format) {
2452         case DISPPLANE_8BPP:
2453                 return DRM_FORMAT_C8;
2454         case DISPPLANE_BGRX555:
2455                 return DRM_FORMAT_XRGB1555;
2456         case DISPPLANE_BGRX565:
2457                 return DRM_FORMAT_RGB565;
2458         default:
2459         case DISPPLANE_BGRX888:
2460                 return DRM_FORMAT_XRGB8888;
2461         case DISPPLANE_RGBX888:
2462                 return DRM_FORMAT_XBGR8888;
2463         case DISPPLANE_BGRX101010:
2464                 return DRM_FORMAT_XRGB2101010;
2465         case DISPPLANE_RGBX101010:
2466                 return DRM_FORMAT_XBGR2101010;
2467         }
2468 }
2469
2470 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2471 {
2472         switch (format) {
2473         case PLANE_CTL_FORMAT_RGB_565:
2474                 return DRM_FORMAT_RGB565;
2475         default:
2476         case PLANE_CTL_FORMAT_XRGB_8888:
2477                 if (rgb_order) {
2478                         if (alpha)
2479                                 return DRM_FORMAT_ABGR8888;
2480                         else
2481                                 return DRM_FORMAT_XBGR8888;
2482                 } else {
2483                         if (alpha)
2484                                 return DRM_FORMAT_ARGB8888;
2485                         else
2486                                 return DRM_FORMAT_XRGB8888;
2487                 }
2488         case PLANE_CTL_FORMAT_XRGB_2101010:
2489                 if (rgb_order)
2490                         return DRM_FORMAT_XBGR2101010;
2491                 else
2492                         return DRM_FORMAT_XRGB2101010;
2493         }
2494 }
2495
2496 static bool
2497 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2498                               struct intel_initial_plane_config *plane_config)
2499 {
2500         struct drm_device *dev = crtc->base.dev;
2501         struct drm_i915_gem_object *obj = NULL;
2502         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2503         struct drm_framebuffer *fb = &plane_config->fb->base;
2504         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2505         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2506                                     PAGE_SIZE);
2507
2508         size_aligned -= base_aligned;
2509
2510         if (plane_config->size == 0)
2511                 return false;
2512
2513         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2514                                                              base_aligned,
2515                                                              base_aligned,
2516                                                              size_aligned);
2517         if (!obj)
2518                 return false;
2519
2520         obj->tiling_mode = plane_config->tiling;
2521         if (obj->tiling_mode == I915_TILING_X)
2522                 obj->stride = fb->pitches[0];
2523
2524         mode_cmd.pixel_format = fb->pixel_format;
2525         mode_cmd.width = fb->width;
2526         mode_cmd.height = fb->height;
2527         mode_cmd.pitches[0] = fb->pitches[0];
2528         mode_cmd.modifier[0] = fb->modifier[0];
2529         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2530
2531         mutex_lock(&dev->struct_mutex);
2532         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2533                                    &mode_cmd, obj)) {
2534                 DRM_DEBUG_KMS("intel fb init failed\n");
2535                 goto out_unref_obj;
2536         }
2537         mutex_unlock(&dev->struct_mutex);
2538
2539         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2540         return true;
2541
2542 out_unref_obj:
2543         drm_gem_object_unreference(&obj->base);
2544         mutex_unlock(&dev->struct_mutex);
2545         return false;
2546 }
2547
2548 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2549 static void
2550 update_state_fb(struct drm_plane *plane)
2551 {
2552         if (plane->fb == plane->state->fb)
2553                 return;
2554
2555         if (plane->state->fb)
2556                 drm_framebuffer_unreference(plane->state->fb);
2557         plane->state->fb = plane->fb;
2558         if (plane->state->fb)
2559                 drm_framebuffer_reference(plane->state->fb);
2560 }
2561
2562 static void
2563 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2564                              struct intel_initial_plane_config *plane_config)
2565 {
2566         struct drm_device *dev = intel_crtc->base.dev;
2567         struct drm_i915_private *dev_priv = dev->dev_private;
2568         struct drm_crtc *c;
2569         struct intel_crtc *i;
2570         struct drm_i915_gem_object *obj;
2571         struct drm_plane *primary = intel_crtc->base.primary;
2572         struct drm_plane_state *plane_state = primary->state;
2573         struct drm_framebuffer *fb;
2574
2575         if (!plane_config->fb)
2576                 return;
2577
2578         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2579                 fb = &plane_config->fb->base;
2580                 goto valid_fb;
2581         }
2582
2583         kfree(plane_config->fb);
2584
2585         /*
2586          * Failed to alloc the obj, check to see if we should share
2587          * an fb with another CRTC instead
2588          */
2589         for_each_crtc(dev, c) {
2590                 i = to_intel_crtc(c);
2591
2592                 if (c == &intel_crtc->base)
2593                         continue;
2594
2595                 if (!i->active)
2596                         continue;
2597
2598                 fb = c->primary->fb;
2599                 if (!fb)
2600                         continue;
2601
2602                 obj = intel_fb_obj(fb);
2603                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2604                         drm_framebuffer_reference(fb);
2605                         goto valid_fb;
2606                 }
2607         }
2608
2609         return;
2610
2611 valid_fb:
2612         plane_state->src_x = plane_state->src_y = 0;
2613         plane_state->src_w = fb->width << 16;
2614         plane_state->src_h = fb->height << 16;
2615
2616         plane_state->crtc_x = plane_state->src_y = 0;
2617         plane_state->crtc_w = fb->width;
2618         plane_state->crtc_h = fb->height;
2619
2620         obj = intel_fb_obj(fb);
2621         if (obj->tiling_mode != I915_TILING_NONE)
2622                 dev_priv->preserve_bios_swizzle = true;
2623
2624         drm_framebuffer_reference(fb);
2625         primary->fb = primary->state->fb = fb;
2626         primary->crtc = primary->state->crtc = &intel_crtc->base;
2627         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2628         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2629 }
2630
2631 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2632                                       struct drm_framebuffer *fb,
2633                                       int x, int y)
2634 {
2635         struct drm_device *dev = crtc->dev;
2636         struct drm_i915_private *dev_priv = dev->dev_private;
2637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638         struct drm_plane *primary = crtc->primary;
2639         bool visible = to_intel_plane_state(primary->state)->visible;
2640         struct drm_i915_gem_object *obj;
2641         int plane = intel_crtc->plane;
2642         unsigned long linear_offset;
2643         u32 dspcntr;
2644         u32 reg = DSPCNTR(plane);
2645         int pixel_size;
2646
2647         if (!visible || !fb) {
2648                 I915_WRITE(reg, 0);
2649                 if (INTEL_INFO(dev)->gen >= 4)
2650                         I915_WRITE(DSPSURF(plane), 0);
2651                 else
2652                         I915_WRITE(DSPADDR(plane), 0);
2653                 POSTING_READ(reg);
2654                 return;
2655         }
2656
2657         obj = intel_fb_obj(fb);
2658         if (WARN_ON(obj == NULL))
2659                 return;
2660
2661         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2662
2663         dspcntr = DISPPLANE_GAMMA_ENABLE;
2664
2665         dspcntr |= DISPLAY_PLANE_ENABLE;
2666
2667         if (INTEL_INFO(dev)->gen < 4) {
2668                 if (intel_crtc->pipe == PIPE_B)
2669                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2670
2671                 /* pipesrc and dspsize control the size that is scaled from,
2672                  * which should always be the user's requested size.
2673                  */
2674                 I915_WRITE(DSPSIZE(plane),
2675                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2676                            (intel_crtc->config->pipe_src_w - 1));
2677                 I915_WRITE(DSPPOS(plane), 0);
2678         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2679                 I915_WRITE(PRIMSIZE(plane),
2680                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2681                            (intel_crtc->config->pipe_src_w - 1));
2682                 I915_WRITE(PRIMPOS(plane), 0);
2683                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2684         }
2685
2686         switch (fb->pixel_format) {
2687         case DRM_FORMAT_C8:
2688                 dspcntr |= DISPPLANE_8BPP;
2689                 break;
2690         case DRM_FORMAT_XRGB1555:
2691                 dspcntr |= DISPPLANE_BGRX555;
2692                 break;
2693         case DRM_FORMAT_RGB565:
2694                 dspcntr |= DISPPLANE_BGRX565;
2695                 break;
2696         case DRM_FORMAT_XRGB8888:
2697                 dspcntr |= DISPPLANE_BGRX888;
2698                 break;
2699         case DRM_FORMAT_XBGR8888:
2700                 dspcntr |= DISPPLANE_RGBX888;
2701                 break;
2702         case DRM_FORMAT_XRGB2101010:
2703                 dspcntr |= DISPPLANE_BGRX101010;
2704                 break;
2705         case DRM_FORMAT_XBGR2101010:
2706                 dspcntr |= DISPPLANE_RGBX101010;
2707                 break;
2708         default:
2709                 BUG();
2710         }
2711
2712         if (INTEL_INFO(dev)->gen >= 4 &&
2713             obj->tiling_mode != I915_TILING_NONE)
2714                 dspcntr |= DISPPLANE_TILED;
2715
2716         if (IS_G4X(dev))
2717                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2718
2719         linear_offset = y * fb->pitches[0] + x * pixel_size;
2720
2721         if (INTEL_INFO(dev)->gen >= 4) {
2722                 intel_crtc->dspaddr_offset =
2723                         intel_gen4_compute_page_offset(dev_priv,
2724                                                        &x, &y, obj->tiling_mode,
2725                                                        pixel_size,
2726                                                        fb->pitches[0]);
2727                 linear_offset -= intel_crtc->dspaddr_offset;
2728         } else {
2729                 intel_crtc->dspaddr_offset = linear_offset;
2730         }
2731
2732         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2733                 dspcntr |= DISPPLANE_ROTATE_180;
2734
2735                 x += (intel_crtc->config->pipe_src_w - 1);
2736                 y += (intel_crtc->config->pipe_src_h - 1);
2737
2738                 /* Finding the last pixel of the last line of the display
2739                 data and adding to linear_offset*/
2740                 linear_offset +=
2741                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2742                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2743         }
2744
2745         intel_crtc->adjusted_x = x;
2746         intel_crtc->adjusted_y = y;
2747
2748         I915_WRITE(reg, dspcntr);
2749
2750         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2751         if (INTEL_INFO(dev)->gen >= 4) {
2752                 I915_WRITE(DSPSURF(plane),
2753                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2754                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2755                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2756         } else
2757                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2758         POSTING_READ(reg);
2759 }
2760
2761 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762                                           struct drm_framebuffer *fb,
2763                                           int x, int y)
2764 {
2765         struct drm_device *dev = crtc->dev;
2766         struct drm_i915_private *dev_priv = dev->dev_private;
2767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2768         struct drm_plane *primary = crtc->primary;
2769         bool visible = to_intel_plane_state(primary->state)->visible;
2770         struct drm_i915_gem_object *obj;
2771         int plane = intel_crtc->plane;
2772         unsigned long linear_offset;
2773         u32 dspcntr;
2774         u32 reg = DSPCNTR(plane);
2775         int pixel_size;
2776
2777         if (!visible || !fb) {
2778                 I915_WRITE(reg, 0);
2779                 I915_WRITE(DSPSURF(plane), 0);
2780                 POSTING_READ(reg);
2781                 return;
2782         }
2783
2784         obj = intel_fb_obj(fb);
2785         if (WARN_ON(obj == NULL))
2786                 return;
2787
2788         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2789
2790         dspcntr = DISPPLANE_GAMMA_ENABLE;
2791
2792         dspcntr |= DISPLAY_PLANE_ENABLE;
2793
2794         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2796
2797         switch (fb->pixel_format) {
2798         case DRM_FORMAT_C8:
2799                 dspcntr |= DISPPLANE_8BPP;
2800                 break;
2801         case DRM_FORMAT_RGB565:
2802                 dspcntr |= DISPPLANE_BGRX565;
2803                 break;
2804         case DRM_FORMAT_XRGB8888:
2805                 dspcntr |= DISPPLANE_BGRX888;
2806                 break;
2807         case DRM_FORMAT_XBGR8888:
2808                 dspcntr |= DISPPLANE_RGBX888;
2809                 break;
2810         case DRM_FORMAT_XRGB2101010:
2811                 dspcntr |= DISPPLANE_BGRX101010;
2812                 break;
2813         case DRM_FORMAT_XBGR2101010:
2814                 dspcntr |= DISPPLANE_RGBX101010;
2815                 break;
2816         default:
2817                 BUG();
2818         }
2819
2820         if (obj->tiling_mode != I915_TILING_NONE)
2821                 dspcntr |= DISPPLANE_TILED;
2822
2823         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2824                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2825
2826         linear_offset = y * fb->pitches[0] + x * pixel_size;
2827         intel_crtc->dspaddr_offset =
2828                 intel_gen4_compute_page_offset(dev_priv,
2829                                                &x, &y, obj->tiling_mode,
2830                                                pixel_size,
2831                                                fb->pitches[0]);
2832         linear_offset -= intel_crtc->dspaddr_offset;
2833         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2834                 dspcntr |= DISPPLANE_ROTATE_180;
2835
2836                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2837                         x += (intel_crtc->config->pipe_src_w - 1);
2838                         y += (intel_crtc->config->pipe_src_h - 1);
2839
2840                         /* Finding the last pixel of the last line of the display
2841                         data and adding to linear_offset*/
2842                         linear_offset +=
2843                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2844                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2845                 }
2846         }
2847
2848         intel_crtc->adjusted_x = x;
2849         intel_crtc->adjusted_y = y;
2850
2851         I915_WRITE(reg, dspcntr);
2852
2853         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2854         I915_WRITE(DSPSURF(plane),
2855                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2856         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2857                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2858         } else {
2859                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2860                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2861         }
2862         POSTING_READ(reg);
2863 }
2864
2865 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2866                               uint32_t pixel_format)
2867 {
2868         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2869
2870         /*
2871          * The stride is either expressed as a multiple of 64 bytes
2872          * chunks for linear buffers or in number of tiles for tiled
2873          * buffers.
2874          */
2875         switch (fb_modifier) {
2876         case DRM_FORMAT_MOD_NONE:
2877                 return 64;
2878         case I915_FORMAT_MOD_X_TILED:
2879                 if (INTEL_INFO(dev)->gen == 2)
2880                         return 128;
2881                 return 512;
2882         case I915_FORMAT_MOD_Y_TILED:
2883                 /* No need to check for old gens and Y tiling since this is
2884                  * about the display engine and those will be blocked before
2885                  * we get here.
2886                  */
2887                 return 128;
2888         case I915_FORMAT_MOD_Yf_TILED:
2889                 if (bits_per_pixel == 8)
2890                         return 64;
2891                 else
2892                         return 128;
2893         default:
2894                 MISSING_CASE(fb_modifier);
2895                 return 64;
2896         }
2897 }
2898
2899 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2900                                      struct drm_i915_gem_object *obj,
2901                                      unsigned int plane)
2902 {
2903         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2904         struct i915_vma *vma;
2905         unsigned char *offset;
2906
2907         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2908                 view = &i915_ggtt_view_rotated;
2909
2910         vma = i915_gem_obj_to_ggtt_view(obj, view);
2911         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2912                 view->type))
2913                 return -1;
2914
2915         offset = (unsigned char *)vma->node.start;
2916
2917         if (plane == 1) {
2918                 offset += vma->ggtt_view.rotation_info.uv_start_page *
2919                           PAGE_SIZE;
2920         }
2921
2922         return (unsigned long)offset;
2923 }
2924
2925 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2926 {
2927         struct drm_device *dev = intel_crtc->base.dev;
2928         struct drm_i915_private *dev_priv = dev->dev_private;
2929
2930         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2931         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2932         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2933 }
2934
2935 /*
2936  * This function detaches (aka. unbinds) unused scalers in hardware
2937  */
2938 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2939 {
2940         struct intel_crtc_scaler_state *scaler_state;
2941         int i;
2942
2943         scaler_state = &intel_crtc->config->scaler_state;
2944
2945         /* loop through and disable scalers that aren't in use */
2946         for (i = 0; i < intel_crtc->num_scalers; i++) {
2947                 if (!scaler_state->scalers[i].in_use)
2948                         skl_detach_scaler(intel_crtc, i);
2949         }
2950 }
2951
2952 u32 skl_plane_ctl_format(uint32_t pixel_format)
2953 {
2954         switch (pixel_format) {
2955         case DRM_FORMAT_C8:
2956                 return PLANE_CTL_FORMAT_INDEXED;
2957         case DRM_FORMAT_RGB565:
2958                 return PLANE_CTL_FORMAT_RGB_565;
2959         case DRM_FORMAT_XBGR8888:
2960                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2961         case DRM_FORMAT_XRGB8888:
2962                 return PLANE_CTL_FORMAT_XRGB_8888;
2963         /*
2964          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2965          * to be already pre-multiplied. We need to add a knob (or a different
2966          * DRM_FORMAT) for user-space to configure that.
2967          */
2968         case DRM_FORMAT_ABGR8888:
2969                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2970                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2971         case DRM_FORMAT_ARGB8888:
2972                 return PLANE_CTL_FORMAT_XRGB_8888 |
2973                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2974         case DRM_FORMAT_XRGB2101010:
2975                 return PLANE_CTL_FORMAT_XRGB_2101010;
2976         case DRM_FORMAT_XBGR2101010:
2977                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2978         case DRM_FORMAT_YUYV:
2979                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2980         case DRM_FORMAT_YVYU:
2981                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2982         case DRM_FORMAT_UYVY:
2983                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2984         case DRM_FORMAT_VYUY:
2985                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2986         default:
2987                 MISSING_CASE(pixel_format);
2988         }
2989
2990         return 0;
2991 }
2992
2993 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2994 {
2995         switch (fb_modifier) {
2996         case DRM_FORMAT_MOD_NONE:
2997                 break;
2998         case I915_FORMAT_MOD_X_TILED:
2999                 return PLANE_CTL_TILED_X;
3000         case I915_FORMAT_MOD_Y_TILED:
3001                 return PLANE_CTL_TILED_Y;
3002         case I915_FORMAT_MOD_Yf_TILED:
3003                 return PLANE_CTL_TILED_YF;
3004         default:
3005                 MISSING_CASE(fb_modifier);
3006         }
3007
3008         return 0;
3009 }
3010
3011 u32 skl_plane_ctl_rotation(unsigned int rotation)
3012 {
3013         switch (rotation) {
3014         case BIT(DRM_ROTATE_0):
3015                 break;
3016         /*
3017          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3018          * while i915 HW rotation is clockwise, thats why this swapping.
3019          */
3020         case BIT(DRM_ROTATE_90):
3021                 return PLANE_CTL_ROTATE_270;
3022         case BIT(DRM_ROTATE_180):
3023                 return PLANE_CTL_ROTATE_180;
3024         case BIT(DRM_ROTATE_270):
3025                 return PLANE_CTL_ROTATE_90;
3026         default:
3027                 MISSING_CASE(rotation);
3028         }
3029
3030         return 0;
3031 }
3032
3033 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3034                                          struct drm_framebuffer *fb,
3035                                          int x, int y)
3036 {
3037         struct drm_device *dev = crtc->dev;
3038         struct drm_i915_private *dev_priv = dev->dev_private;
3039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3040         struct drm_plane *plane = crtc->primary;
3041         bool visible = to_intel_plane_state(plane->state)->visible;
3042         struct drm_i915_gem_object *obj;
3043         int pipe = intel_crtc->pipe;
3044         u32 plane_ctl, stride_div, stride;
3045         u32 tile_height, plane_offset, plane_size;
3046         unsigned int rotation;
3047         int x_offset, y_offset;
3048         unsigned long surf_addr;
3049         struct intel_crtc_state *crtc_state = intel_crtc->config;
3050         struct intel_plane_state *plane_state;
3051         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3052         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3053         int scaler_id = -1;
3054
3055         plane_state = to_intel_plane_state(plane->state);
3056
3057         if (!visible || !fb) {
3058                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3059                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3060                 POSTING_READ(PLANE_CTL(pipe, 0));
3061                 return;
3062         }
3063
3064         plane_ctl = PLANE_CTL_ENABLE |
3065                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3066                     PLANE_CTL_PIPE_CSC_ENABLE;
3067
3068         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3069         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3070         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3071
3072         rotation = plane->state->rotation;
3073         plane_ctl |= skl_plane_ctl_rotation(rotation);
3074
3075         obj = intel_fb_obj(fb);
3076         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3077                                                fb->pixel_format);
3078         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3079
3080         /*
3081          * FIXME: intel_plane_state->src, dst aren't set when transitional
3082          * update_plane helpers are called from legacy paths.
3083          * Once full atomic crtc is available, below check can be avoided.
3084          */
3085         if (drm_rect_width(&plane_state->src)) {
3086                 scaler_id = plane_state->scaler_id;
3087                 src_x = plane_state->src.x1 >> 16;
3088                 src_y = plane_state->src.y1 >> 16;
3089                 src_w = drm_rect_width(&plane_state->src) >> 16;
3090                 src_h = drm_rect_height(&plane_state->src) >> 16;
3091                 dst_x = plane_state->dst.x1;
3092                 dst_y = plane_state->dst.y1;
3093                 dst_w = drm_rect_width(&plane_state->dst);
3094                 dst_h = drm_rect_height(&plane_state->dst);
3095
3096                 WARN_ON(x != src_x || y != src_y);
3097         } else {
3098                 src_w = intel_crtc->config->pipe_src_w;
3099                 src_h = intel_crtc->config->pipe_src_h;
3100         }
3101
3102         if (intel_rotation_90_or_270(rotation)) {
3103                 /* stride = Surface height in tiles */
3104                 tile_height = intel_tile_height(dev, fb->pixel_format,
3105                                                 fb->modifier[0], 0);
3106                 stride = DIV_ROUND_UP(fb->height, tile_height);
3107                 x_offset = stride * tile_height - y - src_h;
3108                 y_offset = x;
3109                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3110         } else {
3111                 stride = fb->pitches[0] / stride_div;
3112                 x_offset = x;
3113                 y_offset = y;
3114                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3115         }
3116         plane_offset = y_offset << 16 | x_offset;
3117
3118         intel_crtc->adjusted_x = x_offset;
3119         intel_crtc->adjusted_y = y_offset;
3120
3121         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3122         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3123         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3124         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3125
3126         if (scaler_id >= 0) {
3127                 uint32_t ps_ctrl = 0;
3128
3129                 WARN_ON(!dst_w || !dst_h);
3130                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3131                         crtc_state->scaler_state.scalers[scaler_id].mode;
3132                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3133                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3134                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3135                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3136                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3137         } else {
3138                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3139         }
3140
3141         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3142
3143         POSTING_READ(PLANE_SURF(pipe, 0));
3144 }
3145
3146 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3147 static int
3148 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3149                            int x, int y, enum mode_set_atomic state)
3150 {
3151         struct drm_device *dev = crtc->dev;
3152         struct drm_i915_private *dev_priv = dev->dev_private;
3153
3154         if (dev_priv->fbc.disable_fbc)
3155                 dev_priv->fbc.disable_fbc(dev_priv);
3156
3157         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3158
3159         return 0;
3160 }
3161
3162 static void intel_complete_page_flips(struct drm_device *dev)
3163 {
3164         struct drm_crtc *crtc;
3165
3166         for_each_crtc(dev, crtc) {
3167                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168                 enum plane plane = intel_crtc->plane;
3169
3170                 intel_prepare_page_flip(dev, plane);
3171                 intel_finish_page_flip_plane(dev, plane);
3172         }
3173 }
3174
3175 static void intel_update_primary_planes(struct drm_device *dev)
3176 {
3177         struct drm_crtc *crtc;
3178
3179         for_each_crtc(dev, crtc) {
3180                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3181                 struct intel_plane_state *plane_state;
3182
3183                 drm_modeset_lock_crtc(crtc, &plane->base);
3184
3185                 plane_state = to_intel_plane_state(plane->base.state);
3186
3187                 if (plane_state->base.fb)
3188                         plane->commit_plane(&plane->base, plane_state);
3189
3190                 drm_modeset_unlock_crtc(crtc);
3191         }
3192 }
3193
3194 void intel_prepare_reset(struct drm_device *dev)
3195 {
3196         /* no reset support for gen2 */
3197         if (IS_GEN2(dev))
3198                 return;
3199
3200         /* reset doesn't touch the display */
3201         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202                 return;
3203
3204         drm_modeset_lock_all(dev);
3205         /*
3206          * Disabling the crtcs gracefully seems nicer. Also the
3207          * g33 docs say we should at least disable all the planes.
3208          */
3209         intel_display_suspend(dev);
3210 }
3211
3212 void intel_finish_reset(struct drm_device *dev)
3213 {
3214         struct drm_i915_private *dev_priv = to_i915(dev);
3215
3216         /*
3217          * Flips in the rings will be nuked by the reset,
3218          * so complete all pending flips so that user space
3219          * will get its events and not get stuck.
3220          */
3221         intel_complete_page_flips(dev);
3222
3223         /* no reset support for gen2 */
3224         if (IS_GEN2(dev))
3225                 return;
3226
3227         /* reset doesn't touch the display */
3228         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3229                 /*
3230                  * Flips in the rings have been nuked by the reset,
3231                  * so update the base address of all primary
3232                  * planes to the the last fb to make sure we're
3233                  * showing the correct fb after a reset.
3234                  *
3235                  * FIXME: Atomic will make this obsolete since we won't schedule
3236                  * CS-based flips (which might get lost in gpu resets) any more.
3237                  */
3238                 intel_update_primary_planes(dev);
3239                 return;
3240         }
3241
3242         /*
3243          * The display has been reset as well,
3244          * so need a full re-initialization.
3245          */
3246         intel_runtime_pm_disable_interrupts(dev_priv);
3247         intel_runtime_pm_enable_interrupts(dev_priv);
3248
3249         intel_modeset_init_hw(dev);
3250
3251         spin_lock_irq(&dev_priv->irq_lock);
3252         if (dev_priv->display.hpd_irq_setup)
3253                 dev_priv->display.hpd_irq_setup(dev);
3254         spin_unlock_irq(&dev_priv->irq_lock);
3255
3256         intel_display_resume(dev);
3257
3258         intel_hpd_init(dev_priv);
3259
3260         drm_modeset_unlock_all(dev);
3261 }
3262
3263 static void
3264 intel_finish_fb(struct drm_framebuffer *old_fb)
3265 {
3266         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3267         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3268         bool was_interruptible = dev_priv->mm.interruptible;
3269         int ret;
3270
3271         /* Big Hammer, we also need to ensure that any pending
3272          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3273          * current scanout is retired before unpinning the old
3274          * framebuffer. Note that we rely on userspace rendering
3275          * into the buffer attached to the pipe they are waiting
3276          * on. If not, userspace generates a GPU hang with IPEHR
3277          * point to the MI_WAIT_FOR_EVENT.
3278          *
3279          * This should only fail upon a hung GPU, in which case we
3280          * can safely continue.
3281          */
3282         dev_priv->mm.interruptible = false;
3283         ret = i915_gem_object_wait_rendering(obj, true);
3284         dev_priv->mm.interruptible = was_interruptible;
3285
3286         WARN_ON(ret);
3287 }
3288
3289 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3290 {
3291         struct drm_device *dev = crtc->dev;
3292         struct drm_i915_private *dev_priv = dev->dev_private;
3293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3294         bool pending;
3295
3296         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3297             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3298                 return false;
3299
3300         spin_lock_irq(&dev->event_lock);
3301         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3302         spin_unlock_irq(&dev->event_lock);
3303
3304         return pending;
3305 }
3306
3307 static void intel_update_pipe_config(struct intel_crtc *crtc,
3308                                      struct intel_crtc_state *old_crtc_state)
3309 {
3310         struct drm_device *dev = crtc->base.dev;
3311         struct drm_i915_private *dev_priv = dev->dev_private;
3312         struct intel_crtc_state *pipe_config =
3313                 to_intel_crtc_state(crtc->base.state);
3314
3315         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3316         crtc->base.mode = crtc->base.state->mode;
3317
3318         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3319                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3320                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3321
3322         if (HAS_DDI(dev))
3323                 intel_set_pipe_csc(&crtc->base);
3324
3325         /*
3326          * Update pipe size and adjust fitter if needed: the reason for this is
3327          * that in compute_mode_changes we check the native mode (not the pfit
3328          * mode) to see if we can flip rather than do a full mode set. In the
3329          * fastboot case, we'll flip, but if we don't update the pipesrc and
3330          * pfit state, we'll end up with a big fb scanned out into the wrong
3331          * sized surface.
3332          */
3333
3334         I915_WRITE(PIPESRC(crtc->pipe),
3335                    ((pipe_config->pipe_src_w - 1) << 16) |
3336                    (pipe_config->pipe_src_h - 1));
3337
3338         /* on skylake this is done by detaching scalers */
3339         if (INTEL_INFO(dev)->gen >= 9) {
3340                 skl_detach_scalers(crtc);
3341
3342                 if (pipe_config->pch_pfit.enabled)
3343                         skylake_pfit_enable(crtc);
3344         } else if (HAS_PCH_SPLIT(dev)) {
3345                 if (pipe_config->pch_pfit.enabled)
3346                         ironlake_pfit_enable(crtc);
3347                 else if (old_crtc_state->pch_pfit.enabled)
3348                         ironlake_pfit_disable(crtc, true);
3349         }
3350 }
3351
3352 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3353 {
3354         struct drm_device *dev = crtc->dev;
3355         struct drm_i915_private *dev_priv = dev->dev_private;
3356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357         int pipe = intel_crtc->pipe;
3358         u32 reg, temp;
3359
3360         /* enable normal train */
3361         reg = FDI_TX_CTL(pipe);
3362         temp = I915_READ(reg);
3363         if (IS_IVYBRIDGE(dev)) {
3364                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3365                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3366         } else {
3367                 temp &= ~FDI_LINK_TRAIN_NONE;
3368                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3369         }
3370         I915_WRITE(reg, temp);
3371
3372         reg = FDI_RX_CTL(pipe);
3373         temp = I915_READ(reg);
3374         if (HAS_PCH_CPT(dev)) {
3375                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3376                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3377         } else {
3378                 temp &= ~FDI_LINK_TRAIN_NONE;
3379                 temp |= FDI_LINK_TRAIN_NONE;
3380         }
3381         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3382
3383         /* wait one idle pattern time */
3384         POSTING_READ(reg);
3385         udelay(1000);
3386
3387         /* IVB wants error correction enabled */
3388         if (IS_IVYBRIDGE(dev))
3389                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3390                            FDI_FE_ERRC_ENABLE);
3391 }
3392
3393 /* The FDI link training functions for ILK/Ibexpeak. */
3394 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3395 {
3396         struct drm_device *dev = crtc->dev;
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399         int pipe = intel_crtc->pipe;
3400         u32 reg, temp, tries;
3401
3402         /* FDI needs bits from pipe first */
3403         assert_pipe_enabled(dev_priv, pipe);
3404
3405         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3406            for train result */
3407         reg = FDI_RX_IMR(pipe);
3408         temp = I915_READ(reg);
3409         temp &= ~FDI_RX_SYMBOL_LOCK;
3410         temp &= ~FDI_RX_BIT_LOCK;
3411         I915_WRITE(reg, temp);
3412         I915_READ(reg);
3413         udelay(150);
3414
3415         /* enable CPU FDI TX and PCH FDI RX */
3416         reg = FDI_TX_CTL(pipe);
3417         temp = I915_READ(reg);
3418         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3419         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3420         temp &= ~FDI_LINK_TRAIN_NONE;
3421         temp |= FDI_LINK_TRAIN_PATTERN_1;
3422         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3423
3424         reg = FDI_RX_CTL(pipe);
3425         temp = I915_READ(reg);
3426         temp &= ~FDI_LINK_TRAIN_NONE;
3427         temp |= FDI_LINK_TRAIN_PATTERN_1;
3428         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3429
3430         POSTING_READ(reg);
3431         udelay(150);
3432
3433         /* Ironlake workaround, enable clock pointer after FDI enable*/
3434         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3435         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3436                    FDI_RX_PHASE_SYNC_POINTER_EN);
3437
3438         reg = FDI_RX_IIR(pipe);
3439         for (tries = 0; tries < 5; tries++) {
3440                 temp = I915_READ(reg);
3441                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3442
3443                 if ((temp & FDI_RX_BIT_LOCK)) {
3444                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3445                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3446                         break;
3447                 }
3448         }
3449         if (tries == 5)
3450                 DRM_ERROR("FDI train 1 fail!\n");
3451
3452         /* Train 2 */
3453         reg = FDI_TX_CTL(pipe);
3454         temp = I915_READ(reg);
3455         temp &= ~FDI_LINK_TRAIN_NONE;
3456         temp |= FDI_LINK_TRAIN_PATTERN_2;
3457         I915_WRITE(reg, temp);
3458
3459         reg = FDI_RX_CTL(pipe);
3460         temp = I915_READ(reg);
3461         temp &= ~FDI_LINK_TRAIN_NONE;
3462         temp |= FDI_LINK_TRAIN_PATTERN_2;
3463         I915_WRITE(reg, temp);
3464
3465         POSTING_READ(reg);
3466         udelay(150);
3467
3468         reg = FDI_RX_IIR(pipe);
3469         for (tries = 0; tries < 5; tries++) {
3470                 temp = I915_READ(reg);
3471                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3472
3473                 if (temp & FDI_RX_SYMBOL_LOCK) {
3474                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3475                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3476                         break;
3477                 }
3478         }
3479         if (tries == 5)
3480                 DRM_ERROR("FDI train 2 fail!\n");
3481
3482         DRM_DEBUG_KMS("FDI train done\n");
3483
3484 }
3485
3486 static const int snb_b_fdi_train_param[] = {
3487         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3488         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3489         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3490         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3491 };
3492
3493 /* The FDI link training functions for SNB/Cougarpoint. */
3494 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3495 {
3496         struct drm_device *dev = crtc->dev;
3497         struct drm_i915_private *dev_priv = dev->dev_private;
3498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499         int pipe = intel_crtc->pipe;
3500         u32 reg, temp, i, retry;
3501
3502         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3503            for train result */
3504         reg = FDI_RX_IMR(pipe);
3505         temp = I915_READ(reg);
3506         temp &= ~FDI_RX_SYMBOL_LOCK;
3507         temp &= ~FDI_RX_BIT_LOCK;
3508         I915_WRITE(reg, temp);
3509
3510         POSTING_READ(reg);
3511         udelay(150);
3512
3513         /* enable CPU FDI TX and PCH FDI RX */
3514         reg = FDI_TX_CTL(pipe);
3515         temp = I915_READ(reg);
3516         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3517         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3518         temp &= ~FDI_LINK_TRAIN_NONE;
3519         temp |= FDI_LINK_TRAIN_PATTERN_1;
3520         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3521         /* SNB-B */
3522         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3523         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3524
3525         I915_WRITE(FDI_RX_MISC(pipe),
3526                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3527
3528         reg = FDI_RX_CTL(pipe);
3529         temp = I915_READ(reg);
3530         if (HAS_PCH_CPT(dev)) {
3531                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3532                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3533         } else {
3534                 temp &= ~FDI_LINK_TRAIN_NONE;
3535                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3536         }
3537         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3538
3539         POSTING_READ(reg);
3540         udelay(150);
3541
3542         for (i = 0; i < 4; i++) {
3543                 reg = FDI_TX_CTL(pipe);
3544                 temp = I915_READ(reg);
3545                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3546                 temp |= snb_b_fdi_train_param[i];
3547                 I915_WRITE(reg, temp);
3548
3549                 POSTING_READ(reg);
3550                 udelay(500);
3551
3552                 for (retry = 0; retry < 5; retry++) {
3553                         reg = FDI_RX_IIR(pipe);
3554                         temp = I915_READ(reg);
3555                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3556                         if (temp & FDI_RX_BIT_LOCK) {
3557                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3558                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3559                                 break;
3560                         }
3561                         udelay(50);
3562                 }
3563                 if (retry < 5)
3564                         break;
3565         }
3566         if (i == 4)
3567                 DRM_ERROR("FDI train 1 fail!\n");
3568
3569         /* Train 2 */
3570         reg = FDI_TX_CTL(pipe);
3571         temp = I915_READ(reg);
3572         temp &= ~FDI_LINK_TRAIN_NONE;
3573         temp |= FDI_LINK_TRAIN_PATTERN_2;
3574         if (IS_GEN6(dev)) {
3575                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3576                 /* SNB-B */
3577                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3578         }
3579         I915_WRITE(reg, temp);
3580
3581         reg = FDI_RX_CTL(pipe);
3582         temp = I915_READ(reg);
3583         if (HAS_PCH_CPT(dev)) {
3584                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3585                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3586         } else {
3587                 temp &= ~FDI_LINK_TRAIN_NONE;
3588                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3589         }
3590         I915_WRITE(reg, temp);
3591
3592         POSTING_READ(reg);
3593         udelay(150);
3594
3595         for (i = 0; i < 4; i++) {
3596                 reg = FDI_TX_CTL(pipe);
3597                 temp = I915_READ(reg);
3598                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3599                 temp |= snb_b_fdi_train_param[i];
3600                 I915_WRITE(reg, temp);
3601
3602                 POSTING_READ(reg);
3603                 udelay(500);
3604
3605                 for (retry = 0; retry < 5; retry++) {
3606                         reg = FDI_RX_IIR(pipe);
3607                         temp = I915_READ(reg);
3608                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3609                         if (temp & FDI_RX_SYMBOL_LOCK) {
3610                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3611                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3612                                 break;
3613                         }
3614                         udelay(50);
3615                 }
3616                 if (retry < 5)
3617                         break;
3618         }
3619         if (i == 4)
3620                 DRM_ERROR("FDI train 2 fail!\n");
3621
3622         DRM_DEBUG_KMS("FDI train done.\n");
3623 }
3624
3625 /* Manual link training for Ivy Bridge A0 parts */
3626 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3627 {
3628         struct drm_device *dev = crtc->dev;
3629         struct drm_i915_private *dev_priv = dev->dev_private;
3630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631         int pipe = intel_crtc->pipe;
3632         u32 reg, temp, i, j;
3633
3634         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3635            for train result */
3636         reg = FDI_RX_IMR(pipe);
3637         temp = I915_READ(reg);
3638         temp &= ~FDI_RX_SYMBOL_LOCK;
3639         temp &= ~FDI_RX_BIT_LOCK;
3640         I915_WRITE(reg, temp);
3641
3642         POSTING_READ(reg);
3643         udelay(150);
3644
3645         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3646                       I915_READ(FDI_RX_IIR(pipe)));
3647
3648         /* Try each vswing and preemphasis setting twice before moving on */
3649         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3650                 /* disable first in case we need to retry */
3651                 reg = FDI_TX_CTL(pipe);
3652                 temp = I915_READ(reg);
3653                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3654                 temp &= ~FDI_TX_ENABLE;
3655                 I915_WRITE(reg, temp);
3656
3657                 reg = FDI_RX_CTL(pipe);
3658                 temp = I915_READ(reg);
3659                 temp &= ~FDI_LINK_TRAIN_AUTO;
3660                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3661                 temp &= ~FDI_RX_ENABLE;
3662                 I915_WRITE(reg, temp);
3663
3664                 /* enable CPU FDI TX and PCH FDI RX */
3665                 reg = FDI_TX_CTL(pipe);
3666                 temp = I915_READ(reg);
3667                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3668                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3669                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3670                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3671                 temp |= snb_b_fdi_train_param[j/2];
3672                 temp |= FDI_COMPOSITE_SYNC;
3673                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3674
3675                 I915_WRITE(FDI_RX_MISC(pipe),
3676                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3677
3678                 reg = FDI_RX_CTL(pipe);
3679                 temp = I915_READ(reg);
3680                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3681                 temp |= FDI_COMPOSITE_SYNC;
3682                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3683
3684                 POSTING_READ(reg);
3685                 udelay(1); /* should be 0.5us */
3686
3687                 for (i = 0; i < 4; i++) {
3688                         reg = FDI_RX_IIR(pipe);
3689                         temp = I915_READ(reg);
3690                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3691
3692                         if (temp & FDI_RX_BIT_LOCK ||
3693                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3694                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3695                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3696                                               i);
3697                                 break;
3698                         }
3699                         udelay(1); /* should be 0.5us */
3700                 }
3701                 if (i == 4) {
3702                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3703                         continue;
3704                 }
3705
3706                 /* Train 2 */
3707                 reg = FDI_TX_CTL(pipe);
3708                 temp = I915_READ(reg);
3709                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3710                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3711                 I915_WRITE(reg, temp);
3712
3713                 reg = FDI_RX_CTL(pipe);
3714                 temp = I915_READ(reg);
3715                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3716                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3717                 I915_WRITE(reg, temp);
3718
3719                 POSTING_READ(reg);
3720                 udelay(2); /* should be 1.5us */
3721
3722                 for (i = 0; i < 4; i++) {
3723                         reg = FDI_RX_IIR(pipe);
3724                         temp = I915_READ(reg);
3725                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3726
3727                         if (temp & FDI_RX_SYMBOL_LOCK ||
3728                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3729                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3730                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3731                                               i);
3732                                 goto train_done;
3733                         }
3734                         udelay(2); /* should be 1.5us */
3735                 }
3736                 if (i == 4)
3737                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3738         }
3739
3740 train_done:
3741         DRM_DEBUG_KMS("FDI train done.\n");
3742 }
3743
3744 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3745 {
3746         struct drm_device *dev = intel_crtc->base.dev;
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748         int pipe = intel_crtc->pipe;
3749         u32 reg, temp;
3750
3751
3752         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3753         reg = FDI_RX_CTL(pipe);
3754         temp = I915_READ(reg);
3755         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3756         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3757         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3758         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3759
3760         POSTING_READ(reg);
3761         udelay(200);
3762
3763         /* Switch from Rawclk to PCDclk */
3764         temp = I915_READ(reg);
3765         I915_WRITE(reg, temp | FDI_PCDCLK);
3766
3767         POSTING_READ(reg);
3768         udelay(200);
3769
3770         /* Enable CPU FDI TX PLL, always on for Ironlake */
3771         reg = FDI_TX_CTL(pipe);
3772         temp = I915_READ(reg);
3773         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3774                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3775
3776                 POSTING_READ(reg);
3777                 udelay(100);
3778         }
3779 }
3780
3781 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3782 {
3783         struct drm_device *dev = intel_crtc->base.dev;
3784         struct drm_i915_private *dev_priv = dev->dev_private;
3785         int pipe = intel_crtc->pipe;
3786         u32 reg, temp;
3787
3788         /* Switch from PCDclk to Rawclk */
3789         reg = FDI_RX_CTL(pipe);
3790         temp = I915_READ(reg);
3791         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3792
3793         /* Disable CPU FDI TX PLL */
3794         reg = FDI_TX_CTL(pipe);
3795         temp = I915_READ(reg);
3796         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3797
3798         POSTING_READ(reg);
3799         udelay(100);
3800
3801         reg = FDI_RX_CTL(pipe);
3802         temp = I915_READ(reg);
3803         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3804
3805         /* Wait for the clocks to turn off. */
3806         POSTING_READ(reg);
3807         udelay(100);
3808 }
3809
3810 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3811 {
3812         struct drm_device *dev = crtc->dev;
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3815         int pipe = intel_crtc->pipe;
3816         u32 reg, temp;
3817
3818         /* disable CPU FDI tx and PCH FDI rx */
3819         reg = FDI_TX_CTL(pipe);
3820         temp = I915_READ(reg);
3821         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3822         POSTING_READ(reg);
3823
3824         reg = FDI_RX_CTL(pipe);
3825         temp = I915_READ(reg);
3826         temp &= ~(0x7 << 16);
3827         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3828         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3829
3830         POSTING_READ(reg);
3831         udelay(100);
3832
3833         /* Ironlake workaround, disable clock pointer after downing FDI */
3834         if (HAS_PCH_IBX(dev))
3835                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3836
3837         /* still set train pattern 1 */
3838         reg = FDI_TX_CTL(pipe);
3839         temp = I915_READ(reg);
3840         temp &= ~FDI_LINK_TRAIN_NONE;
3841         temp |= FDI_LINK_TRAIN_PATTERN_1;
3842         I915_WRITE(reg, temp);
3843
3844         reg = FDI_RX_CTL(pipe);
3845         temp = I915_READ(reg);
3846         if (HAS_PCH_CPT(dev)) {
3847                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3848                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3849         } else {
3850                 temp &= ~FDI_LINK_TRAIN_NONE;
3851                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3852         }
3853         /* BPC in FDI rx is consistent with that in PIPECONF */
3854         temp &= ~(0x07 << 16);
3855         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3856         I915_WRITE(reg, temp);
3857
3858         POSTING_READ(reg);
3859         udelay(100);
3860 }
3861
3862 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3863 {
3864         struct intel_crtc *crtc;
3865
3866         /* Note that we don't need to be called with mode_config.lock here
3867          * as our list of CRTC objects is static for the lifetime of the
3868          * device and so cannot disappear as we iterate. Similarly, we can
3869          * happily treat the predicates as racy, atomic checks as userspace
3870          * cannot claim and pin a new fb without at least acquring the
3871          * struct_mutex and so serialising with us.
3872          */
3873         for_each_intel_crtc(dev, crtc) {
3874                 if (atomic_read(&crtc->unpin_work_count) == 0)
3875                         continue;
3876
3877                 if (crtc->unpin_work)
3878                         intel_wait_for_vblank(dev, crtc->pipe);
3879
3880                 return true;
3881         }
3882
3883         return false;
3884 }
3885
3886 static void page_flip_completed(struct intel_crtc *intel_crtc)
3887 {
3888         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3889         struct intel_unpin_work *work = intel_crtc->unpin_work;
3890
3891         /* ensure that the unpin work is consistent wrt ->pending. */
3892         smp_rmb();
3893         intel_crtc->unpin_work = NULL;
3894
3895         if (work->event)
3896                 drm_send_vblank_event(intel_crtc->base.dev,
3897                                       intel_crtc->pipe,
3898                                       work->event);
3899
3900         drm_crtc_vblank_put(&intel_crtc->base);
3901
3902         wake_up_all(&dev_priv->pending_flip_queue);
3903         queue_work(dev_priv->wq, &work->work);
3904
3905         trace_i915_flip_complete(intel_crtc->plane,
3906                                  work->pending_flip_obj);
3907 }
3908
3909 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3910 {
3911         struct drm_device *dev = crtc->dev;
3912         struct drm_i915_private *dev_priv = dev->dev_private;
3913
3914         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3915         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3916                                        !intel_crtc_has_pending_flip(crtc),
3917                                        60*HZ) == 0)) {
3918                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3919
3920                 spin_lock_irq(&dev->event_lock);
3921                 if (intel_crtc->unpin_work) {
3922                         WARN_ONCE(1, "Removing stuck page flip\n");
3923                         page_flip_completed(intel_crtc);
3924                 }
3925                 spin_unlock_irq(&dev->event_lock);
3926         }
3927
3928         if (crtc->primary->fb) {
3929                 mutex_lock(&dev->struct_mutex);
3930                 intel_finish_fb(crtc->primary->fb);
3931                 mutex_unlock(&dev->struct_mutex);
3932         }
3933 }
3934
3935 /* Program iCLKIP clock to the desired frequency */
3936 static void lpt_program_iclkip(struct drm_crtc *crtc)
3937 {
3938         struct drm_device *dev = crtc->dev;
3939         struct drm_i915_private *dev_priv = dev->dev_private;
3940         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3941         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3942         u32 temp;
3943
3944         mutex_lock(&dev_priv->sb_lock);
3945
3946         /* It is necessary to ungate the pixclk gate prior to programming
3947          * the divisors, and gate it back when it is done.
3948          */
3949         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3950
3951         /* Disable SSCCTL */
3952         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3953                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3954                                 SBI_SSCCTL_DISABLE,
3955                         SBI_ICLK);
3956
3957         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3958         if (clock == 20000) {
3959                 auxdiv = 1;
3960                 divsel = 0x41;
3961                 phaseinc = 0x20;
3962         } else {
3963                 /* The iCLK virtual clock root frequency is in MHz,
3964                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3965                  * divisors, it is necessary to divide one by another, so we
3966                  * convert the virtual clock precision to KHz here for higher
3967                  * precision.
3968                  */
3969                 u32 iclk_virtual_root_freq = 172800 * 1000;
3970                 u32 iclk_pi_range = 64;
3971                 u32 desired_divisor, msb_divisor_value, pi_value;
3972
3973                 desired_divisor = (iclk_virtual_root_freq / clock);
3974                 msb_divisor_value = desired_divisor / iclk_pi_range;
3975                 pi_value = desired_divisor % iclk_pi_range;
3976
3977                 auxdiv = 0;
3978                 divsel = msb_divisor_value - 2;
3979                 phaseinc = pi_value;
3980         }
3981
3982         /* This should not happen with any sane values */
3983         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3984                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3985         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3986                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3987
3988         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3989                         clock,
3990                         auxdiv,
3991                         divsel,
3992                         phasedir,
3993                         phaseinc);
3994
3995         /* Program SSCDIVINTPHASE6 */
3996         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3997         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3998         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3999         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4000         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4001         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4002         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4003         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4004
4005         /* Program SSCAUXDIV */
4006         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4007         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4008         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4009         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4010
4011         /* Enable modulator and associated divider */
4012         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4013         temp &= ~SBI_SSCCTL_DISABLE;
4014         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4015
4016         /* Wait for initialization time */
4017         udelay(24);
4018
4019         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4020
4021         mutex_unlock(&dev_priv->sb_lock);
4022 }
4023
4024 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4025                                                 enum pipe pch_transcoder)
4026 {
4027         struct drm_device *dev = crtc->base.dev;
4028         struct drm_i915_private *dev_priv = dev->dev_private;
4029         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4030
4031         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4032                    I915_READ(HTOTAL(cpu_transcoder)));
4033         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4034                    I915_READ(HBLANK(cpu_transcoder)));
4035         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4036                    I915_READ(HSYNC(cpu_transcoder)));
4037
4038         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4039                    I915_READ(VTOTAL(cpu_transcoder)));
4040         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4041                    I915_READ(VBLANK(cpu_transcoder)));
4042         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4043                    I915_READ(VSYNC(cpu_transcoder)));
4044         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4045                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4046 }
4047
4048 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4049 {
4050         struct drm_i915_private *dev_priv = dev->dev_private;
4051         uint32_t temp;
4052
4053         temp = I915_READ(SOUTH_CHICKEN1);
4054         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4055                 return;
4056
4057         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4058         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4059
4060         temp &= ~FDI_BC_BIFURCATION_SELECT;
4061         if (enable)
4062                 temp |= FDI_BC_BIFURCATION_SELECT;
4063
4064         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4065         I915_WRITE(SOUTH_CHICKEN1, temp);
4066         POSTING_READ(SOUTH_CHICKEN1);
4067 }
4068
4069 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4070 {
4071         struct drm_device *dev = intel_crtc->base.dev;
4072
4073         switch (intel_crtc->pipe) {
4074         case PIPE_A:
4075                 break;
4076         case PIPE_B:
4077                 if (intel_crtc->config->fdi_lanes > 2)
4078                         cpt_set_fdi_bc_bifurcation(dev, false);
4079                 else
4080                         cpt_set_fdi_bc_bifurcation(dev, true);
4081
4082                 break;
4083         case PIPE_C:
4084                 cpt_set_fdi_bc_bifurcation(dev, true);
4085
4086                 break;
4087         default:
4088                 BUG();
4089         }
4090 }
4091
4092 /*
4093  * Enable PCH resources required for PCH ports:
4094  *   - PCH PLLs
4095  *   - FDI training & RX/TX
4096  *   - update transcoder timings
4097  *   - DP transcoding bits
4098  *   - transcoder
4099  */
4100 static void ironlake_pch_enable(struct drm_crtc *crtc)
4101 {
4102         struct drm_device *dev = crtc->dev;
4103         struct drm_i915_private *dev_priv = dev->dev_private;
4104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105         int pipe = intel_crtc->pipe;
4106         u32 reg, temp;
4107
4108         assert_pch_transcoder_disabled(dev_priv, pipe);
4109
4110         if (IS_IVYBRIDGE(dev))
4111                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4112
4113         /* Write the TU size bits before fdi link training, so that error
4114          * detection works. */
4115         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4116                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4117
4118         /* For PCH output, training FDI link */
4119         dev_priv->display.fdi_link_train(crtc);
4120
4121         /* We need to program the right clock selection before writing the pixel
4122          * mutliplier into the DPLL. */
4123         if (HAS_PCH_CPT(dev)) {
4124                 u32 sel;
4125
4126                 temp = I915_READ(PCH_DPLL_SEL);
4127                 temp |= TRANS_DPLL_ENABLE(pipe);
4128                 sel = TRANS_DPLLB_SEL(pipe);
4129                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4130                         temp |= sel;
4131                 else
4132                         temp &= ~sel;
4133                 I915_WRITE(PCH_DPLL_SEL, temp);
4134         }
4135
4136         /* XXX: pch pll's can be enabled any time before we enable the PCH
4137          * transcoder, and we actually should do this to not upset any PCH
4138          * transcoder that already use the clock when we share it.
4139          *
4140          * Note that enable_shared_dpll tries to do the right thing, but
4141          * get_shared_dpll unconditionally resets the pll - we need that to have
4142          * the right LVDS enable sequence. */
4143         intel_enable_shared_dpll(intel_crtc);
4144
4145         /* set transcoder timing, panel must allow it */
4146         assert_panel_unlocked(dev_priv, pipe);
4147         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4148
4149         intel_fdi_normal_train(crtc);
4150
4151         /* For PCH DP, enable TRANS_DP_CTL */
4152         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4153                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4154                 reg = TRANS_DP_CTL(pipe);
4155                 temp = I915_READ(reg);
4156                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4157                           TRANS_DP_SYNC_MASK |
4158                           TRANS_DP_BPC_MASK);
4159                 temp |= TRANS_DP_OUTPUT_ENABLE;
4160                 temp |= bpc << 9; /* same format but at 11:9 */
4161
4162                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4163                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4164                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4165                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4166
4167                 switch (intel_trans_dp_port_sel(crtc)) {
4168                 case PCH_DP_B:
4169                         temp |= TRANS_DP_PORT_SEL_B;
4170                         break;
4171                 case PCH_DP_C:
4172                         temp |= TRANS_DP_PORT_SEL_C;
4173                         break;
4174                 case PCH_DP_D:
4175                         temp |= TRANS_DP_PORT_SEL_D;
4176                         break;
4177                 default:
4178                         BUG();
4179                 }
4180
4181                 I915_WRITE(reg, temp);
4182         }
4183
4184         ironlake_enable_pch_transcoder(dev_priv, pipe);
4185 }
4186
4187 static void lpt_pch_enable(struct drm_crtc *crtc)
4188 {
4189         struct drm_device *dev = crtc->dev;
4190         struct drm_i915_private *dev_priv = dev->dev_private;
4191         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4192         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4193
4194         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4195
4196         lpt_program_iclkip(crtc);
4197
4198         /* Set transcoder timing. */
4199         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4200
4201         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4202 }
4203
4204 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4205                                                 struct intel_crtc_state *crtc_state)
4206 {
4207         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4208         struct intel_shared_dpll *pll;
4209         struct intel_shared_dpll_config *shared_dpll;
4210         enum intel_dpll_id i;
4211
4212         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4213
4214         if (HAS_PCH_IBX(dev_priv->dev)) {
4215                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4216                 i = (enum intel_dpll_id) crtc->pipe;
4217                 pll = &dev_priv->shared_dplls[i];
4218
4219                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4220                               crtc->base.base.id, pll->name);
4221
4222                 WARN_ON(shared_dpll[i].crtc_mask);
4223
4224                 goto found;
4225         }
4226
4227         if (IS_BROXTON(dev_priv->dev)) {
4228                 /* PLL is attached to port in bxt */
4229                 struct intel_encoder *encoder;
4230                 struct intel_digital_port *intel_dig_port;
4231
4232                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4233                 if (WARN_ON(!encoder))
4234                         return NULL;
4235
4236                 intel_dig_port = enc_to_dig_port(&encoder->base);
4237                 /* 1:1 mapping between ports and PLLs */
4238                 i = (enum intel_dpll_id)intel_dig_port->port;
4239                 pll = &dev_priv->shared_dplls[i];
4240                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4241                         crtc->base.base.id, pll->name);
4242                 WARN_ON(shared_dpll[i].crtc_mask);
4243
4244                 goto found;
4245         }
4246
4247         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4248                 pll = &dev_priv->shared_dplls[i];
4249
4250                 /* Only want to check enabled timings first */
4251                 if (shared_dpll[i].crtc_mask == 0)
4252                         continue;
4253
4254                 if (memcmp(&crtc_state->dpll_hw_state,
4255                            &shared_dpll[i].hw_state,
4256                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4257                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4258                                       crtc->base.base.id, pll->name,
4259                                       shared_dpll[i].crtc_mask,
4260                                       pll->active);
4261                         goto found;
4262                 }
4263         }
4264
4265         /* Ok no matching timings, maybe there's a free one? */
4266         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4267                 pll = &dev_priv->shared_dplls[i];
4268                 if (shared_dpll[i].crtc_mask == 0) {
4269                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4270                                       crtc->base.base.id, pll->name);
4271                         goto found;
4272                 }
4273         }
4274
4275         return NULL;
4276
4277 found:
4278         if (shared_dpll[i].crtc_mask == 0)
4279                 shared_dpll[i].hw_state =
4280                         crtc_state->dpll_hw_state;
4281
4282         crtc_state->shared_dpll = i;
4283         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4284                          pipe_name(crtc->pipe));
4285
4286         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4287
4288         return pll;
4289 }
4290
4291 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4292 {
4293         struct drm_i915_private *dev_priv = to_i915(state->dev);
4294         struct intel_shared_dpll_config *shared_dpll;
4295         struct intel_shared_dpll *pll;
4296         enum intel_dpll_id i;
4297
4298         if (!to_intel_atomic_state(state)->dpll_set)
4299                 return;
4300
4301         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4302         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4303                 pll = &dev_priv->shared_dplls[i];
4304                 pll->config = shared_dpll[i];
4305         }
4306 }
4307
4308 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4309 {
4310         struct drm_i915_private *dev_priv = dev->dev_private;
4311         int dslreg = PIPEDSL(pipe);
4312         u32 temp;
4313
4314         temp = I915_READ(dslreg);
4315         udelay(500);
4316         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4317                 if (wait_for(I915_READ(dslreg) != temp, 5))
4318                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4319         }
4320 }
4321
4322 static int
4323 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4324                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4325                   int src_w, int src_h, int dst_w, int dst_h)
4326 {
4327         struct intel_crtc_scaler_state *scaler_state =
4328                 &crtc_state->scaler_state;
4329         struct intel_crtc *intel_crtc =
4330                 to_intel_crtc(crtc_state->base.crtc);
4331         int need_scaling;
4332
4333         need_scaling = intel_rotation_90_or_270(rotation) ?
4334                 (src_h != dst_w || src_w != dst_h):
4335                 (src_w != dst_w || src_h != dst_h);
4336
4337         /*
4338          * if plane is being disabled or scaler is no more required or force detach
4339          *  - free scaler binded to this plane/crtc
4340          *  - in order to do this, update crtc->scaler_usage
4341          *
4342          * Here scaler state in crtc_state is set free so that
4343          * scaler can be assigned to other user. Actual register
4344          * update to free the scaler is done in plane/panel-fit programming.
4345          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4346          */
4347         if (force_detach || !need_scaling) {
4348                 if (*scaler_id >= 0) {
4349                         scaler_state->scaler_users &= ~(1 << scaler_user);
4350                         scaler_state->scalers[*scaler_id].in_use = 0;
4351
4352                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4353                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4354                                 intel_crtc->pipe, scaler_user, *scaler_id,
4355                                 scaler_state->scaler_users);
4356                         *scaler_id = -1;
4357                 }
4358                 return 0;
4359         }
4360
4361         /* range checks */
4362         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4363                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4364
4365                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4366                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4367                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4368                         "size is out of scaler range\n",
4369                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4370                 return -EINVAL;
4371         }
4372
4373         /* mark this plane as a scaler user in crtc_state */
4374         scaler_state->scaler_users |= (1 << scaler_user);
4375         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4376                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4377                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4378                 scaler_state->scaler_users);
4379
4380         return 0;
4381 }
4382
4383 /**
4384  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4385  *
4386  * @state: crtc's scaler state
4387  *
4388  * Return
4389  *     0 - scaler_usage updated successfully
4390  *    error - requested scaling cannot be supported or other error condition
4391  */
4392 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4393 {
4394         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4395         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4396
4397         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4398                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4399
4400         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4401                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4402                 state->pipe_src_w, state->pipe_src_h,
4403                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4404 }
4405
4406 /**
4407  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4408  *
4409  * @state: crtc's scaler state
4410  * @plane_state: atomic plane state to update
4411  *
4412  * Return
4413  *     0 - scaler_usage updated successfully
4414  *    error - requested scaling cannot be supported or other error condition
4415  */
4416 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4417                                    struct intel_plane_state *plane_state)
4418 {
4419
4420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4421         struct intel_plane *intel_plane =
4422                 to_intel_plane(plane_state->base.plane);
4423         struct drm_framebuffer *fb = plane_state->base.fb;
4424         int ret;
4425
4426         bool force_detach = !fb || !plane_state->visible;
4427
4428         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4429                       intel_plane->base.base.id, intel_crtc->pipe,
4430                       drm_plane_index(&intel_plane->base));
4431
4432         ret = skl_update_scaler(crtc_state, force_detach,
4433                                 drm_plane_index(&intel_plane->base),
4434                                 &plane_state->scaler_id,
4435                                 plane_state->base.rotation,
4436                                 drm_rect_width(&plane_state->src) >> 16,
4437                                 drm_rect_height(&plane_state->src) >> 16,
4438                                 drm_rect_width(&plane_state->dst),
4439                                 drm_rect_height(&plane_state->dst));
4440
4441         if (ret || plane_state->scaler_id < 0)
4442                 return ret;
4443
4444         /* check colorkey */
4445         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4446                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4447                               intel_plane->base.base.id);
4448                 return -EINVAL;
4449         }
4450
4451         /* Check src format */
4452         switch (fb->pixel_format) {
4453         case DRM_FORMAT_RGB565:
4454         case DRM_FORMAT_XBGR8888:
4455         case DRM_FORMAT_XRGB8888:
4456         case DRM_FORMAT_ABGR8888:
4457         case DRM_FORMAT_ARGB8888:
4458         case DRM_FORMAT_XRGB2101010:
4459         case DRM_FORMAT_XBGR2101010:
4460         case DRM_FORMAT_YUYV:
4461         case DRM_FORMAT_YVYU:
4462         case DRM_FORMAT_UYVY:
4463         case DRM_FORMAT_VYUY:
4464                 break;
4465         default:
4466                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4467                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4468                 return -EINVAL;
4469         }
4470
4471         return 0;
4472 }
4473
4474 static void skylake_scaler_disable(struct intel_crtc *crtc)
4475 {
4476         int i;
4477
4478         for (i = 0; i < crtc->num_scalers; i++)
4479                 skl_detach_scaler(crtc, i);
4480 }
4481
4482 static void skylake_pfit_enable(struct intel_crtc *crtc)
4483 {
4484         struct drm_device *dev = crtc->base.dev;
4485         struct drm_i915_private *dev_priv = dev->dev_private;
4486         int pipe = crtc->pipe;
4487         struct intel_crtc_scaler_state *scaler_state =
4488                 &crtc->config->scaler_state;
4489
4490         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4491
4492         if (crtc->config->pch_pfit.enabled) {
4493                 int id;
4494
4495                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4496                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4497                         return;
4498                 }
4499
4500                 id = scaler_state->scaler_id;
4501                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4502                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4503                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4504                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4505
4506                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4507         }
4508 }
4509
4510 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4511 {
4512         struct drm_device *dev = crtc->base.dev;
4513         struct drm_i915_private *dev_priv = dev->dev_private;
4514         int pipe = crtc->pipe;
4515
4516         if (crtc->config->pch_pfit.enabled) {
4517                 /* Force use of hard-coded filter coefficients
4518                  * as some pre-programmed values are broken,
4519                  * e.g. x201.
4520                  */
4521                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4522                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4523                                                  PF_PIPE_SEL_IVB(pipe));
4524                 else
4525                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4526                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4527                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4528         }
4529 }
4530
4531 void hsw_enable_ips(struct intel_crtc *crtc)
4532 {
4533         struct drm_device *dev = crtc->base.dev;
4534         struct drm_i915_private *dev_priv = dev->dev_private;
4535
4536         if (!crtc->config->ips_enabled)
4537                 return;
4538
4539         /* We can only enable IPS after we enable a plane and wait for a vblank */
4540         intel_wait_for_vblank(dev, crtc->pipe);
4541
4542         assert_plane_enabled(dev_priv, crtc->plane);
4543         if (IS_BROADWELL(dev)) {
4544                 mutex_lock(&dev_priv->rps.hw_lock);
4545                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4546                 mutex_unlock(&dev_priv->rps.hw_lock);
4547                 /* Quoting Art Runyan: "its not safe to expect any particular
4548                  * value in IPS_CTL bit 31 after enabling IPS through the
4549                  * mailbox." Moreover, the mailbox may return a bogus state,
4550                  * so we need to just enable it and continue on.
4551                  */
4552         } else {
4553                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4554                 /* The bit only becomes 1 in the next vblank, so this wait here
4555                  * is essentially intel_wait_for_vblank. If we don't have this
4556                  * and don't wait for vblanks until the end of crtc_enable, then
4557                  * the HW state readout code will complain that the expected
4558                  * IPS_CTL value is not the one we read. */
4559                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4560                         DRM_ERROR("Timed out waiting for IPS enable\n");
4561         }
4562 }
4563
4564 void hsw_disable_ips(struct intel_crtc *crtc)
4565 {
4566         struct drm_device *dev = crtc->base.dev;
4567         struct drm_i915_private *dev_priv = dev->dev_private;
4568
4569         if (!crtc->config->ips_enabled)
4570                 return;
4571
4572         assert_plane_enabled(dev_priv, crtc->plane);
4573         if (IS_BROADWELL(dev)) {
4574                 mutex_lock(&dev_priv->rps.hw_lock);
4575                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4576                 mutex_unlock(&dev_priv->rps.hw_lock);
4577                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4578                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4579                         DRM_ERROR("Timed out waiting for IPS disable\n");
4580         } else {
4581                 I915_WRITE(IPS_CTL, 0);
4582                 POSTING_READ(IPS_CTL);
4583         }
4584
4585         /* We need to wait for a vblank before we can disable the plane. */
4586         intel_wait_for_vblank(dev, crtc->pipe);
4587 }
4588
4589 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4590 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4591 {
4592         struct drm_device *dev = crtc->dev;
4593         struct drm_i915_private *dev_priv = dev->dev_private;
4594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4595         enum pipe pipe = intel_crtc->pipe;
4596         int i;
4597         bool reenable_ips = false;
4598
4599         /* The clocks have to be on to load the palette. */
4600         if (!crtc->state->active)
4601                 return;
4602
4603         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4604                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4605                         assert_dsi_pll_enabled(dev_priv);
4606                 else
4607                         assert_pll_enabled(dev_priv, pipe);
4608         }
4609
4610         /* Workaround : Do not read or write the pipe palette/gamma data while
4611          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4612          */
4613         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4614             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4615              GAMMA_MODE_MODE_SPLIT)) {
4616                 hsw_disable_ips(intel_crtc);
4617                 reenable_ips = true;
4618         }
4619
4620         for (i = 0; i < 256; i++) {
4621                 u32 palreg;
4622
4623                 if (HAS_GMCH_DISPLAY(dev))
4624                         palreg = PALETTE(pipe, i);
4625                 else
4626                         palreg = LGC_PALETTE(pipe, i);
4627
4628                 I915_WRITE(palreg,
4629                            (intel_crtc->lut_r[i] << 16) |
4630                            (intel_crtc->lut_g[i] << 8) |
4631                            intel_crtc->lut_b[i]);
4632         }
4633
4634         if (reenable_ips)
4635                 hsw_enable_ips(intel_crtc);
4636 }
4637
4638 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4639 {
4640         if (intel_crtc->overlay) {
4641                 struct drm_device *dev = intel_crtc->base.dev;
4642                 struct drm_i915_private *dev_priv = dev->dev_private;
4643
4644                 mutex_lock(&dev->struct_mutex);
4645                 dev_priv->mm.interruptible = false;
4646                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4647                 dev_priv->mm.interruptible = true;
4648                 mutex_unlock(&dev->struct_mutex);
4649         }
4650
4651         /* Let userspace switch the overlay on again. In most cases userspace
4652          * has to recompute where to put it anyway.
4653          */
4654 }
4655
4656 /**
4657  * intel_post_enable_primary - Perform operations after enabling primary plane
4658  * @crtc: the CRTC whose primary plane was just enabled
4659  *
4660  * Performs potentially sleeping operations that must be done after the primary
4661  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4662  * called due to an explicit primary plane update, or due to an implicit
4663  * re-enable that is caused when a sprite plane is updated to no longer
4664  * completely hide the primary plane.
4665  */
4666 static void
4667 intel_post_enable_primary(struct drm_crtc *crtc)
4668 {
4669         struct drm_device *dev = crtc->dev;
4670         struct drm_i915_private *dev_priv = dev->dev_private;
4671         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4672         int pipe = intel_crtc->pipe;
4673
4674         /*
4675          * BDW signals flip done immediately if the plane
4676          * is disabled, even if the plane enable is already
4677          * armed to occur at the next vblank :(
4678          */
4679         if (IS_BROADWELL(dev))
4680                 intel_wait_for_vblank(dev, pipe);
4681
4682         /*
4683          * FIXME IPS should be fine as long as one plane is
4684          * enabled, but in practice it seems to have problems
4685          * when going from primary only to sprite only and vice
4686          * versa.
4687          */
4688         hsw_enable_ips(intel_crtc);
4689
4690         /*
4691          * Gen2 reports pipe underruns whenever all planes are disabled.
4692          * So don't enable underrun reporting before at least some planes
4693          * are enabled.
4694          * FIXME: Need to fix the logic to work when we turn off all planes
4695          * but leave the pipe running.
4696          */
4697         if (IS_GEN2(dev))
4698                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4699
4700         /* Underruns don't raise interrupts, so check manually. */
4701         if (HAS_GMCH_DISPLAY(dev))
4702                 i9xx_check_fifo_underruns(dev_priv);
4703 }
4704
4705 /**
4706  * intel_pre_disable_primary - Perform operations before disabling primary plane
4707  * @crtc: the CRTC whose primary plane is to be disabled
4708  *
4709  * Performs potentially sleeping operations that must be done before the
4710  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4711  * be called due to an explicit primary plane update, or due to an implicit
4712  * disable that is caused when a sprite plane completely hides the primary
4713  * plane.
4714  */
4715 static void
4716 intel_pre_disable_primary(struct drm_crtc *crtc)
4717 {
4718         struct drm_device *dev = crtc->dev;
4719         struct drm_i915_private *dev_priv = dev->dev_private;
4720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4721         int pipe = intel_crtc->pipe;
4722
4723         /*
4724          * Gen2 reports pipe underruns whenever all planes are disabled.
4725          * So diasble underrun reporting before all the planes get disabled.
4726          * FIXME: Need to fix the logic to work when we turn off all planes
4727          * but leave the pipe running.
4728          */
4729         if (IS_GEN2(dev))
4730                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4731
4732         /*
4733          * Vblank time updates from the shadow to live plane control register
4734          * are blocked if the memory self-refresh mode is active at that
4735          * moment. So to make sure the plane gets truly disabled, disable
4736          * first the self-refresh mode. The self-refresh enable bit in turn
4737          * will be checked/applied by the HW only at the next frame start
4738          * event which is after the vblank start event, so we need to have a
4739          * wait-for-vblank between disabling the plane and the pipe.
4740          */
4741         if (HAS_GMCH_DISPLAY(dev)) {
4742                 intel_set_memory_cxsr(dev_priv, false);
4743                 dev_priv->wm.vlv.cxsr = false;
4744                 intel_wait_for_vblank(dev, pipe);
4745         }
4746
4747         /*
4748          * FIXME IPS should be fine as long as one plane is
4749          * enabled, but in practice it seems to have problems
4750          * when going from primary only to sprite only and vice
4751          * versa.
4752          */
4753         hsw_disable_ips(intel_crtc);
4754 }
4755
4756 static void intel_post_plane_update(struct intel_crtc *crtc)
4757 {
4758         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4759         struct drm_device *dev = crtc->base.dev;
4760         struct drm_i915_private *dev_priv = dev->dev_private;
4761         struct drm_plane *plane;
4762
4763         if (atomic->wait_vblank)
4764                 intel_wait_for_vblank(dev, crtc->pipe);
4765
4766         intel_frontbuffer_flip(dev, atomic->fb_bits);
4767
4768         if (atomic->disable_cxsr)
4769                 crtc->wm.cxsr_allowed = true;
4770
4771         if (crtc->atomic.update_wm_post)
4772                 intel_update_watermarks(&crtc->base);
4773
4774         if (atomic->update_fbc)
4775                 intel_fbc_update(dev_priv);
4776
4777         if (atomic->post_enable_primary)
4778                 intel_post_enable_primary(&crtc->base);
4779
4780         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4781                 intel_update_sprite_watermarks(plane, &crtc->base,
4782                                                0, 0, 0, false, false);
4783
4784         memset(atomic, 0, sizeof(*atomic));
4785 }
4786
4787 static void intel_pre_plane_update(struct intel_crtc *crtc)
4788 {
4789         struct drm_device *dev = crtc->base.dev;
4790         struct drm_i915_private *dev_priv = dev->dev_private;
4791         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4792         struct drm_plane *p;
4793
4794         /* Track fb's for any planes being disabled */
4795         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4796                 struct intel_plane *plane = to_intel_plane(p);
4797
4798                 mutex_lock(&dev->struct_mutex);
4799                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4800                                   plane->frontbuffer_bit);
4801                 mutex_unlock(&dev->struct_mutex);
4802         }
4803
4804         if (atomic->wait_for_flips)
4805                 intel_crtc_wait_for_pending_flips(&crtc->base);
4806
4807         if (atomic->disable_fbc)
4808                 intel_fbc_disable_crtc(crtc);
4809
4810         if (crtc->atomic.disable_ips)
4811                 hsw_disable_ips(crtc);
4812
4813         if (atomic->pre_disable_primary)
4814                 intel_pre_disable_primary(&crtc->base);
4815
4816         if (atomic->disable_cxsr) {
4817                 crtc->wm.cxsr_allowed = false;
4818                 intel_set_memory_cxsr(dev_priv, false);
4819         }
4820 }
4821
4822 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4823 {
4824         struct drm_device *dev = crtc->dev;
4825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4826         struct drm_plane *p;
4827         int pipe = intel_crtc->pipe;
4828
4829         intel_crtc_dpms_overlay_disable(intel_crtc);
4830
4831         drm_for_each_plane_mask(p, dev, plane_mask)
4832                 to_intel_plane(p)->disable_plane(p, crtc);
4833
4834         /*
4835          * FIXME: Once we grow proper nuclear flip support out of this we need
4836          * to compute the mask of flip planes precisely. For the time being
4837          * consider this a flip to a NULL plane.
4838          */
4839         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4840 }
4841
4842 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4843 {
4844         struct drm_device *dev = crtc->dev;
4845         struct drm_i915_private *dev_priv = dev->dev_private;
4846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4847         struct intel_encoder *encoder;
4848         int pipe = intel_crtc->pipe;
4849
4850         if (WARN_ON(intel_crtc->active))
4851                 return;
4852
4853         if (intel_crtc->config->has_pch_encoder)
4854                 intel_prepare_shared_dpll(intel_crtc);
4855
4856         if (intel_crtc->config->has_dp_encoder)
4857                 intel_dp_set_m_n(intel_crtc, M1_N1);
4858
4859         intel_set_pipe_timings(intel_crtc);
4860
4861         if (intel_crtc->config->has_pch_encoder) {
4862                 intel_cpu_transcoder_set_m_n(intel_crtc,
4863                                      &intel_crtc->config->fdi_m_n, NULL);
4864         }
4865
4866         ironlake_set_pipeconf(crtc);
4867
4868         intel_crtc->active = true;
4869
4870         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4871         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4872
4873         for_each_encoder_on_crtc(dev, crtc, encoder)
4874                 if (encoder->pre_enable)
4875                         encoder->pre_enable(encoder);
4876
4877         if (intel_crtc->config->has_pch_encoder) {
4878                 /* Note: FDI PLL enabling _must_ be done before we enable the
4879                  * cpu pipes, hence this is separate from all the other fdi/pch
4880                  * enabling. */
4881                 ironlake_fdi_pll_enable(intel_crtc);
4882         } else {
4883                 assert_fdi_tx_disabled(dev_priv, pipe);
4884                 assert_fdi_rx_disabled(dev_priv, pipe);
4885         }
4886
4887         ironlake_pfit_enable(intel_crtc);
4888
4889         /*
4890          * On ILK+ LUT must be loaded before the pipe is running but with
4891          * clocks enabled
4892          */
4893         intel_crtc_load_lut(crtc);
4894
4895         intel_update_watermarks(crtc);
4896         intel_enable_pipe(intel_crtc);
4897
4898         if (intel_crtc->config->has_pch_encoder)
4899                 ironlake_pch_enable(crtc);
4900
4901         assert_vblank_disabled(crtc);
4902         drm_crtc_vblank_on(crtc);
4903
4904         for_each_encoder_on_crtc(dev, crtc, encoder)
4905                 encoder->enable(encoder);
4906
4907         if (HAS_PCH_CPT(dev))
4908                 cpt_verify_modeset(dev, intel_crtc->pipe);
4909 }
4910
4911 /* IPS only exists on ULT machines and is tied to pipe A. */
4912 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4913 {
4914         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4915 }
4916
4917 static void haswell_crtc_enable(struct drm_crtc *crtc)
4918 {
4919         struct drm_device *dev = crtc->dev;
4920         struct drm_i915_private *dev_priv = dev->dev_private;
4921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4922         struct intel_encoder *encoder;
4923         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4924         struct intel_crtc_state *pipe_config =
4925                 to_intel_crtc_state(crtc->state);
4926
4927         if (WARN_ON(intel_crtc->active))
4928                 return;
4929
4930         if (intel_crtc_to_shared_dpll(intel_crtc))
4931                 intel_enable_shared_dpll(intel_crtc);
4932
4933         if (intel_crtc->config->has_dp_encoder)
4934                 intel_dp_set_m_n(intel_crtc, M1_N1);
4935
4936         intel_set_pipe_timings(intel_crtc);
4937
4938         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4939                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4940                            intel_crtc->config->pixel_multiplier - 1);
4941         }
4942
4943         if (intel_crtc->config->has_pch_encoder) {
4944                 intel_cpu_transcoder_set_m_n(intel_crtc,
4945                                      &intel_crtc->config->fdi_m_n, NULL);
4946         }
4947
4948         haswell_set_pipeconf(crtc);
4949
4950         intel_set_pipe_csc(crtc);
4951
4952         intel_crtc->active = true;
4953
4954         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4955         for_each_encoder_on_crtc(dev, crtc, encoder)
4956                 if (encoder->pre_enable)
4957                         encoder->pre_enable(encoder);
4958
4959         if (intel_crtc->config->has_pch_encoder) {
4960                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4961                                                       true);
4962                 dev_priv->display.fdi_link_train(crtc);
4963         }
4964
4965         intel_ddi_enable_pipe_clock(intel_crtc);
4966
4967         if (INTEL_INFO(dev)->gen >= 9)
4968                 skylake_pfit_enable(intel_crtc);
4969         else
4970                 ironlake_pfit_enable(intel_crtc);
4971
4972         /*
4973          * On ILK+ LUT must be loaded before the pipe is running but with
4974          * clocks enabled
4975          */
4976         intel_crtc_load_lut(crtc);
4977
4978         intel_ddi_set_pipe_settings(crtc);
4979         intel_ddi_enable_transcoder_func(crtc);
4980
4981         intel_update_watermarks(crtc);
4982         intel_enable_pipe(intel_crtc);
4983
4984         if (intel_crtc->config->has_pch_encoder)
4985                 lpt_pch_enable(crtc);
4986
4987         if (intel_crtc->config->dp_encoder_is_mst)
4988                 intel_ddi_set_vc_payload_alloc(crtc, true);
4989
4990         assert_vblank_disabled(crtc);
4991         drm_crtc_vblank_on(crtc);
4992
4993         for_each_encoder_on_crtc(dev, crtc, encoder) {
4994                 encoder->enable(encoder);
4995                 intel_opregion_notify_encoder(encoder, true);
4996         }
4997
4998         /* If we change the relative order between pipe/planes enabling, we need
4999          * to change the workaround. */
5000         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5001         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5002                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5003                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5004         }
5005 }
5006
5007 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5008 {
5009         struct drm_device *dev = crtc->base.dev;
5010         struct drm_i915_private *dev_priv = dev->dev_private;
5011         int pipe = crtc->pipe;
5012
5013         /* To avoid upsetting the power well on haswell only disable the pfit if
5014          * it's in use. The hw state code will make sure we get this right. */
5015         if (force || crtc->config->pch_pfit.enabled) {
5016                 I915_WRITE(PF_CTL(pipe), 0);
5017                 I915_WRITE(PF_WIN_POS(pipe), 0);
5018                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5019         }
5020 }
5021
5022 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5023 {
5024         struct drm_device *dev = crtc->dev;
5025         struct drm_i915_private *dev_priv = dev->dev_private;
5026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5027         struct intel_encoder *encoder;
5028         int pipe = intel_crtc->pipe;
5029         u32 reg, temp;
5030
5031         for_each_encoder_on_crtc(dev, crtc, encoder)
5032                 encoder->disable(encoder);
5033
5034         drm_crtc_vblank_off(crtc);
5035         assert_vblank_disabled(crtc);
5036
5037         if (intel_crtc->config->has_pch_encoder)
5038                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5039
5040         intel_disable_pipe(intel_crtc);
5041
5042         ironlake_pfit_disable(intel_crtc, false);
5043
5044         if (intel_crtc->config->has_pch_encoder)
5045                 ironlake_fdi_disable(crtc);
5046
5047         for_each_encoder_on_crtc(dev, crtc, encoder)
5048                 if (encoder->post_disable)
5049                         encoder->post_disable(encoder);
5050
5051         if (intel_crtc->config->has_pch_encoder) {
5052                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5053
5054                 if (HAS_PCH_CPT(dev)) {
5055                         /* disable TRANS_DP_CTL */
5056                         reg = TRANS_DP_CTL(pipe);
5057                         temp = I915_READ(reg);
5058                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5059                                   TRANS_DP_PORT_SEL_MASK);
5060                         temp |= TRANS_DP_PORT_SEL_NONE;
5061                         I915_WRITE(reg, temp);
5062
5063                         /* disable DPLL_SEL */
5064                         temp = I915_READ(PCH_DPLL_SEL);
5065                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5066                         I915_WRITE(PCH_DPLL_SEL, temp);
5067                 }
5068
5069                 ironlake_fdi_pll_disable(intel_crtc);
5070         }
5071
5072         intel_crtc->active = false;
5073         intel_update_watermarks(crtc);
5074 }
5075
5076 static void haswell_crtc_disable(struct drm_crtc *crtc)
5077 {
5078         struct drm_device *dev = crtc->dev;
5079         struct drm_i915_private *dev_priv = dev->dev_private;
5080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5081         struct intel_encoder *encoder;
5082         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5083
5084         for_each_encoder_on_crtc(dev, crtc, encoder) {
5085                 intel_opregion_notify_encoder(encoder, false);
5086                 encoder->disable(encoder);
5087         }
5088
5089         drm_crtc_vblank_off(crtc);
5090         assert_vblank_disabled(crtc);
5091
5092         if (intel_crtc->config->has_pch_encoder)
5093                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5094                                                       false);
5095         intel_disable_pipe(intel_crtc);
5096
5097         if (intel_crtc->config->dp_encoder_is_mst)
5098                 intel_ddi_set_vc_payload_alloc(crtc, false);
5099
5100         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5101
5102         if (INTEL_INFO(dev)->gen >= 9)
5103                 skylake_scaler_disable(intel_crtc);
5104         else
5105                 ironlake_pfit_disable(intel_crtc, false);
5106
5107         intel_ddi_disable_pipe_clock(intel_crtc);
5108
5109         if (intel_crtc->config->has_pch_encoder) {
5110                 lpt_disable_pch_transcoder(dev_priv);
5111                 intel_ddi_fdi_disable(crtc);
5112         }
5113
5114         for_each_encoder_on_crtc(dev, crtc, encoder)
5115                 if (encoder->post_disable)
5116                         encoder->post_disable(encoder);
5117
5118         intel_crtc->active = false;
5119         intel_update_watermarks(crtc);
5120 }
5121
5122 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5123 {
5124         struct drm_device *dev = crtc->base.dev;
5125         struct drm_i915_private *dev_priv = dev->dev_private;
5126         struct intel_crtc_state *pipe_config = crtc->config;
5127
5128         if (!pipe_config->gmch_pfit.control)
5129                 return;
5130
5131         /*
5132          * The panel fitter should only be adjusted whilst the pipe is disabled,
5133          * according to register description and PRM.
5134          */
5135         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5136         assert_pipe_disabled(dev_priv, crtc->pipe);
5137
5138         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5139         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5140
5141         /* Border color in case we don't scale up to the full screen. Black by
5142          * default, change to something else for debugging. */
5143         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5144 }
5145
5146 static enum intel_display_power_domain port_to_power_domain(enum port port)
5147 {
5148         switch (port) {
5149         case PORT_A:
5150                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5151         case PORT_B:
5152                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5153         case PORT_C:
5154                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5155         case PORT_D:
5156                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5157         case PORT_E:
5158                 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5159         default:
5160                 WARN_ON_ONCE(1);
5161                 return POWER_DOMAIN_PORT_OTHER;
5162         }
5163 }
5164
5165 #define for_each_power_domain(domain, mask)                             \
5166         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5167                 if ((1 << (domain)) & (mask))
5168
5169 enum intel_display_power_domain
5170 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5171 {
5172         struct drm_device *dev = intel_encoder->base.dev;
5173         struct intel_digital_port *intel_dig_port;
5174
5175         switch (intel_encoder->type) {
5176         case INTEL_OUTPUT_UNKNOWN:
5177                 /* Only DDI platforms should ever use this output type */
5178                 WARN_ON_ONCE(!HAS_DDI(dev));
5179         case INTEL_OUTPUT_DISPLAYPORT:
5180         case INTEL_OUTPUT_HDMI:
5181         case INTEL_OUTPUT_EDP:
5182                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5183                 return port_to_power_domain(intel_dig_port->port);
5184         case INTEL_OUTPUT_DP_MST:
5185                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5186                 return port_to_power_domain(intel_dig_port->port);
5187         case INTEL_OUTPUT_ANALOG:
5188                 return POWER_DOMAIN_PORT_CRT;
5189         case INTEL_OUTPUT_DSI:
5190                 return POWER_DOMAIN_PORT_DSI;
5191         default:
5192                 return POWER_DOMAIN_PORT_OTHER;
5193         }
5194 }
5195
5196 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5197 {
5198         struct drm_device *dev = crtc->dev;
5199         struct intel_encoder *intel_encoder;
5200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5201         enum pipe pipe = intel_crtc->pipe;
5202         unsigned long mask;
5203         enum transcoder transcoder;
5204
5205         if (!crtc->state->active)
5206                 return 0;
5207
5208         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5209
5210         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5211         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5212         if (intel_crtc->config->pch_pfit.enabled ||
5213             intel_crtc->config->pch_pfit.force_thru)
5214                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5215
5216         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5217                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5218
5219         return mask;
5220 }
5221
5222 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5223 {
5224         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5226         enum intel_display_power_domain domain;
5227         unsigned long domains, new_domains, old_domains;
5228
5229         old_domains = intel_crtc->enabled_power_domains;
5230         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5231
5232         domains = new_domains & ~old_domains;
5233
5234         for_each_power_domain(domain, domains)
5235                 intel_display_power_get(dev_priv, domain);
5236
5237         return old_domains & ~new_domains;
5238 }
5239
5240 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5241                                       unsigned long domains)
5242 {
5243         enum intel_display_power_domain domain;
5244
5245         for_each_power_domain(domain, domains)
5246                 intel_display_power_put(dev_priv, domain);
5247 }
5248
5249 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5250 {
5251         struct drm_device *dev = state->dev;
5252         struct drm_i915_private *dev_priv = dev->dev_private;
5253         unsigned long put_domains[I915_MAX_PIPES] = {};
5254         struct drm_crtc_state *crtc_state;
5255         struct drm_crtc *crtc;
5256         int i;
5257
5258         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5259                 if (needs_modeset(crtc->state))
5260                         put_domains[to_intel_crtc(crtc)->pipe] =
5261                                 modeset_get_crtc_power_domains(crtc);
5262         }
5263
5264         if (dev_priv->display.modeset_commit_cdclk) {
5265                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5266
5267                 if (cdclk != dev_priv->cdclk_freq &&
5268                     !WARN_ON(!state->allow_modeset))
5269                         dev_priv->display.modeset_commit_cdclk(state);
5270         }
5271
5272         for (i = 0; i < I915_MAX_PIPES; i++)
5273                 if (put_domains[i])
5274                         modeset_put_power_domains(dev_priv, put_domains[i]);
5275 }
5276
5277 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5278 {
5279         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5280
5281         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5282             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5283                 return max_cdclk_freq;
5284         else if (IS_CHERRYVIEW(dev_priv))
5285                 return max_cdclk_freq*95/100;
5286         else if (INTEL_INFO(dev_priv)->gen < 4)
5287                 return 2*max_cdclk_freq*90/100;
5288         else
5289                 return max_cdclk_freq*90/100;
5290 }
5291
5292 static void intel_update_max_cdclk(struct drm_device *dev)
5293 {
5294         struct drm_i915_private *dev_priv = dev->dev_private;
5295
5296         if (IS_SKYLAKE(dev)) {
5297                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5298
5299                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5300                         dev_priv->max_cdclk_freq = 675000;
5301                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5302                         dev_priv->max_cdclk_freq = 540000;
5303                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5304                         dev_priv->max_cdclk_freq = 450000;
5305                 else
5306                         dev_priv->max_cdclk_freq = 337500;
5307         } else if (IS_BROADWELL(dev))  {
5308                 /*
5309                  * FIXME with extra cooling we can allow
5310                  * 540 MHz for ULX and 675 Mhz for ULT.
5311                  * How can we know if extra cooling is
5312                  * available? PCI ID, VTB, something else?
5313                  */
5314                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5315                         dev_priv->max_cdclk_freq = 450000;
5316                 else if (IS_BDW_ULX(dev))
5317                         dev_priv->max_cdclk_freq = 450000;
5318                 else if (IS_BDW_ULT(dev))
5319                         dev_priv->max_cdclk_freq = 540000;
5320                 else
5321                         dev_priv->max_cdclk_freq = 675000;
5322         } else if (IS_CHERRYVIEW(dev)) {
5323                 dev_priv->max_cdclk_freq = 320000;
5324         } else if (IS_VALLEYVIEW(dev)) {
5325                 dev_priv->max_cdclk_freq = 400000;
5326         } else {
5327                 /* otherwise assume cdclk is fixed */
5328                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5329         }
5330
5331         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5332
5333         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5334                          dev_priv->max_cdclk_freq);
5335
5336         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5337                          dev_priv->max_dotclk_freq);
5338 }
5339
5340 static void intel_update_cdclk(struct drm_device *dev)
5341 {
5342         struct drm_i915_private *dev_priv = dev->dev_private;
5343
5344         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5345         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5346                          dev_priv->cdclk_freq);
5347
5348         /*
5349          * Program the gmbus_freq based on the cdclk frequency.
5350          * BSpec erroneously claims we should aim for 4MHz, but
5351          * in fact 1MHz is the correct frequency.
5352          */
5353         if (IS_VALLEYVIEW(dev)) {
5354                 /*
5355                  * Program the gmbus_freq based on the cdclk frequency.
5356                  * BSpec erroneously claims we should aim for 4MHz, but
5357                  * in fact 1MHz is the correct frequency.
5358                  */
5359                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5360         }
5361
5362         if (dev_priv->max_cdclk_freq == 0)
5363                 intel_update_max_cdclk(dev);
5364 }
5365
5366 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5367 {
5368         struct drm_i915_private *dev_priv = dev->dev_private;
5369         uint32_t divider;
5370         uint32_t ratio;
5371         uint32_t current_freq;
5372         int ret;
5373
5374         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5375         switch (frequency) {
5376         case 144000:
5377                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5378                 ratio = BXT_DE_PLL_RATIO(60);
5379                 break;
5380         case 288000:
5381                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5382                 ratio = BXT_DE_PLL_RATIO(60);
5383                 break;
5384         case 384000:
5385                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5386                 ratio = BXT_DE_PLL_RATIO(60);
5387                 break;
5388         case 576000:
5389                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5390                 ratio = BXT_DE_PLL_RATIO(60);
5391                 break;
5392         case 624000:
5393                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5394                 ratio = BXT_DE_PLL_RATIO(65);
5395                 break;
5396         case 19200:
5397                 /*
5398                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5399                  * to suppress GCC warning.
5400                  */
5401                 ratio = 0;
5402                 divider = 0;
5403                 break;
5404         default:
5405                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5406
5407                 return;
5408         }
5409
5410         mutex_lock(&dev_priv->rps.hw_lock);
5411         /* Inform power controller of upcoming frequency change */
5412         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5413                                       0x80000000);
5414         mutex_unlock(&dev_priv->rps.hw_lock);
5415
5416         if (ret) {
5417                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5418                           ret, frequency);
5419                 return;
5420         }
5421
5422         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5423         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5424         current_freq = current_freq * 500 + 1000;
5425
5426         /*
5427          * DE PLL has to be disabled when
5428          * - setting to 19.2MHz (bypass, PLL isn't used)
5429          * - before setting to 624MHz (PLL needs toggling)
5430          * - before setting to any frequency from 624MHz (PLL needs toggling)
5431          */
5432         if (frequency == 19200 || frequency == 624000 ||
5433             current_freq == 624000) {
5434                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5435                 /* Timeout 200us */
5436                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5437                              1))
5438                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5439         }
5440
5441         if (frequency != 19200) {
5442                 uint32_t val;
5443
5444                 val = I915_READ(BXT_DE_PLL_CTL);
5445                 val &= ~BXT_DE_PLL_RATIO_MASK;
5446                 val |= ratio;
5447                 I915_WRITE(BXT_DE_PLL_CTL, val);
5448
5449                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5450                 /* Timeout 200us */
5451                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5452                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5453
5454                 val = I915_READ(CDCLK_CTL);
5455                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5456                 val |= divider;
5457                 /*
5458                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5459                  * enable otherwise.
5460                  */
5461                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5462                 if (frequency >= 500000)
5463                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5464
5465                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5466                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5467                 val |= (frequency - 1000) / 500;
5468                 I915_WRITE(CDCLK_CTL, val);
5469         }
5470
5471         mutex_lock(&dev_priv->rps.hw_lock);
5472         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5473                                       DIV_ROUND_UP(frequency, 25000));
5474         mutex_unlock(&dev_priv->rps.hw_lock);
5475
5476         if (ret) {
5477                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5478                           ret, frequency);
5479                 return;
5480         }
5481
5482         intel_update_cdclk(dev);
5483 }
5484
5485 void broxton_init_cdclk(struct drm_device *dev)
5486 {
5487         struct drm_i915_private *dev_priv = dev->dev_private;
5488         uint32_t val;
5489
5490         /*
5491          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5492          * or else the reset will hang because there is no PCH to respond.
5493          * Move the handshake programming to initialization sequence.
5494          * Previously was left up to BIOS.
5495          */
5496         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5497         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5498         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5499
5500         /* Enable PG1 for cdclk */
5501         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5502
5503         /* check if cd clock is enabled */
5504         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5505                 DRM_DEBUG_KMS("Display already initialized\n");
5506                 return;
5507         }
5508
5509         /*
5510          * FIXME:
5511          * - The initial CDCLK needs to be read from VBT.
5512          *   Need to make this change after VBT has changes for BXT.
5513          * - check if setting the max (or any) cdclk freq is really necessary
5514          *   here, it belongs to modeset time
5515          */
5516         broxton_set_cdclk(dev, 624000);
5517
5518         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5519         POSTING_READ(DBUF_CTL);
5520
5521         udelay(10);
5522
5523         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5524                 DRM_ERROR("DBuf power enable timeout!\n");
5525 }
5526
5527 void broxton_uninit_cdclk(struct drm_device *dev)
5528 {
5529         struct drm_i915_private *dev_priv = dev->dev_private;
5530
5531         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5532         POSTING_READ(DBUF_CTL);
5533
5534         udelay(10);
5535
5536         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5537                 DRM_ERROR("DBuf power disable timeout!\n");
5538
5539         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5540         broxton_set_cdclk(dev, 19200);
5541
5542         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5543 }
5544
5545 static const struct skl_cdclk_entry {
5546         unsigned int freq;
5547         unsigned int vco;
5548 } skl_cdclk_frequencies[] = {
5549         { .freq = 308570, .vco = 8640 },
5550         { .freq = 337500, .vco = 8100 },
5551         { .freq = 432000, .vco = 8640 },
5552         { .freq = 450000, .vco = 8100 },
5553         { .freq = 540000, .vco = 8100 },
5554         { .freq = 617140, .vco = 8640 },
5555         { .freq = 675000, .vco = 8100 },
5556 };
5557
5558 static unsigned int skl_cdclk_decimal(unsigned int freq)
5559 {
5560         return (freq - 1000) / 500;
5561 }
5562
5563 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5564 {
5565         unsigned int i;
5566
5567         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5568                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5569
5570                 if (e->freq == freq)
5571                         return e->vco;
5572         }
5573
5574         return 8100;
5575 }
5576
5577 static void
5578 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5579 {
5580         unsigned int min_freq;
5581         u32 val;
5582
5583         /* select the minimum CDCLK before enabling DPLL 0 */
5584         val = I915_READ(CDCLK_CTL);
5585         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5586         val |= CDCLK_FREQ_337_308;
5587
5588         if (required_vco == 8640)
5589                 min_freq = 308570;
5590         else
5591                 min_freq = 337500;
5592
5593         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5594
5595         I915_WRITE(CDCLK_CTL, val);
5596         POSTING_READ(CDCLK_CTL);
5597
5598         /*
5599          * We always enable DPLL0 with the lowest link rate possible, but still
5600          * taking into account the VCO required to operate the eDP panel at the
5601          * desired frequency. The usual DP link rates operate with a VCO of
5602          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5603          * The modeset code is responsible for the selection of the exact link
5604          * rate later on, with the constraint of choosing a frequency that
5605          * works with required_vco.
5606          */
5607         val = I915_READ(DPLL_CTRL1);
5608
5609         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5610                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5611         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5612         if (required_vco == 8640)
5613                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5614                                             SKL_DPLL0);
5615         else
5616                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5617                                             SKL_DPLL0);
5618
5619         I915_WRITE(DPLL_CTRL1, val);
5620         POSTING_READ(DPLL_CTRL1);
5621
5622         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5623
5624         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5625                 DRM_ERROR("DPLL0 not locked\n");
5626 }
5627
5628 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5629 {
5630         int ret;
5631         u32 val;
5632
5633         /* inform PCU we want to change CDCLK */
5634         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5635         mutex_lock(&dev_priv->rps.hw_lock);
5636         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5637         mutex_unlock(&dev_priv->rps.hw_lock);
5638
5639         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5640 }
5641
5642 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5643 {
5644         unsigned int i;
5645
5646         for (i = 0; i < 15; i++) {
5647                 if (skl_cdclk_pcu_ready(dev_priv))
5648                         return true;
5649                 udelay(10);
5650         }
5651
5652         return false;
5653 }
5654
5655 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5656 {
5657         struct drm_device *dev = dev_priv->dev;
5658         u32 freq_select, pcu_ack;
5659
5660         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5661
5662         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5663                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5664                 return;
5665         }
5666
5667         /* set CDCLK_CTL */
5668         switch(freq) {
5669         case 450000:
5670         case 432000:
5671                 freq_select = CDCLK_FREQ_450_432;
5672                 pcu_ack = 1;
5673                 break;
5674         case 540000:
5675                 freq_select = CDCLK_FREQ_540;
5676                 pcu_ack = 2;
5677                 break;
5678         case 308570:
5679         case 337500:
5680         default:
5681                 freq_select = CDCLK_FREQ_337_308;
5682                 pcu_ack = 0;
5683                 break;
5684         case 617140:
5685         case 675000:
5686                 freq_select = CDCLK_FREQ_675_617;
5687                 pcu_ack = 3;
5688                 break;
5689         }
5690
5691         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5692         POSTING_READ(CDCLK_CTL);
5693
5694         /* inform PCU of the change */
5695         mutex_lock(&dev_priv->rps.hw_lock);
5696         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5697         mutex_unlock(&dev_priv->rps.hw_lock);
5698
5699         intel_update_cdclk(dev);
5700 }
5701
5702 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5703 {
5704         /* disable DBUF power */
5705         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5706         POSTING_READ(DBUF_CTL);
5707
5708         udelay(10);
5709
5710         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5711                 DRM_ERROR("DBuf power disable timeout\n");
5712
5713         /*
5714          * DMC assumes ownership of LCPLL and will get confused if we touch it.
5715          */
5716         if (dev_priv->csr.dmc_payload) {
5717                 /* disable DPLL0 */
5718                 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5719                                         ~LCPLL_PLL_ENABLE);
5720                 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5721                         DRM_ERROR("Couldn't disable DPLL0\n");
5722         }
5723
5724         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5725 }
5726
5727 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5728 {
5729         u32 val;
5730         unsigned int required_vco;
5731
5732         /* enable PCH reset handshake */
5733         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5734         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5735
5736         /* enable PG1 and Misc I/O */
5737         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5738
5739         /* DPLL0 not enabled (happens on early BIOS versions) */
5740         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5741                 /* enable DPLL0 */
5742                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5743                 skl_dpll0_enable(dev_priv, required_vco);
5744         }
5745
5746         /* set CDCLK to the frequency the BIOS chose */
5747         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5748
5749         /* enable DBUF power */
5750         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5751         POSTING_READ(DBUF_CTL);
5752
5753         udelay(10);
5754
5755         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5756                 DRM_ERROR("DBuf power enable timeout\n");
5757 }
5758
5759 /* returns HPLL frequency in kHz */
5760 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5761 {
5762         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5763
5764         /* Obtain SKU information */
5765         mutex_lock(&dev_priv->sb_lock);
5766         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5767                 CCK_FUSE_HPLL_FREQ_MASK;
5768         mutex_unlock(&dev_priv->sb_lock);
5769
5770         return vco_freq[hpll_freq] * 1000;
5771 }
5772
5773 /* Adjust CDclk dividers to allow high res or save power if possible */
5774 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5775 {
5776         struct drm_i915_private *dev_priv = dev->dev_private;
5777         u32 val, cmd;
5778
5779         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5780                                         != dev_priv->cdclk_freq);
5781
5782         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5783                 cmd = 2;
5784         else if (cdclk == 266667)
5785                 cmd = 1;
5786         else
5787                 cmd = 0;
5788
5789         mutex_lock(&dev_priv->rps.hw_lock);
5790         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5791         val &= ~DSPFREQGUAR_MASK;
5792         val |= (cmd << DSPFREQGUAR_SHIFT);
5793         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5794         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5795                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5796                      50)) {
5797                 DRM_ERROR("timed out waiting for CDclk change\n");
5798         }
5799         mutex_unlock(&dev_priv->rps.hw_lock);
5800
5801         mutex_lock(&dev_priv->sb_lock);
5802
5803         if (cdclk == 400000) {
5804                 u32 divider;
5805
5806                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5807
5808                 /* adjust cdclk divider */
5809                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5810                 val &= ~DISPLAY_FREQUENCY_VALUES;
5811                 val |= divider;
5812                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5813
5814                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5815                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5816                              50))
5817                         DRM_ERROR("timed out waiting for CDclk change\n");
5818         }
5819
5820         /* adjust self-refresh exit latency value */
5821         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5822         val &= ~0x7f;
5823
5824         /*
5825          * For high bandwidth configs, we set a higher latency in the bunit
5826          * so that the core display fetch happens in time to avoid underruns.
5827          */
5828         if (cdclk == 400000)
5829                 val |= 4500 / 250; /* 4.5 usec */
5830         else
5831                 val |= 3000 / 250; /* 3.0 usec */
5832         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5833
5834         mutex_unlock(&dev_priv->sb_lock);
5835
5836         intel_update_cdclk(dev);
5837 }
5838
5839 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5840 {
5841         struct drm_i915_private *dev_priv = dev->dev_private;
5842         u32 val, cmd;
5843
5844         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5845                                                 != dev_priv->cdclk_freq);
5846
5847         switch (cdclk) {
5848         case 333333:
5849         case 320000:
5850         case 266667:
5851         case 200000:
5852                 break;
5853         default:
5854                 MISSING_CASE(cdclk);
5855                 return;
5856         }
5857
5858         /*
5859          * Specs are full of misinformation, but testing on actual
5860          * hardware has shown that we just need to write the desired
5861          * CCK divider into the Punit register.
5862          */
5863         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5864
5865         mutex_lock(&dev_priv->rps.hw_lock);
5866         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5867         val &= ~DSPFREQGUAR_MASK_CHV;
5868         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5869         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5870         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5871                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5872                      50)) {
5873                 DRM_ERROR("timed out waiting for CDclk change\n");
5874         }
5875         mutex_unlock(&dev_priv->rps.hw_lock);
5876
5877         intel_update_cdclk(dev);
5878 }
5879
5880 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5881                                  int max_pixclk)
5882 {
5883         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5884         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5885
5886         /*
5887          * Really only a few cases to deal with, as only 4 CDclks are supported:
5888          *   200MHz
5889          *   267MHz
5890          *   320/333MHz (depends on HPLL freq)
5891          *   400MHz (VLV only)
5892          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5893          * of the lower bin and adjust if needed.
5894          *
5895          * We seem to get an unstable or solid color picture at 200MHz.
5896          * Not sure what's wrong. For now use 200MHz only when all pipes
5897          * are off.
5898          */
5899         if (!IS_CHERRYVIEW(dev_priv) &&
5900             max_pixclk > freq_320*limit/100)
5901                 return 400000;
5902         else if (max_pixclk > 266667*limit/100)
5903                 return freq_320;
5904         else if (max_pixclk > 0)
5905                 return 266667;
5906         else
5907                 return 200000;
5908 }
5909
5910 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5911                               int max_pixclk)
5912 {
5913         /*
5914          * FIXME:
5915          * - remove the guardband, it's not needed on BXT
5916          * - set 19.2MHz bypass frequency if there are no active pipes
5917          */
5918         if (max_pixclk > 576000*9/10)
5919                 return 624000;
5920         else if (max_pixclk > 384000*9/10)
5921                 return 576000;
5922         else if (max_pixclk > 288000*9/10)
5923                 return 384000;
5924         else if (max_pixclk > 144000*9/10)
5925                 return 288000;
5926         else
5927                 return 144000;
5928 }
5929
5930 /* Compute the max pixel clock for new configuration. Uses atomic state if
5931  * that's non-NULL, look at current state otherwise. */
5932 static int intel_mode_max_pixclk(struct drm_device *dev,
5933                                  struct drm_atomic_state *state)
5934 {
5935         struct intel_crtc *intel_crtc;
5936         struct intel_crtc_state *crtc_state;
5937         int max_pixclk = 0;
5938
5939         for_each_intel_crtc(dev, intel_crtc) {
5940                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5941                 if (IS_ERR(crtc_state))
5942                         return PTR_ERR(crtc_state);
5943
5944                 if (!crtc_state->base.enable)
5945                         continue;
5946
5947                 max_pixclk = max(max_pixclk,
5948                                  crtc_state->base.adjusted_mode.crtc_clock);
5949         }
5950
5951         return max_pixclk;
5952 }
5953
5954 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5955 {
5956         struct drm_device *dev = state->dev;
5957         struct drm_i915_private *dev_priv = dev->dev_private;
5958         int max_pixclk = intel_mode_max_pixclk(dev, state);
5959
5960         if (max_pixclk < 0)
5961                 return max_pixclk;
5962
5963         to_intel_atomic_state(state)->cdclk =
5964                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5965
5966         return 0;
5967 }
5968
5969 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5970 {
5971         struct drm_device *dev = state->dev;
5972         struct drm_i915_private *dev_priv = dev->dev_private;
5973         int max_pixclk = intel_mode_max_pixclk(dev, state);
5974
5975         if (max_pixclk < 0)
5976                 return max_pixclk;
5977
5978         to_intel_atomic_state(state)->cdclk =
5979                 broxton_calc_cdclk(dev_priv, max_pixclk);
5980
5981         return 0;
5982 }
5983
5984 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5985 {
5986         unsigned int credits, default_credits;
5987
5988         if (IS_CHERRYVIEW(dev_priv))
5989                 default_credits = PFI_CREDIT(12);
5990         else
5991                 default_credits = PFI_CREDIT(8);
5992
5993         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5994                 /* CHV suggested value is 31 or 63 */
5995                 if (IS_CHERRYVIEW(dev_priv))
5996                         credits = PFI_CREDIT_63;
5997                 else
5998                         credits = PFI_CREDIT(15);
5999         } else {
6000                 credits = default_credits;
6001         }
6002
6003         /*
6004          * WA - write default credits before re-programming
6005          * FIXME: should we also set the resend bit here?
6006          */
6007         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6008                    default_credits);
6009
6010         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6011                    credits | PFI_CREDIT_RESEND);
6012
6013         /*
6014          * FIXME is this guaranteed to clear
6015          * immediately or should we poll for it?
6016          */
6017         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6018 }
6019
6020 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6021 {
6022         struct drm_device *dev = old_state->dev;
6023         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6024         struct drm_i915_private *dev_priv = dev->dev_private;
6025
6026         /*
6027          * FIXME: We can end up here with all power domains off, yet
6028          * with a CDCLK frequency other than the minimum. To account
6029          * for this take the PIPE-A power domain, which covers the HW
6030          * blocks needed for the following programming. This can be
6031          * removed once it's guaranteed that we get here either with
6032          * the minimum CDCLK set, or the required power domains
6033          * enabled.
6034          */
6035         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6036
6037         if (IS_CHERRYVIEW(dev))
6038                 cherryview_set_cdclk(dev, req_cdclk);
6039         else
6040                 valleyview_set_cdclk(dev, req_cdclk);
6041
6042         vlv_program_pfi_credits(dev_priv);
6043
6044         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6045 }
6046
6047 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6048 {
6049         struct drm_device *dev = crtc->dev;
6050         struct drm_i915_private *dev_priv = to_i915(dev);
6051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6052         struct intel_encoder *encoder;
6053         int pipe = intel_crtc->pipe;
6054         bool is_dsi;
6055
6056         if (WARN_ON(intel_crtc->active))
6057                 return;
6058
6059         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6060
6061         if (intel_crtc->config->has_dp_encoder)
6062                 intel_dp_set_m_n(intel_crtc, M1_N1);
6063
6064         intel_set_pipe_timings(intel_crtc);
6065
6066         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6067                 struct drm_i915_private *dev_priv = dev->dev_private;
6068
6069                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6070                 I915_WRITE(CHV_CANVAS(pipe), 0);
6071         }
6072
6073         i9xx_set_pipeconf(intel_crtc);
6074
6075         intel_crtc->active = true;
6076
6077         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6078
6079         for_each_encoder_on_crtc(dev, crtc, encoder)
6080                 if (encoder->pre_pll_enable)
6081                         encoder->pre_pll_enable(encoder);
6082
6083         if (!is_dsi) {
6084                 if (IS_CHERRYVIEW(dev)) {
6085                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6086                         chv_enable_pll(intel_crtc, intel_crtc->config);
6087                 } else {
6088                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6089                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6090                 }
6091         }
6092
6093         for_each_encoder_on_crtc(dev, crtc, encoder)
6094                 if (encoder->pre_enable)
6095                         encoder->pre_enable(encoder);
6096
6097         i9xx_pfit_enable(intel_crtc);
6098
6099         intel_crtc_load_lut(crtc);
6100
6101         intel_enable_pipe(intel_crtc);
6102
6103         assert_vblank_disabled(crtc);
6104         drm_crtc_vblank_on(crtc);
6105
6106         for_each_encoder_on_crtc(dev, crtc, encoder)
6107                 encoder->enable(encoder);
6108 }
6109
6110 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6111 {
6112         struct drm_device *dev = crtc->base.dev;
6113         struct drm_i915_private *dev_priv = dev->dev_private;
6114
6115         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6116         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6117 }
6118
6119 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6120 {
6121         struct drm_device *dev = crtc->dev;
6122         struct drm_i915_private *dev_priv = to_i915(dev);
6123         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6124         struct intel_encoder *encoder;
6125         int pipe = intel_crtc->pipe;
6126
6127         if (WARN_ON(intel_crtc->active))
6128                 return;
6129
6130         i9xx_set_pll_dividers(intel_crtc);
6131
6132         if (intel_crtc->config->has_dp_encoder)
6133                 intel_dp_set_m_n(intel_crtc, M1_N1);
6134
6135         intel_set_pipe_timings(intel_crtc);
6136
6137         i9xx_set_pipeconf(intel_crtc);
6138
6139         intel_crtc->active = true;
6140
6141         if (!IS_GEN2(dev))
6142                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6143
6144         for_each_encoder_on_crtc(dev, crtc, encoder)
6145                 if (encoder->pre_enable)
6146                         encoder->pre_enable(encoder);
6147
6148         i9xx_enable_pll(intel_crtc);
6149
6150         i9xx_pfit_enable(intel_crtc);
6151
6152         intel_crtc_load_lut(crtc);
6153
6154         intel_update_watermarks(crtc);
6155         intel_enable_pipe(intel_crtc);
6156
6157         assert_vblank_disabled(crtc);
6158         drm_crtc_vblank_on(crtc);
6159
6160         for_each_encoder_on_crtc(dev, crtc, encoder)
6161                 encoder->enable(encoder);
6162 }
6163
6164 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6165 {
6166         struct drm_device *dev = crtc->base.dev;
6167         struct drm_i915_private *dev_priv = dev->dev_private;
6168
6169         if (!crtc->config->gmch_pfit.control)
6170                 return;
6171
6172         assert_pipe_disabled(dev_priv, crtc->pipe);
6173
6174         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6175                          I915_READ(PFIT_CONTROL));
6176         I915_WRITE(PFIT_CONTROL, 0);
6177 }
6178
6179 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6180 {
6181         struct drm_device *dev = crtc->dev;
6182         struct drm_i915_private *dev_priv = dev->dev_private;
6183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6184         struct intel_encoder *encoder;
6185         int pipe = intel_crtc->pipe;
6186
6187         /*
6188          * On gen2 planes are double buffered but the pipe isn't, so we must
6189          * wait for planes to fully turn off before disabling the pipe.
6190          * We also need to wait on all gmch platforms because of the
6191          * self-refresh mode constraint explained above.
6192          */
6193         intel_wait_for_vblank(dev, pipe);
6194
6195         for_each_encoder_on_crtc(dev, crtc, encoder)
6196                 encoder->disable(encoder);
6197
6198         drm_crtc_vblank_off(crtc);
6199         assert_vblank_disabled(crtc);
6200
6201         intel_disable_pipe(intel_crtc);
6202
6203         i9xx_pfit_disable(intel_crtc);
6204
6205         for_each_encoder_on_crtc(dev, crtc, encoder)
6206                 if (encoder->post_disable)
6207                         encoder->post_disable(encoder);
6208
6209         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6210                 if (IS_CHERRYVIEW(dev))
6211                         chv_disable_pll(dev_priv, pipe);
6212                 else if (IS_VALLEYVIEW(dev))
6213                         vlv_disable_pll(dev_priv, pipe);
6214                 else
6215                         i9xx_disable_pll(intel_crtc);
6216         }
6217
6218         for_each_encoder_on_crtc(dev, crtc, encoder)
6219                 if (encoder->post_pll_disable)
6220                         encoder->post_pll_disable(encoder);
6221
6222         if (!IS_GEN2(dev))
6223                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6224
6225         intel_crtc->active = false;
6226         intel_update_watermarks(crtc);
6227 }
6228
6229 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6230 {
6231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6232         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6233         enum intel_display_power_domain domain;
6234         unsigned long domains;
6235
6236         if (!intel_crtc->active)
6237                 return;
6238
6239         if (to_intel_plane_state(crtc->primary->state)->visible) {
6240                 intel_crtc_wait_for_pending_flips(crtc);
6241                 intel_pre_disable_primary(crtc);
6242         }
6243
6244         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6245         dev_priv->display.crtc_disable(crtc);
6246         intel_disable_shared_dpll(intel_crtc);
6247
6248         domains = intel_crtc->enabled_power_domains;
6249         for_each_power_domain(domain, domains)
6250                 intel_display_power_put(dev_priv, domain);
6251         intel_crtc->enabled_power_domains = 0;
6252 }
6253
6254 /*
6255  * turn all crtc's off, but do not adjust state
6256  * This has to be paired with a call to intel_modeset_setup_hw_state.
6257  */
6258 int intel_display_suspend(struct drm_device *dev)
6259 {
6260         struct drm_mode_config *config = &dev->mode_config;
6261         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6262         struct drm_atomic_state *state;
6263         struct drm_crtc *crtc;
6264         unsigned crtc_mask = 0;
6265         int ret = 0;
6266
6267         if (WARN_ON(!ctx))
6268                 return 0;
6269
6270         lockdep_assert_held(&ctx->ww_ctx);
6271         state = drm_atomic_state_alloc(dev);
6272         if (WARN_ON(!state))
6273                 return -ENOMEM;
6274
6275         state->acquire_ctx = ctx;
6276         state->allow_modeset = true;
6277
6278         for_each_crtc(dev, crtc) {
6279                 struct drm_crtc_state *crtc_state =
6280                         drm_atomic_get_crtc_state(state, crtc);
6281
6282                 ret = PTR_ERR_OR_ZERO(crtc_state);
6283                 if (ret)
6284                         goto free;
6285
6286                 if (!crtc_state->active)
6287                         continue;
6288
6289                 crtc_state->active = false;
6290                 crtc_mask |= 1 << drm_crtc_index(crtc);
6291         }
6292
6293         if (crtc_mask) {
6294                 ret = drm_atomic_commit(state);
6295
6296                 if (!ret) {
6297                         for_each_crtc(dev, crtc)
6298                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6299                                         crtc->state->active = true;
6300
6301                         return ret;
6302                 }
6303         }
6304
6305 free:
6306         if (ret)
6307                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6308         drm_atomic_state_free(state);
6309         return ret;
6310 }
6311
6312 void intel_encoder_destroy(struct drm_encoder *encoder)
6313 {
6314         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6315
6316         drm_encoder_cleanup(encoder);
6317         kfree(intel_encoder);
6318 }
6319
6320 /* Cross check the actual hw state with our own modeset state tracking (and it's
6321  * internal consistency). */
6322 static void intel_connector_check_state(struct intel_connector *connector)
6323 {
6324         struct drm_crtc *crtc = connector->base.state->crtc;
6325
6326         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6327                       connector->base.base.id,
6328                       connector->base.name);
6329
6330         if (connector->get_hw_state(connector)) {
6331                 struct intel_encoder *encoder = connector->encoder;
6332                 struct drm_connector_state *conn_state = connector->base.state;
6333
6334                 I915_STATE_WARN(!crtc,
6335                          "connector enabled without attached crtc\n");
6336
6337                 if (!crtc)
6338                         return;
6339
6340                 I915_STATE_WARN(!crtc->state->active,
6341                       "connector is active, but attached crtc isn't\n");
6342
6343                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6344                         return;
6345
6346                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6347                         "atomic encoder doesn't match attached encoder\n");
6348
6349                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6350                         "attached encoder crtc differs from connector crtc\n");
6351         } else {
6352                 I915_STATE_WARN(crtc && crtc->state->active,
6353                         "attached crtc is active, but connector isn't\n");
6354                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6355                         "best encoder set without crtc!\n");
6356         }
6357 }
6358
6359 int intel_connector_init(struct intel_connector *connector)
6360 {
6361         struct drm_connector_state *connector_state;
6362
6363         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6364         if (!connector_state)
6365                 return -ENOMEM;
6366
6367         connector->base.state = connector_state;
6368         return 0;
6369 }
6370
6371 struct intel_connector *intel_connector_alloc(void)
6372 {
6373         struct intel_connector *connector;
6374
6375         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6376         if (!connector)
6377                 return NULL;
6378
6379         if (intel_connector_init(connector) < 0) {
6380                 kfree(connector);
6381                 return NULL;
6382         }
6383
6384         return connector;
6385 }
6386
6387 /* Simple connector->get_hw_state implementation for encoders that support only
6388  * one connector and no cloning and hence the encoder state determines the state
6389  * of the connector. */
6390 bool intel_connector_get_hw_state(struct intel_connector *connector)
6391 {
6392         enum pipe pipe = 0;
6393         struct intel_encoder *encoder = connector->encoder;
6394
6395         return encoder->get_hw_state(encoder, &pipe);
6396 }
6397
6398 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6399 {
6400         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6401                 return crtc_state->fdi_lanes;
6402
6403         return 0;
6404 }
6405
6406 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6407                                      struct intel_crtc_state *pipe_config)
6408 {
6409         struct drm_atomic_state *state = pipe_config->base.state;
6410         struct intel_crtc *other_crtc;
6411         struct intel_crtc_state *other_crtc_state;
6412
6413         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6414                       pipe_name(pipe), pipe_config->fdi_lanes);
6415         if (pipe_config->fdi_lanes > 4) {
6416                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6417                               pipe_name(pipe), pipe_config->fdi_lanes);
6418                 return -EINVAL;
6419         }
6420
6421         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6422                 if (pipe_config->fdi_lanes > 2) {
6423                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6424                                       pipe_config->fdi_lanes);
6425                         return -EINVAL;
6426                 } else {
6427                         return 0;
6428                 }
6429         }
6430
6431         if (INTEL_INFO(dev)->num_pipes == 2)
6432                 return 0;
6433
6434         /* Ivybridge 3 pipe is really complicated */
6435         switch (pipe) {
6436         case PIPE_A:
6437                 return 0;
6438         case PIPE_B:
6439                 if (pipe_config->fdi_lanes <= 2)
6440                         return 0;
6441
6442                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6443                 other_crtc_state =
6444                         intel_atomic_get_crtc_state(state, other_crtc);
6445                 if (IS_ERR(other_crtc_state))
6446                         return PTR_ERR(other_crtc_state);
6447
6448                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6449                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6450                                       pipe_name(pipe), pipe_config->fdi_lanes);
6451                         return -EINVAL;
6452                 }
6453                 return 0;
6454         case PIPE_C:
6455                 if (pipe_config->fdi_lanes > 2) {
6456                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6457                                       pipe_name(pipe), pipe_config->fdi_lanes);
6458                         return -EINVAL;
6459                 }
6460
6461                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6462                 other_crtc_state =
6463                         intel_atomic_get_crtc_state(state, other_crtc);
6464                 if (IS_ERR(other_crtc_state))
6465                         return PTR_ERR(other_crtc_state);
6466
6467                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6468                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6469                         return -EINVAL;
6470                 }
6471                 return 0;
6472         default:
6473                 BUG();
6474         }
6475 }
6476
6477 #define RETRY 1
6478 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6479                                        struct intel_crtc_state *pipe_config)
6480 {
6481         struct drm_device *dev = intel_crtc->base.dev;
6482         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6483         int lane, link_bw, fdi_dotclock, ret;
6484         bool needs_recompute = false;
6485
6486 retry:
6487         /* FDI is a binary signal running at ~2.7GHz, encoding
6488          * each output octet as 10 bits. The actual frequency
6489          * is stored as a divider into a 100MHz clock, and the
6490          * mode pixel clock is stored in units of 1KHz.
6491          * Hence the bw of each lane in terms of the mode signal
6492          * is:
6493          */
6494         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6495
6496         fdi_dotclock = adjusted_mode->crtc_clock;
6497
6498         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6499                                            pipe_config->pipe_bpp);
6500
6501         pipe_config->fdi_lanes = lane;
6502
6503         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6504                                link_bw, &pipe_config->fdi_m_n);
6505
6506         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6507                                        intel_crtc->pipe, pipe_config);
6508         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6509                 pipe_config->pipe_bpp -= 2*3;
6510                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6511                               pipe_config->pipe_bpp);
6512                 needs_recompute = true;
6513                 pipe_config->bw_constrained = true;
6514
6515                 goto retry;
6516         }
6517
6518         if (needs_recompute)
6519                 return RETRY;
6520
6521         return ret;
6522 }
6523
6524 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6525                                      struct intel_crtc_state *pipe_config)
6526 {
6527         if (pipe_config->pipe_bpp > 24)
6528                 return false;
6529
6530         /* HSW can handle pixel rate up to cdclk? */
6531         if (IS_HASWELL(dev_priv->dev))
6532                 return true;
6533
6534         /*
6535          * We compare against max which means we must take
6536          * the increased cdclk requirement into account when
6537          * calculating the new cdclk.
6538          *
6539          * Should measure whether using a lower cdclk w/o IPS
6540          */
6541         return ilk_pipe_pixel_rate(pipe_config) <=
6542                 dev_priv->max_cdclk_freq * 95 / 100;
6543 }
6544
6545 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6546                                    struct intel_crtc_state *pipe_config)
6547 {
6548         struct drm_device *dev = crtc->base.dev;
6549         struct drm_i915_private *dev_priv = dev->dev_private;
6550
6551         pipe_config->ips_enabled = i915.enable_ips &&
6552                 hsw_crtc_supports_ips(crtc) &&
6553                 pipe_config_supports_ips(dev_priv, pipe_config);
6554 }
6555
6556 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6557                                      struct intel_crtc_state *pipe_config)
6558 {
6559         struct drm_device *dev = crtc->base.dev;
6560         struct drm_i915_private *dev_priv = dev->dev_private;
6561         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6562
6563         /* FIXME should check pixel clock limits on all platforms */
6564         if (INTEL_INFO(dev)->gen < 4) {
6565                 int clock_limit = dev_priv->max_cdclk_freq;
6566
6567                 /*
6568                  * Enable pixel doubling when the dot clock
6569                  * is > 90% of the (display) core speed.
6570                  *
6571                  * GDG double wide on either pipe,
6572                  * otherwise pipe A only.
6573                  */
6574                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6575                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6576                         clock_limit *= 2;
6577                         pipe_config->double_wide = true;
6578                 }
6579
6580                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6581                         return -EINVAL;
6582         }
6583
6584         /*
6585          * Pipe horizontal size must be even in:
6586          * - DVO ganged mode
6587          * - LVDS dual channel mode
6588          * - Double wide pipe
6589          */
6590         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6591              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6592                 pipe_config->pipe_src_w &= ~1;
6593
6594         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6595          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6596          */
6597         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6598                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6599                 return -EINVAL;
6600
6601         if (HAS_IPS(dev))
6602                 hsw_compute_ips_config(crtc, pipe_config);
6603
6604         if (pipe_config->has_pch_encoder)
6605                 return ironlake_fdi_compute_config(crtc, pipe_config);
6606
6607         return 0;
6608 }
6609
6610 static int skylake_get_display_clock_speed(struct drm_device *dev)
6611 {
6612         struct drm_i915_private *dev_priv = to_i915(dev);
6613         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6614         uint32_t cdctl = I915_READ(CDCLK_CTL);
6615         uint32_t linkrate;
6616
6617         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6618                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6619
6620         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6621                 return 540000;
6622
6623         linkrate = (I915_READ(DPLL_CTRL1) &
6624                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6625
6626         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6627             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6628                 /* vco 8640 */
6629                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6630                 case CDCLK_FREQ_450_432:
6631                         return 432000;
6632                 case CDCLK_FREQ_337_308:
6633                         return 308570;
6634                 case CDCLK_FREQ_675_617:
6635                         return 617140;
6636                 default:
6637                         WARN(1, "Unknown cd freq selection\n");
6638                 }
6639         } else {
6640                 /* vco 8100 */
6641                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6642                 case CDCLK_FREQ_450_432:
6643                         return 450000;
6644                 case CDCLK_FREQ_337_308:
6645                         return 337500;
6646                 case CDCLK_FREQ_675_617:
6647                         return 675000;
6648                 default:
6649                         WARN(1, "Unknown cd freq selection\n");
6650                 }
6651         }
6652
6653         /* error case, do as if DPLL0 isn't enabled */
6654         return 24000;
6655 }
6656
6657 static int broxton_get_display_clock_speed(struct drm_device *dev)
6658 {
6659         struct drm_i915_private *dev_priv = to_i915(dev);
6660         uint32_t cdctl = I915_READ(CDCLK_CTL);
6661         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6662         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6663         int cdclk;
6664
6665         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6666                 return 19200;
6667
6668         cdclk = 19200 * pll_ratio / 2;
6669
6670         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6671         case BXT_CDCLK_CD2X_DIV_SEL_1:
6672                 return cdclk;  /* 576MHz or 624MHz */
6673         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6674                 return cdclk * 2 / 3; /* 384MHz */
6675         case BXT_CDCLK_CD2X_DIV_SEL_2:
6676                 return cdclk / 2; /* 288MHz */
6677         case BXT_CDCLK_CD2X_DIV_SEL_4:
6678                 return cdclk / 4; /* 144MHz */
6679         }
6680
6681         /* error case, do as if DE PLL isn't enabled */
6682         return 19200;
6683 }
6684
6685 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6686 {
6687         struct drm_i915_private *dev_priv = dev->dev_private;
6688         uint32_t lcpll = I915_READ(LCPLL_CTL);
6689         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6690
6691         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6692                 return 800000;
6693         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6694                 return 450000;
6695         else if (freq == LCPLL_CLK_FREQ_450)
6696                 return 450000;
6697         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6698                 return 540000;
6699         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6700                 return 337500;
6701         else
6702                 return 675000;
6703 }
6704
6705 static int haswell_get_display_clock_speed(struct drm_device *dev)
6706 {
6707         struct drm_i915_private *dev_priv = dev->dev_private;
6708         uint32_t lcpll = I915_READ(LCPLL_CTL);
6709         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6710
6711         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6712                 return 800000;
6713         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6714                 return 450000;
6715         else if (freq == LCPLL_CLK_FREQ_450)
6716                 return 450000;
6717         else if (IS_HSW_ULT(dev))
6718                 return 337500;
6719         else
6720                 return 540000;
6721 }
6722
6723 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6724 {
6725         struct drm_i915_private *dev_priv = dev->dev_private;
6726         u32 val;
6727         int divider;
6728
6729         if (dev_priv->hpll_freq == 0)
6730                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6731
6732         mutex_lock(&dev_priv->sb_lock);
6733         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6734         mutex_unlock(&dev_priv->sb_lock);
6735
6736         divider = val & DISPLAY_FREQUENCY_VALUES;
6737
6738         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6739              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6740              "cdclk change in progress\n");
6741
6742         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6743 }
6744
6745 static int ilk_get_display_clock_speed(struct drm_device *dev)
6746 {
6747         return 450000;
6748 }
6749
6750 static int i945_get_display_clock_speed(struct drm_device *dev)
6751 {
6752         return 400000;
6753 }
6754
6755 static int i915_get_display_clock_speed(struct drm_device *dev)
6756 {
6757         return 333333;
6758 }
6759
6760 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6761 {
6762         return 200000;
6763 }
6764
6765 static int pnv_get_display_clock_speed(struct drm_device *dev)
6766 {
6767         u16 gcfgc = 0;
6768
6769         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6770
6771         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6772         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6773                 return 266667;
6774         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6775                 return 333333;
6776         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6777                 return 444444;
6778         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6779                 return 200000;
6780         default:
6781                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6782         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6783                 return 133333;
6784         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6785                 return 166667;
6786         }
6787 }
6788
6789 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6790 {
6791         u16 gcfgc = 0;
6792
6793         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6794
6795         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6796                 return 133333;
6797         else {
6798                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6799                 case GC_DISPLAY_CLOCK_333_MHZ:
6800                         return 333333;
6801                 default:
6802                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6803                         return 190000;
6804                 }
6805         }
6806 }
6807
6808 static int i865_get_display_clock_speed(struct drm_device *dev)
6809 {
6810         return 266667;
6811 }
6812
6813 static int i85x_get_display_clock_speed(struct drm_device *dev)
6814 {
6815         u16 hpllcc = 0;
6816
6817         /*
6818          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6819          * encoding is different :(
6820          * FIXME is this the right way to detect 852GM/852GMV?
6821          */
6822         if (dev->pdev->revision == 0x1)
6823                 return 133333;
6824
6825         pci_bus_read_config_word(dev->pdev->bus,
6826                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6827
6828         /* Assume that the hardware is in the high speed state.  This
6829          * should be the default.
6830          */
6831         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6832         case GC_CLOCK_133_200:
6833         case GC_CLOCK_133_200_2:
6834         case GC_CLOCK_100_200:
6835                 return 200000;
6836         case GC_CLOCK_166_250:
6837                 return 250000;
6838         case GC_CLOCK_100_133:
6839                 return 133333;
6840         case GC_CLOCK_133_266:
6841         case GC_CLOCK_133_266_2:
6842         case GC_CLOCK_166_266:
6843                 return 266667;
6844         }
6845
6846         /* Shouldn't happen */
6847         return 0;
6848 }
6849
6850 static int i830_get_display_clock_speed(struct drm_device *dev)
6851 {
6852         return 133333;
6853 }
6854
6855 static unsigned int intel_hpll_vco(struct drm_device *dev)
6856 {
6857         struct drm_i915_private *dev_priv = dev->dev_private;
6858         static const unsigned int blb_vco[8] = {
6859                 [0] = 3200000,
6860                 [1] = 4000000,
6861                 [2] = 5333333,
6862                 [3] = 4800000,
6863                 [4] = 6400000,
6864         };
6865         static const unsigned int pnv_vco[8] = {
6866                 [0] = 3200000,
6867                 [1] = 4000000,
6868                 [2] = 5333333,
6869                 [3] = 4800000,
6870                 [4] = 2666667,
6871         };
6872         static const unsigned int cl_vco[8] = {
6873                 [0] = 3200000,
6874                 [1] = 4000000,
6875                 [2] = 5333333,
6876                 [3] = 6400000,
6877                 [4] = 3333333,
6878                 [5] = 3566667,
6879                 [6] = 4266667,
6880         };
6881         static const unsigned int elk_vco[8] = {
6882                 [0] = 3200000,
6883                 [1] = 4000000,
6884                 [2] = 5333333,
6885                 [3] = 4800000,
6886         };
6887         static const unsigned int ctg_vco[8] = {
6888                 [0] = 3200000,
6889                 [1] = 4000000,
6890                 [2] = 5333333,
6891                 [3] = 6400000,
6892                 [4] = 2666667,
6893                 [5] = 4266667,
6894         };
6895         const unsigned int *vco_table;
6896         unsigned int vco;
6897         uint8_t tmp = 0;
6898
6899         /* FIXME other chipsets? */
6900         if (IS_GM45(dev))
6901                 vco_table = ctg_vco;
6902         else if (IS_G4X(dev))
6903                 vco_table = elk_vco;
6904         else if (IS_CRESTLINE(dev))
6905                 vco_table = cl_vco;
6906         else if (IS_PINEVIEW(dev))
6907                 vco_table = pnv_vco;
6908         else if (IS_G33(dev))
6909                 vco_table = blb_vco;
6910         else
6911                 return 0;
6912
6913         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6914
6915         vco = vco_table[tmp & 0x7];
6916         if (vco == 0)
6917                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6918         else
6919                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6920
6921         return vco;
6922 }
6923
6924 static int gm45_get_display_clock_speed(struct drm_device *dev)
6925 {
6926         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6927         uint16_t tmp = 0;
6928
6929         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6930
6931         cdclk_sel = (tmp >> 12) & 0x1;
6932
6933         switch (vco) {
6934         case 2666667:
6935         case 4000000:
6936         case 5333333:
6937                 return cdclk_sel ? 333333 : 222222;
6938         case 3200000:
6939                 return cdclk_sel ? 320000 : 228571;
6940         default:
6941                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6942                 return 222222;
6943         }
6944 }
6945
6946 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6947 {
6948         static const uint8_t div_3200[] = { 16, 10,  8 };
6949         static const uint8_t div_4000[] = { 20, 12, 10 };
6950         static const uint8_t div_5333[] = { 24, 16, 14 };
6951         const uint8_t *div_table;
6952         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6953         uint16_t tmp = 0;
6954
6955         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6956
6957         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6958
6959         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6960                 goto fail;
6961
6962         switch (vco) {
6963         case 3200000:
6964                 div_table = div_3200;
6965                 break;
6966         case 4000000:
6967                 div_table = div_4000;
6968                 break;
6969         case 5333333:
6970                 div_table = div_5333;
6971                 break;
6972         default:
6973                 goto fail;
6974         }
6975
6976         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6977
6978 fail:
6979         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6980         return 200000;
6981 }
6982
6983 static int g33_get_display_clock_speed(struct drm_device *dev)
6984 {
6985         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6986         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6987         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6988         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6989         const uint8_t *div_table;
6990         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6991         uint16_t tmp = 0;
6992
6993         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6994
6995         cdclk_sel = (tmp >> 4) & 0x7;
6996
6997         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6998                 goto fail;
6999
7000         switch (vco) {
7001         case 3200000:
7002                 div_table = div_3200;
7003                 break;
7004         case 4000000:
7005                 div_table = div_4000;
7006                 break;
7007         case 4800000:
7008                 div_table = div_4800;
7009                 break;
7010         case 5333333:
7011                 div_table = div_5333;
7012                 break;
7013         default:
7014                 goto fail;
7015         }
7016
7017         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7018
7019 fail:
7020         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7021         return 190476;
7022 }
7023
7024 static void
7025 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7026 {
7027         while (*num > DATA_LINK_M_N_MASK ||
7028                *den > DATA_LINK_M_N_MASK) {
7029                 *num >>= 1;
7030                 *den >>= 1;
7031         }
7032 }
7033
7034 static void compute_m_n(unsigned int m, unsigned int n,
7035                         uint32_t *ret_m, uint32_t *ret_n)
7036 {
7037         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7038         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7039         intel_reduce_m_n_ratio(ret_m, ret_n);
7040 }
7041
7042 void
7043 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7044                        int pixel_clock, int link_clock,
7045                        struct intel_link_m_n *m_n)
7046 {
7047         m_n->tu = 64;
7048
7049         compute_m_n(bits_per_pixel * pixel_clock,
7050                     link_clock * nlanes * 8,
7051                     &m_n->gmch_m, &m_n->gmch_n);
7052
7053         compute_m_n(pixel_clock, link_clock,
7054                     &m_n->link_m, &m_n->link_n);
7055 }
7056
7057 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7058 {
7059         if (i915.panel_use_ssc >= 0)
7060                 return i915.panel_use_ssc != 0;
7061         return dev_priv->vbt.lvds_use_ssc
7062                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7063 }
7064
7065 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7066                            int num_connectors)
7067 {
7068         struct drm_device *dev = crtc_state->base.crtc->dev;
7069         struct drm_i915_private *dev_priv = dev->dev_private;
7070         int refclk;
7071
7072         WARN_ON(!crtc_state->base.state);
7073
7074         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7075                 refclk = 100000;
7076         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7077             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7078                 refclk = dev_priv->vbt.lvds_ssc_freq;
7079                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7080         } else if (!IS_GEN2(dev)) {
7081                 refclk = 96000;
7082         } else {
7083                 refclk = 48000;
7084         }
7085
7086         return refclk;
7087 }
7088
7089 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7090 {
7091         return (1 << dpll->n) << 16 | dpll->m2;
7092 }
7093
7094 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7095 {
7096         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7097 }
7098
7099 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7100                                      struct intel_crtc_state *crtc_state,
7101                                      intel_clock_t *reduced_clock)
7102 {
7103         struct drm_device *dev = crtc->base.dev;
7104         u32 fp, fp2 = 0;
7105
7106         if (IS_PINEVIEW(dev)) {
7107                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7108                 if (reduced_clock)
7109                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7110         } else {
7111                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7112                 if (reduced_clock)
7113                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7114         }
7115
7116         crtc_state->dpll_hw_state.fp0 = fp;
7117
7118         crtc->lowfreq_avail = false;
7119         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7120             reduced_clock) {
7121                 crtc_state->dpll_hw_state.fp1 = fp2;
7122                 crtc->lowfreq_avail = true;
7123         } else {
7124                 crtc_state->dpll_hw_state.fp1 = fp;
7125         }
7126 }
7127
7128 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7129                 pipe)
7130 {
7131         u32 reg_val;
7132
7133         /*
7134          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7135          * and set it to a reasonable value instead.
7136          */
7137         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7138         reg_val &= 0xffffff00;
7139         reg_val |= 0x00000030;
7140         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7141
7142         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7143         reg_val &= 0x8cffffff;
7144         reg_val = 0x8c000000;
7145         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7146
7147         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7148         reg_val &= 0xffffff00;
7149         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7150
7151         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7152         reg_val &= 0x00ffffff;
7153         reg_val |= 0xb0000000;
7154         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7155 }
7156
7157 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7158                                          struct intel_link_m_n *m_n)
7159 {
7160         struct drm_device *dev = crtc->base.dev;
7161         struct drm_i915_private *dev_priv = dev->dev_private;
7162         int pipe = crtc->pipe;
7163
7164         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7165         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7166         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7167         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7168 }
7169
7170 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7171                                          struct intel_link_m_n *m_n,
7172                                          struct intel_link_m_n *m2_n2)
7173 {
7174         struct drm_device *dev = crtc->base.dev;
7175         struct drm_i915_private *dev_priv = dev->dev_private;
7176         int pipe = crtc->pipe;
7177         enum transcoder transcoder = crtc->config->cpu_transcoder;
7178
7179         if (INTEL_INFO(dev)->gen >= 5) {
7180                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7181                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7182                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7183                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7184                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7185                  * for gen < 8) and if DRRS is supported (to make sure the
7186                  * registers are not unnecessarily accessed).
7187                  */
7188                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7189                         crtc->config->has_drrs) {
7190                         I915_WRITE(PIPE_DATA_M2(transcoder),
7191                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7192                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7193                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7194                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7195                 }
7196         } else {
7197                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7198                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7199                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7200                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7201         }
7202 }
7203
7204 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7205 {
7206         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7207
7208         if (m_n == M1_N1) {
7209                 dp_m_n = &crtc->config->dp_m_n;
7210                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7211         } else if (m_n == M2_N2) {
7212
7213                 /*
7214                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7215                  * needs to be programmed into M1_N1.
7216                  */
7217                 dp_m_n = &crtc->config->dp_m2_n2;
7218         } else {
7219                 DRM_ERROR("Unsupported divider value\n");
7220                 return;
7221         }
7222
7223         if (crtc->config->has_pch_encoder)
7224                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7225         else
7226                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7227 }
7228
7229 static void vlv_compute_dpll(struct intel_crtc *crtc,
7230                              struct intel_crtc_state *pipe_config)
7231 {
7232         u32 dpll, dpll_md;
7233
7234         /*
7235          * Enable DPIO clock input. We should never disable the reference
7236          * clock for pipe B, since VGA hotplug / manual detection depends
7237          * on it.
7238          */
7239         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7240                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7241         /* We should never disable this, set it here for state tracking */
7242         if (crtc->pipe == PIPE_B)
7243                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7244         dpll |= DPLL_VCO_ENABLE;
7245         pipe_config->dpll_hw_state.dpll = dpll;
7246
7247         dpll_md = (pipe_config->pixel_multiplier - 1)
7248                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7249         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7250 }
7251
7252 static void vlv_prepare_pll(struct intel_crtc *crtc,
7253                             const struct intel_crtc_state *pipe_config)
7254 {
7255         struct drm_device *dev = crtc->base.dev;
7256         struct drm_i915_private *dev_priv = dev->dev_private;
7257         int pipe = crtc->pipe;
7258         u32 mdiv;
7259         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7260         u32 coreclk, reg_val;
7261
7262         mutex_lock(&dev_priv->sb_lock);
7263
7264         bestn = pipe_config->dpll.n;
7265         bestm1 = pipe_config->dpll.m1;
7266         bestm2 = pipe_config->dpll.m2;
7267         bestp1 = pipe_config->dpll.p1;
7268         bestp2 = pipe_config->dpll.p2;
7269
7270         /* See eDP HDMI DPIO driver vbios notes doc */
7271
7272         /* PLL B needs special handling */
7273         if (pipe == PIPE_B)
7274                 vlv_pllb_recal_opamp(dev_priv, pipe);
7275
7276         /* Set up Tx target for periodic Rcomp update */
7277         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7278
7279         /* Disable target IRef on PLL */
7280         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7281         reg_val &= 0x00ffffff;
7282         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7283
7284         /* Disable fast lock */
7285         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7286
7287         /* Set idtafcrecal before PLL is enabled */
7288         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7289         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7290         mdiv |= ((bestn << DPIO_N_SHIFT));
7291         mdiv |= (1 << DPIO_K_SHIFT);
7292
7293         /*
7294          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7295          * but we don't support that).
7296          * Note: don't use the DAC post divider as it seems unstable.
7297          */
7298         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7299         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7300
7301         mdiv |= DPIO_ENABLE_CALIBRATION;
7302         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7303
7304         /* Set HBR and RBR LPF coefficients */
7305         if (pipe_config->port_clock == 162000 ||
7306             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7307             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7308                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7309                                  0x009f0003);
7310         else
7311                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7312                                  0x00d0000f);
7313
7314         if (pipe_config->has_dp_encoder) {
7315                 /* Use SSC source */
7316                 if (pipe == PIPE_A)
7317                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7318                                          0x0df40000);
7319                 else
7320                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7321                                          0x0df70000);
7322         } else { /* HDMI or VGA */
7323                 /* Use bend source */
7324                 if (pipe == PIPE_A)
7325                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7326                                          0x0df70000);
7327                 else
7328                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7329                                          0x0df40000);
7330         }
7331
7332         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7333         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7334         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7335             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7336                 coreclk |= 0x01000000;
7337         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7338
7339         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7340         mutex_unlock(&dev_priv->sb_lock);
7341 }
7342
7343 static void chv_compute_dpll(struct intel_crtc *crtc,
7344                              struct intel_crtc_state *pipe_config)
7345 {
7346         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7347                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7348                 DPLL_VCO_ENABLE;
7349         if (crtc->pipe != PIPE_A)
7350                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7351
7352         pipe_config->dpll_hw_state.dpll_md =
7353                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7354 }
7355
7356 static void chv_prepare_pll(struct intel_crtc *crtc,
7357                             const struct intel_crtc_state *pipe_config)
7358 {
7359         struct drm_device *dev = crtc->base.dev;
7360         struct drm_i915_private *dev_priv = dev->dev_private;
7361         int pipe = crtc->pipe;
7362         int dpll_reg = DPLL(crtc->pipe);
7363         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7364         u32 loopfilter, tribuf_calcntr;
7365         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7366         u32 dpio_val;
7367         int vco;
7368
7369         bestn = pipe_config->dpll.n;
7370         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7371         bestm1 = pipe_config->dpll.m1;
7372         bestm2 = pipe_config->dpll.m2 >> 22;
7373         bestp1 = pipe_config->dpll.p1;
7374         bestp2 = pipe_config->dpll.p2;
7375         vco = pipe_config->dpll.vco;
7376         dpio_val = 0;
7377         loopfilter = 0;
7378
7379         /*
7380          * Enable Refclk and SSC
7381          */
7382         I915_WRITE(dpll_reg,
7383                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7384
7385         mutex_lock(&dev_priv->sb_lock);
7386
7387         /* p1 and p2 divider */
7388         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7389                         5 << DPIO_CHV_S1_DIV_SHIFT |
7390                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7391                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7392                         1 << DPIO_CHV_K_DIV_SHIFT);
7393
7394         /* Feedback post-divider - m2 */
7395         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7396
7397         /* Feedback refclk divider - n and m1 */
7398         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7399                         DPIO_CHV_M1_DIV_BY_2 |
7400                         1 << DPIO_CHV_N_DIV_SHIFT);
7401
7402         /* M2 fraction division */
7403         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7404
7405         /* M2 fraction division enable */
7406         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7407         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7408         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7409         if (bestm2_frac)
7410                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7411         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7412
7413         /* Program digital lock detect threshold */
7414         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7415         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7416                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7417         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7418         if (!bestm2_frac)
7419                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7420         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7421
7422         /* Loop filter */
7423         if (vco == 5400000) {
7424                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7425                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7426                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7427                 tribuf_calcntr = 0x9;
7428         } else if (vco <= 6200000) {
7429                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7430                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7431                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7432                 tribuf_calcntr = 0x9;
7433         } else if (vco <= 6480000) {
7434                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7435                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7436                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7437                 tribuf_calcntr = 0x8;
7438         } else {
7439                 /* Not supported. Apply the same limits as in the max case */
7440                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7441                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7442                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7443                 tribuf_calcntr = 0;
7444         }
7445         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7446
7447         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7448         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7449         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7450         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7451
7452         /* AFC Recal */
7453         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7454                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7455                         DPIO_AFC_RECAL);
7456
7457         mutex_unlock(&dev_priv->sb_lock);
7458 }
7459
7460 /**
7461  * vlv_force_pll_on - forcibly enable just the PLL
7462  * @dev_priv: i915 private structure
7463  * @pipe: pipe PLL to enable
7464  * @dpll: PLL configuration
7465  *
7466  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7467  * in cases where we need the PLL enabled even when @pipe is not going to
7468  * be enabled.
7469  */
7470 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7471                       const struct dpll *dpll)
7472 {
7473         struct intel_crtc *crtc =
7474                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7475         struct intel_crtc_state pipe_config = {
7476                 .base.crtc = &crtc->base,
7477                 .pixel_multiplier = 1,
7478                 .dpll = *dpll,
7479         };
7480
7481         if (IS_CHERRYVIEW(dev)) {
7482                 chv_compute_dpll(crtc, &pipe_config);
7483                 chv_prepare_pll(crtc, &pipe_config);
7484                 chv_enable_pll(crtc, &pipe_config);
7485         } else {
7486                 vlv_compute_dpll(crtc, &pipe_config);
7487                 vlv_prepare_pll(crtc, &pipe_config);
7488                 vlv_enable_pll(crtc, &pipe_config);
7489         }
7490 }
7491
7492 /**
7493  * vlv_force_pll_off - forcibly disable just the PLL
7494  * @dev_priv: i915 private structure
7495  * @pipe: pipe PLL to disable
7496  *
7497  * Disable the PLL for @pipe. To be used in cases where we need
7498  * the PLL enabled even when @pipe is not going to be enabled.
7499  */
7500 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7501 {
7502         if (IS_CHERRYVIEW(dev))
7503                 chv_disable_pll(to_i915(dev), pipe);
7504         else
7505                 vlv_disable_pll(to_i915(dev), pipe);
7506 }
7507
7508 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7509                               struct intel_crtc_state *crtc_state,
7510                               intel_clock_t *reduced_clock,
7511                               int num_connectors)
7512 {
7513         struct drm_device *dev = crtc->base.dev;
7514         struct drm_i915_private *dev_priv = dev->dev_private;
7515         u32 dpll;
7516         bool is_sdvo;
7517         struct dpll *clock = &crtc_state->dpll;
7518
7519         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7520
7521         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7522                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7523
7524         dpll = DPLL_VGA_MODE_DIS;
7525
7526         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7527                 dpll |= DPLLB_MODE_LVDS;
7528         else
7529                 dpll |= DPLLB_MODE_DAC_SERIAL;
7530
7531         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7532                 dpll |= (crtc_state->pixel_multiplier - 1)
7533                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7534         }
7535
7536         if (is_sdvo)
7537                 dpll |= DPLL_SDVO_HIGH_SPEED;
7538
7539         if (crtc_state->has_dp_encoder)
7540                 dpll |= DPLL_SDVO_HIGH_SPEED;
7541
7542         /* compute bitmask from p1 value */
7543         if (IS_PINEVIEW(dev))
7544                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7545         else {
7546                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7547                 if (IS_G4X(dev) && reduced_clock)
7548                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7549         }
7550         switch (clock->p2) {
7551         case 5:
7552                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7553                 break;
7554         case 7:
7555                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7556                 break;
7557         case 10:
7558                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7559                 break;
7560         case 14:
7561                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7562                 break;
7563         }
7564         if (INTEL_INFO(dev)->gen >= 4)
7565                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7566
7567         if (crtc_state->sdvo_tv_clock)
7568                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7569         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7570                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7571                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7572         else
7573                 dpll |= PLL_REF_INPUT_DREFCLK;
7574
7575         dpll |= DPLL_VCO_ENABLE;
7576         crtc_state->dpll_hw_state.dpll = dpll;
7577
7578         if (INTEL_INFO(dev)->gen >= 4) {
7579                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7580                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7581                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7582         }
7583 }
7584
7585 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7586                               struct intel_crtc_state *crtc_state,
7587                               intel_clock_t *reduced_clock,
7588                               int num_connectors)
7589 {
7590         struct drm_device *dev = crtc->base.dev;
7591         struct drm_i915_private *dev_priv = dev->dev_private;
7592         u32 dpll;
7593         struct dpll *clock = &crtc_state->dpll;
7594
7595         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7596
7597         dpll = DPLL_VGA_MODE_DIS;
7598
7599         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7600                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7601         } else {
7602                 if (clock->p1 == 2)
7603                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7604                 else
7605                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7606                 if (clock->p2 == 4)
7607                         dpll |= PLL_P2_DIVIDE_BY_4;
7608         }
7609
7610         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7611                 dpll |= DPLL_DVO_2X_MODE;
7612
7613         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7614                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7615                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7616         else
7617                 dpll |= PLL_REF_INPUT_DREFCLK;
7618
7619         dpll |= DPLL_VCO_ENABLE;
7620         crtc_state->dpll_hw_state.dpll = dpll;
7621 }
7622
7623 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7624 {
7625         struct drm_device *dev = intel_crtc->base.dev;
7626         struct drm_i915_private *dev_priv = dev->dev_private;
7627         enum pipe pipe = intel_crtc->pipe;
7628         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7629         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7630         uint32_t crtc_vtotal, crtc_vblank_end;
7631         int vsyncshift = 0;
7632
7633         /* We need to be careful not to changed the adjusted mode, for otherwise
7634          * the hw state checker will get angry at the mismatch. */
7635         crtc_vtotal = adjusted_mode->crtc_vtotal;
7636         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7637
7638         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7639                 /* the chip adds 2 halflines automatically */
7640                 crtc_vtotal -= 1;
7641                 crtc_vblank_end -= 1;
7642
7643                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7644                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7645                 else
7646                         vsyncshift = adjusted_mode->crtc_hsync_start -
7647                                 adjusted_mode->crtc_htotal / 2;
7648                 if (vsyncshift < 0)
7649                         vsyncshift += adjusted_mode->crtc_htotal;
7650         }
7651
7652         if (INTEL_INFO(dev)->gen > 3)
7653                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7654
7655         I915_WRITE(HTOTAL(cpu_transcoder),
7656                    (adjusted_mode->crtc_hdisplay - 1) |
7657                    ((adjusted_mode->crtc_htotal - 1) << 16));
7658         I915_WRITE(HBLANK(cpu_transcoder),
7659                    (adjusted_mode->crtc_hblank_start - 1) |
7660                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7661         I915_WRITE(HSYNC(cpu_transcoder),
7662                    (adjusted_mode->crtc_hsync_start - 1) |
7663                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7664
7665         I915_WRITE(VTOTAL(cpu_transcoder),
7666                    (adjusted_mode->crtc_vdisplay - 1) |
7667                    ((crtc_vtotal - 1) << 16));
7668         I915_WRITE(VBLANK(cpu_transcoder),
7669                    (adjusted_mode->crtc_vblank_start - 1) |
7670                    ((crtc_vblank_end - 1) << 16));
7671         I915_WRITE(VSYNC(cpu_transcoder),
7672                    (adjusted_mode->crtc_vsync_start - 1) |
7673                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7674
7675         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7676          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7677          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7678          * bits. */
7679         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7680             (pipe == PIPE_B || pipe == PIPE_C))
7681                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7682
7683         /* pipesrc controls the size that is scaled from, which should
7684          * always be the user's requested size.
7685          */
7686         I915_WRITE(PIPESRC(pipe),
7687                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7688                    (intel_crtc->config->pipe_src_h - 1));
7689 }
7690
7691 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7692                                    struct intel_crtc_state *pipe_config)
7693 {
7694         struct drm_device *dev = crtc->base.dev;
7695         struct drm_i915_private *dev_priv = dev->dev_private;
7696         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7697         uint32_t tmp;
7698
7699         tmp = I915_READ(HTOTAL(cpu_transcoder));
7700         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7701         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7702         tmp = I915_READ(HBLANK(cpu_transcoder));
7703         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7704         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7705         tmp = I915_READ(HSYNC(cpu_transcoder));
7706         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7707         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7708
7709         tmp = I915_READ(VTOTAL(cpu_transcoder));
7710         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7711         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7712         tmp = I915_READ(VBLANK(cpu_transcoder));
7713         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7714         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7715         tmp = I915_READ(VSYNC(cpu_transcoder));
7716         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7717         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7718
7719         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7720                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7721                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7722                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7723         }
7724
7725         tmp = I915_READ(PIPESRC(crtc->pipe));
7726         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7727         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7728
7729         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7730         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7731 }
7732
7733 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7734                                  struct intel_crtc_state *pipe_config)
7735 {
7736         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7737         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7738         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7739         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7740
7741         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7742         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7743         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7744         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7745
7746         mode->flags = pipe_config->base.adjusted_mode.flags;
7747         mode->type = DRM_MODE_TYPE_DRIVER;
7748
7749         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7750         mode->flags |= pipe_config->base.adjusted_mode.flags;
7751
7752         mode->hsync = drm_mode_hsync(mode);
7753         mode->vrefresh = drm_mode_vrefresh(mode);
7754         drm_mode_set_name(mode);
7755 }
7756
7757 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7758 {
7759         struct drm_device *dev = intel_crtc->base.dev;
7760         struct drm_i915_private *dev_priv = dev->dev_private;
7761         uint32_t pipeconf;
7762
7763         pipeconf = 0;
7764
7765         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7766             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7767                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7768
7769         if (intel_crtc->config->double_wide)
7770                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7771
7772         /* only g4x and later have fancy bpc/dither controls */
7773         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7774                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7775                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7776                         pipeconf |= PIPECONF_DITHER_EN |
7777                                     PIPECONF_DITHER_TYPE_SP;
7778
7779                 switch (intel_crtc->config->pipe_bpp) {
7780                 case 18:
7781                         pipeconf |= PIPECONF_6BPC;
7782                         break;
7783                 case 24:
7784                         pipeconf |= PIPECONF_8BPC;
7785                         break;
7786                 case 30:
7787                         pipeconf |= PIPECONF_10BPC;
7788                         break;
7789                 default:
7790                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7791                         BUG();
7792                 }
7793         }
7794
7795         if (HAS_PIPE_CXSR(dev)) {
7796                 if (intel_crtc->lowfreq_avail) {
7797                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7798                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7799                 } else {
7800                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7801                 }
7802         }
7803
7804         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7805                 if (INTEL_INFO(dev)->gen < 4 ||
7806                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7807                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7808                 else
7809                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7810         } else
7811                 pipeconf |= PIPECONF_PROGRESSIVE;
7812
7813         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7814                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7815
7816         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7817         POSTING_READ(PIPECONF(intel_crtc->pipe));
7818 }
7819
7820 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7821                                    struct intel_crtc_state *crtc_state)
7822 {
7823         struct drm_device *dev = crtc->base.dev;
7824         struct drm_i915_private *dev_priv = dev->dev_private;
7825         int refclk, num_connectors = 0;
7826         intel_clock_t clock;
7827         bool ok;
7828         bool is_dsi = false;
7829         struct intel_encoder *encoder;
7830         const intel_limit_t *limit;
7831         struct drm_atomic_state *state = crtc_state->base.state;
7832         struct drm_connector *connector;
7833         struct drm_connector_state *connector_state;
7834         int i;
7835
7836         memset(&crtc_state->dpll_hw_state, 0,
7837                sizeof(crtc_state->dpll_hw_state));
7838
7839         for_each_connector_in_state(state, connector, connector_state, i) {
7840                 if (connector_state->crtc != &crtc->base)
7841                         continue;
7842
7843                 encoder = to_intel_encoder(connector_state->best_encoder);
7844
7845                 switch (encoder->type) {
7846                 case INTEL_OUTPUT_DSI:
7847                         is_dsi = true;
7848                         break;
7849                 default:
7850                         break;
7851                 }
7852
7853                 num_connectors++;
7854         }
7855
7856         if (is_dsi)
7857                 return 0;
7858
7859         if (!crtc_state->clock_set) {
7860                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7861
7862                 /*
7863                  * Returns a set of divisors for the desired target clock with
7864                  * the given refclk, or FALSE.  The returned values represent
7865                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7866                  * 2) / p1 / p2.
7867                  */
7868                 limit = intel_limit(crtc_state, refclk);
7869                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7870                                                  crtc_state->port_clock,
7871                                                  refclk, NULL, &clock);
7872                 if (!ok) {
7873                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7874                         return -EINVAL;
7875                 }
7876
7877                 /* Compat-code for transition, will disappear. */
7878                 crtc_state->dpll.n = clock.n;
7879                 crtc_state->dpll.m1 = clock.m1;
7880                 crtc_state->dpll.m2 = clock.m2;
7881                 crtc_state->dpll.p1 = clock.p1;
7882                 crtc_state->dpll.p2 = clock.p2;
7883         }
7884
7885         if (IS_GEN2(dev)) {
7886                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7887                                   num_connectors);
7888         } else if (IS_CHERRYVIEW(dev)) {
7889                 chv_compute_dpll(crtc, crtc_state);
7890         } else if (IS_VALLEYVIEW(dev)) {
7891                 vlv_compute_dpll(crtc, crtc_state);
7892         } else {
7893                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7894                                   num_connectors);
7895         }
7896
7897         return 0;
7898 }
7899
7900 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7901                                  struct intel_crtc_state *pipe_config)
7902 {
7903         struct drm_device *dev = crtc->base.dev;
7904         struct drm_i915_private *dev_priv = dev->dev_private;
7905         uint32_t tmp;
7906
7907         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7908                 return;
7909
7910         tmp = I915_READ(PFIT_CONTROL);
7911         if (!(tmp & PFIT_ENABLE))
7912                 return;
7913
7914         /* Check whether the pfit is attached to our pipe. */
7915         if (INTEL_INFO(dev)->gen < 4) {
7916                 if (crtc->pipe != PIPE_B)
7917                         return;
7918         } else {
7919                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7920                         return;
7921         }
7922
7923         pipe_config->gmch_pfit.control = tmp;
7924         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7925         if (INTEL_INFO(dev)->gen < 5)
7926                 pipe_config->gmch_pfit.lvds_border_bits =
7927                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7928 }
7929
7930 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7931                                struct intel_crtc_state *pipe_config)
7932 {
7933         struct drm_device *dev = crtc->base.dev;
7934         struct drm_i915_private *dev_priv = dev->dev_private;
7935         int pipe = pipe_config->cpu_transcoder;
7936         intel_clock_t clock;
7937         u32 mdiv;
7938         int refclk = 100000;
7939
7940         /* In case of MIPI DPLL will not even be used */
7941         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7942                 return;
7943
7944         mutex_lock(&dev_priv->sb_lock);
7945         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7946         mutex_unlock(&dev_priv->sb_lock);
7947
7948         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7949         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7950         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7951         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7952         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7953
7954         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7955 }
7956
7957 static void
7958 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7959                               struct intel_initial_plane_config *plane_config)
7960 {
7961         struct drm_device *dev = crtc->base.dev;
7962         struct drm_i915_private *dev_priv = dev->dev_private;
7963         u32 val, base, offset;
7964         int pipe = crtc->pipe, plane = crtc->plane;
7965         int fourcc, pixel_format;
7966         unsigned int aligned_height;
7967         struct drm_framebuffer *fb;
7968         struct intel_framebuffer *intel_fb;
7969
7970         val = I915_READ(DSPCNTR(plane));
7971         if (!(val & DISPLAY_PLANE_ENABLE))
7972                 return;
7973
7974         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7975         if (!intel_fb) {
7976                 DRM_DEBUG_KMS("failed to alloc fb\n");
7977                 return;
7978         }
7979
7980         fb = &intel_fb->base;
7981
7982         if (INTEL_INFO(dev)->gen >= 4) {
7983                 if (val & DISPPLANE_TILED) {
7984                         plane_config->tiling = I915_TILING_X;
7985                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7986                 }
7987         }
7988
7989         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7990         fourcc = i9xx_format_to_fourcc(pixel_format);
7991         fb->pixel_format = fourcc;
7992         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7993
7994         if (INTEL_INFO(dev)->gen >= 4) {
7995                 if (plane_config->tiling)
7996                         offset = I915_READ(DSPTILEOFF(plane));
7997                 else
7998                         offset = I915_READ(DSPLINOFF(plane));
7999                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8000         } else {
8001                 base = I915_READ(DSPADDR(plane));
8002         }
8003         plane_config->base = base;
8004
8005         val = I915_READ(PIPESRC(pipe));
8006         fb->width = ((val >> 16) & 0xfff) + 1;
8007         fb->height = ((val >> 0) & 0xfff) + 1;
8008
8009         val = I915_READ(DSPSTRIDE(pipe));
8010         fb->pitches[0] = val & 0xffffffc0;
8011
8012         aligned_height = intel_fb_align_height(dev, fb->height,
8013                                                fb->pixel_format,
8014                                                fb->modifier[0]);
8015
8016         plane_config->size = fb->pitches[0] * aligned_height;
8017
8018         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8019                       pipe_name(pipe), plane, fb->width, fb->height,
8020                       fb->bits_per_pixel, base, fb->pitches[0],
8021                       plane_config->size);
8022
8023         plane_config->fb = intel_fb;
8024 }
8025
8026 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8027                                struct intel_crtc_state *pipe_config)
8028 {
8029         struct drm_device *dev = crtc->base.dev;
8030         struct drm_i915_private *dev_priv = dev->dev_private;
8031         int pipe = pipe_config->cpu_transcoder;
8032         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8033         intel_clock_t clock;
8034         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8035         int refclk = 100000;
8036
8037         mutex_lock(&dev_priv->sb_lock);
8038         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8039         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8040         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8041         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8042         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8043         mutex_unlock(&dev_priv->sb_lock);
8044
8045         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8046         clock.m2 = (pll_dw0 & 0xff) << 22;
8047         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8048                 clock.m2 |= pll_dw2 & 0x3fffff;
8049         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8050         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8051         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8052
8053         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8054 }
8055
8056 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8057                                  struct intel_crtc_state *pipe_config)
8058 {
8059         struct drm_device *dev = crtc->base.dev;
8060         struct drm_i915_private *dev_priv = dev->dev_private;
8061         uint32_t tmp;
8062
8063         if (!intel_display_power_is_enabled(dev_priv,
8064                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8065                 return false;
8066
8067         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8068         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8069
8070         tmp = I915_READ(PIPECONF(crtc->pipe));
8071         if (!(tmp & PIPECONF_ENABLE))
8072                 return false;
8073
8074         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8075                 switch (tmp & PIPECONF_BPC_MASK) {
8076                 case PIPECONF_6BPC:
8077                         pipe_config->pipe_bpp = 18;
8078                         break;
8079                 case PIPECONF_8BPC:
8080                         pipe_config->pipe_bpp = 24;
8081                         break;
8082                 case PIPECONF_10BPC:
8083                         pipe_config->pipe_bpp = 30;
8084                         break;
8085                 default:
8086                         break;
8087                 }
8088         }
8089
8090         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8091                 pipe_config->limited_color_range = true;
8092
8093         if (INTEL_INFO(dev)->gen < 4)
8094                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8095
8096         intel_get_pipe_timings(crtc, pipe_config);
8097
8098         i9xx_get_pfit_config(crtc, pipe_config);
8099
8100         if (INTEL_INFO(dev)->gen >= 4) {
8101                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8102                 pipe_config->pixel_multiplier =
8103                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8104                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8105                 pipe_config->dpll_hw_state.dpll_md = tmp;
8106         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8107                 tmp = I915_READ(DPLL(crtc->pipe));
8108                 pipe_config->pixel_multiplier =
8109                         ((tmp & SDVO_MULTIPLIER_MASK)
8110                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8111         } else {
8112                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8113                  * port and will be fixed up in the encoder->get_config
8114                  * function. */
8115                 pipe_config->pixel_multiplier = 1;
8116         }
8117         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8118         if (!IS_VALLEYVIEW(dev)) {
8119                 /*
8120                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8121                  * on 830. Filter it out here so that we don't
8122                  * report errors due to that.
8123                  */
8124                 if (IS_I830(dev))
8125                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8126
8127                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8128                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8129         } else {
8130                 /* Mask out read-only status bits. */
8131                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8132                                                      DPLL_PORTC_READY_MASK |
8133                                                      DPLL_PORTB_READY_MASK);
8134         }
8135
8136         if (IS_CHERRYVIEW(dev))
8137                 chv_crtc_clock_get(crtc, pipe_config);
8138         else if (IS_VALLEYVIEW(dev))
8139                 vlv_crtc_clock_get(crtc, pipe_config);
8140         else
8141                 i9xx_crtc_clock_get(crtc, pipe_config);
8142
8143         /*
8144          * Normally the dotclock is filled in by the encoder .get_config()
8145          * but in case the pipe is enabled w/o any ports we need a sane
8146          * default.
8147          */
8148         pipe_config->base.adjusted_mode.crtc_clock =
8149                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8150
8151         return true;
8152 }
8153
8154 static void ironlake_init_pch_refclk(struct drm_device *dev)
8155 {
8156         struct drm_i915_private *dev_priv = dev->dev_private;
8157         struct intel_encoder *encoder;
8158         u32 val, final;
8159         bool has_lvds = false;
8160         bool has_cpu_edp = false;
8161         bool has_panel = false;
8162         bool has_ck505 = false;
8163         bool can_ssc = false;
8164
8165         /* We need to take the global config into account */
8166         for_each_intel_encoder(dev, encoder) {
8167                 switch (encoder->type) {
8168                 case INTEL_OUTPUT_LVDS:
8169                         has_panel = true;
8170                         has_lvds = true;
8171                         break;
8172                 case INTEL_OUTPUT_EDP:
8173                         has_panel = true;
8174                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8175                                 has_cpu_edp = true;
8176                         break;
8177                 default:
8178                         break;
8179                 }
8180         }
8181
8182         if (HAS_PCH_IBX(dev)) {
8183                 has_ck505 = dev_priv->vbt.display_clock_mode;
8184                 can_ssc = has_ck505;
8185         } else {
8186                 has_ck505 = false;
8187                 can_ssc = true;
8188         }
8189
8190         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8191                       has_panel, has_lvds, has_ck505);
8192
8193         /* Ironlake: try to setup display ref clock before DPLL
8194          * enabling. This is only under driver's control after
8195          * PCH B stepping, previous chipset stepping should be
8196          * ignoring this setting.
8197          */
8198         val = I915_READ(PCH_DREF_CONTROL);
8199
8200         /* As we must carefully and slowly disable/enable each source in turn,
8201          * compute the final state we want first and check if we need to
8202          * make any changes at all.
8203          */
8204         final = val;
8205         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8206         if (has_ck505)
8207                 final |= DREF_NONSPREAD_CK505_ENABLE;
8208         else
8209                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8210
8211         final &= ~DREF_SSC_SOURCE_MASK;
8212         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8213         final &= ~DREF_SSC1_ENABLE;
8214
8215         if (has_panel) {
8216                 final |= DREF_SSC_SOURCE_ENABLE;
8217
8218                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8219                         final |= DREF_SSC1_ENABLE;
8220
8221                 if (has_cpu_edp) {
8222                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8223                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8224                         else
8225                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8226                 } else
8227                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8228         } else {
8229                 final |= DREF_SSC_SOURCE_DISABLE;
8230                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8231         }
8232
8233         if (final == val)
8234                 return;
8235
8236         /* Always enable nonspread source */
8237         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8238
8239         if (has_ck505)
8240                 val |= DREF_NONSPREAD_CK505_ENABLE;
8241         else
8242                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8243
8244         if (has_panel) {
8245                 val &= ~DREF_SSC_SOURCE_MASK;
8246                 val |= DREF_SSC_SOURCE_ENABLE;
8247
8248                 /* SSC must be turned on before enabling the CPU output  */
8249                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8250                         DRM_DEBUG_KMS("Using SSC on panel\n");
8251                         val |= DREF_SSC1_ENABLE;
8252                 } else
8253                         val &= ~DREF_SSC1_ENABLE;
8254
8255                 /* Get SSC going before enabling the outputs */
8256                 I915_WRITE(PCH_DREF_CONTROL, val);
8257                 POSTING_READ(PCH_DREF_CONTROL);
8258                 udelay(200);
8259
8260                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8261
8262                 /* Enable CPU source on CPU attached eDP */
8263                 if (has_cpu_edp) {
8264                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8265                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8266                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8267                         } else
8268                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8269                 } else
8270                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8271
8272                 I915_WRITE(PCH_DREF_CONTROL, val);
8273                 POSTING_READ(PCH_DREF_CONTROL);
8274                 udelay(200);
8275         } else {
8276                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8277
8278                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8279
8280                 /* Turn off CPU output */
8281                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8282
8283                 I915_WRITE(PCH_DREF_CONTROL, val);
8284                 POSTING_READ(PCH_DREF_CONTROL);
8285                 udelay(200);
8286
8287                 /* Turn off the SSC source */
8288                 val &= ~DREF_SSC_SOURCE_MASK;
8289                 val |= DREF_SSC_SOURCE_DISABLE;
8290
8291                 /* Turn off SSC1 */
8292                 val &= ~DREF_SSC1_ENABLE;
8293
8294                 I915_WRITE(PCH_DREF_CONTROL, val);
8295                 POSTING_READ(PCH_DREF_CONTROL);
8296                 udelay(200);
8297         }
8298
8299         BUG_ON(val != final);
8300 }
8301
8302 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8303 {
8304         uint32_t tmp;
8305
8306         tmp = I915_READ(SOUTH_CHICKEN2);
8307         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8308         I915_WRITE(SOUTH_CHICKEN2, tmp);
8309
8310         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8311                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8312                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8313
8314         tmp = I915_READ(SOUTH_CHICKEN2);
8315         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8316         I915_WRITE(SOUTH_CHICKEN2, tmp);
8317
8318         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8319                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8320                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8321 }
8322
8323 /* WaMPhyProgramming:hsw */
8324 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8325 {
8326         uint32_t tmp;
8327
8328         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8329         tmp &= ~(0xFF << 24);
8330         tmp |= (0x12 << 24);
8331         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8332
8333         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8334         tmp |= (1 << 11);
8335         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8336
8337         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8338         tmp |= (1 << 11);
8339         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8340
8341         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8342         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8343         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8344
8345         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8346         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8347         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8348
8349         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8350         tmp &= ~(7 << 13);
8351         tmp |= (5 << 13);
8352         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8353
8354         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8355         tmp &= ~(7 << 13);
8356         tmp |= (5 << 13);
8357         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8358
8359         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8360         tmp &= ~0xFF;
8361         tmp |= 0x1C;
8362         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8363
8364         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8365         tmp &= ~0xFF;
8366         tmp |= 0x1C;
8367         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8368
8369         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8370         tmp &= ~(0xFF << 16);
8371         tmp |= (0x1C << 16);
8372         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8373
8374         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8375         tmp &= ~(0xFF << 16);
8376         tmp |= (0x1C << 16);
8377         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8378
8379         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8380         tmp |= (1 << 27);
8381         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8382
8383         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8384         tmp |= (1 << 27);
8385         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8386
8387         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8388         tmp &= ~(0xF << 28);
8389         tmp |= (4 << 28);
8390         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8391
8392         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8393         tmp &= ~(0xF << 28);
8394         tmp |= (4 << 28);
8395         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8396 }
8397
8398 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8399  * Programming" based on the parameters passed:
8400  * - Sequence to enable CLKOUT_DP
8401  * - Sequence to enable CLKOUT_DP without spread
8402  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8403  */
8404 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8405                                  bool with_fdi)
8406 {
8407         struct drm_i915_private *dev_priv = dev->dev_private;
8408         uint32_t reg, tmp;
8409
8410         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8411                 with_spread = true;
8412         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8413                 with_fdi = false;
8414
8415         mutex_lock(&dev_priv->sb_lock);
8416
8417         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8418         tmp &= ~SBI_SSCCTL_DISABLE;
8419         tmp |= SBI_SSCCTL_PATHALT;
8420         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8421
8422         udelay(24);
8423
8424         if (with_spread) {
8425                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8426                 tmp &= ~SBI_SSCCTL_PATHALT;
8427                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8428
8429                 if (with_fdi) {
8430                         lpt_reset_fdi_mphy(dev_priv);
8431                         lpt_program_fdi_mphy(dev_priv);
8432                 }
8433         }
8434
8435         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8436         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8437         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8438         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8439
8440         mutex_unlock(&dev_priv->sb_lock);
8441 }
8442
8443 /* Sequence to disable CLKOUT_DP */
8444 static void lpt_disable_clkout_dp(struct drm_device *dev)
8445 {
8446         struct drm_i915_private *dev_priv = dev->dev_private;
8447         uint32_t reg, tmp;
8448
8449         mutex_lock(&dev_priv->sb_lock);
8450
8451         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8452         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8453         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8454         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8455
8456         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8457         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8458                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8459                         tmp |= SBI_SSCCTL_PATHALT;
8460                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8461                         udelay(32);
8462                 }
8463                 tmp |= SBI_SSCCTL_DISABLE;
8464                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8465         }
8466
8467         mutex_unlock(&dev_priv->sb_lock);
8468 }
8469
8470 static void lpt_init_pch_refclk(struct drm_device *dev)
8471 {
8472         struct intel_encoder *encoder;
8473         bool has_vga = false;
8474
8475         for_each_intel_encoder(dev, encoder) {
8476                 switch (encoder->type) {
8477                 case INTEL_OUTPUT_ANALOG:
8478                         has_vga = true;
8479                         break;
8480                 default:
8481                         break;
8482                 }
8483         }
8484
8485         if (has_vga)
8486                 lpt_enable_clkout_dp(dev, true, true);
8487         else
8488                 lpt_disable_clkout_dp(dev);
8489 }
8490
8491 /*
8492  * Initialize reference clocks when the driver loads
8493  */
8494 void intel_init_pch_refclk(struct drm_device *dev)
8495 {
8496         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8497                 ironlake_init_pch_refclk(dev);
8498         else if (HAS_PCH_LPT(dev))
8499                 lpt_init_pch_refclk(dev);
8500 }
8501
8502 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8503 {
8504         struct drm_device *dev = crtc_state->base.crtc->dev;
8505         struct drm_i915_private *dev_priv = dev->dev_private;
8506         struct drm_atomic_state *state = crtc_state->base.state;
8507         struct drm_connector *connector;
8508         struct drm_connector_state *connector_state;
8509         struct intel_encoder *encoder;
8510         int num_connectors = 0, i;
8511         bool is_lvds = false;
8512
8513         for_each_connector_in_state(state, connector, connector_state, i) {
8514                 if (connector_state->crtc != crtc_state->base.crtc)
8515                         continue;
8516
8517                 encoder = to_intel_encoder(connector_state->best_encoder);
8518
8519                 switch (encoder->type) {
8520                 case INTEL_OUTPUT_LVDS:
8521                         is_lvds = true;
8522                         break;
8523                 default:
8524                         break;
8525                 }
8526                 num_connectors++;
8527         }
8528
8529         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8530                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8531                               dev_priv->vbt.lvds_ssc_freq);
8532                 return dev_priv->vbt.lvds_ssc_freq;
8533         }
8534
8535         return 120000;
8536 }
8537
8538 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8539 {
8540         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8542         int pipe = intel_crtc->pipe;
8543         uint32_t val;
8544
8545         val = 0;
8546
8547         switch (intel_crtc->config->pipe_bpp) {
8548         case 18:
8549                 val |= PIPECONF_6BPC;
8550                 break;
8551         case 24:
8552                 val |= PIPECONF_8BPC;
8553                 break;
8554         case 30:
8555                 val |= PIPECONF_10BPC;
8556                 break;
8557         case 36:
8558                 val |= PIPECONF_12BPC;
8559                 break;
8560         default:
8561                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8562                 BUG();
8563         }
8564
8565         if (intel_crtc->config->dither)
8566                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8567
8568         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8569                 val |= PIPECONF_INTERLACED_ILK;
8570         else
8571                 val |= PIPECONF_PROGRESSIVE;
8572
8573         if (intel_crtc->config->limited_color_range)
8574                 val |= PIPECONF_COLOR_RANGE_SELECT;
8575
8576         I915_WRITE(PIPECONF(pipe), val);
8577         POSTING_READ(PIPECONF(pipe));
8578 }
8579
8580 /*
8581  * Set up the pipe CSC unit.
8582  *
8583  * Currently only full range RGB to limited range RGB conversion
8584  * is supported, but eventually this should handle various
8585  * RGB<->YCbCr scenarios as well.
8586  */
8587 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8588 {
8589         struct drm_device *dev = crtc->dev;
8590         struct drm_i915_private *dev_priv = dev->dev_private;
8591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8592         int pipe = intel_crtc->pipe;
8593         uint16_t coeff = 0x7800; /* 1.0 */
8594
8595         /*
8596          * TODO: Check what kind of values actually come out of the pipe
8597          * with these coeff/postoff values and adjust to get the best
8598          * accuracy. Perhaps we even need to take the bpc value into
8599          * consideration.
8600          */
8601
8602         if (intel_crtc->config->limited_color_range)
8603                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8604
8605         /*
8606          * GY/GU and RY/RU should be the other way around according
8607          * to BSpec, but reality doesn't agree. Just set them up in
8608          * a way that results in the correct picture.
8609          */
8610         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8611         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8612
8613         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8614         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8615
8616         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8617         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8618
8619         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8620         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8621         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8622
8623         if (INTEL_INFO(dev)->gen > 6) {
8624                 uint16_t postoff = 0;
8625
8626                 if (intel_crtc->config->limited_color_range)
8627                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8628
8629                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8630                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8631                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8632
8633                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8634         } else {
8635                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8636
8637                 if (intel_crtc->config->limited_color_range)
8638                         mode |= CSC_BLACK_SCREEN_OFFSET;
8639
8640                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8641         }
8642 }
8643
8644 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8645 {
8646         struct drm_device *dev = crtc->dev;
8647         struct drm_i915_private *dev_priv = dev->dev_private;
8648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8649         enum pipe pipe = intel_crtc->pipe;
8650         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8651         uint32_t val;
8652
8653         val = 0;
8654
8655         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8656                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8657
8658         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8659                 val |= PIPECONF_INTERLACED_ILK;
8660         else
8661                 val |= PIPECONF_PROGRESSIVE;
8662
8663         I915_WRITE(PIPECONF(cpu_transcoder), val);
8664         POSTING_READ(PIPECONF(cpu_transcoder));
8665
8666         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8667         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8668
8669         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8670                 val = 0;
8671
8672                 switch (intel_crtc->config->pipe_bpp) {
8673                 case 18:
8674                         val |= PIPEMISC_DITHER_6_BPC;
8675                         break;
8676                 case 24:
8677                         val |= PIPEMISC_DITHER_8_BPC;
8678                         break;
8679                 case 30:
8680                         val |= PIPEMISC_DITHER_10_BPC;
8681                         break;
8682                 case 36:
8683                         val |= PIPEMISC_DITHER_12_BPC;
8684                         break;
8685                 default:
8686                         /* Case prevented by pipe_config_set_bpp. */
8687                         BUG();
8688                 }
8689
8690                 if (intel_crtc->config->dither)
8691                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8692
8693                 I915_WRITE(PIPEMISC(pipe), val);
8694         }
8695 }
8696
8697 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8698                                     struct intel_crtc_state *crtc_state,
8699                                     intel_clock_t *clock,
8700                                     bool *has_reduced_clock,
8701                                     intel_clock_t *reduced_clock)
8702 {
8703         struct drm_device *dev = crtc->dev;
8704         struct drm_i915_private *dev_priv = dev->dev_private;
8705         int refclk;
8706         const intel_limit_t *limit;
8707         bool ret;
8708
8709         refclk = ironlake_get_refclk(crtc_state);
8710
8711         /*
8712          * Returns a set of divisors for the desired target clock with the given
8713          * refclk, or FALSE.  The returned values represent the clock equation:
8714          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8715          */
8716         limit = intel_limit(crtc_state, refclk);
8717         ret = dev_priv->display.find_dpll(limit, crtc_state,
8718                                           crtc_state->port_clock,
8719                                           refclk, NULL, clock);
8720         if (!ret)
8721                 return false;
8722
8723         return true;
8724 }
8725
8726 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8727 {
8728         /*
8729          * Account for spread spectrum to avoid
8730          * oversubscribing the link. Max center spread
8731          * is 2.5%; use 5% for safety's sake.
8732          */
8733         u32 bps = target_clock * bpp * 21 / 20;
8734         return DIV_ROUND_UP(bps, link_bw * 8);
8735 }
8736
8737 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8738 {
8739         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8740 }
8741
8742 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8743                                       struct intel_crtc_state *crtc_state,
8744                                       u32 *fp,
8745                                       intel_clock_t *reduced_clock, u32 *fp2)
8746 {
8747         struct drm_crtc *crtc = &intel_crtc->base;
8748         struct drm_device *dev = crtc->dev;
8749         struct drm_i915_private *dev_priv = dev->dev_private;
8750         struct drm_atomic_state *state = crtc_state->base.state;
8751         struct drm_connector *connector;
8752         struct drm_connector_state *connector_state;
8753         struct intel_encoder *encoder;
8754         uint32_t dpll;
8755         int factor, num_connectors = 0, i;
8756         bool is_lvds = false, is_sdvo = false;
8757
8758         for_each_connector_in_state(state, connector, connector_state, i) {
8759                 if (connector_state->crtc != crtc_state->base.crtc)
8760                         continue;
8761
8762                 encoder = to_intel_encoder(connector_state->best_encoder);
8763
8764                 switch (encoder->type) {
8765                 case INTEL_OUTPUT_LVDS:
8766                         is_lvds = true;
8767                         break;
8768                 case INTEL_OUTPUT_SDVO:
8769                 case INTEL_OUTPUT_HDMI:
8770                         is_sdvo = true;
8771                         break;
8772                 default:
8773                         break;
8774                 }
8775
8776                 num_connectors++;
8777         }
8778
8779         /* Enable autotuning of the PLL clock (if permissible) */
8780         factor = 21;
8781         if (is_lvds) {
8782                 if ((intel_panel_use_ssc(dev_priv) &&
8783                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8784                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8785                         factor = 25;
8786         } else if (crtc_state->sdvo_tv_clock)
8787                 factor = 20;
8788
8789         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8790                 *fp |= FP_CB_TUNE;
8791
8792         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8793                 *fp2 |= FP_CB_TUNE;
8794
8795         dpll = 0;
8796
8797         if (is_lvds)
8798                 dpll |= DPLLB_MODE_LVDS;
8799         else
8800                 dpll |= DPLLB_MODE_DAC_SERIAL;
8801
8802         dpll |= (crtc_state->pixel_multiplier - 1)
8803                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8804
8805         if (is_sdvo)
8806                 dpll |= DPLL_SDVO_HIGH_SPEED;
8807         if (crtc_state->has_dp_encoder)
8808                 dpll |= DPLL_SDVO_HIGH_SPEED;
8809
8810         /* compute bitmask from p1 value */
8811         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8812         /* also FPA1 */
8813         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8814
8815         switch (crtc_state->dpll.p2) {
8816         case 5:
8817                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8818                 break;
8819         case 7:
8820                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8821                 break;
8822         case 10:
8823                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8824                 break;
8825         case 14:
8826                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8827                 break;
8828         }
8829
8830         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8831                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8832         else
8833                 dpll |= PLL_REF_INPUT_DREFCLK;
8834
8835         return dpll | DPLL_VCO_ENABLE;
8836 }
8837
8838 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8839                                        struct intel_crtc_state *crtc_state)
8840 {
8841         struct drm_device *dev = crtc->base.dev;
8842         intel_clock_t clock, reduced_clock;
8843         u32 dpll = 0, fp = 0, fp2 = 0;
8844         bool ok, has_reduced_clock = false;
8845         bool is_lvds = false;
8846         struct intel_shared_dpll *pll;
8847
8848         memset(&crtc_state->dpll_hw_state, 0,
8849                sizeof(crtc_state->dpll_hw_state));
8850
8851         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8852
8853         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8854              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8855
8856         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8857                                      &has_reduced_clock, &reduced_clock);
8858         if (!ok && !crtc_state->clock_set) {
8859                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8860                 return -EINVAL;
8861         }
8862         /* Compat-code for transition, will disappear. */
8863         if (!crtc_state->clock_set) {
8864                 crtc_state->dpll.n = clock.n;
8865                 crtc_state->dpll.m1 = clock.m1;
8866                 crtc_state->dpll.m2 = clock.m2;
8867                 crtc_state->dpll.p1 = clock.p1;
8868                 crtc_state->dpll.p2 = clock.p2;
8869         }
8870
8871         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8872         if (crtc_state->has_pch_encoder) {
8873                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8874                 if (has_reduced_clock)
8875                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8876
8877                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8878                                              &fp, &reduced_clock,
8879                                              has_reduced_clock ? &fp2 : NULL);
8880
8881                 crtc_state->dpll_hw_state.dpll = dpll;
8882                 crtc_state->dpll_hw_state.fp0 = fp;
8883                 if (has_reduced_clock)
8884                         crtc_state->dpll_hw_state.fp1 = fp2;
8885                 else
8886                         crtc_state->dpll_hw_state.fp1 = fp;
8887
8888                 pll = intel_get_shared_dpll(crtc, crtc_state);
8889                 if (pll == NULL) {
8890                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8891                                          pipe_name(crtc->pipe));
8892                         return -EINVAL;
8893                 }
8894         }
8895
8896         if (is_lvds && has_reduced_clock)
8897                 crtc->lowfreq_avail = true;
8898         else
8899                 crtc->lowfreq_avail = false;
8900
8901         return 0;
8902 }
8903
8904 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8905                                          struct intel_link_m_n *m_n)
8906 {
8907         struct drm_device *dev = crtc->base.dev;
8908         struct drm_i915_private *dev_priv = dev->dev_private;
8909         enum pipe pipe = crtc->pipe;
8910
8911         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8912         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8913         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8914                 & ~TU_SIZE_MASK;
8915         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8916         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8917                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8918 }
8919
8920 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8921                                          enum transcoder transcoder,
8922                                          struct intel_link_m_n *m_n,
8923                                          struct intel_link_m_n *m2_n2)
8924 {
8925         struct drm_device *dev = crtc->base.dev;
8926         struct drm_i915_private *dev_priv = dev->dev_private;
8927         enum pipe pipe = crtc->pipe;
8928
8929         if (INTEL_INFO(dev)->gen >= 5) {
8930                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8931                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8932                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8933                         & ~TU_SIZE_MASK;
8934                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8935                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8936                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8937                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8938                  * gen < 8) and if DRRS is supported (to make sure the
8939                  * registers are not unnecessarily read).
8940                  */
8941                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8942                         crtc->config->has_drrs) {
8943                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8944                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8945                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8946                                         & ~TU_SIZE_MASK;
8947                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8948                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8949                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8950                 }
8951         } else {
8952                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8953                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8954                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8955                         & ~TU_SIZE_MASK;
8956                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8957                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8958                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8959         }
8960 }
8961
8962 void intel_dp_get_m_n(struct intel_crtc *crtc,
8963                       struct intel_crtc_state *pipe_config)
8964 {
8965         if (pipe_config->has_pch_encoder)
8966                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8967         else
8968                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8969                                              &pipe_config->dp_m_n,
8970                                              &pipe_config->dp_m2_n2);
8971 }
8972
8973 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8974                                         struct intel_crtc_state *pipe_config)
8975 {
8976         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8977                                      &pipe_config->fdi_m_n, NULL);
8978 }
8979
8980 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8981                                     struct intel_crtc_state *pipe_config)
8982 {
8983         struct drm_device *dev = crtc->base.dev;
8984         struct drm_i915_private *dev_priv = dev->dev_private;
8985         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8986         uint32_t ps_ctrl = 0;
8987         int id = -1;
8988         int i;
8989
8990         /* find scaler attached to this pipe */
8991         for (i = 0; i < crtc->num_scalers; i++) {
8992                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8993                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8994                         id = i;
8995                         pipe_config->pch_pfit.enabled = true;
8996                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8997                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8998                         break;
8999                 }
9000         }
9001
9002         scaler_state->scaler_id = id;
9003         if (id >= 0) {
9004                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9005         } else {
9006                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9007         }
9008 }
9009
9010 static void
9011 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9012                                  struct intel_initial_plane_config *plane_config)
9013 {
9014         struct drm_device *dev = crtc->base.dev;
9015         struct drm_i915_private *dev_priv = dev->dev_private;
9016         u32 val, base, offset, stride_mult, tiling;
9017         int pipe = crtc->pipe;
9018         int fourcc, pixel_format;
9019         unsigned int aligned_height;
9020         struct drm_framebuffer *fb;
9021         struct intel_framebuffer *intel_fb;
9022
9023         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9024         if (!intel_fb) {
9025                 DRM_DEBUG_KMS("failed to alloc fb\n");
9026                 return;
9027         }
9028
9029         fb = &intel_fb->base;
9030
9031         val = I915_READ(PLANE_CTL(pipe, 0));
9032         if (!(val & PLANE_CTL_ENABLE))
9033                 goto error;
9034
9035         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9036         fourcc = skl_format_to_fourcc(pixel_format,
9037                                       val & PLANE_CTL_ORDER_RGBX,
9038                                       val & PLANE_CTL_ALPHA_MASK);
9039         fb->pixel_format = fourcc;
9040         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9041
9042         tiling = val & PLANE_CTL_TILED_MASK;
9043         switch (tiling) {
9044         case PLANE_CTL_TILED_LINEAR:
9045                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9046                 break;
9047         case PLANE_CTL_TILED_X:
9048                 plane_config->tiling = I915_TILING_X;
9049                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9050                 break;
9051         case PLANE_CTL_TILED_Y:
9052                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9053                 break;
9054         case PLANE_CTL_TILED_YF:
9055                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9056                 break;
9057         default:
9058                 MISSING_CASE(tiling);
9059                 goto error;
9060         }
9061
9062         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9063         plane_config->base = base;
9064
9065         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9066
9067         val = I915_READ(PLANE_SIZE(pipe, 0));
9068         fb->height = ((val >> 16) & 0xfff) + 1;
9069         fb->width = ((val >> 0) & 0x1fff) + 1;
9070
9071         val = I915_READ(PLANE_STRIDE(pipe, 0));
9072         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9073                                                 fb->pixel_format);
9074         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9075
9076         aligned_height = intel_fb_align_height(dev, fb->height,
9077                                                fb->pixel_format,
9078                                                fb->modifier[0]);
9079
9080         plane_config->size = fb->pitches[0] * aligned_height;
9081
9082         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9083                       pipe_name(pipe), fb->width, fb->height,
9084                       fb->bits_per_pixel, base, fb->pitches[0],
9085                       plane_config->size);
9086
9087         plane_config->fb = intel_fb;
9088         return;
9089
9090 error:
9091         kfree(fb);
9092 }
9093
9094 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9095                                      struct intel_crtc_state *pipe_config)
9096 {
9097         struct drm_device *dev = crtc->base.dev;
9098         struct drm_i915_private *dev_priv = dev->dev_private;
9099         uint32_t tmp;
9100
9101         tmp = I915_READ(PF_CTL(crtc->pipe));
9102
9103         if (tmp & PF_ENABLE) {
9104                 pipe_config->pch_pfit.enabled = true;
9105                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9106                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9107
9108                 /* We currently do not free assignements of panel fitters on
9109                  * ivb/hsw (since we don't use the higher upscaling modes which
9110                  * differentiates them) so just WARN about this case for now. */
9111                 if (IS_GEN7(dev)) {
9112                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9113                                 PF_PIPE_SEL_IVB(crtc->pipe));
9114                 }
9115         }
9116 }
9117
9118 static void
9119 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9120                                   struct intel_initial_plane_config *plane_config)
9121 {
9122         struct drm_device *dev = crtc->base.dev;
9123         struct drm_i915_private *dev_priv = dev->dev_private;
9124         u32 val, base, offset;
9125         int pipe = crtc->pipe;
9126         int fourcc, pixel_format;
9127         unsigned int aligned_height;
9128         struct drm_framebuffer *fb;
9129         struct intel_framebuffer *intel_fb;
9130
9131         val = I915_READ(DSPCNTR(pipe));
9132         if (!(val & DISPLAY_PLANE_ENABLE))
9133                 return;
9134
9135         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9136         if (!intel_fb) {
9137                 DRM_DEBUG_KMS("failed to alloc fb\n");
9138                 return;
9139         }
9140
9141         fb = &intel_fb->base;
9142
9143         if (INTEL_INFO(dev)->gen >= 4) {
9144                 if (val & DISPPLANE_TILED) {
9145                         plane_config->tiling = I915_TILING_X;
9146                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9147                 }
9148         }
9149
9150         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9151         fourcc = i9xx_format_to_fourcc(pixel_format);
9152         fb->pixel_format = fourcc;
9153         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9154
9155         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9156         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9157                 offset = I915_READ(DSPOFFSET(pipe));
9158         } else {
9159                 if (plane_config->tiling)
9160                         offset = I915_READ(DSPTILEOFF(pipe));
9161                 else
9162                         offset = I915_READ(DSPLINOFF(pipe));
9163         }
9164         plane_config->base = base;
9165
9166         val = I915_READ(PIPESRC(pipe));
9167         fb->width = ((val >> 16) & 0xfff) + 1;
9168         fb->height = ((val >> 0) & 0xfff) + 1;
9169
9170         val = I915_READ(DSPSTRIDE(pipe));
9171         fb->pitches[0] = val & 0xffffffc0;
9172
9173         aligned_height = intel_fb_align_height(dev, fb->height,
9174                                                fb->pixel_format,
9175                                                fb->modifier[0]);
9176
9177         plane_config->size = fb->pitches[0] * aligned_height;
9178
9179         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9180                       pipe_name(pipe), fb->width, fb->height,
9181                       fb->bits_per_pixel, base, fb->pitches[0],
9182                       plane_config->size);
9183
9184         plane_config->fb = intel_fb;
9185 }
9186
9187 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9188                                      struct intel_crtc_state *pipe_config)
9189 {
9190         struct drm_device *dev = crtc->base.dev;
9191         struct drm_i915_private *dev_priv = dev->dev_private;
9192         uint32_t tmp;
9193
9194         if (!intel_display_power_is_enabled(dev_priv,
9195                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9196                 return false;
9197
9198         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9199         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9200
9201         tmp = I915_READ(PIPECONF(crtc->pipe));
9202         if (!(tmp & PIPECONF_ENABLE))
9203                 return false;
9204
9205         switch (tmp & PIPECONF_BPC_MASK) {
9206         case PIPECONF_6BPC:
9207                 pipe_config->pipe_bpp = 18;
9208                 break;
9209         case PIPECONF_8BPC:
9210                 pipe_config->pipe_bpp = 24;
9211                 break;
9212         case PIPECONF_10BPC:
9213                 pipe_config->pipe_bpp = 30;
9214                 break;
9215         case PIPECONF_12BPC:
9216                 pipe_config->pipe_bpp = 36;
9217                 break;
9218         default:
9219                 break;
9220         }
9221
9222         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9223                 pipe_config->limited_color_range = true;
9224
9225         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9226                 struct intel_shared_dpll *pll;
9227
9228                 pipe_config->has_pch_encoder = true;
9229
9230                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9231                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9232                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9233
9234                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9235
9236                 if (HAS_PCH_IBX(dev_priv->dev)) {
9237                         pipe_config->shared_dpll =
9238                                 (enum intel_dpll_id) crtc->pipe;
9239                 } else {
9240                         tmp = I915_READ(PCH_DPLL_SEL);
9241                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9242                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9243                         else
9244                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9245                 }
9246
9247                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9248
9249                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9250                                            &pipe_config->dpll_hw_state));
9251
9252                 tmp = pipe_config->dpll_hw_state.dpll;
9253                 pipe_config->pixel_multiplier =
9254                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9255                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9256
9257                 ironlake_pch_clock_get(crtc, pipe_config);
9258         } else {
9259                 pipe_config->pixel_multiplier = 1;
9260         }
9261
9262         intel_get_pipe_timings(crtc, pipe_config);
9263
9264         ironlake_get_pfit_config(crtc, pipe_config);
9265
9266         return true;
9267 }
9268
9269 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9270 {
9271         struct drm_device *dev = dev_priv->dev;
9272         struct intel_crtc *crtc;
9273
9274         for_each_intel_crtc(dev, crtc)
9275                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9276                      pipe_name(crtc->pipe));
9277
9278         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9279         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9280         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9281         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9282         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9283         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9284              "CPU PWM1 enabled\n");
9285         if (IS_HASWELL(dev))
9286                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9287                      "CPU PWM2 enabled\n");
9288         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9289              "PCH PWM1 enabled\n");
9290         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9291              "Utility pin enabled\n");
9292         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9293
9294         /*
9295          * In theory we can still leave IRQs enabled, as long as only the HPD
9296          * interrupts remain enabled. We used to check for that, but since it's
9297          * gen-specific and since we only disable LCPLL after we fully disable
9298          * the interrupts, the check below should be enough.
9299          */
9300         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9301 }
9302
9303 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9304 {
9305         struct drm_device *dev = dev_priv->dev;
9306
9307         if (IS_HASWELL(dev))
9308                 return I915_READ(D_COMP_HSW);
9309         else
9310                 return I915_READ(D_COMP_BDW);
9311 }
9312
9313 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9314 {
9315         struct drm_device *dev = dev_priv->dev;
9316
9317         if (IS_HASWELL(dev)) {
9318                 mutex_lock(&dev_priv->rps.hw_lock);
9319                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9320                                             val))
9321                         DRM_ERROR("Failed to write to D_COMP\n");
9322                 mutex_unlock(&dev_priv->rps.hw_lock);
9323         } else {
9324                 I915_WRITE(D_COMP_BDW, val);
9325                 POSTING_READ(D_COMP_BDW);
9326         }
9327 }
9328
9329 /*
9330  * This function implements pieces of two sequences from BSpec:
9331  * - Sequence for display software to disable LCPLL
9332  * - Sequence for display software to allow package C8+
9333  * The steps implemented here are just the steps that actually touch the LCPLL
9334  * register. Callers should take care of disabling all the display engine
9335  * functions, doing the mode unset, fixing interrupts, etc.
9336  */
9337 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9338                               bool switch_to_fclk, bool allow_power_down)
9339 {
9340         uint32_t val;
9341
9342         assert_can_disable_lcpll(dev_priv);
9343
9344         val = I915_READ(LCPLL_CTL);
9345
9346         if (switch_to_fclk) {
9347                 val |= LCPLL_CD_SOURCE_FCLK;
9348                 I915_WRITE(LCPLL_CTL, val);
9349
9350                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9351                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9352                         DRM_ERROR("Switching to FCLK failed\n");
9353
9354                 val = I915_READ(LCPLL_CTL);
9355         }
9356
9357         val |= LCPLL_PLL_DISABLE;
9358         I915_WRITE(LCPLL_CTL, val);
9359         POSTING_READ(LCPLL_CTL);
9360
9361         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9362                 DRM_ERROR("LCPLL still locked\n");
9363
9364         val = hsw_read_dcomp(dev_priv);
9365         val |= D_COMP_COMP_DISABLE;
9366         hsw_write_dcomp(dev_priv, val);
9367         ndelay(100);
9368
9369         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9370                      1))
9371                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9372
9373         if (allow_power_down) {
9374                 val = I915_READ(LCPLL_CTL);
9375                 val |= LCPLL_POWER_DOWN_ALLOW;
9376                 I915_WRITE(LCPLL_CTL, val);
9377                 POSTING_READ(LCPLL_CTL);
9378         }
9379 }
9380
9381 /*
9382  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9383  * source.
9384  */
9385 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9386 {
9387         uint32_t val;
9388
9389         val = I915_READ(LCPLL_CTL);
9390
9391         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9392                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9393                 return;
9394
9395         /*
9396          * Make sure we're not on PC8 state before disabling PC8, otherwise
9397          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9398          */
9399         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9400
9401         if (val & LCPLL_POWER_DOWN_ALLOW) {
9402                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9403                 I915_WRITE(LCPLL_CTL, val);
9404                 POSTING_READ(LCPLL_CTL);
9405         }
9406
9407         val = hsw_read_dcomp(dev_priv);
9408         val |= D_COMP_COMP_FORCE;
9409         val &= ~D_COMP_COMP_DISABLE;
9410         hsw_write_dcomp(dev_priv, val);
9411
9412         val = I915_READ(LCPLL_CTL);
9413         val &= ~LCPLL_PLL_DISABLE;
9414         I915_WRITE(LCPLL_CTL, val);
9415
9416         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9417                 DRM_ERROR("LCPLL not locked yet\n");
9418
9419         if (val & LCPLL_CD_SOURCE_FCLK) {
9420                 val = I915_READ(LCPLL_CTL);
9421                 val &= ~LCPLL_CD_SOURCE_FCLK;
9422                 I915_WRITE(LCPLL_CTL, val);
9423
9424                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9425                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9426                         DRM_ERROR("Switching back to LCPLL failed\n");
9427         }
9428
9429         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9430         intel_update_cdclk(dev_priv->dev);
9431 }
9432
9433 /*
9434  * Package states C8 and deeper are really deep PC states that can only be
9435  * reached when all the devices on the system allow it, so even if the graphics
9436  * device allows PC8+, it doesn't mean the system will actually get to these
9437  * states. Our driver only allows PC8+ when going into runtime PM.
9438  *
9439  * The requirements for PC8+ are that all the outputs are disabled, the power
9440  * well is disabled and most interrupts are disabled, and these are also
9441  * requirements for runtime PM. When these conditions are met, we manually do
9442  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9443  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9444  * hang the machine.
9445  *
9446  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9447  * the state of some registers, so when we come back from PC8+ we need to
9448  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9449  * need to take care of the registers kept by RC6. Notice that this happens even
9450  * if we don't put the device in PCI D3 state (which is what currently happens
9451  * because of the runtime PM support).
9452  *
9453  * For more, read "Display Sequences for Package C8" on the hardware
9454  * documentation.
9455  */
9456 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9457 {
9458         struct drm_device *dev = dev_priv->dev;
9459         uint32_t val;
9460
9461         DRM_DEBUG_KMS("Enabling package C8+\n");
9462
9463         if (HAS_PCH_LPT_LP(dev)) {
9464                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9465                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9466                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9467         }
9468
9469         lpt_disable_clkout_dp(dev);
9470         hsw_disable_lcpll(dev_priv, true, true);
9471 }
9472
9473 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9474 {
9475         struct drm_device *dev = dev_priv->dev;
9476         uint32_t val;
9477
9478         DRM_DEBUG_KMS("Disabling package C8+\n");
9479
9480         hsw_restore_lcpll(dev_priv);
9481         lpt_init_pch_refclk(dev);
9482
9483         if (HAS_PCH_LPT_LP(dev)) {
9484                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9485                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9486                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9487         }
9488
9489         intel_prepare_ddi(dev);
9490 }
9491
9492 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9493 {
9494         struct drm_device *dev = old_state->dev;
9495         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9496
9497         broxton_set_cdclk(dev, req_cdclk);
9498 }
9499
9500 /* compute the max rate for new configuration */
9501 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9502 {
9503         struct intel_crtc *intel_crtc;
9504         struct intel_crtc_state *crtc_state;
9505         int max_pixel_rate = 0;
9506
9507         for_each_intel_crtc(state->dev, intel_crtc) {
9508                 int pixel_rate;
9509
9510                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9511                 if (IS_ERR(crtc_state))
9512                         return PTR_ERR(crtc_state);
9513
9514                 if (!crtc_state->base.enable)
9515                         continue;
9516
9517                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9518
9519                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9520                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9521                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9522
9523                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9524         }
9525
9526         return max_pixel_rate;
9527 }
9528
9529 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9530 {
9531         struct drm_i915_private *dev_priv = dev->dev_private;
9532         uint32_t val, data;
9533         int ret;
9534
9535         if (WARN((I915_READ(LCPLL_CTL) &
9536                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9537                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9538                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9539                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9540                  "trying to change cdclk frequency with cdclk not enabled\n"))
9541                 return;
9542
9543         mutex_lock(&dev_priv->rps.hw_lock);
9544         ret = sandybridge_pcode_write(dev_priv,
9545                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9546         mutex_unlock(&dev_priv->rps.hw_lock);
9547         if (ret) {
9548                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9549                 return;
9550         }
9551
9552         val = I915_READ(LCPLL_CTL);
9553         val |= LCPLL_CD_SOURCE_FCLK;
9554         I915_WRITE(LCPLL_CTL, val);
9555
9556         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9557                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9558                 DRM_ERROR("Switching to FCLK failed\n");
9559
9560         val = I915_READ(LCPLL_CTL);
9561         val &= ~LCPLL_CLK_FREQ_MASK;
9562
9563         switch (cdclk) {
9564         case 450000:
9565                 val |= LCPLL_CLK_FREQ_450;
9566                 data = 0;
9567                 break;
9568         case 540000:
9569                 val |= LCPLL_CLK_FREQ_54O_BDW;
9570                 data = 1;
9571                 break;
9572         case 337500:
9573                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9574                 data = 2;
9575                 break;
9576         case 675000:
9577                 val |= LCPLL_CLK_FREQ_675_BDW;
9578                 data = 3;
9579                 break;
9580         default:
9581                 WARN(1, "invalid cdclk frequency\n");
9582                 return;
9583         }
9584
9585         I915_WRITE(LCPLL_CTL, val);
9586
9587         val = I915_READ(LCPLL_CTL);
9588         val &= ~LCPLL_CD_SOURCE_FCLK;
9589         I915_WRITE(LCPLL_CTL, val);
9590
9591         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9592                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9593                 DRM_ERROR("Switching back to LCPLL failed\n");
9594
9595         mutex_lock(&dev_priv->rps.hw_lock);
9596         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9597         mutex_unlock(&dev_priv->rps.hw_lock);
9598
9599         intel_update_cdclk(dev);
9600
9601         WARN(cdclk != dev_priv->cdclk_freq,
9602              "cdclk requested %d kHz but got %d kHz\n",
9603              cdclk, dev_priv->cdclk_freq);
9604 }
9605
9606 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9607 {
9608         struct drm_i915_private *dev_priv = to_i915(state->dev);
9609         int max_pixclk = ilk_max_pixel_rate(state);
9610         int cdclk;
9611
9612         /*
9613          * FIXME should also account for plane ratio
9614          * once 64bpp pixel formats are supported.
9615          */
9616         if (max_pixclk > 540000)
9617                 cdclk = 675000;
9618         else if (max_pixclk > 450000)
9619                 cdclk = 540000;
9620         else if (max_pixclk > 337500)
9621                 cdclk = 450000;
9622         else
9623                 cdclk = 337500;
9624
9625         /*
9626          * FIXME move the cdclk caclulation to
9627          * compute_config() so we can fail gracegully.
9628          */
9629         if (cdclk > dev_priv->max_cdclk_freq) {
9630                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9631                           cdclk, dev_priv->max_cdclk_freq);
9632                 cdclk = dev_priv->max_cdclk_freq;
9633         }
9634
9635         to_intel_atomic_state(state)->cdclk = cdclk;
9636
9637         return 0;
9638 }
9639
9640 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9641 {
9642         struct drm_device *dev = old_state->dev;
9643         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9644
9645         broadwell_set_cdclk(dev, req_cdclk);
9646 }
9647
9648 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9649                                       struct intel_crtc_state *crtc_state)
9650 {
9651         if (!intel_ddi_pll_select(crtc, crtc_state))
9652                 return -EINVAL;
9653
9654         crtc->lowfreq_avail = false;
9655
9656         return 0;
9657 }
9658
9659 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9660                                 enum port port,
9661                                 struct intel_crtc_state *pipe_config)
9662 {
9663         switch (port) {
9664         case PORT_A:
9665                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9666                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9667                 break;
9668         case PORT_B:
9669                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9670                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9671                 break;
9672         case PORT_C:
9673                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9674                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9675                 break;
9676         default:
9677                 DRM_ERROR("Incorrect port type\n");
9678         }
9679 }
9680
9681 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9682                                 enum port port,
9683                                 struct intel_crtc_state *pipe_config)
9684 {
9685         u32 temp, dpll_ctl1;
9686
9687         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9688         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9689
9690         switch (pipe_config->ddi_pll_sel) {
9691         case SKL_DPLL0:
9692                 /*
9693                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9694                  * of the shared DPLL framework and thus needs to be read out
9695                  * separately
9696                  */
9697                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9698                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9699                 break;
9700         case SKL_DPLL1:
9701                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9702                 break;
9703         case SKL_DPLL2:
9704                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9705                 break;
9706         case SKL_DPLL3:
9707                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9708                 break;
9709         }
9710 }
9711
9712 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9713                                 enum port port,
9714                                 struct intel_crtc_state *pipe_config)
9715 {
9716         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9717
9718         switch (pipe_config->ddi_pll_sel) {
9719         case PORT_CLK_SEL_WRPLL1:
9720                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9721                 break;
9722         case PORT_CLK_SEL_WRPLL2:
9723                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9724                 break;
9725         }
9726 }
9727
9728 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9729                                        struct intel_crtc_state *pipe_config)
9730 {
9731         struct drm_device *dev = crtc->base.dev;
9732         struct drm_i915_private *dev_priv = dev->dev_private;
9733         struct intel_shared_dpll *pll;
9734         enum port port;
9735         uint32_t tmp;
9736
9737         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9738
9739         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9740
9741         if (IS_SKYLAKE(dev))
9742                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9743         else if (IS_BROXTON(dev))
9744                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9745         else
9746                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9747
9748         if (pipe_config->shared_dpll >= 0) {
9749                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9750
9751                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9752                                            &pipe_config->dpll_hw_state));
9753         }
9754
9755         /*
9756          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9757          * DDI E. So just check whether this pipe is wired to DDI E and whether
9758          * the PCH transcoder is on.
9759          */
9760         if (INTEL_INFO(dev)->gen < 9 &&
9761             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9762                 pipe_config->has_pch_encoder = true;
9763
9764                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9765                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9766                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9767
9768                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9769         }
9770 }
9771
9772 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9773                                     struct intel_crtc_state *pipe_config)
9774 {
9775         struct drm_device *dev = crtc->base.dev;
9776         struct drm_i915_private *dev_priv = dev->dev_private;
9777         enum intel_display_power_domain pfit_domain;
9778         uint32_t tmp;
9779
9780         if (!intel_display_power_is_enabled(dev_priv,
9781                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9782                 return false;
9783
9784         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9785         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9786
9787         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9788         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9789                 enum pipe trans_edp_pipe;
9790                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9791                 default:
9792                         WARN(1, "unknown pipe linked to edp transcoder\n");
9793                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9794                 case TRANS_DDI_EDP_INPUT_A_ON:
9795                         trans_edp_pipe = PIPE_A;
9796                         break;
9797                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9798                         trans_edp_pipe = PIPE_B;
9799                         break;
9800                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9801                         trans_edp_pipe = PIPE_C;
9802                         break;
9803                 }
9804
9805                 if (trans_edp_pipe == crtc->pipe)
9806                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9807         }
9808
9809         if (!intel_display_power_is_enabled(dev_priv,
9810                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9811                 return false;
9812
9813         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9814         if (!(tmp & PIPECONF_ENABLE))
9815                 return false;
9816
9817         haswell_get_ddi_port_state(crtc, pipe_config);
9818
9819         intel_get_pipe_timings(crtc, pipe_config);
9820
9821         if (INTEL_INFO(dev)->gen >= 9) {
9822                 skl_init_scalers(dev, crtc, pipe_config);
9823         }
9824
9825         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9826
9827         if (INTEL_INFO(dev)->gen >= 9) {
9828                 pipe_config->scaler_state.scaler_id = -1;
9829                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9830         }
9831
9832         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9833                 if (INTEL_INFO(dev)->gen >= 9)
9834                         skylake_get_pfit_config(crtc, pipe_config);
9835                 else
9836                         ironlake_get_pfit_config(crtc, pipe_config);
9837         }
9838
9839         if (IS_HASWELL(dev))
9840                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9841                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9842
9843         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9844                 pipe_config->pixel_multiplier =
9845                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9846         } else {
9847                 pipe_config->pixel_multiplier = 1;
9848         }
9849
9850         return true;
9851 }
9852
9853 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9854 {
9855         struct drm_device *dev = crtc->dev;
9856         struct drm_i915_private *dev_priv = dev->dev_private;
9857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9858         uint32_t cntl = 0, size = 0;
9859
9860         if (base) {
9861                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9862                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9863                 unsigned int stride = roundup_pow_of_two(width) * 4;
9864
9865                 switch (stride) {
9866                 default:
9867                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9868                                   width, stride);
9869                         stride = 256;
9870                         /* fallthrough */
9871                 case 256:
9872                 case 512:
9873                 case 1024:
9874                 case 2048:
9875                         break;
9876                 }
9877
9878                 cntl |= CURSOR_ENABLE |
9879                         CURSOR_GAMMA_ENABLE |
9880                         CURSOR_FORMAT_ARGB |
9881                         CURSOR_STRIDE(stride);
9882
9883                 size = (height << 12) | width;
9884         }
9885
9886         if (intel_crtc->cursor_cntl != 0 &&
9887             (intel_crtc->cursor_base != base ||
9888              intel_crtc->cursor_size != size ||
9889              intel_crtc->cursor_cntl != cntl)) {
9890                 /* On these chipsets we can only modify the base/size/stride
9891                  * whilst the cursor is disabled.
9892                  */
9893                 I915_WRITE(CURCNTR(PIPE_A), 0);
9894                 POSTING_READ(CURCNTR(PIPE_A));
9895                 intel_crtc->cursor_cntl = 0;
9896         }
9897
9898         if (intel_crtc->cursor_base != base) {
9899                 I915_WRITE(CURBASE(PIPE_A), base);
9900                 intel_crtc->cursor_base = base;
9901         }
9902
9903         if (intel_crtc->cursor_size != size) {
9904                 I915_WRITE(CURSIZE, size);
9905                 intel_crtc->cursor_size = size;
9906         }
9907
9908         if (intel_crtc->cursor_cntl != cntl) {
9909                 I915_WRITE(CURCNTR(PIPE_A), cntl);
9910                 POSTING_READ(CURCNTR(PIPE_A));
9911                 intel_crtc->cursor_cntl = cntl;
9912         }
9913 }
9914
9915 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9916 {
9917         struct drm_device *dev = crtc->dev;
9918         struct drm_i915_private *dev_priv = dev->dev_private;
9919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9920         int pipe = intel_crtc->pipe;
9921         uint32_t cntl;
9922
9923         cntl = 0;
9924         if (base) {
9925                 cntl = MCURSOR_GAMMA_ENABLE;
9926                 switch (intel_crtc->base.cursor->state->crtc_w) {
9927                         case 64:
9928                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9929                                 break;
9930                         case 128:
9931                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9932                                 break;
9933                         case 256:
9934                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9935                                 break;
9936                         default:
9937                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9938                                 return;
9939                 }
9940                 cntl |= pipe << 28; /* Connect to correct pipe */
9941
9942                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9943                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9944         }
9945
9946         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9947                 cntl |= CURSOR_ROTATE_180;
9948
9949         if (intel_crtc->cursor_cntl != cntl) {
9950                 I915_WRITE(CURCNTR(pipe), cntl);
9951                 POSTING_READ(CURCNTR(pipe));
9952                 intel_crtc->cursor_cntl = cntl;
9953         }
9954
9955         /* and commit changes on next vblank */
9956         I915_WRITE(CURBASE(pipe), base);
9957         POSTING_READ(CURBASE(pipe));
9958
9959         intel_crtc->cursor_base = base;
9960 }
9961
9962 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9963 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9964                                      bool on)
9965 {
9966         struct drm_device *dev = crtc->dev;
9967         struct drm_i915_private *dev_priv = dev->dev_private;
9968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9969         int pipe = intel_crtc->pipe;
9970         struct drm_plane_state *cursor_state = crtc->cursor->state;
9971         int x = cursor_state->crtc_x;
9972         int y = cursor_state->crtc_y;
9973         u32 base = 0, pos = 0;
9974
9975         if (on)
9976                 base = intel_crtc->cursor_addr;
9977
9978         if (x >= intel_crtc->config->pipe_src_w)
9979                 base = 0;
9980
9981         if (y >= intel_crtc->config->pipe_src_h)
9982                 base = 0;
9983
9984         if (x < 0) {
9985                 if (x + cursor_state->crtc_w <= 0)
9986                         base = 0;
9987
9988                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9989                 x = -x;
9990         }
9991         pos |= x << CURSOR_X_SHIFT;
9992
9993         if (y < 0) {
9994                 if (y + cursor_state->crtc_h <= 0)
9995                         base = 0;
9996
9997                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9998                 y = -y;
9999         }
10000         pos |= y << CURSOR_Y_SHIFT;
10001
10002         if (base == 0 && intel_crtc->cursor_base == 0)
10003                 return;
10004
10005         I915_WRITE(CURPOS(pipe), pos);
10006
10007         /* ILK+ do this automagically */
10008         if (HAS_GMCH_DISPLAY(dev) &&
10009             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10010                 base += (cursor_state->crtc_h *
10011                          cursor_state->crtc_w - 1) * 4;
10012         }
10013
10014         if (IS_845G(dev) || IS_I865G(dev))
10015                 i845_update_cursor(crtc, base);
10016         else
10017                 i9xx_update_cursor(crtc, base);
10018 }
10019
10020 static bool cursor_size_ok(struct drm_device *dev,
10021                            uint32_t width, uint32_t height)
10022 {
10023         if (width == 0 || height == 0)
10024                 return false;
10025
10026         /*
10027          * 845g/865g are special in that they are only limited by
10028          * the width of their cursors, the height is arbitrary up to
10029          * the precision of the register. Everything else requires
10030          * square cursors, limited to a few power-of-two sizes.
10031          */
10032         if (IS_845G(dev) || IS_I865G(dev)) {
10033                 if ((width & 63) != 0)
10034                         return false;
10035
10036                 if (width > (IS_845G(dev) ? 64 : 512))
10037                         return false;
10038
10039                 if (height > 1023)
10040                         return false;
10041         } else {
10042                 switch (width | height) {
10043                 case 256:
10044                 case 128:
10045                         if (IS_GEN2(dev))
10046                                 return false;
10047                 case 64:
10048                         break;
10049                 default:
10050                         return false;
10051                 }
10052         }
10053
10054         return true;
10055 }
10056
10057 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10058                                  u16 *blue, uint32_t start, uint32_t size)
10059 {
10060         int end = (start + size > 256) ? 256 : start + size, i;
10061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10062
10063         for (i = start; i < end; i++) {
10064                 intel_crtc->lut_r[i] = red[i] >> 8;
10065                 intel_crtc->lut_g[i] = green[i] >> 8;
10066                 intel_crtc->lut_b[i] = blue[i] >> 8;
10067         }
10068
10069         intel_crtc_load_lut(crtc);
10070 }
10071
10072 /* VESA 640x480x72Hz mode to set on the pipe */
10073 static struct drm_display_mode load_detect_mode = {
10074         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10075                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10076 };
10077
10078 struct drm_framebuffer *
10079 __intel_framebuffer_create(struct drm_device *dev,
10080                            struct drm_mode_fb_cmd2 *mode_cmd,
10081                            struct drm_i915_gem_object *obj)
10082 {
10083         struct intel_framebuffer *intel_fb;
10084         int ret;
10085
10086         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10087         if (!intel_fb) {
10088                 drm_gem_object_unreference(&obj->base);
10089                 return ERR_PTR(-ENOMEM);
10090         }
10091
10092         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10093         if (ret)
10094                 goto err;
10095
10096         return &intel_fb->base;
10097 err:
10098         drm_gem_object_unreference(&obj->base);
10099         kfree(intel_fb);
10100
10101         return ERR_PTR(ret);
10102 }
10103
10104 static struct drm_framebuffer *
10105 intel_framebuffer_create(struct drm_device *dev,
10106                          struct drm_mode_fb_cmd2 *mode_cmd,
10107                          struct drm_i915_gem_object *obj)
10108 {
10109         struct drm_framebuffer *fb;
10110         int ret;
10111
10112         ret = i915_mutex_lock_interruptible(dev);
10113         if (ret)
10114                 return ERR_PTR(ret);
10115         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10116         mutex_unlock(&dev->struct_mutex);
10117
10118         return fb;
10119 }
10120
10121 static u32
10122 intel_framebuffer_pitch_for_width(int width, int bpp)
10123 {
10124         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10125         return ALIGN(pitch, 64);
10126 }
10127
10128 static u32
10129 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10130 {
10131         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10132         return PAGE_ALIGN(pitch * mode->vdisplay);
10133 }
10134
10135 static struct drm_framebuffer *
10136 intel_framebuffer_create_for_mode(struct drm_device *dev,
10137                                   struct drm_display_mode *mode,
10138                                   int depth, int bpp)
10139 {
10140         struct drm_i915_gem_object *obj;
10141         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10142
10143         obj = i915_gem_alloc_object(dev,
10144                                     intel_framebuffer_size_for_mode(mode, bpp));
10145         if (obj == NULL)
10146                 return ERR_PTR(-ENOMEM);
10147
10148         mode_cmd.width = mode->hdisplay;
10149         mode_cmd.height = mode->vdisplay;
10150         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10151                                                                 bpp);
10152         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10153
10154         return intel_framebuffer_create(dev, &mode_cmd, obj);
10155 }
10156
10157 static struct drm_framebuffer *
10158 mode_fits_in_fbdev(struct drm_device *dev,
10159                    struct drm_display_mode *mode)
10160 {
10161 #ifdef CONFIG_DRM_FBDEV_EMULATION
10162         struct drm_i915_private *dev_priv = dev->dev_private;
10163         struct drm_i915_gem_object *obj;
10164         struct drm_framebuffer *fb;
10165
10166         if (!dev_priv->fbdev)
10167                 return NULL;
10168
10169         if (!dev_priv->fbdev->fb)
10170                 return NULL;
10171
10172         obj = dev_priv->fbdev->fb->obj;
10173         BUG_ON(!obj);
10174
10175         fb = &dev_priv->fbdev->fb->base;
10176         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10177                                                                fb->bits_per_pixel))
10178                 return NULL;
10179
10180         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10181                 return NULL;
10182
10183         return fb;
10184 #else
10185         return NULL;
10186 #endif
10187 }
10188
10189 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10190                                            struct drm_crtc *crtc,
10191                                            struct drm_display_mode *mode,
10192                                            struct drm_framebuffer *fb,
10193                                            int x, int y)
10194 {
10195         struct drm_plane_state *plane_state;
10196         int hdisplay, vdisplay;
10197         int ret;
10198
10199         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10200         if (IS_ERR(plane_state))
10201                 return PTR_ERR(plane_state);
10202
10203         if (mode)
10204                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10205         else
10206                 hdisplay = vdisplay = 0;
10207
10208         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10209         if (ret)
10210                 return ret;
10211         drm_atomic_set_fb_for_plane(plane_state, fb);
10212         plane_state->crtc_x = 0;
10213         plane_state->crtc_y = 0;
10214         plane_state->crtc_w = hdisplay;
10215         plane_state->crtc_h = vdisplay;
10216         plane_state->src_x = x << 16;
10217         plane_state->src_y = y << 16;
10218         plane_state->src_w = hdisplay << 16;
10219         plane_state->src_h = vdisplay << 16;
10220
10221         return 0;
10222 }
10223
10224 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10225                                 struct drm_display_mode *mode,
10226                                 struct intel_load_detect_pipe *old,
10227                                 struct drm_modeset_acquire_ctx *ctx)
10228 {
10229         struct intel_crtc *intel_crtc;
10230         struct intel_encoder *intel_encoder =
10231                 intel_attached_encoder(connector);
10232         struct drm_crtc *possible_crtc;
10233         struct drm_encoder *encoder = &intel_encoder->base;
10234         struct drm_crtc *crtc = NULL;
10235         struct drm_device *dev = encoder->dev;
10236         struct drm_framebuffer *fb;
10237         struct drm_mode_config *config = &dev->mode_config;
10238         struct drm_atomic_state *state = NULL;
10239         struct drm_connector_state *connector_state;
10240         struct intel_crtc_state *crtc_state;
10241         int ret, i = -1;
10242
10243         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10244                       connector->base.id, connector->name,
10245                       encoder->base.id, encoder->name);
10246
10247 retry:
10248         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10249         if (ret)
10250                 goto fail;
10251
10252         /*
10253          * Algorithm gets a little messy:
10254          *
10255          *   - if the connector already has an assigned crtc, use it (but make
10256          *     sure it's on first)
10257          *
10258          *   - try to find the first unused crtc that can drive this connector,
10259          *     and use that if we find one
10260          */
10261
10262         /* See if we already have a CRTC for this connector */
10263         if (encoder->crtc) {
10264                 crtc = encoder->crtc;
10265
10266                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10267                 if (ret)
10268                         goto fail;
10269                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10270                 if (ret)
10271                         goto fail;
10272
10273                 old->dpms_mode = connector->dpms;
10274                 old->load_detect_temp = false;
10275
10276                 /* Make sure the crtc and connector are running */
10277                 if (connector->dpms != DRM_MODE_DPMS_ON)
10278                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10279
10280                 return true;
10281         }
10282
10283         /* Find an unused one (if possible) */
10284         for_each_crtc(dev, possible_crtc) {
10285                 i++;
10286                 if (!(encoder->possible_crtcs & (1 << i)))
10287                         continue;
10288                 if (possible_crtc->state->enable)
10289                         continue;
10290
10291                 crtc = possible_crtc;
10292                 break;
10293         }
10294
10295         /*
10296          * If we didn't find an unused CRTC, don't use any.
10297          */
10298         if (!crtc) {
10299                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10300                 goto fail;
10301         }
10302
10303         ret = drm_modeset_lock(&crtc->mutex, ctx);
10304         if (ret)
10305                 goto fail;
10306         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10307         if (ret)
10308                 goto fail;
10309
10310         intel_crtc = to_intel_crtc(crtc);
10311         old->dpms_mode = connector->dpms;
10312         old->load_detect_temp = true;
10313         old->release_fb = NULL;
10314
10315         state = drm_atomic_state_alloc(dev);
10316         if (!state)
10317                 return false;
10318
10319         state->acquire_ctx = ctx;
10320
10321         connector_state = drm_atomic_get_connector_state(state, connector);
10322         if (IS_ERR(connector_state)) {
10323                 ret = PTR_ERR(connector_state);
10324                 goto fail;
10325         }
10326
10327         connector_state->crtc = crtc;
10328         connector_state->best_encoder = &intel_encoder->base;
10329
10330         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10331         if (IS_ERR(crtc_state)) {
10332                 ret = PTR_ERR(crtc_state);
10333                 goto fail;
10334         }
10335
10336         crtc_state->base.active = crtc_state->base.enable = true;
10337
10338         if (!mode)
10339                 mode = &load_detect_mode;
10340
10341         /* We need a framebuffer large enough to accommodate all accesses
10342          * that the plane may generate whilst we perform load detection.
10343          * We can not rely on the fbcon either being present (we get called
10344          * during its initialisation to detect all boot displays, or it may
10345          * not even exist) or that it is large enough to satisfy the
10346          * requested mode.
10347          */
10348         fb = mode_fits_in_fbdev(dev, mode);
10349         if (fb == NULL) {
10350                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10351                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10352                 old->release_fb = fb;
10353         } else
10354                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10355         if (IS_ERR(fb)) {
10356                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10357                 goto fail;
10358         }
10359
10360         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10361         if (ret)
10362                 goto fail;
10363
10364         drm_mode_copy(&crtc_state->base.mode, mode);
10365
10366         if (drm_atomic_commit(state)) {
10367                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10368                 if (old->release_fb)
10369                         old->release_fb->funcs->destroy(old->release_fb);
10370                 goto fail;
10371         }
10372         crtc->primary->crtc = crtc;
10373
10374         /* let the connector get through one full cycle before testing */
10375         intel_wait_for_vblank(dev, intel_crtc->pipe);
10376         return true;
10377
10378 fail:
10379         drm_atomic_state_free(state);
10380         state = NULL;
10381
10382         if (ret == -EDEADLK) {
10383                 drm_modeset_backoff(ctx);
10384                 goto retry;
10385         }
10386
10387         return false;
10388 }
10389
10390 void intel_release_load_detect_pipe(struct drm_connector *connector,
10391                                     struct intel_load_detect_pipe *old,
10392                                     struct drm_modeset_acquire_ctx *ctx)
10393 {
10394         struct drm_device *dev = connector->dev;
10395         struct intel_encoder *intel_encoder =
10396                 intel_attached_encoder(connector);
10397         struct drm_encoder *encoder = &intel_encoder->base;
10398         struct drm_crtc *crtc = encoder->crtc;
10399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10400         struct drm_atomic_state *state;
10401         struct drm_connector_state *connector_state;
10402         struct intel_crtc_state *crtc_state;
10403         int ret;
10404
10405         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10406                       connector->base.id, connector->name,
10407                       encoder->base.id, encoder->name);
10408
10409         if (old->load_detect_temp) {
10410                 state = drm_atomic_state_alloc(dev);
10411                 if (!state)
10412                         goto fail;
10413
10414                 state->acquire_ctx = ctx;
10415
10416                 connector_state = drm_atomic_get_connector_state(state, connector);
10417                 if (IS_ERR(connector_state))
10418                         goto fail;
10419
10420                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10421                 if (IS_ERR(crtc_state))
10422                         goto fail;
10423
10424                 connector_state->best_encoder = NULL;
10425                 connector_state->crtc = NULL;
10426
10427                 crtc_state->base.enable = crtc_state->base.active = false;
10428
10429                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10430                                                       0, 0);
10431                 if (ret)
10432                         goto fail;
10433
10434                 ret = drm_atomic_commit(state);
10435                 if (ret)
10436                         goto fail;
10437
10438                 if (old->release_fb) {
10439                         drm_framebuffer_unregister_private(old->release_fb);
10440                         drm_framebuffer_unreference(old->release_fb);
10441                 }
10442
10443                 return;
10444         }
10445
10446         /* Switch crtc and encoder back off if necessary */
10447         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10448                 connector->funcs->dpms(connector, old->dpms_mode);
10449
10450         return;
10451 fail:
10452         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10453         drm_atomic_state_free(state);
10454 }
10455
10456 static int i9xx_pll_refclk(struct drm_device *dev,
10457                            const struct intel_crtc_state *pipe_config)
10458 {
10459         struct drm_i915_private *dev_priv = dev->dev_private;
10460         u32 dpll = pipe_config->dpll_hw_state.dpll;
10461
10462         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10463                 return dev_priv->vbt.lvds_ssc_freq;
10464         else if (HAS_PCH_SPLIT(dev))
10465                 return 120000;
10466         else if (!IS_GEN2(dev))
10467                 return 96000;
10468         else
10469                 return 48000;
10470 }
10471
10472 /* Returns the clock of the currently programmed mode of the given pipe. */
10473 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10474                                 struct intel_crtc_state *pipe_config)
10475 {
10476         struct drm_device *dev = crtc->base.dev;
10477         struct drm_i915_private *dev_priv = dev->dev_private;
10478         int pipe = pipe_config->cpu_transcoder;
10479         u32 dpll = pipe_config->dpll_hw_state.dpll;
10480         u32 fp;
10481         intel_clock_t clock;
10482         int port_clock;
10483         int refclk = i9xx_pll_refclk(dev, pipe_config);
10484
10485         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10486                 fp = pipe_config->dpll_hw_state.fp0;
10487         else
10488                 fp = pipe_config->dpll_hw_state.fp1;
10489
10490         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10491         if (IS_PINEVIEW(dev)) {
10492                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10493                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10494         } else {
10495                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10496                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10497         }
10498
10499         if (!IS_GEN2(dev)) {
10500                 if (IS_PINEVIEW(dev))
10501                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10502                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10503                 else
10504                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10505                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10506
10507                 switch (dpll & DPLL_MODE_MASK) {
10508                 case DPLLB_MODE_DAC_SERIAL:
10509                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10510                                 5 : 10;
10511                         break;
10512                 case DPLLB_MODE_LVDS:
10513                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10514                                 7 : 14;
10515                         break;
10516                 default:
10517                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10518                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10519                         return;
10520                 }
10521
10522                 if (IS_PINEVIEW(dev))
10523                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10524                 else
10525                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10526         } else {
10527                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10528                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10529
10530                 if (is_lvds) {
10531                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10532                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10533
10534                         if (lvds & LVDS_CLKB_POWER_UP)
10535                                 clock.p2 = 7;
10536                         else
10537                                 clock.p2 = 14;
10538                 } else {
10539                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10540                                 clock.p1 = 2;
10541                         else {
10542                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10543                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10544                         }
10545                         if (dpll & PLL_P2_DIVIDE_BY_4)
10546                                 clock.p2 = 4;
10547                         else
10548                                 clock.p2 = 2;
10549                 }
10550
10551                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10552         }
10553
10554         /*
10555          * This value includes pixel_multiplier. We will use
10556          * port_clock to compute adjusted_mode.crtc_clock in the
10557          * encoder's get_config() function.
10558          */
10559         pipe_config->port_clock = port_clock;
10560 }
10561
10562 int intel_dotclock_calculate(int link_freq,
10563                              const struct intel_link_m_n *m_n)
10564 {
10565         /*
10566          * The calculation for the data clock is:
10567          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10568          * But we want to avoid losing precison if possible, so:
10569          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10570          *
10571          * and the link clock is simpler:
10572          * link_clock = (m * link_clock) / n
10573          */
10574
10575         if (!m_n->link_n)
10576                 return 0;
10577
10578         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10579 }
10580
10581 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10582                                    struct intel_crtc_state *pipe_config)
10583 {
10584         struct drm_device *dev = crtc->base.dev;
10585
10586         /* read out port_clock from the DPLL */
10587         i9xx_crtc_clock_get(crtc, pipe_config);
10588
10589         /*
10590          * This value does not include pixel_multiplier.
10591          * We will check that port_clock and adjusted_mode.crtc_clock
10592          * agree once we know their relationship in the encoder's
10593          * get_config() function.
10594          */
10595         pipe_config->base.adjusted_mode.crtc_clock =
10596                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10597                                          &pipe_config->fdi_m_n);
10598 }
10599
10600 /** Returns the currently programmed mode of the given pipe. */
10601 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10602                                              struct drm_crtc *crtc)
10603 {
10604         struct drm_i915_private *dev_priv = dev->dev_private;
10605         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10606         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10607         struct drm_display_mode *mode;
10608         struct intel_crtc_state pipe_config;
10609         int htot = I915_READ(HTOTAL(cpu_transcoder));
10610         int hsync = I915_READ(HSYNC(cpu_transcoder));
10611         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10612         int vsync = I915_READ(VSYNC(cpu_transcoder));
10613         enum pipe pipe = intel_crtc->pipe;
10614
10615         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10616         if (!mode)
10617                 return NULL;
10618
10619         /*
10620          * Construct a pipe_config sufficient for getting the clock info
10621          * back out of crtc_clock_get.
10622          *
10623          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10624          * to use a real value here instead.
10625          */
10626         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10627         pipe_config.pixel_multiplier = 1;
10628         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10629         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10630         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10631         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10632
10633         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10634         mode->hdisplay = (htot & 0xffff) + 1;
10635         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10636         mode->hsync_start = (hsync & 0xffff) + 1;
10637         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10638         mode->vdisplay = (vtot & 0xffff) + 1;
10639         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10640         mode->vsync_start = (vsync & 0xffff) + 1;
10641         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10642
10643         drm_mode_set_name(mode);
10644
10645         return mode;
10646 }
10647
10648 void intel_mark_busy(struct drm_device *dev)
10649 {
10650         struct drm_i915_private *dev_priv = dev->dev_private;
10651
10652         if (dev_priv->mm.busy)
10653                 return;
10654
10655         intel_runtime_pm_get(dev_priv);
10656         i915_update_gfx_val(dev_priv);
10657         if (INTEL_INFO(dev)->gen >= 6)
10658                 gen6_rps_busy(dev_priv);
10659         dev_priv->mm.busy = true;
10660 }
10661
10662 void intel_mark_idle(struct drm_device *dev)
10663 {
10664         struct drm_i915_private *dev_priv = dev->dev_private;
10665
10666         if (!dev_priv->mm.busy)
10667                 return;
10668
10669         dev_priv->mm.busy = false;
10670
10671         if (INTEL_INFO(dev)->gen >= 6)
10672                 gen6_rps_idle(dev->dev_private);
10673
10674         intel_runtime_pm_put(dev_priv);
10675 }
10676
10677 static void intel_crtc_destroy(struct drm_crtc *crtc)
10678 {
10679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10680         struct drm_device *dev = crtc->dev;
10681         struct intel_unpin_work *work;
10682
10683         spin_lock_irq(&dev->event_lock);
10684         work = intel_crtc->unpin_work;
10685         intel_crtc->unpin_work = NULL;
10686         spin_unlock_irq(&dev->event_lock);
10687
10688         if (work) {
10689                 cancel_work_sync(&work->work);
10690                 kfree(work);
10691         }
10692
10693         drm_crtc_cleanup(crtc);
10694
10695         kfree(intel_crtc);
10696 }
10697
10698 static void intel_unpin_work_fn(struct work_struct *__work)
10699 {
10700         struct intel_unpin_work *work =
10701                 container_of(__work, struct intel_unpin_work, work);
10702         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10703         struct drm_device *dev = crtc->base.dev;
10704         struct drm_plane *primary = crtc->base.primary;
10705
10706         mutex_lock(&dev->struct_mutex);
10707         intel_unpin_fb_obj(work->old_fb, primary->state);
10708         drm_gem_object_unreference(&work->pending_flip_obj->base);
10709
10710         if (work->flip_queued_req)
10711                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10712         mutex_unlock(&dev->struct_mutex);
10713
10714         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10715         drm_framebuffer_unreference(work->old_fb);
10716
10717         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10718         atomic_dec(&crtc->unpin_work_count);
10719
10720         kfree(work);
10721 }
10722
10723 static void do_intel_finish_page_flip(struct drm_device *dev,
10724                                       struct drm_crtc *crtc)
10725 {
10726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10727         struct intel_unpin_work *work;
10728         unsigned long flags;
10729
10730         /* Ignore early vblank irqs */
10731         if (intel_crtc == NULL)
10732                 return;
10733
10734         /*
10735          * This is called both by irq handlers and the reset code (to complete
10736          * lost pageflips) so needs the full irqsave spinlocks.
10737          */
10738         spin_lock_irqsave(&dev->event_lock, flags);
10739         work = intel_crtc->unpin_work;
10740
10741         /* Ensure we don't miss a work->pending update ... */
10742         smp_rmb();
10743
10744         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10745                 spin_unlock_irqrestore(&dev->event_lock, flags);
10746                 return;
10747         }
10748
10749         page_flip_completed(intel_crtc);
10750
10751         spin_unlock_irqrestore(&dev->event_lock, flags);
10752 }
10753
10754 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10755 {
10756         struct drm_i915_private *dev_priv = dev->dev_private;
10757         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10758
10759         do_intel_finish_page_flip(dev, crtc);
10760 }
10761
10762 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10763 {
10764         struct drm_i915_private *dev_priv = dev->dev_private;
10765         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10766
10767         do_intel_finish_page_flip(dev, crtc);
10768 }
10769
10770 /* Is 'a' after or equal to 'b'? */
10771 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10772 {
10773         return !((a - b) & 0x80000000);
10774 }
10775
10776 static bool page_flip_finished(struct intel_crtc *crtc)
10777 {
10778         struct drm_device *dev = crtc->base.dev;
10779         struct drm_i915_private *dev_priv = dev->dev_private;
10780
10781         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10782             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10783                 return true;
10784
10785         /*
10786          * The relevant registers doen't exist on pre-ctg.
10787          * As the flip done interrupt doesn't trigger for mmio
10788          * flips on gmch platforms, a flip count check isn't
10789          * really needed there. But since ctg has the registers,
10790          * include it in the check anyway.
10791          */
10792         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10793                 return true;
10794
10795         /*
10796          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10797          * used the same base address. In that case the mmio flip might
10798          * have completed, but the CS hasn't even executed the flip yet.
10799          *
10800          * A flip count check isn't enough as the CS might have updated
10801          * the base address just after start of vblank, but before we
10802          * managed to process the interrupt. This means we'd complete the
10803          * CS flip too soon.
10804          *
10805          * Combining both checks should get us a good enough result. It may
10806          * still happen that the CS flip has been executed, but has not
10807          * yet actually completed. But in case the base address is the same
10808          * anyway, we don't really care.
10809          */
10810         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10811                 crtc->unpin_work->gtt_offset &&
10812                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10813                                     crtc->unpin_work->flip_count);
10814 }
10815
10816 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10817 {
10818         struct drm_i915_private *dev_priv = dev->dev_private;
10819         struct intel_crtc *intel_crtc =
10820                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10821         unsigned long flags;
10822
10823
10824         /*
10825          * This is called both by irq handlers and the reset code (to complete
10826          * lost pageflips) so needs the full irqsave spinlocks.
10827          *
10828          * NB: An MMIO update of the plane base pointer will also
10829          * generate a page-flip completion irq, i.e. every modeset
10830          * is also accompanied by a spurious intel_prepare_page_flip().
10831          */
10832         spin_lock_irqsave(&dev->event_lock, flags);
10833         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10834                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10835         spin_unlock_irqrestore(&dev->event_lock, flags);
10836 }
10837
10838 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10839 {
10840         /* Ensure that the work item is consistent when activating it ... */
10841         smp_wmb();
10842         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10843         /* and that it is marked active as soon as the irq could fire. */
10844         smp_wmb();
10845 }
10846
10847 static int intel_gen2_queue_flip(struct drm_device *dev,
10848                                  struct drm_crtc *crtc,
10849                                  struct drm_framebuffer *fb,
10850                                  struct drm_i915_gem_object *obj,
10851                                  struct drm_i915_gem_request *req,
10852                                  uint32_t flags)
10853 {
10854         struct intel_engine_cs *ring = req->ring;
10855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10856         u32 flip_mask;
10857         int ret;
10858
10859         ret = intel_ring_begin(req, 6);
10860         if (ret)
10861                 return ret;
10862
10863         /* Can't queue multiple flips, so wait for the previous
10864          * one to finish before executing the next.
10865          */
10866         if (intel_crtc->plane)
10867                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10868         else
10869                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10870         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10871         intel_ring_emit(ring, MI_NOOP);
10872         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10873                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10874         intel_ring_emit(ring, fb->pitches[0]);
10875         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10876         intel_ring_emit(ring, 0); /* aux display base address, unused */
10877
10878         intel_mark_page_flip_active(intel_crtc);
10879         return 0;
10880 }
10881
10882 static int intel_gen3_queue_flip(struct drm_device *dev,
10883                                  struct drm_crtc *crtc,
10884                                  struct drm_framebuffer *fb,
10885                                  struct drm_i915_gem_object *obj,
10886                                  struct drm_i915_gem_request *req,
10887                                  uint32_t flags)
10888 {
10889         struct intel_engine_cs *ring = req->ring;
10890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10891         u32 flip_mask;
10892         int ret;
10893
10894         ret = intel_ring_begin(req, 6);
10895         if (ret)
10896                 return ret;
10897
10898         if (intel_crtc->plane)
10899                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10900         else
10901                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10902         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10903         intel_ring_emit(ring, MI_NOOP);
10904         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10905                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10906         intel_ring_emit(ring, fb->pitches[0]);
10907         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10908         intel_ring_emit(ring, MI_NOOP);
10909
10910         intel_mark_page_flip_active(intel_crtc);
10911         return 0;
10912 }
10913
10914 static int intel_gen4_queue_flip(struct drm_device *dev,
10915                                  struct drm_crtc *crtc,
10916                                  struct drm_framebuffer *fb,
10917                                  struct drm_i915_gem_object *obj,
10918                                  struct drm_i915_gem_request *req,
10919                                  uint32_t flags)
10920 {
10921         struct intel_engine_cs *ring = req->ring;
10922         struct drm_i915_private *dev_priv = dev->dev_private;
10923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10924         uint32_t pf, pipesrc;
10925         int ret;
10926
10927         ret = intel_ring_begin(req, 4);
10928         if (ret)
10929                 return ret;
10930
10931         /* i965+ uses the linear or tiled offsets from the
10932          * Display Registers (which do not change across a page-flip)
10933          * so we need only reprogram the base address.
10934          */
10935         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10936                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10937         intel_ring_emit(ring, fb->pitches[0]);
10938         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10939                         obj->tiling_mode);
10940
10941         /* XXX Enabling the panel-fitter across page-flip is so far
10942          * untested on non-native modes, so ignore it for now.
10943          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10944          */
10945         pf = 0;
10946         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10947         intel_ring_emit(ring, pf | pipesrc);
10948
10949         intel_mark_page_flip_active(intel_crtc);
10950         return 0;
10951 }
10952
10953 static int intel_gen6_queue_flip(struct drm_device *dev,
10954                                  struct drm_crtc *crtc,
10955                                  struct drm_framebuffer *fb,
10956                                  struct drm_i915_gem_object *obj,
10957                                  struct drm_i915_gem_request *req,
10958                                  uint32_t flags)
10959 {
10960         struct intel_engine_cs *ring = req->ring;
10961         struct drm_i915_private *dev_priv = dev->dev_private;
10962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10963         uint32_t pf, pipesrc;
10964         int ret;
10965
10966         ret = intel_ring_begin(req, 4);
10967         if (ret)
10968                 return ret;
10969
10970         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10971                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10972         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10973         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10974
10975         /* Contrary to the suggestions in the documentation,
10976          * "Enable Panel Fitter" does not seem to be required when page
10977          * flipping with a non-native mode, and worse causes a normal
10978          * modeset to fail.
10979          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10980          */
10981         pf = 0;
10982         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10983         intel_ring_emit(ring, pf | pipesrc);
10984
10985         intel_mark_page_flip_active(intel_crtc);
10986         return 0;
10987 }
10988
10989 static int intel_gen7_queue_flip(struct drm_device *dev,
10990                                  struct drm_crtc *crtc,
10991                                  struct drm_framebuffer *fb,
10992                                  struct drm_i915_gem_object *obj,
10993                                  struct drm_i915_gem_request *req,
10994                                  uint32_t flags)
10995 {
10996         struct intel_engine_cs *ring = req->ring;
10997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10998         uint32_t plane_bit = 0;
10999         int len, ret;
11000
11001         switch (intel_crtc->plane) {
11002         case PLANE_A:
11003                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11004                 break;
11005         case PLANE_B:
11006                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11007                 break;
11008         case PLANE_C:
11009                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11010                 break;
11011         default:
11012                 WARN_ONCE(1, "unknown plane in flip command\n");
11013                 return -ENODEV;
11014         }
11015
11016         len = 4;
11017         if (ring->id == RCS) {
11018                 len += 6;
11019                 /*
11020                  * On Gen 8, SRM is now taking an extra dword to accommodate
11021                  * 48bits addresses, and we need a NOOP for the batch size to
11022                  * stay even.
11023                  */
11024                 if (IS_GEN8(dev))
11025                         len += 2;
11026         }
11027
11028         /*
11029          * BSpec MI_DISPLAY_FLIP for IVB:
11030          * "The full packet must be contained within the same cache line."
11031          *
11032          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11033          * cacheline, if we ever start emitting more commands before
11034          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11035          * then do the cacheline alignment, and finally emit the
11036          * MI_DISPLAY_FLIP.
11037          */
11038         ret = intel_ring_cacheline_align(req);
11039         if (ret)
11040                 return ret;
11041
11042         ret = intel_ring_begin(req, len);
11043         if (ret)
11044                 return ret;
11045
11046         /* Unmask the flip-done completion message. Note that the bspec says that
11047          * we should do this for both the BCS and RCS, and that we must not unmask
11048          * more than one flip event at any time (or ensure that one flip message
11049          * can be sent by waiting for flip-done prior to queueing new flips).
11050          * Experimentation says that BCS works despite DERRMR masking all
11051          * flip-done completion events and that unmasking all planes at once
11052          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11053          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11054          */
11055         if (ring->id == RCS) {
11056                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11057                 intel_ring_emit(ring, DERRMR);
11058                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11059                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11060                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11061                 if (IS_GEN8(dev))
11062                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11063                                               MI_SRM_LRM_GLOBAL_GTT);
11064                 else
11065                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11066                                               MI_SRM_LRM_GLOBAL_GTT);
11067                 intel_ring_emit(ring, DERRMR);
11068                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11069                 if (IS_GEN8(dev)) {
11070                         intel_ring_emit(ring, 0);
11071                         intel_ring_emit(ring, MI_NOOP);
11072                 }
11073         }
11074
11075         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11076         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11077         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11078         intel_ring_emit(ring, (MI_NOOP));
11079
11080         intel_mark_page_flip_active(intel_crtc);
11081         return 0;
11082 }
11083
11084 static bool use_mmio_flip(struct intel_engine_cs *ring,
11085                           struct drm_i915_gem_object *obj)
11086 {
11087         /*
11088          * This is not being used for older platforms, because
11089          * non-availability of flip done interrupt forces us to use
11090          * CS flips. Older platforms derive flip done using some clever
11091          * tricks involving the flip_pending status bits and vblank irqs.
11092          * So using MMIO flips there would disrupt this mechanism.
11093          */
11094
11095         if (ring == NULL)
11096                 return true;
11097
11098         if (INTEL_INFO(ring->dev)->gen < 5)
11099                 return false;
11100
11101         if (i915.use_mmio_flip < 0)
11102                 return false;
11103         else if (i915.use_mmio_flip > 0)
11104                 return true;
11105         else if (i915.enable_execlists)
11106                 return true;
11107         else
11108                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11109 }
11110
11111 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11112 {
11113         struct drm_device *dev = intel_crtc->base.dev;
11114         struct drm_i915_private *dev_priv = dev->dev_private;
11115         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11116         const enum pipe pipe = intel_crtc->pipe;
11117         u32 ctl, stride;
11118
11119         ctl = I915_READ(PLANE_CTL(pipe, 0));
11120         ctl &= ~PLANE_CTL_TILED_MASK;
11121         switch (fb->modifier[0]) {
11122         case DRM_FORMAT_MOD_NONE:
11123                 break;
11124         case I915_FORMAT_MOD_X_TILED:
11125                 ctl |= PLANE_CTL_TILED_X;
11126                 break;
11127         case I915_FORMAT_MOD_Y_TILED:
11128                 ctl |= PLANE_CTL_TILED_Y;
11129                 break;
11130         case I915_FORMAT_MOD_Yf_TILED:
11131                 ctl |= PLANE_CTL_TILED_YF;
11132                 break;
11133         default:
11134                 MISSING_CASE(fb->modifier[0]);
11135         }
11136
11137         /*
11138          * The stride is either expressed as a multiple of 64 bytes chunks for
11139          * linear buffers or in number of tiles for tiled buffers.
11140          */
11141         stride = fb->pitches[0] /
11142                  intel_fb_stride_alignment(dev, fb->modifier[0],
11143                                            fb->pixel_format);
11144
11145         /*
11146          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11147          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11148          */
11149         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11150         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11151
11152         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11153         POSTING_READ(PLANE_SURF(pipe, 0));
11154 }
11155
11156 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11157 {
11158         struct drm_device *dev = intel_crtc->base.dev;
11159         struct drm_i915_private *dev_priv = dev->dev_private;
11160         struct intel_framebuffer *intel_fb =
11161                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11162         struct drm_i915_gem_object *obj = intel_fb->obj;
11163         u32 dspcntr;
11164         u32 reg;
11165
11166         reg = DSPCNTR(intel_crtc->plane);
11167         dspcntr = I915_READ(reg);
11168
11169         if (obj->tiling_mode != I915_TILING_NONE)
11170                 dspcntr |= DISPPLANE_TILED;
11171         else
11172                 dspcntr &= ~DISPPLANE_TILED;
11173
11174         I915_WRITE(reg, dspcntr);
11175
11176         I915_WRITE(DSPSURF(intel_crtc->plane),
11177                    intel_crtc->unpin_work->gtt_offset);
11178         POSTING_READ(DSPSURF(intel_crtc->plane));
11179
11180 }
11181
11182 /*
11183  * XXX: This is the temporary way to update the plane registers until we get
11184  * around to using the usual plane update functions for MMIO flips
11185  */
11186 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11187 {
11188         struct drm_device *dev = intel_crtc->base.dev;
11189
11190         intel_mark_page_flip_active(intel_crtc);
11191
11192         intel_pipe_update_start(intel_crtc);
11193
11194         if (INTEL_INFO(dev)->gen >= 9)
11195                 skl_do_mmio_flip(intel_crtc);
11196         else
11197                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11198                 ilk_do_mmio_flip(intel_crtc);
11199
11200         intel_pipe_update_end(intel_crtc);
11201 }
11202
11203 static void intel_mmio_flip_work_func(struct work_struct *work)
11204 {
11205         struct intel_mmio_flip *mmio_flip =
11206                 container_of(work, struct intel_mmio_flip, work);
11207
11208         if (mmio_flip->req)
11209                 WARN_ON(__i915_wait_request(mmio_flip->req,
11210                                             mmio_flip->crtc->reset_counter,
11211                                             false, NULL,
11212                                             &mmio_flip->i915->rps.mmioflips));
11213
11214         intel_do_mmio_flip(mmio_flip->crtc);
11215
11216         i915_gem_request_unreference__unlocked(mmio_flip->req);
11217         kfree(mmio_flip);
11218 }
11219
11220 static int intel_queue_mmio_flip(struct drm_device *dev,
11221                                  struct drm_crtc *crtc,
11222                                  struct drm_framebuffer *fb,
11223                                  struct drm_i915_gem_object *obj,
11224                                  struct intel_engine_cs *ring,
11225                                  uint32_t flags)
11226 {
11227         struct intel_mmio_flip *mmio_flip;
11228
11229         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11230         if (mmio_flip == NULL)
11231                 return -ENOMEM;
11232
11233         mmio_flip->i915 = to_i915(dev);
11234         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11235         mmio_flip->crtc = to_intel_crtc(crtc);
11236
11237         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11238         schedule_work(&mmio_flip->work);
11239
11240         return 0;
11241 }
11242
11243 static int intel_default_queue_flip(struct drm_device *dev,
11244                                     struct drm_crtc *crtc,
11245                                     struct drm_framebuffer *fb,
11246                                     struct drm_i915_gem_object *obj,
11247                                     struct drm_i915_gem_request *req,
11248                                     uint32_t flags)
11249 {
11250         return -ENODEV;
11251 }
11252
11253 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11254                                          struct drm_crtc *crtc)
11255 {
11256         struct drm_i915_private *dev_priv = dev->dev_private;
11257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11258         struct intel_unpin_work *work = intel_crtc->unpin_work;
11259         u32 addr;
11260
11261         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11262                 return true;
11263
11264         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11265                 return false;
11266
11267         if (!work->enable_stall_check)
11268                 return false;
11269
11270         if (work->flip_ready_vblank == 0) {
11271                 if (work->flip_queued_req &&
11272                     !i915_gem_request_completed(work->flip_queued_req, true))
11273                         return false;
11274
11275                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11276         }
11277
11278         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11279                 return false;
11280
11281         /* Potential stall - if we see that the flip has happened,
11282          * assume a missed interrupt. */
11283         if (INTEL_INFO(dev)->gen >= 4)
11284                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11285         else
11286                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11287
11288         /* There is a potential issue here with a false positive after a flip
11289          * to the same address. We could address this by checking for a
11290          * non-incrementing frame counter.
11291          */
11292         return addr == work->gtt_offset;
11293 }
11294
11295 void intel_check_page_flip(struct drm_device *dev, int pipe)
11296 {
11297         struct drm_i915_private *dev_priv = dev->dev_private;
11298         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11300         struct intel_unpin_work *work;
11301
11302         WARN_ON(!in_interrupt());
11303
11304         if (crtc == NULL)
11305                 return;
11306
11307         spin_lock(&dev->event_lock);
11308         work = intel_crtc->unpin_work;
11309         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11310                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11311                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11312                 page_flip_completed(intel_crtc);
11313                 work = NULL;
11314         }
11315         if (work != NULL &&
11316             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11317                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11318         spin_unlock(&dev->event_lock);
11319 }
11320
11321 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11322                                 struct drm_framebuffer *fb,
11323                                 struct drm_pending_vblank_event *event,
11324                                 uint32_t page_flip_flags)
11325 {
11326         struct drm_device *dev = crtc->dev;
11327         struct drm_i915_private *dev_priv = dev->dev_private;
11328         struct drm_framebuffer *old_fb = crtc->primary->fb;
11329         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11331         struct drm_plane *primary = crtc->primary;
11332         enum pipe pipe = intel_crtc->pipe;
11333         struct intel_unpin_work *work;
11334         struct intel_engine_cs *ring;
11335         bool mmio_flip;
11336         struct drm_i915_gem_request *request = NULL;
11337         int ret;
11338
11339         /*
11340          * drm_mode_page_flip_ioctl() should already catch this, but double
11341          * check to be safe.  In the future we may enable pageflipping from
11342          * a disabled primary plane.
11343          */
11344         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11345                 return -EBUSY;
11346
11347         /* Can't change pixel format via MI display flips. */
11348         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11349                 return -EINVAL;
11350
11351         /*
11352          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11353          * Note that pitch changes could also affect these register.
11354          */
11355         if (INTEL_INFO(dev)->gen > 3 &&
11356             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11357              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11358                 return -EINVAL;
11359
11360         if (i915_terminally_wedged(&dev_priv->gpu_error))
11361                 goto out_hang;
11362
11363         work = kzalloc(sizeof(*work), GFP_KERNEL);
11364         if (work == NULL)
11365                 return -ENOMEM;
11366
11367         work->event = event;
11368         work->crtc = crtc;
11369         work->old_fb = old_fb;
11370         INIT_WORK(&work->work, intel_unpin_work_fn);
11371
11372         ret = drm_crtc_vblank_get(crtc);
11373         if (ret)
11374                 goto free_work;
11375
11376         /* We borrow the event spin lock for protecting unpin_work */
11377         spin_lock_irq(&dev->event_lock);
11378         if (intel_crtc->unpin_work) {
11379                 /* Before declaring the flip queue wedged, check if
11380                  * the hardware completed the operation behind our backs.
11381                  */
11382                 if (__intel_pageflip_stall_check(dev, crtc)) {
11383                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11384                         page_flip_completed(intel_crtc);
11385                 } else {
11386                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11387                         spin_unlock_irq(&dev->event_lock);
11388
11389                         drm_crtc_vblank_put(crtc);
11390                         kfree(work);
11391                         return -EBUSY;
11392                 }
11393         }
11394         intel_crtc->unpin_work = work;
11395         spin_unlock_irq(&dev->event_lock);
11396
11397         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11398                 flush_workqueue(dev_priv->wq);
11399
11400         /* Reference the objects for the scheduled work. */
11401         drm_framebuffer_reference(work->old_fb);
11402         drm_gem_object_reference(&obj->base);
11403
11404         crtc->primary->fb = fb;
11405         update_state_fb(crtc->primary);
11406
11407         work->pending_flip_obj = obj;
11408
11409         ret = i915_mutex_lock_interruptible(dev);
11410         if (ret)
11411                 goto cleanup;
11412
11413         atomic_inc(&intel_crtc->unpin_work_count);
11414         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11415
11416         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11417                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11418
11419         if (IS_VALLEYVIEW(dev)) {
11420                 ring = &dev_priv->ring[BCS];
11421                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11422                         /* vlv: DISPLAY_FLIP fails to change tiling */
11423                         ring = NULL;
11424         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11425                 ring = &dev_priv->ring[BCS];
11426         } else if (INTEL_INFO(dev)->gen >= 7) {
11427                 ring = i915_gem_request_get_ring(obj->last_write_req);
11428                 if (ring == NULL || ring->id != RCS)
11429                         ring = &dev_priv->ring[BCS];
11430         } else {
11431                 ring = &dev_priv->ring[RCS];
11432         }
11433
11434         mmio_flip = use_mmio_flip(ring, obj);
11435
11436         /* When using CS flips, we want to emit semaphores between rings.
11437          * However, when using mmio flips we will create a task to do the
11438          * synchronisation, so all we want here is to pin the framebuffer
11439          * into the display plane and skip any waits.
11440          */
11441         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11442                                          crtc->primary->state,
11443                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11444         if (ret)
11445                 goto cleanup_pending;
11446
11447         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11448                                                   obj, 0);
11449         work->gtt_offset += intel_crtc->dspaddr_offset;
11450
11451         if (mmio_flip) {
11452                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11453                                             page_flip_flags);
11454                 if (ret)
11455                         goto cleanup_unpin;
11456
11457                 i915_gem_request_assign(&work->flip_queued_req,
11458                                         obj->last_write_req);
11459         } else {
11460                 if (!request) {
11461                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11462                         if (ret)
11463                                 goto cleanup_unpin;
11464                 }
11465
11466                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11467                                                    page_flip_flags);
11468                 if (ret)
11469                         goto cleanup_unpin;
11470
11471                 i915_gem_request_assign(&work->flip_queued_req, request);
11472         }
11473
11474         if (request)
11475                 i915_add_request_no_flush(request);
11476
11477         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11478         work->enable_stall_check = true;
11479
11480         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11481                           to_intel_plane(primary)->frontbuffer_bit);
11482         mutex_unlock(&dev->struct_mutex);
11483
11484         intel_fbc_disable_crtc(intel_crtc);
11485         intel_frontbuffer_flip_prepare(dev,
11486                                        to_intel_plane(primary)->frontbuffer_bit);
11487
11488         trace_i915_flip_request(intel_crtc->plane, obj);
11489
11490         return 0;
11491
11492 cleanup_unpin:
11493         intel_unpin_fb_obj(fb, crtc->primary->state);
11494 cleanup_pending:
11495         if (request)
11496                 i915_gem_request_cancel(request);
11497         atomic_dec(&intel_crtc->unpin_work_count);
11498         mutex_unlock(&dev->struct_mutex);
11499 cleanup:
11500         crtc->primary->fb = old_fb;
11501         update_state_fb(crtc->primary);
11502
11503         drm_gem_object_unreference_unlocked(&obj->base);
11504         drm_framebuffer_unreference(work->old_fb);
11505
11506         spin_lock_irq(&dev->event_lock);
11507         intel_crtc->unpin_work = NULL;
11508         spin_unlock_irq(&dev->event_lock);
11509
11510         drm_crtc_vblank_put(crtc);
11511 free_work:
11512         kfree(work);
11513
11514         if (ret == -EIO) {
11515                 struct drm_atomic_state *state;
11516                 struct drm_plane_state *plane_state;
11517
11518 out_hang:
11519                 state = drm_atomic_state_alloc(dev);
11520                 if (!state)
11521                         return -ENOMEM;
11522                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11523
11524 retry:
11525                 plane_state = drm_atomic_get_plane_state(state, primary);
11526                 ret = PTR_ERR_OR_ZERO(plane_state);
11527                 if (!ret) {
11528                         drm_atomic_set_fb_for_plane(plane_state, fb);
11529
11530                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11531                         if (!ret)
11532                                 ret = drm_atomic_commit(state);
11533                 }
11534
11535                 if (ret == -EDEADLK) {
11536                         drm_modeset_backoff(state->acquire_ctx);
11537                         drm_atomic_state_clear(state);
11538                         goto retry;
11539                 }
11540
11541                 if (ret)
11542                         drm_atomic_state_free(state);
11543
11544                 if (ret == 0 && event) {
11545                         spin_lock_irq(&dev->event_lock);
11546                         drm_send_vblank_event(dev, pipe, event);
11547                         spin_unlock_irq(&dev->event_lock);
11548                 }
11549         }
11550         return ret;
11551 }
11552
11553
11554 /**
11555  * intel_wm_need_update - Check whether watermarks need updating
11556  * @plane: drm plane
11557  * @state: new plane state
11558  *
11559  * Check current plane state versus the new one to determine whether
11560  * watermarks need to be recalculated.
11561  *
11562  * Returns true or false.
11563  */
11564 static bool intel_wm_need_update(struct drm_plane *plane,
11565                                  struct drm_plane_state *state)
11566 {
11567         /* Update watermarks on tiling changes. */
11568         if (!plane->state->fb || !state->fb ||
11569             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11570             plane->state->rotation != state->rotation)
11571                 return true;
11572
11573         if (plane->state->crtc_w != state->crtc_w)
11574                 return true;
11575
11576         return false;
11577 }
11578
11579 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11580                                     struct drm_plane_state *plane_state)
11581 {
11582         struct drm_crtc *crtc = crtc_state->crtc;
11583         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11584         struct drm_plane *plane = plane_state->plane;
11585         struct drm_device *dev = crtc->dev;
11586         struct drm_i915_private *dev_priv = dev->dev_private;
11587         struct intel_plane_state *old_plane_state =
11588                 to_intel_plane_state(plane->state);
11589         int idx = intel_crtc->base.base.id, ret;
11590         int i = drm_plane_index(plane);
11591         bool mode_changed = needs_modeset(crtc_state);
11592         bool was_crtc_enabled = crtc->state->active;
11593         bool is_crtc_enabled = crtc_state->active;
11594
11595         bool turn_off, turn_on, visible, was_visible;
11596         struct drm_framebuffer *fb = plane_state->fb;
11597
11598         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11599             plane->type != DRM_PLANE_TYPE_CURSOR) {
11600                 ret = skl_update_scaler_plane(
11601                         to_intel_crtc_state(crtc_state),
11602                         to_intel_plane_state(plane_state));
11603                 if (ret)
11604                         return ret;
11605         }
11606
11607         /*
11608          * Disabling a plane is always okay; we just need to update
11609          * fb tracking in a special way since cleanup_fb() won't
11610          * get called by the plane helpers.
11611          */
11612         if (old_plane_state->base.fb && !fb)
11613                 intel_crtc->atomic.disabled_planes |= 1 << i;
11614
11615         was_visible = old_plane_state->visible;
11616         visible = to_intel_plane_state(plane_state)->visible;
11617
11618         if (!was_crtc_enabled && WARN_ON(was_visible))
11619                 was_visible = false;
11620
11621         if (!is_crtc_enabled && WARN_ON(visible))
11622                 visible = false;
11623
11624         if (!was_visible && !visible)
11625                 return 0;
11626
11627         turn_off = was_visible && (!visible || mode_changed);
11628         turn_on = visible && (!was_visible || mode_changed);
11629
11630         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11631                          plane->base.id, fb ? fb->base.id : -1);
11632
11633         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11634                          plane->base.id, was_visible, visible,
11635                          turn_off, turn_on, mode_changed);
11636
11637         if (turn_on) {
11638                 intel_crtc->atomic.update_wm_pre = true;
11639                 /* must disable cxsr around plane enable/disable */
11640                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11641                         intel_crtc->atomic.disable_cxsr = true;
11642                         /* to potentially re-enable cxsr */
11643                         intel_crtc->atomic.wait_vblank = true;
11644                         intel_crtc->atomic.update_wm_post = true;
11645                 }
11646         } else if (turn_off) {
11647                 intel_crtc->atomic.update_wm_post = true;
11648                 /* must disable cxsr around plane enable/disable */
11649                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11650                         if (is_crtc_enabled)
11651                                 intel_crtc->atomic.wait_vblank = true;
11652                         intel_crtc->atomic.disable_cxsr = true;
11653                 }
11654         } else if (intel_wm_need_update(plane, plane_state)) {
11655                 intel_crtc->atomic.update_wm_pre = true;
11656         }
11657
11658         if (visible || was_visible)
11659                 intel_crtc->atomic.fb_bits |=
11660                         to_intel_plane(plane)->frontbuffer_bit;
11661
11662         switch (plane->type) {
11663         case DRM_PLANE_TYPE_PRIMARY:
11664                 intel_crtc->atomic.wait_for_flips = true;
11665                 intel_crtc->atomic.pre_disable_primary = turn_off;
11666                 intel_crtc->atomic.post_enable_primary = turn_on;
11667
11668                 if (turn_off) {
11669                         /*
11670                          * FIXME: Actually if we will still have any other
11671                          * plane enabled on the pipe we could let IPS enabled
11672                          * still, but for now lets consider that when we make
11673                          * primary invisible by setting DSPCNTR to 0 on
11674                          * update_primary_plane function IPS needs to be
11675                          * disable.
11676                          */
11677                         intel_crtc->atomic.disable_ips = true;
11678
11679                         intel_crtc->atomic.disable_fbc = true;
11680                 }
11681
11682                 /*
11683                  * FBC does not work on some platforms for rotated
11684                  * planes, so disable it when rotation is not 0 and
11685                  * update it when rotation is set back to 0.
11686                  *
11687                  * FIXME: This is redundant with the fbc update done in
11688                  * the primary plane enable function except that that
11689                  * one is done too late. We eventually need to unify
11690                  * this.
11691                  */
11692
11693                 if (visible &&
11694                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11695                     dev_priv->fbc.crtc == intel_crtc &&
11696                     plane_state->rotation != BIT(DRM_ROTATE_0))
11697                         intel_crtc->atomic.disable_fbc = true;
11698
11699                 /*
11700                  * BDW signals flip done immediately if the plane
11701                  * is disabled, even if the plane enable is already
11702                  * armed to occur at the next vblank :(
11703                  */
11704                 if (turn_on && IS_BROADWELL(dev))
11705                         intel_crtc->atomic.wait_vblank = true;
11706
11707                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11708                 break;
11709         case DRM_PLANE_TYPE_CURSOR:
11710                 break;
11711         case DRM_PLANE_TYPE_OVERLAY:
11712                 if (turn_off && !mode_changed) {
11713                         intel_crtc->atomic.wait_vblank = true;
11714                         intel_crtc->atomic.update_sprite_watermarks |=
11715                                 1 << i;
11716                 }
11717         }
11718         return 0;
11719 }
11720
11721 static bool encoders_cloneable(const struct intel_encoder *a,
11722                                const struct intel_encoder *b)
11723 {
11724         /* masks could be asymmetric, so check both ways */
11725         return a == b || (a->cloneable & (1 << b->type) &&
11726                           b->cloneable & (1 << a->type));
11727 }
11728
11729 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11730                                          struct intel_crtc *crtc,
11731                                          struct intel_encoder *encoder)
11732 {
11733         struct intel_encoder *source_encoder;
11734         struct drm_connector *connector;
11735         struct drm_connector_state *connector_state;
11736         int i;
11737
11738         for_each_connector_in_state(state, connector, connector_state, i) {
11739                 if (connector_state->crtc != &crtc->base)
11740                         continue;
11741
11742                 source_encoder =
11743                         to_intel_encoder(connector_state->best_encoder);
11744                 if (!encoders_cloneable(encoder, source_encoder))
11745                         return false;
11746         }
11747
11748         return true;
11749 }
11750
11751 static bool check_encoder_cloning(struct drm_atomic_state *state,
11752                                   struct intel_crtc *crtc)
11753 {
11754         struct intel_encoder *encoder;
11755         struct drm_connector *connector;
11756         struct drm_connector_state *connector_state;
11757         int i;
11758
11759         for_each_connector_in_state(state, connector, connector_state, i) {
11760                 if (connector_state->crtc != &crtc->base)
11761                         continue;
11762
11763                 encoder = to_intel_encoder(connector_state->best_encoder);
11764                 if (!check_single_encoder_cloning(state, crtc, encoder))
11765                         return false;
11766         }
11767
11768         return true;
11769 }
11770
11771 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11772                                    struct drm_crtc_state *crtc_state)
11773 {
11774         struct drm_device *dev = crtc->dev;
11775         struct drm_i915_private *dev_priv = dev->dev_private;
11776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11777         struct intel_crtc_state *pipe_config =
11778                 to_intel_crtc_state(crtc_state);
11779         struct drm_atomic_state *state = crtc_state->state;
11780         int ret;
11781         bool mode_changed = needs_modeset(crtc_state);
11782
11783         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11784                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11785                 return -EINVAL;
11786         }
11787
11788         if (mode_changed && !crtc_state->active)
11789                 intel_crtc->atomic.update_wm_post = true;
11790
11791         if (mode_changed && crtc_state->enable &&
11792             dev_priv->display.crtc_compute_clock &&
11793             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11794                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11795                                                            pipe_config);
11796                 if (ret)
11797                         return ret;
11798         }
11799
11800         ret = 0;
11801         if (INTEL_INFO(dev)->gen >= 9) {
11802                 if (mode_changed)
11803                         ret = skl_update_scaler_crtc(pipe_config);
11804
11805                 if (!ret)
11806                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11807                                                          pipe_config);
11808         }
11809
11810         return ret;
11811 }
11812
11813 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11814         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11815         .load_lut = intel_crtc_load_lut,
11816         .atomic_begin = intel_begin_crtc_commit,
11817         .atomic_flush = intel_finish_crtc_commit,
11818         .atomic_check = intel_crtc_atomic_check,
11819 };
11820
11821 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11822 {
11823         struct intel_connector *connector;
11824
11825         for_each_intel_connector(dev, connector) {
11826                 if (connector->base.encoder) {
11827                         connector->base.state->best_encoder =
11828                                 connector->base.encoder;
11829                         connector->base.state->crtc =
11830                                 connector->base.encoder->crtc;
11831                 } else {
11832                         connector->base.state->best_encoder = NULL;
11833                         connector->base.state->crtc = NULL;
11834                 }
11835         }
11836 }
11837
11838 static void
11839 connected_sink_compute_bpp(struct intel_connector *connector,
11840                            struct intel_crtc_state *pipe_config)
11841 {
11842         int bpp = pipe_config->pipe_bpp;
11843
11844         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11845                 connector->base.base.id,
11846                 connector->base.name);
11847
11848         /* Don't use an invalid EDID bpc value */
11849         if (connector->base.display_info.bpc &&
11850             connector->base.display_info.bpc * 3 < bpp) {
11851                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11852                               bpp, connector->base.display_info.bpc*3);
11853                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11854         }
11855
11856         /* Clamp bpp to 8 on screens without EDID 1.4 */
11857         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11858                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11859                               bpp);
11860                 pipe_config->pipe_bpp = 24;
11861         }
11862 }
11863
11864 static int
11865 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11866                           struct intel_crtc_state *pipe_config)
11867 {
11868         struct drm_device *dev = crtc->base.dev;
11869         struct drm_atomic_state *state;
11870         struct drm_connector *connector;
11871         struct drm_connector_state *connector_state;
11872         int bpp, i;
11873
11874         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11875                 bpp = 10*3;
11876         else if (INTEL_INFO(dev)->gen >= 5)
11877                 bpp = 12*3;
11878         else
11879                 bpp = 8*3;
11880
11881
11882         pipe_config->pipe_bpp = bpp;
11883
11884         state = pipe_config->base.state;
11885
11886         /* Clamp display bpp to EDID value */
11887         for_each_connector_in_state(state, connector, connector_state, i) {
11888                 if (connector_state->crtc != &crtc->base)
11889                         continue;
11890
11891                 connected_sink_compute_bpp(to_intel_connector(connector),
11892                                            pipe_config);
11893         }
11894
11895         return bpp;
11896 }
11897
11898 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11899 {
11900         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11901                         "type: 0x%x flags: 0x%x\n",
11902                 mode->crtc_clock,
11903                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11904                 mode->crtc_hsync_end, mode->crtc_htotal,
11905                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11906                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11907 }
11908
11909 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11910                                    struct intel_crtc_state *pipe_config,
11911                                    const char *context)
11912 {
11913         struct drm_device *dev = crtc->base.dev;
11914         struct drm_plane *plane;
11915         struct intel_plane *intel_plane;
11916         struct intel_plane_state *state;
11917         struct drm_framebuffer *fb;
11918
11919         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11920                       context, pipe_config, pipe_name(crtc->pipe));
11921
11922         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11923         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11924                       pipe_config->pipe_bpp, pipe_config->dither);
11925         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11926                       pipe_config->has_pch_encoder,
11927                       pipe_config->fdi_lanes,
11928                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11929                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11930                       pipe_config->fdi_m_n.tu);
11931         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11932                       pipe_config->has_dp_encoder,
11933                       pipe_config->lane_count,
11934                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11935                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11936                       pipe_config->dp_m_n.tu);
11937
11938         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11939                       pipe_config->has_dp_encoder,
11940                       pipe_config->lane_count,
11941                       pipe_config->dp_m2_n2.gmch_m,
11942                       pipe_config->dp_m2_n2.gmch_n,
11943                       pipe_config->dp_m2_n2.link_m,
11944                       pipe_config->dp_m2_n2.link_n,
11945                       pipe_config->dp_m2_n2.tu);
11946
11947         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11948                       pipe_config->has_audio,
11949                       pipe_config->has_infoframe);
11950
11951         DRM_DEBUG_KMS("requested mode:\n");
11952         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11953         DRM_DEBUG_KMS("adjusted mode:\n");
11954         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11955         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11956         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11957         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11958                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11959         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11960                       crtc->num_scalers,
11961                       pipe_config->scaler_state.scaler_users,
11962                       pipe_config->scaler_state.scaler_id);
11963         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11964                       pipe_config->gmch_pfit.control,
11965                       pipe_config->gmch_pfit.pgm_ratios,
11966                       pipe_config->gmch_pfit.lvds_border_bits);
11967         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11968                       pipe_config->pch_pfit.pos,
11969                       pipe_config->pch_pfit.size,
11970                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11971         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11972         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11973
11974         if (IS_BROXTON(dev)) {
11975                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11976                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11977                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11978                               pipe_config->ddi_pll_sel,
11979                               pipe_config->dpll_hw_state.ebb0,
11980                               pipe_config->dpll_hw_state.ebb4,
11981                               pipe_config->dpll_hw_state.pll0,
11982                               pipe_config->dpll_hw_state.pll1,
11983                               pipe_config->dpll_hw_state.pll2,
11984                               pipe_config->dpll_hw_state.pll3,
11985                               pipe_config->dpll_hw_state.pll6,
11986                               pipe_config->dpll_hw_state.pll8,
11987                               pipe_config->dpll_hw_state.pll9,
11988                               pipe_config->dpll_hw_state.pll10,
11989                               pipe_config->dpll_hw_state.pcsdw12);
11990         } else if (IS_SKYLAKE(dev)) {
11991                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11992                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11993                               pipe_config->ddi_pll_sel,
11994                               pipe_config->dpll_hw_state.ctrl1,
11995                               pipe_config->dpll_hw_state.cfgcr1,
11996                               pipe_config->dpll_hw_state.cfgcr2);
11997         } else if (HAS_DDI(dev)) {
11998                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11999                               pipe_config->ddi_pll_sel,
12000                               pipe_config->dpll_hw_state.wrpll);
12001         } else {
12002                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12003                               "fp0: 0x%x, fp1: 0x%x\n",
12004                               pipe_config->dpll_hw_state.dpll,
12005                               pipe_config->dpll_hw_state.dpll_md,
12006                               pipe_config->dpll_hw_state.fp0,
12007                               pipe_config->dpll_hw_state.fp1);
12008         }
12009
12010         DRM_DEBUG_KMS("planes on this crtc\n");
12011         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12012                 intel_plane = to_intel_plane(plane);
12013                 if (intel_plane->pipe != crtc->pipe)
12014                         continue;
12015
12016                 state = to_intel_plane_state(plane->state);
12017                 fb = state->base.fb;
12018                 if (!fb) {
12019                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12020                                 "disabled, scaler_id = %d\n",
12021                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12022                                 plane->base.id, intel_plane->pipe,
12023                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12024                                 drm_plane_index(plane), state->scaler_id);
12025                         continue;
12026                 }
12027
12028                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12029                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12030                         plane->base.id, intel_plane->pipe,
12031                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12032                         drm_plane_index(plane));
12033                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12034                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12035                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12036                         state->scaler_id,
12037                         state->src.x1 >> 16, state->src.y1 >> 16,
12038                         drm_rect_width(&state->src) >> 16,
12039                         drm_rect_height(&state->src) >> 16,
12040                         state->dst.x1, state->dst.y1,
12041                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12042         }
12043 }
12044
12045 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12046 {
12047         struct drm_device *dev = state->dev;
12048         struct intel_encoder *encoder;
12049         struct drm_connector *connector;
12050         struct drm_connector_state *connector_state;
12051         unsigned int used_ports = 0;
12052         int i;
12053
12054         /*
12055          * Walk the connector list instead of the encoder
12056          * list to detect the problem on ddi platforms
12057          * where there's just one encoder per digital port.
12058          */
12059         for_each_connector_in_state(state, connector, connector_state, i) {
12060                 if (!connector_state->best_encoder)
12061                         continue;
12062
12063                 encoder = to_intel_encoder(connector_state->best_encoder);
12064
12065                 WARN_ON(!connector_state->crtc);
12066
12067                 switch (encoder->type) {
12068                         unsigned int port_mask;
12069                 case INTEL_OUTPUT_UNKNOWN:
12070                         if (WARN_ON(!HAS_DDI(dev)))
12071                                 break;
12072                 case INTEL_OUTPUT_DISPLAYPORT:
12073                 case INTEL_OUTPUT_HDMI:
12074                 case INTEL_OUTPUT_EDP:
12075                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12076
12077                         /* the same port mustn't appear more than once */
12078                         if (used_ports & port_mask)
12079                                 return false;
12080
12081                         used_ports |= port_mask;
12082                 default:
12083                         break;
12084                 }
12085         }
12086
12087         return true;
12088 }
12089
12090 static void
12091 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12092 {
12093         struct drm_crtc_state tmp_state;
12094         struct intel_crtc_scaler_state scaler_state;
12095         struct intel_dpll_hw_state dpll_hw_state;
12096         enum intel_dpll_id shared_dpll;
12097         uint32_t ddi_pll_sel;
12098         bool force_thru;
12099
12100         /* FIXME: before the switch to atomic started, a new pipe_config was
12101          * kzalloc'd. Code that depends on any field being zero should be
12102          * fixed, so that the crtc_state can be safely duplicated. For now,
12103          * only fields that are know to not cause problems are preserved. */
12104
12105         tmp_state = crtc_state->base;
12106         scaler_state = crtc_state->scaler_state;
12107         shared_dpll = crtc_state->shared_dpll;
12108         dpll_hw_state = crtc_state->dpll_hw_state;
12109         ddi_pll_sel = crtc_state->ddi_pll_sel;
12110         force_thru = crtc_state->pch_pfit.force_thru;
12111
12112         memset(crtc_state, 0, sizeof *crtc_state);
12113
12114         crtc_state->base = tmp_state;
12115         crtc_state->scaler_state = scaler_state;
12116         crtc_state->shared_dpll = shared_dpll;
12117         crtc_state->dpll_hw_state = dpll_hw_state;
12118         crtc_state->ddi_pll_sel = ddi_pll_sel;
12119         crtc_state->pch_pfit.force_thru = force_thru;
12120 }
12121
12122 static int
12123 intel_modeset_pipe_config(struct drm_crtc *crtc,
12124                           struct intel_crtc_state *pipe_config)
12125 {
12126         struct drm_atomic_state *state = pipe_config->base.state;
12127         struct intel_encoder *encoder;
12128         struct drm_connector *connector;
12129         struct drm_connector_state *connector_state;
12130         int base_bpp, ret = -EINVAL;
12131         int i;
12132         bool retry = true;
12133
12134         clear_intel_crtc_state(pipe_config);
12135
12136         pipe_config->cpu_transcoder =
12137                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12138
12139         /*
12140          * Sanitize sync polarity flags based on requested ones. If neither
12141          * positive or negative polarity is requested, treat this as meaning
12142          * negative polarity.
12143          */
12144         if (!(pipe_config->base.adjusted_mode.flags &
12145               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12146                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12147
12148         if (!(pipe_config->base.adjusted_mode.flags &
12149               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12150                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12151
12152         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12153                                              pipe_config);
12154         if (base_bpp < 0)
12155                 goto fail;
12156
12157         /*
12158          * Determine the real pipe dimensions. Note that stereo modes can
12159          * increase the actual pipe size due to the frame doubling and
12160          * insertion of additional space for blanks between the frame. This
12161          * is stored in the crtc timings. We use the requested mode to do this
12162          * computation to clearly distinguish it from the adjusted mode, which
12163          * can be changed by the connectors in the below retry loop.
12164          */
12165         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12166                                &pipe_config->pipe_src_w,
12167                                &pipe_config->pipe_src_h);
12168
12169 encoder_retry:
12170         /* Ensure the port clock defaults are reset when retrying. */
12171         pipe_config->port_clock = 0;
12172         pipe_config->pixel_multiplier = 1;
12173
12174         /* Fill in default crtc timings, allow encoders to overwrite them. */
12175         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12176                               CRTC_STEREO_DOUBLE);
12177
12178         /* Pass our mode to the connectors and the CRTC to give them a chance to
12179          * adjust it according to limitations or connector properties, and also
12180          * a chance to reject the mode entirely.
12181          */
12182         for_each_connector_in_state(state, connector, connector_state, i) {
12183                 if (connector_state->crtc != crtc)
12184                         continue;
12185
12186                 encoder = to_intel_encoder(connector_state->best_encoder);
12187
12188                 if (!(encoder->compute_config(encoder, pipe_config))) {
12189                         DRM_DEBUG_KMS("Encoder config failure\n");
12190                         goto fail;
12191                 }
12192         }
12193
12194         /* Set default port clock if not overwritten by the encoder. Needs to be
12195          * done afterwards in case the encoder adjusts the mode. */
12196         if (!pipe_config->port_clock)
12197                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12198                         * pipe_config->pixel_multiplier;
12199
12200         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12201         if (ret < 0) {
12202                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12203                 goto fail;
12204         }
12205
12206         if (ret == RETRY) {
12207                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12208                         ret = -EINVAL;
12209                         goto fail;
12210                 }
12211
12212                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12213                 retry = false;
12214                 goto encoder_retry;
12215         }
12216
12217         /* Dithering seems to not pass-through bits correctly when it should, so
12218          * only enable it on 6bpc panels. */
12219         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12220         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12221                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12222
12223 fail:
12224         return ret;
12225 }
12226
12227 static void
12228 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12229 {
12230         struct drm_crtc *crtc;
12231         struct drm_crtc_state *crtc_state;
12232         int i;
12233
12234         /* Double check state. */
12235         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12236                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12237
12238                 /* Update hwmode for vblank functions */
12239                 if (crtc->state->active)
12240                         crtc->hwmode = crtc->state->adjusted_mode;
12241                 else
12242                         crtc->hwmode.crtc_clock = 0;
12243         }
12244 }
12245
12246 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12247 {
12248         int diff;
12249
12250         if (clock1 == clock2)
12251                 return true;
12252
12253         if (!clock1 || !clock2)
12254                 return false;
12255
12256         diff = abs(clock1 - clock2);
12257
12258         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12259                 return true;
12260
12261         return false;
12262 }
12263
12264 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12265         list_for_each_entry((intel_crtc), \
12266                             &(dev)->mode_config.crtc_list, \
12267                             base.head) \
12268                 if (mask & (1 <<(intel_crtc)->pipe))
12269
12270 static bool
12271 intel_compare_m_n(unsigned int m, unsigned int n,
12272                   unsigned int m2, unsigned int n2,
12273                   bool exact)
12274 {
12275         if (m == m2 && n == n2)
12276                 return true;
12277
12278         if (exact || !m || !n || !m2 || !n2)
12279                 return false;
12280
12281         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12282
12283         if (m > m2) {
12284                 while (m > m2) {
12285                         m2 <<= 1;
12286                         n2 <<= 1;
12287                 }
12288         } else if (m < m2) {
12289                 while (m < m2) {
12290                         m <<= 1;
12291                         n <<= 1;
12292                 }
12293         }
12294
12295         return m == m2 && n == n2;
12296 }
12297
12298 static bool
12299 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12300                        struct intel_link_m_n *m2_n2,
12301                        bool adjust)
12302 {
12303         if (m_n->tu == m2_n2->tu &&
12304             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12305                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12306             intel_compare_m_n(m_n->link_m, m_n->link_n,
12307                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12308                 if (adjust)
12309                         *m2_n2 = *m_n;
12310
12311                 return true;
12312         }
12313
12314         return false;
12315 }
12316
12317 static bool
12318 intel_pipe_config_compare(struct drm_device *dev,
12319                           struct intel_crtc_state *current_config,
12320                           struct intel_crtc_state *pipe_config,
12321                           bool adjust)
12322 {
12323         bool ret = true;
12324
12325 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12326         do { \
12327                 if (!adjust) \
12328                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12329                 else \
12330                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12331         } while (0)
12332
12333 #define PIPE_CONF_CHECK_X(name) \
12334         if (current_config->name != pipe_config->name) { \
12335                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12336                           "(expected 0x%08x, found 0x%08x)\n", \
12337                           current_config->name, \
12338                           pipe_config->name); \
12339                 ret = false; \
12340         }
12341
12342 #define PIPE_CONF_CHECK_I(name) \
12343         if (current_config->name != pipe_config->name) { \
12344                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12345                           "(expected %i, found %i)\n", \
12346                           current_config->name, \
12347                           pipe_config->name); \
12348                 ret = false; \
12349         }
12350
12351 #define PIPE_CONF_CHECK_M_N(name) \
12352         if (!intel_compare_link_m_n(&current_config->name, \
12353                                     &pipe_config->name,\
12354                                     adjust)) { \
12355                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12356                           "(expected tu %i gmch %i/%i link %i/%i, " \
12357                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12358                           current_config->name.tu, \
12359                           current_config->name.gmch_m, \
12360                           current_config->name.gmch_n, \
12361                           current_config->name.link_m, \
12362                           current_config->name.link_n, \
12363                           pipe_config->name.tu, \
12364                           pipe_config->name.gmch_m, \
12365                           pipe_config->name.gmch_n, \
12366                           pipe_config->name.link_m, \
12367                           pipe_config->name.link_n); \
12368                 ret = false; \
12369         }
12370
12371 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12372         if (!intel_compare_link_m_n(&current_config->name, \
12373                                     &pipe_config->name, adjust) && \
12374             !intel_compare_link_m_n(&current_config->alt_name, \
12375                                     &pipe_config->name, adjust)) { \
12376                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12377                           "(expected tu %i gmch %i/%i link %i/%i, " \
12378                           "or tu %i gmch %i/%i link %i/%i, " \
12379                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12380                           current_config->name.tu, \
12381                           current_config->name.gmch_m, \
12382                           current_config->name.gmch_n, \
12383                           current_config->name.link_m, \
12384                           current_config->name.link_n, \
12385                           current_config->alt_name.tu, \
12386                           current_config->alt_name.gmch_m, \
12387                           current_config->alt_name.gmch_n, \
12388                           current_config->alt_name.link_m, \
12389                           current_config->alt_name.link_n, \
12390                           pipe_config->name.tu, \
12391                           pipe_config->name.gmch_m, \
12392                           pipe_config->name.gmch_n, \
12393                           pipe_config->name.link_m, \
12394                           pipe_config->name.link_n); \
12395                 ret = false; \
12396         }
12397
12398 /* This is required for BDW+ where there is only one set of registers for
12399  * switching between high and low RR.
12400  * This macro can be used whenever a comparison has to be made between one
12401  * hw state and multiple sw state variables.
12402  */
12403 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12404         if ((current_config->name != pipe_config->name) && \
12405                 (current_config->alt_name != pipe_config->name)) { \
12406                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12407                                   "(expected %i or %i, found %i)\n", \
12408                                   current_config->name, \
12409                                   current_config->alt_name, \
12410                                   pipe_config->name); \
12411                         ret = false; \
12412         }
12413
12414 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12415         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12416                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12417                           "(expected %i, found %i)\n", \
12418                           current_config->name & (mask), \
12419                           pipe_config->name & (mask)); \
12420                 ret = false; \
12421         }
12422
12423 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12424         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12425                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12426                           "(expected %i, found %i)\n", \
12427                           current_config->name, \
12428                           pipe_config->name); \
12429                 ret = false; \
12430         }
12431
12432 #define PIPE_CONF_QUIRK(quirk)  \
12433         ((current_config->quirks | pipe_config->quirks) & (quirk))
12434
12435         PIPE_CONF_CHECK_I(cpu_transcoder);
12436
12437         PIPE_CONF_CHECK_I(has_pch_encoder);
12438         PIPE_CONF_CHECK_I(fdi_lanes);
12439         PIPE_CONF_CHECK_M_N(fdi_m_n);
12440
12441         PIPE_CONF_CHECK_I(has_dp_encoder);
12442         PIPE_CONF_CHECK_I(lane_count);
12443
12444         if (INTEL_INFO(dev)->gen < 8) {
12445                 PIPE_CONF_CHECK_M_N(dp_m_n);
12446
12447                 PIPE_CONF_CHECK_I(has_drrs);
12448                 if (current_config->has_drrs)
12449                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12450         } else
12451                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12452
12453         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12454         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12455         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12456         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12457         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12458         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12459
12460         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12461         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12462         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12463         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12464         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12465         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12466
12467         PIPE_CONF_CHECK_I(pixel_multiplier);
12468         PIPE_CONF_CHECK_I(has_hdmi_sink);
12469         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12470             IS_VALLEYVIEW(dev))
12471                 PIPE_CONF_CHECK_I(limited_color_range);
12472         PIPE_CONF_CHECK_I(has_infoframe);
12473
12474         PIPE_CONF_CHECK_I(has_audio);
12475
12476         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12477                               DRM_MODE_FLAG_INTERLACE);
12478
12479         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12480                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12481                                       DRM_MODE_FLAG_PHSYNC);
12482                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12483                                       DRM_MODE_FLAG_NHSYNC);
12484                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12485                                       DRM_MODE_FLAG_PVSYNC);
12486                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12487                                       DRM_MODE_FLAG_NVSYNC);
12488         }
12489
12490         PIPE_CONF_CHECK_X(gmch_pfit.control);
12491         /* pfit ratios are autocomputed by the hw on gen4+ */
12492         if (INTEL_INFO(dev)->gen < 4)
12493                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12494         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12495
12496         if (!adjust) {
12497                 PIPE_CONF_CHECK_I(pipe_src_w);
12498                 PIPE_CONF_CHECK_I(pipe_src_h);
12499
12500                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12501                 if (current_config->pch_pfit.enabled) {
12502                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12503                         PIPE_CONF_CHECK_X(pch_pfit.size);
12504                 }
12505
12506                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12507         }
12508
12509         /* BDW+ don't expose a synchronous way to read the state */
12510         if (IS_HASWELL(dev))
12511                 PIPE_CONF_CHECK_I(ips_enabled);
12512
12513         PIPE_CONF_CHECK_I(double_wide);
12514
12515         PIPE_CONF_CHECK_X(ddi_pll_sel);
12516
12517         PIPE_CONF_CHECK_I(shared_dpll);
12518         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12519         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12520         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12521         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12522         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12523         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12524         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12525         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12526
12527         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12528                 PIPE_CONF_CHECK_I(pipe_bpp);
12529
12530         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12531         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12532
12533 #undef PIPE_CONF_CHECK_X
12534 #undef PIPE_CONF_CHECK_I
12535 #undef PIPE_CONF_CHECK_I_ALT
12536 #undef PIPE_CONF_CHECK_FLAGS
12537 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12538 #undef PIPE_CONF_QUIRK
12539 #undef INTEL_ERR_OR_DBG_KMS
12540
12541         return ret;
12542 }
12543
12544 static void check_wm_state(struct drm_device *dev)
12545 {
12546         struct drm_i915_private *dev_priv = dev->dev_private;
12547         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12548         struct intel_crtc *intel_crtc;
12549         int plane;
12550
12551         if (INTEL_INFO(dev)->gen < 9)
12552                 return;
12553
12554         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12555         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12556
12557         for_each_intel_crtc(dev, intel_crtc) {
12558                 struct skl_ddb_entry *hw_entry, *sw_entry;
12559                 const enum pipe pipe = intel_crtc->pipe;
12560
12561                 if (!intel_crtc->active)
12562                         continue;
12563
12564                 /* planes */
12565                 for_each_plane(dev_priv, pipe, plane) {
12566                         hw_entry = &hw_ddb.plane[pipe][plane];
12567                         sw_entry = &sw_ddb->plane[pipe][plane];
12568
12569                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12570                                 continue;
12571
12572                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12573                                   "(expected (%u,%u), found (%u,%u))\n",
12574                                   pipe_name(pipe), plane + 1,
12575                                   sw_entry->start, sw_entry->end,
12576                                   hw_entry->start, hw_entry->end);
12577                 }
12578
12579                 /* cursor */
12580                 hw_entry = &hw_ddb.cursor[pipe];
12581                 sw_entry = &sw_ddb->cursor[pipe];
12582
12583                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12584                         continue;
12585
12586                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12587                           "(expected (%u,%u), found (%u,%u))\n",
12588                           pipe_name(pipe),
12589                           sw_entry->start, sw_entry->end,
12590                           hw_entry->start, hw_entry->end);
12591         }
12592 }
12593
12594 static void
12595 check_connector_state(struct drm_device *dev,
12596                       struct drm_atomic_state *old_state)
12597 {
12598         struct drm_connector_state *old_conn_state;
12599         struct drm_connector *connector;
12600         int i;
12601
12602         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12603                 struct drm_encoder *encoder = connector->encoder;
12604                 struct drm_connector_state *state = connector->state;
12605
12606                 /* This also checks the encoder/connector hw state with the
12607                  * ->get_hw_state callbacks. */
12608                 intel_connector_check_state(to_intel_connector(connector));
12609
12610                 I915_STATE_WARN(state->best_encoder != encoder,
12611                      "connector's atomic encoder doesn't match legacy encoder\n");
12612         }
12613 }
12614
12615 static void
12616 check_encoder_state(struct drm_device *dev)
12617 {
12618         struct intel_encoder *encoder;
12619         struct intel_connector *connector;
12620
12621         for_each_intel_encoder(dev, encoder) {
12622                 bool enabled = false;
12623                 enum pipe pipe;
12624
12625                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12626                               encoder->base.base.id,
12627                               encoder->base.name);
12628
12629                 for_each_intel_connector(dev, connector) {
12630                         if (connector->base.state->best_encoder != &encoder->base)
12631                                 continue;
12632                         enabled = true;
12633
12634                         I915_STATE_WARN(connector->base.state->crtc !=
12635                                         encoder->base.crtc,
12636                              "connector's crtc doesn't match encoder crtc\n");
12637                 }
12638
12639                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12640                      "encoder's enabled state mismatch "
12641                      "(expected %i, found %i)\n",
12642                      !!encoder->base.crtc, enabled);
12643
12644                 if (!encoder->base.crtc) {
12645                         bool active;
12646
12647                         active = encoder->get_hw_state(encoder, &pipe);
12648                         I915_STATE_WARN(active,
12649                              "encoder detached but still enabled on pipe %c.\n",
12650                              pipe_name(pipe));
12651                 }
12652         }
12653 }
12654
12655 static void
12656 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12657 {
12658         struct drm_i915_private *dev_priv = dev->dev_private;
12659         struct intel_encoder *encoder;
12660         struct drm_crtc_state *old_crtc_state;
12661         struct drm_crtc *crtc;
12662         int i;
12663
12664         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12665                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12666                 struct intel_crtc_state *pipe_config, *sw_config;
12667                 bool active;
12668
12669                 if (!needs_modeset(crtc->state) &&
12670                     !to_intel_crtc_state(crtc->state)->update_pipe)
12671                         continue;
12672
12673                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12674                 pipe_config = to_intel_crtc_state(old_crtc_state);
12675                 memset(pipe_config, 0, sizeof(*pipe_config));
12676                 pipe_config->base.crtc = crtc;
12677                 pipe_config->base.state = old_state;
12678
12679                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12680                               crtc->base.id);
12681
12682                 active = dev_priv->display.get_pipe_config(intel_crtc,
12683                                                            pipe_config);
12684
12685                 /* hw state is inconsistent with the pipe quirk */
12686                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12687                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12688                         active = crtc->state->active;
12689
12690                 I915_STATE_WARN(crtc->state->active != active,
12691                      "crtc active state doesn't match with hw state "
12692                      "(expected %i, found %i)\n", crtc->state->active, active);
12693
12694                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12695                      "transitional active state does not match atomic hw state "
12696                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12697
12698                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12699                         enum pipe pipe;
12700
12701                         active = encoder->get_hw_state(encoder, &pipe);
12702                         I915_STATE_WARN(active != crtc->state->active,
12703                                 "[ENCODER:%i] active %i with crtc active %i\n",
12704                                 encoder->base.base.id, active, crtc->state->active);
12705
12706                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12707                                         "Encoder connected to wrong pipe %c\n",
12708                                         pipe_name(pipe));
12709
12710                         if (active)
12711                                 encoder->get_config(encoder, pipe_config);
12712                 }
12713
12714                 if (!crtc->state->active)
12715                         continue;
12716
12717                 sw_config = to_intel_crtc_state(crtc->state);
12718                 if (!intel_pipe_config_compare(dev, sw_config,
12719                                                pipe_config, false)) {
12720                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12721                         intel_dump_pipe_config(intel_crtc, pipe_config,
12722                                                "[hw state]");
12723                         intel_dump_pipe_config(intel_crtc, sw_config,
12724                                                "[sw state]");
12725                 }
12726         }
12727 }
12728
12729 static void
12730 check_shared_dpll_state(struct drm_device *dev)
12731 {
12732         struct drm_i915_private *dev_priv = dev->dev_private;
12733         struct intel_crtc *crtc;
12734         struct intel_dpll_hw_state dpll_hw_state;
12735         int i;
12736
12737         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12738                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12739                 int enabled_crtcs = 0, active_crtcs = 0;
12740                 bool active;
12741
12742                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12743
12744                 DRM_DEBUG_KMS("%s\n", pll->name);
12745
12746                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12747
12748                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12749                      "more active pll users than references: %i vs %i\n",
12750                      pll->active, hweight32(pll->config.crtc_mask));
12751                 I915_STATE_WARN(pll->active && !pll->on,
12752                      "pll in active use but not on in sw tracking\n");
12753                 I915_STATE_WARN(pll->on && !pll->active,
12754                      "pll in on but not on in use in sw tracking\n");
12755                 I915_STATE_WARN(pll->on != active,
12756                      "pll on state mismatch (expected %i, found %i)\n",
12757                      pll->on, active);
12758
12759                 for_each_intel_crtc(dev, crtc) {
12760                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12761                                 enabled_crtcs++;
12762                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12763                                 active_crtcs++;
12764                 }
12765                 I915_STATE_WARN(pll->active != active_crtcs,
12766                      "pll active crtcs mismatch (expected %i, found %i)\n",
12767                      pll->active, active_crtcs);
12768                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12769                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12770                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12771
12772                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12773                                        sizeof(dpll_hw_state)),
12774                      "pll hw state mismatch\n");
12775         }
12776 }
12777
12778 static void
12779 intel_modeset_check_state(struct drm_device *dev,
12780                           struct drm_atomic_state *old_state)
12781 {
12782         check_wm_state(dev);
12783         check_connector_state(dev, old_state);
12784         check_encoder_state(dev);
12785         check_crtc_state(dev, old_state);
12786         check_shared_dpll_state(dev);
12787 }
12788
12789 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12790                                      int dotclock)
12791 {
12792         /*
12793          * FDI already provided one idea for the dotclock.
12794          * Yell if the encoder disagrees.
12795          */
12796         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12797              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12798              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12799 }
12800
12801 static void update_scanline_offset(struct intel_crtc *crtc)
12802 {
12803         struct drm_device *dev = crtc->base.dev;
12804
12805         /*
12806          * The scanline counter increments at the leading edge of hsync.
12807          *
12808          * On most platforms it starts counting from vtotal-1 on the
12809          * first active line. That means the scanline counter value is
12810          * always one less than what we would expect. Ie. just after
12811          * start of vblank, which also occurs at start of hsync (on the
12812          * last active line), the scanline counter will read vblank_start-1.
12813          *
12814          * On gen2 the scanline counter starts counting from 1 instead
12815          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12816          * to keep the value positive), instead of adding one.
12817          *
12818          * On HSW+ the behaviour of the scanline counter depends on the output
12819          * type. For DP ports it behaves like most other platforms, but on HDMI
12820          * there's an extra 1 line difference. So we need to add two instead of
12821          * one to the value.
12822          */
12823         if (IS_GEN2(dev)) {
12824                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12825                 int vtotal;
12826
12827                 vtotal = adjusted_mode->crtc_vtotal;
12828                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12829                         vtotal /= 2;
12830
12831                 crtc->scanline_offset = vtotal - 1;
12832         } else if (HAS_DDI(dev) &&
12833                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12834                 crtc->scanline_offset = 2;
12835         } else
12836                 crtc->scanline_offset = 1;
12837 }
12838
12839 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12840 {
12841         struct drm_device *dev = state->dev;
12842         struct drm_i915_private *dev_priv = to_i915(dev);
12843         struct intel_shared_dpll_config *shared_dpll = NULL;
12844         struct intel_crtc *intel_crtc;
12845         struct intel_crtc_state *intel_crtc_state;
12846         struct drm_crtc *crtc;
12847         struct drm_crtc_state *crtc_state;
12848         int i;
12849
12850         if (!dev_priv->display.crtc_compute_clock)
12851                 return;
12852
12853         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12854                 int dpll;
12855
12856                 intel_crtc = to_intel_crtc(crtc);
12857                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12858                 dpll = intel_crtc_state->shared_dpll;
12859
12860                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12861                         continue;
12862
12863                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12864
12865                 if (!shared_dpll)
12866                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12867
12868                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12869         }
12870 }
12871
12872 /*
12873  * This implements the workaround described in the "notes" section of the mode
12874  * set sequence documentation. When going from no pipes or single pipe to
12875  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12876  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12877  */
12878 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12879 {
12880         struct drm_crtc_state *crtc_state;
12881         struct intel_crtc *intel_crtc;
12882         struct drm_crtc *crtc;
12883         struct intel_crtc_state *first_crtc_state = NULL;
12884         struct intel_crtc_state *other_crtc_state = NULL;
12885         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12886         int i;
12887
12888         /* look at all crtc's that are going to be enabled in during modeset */
12889         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12890                 intel_crtc = to_intel_crtc(crtc);
12891
12892                 if (!crtc_state->active || !needs_modeset(crtc_state))
12893                         continue;
12894
12895                 if (first_crtc_state) {
12896                         other_crtc_state = to_intel_crtc_state(crtc_state);
12897                         break;
12898                 } else {
12899                         first_crtc_state = to_intel_crtc_state(crtc_state);
12900                         first_pipe = intel_crtc->pipe;
12901                 }
12902         }
12903
12904         /* No workaround needed? */
12905         if (!first_crtc_state)
12906                 return 0;
12907
12908         /* w/a possibly needed, check how many crtc's are already enabled. */
12909         for_each_intel_crtc(state->dev, intel_crtc) {
12910                 struct intel_crtc_state *pipe_config;
12911
12912                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12913                 if (IS_ERR(pipe_config))
12914                         return PTR_ERR(pipe_config);
12915
12916                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12917
12918                 if (!pipe_config->base.active ||
12919                     needs_modeset(&pipe_config->base))
12920                         continue;
12921
12922                 /* 2 or more enabled crtcs means no need for w/a */
12923                 if (enabled_pipe != INVALID_PIPE)
12924                         return 0;
12925
12926                 enabled_pipe = intel_crtc->pipe;
12927         }
12928
12929         if (enabled_pipe != INVALID_PIPE)
12930                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12931         else if (other_crtc_state)
12932                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12933
12934         return 0;
12935 }
12936
12937 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12938 {
12939         struct drm_crtc *crtc;
12940         struct drm_crtc_state *crtc_state;
12941         int ret = 0;
12942
12943         /* add all active pipes to the state */
12944         for_each_crtc(state->dev, crtc) {
12945                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12946                 if (IS_ERR(crtc_state))
12947                         return PTR_ERR(crtc_state);
12948
12949                 if (!crtc_state->active || needs_modeset(crtc_state))
12950                         continue;
12951
12952                 crtc_state->mode_changed = true;
12953
12954                 ret = drm_atomic_add_affected_connectors(state, crtc);
12955                 if (ret)
12956                         break;
12957
12958                 ret = drm_atomic_add_affected_planes(state, crtc);
12959                 if (ret)
12960                         break;
12961         }
12962
12963         return ret;
12964 }
12965
12966 static int intel_modeset_checks(struct drm_atomic_state *state)
12967 {
12968         struct drm_device *dev = state->dev;
12969         struct drm_i915_private *dev_priv = dev->dev_private;
12970         int ret;
12971
12972         if (!check_digital_port_conflicts(state)) {
12973                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12974                 return -EINVAL;
12975         }
12976
12977         /*
12978          * See if the config requires any additional preparation, e.g.
12979          * to adjust global state with pipes off.  We need to do this
12980          * here so we can get the modeset_pipe updated config for the new
12981          * mode set on this crtc.  For other crtcs we need to use the
12982          * adjusted_mode bits in the crtc directly.
12983          */
12984         if (dev_priv->display.modeset_calc_cdclk) {
12985                 unsigned int cdclk;
12986
12987                 ret = dev_priv->display.modeset_calc_cdclk(state);
12988
12989                 cdclk = to_intel_atomic_state(state)->cdclk;
12990                 if (!ret && cdclk != dev_priv->cdclk_freq)
12991                         ret = intel_modeset_all_pipes(state);
12992
12993                 if (ret < 0)
12994                         return ret;
12995         } else
12996                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12997
12998         intel_modeset_clear_plls(state);
12999
13000         if (IS_HASWELL(dev))
13001                 return haswell_mode_set_planes_workaround(state);
13002
13003         return 0;
13004 }
13005
13006 /**
13007  * intel_atomic_check - validate state object
13008  * @dev: drm device
13009  * @state: state to validate
13010  */
13011 static int intel_atomic_check(struct drm_device *dev,
13012                               struct drm_atomic_state *state)
13013 {
13014         struct drm_crtc *crtc;
13015         struct drm_crtc_state *crtc_state;
13016         int ret, i;
13017         bool any_ms = false;
13018
13019         ret = drm_atomic_helper_check_modeset(dev, state);
13020         if (ret)
13021                 return ret;
13022
13023         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13024                 struct intel_crtc_state *pipe_config =
13025                         to_intel_crtc_state(crtc_state);
13026
13027                 /* Catch I915_MODE_FLAG_INHERITED */
13028                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13029                         crtc_state->mode_changed = true;
13030
13031                 if (!crtc_state->enable) {
13032                         if (needs_modeset(crtc_state))
13033                                 any_ms = true;
13034                         continue;
13035                 }
13036
13037                 if (!needs_modeset(crtc_state))
13038                         continue;
13039
13040                 /* FIXME: For only active_changed we shouldn't need to do any
13041                  * state recomputation at all. */
13042
13043                 ret = drm_atomic_add_affected_connectors(state, crtc);
13044                 if (ret)
13045                         return ret;
13046
13047                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13048                 if (ret)
13049                         return ret;
13050
13051                 if (intel_pipe_config_compare(state->dev,
13052                                         to_intel_crtc_state(crtc->state),
13053                                         pipe_config, true)) {
13054                         crtc_state->mode_changed = false;
13055                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13056                 }
13057
13058                 if (needs_modeset(crtc_state)) {
13059                         any_ms = true;
13060
13061                         ret = drm_atomic_add_affected_planes(state, crtc);
13062                         if (ret)
13063                                 return ret;
13064                 }
13065
13066                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13067                                        needs_modeset(crtc_state) ?
13068                                        "[modeset]" : "[fastset]");
13069         }
13070
13071         if (any_ms) {
13072                 ret = intel_modeset_checks(state);
13073
13074                 if (ret)
13075                         return ret;
13076         } else
13077                 to_intel_atomic_state(state)->cdclk =
13078                         to_i915(state->dev)->cdclk_freq;
13079
13080         return drm_atomic_helper_check_planes(state->dev, state);
13081 }
13082
13083 /**
13084  * intel_atomic_commit - commit validated state object
13085  * @dev: DRM device
13086  * @state: the top-level driver state object
13087  * @async: asynchronous commit
13088  *
13089  * This function commits a top-level state object that has been validated
13090  * with drm_atomic_helper_check().
13091  *
13092  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13093  * we can only handle plane-related operations and do not yet support
13094  * asynchronous commit.
13095  *
13096  * RETURNS
13097  * Zero for success or -errno.
13098  */
13099 static int intel_atomic_commit(struct drm_device *dev,
13100                                struct drm_atomic_state *state,
13101                                bool async)
13102 {
13103         struct drm_i915_private *dev_priv = dev->dev_private;
13104         struct drm_crtc *crtc;
13105         struct drm_crtc_state *crtc_state;
13106         int ret = 0;
13107         int i;
13108         bool any_ms = false;
13109
13110         if (async) {
13111                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13112                 return -EINVAL;
13113         }
13114
13115         ret = drm_atomic_helper_prepare_planes(dev, state);
13116         if (ret)
13117                 return ret;
13118
13119         drm_atomic_helper_swap_state(dev, state);
13120
13121         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13122                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13123
13124                 if (!needs_modeset(crtc->state))
13125                         continue;
13126
13127                 any_ms = true;
13128                 intel_pre_plane_update(intel_crtc);
13129
13130                 if (crtc_state->active) {
13131                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13132                         dev_priv->display.crtc_disable(crtc);
13133                         intel_crtc->active = false;
13134                         intel_disable_shared_dpll(intel_crtc);
13135                 }
13136         }
13137
13138         /* Only after disabling all output pipelines that will be changed can we
13139          * update the the output configuration. */
13140         intel_modeset_update_crtc_state(state);
13141
13142         if (any_ms) {
13143                 intel_shared_dpll_commit(state);
13144
13145                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13146                 modeset_update_crtc_power_domains(state);
13147         }
13148
13149         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13150         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13151                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13152                 bool modeset = needs_modeset(crtc->state);
13153                 bool update_pipe = !modeset &&
13154                         to_intel_crtc_state(crtc->state)->update_pipe;
13155                 unsigned long put_domains = 0;
13156
13157                 if (modeset && crtc->state->active) {
13158                         update_scanline_offset(to_intel_crtc(crtc));
13159                         dev_priv->display.crtc_enable(crtc);
13160                 }
13161
13162                 if (update_pipe) {
13163                         put_domains = modeset_get_crtc_power_domains(crtc);
13164
13165                         /* make sure intel_modeset_check_state runs */
13166                         any_ms = true;
13167                 }
13168
13169                 if (!modeset)
13170                         intel_pre_plane_update(intel_crtc);
13171
13172                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13173
13174                 if (put_domains)
13175                         modeset_put_power_domains(dev_priv, put_domains);
13176
13177                 intel_post_plane_update(intel_crtc);
13178         }
13179
13180         /* FIXME: add subpixel order */
13181
13182         drm_atomic_helper_wait_for_vblanks(dev, state);
13183         drm_atomic_helper_cleanup_planes(dev, state);
13184
13185         if (any_ms)
13186                 intel_modeset_check_state(dev, state);
13187
13188         drm_atomic_state_free(state);
13189
13190         return 0;
13191 }
13192
13193 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13194 {
13195         struct drm_device *dev = crtc->dev;
13196         struct drm_atomic_state *state;
13197         struct drm_crtc_state *crtc_state;
13198         int ret;
13199
13200         state = drm_atomic_state_alloc(dev);
13201         if (!state) {
13202                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13203                               crtc->base.id);
13204                 return;
13205         }
13206
13207         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13208
13209 retry:
13210         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13211         ret = PTR_ERR_OR_ZERO(crtc_state);
13212         if (!ret) {
13213                 if (!crtc_state->active)
13214                         goto out;
13215
13216                 crtc_state->mode_changed = true;
13217                 ret = drm_atomic_commit(state);
13218         }
13219
13220         if (ret == -EDEADLK) {
13221                 drm_atomic_state_clear(state);
13222                 drm_modeset_backoff(state->acquire_ctx);
13223                 goto retry;
13224         }
13225
13226         if (ret)
13227 out:
13228                 drm_atomic_state_free(state);
13229 }
13230
13231 #undef for_each_intel_crtc_masked
13232
13233 static const struct drm_crtc_funcs intel_crtc_funcs = {
13234         .gamma_set = intel_crtc_gamma_set,
13235         .set_config = drm_atomic_helper_set_config,
13236         .destroy = intel_crtc_destroy,
13237         .page_flip = intel_crtc_page_flip,
13238         .atomic_duplicate_state = intel_crtc_duplicate_state,
13239         .atomic_destroy_state = intel_crtc_destroy_state,
13240 };
13241
13242 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13243                                       struct intel_shared_dpll *pll,
13244                                       struct intel_dpll_hw_state *hw_state)
13245 {
13246         uint32_t val;
13247
13248         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13249                 return false;
13250
13251         val = I915_READ(PCH_DPLL(pll->id));
13252         hw_state->dpll = val;
13253         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13254         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13255
13256         return val & DPLL_VCO_ENABLE;
13257 }
13258
13259 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13260                                   struct intel_shared_dpll *pll)
13261 {
13262         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13263         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13264 }
13265
13266 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13267                                 struct intel_shared_dpll *pll)
13268 {
13269         /* PCH refclock must be enabled first */
13270         ibx_assert_pch_refclk_enabled(dev_priv);
13271
13272         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13273
13274         /* Wait for the clocks to stabilize. */
13275         POSTING_READ(PCH_DPLL(pll->id));
13276         udelay(150);
13277
13278         /* The pixel multiplier can only be updated once the
13279          * DPLL is enabled and the clocks are stable.
13280          *
13281          * So write it again.
13282          */
13283         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13284         POSTING_READ(PCH_DPLL(pll->id));
13285         udelay(200);
13286 }
13287
13288 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13289                                  struct intel_shared_dpll *pll)
13290 {
13291         struct drm_device *dev = dev_priv->dev;
13292         struct intel_crtc *crtc;
13293
13294         /* Make sure no transcoder isn't still depending on us. */
13295         for_each_intel_crtc(dev, crtc) {
13296                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13297                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13298         }
13299
13300         I915_WRITE(PCH_DPLL(pll->id), 0);
13301         POSTING_READ(PCH_DPLL(pll->id));
13302         udelay(200);
13303 }
13304
13305 static char *ibx_pch_dpll_names[] = {
13306         "PCH DPLL A",
13307         "PCH DPLL B",
13308 };
13309
13310 static void ibx_pch_dpll_init(struct drm_device *dev)
13311 {
13312         struct drm_i915_private *dev_priv = dev->dev_private;
13313         int i;
13314
13315         dev_priv->num_shared_dpll = 2;
13316
13317         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13318                 dev_priv->shared_dplls[i].id = i;
13319                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13320                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13321                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13322                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13323                 dev_priv->shared_dplls[i].get_hw_state =
13324                         ibx_pch_dpll_get_hw_state;
13325         }
13326 }
13327
13328 static void intel_shared_dpll_init(struct drm_device *dev)
13329 {
13330         struct drm_i915_private *dev_priv = dev->dev_private;
13331
13332         intel_update_cdclk(dev);
13333
13334         if (HAS_DDI(dev))
13335                 intel_ddi_pll_init(dev);
13336         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13337                 ibx_pch_dpll_init(dev);
13338         else
13339                 dev_priv->num_shared_dpll = 0;
13340
13341         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13342 }
13343
13344 /**
13345  * intel_prepare_plane_fb - Prepare fb for usage on plane
13346  * @plane: drm plane to prepare for
13347  * @fb: framebuffer to prepare for presentation
13348  *
13349  * Prepares a framebuffer for usage on a display plane.  Generally this
13350  * involves pinning the underlying object and updating the frontbuffer tracking
13351  * bits.  Some older platforms need special physical address handling for
13352  * cursor planes.
13353  *
13354  * Returns 0 on success, negative error code on failure.
13355  */
13356 int
13357 intel_prepare_plane_fb(struct drm_plane *plane,
13358                        const struct drm_plane_state *new_state)
13359 {
13360         struct drm_device *dev = plane->dev;
13361         struct drm_framebuffer *fb = new_state->fb;
13362         struct intel_plane *intel_plane = to_intel_plane(plane);
13363         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13364         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13365         int ret = 0;
13366
13367         if (!obj)
13368                 return 0;
13369
13370         mutex_lock(&dev->struct_mutex);
13371
13372         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13373             INTEL_INFO(dev)->cursor_needs_physical) {
13374                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13375                 ret = i915_gem_object_attach_phys(obj, align);
13376                 if (ret)
13377                         DRM_DEBUG_KMS("failed to attach phys object\n");
13378         } else {
13379                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13380         }
13381
13382         if (ret == 0)
13383                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13384
13385         mutex_unlock(&dev->struct_mutex);
13386
13387         return ret;
13388 }
13389
13390 /**
13391  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13392  * @plane: drm plane to clean up for
13393  * @fb: old framebuffer that was on plane
13394  *
13395  * Cleans up a framebuffer that has just been removed from a plane.
13396  */
13397 void
13398 intel_cleanup_plane_fb(struct drm_plane *plane,
13399                        const struct drm_plane_state *old_state)
13400 {
13401         struct drm_device *dev = plane->dev;
13402         struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13403
13404         if (!obj)
13405                 return;
13406
13407         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13408             !INTEL_INFO(dev)->cursor_needs_physical) {
13409                 mutex_lock(&dev->struct_mutex);
13410                 intel_unpin_fb_obj(old_state->fb, old_state);
13411                 mutex_unlock(&dev->struct_mutex);
13412         }
13413 }
13414
13415 int
13416 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13417 {
13418         int max_scale;
13419         struct drm_device *dev;
13420         struct drm_i915_private *dev_priv;
13421         int crtc_clock, cdclk;
13422
13423         if (!intel_crtc || !crtc_state)
13424                 return DRM_PLANE_HELPER_NO_SCALING;
13425
13426         dev = intel_crtc->base.dev;
13427         dev_priv = dev->dev_private;
13428         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13429         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13430
13431         if (!crtc_clock || !cdclk)
13432                 return DRM_PLANE_HELPER_NO_SCALING;
13433
13434         /*
13435          * skl max scale is lower of:
13436          *    close to 3 but not 3, -1 is for that purpose
13437          *            or
13438          *    cdclk/crtc_clock
13439          */
13440         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13441
13442         return max_scale;
13443 }
13444
13445 static int
13446 intel_check_primary_plane(struct drm_plane *plane,
13447                           struct intel_crtc_state *crtc_state,
13448                           struct intel_plane_state *state)
13449 {
13450         struct drm_crtc *crtc = state->base.crtc;
13451         struct drm_framebuffer *fb = state->base.fb;
13452         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13453         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13454         bool can_position = false;
13455
13456         /* use scaler when colorkey is not required */
13457         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13458             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13459                 min_scale = 1;
13460                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13461                 can_position = true;
13462         }
13463
13464         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13465                                              &state->dst, &state->clip,
13466                                              min_scale, max_scale,
13467                                              can_position, true,
13468                                              &state->visible);
13469 }
13470
13471 static void
13472 intel_commit_primary_plane(struct drm_plane *plane,
13473                            struct intel_plane_state *state)
13474 {
13475         struct drm_crtc *crtc = state->base.crtc;
13476         struct drm_framebuffer *fb = state->base.fb;
13477         struct drm_device *dev = plane->dev;
13478         struct drm_i915_private *dev_priv = dev->dev_private;
13479         struct intel_crtc *intel_crtc;
13480         struct drm_rect *src = &state->src;
13481
13482         crtc = crtc ? crtc : plane->crtc;
13483         intel_crtc = to_intel_crtc(crtc);
13484
13485         plane->fb = fb;
13486         crtc->x = src->x1 >> 16;
13487         crtc->y = src->y1 >> 16;
13488
13489         if (!crtc->state->active)
13490                 return;
13491
13492         dev_priv->display.update_primary_plane(crtc, fb,
13493                                                state->src.x1 >> 16,
13494                                                state->src.y1 >> 16);
13495 }
13496
13497 static void
13498 intel_disable_primary_plane(struct drm_plane *plane,
13499                             struct drm_crtc *crtc)
13500 {
13501         struct drm_device *dev = plane->dev;
13502         struct drm_i915_private *dev_priv = dev->dev_private;
13503
13504         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13505 }
13506
13507 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13508                                     struct drm_crtc_state *old_crtc_state)
13509 {
13510         struct drm_device *dev = crtc->dev;
13511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13512         struct intel_crtc_state *old_intel_state =
13513                 to_intel_crtc_state(old_crtc_state);
13514         bool modeset = needs_modeset(crtc->state);
13515
13516         if (intel_crtc->atomic.update_wm_pre)
13517                 intel_update_watermarks(crtc);
13518
13519         /* Perform vblank evasion around commit operation */
13520         if (crtc->state->active)
13521                 intel_pipe_update_start(intel_crtc);
13522
13523         if (modeset)
13524                 return;
13525
13526         if (to_intel_crtc_state(crtc->state)->update_pipe)
13527                 intel_update_pipe_config(intel_crtc, old_intel_state);
13528         else if (INTEL_INFO(dev)->gen >= 9)
13529                 skl_detach_scalers(intel_crtc);
13530 }
13531
13532 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13533                                      struct drm_crtc_state *old_crtc_state)
13534 {
13535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13536
13537         if (crtc->state->active)
13538                 intel_pipe_update_end(intel_crtc);
13539 }
13540
13541 /**
13542  * intel_plane_destroy - destroy a plane
13543  * @plane: plane to destroy
13544  *
13545  * Common destruction function for all types of planes (primary, cursor,
13546  * sprite).
13547  */
13548 void intel_plane_destroy(struct drm_plane *plane)
13549 {
13550         struct intel_plane *intel_plane = to_intel_plane(plane);
13551         drm_plane_cleanup(plane);
13552         kfree(intel_plane);
13553 }
13554
13555 const struct drm_plane_funcs intel_plane_funcs = {
13556         .update_plane = drm_atomic_helper_update_plane,
13557         .disable_plane = drm_atomic_helper_disable_plane,
13558         .destroy = intel_plane_destroy,
13559         .set_property = drm_atomic_helper_plane_set_property,
13560         .atomic_get_property = intel_plane_atomic_get_property,
13561         .atomic_set_property = intel_plane_atomic_set_property,
13562         .atomic_duplicate_state = intel_plane_duplicate_state,
13563         .atomic_destroy_state = intel_plane_destroy_state,
13564
13565 };
13566
13567 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13568                                                     int pipe)
13569 {
13570         struct intel_plane *primary;
13571         struct intel_plane_state *state;
13572         const uint32_t *intel_primary_formats;
13573         unsigned int num_formats;
13574
13575         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13576         if (primary == NULL)
13577                 return NULL;
13578
13579         state = intel_create_plane_state(&primary->base);
13580         if (!state) {
13581                 kfree(primary);
13582                 return NULL;
13583         }
13584         primary->base.state = &state->base;
13585
13586         primary->can_scale = false;
13587         primary->max_downscale = 1;
13588         if (INTEL_INFO(dev)->gen >= 9) {
13589                 primary->can_scale = true;
13590                 state->scaler_id = -1;
13591         }
13592         primary->pipe = pipe;
13593         primary->plane = pipe;
13594         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13595         primary->check_plane = intel_check_primary_plane;
13596         primary->commit_plane = intel_commit_primary_plane;
13597         primary->disable_plane = intel_disable_primary_plane;
13598         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13599                 primary->plane = !pipe;
13600
13601         if (INTEL_INFO(dev)->gen >= 9) {
13602                 intel_primary_formats = skl_primary_formats;
13603                 num_formats = ARRAY_SIZE(skl_primary_formats);
13604         } else if (INTEL_INFO(dev)->gen >= 4) {
13605                 intel_primary_formats = i965_primary_formats;
13606                 num_formats = ARRAY_SIZE(i965_primary_formats);
13607         } else {
13608                 intel_primary_formats = i8xx_primary_formats;
13609                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13610         }
13611
13612         drm_universal_plane_init(dev, &primary->base, 0,
13613                                  &intel_plane_funcs,
13614                                  intel_primary_formats, num_formats,
13615                                  DRM_PLANE_TYPE_PRIMARY);
13616
13617         if (INTEL_INFO(dev)->gen >= 4)
13618                 intel_create_rotation_property(dev, primary);
13619
13620         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13621
13622         return &primary->base;
13623 }
13624
13625 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13626 {
13627         if (!dev->mode_config.rotation_property) {
13628                 unsigned long flags = BIT(DRM_ROTATE_0) |
13629                         BIT(DRM_ROTATE_180);
13630
13631                 if (INTEL_INFO(dev)->gen >= 9)
13632                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13633
13634                 dev->mode_config.rotation_property =
13635                         drm_mode_create_rotation_property(dev, flags);
13636         }
13637         if (dev->mode_config.rotation_property)
13638                 drm_object_attach_property(&plane->base.base,
13639                                 dev->mode_config.rotation_property,
13640                                 plane->base.state->rotation);
13641 }
13642
13643 static int
13644 intel_check_cursor_plane(struct drm_plane *plane,
13645                          struct intel_crtc_state *crtc_state,
13646                          struct intel_plane_state *state)
13647 {
13648         struct drm_crtc *crtc = crtc_state->base.crtc;
13649         struct drm_framebuffer *fb = state->base.fb;
13650         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13651         unsigned stride;
13652         int ret;
13653
13654         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13655                                             &state->dst, &state->clip,
13656                                             DRM_PLANE_HELPER_NO_SCALING,
13657                                             DRM_PLANE_HELPER_NO_SCALING,
13658                                             true, true, &state->visible);
13659         if (ret)
13660                 return ret;
13661
13662         /* if we want to turn off the cursor ignore width and height */
13663         if (!obj)
13664                 return 0;
13665
13666         /* Check for which cursor types we support */
13667         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13668                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13669                           state->base.crtc_w, state->base.crtc_h);
13670                 return -EINVAL;
13671         }
13672
13673         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13674         if (obj->base.size < stride * state->base.crtc_h) {
13675                 DRM_DEBUG_KMS("buffer is too small\n");
13676                 return -ENOMEM;
13677         }
13678
13679         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13680                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13681                 return -EINVAL;
13682         }
13683
13684         return 0;
13685 }
13686
13687 static void
13688 intel_disable_cursor_plane(struct drm_plane *plane,
13689                            struct drm_crtc *crtc)
13690 {
13691         intel_crtc_update_cursor(crtc, false);
13692 }
13693
13694 static void
13695 intel_commit_cursor_plane(struct drm_plane *plane,
13696                           struct intel_plane_state *state)
13697 {
13698         struct drm_crtc *crtc = state->base.crtc;
13699         struct drm_device *dev = plane->dev;
13700         struct intel_crtc *intel_crtc;
13701         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13702         uint32_t addr;
13703
13704         crtc = crtc ? crtc : plane->crtc;
13705         intel_crtc = to_intel_crtc(crtc);
13706
13707         if (intel_crtc->cursor_bo == obj)
13708                 goto update;
13709
13710         if (!obj)
13711                 addr = 0;
13712         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13713                 addr = i915_gem_obj_ggtt_offset(obj);
13714         else
13715                 addr = obj->phys_handle->busaddr;
13716
13717         intel_crtc->cursor_addr = addr;
13718         intel_crtc->cursor_bo = obj;
13719
13720 update:
13721         if (crtc->state->active)
13722                 intel_crtc_update_cursor(crtc, state->visible);
13723 }
13724
13725 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13726                                                    int pipe)
13727 {
13728         struct intel_plane *cursor;
13729         struct intel_plane_state *state;
13730
13731         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13732         if (cursor == NULL)
13733                 return NULL;
13734
13735         state = intel_create_plane_state(&cursor->base);
13736         if (!state) {
13737                 kfree(cursor);
13738                 return NULL;
13739         }
13740         cursor->base.state = &state->base;
13741
13742         cursor->can_scale = false;
13743         cursor->max_downscale = 1;
13744         cursor->pipe = pipe;
13745         cursor->plane = pipe;
13746         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13747         cursor->check_plane = intel_check_cursor_plane;
13748         cursor->commit_plane = intel_commit_cursor_plane;
13749         cursor->disable_plane = intel_disable_cursor_plane;
13750
13751         drm_universal_plane_init(dev, &cursor->base, 0,
13752                                  &intel_plane_funcs,
13753                                  intel_cursor_formats,
13754                                  ARRAY_SIZE(intel_cursor_formats),
13755                                  DRM_PLANE_TYPE_CURSOR);
13756
13757         if (INTEL_INFO(dev)->gen >= 4) {
13758                 if (!dev->mode_config.rotation_property)
13759                         dev->mode_config.rotation_property =
13760                                 drm_mode_create_rotation_property(dev,
13761                                                         BIT(DRM_ROTATE_0) |
13762                                                         BIT(DRM_ROTATE_180));
13763                 if (dev->mode_config.rotation_property)
13764                         drm_object_attach_property(&cursor->base.base,
13765                                 dev->mode_config.rotation_property,
13766                                 state->base.rotation);
13767         }
13768
13769         if (INTEL_INFO(dev)->gen >=9)
13770                 state->scaler_id = -1;
13771
13772         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13773
13774         return &cursor->base;
13775 }
13776
13777 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13778         struct intel_crtc_state *crtc_state)
13779 {
13780         int i;
13781         struct intel_scaler *intel_scaler;
13782         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13783
13784         for (i = 0; i < intel_crtc->num_scalers; i++) {
13785                 intel_scaler = &scaler_state->scalers[i];
13786                 intel_scaler->in_use = 0;
13787                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13788         }
13789
13790         scaler_state->scaler_id = -1;
13791 }
13792
13793 static void intel_crtc_init(struct drm_device *dev, int pipe)
13794 {
13795         struct drm_i915_private *dev_priv = dev->dev_private;
13796         struct intel_crtc *intel_crtc;
13797         struct intel_crtc_state *crtc_state = NULL;
13798         struct drm_plane *primary = NULL;
13799         struct drm_plane *cursor = NULL;
13800         int i, ret;
13801
13802         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13803         if (intel_crtc == NULL)
13804                 return;
13805
13806         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13807         if (!crtc_state)
13808                 goto fail;
13809         intel_crtc->config = crtc_state;
13810         intel_crtc->base.state = &crtc_state->base;
13811         crtc_state->base.crtc = &intel_crtc->base;
13812
13813         /* initialize shared scalers */
13814         if (INTEL_INFO(dev)->gen >= 9) {
13815                 if (pipe == PIPE_C)
13816                         intel_crtc->num_scalers = 1;
13817                 else
13818                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13819
13820                 skl_init_scalers(dev, intel_crtc, crtc_state);
13821         }
13822
13823         primary = intel_primary_plane_create(dev, pipe);
13824         if (!primary)
13825                 goto fail;
13826
13827         cursor = intel_cursor_plane_create(dev, pipe);
13828         if (!cursor)
13829                 goto fail;
13830
13831         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13832                                         cursor, &intel_crtc_funcs);
13833         if (ret)
13834                 goto fail;
13835
13836         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13837         for (i = 0; i < 256; i++) {
13838                 intel_crtc->lut_r[i] = i;
13839                 intel_crtc->lut_g[i] = i;
13840                 intel_crtc->lut_b[i] = i;
13841         }
13842
13843         /*
13844          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13845          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13846          */
13847         intel_crtc->pipe = pipe;
13848         intel_crtc->plane = pipe;
13849         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13850                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13851                 intel_crtc->plane = !pipe;
13852         }
13853
13854         intel_crtc->cursor_base = ~0;
13855         intel_crtc->cursor_cntl = ~0;
13856         intel_crtc->cursor_size = ~0;
13857
13858         intel_crtc->wm.cxsr_allowed = true;
13859
13860         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13861                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13862         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13863         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13864
13865         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13866
13867         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13868         return;
13869
13870 fail:
13871         if (primary)
13872                 drm_plane_cleanup(primary);
13873         if (cursor)
13874                 drm_plane_cleanup(cursor);
13875         kfree(crtc_state);
13876         kfree(intel_crtc);
13877 }
13878
13879 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13880 {
13881         struct drm_encoder *encoder = connector->base.encoder;
13882         struct drm_device *dev = connector->base.dev;
13883
13884         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13885
13886         if (!encoder || WARN_ON(!encoder->crtc))
13887                 return INVALID_PIPE;
13888
13889         return to_intel_crtc(encoder->crtc)->pipe;
13890 }
13891
13892 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13893                                 struct drm_file *file)
13894 {
13895         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13896         struct drm_crtc *drmmode_crtc;
13897         struct intel_crtc *crtc;
13898
13899         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13900
13901         if (!drmmode_crtc) {
13902                 DRM_ERROR("no such CRTC id\n");
13903                 return -ENOENT;
13904         }
13905
13906         crtc = to_intel_crtc(drmmode_crtc);
13907         pipe_from_crtc_id->pipe = crtc->pipe;
13908
13909         return 0;
13910 }
13911
13912 static int intel_encoder_clones(struct intel_encoder *encoder)
13913 {
13914         struct drm_device *dev = encoder->base.dev;
13915         struct intel_encoder *source_encoder;
13916         int index_mask = 0;
13917         int entry = 0;
13918
13919         for_each_intel_encoder(dev, source_encoder) {
13920                 if (encoders_cloneable(encoder, source_encoder))
13921                         index_mask |= (1 << entry);
13922
13923                 entry++;
13924         }
13925
13926         return index_mask;
13927 }
13928
13929 static bool has_edp_a(struct drm_device *dev)
13930 {
13931         struct drm_i915_private *dev_priv = dev->dev_private;
13932
13933         if (!IS_MOBILE(dev))
13934                 return false;
13935
13936         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13937                 return false;
13938
13939         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13940                 return false;
13941
13942         return true;
13943 }
13944
13945 static bool intel_crt_present(struct drm_device *dev)
13946 {
13947         struct drm_i915_private *dev_priv = dev->dev_private;
13948
13949         if (INTEL_INFO(dev)->gen >= 9)
13950                 return false;
13951
13952         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13953                 return false;
13954
13955         if (IS_CHERRYVIEW(dev))
13956                 return false;
13957
13958         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13959                 return false;
13960
13961         return true;
13962 }
13963
13964 static void intel_setup_outputs(struct drm_device *dev)
13965 {
13966         struct drm_i915_private *dev_priv = dev->dev_private;
13967         struct intel_encoder *encoder;
13968         bool dpd_is_edp = false;
13969
13970         intel_lvds_init(dev);
13971
13972         if (intel_crt_present(dev))
13973                 intel_crt_init(dev);
13974
13975         if (IS_BROXTON(dev)) {
13976                 /*
13977                  * FIXME: Broxton doesn't support port detection via the
13978                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13979                  * detect the ports.
13980                  */
13981                 intel_ddi_init(dev, PORT_A);
13982                 intel_ddi_init(dev, PORT_B);
13983                 intel_ddi_init(dev, PORT_C);
13984         } else if (HAS_DDI(dev)) {
13985                 int found;
13986
13987                 /*
13988                  * Haswell uses DDI functions to detect digital outputs.
13989                  * On SKL pre-D0 the strap isn't connected, so we assume
13990                  * it's there.
13991                  */
13992                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13993                 /* WaIgnoreDDIAStrap: skl */
13994                 if (found || IS_SKYLAKE(dev))
13995                         intel_ddi_init(dev, PORT_A);
13996
13997                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13998                  * register */
13999                 found = I915_READ(SFUSE_STRAP);
14000
14001                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14002                         intel_ddi_init(dev, PORT_B);
14003                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14004                         intel_ddi_init(dev, PORT_C);
14005                 if (found & SFUSE_STRAP_DDID_DETECTED)
14006                         intel_ddi_init(dev, PORT_D);
14007                 /*
14008                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14009                  */
14010                 if (IS_SKYLAKE(dev) &&
14011                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14012                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14013                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14014                         intel_ddi_init(dev, PORT_E);
14015
14016         } else if (HAS_PCH_SPLIT(dev)) {
14017                 int found;
14018                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14019
14020                 if (has_edp_a(dev))
14021                         intel_dp_init(dev, DP_A, PORT_A);
14022
14023                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14024                         /* PCH SDVOB multiplex with HDMIB */
14025                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14026                         if (!found)
14027                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14028                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14029                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14030                 }
14031
14032                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14033                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14034
14035                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14036                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14037
14038                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14039                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14040
14041                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14042                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14043         } else if (IS_VALLEYVIEW(dev)) {
14044                 /*
14045                  * The DP_DETECTED bit is the latched state of the DDC
14046                  * SDA pin at boot. However since eDP doesn't require DDC
14047                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14048                  * eDP ports may have been muxed to an alternate function.
14049                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14050                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14051                  * detect eDP ports.
14052                  */
14053                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14054                     !intel_dp_is_edp(dev, PORT_B))
14055                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14056                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14057                     intel_dp_is_edp(dev, PORT_B))
14058                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14059
14060                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14061                     !intel_dp_is_edp(dev, PORT_C))
14062                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14063                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14064                     intel_dp_is_edp(dev, PORT_C))
14065                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14066
14067                 if (IS_CHERRYVIEW(dev)) {
14068                         /* eDP not supported on port D, so don't check VBT */
14069                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14070                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14071                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14072                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14073                 }
14074
14075                 intel_dsi_init(dev);
14076         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14077                 bool found = false;
14078
14079                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14080                         DRM_DEBUG_KMS("probing SDVOB\n");
14081                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14082                         if (!found && IS_G4X(dev)) {
14083                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14084                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14085                         }
14086
14087                         if (!found && IS_G4X(dev))
14088                                 intel_dp_init(dev, DP_B, PORT_B);
14089                 }
14090
14091                 /* Before G4X SDVOC doesn't have its own detect register */
14092
14093                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14094                         DRM_DEBUG_KMS("probing SDVOC\n");
14095                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14096                 }
14097
14098                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14099
14100                         if (IS_G4X(dev)) {
14101                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14102                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14103                         }
14104                         if (IS_G4X(dev))
14105                                 intel_dp_init(dev, DP_C, PORT_C);
14106                 }
14107
14108                 if (IS_G4X(dev) &&
14109                     (I915_READ(DP_D) & DP_DETECTED))
14110                         intel_dp_init(dev, DP_D, PORT_D);
14111         } else if (IS_GEN2(dev))
14112                 intel_dvo_init(dev);
14113
14114         if (SUPPORTS_TV(dev))
14115                 intel_tv_init(dev);
14116
14117         intel_psr_init(dev);
14118
14119         for_each_intel_encoder(dev, encoder) {
14120                 encoder->base.possible_crtcs = encoder->crtc_mask;
14121                 encoder->base.possible_clones =
14122                         intel_encoder_clones(encoder);
14123         }
14124
14125         intel_init_pch_refclk(dev);
14126
14127         drm_helper_move_panel_connectors_to_head(dev);
14128 }
14129
14130 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14131 {
14132         struct drm_device *dev = fb->dev;
14133         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14134
14135         drm_framebuffer_cleanup(fb);
14136         mutex_lock(&dev->struct_mutex);
14137         WARN_ON(!intel_fb->obj->framebuffer_references--);
14138         drm_gem_object_unreference(&intel_fb->obj->base);
14139         mutex_unlock(&dev->struct_mutex);
14140         kfree(intel_fb);
14141 }
14142
14143 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14144                                                 struct drm_file *file,
14145                                                 unsigned int *handle)
14146 {
14147         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14148         struct drm_i915_gem_object *obj = intel_fb->obj;
14149
14150         return drm_gem_handle_create(file, &obj->base, handle);
14151 }
14152
14153 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14154                                         struct drm_file *file,
14155                                         unsigned flags, unsigned color,
14156                                         struct drm_clip_rect *clips,
14157                                         unsigned num_clips)
14158 {
14159         struct drm_device *dev = fb->dev;
14160         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14161         struct drm_i915_gem_object *obj = intel_fb->obj;
14162
14163         mutex_lock(&dev->struct_mutex);
14164         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14165         mutex_unlock(&dev->struct_mutex);
14166
14167         return 0;
14168 }
14169
14170 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14171         .destroy = intel_user_framebuffer_destroy,
14172         .create_handle = intel_user_framebuffer_create_handle,
14173         .dirty = intel_user_framebuffer_dirty,
14174 };
14175
14176 static
14177 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14178                          uint32_t pixel_format)
14179 {
14180         u32 gen = INTEL_INFO(dev)->gen;
14181
14182         if (gen >= 9) {
14183                 /* "The stride in bytes must not exceed the of the size of 8K
14184                  *  pixels and 32K bytes."
14185                  */
14186                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14187         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14188                 return 32*1024;
14189         } else if (gen >= 4) {
14190                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14191                         return 16*1024;
14192                 else
14193                         return 32*1024;
14194         } else if (gen >= 3) {
14195                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14196                         return 8*1024;
14197                 else
14198                         return 16*1024;
14199         } else {
14200                 /* XXX DSPC is limited to 4k tiled */
14201                 return 8*1024;
14202         }
14203 }
14204
14205 static int intel_framebuffer_init(struct drm_device *dev,
14206                                   struct intel_framebuffer *intel_fb,
14207                                   struct drm_mode_fb_cmd2 *mode_cmd,
14208                                   struct drm_i915_gem_object *obj)
14209 {
14210         unsigned int aligned_height;
14211         int ret;
14212         u32 pitch_limit, stride_alignment;
14213
14214         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14215
14216         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14217                 /* Enforce that fb modifier and tiling mode match, but only for
14218                  * X-tiled. This is needed for FBC. */
14219                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14220                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14221                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14222                         return -EINVAL;
14223                 }
14224         } else {
14225                 if (obj->tiling_mode == I915_TILING_X)
14226                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14227                 else if (obj->tiling_mode == I915_TILING_Y) {
14228                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14229                         return -EINVAL;
14230                 }
14231         }
14232
14233         /* Passed in modifier sanity checking. */
14234         switch (mode_cmd->modifier[0]) {
14235         case I915_FORMAT_MOD_Y_TILED:
14236         case I915_FORMAT_MOD_Yf_TILED:
14237                 if (INTEL_INFO(dev)->gen < 9) {
14238                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14239                                   mode_cmd->modifier[0]);
14240                         return -EINVAL;
14241                 }
14242         case DRM_FORMAT_MOD_NONE:
14243         case I915_FORMAT_MOD_X_TILED:
14244                 break;
14245         default:
14246                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14247                           mode_cmd->modifier[0]);
14248                 return -EINVAL;
14249         }
14250
14251         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14252                                                      mode_cmd->pixel_format);
14253         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14254                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14255                           mode_cmd->pitches[0], stride_alignment);
14256                 return -EINVAL;
14257         }
14258
14259         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14260                                            mode_cmd->pixel_format);
14261         if (mode_cmd->pitches[0] > pitch_limit) {
14262                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14263                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14264                           "tiled" : "linear",
14265                           mode_cmd->pitches[0], pitch_limit);
14266                 return -EINVAL;
14267         }
14268
14269         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14270             mode_cmd->pitches[0] != obj->stride) {
14271                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14272                           mode_cmd->pitches[0], obj->stride);
14273                 return -EINVAL;
14274         }
14275
14276         /* Reject formats not supported by any plane early. */
14277         switch (mode_cmd->pixel_format) {
14278         case DRM_FORMAT_C8:
14279         case DRM_FORMAT_RGB565:
14280         case DRM_FORMAT_XRGB8888:
14281         case DRM_FORMAT_ARGB8888:
14282                 break;
14283         case DRM_FORMAT_XRGB1555:
14284                 if (INTEL_INFO(dev)->gen > 3) {
14285                         DRM_DEBUG("unsupported pixel format: %s\n",
14286                                   drm_get_format_name(mode_cmd->pixel_format));
14287                         return -EINVAL;
14288                 }
14289                 break;
14290         case DRM_FORMAT_ABGR8888:
14291                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14292                         DRM_DEBUG("unsupported pixel format: %s\n",
14293                                   drm_get_format_name(mode_cmd->pixel_format));
14294                         return -EINVAL;
14295                 }
14296                 break;
14297         case DRM_FORMAT_XBGR8888:
14298         case DRM_FORMAT_XRGB2101010:
14299         case DRM_FORMAT_XBGR2101010:
14300                 if (INTEL_INFO(dev)->gen < 4) {
14301                         DRM_DEBUG("unsupported pixel format: %s\n",
14302                                   drm_get_format_name(mode_cmd->pixel_format));
14303                         return -EINVAL;
14304                 }
14305                 break;
14306         case DRM_FORMAT_ABGR2101010:
14307                 if (!IS_VALLEYVIEW(dev)) {
14308                         DRM_DEBUG("unsupported pixel format: %s\n",
14309                                   drm_get_format_name(mode_cmd->pixel_format));
14310                         return -EINVAL;
14311                 }
14312                 break;
14313         case DRM_FORMAT_YUYV:
14314         case DRM_FORMAT_UYVY:
14315         case DRM_FORMAT_YVYU:
14316         case DRM_FORMAT_VYUY:
14317                 if (INTEL_INFO(dev)->gen < 5) {
14318                         DRM_DEBUG("unsupported pixel format: %s\n",
14319                                   drm_get_format_name(mode_cmd->pixel_format));
14320                         return -EINVAL;
14321                 }
14322                 break;
14323         default:
14324                 DRM_DEBUG("unsupported pixel format: %s\n",
14325                           drm_get_format_name(mode_cmd->pixel_format));
14326                 return -EINVAL;
14327         }
14328
14329         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14330         if (mode_cmd->offsets[0] != 0)
14331                 return -EINVAL;
14332
14333         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14334                                                mode_cmd->pixel_format,
14335                                                mode_cmd->modifier[0]);
14336         /* FIXME drm helper for size checks (especially planar formats)? */
14337         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14338                 return -EINVAL;
14339
14340         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14341         intel_fb->obj = obj;
14342         intel_fb->obj->framebuffer_references++;
14343
14344         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14345         if (ret) {
14346                 DRM_ERROR("framebuffer init failed %d\n", ret);
14347                 return ret;
14348         }
14349
14350         return 0;
14351 }
14352
14353 static struct drm_framebuffer *
14354 intel_user_framebuffer_create(struct drm_device *dev,
14355                               struct drm_file *filp,
14356                               struct drm_mode_fb_cmd2 *mode_cmd)
14357 {
14358         struct drm_i915_gem_object *obj;
14359
14360         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14361                                                 mode_cmd->handles[0]));
14362         if (&obj->base == NULL)
14363                 return ERR_PTR(-ENOENT);
14364
14365         return intel_framebuffer_create(dev, mode_cmd, obj);
14366 }
14367
14368 #ifndef CONFIG_DRM_FBDEV_EMULATION
14369 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14370 {
14371 }
14372 #endif
14373
14374 static const struct drm_mode_config_funcs intel_mode_funcs = {
14375         .fb_create = intel_user_framebuffer_create,
14376         .output_poll_changed = intel_fbdev_output_poll_changed,
14377         .atomic_check = intel_atomic_check,
14378         .atomic_commit = intel_atomic_commit,
14379         .atomic_state_alloc = intel_atomic_state_alloc,
14380         .atomic_state_clear = intel_atomic_state_clear,
14381 };
14382
14383 /* Set up chip specific display functions */
14384 static void intel_init_display(struct drm_device *dev)
14385 {
14386         struct drm_i915_private *dev_priv = dev->dev_private;
14387
14388         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14389                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14390         else if (IS_CHERRYVIEW(dev))
14391                 dev_priv->display.find_dpll = chv_find_best_dpll;
14392         else if (IS_VALLEYVIEW(dev))
14393                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14394         else if (IS_PINEVIEW(dev))
14395                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14396         else
14397                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14398
14399         if (INTEL_INFO(dev)->gen >= 9) {
14400                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14401                 dev_priv->display.get_initial_plane_config =
14402                         skylake_get_initial_plane_config;
14403                 dev_priv->display.crtc_compute_clock =
14404                         haswell_crtc_compute_clock;
14405                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14406                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14407                 dev_priv->display.update_primary_plane =
14408                         skylake_update_primary_plane;
14409         } else if (HAS_DDI(dev)) {
14410                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14411                 dev_priv->display.get_initial_plane_config =
14412                         ironlake_get_initial_plane_config;
14413                 dev_priv->display.crtc_compute_clock =
14414                         haswell_crtc_compute_clock;
14415                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14416                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14417                 dev_priv->display.update_primary_plane =
14418                         ironlake_update_primary_plane;
14419         } else if (HAS_PCH_SPLIT(dev)) {
14420                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14421                 dev_priv->display.get_initial_plane_config =
14422                         ironlake_get_initial_plane_config;
14423                 dev_priv->display.crtc_compute_clock =
14424                         ironlake_crtc_compute_clock;
14425                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14426                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14427                 dev_priv->display.update_primary_plane =
14428                         ironlake_update_primary_plane;
14429         } else if (IS_VALLEYVIEW(dev)) {
14430                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14431                 dev_priv->display.get_initial_plane_config =
14432                         i9xx_get_initial_plane_config;
14433                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14434                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14435                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14436                 dev_priv->display.update_primary_plane =
14437                         i9xx_update_primary_plane;
14438         } else {
14439                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14440                 dev_priv->display.get_initial_plane_config =
14441                         i9xx_get_initial_plane_config;
14442                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14443                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14444                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14445                 dev_priv->display.update_primary_plane =
14446                         i9xx_update_primary_plane;
14447         }
14448
14449         /* Returns the core display clock speed */
14450         if (IS_SKYLAKE(dev))
14451                 dev_priv->display.get_display_clock_speed =
14452                         skylake_get_display_clock_speed;
14453         else if (IS_BROXTON(dev))
14454                 dev_priv->display.get_display_clock_speed =
14455                         broxton_get_display_clock_speed;
14456         else if (IS_BROADWELL(dev))
14457                 dev_priv->display.get_display_clock_speed =
14458                         broadwell_get_display_clock_speed;
14459         else if (IS_HASWELL(dev))
14460                 dev_priv->display.get_display_clock_speed =
14461                         haswell_get_display_clock_speed;
14462         else if (IS_VALLEYVIEW(dev))
14463                 dev_priv->display.get_display_clock_speed =
14464                         valleyview_get_display_clock_speed;
14465         else if (IS_GEN5(dev))
14466                 dev_priv->display.get_display_clock_speed =
14467                         ilk_get_display_clock_speed;
14468         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14469                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14470                 dev_priv->display.get_display_clock_speed =
14471                         i945_get_display_clock_speed;
14472         else if (IS_GM45(dev))
14473                 dev_priv->display.get_display_clock_speed =
14474                         gm45_get_display_clock_speed;
14475         else if (IS_CRESTLINE(dev))
14476                 dev_priv->display.get_display_clock_speed =
14477                         i965gm_get_display_clock_speed;
14478         else if (IS_PINEVIEW(dev))
14479                 dev_priv->display.get_display_clock_speed =
14480                         pnv_get_display_clock_speed;
14481         else if (IS_G33(dev) || IS_G4X(dev))
14482                 dev_priv->display.get_display_clock_speed =
14483                         g33_get_display_clock_speed;
14484         else if (IS_I915G(dev))
14485                 dev_priv->display.get_display_clock_speed =
14486                         i915_get_display_clock_speed;
14487         else if (IS_I945GM(dev) || IS_845G(dev))
14488                 dev_priv->display.get_display_clock_speed =
14489                         i9xx_misc_get_display_clock_speed;
14490         else if (IS_PINEVIEW(dev))
14491                 dev_priv->display.get_display_clock_speed =
14492                         pnv_get_display_clock_speed;
14493         else if (IS_I915GM(dev))
14494                 dev_priv->display.get_display_clock_speed =
14495                         i915gm_get_display_clock_speed;
14496         else if (IS_I865G(dev))
14497                 dev_priv->display.get_display_clock_speed =
14498                         i865_get_display_clock_speed;
14499         else if (IS_I85X(dev))
14500                 dev_priv->display.get_display_clock_speed =
14501                         i85x_get_display_clock_speed;
14502         else { /* 830 */
14503                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14504                 dev_priv->display.get_display_clock_speed =
14505                         i830_get_display_clock_speed;
14506         }
14507
14508         if (IS_GEN5(dev)) {
14509                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14510         } else if (IS_GEN6(dev)) {
14511                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14512         } else if (IS_IVYBRIDGE(dev)) {
14513                 /* FIXME: detect B0+ stepping and use auto training */
14514                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14515         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14516                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14517                 if (IS_BROADWELL(dev)) {
14518                         dev_priv->display.modeset_commit_cdclk =
14519                                 broadwell_modeset_commit_cdclk;
14520                         dev_priv->display.modeset_calc_cdclk =
14521                                 broadwell_modeset_calc_cdclk;
14522                 }
14523         } else if (IS_VALLEYVIEW(dev)) {
14524                 dev_priv->display.modeset_commit_cdclk =
14525                         valleyview_modeset_commit_cdclk;
14526                 dev_priv->display.modeset_calc_cdclk =
14527                         valleyview_modeset_calc_cdclk;
14528         } else if (IS_BROXTON(dev)) {
14529                 dev_priv->display.modeset_commit_cdclk =
14530                         broxton_modeset_commit_cdclk;
14531                 dev_priv->display.modeset_calc_cdclk =
14532                         broxton_modeset_calc_cdclk;
14533         }
14534
14535         switch (INTEL_INFO(dev)->gen) {
14536         case 2:
14537                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14538                 break;
14539
14540         case 3:
14541                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14542                 break;
14543
14544         case 4:
14545         case 5:
14546                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14547                 break;
14548
14549         case 6:
14550                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14551                 break;
14552         case 7:
14553         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14554                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14555                 break;
14556         case 9:
14557                 /* Drop through - unsupported since execlist only. */
14558         default:
14559                 /* Default just returns -ENODEV to indicate unsupported */
14560                 dev_priv->display.queue_flip = intel_default_queue_flip;
14561         }
14562
14563         intel_panel_init_backlight_funcs(dev);
14564
14565         mutex_init(&dev_priv->pps_mutex);
14566 }
14567
14568 /*
14569  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14570  * resume, or other times.  This quirk makes sure that's the case for
14571  * affected systems.
14572  */
14573 static void quirk_pipea_force(struct drm_device *dev)
14574 {
14575         struct drm_i915_private *dev_priv = dev->dev_private;
14576
14577         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14578         DRM_INFO("applying pipe a force quirk\n");
14579 }
14580
14581 static void quirk_pipeb_force(struct drm_device *dev)
14582 {
14583         struct drm_i915_private *dev_priv = dev->dev_private;
14584
14585         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14586         DRM_INFO("applying pipe b force quirk\n");
14587 }
14588
14589 /*
14590  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14591  */
14592 static void quirk_ssc_force_disable(struct drm_device *dev)
14593 {
14594         struct drm_i915_private *dev_priv = dev->dev_private;
14595         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14596         DRM_INFO("applying lvds SSC disable quirk\n");
14597 }
14598
14599 /*
14600  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14601  * brightness value
14602  */
14603 static void quirk_invert_brightness(struct drm_device *dev)
14604 {
14605         struct drm_i915_private *dev_priv = dev->dev_private;
14606         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14607         DRM_INFO("applying inverted panel brightness quirk\n");
14608 }
14609
14610 /* Some VBT's incorrectly indicate no backlight is present */
14611 static void quirk_backlight_present(struct drm_device *dev)
14612 {
14613         struct drm_i915_private *dev_priv = dev->dev_private;
14614         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14615         DRM_INFO("applying backlight present quirk\n");
14616 }
14617
14618 struct intel_quirk {
14619         int device;
14620         int subsystem_vendor;
14621         int subsystem_device;
14622         void (*hook)(struct drm_device *dev);
14623 };
14624
14625 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14626 struct intel_dmi_quirk {
14627         void (*hook)(struct drm_device *dev);
14628         const struct dmi_system_id (*dmi_id_list)[];
14629 };
14630
14631 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14632 {
14633         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14634         return 1;
14635 }
14636
14637 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14638         {
14639                 .dmi_id_list = &(const struct dmi_system_id[]) {
14640                         {
14641                                 .callback = intel_dmi_reverse_brightness,
14642                                 .ident = "NCR Corporation",
14643                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14644                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14645                                 },
14646                         },
14647                         { }  /* terminating entry */
14648                 },
14649                 .hook = quirk_invert_brightness,
14650         },
14651 };
14652
14653 static struct intel_quirk intel_quirks[] = {
14654         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14655         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14656
14657         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14658         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14659
14660         /* 830 needs to leave pipe A & dpll A up */
14661         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14662
14663         /* 830 needs to leave pipe B & dpll B up */
14664         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14665
14666         /* Lenovo U160 cannot use SSC on LVDS */
14667         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14668
14669         /* Sony Vaio Y cannot use SSC on LVDS */
14670         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14671
14672         /* Acer Aspire 5734Z must invert backlight brightness */
14673         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14674
14675         /* Acer/eMachines G725 */
14676         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14677
14678         /* Acer/eMachines e725 */
14679         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14680
14681         /* Acer/Packard Bell NCL20 */
14682         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14683
14684         /* Acer Aspire 4736Z */
14685         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14686
14687         /* Acer Aspire 5336 */
14688         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14689
14690         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14691         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14692
14693         /* Acer C720 Chromebook (Core i3 4005U) */
14694         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14695
14696         /* Apple Macbook 2,1 (Core 2 T7400) */
14697         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14698
14699         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14700         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14701
14702         /* HP Chromebook 14 (Celeron 2955U) */
14703         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14704
14705         /* Dell Chromebook 11 */
14706         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14707 };
14708
14709 static void intel_init_quirks(struct drm_device *dev)
14710 {
14711         struct pci_dev *d = dev->pdev;
14712         int i;
14713
14714         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14715                 struct intel_quirk *q = &intel_quirks[i];
14716
14717                 if (d->device == q->device &&
14718                     (d->subsystem_vendor == q->subsystem_vendor ||
14719                      q->subsystem_vendor == PCI_ANY_ID) &&
14720                     (d->subsystem_device == q->subsystem_device ||
14721                      q->subsystem_device == PCI_ANY_ID))
14722                         q->hook(dev);
14723         }
14724         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14725                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14726                         intel_dmi_quirks[i].hook(dev);
14727         }
14728 }
14729
14730 /* Disable the VGA plane that we never use */
14731 static void i915_disable_vga(struct drm_device *dev)
14732 {
14733         struct drm_i915_private *dev_priv = dev->dev_private;
14734         u8 sr1;
14735         u32 vga_reg = i915_vgacntrl_reg(dev);
14736
14737         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14738         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14739         outb(SR01, VGA_SR_INDEX);
14740         sr1 = inb(VGA_SR_DATA);
14741         outb(sr1 | 1<<5, VGA_SR_DATA);
14742         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14743         udelay(300);
14744
14745         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14746         POSTING_READ(vga_reg);
14747 }
14748
14749 void intel_modeset_init_hw(struct drm_device *dev)
14750 {
14751         intel_update_cdclk(dev);
14752         intel_prepare_ddi(dev);
14753         intel_init_clock_gating(dev);
14754         intel_enable_gt_powersave(dev);
14755 }
14756
14757 void intel_modeset_init(struct drm_device *dev)
14758 {
14759         struct drm_i915_private *dev_priv = dev->dev_private;
14760         int sprite, ret;
14761         enum pipe pipe;
14762         struct intel_crtc *crtc;
14763
14764         drm_mode_config_init(dev);
14765
14766         dev->mode_config.min_width = 0;
14767         dev->mode_config.min_height = 0;
14768
14769         dev->mode_config.preferred_depth = 24;
14770         dev->mode_config.prefer_shadow = 1;
14771
14772         dev->mode_config.allow_fb_modifiers = true;
14773
14774         dev->mode_config.funcs = &intel_mode_funcs;
14775
14776         intel_init_quirks(dev);
14777
14778         intel_init_pm(dev);
14779
14780         if (INTEL_INFO(dev)->num_pipes == 0)
14781                 return;
14782
14783         /*
14784          * There may be no VBT; and if the BIOS enabled SSC we can
14785          * just keep using it to avoid unnecessary flicker.  Whereas if the
14786          * BIOS isn't using it, don't assume it will work even if the VBT
14787          * indicates as much.
14788          */
14789         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14790                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14791                                             DREF_SSC1_ENABLE);
14792
14793                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14794                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14795                                      bios_lvds_use_ssc ? "en" : "dis",
14796                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14797                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14798                 }
14799         }
14800
14801         intel_init_display(dev);
14802         intel_init_audio(dev);
14803
14804         if (IS_GEN2(dev)) {
14805                 dev->mode_config.max_width = 2048;
14806                 dev->mode_config.max_height = 2048;
14807         } else if (IS_GEN3(dev)) {
14808                 dev->mode_config.max_width = 4096;
14809                 dev->mode_config.max_height = 4096;
14810         } else {
14811                 dev->mode_config.max_width = 8192;
14812                 dev->mode_config.max_height = 8192;
14813         }
14814
14815         if (IS_845G(dev) || IS_I865G(dev)) {
14816                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14817                 dev->mode_config.cursor_height = 1023;
14818         } else if (IS_GEN2(dev)) {
14819                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14820                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14821         } else {
14822                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14823                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14824         }
14825
14826         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14827
14828         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14829                       INTEL_INFO(dev)->num_pipes,
14830                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14831
14832         for_each_pipe(dev_priv, pipe) {
14833                 intel_crtc_init(dev, pipe);
14834                 for_each_sprite(dev_priv, pipe, sprite) {
14835                         ret = intel_plane_init(dev, pipe, sprite);
14836                         if (ret)
14837                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14838                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14839                 }
14840         }
14841
14842         intel_shared_dpll_init(dev);
14843
14844         /* Just disable it once at startup */
14845         i915_disable_vga(dev);
14846         intel_setup_outputs(dev);
14847
14848         /* Just in case the BIOS is doing something questionable. */
14849         intel_fbc_disable(dev_priv);
14850
14851         drm_modeset_lock_all(dev);
14852         intel_modeset_setup_hw_state(dev);
14853         drm_modeset_unlock_all(dev);
14854
14855         for_each_intel_crtc(dev, crtc) {
14856                 struct intel_initial_plane_config plane_config = {};
14857
14858                 if (!crtc->active)
14859                         continue;
14860
14861                 /*
14862                  * Note that reserving the BIOS fb up front prevents us
14863                  * from stuffing other stolen allocations like the ring
14864                  * on top.  This prevents some ugliness at boot time, and
14865                  * can even allow for smooth boot transitions if the BIOS
14866                  * fb is large enough for the active pipe configuration.
14867                  */
14868                 dev_priv->display.get_initial_plane_config(crtc,
14869                                                            &plane_config);
14870
14871                 /*
14872                  * If the fb is shared between multiple heads, we'll
14873                  * just get the first one.
14874                  */
14875                 intel_find_initial_plane_obj(crtc, &plane_config);
14876         }
14877 }
14878
14879 static void intel_enable_pipe_a(struct drm_device *dev)
14880 {
14881         struct intel_connector *connector;
14882         struct drm_connector *crt = NULL;
14883         struct intel_load_detect_pipe load_detect_temp;
14884         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14885
14886         /* We can't just switch on the pipe A, we need to set things up with a
14887          * proper mode and output configuration. As a gross hack, enable pipe A
14888          * by enabling the load detect pipe once. */
14889         for_each_intel_connector(dev, connector) {
14890                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14891                         crt = &connector->base;
14892                         break;
14893                 }
14894         }
14895
14896         if (!crt)
14897                 return;
14898
14899         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14900                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14901 }
14902
14903 static bool
14904 intel_check_plane_mapping(struct intel_crtc *crtc)
14905 {
14906         struct drm_device *dev = crtc->base.dev;
14907         struct drm_i915_private *dev_priv = dev->dev_private;
14908         u32 reg, val;
14909
14910         if (INTEL_INFO(dev)->num_pipes == 1)
14911                 return true;
14912
14913         reg = DSPCNTR(!crtc->plane);
14914         val = I915_READ(reg);
14915
14916         if ((val & DISPLAY_PLANE_ENABLE) &&
14917             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14918                 return false;
14919
14920         return true;
14921 }
14922
14923 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14924 {
14925         struct drm_device *dev = crtc->base.dev;
14926         struct intel_encoder *encoder;
14927
14928         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14929                 return true;
14930
14931         return false;
14932 }
14933
14934 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14935 {
14936         struct drm_device *dev = crtc->base.dev;
14937         struct drm_i915_private *dev_priv = dev->dev_private;
14938         u32 reg;
14939
14940         /* Clear any frame start delays used for debugging left by the BIOS */
14941         reg = PIPECONF(crtc->config->cpu_transcoder);
14942         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14943
14944         /* restore vblank interrupts to correct state */
14945         drm_crtc_vblank_reset(&crtc->base);
14946         if (crtc->active) {
14947                 struct intel_plane *plane;
14948
14949                 drm_crtc_vblank_on(&crtc->base);
14950
14951                 /* Disable everything but the primary plane */
14952                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14953                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14954                                 continue;
14955
14956                         plane->disable_plane(&plane->base, &crtc->base);
14957                 }
14958         }
14959
14960         /* We need to sanitize the plane -> pipe mapping first because this will
14961          * disable the crtc (and hence change the state) if it is wrong. Note
14962          * that gen4+ has a fixed plane -> pipe mapping.  */
14963         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14964                 bool plane;
14965
14966                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14967                               crtc->base.base.id);
14968
14969                 /* Pipe has the wrong plane attached and the plane is active.
14970                  * Temporarily change the plane mapping and disable everything
14971                  * ...  */
14972                 plane = crtc->plane;
14973                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14974                 crtc->plane = !plane;
14975                 intel_crtc_disable_noatomic(&crtc->base);
14976                 crtc->plane = plane;
14977         }
14978
14979         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14980             crtc->pipe == PIPE_A && !crtc->active) {
14981                 /* BIOS forgot to enable pipe A, this mostly happens after
14982                  * resume. Force-enable the pipe to fix this, the update_dpms
14983                  * call below we restore the pipe to the right state, but leave
14984                  * the required bits on. */
14985                 intel_enable_pipe_a(dev);
14986         }
14987
14988         /* Adjust the state of the output pipe according to whether we
14989          * have active connectors/encoders. */
14990         if (!intel_crtc_has_encoders(crtc))
14991                 intel_crtc_disable_noatomic(&crtc->base);
14992
14993         if (crtc->active != crtc->base.state->active) {
14994                 struct intel_encoder *encoder;
14995
14996                 /* This can happen either due to bugs in the get_hw_state
14997                  * functions or because of calls to intel_crtc_disable_noatomic,
14998                  * or because the pipe is force-enabled due to the
14999                  * pipe A quirk. */
15000                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15001                               crtc->base.base.id,
15002                               crtc->base.state->enable ? "enabled" : "disabled",
15003                               crtc->active ? "enabled" : "disabled");
15004
15005                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15006                 crtc->base.state->active = crtc->active;
15007                 crtc->base.enabled = crtc->active;
15008
15009                 /* Because we only establish the connector -> encoder ->
15010                  * crtc links if something is active, this means the
15011                  * crtc is now deactivated. Break the links. connector
15012                  * -> encoder links are only establish when things are
15013                  *  actually up, hence no need to break them. */
15014                 WARN_ON(crtc->active);
15015
15016                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15017                         encoder->base.crtc = NULL;
15018         }
15019
15020         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15021                 /*
15022                  * We start out with underrun reporting disabled to avoid races.
15023                  * For correct bookkeeping mark this on active crtcs.
15024                  *
15025                  * Also on gmch platforms we dont have any hardware bits to
15026                  * disable the underrun reporting. Which means we need to start
15027                  * out with underrun reporting disabled also on inactive pipes,
15028                  * since otherwise we'll complain about the garbage we read when
15029                  * e.g. coming up after runtime pm.
15030                  *
15031                  * No protection against concurrent access is required - at
15032                  * worst a fifo underrun happens which also sets this to false.
15033                  */
15034                 crtc->cpu_fifo_underrun_disabled = true;
15035                 crtc->pch_fifo_underrun_disabled = true;
15036         }
15037 }
15038
15039 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15040 {
15041         struct intel_connector *connector;
15042         struct drm_device *dev = encoder->base.dev;
15043         bool active = false;
15044
15045         /* We need to check both for a crtc link (meaning that the
15046          * encoder is active and trying to read from a pipe) and the
15047          * pipe itself being active. */
15048         bool has_active_crtc = encoder->base.crtc &&
15049                 to_intel_crtc(encoder->base.crtc)->active;
15050
15051         for_each_intel_connector(dev, connector) {
15052                 if (connector->base.encoder != &encoder->base)
15053                         continue;
15054
15055                 active = true;
15056                 break;
15057         }
15058
15059         if (active && !has_active_crtc) {
15060                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15061                               encoder->base.base.id,
15062                               encoder->base.name);
15063
15064                 /* Connector is active, but has no active pipe. This is
15065                  * fallout from our resume register restoring. Disable
15066                  * the encoder manually again. */
15067                 if (encoder->base.crtc) {
15068                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15069                                       encoder->base.base.id,
15070                                       encoder->base.name);
15071                         encoder->disable(encoder);
15072                         if (encoder->post_disable)
15073                                 encoder->post_disable(encoder);
15074                 }
15075                 encoder->base.crtc = NULL;
15076
15077                 /* Inconsistent output/port/pipe state happens presumably due to
15078                  * a bug in one of the get_hw_state functions. Or someplace else
15079                  * in our code, like the register restore mess on resume. Clamp
15080                  * things to off as a safer default. */
15081                 for_each_intel_connector(dev, connector) {
15082                         if (connector->encoder != encoder)
15083                                 continue;
15084                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15085                         connector->base.encoder = NULL;
15086                 }
15087         }
15088         /* Enabled encoders without active connectors will be fixed in
15089          * the crtc fixup. */
15090 }
15091
15092 void i915_redisable_vga_power_on(struct drm_device *dev)
15093 {
15094         struct drm_i915_private *dev_priv = dev->dev_private;
15095         u32 vga_reg = i915_vgacntrl_reg(dev);
15096
15097         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15098                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15099                 i915_disable_vga(dev);
15100         }
15101 }
15102
15103 void i915_redisable_vga(struct drm_device *dev)
15104 {
15105         struct drm_i915_private *dev_priv = dev->dev_private;
15106
15107         /* This function can be called both from intel_modeset_setup_hw_state or
15108          * at a very early point in our resume sequence, where the power well
15109          * structures are not yet restored. Since this function is at a very
15110          * paranoid "someone might have enabled VGA while we were not looking"
15111          * level, just check if the power well is enabled instead of trying to
15112          * follow the "don't touch the power well if we don't need it" policy
15113          * the rest of the driver uses. */
15114         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15115                 return;
15116
15117         i915_redisable_vga_power_on(dev);
15118 }
15119
15120 static bool primary_get_hw_state(struct intel_plane *plane)
15121 {
15122         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15123
15124         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15125 }
15126
15127 /* FIXME read out full plane state for all planes */
15128 static void readout_plane_state(struct intel_crtc *crtc)
15129 {
15130         struct drm_plane *primary = crtc->base.primary;
15131         struct intel_plane_state *plane_state =
15132                 to_intel_plane_state(primary->state);
15133
15134         plane_state->visible =
15135                 primary_get_hw_state(to_intel_plane(primary));
15136
15137         if (plane_state->visible)
15138                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15139 }
15140
15141 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15142 {
15143         struct drm_i915_private *dev_priv = dev->dev_private;
15144         enum pipe pipe;
15145         struct intel_crtc *crtc;
15146         struct intel_encoder *encoder;
15147         struct intel_connector *connector;
15148         int i;
15149
15150         for_each_intel_crtc(dev, crtc) {
15151                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15152                 memset(crtc->config, 0, sizeof(*crtc->config));
15153                 crtc->config->base.crtc = &crtc->base;
15154
15155                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15156                                                                  crtc->config);
15157
15158                 crtc->base.state->active = crtc->active;
15159                 crtc->base.enabled = crtc->active;
15160
15161                 readout_plane_state(crtc);
15162
15163                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15164                               crtc->base.base.id,
15165                               crtc->active ? "enabled" : "disabled");
15166         }
15167
15168         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15169                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15170
15171                 pll->on = pll->get_hw_state(dev_priv, pll,
15172                                             &pll->config.hw_state);
15173                 pll->active = 0;
15174                 pll->config.crtc_mask = 0;
15175                 for_each_intel_crtc(dev, crtc) {
15176                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15177                                 pll->active++;
15178                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15179                         }
15180                 }
15181
15182                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15183                               pll->name, pll->config.crtc_mask, pll->on);
15184
15185                 if (pll->config.crtc_mask)
15186                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15187         }
15188
15189         for_each_intel_encoder(dev, encoder) {
15190                 pipe = 0;
15191
15192                 if (encoder->get_hw_state(encoder, &pipe)) {
15193                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15194                         encoder->base.crtc = &crtc->base;
15195                         encoder->get_config(encoder, crtc->config);
15196                 } else {
15197                         encoder->base.crtc = NULL;
15198                 }
15199
15200                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15201                               encoder->base.base.id,
15202                               encoder->base.name,
15203                               encoder->base.crtc ? "enabled" : "disabled",
15204                               pipe_name(pipe));
15205         }
15206
15207         for_each_intel_connector(dev, connector) {
15208                 if (connector->get_hw_state(connector)) {
15209                         connector->base.dpms = DRM_MODE_DPMS_ON;
15210                         connector->base.encoder = &connector->encoder->base;
15211                 } else {
15212                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15213                         connector->base.encoder = NULL;
15214                 }
15215                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15216                               connector->base.base.id,
15217                               connector->base.name,
15218                               connector->base.encoder ? "enabled" : "disabled");
15219         }
15220
15221         for_each_intel_crtc(dev, crtc) {
15222                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15223
15224                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15225                 if (crtc->base.state->active) {
15226                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15227                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15228                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15229
15230                         /*
15231                          * The initial mode needs to be set in order to keep
15232                          * the atomic core happy. It wants a valid mode if the
15233                          * crtc's enabled, so we do the above call.
15234                          *
15235                          * At this point some state updated by the connectors
15236                          * in their ->detect() callback has not run yet, so
15237                          * no recalculation can be done yet.
15238                          *
15239                          * Even if we could do a recalculation and modeset
15240                          * right now it would cause a double modeset if
15241                          * fbdev or userspace chooses a different initial mode.
15242                          *
15243                          * If that happens, someone indicated they wanted a
15244                          * mode change, which means it's safe to do a full
15245                          * recalculation.
15246                          */
15247                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15248
15249                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15250                         update_scanline_offset(crtc);
15251                 }
15252         }
15253 }
15254
15255 /* Scan out the current hw modeset state,
15256  * and sanitizes it to the current state
15257  */
15258 static void
15259 intel_modeset_setup_hw_state(struct drm_device *dev)
15260 {
15261         struct drm_i915_private *dev_priv = dev->dev_private;
15262         enum pipe pipe;
15263         struct intel_crtc *crtc;
15264         struct intel_encoder *encoder;
15265         int i;
15266
15267         intel_modeset_readout_hw_state(dev);
15268
15269         /* HW state is read out, now we need to sanitize this mess. */
15270         for_each_intel_encoder(dev, encoder) {
15271                 intel_sanitize_encoder(encoder);
15272         }
15273
15274         for_each_pipe(dev_priv, pipe) {
15275                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15276                 intel_sanitize_crtc(crtc);
15277                 intel_dump_pipe_config(crtc, crtc->config,
15278                                        "[setup_hw_state]");
15279         }
15280
15281         intel_modeset_update_connector_atomic_state(dev);
15282
15283         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15284                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15285
15286                 if (!pll->on || pll->active)
15287                         continue;
15288
15289                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15290
15291                 pll->disable(dev_priv, pll);
15292                 pll->on = false;
15293         }
15294
15295         if (IS_VALLEYVIEW(dev))
15296                 vlv_wm_get_hw_state(dev);
15297         else if (IS_GEN9(dev))
15298                 skl_wm_get_hw_state(dev);
15299         else if (HAS_PCH_SPLIT(dev))
15300                 ilk_wm_get_hw_state(dev);
15301
15302         for_each_intel_crtc(dev, crtc) {
15303                 unsigned long put_domains;
15304
15305                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15306                 if (WARN_ON(put_domains))
15307                         modeset_put_power_domains(dev_priv, put_domains);
15308         }
15309         intel_display_set_init_power(dev_priv, false);
15310 }
15311
15312 void intel_display_resume(struct drm_device *dev)
15313 {
15314         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15315         struct intel_connector *conn;
15316         struct intel_plane *plane;
15317         struct drm_crtc *crtc;
15318         int ret;
15319
15320         if (!state)
15321                 return;
15322
15323         state->acquire_ctx = dev->mode_config.acquire_ctx;
15324
15325         /* preserve complete old state, including dpll */
15326         intel_atomic_get_shared_dpll_state(state);
15327
15328         for_each_crtc(dev, crtc) {
15329                 struct drm_crtc_state *crtc_state =
15330                         drm_atomic_get_crtc_state(state, crtc);
15331
15332                 ret = PTR_ERR_OR_ZERO(crtc_state);
15333                 if (ret)
15334                         goto err;
15335
15336                 /* force a restore */
15337                 crtc_state->mode_changed = true;
15338         }
15339
15340         for_each_intel_plane(dev, plane) {
15341                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15342                 if (ret)
15343                         goto err;
15344         }
15345
15346         for_each_intel_connector(dev, conn) {
15347                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15348                 if (ret)
15349                         goto err;
15350         }
15351
15352         intel_modeset_setup_hw_state(dev);
15353
15354         i915_redisable_vga(dev);
15355         ret = drm_atomic_commit(state);
15356         if (!ret)
15357                 return;
15358
15359 err:
15360         DRM_ERROR("Restoring old state failed with %i\n", ret);
15361         drm_atomic_state_free(state);
15362 }
15363
15364 void intel_modeset_gem_init(struct drm_device *dev)
15365 {
15366         struct drm_crtc *c;
15367         struct drm_i915_gem_object *obj;
15368         int ret;
15369
15370         mutex_lock(&dev->struct_mutex);
15371         intel_init_gt_powersave(dev);
15372         mutex_unlock(&dev->struct_mutex);
15373
15374         intel_modeset_init_hw(dev);
15375
15376         intel_setup_overlay(dev);
15377
15378         /*
15379          * Make sure any fbs we allocated at startup are properly
15380          * pinned & fenced.  When we do the allocation it's too early
15381          * for this.
15382          */
15383         for_each_crtc(dev, c) {
15384                 obj = intel_fb_obj(c->primary->fb);
15385                 if (obj == NULL)
15386                         continue;
15387
15388                 mutex_lock(&dev->struct_mutex);
15389                 ret = intel_pin_and_fence_fb_obj(c->primary,
15390                                                  c->primary->fb,
15391                                                  c->primary->state,
15392                                                  NULL, NULL);
15393                 mutex_unlock(&dev->struct_mutex);
15394                 if (ret) {
15395                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15396                                   to_intel_crtc(c)->pipe);
15397                         drm_framebuffer_unreference(c->primary->fb);
15398                         c->primary->fb = NULL;
15399                         c->primary->crtc = c->primary->state->crtc = NULL;
15400                         update_state_fb(c->primary);
15401                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15402                 }
15403         }
15404
15405         intel_backlight_register(dev);
15406 }
15407
15408 void intel_connector_unregister(struct intel_connector *intel_connector)
15409 {
15410         struct drm_connector *connector = &intel_connector->base;
15411
15412         intel_panel_destroy_backlight(connector);
15413         drm_connector_unregister(connector);
15414 }
15415
15416 void intel_modeset_cleanup(struct drm_device *dev)
15417 {
15418         struct drm_i915_private *dev_priv = dev->dev_private;
15419         struct drm_connector *connector;
15420
15421         intel_disable_gt_powersave(dev);
15422
15423         intel_backlight_unregister(dev);
15424
15425         /*
15426          * Interrupts and polling as the first thing to avoid creating havoc.
15427          * Too much stuff here (turning of connectors, ...) would
15428          * experience fancy races otherwise.
15429          */
15430         intel_irq_uninstall(dev_priv);
15431
15432         /*
15433          * Due to the hpd irq storm handling the hotplug work can re-arm the
15434          * poll handlers. Hence disable polling after hpd handling is shut down.
15435          */
15436         drm_kms_helper_poll_fini(dev);
15437
15438         intel_unregister_dsm_handler();
15439
15440         intel_fbc_disable(dev_priv);
15441
15442         /* flush any delayed tasks or pending work */
15443         flush_scheduled_work();
15444
15445         /* destroy the backlight and sysfs files before encoders/connectors */
15446         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15447                 struct intel_connector *intel_connector;
15448
15449                 intel_connector = to_intel_connector(connector);
15450                 intel_connector->unregister(intel_connector);
15451         }
15452
15453         drm_mode_config_cleanup(dev);
15454
15455         intel_cleanup_overlay(dev);
15456
15457         mutex_lock(&dev->struct_mutex);
15458         intel_cleanup_gt_powersave(dev);
15459         mutex_unlock(&dev->struct_mutex);
15460 }
15461
15462 /*
15463  * Return which encoder is currently attached for connector.
15464  */
15465 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15466 {
15467         return &intel_attached_encoder(connector)->base;
15468 }
15469
15470 void intel_connector_attach_encoder(struct intel_connector *connector,
15471                                     struct intel_encoder *encoder)
15472 {
15473         connector->encoder = encoder;
15474         drm_mode_connector_attach_encoder(&connector->base,
15475                                           &encoder->base);
15476 }
15477
15478 /*
15479  * set vga decode state - true == enable VGA decode
15480  */
15481 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15482 {
15483         struct drm_i915_private *dev_priv = dev->dev_private;
15484         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15485         u16 gmch_ctrl;
15486
15487         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15488                 DRM_ERROR("failed to read control word\n");
15489                 return -EIO;
15490         }
15491
15492         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15493                 return 0;
15494
15495         if (state)
15496                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15497         else
15498                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15499
15500         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15501                 DRM_ERROR("failed to write control word\n");
15502                 return -EIO;
15503         }
15504
15505         return 0;
15506 }
15507
15508 struct intel_display_error_state {
15509
15510         u32 power_well_driver;
15511
15512         int num_transcoders;
15513
15514         struct intel_cursor_error_state {
15515                 u32 control;
15516                 u32 position;
15517                 u32 base;
15518                 u32 size;
15519         } cursor[I915_MAX_PIPES];
15520
15521         struct intel_pipe_error_state {
15522                 bool power_domain_on;
15523                 u32 source;
15524                 u32 stat;
15525         } pipe[I915_MAX_PIPES];
15526
15527         struct intel_plane_error_state {
15528                 u32 control;
15529                 u32 stride;
15530                 u32 size;
15531                 u32 pos;
15532                 u32 addr;
15533                 u32 surface;
15534                 u32 tile_offset;
15535         } plane[I915_MAX_PIPES];
15536
15537         struct intel_transcoder_error_state {
15538                 bool power_domain_on;
15539                 enum transcoder cpu_transcoder;
15540
15541                 u32 conf;
15542
15543                 u32 htotal;
15544                 u32 hblank;
15545                 u32 hsync;
15546                 u32 vtotal;
15547                 u32 vblank;
15548                 u32 vsync;
15549         } transcoder[4];
15550 };
15551
15552 struct intel_display_error_state *
15553 intel_display_capture_error_state(struct drm_device *dev)
15554 {
15555         struct drm_i915_private *dev_priv = dev->dev_private;
15556         struct intel_display_error_state *error;
15557         int transcoders[] = {
15558                 TRANSCODER_A,
15559                 TRANSCODER_B,
15560                 TRANSCODER_C,
15561                 TRANSCODER_EDP,
15562         };
15563         int i;
15564
15565         if (INTEL_INFO(dev)->num_pipes == 0)
15566                 return NULL;
15567
15568         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15569         if (error == NULL)
15570                 return NULL;
15571
15572         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15573                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15574
15575         for_each_pipe(dev_priv, i) {
15576                 error->pipe[i].power_domain_on =
15577                         __intel_display_power_is_enabled(dev_priv,
15578                                                          POWER_DOMAIN_PIPE(i));
15579                 if (!error->pipe[i].power_domain_on)
15580                         continue;
15581
15582                 error->cursor[i].control = I915_READ(CURCNTR(i));
15583                 error->cursor[i].position = I915_READ(CURPOS(i));
15584                 error->cursor[i].base = I915_READ(CURBASE(i));
15585
15586                 error->plane[i].control = I915_READ(DSPCNTR(i));
15587                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15588                 if (INTEL_INFO(dev)->gen <= 3) {
15589                         error->plane[i].size = I915_READ(DSPSIZE(i));
15590                         error->plane[i].pos = I915_READ(DSPPOS(i));
15591                 }
15592                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15593                         error->plane[i].addr = I915_READ(DSPADDR(i));
15594                 if (INTEL_INFO(dev)->gen >= 4) {
15595                         error->plane[i].surface = I915_READ(DSPSURF(i));
15596                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15597                 }
15598
15599                 error->pipe[i].source = I915_READ(PIPESRC(i));
15600
15601                 if (HAS_GMCH_DISPLAY(dev))
15602                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15603         }
15604
15605         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15606         if (HAS_DDI(dev_priv->dev))
15607                 error->num_transcoders++; /* Account for eDP. */
15608
15609         for (i = 0; i < error->num_transcoders; i++) {
15610                 enum transcoder cpu_transcoder = transcoders[i];
15611
15612                 error->transcoder[i].power_domain_on =
15613                         __intel_display_power_is_enabled(dev_priv,
15614                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15615                 if (!error->transcoder[i].power_domain_on)
15616                         continue;
15617
15618                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15619
15620                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15621                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15622                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15623                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15624                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15625                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15626                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15627         }
15628
15629         return error;
15630 }
15631
15632 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15633
15634 void
15635 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15636                                 struct drm_device *dev,
15637                                 struct intel_display_error_state *error)
15638 {
15639         struct drm_i915_private *dev_priv = dev->dev_private;
15640         int i;
15641
15642         if (!error)
15643                 return;
15644
15645         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15646         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15647                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15648                            error->power_well_driver);
15649         for_each_pipe(dev_priv, i) {
15650                 err_printf(m, "Pipe [%d]:\n", i);
15651                 err_printf(m, "  Power: %s\n",
15652                            error->pipe[i].power_domain_on ? "on" : "off");
15653                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15654                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15655
15656                 err_printf(m, "Plane [%d]:\n", i);
15657                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15658                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15659                 if (INTEL_INFO(dev)->gen <= 3) {
15660                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15661                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15662                 }
15663                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15664                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15665                 if (INTEL_INFO(dev)->gen >= 4) {
15666                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15667                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15668                 }
15669
15670                 err_printf(m, "Cursor [%d]:\n", i);
15671                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15672                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15673                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15674         }
15675
15676         for (i = 0; i < error->num_transcoders; i++) {
15677                 err_printf(m, "CPU transcoder: %c\n",
15678                            transcoder_name(error->transcoder[i].cpu_transcoder));
15679                 err_printf(m, "  Power: %s\n",
15680                            error->transcoder[i].power_domain_on ? "on" : "off");
15681                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15682                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15683                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15684                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15685                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15686                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15687                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15688         }
15689 }
15690
15691 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15692 {
15693         struct intel_crtc *crtc;
15694
15695         for_each_intel_crtc(dev, crtc) {
15696                 struct intel_unpin_work *work;
15697
15698                 spin_lock_irq(&dev->event_lock);
15699
15700                 work = crtc->unpin_work;
15701
15702                 if (work && work->event &&
15703                     work->event->base.file_priv == file) {
15704                         kfree(work->event);
15705                         work->event = NULL;
15706                 }
15707
15708                 spin_unlock_irq(&dev->event_lock);
15709         }
15710 }