drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats supported by all gen */
  49 #define COMMON_PRIMARY_FORMATS \
  50         DRM_FORMAT_C8, \
  51         DRM_FORMAT_RGB565, \
  52         DRM_FORMAT_XRGB8888, \
  53         DRM_FORMAT_ARGB8888
  54
  55 /* Primary plane formats for gen <= 3 */
  56 static const uint32_t intel_primary_formats_gen2[] = {
  57         COMMON_PRIMARY_FORMATS,
  58         DRM_FORMAT_XRGB1555,
  59         DRM_FORMAT_ARGB1555,
  60 };
  61
  62 /* Primary plane formats for gen >= 4 */
  63 static const uint32_t intel_primary_formats_gen4[] = {
  64         COMMON_PRIMARY_FORMATS, \
  65         DRM_FORMAT_XBGR8888,
  66         DRM_FORMAT_ABGR8888,
  67         DRM_FORMAT_XRGB2101010,
  68         DRM_FORMAT_ARGB2101010,
  69         DRM_FORMAT_XBGR2101010,
  70         DRM_FORMAT_ABGR2101010,
  71 };
  72
  73 /* Cursor formats */
  74 static const uint32_t intel_cursor_formats[] = {
  75         DRM_FORMAT_ARGB8888,
  76 };
  77
  78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  79
  80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  81                                 struct intel_crtc_state *pipe_config);
  82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  83                                    struct intel_crtc_state *pipe_config);
  84
  85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  86                           int x, int y, struct drm_framebuffer *old_fb,
  87                           struct drm_atomic_state *state);
  88 static int intel_framebuffer_init(struct drm_device *dev,
  89                                   struct intel_framebuffer *ifb,
  90                                   struct drm_mode_fb_cmd2 *mode_cmd,
  91                                   struct drm_i915_gem_object *obj);
  92 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  93 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  95                                          struct intel_link_m_n *m_n,
  96                                          struct intel_link_m_n *m2_n2);
  97 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  98 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  99 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 100 static void vlv_prepare_pll(struct intel_crtc *crtc,
 101                             const struct intel_crtc_state *pipe_config);
 102 static void chv_prepare_pll(struct intel_crtc *crtc,
 103                             const struct intel_crtc_state *pipe_config);
 104 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 105 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 106
 107 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 108 {
 109         if (!connector->mst_port)
 110                 return connector->encoder;
 111         else
 112                 return &connector->mst_port->mst_encoders[pipe]->base;
 113 }
 114
 115 typedef struct {
 116         int     min, max;
 117 } intel_range_t;
 118
 119 typedef struct {
 120         int     dot_limit;
 121         int     p2_slow, p2_fast;
 122 } intel_p2_t;
 123
 124 typedef struct intel_limit intel_limit_t;
 125 struct intel_limit {
 126         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 127         intel_p2_t          p2;
 128 };
 129
 130 int
 131 intel_pch_rawclk(struct drm_device *dev)
 132 {
 133         struct drm_i915_private *dev_priv = dev->dev_private;
 134
 135         WARN_ON(!HAS_PCH_SPLIT(dev));
 136
 137         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 138 }
 139
 140 static inline u32 /* units of 100MHz */
 141 intel_fdi_link_freq(struct drm_device *dev)
 142 {
 143         if (IS_GEN5(dev)) {
 144                 struct drm_i915_private *dev_priv = dev->dev_private;
 145                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 146         } else
 147                 return 27;
 148 }
 149
 150 static const intel_limit_t intel_limits_i8xx_dac = {
 151         .dot = { .min = 25000, .max = 350000 },
 152         .vco = { .min = 908000, .max = 1512000 },
 153         .n = { .min = 2, .max = 16 },
 154         .m = { .min = 96, .max = 140 },
 155         .m1 = { .min = 18, .max = 26 },
 156         .m2 = { .min = 6, .max = 16 },
 157         .p = { .min = 4, .max = 128 },
 158         .p1 = { .min = 2, .max = 33 },
 159         .p2 = { .dot_limit = 165000,
 160                 .p2_slow = 4, .p2_fast = 2 },
 161 };
 162
 163 static const intel_limit_t intel_limits_i8xx_dvo = {
 164         .dot = { .min = 25000, .max = 350000 },
 165         .vco = { .min = 908000, .max = 1512000 },
 166         .n = { .min = 2, .max = 16 },
 167         .m = { .min = 96, .max = 140 },
 168         .m1 = { .min = 18, .max = 26 },
 169         .m2 = { .min = 6, .max = 16 },
 170         .p = { .min = 4, .max = 128 },
 171         .p1 = { .min = 2, .max = 33 },
 172         .p2 = { .dot_limit = 165000,
 173                 .p2_slow = 4, .p2_fast = 4 },
 174 };
 175
 176 static const intel_limit_t intel_limits_i8xx_lvds = {
 177         .dot = { .min = 25000, .max = 350000 },
 178         .vco = { .min = 908000, .max = 1512000 },
 179         .n = { .min = 2, .max = 16 },
 180         .m = { .min = 96, .max = 140 },
 181         .m1 = { .min = 18, .max = 26 },
 182         .m2 = { .min = 6, .max = 16 },
 183         .p = { .min = 4, .max = 128 },
 184         .p1 = { .min = 1, .max = 6 },
 185         .p2 = { .dot_limit = 165000,
 186                 .p2_slow = 14, .p2_fast = 7 },
 187 };
 188
 189 static const intel_limit_t intel_limits_i9xx_sdvo = {
 190         .dot = { .min = 20000, .max = 400000 },
 191         .vco = { .min = 1400000, .max = 2800000 },
 192         .n = { .min = 1, .max = 6 },
 193         .m = { .min = 70, .max = 120 },
 194         .m1 = { .min = 8, .max = 18 },
 195         .m2 = { .min = 3, .max = 7 },
 196         .p = { .min = 5, .max = 80 },
 197         .p1 = { .min = 1, .max = 8 },
 198         .p2 = { .dot_limit = 200000,
 199                 .p2_slow = 10, .p2_fast = 5 },
 200 };
 201
 202 static const intel_limit_t intel_limits_i9xx_lvds = {
 203         .dot = { .min = 20000, .max = 400000 },
 204         .vco = { .min = 1400000, .max = 2800000 },
 205         .n = { .min = 1, .max = 6 },
 206         .m = { .min = 70, .max = 120 },
 207         .m1 = { .min = 8, .max = 18 },
 208         .m2 = { .min = 3, .max = 7 },
 209         .p = { .min = 7, .max = 98 },
 210         .p1 = { .min = 1, .max = 8 },
 211         .p2 = { .dot_limit = 112000,
 212                 .p2_slow = 14, .p2_fast = 7 },
 213 };
 214
 215
 216 static const intel_limit_t intel_limits_g4x_sdvo = {
 217         .dot = { .min = 25000, .max = 270000 },
 218         .vco = { .min = 1750000, .max = 3500000},
 219         .n = { .min = 1, .max = 4 },
 220         .m = { .min = 104, .max = 138 },
 221         .m1 = { .min = 17, .max = 23 },
 222         .m2 = { .min = 5, .max = 11 },
 223         .p = { .min = 10, .max = 30 },
 224         .p1 = { .min = 1, .max = 3},
 225         .p2 = { .dot_limit = 270000,
 226                 .p2_slow = 10,
 227                 .p2_fast = 10
 228         },
 229 };
 230
 231 static const intel_limit_t intel_limits_g4x_hdmi = {
 232         .dot = { .min = 22000, .max = 400000 },
 233         .vco = { .min = 1750000, .max = 3500000},
 234         .n = { .min = 1, .max = 4 },
 235         .m = { .min = 104, .max = 138 },
 236         .m1 = { .min = 16, .max = 23 },
 237         .m2 = { .min = 5, .max = 11 },
 238         .p = { .min = 5, .max = 80 },
 239         .p1 = { .min = 1, .max = 8},
 240         .p2 = { .dot_limit = 165000,
 241                 .p2_slow = 10, .p2_fast = 5 },
 242 };
 243
 244 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 245         .dot = { .min = 20000, .max = 115000 },
 246         .vco = { .min = 1750000, .max = 3500000 },
 247         .n = { .min = 1, .max = 3 },
 248         .m = { .min = 104, .max = 138 },
 249         .m1 = { .min = 17, .max = 23 },
 250         .m2 = { .min = 5, .max = 11 },
 251         .p = { .min = 28, .max = 112 },
 252         .p1 = { .min = 2, .max = 8 },
 253         .p2 = { .dot_limit = 0,
 254                 .p2_slow = 14, .p2_fast = 14
 255         },
 256 };
 257
 258 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 259         .dot = { .min = 80000, .max = 224000 },
 260         .vco = { .min = 1750000, .max = 3500000 },
 261         .n = { .min = 1, .max = 3 },
 262         .m = { .min = 104, .max = 138 },
 263         .m1 = { .min = 17, .max = 23 },
 264         .m2 = { .min = 5, .max = 11 },
 265         .p = { .min = 14, .max = 42 },
 266         .p1 = { .min = 2, .max = 6 },
 267         .p2 = { .dot_limit = 0,
 268                 .p2_slow = 7, .p2_fast = 7
 269         },
 270 };
 271
 272 static const intel_limit_t intel_limits_pineview_sdvo = {
 273         .dot = { .min = 20000, .max = 400000},
 274         .vco = { .min = 1700000, .max = 3500000 },
 275         /* Pineview's Ncounter is a ring counter */
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         /* Pineview only has one combined m divider, which we treat as m2. */
 279         .m1 = { .min = 0, .max = 0 },
 280         .m2 = { .min = 0, .max = 254 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 200000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285 };
 286
 287 static const intel_limit_t intel_limits_pineview_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1700000, .max = 3500000 },
 290         .n = { .min = 3, .max = 6 },
 291         .m = { .min = 2, .max = 256 },
 292         .m1 = { .min = 0, .max = 0 },
 293         .m2 = { .min = 0, .max = 254 },
 294         .p = { .min = 7, .max = 112 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298 };
 299
 300 /* Ironlake / Sandybridge
 301  *
 302  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 303  * the range value for them is (actual_value - 2).
 304  */
 305 static const intel_limit_t intel_limits_ironlake_dac = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 5 },
 309         .m = { .min = 79, .max = 127 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 5, .max = 80 },
 313         .p1 = { .min = 1, .max = 8 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 10, .p2_fast = 5 },
 316 };
 317
 318 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 319         .dot = { .min = 25000, .max = 350000 },
 320         .vco = { .min = 1760000, .max = 3510000 },
 321         .n = { .min = 1, .max = 3 },
 322         .m = { .min = 79, .max = 118 },
 323         .m1 = { .min = 12, .max = 22 },
 324         .m2 = { .min = 5, .max = 9 },
 325         .p = { .min = 28, .max = 112 },
 326         .p1 = { .min = 2, .max = 8 },
 327         .p2 = { .dot_limit = 225000,
 328                 .p2_slow = 14, .p2_fast = 14 },
 329 };
 330
 331 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 332         .dot = { .min = 25000, .max = 350000 },
 333         .vco = { .min = 1760000, .max = 3510000 },
 334         .n = { .min = 1, .max = 3 },
 335         .m = { .min = 79, .max = 127 },
 336         .m1 = { .min = 12, .max = 22 },
 337         .m2 = { .min = 5, .max = 9 },
 338         .p = { .min = 14, .max = 56 },
 339         .p1 = { .min = 2, .max = 8 },
 340         .p2 = { .dot_limit = 225000,
 341                 .p2_slow = 7, .p2_fast = 7 },
 342 };
 343
 344 /* LVDS 100mhz refclk limits. */
 345 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 346         .dot = { .min = 25000, .max = 350000 },
 347         .vco = { .min = 1760000, .max = 3510000 },
 348         .n = { .min = 1, .max = 2 },
 349         .m = { .min = 79, .max = 126 },
 350         .m1 = { .min = 12, .max = 22 },
 351         .m2 = { .min = 5, .max = 9 },
 352         .p = { .min = 28, .max = 112 },
 353         .p1 = { .min = 2, .max = 8 },
 354         .p2 = { .dot_limit = 225000,
 355                 .p2_slow = 14, .p2_fast = 14 },
 356 };
 357
 358 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 359         .dot = { .min = 25000, .max = 350000 },
 360         .vco = { .min = 1760000, .max = 3510000 },
 361         .n = { .min = 1, .max = 3 },
 362         .m = { .min = 79, .max = 126 },
 363         .m1 = { .min = 12, .max = 22 },
 364         .m2 = { .min = 5, .max = 9 },
 365         .p = { .min = 14, .max = 42 },
 366         .p1 = { .min = 2, .max = 6 },
 367         .p2 = { .dot_limit = 225000,
 368                 .p2_slow = 7, .p2_fast = 7 },
 369 };
 370
 371 static const intel_limit_t intel_limits_vlv = {
 372          /*
 373           * These are the data rate limits (measured in fast clocks)
 374           * since those are the strictest limits we have. The fast
 375           * clock and actual rate limits are more relaxed, so checking
 376           * them would make no difference.
 377           */
 378         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m1 = { .min = 2, .max = 3 },
 382         .m2 = { .min = 11, .max = 156 },
 383         .p1 = { .min = 2, .max = 3 },
 384         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 385 };
 386
 387 static const intel_limit_t intel_limits_chv = {
 388         /*
 389          * These are the data rate limits (measured in fast clocks)
 390          * since those are the strictest limits we have.  The fast
 391          * clock and actual rate limits are more relaxed, so checking
 392          * them would make no difference.
 393          */
 394         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 395         .vco = { .min = 4800000, .max = 6480000 },
 396         .n = { .min = 1, .max = 1 },
 397         .m1 = { .min = 2, .max = 2 },
 398         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 399         .p1 = { .min = 2, .max = 4 },
 400         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 401 };
 402
 403 static void vlv_clock(int refclk, intel_clock_t *clock)
 404 {
 405         clock->m = clock->m1 * clock->m2;
 406         clock->p = clock->p1 * clock->p2;
 407         if (WARN_ON(clock->n == 0 || clock->p == 0))
 408                 return;
 409         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 410         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 411 }
 412
 413 /**
 414  * Returns whether any output on the specified pipe is of the specified type
 415  */
 416 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 417 {
 418         struct drm_device *dev = crtc->base.dev;
 419         struct intel_encoder *encoder;
 420
 421         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 422                 if (encoder->type == type)
 423                         return true;
 424
 425         return false;
 426 }
 427
 428 /**
 429  * Returns whether any output on the specified pipe will have the specified
 430  * type after a staged modeset is complete, i.e., the same as
 431  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 432  * encoder->crtc.
 433  */
 434 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 435 {
 436         struct drm_device *dev = crtc->base.dev;
 437         struct intel_encoder *encoder;
 438
 439         for_each_intel_encoder(dev, encoder)
 440                 if (encoder->new_crtc == crtc && encoder->type == type)
 441                         return true;
 442
 443         return false;
 444 }
 445
 446 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 447                                                 int refclk)
 448 {
 449         struct drm_device *dev = crtc->base.dev;
 450         const intel_limit_t *limit;
 451
 452         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 453                 if (intel_is_dual_link_lvds(dev)) {
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_dual_lvds;
 458                 } else {
 459                         if (refclk == 100000)
 460                                 limit = &intel_limits_ironlake_single_lvds_100m;
 461                         else
 462                                 limit = &intel_limits_ironlake_single_lvds;
 463                 }
 464         } else
 465                 limit = &intel_limits_ironlake_dac;
 466
 467         return limit;
 468 }
 469
 470 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 471 {
 472         struct drm_device *dev = crtc->base.dev;
 473         const intel_limit_t *limit;
 474
 475         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 476                 if (intel_is_dual_link_lvds(dev))
 477                         limit = &intel_limits_g4x_dual_channel_lvds;
 478                 else
 479                         limit = &intel_limits_g4x_single_channel_lvds;
 480         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 481                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 482                 limit = &intel_limits_g4x_hdmi;
 483         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 484                 limit = &intel_limits_g4x_sdvo;
 485         } else /* The option is for other outputs */
 486                 limit = &intel_limits_i9xx_sdvo;
 487
 488         return limit;
 489 }
 490
 491 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 492 {
 493         struct drm_device *dev = crtc->base.dev;
 494         const intel_limit_t *limit;
 495
 496         if (HAS_PCH_SPLIT(dev))
 497                 limit = intel_ironlake_limit(crtc, refclk);
 498         else if (IS_G4X(dev)) {
 499                 limit = intel_g4x_limit(crtc);
 500         } else if (IS_PINEVIEW(dev)) {
 501                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 502                         limit = &intel_limits_pineview_lvds;
 503                 else
 504                         limit = &intel_limits_pineview_sdvo;
 505         } else if (IS_CHERRYVIEW(dev)) {
 506                 limit = &intel_limits_chv;
 507         } else if (IS_VALLEYVIEW(dev)) {
 508                 limit = &intel_limits_vlv;
 509         } else if (!IS_GEN2(dev)) {
 510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 511                         limit = &intel_limits_i9xx_lvds;
 512                 else
 513                         limit = &intel_limits_i9xx_sdvo;
 514         } else {
 515                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 516                         limit = &intel_limits_i8xx_lvds;
 517                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 518                         limit = &intel_limits_i8xx_dvo;
 519                 else
 520                         limit = &intel_limits_i8xx_dac;
 521         }
 522         return limit;
 523 }
 524
 525 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 526 static void pineview_clock(int refclk, intel_clock_t *clock)
 527 {
 528         clock->m = clock->m2 + 2;
 529         clock->p = clock->p1 * clock->p2;
 530         if (WARN_ON(clock->n == 0 || clock->p == 0))
 531                 return;
 532         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 533         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 534 }
 535
 536 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 537 {
 538         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 539 }
 540
 541 static void i9xx_clock(int refclk, intel_clock_t *clock)
 542 {
 543         clock->m = i9xx_dpll_compute_m(clock);
 544         clock->p = clock->p1 * clock->p2;
 545         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 546                 return;
 547         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 548         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 549 }
 550
 551 static void chv_clock(int refclk, intel_clock_t *clock)
 552 {
 553         clock->m = clock->m1 * clock->m2;
 554         clock->p = clock->p1 * clock->p2;
 555         if (WARN_ON(clock->n == 0 || clock->p == 0))
 556                 return;
 557         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 558                         clock->n << 22);
 559         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 560 }
 561
 562 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 563 /**
 564  * Returns whether the given set of divisors are valid for a given refclk with
 565  * the given connectors.
 566  */
 567
 568 static bool intel_PLL_is_valid(struct drm_device *dev,
 569                                const intel_limit_t *limit,
 570                                const intel_clock_t *clock)
 571 {
 572         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 573                 INTELPllInvalid("n out of range\n");
 574         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 575                 INTELPllInvalid("p1 out of range\n");
 576         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 577                 INTELPllInvalid("m2 out of range\n");
 578         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 579                 INTELPllInvalid("m1 out of range\n");
 580
 581         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 582                 if (clock->m1 <= clock->m2)
 583                         INTELPllInvalid("m1 <= m2\n");
 584
 585         if (!IS_VALLEYVIEW(dev)) {
 586                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 587                         INTELPllInvalid("p out of range\n");
 588                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 589                         INTELPllInvalid("m out of range\n");
 590         }
 591
 592         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 593                 INTELPllInvalid("vco out of range\n");
 594         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 595          * connector, etc., rather than just a single range.
 596          */
 597         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 598                 INTELPllInvalid("dot out of range\n");
 599
 600         return true;
 601 }
 602
 603 static bool
 604 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 605                     int target, int refclk, intel_clock_t *match_clock,
 606                     intel_clock_t *best_clock)
 607 {
 608         struct drm_device *dev = crtc->base.dev;
 609         intel_clock_t clock;
 610         int err = target;
 611
 612         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 613                 /*
 614                  * For LVDS just rely on its current settings for dual-channel.
 615                  * We haven't figured out how to reliably set up different
 616                  * single/dual channel state, if we even can.
 617                  */
 618                 if (intel_is_dual_link_lvds(dev))
 619                         clock.p2 = limit->p2.p2_fast;
 620                 else
 621                         clock.p2 = limit->p2.p2_slow;
 622         } else {
 623                 if (target < limit->p2.dot_limit)
 624                         clock.p2 = limit->p2.p2_slow;
 625                 else
 626                         clock.p2 = limit->p2.p2_fast;
 627         }
 628
 629         memset(best_clock, 0, sizeof(*best_clock));
 630
 631         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 632              clock.m1++) {
 633                 for (clock.m2 = limit->m2.min;
 634                      clock.m2 <= limit->m2.max; clock.m2++) {
 635                         if (clock.m2 >= clock.m1)
 636                                 break;
 637                         for (clock.n = limit->n.min;
 638                              clock.n <= limit->n.max; clock.n++) {
 639                                 for (clock.p1 = limit->p1.min;
 640                                         clock.p1 <= limit->p1.max; clock.p1++) {
 641                                         int this_err;
 642
 643                                         i9xx_clock(refclk, &clock);
 644                                         if (!intel_PLL_is_valid(dev, limit,
 645                                                                 &clock))
 646                                                 continue;
 647                                         if (match_clock &&
 648                                             clock.p != match_clock->p)
 649                                                 continue;
 650
 651                                         this_err = abs(clock.dot - target);
 652                                         if (this_err < err) {
 653                                                 *best_clock = clock;
 654                                                 err = this_err;
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660
 661         return (err != target);
 662 }
 663
 664 static bool
 665 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 666                    int target, int refclk, intel_clock_t *match_clock,
 667                    intel_clock_t *best_clock)
 668 {
 669         struct drm_device *dev = crtc->base.dev;
 670         intel_clock_t clock;
 671         int err = target;
 672
 673         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 674                 /*
 675                  * For LVDS just rely on its current settings for dual-channel.
 676                  * We haven't figured out how to reliably set up different
 677                  * single/dual channel state, if we even can.
 678                  */
 679                 if (intel_is_dual_link_lvds(dev))
 680                         clock.p2 = limit->p2.p2_fast;
 681                 else
 682                         clock.p2 = limit->p2.p2_slow;
 683         } else {
 684                 if (target < limit->p2.dot_limit)
 685                         clock.p2 = limit->p2.p2_slow;
 686                 else
 687                         clock.p2 = limit->p2.p2_fast;
 688         }
 689
 690         memset(best_clock, 0, sizeof(*best_clock));
 691
 692         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 693              clock.m1++) {
 694                 for (clock.m2 = limit->m2.min;
 695                      clock.m2 <= limit->m2.max; clock.m2++) {
 696                         for (clock.n = limit->n.min;
 697                              clock.n <= limit->n.max; clock.n++) {
 698                                 for (clock.p1 = limit->p1.min;
 699                                         clock.p1 <= limit->p1.max; clock.p1++) {
 700                                         int this_err;
 701
 702                                         pineview_clock(refclk, &clock);
 703                                         if (!intel_PLL_is_valid(dev, limit,
 704                                                                 &clock))
 705                                                 continue;
 706                                         if (match_clock &&
 707                                             clock.p != match_clock->p)
 708                                                 continue;
 709
 710                                         this_err = abs(clock.dot - target);
 711                                         if (this_err < err) {
 712                                                 *best_clock = clock;
 713                                                 err = this_err;
 714                                         }
 715                                 }
 716                         }
 717                 }
 718         }
 719
 720         return (err != target);
 721 }
 722
 723 static bool
 724 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 725                    int target, int refclk, intel_clock_t *match_clock,
 726                    intel_clock_t *best_clock)
 727 {
 728         struct drm_device *dev = crtc->base.dev;
 729         intel_clock_t clock;
 730         int max_n;
 731         bool found;
 732         /* approximately equals target * 0.00585 */
 733         int err_most = (target >> 8) + (target >> 9);
 734         found = false;
 735
 736         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 737                 if (intel_is_dual_link_lvds(dev))
 738                         clock.p2 = limit->p2.p2_fast;
 739                 else
 740                         clock.p2 = limit->p2.p2_slow;
 741         } else {
 742                 if (target < limit->p2.dot_limit)
 743                         clock.p2 = limit->p2.p2_slow;
 744                 else
 745                         clock.p2 = limit->p2.p2_fast;
 746         }
 747
 748         memset(best_clock, 0, sizeof(*best_clock));
 749         max_n = limit->n.max;
 750         /* based on hardware requirement, prefer smaller n to precision */
 751         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 752                 /* based on hardware requirement, prefere larger m1,m2 */
 753                 for (clock.m1 = limit->m1.max;
 754                      clock.m1 >= limit->m1.min; clock.m1--) {
 755                         for (clock.m2 = limit->m2.max;
 756                              clock.m2 >= limit->m2.min; clock.m2--) {
 757                                 for (clock.p1 = limit->p1.max;
 758                                      clock.p1 >= limit->p1.min; clock.p1--) {
 759                                         int this_err;
 760
 761                                         i9xx_clock(refclk, &clock);
 762                                         if (!intel_PLL_is_valid(dev, limit,
 763                                                                 &clock))
 764                                                 continue;
 765
 766                                         this_err = abs(clock.dot - target);
 767                                         if (this_err < err_most) {
 768                                                 *best_clock = clock;
 769                                                 err_most = this_err;
 770                                                 max_n = clock.n;
 771                                                 found = true;
 772                                         }
 773                                 }
 774                         }
 775                 }
 776         }
 777         return found;
 778 }
 779
 780 /*
 781  * Check if the calculated PLL configuration is more optimal compared to the
 782  * best configuration and error found so far. Return the calculated error.
 783  */
 784 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 785                                const intel_clock_t *calculated_clock,
 786                                const intel_clock_t *best_clock,
 787                                unsigned int best_error_ppm,
 788                                unsigned int *error_ppm)
 789 {
 790         /*
 791          * For CHV ignore the error and consider only the P value.
 792          * Prefer a bigger P value based on HW requirements.
 793          */
 794         if (IS_CHERRYVIEW(dev)) {
 795                 *error_ppm = 0;
 796
 797                 return calculated_clock->p > best_clock->p;
 798         }
 799
 800         if (WARN_ON_ONCE(!target_freq))
 801                 return false;
 802
 803         *error_ppm = div_u64(1000000ULL *
 804                                 abs(target_freq - calculated_clock->dot),
 805                              target_freq);
 806         /*
 807          * Prefer a better P value over a better (smaller) error if the error
 808          * is small. Ensure this preference for future configurations too by
 809          * setting the error to 0.
 810          */
 811         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 812                 *error_ppm = 0;
 813
 814                 return true;
 815         }
 816
 817         return *error_ppm + 10 < best_error_ppm;
 818 }
 819
 820 static bool
 821 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 822                    int target, int refclk, intel_clock_t *match_clock,
 823                    intel_clock_t *best_clock)
 824 {
 825         struct drm_device *dev = crtc->base.dev;
 826         intel_clock_t clock;
 827         unsigned int bestppm = 1000000;
 828         /* min update 19.2 MHz */
 829         int max_n = min(limit->n.max, refclk / 19200);
 830         bool found = false;
 831
 832         target *= 5; /* fast clock */
 833
 834         memset(best_clock, 0, sizeof(*best_clock));
 835
 836         /* based on hardware requirement, prefer smaller n to precision */
 837         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 838                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 839                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 840                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 841                                 clock.p = clock.p1 * clock.p2;
 842                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 843                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 844                                         unsigned int ppm;
 845
 846                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 847                                                                      refclk * clock.m1);
 848
 849                                         vlv_clock(refclk, &clock);
 850
 851                                         if (!intel_PLL_is_valid(dev, limit,
 852                                                                 &clock))
 853                                                 continue;
 854
 855                                         if (!vlv_PLL_is_optimal(dev, target,
 856                                                                 &clock,
 857                                                                 best_clock,
 858                                                                 bestppm, &ppm))
 859                                                 continue;
 860
 861                                         *best_clock = clock;
 862                                         bestppm = ppm;
 863                                         found = true;
 864                                 }
 865                         }
 866                 }
 867         }
 868
 869         return found;
 870 }
 871
 872 static bool
 873 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 874                    int target, int refclk, intel_clock_t *match_clock,
 875                    intel_clock_t *best_clock)
 876 {
 877         struct drm_device *dev = crtc->base.dev;
 878         unsigned int best_error_ppm;
 879         intel_clock_t clock;
 880         uint64_t m2;
 881         int found = false;
 882
 883         memset(best_clock, 0, sizeof(*best_clock));
 884         best_error_ppm = 1000000;
 885
 886         /*
 887          * Based on hardware doc, the n always set to 1, and m1 always
 888          * set to 2.  If requires to support 200Mhz refclk, we need to
 889          * revisit this because n may not 1 anymore.
 890          */
 891         clock.n = 1, clock.m1 = 2;
 892         target *= 5;    /* fast clock */
 893
 894         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 895                 for (clock.p2 = limit->p2.p2_fast;
 896                                 clock.p2 >= limit->p2.p2_slow;
 897                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 898                         unsigned int error_ppm;
 899
 900                         clock.p = clock.p1 * clock.p2;
 901
 902                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 903                                         clock.n) << 22, refclk * clock.m1);
 904
 905                         if (m2 > INT_MAX/clock.m1)
 906                                 continue;
 907
 908                         clock.m2 = m2;
 909
 910                         chv_clock(refclk, &clock);
 911
 912                         if (!intel_PLL_is_valid(dev, limit, &clock))
 913                                 continue;
 914
 915                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 916                                                 best_error_ppm, &error_ppm))
 917                                 continue;
 918
 919                         *best_clock = clock;
 920                         best_error_ppm = error_ppm;
 921                         found = true;
 922                 }
 923         }
 924
 925         return found;
 926 }
 927
 928 bool intel_crtc_active(struct drm_crtc *crtc)
 929 {
 930         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 931
 932         /* Be paranoid as we can arrive here with only partial
 933          * state retrieved from the hardware during setup.
 934          *
 935          * We can ditch the adjusted_mode.crtc_clock check as soon
 936          * as Haswell has gained clock readout/fastboot support.
 937          *
 938          * We can ditch the crtc->primary->fb check as soon as we can
 939          * properly reconstruct framebuffers.
 940          *
 941          * FIXME: The intel_crtc->active here should be switched to
 942          * crtc->state->active once we have proper CRTC states wired up
 943          * for atomic.
 944          */
 945         return intel_crtc->active && crtc->primary->state->fb &&
 946                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 947 }
 948
 949 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 950                                              enum pipe pipe)
 951 {
 952         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 953         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 954
 955         return intel_crtc->config->cpu_transcoder;
 956 }
 957
 958 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 959 {
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961         u32 reg = PIPEDSL(pipe);
 962         u32 line1, line2;
 963         u32 line_mask;
 964
 965         if (IS_GEN2(dev))
 966                 line_mask = DSL_LINEMASK_GEN2;
 967         else
 968                 line_mask = DSL_LINEMASK_GEN3;
 969
 970         line1 = I915_READ(reg) & line_mask;
 971         mdelay(5);
 972         line2 = I915_READ(reg) & line_mask;
 973
 974         return line1 == line2;
 975 }
 976
 977 /*
 978  * intel_wait_for_pipe_off - wait for pipe to turn off
 979  * @crtc: crtc whose pipe to wait for
 980  *
 981  * After disabling a pipe, we can't wait for vblank in the usual way,
 982  * spinning on the vblank interrupt status bit, since we won't actually
 983  * see an interrupt when the pipe is disabled.
 984  *
 985  * On Gen4 and above:
 986  *   wait for the pipe register state bit to turn off
 987  *
 988  * Otherwise:
 989  *   wait for the display line value to settle (it usually
 990  *   ends up stopping at the start of the next frame).
 991  *
 992  */
 993 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 994 {
 995         struct drm_device *dev = crtc->base.dev;
 996         struct drm_i915_private *dev_priv = dev->dev_private;
 997         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
 998         enum pipe pipe = crtc->pipe;
 999
1000         if (INTEL_INFO(dev)->gen >= 4) {
1001                 int reg = PIPECONF(cpu_transcoder);
1002
1003                 /* Wait for the Pipe State to go off */
1004                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1005                              100))
1006                         WARN(1, "pipe_off wait timed out\n");
1007         } else {
1008                 /* Wait for the display line to settle */
1009                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1010                         WARN(1, "pipe_off wait timed out\n");
1011         }
1012 }
1013
1014 /*
1015  * ibx_digital_port_connected - is the specified port connected?
1016  * @dev_priv: i915 private structure
1017  * @port: the port to test
1018  *
1019  * Returns true if @port is connected, false otherwise.
1020  */
1021 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1022                                 struct intel_digital_port *port)
1023 {
1024         u32 bit;
1025
1026         if (HAS_PCH_IBX(dev_priv->dev)) {
1027                 switch (port->port) {
1028                 case PORT_B:
1029                         bit = SDE_PORTB_HOTPLUG;
1030                         break;
1031                 case PORT_C:
1032                         bit = SDE_PORTC_HOTPLUG;
1033                         break;
1034                 case PORT_D:
1035                         bit = SDE_PORTD_HOTPLUG;
1036                         break;
1037                 default:
1038                         return true;
1039                 }
1040         } else {
1041                 switch (port->port) {
1042                 case PORT_B:
1043                         bit = SDE_PORTB_HOTPLUG_CPT;
1044                         break;
1045                 case PORT_C:
1046                         bit = SDE_PORTC_HOTPLUG_CPT;
1047                         break;
1048                 case PORT_D:
1049                         bit = SDE_PORTD_HOTPLUG_CPT;
1050                         break;
1051                 default:
1052                         return true;
1053                 }
1054         }
1055
1056         return I915_READ(SDEISR) & bit;
1057 }
1058
1059 static const char *state_string(bool enabled)
1060 {
1061         return enabled ? "on" : "off";
1062 }
1063
1064 /* Only for pre-ILK configs */
1065 void assert_pll(struct drm_i915_private *dev_priv,
1066                 enum pipe pipe, bool state)
1067 {
1068         int reg;
1069         u32 val;
1070         bool cur_state;
1071
1072         reg = DPLL(pipe);
1073         val = I915_READ(reg);
1074         cur_state = !!(val & DPLL_VCO_ENABLE);
1075         I915_STATE_WARN(cur_state != state,
1076              "PLL state assertion failure (expected %s, current %s)\n",
1077              state_string(state), state_string(cur_state));
1078 }
1079
1080 /* XXX: the dsi pll is shared between MIPI DSI ports */
1081 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1082 {
1083         u32 val;
1084         bool cur_state;
1085
1086         mutex_lock(&dev_priv->dpio_lock);
1087         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1088         mutex_unlock(&dev_priv->dpio_lock);
1089
1090         cur_state = val & DSI_PLL_VCO_EN;
1091         I915_STATE_WARN(cur_state != state,
1092              "DSI PLL state assertion failure (expected %s, current %s)\n",
1093              state_string(state), state_string(cur_state));
1094 }
1095 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1096 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1097
1098 struct intel_shared_dpll *
1099 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1100 {
1101         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1102
1103         if (crtc->config->shared_dpll < 0)
1104                 return NULL;
1105
1106         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1107 }
1108
1109 /* For ILK+ */
1110 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1111                         struct intel_shared_dpll *pll,
1112                         bool state)
1113 {
1114         bool cur_state;
1115         struct intel_dpll_hw_state hw_state;
1116
1117         if (WARN (!pll,
1118                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1119                 return;
1120
1121         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1122         I915_STATE_WARN(cur_state != state,
1123              "%s assertion failure (expected %s, current %s)\n",
1124              pll->name, state_string(state), state_string(cur_state));
1125 }
1126
1127 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1128                           enum pipe pipe, bool state)
1129 {
1130         int reg;
1131         u32 val;
1132         bool cur_state;
1133         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1134                                                                       pipe);
1135
1136         if (HAS_DDI(dev_priv->dev)) {
1137                 /* DDI does not have a specific FDI_TX register */
1138                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1139                 val = I915_READ(reg);
1140                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1141         } else {
1142                 reg = FDI_TX_CTL(pipe);
1143                 val = I915_READ(reg);
1144                 cur_state = !!(val & FDI_TX_ENABLE);
1145         }
1146         I915_STATE_WARN(cur_state != state,
1147              "FDI TX state assertion failure (expected %s, current %s)\n",
1148              state_string(state), state_string(cur_state));
1149 }
1150 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1151 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1152
1153 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1154                           enum pipe pipe, bool state)
1155 {
1156         int reg;
1157         u32 val;
1158         bool cur_state;
1159
1160         reg = FDI_RX_CTL(pipe);
1161         val = I915_READ(reg);
1162         cur_state = !!(val & FDI_RX_ENABLE);
1163         I915_STATE_WARN(cur_state != state,
1164              "FDI RX state assertion failure (expected %s, current %s)\n",
1165              state_string(state), state_string(cur_state));
1166 }
1167 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1168 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1169
1170 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1171                                       enum pipe pipe)
1172 {
1173         int reg;
1174         u32 val;
1175
1176         /* ILK FDI PLL is always enabled */
1177         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1178                 return;
1179
1180         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1181         if (HAS_DDI(dev_priv->dev))
1182                 return;
1183
1184         reg = FDI_TX_CTL(pipe);
1185         val = I915_READ(reg);
1186         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1187 }
1188
1189 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1190                        enum pipe pipe, bool state)
1191 {
1192         int reg;
1193         u32 val;
1194         bool cur_state;
1195
1196         reg = FDI_RX_CTL(pipe);
1197         val = I915_READ(reg);
1198         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1199         I915_STATE_WARN(cur_state != state,
1200              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1201              state_string(state), state_string(cur_state));
1202 }
1203
1204 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1205                            enum pipe pipe)
1206 {
1207         struct drm_device *dev = dev_priv->dev;
1208         int pp_reg;
1209         u32 val;
1210         enum pipe panel_pipe = PIPE_A;
1211         bool locked = true;
1212
1213         if (WARN_ON(HAS_DDI(dev)))
1214                 return;
1215
1216         if (HAS_PCH_SPLIT(dev)) {
1217                 u32 port_sel;
1218
1219                 pp_reg = PCH_PP_CONTROL;
1220                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1221
1222                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1223                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1224                         panel_pipe = PIPE_B;
1225                 /* XXX: else fix for eDP */
1226         } else if (IS_VALLEYVIEW(dev)) {
1227                 /* presumably write lock depends on pipe, not port select */
1228                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1229                 panel_pipe = pipe;
1230         } else {
1231                 pp_reg = PP_CONTROL;
1232                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1233                         panel_pipe = PIPE_B;
1234         }
1235
1236         val = I915_READ(pp_reg);
1237         if (!(val & PANEL_POWER_ON) ||
1238             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1239                 locked = false;
1240
1241         I915_STATE_WARN(panel_pipe == pipe && locked,
1242              "panel assertion failure, pipe %c regs locked\n",
1243              pipe_name(pipe));
1244 }
1245
1246 static void assert_cursor(struct drm_i915_private *dev_priv,
1247                           enum pipe pipe, bool state)
1248 {
1249         struct drm_device *dev = dev_priv->dev;
1250         bool cur_state;
1251
1252         if (IS_845G(dev) || IS_I865G(dev))
1253                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1254         else
1255                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1256
1257         I915_STATE_WARN(cur_state != state,
1258              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1259              pipe_name(pipe), state_string(state), state_string(cur_state));
1260 }
1261 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1262 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1263
1264 void assert_pipe(struct drm_i915_private *dev_priv,
1265                  enum pipe pipe, bool state)
1266 {
1267         int reg;
1268         u32 val;
1269         bool cur_state;
1270         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1271                                                                       pipe);
1272
1273         /* if we need the pipe quirk it must be always on */
1274         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1275             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1276                 state = true;
1277
1278         if (!intel_display_power_is_enabled(dev_priv,
1279                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1280                 cur_state = false;
1281         } else {
1282                 reg = PIPECONF(cpu_transcoder);
1283                 val = I915_READ(reg);
1284                 cur_state = !!(val & PIPECONF_ENABLE);
1285         }
1286
1287         I915_STATE_WARN(cur_state != state,
1288              "pipe %c assertion failure (expected %s, current %s)\n",
1289              pipe_name(pipe), state_string(state), state_string(cur_state));
1290 }
1291
1292 static void assert_plane(struct drm_i915_private *dev_priv,
1293                          enum plane plane, bool state)
1294 {
1295         int reg;
1296         u32 val;
1297         bool cur_state;
1298
1299         reg = DSPCNTR(plane);
1300         val = I915_READ(reg);
1301         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1302         I915_STATE_WARN(cur_state != state,
1303              "plane %c assertion failure (expected %s, current %s)\n",
1304              plane_name(plane), state_string(state), state_string(cur_state));
1305 }
1306
1307 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1308 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1309
1310 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe)
1312 {
1313         struct drm_device *dev = dev_priv->dev;
1314         int reg, i;
1315         u32 val;
1316         int cur_pipe;
1317
1318         /* Primary planes are fixed to pipes on gen4+ */
1319         if (INTEL_INFO(dev)->gen >= 4) {
1320                 reg = DSPCNTR(pipe);
1321                 val = I915_READ(reg);
1322                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1323                      "plane %c assertion failure, should be disabled but not\n",
1324                      plane_name(pipe));
1325                 return;
1326         }
1327
1328         /* Need to check both planes against the pipe */
1329         for_each_pipe(dev_priv, i) {
1330                 reg = DSPCNTR(i);
1331                 val = I915_READ(reg);
1332                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1333                         DISPPLANE_SEL_PIPE_SHIFT;
1334                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1335                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1336                      plane_name(i), pipe_name(pipe));
1337         }
1338 }
1339
1340 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1341                                     enum pipe pipe)
1342 {
1343         struct drm_device *dev = dev_priv->dev;
1344         int reg, sprite;
1345         u32 val;
1346
1347         if (INTEL_INFO(dev)->gen >= 9) {
1348                 for_each_sprite(dev_priv, pipe, sprite) {
1349                         val = I915_READ(PLANE_CTL(pipe, sprite));
1350                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1351                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1352                              sprite, pipe_name(pipe));
1353                 }
1354         } else if (IS_VALLEYVIEW(dev)) {
1355                 for_each_sprite(dev_priv, pipe, sprite) {
1356                         reg = SPCNTR(pipe, sprite);
1357                         val = I915_READ(reg);
1358                         I915_STATE_WARN(val & SP_ENABLE,
1359                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1360                              sprite_name(pipe, sprite), pipe_name(pipe));
1361                 }
1362         } else if (INTEL_INFO(dev)->gen >= 7) {
1363                 reg = SPRCTL(pipe);
1364                 val = I915_READ(reg);
1365                 I915_STATE_WARN(val & SPRITE_ENABLE,
1366                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1367                      plane_name(pipe), pipe_name(pipe));
1368         } else if (INTEL_INFO(dev)->gen >= 5) {
1369                 reg = DVSCNTR(pipe);
1370                 val = I915_READ(reg);
1371                 I915_STATE_WARN(val & DVS_ENABLE,
1372                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1373                      plane_name(pipe), pipe_name(pipe));
1374         }
1375 }
1376
1377 static void assert_vblank_disabled(struct drm_crtc *crtc)
1378 {
1379         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1380                 drm_crtc_vblank_put(crtc);
1381 }
1382
1383 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1384 {
1385         u32 val;
1386         bool enabled;
1387
1388         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1389
1390         val = I915_READ(PCH_DREF_CONTROL);
1391         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1392                             DREF_SUPERSPREAD_SOURCE_MASK));
1393         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1394 }
1395
1396 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1397                                            enum pipe pipe)
1398 {
1399         int reg;
1400         u32 val;
1401         bool enabled;
1402
1403         reg = PCH_TRANSCONF(pipe);
1404         val = I915_READ(reg);
1405         enabled = !!(val & TRANS_ENABLE);
1406         I915_STATE_WARN(enabled,
1407              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1408              pipe_name(pipe));
1409 }
1410
1411 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1412                             enum pipe pipe, u32 port_sel, u32 val)
1413 {
1414         if ((val & DP_PORT_EN) == 0)
1415                 return false;
1416
1417         if (HAS_PCH_CPT(dev_priv->dev)) {
1418                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1419                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1420                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1421                         return false;
1422         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1423                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1424                         return false;
1425         } else {
1426                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1427                         return false;
1428         }
1429         return true;
1430 }
1431
1432 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1433                               enum pipe pipe, u32 val)
1434 {
1435         if ((val & SDVO_ENABLE) == 0)
1436                 return false;
1437
1438         if (HAS_PCH_CPT(dev_priv->dev)) {
1439                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1440                         return false;
1441         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1442                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1443                         return false;
1444         } else {
1445                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1446                         return false;
1447         }
1448         return true;
1449 }
1450
1451 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1452                               enum pipe pipe, u32 val)
1453 {
1454         if ((val & LVDS_PORT_EN) == 0)
1455                 return false;
1456
1457         if (HAS_PCH_CPT(dev_priv->dev)) {
1458                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1459                         return false;
1460         } else {
1461                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1462                         return false;
1463         }
1464         return true;
1465 }
1466
1467 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1468                               enum pipe pipe, u32 val)
1469 {
1470         if ((val & ADPA_DAC_ENABLE) == 0)
1471                 return false;
1472         if (HAS_PCH_CPT(dev_priv->dev)) {
1473                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1474                         return false;
1475         } else {
1476                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1477                         return false;
1478         }
1479         return true;
1480 }
1481
1482 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1483                                    enum pipe pipe, int reg, u32 port_sel)
1484 {
1485         u32 val = I915_READ(reg);
1486         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1487              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1488              reg, pipe_name(pipe));
1489
1490         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1491              && (val & DP_PIPEB_SELECT),
1492              "IBX PCH dp port still using transcoder B\n");
1493 }
1494
1495 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1496                                      enum pipe pipe, int reg)
1497 {
1498         u32 val = I915_READ(reg);
1499         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1500              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1501              reg, pipe_name(pipe));
1502
1503         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1504              && (val & SDVO_PIPE_B_SELECT),
1505              "IBX PCH hdmi port still using transcoder B\n");
1506 }
1507
1508 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1509                                       enum pipe pipe)
1510 {
1511         int reg;
1512         u32 val;
1513
1514         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1515         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1516         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1517
1518         reg = PCH_ADPA;
1519         val = I915_READ(reg);
1520         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1521              "PCH VGA enabled on transcoder %c, should be disabled\n",
1522              pipe_name(pipe));
1523
1524         reg = PCH_LVDS;
1525         val = I915_READ(reg);
1526         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1527              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1528              pipe_name(pipe));
1529
1530         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1531         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1532         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1533 }
1534
1535 static void intel_init_dpio(struct drm_device *dev)
1536 {
1537         struct drm_i915_private *dev_priv = dev->dev_private;
1538
1539         if (!IS_VALLEYVIEW(dev))
1540                 return;
1541
1542         /*
1543          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1544          * CHV x1 PHY (DP/HDMI D)
1545          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1546          */
1547         if (IS_CHERRYVIEW(dev)) {
1548                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1549                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1550         } else {
1551                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1552         }
1553 }
1554
1555 static void vlv_enable_pll(struct intel_crtc *crtc,
1556                            const struct intel_crtc_state *pipe_config)
1557 {
1558         struct drm_device *dev = crtc->base.dev;
1559         struct drm_i915_private *dev_priv = dev->dev_private;
1560         int reg = DPLL(crtc->pipe);
1561         u32 dpll = pipe_config->dpll_hw_state.dpll;
1562
1563         assert_pipe_disabled(dev_priv, crtc->pipe);
1564
1565         /* No really, not for ILK+ */
1566         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1567
1568         /* PLL is protected by panel, make sure we can write it */
1569         if (IS_MOBILE(dev_priv->dev))
1570                 assert_panel_unlocked(dev_priv, crtc->pipe);
1571
1572         I915_WRITE(reg, dpll);
1573         POSTING_READ(reg);
1574         udelay(150);
1575
1576         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1577                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1578
1579         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(crtc->pipe));
1581
1582         /* We do this three times for luck */
1583         I915_WRITE(reg, dpll);
1584         POSTING_READ(reg);
1585         udelay(150); /* wait for warmup */
1586         I915_WRITE(reg, dpll);
1587         POSTING_READ(reg);
1588         udelay(150); /* wait for warmup */
1589         I915_WRITE(reg, dpll);
1590         POSTING_READ(reg);
1591         udelay(150); /* wait for warmup */
1592 }
1593
1594 static void chv_enable_pll(struct intel_crtc *crtc,
1595                            const struct intel_crtc_state *pipe_config)
1596 {
1597         struct drm_device *dev = crtc->base.dev;
1598         struct drm_i915_private *dev_priv = dev->dev_private;
1599         int pipe = crtc->pipe;
1600         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1601         u32 tmp;
1602
1603         assert_pipe_disabled(dev_priv, crtc->pipe);
1604
1605         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1606
1607         mutex_lock(&dev_priv->dpio_lock);
1608
1609         /* Enable back the 10bit clock to display controller */
1610         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1611         tmp |= DPIO_DCLKP_EN;
1612         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1613
1614         /*
1615          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1616          */
1617         udelay(1);
1618
1619         /* Enable PLL */
1620         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1621
1622         /* Check PLL is locked */
1623         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1624                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1625
1626         /* not sure when this should be written */
1627         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1628         POSTING_READ(DPLL_MD(pipe));
1629
1630         mutex_unlock(&dev_priv->dpio_lock);
1631 }
1632
1633 static int intel_num_dvo_pipes(struct drm_device *dev)
1634 {
1635         struct intel_crtc *crtc;
1636         int count = 0;
1637
1638         for_each_intel_crtc(dev, crtc)
1639                 count += crtc->active &&
1640                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1641
1642         return count;
1643 }
1644
1645 static void i9xx_enable_pll(struct intel_crtc *crtc)
1646 {
1647         struct drm_device *dev = crtc->base.dev;
1648         struct drm_i915_private *dev_priv = dev->dev_private;
1649         int reg = DPLL(crtc->pipe);
1650         u32 dpll = crtc->config->dpll_hw_state.dpll;
1651
1652         assert_pipe_disabled(dev_priv, crtc->pipe);
1653
1654         /* No really, not for ILK+ */
1655         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1656
1657         /* PLL is protected by panel, make sure we can write it */
1658         if (IS_MOBILE(dev) && !IS_I830(dev))
1659                 assert_panel_unlocked(dev_priv, crtc->pipe);
1660
1661         /* Enable DVO 2x clock on both PLLs if necessary */
1662         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1663                 /*
1664                  * It appears to be important that we don't enable this
1665                  * for the current pipe before otherwise configuring the
1666                  * PLL. No idea how this should be handled if multiple
1667                  * DVO outputs are enabled simultaneosly.
1668                  */
1669                 dpll |= DPLL_DVO_2X_MODE;
1670                 I915_WRITE(DPLL(!crtc->pipe),
1671                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1672         }
1673
1674         /* Wait for the clocks to stabilize. */
1675         POSTING_READ(reg);
1676         udelay(150);
1677
1678         if (INTEL_INFO(dev)->gen >= 4) {
1679                 I915_WRITE(DPLL_MD(crtc->pipe),
1680                            crtc->config->dpll_hw_state.dpll_md);
1681         } else {
1682                 /* The pixel multiplier can only be updated once the
1683                  * DPLL is enabled and the clocks are stable.
1684                  *
1685                  * So write it again.
1686                  */
1687                 I915_WRITE(reg, dpll);
1688         }
1689
1690         /* We do this three times for luck */
1691         I915_WRITE(reg, dpll);
1692         POSTING_READ(reg);
1693         udelay(150); /* wait for warmup */
1694         I915_WRITE(reg, dpll);
1695         POSTING_READ(reg);
1696         udelay(150); /* wait for warmup */
1697         I915_WRITE(reg, dpll);
1698         POSTING_READ(reg);
1699         udelay(150); /* wait for warmup */
1700 }
1701
1702 /**
1703  * i9xx_disable_pll - disable a PLL
1704  * @dev_priv: i915 private structure
1705  * @pipe: pipe PLL to disable
1706  *
1707  * Disable the PLL for @pipe, making sure the pipe is off first.
1708  *
1709  * Note!  This is for pre-ILK only.
1710  */
1711 static void i9xx_disable_pll(struct intel_crtc *crtc)
1712 {
1713         struct drm_device *dev = crtc->base.dev;
1714         struct drm_i915_private *dev_priv = dev->dev_private;
1715         enum pipe pipe = crtc->pipe;
1716
1717         /* Disable DVO 2x clock on both PLLs if necessary */
1718         if (IS_I830(dev) &&
1719             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1720             intel_num_dvo_pipes(dev) == 1) {
1721                 I915_WRITE(DPLL(PIPE_B),
1722                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1723                 I915_WRITE(DPLL(PIPE_A),
1724                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1725         }
1726
1727         /* Don't disable pipe or pipe PLLs if needed */
1728         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1729             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1730                 return;
1731
1732         /* Make sure the pipe isn't still relying on us */
1733         assert_pipe_disabled(dev_priv, pipe);
1734
1735         I915_WRITE(DPLL(pipe), 0);
1736         POSTING_READ(DPLL(pipe));
1737 }
1738
1739 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1740 {
1741         u32 val = 0;
1742
1743         /* Make sure the pipe isn't still relying on us */
1744         assert_pipe_disabled(dev_priv, pipe);
1745
1746         /*
1747          * Leave integrated clock source and reference clock enabled for pipe B.
1748          * The latter is needed for VGA hotplug / manual detection.
1749          */
1750         if (pipe == PIPE_B)
1751                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1752         I915_WRITE(DPLL(pipe), val);
1753         POSTING_READ(DPLL(pipe));
1754
1755 }
1756
1757 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1758 {
1759         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1760         u32 val;
1761
1762         /* Make sure the pipe isn't still relying on us */
1763         assert_pipe_disabled(dev_priv, pipe);
1764
1765         /* Set PLL en = 0 */
1766         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1767         if (pipe != PIPE_A)
1768                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1769         I915_WRITE(DPLL(pipe), val);
1770         POSTING_READ(DPLL(pipe));
1771
1772         mutex_lock(&dev_priv->dpio_lock);
1773
1774         /* Disable 10bit clock to display controller */
1775         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1776         val &= ~DPIO_DCLKP_EN;
1777         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1778
1779         /* disable left/right clock distribution */
1780         if (pipe != PIPE_B) {
1781                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1782                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1783                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1784         } else {
1785                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1786                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1787                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1788         }
1789
1790         mutex_unlock(&dev_priv->dpio_lock);
1791 }
1792
1793 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1794                 struct intel_digital_port *dport)
1795 {
1796         u32 port_mask;
1797         int dpll_reg;
1798
1799         switch (dport->port) {
1800         case PORT_B:
1801                 port_mask = DPLL_PORTB_READY_MASK;
1802                 dpll_reg = DPLL(0);
1803                 break;
1804         case PORT_C:
1805                 port_mask = DPLL_PORTC_READY_MASK;
1806                 dpll_reg = DPLL(0);
1807                 break;
1808         case PORT_D:
1809                 port_mask = DPLL_PORTD_READY_MASK;
1810                 dpll_reg = DPIO_PHY_STATUS;
1811                 break;
1812         default:
1813                 BUG();
1814         }
1815
1816         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1817                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1818                      port_name(dport->port), I915_READ(dpll_reg));
1819 }
1820
1821 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1822 {
1823         struct drm_device *dev = crtc->base.dev;
1824         struct drm_i915_private *dev_priv = dev->dev_private;
1825         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1826
1827         if (WARN_ON(pll == NULL))
1828                 return;
1829
1830         WARN_ON(!pll->config.crtc_mask);
1831         if (pll->active == 0) {
1832                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1833                 WARN_ON(pll->on);
1834                 assert_shared_dpll_disabled(dev_priv, pll);
1835
1836                 pll->mode_set(dev_priv, pll);
1837         }
1838 }
1839
1840 /**
1841  * intel_enable_shared_dpll - enable PCH PLL
1842  * @dev_priv: i915 private structure
1843  * @pipe: pipe PLL to enable
1844  *
1845  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1846  * drives the transcoder clock.
1847  */
1848 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1849 {
1850         struct drm_device *dev = crtc->base.dev;
1851         struct drm_i915_private *dev_priv = dev->dev_private;
1852         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1853
1854         if (WARN_ON(pll == NULL))
1855                 return;
1856
1857         if (WARN_ON(pll->config.crtc_mask == 0))
1858                 return;
1859
1860         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1861                       pll->name, pll->active, pll->on,
1862                       crtc->base.base.id);
1863
1864         if (pll->active++) {
1865                 WARN_ON(!pll->on);
1866                 assert_shared_dpll_enabled(dev_priv, pll);
1867                 return;
1868         }
1869         WARN_ON(pll->on);
1870
1871         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1872
1873         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1874         pll->enable(dev_priv, pll);
1875         pll->on = true;
1876 }
1877
1878 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1879 {
1880         struct drm_device *dev = crtc->base.dev;
1881         struct drm_i915_private *dev_priv = dev->dev_private;
1882         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1883
1884         /* PCH only available on ILK+ */
1885         BUG_ON(INTEL_INFO(dev)->gen < 5);
1886         if (WARN_ON(pll == NULL))
1887                return;
1888
1889         if (WARN_ON(pll->config.crtc_mask == 0))
1890                 return;
1891
1892         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1893                       pll->name, pll->active, pll->on,
1894                       crtc->base.base.id);
1895
1896         if (WARN_ON(pll->active == 0)) {
1897                 assert_shared_dpll_disabled(dev_priv, pll);
1898                 return;
1899         }
1900
1901         assert_shared_dpll_enabled(dev_priv, pll);
1902         WARN_ON(!pll->on);
1903         if (--pll->active)
1904                 return;
1905
1906         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1907         pll->disable(dev_priv, pll);
1908         pll->on = false;
1909
1910         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1911 }
1912
1913 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1914                                            enum pipe pipe)
1915 {
1916         struct drm_device *dev = dev_priv->dev;
1917         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1918         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1919         uint32_t reg, val, pipeconf_val;
1920
1921         /* PCH only available on ILK+ */
1922         BUG_ON(!HAS_PCH_SPLIT(dev));
1923
1924         /* Make sure PCH DPLL is enabled */
1925         assert_shared_dpll_enabled(dev_priv,
1926                                    intel_crtc_to_shared_dpll(intel_crtc));
1927
1928         /* FDI must be feeding us bits for PCH ports */
1929         assert_fdi_tx_enabled(dev_priv, pipe);
1930         assert_fdi_rx_enabled(dev_priv, pipe);
1931
1932         if (HAS_PCH_CPT(dev)) {
1933                 /* Workaround: Set the timing override bit before enabling the
1934                  * pch transcoder. */
1935                 reg = TRANS_CHICKEN2(pipe);
1936                 val = I915_READ(reg);
1937                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1938                 I915_WRITE(reg, val);
1939         }
1940
1941         reg = PCH_TRANSCONF(pipe);
1942         val = I915_READ(reg);
1943         pipeconf_val = I915_READ(PIPECONF(pipe));
1944
1945         if (HAS_PCH_IBX(dev_priv->dev)) {
1946                 /*
1947                  * make the BPC in transcoder be consistent with
1948                  * that in pipeconf reg.
1949                  */
1950                 val &= ~PIPECONF_BPC_MASK;
1951                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1952         }
1953
1954         val &= ~TRANS_INTERLACE_MASK;
1955         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1956                 if (HAS_PCH_IBX(dev_priv->dev) &&
1957                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1958                         val |= TRANS_LEGACY_INTERLACED_ILK;
1959                 else
1960                         val |= TRANS_INTERLACED;
1961         else
1962                 val |= TRANS_PROGRESSIVE;
1963
1964         I915_WRITE(reg, val | TRANS_ENABLE);
1965         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1966                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1967 }
1968
1969 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1970                                       enum transcoder cpu_transcoder)
1971 {
1972         u32 val, pipeconf_val;
1973
1974         /* PCH only available on ILK+ */
1975         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1976
1977         /* FDI must be feeding us bits for PCH ports */
1978         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1979         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1980
1981         /* Workaround: set timing override bit. */
1982         val = I915_READ(_TRANSA_CHICKEN2);
1983         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1984         I915_WRITE(_TRANSA_CHICKEN2, val);
1985
1986         val = TRANS_ENABLE;
1987         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1988
1989         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1990             PIPECONF_INTERLACED_ILK)
1991                 val |= TRANS_INTERLACED;
1992         else
1993                 val |= TRANS_PROGRESSIVE;
1994
1995         I915_WRITE(LPT_TRANSCONF, val);
1996         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1997                 DRM_ERROR("Failed to enable PCH transcoder\n");
1998 }
1999
2000 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2001                                             enum pipe pipe)
2002 {
2003         struct drm_device *dev = dev_priv->dev;
2004         uint32_t reg, val;
2005
2006         /* FDI relies on the transcoder */
2007         assert_fdi_tx_disabled(dev_priv, pipe);
2008         assert_fdi_rx_disabled(dev_priv, pipe);
2009
2010         /* Ports must be off as well */
2011         assert_pch_ports_disabled(dev_priv, pipe);
2012
2013         reg = PCH_TRANSCONF(pipe);
2014         val = I915_READ(reg);
2015         val &= ~TRANS_ENABLE;
2016         I915_WRITE(reg, val);
2017         /* wait for PCH transcoder off, transcoder state */
2018         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2019                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2020
2021         if (!HAS_PCH_IBX(dev)) {
2022                 /* Workaround: Clear the timing override chicken bit again. */
2023                 reg = TRANS_CHICKEN2(pipe);
2024                 val = I915_READ(reg);
2025                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2026                 I915_WRITE(reg, val);
2027         }
2028 }
2029
2030 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2031 {
2032         u32 val;
2033
2034         val = I915_READ(LPT_TRANSCONF);
2035         val &= ~TRANS_ENABLE;
2036         I915_WRITE(LPT_TRANSCONF, val);
2037         /* wait for PCH transcoder off, transcoder state */
2038         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2039                 DRM_ERROR("Failed to disable PCH transcoder\n");
2040
2041         /* Workaround: clear timing override bit. */
2042         val = I915_READ(_TRANSA_CHICKEN2);
2043         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2044         I915_WRITE(_TRANSA_CHICKEN2, val);
2045 }
2046
2047 /**
2048  * intel_enable_pipe - enable a pipe, asserting requirements
2049  * @crtc: crtc responsible for the pipe
2050  *
2051  * Enable @crtc's pipe, making sure that various hardware specific requirements
2052  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2053  */
2054 static void intel_enable_pipe(struct intel_crtc *crtc)
2055 {
2056         struct drm_device *dev = crtc->base.dev;
2057         struct drm_i915_private *dev_priv = dev->dev_private;
2058         enum pipe pipe = crtc->pipe;
2059         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2060                                                                       pipe);
2061         enum pipe pch_transcoder;
2062         int reg;
2063         u32 val;
2064
2065         assert_planes_disabled(dev_priv, pipe);
2066         assert_cursor_disabled(dev_priv, pipe);
2067         assert_sprites_disabled(dev_priv, pipe);
2068
2069         if (HAS_PCH_LPT(dev_priv->dev))
2070                 pch_transcoder = TRANSCODER_A;
2071         else
2072                 pch_transcoder = pipe;
2073
2074         /*
2075          * A pipe without a PLL won't actually be able to drive bits from
2076          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2077          * need the check.
2078          */
2079         if (!HAS_PCH_SPLIT(dev_priv->dev))
2080                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2081                         assert_dsi_pll_enabled(dev_priv);
2082                 else
2083                         assert_pll_enabled(dev_priv, pipe);
2084         else {
2085                 if (crtc->config->has_pch_encoder) {
2086                         /* if driving the PCH, we need FDI enabled */
2087                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2088                         assert_fdi_tx_pll_enabled(dev_priv,
2089                                                   (enum pipe) cpu_transcoder);
2090                 }
2091                 /* FIXME: assert CPU port conditions for SNB+ */
2092         }
2093
2094         reg = PIPECONF(cpu_transcoder);
2095         val = I915_READ(reg);
2096         if (val & PIPECONF_ENABLE) {
2097                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2098                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2099                 return;
2100         }
2101
2102         I915_WRITE(reg, val | PIPECONF_ENABLE);
2103         POSTING_READ(reg);
2104 }
2105
2106 /**
2107  * intel_disable_pipe - disable a pipe, asserting requirements
2108  * @crtc: crtc whose pipes is to be disabled
2109  *
2110  * Disable the pipe of @crtc, making sure that various hardware
2111  * specific requirements are met, if applicable, e.g. plane
2112  * disabled, panel fitter off, etc.
2113  *
2114  * Will wait until the pipe has shut down before returning.
2115  */
2116 static void intel_disable_pipe(struct intel_crtc *crtc)
2117 {
2118         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2119         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2120         enum pipe pipe = crtc->pipe;
2121         int reg;
2122         u32 val;
2123
2124         /*
2125          * Make sure planes won't keep trying to pump pixels to us,
2126          * or we might hang the display.
2127          */
2128         assert_planes_disabled(dev_priv, pipe);
2129         assert_cursor_disabled(dev_priv, pipe);
2130         assert_sprites_disabled(dev_priv, pipe);
2131
2132         reg = PIPECONF(cpu_transcoder);
2133         val = I915_READ(reg);
2134         if ((val & PIPECONF_ENABLE) == 0)
2135                 return;
2136
2137         /*
2138          * Double wide has implications for planes
2139          * so best keep it disabled when not needed.
2140          */
2141         if (crtc->config->double_wide)
2142                 val &= ~PIPECONF_DOUBLE_WIDE;
2143
2144         /* Don't disable pipe or pipe PLLs if needed */
2145         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2146             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2147                 val &= ~PIPECONF_ENABLE;
2148
2149         I915_WRITE(reg, val);
2150         if ((val & PIPECONF_ENABLE) == 0)
2151                 intel_wait_for_pipe_off(crtc);
2152 }
2153
2154 /*
2155  * Plane regs are double buffered, going from enabled->disabled needs a
2156  * trigger in order to latch.  The display address reg provides this.
2157  */
2158 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2159                                enum plane plane)
2160 {
2161         struct drm_device *dev = dev_priv->dev;
2162         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2163
2164         I915_WRITE(reg, I915_READ(reg));
2165         POSTING_READ(reg);
2166 }
2167
2168 /**
2169  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2170  * @plane:  plane to be enabled
2171  * @crtc: crtc for the plane
2172  *
2173  * Enable @plane on @crtc, making sure that the pipe is running first.
2174  */
2175 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2176                                           struct drm_crtc *crtc)
2177 {
2178         struct drm_device *dev = plane->dev;
2179         struct drm_i915_private *dev_priv = dev->dev_private;
2180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181
2182         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2183         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2184
2185         if (intel_crtc->primary_enabled)
2186                 return;
2187
2188         intel_crtc->primary_enabled = true;
2189
2190         dev_priv->display.update_primary_plane(crtc, plane->fb,
2191                                                crtc->x, crtc->y);
2192
2193         /*
2194          * BDW signals flip done immediately if the plane
2195          * is disabled, even if the plane enable is already
2196          * armed to occur at the next vblank :(
2197          */
2198         if (IS_BROADWELL(dev))
2199                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2200 }
2201
2202 /**
2203  * intel_disable_primary_hw_plane - disable the primary hardware plane
2204  * @plane: plane to be disabled
2205  * @crtc: crtc for the plane
2206  *
2207  * Disable @plane on @crtc, making sure that the pipe is running first.
2208  */
2209 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2210                                            struct drm_crtc *crtc)
2211 {
2212         struct drm_device *dev = plane->dev;
2213         struct drm_i915_private *dev_priv = dev->dev_private;
2214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2215
2216         if (WARN_ON(!intel_crtc->active))
2217                 return;
2218
2219         if (!intel_crtc->primary_enabled)
2220                 return;
2221
2222         intel_crtc->primary_enabled = false;
2223
2224         dev_priv->display.update_primary_plane(crtc, plane->fb,
2225                                                crtc->x, crtc->y);
2226 }
2227
2228 static bool need_vtd_wa(struct drm_device *dev)
2229 {
2230 #ifdef CONFIG_INTEL_IOMMU
2231         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2232                 return true;
2233 #endif
2234         return false;
2235 }
2236
2237 unsigned int
2238 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2239                   uint64_t fb_format_modifier)
2240 {
2241         unsigned int tile_height;
2242         uint32_t pixel_bytes;
2243
2244         switch (fb_format_modifier) {
2245         case DRM_FORMAT_MOD_NONE:
2246                 tile_height = 1;
2247                 break;
2248         case I915_FORMAT_MOD_X_TILED:
2249                 tile_height = IS_GEN2(dev) ? 16 : 8;
2250                 break;
2251         case I915_FORMAT_MOD_Y_TILED:
2252                 tile_height = 32;
2253                 break;
2254         case I915_FORMAT_MOD_Yf_TILED:
2255                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2256                 switch (pixel_bytes) {
2257                 default:
2258                 case 1:
2259                         tile_height = 64;
2260                         break;
2261                 case 2:
2262                 case 4:
2263                         tile_height = 32;
2264                         break;
2265                 case 8:
2266                         tile_height = 16;
2267                         break;
2268                 case 16:
2269                         WARN_ONCE(1,
2270                                   "128-bit pixels are not supported for display!");
2271                         tile_height = 16;
2272                         break;
2273                 }
2274                 break;
2275         default:
2276                 MISSING_CASE(fb_format_modifier);
2277                 tile_height = 1;
2278                 break;
2279         }
2280
2281         return tile_height;
2282 }
2283
2284 unsigned int
2285 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2286                       uint32_t pixel_format, uint64_t fb_format_modifier)
2287 {
2288         return ALIGN(height, intel_tile_height(dev, pixel_format,
2289                                                fb_format_modifier));
2290 }
2291
2292 static int
2293 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2294                         const struct drm_plane_state *plane_state)
2295 {
2296         struct intel_rotation_info *info = &view->rotation_info;
2297         static const struct i915_ggtt_view rotated_view =
2298                                 { .type = I915_GGTT_VIEW_ROTATED };
2299
2300         *view = i915_ggtt_view_normal;
2301
2302         if (!plane_state)
2303                 return 0;
2304
2305         if (!intel_rotation_90_or_270(plane_state->rotation))
2306                 return 0;
2307
2308         *view = rotated_view;
2309
2310         info->height = fb->height;
2311         info->pixel_format = fb->pixel_format;
2312         info->pitch = fb->pitches[0];
2313         info->fb_modifier = fb->modifier[0];
2314
2315         if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2316               info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2317                 DRM_DEBUG_KMS(
2318                               "Y or Yf tiling is needed for 90/270 rotation!\n");
2319                 return -EINVAL;
2320         }
2321
2322         return 0;
2323 }
2324
2325 int
2326 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2327                            struct drm_framebuffer *fb,
2328                            const struct drm_plane_state *plane_state,
2329                            struct intel_engine_cs *pipelined)
2330 {
2331         struct drm_device *dev = fb->dev;
2332         struct drm_i915_private *dev_priv = dev->dev_private;
2333         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2334         struct i915_ggtt_view view;
2335         u32 alignment;
2336         int ret;
2337
2338         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2339
2340         switch (fb->modifier[0]) {
2341         case DRM_FORMAT_MOD_NONE:
2342                 if (INTEL_INFO(dev)->gen >= 9)
2343                         alignment = 256 * 1024;
2344                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2345                         alignment = 128 * 1024;
2346                 else if (INTEL_INFO(dev)->gen >= 4)
2347                         alignment = 4 * 1024;
2348                 else
2349                         alignment = 64 * 1024;
2350                 break;
2351         case I915_FORMAT_MOD_X_TILED:
2352                 if (INTEL_INFO(dev)->gen >= 9)
2353                         alignment = 256 * 1024;
2354                 else {
2355                         /* pin() will align the object as required by fence */
2356                         alignment = 0;
2357                 }
2358                 break;
2359         case I915_FORMAT_MOD_Y_TILED:
2360         case I915_FORMAT_MOD_Yf_TILED:
2361                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2362                           "Y tiling bo slipped through, driver bug!\n"))
2363                         return -EINVAL;
2364                 alignment = 1 * 1024 * 1024;
2365                 break;
2366         default:
2367                 MISSING_CASE(fb->modifier[0]);
2368                 return -EINVAL;
2369         }
2370
2371         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2372         if (ret)
2373                 return ret;
2374
2375         /* Note that the w/a also requires 64 PTE of padding following the
2376          * bo. We currently fill all unused PTE with the shadow page and so
2377          * we should always have valid PTE following the scanout preventing
2378          * the VT-d warning.
2379          */
2380         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2381                 alignment = 256 * 1024;
2382
2383         /*
2384          * Global gtt pte registers are special registers which actually forward
2385          * writes to a chunk of system memory. Which means that there is no risk
2386          * that the register values disappear as soon as we call
2387          * intel_runtime_pm_put(), so it is correct to wrap only the
2388          * pin/unpin/fence and not more.
2389          */
2390         intel_runtime_pm_get(dev_priv);
2391
2392         dev_priv->mm.interruptible = false;
2393         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2394                                                    &view);
2395         if (ret)
2396                 goto err_interruptible;
2397
2398         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2399          * fence, whereas 965+ only requires a fence if using
2400          * framebuffer compression.  For simplicity, we always install
2401          * a fence as the cost is not that onerous.
2402          */
2403         ret = i915_gem_object_get_fence(obj);
2404         if (ret)
2405                 goto err_unpin;
2406
2407         i915_gem_object_pin_fence(obj);
2408
2409         dev_priv->mm.interruptible = true;
2410         intel_runtime_pm_put(dev_priv);
2411         return 0;
2412
2413 err_unpin:
2414         i915_gem_object_unpin_from_display_plane(obj, &view);
2415 err_interruptible:
2416         dev_priv->mm.interruptible = true;
2417         intel_runtime_pm_put(dev_priv);
2418         return ret;
2419 }
2420
2421 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2422                                const struct drm_plane_state *plane_state)
2423 {
2424         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2425         struct i915_ggtt_view view;
2426         int ret;
2427
2428         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2429
2430         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2431         WARN_ONCE(ret, "Couldn't get view from plane state!");
2432
2433         i915_gem_object_unpin_fence(obj);
2434         i915_gem_object_unpin_from_display_plane(obj, &view);
2435 }
2436
2437 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2438  * is assumed to be a power-of-two. */
2439 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2440                                              unsigned int tiling_mode,
2441                                              unsigned int cpp,
2442                                              unsigned int pitch)
2443 {
2444         if (tiling_mode != I915_TILING_NONE) {
2445                 unsigned int tile_rows, tiles;
2446
2447                 tile_rows = *y / 8;
2448                 *y %= 8;
2449
2450                 tiles = *x / (512/cpp);
2451                 *x %= 512/cpp;
2452
2453                 return tile_rows * pitch * 8 + tiles * 4096;
2454         } else {
2455                 unsigned int offset;
2456
2457                 offset = *y * pitch + *x * cpp;
2458                 *y = 0;
2459                 *x = (offset & 4095) / cpp;
2460                 return offset & -4096;
2461         }
2462 }
2463
2464 static int i9xx_format_to_fourcc(int format)
2465 {
2466         switch (format) {
2467         case DISPPLANE_8BPP:
2468                 return DRM_FORMAT_C8;
2469         case DISPPLANE_BGRX555:
2470                 return DRM_FORMAT_XRGB1555;
2471         case DISPPLANE_BGRX565:
2472                 return DRM_FORMAT_RGB565;
2473         default:
2474         case DISPPLANE_BGRX888:
2475                 return DRM_FORMAT_XRGB8888;
2476         case DISPPLANE_RGBX888:
2477                 return DRM_FORMAT_XBGR8888;
2478         case DISPPLANE_BGRX101010:
2479                 return DRM_FORMAT_XRGB2101010;
2480         case DISPPLANE_RGBX101010:
2481                 return DRM_FORMAT_XBGR2101010;
2482         }
2483 }
2484
2485 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2486 {
2487         switch (format) {
2488         case PLANE_CTL_FORMAT_RGB_565:
2489                 return DRM_FORMAT_RGB565;
2490         default:
2491         case PLANE_CTL_FORMAT_XRGB_8888:
2492                 if (rgb_order) {
2493                         if (alpha)
2494                                 return DRM_FORMAT_ABGR8888;
2495                         else
2496                                 return DRM_FORMAT_XBGR8888;
2497                 } else {
2498                         if (alpha)
2499                                 return DRM_FORMAT_ARGB8888;
2500                         else
2501                                 return DRM_FORMAT_XRGB8888;
2502                 }
2503         case PLANE_CTL_FORMAT_XRGB_2101010:
2504                 if (rgb_order)
2505                         return DRM_FORMAT_XBGR2101010;
2506                 else
2507                         return DRM_FORMAT_XRGB2101010;
2508         }
2509 }
2510
2511 static bool
2512 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2513                               struct intel_initial_plane_config *plane_config)
2514 {
2515         struct drm_device *dev = crtc->base.dev;
2516         struct drm_i915_gem_object *obj = NULL;
2517         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2518         struct drm_framebuffer *fb = &plane_config->fb->base;
2519         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2520         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2521                                     PAGE_SIZE);
2522
2523         size_aligned -= base_aligned;
2524
2525         if (plane_config->size == 0)
2526                 return false;
2527
2528         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2529                                                              base_aligned,
2530                                                              base_aligned,
2531                                                              size_aligned);
2532         if (!obj)
2533                 return false;
2534
2535         obj->tiling_mode = plane_config->tiling;
2536         if (obj->tiling_mode == I915_TILING_X)
2537                 obj->stride = fb->pitches[0];
2538
2539         mode_cmd.pixel_format = fb->pixel_format;
2540         mode_cmd.width = fb->width;
2541         mode_cmd.height = fb->height;
2542         mode_cmd.pitches[0] = fb->pitches[0];
2543         mode_cmd.modifier[0] = fb->modifier[0];
2544         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2545
2546         mutex_lock(&dev->struct_mutex);
2547         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2548                                    &mode_cmd, obj)) {
2549                 DRM_DEBUG_KMS("intel fb init failed\n");
2550                 goto out_unref_obj;
2551         }
2552         mutex_unlock(&dev->struct_mutex);
2553
2554         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2555         return true;
2556
2557 out_unref_obj:
2558         drm_gem_object_unreference(&obj->base);
2559         mutex_unlock(&dev->struct_mutex);
2560         return false;
2561 }
2562
2563 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2564 static void
2565 update_state_fb(struct drm_plane *plane)
2566 {
2567         if (plane->fb == plane->state->fb)
2568                 return;
2569
2570         if (plane->state->fb)
2571                 drm_framebuffer_unreference(plane->state->fb);
2572         plane->state->fb = plane->fb;
2573         if (plane->state->fb)
2574                 drm_framebuffer_reference(plane->state->fb);
2575 }
2576
2577 static void
2578 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2579                              struct intel_initial_plane_config *plane_config)
2580 {
2581         struct drm_device *dev = intel_crtc->base.dev;
2582         struct drm_i915_private *dev_priv = dev->dev_private;
2583         struct drm_crtc *c;
2584         struct intel_crtc *i;
2585         struct drm_i915_gem_object *obj;
2586         struct drm_plane *primary = intel_crtc->base.primary;
2587         struct drm_framebuffer *fb;
2588
2589         if (!plane_config->fb)
2590                 return;
2591
2592         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2593                 fb = &plane_config->fb->base;
2594                 goto valid_fb;
2595         }
2596
2597         kfree(plane_config->fb);
2598
2599         /*
2600          * Failed to alloc the obj, check to see if we should share
2601          * an fb with another CRTC instead
2602          */
2603         for_each_crtc(dev, c) {
2604                 i = to_intel_crtc(c);
2605
2606                 if (c == &intel_crtc->base)
2607                         continue;
2608
2609                 if (!i->active)
2610                         continue;
2611
2612                 fb = c->primary->fb;
2613                 if (!fb)
2614                         continue;
2615
2616                 obj = intel_fb_obj(fb);
2617                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2618                         drm_framebuffer_reference(fb);
2619                         goto valid_fb;
2620                 }
2621         }
2622
2623         return;
2624
2625 valid_fb:
2626         obj = intel_fb_obj(fb);
2627         if (obj->tiling_mode != I915_TILING_NONE)
2628                 dev_priv->preserve_bios_swizzle = true;
2629
2630         primary->fb = fb;
2631         primary->state->crtc = &intel_crtc->base;
2632         primary->crtc = &intel_crtc->base;
2633         update_state_fb(primary);
2634         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2635 }
2636
2637 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2638                                       struct drm_framebuffer *fb,
2639                                       int x, int y)
2640 {
2641         struct drm_device *dev = crtc->dev;
2642         struct drm_i915_private *dev_priv = dev->dev_private;
2643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2644         struct drm_i915_gem_object *obj;
2645         int plane = intel_crtc->plane;
2646         unsigned long linear_offset;
2647         u32 dspcntr;
2648         u32 reg = DSPCNTR(plane);
2649         int pixel_size;
2650
2651         if (!intel_crtc->primary_enabled) {
2652                 I915_WRITE(reg, 0);
2653                 if (INTEL_INFO(dev)->gen >= 4)
2654                         I915_WRITE(DSPSURF(plane), 0);
2655                 else
2656                         I915_WRITE(DSPADDR(plane), 0);
2657                 POSTING_READ(reg);
2658                 return;
2659         }
2660
2661         obj = intel_fb_obj(fb);
2662         if (WARN_ON(obj == NULL))
2663                 return;
2664
2665         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2666
2667         dspcntr = DISPPLANE_GAMMA_ENABLE;
2668
2669         dspcntr |= DISPLAY_PLANE_ENABLE;
2670
2671         if (INTEL_INFO(dev)->gen < 4) {
2672                 if (intel_crtc->pipe == PIPE_B)
2673                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2674
2675                 /* pipesrc and dspsize control the size that is scaled from,
2676                  * which should always be the user's requested size.
2677                  */
2678                 I915_WRITE(DSPSIZE(plane),
2679                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680                            (intel_crtc->config->pipe_src_w - 1));
2681                 I915_WRITE(DSPPOS(plane), 0);
2682         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683                 I915_WRITE(PRIMSIZE(plane),
2684                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685                            (intel_crtc->config->pipe_src_w - 1));
2686                 I915_WRITE(PRIMPOS(plane), 0);
2687                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2688         }
2689
2690         switch (fb->pixel_format) {
2691         case DRM_FORMAT_C8:
2692                 dspcntr |= DISPPLANE_8BPP;
2693                 break;
2694         case DRM_FORMAT_XRGB1555:
2695         case DRM_FORMAT_ARGB1555:
2696                 dspcntr |= DISPPLANE_BGRX555;
2697                 break;
2698         case DRM_FORMAT_RGB565:
2699                 dspcntr |= DISPPLANE_BGRX565;
2700                 break;
2701         case DRM_FORMAT_XRGB8888:
2702         case DRM_FORMAT_ARGB8888:
2703                 dspcntr |= DISPPLANE_BGRX888;
2704                 break;
2705         case DRM_FORMAT_XBGR8888:
2706         case DRM_FORMAT_ABGR8888:
2707                 dspcntr |= DISPPLANE_RGBX888;
2708                 break;
2709         case DRM_FORMAT_XRGB2101010:
2710         case DRM_FORMAT_ARGB2101010:
2711                 dspcntr |= DISPPLANE_BGRX101010;
2712                 break;
2713         case DRM_FORMAT_XBGR2101010:
2714         case DRM_FORMAT_ABGR2101010:
2715                 dspcntr |= DISPPLANE_RGBX101010;
2716                 break;
2717         default:
2718                 BUG();
2719         }
2720
2721         if (INTEL_INFO(dev)->gen >= 4 &&
2722             obj->tiling_mode != I915_TILING_NONE)
2723                 dspcntr |= DISPPLANE_TILED;
2724
2725         if (IS_G4X(dev))
2726                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2727
2728         linear_offset = y * fb->pitches[0] + x * pixel_size;
2729
2730         if (INTEL_INFO(dev)->gen >= 4) {
2731                 intel_crtc->dspaddr_offset =
2732                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2733                                                        pixel_size,
2734                                                        fb->pitches[0]);
2735                 linear_offset -= intel_crtc->dspaddr_offset;
2736         } else {
2737                 intel_crtc->dspaddr_offset = linear_offset;
2738         }
2739
2740         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2741                 dspcntr |= DISPPLANE_ROTATE_180;
2742
2743                 x += (intel_crtc->config->pipe_src_w - 1);
2744                 y += (intel_crtc->config->pipe_src_h - 1);
2745
2746                 /* Finding the last pixel of the last line of the display
2747                 data and adding to linear_offset*/
2748                 linear_offset +=
2749                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2750                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2751         }
2752
2753         I915_WRITE(reg, dspcntr);
2754
2755         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2756         if (INTEL_INFO(dev)->gen >= 4) {
2757                 I915_WRITE(DSPSURF(plane),
2758                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2759                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2760                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2761         } else
2762                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2763         POSTING_READ(reg);
2764 }
2765
2766 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2767                                           struct drm_framebuffer *fb,
2768                                           int x, int y)
2769 {
2770         struct drm_device *dev = crtc->dev;
2771         struct drm_i915_private *dev_priv = dev->dev_private;
2772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773         struct drm_i915_gem_object *obj;
2774         int plane = intel_crtc->plane;
2775         unsigned long linear_offset;
2776         u32 dspcntr;
2777         u32 reg = DSPCNTR(plane);
2778         int pixel_size;
2779
2780         if (!intel_crtc->primary_enabled) {
2781                 I915_WRITE(reg, 0);
2782                 I915_WRITE(DSPSURF(plane), 0);
2783                 POSTING_READ(reg);
2784                 return;
2785         }
2786
2787         obj = intel_fb_obj(fb);
2788         if (WARN_ON(obj == NULL))
2789                 return;
2790
2791         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2792
2793         dspcntr = DISPPLANE_GAMMA_ENABLE;
2794
2795         dspcntr |= DISPLAY_PLANE_ENABLE;
2796
2797         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2798                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2799
2800         switch (fb->pixel_format) {
2801         case DRM_FORMAT_C8:
2802                 dspcntr |= DISPPLANE_8BPP;
2803                 break;
2804         case DRM_FORMAT_RGB565:
2805                 dspcntr |= DISPPLANE_BGRX565;
2806                 break;
2807         case DRM_FORMAT_XRGB8888:
2808         case DRM_FORMAT_ARGB8888:
2809                 dspcntr |= DISPPLANE_BGRX888;
2810                 break;
2811         case DRM_FORMAT_XBGR8888:
2812         case DRM_FORMAT_ABGR8888:
2813                 dspcntr |= DISPPLANE_RGBX888;
2814                 break;
2815         case DRM_FORMAT_XRGB2101010:
2816         case DRM_FORMAT_ARGB2101010:
2817                 dspcntr |= DISPPLANE_BGRX101010;
2818                 break;
2819         case DRM_FORMAT_XBGR2101010:
2820         case DRM_FORMAT_ABGR2101010:
2821                 dspcntr |= DISPPLANE_RGBX101010;
2822                 break;
2823         default:
2824                 BUG();
2825         }
2826
2827         if (obj->tiling_mode != I915_TILING_NONE)
2828                 dspcntr |= DISPPLANE_TILED;
2829
2830         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2831                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2832
2833         linear_offset = y * fb->pitches[0] + x * pixel_size;
2834         intel_crtc->dspaddr_offset =
2835                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2836                                                pixel_size,
2837                                                fb->pitches[0]);
2838         linear_offset -= intel_crtc->dspaddr_offset;
2839         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2840                 dspcntr |= DISPPLANE_ROTATE_180;
2841
2842                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2843                         x += (intel_crtc->config->pipe_src_w - 1);
2844                         y += (intel_crtc->config->pipe_src_h - 1);
2845
2846                         /* Finding the last pixel of the last line of the display
2847                         data and adding to linear_offset*/
2848                         linear_offset +=
2849                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2850                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2851                 }
2852         }
2853
2854         I915_WRITE(reg, dspcntr);
2855
2856         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2857         I915_WRITE(DSPSURF(plane),
2858                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2859         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2860                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2861         } else {
2862                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2863                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2864         }
2865         POSTING_READ(reg);
2866 }
2867
2868 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2869                               uint32_t pixel_format)
2870 {
2871         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2872
2873         /*
2874          * The stride is either expressed as a multiple of 64 bytes
2875          * chunks for linear buffers or in number of tiles for tiled
2876          * buffers.
2877          */
2878         switch (fb_modifier) {
2879         case DRM_FORMAT_MOD_NONE:
2880                 return 64;
2881         case I915_FORMAT_MOD_X_TILED:
2882                 if (INTEL_INFO(dev)->gen == 2)
2883                         return 128;
2884                 return 512;
2885         case I915_FORMAT_MOD_Y_TILED:
2886                 /* No need to check for old gens and Y tiling since this is
2887                  * about the display engine and those will be blocked before
2888                  * we get here.
2889                  */
2890                 return 128;
2891         case I915_FORMAT_MOD_Yf_TILED:
2892                 if (bits_per_pixel == 8)
2893                         return 64;
2894                 else
2895                         return 128;
2896         default:
2897                 MISSING_CASE(fb_modifier);
2898                 return 64;
2899         }
2900 }
2901
2902 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2903                                      struct drm_i915_gem_object *obj)
2904 {
2905         enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
2906
2907         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2908                 view = I915_GGTT_VIEW_ROTATED;
2909
2910         return i915_gem_obj_ggtt_offset_view(obj, view);
2911 }
2912
2913 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2914                                          struct drm_framebuffer *fb,
2915                                          int x, int y)
2916 {
2917         struct drm_device *dev = crtc->dev;
2918         struct drm_i915_private *dev_priv = dev->dev_private;
2919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2920         struct drm_i915_gem_object *obj;
2921         int pipe = intel_crtc->pipe;
2922         u32 plane_ctl, stride_div;
2923         unsigned long surf_addr;
2924
2925         if (!intel_crtc->primary_enabled) {
2926                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2927                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2928                 POSTING_READ(PLANE_CTL(pipe, 0));
2929                 return;
2930         }
2931
2932         plane_ctl = PLANE_CTL_ENABLE |
2933                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2934                     PLANE_CTL_PIPE_CSC_ENABLE;
2935
2936         switch (fb->pixel_format) {
2937         case DRM_FORMAT_RGB565:
2938                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2939                 break;
2940         case DRM_FORMAT_XRGB8888:
2941                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2942                 break;
2943         case DRM_FORMAT_ARGB8888:
2944                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2945                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2946                 break;
2947         case DRM_FORMAT_XBGR8888:
2948                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2949                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2950                 break;
2951         case DRM_FORMAT_ABGR8888:
2952                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2953                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2954                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2955                 break;
2956         case DRM_FORMAT_XRGB2101010:
2957                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2958                 break;
2959         case DRM_FORMAT_XBGR2101010:
2960                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2961                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2962                 break;
2963         default:
2964                 BUG();
2965         }
2966
2967         switch (fb->modifier[0]) {
2968         case DRM_FORMAT_MOD_NONE:
2969                 break;
2970         case I915_FORMAT_MOD_X_TILED:
2971                 plane_ctl |= PLANE_CTL_TILED_X;
2972                 break;
2973         case I915_FORMAT_MOD_Y_TILED:
2974                 plane_ctl |= PLANE_CTL_TILED_Y;
2975                 break;
2976         case I915_FORMAT_MOD_Yf_TILED:
2977                 plane_ctl |= PLANE_CTL_TILED_YF;
2978                 break;
2979         default:
2980                 MISSING_CASE(fb->modifier[0]);
2981         }
2982
2983         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2984         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2985                 plane_ctl |= PLANE_CTL_ROTATE_180;
2986
2987         obj = intel_fb_obj(fb);
2988         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2989                                                fb->pixel_format);
2990         surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
2991
2992         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2993         I915_WRITE(PLANE_POS(pipe, 0), 0);
2994         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2995         I915_WRITE(PLANE_SIZE(pipe, 0),
2996                    (intel_crtc->config->pipe_src_h - 1) << 16 |
2997                    (intel_crtc->config->pipe_src_w - 1));
2998         I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2999         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3000
3001         POSTING_READ(PLANE_SURF(pipe, 0));
3002 }
3003
3004 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3005 static int
3006 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3007                            int x, int y, enum mode_set_atomic state)
3008 {
3009         struct drm_device *dev = crtc->dev;
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011
3012         if (dev_priv->display.disable_fbc)
3013                 dev_priv->display.disable_fbc(dev);
3014
3015         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3016
3017         return 0;
3018 }
3019
3020 static void intel_complete_page_flips(struct drm_device *dev)
3021 {
3022         struct drm_crtc *crtc;
3023
3024         for_each_crtc(dev, crtc) {
3025                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3026                 enum plane plane = intel_crtc->plane;
3027
3028                 intel_prepare_page_flip(dev, plane);
3029                 intel_finish_page_flip_plane(dev, plane);
3030         }
3031 }
3032
3033 static void intel_update_primary_planes(struct drm_device *dev)
3034 {
3035         struct drm_i915_private *dev_priv = dev->dev_private;
3036         struct drm_crtc *crtc;
3037
3038         for_each_crtc(dev, crtc) {
3039                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3040
3041                 drm_modeset_lock(&crtc->mutex, NULL);
3042                 /*
3043                  * FIXME: Once we have proper support for primary planes (and
3044                  * disabling them without disabling the entire crtc) allow again
3045                  * a NULL crtc->primary->fb.
3046                  */
3047                 if (intel_crtc->active && crtc->primary->fb)
3048                         dev_priv->display.update_primary_plane(crtc,
3049                                                                crtc->primary->fb,
3050                                                                crtc->x,
3051                                                                crtc->y);
3052                 drm_modeset_unlock(&crtc->mutex);
3053         }
3054 }
3055
3056 void intel_prepare_reset(struct drm_device *dev)
3057 {
3058         struct drm_i915_private *dev_priv = to_i915(dev);
3059         struct intel_crtc *crtc;
3060
3061         /* no reset support for gen2 */
3062         if (IS_GEN2(dev))
3063                 return;
3064
3065         /* reset doesn't touch the display */
3066         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3067                 return;
3068
3069         drm_modeset_lock_all(dev);
3070
3071         /*
3072          * Disabling the crtcs gracefully seems nicer. Also the
3073          * g33 docs say we should at least disable all the planes.
3074          */
3075         for_each_intel_crtc(dev, crtc) {
3076                 if (crtc->active)
3077                         dev_priv->display.crtc_disable(&crtc->base);
3078         }
3079 }
3080
3081 void intel_finish_reset(struct drm_device *dev)
3082 {
3083         struct drm_i915_private *dev_priv = to_i915(dev);
3084
3085         /*
3086          * Flips in the rings will be nuked by the reset,
3087          * so complete all pending flips so that user space
3088          * will get its events and not get stuck.
3089          */
3090         intel_complete_page_flips(dev);
3091
3092         /* no reset support for gen2 */
3093         if (IS_GEN2(dev))
3094                 return;
3095
3096         /* reset doesn't touch the display */
3097         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3098                 /*
3099                  * Flips in the rings have been nuked by the reset,
3100                  * so update the base address of all primary
3101                  * planes to the the last fb to make sure we're
3102                  * showing the correct fb after a reset.
3103                  */
3104                 intel_update_primary_planes(dev);
3105                 return;
3106         }
3107
3108         /*
3109          * The display has been reset as well,
3110          * so need a full re-initialization.
3111          */
3112         intel_runtime_pm_disable_interrupts(dev_priv);
3113         intel_runtime_pm_enable_interrupts(dev_priv);
3114
3115         intel_modeset_init_hw(dev);
3116
3117         spin_lock_irq(&dev_priv->irq_lock);
3118         if (dev_priv->display.hpd_irq_setup)
3119                 dev_priv->display.hpd_irq_setup(dev);
3120         spin_unlock_irq(&dev_priv->irq_lock);
3121
3122         intel_modeset_setup_hw_state(dev, true);
3123
3124         intel_hpd_init(dev_priv);
3125
3126         drm_modeset_unlock_all(dev);
3127 }
3128
3129 static int
3130 intel_finish_fb(struct drm_framebuffer *old_fb)
3131 {
3132         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3133         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3134         bool was_interruptible = dev_priv->mm.interruptible;
3135         int ret;
3136
3137         /* Big Hammer, we also need to ensure that any pending
3138          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3139          * current scanout is retired before unpinning the old
3140          * framebuffer.
3141          *
3142          * This should only fail upon a hung GPU, in which case we
3143          * can safely continue.
3144          */
3145         dev_priv->mm.interruptible = false;
3146         ret = i915_gem_object_finish_gpu(obj);
3147         dev_priv->mm.interruptible = was_interruptible;
3148
3149         return ret;
3150 }
3151
3152 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3153 {
3154         struct drm_device *dev = crtc->dev;
3155         struct drm_i915_private *dev_priv = dev->dev_private;
3156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3157         bool pending;
3158
3159         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3160             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3161                 return false;
3162
3163         spin_lock_irq(&dev->event_lock);
3164         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3165         spin_unlock_irq(&dev->event_lock);
3166
3167         return pending;
3168 }
3169
3170 static void intel_update_pipe_size(struct intel_crtc *crtc)
3171 {
3172         struct drm_device *dev = crtc->base.dev;
3173         struct drm_i915_private *dev_priv = dev->dev_private;
3174         const struct drm_display_mode *adjusted_mode;
3175
3176         if (!i915.fastboot)
3177                 return;
3178
3179         /*
3180          * Update pipe size and adjust fitter if needed: the reason for this is
3181          * that in compute_mode_changes we check the native mode (not the pfit
3182          * mode) to see if we can flip rather than do a full mode set. In the
3183          * fastboot case, we'll flip, but if we don't update the pipesrc and
3184          * pfit state, we'll end up with a big fb scanned out into the wrong
3185          * sized surface.
3186          *
3187          * To fix this properly, we need to hoist the checks up into
3188          * compute_mode_changes (or above), check the actual pfit state and
3189          * whether the platform allows pfit disable with pipe active, and only
3190          * then update the pipesrc and pfit state, even on the flip path.
3191          */
3192
3193         adjusted_mode = &crtc->config->base.adjusted_mode;
3194
3195         I915_WRITE(PIPESRC(crtc->pipe),
3196                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3197                    (adjusted_mode->crtc_vdisplay - 1));
3198         if (!crtc->config->pch_pfit.enabled &&
3199             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3200              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3201                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3202                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3203                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3204         }
3205         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3206         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3207 }
3208
3209 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3210 {
3211         struct drm_device *dev = crtc->dev;
3212         struct drm_i915_private *dev_priv = dev->dev_private;
3213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3214         int pipe = intel_crtc->pipe;
3215         u32 reg, temp;
3216
3217         /* enable normal train */
3218         reg = FDI_TX_CTL(pipe);
3219         temp = I915_READ(reg);
3220         if (IS_IVYBRIDGE(dev)) {
3221                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3222                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3223         } else {
3224                 temp &= ~FDI_LINK_TRAIN_NONE;
3225                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3226         }
3227         I915_WRITE(reg, temp);
3228
3229         reg = FDI_RX_CTL(pipe);
3230         temp = I915_READ(reg);
3231         if (HAS_PCH_CPT(dev)) {
3232                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3233                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3234         } else {
3235                 temp &= ~FDI_LINK_TRAIN_NONE;
3236                 temp |= FDI_LINK_TRAIN_NONE;
3237         }
3238         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3239
3240         /* wait one idle pattern time */
3241         POSTING_READ(reg);
3242         udelay(1000);
3243
3244         /* IVB wants error correction enabled */
3245         if (IS_IVYBRIDGE(dev))
3246                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3247                            FDI_FE_ERRC_ENABLE);
3248 }
3249
3250 /* The FDI link training functions for ILK/Ibexpeak. */
3251 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3252 {
3253         struct drm_device *dev = crtc->dev;
3254         struct drm_i915_private *dev_priv = dev->dev_private;
3255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3256         int pipe = intel_crtc->pipe;
3257         u32 reg, temp, tries;
3258
3259         /* FDI needs bits from pipe first */
3260         assert_pipe_enabled(dev_priv, pipe);
3261
3262         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3263            for train result */
3264         reg = FDI_RX_IMR(pipe);
3265         temp = I915_READ(reg);
3266         temp &= ~FDI_RX_SYMBOL_LOCK;
3267         temp &= ~FDI_RX_BIT_LOCK;
3268         I915_WRITE(reg, temp);
3269         I915_READ(reg);
3270         udelay(150);
3271
3272         /* enable CPU FDI TX and PCH FDI RX */
3273         reg = FDI_TX_CTL(pipe);
3274         temp = I915_READ(reg);
3275         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3276         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3277         temp &= ~FDI_LINK_TRAIN_NONE;
3278         temp |= FDI_LINK_TRAIN_PATTERN_1;
3279         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3280
3281         reg = FDI_RX_CTL(pipe);
3282         temp = I915_READ(reg);
3283         temp &= ~FDI_LINK_TRAIN_NONE;
3284         temp |= FDI_LINK_TRAIN_PATTERN_1;
3285         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3286
3287         POSTING_READ(reg);
3288         udelay(150);
3289
3290         /* Ironlake workaround, enable clock pointer after FDI enable*/
3291         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3292         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3293                    FDI_RX_PHASE_SYNC_POINTER_EN);
3294
3295         reg = FDI_RX_IIR(pipe);
3296         for (tries = 0; tries < 5; tries++) {
3297                 temp = I915_READ(reg);
3298                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3299
3300                 if ((temp & FDI_RX_BIT_LOCK)) {
3301                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3302                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3303                         break;
3304                 }
3305         }
3306         if (tries == 5)
3307                 DRM_ERROR("FDI train 1 fail!\n");
3308
3309         /* Train 2 */
3310         reg = FDI_TX_CTL(pipe);
3311         temp = I915_READ(reg);
3312         temp &= ~FDI_LINK_TRAIN_NONE;
3313         temp |= FDI_LINK_TRAIN_PATTERN_2;
3314         I915_WRITE(reg, temp);
3315
3316         reg = FDI_RX_CTL(pipe);
3317         temp = I915_READ(reg);
3318         temp &= ~FDI_LINK_TRAIN_NONE;
3319         temp |= FDI_LINK_TRAIN_PATTERN_2;
3320         I915_WRITE(reg, temp);
3321
3322         POSTING_READ(reg);
3323         udelay(150);
3324
3325         reg = FDI_RX_IIR(pipe);
3326         for (tries = 0; tries < 5; tries++) {
3327                 temp = I915_READ(reg);
3328                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3329
3330                 if (temp & FDI_RX_SYMBOL_LOCK) {
3331                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3332                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3333                         break;
3334                 }
3335         }
3336         if (tries == 5)
3337                 DRM_ERROR("FDI train 2 fail!\n");
3338
3339         DRM_DEBUG_KMS("FDI train done\n");
3340
3341 }
3342
3343 static const int snb_b_fdi_train_param[] = {
3344         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3345         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3346         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3347         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3348 };
3349
3350 /* The FDI link training functions for SNB/Cougarpoint. */
3351 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3352 {
3353         struct drm_device *dev = crtc->dev;
3354         struct drm_i915_private *dev_priv = dev->dev_private;
3355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3356         int pipe = intel_crtc->pipe;
3357         u32 reg, temp, i, retry;
3358
3359         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3360            for train result */
3361         reg = FDI_RX_IMR(pipe);
3362         temp = I915_READ(reg);
3363         temp &= ~FDI_RX_SYMBOL_LOCK;
3364         temp &= ~FDI_RX_BIT_LOCK;
3365         I915_WRITE(reg, temp);
3366
3367         POSTING_READ(reg);
3368         udelay(150);
3369
3370         /* enable CPU FDI TX and PCH FDI RX */
3371         reg = FDI_TX_CTL(pipe);
3372         temp = I915_READ(reg);
3373         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3374         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3375         temp &= ~FDI_LINK_TRAIN_NONE;
3376         temp |= FDI_LINK_TRAIN_PATTERN_1;
3377         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3378         /* SNB-B */
3379         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3380         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3381
3382         I915_WRITE(FDI_RX_MISC(pipe),
3383                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3384
3385         reg = FDI_RX_CTL(pipe);
3386         temp = I915_READ(reg);
3387         if (HAS_PCH_CPT(dev)) {
3388                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3389                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3390         } else {
3391                 temp &= ~FDI_LINK_TRAIN_NONE;
3392                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3393         }
3394         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3395
3396         POSTING_READ(reg);
3397         udelay(150);
3398
3399         for (i = 0; i < 4; i++) {
3400                 reg = FDI_TX_CTL(pipe);
3401                 temp = I915_READ(reg);
3402                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3403                 temp |= snb_b_fdi_train_param[i];
3404                 I915_WRITE(reg, temp);
3405
3406                 POSTING_READ(reg);
3407                 udelay(500);
3408
3409                 for (retry = 0; retry < 5; retry++) {
3410                         reg = FDI_RX_IIR(pipe);
3411                         temp = I915_READ(reg);
3412                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3413                         if (temp & FDI_RX_BIT_LOCK) {
3414                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3415                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3416                                 break;
3417                         }
3418                         udelay(50);
3419                 }
3420                 if (retry < 5)
3421                         break;
3422         }
3423         if (i == 4)
3424                 DRM_ERROR("FDI train 1 fail!\n");
3425
3426         /* Train 2 */
3427         reg = FDI_TX_CTL(pipe);
3428         temp = I915_READ(reg);
3429         temp &= ~FDI_LINK_TRAIN_NONE;
3430         temp |= FDI_LINK_TRAIN_PATTERN_2;
3431         if (IS_GEN6(dev)) {
3432                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3433                 /* SNB-B */
3434                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3435         }
3436         I915_WRITE(reg, temp);
3437
3438         reg = FDI_RX_CTL(pipe);
3439         temp = I915_READ(reg);
3440         if (HAS_PCH_CPT(dev)) {
3441                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3442                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3443         } else {
3444                 temp &= ~FDI_LINK_TRAIN_NONE;
3445                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3446         }
3447         I915_WRITE(reg, temp);
3448
3449         POSTING_READ(reg);
3450         udelay(150);
3451
3452         for (i = 0; i < 4; i++) {
3453                 reg = FDI_TX_CTL(pipe);
3454                 temp = I915_READ(reg);
3455                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3456                 temp |= snb_b_fdi_train_param[i];
3457                 I915_WRITE(reg, temp);
3458
3459                 POSTING_READ(reg);
3460                 udelay(500);
3461
3462                 for (retry = 0; retry < 5; retry++) {
3463                         reg = FDI_RX_IIR(pipe);
3464                         temp = I915_READ(reg);
3465                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3466                         if (temp & FDI_RX_SYMBOL_LOCK) {
3467                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3468                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3469                                 break;
3470                         }
3471                         udelay(50);
3472                 }
3473                 if (retry < 5)
3474                         break;
3475         }
3476         if (i == 4)
3477                 DRM_ERROR("FDI train 2 fail!\n");
3478
3479         DRM_DEBUG_KMS("FDI train done.\n");
3480 }
3481
3482 /* Manual link training for Ivy Bridge A0 parts */
3483 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3484 {
3485         struct drm_device *dev = crtc->dev;
3486         struct drm_i915_private *dev_priv = dev->dev_private;
3487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3488         int pipe = intel_crtc->pipe;
3489         u32 reg, temp, i, j;
3490
3491         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3492            for train result */
3493         reg = FDI_RX_IMR(pipe);
3494         temp = I915_READ(reg);
3495         temp &= ~FDI_RX_SYMBOL_LOCK;
3496         temp &= ~FDI_RX_BIT_LOCK;
3497         I915_WRITE(reg, temp);
3498
3499         POSTING_READ(reg);
3500         udelay(150);
3501
3502         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3503                       I915_READ(FDI_RX_IIR(pipe)));
3504
3505         /* Try each vswing and preemphasis setting twice before moving on */
3506         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3507                 /* disable first in case we need to retry */
3508                 reg = FDI_TX_CTL(pipe);
3509                 temp = I915_READ(reg);
3510                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3511                 temp &= ~FDI_TX_ENABLE;
3512                 I915_WRITE(reg, temp);
3513
3514                 reg = FDI_RX_CTL(pipe);
3515                 temp = I915_READ(reg);
3516                 temp &= ~FDI_LINK_TRAIN_AUTO;
3517                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3518                 temp &= ~FDI_RX_ENABLE;
3519                 I915_WRITE(reg, temp);
3520
3521                 /* enable CPU FDI TX and PCH FDI RX */
3522                 reg = FDI_TX_CTL(pipe);
3523                 temp = I915_READ(reg);
3524                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3525                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3526                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3527                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3528                 temp |= snb_b_fdi_train_param[j/2];
3529                 temp |= FDI_COMPOSITE_SYNC;
3530                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3531
3532                 I915_WRITE(FDI_RX_MISC(pipe),
3533                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3534
3535                 reg = FDI_RX_CTL(pipe);
3536                 temp = I915_READ(reg);
3537                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3538                 temp |= FDI_COMPOSITE_SYNC;
3539                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3540
3541                 POSTING_READ(reg);
3542                 udelay(1); /* should be 0.5us */
3543
3544                 for (i = 0; i < 4; i++) {
3545                         reg = FDI_RX_IIR(pipe);
3546                         temp = I915_READ(reg);
3547                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3548
3549                         if (temp & FDI_RX_BIT_LOCK ||
3550                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3551                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3552                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3553                                               i);
3554                                 break;
3555                         }
3556                         udelay(1); /* should be 0.5us */
3557                 }
3558                 if (i == 4) {
3559                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3560                         continue;
3561                 }
3562
3563                 /* Train 2 */
3564                 reg = FDI_TX_CTL(pipe);
3565                 temp = I915_READ(reg);
3566                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3567                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3568                 I915_WRITE(reg, temp);
3569
3570                 reg = FDI_RX_CTL(pipe);
3571                 temp = I915_READ(reg);
3572                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3573                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3574                 I915_WRITE(reg, temp);
3575
3576                 POSTING_READ(reg);
3577                 udelay(2); /* should be 1.5us */
3578
3579                 for (i = 0; i < 4; i++) {
3580                         reg = FDI_RX_IIR(pipe);
3581                         temp = I915_READ(reg);
3582                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3583
3584                         if (temp & FDI_RX_SYMBOL_LOCK ||
3585                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3586                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3587                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3588                                               i);
3589                                 goto train_done;
3590                         }
3591                         udelay(2); /* should be 1.5us */
3592                 }
3593                 if (i == 4)
3594                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3595         }
3596
3597 train_done:
3598         DRM_DEBUG_KMS("FDI train done.\n");
3599 }
3600
3601 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3602 {
3603         struct drm_device *dev = intel_crtc->base.dev;
3604         struct drm_i915_private *dev_priv = dev->dev_private;
3605         int pipe = intel_crtc->pipe;
3606         u32 reg, temp;
3607
3608
3609         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3610         reg = FDI_RX_CTL(pipe);
3611         temp = I915_READ(reg);
3612         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3613         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3614         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3615         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3616
3617         POSTING_READ(reg);
3618         udelay(200);
3619
3620         /* Switch from Rawclk to PCDclk */
3621         temp = I915_READ(reg);
3622         I915_WRITE(reg, temp | FDI_PCDCLK);
3623
3624         POSTING_READ(reg);
3625         udelay(200);
3626
3627         /* Enable CPU FDI TX PLL, always on for Ironlake */
3628         reg = FDI_TX_CTL(pipe);
3629         temp = I915_READ(reg);
3630         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3631                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3632
3633                 POSTING_READ(reg);
3634                 udelay(100);
3635         }
3636 }
3637
3638 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3639 {
3640         struct drm_device *dev = intel_crtc->base.dev;
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642         int pipe = intel_crtc->pipe;
3643         u32 reg, temp;
3644
3645         /* Switch from PCDclk to Rawclk */
3646         reg = FDI_RX_CTL(pipe);
3647         temp = I915_READ(reg);
3648         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3649
3650         /* Disable CPU FDI TX PLL */
3651         reg = FDI_TX_CTL(pipe);
3652         temp = I915_READ(reg);
3653         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3654
3655         POSTING_READ(reg);
3656         udelay(100);
3657
3658         reg = FDI_RX_CTL(pipe);
3659         temp = I915_READ(reg);
3660         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3661
3662         /* Wait for the clocks to turn off. */
3663         POSTING_READ(reg);
3664         udelay(100);
3665 }
3666
3667 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3668 {
3669         struct drm_device *dev = crtc->dev;
3670         struct drm_i915_private *dev_priv = dev->dev_private;
3671         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3672         int pipe = intel_crtc->pipe;
3673         u32 reg, temp;
3674
3675         /* disable CPU FDI tx and PCH FDI rx */
3676         reg = FDI_TX_CTL(pipe);
3677         temp = I915_READ(reg);
3678         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3679         POSTING_READ(reg);
3680
3681         reg = FDI_RX_CTL(pipe);
3682         temp = I915_READ(reg);
3683         temp &= ~(0x7 << 16);
3684         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3685         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3686
3687         POSTING_READ(reg);
3688         udelay(100);
3689
3690         /* Ironlake workaround, disable clock pointer after downing FDI */
3691         if (HAS_PCH_IBX(dev))
3692                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3693
3694         /* still set train pattern 1 */
3695         reg = FDI_TX_CTL(pipe);
3696         temp = I915_READ(reg);
3697         temp &= ~FDI_LINK_TRAIN_NONE;
3698         temp |= FDI_LINK_TRAIN_PATTERN_1;
3699         I915_WRITE(reg, temp);
3700
3701         reg = FDI_RX_CTL(pipe);
3702         temp = I915_READ(reg);
3703         if (HAS_PCH_CPT(dev)) {
3704                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3705                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3706         } else {
3707                 temp &= ~FDI_LINK_TRAIN_NONE;
3708                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3709         }
3710         /* BPC in FDI rx is consistent with that in PIPECONF */
3711         temp &= ~(0x07 << 16);
3712         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3713         I915_WRITE(reg, temp);
3714
3715         POSTING_READ(reg);
3716         udelay(100);
3717 }
3718
3719 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3720 {
3721         struct intel_crtc *crtc;
3722
3723         /* Note that we don't need to be called with mode_config.lock here
3724          * as our list of CRTC objects is static for the lifetime of the
3725          * device and so cannot disappear as we iterate. Similarly, we can
3726          * happily treat the predicates as racy, atomic checks as userspace
3727          * cannot claim and pin a new fb without at least acquring the
3728          * struct_mutex and so serialising with us.
3729          */
3730         for_each_intel_crtc(dev, crtc) {
3731                 if (atomic_read(&crtc->unpin_work_count) == 0)
3732                         continue;
3733
3734                 if (crtc->unpin_work)
3735                         intel_wait_for_vblank(dev, crtc->pipe);
3736
3737                 return true;
3738         }
3739
3740         return false;
3741 }
3742
3743 static void page_flip_completed(struct intel_crtc *intel_crtc)
3744 {
3745         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3746         struct intel_unpin_work *work = intel_crtc->unpin_work;
3747
3748         /* ensure that the unpin work is consistent wrt ->pending. */
3749         smp_rmb();
3750         intel_crtc->unpin_work = NULL;
3751
3752         if (work->event)
3753                 drm_send_vblank_event(intel_crtc->base.dev,
3754                                       intel_crtc->pipe,
3755                                       work->event);
3756
3757         drm_crtc_vblank_put(&intel_crtc->base);
3758
3759         wake_up_all(&dev_priv->pending_flip_queue);
3760         queue_work(dev_priv->wq, &work->work);
3761
3762         trace_i915_flip_complete(intel_crtc->plane,
3763                                  work->pending_flip_obj);
3764 }
3765
3766 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3767 {
3768         struct drm_device *dev = crtc->dev;
3769         struct drm_i915_private *dev_priv = dev->dev_private;
3770
3771         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3772         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3773                                        !intel_crtc_has_pending_flip(crtc),
3774                                        60*HZ) == 0)) {
3775                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3776
3777                 spin_lock_irq(&dev->event_lock);
3778                 if (intel_crtc->unpin_work) {
3779                         WARN_ONCE(1, "Removing stuck page flip\n");
3780                         page_flip_completed(intel_crtc);
3781                 }
3782                 spin_unlock_irq(&dev->event_lock);
3783         }
3784
3785         if (crtc->primary->fb) {
3786                 mutex_lock(&dev->struct_mutex);
3787                 intel_finish_fb(crtc->primary->fb);
3788                 mutex_unlock(&dev->struct_mutex);
3789         }
3790 }
3791
3792 /* Program iCLKIP clock to the desired frequency */
3793 static void lpt_program_iclkip(struct drm_crtc *crtc)
3794 {
3795         struct drm_device *dev = crtc->dev;
3796         struct drm_i915_private *dev_priv = dev->dev_private;
3797         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3798         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3799         u32 temp;
3800
3801         mutex_lock(&dev_priv->dpio_lock);
3802
3803         /* It is necessary to ungate the pixclk gate prior to programming
3804          * the divisors, and gate it back when it is done.
3805          */
3806         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3807
3808         /* Disable SSCCTL */
3809         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3810                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3811                                 SBI_SSCCTL_DISABLE,
3812                         SBI_ICLK);
3813
3814         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3815         if (clock == 20000) {
3816                 auxdiv = 1;
3817                 divsel = 0x41;
3818                 phaseinc = 0x20;
3819         } else {
3820                 /* The iCLK virtual clock root frequency is in MHz,
3821                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3822                  * divisors, it is necessary to divide one by another, so we
3823                  * convert the virtual clock precision to KHz here for higher
3824                  * precision.
3825                  */
3826                 u32 iclk_virtual_root_freq = 172800 * 1000;
3827                 u32 iclk_pi_range = 64;
3828                 u32 desired_divisor, msb_divisor_value, pi_value;
3829
3830                 desired_divisor = (iclk_virtual_root_freq / clock);
3831                 msb_divisor_value = desired_divisor / iclk_pi_range;
3832                 pi_value = desired_divisor % iclk_pi_range;
3833
3834                 auxdiv = 0;
3835                 divsel = msb_divisor_value - 2;
3836                 phaseinc = pi_value;
3837         }
3838
3839         /* This should not happen with any sane values */
3840         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3841                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3842         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3843                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3844
3845         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3846                         clock,
3847                         auxdiv,
3848                         divsel,
3849                         phasedir,
3850                         phaseinc);
3851
3852         /* Program SSCDIVINTPHASE6 */
3853         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3854         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3855         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3856         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3857         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3858         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3859         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3860         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3861
3862         /* Program SSCAUXDIV */
3863         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3864         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3865         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3866         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3867
3868         /* Enable modulator and associated divider */
3869         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3870         temp &= ~SBI_SSCCTL_DISABLE;
3871         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3872
3873         /* Wait for initialization time */
3874         udelay(24);
3875
3876         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3877
3878         mutex_unlock(&dev_priv->dpio_lock);
3879 }
3880
3881 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3882                                                 enum pipe pch_transcoder)
3883 {
3884         struct drm_device *dev = crtc->base.dev;
3885         struct drm_i915_private *dev_priv = dev->dev_private;
3886         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3887
3888         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3889                    I915_READ(HTOTAL(cpu_transcoder)));
3890         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3891                    I915_READ(HBLANK(cpu_transcoder)));
3892         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3893                    I915_READ(HSYNC(cpu_transcoder)));
3894
3895         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3896                    I915_READ(VTOTAL(cpu_transcoder)));
3897         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3898                    I915_READ(VBLANK(cpu_transcoder)));
3899         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3900                    I915_READ(VSYNC(cpu_transcoder)));
3901         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3902                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3903 }
3904
3905 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3906 {
3907         struct drm_i915_private *dev_priv = dev->dev_private;
3908         uint32_t temp;
3909
3910         temp = I915_READ(SOUTH_CHICKEN1);
3911         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3912                 return;
3913
3914         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3915         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3916
3917         temp &= ~FDI_BC_BIFURCATION_SELECT;
3918         if (enable)
3919                 temp |= FDI_BC_BIFURCATION_SELECT;
3920
3921         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3922         I915_WRITE(SOUTH_CHICKEN1, temp);
3923         POSTING_READ(SOUTH_CHICKEN1);
3924 }
3925
3926 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3927 {
3928         struct drm_device *dev = intel_crtc->base.dev;
3929
3930         switch (intel_crtc->pipe) {
3931         case PIPE_A:
3932                 break;
3933         case PIPE_B:
3934                 if (intel_crtc->config->fdi_lanes > 2)
3935                         cpt_set_fdi_bc_bifurcation(dev, false);
3936                 else
3937                         cpt_set_fdi_bc_bifurcation(dev, true);
3938
3939                 break;
3940         case PIPE_C:
3941                 cpt_set_fdi_bc_bifurcation(dev, true);
3942
3943                 break;
3944         default:
3945                 BUG();
3946         }
3947 }
3948
3949 /*
3950  * Enable PCH resources required for PCH ports:
3951  *   - PCH PLLs
3952  *   - FDI training & RX/TX
3953  *   - update transcoder timings
3954  *   - DP transcoding bits
3955  *   - transcoder
3956  */
3957 static void ironlake_pch_enable(struct drm_crtc *crtc)
3958 {
3959         struct drm_device *dev = crtc->dev;
3960         struct drm_i915_private *dev_priv = dev->dev_private;
3961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3962         int pipe = intel_crtc->pipe;
3963         u32 reg, temp;
3964
3965         assert_pch_transcoder_disabled(dev_priv, pipe);
3966
3967         if (IS_IVYBRIDGE(dev))
3968                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3969
3970         /* Write the TU size bits before fdi link training, so that error
3971          * detection works. */
3972         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3973                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3974
3975         /* For PCH output, training FDI link */
3976         dev_priv->display.fdi_link_train(crtc);
3977
3978         /* We need to program the right clock selection before writing the pixel
3979          * mutliplier into the DPLL. */
3980         if (HAS_PCH_CPT(dev)) {
3981                 u32 sel;
3982
3983                 temp = I915_READ(PCH_DPLL_SEL);
3984                 temp |= TRANS_DPLL_ENABLE(pipe);
3985                 sel = TRANS_DPLLB_SEL(pipe);
3986                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3987                         temp |= sel;
3988                 else
3989                         temp &= ~sel;
3990                 I915_WRITE(PCH_DPLL_SEL, temp);
3991         }
3992
3993         /* XXX: pch pll's can be enabled any time before we enable the PCH
3994          * transcoder, and we actually should do this to not upset any PCH
3995          * transcoder that already use the clock when we share it.
3996          *
3997          * Note that enable_shared_dpll tries to do the right thing, but
3998          * get_shared_dpll unconditionally resets the pll - we need that to have
3999          * the right LVDS enable sequence. */
4000         intel_enable_shared_dpll(intel_crtc);
4001
4002         /* set transcoder timing, panel must allow it */
4003         assert_panel_unlocked(dev_priv, pipe);
4004         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4005
4006         intel_fdi_normal_train(crtc);
4007
4008         /* For PCH DP, enable TRANS_DP_CTL */
4009         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4010                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4011                 reg = TRANS_DP_CTL(pipe);
4012                 temp = I915_READ(reg);
4013                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4014                           TRANS_DP_SYNC_MASK |
4015                           TRANS_DP_BPC_MASK);
4016                 temp |= (TRANS_DP_OUTPUT_ENABLE |
4017                          TRANS_DP_ENH_FRAMING);
4018                 temp |= bpc << 9; /* same format but at 11:9 */
4019
4020                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4021                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4022                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4023                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4024
4025                 switch (intel_trans_dp_port_sel(crtc)) {
4026                 case PCH_DP_B:
4027                         temp |= TRANS_DP_PORT_SEL_B;
4028                         break;
4029                 case PCH_DP_C:
4030                         temp |= TRANS_DP_PORT_SEL_C;
4031                         break;
4032                 case PCH_DP_D:
4033                         temp |= TRANS_DP_PORT_SEL_D;
4034                         break;
4035                 default:
4036                         BUG();
4037                 }
4038
4039                 I915_WRITE(reg, temp);
4040         }
4041
4042         ironlake_enable_pch_transcoder(dev_priv, pipe);
4043 }
4044
4045 static void lpt_pch_enable(struct drm_crtc *crtc)
4046 {
4047         struct drm_device *dev = crtc->dev;
4048         struct drm_i915_private *dev_priv = dev->dev_private;
4049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4050         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4051
4052         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4053
4054         lpt_program_iclkip(crtc);
4055
4056         /* Set transcoder timing. */
4057         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4058
4059         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4060 }
4061
4062 void intel_put_shared_dpll(struct intel_crtc *crtc)
4063 {
4064         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4065
4066         if (pll == NULL)
4067                 return;
4068
4069         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4070                 WARN(1, "bad %s crtc mask\n", pll->name);
4071                 return;
4072         }
4073
4074         pll->config.crtc_mask &= ~(1 << crtc->pipe);
4075         if (pll->config.crtc_mask == 0) {
4076                 WARN_ON(pll->on);
4077                 WARN_ON(pll->active);
4078         }
4079
4080         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4081 }
4082
4083 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4084                                                 struct intel_crtc_state *crtc_state)
4085 {
4086         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4087         struct intel_shared_dpll *pll;
4088         enum intel_dpll_id i;
4089
4090         if (HAS_PCH_IBX(dev_priv->dev)) {
4091                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4092                 i = (enum intel_dpll_id) crtc->pipe;
4093                 pll = &dev_priv->shared_dplls[i];
4094
4095                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4096                               crtc->base.base.id, pll->name);
4097
4098                 WARN_ON(pll->new_config->crtc_mask);
4099
4100                 goto found;
4101         }
4102
4103         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4104                 pll = &dev_priv->shared_dplls[i];
4105
4106                 /* Only want to check enabled timings first */
4107                 if (pll->new_config->crtc_mask == 0)
4108                         continue;
4109
4110                 if (memcmp(&crtc_state->dpll_hw_state,
4111                            &pll->new_config->hw_state,
4112                            sizeof(pll->new_config->hw_state)) == 0) {
4113                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4114                                       crtc->base.base.id, pll->name,
4115                                       pll->new_config->crtc_mask,
4116                                       pll->active);
4117                         goto found;
4118                 }
4119         }
4120
4121         /* Ok no matching timings, maybe there's a free one? */
4122         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4123                 pll = &dev_priv->shared_dplls[i];
4124                 if (pll->new_config->crtc_mask == 0) {
4125                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4126                                       crtc->base.base.id, pll->name);
4127                         goto found;
4128                 }
4129         }
4130
4131         return NULL;
4132
4133 found:
4134         if (pll->new_config->crtc_mask == 0)
4135                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4136
4137         crtc_state->shared_dpll = i;
4138         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4139                          pipe_name(crtc->pipe));
4140
4141         pll->new_config->crtc_mask |= 1 << crtc->pipe;
4142
4143         return pll;
4144 }
4145
4146 /**
4147  * intel_shared_dpll_start_config - start a new PLL staged config
4148  * @dev_priv: DRM device
4149  * @clear_pipes: mask of pipes that will have their PLLs freed
4150  *
4151  * Starts a new PLL staged config, copying the current config but
4152  * releasing the references of pipes specified in clear_pipes.
4153  */
4154 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4155                                           unsigned clear_pipes)
4156 {
4157         struct intel_shared_dpll *pll;
4158         enum intel_dpll_id i;
4159
4160         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4161                 pll = &dev_priv->shared_dplls[i];
4162
4163                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4164                                           GFP_KERNEL);
4165                 if (!pll->new_config)
4166                         goto cleanup;
4167
4168                 pll->new_config->crtc_mask &= ~clear_pipes;
4169         }
4170
4171         return 0;
4172
4173 cleanup:
4174         while (--i >= 0) {
4175                 pll = &dev_priv->shared_dplls[i];
4176                 kfree(pll->new_config);
4177                 pll->new_config = NULL;
4178         }
4179
4180         return -ENOMEM;
4181 }
4182
4183 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4184 {
4185         struct intel_shared_dpll *pll;
4186         enum intel_dpll_id i;
4187
4188         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4189                 pll = &dev_priv->shared_dplls[i];
4190
4191                 WARN_ON(pll->new_config == &pll->config);
4192
4193                 pll->config = *pll->new_config;
4194                 kfree(pll->new_config);
4195                 pll->new_config = NULL;
4196         }
4197 }
4198
4199 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4200 {
4201         struct intel_shared_dpll *pll;
4202         enum intel_dpll_id i;
4203
4204         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4205                 pll = &dev_priv->shared_dplls[i];
4206
4207                 WARN_ON(pll->new_config == &pll->config);
4208
4209                 kfree(pll->new_config);
4210                 pll->new_config = NULL;
4211         }
4212 }
4213
4214 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4215 {
4216         struct drm_i915_private *dev_priv = dev->dev_private;
4217         int dslreg = PIPEDSL(pipe);
4218         u32 temp;
4219
4220         temp = I915_READ(dslreg);
4221         udelay(500);
4222         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4223                 if (wait_for(I915_READ(dslreg) != temp, 5))
4224                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4225         }
4226 }
4227
4228 static void skylake_pfit_enable(struct intel_crtc *crtc)
4229 {
4230         struct drm_device *dev = crtc->base.dev;
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         int pipe = crtc->pipe;
4233
4234         if (crtc->config->pch_pfit.enabled) {
4235                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4236                 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4237                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4238         }
4239 }
4240
4241 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4242 {
4243         struct drm_device *dev = crtc->base.dev;
4244         struct drm_i915_private *dev_priv = dev->dev_private;
4245         int pipe = crtc->pipe;
4246
4247         if (crtc->config->pch_pfit.enabled) {
4248                 /* Force use of hard-coded filter coefficients
4249                  * as some pre-programmed values are broken,
4250                  * e.g. x201.
4251                  */
4252                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4253                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4254                                                  PF_PIPE_SEL_IVB(pipe));
4255                 else
4256                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4257                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4258                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4259         }
4260 }
4261
4262 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4263 {
4264         struct drm_device *dev = crtc->dev;
4265         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4266         struct drm_plane *plane;
4267         struct intel_plane *intel_plane;
4268
4269         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4270                 intel_plane = to_intel_plane(plane);
4271                 if (intel_plane->pipe == pipe)
4272                         intel_plane_restore(&intel_plane->base);
4273         }
4274 }
4275
4276 /*
4277  * Disable a plane internally without actually modifying the plane's state.
4278  * This will allow us to easily restore the plane later by just reprogramming
4279  * its state.
4280  */
4281 static void disable_plane_internal(struct drm_plane *plane)
4282 {
4283         struct intel_plane *intel_plane = to_intel_plane(plane);
4284         struct drm_plane_state *state =
4285                 plane->funcs->atomic_duplicate_state(plane);
4286         struct intel_plane_state *intel_state = to_intel_plane_state(state);
4287
4288         intel_state->visible = false;
4289         intel_plane->commit_plane(plane, intel_state);
4290
4291         intel_plane_destroy_state(plane, state);
4292 }
4293
4294 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4295 {
4296         struct drm_device *dev = crtc->dev;
4297         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4298         struct drm_plane *plane;
4299         struct intel_plane *intel_plane;
4300
4301         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4302                 intel_plane = to_intel_plane(plane);
4303                 if (plane->fb && intel_plane->pipe == pipe)
4304                         disable_plane_internal(plane);
4305         }
4306 }
4307
4308 void hsw_enable_ips(struct intel_crtc *crtc)
4309 {
4310         struct drm_device *dev = crtc->base.dev;
4311         struct drm_i915_private *dev_priv = dev->dev_private;
4312
4313         if (!crtc->config->ips_enabled)
4314                 return;
4315
4316         /* We can only enable IPS after we enable a plane and wait for a vblank */
4317         intel_wait_for_vblank(dev, crtc->pipe);
4318
4319         assert_plane_enabled(dev_priv, crtc->plane);
4320         if (IS_BROADWELL(dev)) {
4321                 mutex_lock(&dev_priv->rps.hw_lock);
4322                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4323                 mutex_unlock(&dev_priv->rps.hw_lock);
4324                 /* Quoting Art Runyan: "its not safe to expect any particular
4325                  * value in IPS_CTL bit 31 after enabling IPS through the
4326                  * mailbox." Moreover, the mailbox may return a bogus state,
4327                  * so we need to just enable it and continue on.
4328                  */
4329         } else {
4330                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4331                 /* The bit only becomes 1 in the next vblank, so this wait here
4332                  * is essentially intel_wait_for_vblank. If we don't have this
4333                  * and don't wait for vblanks until the end of crtc_enable, then
4334                  * the HW state readout code will complain that the expected
4335                  * IPS_CTL value is not the one we read. */
4336                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4337                         DRM_ERROR("Timed out waiting for IPS enable\n");
4338         }
4339 }
4340
4341 void hsw_disable_ips(struct intel_crtc *crtc)
4342 {
4343         struct drm_device *dev = crtc->base.dev;
4344         struct drm_i915_private *dev_priv = dev->dev_private;
4345
4346         if (!crtc->config->ips_enabled)
4347                 return;
4348
4349         assert_plane_enabled(dev_priv, crtc->plane);
4350         if (IS_BROADWELL(dev)) {
4351                 mutex_lock(&dev_priv->rps.hw_lock);
4352                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4353                 mutex_unlock(&dev_priv->rps.hw_lock);
4354                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4355                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4356                         DRM_ERROR("Timed out waiting for IPS disable\n");
4357         } else {
4358                 I915_WRITE(IPS_CTL, 0);
4359                 POSTING_READ(IPS_CTL);
4360         }
4361
4362         /* We need to wait for a vblank before we can disable the plane. */
4363         intel_wait_for_vblank(dev, crtc->pipe);
4364 }
4365
4366 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4367 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4368 {
4369         struct drm_device *dev = crtc->dev;
4370         struct drm_i915_private *dev_priv = dev->dev_private;
4371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4372         enum pipe pipe = intel_crtc->pipe;
4373         int palreg = PALETTE(pipe);
4374         int i;
4375         bool reenable_ips = false;
4376
4377         /* The clocks have to be on to load the palette. */
4378         if (!crtc->state->enable || !intel_crtc->active)
4379                 return;
4380
4381         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4382                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4383                         assert_dsi_pll_enabled(dev_priv);
4384                 else
4385                         assert_pll_enabled(dev_priv, pipe);
4386         }
4387
4388         /* use legacy palette for Ironlake */
4389         if (!HAS_GMCH_DISPLAY(dev))
4390                 palreg = LGC_PALETTE(pipe);
4391
4392         /* Workaround : Do not read or write the pipe palette/gamma data while
4393          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4394          */
4395         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4396             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4397              GAMMA_MODE_MODE_SPLIT)) {
4398                 hsw_disable_ips(intel_crtc);
4399                 reenable_ips = true;
4400         }
4401
4402         for (i = 0; i < 256; i++) {
4403                 I915_WRITE(palreg + 4 * i,
4404                            (intel_crtc->lut_r[i] << 16) |
4405                            (intel_crtc->lut_g[i] << 8) |
4406                            intel_crtc->lut_b[i]);
4407         }
4408
4409         if (reenable_ips)
4410                 hsw_enable_ips(intel_crtc);
4411 }
4412
4413 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4414 {
4415         if (!enable && intel_crtc->overlay) {
4416                 struct drm_device *dev = intel_crtc->base.dev;
4417                 struct drm_i915_private *dev_priv = dev->dev_private;
4418
4419                 mutex_lock(&dev->struct_mutex);
4420                 dev_priv->mm.interruptible = false;
4421                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4422                 dev_priv->mm.interruptible = true;
4423                 mutex_unlock(&dev->struct_mutex);
4424         }
4425
4426         /* Let userspace switch the overlay on again. In most cases userspace
4427          * has to recompute where to put it anyway.
4428          */
4429 }
4430
4431 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4432 {
4433         struct drm_device *dev = crtc->dev;
4434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4435         int pipe = intel_crtc->pipe;
4436
4437         intel_enable_primary_hw_plane(crtc->primary, crtc);
4438         intel_enable_sprite_planes(crtc);
4439         intel_crtc_update_cursor(crtc, true);
4440         intel_crtc_dpms_overlay(intel_crtc, true);
4441
4442         hsw_enable_ips(intel_crtc);
4443
4444         mutex_lock(&dev->struct_mutex);
4445         intel_fbc_update(dev);
4446         mutex_unlock(&dev->struct_mutex);
4447
4448         /*
4449          * FIXME: Once we grow proper nuclear flip support out of this we need
4450          * to compute the mask of flip planes precisely. For the time being
4451          * consider this a flip from a NULL plane.
4452          */
4453         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4454 }
4455
4456 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4457 {
4458         struct drm_device *dev = crtc->dev;
4459         struct drm_i915_private *dev_priv = dev->dev_private;
4460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4461         int pipe = intel_crtc->pipe;
4462
4463         intel_crtc_wait_for_pending_flips(crtc);
4464
4465         if (dev_priv->fbc.crtc == intel_crtc)
4466                 intel_fbc_disable(dev);
4467
4468         hsw_disable_ips(intel_crtc);
4469
4470         intel_crtc_dpms_overlay(intel_crtc, false);
4471         intel_crtc_update_cursor(crtc, false);
4472         intel_disable_sprite_planes(crtc);
4473         intel_disable_primary_hw_plane(crtc->primary, crtc);
4474
4475         /*
4476          * FIXME: Once we grow proper nuclear flip support out of this we need
4477          * to compute the mask of flip planes precisely. For the time being
4478          * consider this a flip to a NULL plane.
4479          */
4480         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4481 }
4482
4483 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4484 {
4485         struct drm_device *dev = crtc->dev;
4486         struct drm_i915_private *dev_priv = dev->dev_private;
4487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4488         struct intel_encoder *encoder;
4489         int pipe = intel_crtc->pipe;
4490
4491         WARN_ON(!crtc->state->enable);
4492
4493         if (intel_crtc->active)
4494                 return;
4495
4496         if (intel_crtc->config->has_pch_encoder)
4497                 intel_prepare_shared_dpll(intel_crtc);
4498
4499         if (intel_crtc->config->has_dp_encoder)
4500                 intel_dp_set_m_n(intel_crtc, M1_N1);
4501
4502         intel_set_pipe_timings(intel_crtc);
4503
4504         if (intel_crtc->config->has_pch_encoder) {
4505                 intel_cpu_transcoder_set_m_n(intel_crtc,
4506                                      &intel_crtc->config->fdi_m_n, NULL);
4507         }
4508
4509         ironlake_set_pipeconf(crtc);
4510
4511         intel_crtc->active = true;
4512
4513         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4514         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4515
4516         for_each_encoder_on_crtc(dev, crtc, encoder)
4517                 if (encoder->pre_enable)
4518                         encoder->pre_enable(encoder);
4519
4520         if (intel_crtc->config->has_pch_encoder) {
4521                 /* Note: FDI PLL enabling _must_ be done before we enable the
4522                  * cpu pipes, hence this is separate from all the other fdi/pch
4523                  * enabling. */
4524                 ironlake_fdi_pll_enable(intel_crtc);
4525         } else {
4526                 assert_fdi_tx_disabled(dev_priv, pipe);
4527                 assert_fdi_rx_disabled(dev_priv, pipe);
4528         }
4529
4530         ironlake_pfit_enable(intel_crtc);
4531
4532         /*
4533          * On ILK+ LUT must be loaded before the pipe is running but with
4534          * clocks enabled
4535          */
4536         intel_crtc_load_lut(crtc);
4537
4538         intel_update_watermarks(crtc);
4539         intel_enable_pipe(intel_crtc);
4540
4541         if (intel_crtc->config->has_pch_encoder)
4542                 ironlake_pch_enable(crtc);
4543
4544         assert_vblank_disabled(crtc);
4545         drm_crtc_vblank_on(crtc);
4546
4547         for_each_encoder_on_crtc(dev, crtc, encoder)
4548                 encoder->enable(encoder);
4549
4550         if (HAS_PCH_CPT(dev))
4551                 cpt_verify_modeset(dev, intel_crtc->pipe);
4552
4553         intel_crtc_enable_planes(crtc);
4554 }
4555
4556 /* IPS only exists on ULT machines and is tied to pipe A. */
4557 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4558 {
4559         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4560 }
4561
4562 /*
4563  * This implements the workaround described in the "notes" section of the mode
4564  * set sequence documentation. When going from no pipes or single pipe to
4565  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4566  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4567  */
4568 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4569 {
4570         struct drm_device *dev = crtc->base.dev;
4571         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4572
4573         /* We want to get the other_active_crtc only if there's only 1 other
4574          * active crtc. */
4575         for_each_intel_crtc(dev, crtc_it) {
4576                 if (!crtc_it->active || crtc_it == crtc)
4577                         continue;
4578
4579                 if (other_active_crtc)
4580                         return;
4581
4582                 other_active_crtc = crtc_it;
4583         }
4584         if (!other_active_crtc)
4585                 return;
4586
4587         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4588         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4589 }
4590
4591 static void haswell_crtc_enable(struct drm_crtc *crtc)
4592 {
4593         struct drm_device *dev = crtc->dev;
4594         struct drm_i915_private *dev_priv = dev->dev_private;
4595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4596         struct intel_encoder *encoder;
4597         int pipe = intel_crtc->pipe;
4598
4599         WARN_ON(!crtc->state->enable);
4600
4601         if (intel_crtc->active)
4602                 return;
4603
4604         if (intel_crtc_to_shared_dpll(intel_crtc))
4605                 intel_enable_shared_dpll(intel_crtc);
4606
4607         if (intel_crtc->config->has_dp_encoder)
4608                 intel_dp_set_m_n(intel_crtc, M1_N1);
4609
4610         intel_set_pipe_timings(intel_crtc);
4611
4612         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4613                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4614                            intel_crtc->config->pixel_multiplier - 1);
4615         }
4616
4617         if (intel_crtc->config->has_pch_encoder) {
4618                 intel_cpu_transcoder_set_m_n(intel_crtc,
4619                                      &intel_crtc->config->fdi_m_n, NULL);
4620         }
4621
4622         haswell_set_pipeconf(crtc);
4623
4624         intel_set_pipe_csc(crtc);
4625
4626         intel_crtc->active = true;
4627
4628         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4629         for_each_encoder_on_crtc(dev, crtc, encoder)
4630                 if (encoder->pre_enable)
4631                         encoder->pre_enable(encoder);
4632
4633         if (intel_crtc->config->has_pch_encoder) {
4634                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4635                                                       true);
4636                 dev_priv->display.fdi_link_train(crtc);
4637         }
4638
4639         intel_ddi_enable_pipe_clock(intel_crtc);
4640
4641         if (IS_SKYLAKE(dev))
4642                 skylake_pfit_enable(intel_crtc);
4643         else
4644                 ironlake_pfit_enable(intel_crtc);
4645
4646         /*
4647          * On ILK+ LUT must be loaded before the pipe is running but with
4648          * clocks enabled
4649          */
4650         intel_crtc_load_lut(crtc);
4651
4652         intel_ddi_set_pipe_settings(crtc);
4653         intel_ddi_enable_transcoder_func(crtc);
4654
4655         intel_update_watermarks(crtc);
4656         intel_enable_pipe(intel_crtc);
4657
4658         if (intel_crtc->config->has_pch_encoder)
4659                 lpt_pch_enable(crtc);
4660
4661         if (intel_crtc->config->dp_encoder_is_mst)
4662                 intel_ddi_set_vc_payload_alloc(crtc, true);
4663
4664         assert_vblank_disabled(crtc);
4665         drm_crtc_vblank_on(crtc);
4666
4667         for_each_encoder_on_crtc(dev, crtc, encoder) {
4668                 encoder->enable(encoder);
4669                 intel_opregion_notify_encoder(encoder, true);
4670         }
4671
4672         /* If we change the relative order between pipe/planes enabling, we need
4673          * to change the workaround. */
4674         haswell_mode_set_planes_workaround(intel_crtc);
4675         intel_crtc_enable_planes(crtc);
4676 }
4677
4678 static void skylake_pfit_disable(struct intel_crtc *crtc)
4679 {
4680         struct drm_device *dev = crtc->base.dev;
4681         struct drm_i915_private *dev_priv = dev->dev_private;
4682         int pipe = crtc->pipe;
4683
4684         /* To avoid upsetting the power well on haswell only disable the pfit if
4685          * it's in use. The hw state code will make sure we get this right. */
4686         if (crtc->config->pch_pfit.enabled) {
4687                 I915_WRITE(PS_CTL(pipe), 0);
4688                 I915_WRITE(PS_WIN_POS(pipe), 0);
4689                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4690         }
4691 }
4692
4693 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4694 {
4695         struct drm_device *dev = crtc->base.dev;
4696         struct drm_i915_private *dev_priv = dev->dev_private;
4697         int pipe = crtc->pipe;
4698
4699         /* To avoid upsetting the power well on haswell only disable the pfit if
4700          * it's in use. The hw state code will make sure we get this right. */
4701         if (crtc->config->pch_pfit.enabled) {
4702                 I915_WRITE(PF_CTL(pipe), 0);
4703                 I915_WRITE(PF_WIN_POS(pipe), 0);
4704                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4705         }
4706 }
4707
4708 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4709 {
4710         struct drm_device *dev = crtc->dev;
4711         struct drm_i915_private *dev_priv = dev->dev_private;
4712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713         struct intel_encoder *encoder;
4714         int pipe = intel_crtc->pipe;
4715         u32 reg, temp;
4716
4717         if (!intel_crtc->active)
4718                 return;
4719
4720         intel_crtc_disable_planes(crtc);
4721
4722         for_each_encoder_on_crtc(dev, crtc, encoder)
4723                 encoder->disable(encoder);
4724
4725         drm_crtc_vblank_off(crtc);
4726         assert_vblank_disabled(crtc);
4727
4728         if (intel_crtc->config->has_pch_encoder)
4729                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4730
4731         intel_disable_pipe(intel_crtc);
4732
4733         ironlake_pfit_disable(intel_crtc);
4734
4735         for_each_encoder_on_crtc(dev, crtc, encoder)
4736                 if (encoder->post_disable)
4737                         encoder->post_disable(encoder);
4738
4739         if (intel_crtc->config->has_pch_encoder) {
4740                 ironlake_fdi_disable(crtc);
4741
4742                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4743
4744                 if (HAS_PCH_CPT(dev)) {
4745                         /* disable TRANS_DP_CTL */
4746                         reg = TRANS_DP_CTL(pipe);
4747                         temp = I915_READ(reg);
4748                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4749                                   TRANS_DP_PORT_SEL_MASK);
4750                         temp |= TRANS_DP_PORT_SEL_NONE;
4751                         I915_WRITE(reg, temp);
4752
4753                         /* disable DPLL_SEL */
4754                         temp = I915_READ(PCH_DPLL_SEL);
4755                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4756                         I915_WRITE(PCH_DPLL_SEL, temp);
4757                 }
4758
4759                 /* disable PCH DPLL */
4760                 intel_disable_shared_dpll(intel_crtc);
4761
4762                 ironlake_fdi_pll_disable(intel_crtc);
4763         }
4764
4765         intel_crtc->active = false;
4766         intel_update_watermarks(crtc);
4767
4768         mutex_lock(&dev->struct_mutex);
4769         intel_fbc_update(dev);
4770         mutex_unlock(&dev->struct_mutex);
4771 }
4772
4773 static void haswell_crtc_disable(struct drm_crtc *crtc)
4774 {
4775         struct drm_device *dev = crtc->dev;
4776         struct drm_i915_private *dev_priv = dev->dev_private;
4777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4778         struct intel_encoder *encoder;
4779         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4780
4781         if (!intel_crtc->active)
4782                 return;
4783
4784         intel_crtc_disable_planes(crtc);
4785
4786         for_each_encoder_on_crtc(dev, crtc, encoder) {
4787                 intel_opregion_notify_encoder(encoder, false);
4788                 encoder->disable(encoder);
4789         }
4790
4791         drm_crtc_vblank_off(crtc);
4792         assert_vblank_disabled(crtc);
4793
4794         if (intel_crtc->config->has_pch_encoder)
4795                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4796                                                       false);
4797         intel_disable_pipe(intel_crtc);
4798
4799         if (intel_crtc->config->dp_encoder_is_mst)
4800                 intel_ddi_set_vc_payload_alloc(crtc, false);
4801
4802         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4803
4804         if (IS_SKYLAKE(dev))
4805                 skylake_pfit_disable(intel_crtc);
4806         else
4807                 ironlake_pfit_disable(intel_crtc);
4808
4809         intel_ddi_disable_pipe_clock(intel_crtc);
4810
4811         if (intel_crtc->config->has_pch_encoder) {
4812                 lpt_disable_pch_transcoder(dev_priv);
4813                 intel_ddi_fdi_disable(crtc);
4814         }
4815
4816         for_each_encoder_on_crtc(dev, crtc, encoder)
4817                 if (encoder->post_disable)
4818                         encoder->post_disable(encoder);
4819
4820         intel_crtc->active = false;
4821         intel_update_watermarks(crtc);
4822
4823         mutex_lock(&dev->struct_mutex);
4824         intel_fbc_update(dev);
4825         mutex_unlock(&dev->struct_mutex);
4826
4827         if (intel_crtc_to_shared_dpll(intel_crtc))
4828                 intel_disable_shared_dpll(intel_crtc);
4829 }
4830
4831 static void ironlake_crtc_off(struct drm_crtc *crtc)
4832 {
4833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4834         intel_put_shared_dpll(intel_crtc);
4835 }
4836
4837
4838 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4839 {
4840         struct drm_device *dev = crtc->base.dev;
4841         struct drm_i915_private *dev_priv = dev->dev_private;
4842         struct intel_crtc_state *pipe_config = crtc->config;
4843
4844         if (!pipe_config->gmch_pfit.control)
4845                 return;
4846
4847         /*
4848          * The panel fitter should only be adjusted whilst the pipe is disabled,
4849          * according to register description and PRM.
4850          */
4851         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4852         assert_pipe_disabled(dev_priv, crtc->pipe);
4853
4854         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4855         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4856
4857         /* Border color in case we don't scale up to the full screen. Black by
4858          * default, change to something else for debugging. */
4859         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4860 }
4861
4862 static enum intel_display_power_domain port_to_power_domain(enum port port)
4863 {
4864         switch (port) {
4865         case PORT_A:
4866                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4867         case PORT_B:
4868                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4869         case PORT_C:
4870                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4871         case PORT_D:
4872                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4873         default:
4874                 WARN_ON_ONCE(1);
4875                 return POWER_DOMAIN_PORT_OTHER;
4876         }
4877 }
4878
4879 #define for_each_power_domain(domain, mask)                             \
4880         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4881                 if ((1 << (domain)) & (mask))
4882
4883 enum intel_display_power_domain
4884 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4885 {
4886         struct drm_device *dev = intel_encoder->base.dev;
4887         struct intel_digital_port *intel_dig_port;
4888
4889         switch (intel_encoder->type) {
4890         case INTEL_OUTPUT_UNKNOWN:
4891                 /* Only DDI platforms should ever use this output type */
4892                 WARN_ON_ONCE(!HAS_DDI(dev));
4893         case INTEL_OUTPUT_DISPLAYPORT:
4894         case INTEL_OUTPUT_HDMI:
4895         case INTEL_OUTPUT_EDP:
4896                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4897                 return port_to_power_domain(intel_dig_port->port);
4898         case INTEL_OUTPUT_DP_MST:
4899                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4900                 return port_to_power_domain(intel_dig_port->port);
4901         case INTEL_OUTPUT_ANALOG:
4902                 return POWER_DOMAIN_PORT_CRT;
4903         case INTEL_OUTPUT_DSI:
4904                 return POWER_DOMAIN_PORT_DSI;
4905         default:
4906                 return POWER_DOMAIN_PORT_OTHER;
4907         }
4908 }
4909
4910 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4911 {
4912         struct drm_device *dev = crtc->dev;
4913         struct intel_encoder *intel_encoder;
4914         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4915         enum pipe pipe = intel_crtc->pipe;
4916         unsigned long mask;
4917         enum transcoder transcoder;
4918
4919         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4920
4921         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4922         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4923         if (intel_crtc->config->pch_pfit.enabled ||
4924             intel_crtc->config->pch_pfit.force_thru)
4925                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4926
4927         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4928                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4929
4930         return mask;
4931 }
4932
4933 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
4934 {
4935         struct drm_device *dev = state->dev;
4936         struct drm_i915_private *dev_priv = dev->dev_private;
4937         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4938         struct intel_crtc *crtc;
4939
4940         /*
4941          * First get all needed power domains, then put all unneeded, to avoid
4942          * any unnecessary toggling of the power wells.
4943          */
4944         for_each_intel_crtc(dev, crtc) {
4945                 enum intel_display_power_domain domain;
4946
4947                 if (!crtc->base.state->enable)
4948                         continue;
4949
4950                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4951
4952                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4953                         intel_display_power_get(dev_priv, domain);
4954         }
4955
4956         if (dev_priv->display.modeset_global_resources)
4957                 dev_priv->display.modeset_global_resources(state);
4958
4959         for_each_intel_crtc(dev, crtc) {
4960                 enum intel_display_power_domain domain;
4961
4962                 for_each_power_domain(domain, crtc->enabled_power_domains)
4963                         intel_display_power_put(dev_priv, domain);
4964
4965                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4966         }
4967
4968         intel_display_set_init_power(dev_priv, false);
4969 }
4970
4971 /* returns HPLL frequency in kHz */
4972 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4973 {
4974         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4975
4976         /* Obtain SKU information */
4977         mutex_lock(&dev_priv->dpio_lock);
4978         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4979                 CCK_FUSE_HPLL_FREQ_MASK;
4980         mutex_unlock(&dev_priv->dpio_lock);
4981
4982         return vco_freq[hpll_freq] * 1000;
4983 }
4984
4985 static void vlv_update_cdclk(struct drm_device *dev)
4986 {
4987         struct drm_i915_private *dev_priv = dev->dev_private;
4988
4989         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4990         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4991                          dev_priv->vlv_cdclk_freq);
4992
4993         /*
4994          * Program the gmbus_freq based on the cdclk frequency.
4995          * BSpec erroneously claims we should aim for 4MHz, but
4996          * in fact 1MHz is the correct frequency.
4997          */
4998         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4999 }
5000
5001 /* Adjust CDclk dividers to allow high res or save power if possible */
5002 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5003 {
5004         struct drm_i915_private *dev_priv = dev->dev_private;
5005         u32 val, cmd;
5006
5007         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5008
5009         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5010                 cmd = 2;
5011         else if (cdclk == 266667)
5012                 cmd = 1;
5013         else
5014                 cmd = 0;
5015
5016         mutex_lock(&dev_priv->rps.hw_lock);
5017         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5018         val &= ~DSPFREQGUAR_MASK;
5019         val |= (cmd << DSPFREQGUAR_SHIFT);
5020         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5021         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5022                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5023                      50)) {
5024                 DRM_ERROR("timed out waiting for CDclk change\n");
5025         }
5026         mutex_unlock(&dev_priv->rps.hw_lock);
5027
5028         if (cdclk == 400000) {
5029                 u32 divider;
5030
5031                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5032
5033                 mutex_lock(&dev_priv->dpio_lock);
5034                 /* adjust cdclk divider */
5035                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5036                 val &= ~DISPLAY_FREQUENCY_VALUES;
5037                 val |= divider;
5038                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5039
5040                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5041                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5042                              50))
5043                         DRM_ERROR("timed out waiting for CDclk change\n");
5044                 mutex_unlock(&dev_priv->dpio_lock);
5045         }
5046
5047         mutex_lock(&dev_priv->dpio_lock);
5048         /* adjust self-refresh exit latency value */
5049         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5050         val &= ~0x7f;
5051
5052         /*
5053          * For high bandwidth configs, we set a higher latency in the bunit
5054          * so that the core display fetch happens in time to avoid underruns.
5055          */
5056         if (cdclk == 400000)
5057                 val |= 4500 / 250; /* 4.5 usec */
5058         else
5059                 val |= 3000 / 250; /* 3.0 usec */
5060         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5061         mutex_unlock(&dev_priv->dpio_lock);
5062
5063         vlv_update_cdclk(dev);
5064 }
5065
5066 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5067 {
5068         struct drm_i915_private *dev_priv = dev->dev_private;
5069         u32 val, cmd;
5070
5071         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5072
5073         switch (cdclk) {
5074         case 333333:
5075         case 320000:
5076         case 266667:
5077         case 200000:
5078                 break;
5079         default:
5080                 MISSING_CASE(cdclk);
5081                 return;
5082         }
5083
5084         /*
5085          * Specs are full of misinformation, but testing on actual
5086          * hardware has shown that we just need to write the desired
5087          * CCK divider into the Punit register.
5088          */
5089         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5090
5091         mutex_lock(&dev_priv->rps.hw_lock);
5092         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5093         val &= ~DSPFREQGUAR_MASK_CHV;
5094         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5095         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5096         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5097                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5098                      50)) {
5099                 DRM_ERROR("timed out waiting for CDclk change\n");
5100         }
5101         mutex_unlock(&dev_priv->rps.hw_lock);
5102
5103         vlv_update_cdclk(dev);
5104 }
5105
5106 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5107                                  int max_pixclk)
5108 {
5109         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5110         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5111
5112         /*
5113          * Really only a few cases to deal with, as only 4 CDclks are supported:
5114          *   200MHz
5115          *   267MHz
5116          *   320/333MHz (depends on HPLL freq)
5117          *   400MHz (VLV only)
5118          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5119          * of the lower bin and adjust if needed.
5120          *
5121          * We seem to get an unstable or solid color picture at 200MHz.
5122          * Not sure what's wrong. For now use 200MHz only when all pipes
5123          * are off.
5124          */
5125         if (!IS_CHERRYVIEW(dev_priv) &&
5126             max_pixclk > freq_320*limit/100)
5127                 return 400000;
5128         else if (max_pixclk > 266667*limit/100)
5129                 return freq_320;
5130         else if (max_pixclk > 0)
5131                 return 266667;
5132         else
5133                 return 200000;
5134 }
5135
5136 /* compute the max pixel clock for new configuration */
5137 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5138 {
5139         struct drm_device *dev = dev_priv->dev;
5140         struct intel_crtc *intel_crtc;
5141         int max_pixclk = 0;
5142
5143         for_each_intel_crtc(dev, intel_crtc) {
5144                 if (intel_crtc->new_enabled)
5145                         max_pixclk = max(max_pixclk,
5146                                          intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5147         }
5148
5149         return max_pixclk;
5150 }
5151
5152 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5153                                             unsigned *prepare_pipes)
5154 {
5155         struct drm_i915_private *dev_priv = dev->dev_private;
5156         struct intel_crtc *intel_crtc;
5157         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5158
5159         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5160             dev_priv->vlv_cdclk_freq)
5161                 return;
5162
5163         /* disable/enable all currently active pipes while we change cdclk */
5164         for_each_intel_crtc(dev, intel_crtc)
5165                 if (intel_crtc->base.state->enable)
5166                         *prepare_pipes |= (1 << intel_crtc->pipe);
5167 }
5168
5169 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5170 {
5171         unsigned int credits, default_credits;
5172
5173         if (IS_CHERRYVIEW(dev_priv))
5174                 default_credits = PFI_CREDIT(12);
5175         else
5176                 default_credits = PFI_CREDIT(8);
5177
5178         if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5179                 /* CHV suggested value is 31 or 63 */
5180                 if (IS_CHERRYVIEW(dev_priv))
5181                         credits = PFI_CREDIT_31;
5182                 else
5183                         credits = PFI_CREDIT(15);
5184         } else {
5185                 credits = default_credits;
5186         }
5187
5188         /*
5189          * WA - write default credits before re-programming
5190          * FIXME: should we also set the resend bit here?
5191          */
5192         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5193                    default_credits);
5194
5195         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5196                    credits | PFI_CREDIT_RESEND);
5197
5198         /*
5199          * FIXME is this guaranteed to clear
5200          * immediately or should we poll for it?
5201          */
5202         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5203 }
5204
5205 static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
5206 {
5207         struct drm_device *dev = state->dev;
5208         struct drm_i915_private *dev_priv = dev->dev_private;
5209         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5210         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5211
5212         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5213                 /*
5214                  * FIXME: We can end up here with all power domains off, yet
5215                  * with a CDCLK frequency other than the minimum. To account
5216                  * for this take the PIPE-A power domain, which covers the HW
5217                  * blocks needed for the following programming. This can be
5218                  * removed once it's guaranteed that we get here either with
5219                  * the minimum CDCLK set, or the required power domains
5220                  * enabled.
5221                  */
5222                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5223
5224                 if (IS_CHERRYVIEW(dev))
5225                         cherryview_set_cdclk(dev, req_cdclk);
5226                 else
5227                         valleyview_set_cdclk(dev, req_cdclk);
5228
5229                 vlv_program_pfi_credits(dev_priv);
5230
5231                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5232         }
5233 }
5234
5235 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5236 {
5237         struct drm_device *dev = crtc->dev;
5238         struct drm_i915_private *dev_priv = to_i915(dev);
5239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5240         struct intel_encoder *encoder;
5241         int pipe = intel_crtc->pipe;
5242         bool is_dsi;
5243
5244         WARN_ON(!crtc->state->enable);
5245
5246         if (intel_crtc->active)
5247                 return;
5248
5249         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5250
5251         if (!is_dsi) {
5252                 if (IS_CHERRYVIEW(dev))
5253                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5254                 else
5255                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5256         }
5257
5258         if (intel_crtc->config->has_dp_encoder)
5259                 intel_dp_set_m_n(intel_crtc, M1_N1);
5260
5261         intel_set_pipe_timings(intel_crtc);
5262
5263         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5264                 struct drm_i915_private *dev_priv = dev->dev_private;
5265
5266                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5267                 I915_WRITE(CHV_CANVAS(pipe), 0);
5268         }
5269
5270         i9xx_set_pipeconf(intel_crtc);
5271
5272         intel_crtc->active = true;
5273
5274         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5275
5276         for_each_encoder_on_crtc(dev, crtc, encoder)
5277                 if (encoder->pre_pll_enable)
5278                         encoder->pre_pll_enable(encoder);
5279
5280         if (!is_dsi) {
5281                 if (IS_CHERRYVIEW(dev))
5282                         chv_enable_pll(intel_crtc, intel_crtc->config);
5283                 else
5284                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5285         }
5286
5287         for_each_encoder_on_crtc(dev, crtc, encoder)
5288                 if (encoder->pre_enable)
5289                         encoder->pre_enable(encoder);
5290
5291         i9xx_pfit_enable(intel_crtc);
5292
5293         intel_crtc_load_lut(crtc);
5294
5295         intel_update_watermarks(crtc);
5296         intel_enable_pipe(intel_crtc);
5297
5298         assert_vblank_disabled(crtc);
5299         drm_crtc_vblank_on(crtc);
5300
5301         for_each_encoder_on_crtc(dev, crtc, encoder)
5302                 encoder->enable(encoder);
5303
5304         intel_crtc_enable_planes(crtc);
5305
5306         /* Underruns don't raise interrupts, so check manually. */
5307         i9xx_check_fifo_underruns(dev_priv);
5308 }
5309
5310 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5311 {
5312         struct drm_device *dev = crtc->base.dev;
5313         struct drm_i915_private *dev_priv = dev->dev_private;
5314
5315         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5316         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5317 }
5318
5319 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5320 {
5321         struct drm_device *dev = crtc->dev;
5322         struct drm_i915_private *dev_priv = to_i915(dev);
5323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5324         struct intel_encoder *encoder;
5325         int pipe = intel_crtc->pipe;
5326
5327         WARN_ON(!crtc->state->enable);
5328
5329         if (intel_crtc->active)
5330                 return;
5331
5332         i9xx_set_pll_dividers(intel_crtc);
5333
5334         if (intel_crtc->config->has_dp_encoder)
5335                 intel_dp_set_m_n(intel_crtc, M1_N1);
5336
5337         intel_set_pipe_timings(intel_crtc);
5338
5339         i9xx_set_pipeconf(intel_crtc);
5340
5341         intel_crtc->active = true;
5342
5343         if (!IS_GEN2(dev))
5344                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5345
5346         for_each_encoder_on_crtc(dev, crtc, encoder)
5347                 if (encoder->pre_enable)
5348                         encoder->pre_enable(encoder);
5349
5350         i9xx_enable_pll(intel_crtc);
5351
5352         i9xx_pfit_enable(intel_crtc);
5353
5354         intel_crtc_load_lut(crtc);
5355
5356         intel_update_watermarks(crtc);
5357         intel_enable_pipe(intel_crtc);
5358
5359         assert_vblank_disabled(crtc);
5360         drm_crtc_vblank_on(crtc);
5361
5362         for_each_encoder_on_crtc(dev, crtc, encoder)
5363                 encoder->enable(encoder);
5364
5365         intel_crtc_enable_planes(crtc);
5366
5367         /*
5368          * Gen2 reports pipe underruns whenever all planes are disabled.
5369          * So don't enable underrun reporting before at least some planes
5370          * are enabled.
5371          * FIXME: Need to fix the logic to work when we turn off all planes
5372          * but leave the pipe running.
5373          */
5374         if (IS_GEN2(dev))
5375                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5376
5377         /* Underruns don't raise interrupts, so check manually. */
5378         i9xx_check_fifo_underruns(dev_priv);
5379 }
5380
5381 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5382 {
5383         struct drm_device *dev = crtc->base.dev;
5384         struct drm_i915_private *dev_priv = dev->dev_private;
5385
5386         if (!crtc->config->gmch_pfit.control)
5387                 return;
5388
5389         assert_pipe_disabled(dev_priv, crtc->pipe);
5390
5391         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5392                          I915_READ(PFIT_CONTROL));
5393         I915_WRITE(PFIT_CONTROL, 0);
5394 }
5395
5396 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5397 {
5398         struct drm_device *dev = crtc->dev;
5399         struct drm_i915_private *dev_priv = dev->dev_private;
5400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5401         struct intel_encoder *encoder;
5402         int pipe = intel_crtc->pipe;
5403
5404         if (!intel_crtc->active)
5405                 return;
5406
5407         /*
5408          * Gen2 reports pipe underruns whenever all planes are disabled.
5409          * So diasble underrun reporting before all the planes get disabled.
5410          * FIXME: Need to fix the logic to work when we turn off all planes
5411          * but leave the pipe running.
5412          */
5413         if (IS_GEN2(dev))
5414                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5415
5416         /*
5417          * Vblank time updates from the shadow to live plane control register
5418          * are blocked if the memory self-refresh mode is active at that
5419          * moment. So to make sure the plane gets truly disabled, disable
5420          * first the self-refresh mode. The self-refresh enable bit in turn
5421          * will be checked/applied by the HW only at the next frame start
5422          * event which is after the vblank start event, so we need to have a
5423          * wait-for-vblank between disabling the plane and the pipe.
5424          */
5425         intel_set_memory_cxsr(dev_priv, false);
5426         intel_crtc_disable_planes(crtc);
5427
5428         /*
5429          * On gen2 planes are double buffered but the pipe isn't, so we must
5430          * wait for planes to fully turn off before disabling the pipe.
5431          * We also need to wait on all gmch platforms because of the
5432          * self-refresh mode constraint explained above.
5433          */
5434         intel_wait_for_vblank(dev, pipe);
5435
5436         for_each_encoder_on_crtc(dev, crtc, encoder)
5437                 encoder->disable(encoder);
5438
5439         drm_crtc_vblank_off(crtc);
5440         assert_vblank_disabled(crtc);
5441
5442         intel_disable_pipe(intel_crtc);
5443
5444         i9xx_pfit_disable(intel_crtc);
5445
5446         for_each_encoder_on_crtc(dev, crtc, encoder)
5447                 if (encoder->post_disable)
5448                         encoder->post_disable(encoder);
5449
5450         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5451                 if (IS_CHERRYVIEW(dev))
5452                         chv_disable_pll(dev_priv, pipe);
5453                 else if (IS_VALLEYVIEW(dev))
5454                         vlv_disable_pll(dev_priv, pipe);
5455                 else
5456                         i9xx_disable_pll(intel_crtc);
5457         }
5458
5459         if (!IS_GEN2(dev))
5460                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5461
5462         intel_crtc->active = false;
5463         intel_update_watermarks(crtc);
5464
5465         mutex_lock(&dev->struct_mutex);
5466         intel_fbc_update(dev);
5467         mutex_unlock(&dev->struct_mutex);
5468 }
5469
5470 static void i9xx_crtc_off(struct drm_crtc *crtc)
5471 {
5472 }
5473
5474 /* Master function to enable/disable CRTC and corresponding power wells */
5475 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5476 {
5477         struct drm_device *dev = crtc->dev;
5478         struct drm_i915_private *dev_priv = dev->dev_private;
5479         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5480         enum intel_display_power_domain domain;
5481         unsigned long domains;
5482
5483         if (enable) {
5484                 if (!intel_crtc->active) {
5485                         domains = get_crtc_power_domains(crtc);
5486                         for_each_power_domain(domain, domains)
5487                                 intel_display_power_get(dev_priv, domain);
5488                         intel_crtc->enabled_power_domains = domains;
5489
5490                         dev_priv->display.crtc_enable(crtc);
5491                 }
5492         } else {
5493                 if (intel_crtc->active) {
5494                         dev_priv->display.crtc_disable(crtc);
5495
5496                         domains = intel_crtc->enabled_power_domains;
5497                         for_each_power_domain(domain, domains)
5498                                 intel_display_power_put(dev_priv, domain);
5499                         intel_crtc->enabled_power_domains = 0;
5500                 }
5501         }
5502 }
5503
5504 /**
5505  * Sets the power management mode of the pipe and plane.
5506  */
5507 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5508 {
5509         struct drm_device *dev = crtc->dev;
5510         struct intel_encoder *intel_encoder;
5511         bool enable = false;
5512
5513         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5514                 enable |= intel_encoder->connectors_active;
5515
5516         intel_crtc_control(crtc, enable);
5517 }
5518
5519 static void intel_crtc_disable(struct drm_crtc *crtc)
5520 {
5521         struct drm_device *dev = crtc->dev;
5522         struct drm_connector *connector;
5523         struct drm_i915_private *dev_priv = dev->dev_private;
5524
5525         /* crtc should still be enabled when we disable it. */
5526         WARN_ON(!crtc->state->enable);
5527
5528         dev_priv->display.crtc_disable(crtc);
5529         dev_priv->display.off(crtc);
5530
5531         crtc->primary->funcs->disable_plane(crtc->primary);
5532
5533         /* Update computed state. */
5534         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5535                 if (!connector->encoder || !connector->encoder->crtc)
5536                         continue;
5537
5538                 if (connector->encoder->crtc != crtc)
5539                         continue;
5540
5541                 connector->dpms = DRM_MODE_DPMS_OFF;
5542                 to_intel_encoder(connector->encoder)->connectors_active = false;
5543         }
5544 }
5545
5546 void intel_encoder_destroy(struct drm_encoder *encoder)
5547 {
5548         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5549
5550         drm_encoder_cleanup(encoder);
5551         kfree(intel_encoder);
5552 }
5553
5554 /* Simple dpms helper for encoders with just one connector, no cloning and only
5555  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5556  * state of the entire output pipe. */
5557 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5558 {
5559         if (mode == DRM_MODE_DPMS_ON) {
5560                 encoder->connectors_active = true;
5561
5562                 intel_crtc_update_dpms(encoder->base.crtc);
5563         } else {
5564                 encoder->connectors_active = false;
5565
5566                 intel_crtc_update_dpms(encoder->base.crtc);
5567         }
5568 }
5569
5570 /* Cross check the actual hw state with our own modeset state tracking (and it's
5571  * internal consistency). */
5572 static void intel_connector_check_state(struct intel_connector *connector)
5573 {
5574         if (connector->get_hw_state(connector)) {
5575                 struct intel_encoder *encoder = connector->encoder;
5576                 struct drm_crtc *crtc;
5577                 bool encoder_enabled;
5578                 enum pipe pipe;
5579
5580                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5581                               connector->base.base.id,
5582                               connector->base.name);
5583
5584                 /* there is no real hw state for MST connectors */
5585                 if (connector->mst_port)
5586                         return;
5587
5588                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5589                      "wrong connector dpms state\n");
5590                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5591                      "active connector not linked to encoder\n");
5592
5593                 if (encoder) {
5594                         I915_STATE_WARN(!encoder->connectors_active,
5595                              "encoder->connectors_active not set\n");
5596
5597                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5598                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5599                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
5600                                 return;
5601
5602                         crtc = encoder->base.crtc;
5603
5604                         I915_STATE_WARN(!crtc->state->enable,
5605                                         "crtc not enabled\n");
5606                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5607                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5608                              "encoder active on the wrong pipe\n");
5609                 }
5610         }
5611 }
5612
5613 /* Even simpler default implementation, if there's really no special case to
5614  * consider. */
5615 void intel_connector_dpms(struct drm_connector *connector, int mode)
5616 {
5617         /* All the simple cases only support two dpms states. */
5618         if (mode != DRM_MODE_DPMS_ON)
5619                 mode = DRM_MODE_DPMS_OFF;
5620
5621         if (mode == connector->dpms)
5622                 return;
5623
5624         connector->dpms = mode;
5625
5626         /* Only need to change hw state when actually enabled */
5627         if (connector->encoder)
5628                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5629
5630         intel_modeset_check_state(connector->dev);
5631 }
5632
5633 /* Simple connector->get_hw_state implementation for encoders that support only
5634  * one connector and no cloning and hence the encoder state determines the state
5635  * of the connector. */
5636 bool intel_connector_get_hw_state(struct intel_connector *connector)
5637 {
5638         enum pipe pipe = 0;
5639         struct intel_encoder *encoder = connector->encoder;
5640
5641         return encoder->get_hw_state(encoder, &pipe);
5642 }
5643
5644 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5645 {
5646         struct intel_crtc *crtc =
5647                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5648
5649         if (crtc->base.state->enable &&
5650             crtc->config->has_pch_encoder)
5651                 return crtc->config->fdi_lanes;
5652
5653         return 0;
5654 }
5655
5656 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5657                                      struct intel_crtc_state *pipe_config)
5658 {
5659         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5660                       pipe_name(pipe), pipe_config->fdi_lanes);
5661         if (pipe_config->fdi_lanes > 4) {
5662                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5663                               pipe_name(pipe), pipe_config->fdi_lanes);
5664                 return false;
5665         }
5666
5667         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5668                 if (pipe_config->fdi_lanes > 2) {
5669                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5670                                       pipe_config->fdi_lanes);
5671                         return false;
5672                 } else {
5673                         return true;
5674                 }
5675         }
5676
5677         if (INTEL_INFO(dev)->num_pipes == 2)
5678                 return true;
5679
5680         /* Ivybridge 3 pipe is really complicated */
5681         switch (pipe) {
5682         case PIPE_A:
5683                 return true;
5684         case PIPE_B:
5685                 if (pipe_config->fdi_lanes > 2 &&
5686                     pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5687                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5688                                       pipe_name(pipe), pipe_config->fdi_lanes);
5689                         return false;
5690                 }
5691                 return true;
5692         case PIPE_C:
5693                 if (pipe_config->fdi_lanes > 2) {
5694                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5695                                       pipe_name(pipe), pipe_config->fdi_lanes);
5696                         return false;
5697                 }
5698                 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5699                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5700                         return false;
5701                 }
5702                 return true;
5703         default:
5704                 BUG();
5705         }
5706 }
5707
5708 #define RETRY 1
5709 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5710                                        struct intel_crtc_state *pipe_config)
5711 {
5712         struct drm_device *dev = intel_crtc->base.dev;
5713         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5714         int lane, link_bw, fdi_dotclock;
5715         bool setup_ok, needs_recompute = false;
5716
5717 retry:
5718         /* FDI is a binary signal running at ~2.7GHz, encoding
5719          * each output octet as 10 bits. The actual frequency
5720          * is stored as a divider into a 100MHz clock, and the
5721          * mode pixel clock is stored in units of 1KHz.
5722          * Hence the bw of each lane in terms of the mode signal
5723          * is:
5724          */
5725         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5726
5727         fdi_dotclock = adjusted_mode->crtc_clock;
5728
5729         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5730                                            pipe_config->pipe_bpp);
5731
5732         pipe_config->fdi_lanes = lane;
5733
5734         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5735                                link_bw, &pipe_config->fdi_m_n);
5736
5737         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5738                                             intel_crtc->pipe, pipe_config);
5739         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5740                 pipe_config->pipe_bpp -= 2*3;
5741                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5742                               pipe_config->pipe_bpp);
5743                 needs_recompute = true;
5744                 pipe_config->bw_constrained = true;
5745
5746                 goto retry;
5747         }
5748
5749         if (needs_recompute)
5750                 return RETRY;
5751
5752         return setup_ok ? 0 : -EINVAL;
5753 }
5754
5755 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5756                                    struct intel_crtc_state *pipe_config)
5757 {
5758         pipe_config->ips_enabled = i915.enable_ips &&
5759                                    hsw_crtc_supports_ips(crtc) &&
5760                                    pipe_config->pipe_bpp <= 24;
5761 }
5762
5763 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5764                                      struct intel_crtc_state *pipe_config)
5765 {
5766         struct drm_device *dev = crtc->base.dev;
5767         struct drm_i915_private *dev_priv = dev->dev_private;
5768         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5769
5770         /* FIXME should check pixel clock limits on all platforms */
5771         if (INTEL_INFO(dev)->gen < 4) {
5772                 int clock_limit =
5773                         dev_priv->display.get_display_clock_speed(dev);
5774
5775                 /*
5776                  * Enable pixel doubling when the dot clock
5777                  * is > 90% of the (display) core speed.
5778                  *
5779                  * GDG double wide on either pipe,
5780                  * otherwise pipe A only.
5781                  */
5782                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5783                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5784                         clock_limit *= 2;
5785                         pipe_config->double_wide = true;
5786                 }
5787
5788                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5789                         return -EINVAL;
5790         }
5791
5792         /*
5793          * Pipe horizontal size must be even in:
5794          * - DVO ganged mode
5795          * - LVDS dual channel mode
5796          * - Double wide pipe
5797          */
5798         if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5799              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5800                 pipe_config->pipe_src_w &= ~1;
5801
5802         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5803          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5804          */
5805         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5806                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5807                 return -EINVAL;
5808
5809         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5810                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5811         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5812                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5813                  * for lvds. */
5814                 pipe_config->pipe_bpp = 8*3;
5815         }
5816
5817         if (HAS_IPS(dev))
5818                 hsw_compute_ips_config(crtc, pipe_config);
5819
5820         if (pipe_config->has_pch_encoder)
5821                 return ironlake_fdi_compute_config(crtc, pipe_config);
5822
5823         return 0;
5824 }
5825
5826 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5827 {
5828         struct drm_i915_private *dev_priv = dev->dev_private;
5829         u32 val;
5830         int divider;
5831
5832         if (dev_priv->hpll_freq == 0)
5833                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5834
5835         mutex_lock(&dev_priv->dpio_lock);
5836         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5837         mutex_unlock(&dev_priv->dpio_lock);
5838
5839         divider = val & DISPLAY_FREQUENCY_VALUES;
5840
5841         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5842              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5843              "cdclk change in progress\n");
5844
5845         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5846 }
5847
5848 static int i945_get_display_clock_speed(struct drm_device *dev)
5849 {
5850         return 400000;
5851 }
5852
5853 static int i915_get_display_clock_speed(struct drm_device *dev)
5854 {
5855         return 333000;
5856 }
5857
5858 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5859 {
5860         return 200000;
5861 }
5862
5863 static int pnv_get_display_clock_speed(struct drm_device *dev)
5864 {
5865         u16 gcfgc = 0;
5866
5867         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5868
5869         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5870         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5871                 return 267000;
5872         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5873                 return 333000;
5874         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5875                 return 444000;
5876         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5877                 return 200000;
5878         default:
5879                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5880         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5881                 return 133000;
5882         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5883                 return 167000;
5884         }
5885 }
5886
5887 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5888 {
5889         u16 gcfgc = 0;
5890
5891         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5892
5893         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5894                 return 133000;
5895         else {
5896                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5897                 case GC_DISPLAY_CLOCK_333_MHZ:
5898                         return 333000;
5899                 default:
5900                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5901                         return 190000;
5902                 }
5903         }
5904 }
5905
5906 static int i865_get_display_clock_speed(struct drm_device *dev)
5907 {
5908         return 266000;
5909 }
5910
5911 static int i855_get_display_clock_speed(struct drm_device *dev)
5912 {
5913         u16 hpllcc = 0;
5914         /* Assume that the hardware is in the high speed state.  This
5915          * should be the default.
5916          */
5917         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5918         case GC_CLOCK_133_200:
5919         case GC_CLOCK_100_200:
5920                 return 200000;
5921         case GC_CLOCK_166_250:
5922                 return 250000;
5923         case GC_CLOCK_100_133:
5924                 return 133000;
5925         }
5926
5927         /* Shouldn't happen */
5928         return 0;
5929 }
5930
5931 static int i830_get_display_clock_speed(struct drm_device *dev)
5932 {
5933         return 133000;
5934 }
5935
5936 static void
5937 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5938 {
5939         while (*num > DATA_LINK_M_N_MASK ||
5940                *den > DATA_LINK_M_N_MASK) {
5941                 *num >>= 1;
5942                 *den >>= 1;
5943         }
5944 }
5945
5946 static void compute_m_n(unsigned int m, unsigned int n,
5947                         uint32_t *ret_m, uint32_t *ret_n)
5948 {
5949         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5950         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5951         intel_reduce_m_n_ratio(ret_m, ret_n);
5952 }
5953
5954 void
5955 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5956                        int pixel_clock, int link_clock,
5957                        struct intel_link_m_n *m_n)
5958 {
5959         m_n->tu = 64;
5960
5961         compute_m_n(bits_per_pixel * pixel_clock,
5962                     link_clock * nlanes * 8,
5963                     &m_n->gmch_m, &m_n->gmch_n);
5964
5965         compute_m_n(pixel_clock, link_clock,
5966                     &m_n->link_m, &m_n->link_n);
5967 }
5968
5969 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5970 {
5971         if (i915.panel_use_ssc >= 0)
5972                 return i915.panel_use_ssc != 0;
5973         return dev_priv->vbt.lvds_use_ssc
5974                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5975 }
5976
5977 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5978 {
5979         struct drm_device *dev = crtc->base.dev;
5980         struct drm_i915_private *dev_priv = dev->dev_private;
5981         int refclk;
5982
5983         if (IS_VALLEYVIEW(dev)) {
5984                 refclk = 100000;
5985         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5986             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5987                 refclk = dev_priv->vbt.lvds_ssc_freq;
5988                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5989         } else if (!IS_GEN2(dev)) {
5990                 refclk = 96000;
5991         } else {
5992                 refclk = 48000;
5993         }
5994
5995         return refclk;
5996 }
5997
5998 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5999 {
6000         return (1 << dpll->n) << 16 | dpll->m2;
6001 }
6002
6003 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6004 {
6005         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6006 }
6007
6008 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6009                                      struct intel_crtc_state *crtc_state,
6010                                      intel_clock_t *reduced_clock)
6011 {
6012         struct drm_device *dev = crtc->base.dev;
6013         u32 fp, fp2 = 0;
6014
6015         if (IS_PINEVIEW(dev)) {
6016                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6017                 if (reduced_clock)
6018                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6019         } else {
6020                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6021                 if (reduced_clock)
6022                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6023         }
6024
6025         crtc_state->dpll_hw_state.fp0 = fp;
6026
6027         crtc->lowfreq_avail = false;
6028         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6029             reduced_clock) {
6030                 crtc_state->dpll_hw_state.fp1 = fp2;
6031                 crtc->lowfreq_avail = true;
6032         } else {
6033                 crtc_state->dpll_hw_state.fp1 = fp;
6034         }
6035 }
6036
6037 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6038                 pipe)
6039 {
6040         u32 reg_val;
6041
6042         /*
6043          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6044          * and set it to a reasonable value instead.
6045          */
6046         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6047         reg_val &= 0xffffff00;
6048         reg_val |= 0x00000030;
6049         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6050
6051         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6052         reg_val &= 0x8cffffff;
6053         reg_val = 0x8c000000;
6054         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6055
6056         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6057         reg_val &= 0xffffff00;
6058         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6059
6060         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6061         reg_val &= 0x00ffffff;
6062         reg_val |= 0xb0000000;
6063         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6064 }
6065
6066 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6067                                          struct intel_link_m_n *m_n)
6068 {
6069         struct drm_device *dev = crtc->base.dev;
6070         struct drm_i915_private *dev_priv = dev->dev_private;
6071         int pipe = crtc->pipe;
6072
6073         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6074         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6075         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6076         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6077 }
6078
6079 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6080                                          struct intel_link_m_n *m_n,
6081                                          struct intel_link_m_n *m2_n2)
6082 {
6083         struct drm_device *dev = crtc->base.dev;
6084         struct drm_i915_private *dev_priv = dev->dev_private;
6085         int pipe = crtc->pipe;
6086         enum transcoder transcoder = crtc->config->cpu_transcoder;
6087
6088         if (INTEL_INFO(dev)->gen >= 5) {
6089                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6090                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6091                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6092                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6093                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6094                  * for gen < 8) and if DRRS is supported (to make sure the
6095                  * registers are not unnecessarily accessed).
6096                  */
6097                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6098                         crtc->config->has_drrs) {
6099                         I915_WRITE(PIPE_DATA_M2(transcoder),
6100                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6101                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6102                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6103                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6104                 }
6105         } else {
6106                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6107                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6108                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6109                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6110         }
6111 }
6112
6113 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6114 {
6115         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6116
6117         if (m_n == M1_N1) {
6118                 dp_m_n = &crtc->config->dp_m_n;
6119                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6120         } else if (m_n == M2_N2) {
6121
6122                 /*
6123                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6124                  * needs to be programmed into M1_N1.
6125                  */
6126                 dp_m_n = &crtc->config->dp_m2_n2;
6127         } else {
6128                 DRM_ERROR("Unsupported divider value\n");
6129                 return;
6130         }
6131
6132         if (crtc->config->has_pch_encoder)
6133                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6134         else
6135                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6136 }
6137
6138 static void vlv_update_pll(struct intel_crtc *crtc,
6139                            struct intel_crtc_state *pipe_config)
6140 {
6141         u32 dpll, dpll_md;
6142
6143         /*
6144          * Enable DPIO clock input. We should never disable the reference
6145          * clock for pipe B, since VGA hotplug / manual detection depends
6146          * on it.
6147          */
6148         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6149                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6150         /* We should never disable this, set it here for state tracking */
6151         if (crtc->pipe == PIPE_B)
6152                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6153         dpll |= DPLL_VCO_ENABLE;
6154         pipe_config->dpll_hw_state.dpll = dpll;
6155
6156         dpll_md = (pipe_config->pixel_multiplier - 1)
6157                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6158         pipe_config->dpll_hw_state.dpll_md = dpll_md;
6159 }
6160
6161 static void vlv_prepare_pll(struct intel_crtc *crtc,
6162                             const struct intel_crtc_state *pipe_config)
6163 {
6164         struct drm_device *dev = crtc->base.dev;
6165         struct drm_i915_private *dev_priv = dev->dev_private;
6166         int pipe = crtc->pipe;
6167         u32 mdiv;
6168         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6169         u32 coreclk, reg_val;
6170
6171         mutex_lock(&dev_priv->dpio_lock);
6172
6173         bestn = pipe_config->dpll.n;
6174         bestm1 = pipe_config->dpll.m1;
6175         bestm2 = pipe_config->dpll.m2;
6176         bestp1 = pipe_config->dpll.p1;
6177         bestp2 = pipe_config->dpll.p2;
6178
6179         /* See eDP HDMI DPIO driver vbios notes doc */
6180
6181         /* PLL B needs special handling */
6182         if (pipe == PIPE_B)
6183                 vlv_pllb_recal_opamp(dev_priv, pipe);
6184
6185         /* Set up Tx target for periodic Rcomp update */
6186         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6187
6188         /* Disable target IRef on PLL */
6189         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6190         reg_val &= 0x00ffffff;
6191         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6192
6193         /* Disable fast lock */
6194         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6195
6196         /* Set idtafcrecal before PLL is enabled */
6197         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6198         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6199         mdiv |= ((bestn << DPIO_N_SHIFT));
6200         mdiv |= (1 << DPIO_K_SHIFT);
6201
6202         /*
6203          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6204          * but we don't support that).
6205          * Note: don't use the DAC post divider as it seems unstable.
6206          */
6207         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6208         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6209
6210         mdiv |= DPIO_ENABLE_CALIBRATION;
6211         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6212
6213         /* Set HBR and RBR LPF coefficients */
6214         if (pipe_config->port_clock == 162000 ||
6215             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6216             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6217                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6218                                  0x009f0003);
6219         else
6220                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6221                                  0x00d0000f);
6222
6223         if (pipe_config->has_dp_encoder) {
6224                 /* Use SSC source */
6225                 if (pipe == PIPE_A)
6226                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6227                                          0x0df40000);
6228                 else
6229                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6230                                          0x0df70000);
6231         } else { /* HDMI or VGA */
6232                 /* Use bend source */
6233                 if (pipe == PIPE_A)
6234                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6235                                          0x0df70000);
6236                 else
6237                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6238                                          0x0df40000);
6239         }
6240
6241         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6242         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6243         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6244             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6245                 coreclk |= 0x01000000;
6246         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6247
6248         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6249         mutex_unlock(&dev_priv->dpio_lock);
6250 }
6251
6252 static void chv_update_pll(struct intel_crtc *crtc,
6253                            struct intel_crtc_state *pipe_config)
6254 {
6255         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6256                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6257                 DPLL_VCO_ENABLE;
6258         if (crtc->pipe != PIPE_A)
6259                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6260
6261         pipe_config->dpll_hw_state.dpll_md =
6262                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6263 }
6264
6265 static void chv_prepare_pll(struct intel_crtc *crtc,
6266                             const struct intel_crtc_state *pipe_config)
6267 {
6268         struct drm_device *dev = crtc->base.dev;
6269         struct drm_i915_private *dev_priv = dev->dev_private;
6270         int pipe = crtc->pipe;
6271         int dpll_reg = DPLL(crtc->pipe);
6272         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6273         u32 loopfilter, tribuf_calcntr;
6274         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6275         u32 dpio_val;
6276         int vco;
6277
6278         bestn = pipe_config->dpll.n;
6279         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6280         bestm1 = pipe_config->dpll.m1;
6281         bestm2 = pipe_config->dpll.m2 >> 22;
6282         bestp1 = pipe_config->dpll.p1;
6283         bestp2 = pipe_config->dpll.p2;
6284         vco = pipe_config->dpll.vco;
6285         dpio_val = 0;
6286         loopfilter = 0;
6287
6288         /*
6289          * Enable Refclk and SSC
6290          */
6291         I915_WRITE(dpll_reg,
6292                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6293
6294         mutex_lock(&dev_priv->dpio_lock);
6295
6296         /* p1 and p2 divider */
6297         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6298                         5 << DPIO_CHV_S1_DIV_SHIFT |
6299                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6300                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6301                         1 << DPIO_CHV_K_DIV_SHIFT);
6302
6303         /* Feedback post-divider - m2 */
6304         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6305
6306         /* Feedback refclk divider - n and m1 */
6307         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6308                         DPIO_CHV_M1_DIV_BY_2 |
6309                         1 << DPIO_CHV_N_DIV_SHIFT);
6310
6311         /* M2 fraction division */
6312         if (bestm2_frac)
6313                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6314
6315         /* M2 fraction division enable */
6316         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6317         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6318         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6319         if (bestm2_frac)
6320                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6321         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6322
6323         /* Program digital lock detect threshold */
6324         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6325         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6326                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6327         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6328         if (!bestm2_frac)
6329                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6330         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6331
6332         /* Loop filter */
6333         if (vco == 5400000) {
6334                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6335                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6336                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6337                 tribuf_calcntr = 0x9;
6338         } else if (vco <= 6200000) {
6339                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6340                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6341                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6342                 tribuf_calcntr = 0x9;
6343         } else if (vco <= 6480000) {
6344                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6345                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6346                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6347                 tribuf_calcntr = 0x8;
6348         } else {
6349                 /* Not supported. Apply the same limits as in the max case */
6350                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6351                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6352                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6353                 tribuf_calcntr = 0;
6354         }
6355         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6356
6357         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6358         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6359         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6360         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6361
6362         /* AFC Recal */
6363         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6364                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6365                         DPIO_AFC_RECAL);
6366
6367         mutex_unlock(&dev_priv->dpio_lock);
6368 }
6369
6370 /**
6371  * vlv_force_pll_on - forcibly enable just the PLL
6372  * @dev_priv: i915 private structure
6373  * @pipe: pipe PLL to enable
6374  * @dpll: PLL configuration
6375  *
6376  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6377  * in cases where we need the PLL enabled even when @pipe is not going to
6378  * be enabled.
6379  */
6380 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6381                       const struct dpll *dpll)
6382 {
6383         struct intel_crtc *crtc =
6384                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6385         struct intel_crtc_state pipe_config = {
6386                 .pixel_multiplier = 1,
6387                 .dpll = *dpll,
6388         };
6389
6390         if (IS_CHERRYVIEW(dev)) {
6391                 chv_update_pll(crtc, &pipe_config);
6392                 chv_prepare_pll(crtc, &pipe_config);
6393                 chv_enable_pll(crtc, &pipe_config);
6394         } else {
6395                 vlv_update_pll(crtc, &pipe_config);
6396                 vlv_prepare_pll(crtc, &pipe_config);
6397                 vlv_enable_pll(crtc, &pipe_config);
6398         }
6399 }
6400
6401 /**
6402  * vlv_force_pll_off - forcibly disable just the PLL
6403  * @dev_priv: i915 private structure
6404  * @pipe: pipe PLL to disable
6405  *
6406  * Disable the PLL for @pipe. To be used in cases where we need
6407  * the PLL enabled even when @pipe is not going to be enabled.
6408  */
6409 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6410 {
6411         if (IS_CHERRYVIEW(dev))
6412                 chv_disable_pll(to_i915(dev), pipe);
6413         else
6414                 vlv_disable_pll(to_i915(dev), pipe);
6415 }
6416
6417 static void i9xx_update_pll(struct intel_crtc *crtc,
6418                             struct intel_crtc_state *crtc_state,
6419                             intel_clock_t *reduced_clock,
6420                             int num_connectors)
6421 {
6422         struct drm_device *dev = crtc->base.dev;
6423         struct drm_i915_private *dev_priv = dev->dev_private;
6424         u32 dpll;
6425         bool is_sdvo;
6426         struct dpll *clock = &crtc_state->dpll;
6427
6428         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6429
6430         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6431                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6432
6433         dpll = DPLL_VGA_MODE_DIS;
6434
6435         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6436                 dpll |= DPLLB_MODE_LVDS;
6437         else
6438                 dpll |= DPLLB_MODE_DAC_SERIAL;
6439
6440         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6441                 dpll |= (crtc_state->pixel_multiplier - 1)
6442                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6443         }
6444
6445         if (is_sdvo)
6446                 dpll |= DPLL_SDVO_HIGH_SPEED;
6447
6448         if (crtc_state->has_dp_encoder)
6449                 dpll |= DPLL_SDVO_HIGH_SPEED;
6450
6451         /* compute bitmask from p1 value */
6452         if (IS_PINEVIEW(dev))
6453                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6454         else {
6455                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6456                 if (IS_G4X(dev) && reduced_clock)
6457                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6458         }
6459         switch (clock->p2) {
6460         case 5:
6461                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6462                 break;
6463         case 7:
6464                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6465                 break;
6466         case 10:
6467                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6468                 break;
6469         case 14:
6470                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6471                 break;
6472         }
6473         if (INTEL_INFO(dev)->gen >= 4)
6474                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6475
6476         if (crtc_state->sdvo_tv_clock)
6477                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6478         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6479                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6480                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6481         else
6482                 dpll |= PLL_REF_INPUT_DREFCLK;
6483
6484         dpll |= DPLL_VCO_ENABLE;
6485         crtc_state->dpll_hw_state.dpll = dpll;
6486
6487         if (INTEL_INFO(dev)->gen >= 4) {
6488                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6489                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6490                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6491         }
6492 }
6493
6494 static void i8xx_update_pll(struct intel_crtc *crtc,
6495                             struct intel_crtc_state *crtc_state,
6496                             intel_clock_t *reduced_clock,
6497                             int num_connectors)
6498 {
6499         struct drm_device *dev = crtc->base.dev;
6500         struct drm_i915_private *dev_priv = dev->dev_private;
6501         u32 dpll;
6502         struct dpll *clock = &crtc_state->dpll;
6503
6504         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6505
6506         dpll = DPLL_VGA_MODE_DIS;
6507
6508         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6509                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6510         } else {
6511                 if (clock->p1 == 2)
6512                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6513                 else
6514                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6515                 if (clock->p2 == 4)
6516                         dpll |= PLL_P2_DIVIDE_BY_4;
6517         }
6518
6519         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6520                 dpll |= DPLL_DVO_2X_MODE;
6521
6522         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6523                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6524                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6525         else
6526                 dpll |= PLL_REF_INPUT_DREFCLK;
6527
6528         dpll |= DPLL_VCO_ENABLE;
6529         crtc_state->dpll_hw_state.dpll = dpll;
6530 }
6531
6532 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6533 {
6534         struct drm_device *dev = intel_crtc->base.dev;
6535         struct drm_i915_private *dev_priv = dev->dev_private;
6536         enum pipe pipe = intel_crtc->pipe;
6537         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6538         struct drm_display_mode *adjusted_mode =
6539                 &intel_crtc->config->base.adjusted_mode;
6540         uint32_t crtc_vtotal, crtc_vblank_end;
6541         int vsyncshift = 0;
6542
6543         /* We need to be careful not to changed the adjusted mode, for otherwise
6544          * the hw state checker will get angry at the mismatch. */
6545         crtc_vtotal = adjusted_mode->crtc_vtotal;
6546         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6547
6548         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6549                 /* the chip adds 2 halflines automatically */
6550                 crtc_vtotal -= 1;
6551                 crtc_vblank_end -= 1;
6552
6553                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6554                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6555                 else
6556                         vsyncshift = adjusted_mode->crtc_hsync_start -
6557                                 adjusted_mode->crtc_htotal / 2;
6558                 if (vsyncshift < 0)
6559                         vsyncshift += adjusted_mode->crtc_htotal;
6560         }
6561
6562         if (INTEL_INFO(dev)->gen > 3)
6563                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6564
6565         I915_WRITE(HTOTAL(cpu_transcoder),
6566                    (adjusted_mode->crtc_hdisplay - 1) |
6567                    ((adjusted_mode->crtc_htotal - 1) << 16));
6568         I915_WRITE(HBLANK(cpu_transcoder),
6569                    (adjusted_mode->crtc_hblank_start - 1) |
6570                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6571         I915_WRITE(HSYNC(cpu_transcoder),
6572                    (adjusted_mode->crtc_hsync_start - 1) |
6573                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6574
6575         I915_WRITE(VTOTAL(cpu_transcoder),
6576                    (adjusted_mode->crtc_vdisplay - 1) |
6577                    ((crtc_vtotal - 1) << 16));
6578         I915_WRITE(VBLANK(cpu_transcoder),
6579                    (adjusted_mode->crtc_vblank_start - 1) |
6580                    ((crtc_vblank_end - 1) << 16));
6581         I915_WRITE(VSYNC(cpu_transcoder),
6582                    (adjusted_mode->crtc_vsync_start - 1) |
6583                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6584
6585         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6586          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6587          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6588          * bits. */
6589         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6590             (pipe == PIPE_B || pipe == PIPE_C))
6591                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6592
6593         /* pipesrc controls the size that is scaled from, which should
6594          * always be the user's requested size.
6595          */
6596         I915_WRITE(PIPESRC(pipe),
6597                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6598                    (intel_crtc->config->pipe_src_h - 1));
6599 }
6600
6601 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6602                                    struct intel_crtc_state *pipe_config)
6603 {
6604         struct drm_device *dev = crtc->base.dev;
6605         struct drm_i915_private *dev_priv = dev->dev_private;
6606         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6607         uint32_t tmp;
6608
6609         tmp = I915_READ(HTOTAL(cpu_transcoder));
6610         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6611         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6612         tmp = I915_READ(HBLANK(cpu_transcoder));
6613         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6614         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6615         tmp = I915_READ(HSYNC(cpu_transcoder));
6616         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6617         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6618
6619         tmp = I915_READ(VTOTAL(cpu_transcoder));
6620         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6621         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6622         tmp = I915_READ(VBLANK(cpu_transcoder));
6623         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6624         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6625         tmp = I915_READ(VSYNC(cpu_transcoder));
6626         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6627         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6628
6629         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6630                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6631                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6632                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6633         }
6634
6635         tmp = I915_READ(PIPESRC(crtc->pipe));
6636         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6637         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6638
6639         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6640         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6641 }
6642
6643 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6644                                  struct intel_crtc_state *pipe_config)
6645 {
6646         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6647         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6648         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6649         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6650
6651         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6652         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6653         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6654         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6655
6656         mode->flags = pipe_config->base.adjusted_mode.flags;
6657
6658         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6659         mode->flags |= pipe_config->base.adjusted_mode.flags;
6660 }
6661
6662 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6663 {
6664         struct drm_device *dev = intel_crtc->base.dev;
6665         struct drm_i915_private *dev_priv = dev->dev_private;
6666         uint32_t pipeconf;
6667
6668         pipeconf = 0;
6669
6670         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6671             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6672                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6673
6674         if (intel_crtc->config->double_wide)
6675                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6676
6677         /* only g4x and later have fancy bpc/dither controls */
6678         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6679                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6680                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6681                         pipeconf |= PIPECONF_DITHER_EN |
6682                                     PIPECONF_DITHER_TYPE_SP;
6683
6684                 switch (intel_crtc->config->pipe_bpp) {
6685                 case 18:
6686                         pipeconf |= PIPECONF_6BPC;
6687                         break;
6688                 case 24:
6689                         pipeconf |= PIPECONF_8BPC;
6690                         break;
6691                 case 30:
6692                         pipeconf |= PIPECONF_10BPC;
6693                         break;
6694                 default:
6695                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6696                         BUG();
6697                 }
6698         }
6699
6700         if (HAS_PIPE_CXSR(dev)) {
6701                 if (intel_crtc->lowfreq_avail) {
6702                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6703                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6704                 } else {
6705                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6706                 }
6707         }
6708
6709         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6710                 if (INTEL_INFO(dev)->gen < 4 ||
6711                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6712                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6713                 else
6714                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6715         } else
6716                 pipeconf |= PIPECONF_PROGRESSIVE;
6717
6718         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6719                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6720
6721         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6722         POSTING_READ(PIPECONF(intel_crtc->pipe));
6723 }
6724
6725 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6726                                    struct intel_crtc_state *crtc_state)
6727 {
6728         struct drm_device *dev = crtc->base.dev;
6729         struct drm_i915_private *dev_priv = dev->dev_private;
6730         int refclk, num_connectors = 0;
6731         intel_clock_t clock, reduced_clock;
6732         bool ok, has_reduced_clock = false;
6733         bool is_lvds = false, is_dsi = false;
6734         struct intel_encoder *encoder;
6735         const intel_limit_t *limit;
6736
6737         for_each_intel_encoder(dev, encoder) {
6738                 if (encoder->new_crtc != crtc)
6739                         continue;
6740
6741                 switch (encoder->type) {
6742                 case INTEL_OUTPUT_LVDS:
6743                         is_lvds = true;
6744                         break;
6745                 case INTEL_OUTPUT_DSI:
6746                         is_dsi = true;
6747                         break;
6748                 default:
6749                         break;
6750                 }
6751
6752                 num_connectors++;
6753         }
6754
6755         if (is_dsi)
6756                 return 0;
6757
6758         if (!crtc_state->clock_set) {
6759                 refclk = i9xx_get_refclk(crtc, num_connectors);
6760
6761                 /*
6762                  * Returns a set of divisors for the desired target clock with
6763                  * the given refclk, or FALSE.  The returned values represent
6764                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6765                  * 2) / p1 / p2.
6766                  */
6767                 limit = intel_limit(crtc, refclk);
6768                 ok = dev_priv->display.find_dpll(limit, crtc,
6769                                                  crtc_state->port_clock,
6770                                                  refclk, NULL, &clock);
6771                 if (!ok) {
6772                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6773                         return -EINVAL;
6774                 }
6775
6776                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6777                         /*
6778                          * Ensure we match the reduced clock's P to the target
6779                          * clock.  If the clocks don't match, we can't switch
6780                          * the display clock by using the FP0/FP1. In such case
6781                          * we will disable the LVDS downclock feature.
6782                          */
6783                         has_reduced_clock =
6784                                 dev_priv->display.find_dpll(limit, crtc,
6785                                                             dev_priv->lvds_downclock,
6786                                                             refclk, &clock,
6787                                                             &reduced_clock);
6788                 }
6789                 /* Compat-code for transition, will disappear. */
6790                 crtc_state->dpll.n = clock.n;
6791                 crtc_state->dpll.m1 = clock.m1;
6792                 crtc_state->dpll.m2 = clock.m2;
6793                 crtc_state->dpll.p1 = clock.p1;
6794                 crtc_state->dpll.p2 = clock.p2;
6795         }
6796
6797         if (IS_GEN2(dev)) {
6798                 i8xx_update_pll(crtc, crtc_state,
6799                                 has_reduced_clock ? &reduced_clock : NULL,
6800                                 num_connectors);
6801         } else if (IS_CHERRYVIEW(dev)) {
6802                 chv_update_pll(crtc, crtc_state);
6803         } else if (IS_VALLEYVIEW(dev)) {
6804                 vlv_update_pll(crtc, crtc_state);
6805         } else {
6806                 i9xx_update_pll(crtc, crtc_state,
6807                                 has_reduced_clock ? &reduced_clock : NULL,
6808                                 num_connectors);
6809         }
6810
6811         return 0;
6812 }
6813
6814 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6815                                  struct intel_crtc_state *pipe_config)
6816 {
6817         struct drm_device *dev = crtc->base.dev;
6818         struct drm_i915_private *dev_priv = dev->dev_private;
6819         uint32_t tmp;
6820
6821         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6822                 return;
6823
6824         tmp = I915_READ(PFIT_CONTROL);
6825         if (!(tmp & PFIT_ENABLE))
6826                 return;
6827
6828         /* Check whether the pfit is attached to our pipe. */
6829         if (INTEL_INFO(dev)->gen < 4) {
6830                 if (crtc->pipe != PIPE_B)
6831                         return;
6832         } else {
6833                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6834                         return;
6835         }
6836
6837         pipe_config->gmch_pfit.control = tmp;
6838         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6839         if (INTEL_INFO(dev)->gen < 5)
6840                 pipe_config->gmch_pfit.lvds_border_bits =
6841                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6842 }
6843
6844 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6845                                struct intel_crtc_state *pipe_config)
6846 {
6847         struct drm_device *dev = crtc->base.dev;
6848         struct drm_i915_private *dev_priv = dev->dev_private;
6849         int pipe = pipe_config->cpu_transcoder;
6850         intel_clock_t clock;
6851         u32 mdiv;
6852         int refclk = 100000;
6853
6854         /* In case of MIPI DPLL will not even be used */
6855         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6856                 return;
6857
6858         mutex_lock(&dev_priv->dpio_lock);
6859         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6860         mutex_unlock(&dev_priv->dpio_lock);
6861
6862         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6863         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6864         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6865         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6866         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6867
6868         vlv_clock(refclk, &clock);
6869
6870         /* clock.dot is the fast clock */
6871         pipe_config->port_clock = clock.dot / 5;
6872 }
6873
6874 static void
6875 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6876                               struct intel_initial_plane_config *plane_config)
6877 {
6878         struct drm_device *dev = crtc->base.dev;
6879         struct drm_i915_private *dev_priv = dev->dev_private;
6880         u32 val, base, offset;
6881         int pipe = crtc->pipe, plane = crtc->plane;
6882         int fourcc, pixel_format;
6883         unsigned int aligned_height;
6884         struct drm_framebuffer *fb;
6885         struct intel_framebuffer *intel_fb;
6886
6887         val = I915_READ(DSPCNTR(plane));
6888         if (!(val & DISPLAY_PLANE_ENABLE))
6889                 return;
6890
6891         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6892         if (!intel_fb) {
6893                 DRM_DEBUG_KMS("failed to alloc fb\n");
6894                 return;
6895         }
6896
6897         fb = &intel_fb->base;
6898
6899         if (INTEL_INFO(dev)->gen >= 4) {
6900                 if (val & DISPPLANE_TILED) {
6901                         plane_config->tiling = I915_TILING_X;
6902                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6903                 }
6904         }
6905
6906         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6907         fourcc = i9xx_format_to_fourcc(pixel_format);
6908         fb->pixel_format = fourcc;
6909         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6910
6911         if (INTEL_INFO(dev)->gen >= 4) {
6912                 if (plane_config->tiling)
6913                         offset = I915_READ(DSPTILEOFF(plane));
6914                 else
6915                         offset = I915_READ(DSPLINOFF(plane));
6916                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6917         } else {
6918                 base = I915_READ(DSPADDR(plane));
6919         }
6920         plane_config->base = base;
6921
6922         val = I915_READ(PIPESRC(pipe));
6923         fb->width = ((val >> 16) & 0xfff) + 1;
6924         fb->height = ((val >> 0) & 0xfff) + 1;
6925
6926         val = I915_READ(DSPSTRIDE(pipe));
6927         fb->pitches[0] = val & 0xffffffc0;
6928
6929         aligned_height = intel_fb_align_height(dev, fb->height,
6930                                                fb->pixel_format,
6931                                                fb->modifier[0]);
6932
6933         plane_config->size = fb->pitches[0] * aligned_height;
6934
6935         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6936                       pipe_name(pipe), plane, fb->width, fb->height,
6937                       fb->bits_per_pixel, base, fb->pitches[0],
6938                       plane_config->size);
6939
6940         plane_config->fb = intel_fb;
6941 }
6942
6943 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6944                                struct intel_crtc_state *pipe_config)
6945 {
6946         struct drm_device *dev = crtc->base.dev;
6947         struct drm_i915_private *dev_priv = dev->dev_private;
6948         int pipe = pipe_config->cpu_transcoder;
6949         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6950         intel_clock_t clock;
6951         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6952         int refclk = 100000;
6953
6954         mutex_lock(&dev_priv->dpio_lock);
6955         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6956         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6957         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6958         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6959         mutex_unlock(&dev_priv->dpio_lock);
6960
6961         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6962         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6963         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6964         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6965         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6966
6967         chv_clock(refclk, &clock);
6968
6969         /* clock.dot is the fast clock */
6970         pipe_config->port_clock = clock.dot / 5;
6971 }
6972
6973 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6974                                  struct intel_crtc_state *pipe_config)
6975 {
6976         struct drm_device *dev = crtc->base.dev;
6977         struct drm_i915_private *dev_priv = dev->dev_private;
6978         uint32_t tmp;
6979
6980         if (!intel_display_power_is_enabled(dev_priv,
6981                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6982                 return false;
6983
6984         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6985         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6986
6987         tmp = I915_READ(PIPECONF(crtc->pipe));
6988         if (!(tmp & PIPECONF_ENABLE))
6989                 return false;
6990
6991         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6992                 switch (tmp & PIPECONF_BPC_MASK) {
6993                 case PIPECONF_6BPC:
6994                         pipe_config->pipe_bpp = 18;
6995                         break;
6996                 case PIPECONF_8BPC:
6997                         pipe_config->pipe_bpp = 24;
6998                         break;
6999                 case PIPECONF_10BPC:
7000                         pipe_config->pipe_bpp = 30;
7001                         break;
7002                 default:
7003                         break;
7004                 }
7005         }
7006
7007         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7008                 pipe_config->limited_color_range = true;
7009
7010         if (INTEL_INFO(dev)->gen < 4)
7011                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7012
7013         intel_get_pipe_timings(crtc, pipe_config);
7014
7015         i9xx_get_pfit_config(crtc, pipe_config);
7016
7017         if (INTEL_INFO(dev)->gen >= 4) {
7018                 tmp = I915_READ(DPLL_MD(crtc->pipe));
7019                 pipe_config->pixel_multiplier =
7020                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7021                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7022                 pipe_config->dpll_hw_state.dpll_md = tmp;
7023         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7024                 tmp = I915_READ(DPLL(crtc->pipe));
7025                 pipe_config->pixel_multiplier =
7026                         ((tmp & SDVO_MULTIPLIER_MASK)
7027                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7028         } else {
7029                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7030                  * port and will be fixed up in the encoder->get_config
7031                  * function. */
7032                 pipe_config->pixel_multiplier = 1;
7033         }
7034         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7035         if (!IS_VALLEYVIEW(dev)) {
7036                 /*
7037                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7038                  * on 830. Filter it out here so that we don't
7039                  * report errors due to that.
7040                  */
7041                 if (IS_I830(dev))
7042                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7043
7044                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7045                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7046         } else {
7047                 /* Mask out read-only status bits. */
7048                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7049                                                      DPLL_PORTC_READY_MASK |
7050                                                      DPLL_PORTB_READY_MASK);
7051         }
7052
7053         if (IS_CHERRYVIEW(dev))
7054                 chv_crtc_clock_get(crtc, pipe_config);
7055         else if (IS_VALLEYVIEW(dev))
7056                 vlv_crtc_clock_get(crtc, pipe_config);
7057         else
7058                 i9xx_crtc_clock_get(crtc, pipe_config);
7059
7060         return true;
7061 }
7062
7063 static void ironlake_init_pch_refclk(struct drm_device *dev)
7064 {
7065         struct drm_i915_private *dev_priv = dev->dev_private;
7066         struct intel_encoder *encoder;
7067         u32 val, final;
7068         bool has_lvds = false;
7069         bool has_cpu_edp = false;
7070         bool has_panel = false;
7071         bool has_ck505 = false;
7072         bool can_ssc = false;
7073
7074         /* We need to take the global config into account */
7075         for_each_intel_encoder(dev, encoder) {
7076                 switch (encoder->type) {
7077                 case INTEL_OUTPUT_LVDS:
7078                         has_panel = true;
7079                         has_lvds = true;
7080                         break;
7081                 case INTEL_OUTPUT_EDP:
7082                         has_panel = true;
7083                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7084                                 has_cpu_edp = true;
7085                         break;
7086                 default:
7087                         break;
7088                 }
7089         }
7090
7091         if (HAS_PCH_IBX(dev)) {
7092                 has_ck505 = dev_priv->vbt.display_clock_mode;
7093                 can_ssc = has_ck505;
7094         } else {
7095                 has_ck505 = false;
7096                 can_ssc = true;
7097         }
7098
7099         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7100                       has_panel, has_lvds, has_ck505);
7101
7102         /* Ironlake: try to setup display ref clock before DPLL
7103          * enabling. This is only under driver's control after
7104          * PCH B stepping, previous chipset stepping should be
7105          * ignoring this setting.
7106          */
7107         val = I915_READ(PCH_DREF_CONTROL);
7108
7109         /* As we must carefully and slowly disable/enable each source in turn,
7110          * compute the final state we want first and check if we need to
7111          * make any changes at all.
7112          */
7113         final = val;
7114         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7115         if (has_ck505)
7116                 final |= DREF_NONSPREAD_CK505_ENABLE;
7117         else
7118                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7119
7120         final &= ~DREF_SSC_SOURCE_MASK;
7121         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7122         final &= ~DREF_SSC1_ENABLE;
7123
7124         if (has_panel) {
7125                 final |= DREF_SSC_SOURCE_ENABLE;
7126
7127                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7128                         final |= DREF_SSC1_ENABLE;
7129
7130                 if (has_cpu_edp) {
7131                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7132                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7133                         else
7134                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7135                 } else
7136                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7137         } else {
7138                 final |= DREF_SSC_SOURCE_DISABLE;
7139                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7140         }
7141
7142         if (final == val)
7143                 return;
7144
7145         /* Always enable nonspread source */
7146         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7147
7148         if (has_ck505)
7149                 val |= DREF_NONSPREAD_CK505_ENABLE;
7150         else
7151                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7152
7153         if (has_panel) {
7154                 val &= ~DREF_SSC_SOURCE_MASK;
7155                 val |= DREF_SSC_SOURCE_ENABLE;
7156
7157                 /* SSC must be turned on before enabling the CPU output  */
7158                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7159                         DRM_DEBUG_KMS("Using SSC on panel\n");
7160                         val |= DREF_SSC1_ENABLE;
7161                 } else
7162                         val &= ~DREF_SSC1_ENABLE;
7163
7164                 /* Get SSC going before enabling the outputs */
7165                 I915_WRITE(PCH_DREF_CONTROL, val);
7166                 POSTING_READ(PCH_DREF_CONTROL);
7167                 udelay(200);
7168
7169                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7170
7171                 /* Enable CPU source on CPU attached eDP */
7172                 if (has_cpu_edp) {
7173                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7174                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7175                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7176                         } else
7177                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7178                 } else
7179                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7180
7181                 I915_WRITE(PCH_DREF_CONTROL, val);
7182                 POSTING_READ(PCH_DREF_CONTROL);
7183                 udelay(200);
7184         } else {
7185                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7186
7187                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7188
7189                 /* Turn off CPU output */
7190                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7191
7192                 I915_WRITE(PCH_DREF_CONTROL, val);
7193                 POSTING_READ(PCH_DREF_CONTROL);
7194                 udelay(200);
7195
7196                 /* Turn off the SSC source */
7197                 val &= ~DREF_SSC_SOURCE_MASK;
7198                 val |= DREF_SSC_SOURCE_DISABLE;
7199
7200                 /* Turn off SSC1 */
7201                 val &= ~DREF_SSC1_ENABLE;
7202
7203                 I915_WRITE(PCH_DREF_CONTROL, val);
7204                 POSTING_READ(PCH_DREF_CONTROL);
7205                 udelay(200);
7206         }
7207
7208         BUG_ON(val != final);
7209 }
7210
7211 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7212 {
7213         uint32_t tmp;
7214
7215         tmp = I915_READ(SOUTH_CHICKEN2);
7216         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7217         I915_WRITE(SOUTH_CHICKEN2, tmp);
7218
7219         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7220                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7221                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7222
7223         tmp = I915_READ(SOUTH_CHICKEN2);
7224         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7225         I915_WRITE(SOUTH_CHICKEN2, tmp);
7226
7227         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7228                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7229                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7230 }
7231
7232 /* WaMPhyProgramming:hsw */
7233 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7234 {
7235         uint32_t tmp;
7236
7237         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7238         tmp &= ~(0xFF << 24);
7239         tmp |= (0x12 << 24);
7240         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7241
7242         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7243         tmp |= (1 << 11);
7244         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7245
7246         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7247         tmp |= (1 << 11);
7248         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7249
7250         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7251         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7252         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7253
7254         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7255         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7256         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7257
7258         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7259         tmp &= ~(7 << 13);
7260         tmp |= (5 << 13);
7261         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7262
7263         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7264         tmp &= ~(7 << 13);
7265         tmp |= (5 << 13);
7266         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7267
7268         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7269         tmp &= ~0xFF;
7270         tmp |= 0x1C;
7271         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7272
7273         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7274         tmp &= ~0xFF;
7275         tmp |= 0x1C;
7276         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7277
7278         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7279         tmp &= ~(0xFF << 16);
7280         tmp |= (0x1C << 16);
7281         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7282
7283         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7284         tmp &= ~(0xFF << 16);
7285         tmp |= (0x1C << 16);
7286         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7287
7288         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7289         tmp |= (1 << 27);
7290         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7291
7292         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7293         tmp |= (1 << 27);
7294         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7295
7296         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7297         tmp &= ~(0xF << 28);
7298         tmp |= (4 << 28);
7299         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7300
7301         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7302         tmp &= ~(0xF << 28);
7303         tmp |= (4 << 28);
7304         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7305 }
7306
7307 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7308  * Programming" based on the parameters passed:
7309  * - Sequence to enable CLKOUT_DP
7310  * - Sequence to enable CLKOUT_DP without spread
7311  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7312  */
7313 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7314                                  bool with_fdi)
7315 {
7316         struct drm_i915_private *dev_priv = dev->dev_private;
7317         uint32_t reg, tmp;
7318
7319         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7320                 with_spread = true;
7321         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7322                  with_fdi, "LP PCH doesn't have FDI\n"))
7323                 with_fdi = false;
7324
7325         mutex_lock(&dev_priv->dpio_lock);
7326
7327         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7328         tmp &= ~SBI_SSCCTL_DISABLE;
7329         tmp |= SBI_SSCCTL_PATHALT;
7330         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7331
7332         udelay(24);
7333
7334         if (with_spread) {
7335                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7336                 tmp &= ~SBI_SSCCTL_PATHALT;
7337                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7338
7339                 if (with_fdi) {
7340                         lpt_reset_fdi_mphy(dev_priv);
7341                         lpt_program_fdi_mphy(dev_priv);
7342                 }
7343         }
7344
7345         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7346                SBI_GEN0 : SBI_DBUFF0;
7347         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7348         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7349         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7350
7351         mutex_unlock(&dev_priv->dpio_lock);
7352 }
7353
7354 /* Sequence to disable CLKOUT_DP */
7355 static void lpt_disable_clkout_dp(struct drm_device *dev)
7356 {
7357         struct drm_i915_private *dev_priv = dev->dev_private;
7358         uint32_t reg, tmp;
7359
7360         mutex_lock(&dev_priv->dpio_lock);
7361
7362         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7363                SBI_GEN0 : SBI_DBUFF0;
7364         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7365         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7366         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7367
7368         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7369         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7370                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7371                         tmp |= SBI_SSCCTL_PATHALT;
7372                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7373                         udelay(32);
7374                 }
7375                 tmp |= SBI_SSCCTL_DISABLE;
7376                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7377         }
7378
7379         mutex_unlock(&dev_priv->dpio_lock);
7380 }
7381
7382 static void lpt_init_pch_refclk(struct drm_device *dev)
7383 {
7384         struct intel_encoder *encoder;
7385         bool has_vga = false;
7386
7387         for_each_intel_encoder(dev, encoder) {
7388                 switch (encoder->type) {
7389                 case INTEL_OUTPUT_ANALOG:
7390                         has_vga = true;
7391                         break;
7392                 default:
7393                         break;
7394                 }
7395         }
7396
7397         if (has_vga)
7398                 lpt_enable_clkout_dp(dev, true, true);
7399         else
7400                 lpt_disable_clkout_dp(dev);
7401 }
7402
7403 /*
7404  * Initialize reference clocks when the driver loads
7405  */
7406 void intel_init_pch_refclk(struct drm_device *dev)
7407 {
7408         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7409                 ironlake_init_pch_refclk(dev);
7410         else if (HAS_PCH_LPT(dev))
7411                 lpt_init_pch_refclk(dev);
7412 }
7413
7414 static int ironlake_get_refclk(struct drm_crtc *crtc)
7415 {
7416         struct drm_device *dev = crtc->dev;
7417         struct drm_i915_private *dev_priv = dev->dev_private;
7418         struct intel_encoder *encoder;
7419         int num_connectors = 0;
7420         bool is_lvds = false;
7421
7422         for_each_intel_encoder(dev, encoder) {
7423                 if (encoder->new_crtc != to_intel_crtc(crtc))
7424                         continue;
7425
7426                 switch (encoder->type) {
7427                 case INTEL_OUTPUT_LVDS:
7428                         is_lvds = true;
7429                         break;
7430                 default:
7431                         break;
7432                 }
7433                 num_connectors++;
7434         }
7435
7436         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7437                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7438                               dev_priv->vbt.lvds_ssc_freq);
7439                 return dev_priv->vbt.lvds_ssc_freq;
7440         }
7441
7442         return 120000;
7443 }
7444
7445 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7446 {
7447         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7449         int pipe = intel_crtc->pipe;
7450         uint32_t val;
7451
7452         val = 0;
7453
7454         switch (intel_crtc->config->pipe_bpp) {
7455         case 18:
7456                 val |= PIPECONF_6BPC;
7457                 break;
7458         case 24:
7459                 val |= PIPECONF_8BPC;
7460                 break;
7461         case 30:
7462                 val |= PIPECONF_10BPC;
7463                 break;
7464         case 36:
7465                 val |= PIPECONF_12BPC;
7466                 break;
7467         default:
7468                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7469                 BUG();
7470         }
7471
7472         if (intel_crtc->config->dither)
7473                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7474
7475         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7476                 val |= PIPECONF_INTERLACED_ILK;
7477         else
7478                 val |= PIPECONF_PROGRESSIVE;
7479
7480         if (intel_crtc->config->limited_color_range)
7481                 val |= PIPECONF_COLOR_RANGE_SELECT;
7482
7483         I915_WRITE(PIPECONF(pipe), val);
7484         POSTING_READ(PIPECONF(pipe));
7485 }
7486
7487 /*
7488  * Set up the pipe CSC unit.
7489  *
7490  * Currently only full range RGB to limited range RGB conversion
7491  * is supported, but eventually this should handle various
7492  * RGB<->YCbCr scenarios as well.
7493  */
7494 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7495 {
7496         struct drm_device *dev = crtc->dev;
7497         struct drm_i915_private *dev_priv = dev->dev_private;
7498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7499         int pipe = intel_crtc->pipe;
7500         uint16_t coeff = 0x7800; /* 1.0 */
7501
7502         /*
7503          * TODO: Check what kind of values actually come out of the pipe
7504          * with these coeff/postoff values and adjust to get the best
7505          * accuracy. Perhaps we even need to take the bpc value into
7506          * consideration.
7507          */
7508
7509         if (intel_crtc->config->limited_color_range)
7510                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7511
7512         /*
7513          * GY/GU and RY/RU should be the other way around according
7514          * to BSpec, but reality doesn't agree. Just set them up in
7515          * a way that results in the correct picture.
7516          */
7517         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7518         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7519
7520         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7521         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7522
7523         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7524         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7525
7526         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7527         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7528         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7529
7530         if (INTEL_INFO(dev)->gen > 6) {
7531                 uint16_t postoff = 0;
7532
7533                 if (intel_crtc->config->limited_color_range)
7534                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7535
7536                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7537                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7538                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7539
7540                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7541         } else {
7542                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7543
7544                 if (intel_crtc->config->limited_color_range)
7545                         mode |= CSC_BLACK_SCREEN_OFFSET;
7546
7547                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7548         }
7549 }
7550
7551 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7552 {
7553         struct drm_device *dev = crtc->dev;
7554         struct drm_i915_private *dev_priv = dev->dev_private;
7555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7556         enum pipe pipe = intel_crtc->pipe;
7557         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7558         uint32_t val;
7559
7560         val = 0;
7561
7562         if (IS_HASWELL(dev) && intel_crtc->config->dither)
7563                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7564
7565         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7566                 val |= PIPECONF_INTERLACED_ILK;
7567         else
7568                 val |= PIPECONF_PROGRESSIVE;
7569
7570         I915_WRITE(PIPECONF(cpu_transcoder), val);
7571         POSTING_READ(PIPECONF(cpu_transcoder));
7572
7573         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7574         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7575
7576         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7577                 val = 0;
7578
7579                 switch (intel_crtc->config->pipe_bpp) {
7580                 case 18:
7581                         val |= PIPEMISC_DITHER_6_BPC;
7582                         break;
7583                 case 24:
7584                         val |= PIPEMISC_DITHER_8_BPC;
7585                         break;
7586                 case 30:
7587                         val |= PIPEMISC_DITHER_10_BPC;
7588                         break;
7589                 case 36:
7590                         val |= PIPEMISC_DITHER_12_BPC;
7591                         break;
7592                 default:
7593                         /* Case prevented by pipe_config_set_bpp. */
7594                         BUG();
7595                 }
7596
7597                 if (intel_crtc->config->dither)
7598                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7599
7600                 I915_WRITE(PIPEMISC(pipe), val);
7601         }
7602 }
7603
7604 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7605                                     struct intel_crtc_state *crtc_state,
7606                                     intel_clock_t *clock,
7607                                     bool *has_reduced_clock,
7608                                     intel_clock_t *reduced_clock)
7609 {
7610         struct drm_device *dev = crtc->dev;
7611         struct drm_i915_private *dev_priv = dev->dev_private;
7612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7613         int refclk;
7614         const intel_limit_t *limit;
7615         bool ret, is_lvds = false;
7616
7617         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7618
7619         refclk = ironlake_get_refclk(crtc);
7620
7621         /*
7622          * Returns a set of divisors for the desired target clock with the given
7623          * refclk, or FALSE.  The returned values represent the clock equation:
7624          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7625          */
7626         limit = intel_limit(intel_crtc, refclk);
7627         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7628                                           crtc_state->port_clock,
7629                                           refclk, NULL, clock);
7630         if (!ret)
7631                 return false;
7632
7633         if (is_lvds && dev_priv->lvds_downclock_avail) {
7634                 /*
7635                  * Ensure we match the reduced clock's P to the target clock.
7636                  * If the clocks don't match, we can't switch the display clock
7637                  * by using the FP0/FP1. In such case we will disable the LVDS
7638                  * downclock feature.
7639                 */
7640                 *has_reduced_clock =
7641                         dev_priv->display.find_dpll(limit, intel_crtc,
7642                                                     dev_priv->lvds_downclock,
7643                                                     refclk, clock,
7644                                                     reduced_clock);
7645         }
7646
7647         return true;
7648 }
7649
7650 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7651 {
7652         /*
7653          * Account for spread spectrum to avoid
7654          * oversubscribing the link. Max center spread
7655          * is 2.5%; use 5% for safety's sake.
7656          */
7657         u32 bps = target_clock * bpp * 21 / 20;
7658         return DIV_ROUND_UP(bps, link_bw * 8);
7659 }
7660
7661 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7662 {
7663         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7664 }
7665
7666 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7667                                       struct intel_crtc_state *crtc_state,
7668                                       u32 *fp,
7669                                       intel_clock_t *reduced_clock, u32 *fp2)
7670 {
7671         struct drm_crtc *crtc = &intel_crtc->base;
7672         struct drm_device *dev = crtc->dev;
7673         struct drm_i915_private *dev_priv = dev->dev_private;
7674         struct intel_encoder *intel_encoder;
7675         uint32_t dpll;
7676         int factor, num_connectors = 0;
7677         bool is_lvds = false, is_sdvo = false;
7678
7679         for_each_intel_encoder(dev, intel_encoder) {
7680                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7681                         continue;
7682
7683                 switch (intel_encoder->type) {
7684                 case INTEL_OUTPUT_LVDS:
7685                         is_lvds = true;
7686                         break;
7687                 case INTEL_OUTPUT_SDVO:
7688                 case INTEL_OUTPUT_HDMI:
7689                         is_sdvo = true;
7690                         break;
7691                 default:
7692                         break;
7693                 }
7694
7695                 num_connectors++;
7696         }
7697
7698         /* Enable autotuning of the PLL clock (if permissible) */
7699         factor = 21;
7700         if (is_lvds) {
7701                 if ((intel_panel_use_ssc(dev_priv) &&
7702                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7703                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7704                         factor = 25;
7705         } else if (crtc_state->sdvo_tv_clock)
7706                 factor = 20;
7707
7708         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7709                 *fp |= FP_CB_TUNE;
7710
7711         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7712                 *fp2 |= FP_CB_TUNE;
7713
7714         dpll = 0;
7715
7716         if (is_lvds)
7717                 dpll |= DPLLB_MODE_LVDS;
7718         else
7719                 dpll |= DPLLB_MODE_DAC_SERIAL;
7720
7721         dpll |= (crtc_state->pixel_multiplier - 1)
7722                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7723
7724         if (is_sdvo)
7725                 dpll |= DPLL_SDVO_HIGH_SPEED;
7726         if (crtc_state->has_dp_encoder)
7727                 dpll |= DPLL_SDVO_HIGH_SPEED;
7728
7729         /* compute bitmask from p1 value */
7730         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7731         /* also FPA1 */
7732         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7733
7734         switch (crtc_state->dpll.p2) {
7735         case 5:
7736                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7737                 break;
7738         case 7:
7739                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7740                 break;
7741         case 10:
7742                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7743                 break;
7744         case 14:
7745                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7746                 break;
7747         }
7748
7749         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7750                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7751         else
7752                 dpll |= PLL_REF_INPUT_DREFCLK;
7753
7754         return dpll | DPLL_VCO_ENABLE;
7755 }
7756
7757 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7758                                        struct intel_crtc_state *crtc_state)
7759 {
7760         struct drm_device *dev = crtc->base.dev;
7761         intel_clock_t clock, reduced_clock;
7762         u32 dpll = 0, fp = 0, fp2 = 0;
7763         bool ok, has_reduced_clock = false;
7764         bool is_lvds = false;
7765         struct intel_shared_dpll *pll;
7766
7767         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7768
7769         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7770              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7771
7772         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7773                                      &has_reduced_clock, &reduced_clock);
7774         if (!ok && !crtc_state->clock_set) {
7775                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7776                 return -EINVAL;
7777         }
7778         /* Compat-code for transition, will disappear. */
7779         if (!crtc_state->clock_set) {
7780                 crtc_state->dpll.n = clock.n;
7781                 crtc_state->dpll.m1 = clock.m1;
7782                 crtc_state->dpll.m2 = clock.m2;
7783                 crtc_state->dpll.p1 = clock.p1;
7784                 crtc_state->dpll.p2 = clock.p2;
7785         }
7786
7787         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7788         if (crtc_state->has_pch_encoder) {
7789                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7790                 if (has_reduced_clock)
7791                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7792
7793                 dpll = ironlake_compute_dpll(crtc, crtc_state,
7794                                              &fp, &reduced_clock,
7795                                              has_reduced_clock ? &fp2 : NULL);
7796
7797                 crtc_state->dpll_hw_state.dpll = dpll;
7798                 crtc_state->dpll_hw_state.fp0 = fp;
7799                 if (has_reduced_clock)
7800                         crtc_state->dpll_hw_state.fp1 = fp2;
7801                 else
7802                         crtc_state->dpll_hw_state.fp1 = fp;
7803
7804                 pll = intel_get_shared_dpll(crtc, crtc_state);
7805                 if (pll == NULL) {
7806                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7807                                          pipe_name(crtc->pipe));
7808                         return -EINVAL;
7809                 }
7810         }
7811
7812         if (is_lvds && has_reduced_clock)
7813                 crtc->lowfreq_avail = true;
7814         else
7815                 crtc->lowfreq_avail = false;
7816
7817         return 0;
7818 }
7819
7820 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7821                                          struct intel_link_m_n *m_n)
7822 {
7823         struct drm_device *dev = crtc->base.dev;
7824         struct drm_i915_private *dev_priv = dev->dev_private;
7825         enum pipe pipe = crtc->pipe;
7826
7827         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7828         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7829         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7830                 & ~TU_SIZE_MASK;
7831         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7832         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7833                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7834 }
7835
7836 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7837                                          enum transcoder transcoder,
7838                                          struct intel_link_m_n *m_n,
7839                                          struct intel_link_m_n *m2_n2)
7840 {
7841         struct drm_device *dev = crtc->base.dev;
7842         struct drm_i915_private *dev_priv = dev->dev_private;
7843         enum pipe pipe = crtc->pipe;
7844
7845         if (INTEL_INFO(dev)->gen >= 5) {
7846                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7847                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7848                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7849                         & ~TU_SIZE_MASK;
7850                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7851                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7852                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7853                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7854                  * gen < 8) and if DRRS is supported (to make sure the
7855                  * registers are not unnecessarily read).
7856                  */
7857                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7858                         crtc->config->has_drrs) {
7859                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7860                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7861                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7862                                         & ~TU_SIZE_MASK;
7863                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7864                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7865                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7866                 }
7867         } else {
7868                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7869                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7870                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7871                         & ~TU_SIZE_MASK;
7872                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7873                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7874                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7875         }
7876 }
7877
7878 void intel_dp_get_m_n(struct intel_crtc *crtc,
7879                       struct intel_crtc_state *pipe_config)
7880 {
7881         if (pipe_config->has_pch_encoder)
7882                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7883         else
7884                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7885                                              &pipe_config->dp_m_n,
7886                                              &pipe_config->dp_m2_n2);
7887 }
7888
7889 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7890                                         struct intel_crtc_state *pipe_config)
7891 {
7892         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7893                                      &pipe_config->fdi_m_n, NULL);
7894 }
7895
7896 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7897                                     struct intel_crtc_state *pipe_config)
7898 {
7899         struct drm_device *dev = crtc->base.dev;
7900         struct drm_i915_private *dev_priv = dev->dev_private;
7901         uint32_t tmp;
7902
7903         tmp = I915_READ(PS_CTL(crtc->pipe));
7904
7905         if (tmp & PS_ENABLE) {
7906                 pipe_config->pch_pfit.enabled = true;
7907                 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7908                 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7909         }
7910 }
7911
7912 static void
7913 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7914                                  struct intel_initial_plane_config *plane_config)
7915 {
7916         struct drm_device *dev = crtc->base.dev;
7917         struct drm_i915_private *dev_priv = dev->dev_private;
7918         u32 val, base, offset, stride_mult, tiling;
7919         int pipe = crtc->pipe;
7920         int fourcc, pixel_format;
7921         unsigned int aligned_height;
7922         struct drm_framebuffer *fb;
7923         struct intel_framebuffer *intel_fb;
7924
7925         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7926         if (!intel_fb) {
7927                 DRM_DEBUG_KMS("failed to alloc fb\n");
7928                 return;
7929         }
7930
7931         fb = &intel_fb->base;
7932
7933         val = I915_READ(PLANE_CTL(pipe, 0));
7934         if (!(val & PLANE_CTL_ENABLE))
7935                 goto error;
7936
7937         pixel_format = val & PLANE_CTL_FORMAT_MASK;
7938         fourcc = skl_format_to_fourcc(pixel_format,
7939                                       val & PLANE_CTL_ORDER_RGBX,
7940                                       val & PLANE_CTL_ALPHA_MASK);
7941         fb->pixel_format = fourcc;
7942         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7943
7944         tiling = val & PLANE_CTL_TILED_MASK;
7945         switch (tiling) {
7946         case PLANE_CTL_TILED_LINEAR:
7947                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7948                 break;
7949         case PLANE_CTL_TILED_X:
7950                 plane_config->tiling = I915_TILING_X;
7951                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7952                 break;
7953         case PLANE_CTL_TILED_Y:
7954                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7955                 break;
7956         case PLANE_CTL_TILED_YF:
7957                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7958                 break;
7959         default:
7960                 MISSING_CASE(tiling);
7961                 goto error;
7962         }
7963
7964         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7965         plane_config->base = base;
7966
7967         offset = I915_READ(PLANE_OFFSET(pipe, 0));
7968
7969         val = I915_READ(PLANE_SIZE(pipe, 0));
7970         fb->height = ((val >> 16) & 0xfff) + 1;
7971         fb->width = ((val >> 0) & 0x1fff) + 1;
7972
7973         val = I915_READ(PLANE_STRIDE(pipe, 0));
7974         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7975                                                 fb->pixel_format);
7976         fb->pitches[0] = (val & 0x3ff) * stride_mult;
7977
7978         aligned_height = intel_fb_align_height(dev, fb->height,
7979                                                fb->pixel_format,
7980                                                fb->modifier[0]);
7981
7982         plane_config->size = fb->pitches[0] * aligned_height;
7983
7984         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7985                       pipe_name(pipe), fb->width, fb->height,
7986                       fb->bits_per_pixel, base, fb->pitches[0],
7987                       plane_config->size);
7988
7989         plane_config->fb = intel_fb;
7990         return;
7991
7992 error:
7993         kfree(fb);
7994 }
7995
7996 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7997                                      struct intel_crtc_state *pipe_config)
7998 {
7999         struct drm_device *dev = crtc->base.dev;
8000         struct drm_i915_private *dev_priv = dev->dev_private;
8001         uint32_t tmp;
8002
8003         tmp = I915_READ(PF_CTL(crtc->pipe));
8004
8005         if (tmp & PF_ENABLE) {
8006                 pipe_config->pch_pfit.enabled = true;
8007                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8008                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8009
8010                 /* We currently do not free assignements of panel fitters on
8011                  * ivb/hsw (since we don't use the higher upscaling modes which
8012                  * differentiates them) so just WARN about this case for now. */
8013                 if (IS_GEN7(dev)) {
8014                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8015                                 PF_PIPE_SEL_IVB(crtc->pipe));
8016                 }
8017         }
8018 }
8019
8020 static void
8021 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8022                                   struct intel_initial_plane_config *plane_config)
8023 {
8024         struct drm_device *dev = crtc->base.dev;
8025         struct drm_i915_private *dev_priv = dev->dev_private;
8026         u32 val, base, offset;
8027         int pipe = crtc->pipe;
8028         int fourcc, pixel_format;
8029         unsigned int aligned_height;
8030         struct drm_framebuffer *fb;
8031         struct intel_framebuffer *intel_fb;
8032
8033         val = I915_READ(DSPCNTR(pipe));
8034         if (!(val & DISPLAY_PLANE_ENABLE))
8035                 return;
8036
8037         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8038         if (!intel_fb) {
8039                 DRM_DEBUG_KMS("failed to alloc fb\n");
8040                 return;
8041         }
8042
8043         fb = &intel_fb->base;
8044
8045         if (INTEL_INFO(dev)->gen >= 4) {
8046                 if (val & DISPPLANE_TILED) {
8047                         plane_config->tiling = I915_TILING_X;
8048                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8049                 }
8050         }
8051
8052         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8053         fourcc = i9xx_format_to_fourcc(pixel_format);
8054         fb->pixel_format = fourcc;
8055         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8056
8057         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8058         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8059                 offset = I915_READ(DSPOFFSET(pipe));
8060         } else {
8061                 if (plane_config->tiling)
8062                         offset = I915_READ(DSPTILEOFF(pipe));
8063                 else
8064                         offset = I915_READ(DSPLINOFF(pipe));
8065         }
8066         plane_config->base = base;
8067
8068         val = I915_READ(PIPESRC(pipe));
8069         fb->width = ((val >> 16) & 0xfff) + 1;
8070         fb->height = ((val >> 0) & 0xfff) + 1;
8071
8072         val = I915_READ(DSPSTRIDE(pipe));
8073         fb->pitches[0] = val & 0xffffffc0;
8074
8075         aligned_height = intel_fb_align_height(dev, fb->height,
8076                                                fb->pixel_format,
8077                                                fb->modifier[0]);
8078
8079         plane_config->size = fb->pitches[0] * aligned_height;
8080
8081         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8082                       pipe_name(pipe), fb->width, fb->height,
8083                       fb->bits_per_pixel, base, fb->pitches[0],
8084                       plane_config->size);
8085
8086         plane_config->fb = intel_fb;
8087 }
8088
8089 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8090                                      struct intel_crtc_state *pipe_config)
8091 {
8092         struct drm_device *dev = crtc->base.dev;
8093         struct drm_i915_private *dev_priv = dev->dev_private;
8094         uint32_t tmp;
8095
8096         if (!intel_display_power_is_enabled(dev_priv,
8097                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8098                 return false;
8099
8100         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8101         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8102
8103         tmp = I915_READ(PIPECONF(crtc->pipe));
8104         if (!(tmp & PIPECONF_ENABLE))
8105                 return false;
8106
8107         switch (tmp & PIPECONF_BPC_MASK) {
8108         case PIPECONF_6BPC:
8109                 pipe_config->pipe_bpp = 18;
8110                 break;
8111         case PIPECONF_8BPC:
8112                 pipe_config->pipe_bpp = 24;
8113                 break;
8114         case PIPECONF_10BPC:
8115                 pipe_config->pipe_bpp = 30;
8116                 break;
8117         case PIPECONF_12BPC:
8118                 pipe_config->pipe_bpp = 36;
8119                 break;
8120         default:
8121                 break;
8122         }
8123
8124         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8125                 pipe_config->limited_color_range = true;
8126
8127         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8128                 struct intel_shared_dpll *pll;
8129
8130                 pipe_config->has_pch_encoder = true;
8131
8132                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8133                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8134                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8135
8136                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8137
8138                 if (HAS_PCH_IBX(dev_priv->dev)) {
8139                         pipe_config->shared_dpll =
8140                                 (enum intel_dpll_id) crtc->pipe;
8141                 } else {
8142                         tmp = I915_READ(PCH_DPLL_SEL);
8143                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8144                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8145                         else
8146                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8147                 }
8148
8149                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8150
8151                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8152                                            &pipe_config->dpll_hw_state));
8153
8154                 tmp = pipe_config->dpll_hw_state.dpll;
8155                 pipe_config->pixel_multiplier =
8156                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8157                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8158
8159                 ironlake_pch_clock_get(crtc, pipe_config);
8160         } else {
8161                 pipe_config->pixel_multiplier = 1;
8162         }
8163
8164         intel_get_pipe_timings(crtc, pipe_config);
8165
8166         ironlake_get_pfit_config(crtc, pipe_config);
8167
8168         return true;
8169 }
8170
8171 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8172 {
8173         struct drm_device *dev = dev_priv->dev;
8174         struct intel_crtc *crtc;
8175
8176         for_each_intel_crtc(dev, crtc)
8177                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8178                      pipe_name(crtc->pipe));
8179
8180         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8181         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8182         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8183         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8184         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8185         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8186              "CPU PWM1 enabled\n");
8187         if (IS_HASWELL(dev))
8188                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8189                      "CPU PWM2 enabled\n");
8190         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8191              "PCH PWM1 enabled\n");
8192         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8193              "Utility pin enabled\n");
8194         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8195
8196         /*
8197          * In theory we can still leave IRQs enabled, as long as only the HPD
8198          * interrupts remain enabled. We used to check for that, but since it's
8199          * gen-specific and since we only disable LCPLL after we fully disable
8200          * the interrupts, the check below should be enough.
8201          */
8202         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8203 }
8204
8205 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8206 {
8207         struct drm_device *dev = dev_priv->dev;
8208
8209         if (IS_HASWELL(dev))
8210                 return I915_READ(D_COMP_HSW);
8211         else
8212                 return I915_READ(D_COMP_BDW);
8213 }
8214
8215 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8216 {
8217         struct drm_device *dev = dev_priv->dev;
8218
8219         if (IS_HASWELL(dev)) {
8220                 mutex_lock(&dev_priv->rps.hw_lock);
8221                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8222                                             val))
8223                         DRM_ERROR("Failed to write to D_COMP\n");
8224                 mutex_unlock(&dev_priv->rps.hw_lock);
8225         } else {
8226                 I915_WRITE(D_COMP_BDW, val);
8227                 POSTING_READ(D_COMP_BDW);
8228         }
8229 }
8230
8231 /*
8232  * This function implements pieces of two sequences from BSpec:
8233  * - Sequence for display software to disable LCPLL
8234  * - Sequence for display software to allow package C8+
8235  * The steps implemented here are just the steps that actually touch the LCPLL
8236  * register. Callers should take care of disabling all the display engine
8237  * functions, doing the mode unset, fixing interrupts, etc.
8238  */
8239 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8240                               bool switch_to_fclk, bool allow_power_down)
8241 {
8242         uint32_t val;
8243
8244         assert_can_disable_lcpll(dev_priv);
8245
8246         val = I915_READ(LCPLL_CTL);
8247
8248         if (switch_to_fclk) {
8249                 val |= LCPLL_CD_SOURCE_FCLK;
8250                 I915_WRITE(LCPLL_CTL, val);
8251
8252                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8253                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
8254                         DRM_ERROR("Switching to FCLK failed\n");
8255
8256                 val = I915_READ(LCPLL_CTL);
8257         }
8258
8259         val |= LCPLL_PLL_DISABLE;
8260         I915_WRITE(LCPLL_CTL, val);
8261         POSTING_READ(LCPLL_CTL);
8262
8263         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8264                 DRM_ERROR("LCPLL still locked\n");
8265
8266         val = hsw_read_dcomp(dev_priv);
8267         val |= D_COMP_COMP_DISABLE;
8268         hsw_write_dcomp(dev_priv, val);
8269         ndelay(100);
8270
8271         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8272                      1))
8273                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8274
8275         if (allow_power_down) {
8276                 val = I915_READ(LCPLL_CTL);
8277                 val |= LCPLL_POWER_DOWN_ALLOW;
8278                 I915_WRITE(LCPLL_CTL, val);
8279                 POSTING_READ(LCPLL_CTL);
8280         }
8281 }
8282
8283 /*
8284  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8285  * source.
8286  */
8287 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8288 {
8289         uint32_t val;
8290
8291         val = I915_READ(LCPLL_CTL);
8292
8293         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8294                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8295                 return;
8296
8297         /*
8298          * Make sure we're not on PC8 state before disabling PC8, otherwise
8299          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8300          */
8301         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8302
8303         if (val & LCPLL_POWER_DOWN_ALLOW) {
8304                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8305                 I915_WRITE(LCPLL_CTL, val);
8306                 POSTING_READ(LCPLL_CTL);
8307         }
8308
8309         val = hsw_read_dcomp(dev_priv);
8310         val |= D_COMP_COMP_FORCE;
8311         val &= ~D_COMP_COMP_DISABLE;
8312         hsw_write_dcomp(dev_priv, val);
8313
8314         val = I915_READ(LCPLL_CTL);
8315         val &= ~LCPLL_PLL_DISABLE;
8316         I915_WRITE(LCPLL_CTL, val);
8317
8318         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8319                 DRM_ERROR("LCPLL not locked yet\n");
8320
8321         if (val & LCPLL_CD_SOURCE_FCLK) {
8322                 val = I915_READ(LCPLL_CTL);
8323                 val &= ~LCPLL_CD_SOURCE_FCLK;
8324                 I915_WRITE(LCPLL_CTL, val);
8325
8326                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8327                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8328                         DRM_ERROR("Switching back to LCPLL failed\n");
8329         }
8330
8331         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8332 }
8333
8334 /*
8335  * Package states C8 and deeper are really deep PC states that can only be
8336  * reached when all the devices on the system allow it, so even if the graphics
8337  * device allows PC8+, it doesn't mean the system will actually get to these
8338  * states. Our driver only allows PC8+ when going into runtime PM.
8339  *
8340  * The requirements for PC8+ are that all the outputs are disabled, the power
8341  * well is disabled and most interrupts are disabled, and these are also
8342  * requirements for runtime PM. When these conditions are met, we manually do
8343  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8344  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8345  * hang the machine.
8346  *
8347  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8348  * the state of some registers, so when we come back from PC8+ we need to
8349  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8350  * need to take care of the registers kept by RC6. Notice that this happens even
8351  * if we don't put the device in PCI D3 state (which is what currently happens
8352  * because of the runtime PM support).
8353  *
8354  * For more, read "Display Sequences for Package C8" on the hardware
8355  * documentation.
8356  */
8357 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8358 {
8359         struct drm_device *dev = dev_priv->dev;
8360         uint32_t val;
8361
8362         DRM_DEBUG_KMS("Enabling package C8+\n");
8363
8364         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8365                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8366                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8367                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8368         }
8369
8370         lpt_disable_clkout_dp(dev);
8371         hsw_disable_lcpll(dev_priv, true, true);
8372 }
8373
8374 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8375 {
8376         struct drm_device *dev = dev_priv->dev;
8377         uint32_t val;
8378
8379         DRM_DEBUG_KMS("Disabling package C8+\n");
8380
8381         hsw_restore_lcpll(dev_priv);
8382         lpt_init_pch_refclk(dev);
8383
8384         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8385                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8386                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8387                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8388         }
8389
8390         intel_prepare_ddi(dev);
8391 }
8392
8393 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8394                                       struct intel_crtc_state *crtc_state)
8395 {
8396         if (!intel_ddi_pll_select(crtc, crtc_state))
8397                 return -EINVAL;
8398
8399         crtc->lowfreq_avail = false;
8400
8401         return 0;
8402 }
8403
8404 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8405                                 enum port port,
8406                                 struct intel_crtc_state *pipe_config)
8407 {
8408         u32 temp, dpll_ctl1;
8409
8410         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8411         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8412
8413         switch (pipe_config->ddi_pll_sel) {
8414         case SKL_DPLL0:
8415                 /*
8416                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8417                  * of the shared DPLL framework and thus needs to be read out
8418                  * separately
8419                  */
8420                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8421                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8422                 break;
8423         case SKL_DPLL1:
8424                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8425                 break;
8426         case SKL_DPLL2:
8427                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8428                 break;
8429         case SKL_DPLL3:
8430                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8431                 break;
8432         }
8433 }
8434
8435 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8436                                 enum port port,
8437                                 struct intel_crtc_state *pipe_config)
8438 {
8439         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8440
8441         switch (pipe_config->ddi_pll_sel) {
8442         case PORT_CLK_SEL_WRPLL1:
8443                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8444                 break;
8445         case PORT_CLK_SEL_WRPLL2:
8446                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8447                 break;
8448         }
8449 }
8450
8451 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8452                                        struct intel_crtc_state *pipe_config)
8453 {
8454         struct drm_device *dev = crtc->base.dev;
8455         struct drm_i915_private *dev_priv = dev->dev_private;
8456         struct intel_shared_dpll *pll;
8457         enum port port;
8458         uint32_t tmp;
8459
8460         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8461
8462         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8463
8464         if (IS_SKYLAKE(dev))
8465                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8466         else
8467                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8468
8469         if (pipe_config->shared_dpll >= 0) {
8470                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8471
8472                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8473                                            &pipe_config->dpll_hw_state));
8474         }
8475
8476         /*
8477          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8478          * DDI E. So just check whether this pipe is wired to DDI E and whether
8479          * the PCH transcoder is on.
8480          */
8481         if (INTEL_INFO(dev)->gen < 9 &&
8482             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8483                 pipe_config->has_pch_encoder = true;
8484
8485                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8486                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8487                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8488
8489                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8490         }
8491 }
8492
8493 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8494                                     struct intel_crtc_state *pipe_config)
8495 {
8496         struct drm_device *dev = crtc->base.dev;
8497         struct drm_i915_private *dev_priv = dev->dev_private;
8498         enum intel_display_power_domain pfit_domain;
8499         uint32_t tmp;
8500
8501         if (!intel_display_power_is_enabled(dev_priv,
8502                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8503                 return false;
8504
8505         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8506         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8507
8508         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8509         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8510                 enum pipe trans_edp_pipe;
8511                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8512                 default:
8513                         WARN(1, "unknown pipe linked to edp transcoder\n");
8514                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8515                 case TRANS_DDI_EDP_INPUT_A_ON:
8516                         trans_edp_pipe = PIPE_A;
8517                         break;
8518                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8519                         trans_edp_pipe = PIPE_B;
8520                         break;
8521                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8522                         trans_edp_pipe = PIPE_C;
8523                         break;
8524                 }
8525
8526                 if (trans_edp_pipe == crtc->pipe)
8527                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8528         }
8529
8530         if (!intel_display_power_is_enabled(dev_priv,
8531                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8532                 return false;
8533
8534         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8535         if (!(tmp & PIPECONF_ENABLE))
8536                 return false;
8537
8538         haswell_get_ddi_port_state(crtc, pipe_config);
8539
8540         intel_get_pipe_timings(crtc, pipe_config);
8541
8542         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8543         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8544                 if (IS_SKYLAKE(dev))
8545                         skylake_get_pfit_config(crtc, pipe_config);
8546                 else
8547                         ironlake_get_pfit_config(crtc, pipe_config);
8548         }
8549
8550         if (IS_HASWELL(dev))
8551                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8552                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8553
8554         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8555                 pipe_config->pixel_multiplier =
8556                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8557         } else {
8558                 pipe_config->pixel_multiplier = 1;
8559         }
8560
8561         return true;
8562 }
8563
8564 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8565 {
8566         struct drm_device *dev = crtc->dev;
8567         struct drm_i915_private *dev_priv = dev->dev_private;
8568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8569         uint32_t cntl = 0, size = 0;
8570
8571         if (base) {
8572                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8573                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8574                 unsigned int stride = roundup_pow_of_two(width) * 4;
8575
8576                 switch (stride) {
8577                 default:
8578                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8579                                   width, stride);
8580                         stride = 256;
8581                         /* fallthrough */
8582                 case 256:
8583                 case 512:
8584                 case 1024:
8585                 case 2048:
8586                         break;
8587                 }
8588
8589                 cntl |= CURSOR_ENABLE |
8590                         CURSOR_GAMMA_ENABLE |
8591                         CURSOR_FORMAT_ARGB |
8592                         CURSOR_STRIDE(stride);
8593
8594                 size = (height << 12) | width;
8595         }
8596
8597         if (intel_crtc->cursor_cntl != 0 &&
8598             (intel_crtc->cursor_base != base ||
8599              intel_crtc->cursor_size != size ||
8600              intel_crtc->cursor_cntl != cntl)) {
8601                 /* On these chipsets we can only modify the base/size/stride
8602                  * whilst the cursor is disabled.
8603                  */
8604                 I915_WRITE(_CURACNTR, 0);
8605                 POSTING_READ(_CURACNTR);
8606                 intel_crtc->cursor_cntl = 0;
8607         }
8608
8609         if (intel_crtc->cursor_base != base) {
8610                 I915_WRITE(_CURABASE, base);
8611                 intel_crtc->cursor_base = base;
8612         }
8613
8614         if (intel_crtc->cursor_size != size) {
8615                 I915_WRITE(CURSIZE, size);
8616                 intel_crtc->cursor_size = size;
8617         }
8618
8619         if (intel_crtc->cursor_cntl != cntl) {
8620                 I915_WRITE(_CURACNTR, cntl);
8621                 POSTING_READ(_CURACNTR);
8622                 intel_crtc->cursor_cntl = cntl;
8623         }
8624 }
8625
8626 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8627 {
8628         struct drm_device *dev = crtc->dev;
8629         struct drm_i915_private *dev_priv = dev->dev_private;
8630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8631         int pipe = intel_crtc->pipe;
8632         uint32_t cntl;
8633
8634         cntl = 0;
8635         if (base) {
8636                 cntl = MCURSOR_GAMMA_ENABLE;
8637                 switch (intel_crtc->base.cursor->state->crtc_w) {
8638                         case 64:
8639                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8640                                 break;
8641                         case 128:
8642                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8643                                 break;
8644                         case 256:
8645                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8646                                 break;
8647                         default:
8648                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8649                                 return;
8650                 }
8651                 cntl |= pipe << 28; /* Connect to correct pipe */
8652
8653                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8654                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8655         }
8656
8657         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8658                 cntl |= CURSOR_ROTATE_180;
8659
8660         if (intel_crtc->cursor_cntl != cntl) {
8661                 I915_WRITE(CURCNTR(pipe), cntl);
8662                 POSTING_READ(CURCNTR(pipe));
8663                 intel_crtc->cursor_cntl = cntl;
8664         }
8665
8666         /* and commit changes on next vblank */
8667         I915_WRITE(CURBASE(pipe), base);
8668         POSTING_READ(CURBASE(pipe));
8669
8670         intel_crtc->cursor_base = base;
8671 }
8672
8673 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8674 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8675                                      bool on)
8676 {
8677         struct drm_device *dev = crtc->dev;
8678         struct drm_i915_private *dev_priv = dev->dev_private;
8679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8680         int pipe = intel_crtc->pipe;
8681         int x = crtc->cursor_x;
8682         int y = crtc->cursor_y;
8683         u32 base = 0, pos = 0;
8684
8685         if (on)
8686                 base = intel_crtc->cursor_addr;
8687
8688         if (x >= intel_crtc->config->pipe_src_w)
8689                 base = 0;
8690
8691         if (y >= intel_crtc->config->pipe_src_h)
8692                 base = 0;
8693
8694         if (x < 0) {
8695                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8696                         base = 0;
8697
8698                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8699                 x = -x;
8700         }
8701         pos |= x << CURSOR_X_SHIFT;
8702
8703         if (y < 0) {
8704                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8705                         base = 0;
8706
8707                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8708                 y = -y;
8709         }
8710         pos |= y << CURSOR_Y_SHIFT;
8711
8712         if (base == 0 && intel_crtc->cursor_base == 0)
8713                 return;
8714
8715         I915_WRITE(CURPOS(pipe), pos);
8716
8717         /* ILK+ do this automagically */
8718         if (HAS_GMCH_DISPLAY(dev) &&
8719             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8720                 base += (intel_crtc->base.cursor->state->crtc_h *
8721                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8722         }
8723
8724         if (IS_845G(dev) || IS_I865G(dev))
8725                 i845_update_cursor(crtc, base);
8726         else
8727                 i9xx_update_cursor(crtc, base);
8728 }
8729
8730 static bool cursor_size_ok(struct drm_device *dev,
8731                            uint32_t width, uint32_t height)
8732 {
8733         if (width == 0 || height == 0)
8734                 return false;
8735
8736         /*
8737          * 845g/865g are special in that they are only limited by
8738          * the width of their cursors, the height is arbitrary up to
8739          * the precision of the register. Everything else requires
8740          * square cursors, limited to a few power-of-two sizes.
8741          */
8742         if (IS_845G(dev) || IS_I865G(dev)) {
8743                 if ((width & 63) != 0)
8744                         return false;
8745
8746                 if (width > (IS_845G(dev) ? 64 : 512))
8747                         return false;
8748
8749                 if (height > 1023)
8750                         return false;
8751         } else {
8752                 switch (width | height) {
8753                 case 256:
8754                 case 128:
8755                         if (IS_GEN2(dev))
8756                                 return false;
8757                 case 64:
8758                         break;
8759                 default:
8760                         return false;
8761                 }
8762         }
8763
8764         return true;
8765 }
8766
8767 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8768                                  u16 *blue, uint32_t start, uint32_t size)
8769 {
8770         int end = (start + size > 256) ? 256 : start + size, i;
8771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8772
8773         for (i = start; i < end; i++) {
8774                 intel_crtc->lut_r[i] = red[i] >> 8;
8775                 intel_crtc->lut_g[i] = green[i] >> 8;
8776                 intel_crtc->lut_b[i] = blue[i] >> 8;
8777         }
8778
8779         intel_crtc_load_lut(crtc);
8780 }
8781
8782 /* VESA 640x480x72Hz mode to set on the pipe */
8783 static struct drm_display_mode load_detect_mode = {
8784         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8785                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8786 };
8787
8788 struct drm_framebuffer *
8789 __intel_framebuffer_create(struct drm_device *dev,
8790                            struct drm_mode_fb_cmd2 *mode_cmd,
8791                            struct drm_i915_gem_object *obj)
8792 {
8793         struct intel_framebuffer *intel_fb;
8794         int ret;
8795
8796         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8797         if (!intel_fb) {
8798                 drm_gem_object_unreference(&obj->base);
8799                 return ERR_PTR(-ENOMEM);
8800         }
8801
8802         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8803         if (ret)
8804                 goto err;
8805
8806         return &intel_fb->base;
8807 err:
8808         drm_gem_object_unreference(&obj->base);
8809         kfree(intel_fb);
8810
8811         return ERR_PTR(ret);
8812 }
8813
8814 static struct drm_framebuffer *
8815 intel_framebuffer_create(struct drm_device *dev,
8816                          struct drm_mode_fb_cmd2 *mode_cmd,
8817                          struct drm_i915_gem_object *obj)
8818 {
8819         struct drm_framebuffer *fb;
8820         int ret;
8821
8822         ret = i915_mutex_lock_interruptible(dev);
8823         if (ret)
8824                 return ERR_PTR(ret);
8825         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8826         mutex_unlock(&dev->struct_mutex);
8827
8828         return fb;
8829 }
8830
8831 static u32
8832 intel_framebuffer_pitch_for_width(int width, int bpp)
8833 {
8834         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8835         return ALIGN(pitch, 64);
8836 }
8837
8838 static u32
8839 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8840 {
8841         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8842         return PAGE_ALIGN(pitch * mode->vdisplay);
8843 }
8844
8845 static struct drm_framebuffer *
8846 intel_framebuffer_create_for_mode(struct drm_device *dev,
8847                                   struct drm_display_mode *mode,
8848                                   int depth, int bpp)
8849 {
8850         struct drm_i915_gem_object *obj;
8851         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8852
8853         obj = i915_gem_alloc_object(dev,
8854                                     intel_framebuffer_size_for_mode(mode, bpp));
8855         if (obj == NULL)
8856                 return ERR_PTR(-ENOMEM);
8857
8858         mode_cmd.width = mode->hdisplay;
8859         mode_cmd.height = mode->vdisplay;
8860         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8861                                                                 bpp);
8862         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8863
8864         return intel_framebuffer_create(dev, &mode_cmd, obj);
8865 }
8866
8867 static struct drm_framebuffer *
8868 mode_fits_in_fbdev(struct drm_device *dev,
8869                    struct drm_display_mode *mode)
8870 {
8871 #ifdef CONFIG_DRM_I915_FBDEV
8872         struct drm_i915_private *dev_priv = dev->dev_private;
8873         struct drm_i915_gem_object *obj;
8874         struct drm_framebuffer *fb;
8875
8876         if (!dev_priv->fbdev)
8877                 return NULL;
8878
8879         if (!dev_priv->fbdev->fb)
8880                 return NULL;
8881
8882         obj = dev_priv->fbdev->fb->obj;
8883         BUG_ON(!obj);
8884
8885         fb = &dev_priv->fbdev->fb->base;
8886         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8887                                                                fb->bits_per_pixel))
8888                 return NULL;
8889
8890         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8891                 return NULL;
8892
8893         return fb;
8894 #else
8895         return NULL;
8896 #endif
8897 }
8898
8899 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8900                                 struct drm_display_mode *mode,
8901                                 struct intel_load_detect_pipe *old,
8902                                 struct drm_modeset_acquire_ctx *ctx)
8903 {
8904         struct intel_crtc *intel_crtc;
8905         struct intel_encoder *intel_encoder =
8906                 intel_attached_encoder(connector);
8907         struct drm_crtc *possible_crtc;
8908         struct drm_encoder *encoder = &intel_encoder->base;
8909         struct drm_crtc *crtc = NULL;
8910         struct drm_device *dev = encoder->dev;
8911         struct drm_framebuffer *fb;
8912         struct drm_mode_config *config = &dev->mode_config;
8913         struct drm_atomic_state *state = NULL;
8914         struct drm_connector_state *connector_state;
8915         int ret, i = -1;
8916
8917         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8918                       connector->base.id, connector->name,
8919                       encoder->base.id, encoder->name);
8920
8921 retry:
8922         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8923         if (ret)
8924                 goto fail_unlock;
8925
8926         /*
8927          * Algorithm gets a little messy:
8928          *
8929          *   - if the connector already has an assigned crtc, use it (but make
8930          *     sure it's on first)
8931          *
8932          *   - try to find the first unused crtc that can drive this connector,
8933          *     and use that if we find one
8934          */
8935
8936         /* See if we already have a CRTC for this connector */
8937         if (encoder->crtc) {
8938                 crtc = encoder->crtc;
8939
8940                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8941                 if (ret)
8942                         goto fail_unlock;
8943                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8944                 if (ret)
8945                         goto fail_unlock;
8946
8947                 old->dpms_mode = connector->dpms;
8948                 old->load_detect_temp = false;
8949
8950                 /* Make sure the crtc and connector are running */
8951                 if (connector->dpms != DRM_MODE_DPMS_ON)
8952                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8953
8954                 return true;
8955         }
8956
8957         /* Find an unused one (if possible) */
8958         for_each_crtc(dev, possible_crtc) {
8959                 i++;
8960                 if (!(encoder->possible_crtcs & (1 << i)))
8961                         continue;
8962                 if (possible_crtc->state->enable)
8963                         continue;
8964                 /* This can occur when applying the pipe A quirk on resume. */
8965                 if (to_intel_crtc(possible_crtc)->new_enabled)
8966                         continue;
8967
8968                 crtc = possible_crtc;
8969                 break;
8970         }
8971
8972         /*
8973          * If we didn't find an unused CRTC, don't use any.
8974          */
8975         if (!crtc) {
8976                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8977                 goto fail_unlock;
8978         }
8979
8980         ret = drm_modeset_lock(&crtc->mutex, ctx);
8981         if (ret)
8982                 goto fail_unlock;
8983         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8984         if (ret)
8985                 goto fail_unlock;
8986         intel_encoder->new_crtc = to_intel_crtc(crtc);
8987         to_intel_connector(connector)->new_encoder = intel_encoder;
8988
8989         intel_crtc = to_intel_crtc(crtc);
8990         intel_crtc->new_enabled = true;
8991         intel_crtc->new_config = intel_crtc->config;
8992         old->dpms_mode = connector->dpms;
8993         old->load_detect_temp = true;
8994         old->release_fb = NULL;
8995
8996         state = drm_atomic_state_alloc(dev);
8997         if (!state)
8998                 return false;
8999
9000         state->acquire_ctx = ctx;
9001
9002         connector_state = drm_atomic_get_connector_state(state, connector);
9003         if (IS_ERR(connector_state)) {
9004                 ret = PTR_ERR(connector_state);
9005                 goto fail;
9006         }
9007
9008         connector_state->crtc = crtc;
9009         connector_state->best_encoder = &intel_encoder->base;
9010
9011         if (!mode)
9012                 mode = &load_detect_mode;
9013
9014         /* We need a framebuffer large enough to accommodate all accesses
9015          * that the plane may generate whilst we perform load detection.
9016          * We can not rely on the fbcon either being present (we get called
9017          * during its initialisation to detect all boot displays, or it may
9018          * not even exist) or that it is large enough to satisfy the
9019          * requested mode.
9020          */
9021         fb = mode_fits_in_fbdev(dev, mode);
9022         if (fb == NULL) {
9023                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9024                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9025                 old->release_fb = fb;
9026         } else
9027                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9028         if (IS_ERR(fb)) {
9029                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9030                 goto fail;
9031         }
9032
9033         if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
9034                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9035                 if (old->release_fb)
9036                         old->release_fb->funcs->destroy(old->release_fb);
9037                 goto fail;
9038         }
9039         crtc->primary->crtc = crtc;
9040
9041         /* let the connector get through one full cycle before testing */
9042         intel_wait_for_vblank(dev, intel_crtc->pipe);
9043         return true;
9044
9045  fail:
9046         intel_crtc->new_enabled = crtc->state->enable;
9047         if (intel_crtc->new_enabled)
9048                 intel_crtc->new_config = intel_crtc->config;
9049         else
9050                 intel_crtc->new_config = NULL;
9051 fail_unlock:
9052         if (state) {
9053                 drm_atomic_state_free(state);
9054                 state = NULL;
9055         }
9056
9057         if (ret == -EDEADLK) {
9058                 drm_modeset_backoff(ctx);
9059                 goto retry;
9060         }
9061
9062         return false;
9063 }
9064
9065 void intel_release_load_detect_pipe(struct drm_connector *connector,
9066                                     struct intel_load_detect_pipe *old,
9067                                     struct drm_modeset_acquire_ctx *ctx)
9068 {
9069         struct drm_device *dev = connector->dev;
9070         struct intel_encoder *intel_encoder =
9071                 intel_attached_encoder(connector);
9072         struct drm_encoder *encoder = &intel_encoder->base;
9073         struct drm_crtc *crtc = encoder->crtc;
9074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9075         struct drm_atomic_state *state;
9076         struct drm_connector_state *connector_state;
9077
9078         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9079                       connector->base.id, connector->name,
9080                       encoder->base.id, encoder->name);
9081
9082         if (old->load_detect_temp) {
9083                 state = drm_atomic_state_alloc(dev);
9084                 if (!state)
9085                         goto fail;
9086
9087                 state->acquire_ctx = ctx;
9088
9089                 connector_state = drm_atomic_get_connector_state(state, connector);
9090                 if (IS_ERR(connector_state))
9091                         goto fail;
9092
9093                 to_intel_connector(connector)->new_encoder = NULL;
9094                 intel_encoder->new_crtc = NULL;
9095                 intel_crtc->new_enabled = false;
9096                 intel_crtc->new_config = NULL;
9097
9098                 connector_state->best_encoder = NULL;
9099                 connector_state->crtc = NULL;
9100
9101                 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9102
9103                 drm_atomic_state_free(state);
9104
9105                 if (old->release_fb) {
9106                         drm_framebuffer_unregister_private(old->release_fb);
9107                         drm_framebuffer_unreference(old->release_fb);
9108                 }
9109
9110                 return;
9111         }
9112
9113         /* Switch crtc and encoder back off if necessary */
9114         if (old->dpms_mode != DRM_MODE_DPMS_ON)
9115                 connector->funcs->dpms(connector, old->dpms_mode);
9116
9117         return;
9118 fail:
9119         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9120         drm_atomic_state_free(state);
9121 }
9122
9123 static int i9xx_pll_refclk(struct drm_device *dev,
9124                            const struct intel_crtc_state *pipe_config)
9125 {
9126         struct drm_i915_private *dev_priv = dev->dev_private;
9127         u32 dpll = pipe_config->dpll_hw_state.dpll;
9128
9129         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9130                 return dev_priv->vbt.lvds_ssc_freq;
9131         else if (HAS_PCH_SPLIT(dev))
9132                 return 120000;
9133         else if (!IS_GEN2(dev))
9134                 return 96000;
9135         else
9136                 return 48000;
9137 }
9138
9139 /* Returns the clock of the currently programmed mode of the given pipe. */
9140 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9141                                 struct intel_crtc_state *pipe_config)
9142 {
9143         struct drm_device *dev = crtc->base.dev;
9144         struct drm_i915_private *dev_priv = dev->dev_private;
9145         int pipe = pipe_config->cpu_transcoder;
9146         u32 dpll = pipe_config->dpll_hw_state.dpll;
9147         u32 fp;
9148         intel_clock_t clock;
9149         int refclk = i9xx_pll_refclk(dev, pipe_config);
9150
9151         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9152                 fp = pipe_config->dpll_hw_state.fp0;
9153         else
9154                 fp = pipe_config->dpll_hw_state.fp1;
9155
9156         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9157         if (IS_PINEVIEW(dev)) {
9158                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9159                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9160         } else {
9161                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9162                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9163         }
9164
9165         if (!IS_GEN2(dev)) {
9166                 if (IS_PINEVIEW(dev))
9167                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9168                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9169                 else
9170                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9171                                DPLL_FPA01_P1_POST_DIV_SHIFT);
9172
9173                 switch (dpll & DPLL_MODE_MASK) {
9174                 case DPLLB_MODE_DAC_SERIAL:
9175                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9176                                 5 : 10;
9177                         break;
9178                 case DPLLB_MODE_LVDS:
9179                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9180                                 7 : 14;
9181                         break;
9182                 default:
9183                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9184                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9185                         return;
9186                 }
9187
9188                 if (IS_PINEVIEW(dev))
9189                         pineview_clock(refclk, &clock);
9190                 else
9191                         i9xx_clock(refclk, &clock);
9192         } else {
9193                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9194                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9195
9196                 if (is_lvds) {
9197                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9198                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9199
9200                         if (lvds & LVDS_CLKB_POWER_UP)
9201                                 clock.p2 = 7;
9202                         else
9203                                 clock.p2 = 14;
9204                 } else {
9205                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9206                                 clock.p1 = 2;
9207                         else {
9208                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9209                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9210                         }
9211                         if (dpll & PLL_P2_DIVIDE_BY_4)
9212                                 clock.p2 = 4;
9213                         else
9214                                 clock.p2 = 2;
9215                 }
9216
9217                 i9xx_clock(refclk, &clock);
9218         }
9219
9220         /*
9221          * This value includes pixel_multiplier. We will use
9222          * port_clock to compute adjusted_mode.crtc_clock in the
9223          * encoder's get_config() function.
9224          */
9225         pipe_config->port_clock = clock.dot;
9226 }
9227
9228 int intel_dotclock_calculate(int link_freq,
9229                              const struct intel_link_m_n *m_n)
9230 {
9231         /*
9232          * The calculation for the data clock is:
9233          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9234          * But we want to avoid losing precison if possible, so:
9235          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9236          *
9237          * and the link clock is simpler:
9238          * link_clock = (m * link_clock) / n
9239          */
9240
9241         if (!m_n->link_n)
9242                 return 0;
9243
9244         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9245 }
9246
9247 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9248                                    struct intel_crtc_state *pipe_config)
9249 {
9250         struct drm_device *dev = crtc->base.dev;
9251
9252         /* read out port_clock from the DPLL */
9253         i9xx_crtc_clock_get(crtc, pipe_config);
9254
9255         /*
9256          * This value does not include pixel_multiplier.
9257          * We will check that port_clock and adjusted_mode.crtc_clock
9258          * agree once we know their relationship in the encoder's
9259          * get_config() function.
9260          */
9261         pipe_config->base.adjusted_mode.crtc_clock =
9262                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9263                                          &pipe_config->fdi_m_n);
9264 }
9265
9266 /** Returns the currently programmed mode of the given pipe. */
9267 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9268                                              struct drm_crtc *crtc)
9269 {
9270         struct drm_i915_private *dev_priv = dev->dev_private;
9271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9272         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9273         struct drm_display_mode *mode;
9274         struct intel_crtc_state pipe_config;
9275         int htot = I915_READ(HTOTAL(cpu_transcoder));
9276         int hsync = I915_READ(HSYNC(cpu_transcoder));
9277         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9278         int vsync = I915_READ(VSYNC(cpu_transcoder));
9279         enum pipe pipe = intel_crtc->pipe;
9280
9281         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9282         if (!mode)
9283                 return NULL;
9284
9285         /*
9286          * Construct a pipe_config sufficient for getting the clock info
9287          * back out of crtc_clock_get.
9288          *
9289          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9290          * to use a real value here instead.
9291          */
9292         pipe_config.cpu_transcoder = (enum transcoder) pipe;
9293         pipe_config.pixel_multiplier = 1;
9294         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9295         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9296         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9297         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9298
9299         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9300         mode->hdisplay = (htot & 0xffff) + 1;
9301         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9302         mode->hsync_start = (hsync & 0xffff) + 1;
9303         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9304         mode->vdisplay = (vtot & 0xffff) + 1;
9305         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9306         mode->vsync_start = (vsync & 0xffff) + 1;
9307         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9308
9309         drm_mode_set_name(mode);
9310
9311         return mode;
9312 }
9313
9314 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9315 {
9316         struct drm_device *dev = crtc->dev;
9317         struct drm_i915_private *dev_priv = dev->dev_private;
9318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9319
9320         if (!HAS_GMCH_DISPLAY(dev))
9321                 return;
9322
9323         if (!dev_priv->lvds_downclock_avail)
9324                 return;
9325
9326         /*
9327          * Since this is called by a timer, we should never get here in
9328          * the manual case.
9329          */
9330         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9331                 int pipe = intel_crtc->pipe;
9332                 int dpll_reg = DPLL(pipe);
9333                 int dpll;
9334
9335                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9336
9337                 assert_panel_unlocked(dev_priv, pipe);
9338
9339                 dpll = I915_READ(dpll_reg);
9340                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9341                 I915_WRITE(dpll_reg, dpll);
9342                 intel_wait_for_vblank(dev, pipe);
9343                 dpll = I915_READ(dpll_reg);
9344                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9345                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9346         }
9347
9348 }
9349
9350 void intel_mark_busy(struct drm_device *dev)
9351 {
9352         struct drm_i915_private *dev_priv = dev->dev_private;
9353
9354         if (dev_priv->mm.busy)
9355                 return;
9356
9357         intel_runtime_pm_get(dev_priv);
9358         i915_update_gfx_val(dev_priv);
9359         if (INTEL_INFO(dev)->gen >= 6)
9360                 gen6_rps_busy(dev_priv);
9361         dev_priv->mm.busy = true;
9362 }
9363
9364 void intel_mark_idle(struct drm_device *dev)
9365 {
9366         struct drm_i915_private *dev_priv = dev->dev_private;
9367         struct drm_crtc *crtc;
9368
9369         if (!dev_priv->mm.busy)
9370                 return;
9371
9372         dev_priv->mm.busy = false;
9373
9374         for_each_crtc(dev, crtc) {
9375                 if (!crtc->primary->fb)
9376                         continue;
9377
9378                 intel_decrease_pllclock(crtc);
9379         }
9380
9381         if (INTEL_INFO(dev)->gen >= 6)
9382                 gen6_rps_idle(dev->dev_private);
9383
9384         intel_runtime_pm_put(dev_priv);
9385 }
9386
9387 static void intel_crtc_set_state(struct intel_crtc *crtc,
9388                                  struct intel_crtc_state *crtc_state)
9389 {
9390         kfree(crtc->config);
9391         crtc->config = crtc_state;
9392         crtc->base.state = &crtc_state->base;
9393 }
9394
9395 static void intel_crtc_destroy(struct drm_crtc *crtc)
9396 {
9397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9398         struct drm_device *dev = crtc->dev;
9399         struct intel_unpin_work *work;
9400
9401         spin_lock_irq(&dev->event_lock);
9402         work = intel_crtc->unpin_work;
9403         intel_crtc->unpin_work = NULL;
9404         spin_unlock_irq(&dev->event_lock);
9405
9406         if (work) {
9407                 cancel_work_sync(&work->work);
9408                 kfree(work);
9409         }
9410
9411         intel_crtc_set_state(intel_crtc, NULL);
9412         drm_crtc_cleanup(crtc);
9413
9414         kfree(intel_crtc);
9415 }
9416
9417 static void intel_unpin_work_fn(struct work_struct *__work)
9418 {
9419         struct intel_unpin_work *work =
9420                 container_of(__work, struct intel_unpin_work, work);
9421         struct drm_device *dev = work->crtc->dev;
9422         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9423
9424         mutex_lock(&dev->struct_mutex);
9425         intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
9426         drm_gem_object_unreference(&work->pending_flip_obj->base);
9427
9428         intel_fbc_update(dev);
9429
9430         if (work->flip_queued_req)
9431                 i915_gem_request_assign(&work->flip_queued_req, NULL);
9432         mutex_unlock(&dev->struct_mutex);
9433
9434         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9435         drm_framebuffer_unreference(work->old_fb);
9436
9437         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9438         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9439
9440         kfree(work);
9441 }
9442
9443 static void do_intel_finish_page_flip(struct drm_device *dev,
9444                                       struct drm_crtc *crtc)
9445 {
9446         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9447         struct intel_unpin_work *work;
9448         unsigned long flags;
9449
9450         /* Ignore early vblank irqs */
9451         if (intel_crtc == NULL)
9452                 return;
9453
9454         /*
9455          * This is called both by irq handlers and the reset code (to complete
9456          * lost pageflips) so needs the full irqsave spinlocks.
9457          */
9458         spin_lock_irqsave(&dev->event_lock, flags);
9459         work = intel_crtc->unpin_work;
9460
9461         /* Ensure we don't miss a work->pending update ... */
9462         smp_rmb();
9463
9464         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9465                 spin_unlock_irqrestore(&dev->event_lock, flags);
9466                 return;
9467         }
9468
9469         page_flip_completed(intel_crtc);
9470
9471         spin_unlock_irqrestore(&dev->event_lock, flags);
9472 }
9473
9474 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9475 {
9476         struct drm_i915_private *dev_priv = dev->dev_private;
9477         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9478
9479         do_intel_finish_page_flip(dev, crtc);
9480 }
9481
9482 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9483 {
9484         struct drm_i915_private *dev_priv = dev->dev_private;
9485         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9486
9487         do_intel_finish_page_flip(dev, crtc);
9488 }
9489
9490 /* Is 'a' after or equal to 'b'? */
9491 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9492 {
9493         return !((a - b) & 0x80000000);
9494 }
9495
9496 static bool page_flip_finished(struct intel_crtc *crtc)
9497 {
9498         struct drm_device *dev = crtc->base.dev;
9499         struct drm_i915_private *dev_priv = dev->dev_private;
9500
9501         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9502             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9503                 return true;
9504
9505         /*
9506          * The relevant registers doen't exist on pre-ctg.
9507          * As the flip done interrupt doesn't trigger for mmio
9508          * flips on gmch platforms, a flip count check isn't
9509          * really needed there. But since ctg has the registers,
9510          * include it in the check anyway.
9511          */
9512         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9513                 return true;
9514
9515         /*
9516          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9517          * used the same base address. In that case the mmio flip might
9518          * have completed, but the CS hasn't even executed the flip yet.
9519          *
9520          * A flip count check isn't enough as the CS might have updated
9521          * the base address just after start of vblank, but before we
9522          * managed to process the interrupt. This means we'd complete the
9523          * CS flip too soon.
9524          *
9525          * Combining both checks should get us a good enough result. It may
9526          * still happen that the CS flip has been executed, but has not
9527          * yet actually completed. But in case the base address is the same
9528          * anyway, we don't really care.
9529          */
9530         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9531                 crtc->unpin_work->gtt_offset &&
9532                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9533                                     crtc->unpin_work->flip_count);
9534 }
9535
9536 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9537 {
9538         struct drm_i915_private *dev_priv = dev->dev_private;
9539         struct intel_crtc *intel_crtc =
9540                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9541         unsigned long flags;
9542
9543
9544         /*
9545          * This is called both by irq handlers and the reset code (to complete
9546          * lost pageflips) so needs the full irqsave spinlocks.
9547          *
9548          * NB: An MMIO update of the plane base pointer will also
9549          * generate a page-flip completion irq, i.e. every modeset
9550          * is also accompanied by a spurious intel_prepare_page_flip().
9551          */
9552         spin_lock_irqsave(&dev->event_lock, flags);
9553         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9554                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9555         spin_unlock_irqrestore(&dev->event_lock, flags);
9556 }
9557
9558 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9559 {
9560         /* Ensure that the work item is consistent when activating it ... */
9561         smp_wmb();
9562         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9563         /* and that it is marked active as soon as the irq could fire. */
9564         smp_wmb();
9565 }
9566
9567 static int intel_gen2_queue_flip(struct drm_device *dev,
9568                                  struct drm_crtc *crtc,
9569                                  struct drm_framebuffer *fb,
9570                                  struct drm_i915_gem_object *obj,
9571                                  struct intel_engine_cs *ring,
9572                                  uint32_t flags)
9573 {
9574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9575         u32 flip_mask;
9576         int ret;
9577
9578         ret = intel_ring_begin(ring, 6);
9579         if (ret)
9580                 return ret;
9581
9582         /* Can't queue multiple flips, so wait for the previous
9583          * one to finish before executing the next.
9584          */
9585         if (intel_crtc->plane)
9586                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9587         else
9588                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9589         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9590         intel_ring_emit(ring, MI_NOOP);
9591         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9592                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9593         intel_ring_emit(ring, fb->pitches[0]);
9594         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9595         intel_ring_emit(ring, 0); /* aux display base address, unused */
9596
9597         intel_mark_page_flip_active(intel_crtc);
9598         __intel_ring_advance(ring);
9599         return 0;
9600 }
9601
9602 static int intel_gen3_queue_flip(struct drm_device *dev,
9603                                  struct drm_crtc *crtc,
9604                                  struct drm_framebuffer *fb,
9605                                  struct drm_i915_gem_object *obj,
9606                                  struct intel_engine_cs *ring,
9607                                  uint32_t flags)
9608 {
9609         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9610         u32 flip_mask;
9611         int ret;
9612
9613         ret = intel_ring_begin(ring, 6);
9614         if (ret)
9615                 return ret;
9616
9617         if (intel_crtc->plane)
9618                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9619         else
9620                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9621         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9622         intel_ring_emit(ring, MI_NOOP);
9623         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9624                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9625         intel_ring_emit(ring, fb->pitches[0]);
9626         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9627         intel_ring_emit(ring, MI_NOOP);
9628
9629         intel_mark_page_flip_active(intel_crtc);
9630         __intel_ring_advance(ring);
9631         return 0;
9632 }
9633
9634 static int intel_gen4_queue_flip(struct drm_device *dev,
9635                                  struct drm_crtc *crtc,
9636                                  struct drm_framebuffer *fb,
9637                                  struct drm_i915_gem_object *obj,
9638                                  struct intel_engine_cs *ring,
9639                                  uint32_t flags)
9640 {
9641         struct drm_i915_private *dev_priv = dev->dev_private;
9642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9643         uint32_t pf, pipesrc;
9644         int ret;
9645
9646         ret = intel_ring_begin(ring, 4);
9647         if (ret)
9648                 return ret;
9649
9650         /* i965+ uses the linear or tiled offsets from the
9651          * Display Registers (which do not change across a page-flip)
9652          * so we need only reprogram the base address.
9653          */
9654         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9655                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9656         intel_ring_emit(ring, fb->pitches[0]);
9657         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9658                         obj->tiling_mode);
9659
9660         /* XXX Enabling the panel-fitter across page-flip is so far
9661          * untested on non-native modes, so ignore it for now.
9662          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9663          */
9664         pf = 0;
9665         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9666         intel_ring_emit(ring, pf | pipesrc);
9667
9668         intel_mark_page_flip_active(intel_crtc);
9669         __intel_ring_advance(ring);
9670         return 0;
9671 }
9672
9673 static int intel_gen6_queue_flip(struct drm_device *dev,
9674                                  struct drm_crtc *crtc,
9675                                  struct drm_framebuffer *fb,
9676                                  struct drm_i915_gem_object *obj,
9677                                  struct intel_engine_cs *ring,
9678                                  uint32_t flags)
9679 {
9680         struct drm_i915_private *dev_priv = dev->dev_private;
9681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9682         uint32_t pf, pipesrc;
9683         int ret;
9684
9685         ret = intel_ring_begin(ring, 4);
9686         if (ret)
9687                 return ret;
9688
9689         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9690                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9691         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9692         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9693
9694         /* Contrary to the suggestions in the documentation,
9695          * "Enable Panel Fitter" does not seem to be required when page
9696          * flipping with a non-native mode, and worse causes a normal
9697          * modeset to fail.
9698          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9699          */
9700         pf = 0;
9701         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9702         intel_ring_emit(ring, pf | pipesrc);
9703
9704         intel_mark_page_flip_active(intel_crtc);
9705         __intel_ring_advance(ring);
9706         return 0;
9707 }
9708
9709 static int intel_gen7_queue_flip(struct drm_device *dev,
9710                                  struct drm_crtc *crtc,
9711                                  struct drm_framebuffer *fb,
9712                                  struct drm_i915_gem_object *obj,
9713                                  struct intel_engine_cs *ring,
9714                                  uint32_t flags)
9715 {
9716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9717         uint32_t plane_bit = 0;
9718         int len, ret;
9719
9720         switch (intel_crtc->plane) {
9721         case PLANE_A:
9722                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9723                 break;
9724         case PLANE_B:
9725                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9726                 break;
9727         case PLANE_C:
9728                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9729                 break;
9730         default:
9731                 WARN_ONCE(1, "unknown plane in flip command\n");
9732                 return -ENODEV;
9733         }
9734
9735         len = 4;
9736         if (ring->id == RCS) {
9737                 len += 6;
9738                 /*
9739                  * On Gen 8, SRM is now taking an extra dword to accommodate
9740                  * 48bits addresses, and we need a NOOP for the batch size to
9741                  * stay even.
9742                  */
9743                 if (IS_GEN8(dev))
9744                         len += 2;
9745         }
9746
9747         /*
9748          * BSpec MI_DISPLAY_FLIP for IVB:
9749          * "The full packet must be contained within the same cache line."
9750          *
9751          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9752          * cacheline, if we ever start emitting more commands before
9753          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9754          * then do the cacheline alignment, and finally emit the
9755          * MI_DISPLAY_FLIP.
9756          */
9757         ret = intel_ring_cacheline_align(ring);
9758         if (ret)
9759                 return ret;
9760
9761         ret = intel_ring_begin(ring, len);
9762         if (ret)
9763                 return ret;
9764
9765         /* Unmask the flip-done completion message. Note that the bspec says that
9766          * we should do this for both the BCS and RCS, and that we must not unmask
9767          * more than one flip event at any time (or ensure that one flip message
9768          * can be sent by waiting for flip-done prior to queueing new flips).
9769          * Experimentation says that BCS works despite DERRMR masking all
9770          * flip-done completion events and that unmasking all planes at once
9771          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9772          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9773          */
9774         if (ring->id == RCS) {
9775                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9776                 intel_ring_emit(ring, DERRMR);
9777                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9778                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9779                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9780                 if (IS_GEN8(dev))
9781                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9782                                               MI_SRM_LRM_GLOBAL_GTT);
9783                 else
9784                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9785                                               MI_SRM_LRM_GLOBAL_GTT);
9786                 intel_ring_emit(ring, DERRMR);
9787                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9788                 if (IS_GEN8(dev)) {
9789                         intel_ring_emit(ring, 0);
9790                         intel_ring_emit(ring, MI_NOOP);
9791                 }
9792         }
9793
9794         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9795         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9796         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9797         intel_ring_emit(ring, (MI_NOOP));
9798
9799         intel_mark_page_flip_active(intel_crtc);
9800         __intel_ring_advance(ring);
9801         return 0;
9802 }
9803
9804 static bool use_mmio_flip(struct intel_engine_cs *ring,
9805                           struct drm_i915_gem_object *obj)
9806 {
9807         /*
9808          * This is not being used for older platforms, because
9809          * non-availability of flip done interrupt forces us to use
9810          * CS flips. Older platforms derive flip done using some clever
9811          * tricks involving the flip_pending status bits and vblank irqs.
9812          * So using MMIO flips there would disrupt this mechanism.
9813          */
9814
9815         if (ring == NULL)
9816                 return true;
9817
9818         if (INTEL_INFO(ring->dev)->gen < 5)
9819                 return false;
9820
9821         if (i915.use_mmio_flip < 0)
9822                 return false;
9823         else if (i915.use_mmio_flip > 0)
9824                 return true;
9825         else if (i915.enable_execlists)
9826                 return true;
9827         else
9828                 return ring != i915_gem_request_get_ring(obj->last_read_req);
9829 }
9830
9831 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9832 {
9833         struct drm_device *dev = intel_crtc->base.dev;
9834         struct drm_i915_private *dev_priv = dev->dev_private;
9835         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9836         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9837         struct drm_i915_gem_object *obj = intel_fb->obj;
9838         const enum pipe pipe = intel_crtc->pipe;
9839         u32 ctl, stride;
9840
9841         ctl = I915_READ(PLANE_CTL(pipe, 0));
9842         ctl &= ~PLANE_CTL_TILED_MASK;
9843         if (obj->tiling_mode == I915_TILING_X)
9844                 ctl |= PLANE_CTL_TILED_X;
9845
9846         /*
9847          * The stride is either expressed as a multiple of 64 bytes chunks for
9848          * linear buffers or in number of tiles for tiled buffers.
9849          */
9850         stride = fb->pitches[0] >> 6;
9851         if (obj->tiling_mode == I915_TILING_X)
9852                 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9853
9854         /*
9855          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9856          * PLANE_SURF updates, the update is then guaranteed to be atomic.
9857          */
9858         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9859         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9860
9861         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9862         POSTING_READ(PLANE_SURF(pipe, 0));
9863 }
9864
9865 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9866 {
9867         struct drm_device *dev = intel_crtc->base.dev;
9868         struct drm_i915_private *dev_priv = dev->dev_private;
9869         struct intel_framebuffer *intel_fb =
9870                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9871         struct drm_i915_gem_object *obj = intel_fb->obj;
9872         u32 dspcntr;
9873         u32 reg;
9874
9875         reg = DSPCNTR(intel_crtc->plane);
9876         dspcntr = I915_READ(reg);
9877
9878         if (obj->tiling_mode != I915_TILING_NONE)
9879                 dspcntr |= DISPPLANE_TILED;
9880         else
9881                 dspcntr &= ~DISPPLANE_TILED;
9882
9883         I915_WRITE(reg, dspcntr);
9884
9885         I915_WRITE(DSPSURF(intel_crtc->plane),
9886                    intel_crtc->unpin_work->gtt_offset);
9887         POSTING_READ(DSPSURF(intel_crtc->plane));
9888
9889 }
9890
9891 /*
9892  * XXX: This is the temporary way to update the plane registers until we get
9893  * around to using the usual plane update functions for MMIO flips
9894  */
9895 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9896 {
9897         struct drm_device *dev = intel_crtc->base.dev;
9898         bool atomic_update;
9899         u32 start_vbl_count;
9900
9901         intel_mark_page_flip_active(intel_crtc);
9902
9903         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9904
9905         if (INTEL_INFO(dev)->gen >= 9)
9906                 skl_do_mmio_flip(intel_crtc);
9907         else
9908                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9909                 ilk_do_mmio_flip(intel_crtc);
9910
9911         if (atomic_update)
9912                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9913 }
9914
9915 static void intel_mmio_flip_work_func(struct work_struct *work)
9916 {
9917         struct intel_crtc *crtc =
9918                 container_of(work, struct intel_crtc, mmio_flip.work);
9919         struct intel_mmio_flip *mmio_flip;
9920
9921         mmio_flip = &crtc->mmio_flip;
9922         if (mmio_flip->req)
9923                 WARN_ON(__i915_wait_request(mmio_flip->req,
9924                                             crtc->reset_counter,
9925                                             false, NULL, NULL) != 0);
9926
9927         intel_do_mmio_flip(crtc);
9928         if (mmio_flip->req) {
9929                 mutex_lock(&crtc->base.dev->struct_mutex);
9930                 i915_gem_request_assign(&mmio_flip->req, NULL);
9931                 mutex_unlock(&crtc->base.dev->struct_mutex);
9932         }
9933 }
9934
9935 static int intel_queue_mmio_flip(struct drm_device *dev,
9936                                  struct drm_crtc *crtc,
9937                                  struct drm_framebuffer *fb,
9938                                  struct drm_i915_gem_object *obj,
9939                                  struct intel_engine_cs *ring,
9940                                  uint32_t flags)
9941 {
9942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9943
9944         i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9945                                 obj->last_write_req);
9946
9947         schedule_work(&intel_crtc->mmio_flip.work);
9948
9949         return 0;
9950 }
9951
9952 static int intel_default_queue_flip(struct drm_device *dev,
9953                                     struct drm_crtc *crtc,
9954                                     struct drm_framebuffer *fb,
9955                                     struct drm_i915_gem_object *obj,
9956                                     struct intel_engine_cs *ring,
9957                                     uint32_t flags)
9958 {
9959         return -ENODEV;
9960 }
9961
9962 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9963                                          struct drm_crtc *crtc)
9964 {
9965         struct drm_i915_private *dev_priv = dev->dev_private;
9966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9967         struct intel_unpin_work *work = intel_crtc->unpin_work;
9968         u32 addr;
9969
9970         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9971                 return true;
9972
9973         if (!work->enable_stall_check)
9974                 return false;
9975
9976         if (work->flip_ready_vblank == 0) {
9977                 if (work->flip_queued_req &&
9978                     !i915_gem_request_completed(work->flip_queued_req, true))
9979                         return false;
9980
9981                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9982         }
9983
9984         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9985                 return false;
9986
9987         /* Potential stall - if we see that the flip has happened,
9988          * assume a missed interrupt. */
9989         if (INTEL_INFO(dev)->gen >= 4)
9990                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9991         else
9992                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9993
9994         /* There is a potential issue here with a false positive after a flip
9995          * to the same address. We could address this by checking for a
9996          * non-incrementing frame counter.
9997          */
9998         return addr == work->gtt_offset;
9999 }
10000
10001 void intel_check_page_flip(struct drm_device *dev, int pipe)
10002 {
10003         struct drm_i915_private *dev_priv = dev->dev_private;
10004         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10006
10007         WARN_ON(!in_interrupt());
10008
10009         if (crtc == NULL)
10010                 return;
10011
10012         spin_lock(&dev->event_lock);
10013         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
10014                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10015                          intel_crtc->unpin_work->flip_queued_vblank,
10016                          drm_vblank_count(dev, pipe));
10017                 page_flip_completed(intel_crtc);
10018         }
10019         spin_unlock(&dev->event_lock);
10020 }
10021
10022 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10023                                 struct drm_framebuffer *fb,
10024                                 struct drm_pending_vblank_event *event,
10025                                 uint32_t page_flip_flags)
10026 {
10027         struct drm_device *dev = crtc->dev;
10028         struct drm_i915_private *dev_priv = dev->dev_private;
10029         struct drm_framebuffer *old_fb = crtc->primary->fb;
10030         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10032         struct drm_plane *primary = crtc->primary;
10033         enum pipe pipe = intel_crtc->pipe;
10034         struct intel_unpin_work *work;
10035         struct intel_engine_cs *ring;
10036         int ret;
10037
10038         /*
10039          * drm_mode_page_flip_ioctl() should already catch this, but double
10040          * check to be safe.  In the future we may enable pageflipping from
10041          * a disabled primary plane.
10042          */
10043         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10044                 return -EBUSY;
10045
10046         /* Can't change pixel format via MI display flips. */
10047         if (fb->pixel_format != crtc->primary->fb->pixel_format)
10048                 return -EINVAL;
10049
10050         /*
10051          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10052          * Note that pitch changes could also affect these register.
10053          */
10054         if (INTEL_INFO(dev)->gen > 3 &&
10055             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10056              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10057                 return -EINVAL;
10058
10059         if (i915_terminally_wedged(&dev_priv->gpu_error))
10060                 goto out_hang;
10061
10062         work = kzalloc(sizeof(*work), GFP_KERNEL);
10063         if (work == NULL)
10064                 return -ENOMEM;
10065
10066         work->event = event;
10067         work->crtc = crtc;
10068         work->old_fb = old_fb;
10069         INIT_WORK(&work->work, intel_unpin_work_fn);
10070
10071         ret = drm_crtc_vblank_get(crtc);
10072         if (ret)
10073                 goto free_work;
10074
10075         /* We borrow the event spin lock for protecting unpin_work */
10076         spin_lock_irq(&dev->event_lock);
10077         if (intel_crtc->unpin_work) {
10078                 /* Before declaring the flip queue wedged, check if
10079                  * the hardware completed the operation behind our backs.
10080                  */
10081                 if (__intel_pageflip_stall_check(dev, crtc)) {
10082                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10083                         page_flip_completed(intel_crtc);
10084                 } else {
10085                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10086                         spin_unlock_irq(&dev->event_lock);
10087
10088                         drm_crtc_vblank_put(crtc);
10089                         kfree(work);
10090                         return -EBUSY;
10091                 }
10092         }
10093         intel_crtc->unpin_work = work;
10094         spin_unlock_irq(&dev->event_lock);
10095
10096         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10097                 flush_workqueue(dev_priv->wq);
10098
10099         /* Reference the objects for the scheduled work. */
10100         drm_framebuffer_reference(work->old_fb);
10101         drm_gem_object_reference(&obj->base);
10102
10103         crtc->primary->fb = fb;
10104         update_state_fb(crtc->primary);
10105
10106         work->pending_flip_obj = obj;
10107
10108         ret = i915_mutex_lock_interruptible(dev);
10109         if (ret)
10110                 goto cleanup;
10111
10112         atomic_inc(&intel_crtc->unpin_work_count);
10113         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10114
10115         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10116                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10117
10118         if (IS_VALLEYVIEW(dev)) {
10119                 ring = &dev_priv->ring[BCS];
10120                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10121                         /* vlv: DISPLAY_FLIP fails to change tiling */
10122                         ring = NULL;
10123         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10124                 ring = &dev_priv->ring[BCS];
10125         } else if (INTEL_INFO(dev)->gen >= 7) {
10126                 ring = i915_gem_request_get_ring(obj->last_read_req);
10127                 if (ring == NULL || ring->id != RCS)
10128                         ring = &dev_priv->ring[BCS];
10129         } else {
10130                 ring = &dev_priv->ring[RCS];
10131         }
10132
10133         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10134                                          crtc->primary->state, ring);
10135         if (ret)
10136                 goto cleanup_pending;
10137
10138         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10139                                                   + intel_crtc->dspaddr_offset;
10140
10141         if (use_mmio_flip(ring, obj)) {
10142                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10143                                             page_flip_flags);
10144                 if (ret)
10145                         goto cleanup_unpin;
10146
10147                 i915_gem_request_assign(&work->flip_queued_req,
10148                                         obj->last_write_req);
10149         } else {
10150                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10151                                                    page_flip_flags);
10152                 if (ret)
10153                         goto cleanup_unpin;
10154
10155                 i915_gem_request_assign(&work->flip_queued_req,
10156                                         intel_ring_get_request(ring));
10157         }
10158
10159         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10160         work->enable_stall_check = true;
10161
10162         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10163                           INTEL_FRONTBUFFER_PRIMARY(pipe));
10164
10165         intel_fbc_disable(dev);
10166         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10167         mutex_unlock(&dev->struct_mutex);
10168
10169         trace_i915_flip_request(intel_crtc->plane, obj);
10170
10171         return 0;
10172
10173 cleanup_unpin:
10174         intel_unpin_fb_obj(fb, crtc->primary->state);
10175 cleanup_pending:
10176         atomic_dec(&intel_crtc->unpin_work_count);
10177         mutex_unlock(&dev->struct_mutex);
10178 cleanup:
10179         crtc->primary->fb = old_fb;
10180         update_state_fb(crtc->primary);
10181
10182         drm_gem_object_unreference_unlocked(&obj->base);
10183         drm_framebuffer_unreference(work->old_fb);
10184
10185         spin_lock_irq(&dev->event_lock);
10186         intel_crtc->unpin_work = NULL;
10187         spin_unlock_irq(&dev->event_lock);
10188
10189         drm_crtc_vblank_put(crtc);
10190 free_work:
10191         kfree(work);
10192
10193         if (ret == -EIO) {
10194 out_hang:
10195                 ret = intel_plane_restore(primary);
10196                 if (ret == 0 && event) {
10197                         spin_lock_irq(&dev->event_lock);
10198                         drm_send_vblank_event(dev, pipe, event);
10199                         spin_unlock_irq(&dev->event_lock);
10200                 }
10201         }
10202         return ret;
10203 }
10204
10205 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10206         .mode_set_base_atomic = intel_pipe_set_base_atomic,
10207         .load_lut = intel_crtc_load_lut,
10208         .atomic_begin = intel_begin_crtc_commit,
10209         .atomic_flush = intel_finish_crtc_commit,
10210 };
10211
10212 /**
10213  * intel_modeset_update_staged_output_state
10214  *
10215  * Updates the staged output configuration state, e.g. after we've read out the
10216  * current hw state.
10217  */
10218 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10219 {
10220         struct intel_crtc *crtc;
10221         struct intel_encoder *encoder;
10222         struct intel_connector *connector;
10223
10224         for_each_intel_connector(dev, connector) {
10225                 connector->new_encoder =
10226                         to_intel_encoder(connector->base.encoder);
10227         }
10228
10229         for_each_intel_encoder(dev, encoder) {
10230                 encoder->new_crtc =
10231                         to_intel_crtc(encoder->base.crtc);
10232         }
10233
10234         for_each_intel_crtc(dev, crtc) {
10235                 crtc->new_enabled = crtc->base.state->enable;
10236
10237                 if (crtc->new_enabled)
10238                         crtc->new_config = crtc->config;
10239                 else
10240                         crtc->new_config = NULL;
10241         }
10242 }
10243
10244 /* Transitional helper to copy current connector/encoder state to
10245  * connector->state. This is needed so that code that is partially
10246  * converted to atomic does the right thing.
10247  */
10248 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10249 {
10250         struct intel_connector *connector;
10251
10252         for_each_intel_connector(dev, connector) {
10253                 if (connector->base.encoder) {
10254                         connector->base.state->best_encoder =
10255                                 connector->base.encoder;
10256                         connector->base.state->crtc =
10257                                 connector->base.encoder->crtc;
10258                 } else {
10259                         connector->base.state->best_encoder = NULL;
10260                         connector->base.state->crtc = NULL;
10261                 }
10262         }
10263 }
10264
10265 /**
10266  * intel_modeset_commit_output_state
10267  *
10268  * This function copies the stage display pipe configuration to the real one.
10269  */
10270 static void intel_modeset_commit_output_state(struct drm_device *dev)
10271 {
10272         struct intel_crtc *crtc;
10273         struct intel_encoder *encoder;
10274         struct intel_connector *connector;
10275
10276         for_each_intel_connector(dev, connector) {
10277                 connector->base.encoder = &connector->new_encoder->base;
10278         }
10279
10280         for_each_intel_encoder(dev, encoder) {
10281                 encoder->base.crtc = &encoder->new_crtc->base;
10282         }
10283
10284         for_each_intel_crtc(dev, crtc) {
10285                 crtc->base.state->enable = crtc->new_enabled;
10286                 crtc->base.enabled = crtc->new_enabled;
10287         }
10288
10289         intel_modeset_update_connector_atomic_state(dev);
10290 }
10291
10292 static void
10293 connected_sink_compute_bpp(struct intel_connector *connector,
10294                            struct intel_crtc_state *pipe_config)
10295 {
10296         int bpp = pipe_config->pipe_bpp;
10297
10298         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10299                 connector->base.base.id,
10300                 connector->base.name);
10301
10302         /* Don't use an invalid EDID bpc value */
10303         if (connector->base.display_info.bpc &&
10304             connector->base.display_info.bpc * 3 < bpp) {
10305                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10306                               bpp, connector->base.display_info.bpc*3);
10307                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10308         }
10309
10310         /* Clamp bpp to 8 on screens without EDID 1.4 */
10311         if (connector->base.display_info.bpc == 0 && bpp > 24) {
10312                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10313                               bpp);
10314                 pipe_config->pipe_bpp = 24;
10315         }
10316 }
10317
10318 static int
10319 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10320                           struct drm_framebuffer *fb,
10321                           struct intel_crtc_state *pipe_config)
10322 {
10323         struct drm_device *dev = crtc->base.dev;
10324         struct drm_atomic_state *state;
10325         struct intel_connector *connector;
10326         int bpp, i;
10327
10328         switch (fb->pixel_format) {
10329         case DRM_FORMAT_C8:
10330                 bpp = 8*3; /* since we go through a colormap */
10331                 break;
10332         case DRM_FORMAT_XRGB1555:
10333         case DRM_FORMAT_ARGB1555:
10334                 /* checked in intel_framebuffer_init already */
10335                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10336                         return -EINVAL;
10337         case DRM_FORMAT_RGB565:
10338                 bpp = 6*3; /* min is 18bpp */
10339                 break;
10340         case DRM_FORMAT_XBGR8888:
10341         case DRM_FORMAT_ABGR8888:
10342                 /* checked in intel_framebuffer_init already */
10343                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10344                         return -EINVAL;
10345         case DRM_FORMAT_XRGB8888:
10346         case DRM_FORMAT_ARGB8888:
10347                 bpp = 8*3;
10348                 break;
10349         case DRM_FORMAT_XRGB2101010:
10350         case DRM_FORMAT_ARGB2101010:
10351         case DRM_FORMAT_XBGR2101010:
10352         case DRM_FORMAT_ABGR2101010:
10353                 /* checked in intel_framebuffer_init already */
10354                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10355                         return -EINVAL;
10356                 bpp = 10*3;
10357                 break;
10358         /* TODO: gen4+ supports 16 bpc floating point, too. */
10359         default:
10360                 DRM_DEBUG_KMS("unsupported depth\n");
10361                 return -EINVAL;
10362         }
10363
10364         pipe_config->pipe_bpp = bpp;
10365
10366         state = pipe_config->base.state;
10367
10368         /* Clamp display bpp to EDID value */
10369         for (i = 0; i < state->num_connector; i++) {
10370                 if (!state->connectors[i])
10371                         continue;
10372
10373                 connector = to_intel_connector(state->connectors[i]);
10374                 if (state->connector_states[i]->crtc != &crtc->base)
10375                         continue;
10376
10377                 connected_sink_compute_bpp(connector, pipe_config);
10378         }
10379
10380         return bpp;
10381 }
10382
10383 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10384 {
10385         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10386                         "type: 0x%x flags: 0x%x\n",
10387                 mode->crtc_clock,
10388                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10389                 mode->crtc_hsync_end, mode->crtc_htotal,
10390                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10391                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10392 }
10393
10394 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10395                                    struct intel_crtc_state *pipe_config,
10396                                    const char *context)
10397 {
10398         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10399                       context, pipe_name(crtc->pipe));
10400
10401         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10402         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10403                       pipe_config->pipe_bpp, pipe_config->dither);
10404         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10405                       pipe_config->has_pch_encoder,
10406                       pipe_config->fdi_lanes,
10407                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10408                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10409                       pipe_config->fdi_m_n.tu);
10410         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10411                       pipe_config->has_dp_encoder,
10412                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10413                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10414                       pipe_config->dp_m_n.tu);
10415
10416         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10417                       pipe_config->has_dp_encoder,
10418                       pipe_config->dp_m2_n2.gmch_m,
10419                       pipe_config->dp_m2_n2.gmch_n,
10420                       pipe_config->dp_m2_n2.link_m,
10421                       pipe_config->dp_m2_n2.link_n,
10422                       pipe_config->dp_m2_n2.tu);
10423
10424         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10425                       pipe_config->has_audio,
10426                       pipe_config->has_infoframe);
10427
10428         DRM_DEBUG_KMS("requested mode:\n");
10429         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10430         DRM_DEBUG_KMS("adjusted mode:\n");
10431         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10432         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10433         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10434         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10435                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10436         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10437                       pipe_config->gmch_pfit.control,
10438                       pipe_config->gmch_pfit.pgm_ratios,
10439                       pipe_config->gmch_pfit.lvds_border_bits);
10440         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10441                       pipe_config->pch_pfit.pos,
10442                       pipe_config->pch_pfit.size,
10443                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10444         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10445         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10446 }
10447
10448 static bool encoders_cloneable(const struct intel_encoder *a,
10449                                const struct intel_encoder *b)
10450 {
10451         /* masks could be asymmetric, so check both ways */
10452         return a == b || (a->cloneable & (1 << b->type) &&
10453                           b->cloneable & (1 << a->type));
10454 }
10455
10456 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10457                                          struct intel_encoder *encoder)
10458 {
10459         struct drm_device *dev = crtc->base.dev;
10460         struct intel_encoder *source_encoder;
10461
10462         for_each_intel_encoder(dev, source_encoder) {
10463                 if (source_encoder->new_crtc != crtc)
10464                         continue;
10465
10466                 if (!encoders_cloneable(encoder, source_encoder))
10467                         return false;
10468         }
10469
10470         return true;
10471 }
10472
10473 static bool check_encoder_cloning(struct intel_crtc *crtc)
10474 {
10475         struct drm_device *dev = crtc->base.dev;
10476         struct intel_encoder *encoder;
10477
10478         for_each_intel_encoder(dev, encoder) {
10479                 if (encoder->new_crtc != crtc)
10480                         continue;
10481
10482                 if (!check_single_encoder_cloning(crtc, encoder))
10483                         return false;
10484         }
10485
10486         return true;
10487 }
10488
10489 static bool check_digital_port_conflicts(struct drm_device *dev)
10490 {
10491         struct intel_connector *connector;
10492         unsigned int used_ports = 0;
10493
10494         /*
10495          * Walk the connector list instead of the encoder
10496          * list to detect the problem on ddi platforms
10497          * where there's just one encoder per digital port.
10498          */
10499         for_each_intel_connector(dev, connector) {
10500                 struct intel_encoder *encoder = connector->new_encoder;
10501
10502                 if (!encoder)
10503                         continue;
10504
10505                 WARN_ON(!encoder->new_crtc);
10506
10507                 switch (encoder->type) {
10508                         unsigned int port_mask;
10509                 case INTEL_OUTPUT_UNKNOWN:
10510                         if (WARN_ON(!HAS_DDI(dev)))
10511                                 break;
10512                 case INTEL_OUTPUT_DISPLAYPORT:
10513                 case INTEL_OUTPUT_HDMI:
10514                 case INTEL_OUTPUT_EDP:
10515                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10516
10517                         /* the same port mustn't appear more than once */
10518                         if (used_ports & port_mask)
10519                                 return false;
10520
10521                         used_ports |= port_mask;
10522                 default:
10523                         break;
10524                 }
10525         }
10526
10527         return true;
10528 }
10529
10530 static void
10531 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10532 {
10533         struct drm_crtc_state tmp_state;
10534
10535         /* Clear only the intel specific part of the crtc state */
10536         tmp_state = crtc_state->base;
10537         memset(crtc_state, 0, sizeof *crtc_state);
10538         crtc_state->base = tmp_state;
10539 }
10540
10541 static struct intel_crtc_state *
10542 intel_modeset_pipe_config(struct drm_crtc *crtc,
10543                           struct drm_framebuffer *fb,
10544                           struct drm_display_mode *mode,
10545                           struct drm_atomic_state *state)
10546 {
10547         struct drm_device *dev = crtc->dev;
10548         struct intel_encoder *encoder;
10549         struct intel_connector *connector;
10550         struct drm_connector_state *connector_state;
10551         struct intel_crtc_state *pipe_config;
10552         int plane_bpp, ret = -EINVAL;
10553         int i;
10554         bool retry = true;
10555
10556         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10557                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10558                 return ERR_PTR(-EINVAL);
10559         }
10560
10561         if (!check_digital_port_conflicts(dev)) {
10562                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10563                 return ERR_PTR(-EINVAL);
10564         }
10565
10566         pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
10567         if (IS_ERR(pipe_config))
10568                 return pipe_config;
10569
10570         clear_intel_crtc_state(pipe_config);
10571
10572         pipe_config->base.crtc = crtc;
10573         drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10574         drm_mode_copy(&pipe_config->base.mode, mode);
10575
10576         pipe_config->cpu_transcoder =
10577                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10578         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10579
10580         /*
10581          * Sanitize sync polarity flags based on requested ones. If neither
10582          * positive or negative polarity is requested, treat this as meaning
10583          * negative polarity.
10584          */
10585         if (!(pipe_config->base.adjusted_mode.flags &
10586               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10587                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10588
10589         if (!(pipe_config->base.adjusted_mode.flags &
10590               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10591                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10592
10593         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10594          * plane pixel format and any sink constraints into account. Returns the
10595          * source plane bpp so that dithering can be selected on mismatches
10596          * after encoders and crtc also have had their say. */
10597         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10598                                               fb, pipe_config);
10599         if (plane_bpp < 0)
10600                 goto fail;
10601
10602         /*
10603          * Determine the real pipe dimensions. Note that stereo modes can
10604          * increase the actual pipe size due to the frame doubling and
10605          * insertion of additional space for blanks between the frame. This
10606          * is stored in the crtc timings. We use the requested mode to do this
10607          * computation to clearly distinguish it from the adjusted mode, which
10608          * can be changed by the connectors in the below retry loop.
10609          */
10610         drm_crtc_get_hv_timing(&pipe_config->base.mode,
10611                                &pipe_config->pipe_src_w,
10612                                &pipe_config->pipe_src_h);
10613
10614 encoder_retry:
10615         /* Ensure the port clock defaults are reset when retrying. */
10616         pipe_config->port_clock = 0;
10617         pipe_config->pixel_multiplier = 1;
10618
10619         /* Fill in default crtc timings, allow encoders to overwrite them. */
10620         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10621                               CRTC_STEREO_DOUBLE);
10622
10623         /* Pass our mode to the connectors and the CRTC to give them a chance to
10624          * adjust it according to limitations or connector properties, and also
10625          * a chance to reject the mode entirely.
10626          */
10627         for (i = 0; i < state->num_connector; i++) {
10628                 connector = to_intel_connector(state->connectors[i]);
10629                 if (!connector)
10630                         continue;
10631
10632                 connector_state = state->connector_states[i];
10633                 if (connector_state->crtc != crtc)
10634                         continue;
10635
10636                 encoder = to_intel_encoder(connector_state->best_encoder);
10637
10638                 if (!(encoder->compute_config(encoder, pipe_config))) {
10639                         DRM_DEBUG_KMS("Encoder config failure\n");
10640                         goto fail;
10641                 }
10642         }
10643
10644         /* Set default port clock if not overwritten by the encoder. Needs to be
10645          * done afterwards in case the encoder adjusts the mode. */
10646         if (!pipe_config->port_clock)
10647                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10648                         * pipe_config->pixel_multiplier;
10649
10650         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10651         if (ret < 0) {
10652                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10653                 goto fail;
10654         }
10655
10656         if (ret == RETRY) {
10657                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10658                         ret = -EINVAL;
10659                         goto fail;
10660                 }
10661
10662                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10663                 retry = false;
10664                 goto encoder_retry;
10665         }
10666
10667         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10668         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10669                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10670
10671         return pipe_config;
10672 fail:
10673         return ERR_PTR(ret);
10674 }
10675
10676 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10677  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10678 static void
10679 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10680                              unsigned *prepare_pipes, unsigned *disable_pipes)
10681 {
10682         struct intel_crtc *intel_crtc;
10683         struct drm_device *dev = crtc->dev;
10684         struct intel_encoder *encoder;
10685         struct intel_connector *connector;
10686         struct drm_crtc *tmp_crtc;
10687
10688         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10689
10690         /* Check which crtcs have changed outputs connected to them, these need
10691          * to be part of the prepare_pipes mask. We don't (yet) support global
10692          * modeset across multiple crtcs, so modeset_pipes will only have one
10693          * bit set at most. */
10694         for_each_intel_connector(dev, connector) {
10695                 if (connector->base.encoder == &connector->new_encoder->base)
10696                         continue;
10697
10698                 if (connector->base.encoder) {
10699                         tmp_crtc = connector->base.encoder->crtc;
10700
10701                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10702                 }
10703
10704                 if (connector->new_encoder)
10705                         *prepare_pipes |=
10706                                 1 << connector->new_encoder->new_crtc->pipe;
10707         }
10708
10709         for_each_intel_encoder(dev, encoder) {
10710                 if (encoder->base.crtc == &encoder->new_crtc->base)
10711                         continue;
10712
10713                 if (encoder->base.crtc) {
10714                         tmp_crtc = encoder->base.crtc;
10715
10716                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10717                 }
10718
10719                 if (encoder->new_crtc)
10720                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10721         }
10722
10723         /* Check for pipes that will be enabled/disabled ... */
10724         for_each_intel_crtc(dev, intel_crtc) {
10725                 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10726                         continue;
10727
10728                 if (!intel_crtc->new_enabled)
10729                         *disable_pipes |= 1 << intel_crtc->pipe;
10730                 else
10731                         *prepare_pipes |= 1 << intel_crtc->pipe;
10732         }
10733
10734
10735         /* set_mode is also used to update properties on life display pipes. */
10736         intel_crtc = to_intel_crtc(crtc);
10737         if (intel_crtc->new_enabled)
10738                 *prepare_pipes |= 1 << intel_crtc->pipe;
10739
10740         /*
10741          * For simplicity do a full modeset on any pipe where the output routing
10742          * changed. We could be more clever, but that would require us to be
10743          * more careful with calling the relevant encoder->mode_set functions.
10744          */
10745         if (*prepare_pipes)
10746                 *modeset_pipes = *prepare_pipes;
10747
10748         /* ... and mask these out. */
10749         *modeset_pipes &= ~(*disable_pipes);
10750         *prepare_pipes &= ~(*disable_pipes);
10751
10752         /*
10753          * HACK: We don't (yet) fully support global modesets. intel_set_config
10754          * obies this rule, but the modeset restore mode of
10755          * intel_modeset_setup_hw_state does not.
10756          */
10757         *modeset_pipes &= 1 << intel_crtc->pipe;
10758         *prepare_pipes &= 1 << intel_crtc->pipe;
10759
10760         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10761                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10762 }
10763
10764 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10765 {
10766         struct drm_encoder *encoder;
10767         struct drm_device *dev = crtc->dev;
10768
10769         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10770                 if (encoder->crtc == crtc)
10771                         return true;
10772
10773         return false;
10774 }
10775
10776 static void
10777 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10778 {
10779         struct drm_i915_private *dev_priv = dev->dev_private;
10780         struct intel_encoder *intel_encoder;
10781         struct intel_crtc *intel_crtc;
10782         struct drm_connector *connector;
10783
10784         intel_shared_dpll_commit(dev_priv);
10785
10786         for_each_intel_encoder(dev, intel_encoder) {
10787                 if (!intel_encoder->base.crtc)
10788                         continue;
10789
10790                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10791
10792                 if (prepare_pipes & (1 << intel_crtc->pipe))
10793                         intel_encoder->connectors_active = false;
10794         }
10795
10796         intel_modeset_commit_output_state(dev);
10797
10798         /* Double check state. */
10799         for_each_intel_crtc(dev, intel_crtc) {
10800                 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10801                 WARN_ON(intel_crtc->new_config &&
10802                         intel_crtc->new_config != intel_crtc->config);
10803                 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10804         }
10805
10806         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10807                 if (!connector->encoder || !connector->encoder->crtc)
10808                         continue;
10809
10810                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10811
10812                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10813                         struct drm_property *dpms_property =
10814                                 dev->mode_config.dpms_property;
10815
10816                         connector->dpms = DRM_MODE_DPMS_ON;
10817                         drm_object_property_set_value(&connector->base,
10818                                                          dpms_property,
10819                                                          DRM_MODE_DPMS_ON);
10820
10821                         intel_encoder = to_intel_encoder(connector->encoder);
10822                         intel_encoder->connectors_active = true;
10823                 }
10824         }
10825
10826 }
10827
10828 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10829 {
10830         int diff;
10831
10832         if (clock1 == clock2)
10833                 return true;
10834
10835         if (!clock1 || !clock2)
10836                 return false;
10837
10838         diff = abs(clock1 - clock2);
10839
10840         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10841                 return true;
10842
10843         return false;
10844 }
10845
10846 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10847         list_for_each_entry((intel_crtc), \
10848                             &(dev)->mode_config.crtc_list, \
10849                             base.head) \
10850                 if (mask & (1 <<(intel_crtc)->pipe))
10851
10852 static bool
10853 intel_pipe_config_compare(struct drm_device *dev,
10854                           struct intel_crtc_state *current_config,
10855                           struct intel_crtc_state *pipe_config)
10856 {
10857 #define PIPE_CONF_CHECK_X(name) \
10858         if (current_config->name != pipe_config->name) { \
10859                 DRM_ERROR("mismatch in " #name " " \
10860                           "(expected 0x%08x, found 0x%08x)\n", \
10861                           current_config->name, \
10862                           pipe_config->name); \
10863                 return false; \
10864         }
10865
10866 #define PIPE_CONF_CHECK_I(name) \
10867         if (current_config->name != pipe_config->name) { \
10868                 DRM_ERROR("mismatch in " #name " " \
10869                           "(expected %i, found %i)\n", \
10870                           current_config->name, \
10871                           pipe_config->name); \
10872                 return false; \
10873         }
10874
10875 /* This is required for BDW+ where there is only one set of registers for
10876  * switching between high and low RR.
10877  * This macro can be used whenever a comparison has to be made between one
10878  * hw state and multiple sw state variables.
10879  */
10880 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10881         if ((current_config->name != pipe_config->name) && \
10882                 (current_config->alt_name != pipe_config->name)) { \
10883                         DRM_ERROR("mismatch in " #name " " \
10884                                   "(expected %i or %i, found %i)\n", \
10885                                   current_config->name, \
10886                                   current_config->alt_name, \
10887                                   pipe_config->name); \
10888                         return false; \
10889         }
10890
10891 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10892         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10893                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10894                           "(expected %i, found %i)\n", \
10895                           current_config->name & (mask), \
10896                           pipe_config->name & (mask)); \
10897                 return false; \
10898         }
10899
10900 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10901         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10902                 DRM_ERROR("mismatch in " #name " " \
10903                           "(expected %i, found %i)\n", \
10904                           current_config->name, \
10905                           pipe_config->name); \
10906                 return false; \
10907         }
10908
10909 #define PIPE_CONF_QUIRK(quirk)  \
10910         ((current_config->quirks | pipe_config->quirks) & (quirk))
10911
10912         PIPE_CONF_CHECK_I(cpu_transcoder);
10913
10914         PIPE_CONF_CHECK_I(has_pch_encoder);
10915         PIPE_CONF_CHECK_I(fdi_lanes);
10916         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10917         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10918         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10919         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10920         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10921
10922         PIPE_CONF_CHECK_I(has_dp_encoder);
10923
10924         if (INTEL_INFO(dev)->gen < 8) {
10925                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10926                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10927                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10928                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10929                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10930
10931                 if (current_config->has_drrs) {
10932                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10933                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10934                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10935                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10936                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10937                 }
10938         } else {
10939                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10940                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10941                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10942                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10943                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10944         }
10945
10946         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10947         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10948         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10949         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10950         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10951         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10952
10953         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10954         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10955         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10956         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10957         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10958         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10959
10960         PIPE_CONF_CHECK_I(pixel_multiplier);
10961         PIPE_CONF_CHECK_I(has_hdmi_sink);
10962         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10963             IS_VALLEYVIEW(dev))
10964                 PIPE_CONF_CHECK_I(limited_color_range);
10965         PIPE_CONF_CHECK_I(has_infoframe);
10966
10967         PIPE_CONF_CHECK_I(has_audio);
10968
10969         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10970                               DRM_MODE_FLAG_INTERLACE);
10971
10972         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10973                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10974                                       DRM_MODE_FLAG_PHSYNC);
10975                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10976                                       DRM_MODE_FLAG_NHSYNC);
10977                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10978                                       DRM_MODE_FLAG_PVSYNC);
10979                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10980                                       DRM_MODE_FLAG_NVSYNC);
10981         }
10982
10983         PIPE_CONF_CHECK_I(pipe_src_w);
10984         PIPE_CONF_CHECK_I(pipe_src_h);
10985
10986         /*
10987          * FIXME: BIOS likes to set up a cloned config with lvds+external
10988          * screen. Since we don't yet re-compute the pipe config when moving
10989          * just the lvds port away to another pipe the sw tracking won't match.
10990          *
10991          * Proper atomic modesets with recomputed global state will fix this.
10992          * Until then just don't check gmch state for inherited modes.
10993          */
10994         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10995                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10996                 /* pfit ratios are autocomputed by the hw on gen4+ */
10997                 if (INTEL_INFO(dev)->gen < 4)
10998                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10999                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11000         }
11001
11002         PIPE_CONF_CHECK_I(pch_pfit.enabled);
11003         if (current_config->pch_pfit.enabled) {
11004                 PIPE_CONF_CHECK_I(pch_pfit.pos);
11005                 PIPE_CONF_CHECK_I(pch_pfit.size);
11006         }
11007
11008         /* BDW+ don't expose a synchronous way to read the state */
11009         if (IS_HASWELL(dev))
11010                 PIPE_CONF_CHECK_I(ips_enabled);
11011
11012         PIPE_CONF_CHECK_I(double_wide);
11013
11014         PIPE_CONF_CHECK_X(ddi_pll_sel);
11015
11016         PIPE_CONF_CHECK_I(shared_dpll);
11017         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11018         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11019         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11020         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11021         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11022         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11023         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11024         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11025
11026         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11027                 PIPE_CONF_CHECK_I(pipe_bpp);
11028
11029         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11030         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11031
11032 #undef PIPE_CONF_CHECK_X
11033 #undef PIPE_CONF_CHECK_I
11034 #undef PIPE_CONF_CHECK_I_ALT
11035 #undef PIPE_CONF_CHECK_FLAGS
11036 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11037 #undef PIPE_CONF_QUIRK
11038
11039         return true;
11040 }
11041
11042 static void check_wm_state(struct drm_device *dev)
11043 {
11044         struct drm_i915_private *dev_priv = dev->dev_private;
11045         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11046         struct intel_crtc *intel_crtc;
11047         int plane;
11048
11049         if (INTEL_INFO(dev)->gen < 9)
11050                 return;
11051
11052         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11053         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11054
11055         for_each_intel_crtc(dev, intel_crtc) {
11056                 struct skl_ddb_entry *hw_entry, *sw_entry;
11057                 const enum pipe pipe = intel_crtc->pipe;
11058
11059                 if (!intel_crtc->active)
11060                         continue;
11061
11062                 /* planes */
11063                 for_each_plane(dev_priv, pipe, plane) {
11064                         hw_entry = &hw_ddb.plane[pipe][plane];
11065                         sw_entry = &sw_ddb->plane[pipe][plane];
11066
11067                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
11068                                 continue;
11069
11070                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11071                                   "(expected (%u,%u), found (%u,%u))\n",
11072                                   pipe_name(pipe), plane + 1,
11073                                   sw_entry->start, sw_entry->end,
11074                                   hw_entry->start, hw_entry->end);
11075                 }
11076
11077                 /* cursor */
11078                 hw_entry = &hw_ddb.cursor[pipe];
11079                 sw_entry = &sw_ddb->cursor[pipe];
11080
11081                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11082                         continue;
11083
11084                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11085                           "(expected (%u,%u), found (%u,%u))\n",
11086                           pipe_name(pipe),
11087                           sw_entry->start, sw_entry->end,
11088                           hw_entry->start, hw_entry->end);
11089         }
11090 }
11091
11092 static void
11093 check_connector_state(struct drm_device *dev)
11094 {
11095         struct intel_connector *connector;
11096
11097         for_each_intel_connector(dev, connector) {
11098                 /* This also checks the encoder/connector hw state with the
11099                  * ->get_hw_state callbacks. */
11100                 intel_connector_check_state(connector);
11101
11102                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11103                      "connector's staged encoder doesn't match current encoder\n");
11104         }
11105 }
11106
11107 static void
11108 check_encoder_state(struct drm_device *dev)
11109 {
11110         struct intel_encoder *encoder;
11111         struct intel_connector *connector;
11112
11113         for_each_intel_encoder(dev, encoder) {
11114                 bool enabled = false;
11115                 bool active = false;
11116                 enum pipe pipe, tracked_pipe;
11117
11118                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11119                               encoder->base.base.id,
11120                               encoder->base.name);
11121
11122                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11123                      "encoder's stage crtc doesn't match current crtc\n");
11124                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11125                      "encoder's active_connectors set, but no crtc\n");
11126
11127                 for_each_intel_connector(dev, connector) {
11128                         if (connector->base.encoder != &encoder->base)
11129                                 continue;
11130                         enabled = true;
11131                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11132                                 active = true;
11133                 }
11134                 /*
11135                  * for MST connectors if we unplug the connector is gone
11136                  * away but the encoder is still connected to a crtc
11137                  * until a modeset happens in response to the hotplug.
11138                  */
11139                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11140                         continue;
11141
11142                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11143                      "encoder's enabled state mismatch "
11144                      "(expected %i, found %i)\n",
11145                      !!encoder->base.crtc, enabled);
11146                 I915_STATE_WARN(active && !encoder->base.crtc,
11147                      "active encoder with no crtc\n");
11148
11149                 I915_STATE_WARN(encoder->connectors_active != active,
11150                      "encoder's computed active state doesn't match tracked active state "
11151                      "(expected %i, found %i)\n", active, encoder->connectors_active);
11152
11153                 active = encoder->get_hw_state(encoder, &pipe);
11154                 I915_STATE_WARN(active != encoder->connectors_active,
11155                      "encoder's hw state doesn't match sw tracking "
11156                      "(expected %i, found %i)\n",
11157                      encoder->connectors_active, active);
11158
11159                 if (!encoder->base.crtc)
11160                         continue;
11161
11162                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11163                 I915_STATE_WARN(active && pipe != tracked_pipe,
11164                      "active encoder's pipe doesn't match"
11165                      "(expected %i, found %i)\n",
11166                      tracked_pipe, pipe);
11167
11168         }
11169 }
11170
11171 static void
11172 check_crtc_state(struct drm_device *dev)
11173 {
11174         struct drm_i915_private *dev_priv = dev->dev_private;
11175         struct intel_crtc *crtc;
11176         struct intel_encoder *encoder;
11177         struct intel_crtc_state pipe_config;
11178
11179         for_each_intel_crtc(dev, crtc) {
11180                 bool enabled = false;
11181                 bool active = false;
11182
11183                 memset(&pipe_config, 0, sizeof(pipe_config));
11184
11185                 DRM_DEBUG_KMS("[CRTC:%d]\n",
11186                               crtc->base.base.id);
11187
11188                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11189                      "active crtc, but not enabled in sw tracking\n");
11190
11191                 for_each_intel_encoder(dev, encoder) {
11192                         if (encoder->base.crtc != &crtc->base)
11193                                 continue;
11194                         enabled = true;
11195                         if (encoder->connectors_active)
11196                                 active = true;
11197                 }
11198
11199                 I915_STATE_WARN(active != crtc->active,
11200                      "crtc's computed active state doesn't match tracked active state "
11201                      "(expected %i, found %i)\n", active, crtc->active);
11202                 I915_STATE_WARN(enabled != crtc->base.state->enable,
11203                      "crtc's computed enabled state doesn't match tracked enabled state "
11204                      "(expected %i, found %i)\n", enabled,
11205                                 crtc->base.state->enable);
11206
11207                 active = dev_priv->display.get_pipe_config(crtc,
11208                                                            &pipe_config);
11209
11210                 /* hw state is inconsistent with the pipe quirk */
11211                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11212                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11213                         active = crtc->active;
11214
11215                 for_each_intel_encoder(dev, encoder) {
11216                         enum pipe pipe;
11217                         if (encoder->base.crtc != &crtc->base)
11218                                 continue;
11219                         if (encoder->get_hw_state(encoder, &pipe))
11220                                 encoder->get_config(encoder, &pipe_config);
11221                 }
11222
11223                 I915_STATE_WARN(crtc->active != active,
11224                      "crtc active state doesn't match with hw state "
11225                      "(expected %i, found %i)\n", crtc->active, active);
11226
11227                 if (active &&
11228                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11229                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
11230                         intel_dump_pipe_config(crtc, &pipe_config,
11231                                                "[hw state]");
11232                         intel_dump_pipe_config(crtc, crtc->config,
11233                                                "[sw state]");
11234                 }
11235         }
11236 }
11237
11238 static void
11239 check_shared_dpll_state(struct drm_device *dev)
11240 {
11241         struct drm_i915_private *dev_priv = dev->dev_private;
11242         struct intel_crtc *crtc;
11243         struct intel_dpll_hw_state dpll_hw_state;
11244         int i;
11245
11246         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11247                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11248                 int enabled_crtcs = 0, active_crtcs = 0;
11249                 bool active;
11250
11251                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11252
11253                 DRM_DEBUG_KMS("%s\n", pll->name);
11254
11255                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11256
11257                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11258                      "more active pll users than references: %i vs %i\n",
11259                      pll->active, hweight32(pll->config.crtc_mask));
11260                 I915_STATE_WARN(pll->active && !pll->on,
11261                      "pll in active use but not on in sw tracking\n");
11262                 I915_STATE_WARN(pll->on && !pll->active,
11263                      "pll in on but not on in use in sw tracking\n");
11264                 I915_STATE_WARN(pll->on != active,
11265                      "pll on state mismatch (expected %i, found %i)\n",
11266                      pll->on, active);
11267
11268                 for_each_intel_crtc(dev, crtc) {
11269                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11270                                 enabled_crtcs++;
11271                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11272                                 active_crtcs++;
11273                 }
11274                 I915_STATE_WARN(pll->active != active_crtcs,
11275                      "pll active crtcs mismatch (expected %i, found %i)\n",
11276                      pll->active, active_crtcs);
11277                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11278                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
11279                      hweight32(pll->config.crtc_mask), enabled_crtcs);
11280
11281                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11282                                        sizeof(dpll_hw_state)),
11283                      "pll hw state mismatch\n");
11284         }
11285 }
11286
11287 void
11288 intel_modeset_check_state(struct drm_device *dev)
11289 {
11290         check_wm_state(dev);
11291         check_connector_state(dev);
11292         check_encoder_state(dev);
11293         check_crtc_state(dev);
11294         check_shared_dpll_state(dev);
11295 }
11296
11297 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11298                                      int dotclock)
11299 {
11300         /*
11301          * FDI already provided one idea for the dotclock.
11302          * Yell if the encoder disagrees.
11303          */
11304         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11305              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11306              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11307 }
11308
11309 static void update_scanline_offset(struct intel_crtc *crtc)
11310 {
11311         struct drm_device *dev = crtc->base.dev;
11312
11313         /*
11314          * The scanline counter increments at the leading edge of hsync.
11315          *
11316          * On most platforms it starts counting from vtotal-1 on the
11317          * first active line. That means the scanline counter value is
11318          * always one less than what we would expect. Ie. just after
11319          * start of vblank, which also occurs at start of hsync (on the
11320          * last active line), the scanline counter will read vblank_start-1.
11321          *
11322          * On gen2 the scanline counter starts counting from 1 instead
11323          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11324          * to keep the value positive), instead of adding one.
11325          *
11326          * On HSW+ the behaviour of the scanline counter depends on the output
11327          * type. For DP ports it behaves like most other platforms, but on HDMI
11328          * there's an extra 1 line difference. So we need to add two instead of
11329          * one to the value.
11330          */
11331         if (IS_GEN2(dev)) {
11332                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11333                 int vtotal;
11334
11335                 vtotal = mode->crtc_vtotal;
11336                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11337                         vtotal /= 2;
11338
11339                 crtc->scanline_offset = vtotal - 1;
11340         } else if (HAS_DDI(dev) &&
11341                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11342                 crtc->scanline_offset = 2;
11343         } else
11344                 crtc->scanline_offset = 1;
11345 }
11346
11347 static struct intel_crtc_state *
11348 intel_modeset_compute_config(struct drm_crtc *crtc,
11349                              struct drm_display_mode *mode,
11350                              struct drm_framebuffer *fb,
11351                              struct drm_atomic_state *state,
11352                              unsigned *modeset_pipes,
11353                              unsigned *prepare_pipes,
11354                              unsigned *disable_pipes)
11355 {
11356         struct drm_device *dev = crtc->dev;
11357         struct intel_crtc_state *pipe_config = NULL;
11358         struct intel_crtc *intel_crtc;
11359         int ret = 0;
11360
11361         ret = drm_atomic_add_affected_connectors(state, crtc);
11362         if (ret)
11363                 return ERR_PTR(ret);
11364
11365         intel_modeset_affected_pipes(crtc, modeset_pipes,
11366                                      prepare_pipes, disable_pipes);
11367
11368         for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
11369                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11370                 if (IS_ERR(pipe_config))
11371                         return pipe_config;
11372
11373                 pipe_config->base.enable = false;
11374         }
11375
11376         /*
11377          * Note this needs changes when we start tracking multiple modes
11378          * and crtcs.  At that point we'll need to compute the whole config
11379          * (i.e. one pipe_config for each crtc) rather than just the one
11380          * for this crtc.
11381          */
11382         for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
11383                 /* FIXME: For now we still expect modeset_pipes has at most
11384                  * one bit set. */
11385                 if (WARN_ON(&intel_crtc->base != crtc))
11386                         continue;
11387
11388                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state);
11389                 if (IS_ERR(pipe_config))
11390                         return pipe_config;
11391
11392                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11393                                        "[modeset]");
11394         }
11395
11396         return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
11397 }
11398
11399 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11400                                        unsigned modeset_pipes,
11401                                        unsigned disable_pipes)
11402 {
11403         struct drm_i915_private *dev_priv = to_i915(dev);
11404         unsigned clear_pipes = modeset_pipes | disable_pipes;
11405         struct intel_crtc *intel_crtc;
11406         int ret = 0;
11407
11408         if (!dev_priv->display.crtc_compute_clock)
11409                 return 0;
11410
11411         ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11412         if (ret)
11413                 goto done;
11414
11415         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11416                 struct intel_crtc_state *state = intel_crtc->new_config;
11417                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11418                                                            state);
11419                 if (ret) {
11420                         intel_shared_dpll_abort_config(dev_priv);
11421                         goto done;
11422                 }
11423         }
11424
11425 done:
11426         return ret;
11427 }
11428
11429 static int __intel_set_mode(struct drm_crtc *crtc,
11430                             struct drm_display_mode *mode,
11431                             int x, int y, struct drm_framebuffer *fb,
11432                             struct intel_crtc_state *pipe_config,
11433                             unsigned modeset_pipes,
11434                             unsigned prepare_pipes,
11435                             unsigned disable_pipes)
11436 {
11437         struct drm_device *dev = crtc->dev;
11438         struct drm_i915_private *dev_priv = dev->dev_private;
11439         struct drm_display_mode *saved_mode;
11440         struct intel_crtc_state *crtc_state_copy = NULL;
11441         struct intel_crtc *intel_crtc;
11442         int ret = 0;
11443
11444         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11445         if (!saved_mode)
11446                 return -ENOMEM;
11447
11448         crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
11449         if (!crtc_state_copy) {
11450                 ret = -ENOMEM;
11451                 goto done;
11452         }
11453
11454         *saved_mode = crtc->mode;
11455
11456         if (modeset_pipes)
11457                 to_intel_crtc(crtc)->new_config = pipe_config;
11458
11459         /*
11460          * See if the config requires any additional preparation, e.g.
11461          * to adjust global state with pipes off.  We need to do this
11462          * here so we can get the modeset_pipe updated config for the new
11463          * mode set on this crtc.  For other crtcs we need to use the
11464          * adjusted_mode bits in the crtc directly.
11465          */
11466         if (IS_VALLEYVIEW(dev)) {
11467                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11468
11469                 /* may have added more to prepare_pipes than we should */
11470                 prepare_pipes &= ~disable_pipes;
11471         }
11472
11473         ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11474         if (ret)
11475                 goto done;
11476
11477         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11478                 intel_crtc_disable(&intel_crtc->base);
11479
11480         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11481                 if (intel_crtc->base.state->enable)
11482                         dev_priv->display.crtc_disable(&intel_crtc->base);
11483         }
11484
11485         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11486          * to set it here already despite that we pass it down the callchain.
11487          *
11488          * Note we'll need to fix this up when we start tracking multiple
11489          * pipes; here we assume a single modeset_pipe and only track the
11490          * single crtc and mode.
11491          */
11492         if (modeset_pipes) {
11493                 crtc->mode = *mode;
11494                 /* mode_set/enable/disable functions rely on a correct pipe
11495                  * config. */
11496                 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11497
11498                 /*
11499                  * Calculate and store various constants which
11500                  * are later needed by vblank and swap-completion
11501                  * timestamping. They are derived from true hwmode.
11502                  */
11503                 drm_calc_timestamping_constants(crtc,
11504                                                 &pipe_config->base.adjusted_mode);
11505         }
11506
11507         /* Only after disabling all output pipelines that will be changed can we
11508          * update the the output configuration. */
11509         intel_modeset_update_state(dev, prepare_pipes);
11510
11511         modeset_update_crtc_power_domains(pipe_config->base.state);
11512
11513         /* Set up the DPLL and any encoders state that needs to adjust or depend
11514          * on the DPLL.
11515          */
11516         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11517                 struct drm_plane *primary = intel_crtc->base.primary;
11518                 int vdisplay, hdisplay;
11519
11520                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11521                 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11522                                                    fb, 0, 0,
11523                                                    hdisplay, vdisplay,
11524                                                    x << 16, y << 16,
11525                                                    hdisplay << 16, vdisplay << 16);
11526         }
11527
11528         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11529         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11530                 update_scanline_offset(intel_crtc);
11531
11532                 dev_priv->display.crtc_enable(&intel_crtc->base);
11533         }
11534
11535         /* FIXME: add subpixel order */
11536 done:
11537         if (ret && crtc->state->enable)
11538                 crtc->mode = *saved_mode;
11539
11540         if (ret == 0 && pipe_config) {
11541                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11542
11543                 /* The pipe_config will be freed with the atomic state, so
11544                  * make a copy. */
11545                 memcpy(crtc_state_copy, intel_crtc->config,
11546                        sizeof *crtc_state_copy);
11547                 intel_crtc->config = crtc_state_copy;
11548                 intel_crtc->base.state = &crtc_state_copy->base;
11549
11550                 if (modeset_pipes)
11551                         intel_crtc->new_config = intel_crtc->config;
11552         } else {
11553                 kfree(crtc_state_copy);
11554         }
11555
11556         kfree(saved_mode);
11557         return ret;
11558 }
11559
11560 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11561                                 struct drm_display_mode *mode,
11562                                 int x, int y, struct drm_framebuffer *fb,
11563                                 struct intel_crtc_state *pipe_config,
11564                                 unsigned modeset_pipes,
11565                                 unsigned prepare_pipes,
11566                                 unsigned disable_pipes)
11567 {
11568         int ret;
11569
11570         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11571                                prepare_pipes, disable_pipes);
11572
11573         if (ret == 0)
11574                 intel_modeset_check_state(crtc->dev);
11575
11576         return ret;
11577 }
11578
11579 static int intel_set_mode(struct drm_crtc *crtc,
11580                           struct drm_display_mode *mode,
11581                           int x, int y, struct drm_framebuffer *fb,
11582                           struct drm_atomic_state *state)
11583 {
11584         struct intel_crtc_state *pipe_config;
11585         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11586         int ret = 0;
11587
11588         pipe_config = intel_modeset_compute_config(crtc, mode, fb, state,
11589                                                    &modeset_pipes,
11590                                                    &prepare_pipes,
11591                                                    &disable_pipes);
11592
11593         if (IS_ERR(pipe_config)) {
11594                 ret = PTR_ERR(pipe_config);
11595                 goto out;
11596         }
11597
11598         ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11599                                    modeset_pipes, prepare_pipes,
11600                                    disable_pipes);
11601         if (ret)
11602                 goto out;
11603
11604 out:
11605         return ret;
11606 }
11607
11608 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11609 {
11610         struct drm_device *dev = crtc->dev;
11611         struct drm_atomic_state *state;
11612         struct intel_encoder *encoder;
11613         struct intel_connector *connector;
11614         struct drm_connector_state *connector_state;
11615
11616         state = drm_atomic_state_alloc(dev);
11617         if (!state) {
11618                 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
11619                               crtc->base.id);
11620                 return;
11621         }
11622
11623         state->acquire_ctx = dev->mode_config.acquire_ctx;
11624
11625         /* The force restore path in the HW readout code relies on the staged
11626          * config still keeping the user requested config while the actual
11627          * state has been overwritten by the configuration read from HW. We
11628          * need to copy the staged config to the atomic state, otherwise the
11629          * mode set will just reapply the state the HW is already in. */
11630         for_each_intel_encoder(dev, encoder) {
11631                 if (&encoder->new_crtc->base != crtc)
11632                         continue;
11633
11634                 for_each_intel_connector(dev, connector) {
11635                         if (connector->new_encoder != encoder)
11636                                 continue;
11637
11638                         connector_state = drm_atomic_get_connector_state(state, &connector->base);
11639                         if (IS_ERR(connector_state)) {
11640                                 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
11641                                               connector->base.base.id,
11642                                               connector->base.name,
11643                                               PTR_ERR(connector_state));
11644                                 continue;
11645                         }
11646
11647                         connector_state->crtc = crtc;
11648                         connector_state->best_encoder = &encoder->base;
11649                 }
11650         }
11651
11652         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
11653                        state);
11654
11655         drm_atomic_state_free(state);
11656 }
11657
11658 #undef for_each_intel_crtc_masked
11659
11660 static void intel_set_config_free(struct intel_set_config *config)
11661 {
11662         if (!config)
11663                 return;
11664
11665         kfree(config->save_connector_encoders);
11666         kfree(config->save_encoder_crtcs);
11667         kfree(config->save_crtc_enabled);
11668         kfree(config);
11669 }
11670
11671 static int intel_set_config_save_state(struct drm_device *dev,
11672                                        struct intel_set_config *config)
11673 {
11674         struct drm_crtc *crtc;
11675         struct drm_encoder *encoder;
11676         struct drm_connector *connector;
11677         int count;
11678
11679         config->save_crtc_enabled =
11680                 kcalloc(dev->mode_config.num_crtc,
11681                         sizeof(bool), GFP_KERNEL);
11682         if (!config->save_crtc_enabled)
11683                 return -ENOMEM;
11684
11685         config->save_encoder_crtcs =
11686                 kcalloc(dev->mode_config.num_encoder,
11687                         sizeof(struct drm_crtc *), GFP_KERNEL);
11688         if (!config->save_encoder_crtcs)
11689                 return -ENOMEM;
11690
11691         config->save_connector_encoders =
11692                 kcalloc(dev->mode_config.num_connector,
11693                         sizeof(struct drm_encoder *), GFP_KERNEL);
11694         if (!config->save_connector_encoders)
11695                 return -ENOMEM;
11696
11697         /* Copy data. Note that driver private data is not affected.
11698          * Should anything bad happen only the expected state is
11699          * restored, not the drivers personal bookkeeping.
11700          */
11701         count = 0;
11702         for_each_crtc(dev, crtc) {
11703                 config->save_crtc_enabled[count++] = crtc->state->enable;
11704         }
11705
11706         count = 0;
11707         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11708                 config->save_encoder_crtcs[count++] = encoder->crtc;
11709         }
11710
11711         count = 0;
11712         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11713                 config->save_connector_encoders[count++] = connector->encoder;
11714         }
11715
11716         return 0;
11717 }
11718
11719 static void intel_set_config_restore_state(struct drm_device *dev,
11720                                            struct intel_set_config *config)
11721 {
11722         struct intel_crtc *crtc;
11723         struct intel_encoder *encoder;
11724         struct intel_connector *connector;
11725         int count;
11726
11727         count = 0;
11728         for_each_intel_crtc(dev, crtc) {
11729                 crtc->new_enabled = config->save_crtc_enabled[count++];
11730
11731                 if (crtc->new_enabled)
11732                         crtc->new_config = crtc->config;
11733                 else
11734                         crtc->new_config = NULL;
11735         }
11736
11737         count = 0;
11738         for_each_intel_encoder(dev, encoder) {
11739                 encoder->new_crtc =
11740                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11741         }
11742
11743         count = 0;
11744         for_each_intel_connector(dev, connector) {
11745                 connector->new_encoder =
11746                         to_intel_encoder(config->save_connector_encoders[count++]);
11747         }
11748 }
11749
11750 static bool
11751 is_crtc_connector_off(struct drm_mode_set *set)
11752 {
11753         int i;
11754
11755         if (set->num_connectors == 0)
11756                 return false;
11757
11758         if (WARN_ON(set->connectors == NULL))
11759                 return false;
11760
11761         for (i = 0; i < set->num_connectors; i++)
11762                 if (set->connectors[i]->encoder &&
11763                     set->connectors[i]->encoder->crtc == set->crtc &&
11764                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11765                         return true;
11766
11767         return false;
11768 }
11769
11770 static void
11771 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11772                                       struct intel_set_config *config)
11773 {
11774
11775         /* We should be able to check here if the fb has the same properties
11776          * and then just flip_or_move it */
11777         if (is_crtc_connector_off(set)) {
11778                 config->mode_changed = true;
11779         } else if (set->crtc->primary->fb != set->fb) {
11780                 /*
11781                  * If we have no fb, we can only flip as long as the crtc is
11782                  * active, otherwise we need a full mode set.  The crtc may
11783                  * be active if we've only disabled the primary plane, or
11784                  * in fastboot situations.
11785                  */
11786                 if (set->crtc->primary->fb == NULL) {
11787                         struct intel_crtc *intel_crtc =
11788                                 to_intel_crtc(set->crtc);
11789
11790                         if (intel_crtc->active) {
11791                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11792                                 config->fb_changed = true;
11793                         } else {
11794                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11795                                 config->mode_changed = true;
11796                         }
11797                 } else if (set->fb == NULL) {
11798                         config->mode_changed = true;
11799                 } else if (set->fb->pixel_format !=
11800                            set->crtc->primary->fb->pixel_format) {
11801                         config->mode_changed = true;
11802                 } else {
11803                         config->fb_changed = true;
11804                 }
11805         }
11806
11807         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11808                 config->fb_changed = true;
11809
11810         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11811                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11812                 drm_mode_debug_printmodeline(&set->crtc->mode);
11813                 drm_mode_debug_printmodeline(set->mode);
11814                 config->mode_changed = true;
11815         }
11816
11817         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11818                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11819 }
11820
11821 static int
11822 intel_modeset_stage_output_state(struct drm_device *dev,
11823                                  struct drm_mode_set *set,
11824                                  struct intel_set_config *config,
11825                                  struct drm_atomic_state *state)
11826 {
11827         struct intel_connector *connector;
11828         struct drm_connector_state *connector_state;
11829         struct intel_encoder *encoder;
11830         struct intel_crtc *crtc;
11831         int ro;
11832
11833         /* The upper layers ensure that we either disable a crtc or have a list
11834          * of connectors. For paranoia, double-check this. */
11835         WARN_ON(!set->fb && (set->num_connectors != 0));
11836         WARN_ON(set->fb && (set->num_connectors == 0));
11837
11838         for_each_intel_connector(dev, connector) {
11839                 /* Otherwise traverse passed in connector list and get encoders
11840                  * for them. */
11841                 for (ro = 0; ro < set->num_connectors; ro++) {
11842                         if (set->connectors[ro] == &connector->base) {
11843                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11844                                 break;
11845                         }
11846                 }
11847
11848                 /* If we disable the crtc, disable all its connectors. Also, if
11849                  * the connector is on the changing crtc but not on the new
11850                  * connector list, disable it. */
11851                 if ((!set->fb || ro == set->num_connectors) &&
11852                     connector->base.encoder &&
11853                     connector->base.encoder->crtc == set->crtc) {
11854                         connector->new_encoder = NULL;
11855
11856                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11857                                 connector->base.base.id,
11858                                 connector->base.name);
11859                 }
11860
11861
11862                 if (&connector->new_encoder->base != connector->base.encoder) {
11863                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11864                                       connector->base.base.id,
11865                                       connector->base.name);
11866                         config->mode_changed = true;
11867                 }
11868         }
11869         /* connector->new_encoder is now updated for all connectors. */
11870
11871         /* Update crtc of enabled connectors. */
11872         for_each_intel_connector(dev, connector) {
11873                 struct drm_crtc *new_crtc;
11874
11875                 if (!connector->new_encoder)
11876                         continue;
11877
11878                 new_crtc = connector->new_encoder->base.crtc;
11879
11880                 for (ro = 0; ro < set->num_connectors; ro++) {
11881                         if (set->connectors[ro] == &connector->base)
11882                                 new_crtc = set->crtc;
11883                 }
11884
11885                 /* Make sure the new CRTC will work with the encoder */
11886                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11887                                          new_crtc)) {
11888                         return -EINVAL;
11889                 }
11890                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11891
11892                 connector_state =
11893                         drm_atomic_get_connector_state(state, &connector->base);
11894                 if (IS_ERR(connector_state))
11895                         return PTR_ERR(connector_state);
11896
11897                 connector_state->crtc = new_crtc;
11898                 connector_state->best_encoder = &connector->new_encoder->base;
11899
11900                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11901                         connector->base.base.id,
11902                         connector->base.name,
11903                         new_crtc->base.id);
11904         }
11905
11906         /* Check for any encoders that needs to be disabled. */
11907         for_each_intel_encoder(dev, encoder) {
11908                 int num_connectors = 0;
11909                 for_each_intel_connector(dev, connector) {
11910                         if (connector->new_encoder == encoder) {
11911                                 WARN_ON(!connector->new_encoder->new_crtc);
11912                                 num_connectors++;
11913                         }
11914                 }
11915
11916                 if (num_connectors == 0)
11917                         encoder->new_crtc = NULL;
11918                 else if (num_connectors > 1)
11919                         return -EINVAL;
11920
11921                 /* Only now check for crtc changes so we don't miss encoders
11922                  * that will be disabled. */
11923                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11924                         DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11925                                       encoder->base.base.id,
11926                                       encoder->base.name);
11927                         config->mode_changed = true;
11928                 }
11929         }
11930         /* Now we've also updated encoder->new_crtc for all encoders. */
11931         for_each_intel_connector(dev, connector) {
11932                 connector_state =
11933                         drm_atomic_get_connector_state(state, &connector->base);
11934
11935                 if (connector->new_encoder) {
11936                         if (connector->new_encoder != connector->encoder)
11937                                 connector->encoder = connector->new_encoder;
11938                 } else {
11939                         connector_state->crtc = NULL;
11940                 }
11941         }
11942         for_each_intel_crtc(dev, crtc) {
11943                 crtc->new_enabled = false;
11944
11945                 for_each_intel_encoder(dev, encoder) {
11946                         if (encoder->new_crtc == crtc) {
11947                                 crtc->new_enabled = true;
11948                                 break;
11949                         }
11950                 }
11951
11952                 if (crtc->new_enabled != crtc->base.state->enable) {
11953                         DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11954                                       crtc->base.base.id,
11955                                       crtc->new_enabled ? "en" : "dis");
11956                         config->mode_changed = true;
11957                 }
11958
11959                 if (crtc->new_enabled)
11960                         crtc->new_config = crtc->config;
11961                 else
11962                         crtc->new_config = NULL;
11963         }
11964
11965         return 0;
11966 }
11967
11968 static void disable_crtc_nofb(struct intel_crtc *crtc)
11969 {
11970         struct drm_device *dev = crtc->base.dev;
11971         struct intel_encoder *encoder;
11972         struct intel_connector *connector;
11973
11974         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11975                       pipe_name(crtc->pipe));
11976
11977         for_each_intel_connector(dev, connector) {
11978                 if (connector->new_encoder &&
11979                     connector->new_encoder->new_crtc == crtc)
11980                         connector->new_encoder = NULL;
11981         }
11982
11983         for_each_intel_encoder(dev, encoder) {
11984                 if (encoder->new_crtc == crtc)
11985                         encoder->new_crtc = NULL;
11986         }
11987
11988         crtc->new_enabled = false;
11989         crtc->new_config = NULL;
11990 }
11991
11992 static int intel_crtc_set_config(struct drm_mode_set *set)
11993 {
11994         struct drm_device *dev;
11995         struct drm_mode_set save_set;
11996         struct drm_atomic_state *state = NULL;
11997         struct intel_set_config *config;
11998         struct intel_crtc_state *pipe_config;
11999         unsigned modeset_pipes, prepare_pipes, disable_pipes;
12000         int ret;
12001
12002         BUG_ON(!set);
12003         BUG_ON(!set->crtc);
12004         BUG_ON(!set->crtc->helper_private);
12005
12006         /* Enforce sane interface api - has been abused by the fb helper. */
12007         BUG_ON(!set->mode && set->fb);
12008         BUG_ON(set->fb && set->num_connectors == 0);
12009
12010         if (set->fb) {
12011                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12012                                 set->crtc->base.id, set->fb->base.id,
12013                                 (int)set->num_connectors, set->x, set->y);
12014         } else {
12015                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12016         }
12017
12018         dev = set->crtc->dev;
12019
12020         ret = -ENOMEM;
12021         config = kzalloc(sizeof(*config), GFP_KERNEL);
12022         if (!config)
12023                 goto out_config;
12024
12025         ret = intel_set_config_save_state(dev, config);
12026         if (ret)
12027                 goto out_config;
12028
12029         save_set.crtc = set->crtc;
12030         save_set.mode = &set->crtc->mode;
12031         save_set.x = set->crtc->x;
12032         save_set.y = set->crtc->y;
12033         save_set.fb = set->crtc->primary->fb;
12034
12035         /* Compute whether we need a full modeset, only an fb base update or no
12036          * change at all. In the future we might also check whether only the
12037          * mode changed, e.g. for LVDS where we only change the panel fitter in
12038          * such cases. */
12039         intel_set_config_compute_mode_changes(set, config);
12040
12041         state = drm_atomic_state_alloc(dev);
12042         if (!state) {
12043                 ret = -ENOMEM;
12044                 goto out_config;
12045         }
12046
12047         state->acquire_ctx = dev->mode_config.acquire_ctx;
12048
12049         ret = intel_modeset_stage_output_state(dev, set, config, state);
12050         if (ret)
12051                 goto fail;
12052
12053         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
12054                                                    set->fb, state,
12055                                                    &modeset_pipes,
12056                                                    &prepare_pipes,
12057                                                    &disable_pipes);
12058         if (IS_ERR(pipe_config)) {
12059                 ret = PTR_ERR(pipe_config);
12060                 goto fail;
12061         } else if (pipe_config) {
12062                 if (pipe_config->has_audio !=
12063                     to_intel_crtc(set->crtc)->config->has_audio)
12064                         config->mode_changed = true;
12065
12066                 /*
12067                  * Note we have an issue here with infoframes: current code
12068                  * only updates them on the full mode set path per hw
12069                  * requirements.  So here we should be checking for any
12070                  * required changes and forcing a mode set.
12071                  */
12072         }
12073
12074         intel_update_pipe_size(to_intel_crtc(set->crtc));
12075
12076         if (config->mode_changed) {
12077                 ret = intel_set_mode_pipes(set->crtc, set->mode,
12078                                            set->x, set->y, set->fb, pipe_config,
12079                                            modeset_pipes, prepare_pipes,
12080                                            disable_pipes);
12081         } else if (config->fb_changed) {
12082                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12083                 struct drm_plane *primary = set->crtc->primary;
12084                 int vdisplay, hdisplay;
12085
12086                 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
12087                 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
12088                                                    0, 0, hdisplay, vdisplay,
12089                                                    set->x << 16, set->y << 16,
12090                                                    hdisplay << 16, vdisplay << 16);
12091
12092                 /*
12093                  * We need to make sure the primary plane is re-enabled if it
12094                  * has previously been turned off.
12095                  */
12096                 if (!intel_crtc->primary_enabled && ret == 0) {
12097                         WARN_ON(!intel_crtc->active);
12098                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
12099                 }
12100
12101                 /*
12102                  * In the fastboot case this may be our only check of the
12103                  * state after boot.  It would be better to only do it on
12104                  * the first update, but we don't have a nice way of doing that
12105                  * (and really, set_config isn't used much for high freq page
12106                  * flipping, so increasing its cost here shouldn't be a big
12107                  * deal).
12108                  */
12109                 if (i915.fastboot && ret == 0)
12110                         intel_modeset_check_state(set->crtc->dev);
12111         }
12112
12113         if (ret) {
12114                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12115                               set->crtc->base.id, ret);
12116 fail:
12117                 intel_set_config_restore_state(dev, config);
12118
12119                 drm_atomic_state_clear(state);
12120
12121                 /*
12122                  * HACK: if the pipe was on, but we didn't have a framebuffer,
12123                  * force the pipe off to avoid oopsing in the modeset code
12124                  * due to fb==NULL. This should only happen during boot since
12125                  * we don't yet reconstruct the FB from the hardware state.
12126                  */
12127                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12128                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12129
12130                 /* Try to restore the config */
12131                 if (config->mode_changed &&
12132                     intel_set_mode(save_set.crtc, save_set.mode,
12133                                    save_set.x, save_set.y, save_set.fb,
12134                                    state))
12135                         DRM_ERROR("failed to restore config after modeset failure\n");
12136         }
12137
12138 out_config:
12139         if (state)
12140                 drm_atomic_state_free(state);
12141
12142         intel_set_config_free(config);
12143         return ret;
12144 }
12145
12146 static const struct drm_crtc_funcs intel_crtc_funcs = {
12147         .gamma_set = intel_crtc_gamma_set,
12148         .set_config = intel_crtc_set_config,
12149         .destroy = intel_crtc_destroy,
12150         .page_flip = intel_crtc_page_flip,
12151         .atomic_duplicate_state = intel_crtc_duplicate_state,
12152         .atomic_destroy_state = intel_crtc_destroy_state,
12153 };
12154
12155 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12156                                       struct intel_shared_dpll *pll,
12157                                       struct intel_dpll_hw_state *hw_state)
12158 {
12159         uint32_t val;
12160
12161         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12162                 return false;
12163
12164         val = I915_READ(PCH_DPLL(pll->id));
12165         hw_state->dpll = val;
12166         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12167         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12168
12169         return val & DPLL_VCO_ENABLE;
12170 }
12171
12172 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12173                                   struct intel_shared_dpll *pll)
12174 {
12175         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12176         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12177 }
12178
12179 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12180                                 struct intel_shared_dpll *pll)
12181 {
12182         /* PCH refclock must be enabled first */
12183         ibx_assert_pch_refclk_enabled(dev_priv);
12184
12185         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12186
12187         /* Wait for the clocks to stabilize. */
12188         POSTING_READ(PCH_DPLL(pll->id));
12189         udelay(150);
12190
12191         /* The pixel multiplier can only be updated once the
12192          * DPLL is enabled and the clocks are stable.
12193          *
12194          * So write it again.
12195          */
12196         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12197         POSTING_READ(PCH_DPLL(pll->id));
12198         udelay(200);
12199 }
12200
12201 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12202                                  struct intel_shared_dpll *pll)
12203 {
12204         struct drm_device *dev = dev_priv->dev;
12205         struct intel_crtc *crtc;
12206
12207         /* Make sure no transcoder isn't still depending on us. */
12208         for_each_intel_crtc(dev, crtc) {
12209                 if (intel_crtc_to_shared_dpll(crtc) == pll)
12210                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12211         }
12212
12213         I915_WRITE(PCH_DPLL(pll->id), 0);
12214         POSTING_READ(PCH_DPLL(pll->id));
12215         udelay(200);
12216 }
12217
12218 static char *ibx_pch_dpll_names[] = {
12219         "PCH DPLL A",
12220         "PCH DPLL B",
12221 };
12222
12223 static void ibx_pch_dpll_init(struct drm_device *dev)
12224 {
12225         struct drm_i915_private *dev_priv = dev->dev_private;
12226         int i;
12227
12228         dev_priv->num_shared_dpll = 2;
12229
12230         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12231                 dev_priv->shared_dplls[i].id = i;
12232                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12233                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12234                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12235                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12236                 dev_priv->shared_dplls[i].get_hw_state =
12237                         ibx_pch_dpll_get_hw_state;
12238         }
12239 }
12240
12241 static void intel_shared_dpll_init(struct drm_device *dev)
12242 {
12243         struct drm_i915_private *dev_priv = dev->dev_private;
12244
12245         if (HAS_DDI(dev))
12246                 intel_ddi_pll_init(dev);
12247         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12248                 ibx_pch_dpll_init(dev);
12249         else
12250                 dev_priv->num_shared_dpll = 0;
12251
12252         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12253 }
12254
12255 /**
12256  * intel_wm_need_update - Check whether watermarks need updating
12257  * @plane: drm plane
12258  * @state: new plane state
12259  *
12260  * Check current plane state versus the new one to determine whether
12261  * watermarks need to be recalculated.
12262  *
12263  * Returns true or false.
12264  */
12265 bool intel_wm_need_update(struct drm_plane *plane,
12266                           struct drm_plane_state *state)
12267 {
12268         /* Update watermarks on tiling changes. */
12269         if (!plane->state->fb || !state->fb ||
12270             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12271             plane->state->rotation != state->rotation)
12272                 return true;
12273
12274         return false;
12275 }
12276
12277 /**
12278  * intel_prepare_plane_fb - Prepare fb for usage on plane
12279  * @plane: drm plane to prepare for
12280  * @fb: framebuffer to prepare for presentation
12281  *
12282  * Prepares a framebuffer for usage on a display plane.  Generally this
12283  * involves pinning the underlying object and updating the frontbuffer tracking
12284  * bits.  Some older platforms need special physical address handling for
12285  * cursor planes.
12286  *
12287  * Returns 0 on success, negative error code on failure.
12288  */
12289 int
12290 intel_prepare_plane_fb(struct drm_plane *plane,
12291                        struct drm_framebuffer *fb,
12292                        const struct drm_plane_state *new_state)
12293 {
12294         struct drm_device *dev = plane->dev;
12295         struct intel_plane *intel_plane = to_intel_plane(plane);
12296         enum pipe pipe = intel_plane->pipe;
12297         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12298         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12299         unsigned frontbuffer_bits = 0;
12300         int ret = 0;
12301
12302         if (!obj)
12303                 return 0;
12304
12305         switch (plane->type) {
12306         case DRM_PLANE_TYPE_PRIMARY:
12307                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12308                 break;
12309         case DRM_PLANE_TYPE_CURSOR:
12310                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12311                 break;
12312         case DRM_PLANE_TYPE_OVERLAY:
12313                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12314                 break;
12315         }
12316
12317         mutex_lock(&dev->struct_mutex);
12318
12319         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12320             INTEL_INFO(dev)->cursor_needs_physical) {
12321                 int align = IS_I830(dev) ? 16 * 1024 : 256;
12322                 ret = i915_gem_object_attach_phys(obj, align);
12323                 if (ret)
12324                         DRM_DEBUG_KMS("failed to attach phys object\n");
12325         } else {
12326                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12327         }
12328
12329         if (ret == 0)
12330                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12331
12332         mutex_unlock(&dev->struct_mutex);
12333
12334         return ret;
12335 }
12336
12337 /**
12338  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12339  * @plane: drm plane to clean up for
12340  * @fb: old framebuffer that was on plane
12341  *
12342  * Cleans up a framebuffer that has just been removed from a plane.
12343  */
12344 void
12345 intel_cleanup_plane_fb(struct drm_plane *plane,
12346                        struct drm_framebuffer *fb,
12347                        const struct drm_plane_state *old_state)
12348 {
12349         struct drm_device *dev = plane->dev;
12350         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12351
12352         if (WARN_ON(!obj))
12353                 return;
12354
12355         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12356             !INTEL_INFO(dev)->cursor_needs_physical) {
12357                 mutex_lock(&dev->struct_mutex);
12358                 intel_unpin_fb_obj(fb, old_state);
12359                 mutex_unlock(&dev->struct_mutex);
12360         }
12361 }
12362
12363 static int
12364 intel_check_primary_plane(struct drm_plane *plane,
12365                           struct intel_plane_state *state)
12366 {
12367         struct drm_device *dev = plane->dev;
12368         struct drm_i915_private *dev_priv = dev->dev_private;
12369         struct drm_crtc *crtc = state->base.crtc;
12370         struct intel_crtc *intel_crtc;
12371         struct drm_framebuffer *fb = state->base.fb;
12372         struct drm_rect *dest = &state->dst;
12373         struct drm_rect *src = &state->src;
12374         const struct drm_rect *clip = &state->clip;
12375         int ret;
12376
12377         crtc = crtc ? crtc : plane->crtc;
12378         intel_crtc = to_intel_crtc(crtc);
12379
12380         ret = drm_plane_helper_check_update(plane, crtc, fb,
12381                                             src, dest, clip,
12382                                             DRM_PLANE_HELPER_NO_SCALING,
12383                                             DRM_PLANE_HELPER_NO_SCALING,
12384                                             false, true, &state->visible);
12385         if (ret)
12386                 return ret;
12387
12388         if (intel_crtc->active) {
12389                 intel_crtc->atomic.wait_for_flips = true;
12390
12391                 /*
12392                  * FBC does not work on some platforms for rotated
12393                  * planes, so disable it when rotation is not 0 and
12394                  * update it when rotation is set back to 0.
12395                  *
12396                  * FIXME: This is redundant with the fbc update done in
12397                  * the primary plane enable function except that that
12398                  * one is done too late. We eventually need to unify
12399                  * this.
12400                  */
12401                 if (intel_crtc->primary_enabled &&
12402                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12403                     dev_priv->fbc.crtc == intel_crtc &&
12404                     state->base.rotation != BIT(DRM_ROTATE_0)) {
12405                         intel_crtc->atomic.disable_fbc = true;
12406                 }
12407
12408                 if (state->visible) {
12409                         /*
12410                          * BDW signals flip done immediately if the plane
12411                          * is disabled, even if the plane enable is already
12412                          * armed to occur at the next vblank :(
12413                          */
12414                         if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12415                                 intel_crtc->atomic.wait_vblank = true;
12416                 }
12417
12418                 intel_crtc->atomic.fb_bits |=
12419                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12420
12421                 intel_crtc->atomic.update_fbc = true;
12422
12423                 if (intel_wm_need_update(plane, &state->base))
12424                         intel_crtc->atomic.update_wm = true;
12425         }
12426
12427         return 0;
12428 }
12429
12430 static void
12431 intel_commit_primary_plane(struct drm_plane *plane,
12432                            struct intel_plane_state *state)
12433 {
12434         struct drm_crtc *crtc = state->base.crtc;
12435         struct drm_framebuffer *fb = state->base.fb;
12436         struct drm_device *dev = plane->dev;
12437         struct drm_i915_private *dev_priv = dev->dev_private;
12438         struct intel_crtc *intel_crtc;
12439         struct drm_rect *src = &state->src;
12440
12441         crtc = crtc ? crtc : plane->crtc;
12442         intel_crtc = to_intel_crtc(crtc);
12443
12444         plane->fb = fb;
12445         crtc->x = src->x1 >> 16;
12446         crtc->y = src->y1 >> 16;
12447
12448         if (intel_crtc->active) {
12449                 if (state->visible) {
12450                         /* FIXME: kill this fastboot hack */
12451                         intel_update_pipe_size(intel_crtc);
12452
12453                         intel_crtc->primary_enabled = true;
12454
12455                         dev_priv->display.update_primary_plane(crtc, plane->fb,
12456                                         crtc->x, crtc->y);
12457                 } else {
12458                         /*
12459                          * If clipping results in a non-visible primary plane,
12460                          * we'll disable the primary plane.  Note that this is
12461                          * a bit different than what happens if userspace
12462                          * explicitly disables the plane by passing fb=0
12463                          * because plane->fb still gets set and pinned.
12464                          */
12465                         intel_disable_primary_hw_plane(plane, crtc);
12466                 }
12467         }
12468 }
12469
12470 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12471 {
12472         struct drm_device *dev = crtc->dev;
12473         struct drm_i915_private *dev_priv = dev->dev_private;
12474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12475         struct intel_plane *intel_plane;
12476         struct drm_plane *p;
12477         unsigned fb_bits = 0;
12478
12479         /* Track fb's for any planes being disabled */
12480         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12481                 intel_plane = to_intel_plane(p);
12482
12483                 if (intel_crtc->atomic.disabled_planes &
12484                     (1 << drm_plane_index(p))) {
12485                         switch (p->type) {
12486                         case DRM_PLANE_TYPE_PRIMARY:
12487                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12488                                 break;
12489                         case DRM_PLANE_TYPE_CURSOR:
12490                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12491                                 break;
12492                         case DRM_PLANE_TYPE_OVERLAY:
12493                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12494                                 break;
12495                         }
12496
12497                         mutex_lock(&dev->struct_mutex);
12498                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12499                         mutex_unlock(&dev->struct_mutex);
12500                 }
12501         }
12502
12503         if (intel_crtc->atomic.wait_for_flips)
12504                 intel_crtc_wait_for_pending_flips(crtc);
12505
12506         if (intel_crtc->atomic.disable_fbc)
12507                 intel_fbc_disable(dev);
12508
12509         if (intel_crtc->atomic.pre_disable_primary)
12510                 intel_pre_disable_primary(crtc);
12511
12512         if (intel_crtc->atomic.update_wm)
12513                 intel_update_watermarks(crtc);
12514
12515         intel_runtime_pm_get(dev_priv);
12516
12517         /* Perform vblank evasion around commit operation */
12518         if (intel_crtc->active)
12519                 intel_crtc->atomic.evade =
12520                         intel_pipe_update_start(intel_crtc,
12521                                                 &intel_crtc->atomic.start_vbl_count);
12522 }
12523
12524 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12525 {
12526         struct drm_device *dev = crtc->dev;
12527         struct drm_i915_private *dev_priv = dev->dev_private;
12528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12529         struct drm_plane *p;
12530
12531         if (intel_crtc->atomic.evade)
12532                 intel_pipe_update_end(intel_crtc,
12533                                       intel_crtc->atomic.start_vbl_count);
12534
12535         intel_runtime_pm_put(dev_priv);
12536
12537         if (intel_crtc->atomic.wait_vblank)
12538                 intel_wait_for_vblank(dev, intel_crtc->pipe);
12539
12540         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12541
12542         if (intel_crtc->atomic.update_fbc) {
12543                 mutex_lock(&dev->struct_mutex);
12544                 intel_fbc_update(dev);
12545                 mutex_unlock(&dev->struct_mutex);
12546         }
12547
12548         if (intel_crtc->atomic.post_enable_primary)
12549                 intel_post_enable_primary(crtc);
12550
12551         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12552                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12553                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12554                                                        false, false);
12555
12556         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12557 }
12558
12559 /**
12560  * intel_plane_destroy - destroy a plane
12561  * @plane: plane to destroy
12562  *
12563  * Common destruction function for all types of planes (primary, cursor,
12564  * sprite).
12565  */
12566 void intel_plane_destroy(struct drm_plane *plane)
12567 {
12568         struct intel_plane *intel_plane = to_intel_plane(plane);
12569         drm_plane_cleanup(plane);
12570         kfree(intel_plane);
12571 }
12572
12573 const struct drm_plane_funcs intel_plane_funcs = {
12574         .update_plane = drm_plane_helper_update,
12575         .disable_plane = drm_plane_helper_disable,
12576         .destroy = intel_plane_destroy,
12577         .set_property = drm_atomic_helper_plane_set_property,
12578         .atomic_get_property = intel_plane_atomic_get_property,
12579         .atomic_set_property = intel_plane_atomic_set_property,
12580         .atomic_duplicate_state = intel_plane_duplicate_state,
12581         .atomic_destroy_state = intel_plane_destroy_state,
12582
12583 };
12584
12585 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12586                                                     int pipe)
12587 {
12588         struct intel_plane *primary;
12589         struct intel_plane_state *state;
12590         const uint32_t *intel_primary_formats;
12591         int num_formats;
12592
12593         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12594         if (primary == NULL)
12595                 return NULL;
12596
12597         state = intel_create_plane_state(&primary->base);
12598         if (!state) {
12599                 kfree(primary);
12600                 return NULL;
12601         }
12602         primary->base.state = &state->base;
12603
12604         primary->can_scale = false;
12605         primary->max_downscale = 1;
12606         primary->pipe = pipe;
12607         primary->plane = pipe;
12608         primary->check_plane = intel_check_primary_plane;
12609         primary->commit_plane = intel_commit_primary_plane;
12610         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12611                 primary->plane = !pipe;
12612
12613         if (INTEL_INFO(dev)->gen <= 3) {
12614                 intel_primary_formats = intel_primary_formats_gen2;
12615                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12616         } else {
12617                 intel_primary_formats = intel_primary_formats_gen4;
12618                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12619         }
12620
12621         drm_universal_plane_init(dev, &primary->base, 0,
12622                                  &intel_plane_funcs,
12623                                  intel_primary_formats, num_formats,
12624                                  DRM_PLANE_TYPE_PRIMARY);
12625
12626         if (INTEL_INFO(dev)->gen >= 4) {
12627                 if (!dev->mode_config.rotation_property)
12628                         dev->mode_config.rotation_property =
12629                                 drm_mode_create_rotation_property(dev,
12630                                                         BIT(DRM_ROTATE_0) |
12631                                                         BIT(DRM_ROTATE_180));
12632                 if (dev->mode_config.rotation_property)
12633                         drm_object_attach_property(&primary->base.base,
12634                                 dev->mode_config.rotation_property,
12635                                 state->base.rotation);
12636         }
12637
12638         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12639
12640         return &primary->base;
12641 }
12642
12643 static int
12644 intel_check_cursor_plane(struct drm_plane *plane,
12645                          struct intel_plane_state *state)
12646 {
12647         struct drm_crtc *crtc = state->base.crtc;
12648         struct drm_device *dev = plane->dev;
12649         struct drm_framebuffer *fb = state->base.fb;
12650         struct drm_rect *dest = &state->dst;
12651         struct drm_rect *src = &state->src;
12652         const struct drm_rect *clip = &state->clip;
12653         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12654         struct intel_crtc *intel_crtc;
12655         unsigned stride;
12656         int ret;
12657
12658         crtc = crtc ? crtc : plane->crtc;
12659         intel_crtc = to_intel_crtc(crtc);
12660
12661         ret = drm_plane_helper_check_update(plane, crtc, fb,
12662                                             src, dest, clip,
12663                                             DRM_PLANE_HELPER_NO_SCALING,
12664                                             DRM_PLANE_HELPER_NO_SCALING,
12665                                             true, true, &state->visible);
12666         if (ret)
12667                 return ret;
12668
12669
12670         /* if we want to turn off the cursor ignore width and height */
12671         if (!obj)
12672                 goto finish;
12673
12674         /* Check for which cursor types we support */
12675         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12676                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12677                           state->base.crtc_w, state->base.crtc_h);
12678                 return -EINVAL;
12679         }
12680
12681         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12682         if (obj->base.size < stride * state->base.crtc_h) {
12683                 DRM_DEBUG_KMS("buffer is too small\n");
12684                 return -ENOMEM;
12685         }
12686
12687         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12688                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12689                 ret = -EINVAL;
12690         }
12691
12692 finish:
12693         if (intel_crtc->active) {
12694                 if (plane->state->crtc_w != state->base.crtc_w)
12695                         intel_crtc->atomic.update_wm = true;
12696
12697                 intel_crtc->atomic.fb_bits |=
12698                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12699         }
12700
12701         return ret;
12702 }
12703
12704 static void
12705 intel_commit_cursor_plane(struct drm_plane *plane,
12706                           struct intel_plane_state *state)
12707 {
12708         struct drm_crtc *crtc = state->base.crtc;
12709         struct drm_device *dev = plane->dev;
12710         struct intel_crtc *intel_crtc;
12711         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12712         uint32_t addr;
12713
12714         crtc = crtc ? crtc : plane->crtc;
12715         intel_crtc = to_intel_crtc(crtc);
12716
12717         plane->fb = state->base.fb;
12718         crtc->cursor_x = state->base.crtc_x;
12719         crtc->cursor_y = state->base.crtc_y;
12720
12721         if (intel_crtc->cursor_bo == obj)
12722                 goto update;
12723
12724         if (!obj)
12725                 addr = 0;
12726         else if (!INTEL_INFO(dev)->cursor_needs_physical)
12727                 addr = i915_gem_obj_ggtt_offset(obj);
12728         else
12729                 addr = obj->phys_handle->busaddr;
12730
12731         intel_crtc->cursor_addr = addr;
12732         intel_crtc->cursor_bo = obj;
12733 update:
12734
12735         if (intel_crtc->active)
12736                 intel_crtc_update_cursor(crtc, state->visible);
12737 }
12738
12739 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12740                                                    int pipe)
12741 {
12742         struct intel_plane *cursor;
12743         struct intel_plane_state *state;
12744
12745         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12746         if (cursor == NULL)
12747                 return NULL;
12748
12749         state = intel_create_plane_state(&cursor->base);
12750         if (!state) {
12751                 kfree(cursor);
12752                 return NULL;
12753         }
12754         cursor->base.state = &state->base;
12755
12756         cursor->can_scale = false;
12757         cursor->max_downscale = 1;
12758         cursor->pipe = pipe;
12759         cursor->plane = pipe;
12760         cursor->check_plane = intel_check_cursor_plane;
12761         cursor->commit_plane = intel_commit_cursor_plane;
12762
12763         drm_universal_plane_init(dev, &cursor->base, 0,
12764                                  &intel_plane_funcs,
12765                                  intel_cursor_formats,
12766                                  ARRAY_SIZE(intel_cursor_formats),
12767                                  DRM_PLANE_TYPE_CURSOR);
12768
12769         if (INTEL_INFO(dev)->gen >= 4) {
12770                 if (!dev->mode_config.rotation_property)
12771                         dev->mode_config.rotation_property =
12772                                 drm_mode_create_rotation_property(dev,
12773                                                         BIT(DRM_ROTATE_0) |
12774                                                         BIT(DRM_ROTATE_180));
12775                 if (dev->mode_config.rotation_property)
12776                         drm_object_attach_property(&cursor->base.base,
12777                                 dev->mode_config.rotation_property,
12778                                 state->base.rotation);
12779         }
12780
12781         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12782
12783         return &cursor->base;
12784 }
12785
12786 static void intel_crtc_init(struct drm_device *dev, int pipe)
12787 {
12788         struct drm_i915_private *dev_priv = dev->dev_private;
12789         struct intel_crtc *intel_crtc;
12790         struct intel_crtc_state *crtc_state = NULL;
12791         struct drm_plane *primary = NULL;
12792         struct drm_plane *cursor = NULL;
12793         int i, ret;
12794
12795         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12796         if (intel_crtc == NULL)
12797                 return;
12798
12799         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12800         if (!crtc_state)
12801                 goto fail;
12802         intel_crtc_set_state(intel_crtc, crtc_state);
12803         crtc_state->base.crtc = &intel_crtc->base;
12804
12805         primary = intel_primary_plane_create(dev, pipe);
12806         if (!primary)
12807                 goto fail;
12808
12809         cursor = intel_cursor_plane_create(dev, pipe);
12810         if (!cursor)
12811                 goto fail;
12812
12813         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12814                                         cursor, &intel_crtc_funcs);
12815         if (ret)
12816                 goto fail;
12817
12818         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12819         for (i = 0; i < 256; i++) {
12820                 intel_crtc->lut_r[i] = i;
12821                 intel_crtc->lut_g[i] = i;
12822                 intel_crtc->lut_b[i] = i;
12823         }
12824
12825         /*
12826          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12827          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12828          */
12829         intel_crtc->pipe = pipe;
12830         intel_crtc->plane = pipe;
12831         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12832                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12833                 intel_crtc->plane = !pipe;
12834         }
12835
12836         intel_crtc->cursor_base = ~0;
12837         intel_crtc->cursor_cntl = ~0;
12838         intel_crtc->cursor_size = ~0;
12839
12840         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12841                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12842         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12843         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12844
12845         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12846
12847         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12848
12849         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12850         return;
12851
12852 fail:
12853         if (primary)
12854                 drm_plane_cleanup(primary);
12855         if (cursor)
12856                 drm_plane_cleanup(cursor);
12857         kfree(crtc_state);
12858         kfree(intel_crtc);
12859 }
12860
12861 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12862 {
12863         struct drm_encoder *encoder = connector->base.encoder;
12864         struct drm_device *dev = connector->base.dev;
12865
12866         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12867
12868         if (!encoder || WARN_ON(!encoder->crtc))
12869                 return INVALID_PIPE;
12870
12871         return to_intel_crtc(encoder->crtc)->pipe;
12872 }
12873
12874 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12875                                 struct drm_file *file)
12876 {
12877         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12878         struct drm_crtc *drmmode_crtc;
12879         struct intel_crtc *crtc;
12880
12881         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12882
12883         if (!drmmode_crtc) {
12884                 DRM_ERROR("no such CRTC id\n");
12885                 return -ENOENT;
12886         }
12887
12888         crtc = to_intel_crtc(drmmode_crtc);
12889         pipe_from_crtc_id->pipe = crtc->pipe;
12890
12891         return 0;
12892 }
12893
12894 static int intel_encoder_clones(struct intel_encoder *encoder)
12895 {
12896         struct drm_device *dev = encoder->base.dev;
12897         struct intel_encoder *source_encoder;
12898         int index_mask = 0;
12899         int entry = 0;
12900
12901         for_each_intel_encoder(dev, source_encoder) {
12902                 if (encoders_cloneable(encoder, source_encoder))
12903                         index_mask |= (1 << entry);
12904
12905                 entry++;
12906         }
12907
12908         return index_mask;
12909 }
12910
12911 static bool has_edp_a(struct drm_device *dev)
12912 {
12913         struct drm_i915_private *dev_priv = dev->dev_private;
12914
12915         if (!IS_MOBILE(dev))
12916                 return false;
12917
12918         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12919                 return false;
12920
12921         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12922                 return false;
12923
12924         return true;
12925 }
12926
12927 static bool intel_crt_present(struct drm_device *dev)
12928 {
12929         struct drm_i915_private *dev_priv = dev->dev_private;
12930
12931         if (INTEL_INFO(dev)->gen >= 9)
12932                 return false;
12933
12934         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12935                 return false;
12936
12937         if (IS_CHERRYVIEW(dev))
12938                 return false;
12939
12940         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12941                 return false;
12942
12943         return true;
12944 }
12945
12946 static void intel_setup_outputs(struct drm_device *dev)
12947 {
12948         struct drm_i915_private *dev_priv = dev->dev_private;
12949         struct intel_encoder *encoder;
12950         struct drm_connector *connector;
12951         bool dpd_is_edp = false;
12952
12953         intel_lvds_init(dev);
12954
12955         if (intel_crt_present(dev))
12956                 intel_crt_init(dev);
12957
12958         if (HAS_DDI(dev)) {
12959                 int found;
12960
12961                 /*
12962                  * Haswell uses DDI functions to detect digital outputs.
12963                  * On SKL pre-D0 the strap isn't connected, so we assume
12964                  * it's there.
12965                  */
12966                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12967                 /* WaIgnoreDDIAStrap: skl */
12968                 if (found ||
12969                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12970                         intel_ddi_init(dev, PORT_A);
12971
12972                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12973                  * register */
12974                 found = I915_READ(SFUSE_STRAP);
12975
12976                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12977                         intel_ddi_init(dev, PORT_B);
12978                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12979                         intel_ddi_init(dev, PORT_C);
12980                 if (found & SFUSE_STRAP_DDID_DETECTED)
12981                         intel_ddi_init(dev, PORT_D);
12982         } else if (HAS_PCH_SPLIT(dev)) {
12983                 int found;
12984                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12985
12986                 if (has_edp_a(dev))
12987                         intel_dp_init(dev, DP_A, PORT_A);
12988
12989                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12990                         /* PCH SDVOB multiplex with HDMIB */
12991                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12992                         if (!found)
12993                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12994                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12995                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12996                 }
12997
12998                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12999                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13000
13001                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13002                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13003
13004                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13005                         intel_dp_init(dev, PCH_DP_C, PORT_C);
13006
13007                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13008                         intel_dp_init(dev, PCH_DP_D, PORT_D);
13009         } else if (IS_VALLEYVIEW(dev)) {
13010                 /*
13011                  * The DP_DETECTED bit is the latched state of the DDC
13012                  * SDA pin at boot. However since eDP doesn't require DDC
13013                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
13014                  * eDP ports may have been muxed to an alternate function.
13015                  * Thus we can't rely on the DP_DETECTED bit alone to detect
13016                  * eDP ports. Consult the VBT as well as DP_DETECTED to
13017                  * detect eDP ports.
13018                  */
13019                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13020                     !intel_dp_is_edp(dev, PORT_B))
13021                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13022                                         PORT_B);
13023                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13024                     intel_dp_is_edp(dev, PORT_B))
13025                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13026
13027                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13028                     !intel_dp_is_edp(dev, PORT_C))
13029                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13030                                         PORT_C);
13031                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13032                     intel_dp_is_edp(dev, PORT_C))
13033                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13034
13035                 if (IS_CHERRYVIEW(dev)) {
13036                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13037                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13038                                                 PORT_D);
13039                         /* eDP not supported on port D, so don't check VBT */
13040                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13041                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13042                 }
13043
13044                 intel_dsi_init(dev);
13045         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13046                 bool found = false;
13047
13048                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13049                         DRM_DEBUG_KMS("probing SDVOB\n");
13050                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13051                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13052                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13053                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13054                         }
13055
13056                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
13057                                 intel_dp_init(dev, DP_B, PORT_B);
13058                 }
13059
13060                 /* Before G4X SDVOC doesn't have its own detect register */
13061
13062                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13063                         DRM_DEBUG_KMS("probing SDVOC\n");
13064                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13065                 }
13066
13067                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13068
13069                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13070                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13071                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13072                         }
13073                         if (SUPPORTS_INTEGRATED_DP(dev))
13074                                 intel_dp_init(dev, DP_C, PORT_C);
13075                 }
13076
13077                 if (SUPPORTS_INTEGRATED_DP(dev) &&
13078                     (I915_READ(DP_D) & DP_DETECTED))
13079                         intel_dp_init(dev, DP_D, PORT_D);
13080         } else if (IS_GEN2(dev))
13081                 intel_dvo_init(dev);
13082
13083         if (SUPPORTS_TV(dev))
13084                 intel_tv_init(dev);
13085
13086         /*
13087          * FIXME:  We don't have full atomic support yet, but we want to be
13088          * able to enable/test plane updates via the atomic interface in the
13089          * meantime.  However as soon as we flip DRIVER_ATOMIC on, the DRM core
13090          * will take some atomic codepaths to lookup properties during
13091          * drmModeGetConnector() that unconditionally dereference
13092          * connector->state.
13093          *
13094          * We create a dummy connector state here for each connector to ensure
13095          * the DRM core doesn't try to dereference a NULL connector->state.
13096          * The actual connector properties will never be updated or contain
13097          * useful information, but since we're doing this specifically for
13098          * testing/debug of the plane operations (and only when a specific
13099          * kernel module option is given), that shouldn't really matter.
13100          *
13101          * We are also relying on these states to convert the legacy mode set
13102          * to use a drm_atomic_state struct. The states are kept consistent
13103          * with actual state, so that it is safe to rely on that instead of
13104          * the staged config.
13105          *
13106          * Once atomic support for crtc's + connectors lands, this loop should
13107          * be removed since we'll be setting up real connector state, which
13108          * will contain Intel-specific properties.
13109          */
13110         list_for_each_entry(connector,
13111                             &dev->mode_config.connector_list,
13112                             head) {
13113                 if (!WARN_ON(connector->state)) {
13114                         connector->state = kzalloc(sizeof(*connector->state),
13115                                                    GFP_KERNEL);
13116                 }
13117         }
13118
13119         intel_psr_init(dev);
13120
13121         for_each_intel_encoder(dev, encoder) {
13122                 encoder->base.possible_crtcs = encoder->crtc_mask;
13123                 encoder->base.possible_clones =
13124                         intel_encoder_clones(encoder);
13125         }
13126
13127         intel_init_pch_refclk(dev);
13128
13129         drm_helper_move_panel_connectors_to_head(dev);
13130 }
13131
13132 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13133 {
13134         struct drm_device *dev = fb->dev;
13135         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13136
13137         drm_framebuffer_cleanup(fb);
13138         mutex_lock(&dev->struct_mutex);
13139         WARN_ON(!intel_fb->obj->framebuffer_references--);
13140         drm_gem_object_unreference(&intel_fb->obj->base);
13141         mutex_unlock(&dev->struct_mutex);
13142         kfree(intel_fb);
13143 }
13144
13145 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13146                                                 struct drm_file *file,
13147                                                 unsigned int *handle)
13148 {
13149         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13150         struct drm_i915_gem_object *obj = intel_fb->obj;
13151
13152         return drm_gem_handle_create(file, &obj->base, handle);
13153 }
13154
13155 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13156         .destroy = intel_user_framebuffer_destroy,
13157         .create_handle = intel_user_framebuffer_create_handle,
13158 };
13159
13160 static
13161 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13162                          uint32_t pixel_format)
13163 {
13164         u32 gen = INTEL_INFO(dev)->gen;
13165
13166         if (gen >= 9) {
13167                 /* "The stride in bytes must not exceed the of the size of 8K
13168                  *  pixels and 32K bytes."
13169                  */
13170                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13171         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13172                 return 32*1024;
13173         } else if (gen >= 4) {
13174                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13175                         return 16*1024;
13176                 else
13177                         return 32*1024;
13178         } else if (gen >= 3) {
13179                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13180                         return 8*1024;
13181                 else
13182                         return 16*1024;
13183         } else {
13184                 /* XXX DSPC is limited to 4k tiled */
13185                 return 8*1024;
13186         }
13187 }
13188
13189 static int intel_framebuffer_init(struct drm_device *dev,
13190                                   struct intel_framebuffer *intel_fb,
13191                                   struct drm_mode_fb_cmd2 *mode_cmd,
13192                                   struct drm_i915_gem_object *obj)
13193 {
13194         unsigned int aligned_height;
13195         int ret;
13196         u32 pitch_limit, stride_alignment;
13197
13198         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13199
13200         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13201                 /* Enforce that fb modifier and tiling mode match, but only for
13202                  * X-tiled. This is needed for FBC. */
13203                 if (!!(obj->tiling_mode == I915_TILING_X) !=
13204                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13205                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13206                         return -EINVAL;
13207                 }
13208         } else {
13209                 if (obj->tiling_mode == I915_TILING_X)
13210                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13211                 else if (obj->tiling_mode == I915_TILING_Y) {
13212                         DRM_DEBUG("No Y tiling for legacy addfb\n");
13213                         return -EINVAL;
13214                 }
13215         }
13216
13217         /* Passed in modifier sanity checking. */
13218         switch (mode_cmd->modifier[0]) {
13219         case I915_FORMAT_MOD_Y_TILED:
13220         case I915_FORMAT_MOD_Yf_TILED:
13221                 if (INTEL_INFO(dev)->gen < 9) {
13222                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13223                                   mode_cmd->modifier[0]);
13224                         return -EINVAL;
13225                 }
13226         case DRM_FORMAT_MOD_NONE:
13227         case I915_FORMAT_MOD_X_TILED:
13228                 break;
13229         default:
13230                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13231                           mode_cmd->modifier[0]);
13232                 return -EINVAL;
13233         }
13234
13235         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13236                                                      mode_cmd->pixel_format);
13237         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13238                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13239                           mode_cmd->pitches[0], stride_alignment);
13240                 return -EINVAL;
13241         }
13242
13243         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13244                                            mode_cmd->pixel_format);
13245         if (mode_cmd->pitches[0] > pitch_limit) {
13246                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13247                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13248                           "tiled" : "linear",
13249                           mode_cmd->pitches[0], pitch_limit);
13250                 return -EINVAL;
13251         }
13252
13253         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13254             mode_cmd->pitches[0] != obj->stride) {
13255                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13256                           mode_cmd->pitches[0], obj->stride);
13257                 return -EINVAL;
13258         }
13259
13260         /* Reject formats not supported by any plane early. */
13261         switch (mode_cmd->pixel_format) {
13262         case DRM_FORMAT_C8:
13263         case DRM_FORMAT_RGB565:
13264         case DRM_FORMAT_XRGB8888:
13265         case DRM_FORMAT_ARGB8888:
13266                 break;
13267         case DRM_FORMAT_XRGB1555:
13268         case DRM_FORMAT_ARGB1555:
13269                 if (INTEL_INFO(dev)->gen > 3) {
13270                         DRM_DEBUG("unsupported pixel format: %s\n",
13271                                   drm_get_format_name(mode_cmd->pixel_format));
13272                         return -EINVAL;
13273                 }
13274                 break;
13275         case DRM_FORMAT_XBGR8888:
13276         case DRM_FORMAT_ABGR8888:
13277         case DRM_FORMAT_XRGB2101010:
13278         case DRM_FORMAT_ARGB2101010:
13279         case DRM_FORMAT_XBGR2101010:
13280         case DRM_FORMAT_ABGR2101010:
13281                 if (INTEL_INFO(dev)->gen < 4) {
13282                         DRM_DEBUG("unsupported pixel format: %s\n",
13283                                   drm_get_format_name(mode_cmd->pixel_format));
13284                         return -EINVAL;
13285                 }
13286                 break;
13287         case DRM_FORMAT_YUYV:
13288         case DRM_FORMAT_UYVY:
13289         case DRM_FORMAT_YVYU:
13290         case DRM_FORMAT_VYUY:
13291                 if (INTEL_INFO(dev)->gen < 5) {
13292                         DRM_DEBUG("unsupported pixel format: %s\n",
13293                                   drm_get_format_name(mode_cmd->pixel_format));
13294                         return -EINVAL;
13295                 }
13296                 break;
13297         default:
13298                 DRM_DEBUG("unsupported pixel format: %s\n",
13299                           drm_get_format_name(mode_cmd->pixel_format));
13300                 return -EINVAL;
13301         }
13302
13303         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13304         if (mode_cmd->offsets[0] != 0)
13305                 return -EINVAL;
13306
13307         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13308                                                mode_cmd->pixel_format,
13309                                                mode_cmd->modifier[0]);
13310         /* FIXME drm helper for size checks (especially planar formats)? */
13311         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13312                 return -EINVAL;
13313
13314         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13315         intel_fb->obj = obj;
13316         intel_fb->obj->framebuffer_references++;
13317
13318         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13319         if (ret) {
13320                 DRM_ERROR("framebuffer init failed %d\n", ret);
13321                 return ret;
13322         }
13323
13324         return 0;
13325 }
13326
13327 static struct drm_framebuffer *
13328 intel_user_framebuffer_create(struct drm_device *dev,
13329                               struct drm_file *filp,
13330                               struct drm_mode_fb_cmd2 *mode_cmd)
13331 {
13332         struct drm_i915_gem_object *obj;
13333
13334         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13335                                                 mode_cmd->handles[0]));
13336         if (&obj->base == NULL)
13337                 return ERR_PTR(-ENOENT);
13338
13339         return intel_framebuffer_create(dev, mode_cmd, obj);
13340 }
13341
13342 #ifndef CONFIG_DRM_I915_FBDEV
13343 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13344 {
13345 }
13346 #endif
13347
13348 static const struct drm_mode_config_funcs intel_mode_funcs = {
13349         .fb_create = intel_user_framebuffer_create,
13350         .output_poll_changed = intel_fbdev_output_poll_changed,
13351         .atomic_check = intel_atomic_check,
13352         .atomic_commit = intel_atomic_commit,
13353 };
13354
13355 /* Set up chip specific display functions */
13356 static void intel_init_display(struct drm_device *dev)
13357 {
13358         struct drm_i915_private *dev_priv = dev->dev_private;
13359
13360         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13361                 dev_priv->display.find_dpll = g4x_find_best_dpll;
13362         else if (IS_CHERRYVIEW(dev))
13363                 dev_priv->display.find_dpll = chv_find_best_dpll;
13364         else if (IS_VALLEYVIEW(dev))
13365                 dev_priv->display.find_dpll = vlv_find_best_dpll;
13366         else if (IS_PINEVIEW(dev))
13367                 dev_priv->display.find_dpll = pnv_find_best_dpll;
13368         else
13369                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13370
13371         if (INTEL_INFO(dev)->gen >= 9) {
13372                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13373                 dev_priv->display.get_initial_plane_config =
13374                         skylake_get_initial_plane_config;
13375                 dev_priv->display.crtc_compute_clock =
13376                         haswell_crtc_compute_clock;
13377                 dev_priv->display.crtc_enable = haswell_crtc_enable;
13378                 dev_priv->display.crtc_disable = haswell_crtc_disable;
13379                 dev_priv->display.off = ironlake_crtc_off;
13380                 dev_priv->display.update_primary_plane =
13381                         skylake_update_primary_plane;
13382         } else if (HAS_DDI(dev)) {
13383                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13384                 dev_priv->display.get_initial_plane_config =
13385                         ironlake_get_initial_plane_config;
13386                 dev_priv->display.crtc_compute_clock =
13387                         haswell_crtc_compute_clock;
13388                 dev_priv->display.crtc_enable = haswell_crtc_enable;
13389                 dev_priv->display.crtc_disable = haswell_crtc_disable;
13390                 dev_priv->display.off = ironlake_crtc_off;
13391                 dev_priv->display.update_primary_plane =
13392                         ironlake_update_primary_plane;
13393         } else if (HAS_PCH_SPLIT(dev)) {
13394                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13395                 dev_priv->display.get_initial_plane_config =
13396                         ironlake_get_initial_plane_config;
13397                 dev_priv->display.crtc_compute_clock =
13398                         ironlake_crtc_compute_clock;
13399                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13400                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13401                 dev_priv->display.off = ironlake_crtc_off;
13402                 dev_priv->display.update_primary_plane =
13403                         ironlake_update_primary_plane;
13404         } else if (IS_VALLEYVIEW(dev)) {
13405                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13406                 dev_priv->display.get_initial_plane_config =
13407                         i9xx_get_initial_plane_config;
13408                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13409                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13410                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13411                 dev_priv->display.off = i9xx_crtc_off;
13412                 dev_priv->display.update_primary_plane =
13413                         i9xx_update_primary_plane;
13414         } else {
13415                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13416                 dev_priv->display.get_initial_plane_config =
13417                         i9xx_get_initial_plane_config;
13418                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13419                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13420                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13421                 dev_priv->display.off = i9xx_crtc_off;
13422                 dev_priv->display.update_primary_plane =
13423                         i9xx_update_primary_plane;
13424         }
13425
13426         /* Returns the core display clock speed */
13427         if (IS_VALLEYVIEW(dev))
13428                 dev_priv->display.get_display_clock_speed =
13429                         valleyview_get_display_clock_speed;
13430         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13431                 dev_priv->display.get_display_clock_speed =
13432                         i945_get_display_clock_speed;
13433         else if (IS_I915G(dev))
13434                 dev_priv->display.get_display_clock_speed =
13435                         i915_get_display_clock_speed;
13436         else if (IS_I945GM(dev) || IS_845G(dev))
13437                 dev_priv->display.get_display_clock_speed =
13438                         i9xx_misc_get_display_clock_speed;
13439         else if (IS_PINEVIEW(dev))
13440                 dev_priv->display.get_display_clock_speed =
13441                         pnv_get_display_clock_speed;
13442         else if (IS_I915GM(dev))
13443                 dev_priv->display.get_display_clock_speed =
13444                         i915gm_get_display_clock_speed;
13445         else if (IS_I865G(dev))
13446                 dev_priv->display.get_display_clock_speed =
13447                         i865_get_display_clock_speed;
13448         else if (IS_I85X(dev))
13449                 dev_priv->display.get_display_clock_speed =
13450                         i855_get_display_clock_speed;
13451         else /* 852, 830 */
13452                 dev_priv->display.get_display_clock_speed =
13453                         i830_get_display_clock_speed;
13454
13455         if (IS_GEN5(dev)) {
13456                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13457         } else if (IS_GEN6(dev)) {
13458                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13459         } else if (IS_IVYBRIDGE(dev)) {
13460                 /* FIXME: detect B0+ stepping and use auto training */
13461                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13462         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13463                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13464         } else if (IS_VALLEYVIEW(dev)) {
13465                 dev_priv->display.modeset_global_resources =
13466                         valleyview_modeset_global_resources;
13467         }
13468
13469         switch (INTEL_INFO(dev)->gen) {
13470         case 2:
13471                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13472                 break;
13473
13474         case 3:
13475                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13476                 break;
13477
13478         case 4:
13479         case 5:
13480                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13481                 break;
13482
13483         case 6:
13484                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13485                 break;
13486         case 7:
13487         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13488                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13489                 break;
13490         case 9:
13491                 /* Drop through - unsupported since execlist only. */
13492         default:
13493                 /* Default just returns -ENODEV to indicate unsupported */
13494                 dev_priv->display.queue_flip = intel_default_queue_flip;
13495         }
13496
13497         intel_panel_init_backlight_funcs(dev);
13498
13499         mutex_init(&dev_priv->pps_mutex);
13500 }
13501
13502 /*
13503  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13504  * resume, or other times.  This quirk makes sure that's the case for
13505  * affected systems.
13506  */
13507 static void quirk_pipea_force(struct drm_device *dev)
13508 {
13509         struct drm_i915_private *dev_priv = dev->dev_private;
13510
13511         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13512         DRM_INFO("applying pipe a force quirk\n");
13513 }
13514
13515 static void quirk_pipeb_force(struct drm_device *dev)
13516 {
13517         struct drm_i915_private *dev_priv = dev->dev_private;
13518
13519         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13520         DRM_INFO("applying pipe b force quirk\n");
13521 }
13522
13523 /*
13524  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13525  */
13526 static void quirk_ssc_force_disable(struct drm_device *dev)
13527 {
13528         struct drm_i915_private *dev_priv = dev->dev_private;
13529         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13530         DRM_INFO("applying lvds SSC disable quirk\n");
13531 }
13532
13533 /*
13534  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13535  * brightness value
13536  */
13537 static void quirk_invert_brightness(struct drm_device *dev)
13538 {
13539         struct drm_i915_private *dev_priv = dev->dev_private;
13540         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13541         DRM_INFO("applying inverted panel brightness quirk\n");
13542 }
13543
13544 /* Some VBT's incorrectly indicate no backlight is present */
13545 static void quirk_backlight_present(struct drm_device *dev)
13546 {
13547         struct drm_i915_private *dev_priv = dev->dev_private;
13548         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13549         DRM_INFO("applying backlight present quirk\n");
13550 }
13551
13552 struct intel_quirk {
13553         int device;
13554         int subsystem_vendor;
13555         int subsystem_device;
13556         void (*hook)(struct drm_device *dev);
13557 };
13558
13559 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13560 struct intel_dmi_quirk {
13561         void (*hook)(struct drm_device *dev);
13562         const struct dmi_system_id (*dmi_id_list)[];
13563 };
13564
13565 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13566 {
13567         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13568         return 1;
13569 }
13570
13571 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13572         {
13573                 .dmi_id_list = &(const struct dmi_system_id[]) {
13574                         {
13575                                 .callback = intel_dmi_reverse_brightness,
13576                                 .ident = "NCR Corporation",
13577                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13578                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
13579                                 },
13580                         },
13581                         { }  /* terminating entry */
13582                 },
13583                 .hook = quirk_invert_brightness,
13584         },
13585 };
13586
13587 static struct intel_quirk intel_quirks[] = {
13588         /* HP Mini needs pipe A force quirk (LP: #322104) */
13589         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13590
13591         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13592         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13593
13594         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13595         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13596
13597         /* 830 needs to leave pipe A & dpll A up */
13598         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13599
13600         /* 830 needs to leave pipe B & dpll B up */
13601         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13602
13603         /* Lenovo U160 cannot use SSC on LVDS */
13604         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13605
13606         /* Sony Vaio Y cannot use SSC on LVDS */
13607         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13608
13609         /* Acer Aspire 5734Z must invert backlight brightness */
13610         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13611
13612         /* Acer/eMachines G725 */
13613         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13614
13615         /* Acer/eMachines e725 */
13616         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13617
13618         /* Acer/Packard Bell NCL20 */
13619         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13620
13621         /* Acer Aspire 4736Z */
13622         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13623
13624         /* Acer Aspire 5336 */
13625         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13626
13627         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13628         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13629
13630         /* Acer C720 Chromebook (Core i3 4005U) */
13631         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13632
13633         /* Apple Macbook 2,1 (Core 2 T7400) */
13634         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13635
13636         /* Toshiba CB35 Chromebook (Celeron 2955U) */
13637         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13638
13639         /* HP Chromebook 14 (Celeron 2955U) */
13640         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13641
13642         /* Dell Chromebook 11 */
13643         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13644 };
13645
13646 static void intel_init_quirks(struct drm_device *dev)
13647 {
13648         struct pci_dev *d = dev->pdev;
13649         int i;
13650
13651         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13652                 struct intel_quirk *q = &intel_quirks[i];
13653
13654                 if (d->device == q->device &&
13655                     (d->subsystem_vendor == q->subsystem_vendor ||
13656                      q->subsystem_vendor == PCI_ANY_ID) &&
13657                     (d->subsystem_device == q->subsystem_device ||
13658                      q->subsystem_device == PCI_ANY_ID))
13659                         q->hook(dev);
13660         }
13661         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13662                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13663                         intel_dmi_quirks[i].hook(dev);
13664         }
13665 }
13666
13667 /* Disable the VGA plane that we never use */
13668 static void i915_disable_vga(struct drm_device *dev)
13669 {
13670         struct drm_i915_private *dev_priv = dev->dev_private;
13671         u8 sr1;
13672         u32 vga_reg = i915_vgacntrl_reg(dev);
13673
13674         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13675         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13676         outb(SR01, VGA_SR_INDEX);
13677         sr1 = inb(VGA_SR_DATA);
13678         outb(sr1 | 1<<5, VGA_SR_DATA);
13679         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13680         udelay(300);
13681
13682         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13683         POSTING_READ(vga_reg);
13684 }
13685
13686 void intel_modeset_init_hw(struct drm_device *dev)
13687 {
13688         intel_prepare_ddi(dev);
13689
13690         if (IS_VALLEYVIEW(dev))
13691                 vlv_update_cdclk(dev);
13692
13693         intel_init_clock_gating(dev);
13694
13695         intel_enable_gt_powersave(dev);
13696 }
13697
13698 void intel_modeset_init(struct drm_device *dev)
13699 {
13700         struct drm_i915_private *dev_priv = dev->dev_private;
13701         int sprite, ret;
13702         enum pipe pipe;
13703         struct intel_crtc *crtc;
13704
13705         drm_mode_config_init(dev);
13706
13707         dev->mode_config.min_width = 0;
13708         dev->mode_config.min_height = 0;
13709
13710         dev->mode_config.preferred_depth = 24;
13711         dev->mode_config.prefer_shadow = 1;
13712
13713         dev->mode_config.allow_fb_modifiers = true;
13714
13715         dev->mode_config.funcs = &intel_mode_funcs;
13716
13717         intel_init_quirks(dev);
13718
13719         intel_init_pm(dev);
13720
13721         if (INTEL_INFO(dev)->num_pipes == 0)
13722                 return;
13723
13724         intel_init_display(dev);
13725         intel_init_audio(dev);
13726
13727         if (IS_GEN2(dev)) {
13728                 dev->mode_config.max_width = 2048;
13729                 dev->mode_config.max_height = 2048;
13730         } else if (IS_GEN3(dev)) {
13731                 dev->mode_config.max_width = 4096;
13732                 dev->mode_config.max_height = 4096;
13733         } else {
13734                 dev->mode_config.max_width = 8192;
13735                 dev->mode_config.max_height = 8192;
13736         }
13737
13738         if (IS_845G(dev) || IS_I865G(dev)) {
13739                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13740                 dev->mode_config.cursor_height = 1023;
13741         } else if (IS_GEN2(dev)) {
13742                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13743                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13744         } else {
13745                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13746                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13747         }
13748
13749         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13750
13751         DRM_DEBUG_KMS("%d display pipe%s available.\n",
13752                       INTEL_INFO(dev)->num_pipes,
13753                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13754
13755         for_each_pipe(dev_priv, pipe) {
13756                 intel_crtc_init(dev, pipe);
13757                 for_each_sprite(dev_priv, pipe, sprite) {
13758                         ret = intel_plane_init(dev, pipe, sprite);
13759                         if (ret)
13760                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13761                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13762                 }
13763         }
13764
13765         intel_init_dpio(dev);
13766
13767         intel_shared_dpll_init(dev);
13768
13769         /* Just disable it once at startup */
13770         i915_disable_vga(dev);
13771         intel_setup_outputs(dev);
13772
13773         /* Just in case the BIOS is doing something questionable. */
13774         intel_fbc_disable(dev);
13775
13776         drm_modeset_lock_all(dev);
13777         intel_modeset_setup_hw_state(dev, false);
13778         drm_modeset_unlock_all(dev);
13779
13780         for_each_intel_crtc(dev, crtc) {
13781                 if (!crtc->active)
13782                         continue;
13783
13784                 /*
13785                  * Note that reserving the BIOS fb up front prevents us
13786                  * from stuffing other stolen allocations like the ring
13787                  * on top.  This prevents some ugliness at boot time, and
13788                  * can even allow for smooth boot transitions if the BIOS
13789                  * fb is large enough for the active pipe configuration.
13790                  */
13791                 if (dev_priv->display.get_initial_plane_config) {
13792                         dev_priv->display.get_initial_plane_config(crtc,
13793                                                            &crtc->plane_config);
13794                         /*
13795                          * If the fb is shared between multiple heads, we'll
13796                          * just get the first one.
13797                          */
13798                         intel_find_initial_plane_obj(crtc, &crtc->plane_config);
13799                 }
13800         }
13801 }
13802
13803 static void intel_enable_pipe_a(struct drm_device *dev)
13804 {
13805         struct intel_connector *connector;
13806         struct drm_connector *crt = NULL;
13807         struct intel_load_detect_pipe load_detect_temp;
13808         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13809
13810         /* We can't just switch on the pipe A, we need to set things up with a
13811          * proper mode and output configuration. As a gross hack, enable pipe A
13812          * by enabling the load detect pipe once. */
13813         for_each_intel_connector(dev, connector) {
13814                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13815                         crt = &connector->base;
13816                         break;
13817                 }
13818         }
13819
13820         if (!crt)
13821                 return;
13822
13823         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13824                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
13825 }
13826
13827 static bool
13828 intel_check_plane_mapping(struct intel_crtc *crtc)
13829 {
13830         struct drm_device *dev = crtc->base.dev;
13831         struct drm_i915_private *dev_priv = dev->dev_private;
13832         u32 reg, val;
13833
13834         if (INTEL_INFO(dev)->num_pipes == 1)
13835                 return true;
13836
13837         reg = DSPCNTR(!crtc->plane);
13838         val = I915_READ(reg);
13839
13840         if ((val & DISPLAY_PLANE_ENABLE) &&
13841             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13842                 return false;
13843
13844         return true;
13845 }
13846
13847 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13848 {
13849         struct drm_device *dev = crtc->base.dev;
13850         struct drm_i915_private *dev_priv = dev->dev_private;
13851         u32 reg;
13852
13853         /* Clear any frame start delays used for debugging left by the BIOS */
13854         reg = PIPECONF(crtc->config->cpu_transcoder);
13855         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13856
13857         /* restore vblank interrupts to correct state */
13858         drm_crtc_vblank_reset(&crtc->base);
13859         if (crtc->active) {
13860                 update_scanline_offset(crtc);
13861                 drm_crtc_vblank_on(&crtc->base);
13862         }
13863
13864         /* We need to sanitize the plane -> pipe mapping first because this will
13865          * disable the crtc (and hence change the state) if it is wrong. Note
13866          * that gen4+ has a fixed plane -> pipe mapping.  */
13867         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13868                 struct intel_connector *connector;
13869                 bool plane;
13870
13871                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13872                               crtc->base.base.id);
13873
13874                 /* Pipe has the wrong plane attached and the plane is active.
13875                  * Temporarily change the plane mapping and disable everything
13876                  * ...  */
13877                 plane = crtc->plane;
13878                 crtc->plane = !plane;
13879                 crtc->primary_enabled = true;
13880                 dev_priv->display.crtc_disable(&crtc->base);
13881                 crtc->plane = plane;
13882
13883                 /* ... and break all links. */
13884                 for_each_intel_connector(dev, connector) {
13885                         if (connector->encoder->base.crtc != &crtc->base)
13886                                 continue;
13887
13888                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13889                         connector->base.encoder = NULL;
13890                 }
13891                 /* multiple connectors may have the same encoder:
13892                  *  handle them and break crtc link separately */
13893                 for_each_intel_connector(dev, connector)
13894                         if (connector->encoder->base.crtc == &crtc->base) {
13895                                 connector->encoder->base.crtc = NULL;
13896                                 connector->encoder->connectors_active = false;
13897                         }
13898
13899                 WARN_ON(crtc->active);
13900                 crtc->base.state->enable = false;
13901                 crtc->base.enabled = false;
13902         }
13903
13904         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13905             crtc->pipe == PIPE_A && !crtc->active) {
13906                 /* BIOS forgot to enable pipe A, this mostly happens after
13907                  * resume. Force-enable the pipe to fix this, the update_dpms
13908                  * call below we restore the pipe to the right state, but leave
13909                  * the required bits on. */
13910                 intel_enable_pipe_a(dev);
13911         }
13912
13913         /* Adjust the state of the output pipe according to whether we
13914          * have active connectors/encoders. */
13915         intel_crtc_update_dpms(&crtc->base);
13916
13917         if (crtc->active != crtc->base.state->enable) {
13918                 struct intel_encoder *encoder;
13919
13920                 /* This can happen either due to bugs in the get_hw_state
13921                  * functions or because the pipe is force-enabled due to the
13922                  * pipe A quirk. */
13923                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13924                               crtc->base.base.id,
13925                               crtc->base.state->enable ? "enabled" : "disabled",
13926                               crtc->active ? "enabled" : "disabled");
13927
13928                 crtc->base.state->enable = crtc->active;
13929                 crtc->base.enabled = crtc->active;
13930
13931                 /* Because we only establish the connector -> encoder ->
13932                  * crtc links if something is active, this means the
13933                  * crtc is now deactivated. Break the links. connector
13934                  * -> encoder links are only establish when things are
13935                  *  actually up, hence no need to break them. */
13936                 WARN_ON(crtc->active);
13937
13938                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13939                         WARN_ON(encoder->connectors_active);
13940                         encoder->base.crtc = NULL;
13941                 }
13942         }
13943
13944         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13945                 /*
13946                  * We start out with underrun reporting disabled to avoid races.
13947                  * For correct bookkeeping mark this on active crtcs.
13948                  *
13949                  * Also on gmch platforms we dont have any hardware bits to
13950                  * disable the underrun reporting. Which means we need to start
13951                  * out with underrun reporting disabled also on inactive pipes,
13952                  * since otherwise we'll complain about the garbage we read when
13953                  * e.g. coming up after runtime pm.
13954                  *
13955                  * No protection against concurrent access is required - at
13956                  * worst a fifo underrun happens which also sets this to false.
13957                  */
13958                 crtc->cpu_fifo_underrun_disabled = true;
13959                 crtc->pch_fifo_underrun_disabled = true;
13960         }
13961 }
13962
13963 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13964 {
13965         struct intel_connector *connector;
13966         struct drm_device *dev = encoder->base.dev;
13967
13968         /* We need to check both for a crtc link (meaning that the
13969          * encoder is active and trying to read from a pipe) and the
13970          * pipe itself being active. */
13971         bool has_active_crtc = encoder->base.crtc &&
13972                 to_intel_crtc(encoder->base.crtc)->active;
13973
13974         if (encoder->connectors_active && !has_active_crtc) {
13975                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13976                               encoder->base.base.id,
13977                               encoder->base.name);
13978
13979                 /* Connector is active, but has no active pipe. This is
13980                  * fallout from our resume register restoring. Disable
13981                  * the encoder manually again. */
13982                 if (encoder->base.crtc) {
13983                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13984                                       encoder->base.base.id,
13985                                       encoder->base.name);
13986                         encoder->disable(encoder);
13987                         if (encoder->post_disable)
13988                                 encoder->post_disable(encoder);
13989                 }
13990                 encoder->base.crtc = NULL;
13991                 encoder->connectors_active = false;
13992
13993                 /* Inconsistent output/port/pipe state happens presumably due to
13994                  * a bug in one of the get_hw_state functions. Or someplace else
13995                  * in our code, like the register restore mess on resume. Clamp
13996                  * things to off as a safer default. */
13997                 for_each_intel_connector(dev, connector) {
13998                         if (connector->encoder != encoder)
13999                                 continue;
14000                         connector->base.dpms = DRM_MODE_DPMS_OFF;
14001                         connector->base.encoder = NULL;
14002                 }
14003         }
14004         /* Enabled encoders without active connectors will be fixed in
14005          * the crtc fixup. */
14006 }
14007
14008 void i915_redisable_vga_power_on(struct drm_device *dev)
14009 {
14010         struct drm_i915_private *dev_priv = dev->dev_private;
14011         u32 vga_reg = i915_vgacntrl_reg(dev);
14012
14013         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14014                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14015                 i915_disable_vga(dev);
14016         }
14017 }
14018
14019 void i915_redisable_vga(struct drm_device *dev)
14020 {
14021         struct drm_i915_private *dev_priv = dev->dev_private;
14022
14023         /* This function can be called both from intel_modeset_setup_hw_state or
14024          * at a very early point in our resume sequence, where the power well
14025          * structures are not yet restored. Since this function is at a very
14026          * paranoid "someone might have enabled VGA while we were not looking"
14027          * level, just check if the power well is enabled instead of trying to
14028          * follow the "don't touch the power well if we don't need it" policy
14029          * the rest of the driver uses. */
14030         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14031                 return;
14032
14033         i915_redisable_vga_power_on(dev);
14034 }
14035
14036 static bool primary_get_hw_state(struct intel_crtc *crtc)
14037 {
14038         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14039
14040         if (!crtc->active)
14041                 return false;
14042
14043         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14044 }
14045
14046 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14047 {
14048         struct drm_i915_private *dev_priv = dev->dev_private;
14049         enum pipe pipe;
14050         struct intel_crtc *crtc;
14051         struct intel_encoder *encoder;
14052         struct intel_connector *connector;
14053         int i;
14054
14055         for_each_intel_crtc(dev, crtc) {
14056                 memset(crtc->config, 0, sizeof(*crtc->config));
14057
14058                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14059
14060                 crtc->active = dev_priv->display.get_pipe_config(crtc,
14061                                                                  crtc->config);
14062
14063                 crtc->base.state->enable = crtc->active;
14064                 crtc->base.enabled = crtc->active;
14065                 crtc->primary_enabled = primary_get_hw_state(crtc);
14066
14067                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14068                               crtc->base.base.id,
14069                               crtc->active ? "enabled" : "disabled");
14070         }
14071
14072         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14073                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14074
14075                 pll->on = pll->get_hw_state(dev_priv, pll,
14076                                             &pll->config.hw_state);
14077                 pll->active = 0;
14078                 pll->config.crtc_mask = 0;
14079                 for_each_intel_crtc(dev, crtc) {
14080                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14081                                 pll->active++;
14082                                 pll->config.crtc_mask |= 1 << crtc->pipe;
14083                         }
14084                 }
14085
14086                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14087                               pll->name, pll->config.crtc_mask, pll->on);
14088
14089                 if (pll->config.crtc_mask)
14090                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14091         }
14092
14093         for_each_intel_encoder(dev, encoder) {
14094                 pipe = 0;
14095
14096                 if (encoder->get_hw_state(encoder, &pipe)) {
14097                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14098                         encoder->base.crtc = &crtc->base;
14099                         encoder->get_config(encoder, crtc->config);
14100                 } else {
14101                         encoder->base.crtc = NULL;
14102                 }
14103
14104                 encoder->connectors_active = false;
14105                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14106                               encoder->base.base.id,
14107                               encoder->base.name,
14108                               encoder->base.crtc ? "enabled" : "disabled",
14109                               pipe_name(pipe));
14110         }
14111
14112         for_each_intel_connector(dev, connector) {
14113                 if (connector->get_hw_state(connector)) {
14114                         connector->base.dpms = DRM_MODE_DPMS_ON;
14115                         connector->encoder->connectors_active = true;
14116                         connector->base.encoder = &connector->encoder->base;
14117                 } else {
14118                         connector->base.dpms = DRM_MODE_DPMS_OFF;
14119                         connector->base.encoder = NULL;
14120                 }
14121                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14122                               connector->base.base.id,
14123                               connector->base.name,
14124                               connector->base.encoder ? "enabled" : "disabled");
14125         }
14126 }
14127
14128 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14129  * and i915 state tracking structures. */
14130 void intel_modeset_setup_hw_state(struct drm_device *dev,
14131                                   bool force_restore)
14132 {
14133         struct drm_i915_private *dev_priv = dev->dev_private;
14134         enum pipe pipe;
14135         struct intel_crtc *crtc;
14136         struct intel_encoder *encoder;
14137         int i;
14138
14139         intel_modeset_readout_hw_state(dev);
14140
14141         /*
14142          * Now that we have the config, copy it to each CRTC struct
14143          * Note that this could go away if we move to using crtc_config
14144          * checking everywhere.
14145          */
14146         for_each_intel_crtc(dev, crtc) {
14147                 if (crtc->active && i915.fastboot) {
14148                         intel_mode_from_pipe_config(&crtc->base.mode,
14149                                                     crtc->config);
14150                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14151                                       crtc->base.base.id);
14152                         drm_mode_debug_printmodeline(&crtc->base.mode);
14153                 }
14154         }
14155
14156         /* HW state is read out, now we need to sanitize this mess. */
14157         for_each_intel_encoder(dev, encoder) {
14158                 intel_sanitize_encoder(encoder);
14159         }
14160
14161         for_each_pipe(dev_priv, pipe) {
14162                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14163                 intel_sanitize_crtc(crtc);
14164                 intel_dump_pipe_config(crtc, crtc->config,
14165                                        "[setup_hw_state]");
14166         }
14167
14168         intel_modeset_update_connector_atomic_state(dev);
14169
14170         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14171                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14172
14173                 if (!pll->on || pll->active)
14174                         continue;
14175
14176                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14177
14178                 pll->disable(dev_priv, pll);
14179                 pll->on = false;
14180         }
14181
14182         if (IS_GEN9(dev))
14183                 skl_wm_get_hw_state(dev);
14184         else if (HAS_PCH_SPLIT(dev))
14185                 ilk_wm_get_hw_state(dev);
14186
14187         if (force_restore) {
14188                 i915_redisable_vga(dev);
14189
14190                 /*
14191                  * We need to use raw interfaces for restoring state to avoid
14192                  * checking (bogus) intermediate states.
14193                  */
14194                 for_each_pipe(dev_priv, pipe) {
14195                         struct drm_crtc *crtc =
14196                                 dev_priv->pipe_to_crtc_mapping[pipe];
14197
14198                         intel_crtc_restore_mode(crtc);
14199                 }
14200         } else {
14201                 intel_modeset_update_staged_output_state(dev);
14202         }
14203
14204         intel_modeset_check_state(dev);
14205 }
14206
14207 void intel_modeset_gem_init(struct drm_device *dev)
14208 {
14209         struct drm_i915_private *dev_priv = dev->dev_private;
14210         struct drm_crtc *c;
14211         struct drm_i915_gem_object *obj;
14212
14213         mutex_lock(&dev->struct_mutex);
14214         intel_init_gt_powersave(dev);
14215         mutex_unlock(&dev->struct_mutex);
14216
14217         /*
14218          * There may be no VBT; and if the BIOS enabled SSC we can
14219          * just keep using it to avoid unnecessary flicker.  Whereas if the
14220          * BIOS isn't using it, don't assume it will work even if the VBT
14221          * indicates as much.
14222          */
14223         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14224                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14225                                                 DREF_SSC1_ENABLE);
14226
14227         intel_modeset_init_hw(dev);
14228
14229         intel_setup_overlay(dev);
14230
14231         /*
14232          * Make sure any fbs we allocated at startup are properly
14233          * pinned & fenced.  When we do the allocation it's too early
14234          * for this.
14235          */
14236         mutex_lock(&dev->struct_mutex);
14237         for_each_crtc(dev, c) {
14238                 obj = intel_fb_obj(c->primary->fb);
14239                 if (obj == NULL)
14240                         continue;
14241
14242                 if (intel_pin_and_fence_fb_obj(c->primary,
14243                                                c->primary->fb,
14244                                                c->primary->state,
14245                                                NULL)) {
14246                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
14247                                   to_intel_crtc(c)->pipe);
14248                         drm_framebuffer_unreference(c->primary->fb);
14249                         c->primary->fb = NULL;
14250                         update_state_fb(c->primary);
14251                 }
14252         }
14253         mutex_unlock(&dev->struct_mutex);
14254
14255         intel_backlight_register(dev);
14256 }
14257
14258 void intel_connector_unregister(struct intel_connector *intel_connector)
14259 {
14260         struct drm_connector *connector = &intel_connector->base;
14261
14262         intel_panel_destroy_backlight(connector);
14263         drm_connector_unregister(connector);
14264 }
14265
14266 void intel_modeset_cleanup(struct drm_device *dev)
14267 {
14268         struct drm_i915_private *dev_priv = dev->dev_private;
14269         struct drm_connector *connector;
14270
14271         intel_disable_gt_powersave(dev);
14272
14273         intel_backlight_unregister(dev);
14274
14275         /*
14276          * Interrupts and polling as the first thing to avoid creating havoc.
14277          * Too much stuff here (turning of connectors, ...) would
14278          * experience fancy races otherwise.
14279          */
14280         intel_irq_uninstall(dev_priv);
14281
14282         /*
14283          * Due to the hpd irq storm handling the hotplug work can re-arm the
14284          * poll handlers. Hence disable polling after hpd handling is shut down.
14285          */
14286         drm_kms_helper_poll_fini(dev);
14287
14288         mutex_lock(&dev->struct_mutex);
14289
14290         intel_unregister_dsm_handler();
14291
14292         intel_fbc_disable(dev);
14293
14294         mutex_unlock(&dev->struct_mutex);
14295
14296         /* flush any delayed tasks or pending work */
14297         flush_scheduled_work();
14298
14299         /* destroy the backlight and sysfs files before encoders/connectors */
14300         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
14301                 struct intel_connector *intel_connector;
14302
14303                 intel_connector = to_intel_connector(connector);
14304                 intel_connector->unregister(intel_connector);
14305         }
14306
14307         drm_mode_config_cleanup(dev);
14308
14309         intel_cleanup_overlay(dev);
14310
14311         mutex_lock(&dev->struct_mutex);
14312         intel_cleanup_gt_powersave(dev);
14313         mutex_unlock(&dev->struct_mutex);
14314 }
14315
14316 /*
14317  * Return which encoder is currently attached for connector.
14318  */
14319 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14320 {
14321         return &intel_attached_encoder(connector)->base;
14322 }
14323
14324 void intel_connector_attach_encoder(struct intel_connector *connector,
14325                                     struct intel_encoder *encoder)
14326 {
14327         connector->encoder = encoder;
14328         drm_mode_connector_attach_encoder(&connector->base,
14329                                           &encoder->base);
14330 }
14331
14332 /*
14333  * set vga decode state - true == enable VGA decode
14334  */
14335 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14336 {
14337         struct drm_i915_private *dev_priv = dev->dev_private;
14338         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14339         u16 gmch_ctrl;
14340
14341         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14342                 DRM_ERROR("failed to read control word\n");
14343                 return -EIO;
14344         }
14345
14346         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14347                 return 0;
14348
14349         if (state)
14350                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14351         else
14352                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14353
14354         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14355                 DRM_ERROR("failed to write control word\n");
14356                 return -EIO;
14357         }
14358
14359         return 0;
14360 }
14361
14362 struct intel_display_error_state {
14363
14364         u32 power_well_driver;
14365
14366         int num_transcoders;
14367
14368         struct intel_cursor_error_state {
14369                 u32 control;
14370                 u32 position;
14371                 u32 base;
14372                 u32 size;
14373         } cursor[I915_MAX_PIPES];
14374
14375         struct intel_pipe_error_state {
14376                 bool power_domain_on;
14377                 u32 source;
14378                 u32 stat;
14379         } pipe[I915_MAX_PIPES];
14380
14381         struct intel_plane_error_state {
14382                 u32 control;
14383                 u32 stride;
14384                 u32 size;
14385                 u32 pos;
14386                 u32 addr;
14387                 u32 surface;
14388                 u32 tile_offset;
14389         } plane[I915_MAX_PIPES];
14390
14391         struct intel_transcoder_error_state {
14392                 bool power_domain_on;
14393                 enum transcoder cpu_transcoder;
14394
14395                 u32 conf;
14396
14397                 u32 htotal;
14398                 u32 hblank;
14399                 u32 hsync;
14400                 u32 vtotal;
14401                 u32 vblank;
14402                 u32 vsync;
14403         } transcoder[4];
14404 };
14405
14406 struct intel_display_error_state *
14407 intel_display_capture_error_state(struct drm_device *dev)
14408 {
14409         struct drm_i915_private *dev_priv = dev->dev_private;
14410         struct intel_display_error_state *error;
14411         int transcoders[] = {
14412                 TRANSCODER_A,
14413                 TRANSCODER_B,
14414                 TRANSCODER_C,
14415                 TRANSCODER_EDP,
14416         };
14417         int i;
14418
14419         if (INTEL_INFO(dev)->num_pipes == 0)
14420                 return NULL;
14421
14422         error = kzalloc(sizeof(*error), GFP_ATOMIC);
14423         if (error == NULL)
14424                 return NULL;
14425
14426         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14427                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14428
14429         for_each_pipe(dev_priv, i) {
14430                 error->pipe[i].power_domain_on =
14431                         __intel_display_power_is_enabled(dev_priv,
14432                                                          POWER_DOMAIN_PIPE(i));
14433                 if (!error->pipe[i].power_domain_on)
14434                         continue;
14435
14436                 error->cursor[i].control = I915_READ(CURCNTR(i));
14437                 error->cursor[i].position = I915_READ(CURPOS(i));
14438                 error->cursor[i].base = I915_READ(CURBASE(i));
14439
14440                 error->plane[i].control = I915_READ(DSPCNTR(i));
14441                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14442                 if (INTEL_INFO(dev)->gen <= 3) {
14443                         error->plane[i].size = I915_READ(DSPSIZE(i));
14444                         error->plane[i].pos = I915_READ(DSPPOS(i));
14445                 }
14446                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14447                         error->plane[i].addr = I915_READ(DSPADDR(i));
14448                 if (INTEL_INFO(dev)->gen >= 4) {
14449                         error->plane[i].surface = I915_READ(DSPSURF(i));
14450                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14451                 }
14452
14453                 error->pipe[i].source = I915_READ(PIPESRC(i));
14454
14455                 if (HAS_GMCH_DISPLAY(dev))
14456                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
14457         }
14458
14459         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14460         if (HAS_DDI(dev_priv->dev))
14461                 error->num_transcoders++; /* Account for eDP. */
14462
14463         for (i = 0; i < error->num_transcoders; i++) {
14464                 enum transcoder cpu_transcoder = transcoders[i];
14465
14466                 error->transcoder[i].power_domain_on =
14467                         __intel_display_power_is_enabled(dev_priv,
14468                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14469                 if (!error->transcoder[i].power_domain_on)
14470                         continue;
14471
14472                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14473
14474                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14475                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14476                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14477                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14478                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14479                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14480                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14481         }
14482
14483         return error;
14484 }
14485
14486 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14487
14488 void
14489 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14490                                 struct drm_device *dev,
14491                                 struct intel_display_error_state *error)
14492 {
14493         struct drm_i915_private *dev_priv = dev->dev_private;
14494         int i;
14495
14496         if (!error)
14497                 return;
14498
14499         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14500         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14501                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14502                            error->power_well_driver);
14503         for_each_pipe(dev_priv, i) {
14504                 err_printf(m, "Pipe [%d]:\n", i);
14505                 err_printf(m, "  Power: %s\n",
14506                            error->pipe[i].power_domain_on ? "on" : "off");
14507                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
14508                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
14509
14510                 err_printf(m, "Plane [%d]:\n", i);
14511                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
14512                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
14513                 if (INTEL_INFO(dev)->gen <= 3) {
14514                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
14515                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
14516                 }
14517                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14518                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
14519                 if (INTEL_INFO(dev)->gen >= 4) {
14520                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
14521                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
14522                 }
14523
14524                 err_printf(m, "Cursor [%d]:\n", i);
14525                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
14526                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
14527                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
14528         }
14529
14530         for (i = 0; i < error->num_transcoders; i++) {
14531                 err_printf(m, "CPU transcoder: %c\n",
14532                            transcoder_name(error->transcoder[i].cpu_transcoder));
14533                 err_printf(m, "  Power: %s\n",
14534                            error->transcoder[i].power_domain_on ? "on" : "off");
14535                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
14536                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
14537                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
14538                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
14539                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
14540                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
14541                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
14542         }
14543 }
14544
14545 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14546 {
14547         struct intel_crtc *crtc;
14548
14549         for_each_intel_crtc(dev, crtc) {
14550                 struct intel_unpin_work *work;
14551
14552                 spin_lock_irq(&dev->event_lock);
14553
14554                 work = crtc->unpin_work;
14555
14556                 if (work && work->event &&
14557                     work->event->base.file_priv == file) {
14558                         kfree(work->event);
14559                         work->event = NULL;
14560                 }
14561
14562                 spin_unlock_irq(&dev->event_lock);
14563         }
14564 }