2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *, intel_clock_t *);
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
102 static inline u32 /* units of 100MHz */
103 intel_fdi_link_freq(struct drm_device *dev)
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 static const intel_limit_t intel_limits_i8xx_dvo = {
113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
123 .find_pll = intel_find_best_PLL,
126 static const intel_limit_t intel_limits_i8xx_lvds = {
127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
137 .find_pll = intel_find_best_PLL,
140 static const intel_limit_t intel_limits_i9xx_sdvo = {
141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
151 .find_pll = intel_find_best_PLL,
154 static const intel_limit_t intel_limits_i9xx_lvds = {
155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
169 static const intel_limit_t intel_limits_g4x_sdvo = {
170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
182 .find_pll = intel_g4x_find_best_PLL,
185 static const intel_limit_t intel_limits_g4x_hdmi = {
186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
196 .find_pll = intel_g4x_find_best_PLL,
199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
211 .find_pll = intel_g4x_find_best_PLL,
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
226 .find_pll = intel_g4x_find_best_PLL,
229 static const intel_limit_t intel_limits_g4x_display_port = {
230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
239 .p2_slow = 10, .p2_fast = 10 },
240 .find_pll = intel_find_pll_g4x_dp,
243 static const intel_limit_t intel_limits_pineview_sdvo = {
244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
246 /* Pineview's Ncounter is a ring counter */
247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
249 /* Pineview only has one combined m divider, which we treat as m2. */
250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
256 .find_pll = intel_find_best_PLL,
259 static const intel_limit_t intel_limits_pineview_lvds = {
260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
270 .find_pll = intel_find_best_PLL,
273 /* Ironlake / Sandybridge
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
278 static const intel_limit_t intel_limits_ironlake_dac = {
279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
289 .find_pll = intel_g4x_find_best_PLL,
292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
303 .find_pll = intel_g4x_find_best_PLL,
306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
317 .find_pll = intel_g4x_find_best_PLL,
320 /* LVDS 100mhz refclk limits. */
321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
329 .p1 = { .min = 2, .max = 8 },
330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
332 .find_pll = intel_g4x_find_best_PLL,
335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
343 .p1 = { .min = 2, .max = 6 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
346 .find_pll = intel_g4x_find_best_PLL,
349 static const intel_limit_t intel_limits_ironlake_display_port = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
359 .p2_slow = 10, .p2_fast = 10 },
360 .find_pll = intel_find_pll_ironlake_dp,
363 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
368 const intel_limit_t *limit;
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
374 if (refclk == 100000)
375 limit = &intel_limits_ironlake_dual_lvds_100m;
377 limit = &intel_limits_ironlake_dual_lvds;
379 if (refclk == 100000)
380 limit = &intel_limits_ironlake_single_lvds_100m;
382 limit = &intel_limits_ironlake_single_lvds;
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
386 limit = &intel_limits_ironlake_display_port;
388 limit = &intel_limits_ironlake_dac;
393 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
402 /* LVDS with dual channel */
403 limit = &intel_limits_g4x_dual_channel_lvds;
405 /* LVDS with dual channel */
406 limit = &intel_limits_g4x_single_channel_lvds;
407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
409 limit = &intel_limits_g4x_hdmi;
410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
411 limit = &intel_limits_g4x_sdvo;
412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
413 limit = &intel_limits_g4x_display_port;
414 } else /* The option is for other outputs */
415 limit = &intel_limits_i9xx_sdvo;
420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
425 if (HAS_PCH_SPLIT(dev))
426 limit = intel_ironlake_limit(crtc, refclk);
427 else if (IS_G4X(dev)) {
428 limit = intel_g4x_limit(crtc);
429 } else if (IS_PINEVIEW(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_pineview_lvds;
433 limit = &intel_limits_pineview_sdvo;
434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
438 limit = &intel_limits_i9xx_sdvo;
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
441 limit = &intel_limits_i8xx_lvds;
443 limit = &intel_limits_i8xx_dvo;
448 /* m1 is reserved as 0 in Pineview, n is a ring counter */
449 static void pineview_clock(int refclk, intel_clock_t *clock)
451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
457 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
470 * Returns whether any output on the specified pipe is of the specified type
472 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
485 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
491 static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
496 INTELPllInvalid("p1 out of range\n");
497 if (clock->p < limit->p.min || limit->p.max < clock->p)
498 INTELPllInvalid("p out of range\n");
499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
500 INTELPllInvalid("m2 out of range\n");
501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
502 INTELPllInvalid("m1 out of range\n");
503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
504 INTELPllInvalid("m1 <= m2\n");
505 if (clock->m < limit->m.min || limit->m.max < clock->m)
506 INTELPllInvalid("m out of range\n");
507 if (clock->n < limit->n.min || limit->n.max < clock->n)
508 INTELPllInvalid("n out of range\n");
509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
510 INTELPllInvalid("vco out of range\n");
511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
515 INTELPllInvalid("dot out of range\n");
521 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
532 (I915_READ(LVDS)) != 0) {
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
541 clock.p2 = limit->p2.p2_fast;
543 clock.p2 = limit->p2.p2_slow;
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
548 clock.p2 = limit->p2.p2_fast;
551 memset(best_clock, 0, sizeof(*best_clock));
553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
566 intel_clock(dev, refclk, &clock);
567 if (!intel_PLL_is_valid(dev, limit,
571 clock.p != match_clock->p)
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
584 return (err != target);
588 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
604 if (HAS_PCH_SPLIT(dev))
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
610 clock.p2 = limit->p2.p2_fast;
612 clock.p2 = limit->p2.p2_slow;
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
617 clock.p2 = limit->p2.p2_fast;
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
622 /* based on hardware requirement, prefer smaller n to precision */
623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
624 /* based on hardware requirement, prefere larger m1,m2 */
625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
633 intel_clock(dev, refclk, &clock);
634 if (!intel_PLL_is_valid(dev, limit,
638 clock.p != match_clock->p)
641 this_err = abs(clock.dot - target);
642 if (this_err < err_most) {
656 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
660 struct drm_device *dev = crtc->dev;
663 if (target < 200000) {
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
681 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
683 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
688 if (target < 200000) {
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
710 * intel_wait_for_vblank - wait for vblank on a given pipe
712 * @pipe: pipe to wait for
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
717 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
719 struct drm_i915_private *dev_priv = dev->dev_private;
720 int pipestat_reg = PIPESTAT(pipe);
722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
738 /* Wait for vblank interrupt bit to set */
739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
742 DRM_DEBUG_KMS("vblank wait timed out\n");
746 * intel_wait_for_pipe_off - wait for pipe to turn off
748 * @pipe: pipe to wait for
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
755 * wait for the pipe register state bit to turn off
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
762 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
764 struct drm_i915_private *dev_priv = dev->dev_private;
766 if (INTEL_INFO(dev)->gen >= 4) {
767 int reg = PIPECONF(pipe);
769 /* Wait for the Pipe State to go off */
770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
775 int reg = PIPEDSL(pipe);
776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
778 /* Wait for the display line to settle */
780 last_line = I915_READ(reg) & DSL_LINEMASK;
782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
789 static const char *state_string(bool enabled)
791 return enabled ? "on" : "off";
794 /* Only for pre-ILK configs */
795 static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
809 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
810 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
813 static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
820 if (HAS_PCH_CPT(dev_priv->dev)) {
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
840 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
843 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
857 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
860 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
874 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
877 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
892 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
903 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
906 int pp_reg, lvds_reg;
908 enum pipe panel_pipe = PIPE_A;
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
932 void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
939 reg = PIPECONF(pipe);
940 val = I915_READ(reg);
941 cur_state = !!(val & PIPECONF_ENABLE);
942 WARN(cur_state != state,
943 "pipe %c assertion failure (expected %s, current %s)\n",
944 pipe_name(pipe), state_string(state), state_string(cur_state));
947 static void assert_plane(struct drm_i915_private *dev_priv,
948 enum plane plane, bool state)
954 reg = DSPCNTR(plane);
955 val = I915_READ(reg);
956 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
957 WARN(cur_state != state,
958 "plane %c assertion failure (expected %s, current %s)\n",
959 plane_name(plane), state_string(state), state_string(cur_state));
962 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
963 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
965 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
972 /* Planes are fixed to pipes on ILK+ */
973 if (HAS_PCH_SPLIT(dev_priv->dev)) {
975 val = I915_READ(reg);
976 WARN((val & DISPLAY_PLANE_ENABLE),
977 "plane %c assertion failure, should be disabled but not\n",
982 /* Need to check both planes against the pipe */
983 for (i = 0; i < 2; i++) {
985 val = I915_READ(reg);
986 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
987 DISPPLANE_SEL_PIPE_SHIFT;
988 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
989 "plane %c assertion failure, should be off on pipe %c but is still active\n",
990 plane_name(i), pipe_name(pipe));
994 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999 val = I915_READ(PCH_DREF_CONTROL);
1000 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1001 DREF_SUPERSPREAD_SOURCE_MASK));
1002 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1005 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1012 reg = TRANSCONF(pipe);
1013 val = I915_READ(reg);
1014 enabled = !!(val & TRANS_ENABLE);
1016 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1020 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, u32 port_sel, u32 val)
1023 if ((val & DP_PORT_EN) == 0)
1026 if (HAS_PCH_CPT(dev_priv->dev)) {
1027 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1028 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1029 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1032 if ((val & DP_PIPE_MASK) != (pipe << 30))
1038 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1039 enum pipe pipe, u32 val)
1041 if ((val & PORT_ENABLE) == 0)
1044 if (HAS_PCH_CPT(dev_priv->dev)) {
1045 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1048 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1054 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1055 enum pipe pipe, u32 val)
1057 if ((val & LVDS_PORT_EN) == 0)
1060 if (HAS_PCH_CPT(dev_priv->dev)) {
1061 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1064 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1070 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1071 enum pipe pipe, u32 val)
1073 if ((val & ADPA_DAC_ENABLE) == 0)
1075 if (HAS_PCH_CPT(dev_priv->dev)) {
1076 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1079 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1085 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, int reg, u32 port_sel)
1088 u32 val = I915_READ(reg);
1089 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1090 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1091 reg, pipe_name(pipe));
1094 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, int reg)
1097 u32 val = I915_READ(reg);
1098 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1099 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1100 reg, pipe_name(pipe));
1103 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1109 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1110 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1111 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1114 val = I915_READ(reg);
1115 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1116 "PCH VGA enabled on transcoder %c, should be disabled\n",
1120 val = I915_READ(reg);
1121 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1122 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1125 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1126 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1127 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1131 * intel_enable_pll - enable a PLL
1132 * @dev_priv: i915 private structure
1133 * @pipe: pipe PLL to enable
1135 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1136 * make sure the PLL reg is writable first though, since the panel write
1137 * protect mechanism may be enabled.
1139 * Note! This is for pre-ILK only.
1141 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146 /* No really, not for ILK+ */
1147 BUG_ON(dev_priv->info->gen >= 5);
1149 /* PLL is protected by panel, make sure we can write it */
1150 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1151 assert_panel_unlocked(dev_priv, pipe);
1154 val = I915_READ(reg);
1155 val |= DPLL_VCO_ENABLE;
1157 /* We do this three times for luck */
1158 I915_WRITE(reg, val);
1160 udelay(150); /* wait for warmup */
1161 I915_WRITE(reg, val);
1163 udelay(150); /* wait for warmup */
1164 I915_WRITE(reg, val);
1166 udelay(150); /* wait for warmup */
1170 * intel_disable_pll - disable a PLL
1171 * @dev_priv: i915 private structure
1172 * @pipe: pipe PLL to disable
1174 * Disable the PLL for @pipe, making sure the pipe is off first.
1176 * Note! This is for pre-ILK only.
1178 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183 /* Don't disable pipe A or pipe A PLLs if needed */
1184 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1187 /* Make sure the pipe isn't still relying on us */
1188 assert_pipe_disabled(dev_priv, pipe);
1191 val = I915_READ(reg);
1192 val &= ~DPLL_VCO_ENABLE;
1193 I915_WRITE(reg, val);
1198 * intel_enable_pch_pll - enable PCH PLL
1199 * @dev_priv: i915 private structure
1200 * @pipe: pipe PLL to enable
1202 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1203 * drives the transcoder clock.
1205 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1217 /* PCH refclock must be enabled first */
1218 assert_pch_refclk_enabled(dev_priv);
1220 reg = PCH_DPLL(pipe);
1221 val = I915_READ(reg);
1222 val |= DPLL_VCO_ENABLE;
1223 I915_WRITE(reg, val);
1228 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1232 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1233 pll_sel = TRANSC_DPLL_ENABLE;
1238 /* PCH only available on ILK+ */
1239 BUG_ON(dev_priv->info->gen < 5);
1241 /* Make sure transcoder isn't still depending on us */
1242 assert_transcoder_disabled(dev_priv, pipe);
1245 pll_sel |= TRANSC_DPLLA_SEL;
1247 pll_sel |= TRANSC_DPLLB_SEL;
1250 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1253 reg = PCH_DPLL(pipe);
1254 val = I915_READ(reg);
1255 val &= ~DPLL_VCO_ENABLE;
1256 I915_WRITE(reg, val);
1261 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1267 /* PCH only available on ILK+ */
1268 BUG_ON(dev_priv->info->gen < 5);
1270 /* Make sure PCH DPLL is enabled */
1271 assert_pch_pll_enabled(dev_priv, pipe);
1273 /* FDI must be feeding us bits for PCH ports */
1274 assert_fdi_tx_enabled(dev_priv, pipe);
1275 assert_fdi_rx_enabled(dev_priv, pipe);
1277 reg = TRANSCONF(pipe);
1278 val = I915_READ(reg);
1280 if (HAS_PCH_IBX(dev_priv->dev)) {
1282 * make the BPC in transcoder be consistent with
1283 * that in pipeconf reg.
1285 val &= ~PIPE_BPC_MASK;
1286 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1288 I915_WRITE(reg, val | TRANS_ENABLE);
1289 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1290 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1293 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1299 /* FDI relies on the transcoder */
1300 assert_fdi_tx_disabled(dev_priv, pipe);
1301 assert_fdi_rx_disabled(dev_priv, pipe);
1303 /* Ports must be off as well */
1304 assert_pch_ports_disabled(dev_priv, pipe);
1306 reg = TRANSCONF(pipe);
1307 val = I915_READ(reg);
1308 val &= ~TRANS_ENABLE;
1309 I915_WRITE(reg, val);
1310 /* wait for PCH transcoder off, transcoder state */
1311 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1312 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1316 * intel_enable_pipe - enable a pipe, asserting requirements
1317 * @dev_priv: i915 private structure
1318 * @pipe: pipe to enable
1319 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1321 * Enable @pipe, making sure that various hardware specific requirements
1322 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1324 * @pipe should be %PIPE_A or %PIPE_B.
1326 * Will wait until the pipe is actually running (i.e. first vblank) before
1329 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1336 * A pipe without a PLL won't actually be able to drive bits from
1337 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1340 if (!HAS_PCH_SPLIT(dev_priv->dev))
1341 assert_pll_enabled(dev_priv, pipe);
1344 /* if driving the PCH, we need FDI enabled */
1345 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1346 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1348 /* FIXME: assert CPU port conditions for SNB+ */
1351 reg = PIPECONF(pipe);
1352 val = I915_READ(reg);
1353 if (val & PIPECONF_ENABLE)
1356 I915_WRITE(reg, val | PIPECONF_ENABLE);
1357 intel_wait_for_vblank(dev_priv->dev, pipe);
1361 * intel_disable_pipe - disable a pipe, asserting requirements
1362 * @dev_priv: i915 private structure
1363 * @pipe: pipe to disable
1365 * Disable @pipe, making sure that various hardware specific requirements
1366 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1368 * @pipe should be %PIPE_A or %PIPE_B.
1370 * Will wait until the pipe has shut down before returning.
1372 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1379 * Make sure planes won't keep trying to pump pixels to us,
1380 * or we might hang the display.
1382 assert_planes_disabled(dev_priv, pipe);
1384 /* Don't disable pipe A or pipe A PLLs if needed */
1385 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1388 reg = PIPECONF(pipe);
1389 val = I915_READ(reg);
1390 if ((val & PIPECONF_ENABLE) == 0)
1393 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1394 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1398 * Plane regs are double buffered, going from enabled->disabled needs a
1399 * trigger in order to latch. The display address reg provides this.
1401 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1404 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1405 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1409 * intel_enable_plane - enable a display plane on a given pipe
1410 * @dev_priv: i915 private structure
1411 * @plane: plane to enable
1412 * @pipe: pipe being fed
1414 * Enable @plane on @pipe, making sure that @pipe is running first.
1416 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1417 enum plane plane, enum pipe pipe)
1422 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1423 assert_pipe_enabled(dev_priv, pipe);
1425 reg = DSPCNTR(plane);
1426 val = I915_READ(reg);
1427 if (val & DISPLAY_PLANE_ENABLE)
1430 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1431 intel_flush_display_plane(dev_priv, plane);
1432 intel_wait_for_vblank(dev_priv->dev, pipe);
1436 * intel_disable_plane - disable a display plane
1437 * @dev_priv: i915 private structure
1438 * @plane: plane to disable
1439 * @pipe: pipe consuming the data
1441 * Disable @plane; should be an independent operation.
1443 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1444 enum plane plane, enum pipe pipe)
1449 reg = DSPCNTR(plane);
1450 val = I915_READ(reg);
1451 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1454 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1455 intel_flush_display_plane(dev_priv, plane);
1456 intel_wait_for_vblank(dev_priv->dev, pipe);
1459 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1460 enum pipe pipe, int reg, u32 port_sel)
1462 u32 val = I915_READ(reg);
1463 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1464 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1465 I915_WRITE(reg, val & ~DP_PORT_EN);
1469 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1470 enum pipe pipe, int reg)
1472 u32 val = I915_READ(reg);
1473 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1474 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1476 I915_WRITE(reg, val & ~PORT_ENABLE);
1480 /* Disable any ports connected to this transcoder */
1481 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1486 val = I915_READ(PCH_PP_CONTROL);
1487 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1489 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1490 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1491 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1494 val = I915_READ(reg);
1495 if (adpa_pipe_enabled(dev_priv, val, pipe))
1496 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1499 val = I915_READ(reg);
1500 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1501 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1502 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1507 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1508 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1509 disable_pch_hdmi(dev_priv, pipe, HDMID);
1512 static void i8xx_disable_fbc(struct drm_device *dev)
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1517 /* Disable compression */
1518 fbc_ctl = I915_READ(FBC_CONTROL);
1519 if ((fbc_ctl & FBC_CTL_EN) == 0)
1522 fbc_ctl &= ~FBC_CTL_EN;
1523 I915_WRITE(FBC_CONTROL, fbc_ctl);
1525 /* Wait for compressing bit to clear */
1526 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1527 DRM_DEBUG_KMS("FBC idle timed out\n");
1531 DRM_DEBUG_KMS("disabled FBC\n");
1534 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1536 struct drm_device *dev = crtc->dev;
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538 struct drm_framebuffer *fb = crtc->fb;
1539 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1540 struct drm_i915_gem_object *obj = intel_fb->obj;
1541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1544 u32 fbc_ctl, fbc_ctl2;
1546 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1547 if (fb->pitches[0] < cfb_pitch)
1548 cfb_pitch = fb->pitches[0];
1550 /* FBC_CTL wants 64B units */
1551 cfb_pitch = (cfb_pitch / 64) - 1;
1552 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1554 /* Clear old tags */
1555 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1556 I915_WRITE(FBC_TAG + (i * 4), 0);
1559 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1561 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1562 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1565 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1567 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1568 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1569 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1570 fbc_ctl |= obj->fence_reg;
1571 I915_WRITE(FBC_CONTROL, fbc_ctl);
1573 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1574 cfb_pitch, crtc->y, intel_crtc->plane);
1577 static bool i8xx_fbc_enabled(struct drm_device *dev)
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1581 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1584 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1586 struct drm_device *dev = crtc->dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 struct drm_framebuffer *fb = crtc->fb;
1589 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1590 struct drm_i915_gem_object *obj = intel_fb->obj;
1591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1592 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1593 unsigned long stall_watermark = 200;
1596 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1597 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1598 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1600 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1601 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1602 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1603 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1606 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1608 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1611 static void g4x_disable_fbc(struct drm_device *dev)
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1616 /* Disable compression */
1617 dpfc_ctl = I915_READ(DPFC_CONTROL);
1618 if (dpfc_ctl & DPFC_CTL_EN) {
1619 dpfc_ctl &= ~DPFC_CTL_EN;
1620 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1622 DRM_DEBUG_KMS("disabled FBC\n");
1626 static bool g4x_fbc_enabled(struct drm_device *dev)
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1630 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1633 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1638 /* Make sure blitter notifies FBC of writes */
1639 gen6_gt_force_wake_get(dev_priv);
1640 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1641 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1642 GEN6_BLITTER_LOCK_SHIFT;
1643 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1644 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1645 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1646 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1647 GEN6_BLITTER_LOCK_SHIFT);
1648 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1649 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1650 gen6_gt_force_wake_put(dev_priv);
1653 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1655 struct drm_device *dev = crtc->dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 struct drm_framebuffer *fb = crtc->fb;
1658 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1659 struct drm_i915_gem_object *obj = intel_fb->obj;
1660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1661 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1662 unsigned long stall_watermark = 200;
1665 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1666 dpfc_ctl &= DPFC_RESERVED;
1667 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1668 /* Set persistent mode for front-buffer rendering, ala X. */
1669 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1670 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1671 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1673 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1674 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1675 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1676 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1677 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1679 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1682 I915_WRITE(SNB_DPFC_CTL_SA,
1683 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1684 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1685 sandybridge_blit_fbc_update(dev);
1688 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1691 static void ironlake_disable_fbc(struct drm_device *dev)
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1696 /* Disable compression */
1697 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1698 if (dpfc_ctl & DPFC_CTL_EN) {
1699 dpfc_ctl &= ~DPFC_CTL_EN;
1700 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1702 DRM_DEBUG_KMS("disabled FBC\n");
1706 static bool ironlake_fbc_enabled(struct drm_device *dev)
1708 struct drm_i915_private *dev_priv = dev->dev_private;
1710 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1713 bool intel_fbc_enabled(struct drm_device *dev)
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1717 if (!dev_priv->display.fbc_enabled)
1720 return dev_priv->display.fbc_enabled(dev);
1723 static void intel_fbc_work_fn(struct work_struct *__work)
1725 struct intel_fbc_work *work =
1726 container_of(to_delayed_work(__work),
1727 struct intel_fbc_work, work);
1728 struct drm_device *dev = work->crtc->dev;
1729 struct drm_i915_private *dev_priv = dev->dev_private;
1731 mutex_lock(&dev->struct_mutex);
1732 if (work == dev_priv->fbc_work) {
1733 /* Double check that we haven't switched fb without cancelling
1736 if (work->crtc->fb == work->fb) {
1737 dev_priv->display.enable_fbc(work->crtc,
1740 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1741 dev_priv->cfb_fb = work->crtc->fb->base.id;
1742 dev_priv->cfb_y = work->crtc->y;
1745 dev_priv->fbc_work = NULL;
1747 mutex_unlock(&dev->struct_mutex);
1752 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1754 if (dev_priv->fbc_work == NULL)
1757 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1759 /* Synchronisation is provided by struct_mutex and checking of
1760 * dev_priv->fbc_work, so we can perform the cancellation
1761 * entirely asynchronously.
1763 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1764 /* tasklet was killed before being run, clean up */
1765 kfree(dev_priv->fbc_work);
1767 /* Mark the work as no longer wanted so that if it does
1768 * wake-up (because the work was already running and waiting
1769 * for our mutex), it will discover that is no longer
1772 dev_priv->fbc_work = NULL;
1775 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1777 struct intel_fbc_work *work;
1778 struct drm_device *dev = crtc->dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1781 if (!dev_priv->display.enable_fbc)
1784 intel_cancel_fbc_work(dev_priv);
1786 work = kzalloc(sizeof *work, GFP_KERNEL);
1788 dev_priv->display.enable_fbc(crtc, interval);
1793 work->fb = crtc->fb;
1794 work->interval = interval;
1795 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1797 dev_priv->fbc_work = work;
1799 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1801 /* Delay the actual enabling to let pageflipping cease and the
1802 * display to settle before starting the compression. Note that
1803 * this delay also serves a second purpose: it allows for a
1804 * vblank to pass after disabling the FBC before we attempt
1805 * to modify the control registers.
1807 * A more complicated solution would involve tracking vblanks
1808 * following the termination of the page-flipping sequence
1809 * and indeed performing the enable as a co-routine and not
1810 * waiting synchronously upon the vblank.
1812 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1815 void intel_disable_fbc(struct drm_device *dev)
1817 struct drm_i915_private *dev_priv = dev->dev_private;
1819 intel_cancel_fbc_work(dev_priv);
1821 if (!dev_priv->display.disable_fbc)
1824 dev_priv->display.disable_fbc(dev);
1825 dev_priv->cfb_plane = -1;
1829 * intel_update_fbc - enable/disable FBC as needed
1830 * @dev: the drm_device
1832 * Set up the framebuffer compression hardware at mode set time. We
1833 * enable it if possible:
1834 * - plane A only (on pre-965)
1835 * - no pixel mulitply/line duplication
1836 * - no alpha buffer discard
1838 * - framebuffer <= 2048 in width, 1536 in height
1840 * We can't assume that any compression will take place (worst case),
1841 * so the compressed buffer has to be the same size as the uncompressed
1842 * one. It also must reside (along with the line length buffer) in
1845 * We need to enable/disable FBC on a global basis.
1847 static void intel_update_fbc(struct drm_device *dev)
1849 struct drm_i915_private *dev_priv = dev->dev_private;
1850 struct drm_crtc *crtc = NULL, *tmp_crtc;
1851 struct intel_crtc *intel_crtc;
1852 struct drm_framebuffer *fb;
1853 struct intel_framebuffer *intel_fb;
1854 struct drm_i915_gem_object *obj;
1857 DRM_DEBUG_KMS("\n");
1859 if (!i915_powersave)
1862 if (!I915_HAS_FBC(dev))
1866 * If FBC is already on, we just have to verify that we can
1867 * keep it that way...
1868 * Need to disable if:
1869 * - more than one pipe is active
1870 * - changing FBC params (stride, fence, mode)
1871 * - new fb is too large to fit in compressed buffer
1872 * - going to an unsupported config (interlace, pixel multiply, etc.)
1874 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1875 if (tmp_crtc->enabled && tmp_crtc->fb) {
1877 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1878 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1885 if (!crtc || crtc->fb == NULL) {
1886 DRM_DEBUG_KMS("no output, disabling\n");
1887 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1891 intel_crtc = to_intel_crtc(crtc);
1893 intel_fb = to_intel_framebuffer(fb);
1894 obj = intel_fb->obj;
1896 enable_fbc = i915_enable_fbc;
1897 if (enable_fbc < 0) {
1898 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1900 if (INTEL_INFO(dev)->gen <= 5)
1904 DRM_DEBUG_KMS("fbc disabled per module param\n");
1905 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1908 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1909 DRM_DEBUG_KMS("framebuffer too large, disabling "
1911 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1914 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1915 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1916 DRM_DEBUG_KMS("mode incompatible with compression, "
1918 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1921 if ((crtc->mode.hdisplay > 2048) ||
1922 (crtc->mode.vdisplay > 1536)) {
1923 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1924 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1927 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1928 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1929 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1933 /* The use of a CPU fence is mandatory in order to detect writes
1934 * by the CPU to the scanout and trigger updates to the FBC.
1936 if (obj->tiling_mode != I915_TILING_X ||
1937 obj->fence_reg == I915_FENCE_REG_NONE) {
1938 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1939 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1943 /* If the kernel debugger is active, always disable compression */
1944 if (in_dbg_master())
1947 /* If the scanout has not changed, don't modify the FBC settings.
1948 * Note that we make the fundamental assumption that the fb->obj
1949 * cannot be unpinned (and have its GTT offset and fence revoked)
1950 * without first being decoupled from the scanout and FBC disabled.
1952 if (dev_priv->cfb_plane == intel_crtc->plane &&
1953 dev_priv->cfb_fb == fb->base.id &&
1954 dev_priv->cfb_y == crtc->y)
1957 if (intel_fbc_enabled(dev)) {
1958 /* We update FBC along two paths, after changing fb/crtc
1959 * configuration (modeswitching) and after page-flipping
1960 * finishes. For the latter, we know that not only did
1961 * we disable the FBC at the start of the page-flip
1962 * sequence, but also more than one vblank has passed.
1964 * For the former case of modeswitching, it is possible
1965 * to switch between two FBC valid configurations
1966 * instantaneously so we do need to disable the FBC
1967 * before we can modify its control registers. We also
1968 * have to wait for the next vblank for that to take
1969 * effect. However, since we delay enabling FBC we can
1970 * assume that a vblank has passed since disabling and
1971 * that we can safely alter the registers in the deferred
1974 * In the scenario that we go from a valid to invalid
1975 * and then back to valid FBC configuration we have
1976 * no strict enforcement that a vblank occurred since
1977 * disabling the FBC. However, along all current pipe
1978 * disabling paths we do need to wait for a vblank at
1979 * some point. And we wait before enabling FBC anyway.
1981 DRM_DEBUG_KMS("disabling active FBC for update\n");
1982 intel_disable_fbc(dev);
1985 intel_enable_fbc(crtc, 500);
1989 /* Multiple disables should be harmless */
1990 if (intel_fbc_enabled(dev)) {
1991 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1992 intel_disable_fbc(dev);
1997 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1998 struct drm_i915_gem_object *obj,
1999 struct intel_ring_buffer *pipelined)
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2005 switch (obj->tiling_mode) {
2006 case I915_TILING_NONE:
2007 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2008 alignment = 128 * 1024;
2009 else if (INTEL_INFO(dev)->gen >= 4)
2010 alignment = 4 * 1024;
2012 alignment = 64 * 1024;
2015 /* pin() will align the object as required by fence */
2019 /* FIXME: Is this true? */
2020 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2026 dev_priv->mm.interruptible = false;
2027 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2029 goto err_interruptible;
2031 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2032 * fence, whereas 965+ only requires a fence if using
2033 * framebuffer compression. For simplicity, we always install
2034 * a fence as the cost is not that onerous.
2036 if (obj->tiling_mode != I915_TILING_NONE) {
2037 ret = i915_gem_object_get_fence(obj, pipelined);
2042 dev_priv->mm.interruptible = true;
2046 i915_gem_object_unpin(obj);
2048 dev_priv->mm.interruptible = true;
2052 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2055 struct drm_device *dev = crtc->dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2058 struct intel_framebuffer *intel_fb;
2059 struct drm_i915_gem_object *obj;
2060 int plane = intel_crtc->plane;
2061 unsigned long Start, Offset;
2070 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2074 intel_fb = to_intel_framebuffer(fb);
2075 obj = intel_fb->obj;
2077 reg = DSPCNTR(plane);
2078 dspcntr = I915_READ(reg);
2079 /* Mask out pixel format bits in case we change it */
2080 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2081 switch (fb->bits_per_pixel) {
2083 dspcntr |= DISPPLANE_8BPP;
2086 if (fb->depth == 15)
2087 dspcntr |= DISPPLANE_15_16BPP;
2089 dspcntr |= DISPPLANE_16BPP;
2093 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2096 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2099 if (INTEL_INFO(dev)->gen >= 4) {
2100 if (obj->tiling_mode != I915_TILING_NONE)
2101 dspcntr |= DISPPLANE_TILED;
2103 dspcntr &= ~DISPPLANE_TILED;
2106 I915_WRITE(reg, dspcntr);
2108 Start = obj->gtt_offset;
2109 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2111 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2112 Start, Offset, x, y, fb->pitches[0]);
2113 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2114 if (INTEL_INFO(dev)->gen >= 4) {
2115 I915_WRITE(DSPSURF(plane), Start);
2116 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2117 I915_WRITE(DSPADDR(plane), Offset);
2119 I915_WRITE(DSPADDR(plane), Start + Offset);
2125 static int ironlake_update_plane(struct drm_crtc *crtc,
2126 struct drm_framebuffer *fb, int x, int y)
2128 struct drm_device *dev = crtc->dev;
2129 struct drm_i915_private *dev_priv = dev->dev_private;
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131 struct intel_framebuffer *intel_fb;
2132 struct drm_i915_gem_object *obj;
2133 int plane = intel_crtc->plane;
2134 unsigned long Start, Offset;
2144 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2148 intel_fb = to_intel_framebuffer(fb);
2149 obj = intel_fb->obj;
2151 reg = DSPCNTR(plane);
2152 dspcntr = I915_READ(reg);
2153 /* Mask out pixel format bits in case we change it */
2154 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2155 switch (fb->bits_per_pixel) {
2157 dspcntr |= DISPPLANE_8BPP;
2160 if (fb->depth != 16)
2163 dspcntr |= DISPPLANE_16BPP;
2167 if (fb->depth == 24)
2168 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2169 else if (fb->depth == 30)
2170 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2175 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2179 if (obj->tiling_mode != I915_TILING_NONE)
2180 dspcntr |= DISPPLANE_TILED;
2182 dspcntr &= ~DISPPLANE_TILED;
2185 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2187 I915_WRITE(reg, dspcntr);
2189 Start = obj->gtt_offset;
2190 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2192 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2193 Start, Offset, x, y, fb->pitches[0]);
2194 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2195 I915_WRITE(DSPSURF(plane), Start);
2196 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2197 I915_WRITE(DSPADDR(plane), Offset);
2203 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2205 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2206 int x, int y, enum mode_set_atomic state)
2208 struct drm_device *dev = crtc->dev;
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2212 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2216 intel_update_fbc(dev);
2217 intel_increase_pllclock(crtc);
2223 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2224 struct drm_framebuffer *old_fb)
2226 struct drm_device *dev = crtc->dev;
2227 struct drm_i915_master_private *master_priv;
2228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2233 DRM_ERROR("No FB bound\n");
2237 switch (intel_crtc->plane) {
2242 if (IS_IVYBRIDGE(dev))
2244 /* fall through otherwise */
2246 DRM_ERROR("no plane for crtc\n");
2250 mutex_lock(&dev->struct_mutex);
2251 ret = intel_pin_and_fence_fb_obj(dev,
2252 to_intel_framebuffer(crtc->fb)->obj,
2255 mutex_unlock(&dev->struct_mutex);
2256 DRM_ERROR("pin & fence failed\n");
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2264 wait_event(dev_priv->pending_flip_queue,
2265 atomic_read(&dev_priv->mm.wedged) ||
2266 atomic_read(&obj->pending_flip) == 0);
2268 /* Big Hammer, we also need to ensure that any pending
2269 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2270 * current scanout is retired before unpinning the old
2273 * This should only fail upon a hung GPU, in which case we
2274 * can safely continue.
2276 ret = i915_gem_object_finish_gpu(obj);
2280 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2281 LEAVE_ATOMIC_MODE_SET);
2283 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2284 mutex_unlock(&dev->struct_mutex);
2285 DRM_ERROR("failed to update base address\n");
2290 intel_wait_for_vblank(dev, intel_crtc->pipe);
2291 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2294 mutex_unlock(&dev->struct_mutex);
2296 if (!dev->primary->master)
2299 master_priv = dev->primary->master->driver_priv;
2300 if (!master_priv->sarea_priv)
2303 if (intel_crtc->pipe) {
2304 master_priv->sarea_priv->pipeB_x = x;
2305 master_priv->sarea_priv->pipeB_y = y;
2307 master_priv->sarea_priv->pipeA_x = x;
2308 master_priv->sarea_priv->pipeA_y = y;
2314 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2316 struct drm_device *dev = crtc->dev;
2317 struct drm_i915_private *dev_priv = dev->dev_private;
2320 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2321 dpa_ctl = I915_READ(DP_A);
2322 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2324 if (clock < 200000) {
2326 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2327 /* workaround for 160Mhz:
2328 1) program 0x4600c bits 15:0 = 0x8124
2329 2) program 0x46010 bit 0 = 1
2330 3) program 0x46034 bit 24 = 1
2331 4) program 0x64000 bit 14 = 1
2333 temp = I915_READ(0x4600c);
2335 I915_WRITE(0x4600c, temp | 0x8124);
2337 temp = I915_READ(0x46010);
2338 I915_WRITE(0x46010, temp | 1);
2340 temp = I915_READ(0x46034);
2341 I915_WRITE(0x46034, temp | (1 << 24));
2343 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2345 I915_WRITE(DP_A, dpa_ctl);
2351 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2353 struct drm_device *dev = crtc->dev;
2354 struct drm_i915_private *dev_priv = dev->dev_private;
2355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2356 int pipe = intel_crtc->pipe;
2359 /* enable normal train */
2360 reg = FDI_TX_CTL(pipe);
2361 temp = I915_READ(reg);
2362 if (IS_IVYBRIDGE(dev)) {
2363 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2364 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2366 temp &= ~FDI_LINK_TRAIN_NONE;
2367 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2369 I915_WRITE(reg, temp);
2371 reg = FDI_RX_CTL(pipe);
2372 temp = I915_READ(reg);
2373 if (HAS_PCH_CPT(dev)) {
2374 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2375 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2377 temp &= ~FDI_LINK_TRAIN_NONE;
2378 temp |= FDI_LINK_TRAIN_NONE;
2380 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2382 /* wait one idle pattern time */
2386 /* IVB wants error correction enabled */
2387 if (IS_IVYBRIDGE(dev))
2388 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2389 FDI_FE_ERRC_ENABLE);
2392 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2394 struct drm_i915_private *dev_priv = dev->dev_private;
2395 u32 flags = I915_READ(SOUTH_CHICKEN1);
2397 flags |= FDI_PHASE_SYNC_OVR(pipe);
2398 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2399 flags |= FDI_PHASE_SYNC_EN(pipe);
2400 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2401 POSTING_READ(SOUTH_CHICKEN1);
2404 /* The FDI link training functions for ILK/Ibexpeak. */
2405 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2407 struct drm_device *dev = crtc->dev;
2408 struct drm_i915_private *dev_priv = dev->dev_private;
2409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2410 int pipe = intel_crtc->pipe;
2411 int plane = intel_crtc->plane;
2412 u32 reg, temp, tries;
2414 /* FDI needs bits from pipe & plane first */
2415 assert_pipe_enabled(dev_priv, pipe);
2416 assert_plane_enabled(dev_priv, plane);
2418 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2420 reg = FDI_RX_IMR(pipe);
2421 temp = I915_READ(reg);
2422 temp &= ~FDI_RX_SYMBOL_LOCK;
2423 temp &= ~FDI_RX_BIT_LOCK;
2424 I915_WRITE(reg, temp);
2428 /* enable CPU FDI TX and PCH FDI RX */
2429 reg = FDI_TX_CTL(pipe);
2430 temp = I915_READ(reg);
2432 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_PATTERN_1;
2435 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2437 reg = FDI_RX_CTL(pipe);
2438 temp = I915_READ(reg);
2439 temp &= ~FDI_LINK_TRAIN_NONE;
2440 temp |= FDI_LINK_TRAIN_PATTERN_1;
2441 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2446 /* Ironlake workaround, enable clock pointer after FDI enable*/
2447 if (HAS_PCH_IBX(dev)) {
2448 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2449 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2450 FDI_RX_PHASE_SYNC_POINTER_EN);
2453 reg = FDI_RX_IIR(pipe);
2454 for (tries = 0; tries < 5; tries++) {
2455 temp = I915_READ(reg);
2456 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2458 if ((temp & FDI_RX_BIT_LOCK)) {
2459 DRM_DEBUG_KMS("FDI train 1 done.\n");
2460 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2465 DRM_ERROR("FDI train 1 fail!\n");
2468 reg = FDI_TX_CTL(pipe);
2469 temp = I915_READ(reg);
2470 temp &= ~FDI_LINK_TRAIN_NONE;
2471 temp |= FDI_LINK_TRAIN_PATTERN_2;
2472 I915_WRITE(reg, temp);
2474 reg = FDI_RX_CTL(pipe);
2475 temp = I915_READ(reg);
2476 temp &= ~FDI_LINK_TRAIN_NONE;
2477 temp |= FDI_LINK_TRAIN_PATTERN_2;
2478 I915_WRITE(reg, temp);
2483 reg = FDI_RX_IIR(pipe);
2484 for (tries = 0; tries < 5; tries++) {
2485 temp = I915_READ(reg);
2486 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2488 if (temp & FDI_RX_SYMBOL_LOCK) {
2489 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2490 DRM_DEBUG_KMS("FDI train 2 done.\n");
2495 DRM_ERROR("FDI train 2 fail!\n");
2497 DRM_DEBUG_KMS("FDI train done\n");
2501 static const int snb_b_fdi_train_param[] = {
2502 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2503 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2504 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2505 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2508 /* The FDI link training functions for SNB/Cougarpoint. */
2509 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2511 struct drm_device *dev = crtc->dev;
2512 struct drm_i915_private *dev_priv = dev->dev_private;
2513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2514 int pipe = intel_crtc->pipe;
2517 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2519 reg = FDI_RX_IMR(pipe);
2520 temp = I915_READ(reg);
2521 temp &= ~FDI_RX_SYMBOL_LOCK;
2522 temp &= ~FDI_RX_BIT_LOCK;
2523 I915_WRITE(reg, temp);
2528 /* enable CPU FDI TX and PCH FDI RX */
2529 reg = FDI_TX_CTL(pipe);
2530 temp = I915_READ(reg);
2532 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2533 temp &= ~FDI_LINK_TRAIN_NONE;
2534 temp |= FDI_LINK_TRAIN_PATTERN_1;
2535 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2537 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2538 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2554 if (HAS_PCH_CPT(dev))
2555 cpt_phase_pointer_enable(dev, pipe);
2557 for (i = 0; i < 4; i++) {
2558 reg = FDI_TX_CTL(pipe);
2559 temp = I915_READ(reg);
2560 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2561 temp |= snb_b_fdi_train_param[i];
2562 I915_WRITE(reg, temp);
2567 reg = FDI_RX_IIR(pipe);
2568 temp = I915_READ(reg);
2569 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2571 if (temp & FDI_RX_BIT_LOCK) {
2572 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2573 DRM_DEBUG_KMS("FDI train 1 done.\n");
2578 DRM_ERROR("FDI train 1 fail!\n");
2581 reg = FDI_TX_CTL(pipe);
2582 temp = I915_READ(reg);
2583 temp &= ~FDI_LINK_TRAIN_NONE;
2584 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 I915_WRITE(reg, temp);
2592 reg = FDI_RX_CTL(pipe);
2593 temp = I915_READ(reg);
2594 if (HAS_PCH_CPT(dev)) {
2595 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 temp &= ~FDI_LINK_TRAIN_NONE;
2599 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 I915_WRITE(reg, temp);
2606 for (i = 0; i < 4; i++) {
2607 reg = FDI_TX_CTL(pipe);
2608 temp = I915_READ(reg);
2609 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610 temp |= snb_b_fdi_train_param[i];
2611 I915_WRITE(reg, temp);
2616 reg = FDI_RX_IIR(pipe);
2617 temp = I915_READ(reg);
2618 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2620 if (temp & FDI_RX_SYMBOL_LOCK) {
2621 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2622 DRM_DEBUG_KMS("FDI train 2 done.\n");
2627 DRM_ERROR("FDI train 2 fail!\n");
2629 DRM_DEBUG_KMS("FDI train done.\n");
2632 /* Manual link training for Ivy Bridge A0 parts */
2633 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2635 struct drm_device *dev = crtc->dev;
2636 struct drm_i915_private *dev_priv = dev->dev_private;
2637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638 int pipe = intel_crtc->pipe;
2641 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2643 reg = FDI_RX_IMR(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_RX_SYMBOL_LOCK;
2646 temp &= ~FDI_RX_BIT_LOCK;
2647 I915_WRITE(reg, temp);
2652 /* enable CPU FDI TX and PCH FDI RX */
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2656 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2657 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2658 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2661 temp |= FDI_COMPOSITE_SYNC;
2662 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2664 reg = FDI_RX_CTL(pipe);
2665 temp = I915_READ(reg);
2666 temp &= ~FDI_LINK_TRAIN_AUTO;
2667 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2668 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2669 temp |= FDI_COMPOSITE_SYNC;
2670 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2675 if (HAS_PCH_CPT(dev))
2676 cpt_phase_pointer_enable(dev, pipe);
2678 for (i = 0; i < 4; i++) {
2679 reg = FDI_TX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2682 temp |= snb_b_fdi_train_param[i];
2683 I915_WRITE(reg, temp);
2688 reg = FDI_RX_IIR(pipe);
2689 temp = I915_READ(reg);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2692 if (temp & FDI_RX_BIT_LOCK ||
2693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2695 DRM_DEBUG_KMS("FDI train 1 done.\n");
2700 DRM_ERROR("FDI train 1 fail!\n");
2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2706 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2707 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2708 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2709 I915_WRITE(reg, temp);
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2715 I915_WRITE(reg, temp);
2720 for (i = 0; i < 4; i++) {
2721 reg = FDI_TX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724 temp |= snb_b_fdi_train_param[i];
2725 I915_WRITE(reg, temp);
2730 reg = FDI_RX_IIR(pipe);
2731 temp = I915_READ(reg);
2732 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2734 if (temp & FDI_RX_SYMBOL_LOCK) {
2735 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2736 DRM_DEBUG_KMS("FDI train 2 done.\n");
2741 DRM_ERROR("FDI train 2 fail!\n");
2743 DRM_DEBUG_KMS("FDI train done.\n");
2746 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2748 struct drm_device *dev = crtc->dev;
2749 struct drm_i915_private *dev_priv = dev->dev_private;
2750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2751 int pipe = intel_crtc->pipe;
2754 /* Write the TU size bits so error detection works */
2755 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2756 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2758 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2759 reg = FDI_RX_CTL(pipe);
2760 temp = I915_READ(reg);
2761 temp &= ~((0x7 << 19) | (0x7 << 16));
2762 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2763 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2764 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2769 /* Switch from Rawclk to PCDclk */
2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp | FDI_PCDCLK);
2776 /* Enable CPU FDI TX PLL, always on for Ironlake */
2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2780 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2787 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 u32 flags = I915_READ(SOUTH_CHICKEN1);
2792 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2793 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2794 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2795 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2796 POSTING_READ(SOUTH_CHICKEN1);
2798 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2800 struct drm_device *dev = crtc->dev;
2801 struct drm_i915_private *dev_priv = dev->dev_private;
2802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2803 int pipe = intel_crtc->pipe;
2806 /* disable CPU FDI tx and PCH FDI rx */
2807 reg = FDI_TX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2812 reg = FDI_RX_CTL(pipe);
2813 temp = I915_READ(reg);
2814 temp &= ~(0x7 << 16);
2815 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2816 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2821 /* Ironlake workaround, disable clock pointer after downing FDI */
2822 if (HAS_PCH_IBX(dev)) {
2823 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2824 I915_WRITE(FDI_RX_CHICKEN(pipe),
2825 I915_READ(FDI_RX_CHICKEN(pipe) &
2826 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2827 } else if (HAS_PCH_CPT(dev)) {
2828 cpt_phase_pointer_disable(dev, pipe);
2831 /* still set train pattern 1 */
2832 reg = FDI_TX_CTL(pipe);
2833 temp = I915_READ(reg);
2834 temp &= ~FDI_LINK_TRAIN_NONE;
2835 temp |= FDI_LINK_TRAIN_PATTERN_1;
2836 I915_WRITE(reg, temp);
2838 reg = FDI_RX_CTL(pipe);
2839 temp = I915_READ(reg);
2840 if (HAS_PCH_CPT(dev)) {
2841 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2842 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2844 temp &= ~FDI_LINK_TRAIN_NONE;
2845 temp |= FDI_LINK_TRAIN_PATTERN_1;
2847 /* BPC in FDI rx is consistent with that in PIPECONF */
2848 temp &= ~(0x07 << 16);
2849 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2850 I915_WRITE(reg, temp);
2857 * When we disable a pipe, we need to clear any pending scanline wait events
2858 * to avoid hanging the ring, which we assume we are waiting on.
2860 static void intel_clear_scanline_wait(struct drm_device *dev)
2862 struct drm_i915_private *dev_priv = dev->dev_private;
2863 struct intel_ring_buffer *ring;
2867 /* Can't break the hang on i8xx */
2870 ring = LP_RING(dev_priv);
2871 tmp = I915_READ_CTL(ring);
2872 if (tmp & RING_WAIT)
2873 I915_WRITE_CTL(ring, tmp);
2876 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2878 struct drm_i915_gem_object *obj;
2879 struct drm_i915_private *dev_priv;
2881 if (crtc->fb == NULL)
2884 obj = to_intel_framebuffer(crtc->fb)->obj;
2885 dev_priv = crtc->dev->dev_private;
2886 wait_event(dev_priv->pending_flip_queue,
2887 atomic_read(&obj->pending_flip) == 0);
2890 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_mode_config *mode_config = &dev->mode_config;
2894 struct intel_encoder *encoder;
2897 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2898 * must be driven by its own crtc; no sharing is possible.
2900 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2901 if (encoder->base.crtc != crtc)
2904 switch (encoder->type) {
2905 case INTEL_OUTPUT_EDP:
2906 if (!intel_encoder_is_pch_edp(&encoder->base))
2916 * Enable PCH resources required for PCH ports:
2918 * - FDI training & RX/TX
2919 * - update transcoder timings
2920 * - DP transcoding bits
2923 static void ironlake_pch_enable(struct drm_crtc *crtc)
2925 struct drm_device *dev = crtc->dev;
2926 struct drm_i915_private *dev_priv = dev->dev_private;
2927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2928 int pipe = intel_crtc->pipe;
2929 u32 reg, temp, transc_sel;
2931 /* For PCH output, training FDI link */
2932 dev_priv->display.fdi_link_train(crtc);
2934 intel_enable_pch_pll(dev_priv, pipe);
2936 if (HAS_PCH_CPT(dev)) {
2937 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2940 /* Be sure PCH DPLL SEL is set */
2941 temp = I915_READ(PCH_DPLL_SEL);
2943 temp &= ~(TRANSA_DPLLB_SEL);
2944 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2945 } else if (pipe == 1) {
2946 temp &= ~(TRANSB_DPLLB_SEL);
2947 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2948 } else if (pipe == 2) {
2949 temp &= ~(TRANSC_DPLLB_SEL);
2950 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2952 I915_WRITE(PCH_DPLL_SEL, temp);
2955 /* set transcoder timing, panel must allow it */
2956 assert_panel_unlocked(dev_priv, pipe);
2957 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2958 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2959 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2961 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2962 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2963 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2965 intel_fdi_normal_train(crtc);
2967 /* For PCH DP, enable TRANS_DP_CTL */
2968 if (HAS_PCH_CPT(dev) &&
2969 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2970 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2971 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2972 reg = TRANS_DP_CTL(pipe);
2973 temp = I915_READ(reg);
2974 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2975 TRANS_DP_SYNC_MASK |
2977 temp |= (TRANS_DP_OUTPUT_ENABLE |
2978 TRANS_DP_ENH_FRAMING);
2979 temp |= bpc << 9; /* same format but at 11:9 */
2981 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2982 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2983 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2984 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2986 switch (intel_trans_dp_port_sel(crtc)) {
2988 temp |= TRANS_DP_PORT_SEL_B;
2991 temp |= TRANS_DP_PORT_SEL_C;
2994 temp |= TRANS_DP_PORT_SEL_D;
2997 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2998 temp |= TRANS_DP_PORT_SEL_B;
3002 I915_WRITE(reg, temp);
3005 intel_enable_transcoder(dev_priv, pipe);
3008 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3014 temp = I915_READ(dslreg);
3016 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3017 /* Without this, mode sets may fail silently on FDI */
3018 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3020 I915_WRITE(tc2reg, 0);
3021 if (wait_for(I915_READ(dslreg) != temp, 5))
3022 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3026 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3028 struct drm_device *dev = crtc->dev;
3029 struct drm_i915_private *dev_priv = dev->dev_private;
3030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031 int pipe = intel_crtc->pipe;
3032 int plane = intel_crtc->plane;
3036 if (intel_crtc->active)
3039 intel_crtc->active = true;
3040 intel_update_watermarks(dev);
3042 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3043 temp = I915_READ(PCH_LVDS);
3044 if ((temp & LVDS_PORT_EN) == 0)
3045 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3048 is_pch_port = intel_crtc_driving_pch(crtc);
3051 ironlake_fdi_pll_enable(crtc);
3053 ironlake_fdi_disable(crtc);
3055 /* Enable panel fitting for LVDS */
3056 if (dev_priv->pch_pf_size &&
3057 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3058 /* Force use of hard-coded filter coefficients
3059 * as some pre-programmed values are broken,
3062 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3063 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3064 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3068 * On ILK+ LUT must be loaded before the pipe is running but with
3071 intel_crtc_load_lut(crtc);
3073 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3074 intel_enable_plane(dev_priv, plane, pipe);
3077 ironlake_pch_enable(crtc);
3079 mutex_lock(&dev->struct_mutex);
3080 intel_update_fbc(dev);
3081 mutex_unlock(&dev->struct_mutex);
3083 intel_crtc_update_cursor(crtc, true);
3086 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3088 struct drm_device *dev = crtc->dev;
3089 struct drm_i915_private *dev_priv = dev->dev_private;
3090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3091 int pipe = intel_crtc->pipe;
3092 int plane = intel_crtc->plane;
3095 if (!intel_crtc->active)
3098 intel_crtc_wait_for_pending_flips(crtc);
3099 drm_vblank_off(dev, pipe);
3100 intel_crtc_update_cursor(crtc, false);
3102 intel_disable_plane(dev_priv, plane, pipe);
3104 if (dev_priv->cfb_plane == plane)
3105 intel_disable_fbc(dev);
3107 intel_disable_pipe(dev_priv, pipe);
3110 I915_WRITE(PF_CTL(pipe), 0);
3111 I915_WRITE(PF_WIN_SZ(pipe), 0);
3113 ironlake_fdi_disable(crtc);
3115 /* This is a horrible layering violation; we should be doing this in
3116 * the connector/encoder ->prepare instead, but we don't always have
3117 * enough information there about the config to know whether it will
3118 * actually be necessary or just cause undesired flicker.
3120 intel_disable_pch_ports(dev_priv, pipe);
3122 intel_disable_transcoder(dev_priv, pipe);
3124 if (HAS_PCH_CPT(dev)) {
3125 /* disable TRANS_DP_CTL */
3126 reg = TRANS_DP_CTL(pipe);
3127 temp = I915_READ(reg);
3128 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3129 temp |= TRANS_DP_PORT_SEL_NONE;
3130 I915_WRITE(reg, temp);
3132 /* disable DPLL_SEL */
3133 temp = I915_READ(PCH_DPLL_SEL);
3136 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3139 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3142 /* C shares PLL A or B */
3143 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3148 I915_WRITE(PCH_DPLL_SEL, temp);
3151 /* disable PCH DPLL */
3152 if (!intel_crtc->no_pll)
3153 intel_disable_pch_pll(dev_priv, pipe);
3155 /* Switch from PCDclk to Rawclk */
3156 reg = FDI_RX_CTL(pipe);
3157 temp = I915_READ(reg);
3158 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3160 /* Disable CPU FDI TX PLL */
3161 reg = FDI_TX_CTL(pipe);
3162 temp = I915_READ(reg);
3163 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3168 reg = FDI_RX_CTL(pipe);
3169 temp = I915_READ(reg);
3170 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3172 /* Wait for the clocks to turn off. */
3176 intel_crtc->active = false;
3177 intel_update_watermarks(dev);
3179 mutex_lock(&dev->struct_mutex);
3180 intel_update_fbc(dev);
3181 intel_clear_scanline_wait(dev);
3182 mutex_unlock(&dev->struct_mutex);
3185 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188 int pipe = intel_crtc->pipe;
3189 int plane = intel_crtc->plane;
3191 /* XXX: When our outputs are all unaware of DPMS modes other than off
3192 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3195 case DRM_MODE_DPMS_ON:
3196 case DRM_MODE_DPMS_STANDBY:
3197 case DRM_MODE_DPMS_SUSPEND:
3198 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3199 ironlake_crtc_enable(crtc);
3202 case DRM_MODE_DPMS_OFF:
3203 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3204 ironlake_crtc_disable(crtc);
3209 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3211 if (!enable && intel_crtc->overlay) {
3212 struct drm_device *dev = intel_crtc->base.dev;
3213 struct drm_i915_private *dev_priv = dev->dev_private;
3215 mutex_lock(&dev->struct_mutex);
3216 dev_priv->mm.interruptible = false;
3217 (void) intel_overlay_switch_off(intel_crtc->overlay);
3218 dev_priv->mm.interruptible = true;
3219 mutex_unlock(&dev->struct_mutex);
3222 /* Let userspace switch the overlay on again. In most cases userspace
3223 * has to recompute where to put it anyway.
3227 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3229 struct drm_device *dev = crtc->dev;
3230 struct drm_i915_private *dev_priv = dev->dev_private;
3231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3232 int pipe = intel_crtc->pipe;
3233 int plane = intel_crtc->plane;
3235 if (intel_crtc->active)
3238 intel_crtc->active = true;
3239 intel_update_watermarks(dev);
3241 intel_enable_pll(dev_priv, pipe);
3242 intel_enable_pipe(dev_priv, pipe, false);
3243 intel_enable_plane(dev_priv, plane, pipe);
3245 intel_crtc_load_lut(crtc);
3246 intel_update_fbc(dev);
3248 /* Give the overlay scaler a chance to enable if it's on this pipe */
3249 intel_crtc_dpms_overlay(intel_crtc, true);
3250 intel_crtc_update_cursor(crtc, true);
3253 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3255 struct drm_device *dev = crtc->dev;
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3258 int pipe = intel_crtc->pipe;
3259 int plane = intel_crtc->plane;
3261 if (!intel_crtc->active)
3264 /* Give the overlay scaler a chance to disable if it's on this pipe */
3265 intel_crtc_wait_for_pending_flips(crtc);
3266 drm_vblank_off(dev, pipe);
3267 intel_crtc_dpms_overlay(intel_crtc, false);
3268 intel_crtc_update_cursor(crtc, false);
3270 if (dev_priv->cfb_plane == plane)
3271 intel_disable_fbc(dev);
3273 intel_disable_plane(dev_priv, plane, pipe);
3274 intel_disable_pipe(dev_priv, pipe);
3275 intel_disable_pll(dev_priv, pipe);
3277 intel_crtc->active = false;
3278 intel_update_fbc(dev);
3279 intel_update_watermarks(dev);
3280 intel_clear_scanline_wait(dev);
3283 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3285 /* XXX: When our outputs are all unaware of DPMS modes other than off
3286 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3289 case DRM_MODE_DPMS_ON:
3290 case DRM_MODE_DPMS_STANDBY:
3291 case DRM_MODE_DPMS_SUSPEND:
3292 i9xx_crtc_enable(crtc);
3294 case DRM_MODE_DPMS_OFF:
3295 i9xx_crtc_disable(crtc);
3301 * Sets the power management mode of the pipe and plane.
3303 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3305 struct drm_device *dev = crtc->dev;
3306 struct drm_i915_private *dev_priv = dev->dev_private;
3307 struct drm_i915_master_private *master_priv;
3308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3309 int pipe = intel_crtc->pipe;
3312 if (intel_crtc->dpms_mode == mode)
3315 intel_crtc->dpms_mode = mode;
3317 dev_priv->display.dpms(crtc, mode);
3319 if (!dev->primary->master)
3322 master_priv = dev->primary->master->driver_priv;
3323 if (!master_priv->sarea_priv)
3326 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3330 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3331 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3334 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3335 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3338 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3343 static void intel_crtc_disable(struct drm_crtc *crtc)
3345 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3346 struct drm_device *dev = crtc->dev;
3348 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3349 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3350 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3353 mutex_lock(&dev->struct_mutex);
3354 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3355 mutex_unlock(&dev->struct_mutex);
3359 /* Prepare for a mode set.
3361 * Note we could be a lot smarter here. We need to figure out which outputs
3362 * will be enabled, which disabled (in short, how the config will changes)
3363 * and perform the minimum necessary steps to accomplish that, e.g. updating
3364 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3365 * panel fitting is in the proper state, etc.
3367 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3369 i9xx_crtc_disable(crtc);
3372 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3374 i9xx_crtc_enable(crtc);
3377 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3379 ironlake_crtc_disable(crtc);
3382 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3384 ironlake_crtc_enable(crtc);
3387 void intel_encoder_prepare(struct drm_encoder *encoder)
3389 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3390 /* lvds has its own version of prepare see intel_lvds_prepare */
3391 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3394 void intel_encoder_commit(struct drm_encoder *encoder)
3396 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3397 struct drm_device *dev = encoder->dev;
3398 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3399 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3401 /* lvds has its own version of commit see intel_lvds_commit */
3402 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3404 if (HAS_PCH_CPT(dev))
3405 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3408 void intel_encoder_destroy(struct drm_encoder *encoder)
3410 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3412 drm_encoder_cleanup(encoder);
3413 kfree(intel_encoder);
3416 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3417 struct drm_display_mode *mode,
3418 struct drm_display_mode *adjusted_mode)
3420 struct drm_device *dev = crtc->dev;
3422 if (HAS_PCH_SPLIT(dev)) {
3423 /* FDI link clock is fixed at 2.7G */
3424 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3428 /* XXX some encoders set the crtcinfo, others don't.
3429 * Obviously we need some form of conflict resolution here...
3431 if (adjusted_mode->crtc_htotal == 0)
3432 drm_mode_set_crtcinfo(adjusted_mode, 0);
3437 static int i945_get_display_clock_speed(struct drm_device *dev)
3442 static int i915_get_display_clock_speed(struct drm_device *dev)
3447 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3452 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3456 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3458 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3461 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3462 case GC_DISPLAY_CLOCK_333_MHZ:
3465 case GC_DISPLAY_CLOCK_190_200_MHZ:
3471 static int i865_get_display_clock_speed(struct drm_device *dev)
3476 static int i855_get_display_clock_speed(struct drm_device *dev)
3479 /* Assume that the hardware is in the high speed state. This
3480 * should be the default.
3482 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3483 case GC_CLOCK_133_200:
3484 case GC_CLOCK_100_200:
3486 case GC_CLOCK_166_250:
3488 case GC_CLOCK_100_133:
3492 /* Shouldn't happen */
3496 static int i830_get_display_clock_speed(struct drm_device *dev)
3510 fdi_reduce_ratio(u32 *num, u32 *den)
3512 while (*num > 0xffffff || *den > 0xffffff) {
3519 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3520 int link_clock, struct fdi_m_n *m_n)
3522 m_n->tu = 64; /* default size */
3524 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3525 m_n->gmch_m = bits_per_pixel * pixel_clock;
3526 m_n->gmch_n = link_clock * nlanes * 8;
3527 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3529 m_n->link_m = pixel_clock;
3530 m_n->link_n = link_clock;
3531 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3535 struct intel_watermark_params {
3536 unsigned long fifo_size;
3537 unsigned long max_wm;
3538 unsigned long default_wm;
3539 unsigned long guard_size;
3540 unsigned long cacheline_size;
3543 /* Pineview has different values for various configs */
3544 static const struct intel_watermark_params pineview_display_wm = {
3545 PINEVIEW_DISPLAY_FIFO,
3549 PINEVIEW_FIFO_LINE_SIZE
3551 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3552 PINEVIEW_DISPLAY_FIFO,
3554 PINEVIEW_DFT_HPLLOFF_WM,
3556 PINEVIEW_FIFO_LINE_SIZE
3558 static const struct intel_watermark_params pineview_cursor_wm = {
3559 PINEVIEW_CURSOR_FIFO,
3560 PINEVIEW_CURSOR_MAX_WM,
3561 PINEVIEW_CURSOR_DFT_WM,
3562 PINEVIEW_CURSOR_GUARD_WM,
3563 PINEVIEW_FIFO_LINE_SIZE,
3565 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3566 PINEVIEW_CURSOR_FIFO,
3567 PINEVIEW_CURSOR_MAX_WM,
3568 PINEVIEW_CURSOR_DFT_WM,
3569 PINEVIEW_CURSOR_GUARD_WM,
3570 PINEVIEW_FIFO_LINE_SIZE
3572 static const struct intel_watermark_params g4x_wm_info = {
3579 static const struct intel_watermark_params g4x_cursor_wm_info = {
3586 static const struct intel_watermark_params i965_cursor_wm_info = {
3591 I915_FIFO_LINE_SIZE,
3593 static const struct intel_watermark_params i945_wm_info = {
3600 static const struct intel_watermark_params i915_wm_info = {
3607 static const struct intel_watermark_params i855_wm_info = {
3614 static const struct intel_watermark_params i830_wm_info = {
3622 static const struct intel_watermark_params ironlake_display_wm_info = {
3629 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3636 static const struct intel_watermark_params ironlake_display_srwm_info = {
3637 ILK_DISPLAY_SR_FIFO,
3638 ILK_DISPLAY_MAX_SRWM,
3639 ILK_DISPLAY_DFT_SRWM,
3643 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3645 ILK_CURSOR_MAX_SRWM,
3646 ILK_CURSOR_DFT_SRWM,
3651 static const struct intel_watermark_params sandybridge_display_wm_info = {
3658 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3665 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3666 SNB_DISPLAY_SR_FIFO,
3667 SNB_DISPLAY_MAX_SRWM,
3668 SNB_DISPLAY_DFT_SRWM,
3672 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3674 SNB_CURSOR_MAX_SRWM,
3675 SNB_CURSOR_DFT_SRWM,
3682 * intel_calculate_wm - calculate watermark level
3683 * @clock_in_khz: pixel clock
3684 * @wm: chip FIFO params
3685 * @pixel_size: display pixel size
3686 * @latency_ns: memory latency for the platform
3688 * Calculate the watermark level (the level at which the display plane will
3689 * start fetching from memory again). Each chip has a different display
3690 * FIFO size and allocation, so the caller needs to figure that out and pass
3691 * in the correct intel_watermark_params structure.
3693 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3694 * on the pixel size. When it reaches the watermark level, it'll start
3695 * fetching FIFO line sized based chunks from memory until the FIFO fills
3696 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3697 * will occur, and a display engine hang could result.
3699 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3700 const struct intel_watermark_params *wm,
3703 unsigned long latency_ns)
3705 long entries_required, wm_size;
3708 * Note: we need to make sure we don't overflow for various clock &
3710 * clocks go from a few thousand to several hundred thousand.
3711 * latency is usually a few thousand
3713 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3715 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3717 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3719 wm_size = fifo_size - (entries_required + wm->guard_size);
3721 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3723 /* Don't promote wm_size to unsigned... */
3724 if (wm_size > (long)wm->max_wm)
3725 wm_size = wm->max_wm;
3727 wm_size = wm->default_wm;
3731 struct cxsr_latency {
3734 unsigned long fsb_freq;
3735 unsigned long mem_freq;
3736 unsigned long display_sr;
3737 unsigned long display_hpll_disable;
3738 unsigned long cursor_sr;
3739 unsigned long cursor_hpll_disable;
3742 static const struct cxsr_latency cxsr_latency_table[] = {
3743 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3744 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3745 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3746 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3747 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3749 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3750 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3751 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3752 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3753 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3755 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3756 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3757 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3758 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3759 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3761 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3762 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3763 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3764 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3765 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3767 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3768 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3769 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3770 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3771 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3773 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3774 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3775 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3776 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3777 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3780 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3785 const struct cxsr_latency *latency;
3788 if (fsb == 0 || mem == 0)
3791 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3792 latency = &cxsr_latency_table[i];
3793 if (is_desktop == latency->is_desktop &&
3794 is_ddr3 == latency->is_ddr3 &&
3795 fsb == latency->fsb_freq && mem == latency->mem_freq)
3799 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3804 static void pineview_disable_cxsr(struct drm_device *dev)
3806 struct drm_i915_private *dev_priv = dev->dev_private;
3808 /* deactivate cxsr */
3809 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3813 * Latency for FIFO fetches is dependent on several factors:
3814 * - memory configuration (speed, channels)
3816 * - current MCH state
3817 * It can be fairly high in some situations, so here we assume a fairly
3818 * pessimal value. It's a tradeoff between extra memory fetches (if we
3819 * set this value too high, the FIFO will fetch frequently to stay full)
3820 * and power consumption (set it too low to save power and we might see
3821 * FIFO underruns and display "flicker").
3823 * A value of 5us seems to be a good balance; safe for very low end
3824 * platforms but not overly aggressive on lower latency configs.
3826 static const int latency_ns = 5000;
3828 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3830 struct drm_i915_private *dev_priv = dev->dev_private;
3831 uint32_t dsparb = I915_READ(DSPARB);
3834 size = dsparb & 0x7f;
3836 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3838 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3839 plane ? "B" : "A", size);
3844 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3846 struct drm_i915_private *dev_priv = dev->dev_private;
3847 uint32_t dsparb = I915_READ(DSPARB);
3850 size = dsparb & 0x1ff;
3852 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3853 size >>= 1; /* Convert to cachelines */
3855 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3856 plane ? "B" : "A", size);
3861 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3863 struct drm_i915_private *dev_priv = dev->dev_private;
3864 uint32_t dsparb = I915_READ(DSPARB);
3867 size = dsparb & 0x7f;
3868 size >>= 2; /* Convert to cachelines */
3870 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3877 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 uint32_t dsparb = I915_READ(DSPARB);
3883 size = dsparb & 0x7f;
3884 size >>= 1; /* Convert to cachelines */
3886 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3887 plane ? "B" : "A", size);
3892 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3894 struct drm_crtc *crtc, *enabled = NULL;
3896 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3897 if (crtc->enabled && crtc->fb) {
3907 static void pineview_update_wm(struct drm_device *dev)
3909 struct drm_i915_private *dev_priv = dev->dev_private;
3910 struct drm_crtc *crtc;
3911 const struct cxsr_latency *latency;
3915 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3916 dev_priv->fsb_freq, dev_priv->mem_freq);
3918 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3919 pineview_disable_cxsr(dev);
3923 crtc = single_enabled_crtc(dev);
3925 int clock = crtc->mode.clock;
3926 int pixel_size = crtc->fb->bits_per_pixel / 8;
3929 wm = intel_calculate_wm(clock, &pineview_display_wm,
3930 pineview_display_wm.fifo_size,
3931 pixel_size, latency->display_sr);
3932 reg = I915_READ(DSPFW1);
3933 reg &= ~DSPFW_SR_MASK;
3934 reg |= wm << DSPFW_SR_SHIFT;
3935 I915_WRITE(DSPFW1, reg);
3936 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3939 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3940 pineview_display_wm.fifo_size,
3941 pixel_size, latency->cursor_sr);
3942 reg = I915_READ(DSPFW3);
3943 reg &= ~DSPFW_CURSOR_SR_MASK;
3944 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3945 I915_WRITE(DSPFW3, reg);
3947 /* Display HPLL off SR */
3948 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3949 pineview_display_hplloff_wm.fifo_size,
3950 pixel_size, latency->display_hpll_disable);
3951 reg = I915_READ(DSPFW3);
3952 reg &= ~DSPFW_HPLL_SR_MASK;
3953 reg |= wm & DSPFW_HPLL_SR_MASK;
3954 I915_WRITE(DSPFW3, reg);
3956 /* cursor HPLL off SR */
3957 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3958 pineview_display_hplloff_wm.fifo_size,
3959 pixel_size, latency->cursor_hpll_disable);
3960 reg = I915_READ(DSPFW3);
3961 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3962 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3963 I915_WRITE(DSPFW3, reg);
3964 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3968 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3969 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3971 pineview_disable_cxsr(dev);
3972 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3976 static bool g4x_compute_wm0(struct drm_device *dev,
3978 const struct intel_watermark_params *display,
3979 int display_latency_ns,
3980 const struct intel_watermark_params *cursor,
3981 int cursor_latency_ns,
3985 struct drm_crtc *crtc;
3986 int htotal, hdisplay, clock, pixel_size;
3987 int line_time_us, line_count;
3988 int entries, tlb_miss;
3990 crtc = intel_get_crtc_for_plane(dev, plane);
3991 if (crtc->fb == NULL || !crtc->enabled) {
3992 *cursor_wm = cursor->guard_size;
3993 *plane_wm = display->guard_size;
3997 htotal = crtc->mode.htotal;
3998 hdisplay = crtc->mode.hdisplay;
3999 clock = crtc->mode.clock;
4000 pixel_size = crtc->fb->bits_per_pixel / 8;
4002 /* Use the small buffer method to calculate plane watermark */
4003 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4004 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4006 entries += tlb_miss;
4007 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4008 *plane_wm = entries + display->guard_size;
4009 if (*plane_wm > (int)display->max_wm)
4010 *plane_wm = display->max_wm;
4012 /* Use the large buffer method to calculate cursor watermark */
4013 line_time_us = ((htotal * 1000) / clock);
4014 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4015 entries = line_count * 64 * pixel_size;
4016 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4018 entries += tlb_miss;
4019 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4020 *cursor_wm = entries + cursor->guard_size;
4021 if (*cursor_wm > (int)cursor->max_wm)
4022 *cursor_wm = (int)cursor->max_wm;
4028 * Check the wm result.
4030 * If any calculated watermark values is larger than the maximum value that
4031 * can be programmed into the associated watermark register, that watermark
4034 static bool g4x_check_srwm(struct drm_device *dev,
4035 int display_wm, int cursor_wm,
4036 const struct intel_watermark_params *display,
4037 const struct intel_watermark_params *cursor)
4039 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4040 display_wm, cursor_wm);
4042 if (display_wm > display->max_wm) {
4043 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4044 display_wm, display->max_wm);
4048 if (cursor_wm > cursor->max_wm) {
4049 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4050 cursor_wm, cursor->max_wm);
4054 if (!(display_wm || cursor_wm)) {
4055 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4062 static bool g4x_compute_srwm(struct drm_device *dev,
4065 const struct intel_watermark_params *display,
4066 const struct intel_watermark_params *cursor,
4067 int *display_wm, int *cursor_wm)
4069 struct drm_crtc *crtc;
4070 int hdisplay, htotal, pixel_size, clock;
4071 unsigned long line_time_us;
4072 int line_count, line_size;
4077 *display_wm = *cursor_wm = 0;
4081 crtc = intel_get_crtc_for_plane(dev, plane);
4082 hdisplay = crtc->mode.hdisplay;
4083 htotal = crtc->mode.htotal;
4084 clock = crtc->mode.clock;
4085 pixel_size = crtc->fb->bits_per_pixel / 8;
4087 line_time_us = (htotal * 1000) / clock;
4088 line_count = (latency_ns / line_time_us + 1000) / 1000;
4089 line_size = hdisplay * pixel_size;
4091 /* Use the minimum of the small and large buffer method for primary */
4092 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4093 large = line_count * line_size;
4095 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4096 *display_wm = entries + display->guard_size;
4098 /* calculate the self-refresh watermark for display cursor */
4099 entries = line_count * pixel_size * 64;
4100 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4101 *cursor_wm = entries + cursor->guard_size;
4103 return g4x_check_srwm(dev,
4104 *display_wm, *cursor_wm,
4108 #define single_plane_enabled(mask) is_power_of_2(mask)
4110 static void g4x_update_wm(struct drm_device *dev)
4112 static const int sr_latency_ns = 12000;
4113 struct drm_i915_private *dev_priv = dev->dev_private;
4114 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4115 int plane_sr, cursor_sr;
4116 unsigned int enabled = 0;
4118 if (g4x_compute_wm0(dev, 0,
4119 &g4x_wm_info, latency_ns,
4120 &g4x_cursor_wm_info, latency_ns,
4121 &planea_wm, &cursora_wm))
4124 if (g4x_compute_wm0(dev, 1,
4125 &g4x_wm_info, latency_ns,
4126 &g4x_cursor_wm_info, latency_ns,
4127 &planeb_wm, &cursorb_wm))
4130 plane_sr = cursor_sr = 0;
4131 if (single_plane_enabled(enabled) &&
4132 g4x_compute_srwm(dev, ffs(enabled) - 1,
4135 &g4x_cursor_wm_info,
4136 &plane_sr, &cursor_sr))
4137 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4139 I915_WRITE(FW_BLC_SELF,
4140 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4142 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4143 planea_wm, cursora_wm,
4144 planeb_wm, cursorb_wm,
4145 plane_sr, cursor_sr);
4148 (plane_sr << DSPFW_SR_SHIFT) |
4149 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4150 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4153 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4154 (cursora_wm << DSPFW_CURSORA_SHIFT));
4155 /* HPLL off in SR has some issues on G4x... disable it */
4157 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4158 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4161 static void i965_update_wm(struct drm_device *dev)
4163 struct drm_i915_private *dev_priv = dev->dev_private;
4164 struct drm_crtc *crtc;
4168 /* Calc sr entries for one plane configs */
4169 crtc = single_enabled_crtc(dev);
4171 /* self-refresh has much higher latency */
4172 static const int sr_latency_ns = 12000;
4173 int clock = crtc->mode.clock;
4174 int htotal = crtc->mode.htotal;
4175 int hdisplay = crtc->mode.hdisplay;
4176 int pixel_size = crtc->fb->bits_per_pixel / 8;
4177 unsigned long line_time_us;
4180 line_time_us = ((htotal * 1000) / clock);
4182 /* Use ns/us then divide to preserve precision */
4183 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4184 pixel_size * hdisplay;
4185 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4186 srwm = I965_FIFO_SIZE - entries;
4190 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4193 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4195 entries = DIV_ROUND_UP(entries,
4196 i965_cursor_wm_info.cacheline_size);
4197 cursor_sr = i965_cursor_wm_info.fifo_size -
4198 (entries + i965_cursor_wm_info.guard_size);
4200 if (cursor_sr > i965_cursor_wm_info.max_wm)
4201 cursor_sr = i965_cursor_wm_info.max_wm;
4203 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4204 "cursor %d\n", srwm, cursor_sr);
4206 if (IS_CRESTLINE(dev))
4207 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4209 /* Turn off self refresh if both pipes are enabled */
4210 if (IS_CRESTLINE(dev))
4211 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4215 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4218 /* 965 has limitations... */
4219 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4220 (8 << 16) | (8 << 8) | (8 << 0));
4221 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4222 /* update cursor SR watermark */
4223 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4226 static void i9xx_update_wm(struct drm_device *dev)
4228 struct drm_i915_private *dev_priv = dev->dev_private;
4229 const struct intel_watermark_params *wm_info;
4234 int planea_wm, planeb_wm;
4235 struct drm_crtc *crtc, *enabled = NULL;
4238 wm_info = &i945_wm_info;
4239 else if (!IS_GEN2(dev))
4240 wm_info = &i915_wm_info;
4242 wm_info = &i855_wm_info;
4244 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4245 crtc = intel_get_crtc_for_plane(dev, 0);
4246 if (crtc->enabled && crtc->fb) {
4247 planea_wm = intel_calculate_wm(crtc->mode.clock,
4249 crtc->fb->bits_per_pixel / 8,
4253 planea_wm = fifo_size - wm_info->guard_size;
4255 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4256 crtc = intel_get_crtc_for_plane(dev, 1);
4257 if (crtc->enabled && crtc->fb) {
4258 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4260 crtc->fb->bits_per_pixel / 8,
4262 if (enabled == NULL)
4267 planeb_wm = fifo_size - wm_info->guard_size;
4269 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4272 * Overlay gets an aggressive default since video jitter is bad.
4276 /* Play safe and disable self-refresh before adjusting watermarks. */
4277 if (IS_I945G(dev) || IS_I945GM(dev))
4278 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4279 else if (IS_I915GM(dev))
4280 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4282 /* Calc sr entries for one plane configs */
4283 if (HAS_FW_BLC(dev) && enabled) {
4284 /* self-refresh has much higher latency */
4285 static const int sr_latency_ns = 6000;
4286 int clock = enabled->mode.clock;
4287 int htotal = enabled->mode.htotal;
4288 int hdisplay = enabled->mode.hdisplay;
4289 int pixel_size = enabled->fb->bits_per_pixel / 8;
4290 unsigned long line_time_us;
4293 line_time_us = (htotal * 1000) / clock;
4295 /* Use ns/us then divide to preserve precision */
4296 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4297 pixel_size * hdisplay;
4298 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4299 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4300 srwm = wm_info->fifo_size - entries;
4304 if (IS_I945G(dev) || IS_I945GM(dev))
4305 I915_WRITE(FW_BLC_SELF,
4306 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4307 else if (IS_I915GM(dev))
4308 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4311 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4312 planea_wm, planeb_wm, cwm, srwm);
4314 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4315 fwater_hi = (cwm & 0x1f);
4317 /* Set request length to 8 cachelines per fetch */
4318 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4319 fwater_hi = fwater_hi | (1 << 8);
4321 I915_WRITE(FW_BLC, fwater_lo);
4322 I915_WRITE(FW_BLC2, fwater_hi);
4324 if (HAS_FW_BLC(dev)) {
4326 if (IS_I945G(dev) || IS_I945GM(dev))
4327 I915_WRITE(FW_BLC_SELF,
4328 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4329 else if (IS_I915GM(dev))
4330 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4331 DRM_DEBUG_KMS("memory self refresh enabled\n");
4333 DRM_DEBUG_KMS("memory self refresh disabled\n");
4337 static void i830_update_wm(struct drm_device *dev)
4339 struct drm_i915_private *dev_priv = dev->dev_private;
4340 struct drm_crtc *crtc;
4344 crtc = single_enabled_crtc(dev);
4348 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4349 dev_priv->display.get_fifo_size(dev, 0),
4350 crtc->fb->bits_per_pixel / 8,
4352 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4353 fwater_lo |= (3<<8) | planea_wm;
4355 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4357 I915_WRITE(FW_BLC, fwater_lo);
4360 #define ILK_LP0_PLANE_LATENCY 700
4361 #define ILK_LP0_CURSOR_LATENCY 1300
4364 * Check the wm result.
4366 * If any calculated watermark values is larger than the maximum value that
4367 * can be programmed into the associated watermark register, that watermark
4370 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4371 int fbc_wm, int display_wm, int cursor_wm,
4372 const struct intel_watermark_params *display,
4373 const struct intel_watermark_params *cursor)
4375 struct drm_i915_private *dev_priv = dev->dev_private;
4377 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4378 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4380 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4381 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4382 fbc_wm, SNB_FBC_MAX_SRWM, level);
4384 /* fbc has it's own way to disable FBC WM */
4385 I915_WRITE(DISP_ARB_CTL,
4386 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4390 if (display_wm > display->max_wm) {
4391 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4392 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4396 if (cursor_wm > cursor->max_wm) {
4397 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4398 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4402 if (!(fbc_wm || display_wm || cursor_wm)) {
4403 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4411 * Compute watermark values of WM[1-3],
4413 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4415 const struct intel_watermark_params *display,
4416 const struct intel_watermark_params *cursor,
4417 int *fbc_wm, int *display_wm, int *cursor_wm)
4419 struct drm_crtc *crtc;
4420 unsigned long line_time_us;
4421 int hdisplay, htotal, pixel_size, clock;
4422 int line_count, line_size;
4427 *fbc_wm = *display_wm = *cursor_wm = 0;
4431 crtc = intel_get_crtc_for_plane(dev, plane);
4432 hdisplay = crtc->mode.hdisplay;
4433 htotal = crtc->mode.htotal;
4434 clock = crtc->mode.clock;
4435 pixel_size = crtc->fb->bits_per_pixel / 8;
4437 line_time_us = (htotal * 1000) / clock;
4438 line_count = (latency_ns / line_time_us + 1000) / 1000;
4439 line_size = hdisplay * pixel_size;
4441 /* Use the minimum of the small and large buffer method for primary */
4442 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4443 large = line_count * line_size;
4445 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4446 *display_wm = entries + display->guard_size;
4450 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4452 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4454 /* calculate the self-refresh watermark for display cursor */
4455 entries = line_count * pixel_size * 64;
4456 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4457 *cursor_wm = entries + cursor->guard_size;
4459 return ironlake_check_srwm(dev, level,
4460 *fbc_wm, *display_wm, *cursor_wm,
4464 static void ironlake_update_wm(struct drm_device *dev)
4466 struct drm_i915_private *dev_priv = dev->dev_private;
4467 int fbc_wm, plane_wm, cursor_wm;
4468 unsigned int enabled;
4471 if (g4x_compute_wm0(dev, 0,
4472 &ironlake_display_wm_info,
4473 ILK_LP0_PLANE_LATENCY,
4474 &ironlake_cursor_wm_info,
4475 ILK_LP0_CURSOR_LATENCY,
4476 &plane_wm, &cursor_wm)) {
4477 I915_WRITE(WM0_PIPEA_ILK,
4478 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4479 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4480 " plane %d, " "cursor: %d\n",
4481 plane_wm, cursor_wm);
4485 if (g4x_compute_wm0(dev, 1,
4486 &ironlake_display_wm_info,
4487 ILK_LP0_PLANE_LATENCY,
4488 &ironlake_cursor_wm_info,
4489 ILK_LP0_CURSOR_LATENCY,
4490 &plane_wm, &cursor_wm)) {
4491 I915_WRITE(WM0_PIPEB_ILK,
4492 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4493 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4494 " plane %d, cursor: %d\n",
4495 plane_wm, cursor_wm);
4500 * Calculate and update the self-refresh watermark only when one
4501 * display plane is used.
4503 I915_WRITE(WM3_LP_ILK, 0);
4504 I915_WRITE(WM2_LP_ILK, 0);
4505 I915_WRITE(WM1_LP_ILK, 0);
4507 if (!single_plane_enabled(enabled))
4509 enabled = ffs(enabled) - 1;
4512 if (!ironlake_compute_srwm(dev, 1, enabled,
4513 ILK_READ_WM1_LATENCY() * 500,
4514 &ironlake_display_srwm_info,
4515 &ironlake_cursor_srwm_info,
4516 &fbc_wm, &plane_wm, &cursor_wm))
4519 I915_WRITE(WM1_LP_ILK,
4521 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4522 (fbc_wm << WM1_LP_FBC_SHIFT) |
4523 (plane_wm << WM1_LP_SR_SHIFT) |
4527 if (!ironlake_compute_srwm(dev, 2, enabled,
4528 ILK_READ_WM2_LATENCY() * 500,
4529 &ironlake_display_srwm_info,
4530 &ironlake_cursor_srwm_info,
4531 &fbc_wm, &plane_wm, &cursor_wm))
4534 I915_WRITE(WM2_LP_ILK,
4536 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4537 (fbc_wm << WM1_LP_FBC_SHIFT) |
4538 (plane_wm << WM1_LP_SR_SHIFT) |
4542 * WM3 is unsupported on ILK, probably because we don't have latency
4543 * data for that power state
4547 void sandybridge_update_wm(struct drm_device *dev)
4549 struct drm_i915_private *dev_priv = dev->dev_private;
4550 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4551 int fbc_wm, plane_wm, cursor_wm;
4552 unsigned int enabled;
4555 if (g4x_compute_wm0(dev, 0,
4556 &sandybridge_display_wm_info, latency,
4557 &sandybridge_cursor_wm_info, latency,
4558 &plane_wm, &cursor_wm)) {
4559 I915_WRITE(WM0_PIPEA_ILK,
4560 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4561 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4562 " plane %d, " "cursor: %d\n",
4563 plane_wm, cursor_wm);
4567 if (g4x_compute_wm0(dev, 1,
4568 &sandybridge_display_wm_info, latency,
4569 &sandybridge_cursor_wm_info, latency,
4570 &plane_wm, &cursor_wm)) {
4571 I915_WRITE(WM0_PIPEB_ILK,
4572 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4573 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4574 " plane %d, cursor: %d\n",
4575 plane_wm, cursor_wm);
4579 /* IVB has 3 pipes */
4580 if (IS_IVYBRIDGE(dev) &&
4581 g4x_compute_wm0(dev, 2,
4582 &sandybridge_display_wm_info, latency,
4583 &sandybridge_cursor_wm_info, latency,
4584 &plane_wm, &cursor_wm)) {
4585 I915_WRITE(WM0_PIPEC_IVB,
4586 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4587 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4588 " plane %d, cursor: %d\n",
4589 plane_wm, cursor_wm);
4594 * Calculate and update the self-refresh watermark only when one
4595 * display plane is used.
4597 * SNB support 3 levels of watermark.
4599 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4600 * and disabled in the descending order
4603 I915_WRITE(WM3_LP_ILK, 0);
4604 I915_WRITE(WM2_LP_ILK, 0);
4605 I915_WRITE(WM1_LP_ILK, 0);
4607 if (!single_plane_enabled(enabled) ||
4608 dev_priv->sprite_scaling_enabled)
4610 enabled = ffs(enabled) - 1;
4613 if (!ironlake_compute_srwm(dev, 1, enabled,
4614 SNB_READ_WM1_LATENCY() * 500,
4615 &sandybridge_display_srwm_info,
4616 &sandybridge_cursor_srwm_info,
4617 &fbc_wm, &plane_wm, &cursor_wm))
4620 I915_WRITE(WM1_LP_ILK,
4622 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4623 (fbc_wm << WM1_LP_FBC_SHIFT) |
4624 (plane_wm << WM1_LP_SR_SHIFT) |
4628 if (!ironlake_compute_srwm(dev, 2, enabled,
4629 SNB_READ_WM2_LATENCY() * 500,
4630 &sandybridge_display_srwm_info,
4631 &sandybridge_cursor_srwm_info,
4632 &fbc_wm, &plane_wm, &cursor_wm))
4635 I915_WRITE(WM2_LP_ILK,
4637 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4638 (fbc_wm << WM1_LP_FBC_SHIFT) |
4639 (plane_wm << WM1_LP_SR_SHIFT) |
4643 if (!ironlake_compute_srwm(dev, 3, enabled,
4644 SNB_READ_WM3_LATENCY() * 500,
4645 &sandybridge_display_srwm_info,
4646 &sandybridge_cursor_srwm_info,
4647 &fbc_wm, &plane_wm, &cursor_wm))
4650 I915_WRITE(WM3_LP_ILK,
4652 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4653 (fbc_wm << WM1_LP_FBC_SHIFT) |
4654 (plane_wm << WM1_LP_SR_SHIFT) |
4659 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4660 uint32_t sprite_width, int pixel_size,
4661 const struct intel_watermark_params *display,
4662 int display_latency_ns, int *sprite_wm)
4664 struct drm_crtc *crtc;
4666 int entries, tlb_miss;
4668 crtc = intel_get_crtc_for_plane(dev, plane);
4669 if (crtc->fb == NULL || !crtc->enabled) {
4670 *sprite_wm = display->guard_size;
4674 clock = crtc->mode.clock;
4676 /* Use the small buffer method to calculate the sprite watermark */
4677 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4678 tlb_miss = display->fifo_size*display->cacheline_size -
4681 entries += tlb_miss;
4682 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4683 *sprite_wm = entries + display->guard_size;
4684 if (*sprite_wm > (int)display->max_wm)
4685 *sprite_wm = display->max_wm;
4691 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4692 uint32_t sprite_width, int pixel_size,
4693 const struct intel_watermark_params *display,
4694 int latency_ns, int *sprite_wm)
4696 struct drm_crtc *crtc;
4697 unsigned long line_time_us;
4699 int line_count, line_size;
4708 crtc = intel_get_crtc_for_plane(dev, plane);
4709 clock = crtc->mode.clock;
4711 line_time_us = (sprite_width * 1000) / clock;
4712 line_count = (latency_ns / line_time_us + 1000) / 1000;
4713 line_size = sprite_width * pixel_size;
4715 /* Use the minimum of the small and large buffer method for primary */
4716 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4717 large = line_count * line_size;
4719 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4720 *sprite_wm = entries + display->guard_size;
4722 return *sprite_wm > 0x3ff ? false : true;
4725 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4726 uint32_t sprite_width, int pixel_size)
4728 struct drm_i915_private *dev_priv = dev->dev_private;
4729 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4735 reg = WM0_PIPEA_ILK;
4738 reg = WM0_PIPEB_ILK;
4741 reg = WM0_PIPEC_IVB;
4744 return; /* bad pipe */
4747 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4748 &sandybridge_display_wm_info,
4749 latency, &sprite_wm);
4751 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4756 I915_WRITE(reg, I915_READ(reg) | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4757 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4760 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4762 &sandybridge_display_srwm_info,
4763 SNB_READ_WM1_LATENCY() * 500,
4766 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4770 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4772 /* Only IVB has two more LP watermarks for sprite */
4773 if (!IS_IVYBRIDGE(dev))
4776 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4778 &sandybridge_display_srwm_info,
4779 SNB_READ_WM2_LATENCY() * 500,
4782 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4786 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4788 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4790 &sandybridge_display_srwm_info,
4791 SNB_READ_WM3_LATENCY() * 500,
4794 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4798 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4802 * intel_update_watermarks - update FIFO watermark values based on current modes
4804 * Calculate watermark values for the various WM regs based on current mode
4805 * and plane configuration.
4807 * There are several cases to deal with here:
4808 * - normal (i.e. non-self-refresh)
4809 * - self-refresh (SR) mode
4810 * - lines are large relative to FIFO size (buffer can hold up to 2)
4811 * - lines are small relative to FIFO size (buffer can hold more than 2
4812 * lines), so need to account for TLB latency
4814 * The normal calculation is:
4815 * watermark = dotclock * bytes per pixel * latency
4816 * where latency is platform & configuration dependent (we assume pessimal
4819 * The SR calculation is:
4820 * watermark = (trunc(latency/line time)+1) * surface width *
4823 * line time = htotal / dotclock
4824 * surface width = hdisplay for normal plane and 64 for cursor
4825 * and latency is assumed to be high, as above.
4827 * The final value programmed to the register should always be rounded up,
4828 * and include an extra 2 entries to account for clock crossings.
4830 * We don't use the sprite, so we can ignore that. And on Crestline we have
4831 * to set the non-SR watermarks to 8.
4833 static void intel_update_watermarks(struct drm_device *dev)
4835 struct drm_i915_private *dev_priv = dev->dev_private;
4837 if (dev_priv->display.update_wm)
4838 dev_priv->display.update_wm(dev);
4841 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4842 uint32_t sprite_width, int pixel_size)
4844 struct drm_i915_private *dev_priv = dev->dev_private;
4846 if (dev_priv->display.update_sprite_wm)
4847 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4851 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4853 if (i915_panel_use_ssc >= 0)
4854 return i915_panel_use_ssc != 0;
4855 return dev_priv->lvds_use_ssc
4856 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4860 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4861 * @crtc: CRTC structure
4862 * @mode: requested mode
4864 * A pipe may be connected to one or more outputs. Based on the depth of the
4865 * attached framebuffer, choose a good color depth to use on the pipe.
4867 * If possible, match the pipe depth to the fb depth. In some cases, this
4868 * isn't ideal, because the connected output supports a lesser or restricted
4869 * set of depths. Resolve that here:
4870 * LVDS typically supports only 6bpc, so clamp down in that case
4871 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4872 * Displays may support a restricted set as well, check EDID and clamp as
4874 * DP may want to dither down to 6bpc to fit larger modes
4877 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4878 * true if they don't match).
4880 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4881 unsigned int *pipe_bpp,
4882 struct drm_display_mode *mode)
4884 struct drm_device *dev = crtc->dev;
4885 struct drm_i915_private *dev_priv = dev->dev_private;
4886 struct drm_encoder *encoder;
4887 struct drm_connector *connector;
4888 unsigned int display_bpc = UINT_MAX, bpc;
4890 /* Walk the encoders & connectors on this crtc, get min bpc */
4891 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4892 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4894 if (encoder->crtc != crtc)
4897 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4898 unsigned int lvds_bpc;
4900 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4906 if (lvds_bpc < display_bpc) {
4907 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4908 display_bpc = lvds_bpc;
4913 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4914 /* Use VBT settings if we have an eDP panel */
4915 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4917 if (edp_bpc < display_bpc) {
4918 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4919 display_bpc = edp_bpc;
4924 /* Not one of the known troublemakers, check the EDID */
4925 list_for_each_entry(connector, &dev->mode_config.connector_list,
4927 if (connector->encoder != encoder)
4930 /* Don't use an invalid EDID bpc value */
4931 if (connector->display_info.bpc &&
4932 connector->display_info.bpc < display_bpc) {
4933 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4934 display_bpc = connector->display_info.bpc;
4939 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4940 * through, clamp it down. (Note: >12bpc will be caught below.)
4942 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4943 if (display_bpc > 8 && display_bpc < 12) {
4944 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4947 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4953 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4954 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4959 * We could just drive the pipe at the highest bpc all the time and
4960 * enable dithering as needed, but that costs bandwidth. So choose
4961 * the minimum value that expresses the full color range of the fb but
4962 * also stays within the max display bpc discovered above.
4965 switch (crtc->fb->depth) {
4967 bpc = 8; /* since we go through a colormap */
4971 bpc = 6; /* min is 18bpp */
4983 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4984 bpc = min((unsigned int)8, display_bpc);
4988 display_bpc = min(display_bpc, bpc);
4990 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4993 *pipe_bpp = display_bpc * 3;
4995 return display_bpc != bpc;
4998 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5000 struct drm_device *dev = crtc->dev;
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5004 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5005 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5006 refclk = dev_priv->lvds_ssc_freq * 1000;
5007 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5009 } else if (!IS_GEN2(dev)) {
5018 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5019 intel_clock_t *clock)
5021 /* SDVO TV has fixed PLL values depend on its clock range,
5022 this mirrors vbios setting. */
5023 if (adjusted_mode->clock >= 100000
5024 && adjusted_mode->clock < 140500) {
5030 } else if (adjusted_mode->clock >= 140500
5031 && adjusted_mode->clock <= 200000) {
5040 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5041 intel_clock_t *clock,
5042 intel_clock_t *reduced_clock)
5044 struct drm_device *dev = crtc->dev;
5045 struct drm_i915_private *dev_priv = dev->dev_private;
5046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5047 int pipe = intel_crtc->pipe;
5050 if (IS_PINEVIEW(dev)) {
5051 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5053 fp2 = (1 << reduced_clock->n) << 16 |
5054 reduced_clock->m1 << 8 | reduced_clock->m2;
5056 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5058 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5062 I915_WRITE(FP0(pipe), fp);
5064 intel_crtc->lowfreq_avail = false;
5065 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5066 reduced_clock && i915_powersave) {
5067 I915_WRITE(FP1(pipe), fp2);
5068 intel_crtc->lowfreq_avail = true;
5070 I915_WRITE(FP1(pipe), fp);
5074 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5075 struct drm_display_mode *mode,
5076 struct drm_display_mode *adjusted_mode,
5078 struct drm_framebuffer *old_fb)
5080 struct drm_device *dev = crtc->dev;
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5083 int pipe = intel_crtc->pipe;
5084 int plane = intel_crtc->plane;
5085 int refclk, num_connectors = 0;
5086 intel_clock_t clock, reduced_clock;
5087 u32 dpll, dspcntr, pipeconf;
5088 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5089 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5090 struct drm_mode_config *mode_config = &dev->mode_config;
5091 struct intel_encoder *encoder;
5092 const intel_limit_t *limit;
5097 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5098 if (encoder->base.crtc != crtc)
5101 switch (encoder->type) {
5102 case INTEL_OUTPUT_LVDS:
5105 case INTEL_OUTPUT_SDVO:
5106 case INTEL_OUTPUT_HDMI:
5108 if (encoder->needs_tv_clock)
5111 case INTEL_OUTPUT_DVO:
5114 case INTEL_OUTPUT_TVOUT:
5117 case INTEL_OUTPUT_ANALOG:
5120 case INTEL_OUTPUT_DISPLAYPORT:
5128 refclk = i9xx_get_refclk(crtc, num_connectors);
5131 * Returns a set of divisors for the desired target clock with the given
5132 * refclk, or FALSE. The returned values represent the clock equation:
5133 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5135 limit = intel_limit(crtc, refclk);
5136 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5139 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5143 /* Ensure that the cursor is valid for the new mode before changing... */
5144 intel_crtc_update_cursor(crtc, true);
5146 if (is_lvds && dev_priv->lvds_downclock_avail) {
5148 * Ensure we match the reduced clock's P to the target clock.
5149 * If the clocks don't match, we can't switch the display clock
5150 * by using the FP0/FP1. In such case we will disable the LVDS
5151 * downclock feature.
5153 has_reduced_clock = limit->find_pll(limit, crtc,
5154 dev_priv->lvds_downclock,
5160 if (is_sdvo && is_tv)
5161 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5163 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5164 &reduced_clock : NULL);
5166 dpll = DPLL_VGA_MODE_DIS;
5168 if (!IS_GEN2(dev)) {
5170 dpll |= DPLLB_MODE_LVDS;
5172 dpll |= DPLLB_MODE_DAC_SERIAL;
5174 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5175 if (pixel_multiplier > 1) {
5176 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5177 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5179 dpll |= DPLL_DVO_HIGH_SPEED;
5182 dpll |= DPLL_DVO_HIGH_SPEED;
5184 /* compute bitmask from p1 value */
5185 if (IS_PINEVIEW(dev))
5186 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5188 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5189 if (IS_G4X(dev) && has_reduced_clock)
5190 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5194 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5197 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5200 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5203 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5206 if (INTEL_INFO(dev)->gen >= 4)
5207 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5210 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5213 dpll |= PLL_P1_DIVIDE_BY_TWO;
5215 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5217 dpll |= PLL_P2_DIVIDE_BY_4;
5221 if (is_sdvo && is_tv)
5222 dpll |= PLL_REF_INPUT_TVCLKINBC;
5224 /* XXX: just matching BIOS for now */
5225 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5227 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5228 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5230 dpll |= PLL_REF_INPUT_DREFCLK;
5232 /* setup pipeconf */
5233 pipeconf = I915_READ(PIPECONF(pipe));
5235 /* Set up the display plane register */
5236 dspcntr = DISPPLANE_GAMMA_ENABLE;
5239 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5241 dspcntr |= DISPPLANE_SEL_PIPE_B;
5243 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5244 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5247 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5251 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5252 pipeconf |= PIPECONF_DOUBLE_WIDE;
5254 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5257 /* default to 8bpc */
5258 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5260 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5261 pipeconf |= PIPECONF_BPP_6 |
5262 PIPECONF_DITHER_EN |
5263 PIPECONF_DITHER_TYPE_SP;
5267 dpll |= DPLL_VCO_ENABLE;
5269 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5270 drm_mode_debug_printmodeline(mode);
5272 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5274 POSTING_READ(DPLL(pipe));
5277 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5278 * This is an exception to the general rule that mode_set doesn't turn
5282 temp = I915_READ(LVDS);
5283 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5285 temp |= LVDS_PIPEB_SELECT;
5287 temp &= ~LVDS_PIPEB_SELECT;
5289 /* set the corresponsding LVDS_BORDER bit */
5290 temp |= dev_priv->lvds_border_bits;
5291 /* Set the B0-B3 data pairs corresponding to whether we're going to
5292 * set the DPLLs for dual-channel mode or not.
5295 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5297 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5299 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5300 * appropriately here, but we need to look more thoroughly into how
5301 * panels behave in the two modes.
5303 /* set the dithering flag on LVDS as needed */
5304 if (INTEL_INFO(dev)->gen >= 4) {
5305 if (dev_priv->lvds_dither)
5306 temp |= LVDS_ENABLE_DITHER;
5308 temp &= ~LVDS_ENABLE_DITHER;
5310 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5311 lvds_sync |= LVDS_HSYNC_POLARITY;
5312 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5313 lvds_sync |= LVDS_VSYNC_POLARITY;
5314 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5316 char flags[2] = "-+";
5317 DRM_INFO("Changing LVDS panel from "
5318 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5319 flags[!(temp & LVDS_HSYNC_POLARITY)],
5320 flags[!(temp & LVDS_VSYNC_POLARITY)],
5321 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5322 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5323 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5326 I915_WRITE(LVDS, temp);
5330 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5333 I915_WRITE(DPLL(pipe), dpll);
5335 /* Wait for the clocks to stabilize. */
5336 POSTING_READ(DPLL(pipe));
5339 if (INTEL_INFO(dev)->gen >= 4) {
5342 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5344 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5348 I915_WRITE(DPLL_MD(pipe), temp);
5350 /* The pixel multiplier can only be updated once the
5351 * DPLL is enabled and the clocks are stable.
5353 * So write it again.
5355 I915_WRITE(DPLL(pipe), dpll);
5358 if (HAS_PIPE_CXSR(dev)) {
5359 if (intel_crtc->lowfreq_avail) {
5360 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5361 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5363 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5364 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5368 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5369 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5370 /* the chip adds 2 halflines automatically */
5371 adjusted_mode->crtc_vdisplay -= 1;
5372 adjusted_mode->crtc_vtotal -= 1;
5373 adjusted_mode->crtc_vblank_start -= 1;
5374 adjusted_mode->crtc_vblank_end -= 1;
5375 adjusted_mode->crtc_vsync_end -= 1;
5376 adjusted_mode->crtc_vsync_start -= 1;
5378 pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
5380 I915_WRITE(HTOTAL(pipe),
5381 (adjusted_mode->crtc_hdisplay - 1) |
5382 ((adjusted_mode->crtc_htotal - 1) << 16));
5383 I915_WRITE(HBLANK(pipe),
5384 (adjusted_mode->crtc_hblank_start - 1) |
5385 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5386 I915_WRITE(HSYNC(pipe),
5387 (adjusted_mode->crtc_hsync_start - 1) |
5388 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5390 I915_WRITE(VTOTAL(pipe),
5391 (adjusted_mode->crtc_vdisplay - 1) |
5392 ((adjusted_mode->crtc_vtotal - 1) << 16));
5393 I915_WRITE(VBLANK(pipe),
5394 (adjusted_mode->crtc_vblank_start - 1) |
5395 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5396 I915_WRITE(VSYNC(pipe),
5397 (adjusted_mode->crtc_vsync_start - 1) |
5398 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5400 /* pipesrc and dspsize control the size that is scaled from,
5401 * which should always be the user's requested size.
5403 I915_WRITE(DSPSIZE(plane),
5404 ((mode->vdisplay - 1) << 16) |
5405 (mode->hdisplay - 1));
5406 I915_WRITE(DSPPOS(plane), 0);
5407 I915_WRITE(PIPESRC(pipe),
5408 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5410 I915_WRITE(PIPECONF(pipe), pipeconf);
5411 POSTING_READ(PIPECONF(pipe));
5412 intel_enable_pipe(dev_priv, pipe, false);
5414 intel_wait_for_vblank(dev, pipe);
5416 I915_WRITE(DSPCNTR(plane), dspcntr);
5417 POSTING_READ(DSPCNTR(plane));
5418 intel_enable_plane(dev_priv, plane, pipe);
5420 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5422 intel_update_watermarks(dev);
5428 * Initialize reference clocks when the driver loads
5430 void ironlake_init_pch_refclk(struct drm_device *dev)
5432 struct drm_i915_private *dev_priv = dev->dev_private;
5433 struct drm_mode_config *mode_config = &dev->mode_config;
5434 struct intel_encoder *encoder;
5436 bool has_lvds = false;
5437 bool has_cpu_edp = false;
5438 bool has_pch_edp = false;
5439 bool has_panel = false;
5440 bool has_ck505 = false;
5441 bool can_ssc = false;
5443 /* We need to take the global config into account */
5444 list_for_each_entry(encoder, &mode_config->encoder_list,
5446 switch (encoder->type) {
5447 case INTEL_OUTPUT_LVDS:
5451 case INTEL_OUTPUT_EDP:
5453 if (intel_encoder_is_pch_edp(&encoder->base))
5461 if (HAS_PCH_IBX(dev)) {
5462 has_ck505 = dev_priv->display_clock_mode;
5463 can_ssc = has_ck505;
5469 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5470 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5473 /* Ironlake: try to setup display ref clock before DPLL
5474 * enabling. This is only under driver's control after
5475 * PCH B stepping, previous chipset stepping should be
5476 * ignoring this setting.
5478 temp = I915_READ(PCH_DREF_CONTROL);
5479 /* Always enable nonspread source */
5480 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5483 temp |= DREF_NONSPREAD_CK505_ENABLE;
5485 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5488 temp &= ~DREF_SSC_SOURCE_MASK;
5489 temp |= DREF_SSC_SOURCE_ENABLE;
5491 /* SSC must be turned on before enabling the CPU output */
5492 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5493 DRM_DEBUG_KMS("Using SSC on panel\n");
5494 temp |= DREF_SSC1_ENABLE;
5497 /* Get SSC going before enabling the outputs */
5498 I915_WRITE(PCH_DREF_CONTROL, temp);
5499 POSTING_READ(PCH_DREF_CONTROL);
5502 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5504 /* Enable CPU source on CPU attached eDP */
5506 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5507 DRM_DEBUG_KMS("Using SSC on eDP\n");
5508 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5511 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5513 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5515 I915_WRITE(PCH_DREF_CONTROL, temp);
5516 POSTING_READ(PCH_DREF_CONTROL);
5519 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5521 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5523 /* Turn off CPU output */
5524 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5526 I915_WRITE(PCH_DREF_CONTROL, temp);
5527 POSTING_READ(PCH_DREF_CONTROL);
5530 /* Turn off the SSC source */
5531 temp &= ~DREF_SSC_SOURCE_MASK;
5532 temp |= DREF_SSC_SOURCE_DISABLE;
5535 temp &= ~ DREF_SSC1_ENABLE;
5537 I915_WRITE(PCH_DREF_CONTROL, temp);
5538 POSTING_READ(PCH_DREF_CONTROL);
5543 static int ironlake_get_refclk(struct drm_crtc *crtc)
5545 struct drm_device *dev = crtc->dev;
5546 struct drm_i915_private *dev_priv = dev->dev_private;
5547 struct intel_encoder *encoder;
5548 struct drm_mode_config *mode_config = &dev->mode_config;
5549 struct intel_encoder *edp_encoder = NULL;
5550 int num_connectors = 0;
5551 bool is_lvds = false;
5553 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5554 if (encoder->base.crtc != crtc)
5557 switch (encoder->type) {
5558 case INTEL_OUTPUT_LVDS:
5561 case INTEL_OUTPUT_EDP:
5562 edp_encoder = encoder;
5568 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5569 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5570 dev_priv->lvds_ssc_freq);
5571 return dev_priv->lvds_ssc_freq * 1000;
5577 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5578 struct drm_display_mode *mode,
5579 struct drm_display_mode *adjusted_mode,
5581 struct drm_framebuffer *old_fb)
5583 struct drm_device *dev = crtc->dev;
5584 struct drm_i915_private *dev_priv = dev->dev_private;
5585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5586 int pipe = intel_crtc->pipe;
5587 int plane = intel_crtc->plane;
5588 int refclk, num_connectors = 0;
5589 intel_clock_t clock, reduced_clock;
5590 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5591 bool ok, has_reduced_clock = false, is_sdvo = false;
5592 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5593 struct intel_encoder *has_edp_encoder = NULL;
5594 struct drm_mode_config *mode_config = &dev->mode_config;
5595 struct intel_encoder *encoder;
5596 const intel_limit_t *limit;
5598 struct fdi_m_n m_n = {0};
5601 int target_clock, pixel_multiplier, lane, link_bw, factor;
5602 unsigned int pipe_bpp;
5605 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5606 if (encoder->base.crtc != crtc)
5609 switch (encoder->type) {
5610 case INTEL_OUTPUT_LVDS:
5613 case INTEL_OUTPUT_SDVO:
5614 case INTEL_OUTPUT_HDMI:
5616 if (encoder->needs_tv_clock)
5619 case INTEL_OUTPUT_TVOUT:
5622 case INTEL_OUTPUT_ANALOG:
5625 case INTEL_OUTPUT_DISPLAYPORT:
5628 case INTEL_OUTPUT_EDP:
5629 has_edp_encoder = encoder;
5636 refclk = ironlake_get_refclk(crtc);
5639 * Returns a set of divisors for the desired target clock with the given
5640 * refclk, or FALSE. The returned values represent the clock equation:
5641 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5643 limit = intel_limit(crtc, refclk);
5644 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5647 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5651 /* Ensure that the cursor is valid for the new mode before changing... */
5652 intel_crtc_update_cursor(crtc, true);
5654 if (is_lvds && dev_priv->lvds_downclock_avail) {
5656 * Ensure we match the reduced clock's P to the target clock.
5657 * If the clocks don't match, we can't switch the display clock
5658 * by using the FP0/FP1. In such case we will disable the LVDS
5659 * downclock feature.
5661 has_reduced_clock = limit->find_pll(limit, crtc,
5662 dev_priv->lvds_downclock,
5667 /* SDVO TV has fixed PLL values depend on its clock range,
5668 this mirrors vbios setting. */
5669 if (is_sdvo && is_tv) {
5670 if (adjusted_mode->clock >= 100000
5671 && adjusted_mode->clock < 140500) {
5677 } else if (adjusted_mode->clock >= 140500
5678 && adjusted_mode->clock <= 200000) {
5688 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5690 /* CPU eDP doesn't require FDI link, so just set DP M/N
5691 according to current link config */
5692 if (has_edp_encoder &&
5693 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5694 target_clock = mode->clock;
5695 intel_edp_link_config(has_edp_encoder,
5698 /* [e]DP over FDI requires target mode clock
5699 instead of link clock */
5700 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5701 target_clock = mode->clock;
5703 target_clock = adjusted_mode->clock;
5705 /* FDI is a binary signal running at ~2.7GHz, encoding
5706 * each output octet as 10 bits. The actual frequency
5707 * is stored as a divider into a 100MHz clock, and the
5708 * mode pixel clock is stored in units of 1KHz.
5709 * Hence the bw of each lane in terms of the mode signal
5712 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5715 /* determine panel color depth */
5716 temp = I915_READ(PIPECONF(pipe));
5717 temp &= ~PIPE_BPC_MASK;
5718 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5733 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5740 intel_crtc->bpp = pipe_bpp;
5741 I915_WRITE(PIPECONF(pipe), temp);
5745 * Account for spread spectrum to avoid
5746 * oversubscribing the link. Max center spread
5747 * is 2.5%; use 5% for safety's sake.
5749 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5750 lane = bps / (link_bw * 8) + 1;
5753 intel_crtc->fdi_lanes = lane;
5755 if (pixel_multiplier > 1)
5756 link_bw *= pixel_multiplier;
5757 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5760 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5761 if (has_reduced_clock)
5762 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5765 /* Enable autotuning of the PLL clock (if permissible) */
5768 if ((intel_panel_use_ssc(dev_priv) &&
5769 dev_priv->lvds_ssc_freq == 100) ||
5770 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5772 } else if (is_sdvo && is_tv)
5775 if (clock.m < factor * clock.n)
5781 dpll |= DPLLB_MODE_LVDS;
5783 dpll |= DPLLB_MODE_DAC_SERIAL;
5785 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5786 if (pixel_multiplier > 1) {
5787 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5789 dpll |= DPLL_DVO_HIGH_SPEED;
5791 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5792 dpll |= DPLL_DVO_HIGH_SPEED;
5794 /* compute bitmask from p1 value */
5795 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5797 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5801 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5804 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5807 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5810 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5814 if (is_sdvo && is_tv)
5815 dpll |= PLL_REF_INPUT_TVCLKINBC;
5817 /* XXX: just matching BIOS for now */
5818 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5820 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5821 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5823 dpll |= PLL_REF_INPUT_DREFCLK;
5825 /* setup pipeconf */
5826 pipeconf = I915_READ(PIPECONF(pipe));
5828 /* Set up the display plane register */
5829 dspcntr = DISPPLANE_GAMMA_ENABLE;
5831 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5832 drm_mode_debug_printmodeline(mode);
5834 /* PCH eDP needs FDI, but CPU eDP does not */
5835 if (!intel_crtc->no_pll) {
5836 if (!has_edp_encoder ||
5837 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5838 I915_WRITE(PCH_FP0(pipe), fp);
5839 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5841 POSTING_READ(PCH_DPLL(pipe));
5845 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5846 fp == I915_READ(PCH_FP0(0))) {
5847 intel_crtc->use_pll_a = true;
5848 DRM_DEBUG_KMS("using pipe a dpll\n");
5849 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5850 fp == I915_READ(PCH_FP0(1))) {
5851 intel_crtc->use_pll_a = false;
5852 DRM_DEBUG_KMS("using pipe b dpll\n");
5854 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5859 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5860 * This is an exception to the general rule that mode_set doesn't turn
5864 temp = I915_READ(PCH_LVDS);
5865 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5866 if (HAS_PCH_CPT(dev)) {
5867 temp &= ~PORT_TRANS_SEL_MASK;
5868 temp |= PORT_TRANS_SEL_CPT(pipe);
5871 temp |= LVDS_PIPEB_SELECT;
5873 temp &= ~LVDS_PIPEB_SELECT;
5876 /* set the corresponsding LVDS_BORDER bit */
5877 temp |= dev_priv->lvds_border_bits;
5878 /* Set the B0-B3 data pairs corresponding to whether we're going to
5879 * set the DPLLs for dual-channel mode or not.
5882 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5884 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5886 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5887 * appropriately here, but we need to look more thoroughly into how
5888 * panels behave in the two modes.
5890 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5891 lvds_sync |= LVDS_HSYNC_POLARITY;
5892 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5893 lvds_sync |= LVDS_VSYNC_POLARITY;
5894 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5896 char flags[2] = "-+";
5897 DRM_INFO("Changing LVDS panel from "
5898 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5899 flags[!(temp & LVDS_HSYNC_POLARITY)],
5900 flags[!(temp & LVDS_VSYNC_POLARITY)],
5901 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5902 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5903 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5906 I915_WRITE(PCH_LVDS, temp);
5909 pipeconf &= ~PIPECONF_DITHER_EN;
5910 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5911 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5912 pipeconf |= PIPECONF_DITHER_EN;
5913 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5915 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5916 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5918 /* For non-DP output, clear any trans DP clock recovery setting.*/
5919 I915_WRITE(TRANSDATA_M1(pipe), 0);
5920 I915_WRITE(TRANSDATA_N1(pipe), 0);
5921 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5922 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5925 if (!intel_crtc->no_pll &&
5926 (!has_edp_encoder ||
5927 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5928 I915_WRITE(PCH_DPLL(pipe), dpll);
5930 /* Wait for the clocks to stabilize. */
5931 POSTING_READ(PCH_DPLL(pipe));
5934 /* The pixel multiplier can only be updated once the
5935 * DPLL is enabled and the clocks are stable.
5937 * So write it again.
5939 I915_WRITE(PCH_DPLL(pipe), dpll);
5942 intel_crtc->lowfreq_avail = false;
5943 if (!intel_crtc->no_pll) {
5944 if (is_lvds && has_reduced_clock && i915_powersave) {
5945 I915_WRITE(PCH_FP1(pipe), fp2);
5946 intel_crtc->lowfreq_avail = true;
5947 if (HAS_PIPE_CXSR(dev)) {
5948 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5949 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5952 I915_WRITE(PCH_FP1(pipe), fp);
5953 if (HAS_PIPE_CXSR(dev)) {
5954 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5955 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5960 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5961 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5962 /* the chip adds 2 halflines automatically */
5963 adjusted_mode->crtc_vdisplay -= 1;
5964 adjusted_mode->crtc_vtotal -= 1;
5965 adjusted_mode->crtc_vblank_start -= 1;
5966 adjusted_mode->crtc_vblank_end -= 1;
5967 adjusted_mode->crtc_vsync_end -= 1;
5968 adjusted_mode->crtc_vsync_start -= 1;
5970 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5972 I915_WRITE(HTOTAL(pipe),
5973 (adjusted_mode->crtc_hdisplay - 1) |
5974 ((adjusted_mode->crtc_htotal - 1) << 16));
5975 I915_WRITE(HBLANK(pipe),
5976 (adjusted_mode->crtc_hblank_start - 1) |
5977 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5978 I915_WRITE(HSYNC(pipe),
5979 (adjusted_mode->crtc_hsync_start - 1) |
5980 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5982 I915_WRITE(VTOTAL(pipe),
5983 (adjusted_mode->crtc_vdisplay - 1) |
5984 ((adjusted_mode->crtc_vtotal - 1) << 16));
5985 I915_WRITE(VBLANK(pipe),
5986 (adjusted_mode->crtc_vblank_start - 1) |
5987 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5988 I915_WRITE(VSYNC(pipe),
5989 (adjusted_mode->crtc_vsync_start - 1) |
5990 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5992 /* pipesrc controls the size that is scaled from, which should
5993 * always be the user's requested size.
5995 I915_WRITE(PIPESRC(pipe),
5996 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5998 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5999 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6000 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6001 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6003 if (has_edp_encoder &&
6004 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6005 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6008 I915_WRITE(PIPECONF(pipe), pipeconf);
6009 POSTING_READ(PIPECONF(pipe));
6011 intel_wait_for_vblank(dev, pipe);
6014 /* enable address swizzle for tiling buffer */
6015 temp = I915_READ(DISP_ARB_CTL);
6016 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
6019 I915_WRITE(DSPCNTR(plane), dspcntr);
6020 POSTING_READ(DSPCNTR(plane));
6022 ret = intel_pipe_set_base(crtc, x, y, old_fb);
6024 intel_update_watermarks(dev);
6029 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6030 struct drm_display_mode *mode,
6031 struct drm_display_mode *adjusted_mode,
6033 struct drm_framebuffer *old_fb)
6035 struct drm_device *dev = crtc->dev;
6036 struct drm_i915_private *dev_priv = dev->dev_private;
6037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6038 int pipe = intel_crtc->pipe;
6041 drm_vblank_pre_modeset(dev, pipe);
6043 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6045 drm_vblank_post_modeset(dev, pipe);
6048 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6050 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6055 static bool intel_eld_uptodate(struct drm_connector *connector,
6056 int reg_eldv, uint32_t bits_eldv,
6057 int reg_elda, uint32_t bits_elda,
6060 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6061 uint8_t *eld = connector->eld;
6064 i = I915_READ(reg_eldv);
6073 i = I915_READ(reg_elda);
6075 I915_WRITE(reg_elda, i);
6077 for (i = 0; i < eld[2]; i++)
6078 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6084 static void g4x_write_eld(struct drm_connector *connector,
6085 struct drm_crtc *crtc)
6087 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6088 uint8_t *eld = connector->eld;
6093 i = I915_READ(G4X_AUD_VID_DID);
6095 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6096 eldv = G4X_ELDV_DEVCL_DEVBLC;
6098 eldv = G4X_ELDV_DEVCTG;
6100 if (intel_eld_uptodate(connector,
6101 G4X_AUD_CNTL_ST, eldv,
6102 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6103 G4X_HDMIW_HDMIEDID))
6106 i = I915_READ(G4X_AUD_CNTL_ST);
6107 i &= ~(eldv | G4X_ELD_ADDR);
6108 len = (i >> 9) & 0x1f; /* ELD buffer size */
6109 I915_WRITE(G4X_AUD_CNTL_ST, i);
6114 len = min_t(uint8_t, eld[2], len);
6115 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6116 for (i = 0; i < len; i++)
6117 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6119 i = I915_READ(G4X_AUD_CNTL_ST);
6121 I915_WRITE(G4X_AUD_CNTL_ST, i);
6124 static void ironlake_write_eld(struct drm_connector *connector,
6125 struct drm_crtc *crtc)
6127 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6128 uint8_t *eld = connector->eld;
6136 if (HAS_PCH_IBX(connector->dev)) {
6137 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6138 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6139 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6141 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6142 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6143 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6146 i = to_intel_crtc(crtc)->pipe;
6147 hdmiw_hdmiedid += i * 0x100;
6148 aud_cntl_st += i * 0x100;
6150 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6152 i = I915_READ(aud_cntl_st);
6153 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6155 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6156 /* operate blindly on all ports */
6157 eldv = IBX_ELD_VALIDB;
6158 eldv |= IBX_ELD_VALIDB << 4;
6159 eldv |= IBX_ELD_VALIDB << 8;
6161 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6162 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6165 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6166 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6167 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6170 if (intel_eld_uptodate(connector,
6171 aud_cntrl_st2, eldv,
6172 aud_cntl_st, IBX_ELD_ADDRESS,
6176 i = I915_READ(aud_cntrl_st2);
6178 I915_WRITE(aud_cntrl_st2, i);
6183 i = I915_READ(aud_cntl_st);
6184 i &= ~IBX_ELD_ADDRESS;
6185 I915_WRITE(aud_cntl_st, i);
6187 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6188 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6189 for (i = 0; i < len; i++)
6190 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6192 i = I915_READ(aud_cntrl_st2);
6194 I915_WRITE(aud_cntrl_st2, i);
6197 void intel_write_eld(struct drm_encoder *encoder,
6198 struct drm_display_mode *mode)
6200 struct drm_crtc *crtc = encoder->crtc;
6201 struct drm_connector *connector;
6202 struct drm_device *dev = encoder->dev;
6203 struct drm_i915_private *dev_priv = dev->dev_private;
6205 connector = drm_select_eld(encoder, mode);
6209 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6211 drm_get_connector_name(connector),
6212 connector->encoder->base.id,
6213 drm_get_encoder_name(connector->encoder));
6215 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6217 if (dev_priv->display.write_eld)
6218 dev_priv->display.write_eld(connector, crtc);
6221 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6222 void intel_crtc_load_lut(struct drm_crtc *crtc)
6224 struct drm_device *dev = crtc->dev;
6225 struct drm_i915_private *dev_priv = dev->dev_private;
6226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6227 int palreg = PALETTE(intel_crtc->pipe);
6230 /* The clocks have to be on to load the palette. */
6234 /* use legacy palette for Ironlake */
6235 if (HAS_PCH_SPLIT(dev))
6236 palreg = LGC_PALETTE(intel_crtc->pipe);
6238 for (i = 0; i < 256; i++) {
6239 I915_WRITE(palreg + 4 * i,
6240 (intel_crtc->lut_r[i] << 16) |
6241 (intel_crtc->lut_g[i] << 8) |
6242 intel_crtc->lut_b[i]);
6246 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6248 struct drm_device *dev = crtc->dev;
6249 struct drm_i915_private *dev_priv = dev->dev_private;
6250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6251 bool visible = base != 0;
6254 if (intel_crtc->cursor_visible == visible)
6257 cntl = I915_READ(_CURACNTR);
6259 /* On these chipsets we can only modify the base whilst
6260 * the cursor is disabled.
6262 I915_WRITE(_CURABASE, base);
6264 cntl &= ~(CURSOR_FORMAT_MASK);
6265 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6266 cntl |= CURSOR_ENABLE |
6267 CURSOR_GAMMA_ENABLE |
6270 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6271 I915_WRITE(_CURACNTR, cntl);
6273 intel_crtc->cursor_visible = visible;
6276 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6278 struct drm_device *dev = crtc->dev;
6279 struct drm_i915_private *dev_priv = dev->dev_private;
6280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6281 int pipe = intel_crtc->pipe;
6282 bool visible = base != 0;
6284 if (intel_crtc->cursor_visible != visible) {
6285 uint32_t cntl = I915_READ(CURCNTR(pipe));
6287 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6288 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6289 cntl |= pipe << 28; /* Connect to correct pipe */
6291 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6292 cntl |= CURSOR_MODE_DISABLE;
6294 I915_WRITE(CURCNTR(pipe), cntl);
6296 intel_crtc->cursor_visible = visible;
6298 /* and commit changes on next vblank */
6299 I915_WRITE(CURBASE(pipe), base);
6302 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6304 struct drm_device *dev = crtc->dev;
6305 struct drm_i915_private *dev_priv = dev->dev_private;
6306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6307 int pipe = intel_crtc->pipe;
6308 bool visible = base != 0;
6310 if (intel_crtc->cursor_visible != visible) {
6311 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6313 cntl &= ~CURSOR_MODE;
6314 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6316 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6317 cntl |= CURSOR_MODE_DISABLE;
6319 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6321 intel_crtc->cursor_visible = visible;
6323 /* and commit changes on next vblank */
6324 I915_WRITE(CURBASE_IVB(pipe), base);
6327 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6328 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6331 struct drm_device *dev = crtc->dev;
6332 struct drm_i915_private *dev_priv = dev->dev_private;
6333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6334 int pipe = intel_crtc->pipe;
6335 int x = intel_crtc->cursor_x;
6336 int y = intel_crtc->cursor_y;
6342 if (on && crtc->enabled && crtc->fb) {
6343 base = intel_crtc->cursor_addr;
6344 if (x > (int) crtc->fb->width)
6347 if (y > (int) crtc->fb->height)
6353 if (x + intel_crtc->cursor_width < 0)
6356 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6359 pos |= x << CURSOR_X_SHIFT;
6362 if (y + intel_crtc->cursor_height < 0)
6365 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6368 pos |= y << CURSOR_Y_SHIFT;
6370 visible = base != 0;
6371 if (!visible && !intel_crtc->cursor_visible)
6374 if (IS_IVYBRIDGE(dev)) {
6375 I915_WRITE(CURPOS_IVB(pipe), pos);
6376 ivb_update_cursor(crtc, base);
6378 I915_WRITE(CURPOS(pipe), pos);
6379 if (IS_845G(dev) || IS_I865G(dev))
6380 i845_update_cursor(crtc, base);
6382 i9xx_update_cursor(crtc, base);
6386 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6389 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6390 struct drm_file *file,
6392 uint32_t width, uint32_t height)
6394 struct drm_device *dev = crtc->dev;
6395 struct drm_i915_private *dev_priv = dev->dev_private;
6396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6397 struct drm_i915_gem_object *obj;
6401 DRM_DEBUG_KMS("\n");
6403 /* if we want to turn off the cursor ignore width and height */
6405 DRM_DEBUG_KMS("cursor off\n");
6408 mutex_lock(&dev->struct_mutex);
6412 /* Currently we only support 64x64 cursors */
6413 if (width != 64 || height != 64) {
6414 DRM_ERROR("we currently only support 64x64 cursors\n");
6418 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6419 if (&obj->base == NULL)
6422 if (obj->base.size < width * height * 4) {
6423 DRM_ERROR("buffer is to small\n");
6428 /* we only need to pin inside GTT if cursor is non-phy */
6429 mutex_lock(&dev->struct_mutex);
6430 if (!dev_priv->info->cursor_needs_physical) {
6431 if (obj->tiling_mode) {
6432 DRM_ERROR("cursor cannot be tiled\n");
6437 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6439 DRM_ERROR("failed to move cursor bo into the GTT\n");
6443 ret = i915_gem_object_put_fence(obj);
6445 DRM_ERROR("failed to release fence for cursor");
6449 addr = obj->gtt_offset;
6451 int align = IS_I830(dev) ? 16 * 1024 : 256;
6452 ret = i915_gem_attach_phys_object(dev, obj,
6453 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6456 DRM_ERROR("failed to attach phys object\n");
6459 addr = obj->phys_obj->handle->busaddr;
6463 I915_WRITE(CURSIZE, (height << 12) | width);
6466 if (intel_crtc->cursor_bo) {
6467 if (dev_priv->info->cursor_needs_physical) {
6468 if (intel_crtc->cursor_bo != obj)
6469 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6471 i915_gem_object_unpin(intel_crtc->cursor_bo);
6472 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6475 mutex_unlock(&dev->struct_mutex);
6477 intel_crtc->cursor_addr = addr;
6478 intel_crtc->cursor_bo = obj;
6479 intel_crtc->cursor_width = width;
6480 intel_crtc->cursor_height = height;
6482 intel_crtc_update_cursor(crtc, true);
6486 i915_gem_object_unpin(obj);
6488 mutex_unlock(&dev->struct_mutex);
6490 drm_gem_object_unreference_unlocked(&obj->base);
6494 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6498 intel_crtc->cursor_x = x;
6499 intel_crtc->cursor_y = y;
6501 intel_crtc_update_cursor(crtc, true);
6506 /** Sets the color ramps on behalf of RandR */
6507 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6508 u16 blue, int regno)
6510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6512 intel_crtc->lut_r[regno] = red >> 8;
6513 intel_crtc->lut_g[regno] = green >> 8;
6514 intel_crtc->lut_b[regno] = blue >> 8;
6517 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6518 u16 *blue, int regno)
6520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6522 *red = intel_crtc->lut_r[regno] << 8;
6523 *green = intel_crtc->lut_g[regno] << 8;
6524 *blue = intel_crtc->lut_b[regno] << 8;
6527 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6528 u16 *blue, uint32_t start, uint32_t size)
6530 int end = (start + size > 256) ? 256 : start + size, i;
6531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6533 for (i = start; i < end; i++) {
6534 intel_crtc->lut_r[i] = red[i] >> 8;
6535 intel_crtc->lut_g[i] = green[i] >> 8;
6536 intel_crtc->lut_b[i] = blue[i] >> 8;
6539 intel_crtc_load_lut(crtc);
6543 * Get a pipe with a simple mode set on it for doing load-based monitor
6546 * It will be up to the load-detect code to adjust the pipe as appropriate for
6547 * its requirements. The pipe will be connected to no other encoders.
6549 * Currently this code will only succeed if there is a pipe with no encoders
6550 * configured for it. In the future, it could choose to temporarily disable
6551 * some outputs to free up a pipe for its use.
6553 * \return crtc, or NULL if no pipes are available.
6556 /* VESA 640x480x72Hz mode to set on the pipe */
6557 static struct drm_display_mode load_detect_mode = {
6558 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6559 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6562 static struct drm_framebuffer *
6563 intel_framebuffer_create(struct drm_device *dev,
6564 struct drm_mode_fb_cmd2 *mode_cmd,
6565 struct drm_i915_gem_object *obj)
6567 struct intel_framebuffer *intel_fb;
6570 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6572 drm_gem_object_unreference_unlocked(&obj->base);
6573 return ERR_PTR(-ENOMEM);
6576 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6578 drm_gem_object_unreference_unlocked(&obj->base);
6580 return ERR_PTR(ret);
6583 return &intel_fb->base;
6587 intel_framebuffer_pitch_for_width(int width, int bpp)
6589 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6590 return ALIGN(pitch, 64);
6594 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6596 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6597 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6600 static struct drm_framebuffer *
6601 intel_framebuffer_create_for_mode(struct drm_device *dev,
6602 struct drm_display_mode *mode,
6605 struct drm_i915_gem_object *obj;
6606 struct drm_mode_fb_cmd2 mode_cmd;
6608 obj = i915_gem_alloc_object(dev,
6609 intel_framebuffer_size_for_mode(mode, bpp));
6611 return ERR_PTR(-ENOMEM);
6613 mode_cmd.width = mode->hdisplay;
6614 mode_cmd.height = mode->vdisplay;
6615 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6617 mode_cmd.pixel_format = 0;
6619 return intel_framebuffer_create(dev, &mode_cmd, obj);
6622 static struct drm_framebuffer *
6623 mode_fits_in_fbdev(struct drm_device *dev,
6624 struct drm_display_mode *mode)
6626 struct drm_i915_private *dev_priv = dev->dev_private;
6627 struct drm_i915_gem_object *obj;
6628 struct drm_framebuffer *fb;
6630 if (dev_priv->fbdev == NULL)
6633 obj = dev_priv->fbdev->ifb.obj;
6637 fb = &dev_priv->fbdev->ifb.base;
6638 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6639 fb->bits_per_pixel))
6642 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6648 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6649 struct drm_connector *connector,
6650 struct drm_display_mode *mode,
6651 struct intel_load_detect_pipe *old)
6653 struct intel_crtc *intel_crtc;
6654 struct drm_crtc *possible_crtc;
6655 struct drm_encoder *encoder = &intel_encoder->base;
6656 struct drm_crtc *crtc = NULL;
6657 struct drm_device *dev = encoder->dev;
6658 struct drm_framebuffer *old_fb;
6661 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6662 connector->base.id, drm_get_connector_name(connector),
6663 encoder->base.id, drm_get_encoder_name(encoder));
6666 * Algorithm gets a little messy:
6668 * - if the connector already has an assigned crtc, use it (but make
6669 * sure it's on first)
6671 * - try to find the first unused crtc that can drive this connector,
6672 * and use that if we find one
6675 /* See if we already have a CRTC for this connector */
6676 if (encoder->crtc) {
6677 crtc = encoder->crtc;
6679 intel_crtc = to_intel_crtc(crtc);
6680 old->dpms_mode = intel_crtc->dpms_mode;
6681 old->load_detect_temp = false;
6683 /* Make sure the crtc and connector are running */
6684 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6685 struct drm_encoder_helper_funcs *encoder_funcs;
6686 struct drm_crtc_helper_funcs *crtc_funcs;
6688 crtc_funcs = crtc->helper_private;
6689 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6691 encoder_funcs = encoder->helper_private;
6692 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6698 /* Find an unused one (if possible) */
6699 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6701 if (!(encoder->possible_crtcs & (1 << i)))
6703 if (!possible_crtc->enabled) {
6704 crtc = possible_crtc;
6710 * If we didn't find an unused CRTC, don't use any.
6713 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6717 encoder->crtc = crtc;
6718 connector->encoder = encoder;
6720 intel_crtc = to_intel_crtc(crtc);
6721 old->dpms_mode = intel_crtc->dpms_mode;
6722 old->load_detect_temp = true;
6723 old->release_fb = NULL;
6726 mode = &load_detect_mode;
6730 /* We need a framebuffer large enough to accommodate all accesses
6731 * that the plane may generate whilst we perform load detection.
6732 * We can not rely on the fbcon either being present (we get called
6733 * during its initialisation to detect all boot displays, or it may
6734 * not even exist) or that it is large enough to satisfy the
6737 crtc->fb = mode_fits_in_fbdev(dev, mode);
6738 if (crtc->fb == NULL) {
6739 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6740 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6741 old->release_fb = crtc->fb;
6743 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6744 if (IS_ERR(crtc->fb)) {
6745 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6750 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6751 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6752 if (old->release_fb)
6753 old->release_fb->funcs->destroy(old->release_fb);
6758 /* let the connector get through one full cycle before testing */
6759 intel_wait_for_vblank(dev, intel_crtc->pipe);
6764 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6765 struct drm_connector *connector,
6766 struct intel_load_detect_pipe *old)
6768 struct drm_encoder *encoder = &intel_encoder->base;
6769 struct drm_device *dev = encoder->dev;
6770 struct drm_crtc *crtc = encoder->crtc;
6771 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6772 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6774 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6775 connector->base.id, drm_get_connector_name(connector),
6776 encoder->base.id, drm_get_encoder_name(encoder));
6778 if (old->load_detect_temp) {
6779 connector->encoder = NULL;
6780 drm_helper_disable_unused_functions(dev);
6782 if (old->release_fb)
6783 old->release_fb->funcs->destroy(old->release_fb);
6788 /* Switch crtc and encoder back off if necessary */
6789 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6790 encoder_funcs->dpms(encoder, old->dpms_mode);
6791 crtc_funcs->dpms(crtc, old->dpms_mode);
6795 /* Returns the clock of the currently programmed mode of the given pipe. */
6796 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6798 struct drm_i915_private *dev_priv = dev->dev_private;
6799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6800 int pipe = intel_crtc->pipe;
6801 u32 dpll = I915_READ(DPLL(pipe));
6803 intel_clock_t clock;
6805 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6806 fp = I915_READ(FP0(pipe));
6808 fp = I915_READ(FP1(pipe));
6810 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6811 if (IS_PINEVIEW(dev)) {
6812 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6813 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6815 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6816 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6819 if (!IS_GEN2(dev)) {
6820 if (IS_PINEVIEW(dev))
6821 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6822 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6824 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6825 DPLL_FPA01_P1_POST_DIV_SHIFT);
6827 switch (dpll & DPLL_MODE_MASK) {
6828 case DPLLB_MODE_DAC_SERIAL:
6829 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6832 case DPLLB_MODE_LVDS:
6833 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6837 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6838 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6842 /* XXX: Handle the 100Mhz refclk */
6843 intel_clock(dev, 96000, &clock);
6845 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6848 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6849 DPLL_FPA01_P1_POST_DIV_SHIFT);
6852 if ((dpll & PLL_REF_INPUT_MASK) ==
6853 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6854 /* XXX: might not be 66MHz */
6855 intel_clock(dev, 66000, &clock);
6857 intel_clock(dev, 48000, &clock);
6859 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6862 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6863 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6865 if (dpll & PLL_P2_DIVIDE_BY_4)
6870 intel_clock(dev, 48000, &clock);
6874 /* XXX: It would be nice to validate the clocks, but we can't reuse
6875 * i830PllIsValid() because it relies on the xf86_config connector
6876 * configuration being accurate, which it isn't necessarily.
6882 /** Returns the currently programmed mode of the given pipe. */
6883 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6884 struct drm_crtc *crtc)
6886 struct drm_i915_private *dev_priv = dev->dev_private;
6887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6888 int pipe = intel_crtc->pipe;
6889 struct drm_display_mode *mode;
6890 int htot = I915_READ(HTOTAL(pipe));
6891 int hsync = I915_READ(HSYNC(pipe));
6892 int vtot = I915_READ(VTOTAL(pipe));
6893 int vsync = I915_READ(VSYNC(pipe));
6895 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6899 mode->clock = intel_crtc_clock_get(dev, crtc);
6900 mode->hdisplay = (htot & 0xffff) + 1;
6901 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6902 mode->hsync_start = (hsync & 0xffff) + 1;
6903 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6904 mode->vdisplay = (vtot & 0xffff) + 1;
6905 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6906 mode->vsync_start = (vsync & 0xffff) + 1;
6907 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6909 drm_mode_set_name(mode);
6910 drm_mode_set_crtcinfo(mode, 0);
6915 #define GPU_IDLE_TIMEOUT 500 /* ms */
6917 /* When this timer fires, we've been idle for awhile */
6918 static void intel_gpu_idle_timer(unsigned long arg)
6920 struct drm_device *dev = (struct drm_device *)arg;
6921 drm_i915_private_t *dev_priv = dev->dev_private;
6923 if (!list_empty(&dev_priv->mm.active_list)) {
6924 /* Still processing requests, so just re-arm the timer. */
6925 mod_timer(&dev_priv->idle_timer, jiffies +
6926 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6930 dev_priv->busy = false;
6931 queue_work(dev_priv->wq, &dev_priv->idle_work);
6934 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6936 static void intel_crtc_idle_timer(unsigned long arg)
6938 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6939 struct drm_crtc *crtc = &intel_crtc->base;
6940 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6941 struct intel_framebuffer *intel_fb;
6943 intel_fb = to_intel_framebuffer(crtc->fb);
6944 if (intel_fb && intel_fb->obj->active) {
6945 /* The framebuffer is still being accessed by the GPU. */
6946 mod_timer(&intel_crtc->idle_timer, jiffies +
6947 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6951 intel_crtc->busy = false;
6952 queue_work(dev_priv->wq, &dev_priv->idle_work);
6955 static void intel_increase_pllclock(struct drm_crtc *crtc)
6957 struct drm_device *dev = crtc->dev;
6958 drm_i915_private_t *dev_priv = dev->dev_private;
6959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6960 int pipe = intel_crtc->pipe;
6961 int dpll_reg = DPLL(pipe);
6964 if (HAS_PCH_SPLIT(dev))
6967 if (!dev_priv->lvds_downclock_avail)
6970 dpll = I915_READ(dpll_reg);
6971 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6972 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6974 /* Unlock panel regs */
6975 I915_WRITE(PP_CONTROL,
6976 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6978 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6979 I915_WRITE(dpll_reg, dpll);
6980 intel_wait_for_vblank(dev, pipe);
6982 dpll = I915_READ(dpll_reg);
6983 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6984 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6986 /* ...and lock them again */
6987 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6990 /* Schedule downclock */
6991 mod_timer(&intel_crtc->idle_timer, jiffies +
6992 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6995 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6997 struct drm_device *dev = crtc->dev;
6998 drm_i915_private_t *dev_priv = dev->dev_private;
6999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7000 int pipe = intel_crtc->pipe;
7001 int dpll_reg = DPLL(pipe);
7002 int dpll = I915_READ(dpll_reg);
7004 if (HAS_PCH_SPLIT(dev))
7007 if (!dev_priv->lvds_downclock_avail)
7011 * Since this is called by a timer, we should never get here in
7014 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7015 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7017 /* Unlock panel regs */
7018 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
7021 dpll |= DISPLAY_RATE_SELECT_FPA1;
7022 I915_WRITE(dpll_reg, dpll);
7023 intel_wait_for_vblank(dev, pipe);
7024 dpll = I915_READ(dpll_reg);
7025 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7026 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7028 /* ...and lock them again */
7029 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7035 * intel_idle_update - adjust clocks for idleness
7036 * @work: work struct
7038 * Either the GPU or display (or both) went idle. Check the busy status
7039 * here and adjust the CRTC and GPU clocks as necessary.
7041 static void intel_idle_update(struct work_struct *work)
7043 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7045 struct drm_device *dev = dev_priv->dev;
7046 struct drm_crtc *crtc;
7047 struct intel_crtc *intel_crtc;
7049 if (!i915_powersave)
7052 mutex_lock(&dev->struct_mutex);
7054 i915_update_gfx_val(dev_priv);
7056 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7057 /* Skip inactive CRTCs */
7061 intel_crtc = to_intel_crtc(crtc);
7062 if (!intel_crtc->busy)
7063 intel_decrease_pllclock(crtc);
7067 mutex_unlock(&dev->struct_mutex);
7071 * intel_mark_busy - mark the GPU and possibly the display busy
7073 * @obj: object we're operating on
7075 * Callers can use this function to indicate that the GPU is busy processing
7076 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7077 * buffer), we'll also mark the display as busy, so we know to increase its
7080 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7082 drm_i915_private_t *dev_priv = dev->dev_private;
7083 struct drm_crtc *crtc = NULL;
7084 struct intel_framebuffer *intel_fb;
7085 struct intel_crtc *intel_crtc;
7087 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7090 if (!dev_priv->busy)
7091 dev_priv->busy = true;
7093 mod_timer(&dev_priv->idle_timer, jiffies +
7094 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7096 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7100 intel_crtc = to_intel_crtc(crtc);
7101 intel_fb = to_intel_framebuffer(crtc->fb);
7102 if (intel_fb->obj == obj) {
7103 if (!intel_crtc->busy) {
7104 /* Non-busy -> busy, upclock */
7105 intel_increase_pllclock(crtc);
7106 intel_crtc->busy = true;
7108 /* Busy -> busy, put off timer */
7109 mod_timer(&intel_crtc->idle_timer, jiffies +
7110 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7116 static void intel_crtc_destroy(struct drm_crtc *crtc)
7118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7119 struct drm_device *dev = crtc->dev;
7120 struct intel_unpin_work *work;
7121 unsigned long flags;
7123 spin_lock_irqsave(&dev->event_lock, flags);
7124 work = intel_crtc->unpin_work;
7125 intel_crtc->unpin_work = NULL;
7126 spin_unlock_irqrestore(&dev->event_lock, flags);
7129 cancel_work_sync(&work->work);
7133 drm_crtc_cleanup(crtc);
7138 static void intel_unpin_work_fn(struct work_struct *__work)
7140 struct intel_unpin_work *work =
7141 container_of(__work, struct intel_unpin_work, work);
7143 mutex_lock(&work->dev->struct_mutex);
7144 i915_gem_object_unpin(work->old_fb_obj);
7145 drm_gem_object_unreference(&work->pending_flip_obj->base);
7146 drm_gem_object_unreference(&work->old_fb_obj->base);
7148 intel_update_fbc(work->dev);
7149 mutex_unlock(&work->dev->struct_mutex);
7153 static void do_intel_finish_page_flip(struct drm_device *dev,
7154 struct drm_crtc *crtc)
7156 drm_i915_private_t *dev_priv = dev->dev_private;
7157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7158 struct intel_unpin_work *work;
7159 struct drm_i915_gem_object *obj;
7160 struct drm_pending_vblank_event *e;
7161 struct timeval tnow, tvbl;
7162 unsigned long flags;
7164 /* Ignore early vblank irqs */
7165 if (intel_crtc == NULL)
7168 do_gettimeofday(&tnow);
7170 spin_lock_irqsave(&dev->event_lock, flags);
7171 work = intel_crtc->unpin_work;
7172 if (work == NULL || !work->pending) {
7173 spin_unlock_irqrestore(&dev->event_lock, flags);
7177 intel_crtc->unpin_work = NULL;
7181 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7183 /* Called before vblank count and timestamps have
7184 * been updated for the vblank interval of flip
7185 * completion? Need to increment vblank count and
7186 * add one videorefresh duration to returned timestamp
7187 * to account for this. We assume this happened if we
7188 * get called over 0.9 frame durations after the last
7189 * timestamped vblank.
7191 * This calculation can not be used with vrefresh rates
7192 * below 5Hz (10Hz to be on the safe side) without
7193 * promoting to 64 integers.
7195 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7196 9 * crtc->framedur_ns) {
7197 e->event.sequence++;
7198 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7202 e->event.tv_sec = tvbl.tv_sec;
7203 e->event.tv_usec = tvbl.tv_usec;
7205 list_add_tail(&e->base.link,
7206 &e->base.file_priv->event_list);
7207 wake_up_interruptible(&e->base.file_priv->event_wait);
7210 drm_vblank_put(dev, intel_crtc->pipe);
7212 spin_unlock_irqrestore(&dev->event_lock, flags);
7214 obj = work->old_fb_obj;
7216 atomic_clear_mask(1 << intel_crtc->plane,
7217 &obj->pending_flip.counter);
7218 if (atomic_read(&obj->pending_flip) == 0)
7219 wake_up(&dev_priv->pending_flip_queue);
7221 schedule_work(&work->work);
7223 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7226 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7228 drm_i915_private_t *dev_priv = dev->dev_private;
7229 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7231 do_intel_finish_page_flip(dev, crtc);
7234 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7236 drm_i915_private_t *dev_priv = dev->dev_private;
7237 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7239 do_intel_finish_page_flip(dev, crtc);
7242 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7244 drm_i915_private_t *dev_priv = dev->dev_private;
7245 struct intel_crtc *intel_crtc =
7246 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7247 unsigned long flags;
7249 spin_lock_irqsave(&dev->event_lock, flags);
7250 if (intel_crtc->unpin_work) {
7251 if ((++intel_crtc->unpin_work->pending) > 1)
7252 DRM_ERROR("Prepared flip multiple times\n");
7254 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7256 spin_unlock_irqrestore(&dev->event_lock, flags);
7259 static int intel_gen2_queue_flip(struct drm_device *dev,
7260 struct drm_crtc *crtc,
7261 struct drm_framebuffer *fb,
7262 struct drm_i915_gem_object *obj)
7264 struct drm_i915_private *dev_priv = dev->dev_private;
7265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7266 unsigned long offset;
7270 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7274 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7275 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7277 ret = BEGIN_LP_RING(6);
7281 /* Can't queue multiple flips, so wait for the previous
7282 * one to finish before executing the next.
7284 if (intel_crtc->plane)
7285 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7287 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7288 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7290 OUT_RING(MI_DISPLAY_FLIP |
7291 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7292 OUT_RING(fb->pitches[0]);
7293 OUT_RING(obj->gtt_offset + offset);
7300 static int intel_gen3_queue_flip(struct drm_device *dev,
7301 struct drm_crtc *crtc,
7302 struct drm_framebuffer *fb,
7303 struct drm_i915_gem_object *obj)
7305 struct drm_i915_private *dev_priv = dev->dev_private;
7306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7307 unsigned long offset;
7311 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7315 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7316 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7318 ret = BEGIN_LP_RING(6);
7322 if (intel_crtc->plane)
7323 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7325 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7326 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7328 OUT_RING(MI_DISPLAY_FLIP_I915 |
7329 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7330 OUT_RING(fb->pitches[0]);
7331 OUT_RING(obj->gtt_offset + offset);
7339 static int intel_gen4_queue_flip(struct drm_device *dev,
7340 struct drm_crtc *crtc,
7341 struct drm_framebuffer *fb,
7342 struct drm_i915_gem_object *obj)
7344 struct drm_i915_private *dev_priv = dev->dev_private;
7345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7346 uint32_t pf, pipesrc;
7349 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7353 ret = BEGIN_LP_RING(4);
7357 /* i965+ uses the linear or tiled offsets from the
7358 * Display Registers (which do not change across a page-flip)
7359 * so we need only reprogram the base address.
7361 OUT_RING(MI_DISPLAY_FLIP |
7362 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7363 OUT_RING(fb->pitches[0]);
7364 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7366 /* XXX Enabling the panel-fitter across page-flip is so far
7367 * untested on non-native modes, so ignore it for now.
7368 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7371 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7372 OUT_RING(pf | pipesrc);
7378 static int intel_gen6_queue_flip(struct drm_device *dev,
7379 struct drm_crtc *crtc,
7380 struct drm_framebuffer *fb,
7381 struct drm_i915_gem_object *obj)
7383 struct drm_i915_private *dev_priv = dev->dev_private;
7384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7385 uint32_t pf, pipesrc;
7388 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7392 ret = BEGIN_LP_RING(4);
7396 OUT_RING(MI_DISPLAY_FLIP |
7397 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7398 OUT_RING(fb->pitches[0] | obj->tiling_mode);
7399 OUT_RING(obj->gtt_offset);
7401 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7402 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7403 OUT_RING(pf | pipesrc);
7410 * On gen7 we currently use the blit ring because (in early silicon at least)
7411 * the render ring doesn't give us interrpts for page flip completion, which
7412 * means clients will hang after the first flip is queued. Fortunately the
7413 * blit ring generates interrupts properly, so use it instead.
7415 static int intel_gen7_queue_flip(struct drm_device *dev,
7416 struct drm_crtc *crtc,
7417 struct drm_framebuffer *fb,
7418 struct drm_i915_gem_object *obj)
7420 struct drm_i915_private *dev_priv = dev->dev_private;
7421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7422 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7425 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7429 ret = intel_ring_begin(ring, 4);
7433 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7434 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7435 intel_ring_emit(ring, (obj->gtt_offset));
7436 intel_ring_emit(ring, (MI_NOOP));
7437 intel_ring_advance(ring);
7442 static int intel_default_queue_flip(struct drm_device *dev,
7443 struct drm_crtc *crtc,
7444 struct drm_framebuffer *fb,
7445 struct drm_i915_gem_object *obj)
7450 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7451 struct drm_framebuffer *fb,
7452 struct drm_pending_vblank_event *event)
7454 struct drm_device *dev = crtc->dev;
7455 struct drm_i915_private *dev_priv = dev->dev_private;
7456 struct intel_framebuffer *intel_fb;
7457 struct drm_i915_gem_object *obj;
7458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7459 struct intel_unpin_work *work;
7460 unsigned long flags;
7463 work = kzalloc(sizeof *work, GFP_KERNEL);
7467 work->event = event;
7468 work->dev = crtc->dev;
7469 intel_fb = to_intel_framebuffer(crtc->fb);
7470 work->old_fb_obj = intel_fb->obj;
7471 INIT_WORK(&work->work, intel_unpin_work_fn);
7473 ret = drm_vblank_get(dev, intel_crtc->pipe);
7477 /* We borrow the event spin lock for protecting unpin_work */
7478 spin_lock_irqsave(&dev->event_lock, flags);
7479 if (intel_crtc->unpin_work) {
7480 spin_unlock_irqrestore(&dev->event_lock, flags);
7482 drm_vblank_put(dev, intel_crtc->pipe);
7484 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7487 intel_crtc->unpin_work = work;
7488 spin_unlock_irqrestore(&dev->event_lock, flags);
7490 intel_fb = to_intel_framebuffer(fb);
7491 obj = intel_fb->obj;
7493 mutex_lock(&dev->struct_mutex);
7495 /* Reference the objects for the scheduled work. */
7496 drm_gem_object_reference(&work->old_fb_obj->base);
7497 drm_gem_object_reference(&obj->base);
7501 work->pending_flip_obj = obj;
7503 work->enable_stall_check = true;
7505 /* Block clients from rendering to the new back buffer until
7506 * the flip occurs and the object is no longer visible.
7508 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7510 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7512 goto cleanup_pending;
7514 intel_disable_fbc(dev);
7515 mutex_unlock(&dev->struct_mutex);
7517 trace_i915_flip_request(intel_crtc->plane, obj);
7522 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7523 drm_gem_object_unreference(&work->old_fb_obj->base);
7524 drm_gem_object_unreference(&obj->base);
7525 mutex_unlock(&dev->struct_mutex);
7527 spin_lock_irqsave(&dev->event_lock, flags);
7528 intel_crtc->unpin_work = NULL;
7529 spin_unlock_irqrestore(&dev->event_lock, flags);
7531 drm_vblank_put(dev, intel_crtc->pipe);
7538 static void intel_sanitize_modesetting(struct drm_device *dev,
7539 int pipe, int plane)
7541 struct drm_i915_private *dev_priv = dev->dev_private;
7544 if (HAS_PCH_SPLIT(dev))
7547 /* Who knows what state these registers were left in by the BIOS or
7550 * If we leave the registers in a conflicting state (e.g. with the
7551 * display plane reading from the other pipe than the one we intend
7552 * to use) then when we attempt to teardown the active mode, we will
7553 * not disable the pipes and planes in the correct order -- leaving
7554 * a plane reading from a disabled pipe and possibly leading to
7555 * undefined behaviour.
7558 reg = DSPCNTR(plane);
7559 val = I915_READ(reg);
7561 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7563 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7566 /* This display plane is active and attached to the other CPU pipe. */
7569 /* Disable the plane and wait for it to stop reading from the pipe. */
7570 intel_disable_plane(dev_priv, plane, pipe);
7571 intel_disable_pipe(dev_priv, pipe);
7574 static void intel_crtc_reset(struct drm_crtc *crtc)
7576 struct drm_device *dev = crtc->dev;
7577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7579 /* Reset flags back to the 'unknown' status so that they
7580 * will be correctly set on the initial modeset.
7582 intel_crtc->dpms_mode = -1;
7584 /* We need to fix up any BIOS configuration that conflicts with
7587 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7590 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7591 .dpms = intel_crtc_dpms,
7592 .mode_fixup = intel_crtc_mode_fixup,
7593 .mode_set = intel_crtc_mode_set,
7594 .mode_set_base = intel_pipe_set_base,
7595 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7596 .load_lut = intel_crtc_load_lut,
7597 .disable = intel_crtc_disable,
7600 static const struct drm_crtc_funcs intel_crtc_funcs = {
7601 .reset = intel_crtc_reset,
7602 .cursor_set = intel_crtc_cursor_set,
7603 .cursor_move = intel_crtc_cursor_move,
7604 .gamma_set = intel_crtc_gamma_set,
7605 .set_config = drm_crtc_helper_set_config,
7606 .destroy = intel_crtc_destroy,
7607 .page_flip = intel_crtc_page_flip,
7610 static void intel_crtc_init(struct drm_device *dev, int pipe)
7612 drm_i915_private_t *dev_priv = dev->dev_private;
7613 struct intel_crtc *intel_crtc;
7616 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7617 if (intel_crtc == NULL)
7620 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7622 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7623 for (i = 0; i < 256; i++) {
7624 intel_crtc->lut_r[i] = i;
7625 intel_crtc->lut_g[i] = i;
7626 intel_crtc->lut_b[i] = i;
7629 /* Swap pipes & planes for FBC on pre-965 */
7630 intel_crtc->pipe = pipe;
7631 intel_crtc->plane = pipe;
7632 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7633 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7634 intel_crtc->plane = !pipe;
7637 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7638 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7639 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7640 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7642 intel_crtc_reset(&intel_crtc->base);
7643 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7644 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7646 if (HAS_PCH_SPLIT(dev)) {
7647 if (pipe == 2 && IS_IVYBRIDGE(dev))
7648 intel_crtc->no_pll = true;
7649 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7650 intel_helper_funcs.commit = ironlake_crtc_commit;
7652 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7653 intel_helper_funcs.commit = i9xx_crtc_commit;
7656 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7658 intel_crtc->busy = false;
7660 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7661 (unsigned long)intel_crtc);
7664 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7665 struct drm_file *file)
7667 drm_i915_private_t *dev_priv = dev->dev_private;
7668 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7669 struct drm_mode_object *drmmode_obj;
7670 struct intel_crtc *crtc;
7673 DRM_ERROR("called with no initialization\n");
7677 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7678 DRM_MODE_OBJECT_CRTC);
7681 DRM_ERROR("no such CRTC id\n");
7685 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7686 pipe_from_crtc_id->pipe = crtc->pipe;
7691 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7693 struct intel_encoder *encoder;
7697 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7698 if (type_mask & encoder->clone_mask)
7699 index_mask |= (1 << entry);
7706 static bool has_edp_a(struct drm_device *dev)
7708 struct drm_i915_private *dev_priv = dev->dev_private;
7710 if (!IS_MOBILE(dev))
7713 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7717 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7723 static void intel_setup_outputs(struct drm_device *dev)
7725 struct drm_i915_private *dev_priv = dev->dev_private;
7726 struct intel_encoder *encoder;
7727 bool dpd_is_edp = false;
7728 bool has_lvds = false;
7730 if (IS_MOBILE(dev) && !IS_I830(dev))
7731 has_lvds = intel_lvds_init(dev);
7732 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7733 /* disable the panel fitter on everything but LVDS */
7734 I915_WRITE(PFIT_CONTROL, 0);
7737 if (HAS_PCH_SPLIT(dev)) {
7738 dpd_is_edp = intel_dpd_is_edp(dev);
7741 intel_dp_init(dev, DP_A);
7743 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7744 intel_dp_init(dev, PCH_DP_D);
7747 intel_crt_init(dev);
7749 if (HAS_PCH_SPLIT(dev)) {
7752 if (I915_READ(HDMIB) & PORT_DETECTED) {
7753 /* PCH SDVOB multiplex with HDMIB */
7754 found = intel_sdvo_init(dev, PCH_SDVOB);
7756 intel_hdmi_init(dev, HDMIB);
7757 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7758 intel_dp_init(dev, PCH_DP_B);
7761 if (I915_READ(HDMIC) & PORT_DETECTED)
7762 intel_hdmi_init(dev, HDMIC);
7764 if (I915_READ(HDMID) & PORT_DETECTED)
7765 intel_hdmi_init(dev, HDMID);
7767 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7768 intel_dp_init(dev, PCH_DP_C);
7770 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7771 intel_dp_init(dev, PCH_DP_D);
7773 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7776 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7777 DRM_DEBUG_KMS("probing SDVOB\n");
7778 found = intel_sdvo_init(dev, SDVOB);
7779 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7780 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7781 intel_hdmi_init(dev, SDVOB);
7784 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7785 DRM_DEBUG_KMS("probing DP_B\n");
7786 intel_dp_init(dev, DP_B);
7790 /* Before G4X SDVOC doesn't have its own detect register */
7792 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7793 DRM_DEBUG_KMS("probing SDVOC\n");
7794 found = intel_sdvo_init(dev, SDVOC);
7797 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7799 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7800 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7801 intel_hdmi_init(dev, SDVOC);
7803 if (SUPPORTS_INTEGRATED_DP(dev)) {
7804 DRM_DEBUG_KMS("probing DP_C\n");
7805 intel_dp_init(dev, DP_C);
7809 if (SUPPORTS_INTEGRATED_DP(dev) &&
7810 (I915_READ(DP_D) & DP_DETECTED)) {
7811 DRM_DEBUG_KMS("probing DP_D\n");
7812 intel_dp_init(dev, DP_D);
7814 } else if (IS_GEN2(dev))
7815 intel_dvo_init(dev);
7817 if (SUPPORTS_TV(dev))
7820 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7821 encoder->base.possible_crtcs = encoder->crtc_mask;
7822 encoder->base.possible_clones =
7823 intel_encoder_clones(dev, encoder->clone_mask);
7826 /* disable all the possible outputs/crtcs before entering KMS mode */
7827 drm_helper_disable_unused_functions(dev);
7829 if (HAS_PCH_SPLIT(dev))
7830 ironlake_init_pch_refclk(dev);
7833 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7835 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7837 drm_framebuffer_cleanup(fb);
7838 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7843 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7844 struct drm_file *file,
7845 unsigned int *handle)
7847 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7848 struct drm_i915_gem_object *obj = intel_fb->obj;
7850 return drm_gem_handle_create(file, &obj->base, handle);
7853 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7854 .destroy = intel_user_framebuffer_destroy,
7855 .create_handle = intel_user_framebuffer_create_handle,
7858 int intel_framebuffer_init(struct drm_device *dev,
7859 struct intel_framebuffer *intel_fb,
7860 struct drm_mode_fb_cmd2 *mode_cmd,
7861 struct drm_i915_gem_object *obj)
7865 if (obj->tiling_mode == I915_TILING_Y)
7868 if (mode_cmd->pitches[0] & 63)
7871 switch (mode_cmd->pixel_format) {
7872 case DRM_FORMAT_RGB332:
7873 case DRM_FORMAT_RGB565:
7874 case DRM_FORMAT_XRGB8888:
7875 case DRM_FORMAT_ARGB8888:
7876 case DRM_FORMAT_XRGB2101010:
7877 case DRM_FORMAT_ARGB2101010:
7878 /* RGB formats are common across chipsets */
7880 case DRM_FORMAT_YUYV:
7881 case DRM_FORMAT_UYVY:
7882 case DRM_FORMAT_YVYU:
7883 case DRM_FORMAT_VYUY:
7886 DRM_ERROR("unsupported pixel format\n");
7890 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7892 DRM_ERROR("framebuffer init failed %d\n", ret);
7896 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7897 intel_fb->obj = obj;
7901 static struct drm_framebuffer *
7902 intel_user_framebuffer_create(struct drm_device *dev,
7903 struct drm_file *filp,
7904 struct drm_mode_fb_cmd2 *mode_cmd)
7906 struct drm_i915_gem_object *obj;
7908 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7909 mode_cmd->handles[0]));
7910 if (&obj->base == NULL)
7911 return ERR_PTR(-ENOENT);
7913 return intel_framebuffer_create(dev, mode_cmd, obj);
7916 static const struct drm_mode_config_funcs intel_mode_funcs = {
7917 .fb_create = intel_user_framebuffer_create,
7918 .output_poll_changed = intel_fb_output_poll_changed,
7921 static struct drm_i915_gem_object *
7922 intel_alloc_context_page(struct drm_device *dev)
7924 struct drm_i915_gem_object *ctx;
7927 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7929 ctx = i915_gem_alloc_object(dev, 4096);
7931 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7935 ret = i915_gem_object_pin(ctx, 4096, true);
7937 DRM_ERROR("failed to pin power context: %d\n", ret);
7941 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7943 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7950 i915_gem_object_unpin(ctx);
7952 drm_gem_object_unreference(&ctx->base);
7953 mutex_unlock(&dev->struct_mutex);
7957 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7959 struct drm_i915_private *dev_priv = dev->dev_private;
7962 rgvswctl = I915_READ16(MEMSWCTL);
7963 if (rgvswctl & MEMCTL_CMD_STS) {
7964 DRM_DEBUG("gpu busy, RCS change rejected\n");
7965 return false; /* still busy with another command */
7968 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7969 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7970 I915_WRITE16(MEMSWCTL, rgvswctl);
7971 POSTING_READ16(MEMSWCTL);
7973 rgvswctl |= MEMCTL_CMD_STS;
7974 I915_WRITE16(MEMSWCTL, rgvswctl);
7979 void ironlake_enable_drps(struct drm_device *dev)
7981 struct drm_i915_private *dev_priv = dev->dev_private;
7982 u32 rgvmodectl = I915_READ(MEMMODECTL);
7983 u8 fmax, fmin, fstart, vstart;
7985 /* Enable temp reporting */
7986 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7987 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7989 /* 100ms RC evaluation intervals */
7990 I915_WRITE(RCUPEI, 100000);
7991 I915_WRITE(RCDNEI, 100000);
7993 /* Set max/min thresholds to 90ms and 80ms respectively */
7994 I915_WRITE(RCBMAXAVG, 90000);
7995 I915_WRITE(RCBMINAVG, 80000);
7997 I915_WRITE(MEMIHYST, 1);
7999 /* Set up min, max, and cur for interrupt handling */
8000 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8001 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8002 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8003 MEMMODE_FSTART_SHIFT;
8005 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8008 dev_priv->fmax = fmax; /* IPS callback will increase this */
8009 dev_priv->fstart = fstart;
8011 dev_priv->max_delay = fstart;
8012 dev_priv->min_delay = fmin;
8013 dev_priv->cur_delay = fstart;
8015 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8016 fmax, fmin, fstart);
8018 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8021 * Interrupts will be enabled in ironlake_irq_postinstall
8024 I915_WRITE(VIDSTART, vstart);
8025 POSTING_READ(VIDSTART);
8027 rgvmodectl |= MEMMODE_SWMODE_EN;
8028 I915_WRITE(MEMMODECTL, rgvmodectl);
8030 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8031 DRM_ERROR("stuck trying to change perf mode\n");
8034 ironlake_set_drps(dev, fstart);
8036 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8038 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8039 dev_priv->last_count2 = I915_READ(0x112f4);
8040 getrawmonotonic(&dev_priv->last_time2);
8043 void ironlake_disable_drps(struct drm_device *dev)
8045 struct drm_i915_private *dev_priv = dev->dev_private;
8046 u16 rgvswctl = I915_READ16(MEMSWCTL);
8048 /* Ack interrupts, disable EFC interrupt */
8049 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8050 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8051 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8052 I915_WRITE(DEIIR, DE_PCU_EVENT);
8053 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8055 /* Go back to the starting frequency */
8056 ironlake_set_drps(dev, dev_priv->fstart);
8058 rgvswctl |= MEMCTL_CMD_STS;
8059 I915_WRITE(MEMSWCTL, rgvswctl);
8064 void gen6_set_rps(struct drm_device *dev, u8 val)
8066 struct drm_i915_private *dev_priv = dev->dev_private;
8069 swreq = (val & 0x3ff) << 25;
8070 I915_WRITE(GEN6_RPNSWREQ, swreq);
8073 void gen6_disable_rps(struct drm_device *dev)
8075 struct drm_i915_private *dev_priv = dev->dev_private;
8077 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8078 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8079 I915_WRITE(GEN6_PMIER, 0);
8080 /* Complete PM interrupt masking here doesn't race with the rps work
8081 * item again unmasking PM interrupts because that is using a different
8082 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8083 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8085 spin_lock_irq(&dev_priv->rps_lock);
8086 dev_priv->pm_iir = 0;
8087 spin_unlock_irq(&dev_priv->rps_lock);
8089 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8092 static unsigned long intel_pxfreq(u32 vidfreq)
8095 int div = (vidfreq & 0x3f0000) >> 16;
8096 int post = (vidfreq & 0x3000) >> 12;
8097 int pre = (vidfreq & 0x7);
8102 freq = ((div * 133333) / ((1<<post) * pre));
8107 void intel_init_emon(struct drm_device *dev)
8109 struct drm_i915_private *dev_priv = dev->dev_private;
8114 /* Disable to program */
8118 /* Program energy weights for various events */
8119 I915_WRITE(SDEW, 0x15040d00);
8120 I915_WRITE(CSIEW0, 0x007f0000);
8121 I915_WRITE(CSIEW1, 0x1e220004);
8122 I915_WRITE(CSIEW2, 0x04000004);
8124 for (i = 0; i < 5; i++)
8125 I915_WRITE(PEW + (i * 4), 0);
8126 for (i = 0; i < 3; i++)
8127 I915_WRITE(DEW + (i * 4), 0);
8129 /* Program P-state weights to account for frequency power adjustment */
8130 for (i = 0; i < 16; i++) {
8131 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8132 unsigned long freq = intel_pxfreq(pxvidfreq);
8133 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8138 val *= (freq / 1000);
8140 val /= (127*127*900);
8142 DRM_ERROR("bad pxval: %ld\n", val);
8145 /* Render standby states get 0 weight */
8149 for (i = 0; i < 4; i++) {
8150 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8151 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8152 I915_WRITE(PXW + (i * 4), val);
8155 /* Adjust magic regs to magic values (more experimental results) */
8156 I915_WRITE(OGW0, 0);
8157 I915_WRITE(OGW1, 0);
8158 I915_WRITE(EG0, 0x00007f00);
8159 I915_WRITE(EG1, 0x0000000e);
8160 I915_WRITE(EG2, 0x000e0000);
8161 I915_WRITE(EG3, 0x68000300);
8162 I915_WRITE(EG4, 0x42000000);
8163 I915_WRITE(EG5, 0x00140031);
8167 for (i = 0; i < 8; i++)
8168 I915_WRITE(PXWL + (i * 4), 0);
8170 /* Enable PMON + select events */
8171 I915_WRITE(ECR, 0x80000019);
8173 lcfuse = I915_READ(LCFUSE02);
8175 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8178 static bool intel_enable_rc6(struct drm_device *dev)
8181 * Respect the kernel parameter if it is set
8183 if (i915_enable_rc6 >= 0)
8184 return i915_enable_rc6;
8187 * Disable RC6 on Ironlake
8189 if (INTEL_INFO(dev)->gen == 5)
8193 * Disable rc6 on Sandybridge
8195 if (INTEL_INFO(dev)->gen == 6) {
8196 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8199 DRM_DEBUG_DRIVER("RC6 enabled\n");
8203 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8205 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8206 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8207 u32 pcu_mbox, rc6_mask = 0;
8208 int cur_freq, min_freq, max_freq;
8211 /* Here begins a magic sequence of register writes to enable
8212 * auto-downclocking.
8214 * Perhaps there might be some value in exposing these to
8217 I915_WRITE(GEN6_RC_STATE, 0);
8218 mutex_lock(&dev_priv->dev->struct_mutex);
8219 gen6_gt_force_wake_get(dev_priv);
8221 /* disable the counters and set deterministic thresholds */
8222 I915_WRITE(GEN6_RC_CONTROL, 0);
8224 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8225 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8226 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8227 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8228 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8230 for (i = 0; i < I915_NUM_RINGS; i++)
8231 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8233 I915_WRITE(GEN6_RC_SLEEP, 0);
8234 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8235 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8236 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8237 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8239 if (intel_enable_rc6(dev_priv->dev))
8240 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8241 GEN6_RC_CTL_RC6_ENABLE;
8243 I915_WRITE(GEN6_RC_CONTROL,
8245 GEN6_RC_CTL_EI_MODE(1) |
8246 GEN6_RC_CTL_HW_ENABLE);
8248 I915_WRITE(GEN6_RPNSWREQ,
8249 GEN6_FREQUENCY(10) |
8251 GEN6_AGGRESSIVE_TURBO);
8252 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8253 GEN6_FREQUENCY(12));
8255 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8256 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8259 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8260 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8261 I915_WRITE(GEN6_RP_UP_EI, 100000);
8262 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8263 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8264 I915_WRITE(GEN6_RP_CONTROL,
8265 GEN6_RP_MEDIA_TURBO |
8266 GEN6_RP_MEDIA_HW_MODE |
8267 GEN6_RP_MEDIA_IS_GFX |
8269 GEN6_RP_UP_BUSY_AVG |
8270 GEN6_RP_DOWN_IDLE_CONT);
8272 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8274 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8276 I915_WRITE(GEN6_PCODE_DATA, 0);
8277 I915_WRITE(GEN6_PCODE_MAILBOX,
8279 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8280 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8282 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8284 min_freq = (rp_state_cap & 0xff0000) >> 16;
8285 max_freq = rp_state_cap & 0xff;
8286 cur_freq = (gt_perf_status & 0xff00) >> 8;
8288 /* Check for overclock support */
8289 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8291 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8292 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8293 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8294 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8296 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8297 if (pcu_mbox & (1<<31)) { /* OC supported */
8298 max_freq = pcu_mbox & 0xff;
8299 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8302 /* In units of 100MHz */
8303 dev_priv->max_delay = max_freq;
8304 dev_priv->min_delay = min_freq;
8305 dev_priv->cur_delay = cur_freq;
8307 /* requires MSI enabled */
8308 I915_WRITE(GEN6_PMIER,
8309 GEN6_PM_MBOX_EVENT |
8310 GEN6_PM_THERMAL_EVENT |
8311 GEN6_PM_RP_DOWN_TIMEOUT |
8312 GEN6_PM_RP_UP_THRESHOLD |
8313 GEN6_PM_RP_DOWN_THRESHOLD |
8314 GEN6_PM_RP_UP_EI_EXPIRED |
8315 GEN6_PM_RP_DOWN_EI_EXPIRED);
8316 spin_lock_irq(&dev_priv->rps_lock);
8317 WARN_ON(dev_priv->pm_iir != 0);
8318 I915_WRITE(GEN6_PMIMR, 0);
8319 spin_unlock_irq(&dev_priv->rps_lock);
8320 /* enable all PM interrupts */
8321 I915_WRITE(GEN6_PMINTRMSK, 0);
8323 gen6_gt_force_wake_put(dev_priv);
8324 mutex_unlock(&dev_priv->dev->struct_mutex);
8327 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8330 int gpu_freq, ia_freq, max_ia_freq;
8331 int scaling_factor = 180;
8333 max_ia_freq = cpufreq_quick_get_max(0);
8335 * Default to measured freq if none found, PCU will ensure we don't go
8339 max_ia_freq = tsc_khz;
8341 /* Convert from kHz to MHz */
8342 max_ia_freq /= 1000;
8344 mutex_lock(&dev_priv->dev->struct_mutex);
8347 * For each potential GPU frequency, load a ring frequency we'd like
8348 * to use for memory access. We do this by specifying the IA frequency
8349 * the PCU should use as a reference to determine the ring frequency.
8351 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8353 int diff = dev_priv->max_delay - gpu_freq;
8356 * For GPU frequencies less than 750MHz, just use the lowest
8359 if (gpu_freq < min_freq)
8362 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8363 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8365 I915_WRITE(GEN6_PCODE_DATA,
8366 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8368 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8369 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8370 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8371 GEN6_PCODE_READY) == 0, 10)) {
8372 DRM_ERROR("pcode write of freq table timed out\n");
8377 mutex_unlock(&dev_priv->dev->struct_mutex);
8380 static void ironlake_init_clock_gating(struct drm_device *dev)
8382 struct drm_i915_private *dev_priv = dev->dev_private;
8383 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8385 /* Required for FBC */
8386 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8387 DPFCRUNIT_CLOCK_GATE_DISABLE |
8388 DPFDUNIT_CLOCK_GATE_DISABLE;
8389 /* Required for CxSR */
8390 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8392 I915_WRITE(PCH_3DCGDIS0,
8393 MARIUNIT_CLOCK_GATE_DISABLE |
8394 SVSMUNIT_CLOCK_GATE_DISABLE);
8395 I915_WRITE(PCH_3DCGDIS1,
8396 VFMUNIT_CLOCK_GATE_DISABLE);
8398 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8401 * According to the spec the following bits should be set in
8402 * order to enable memory self-refresh
8403 * The bit 22/21 of 0x42004
8404 * The bit 5 of 0x42020
8405 * The bit 15 of 0x45000
8407 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8408 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8409 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8410 I915_WRITE(ILK_DSPCLK_GATE,
8411 (I915_READ(ILK_DSPCLK_GATE) |
8412 ILK_DPARB_CLK_GATE));
8413 I915_WRITE(DISP_ARB_CTL,
8414 (I915_READ(DISP_ARB_CTL) |
8416 I915_WRITE(WM3_LP_ILK, 0);
8417 I915_WRITE(WM2_LP_ILK, 0);
8418 I915_WRITE(WM1_LP_ILK, 0);
8421 * Based on the document from hardware guys the following bits
8422 * should be set unconditionally in order to enable FBC.
8423 * The bit 22 of 0x42000
8424 * The bit 22 of 0x42004
8425 * The bit 7,8,9 of 0x42020.
8427 if (IS_IRONLAKE_M(dev)) {
8428 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8429 I915_READ(ILK_DISPLAY_CHICKEN1) |
8431 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8432 I915_READ(ILK_DISPLAY_CHICKEN2) |
8434 I915_WRITE(ILK_DSPCLK_GATE,
8435 I915_READ(ILK_DSPCLK_GATE) |
8441 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8442 I915_READ(ILK_DISPLAY_CHICKEN2) |
8443 ILK_ELPIN_409_SELECT);
8444 I915_WRITE(_3D_CHICKEN2,
8445 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8446 _3D_CHICKEN2_WM_READ_PIPELINED);
8449 static void gen6_init_clock_gating(struct drm_device *dev)
8451 struct drm_i915_private *dev_priv = dev->dev_private;
8453 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8455 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8457 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8458 I915_READ(ILK_DISPLAY_CHICKEN2) |
8459 ILK_ELPIN_409_SELECT);
8461 I915_WRITE(WM3_LP_ILK, 0);
8462 I915_WRITE(WM2_LP_ILK, 0);
8463 I915_WRITE(WM1_LP_ILK, 0);
8465 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8466 * gating disable must be set. Failure to set it results in
8467 * flickering pixels due to Z write ordering failures after
8468 * some amount of runtime in the Mesa "fire" demo, and Unigine
8469 * Sanctuary and Tropics, and apparently anything else with
8470 * alpha test or pixel discard.
8472 * According to the spec, bit 11 (RCCUNIT) must also be set,
8473 * but we didn't debug actual testcases to find it out.
8475 I915_WRITE(GEN6_UCGCTL2,
8476 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8477 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8480 * According to the spec the following bits should be
8481 * set in order to enable memory self-refresh and fbc:
8482 * The bit21 and bit22 of 0x42000
8483 * The bit21 and bit22 of 0x42004
8484 * The bit5 and bit7 of 0x42020
8485 * The bit14 of 0x70180
8486 * The bit14 of 0x71180
8488 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8489 I915_READ(ILK_DISPLAY_CHICKEN1) |
8490 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8491 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8492 I915_READ(ILK_DISPLAY_CHICKEN2) |
8493 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8494 I915_WRITE(ILK_DSPCLK_GATE,
8495 I915_READ(ILK_DSPCLK_GATE) |
8496 ILK_DPARB_CLK_GATE |
8499 for_each_pipe(pipe) {
8500 I915_WRITE(DSPCNTR(pipe),
8501 I915_READ(DSPCNTR(pipe)) |
8502 DISPPLANE_TRICKLE_FEED_DISABLE);
8503 intel_flush_display_plane(dev_priv, pipe);
8507 static void ivybridge_init_clock_gating(struct drm_device *dev)
8509 struct drm_i915_private *dev_priv = dev->dev_private;
8511 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8513 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8515 I915_WRITE(WM3_LP_ILK, 0);
8516 I915_WRITE(WM2_LP_ILK, 0);
8517 I915_WRITE(WM1_LP_ILK, 0);
8519 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8521 I915_WRITE(IVB_CHICKEN3,
8522 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8523 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8525 for_each_pipe(pipe) {
8526 I915_WRITE(DSPCNTR(pipe),
8527 I915_READ(DSPCNTR(pipe)) |
8528 DISPPLANE_TRICKLE_FEED_DISABLE);
8529 intel_flush_display_plane(dev_priv, pipe);
8533 static void g4x_init_clock_gating(struct drm_device *dev)
8535 struct drm_i915_private *dev_priv = dev->dev_private;
8536 uint32_t dspclk_gate;
8538 I915_WRITE(RENCLK_GATE_D1, 0);
8539 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8540 GS_UNIT_CLOCK_GATE_DISABLE |
8541 CL_UNIT_CLOCK_GATE_DISABLE);
8542 I915_WRITE(RAMCLK_GATE_D, 0);
8543 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8544 OVRUNIT_CLOCK_GATE_DISABLE |
8545 OVCUNIT_CLOCK_GATE_DISABLE;
8547 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8548 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8551 static void crestline_init_clock_gating(struct drm_device *dev)
8553 struct drm_i915_private *dev_priv = dev->dev_private;
8555 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8556 I915_WRITE(RENCLK_GATE_D2, 0);
8557 I915_WRITE(DSPCLK_GATE_D, 0);
8558 I915_WRITE(RAMCLK_GATE_D, 0);
8559 I915_WRITE16(DEUC, 0);
8562 static void broadwater_init_clock_gating(struct drm_device *dev)
8564 struct drm_i915_private *dev_priv = dev->dev_private;
8566 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8567 I965_RCC_CLOCK_GATE_DISABLE |
8568 I965_RCPB_CLOCK_GATE_DISABLE |
8569 I965_ISC_CLOCK_GATE_DISABLE |
8570 I965_FBC_CLOCK_GATE_DISABLE);
8571 I915_WRITE(RENCLK_GATE_D2, 0);
8574 static void gen3_init_clock_gating(struct drm_device *dev)
8576 struct drm_i915_private *dev_priv = dev->dev_private;
8577 u32 dstate = I915_READ(D_STATE);
8579 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8580 DSTATE_DOT_CLOCK_GATING;
8581 I915_WRITE(D_STATE, dstate);
8584 static void i85x_init_clock_gating(struct drm_device *dev)
8586 struct drm_i915_private *dev_priv = dev->dev_private;
8588 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8591 static void i830_init_clock_gating(struct drm_device *dev)
8593 struct drm_i915_private *dev_priv = dev->dev_private;
8595 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8598 static void ibx_init_clock_gating(struct drm_device *dev)
8600 struct drm_i915_private *dev_priv = dev->dev_private;
8603 * On Ibex Peak and Cougar Point, we need to disable clock
8604 * gating for the panel power sequencer or it will fail to
8605 * start up when no ports are active.
8607 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8610 static void cpt_init_clock_gating(struct drm_device *dev)
8612 struct drm_i915_private *dev_priv = dev->dev_private;
8616 * On Ibex Peak and Cougar Point, we need to disable clock
8617 * gating for the panel power sequencer or it will fail to
8618 * start up when no ports are active.
8620 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8621 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8622 DPLS_EDP_PPS_FIX_DIS);
8623 /* Without this, mode sets may fail silently on FDI */
8625 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8628 static void ironlake_teardown_rc6(struct drm_device *dev)
8630 struct drm_i915_private *dev_priv = dev->dev_private;
8632 if (dev_priv->renderctx) {
8633 i915_gem_object_unpin(dev_priv->renderctx);
8634 drm_gem_object_unreference(&dev_priv->renderctx->base);
8635 dev_priv->renderctx = NULL;
8638 if (dev_priv->pwrctx) {
8639 i915_gem_object_unpin(dev_priv->pwrctx);
8640 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8641 dev_priv->pwrctx = NULL;
8645 static void ironlake_disable_rc6(struct drm_device *dev)
8647 struct drm_i915_private *dev_priv = dev->dev_private;
8649 if (I915_READ(PWRCTXA)) {
8650 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8651 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8652 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8655 I915_WRITE(PWRCTXA, 0);
8656 POSTING_READ(PWRCTXA);
8658 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8659 POSTING_READ(RSTDBYCTL);
8662 ironlake_teardown_rc6(dev);
8665 static int ironlake_setup_rc6(struct drm_device *dev)
8667 struct drm_i915_private *dev_priv = dev->dev_private;
8669 if (dev_priv->renderctx == NULL)
8670 dev_priv->renderctx = intel_alloc_context_page(dev);
8671 if (!dev_priv->renderctx)
8674 if (dev_priv->pwrctx == NULL)
8675 dev_priv->pwrctx = intel_alloc_context_page(dev);
8676 if (!dev_priv->pwrctx) {
8677 ironlake_teardown_rc6(dev);
8684 void ironlake_enable_rc6(struct drm_device *dev)
8686 struct drm_i915_private *dev_priv = dev->dev_private;
8689 /* rc6 disabled by default due to repeated reports of hanging during
8692 if (!intel_enable_rc6(dev))
8695 mutex_lock(&dev->struct_mutex);
8696 ret = ironlake_setup_rc6(dev);
8698 mutex_unlock(&dev->struct_mutex);
8703 * GPU can automatically power down the render unit if given a page
8706 ret = BEGIN_LP_RING(6);
8708 ironlake_teardown_rc6(dev);
8709 mutex_unlock(&dev->struct_mutex);
8713 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8714 OUT_RING(MI_SET_CONTEXT);
8715 OUT_RING(dev_priv->renderctx->gtt_offset |
8717 MI_SAVE_EXT_STATE_EN |
8718 MI_RESTORE_EXT_STATE_EN |
8719 MI_RESTORE_INHIBIT);
8720 OUT_RING(MI_SUSPEND_FLUSH);
8726 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8727 * does an implicit flush, combined with MI_FLUSH above, it should be
8728 * safe to assume that renderctx is valid
8730 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8732 DRM_ERROR("failed to enable ironlake power power savings\n");
8733 ironlake_teardown_rc6(dev);
8734 mutex_unlock(&dev->struct_mutex);
8738 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8739 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8740 mutex_unlock(&dev->struct_mutex);
8743 void intel_init_clock_gating(struct drm_device *dev)
8745 struct drm_i915_private *dev_priv = dev->dev_private;
8747 dev_priv->display.init_clock_gating(dev);
8749 if (dev_priv->display.init_pch_clock_gating)
8750 dev_priv->display.init_pch_clock_gating(dev);
8753 /* Set up chip specific display functions */
8754 static void intel_init_display(struct drm_device *dev)
8756 struct drm_i915_private *dev_priv = dev->dev_private;
8758 /* We always want a DPMS function */
8759 if (HAS_PCH_SPLIT(dev)) {
8760 dev_priv->display.dpms = ironlake_crtc_dpms;
8761 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8762 dev_priv->display.update_plane = ironlake_update_plane;
8764 dev_priv->display.dpms = i9xx_crtc_dpms;
8765 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8766 dev_priv->display.update_plane = i9xx_update_plane;
8769 if (I915_HAS_FBC(dev)) {
8770 if (HAS_PCH_SPLIT(dev)) {
8771 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8772 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8773 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8774 } else if (IS_GM45(dev)) {
8775 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8776 dev_priv->display.enable_fbc = g4x_enable_fbc;
8777 dev_priv->display.disable_fbc = g4x_disable_fbc;
8778 } else if (IS_CRESTLINE(dev)) {
8779 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8780 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8781 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8783 /* 855GM needs testing */
8786 /* Returns the core display clock speed */
8787 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8788 dev_priv->display.get_display_clock_speed =
8789 i945_get_display_clock_speed;
8790 else if (IS_I915G(dev))
8791 dev_priv->display.get_display_clock_speed =
8792 i915_get_display_clock_speed;
8793 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8794 dev_priv->display.get_display_clock_speed =
8795 i9xx_misc_get_display_clock_speed;
8796 else if (IS_I915GM(dev))
8797 dev_priv->display.get_display_clock_speed =
8798 i915gm_get_display_clock_speed;
8799 else if (IS_I865G(dev))
8800 dev_priv->display.get_display_clock_speed =
8801 i865_get_display_clock_speed;
8802 else if (IS_I85X(dev))
8803 dev_priv->display.get_display_clock_speed =
8804 i855_get_display_clock_speed;
8806 dev_priv->display.get_display_clock_speed =
8807 i830_get_display_clock_speed;
8809 /* For FIFO watermark updates */
8810 if (HAS_PCH_SPLIT(dev)) {
8811 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8812 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8814 /* IVB configs may use multi-threaded forcewake */
8815 if (IS_IVYBRIDGE(dev)) {
8818 /* A small trick here - if the bios hasn't configured MT forcewake,
8819 * and if the device is in RC6, then force_wake_mt_get will not wake
8820 * the device and the ECOBUS read will return zero. Which will be
8821 * (correctly) interpreted by the test below as MT forcewake being
8824 mutex_lock(&dev->struct_mutex);
8825 __gen6_gt_force_wake_mt_get(dev_priv);
8826 ecobus = I915_READ_NOTRACE(ECOBUS);
8827 __gen6_gt_force_wake_mt_put(dev_priv);
8828 mutex_unlock(&dev->struct_mutex);
8830 if (ecobus & FORCEWAKE_MT_ENABLE) {
8831 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8832 dev_priv->display.force_wake_get =
8833 __gen6_gt_force_wake_mt_get;
8834 dev_priv->display.force_wake_put =
8835 __gen6_gt_force_wake_mt_put;
8839 if (HAS_PCH_IBX(dev))
8840 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8841 else if (HAS_PCH_CPT(dev))
8842 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8845 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8846 dev_priv->display.update_wm = ironlake_update_wm;
8848 DRM_DEBUG_KMS("Failed to get proper latency. "
8850 dev_priv->display.update_wm = NULL;
8852 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8853 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8854 dev_priv->display.write_eld = ironlake_write_eld;
8855 } else if (IS_GEN6(dev)) {
8856 if (SNB_READ_WM0_LATENCY()) {
8857 dev_priv->display.update_wm = sandybridge_update_wm;
8858 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8860 DRM_DEBUG_KMS("Failed to read display plane latency. "
8862 dev_priv->display.update_wm = NULL;
8864 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8865 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8866 dev_priv->display.write_eld = ironlake_write_eld;
8867 } else if (IS_IVYBRIDGE(dev)) {
8868 /* FIXME: detect B0+ stepping and use auto training */
8869 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8870 if (SNB_READ_WM0_LATENCY()) {
8871 dev_priv->display.update_wm = sandybridge_update_wm;
8872 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8874 DRM_DEBUG_KMS("Failed to read display plane latency. "
8876 dev_priv->display.update_wm = NULL;
8878 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8879 dev_priv->display.write_eld = ironlake_write_eld;
8881 dev_priv->display.update_wm = NULL;
8882 } else if (IS_PINEVIEW(dev)) {
8883 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8886 dev_priv->mem_freq)) {
8887 DRM_INFO("failed to find known CxSR latency "
8888 "(found ddr%s fsb freq %d, mem freq %d), "
8890 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8891 dev_priv->fsb_freq, dev_priv->mem_freq);
8892 /* Disable CxSR and never update its watermark again */
8893 pineview_disable_cxsr(dev);
8894 dev_priv->display.update_wm = NULL;
8896 dev_priv->display.update_wm = pineview_update_wm;
8897 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8898 } else if (IS_G4X(dev)) {
8899 dev_priv->display.write_eld = g4x_write_eld;
8900 dev_priv->display.update_wm = g4x_update_wm;
8901 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8902 } else if (IS_GEN4(dev)) {
8903 dev_priv->display.update_wm = i965_update_wm;
8904 if (IS_CRESTLINE(dev))
8905 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8906 else if (IS_BROADWATER(dev))
8907 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8908 } else if (IS_GEN3(dev)) {
8909 dev_priv->display.update_wm = i9xx_update_wm;
8910 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8911 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8912 } else if (IS_I865G(dev)) {
8913 dev_priv->display.update_wm = i830_update_wm;
8914 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8915 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8916 } else if (IS_I85X(dev)) {
8917 dev_priv->display.update_wm = i9xx_update_wm;
8918 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8919 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8921 dev_priv->display.update_wm = i830_update_wm;
8922 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8924 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8926 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8929 /* Default just returns -ENODEV to indicate unsupported */
8930 dev_priv->display.queue_flip = intel_default_queue_flip;
8932 switch (INTEL_INFO(dev)->gen) {
8934 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8938 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8943 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8947 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8950 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8956 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8957 * resume, or other times. This quirk makes sure that's the case for
8960 static void quirk_pipea_force(struct drm_device *dev)
8962 struct drm_i915_private *dev_priv = dev->dev_private;
8964 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8965 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8969 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8971 static void quirk_ssc_force_disable(struct drm_device *dev)
8973 struct drm_i915_private *dev_priv = dev->dev_private;
8974 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8977 struct intel_quirk {
8979 int subsystem_vendor;
8980 int subsystem_device;
8981 void (*hook)(struct drm_device *dev);
8984 struct intel_quirk intel_quirks[] = {
8985 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8986 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8987 /* HP Mini needs pipe A force quirk (LP: #322104) */
8988 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8990 /* Thinkpad R31 needs pipe A force quirk */
8991 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8992 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8993 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8995 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8996 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8997 /* ThinkPad X40 needs pipe A force quirk */
8999 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9000 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9002 /* 855 & before need to leave pipe A & dpll A up */
9003 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9004 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9006 /* Lenovo U160 cannot use SSC on LVDS */
9007 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9009 /* Sony Vaio Y cannot use SSC on LVDS */
9010 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9013 static void intel_init_quirks(struct drm_device *dev)
9015 struct pci_dev *d = dev->pdev;
9018 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9019 struct intel_quirk *q = &intel_quirks[i];
9021 if (d->device == q->device &&
9022 (d->subsystem_vendor == q->subsystem_vendor ||
9023 q->subsystem_vendor == PCI_ANY_ID) &&
9024 (d->subsystem_device == q->subsystem_device ||
9025 q->subsystem_device == PCI_ANY_ID))
9030 /* Disable the VGA plane that we never use */
9031 static void i915_disable_vga(struct drm_device *dev)
9033 struct drm_i915_private *dev_priv = dev->dev_private;
9037 if (HAS_PCH_SPLIT(dev))
9038 vga_reg = CPU_VGACNTRL;
9042 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9043 outb(1, VGA_SR_INDEX);
9044 sr1 = inb(VGA_SR_DATA);
9045 outb(sr1 | 1<<5, VGA_SR_DATA);
9046 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9049 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9050 POSTING_READ(vga_reg);
9053 void intel_modeset_init(struct drm_device *dev)
9055 struct drm_i915_private *dev_priv = dev->dev_private;
9058 drm_mode_config_init(dev);
9060 dev->mode_config.min_width = 0;
9061 dev->mode_config.min_height = 0;
9063 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9065 intel_init_quirks(dev);
9067 intel_init_display(dev);
9070 dev->mode_config.max_width = 2048;
9071 dev->mode_config.max_height = 2048;
9072 } else if (IS_GEN3(dev)) {
9073 dev->mode_config.max_width = 4096;
9074 dev->mode_config.max_height = 4096;
9076 dev->mode_config.max_width = 8192;
9077 dev->mode_config.max_height = 8192;
9079 dev->mode_config.fb_base = dev->agp->base;
9081 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9082 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9084 for (i = 0; i < dev_priv->num_pipe; i++) {
9085 intel_crtc_init(dev, i);
9086 ret = intel_plane_init(dev, i);
9088 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9091 /* Just disable it once at startup */
9092 i915_disable_vga(dev);
9093 intel_setup_outputs(dev);
9095 intel_init_clock_gating(dev);
9097 if (IS_IRONLAKE_M(dev)) {
9098 ironlake_enable_drps(dev);
9099 intel_init_emon(dev);
9102 if (IS_GEN6(dev) || IS_GEN7(dev)) {
9103 gen6_enable_rps(dev_priv);
9104 gen6_update_ring_freq(dev_priv);
9107 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9108 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9109 (unsigned long)dev);
9112 void intel_modeset_gem_init(struct drm_device *dev)
9114 if (IS_IRONLAKE_M(dev))
9115 ironlake_enable_rc6(dev);
9117 intel_setup_overlay(dev);
9120 void intel_modeset_cleanup(struct drm_device *dev)
9122 struct drm_i915_private *dev_priv = dev->dev_private;
9123 struct drm_crtc *crtc;
9124 struct intel_crtc *intel_crtc;
9126 drm_kms_helper_poll_fini(dev);
9127 mutex_lock(&dev->struct_mutex);
9129 intel_unregister_dsm_handler();
9132 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9133 /* Skip inactive CRTCs */
9137 intel_crtc = to_intel_crtc(crtc);
9138 intel_increase_pllclock(crtc);
9141 intel_disable_fbc(dev);
9143 if (IS_IRONLAKE_M(dev))
9144 ironlake_disable_drps(dev);
9145 if (IS_GEN6(dev) || IS_GEN7(dev))
9146 gen6_disable_rps(dev);
9148 if (IS_IRONLAKE_M(dev))
9149 ironlake_disable_rc6(dev);
9151 mutex_unlock(&dev->struct_mutex);
9153 /* Disable the irq before mode object teardown, for the irq might
9154 * enqueue unpin/hotplug work. */
9155 drm_irq_uninstall(dev);
9156 cancel_work_sync(&dev_priv->hotplug_work);
9157 cancel_work_sync(&dev_priv->rps_work);
9159 /* flush any delayed tasks or pending work */
9160 flush_scheduled_work();
9162 /* Shut off idle work before the crtcs get freed. */
9163 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9164 intel_crtc = to_intel_crtc(crtc);
9165 del_timer_sync(&intel_crtc->idle_timer);
9167 del_timer_sync(&dev_priv->idle_timer);
9168 cancel_work_sync(&dev_priv->idle_work);
9170 drm_mode_config_cleanup(dev);
9174 * Return which encoder is currently attached for connector.
9176 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9178 return &intel_attached_encoder(connector)->base;
9181 void intel_connector_attach_encoder(struct intel_connector *connector,
9182 struct intel_encoder *encoder)
9184 connector->encoder = encoder;
9185 drm_mode_connector_attach_encoder(&connector->base,
9190 * set vga decode state - true == enable VGA decode
9192 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9194 struct drm_i915_private *dev_priv = dev->dev_private;
9197 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9199 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9201 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9202 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9206 #ifdef CONFIG_DEBUG_FS
9207 #include <linux/seq_file.h>
9209 struct intel_display_error_state {
9210 struct intel_cursor_error_state {
9217 struct intel_pipe_error_state {
9229 struct intel_plane_error_state {
9240 struct intel_display_error_state *
9241 intel_display_capture_error_state(struct drm_device *dev)
9243 drm_i915_private_t *dev_priv = dev->dev_private;
9244 struct intel_display_error_state *error;
9247 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9251 for (i = 0; i < 2; i++) {
9252 error->cursor[i].control = I915_READ(CURCNTR(i));
9253 error->cursor[i].position = I915_READ(CURPOS(i));
9254 error->cursor[i].base = I915_READ(CURBASE(i));
9256 error->plane[i].control = I915_READ(DSPCNTR(i));
9257 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9258 error->plane[i].size = I915_READ(DSPSIZE(i));
9259 error->plane[i].pos = I915_READ(DSPPOS(i));
9260 error->plane[i].addr = I915_READ(DSPADDR(i));
9261 if (INTEL_INFO(dev)->gen >= 4) {
9262 error->plane[i].surface = I915_READ(DSPSURF(i));
9263 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9266 error->pipe[i].conf = I915_READ(PIPECONF(i));
9267 error->pipe[i].source = I915_READ(PIPESRC(i));
9268 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9269 error->pipe[i].hblank = I915_READ(HBLANK(i));
9270 error->pipe[i].hsync = I915_READ(HSYNC(i));
9271 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9272 error->pipe[i].vblank = I915_READ(VBLANK(i));
9273 error->pipe[i].vsync = I915_READ(VSYNC(i));
9280 intel_display_print_error_state(struct seq_file *m,
9281 struct drm_device *dev,
9282 struct intel_display_error_state *error)
9286 for (i = 0; i < 2; i++) {
9287 seq_printf(m, "Pipe [%d]:\n", i);
9288 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9289 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9290 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9291 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9292 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9293 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9294 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9295 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9297 seq_printf(m, "Plane [%d]:\n", i);
9298 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9299 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9300 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9301 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9302 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9303 if (INTEL_INFO(dev)->gen >= 4) {
9304 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9305 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9308 seq_printf(m, "Cursor [%d]:\n", i);
9309 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9310 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9311 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);