drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         /**
  75          * find_pll() - Find the best values for the PLL
  76          * @limit: limits for the PLL
  77          * @crtc: current CRTC
  78          * @target: target frequency in kHz
  79          * @refclk: reference clock frequency in kHz
  80          * @match_clock: if provided, @best_clock P divider must
  81          *               match the P divider from @match_clock
  82          *               used for LVDS downclocking
  83          * @best_clock: best PLL values found
  84          *
  85          * Returns true on success, false on failure.
  86          */
  87         bool (*find_pll)(const intel_limit_t *limit,
  88                          struct drm_crtc *crtc,
  89                          int target, int refclk,
  90                          intel_clock_t *match_clock,
  91                          intel_clock_t *best_clock);
  92 };
  93
  94 /* FDI */
  95 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  96
  97 int
  98 intel_pch_rawclk(struct drm_device *dev)
  99 {
 100         struct drm_i915_private *dev_priv = dev->dev_private;
 101
 102         WARN_ON(!HAS_PCH_SPLIT(dev));
 103
 104         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 105 }
 106
 107 static bool
 108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 109                     int target, int refclk, intel_clock_t *match_clock,
 110                     intel_clock_t *best_clock);
 111 static bool
 112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static bool
 117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 118                       int target, int refclk, intel_clock_t *match_clock,
 119                       intel_clock_t *best_clock);
 120 static bool
 121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 122                            int target, int refclk, intel_clock_t *match_clock,
 123                            intel_clock_t *best_clock);
 124
 125 static bool
 126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 127                         int target, int refclk, intel_clock_t *match_clock,
 128                         intel_clock_t *best_clock);
 129
 130 static inline u32 /* units of 100MHz */
 131 intel_fdi_link_freq(struct drm_device *dev)
 132 {
 133         if (IS_GEN5(dev)) {
 134                 struct drm_i915_private *dev_priv = dev->dev_private;
 135                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 136         } else
 137                 return 27;
 138 }
 139
 140 static const intel_limit_t intel_limits_i8xx_dvo = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 2, .max = 33 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 4, .p2_fast = 2 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i8xx_lvds = {
 155         .dot = { .min = 25000, .max = 350000 },
 156         .vco = { .min = 930000, .max = 1400000 },
 157         .n = { .min = 3, .max = 16 },
 158         .m = { .min = 96, .max = 140 },
 159         .m1 = { .min = 18, .max = 26 },
 160         .m2 = { .min = 6, .max = 16 },
 161         .p = { .min = 4, .max = 128 },
 162         .p1 = { .min = 1, .max = 6 },
 163         .p2 = { .dot_limit = 165000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_sdvo = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 8, .max = 18 },
 174         .m2 = { .min = 3, .max = 7 },
 175         .p = { .min = 5, .max = 80 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 200000,
 178                 .p2_slow = 10, .p2_fast = 5 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182 static const intel_limit_t intel_limits_i9xx_lvds = {
 183         .dot = { .min = 20000, .max = 400000 },
 184         .vco = { .min = 1400000, .max = 2800000 },
 185         .n = { .min = 1, .max = 6 },
 186         .m = { .min = 70, .max = 120 },
 187         .m1 = { .min = 8, .max = 18 },
 188         .m2 = { .min = 3, .max = 7 },
 189         .p = { .min = 7, .max = 98 },
 190         .p1 = { .min = 1, .max = 8 },
 191         .p2 = { .dot_limit = 112000,
 192                 .p2_slow = 14, .p2_fast = 7 },
 193         .find_pll = intel_find_best_PLL,
 194 };
 195
 196
 197 static const intel_limit_t intel_limits_g4x_sdvo = {
 198         .dot = { .min = 25000, .max = 270000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 17, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 10, .max = 30 },
 205         .p1 = { .min = 1, .max = 3},
 206         .p2 = { .dot_limit = 270000,
 207                 .p2_slow = 10,
 208                 .p2_fast = 10
 209         },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_hdmi = {
 214         .dot = { .min = 22000, .max = 400000 },
 215         .vco = { .min = 1750000, .max = 3500000},
 216         .n = { .min = 1, .max = 4 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 16, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 5, .max = 80 },
 221         .p1 = { .min = 1, .max = 8},
 222         .p2 = { .dot_limit = 165000,
 223                 .p2_slow = 10, .p2_fast = 5 },
 224         .find_pll = intel_g4x_find_best_PLL,
 225 };
 226
 227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 228         .dot = { .min = 20000, .max = 115000 },
 229         .vco = { .min = 1750000, .max = 3500000 },
 230         .n = { .min = 1, .max = 3 },
 231         .m = { .min = 104, .max = 138 },
 232         .m1 = { .min = 17, .max = 23 },
 233         .m2 = { .min = 5, .max = 11 },
 234         .p = { .min = 28, .max = 112 },
 235         .p1 = { .min = 2, .max = 8 },
 236         .p2 = { .dot_limit = 0,
 237                 .p2_slow = 14, .p2_fast = 14
 238         },
 239         .find_pll = intel_g4x_find_best_PLL,
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 243         .dot = { .min = 80000, .max = 224000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 14, .max = 42 },
 250         .p1 = { .min = 2, .max = 6 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 7, .p2_fast = 7
 253         },
 254         .find_pll = intel_g4x_find_best_PLL,
 255 };
 256
 257 static const intel_limit_t intel_limits_g4x_display_port = {
 258         .dot = { .min = 161670, .max = 227000 },
 259         .vco = { .min = 1750000, .max = 3500000},
 260         .n = { .min = 1, .max = 2 },
 261         .m = { .min = 97, .max = 108 },
 262         .m1 = { .min = 0x10, .max = 0x12 },
 263         .m2 = { .min = 0x05, .max = 0x06 },
 264         .p = { .min = 10, .max = 20 },
 265         .p1 = { .min = 1, .max = 2},
 266         .p2 = { .dot_limit = 0,
 267                 .p2_slow = 10, .p2_fast = 10 },
 268         .find_pll = intel_find_pll_g4x_dp,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_sdvo = {
 272         .dot = { .min = 20000, .max = 400000},
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         /* Pineview's Ncounter is a ring counter */
 275         .n = { .min = 3, .max = 6 },
 276         .m = { .min = 2, .max = 256 },
 277         /* Pineview only has one combined m divider, which we treat as m2. */
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 200000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_pineview_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1700000, .max = 3500000 },
 290         .n = { .min = 3, .max = 6 },
 291         .m = { .min = 2, .max = 256 },
 292         .m1 = { .min = 0, .max = 0 },
 293         .m2 = { .min = 0, .max = 254 },
 294         .p = { .min = 7, .max = 112 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_find_best_PLL,
 299 };
 300
 301 /* Ironlake / Sandybridge
 302  *
 303  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 304  * the range value for them is (actual_value - 2).
 305  */
 306 static const intel_limit_t intel_limits_ironlake_dac = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 5 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 5, .max = 80 },
 314         .p1 = { .min = 1, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 10, .p2_fast = 5 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 118 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 14, .p2_fast = 14 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 335         .dot = { .min = 25000, .max = 350000 },
 336         .vco = { .min = 1760000, .max = 3510000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 79, .max = 127 },
 339         .m1 = { .min = 12, .max = 22 },
 340         .m2 = { .min = 5, .max = 9 },
 341         .p = { .min = 14, .max = 56 },
 342         .p1 = { .min = 2, .max = 8 },
 343         .p2 = { .dot_limit = 225000,
 344                 .p2_slow = 7, .p2_fast = 7 },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 /* LVDS 100mhz refclk limits. */
 349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 28, .max = 112 },
 357         .p1 = { .min = 2, .max = 8 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 14, .p2_fast = 14 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000 },
 366         .n = { .min = 1, .max = 3 },
 367         .m = { .min = 79, .max = 126 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 14, .max = 42 },
 371         .p1 = { .min = 2, .max = 6 },
 372         .p2 = { .dot_limit = 225000,
 373                 .p2_slow = 7, .p2_fast = 7 },
 374         .find_pll = intel_g4x_find_best_PLL,
 375 };
 376
 377 static const intel_limit_t intel_limits_ironlake_display_port = {
 378         .dot = { .min = 25000, .max = 350000 },
 379         .vco = { .min = 1760000, .max = 3510000},
 380         .n = { .min = 1, .max = 2 },
 381         .m = { .min = 81, .max = 90 },
 382         .m1 = { .min = 12, .max = 22 },
 383         .m2 = { .min = 5, .max = 9 },
 384         .p = { .min = 10, .max = 20 },
 385         .p1 = { .min = 1, .max = 2},
 386         .p2 = { .dot_limit = 0,
 387                 .p2_slow = 10, .p2_fast = 10 },
 388         .find_pll = intel_find_pll_ironlake_dp,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_dac = {
 392         .dot = { .min = 25000, .max = 270000 },
 393         .vco = { .min = 4000000, .max = 6000000 },
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 22, .max = 450 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_hdmi = {
 406         .dot = { .min = 20000, .max = 165000 },
 407         .vco = { .min = 4000000, .max = 5994000},
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 60, .max = 300 }, /* guess */
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 static const intel_limit_t intel_limits_vlv_dp = {
 420         .dot = { .min = 25000, .max = 270000 },
 421         .vco = { .min = 4000000, .max = 6000000 },
 422         .n = { .min = 1, .max = 7 },
 423         .m = { .min = 22, .max = 450 },
 424         .m1 = { .min = 2, .max = 3 },
 425         .m2 = { .min = 11, .max = 156 },
 426         .p = { .min = 10, .max = 30 },
 427         .p1 = { .min = 2, .max = 3 },
 428         .p2 = { .dot_limit = 270000,
 429                 .p2_slow = 2, .p2_fast = 20 },
 430         .find_pll = intel_vlv_find_best_pll,
 431 };
 432
 433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 434 {
 435         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 436
 437         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 438                 DRM_ERROR("DPIO idle wait timed out\n");
 439                 return 0;
 440         }
 441
 442         I915_WRITE(DPIO_REG, reg);
 443         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 444                    DPIO_BYTE);
 445         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 446                 DRM_ERROR("DPIO read wait timed out\n");
 447                 return 0;
 448         }
 449
 450         return I915_READ(DPIO_DATA);
 451 }
 452
 453 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 454                              u32 val)
 455 {
 456         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 457
 458         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 459                 DRM_ERROR("DPIO idle wait timed out\n");
 460                 return;
 461         }
 462
 463         I915_WRITE(DPIO_DATA, val);
 464         I915_WRITE(DPIO_REG, reg);
 465         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 466                    DPIO_BYTE);
 467         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 468                 DRM_ERROR("DPIO write wait timed out\n");
 469 }
 470
 471 static void vlv_init_dpio(struct drm_device *dev)
 472 {
 473         struct drm_i915_private *dev_priv = dev->dev_private;
 474
 475         /* Reset the DPIO config */
 476         I915_WRITE(DPIO_CTL, 0);
 477         POSTING_READ(DPIO_CTL);
 478         I915_WRITE(DPIO_CTL, 1);
 479         POSTING_READ(DPIO_CTL);
 480 }
 481
 482 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 483                                                 int refclk)
 484 {
 485         struct drm_device *dev = crtc->dev;
 486         const intel_limit_t *limit;
 487
 488         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 489                 if (intel_is_dual_link_lvds(dev)) {
 490                         if (refclk == 100000)
 491                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 492                         else
 493                                 limit = &intel_limits_ironlake_dual_lvds;
 494                 } else {
 495                         if (refclk == 100000)
 496                                 limit = &intel_limits_ironlake_single_lvds_100m;
 497                         else
 498                                 limit = &intel_limits_ironlake_single_lvds;
 499                 }
 500         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 501                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 502                 limit = &intel_limits_ironlake_display_port;
 503         else
 504                 limit = &intel_limits_ironlake_dac;
 505
 506         return limit;
 507 }
 508
 509 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 510 {
 511         struct drm_device *dev = crtc->dev;
 512         const intel_limit_t *limit;
 513
 514         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 515                 if (intel_is_dual_link_lvds(dev))
 516                         limit = &intel_limits_g4x_dual_channel_lvds;
 517                 else
 518                         limit = &intel_limits_g4x_single_channel_lvds;
 519         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 520                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 521                 limit = &intel_limits_g4x_hdmi;
 522         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 523                 limit = &intel_limits_g4x_sdvo;
 524         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 525                 limit = &intel_limits_g4x_display_port;
 526         } else /* The option is for other outputs */
 527                 limit = &intel_limits_i9xx_sdvo;
 528
 529         return limit;
 530 }
 531
 532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 533 {
 534         struct drm_device *dev = crtc->dev;
 535         const intel_limit_t *limit;
 536
 537         if (HAS_PCH_SPLIT(dev))
 538                 limit = intel_ironlake_limit(crtc, refclk);
 539         else if (IS_G4X(dev)) {
 540                 limit = intel_g4x_limit(crtc);
 541         } else if (IS_PINEVIEW(dev)) {
 542                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 543                         limit = &intel_limits_pineview_lvds;
 544                 else
 545                         limit = &intel_limits_pineview_sdvo;
 546         } else if (IS_VALLEYVIEW(dev)) {
 547                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 548                         limit = &intel_limits_vlv_dac;
 549                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 550                         limit = &intel_limits_vlv_hdmi;
 551                 else
 552                         limit = &intel_limits_vlv_dp;
 553         } else if (!IS_GEN2(dev)) {
 554                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 555                         limit = &intel_limits_i9xx_lvds;
 556                 else
 557                         limit = &intel_limits_i9xx_sdvo;
 558         } else {
 559                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 560                         limit = &intel_limits_i8xx_lvds;
 561                 else
 562                         limit = &intel_limits_i8xx_dvo;
 563         }
 564         return limit;
 565 }
 566
 567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 568 static void pineview_clock(int refclk, intel_clock_t *clock)
 569 {
 570         clock->m = clock->m2 + 2;
 571         clock->p = clock->p1 * clock->p2;
 572         clock->vco = refclk * clock->m / clock->n;
 573         clock->dot = clock->vco / clock->p;
 574 }
 575
 576 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 577 {
 578         if (IS_PINEVIEW(dev)) {
 579                 pineview_clock(refclk, clock);
 580                 return;
 581         }
 582         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 583         clock->p = clock->p1 * clock->p2;
 584         clock->vco = refclk * clock->m / (clock->n + 2);
 585         clock->dot = clock->vco / clock->p;
 586 }
 587
 588 /**
 589  * Returns whether any output on the specified pipe is of the specified type
 590  */
 591 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 592 {
 593         struct drm_device *dev = crtc->dev;
 594         struct intel_encoder *encoder;
 595
 596         for_each_encoder_on_crtc(dev, crtc, encoder)
 597                 if (encoder->type == type)
 598                         return true;
 599
 600         return false;
 601 }
 602
 603 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 604 /**
 605  * Returns whether the given set of divisors are valid for a given refclk with
 606  * the given connectors.
 607  */
 608
 609 static bool intel_PLL_is_valid(struct drm_device *dev,
 610                                const intel_limit_t *limit,
 611                                const intel_clock_t *clock)
 612 {
 613         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 614                 INTELPllInvalid("p1 out of range\n");
 615         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 616                 INTELPllInvalid("p out of range\n");
 617         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 618                 INTELPllInvalid("m2 out of range\n");
 619         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 620                 INTELPllInvalid("m1 out of range\n");
 621         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 622                 INTELPllInvalid("m1 <= m2\n");
 623         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 624                 INTELPllInvalid("m out of range\n");
 625         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 626                 INTELPllInvalid("n out of range\n");
 627         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 628                 INTELPllInvalid("vco out of range\n");
 629         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 630          * connector, etc., rather than just a single range.
 631          */
 632         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 633                 INTELPllInvalid("dot out of range\n");
 634
 635         return true;
 636 }
 637
 638 static bool
 639 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 640                     int target, int refclk, intel_clock_t *match_clock,
 641                     intel_clock_t *best_clock)
 642
 643 {
 644         struct drm_device *dev = crtc->dev;
 645         intel_clock_t clock;
 646         int err = target;
 647
 648         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 649                 /*
 650                  * For LVDS just rely on its current settings for dual-channel.
 651                  * We haven't figured out how to reliably set up different
 652                  * single/dual channel state, if we even can.
 653                  */
 654                 if (intel_is_dual_link_lvds(dev))
 655                         clock.p2 = limit->p2.p2_fast;
 656                 else
 657                         clock.p2 = limit->p2.p2_slow;
 658         } else {
 659                 if (target < limit->p2.dot_limit)
 660                         clock.p2 = limit->p2.p2_slow;
 661                 else
 662                         clock.p2 = limit->p2.p2_fast;
 663         }
 664
 665         memset(best_clock, 0, sizeof(*best_clock));
 666
 667         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 668              clock.m1++) {
 669                 for (clock.m2 = limit->m2.min;
 670                      clock.m2 <= limit->m2.max; clock.m2++) {
 671                         /* m1 is always 0 in Pineview */
 672                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 673                                 break;
 674                         for (clock.n = limit->n.min;
 675                              clock.n <= limit->n.max; clock.n++) {
 676                                 for (clock.p1 = limit->p1.min;
 677                                         clock.p1 <= limit->p1.max; clock.p1++) {
 678                                         int this_err;
 679
 680                                         intel_clock(dev, refclk, &clock);
 681                                         if (!intel_PLL_is_valid(dev, limit,
 682                                                                 &clock))
 683                                                 continue;
 684                                         if (match_clock &&
 685                                             clock.p != match_clock->p)
 686                                                 continue;
 687
 688                                         this_err = abs(clock.dot - target);
 689                                         if (this_err < err) {
 690                                                 *best_clock = clock;
 691                                                 err = this_err;
 692                                         }
 693                                 }
 694                         }
 695                 }
 696         }
 697
 698         return (err != target);
 699 }
 700
 701 static bool
 702 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 703                         int target, int refclk, intel_clock_t *match_clock,
 704                         intel_clock_t *best_clock)
 705 {
 706         struct drm_device *dev = crtc->dev;
 707         intel_clock_t clock;
 708         int max_n;
 709         bool found;
 710         /* approximately equals target * 0.00585 */
 711         int err_most = (target >> 8) + (target >> 9);
 712         found = false;
 713
 714         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 715                 int lvds_reg;
 716
 717                 if (HAS_PCH_SPLIT(dev))
 718                         lvds_reg = PCH_LVDS;
 719                 else
 720                         lvds_reg = LVDS;
 721                 if (intel_is_dual_link_lvds(dev))
 722                         clock.p2 = limit->p2.p2_fast;
 723                 else
 724                         clock.p2 = limit->p2.p2_slow;
 725         } else {
 726                 if (target < limit->p2.dot_limit)
 727                         clock.p2 = limit->p2.p2_slow;
 728                 else
 729                         clock.p2 = limit->p2.p2_fast;
 730         }
 731
 732         memset(best_clock, 0, sizeof(*best_clock));
 733         max_n = limit->n.max;
 734         /* based on hardware requirement, prefer smaller n to precision */
 735         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 736                 /* based on hardware requirement, prefere larger m1,m2 */
 737                 for (clock.m1 = limit->m1.max;
 738                      clock.m1 >= limit->m1.min; clock.m1--) {
 739                         for (clock.m2 = limit->m2.max;
 740                              clock.m2 >= limit->m2.min; clock.m2--) {
 741                                 for (clock.p1 = limit->p1.max;
 742                                      clock.p1 >= limit->p1.min; clock.p1--) {
 743                                         int this_err;
 744
 745                                         intel_clock(dev, refclk, &clock);
 746                                         if (!intel_PLL_is_valid(dev, limit,
 747                                                                 &clock))
 748                                                 continue;
 749                                         if (match_clock &&
 750                                             clock.p != match_clock->p)
 751                                                 continue;
 752
 753                                         this_err = abs(clock.dot - target);
 754                                         if (this_err < err_most) {
 755                                                 *best_clock = clock;
 756                                                 err_most = this_err;
 757                                                 max_n = clock.n;
 758                                                 found = true;
 759                                         }
 760                                 }
 761                         }
 762                 }
 763         }
 764         return found;
 765 }
 766
 767 static bool
 768 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 769                            int target, int refclk, intel_clock_t *match_clock,
 770                            intel_clock_t *best_clock)
 771 {
 772         struct drm_device *dev = crtc->dev;
 773         intel_clock_t clock;
 774
 775         if (target < 200000) {
 776                 clock.n = 1;
 777                 clock.p1 = 2;
 778                 clock.p2 = 10;
 779                 clock.m1 = 12;
 780                 clock.m2 = 9;
 781         } else {
 782                 clock.n = 2;
 783                 clock.p1 = 1;
 784                 clock.p2 = 10;
 785                 clock.m1 = 14;
 786                 clock.m2 = 8;
 787         }
 788         intel_clock(dev, refclk, &clock);
 789         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 790         return true;
 791 }
 792
 793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 794 static bool
 795 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 796                       int target, int refclk, intel_clock_t *match_clock,
 797                       intel_clock_t *best_clock)
 798 {
 799         intel_clock_t clock;
 800         if (target < 200000) {
 801                 clock.p1 = 2;
 802                 clock.p2 = 10;
 803                 clock.n = 2;
 804                 clock.m1 = 23;
 805                 clock.m2 = 8;
 806         } else {
 807                 clock.p1 = 1;
 808                 clock.p2 = 10;
 809                 clock.n = 1;
 810                 clock.m1 = 14;
 811                 clock.m2 = 2;
 812         }
 813         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 814         clock.p = (clock.p1 * clock.p2);
 815         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 816         clock.vco = 0;
 817         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 818         return true;
 819 }
 820 static bool
 821 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 822                         int target, int refclk, intel_clock_t *match_clock,
 823                         intel_clock_t *best_clock)
 824 {
 825         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 826         u32 m, n, fastclk;
 827         u32 updrate, minupdate, fracbits, p;
 828         unsigned long bestppm, ppm, absppm;
 829         int dotclk, flag;
 830
 831         flag = 0;
 832         dotclk = target * 1000;
 833         bestppm = 1000000;
 834         ppm = absppm = 0;
 835         fastclk = dotclk / (2*100);
 836         updrate = 0;
 837         minupdate = 19200;
 838         fracbits = 1;
 839         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 840         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 841
 842         /* based on hardware requirement, prefer smaller n to precision */
 843         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 844                 updrate = refclk / n;
 845                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 846                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 847                                 if (p2 > 10)
 848                                         p2 = p2 - 1;
 849                                 p = p1 * p2;
 850                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 851                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 852                                         m2 = (((2*(fastclk * p * n / m1 )) +
 853                                                refclk) / (2*refclk));
 854                                         m = m1 * m2;
 855                                         vco = updrate * m;
 856                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 857                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 858                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 859                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 860                                                         bestppm = 0;
 861                                                         flag = 1;
 862                                                 }
 863                                                 if (absppm < bestppm - 10) {
 864                                                         bestppm = absppm;
 865                                                         flag = 1;
 866                                                 }
 867                                                 if (flag) {
 868                                                         bestn = n;
 869                                                         bestm1 = m1;
 870                                                         bestm2 = m2;
 871                                                         bestp1 = p1;
 872                                                         bestp2 = p2;
 873                                                         flag = 0;
 874                                                 }
 875                                         }
 876                                 }
 877                         }
 878                 }
 879         }
 880         best_clock->n = bestn;
 881         best_clock->m1 = bestm1;
 882         best_clock->m2 = bestm2;
 883         best_clock->p1 = bestp1;
 884         best_clock->p2 = bestp2;
 885
 886         return true;
 887 }
 888
 889 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 890                                              enum pipe pipe)
 891 {
 892         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 894
 895         return intel_crtc->cpu_transcoder;
 896 }
 897
 898 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 899 {
 900         struct drm_i915_private *dev_priv = dev->dev_private;
 901         u32 frame, frame_reg = PIPEFRAME(pipe);
 902
 903         frame = I915_READ(frame_reg);
 904
 905         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 906                 DRM_DEBUG_KMS("vblank wait timed out\n");
 907 }
 908
 909 /**
 910  * intel_wait_for_vblank - wait for vblank on a given pipe
 911  * @dev: drm device
 912  * @pipe: pipe to wait for
 913  *
 914  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 915  * mode setting code.
 916  */
 917 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 918 {
 919         struct drm_i915_private *dev_priv = dev->dev_private;
 920         int pipestat_reg = PIPESTAT(pipe);
 921
 922         if (INTEL_INFO(dev)->gen >= 5) {
 923                 ironlake_wait_for_vblank(dev, pipe);
 924                 return;
 925         }
 926
 927         /* Clear existing vblank status. Note this will clear any other
 928          * sticky status fields as well.
 929          *
 930          * This races with i915_driver_irq_handler() with the result
 931          * that either function could miss a vblank event.  Here it is not
 932          * fatal, as we will either wait upon the next vblank interrupt or
 933          * timeout.  Generally speaking intel_wait_for_vblank() is only
 934          * called during modeset at which time the GPU should be idle and
 935          * should *not* be performing page flips and thus not waiting on
 936          * vblanks...
 937          * Currently, the result of us stealing a vblank from the irq
 938          * handler is that a single frame will be skipped during swapbuffers.
 939          */
 940         I915_WRITE(pipestat_reg,
 941                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 942
 943         /* Wait for vblank interrupt bit to set */
 944         if (wait_for(I915_READ(pipestat_reg) &
 945                      PIPE_VBLANK_INTERRUPT_STATUS,
 946                      50))
 947                 DRM_DEBUG_KMS("vblank wait timed out\n");
 948 }
 949
 950 /*
 951  * intel_wait_for_pipe_off - wait for pipe to turn off
 952  * @dev: drm device
 953  * @pipe: pipe to wait for
 954  *
 955  * After disabling a pipe, we can't wait for vblank in the usual way,
 956  * spinning on the vblank interrupt status bit, since we won't actually
 957  * see an interrupt when the pipe is disabled.
 958  *
 959  * On Gen4 and above:
 960  *   wait for the pipe register state bit to turn off
 961  *
 962  * Otherwise:
 963  *   wait for the display line value to settle (it usually
 964  *   ends up stopping at the start of the next frame).
 965  *
 966  */
 967 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 968 {
 969         struct drm_i915_private *dev_priv = dev->dev_private;
 970         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 971                                                                       pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 4) {
 974                 int reg = PIPECONF(cpu_transcoder);
 975
 976                 /* Wait for the Pipe State to go off */
 977                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 978                              100))
 979                         WARN(1, "pipe_off wait timed out\n");
 980         } else {
 981                 u32 last_line, line_mask;
 982                 int reg = PIPEDSL(pipe);
 983                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 984
 985                 if (IS_GEN2(dev))
 986                         line_mask = DSL_LINEMASK_GEN2;
 987                 else
 988                         line_mask = DSL_LINEMASK_GEN3;
 989
 990                 /* Wait for the display line to settle */
 991                 do {
 992                         last_line = I915_READ(reg) & line_mask;
 993                         mdelay(5);
 994                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 995                          time_after(timeout, jiffies));
 996                 if (time_after(jiffies, timeout))
 997                         WARN(1, "pipe_off wait timed out\n");
 998         }
 999 }
1000
1001 /*
1002  * ibx_digital_port_connected - is the specified port connected?
1003  * @dev_priv: i915 private structure
1004  * @port: the port to test
1005  *
1006  * Returns true if @port is connected, false otherwise.
1007  */
1008 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009                                 struct intel_digital_port *port)
1010 {
1011         u32 bit;
1012
1013         if (HAS_PCH_IBX(dev_priv->dev)) {
1014                 switch(port->port) {
1015                 case PORT_B:
1016                         bit = SDE_PORTB_HOTPLUG;
1017                         break;
1018                 case PORT_C:
1019                         bit = SDE_PORTC_HOTPLUG;
1020                         break;
1021                 case PORT_D:
1022                         bit = SDE_PORTD_HOTPLUG;
1023                         break;
1024                 default:
1025                         return true;
1026                 }
1027         } else {
1028                 switch(port->port) {
1029                 case PORT_B:
1030                         bit = SDE_PORTB_HOTPLUG_CPT;
1031                         break;
1032                 case PORT_C:
1033                         bit = SDE_PORTC_HOTPLUG_CPT;
1034                         break;
1035                 case PORT_D:
1036                         bit = SDE_PORTD_HOTPLUG_CPT;
1037                         break;
1038                 default:
1039                         return true;
1040                 }
1041         }
1042
1043         return I915_READ(SDEISR) & bit;
1044 }
1045
1046 static const char *state_string(bool enabled)
1047 {
1048         return enabled ? "on" : "off";
1049 }
1050
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private *dev_priv,
1053                        enum pipe pipe, bool state)
1054 {
1055         int reg;
1056         u32 val;
1057         bool cur_state;
1058
1059         reg = DPLL(pipe);
1060         val = I915_READ(reg);
1061         cur_state = !!(val & DPLL_VCO_ENABLE);
1062         WARN(cur_state != state,
1063              "PLL state assertion failure (expected %s, current %s)\n",
1064              state_string(state), state_string(cur_state));
1065 }
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
1069 /* For ILK+ */
1070 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1071                            struct intel_pch_pll *pll,
1072                            struct intel_crtc *crtc,
1073                            bool state)
1074 {
1075         u32 val;
1076         bool cur_state;
1077
1078         if (HAS_PCH_LPT(dev_priv->dev)) {
1079                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080                 return;
1081         }
1082
1083         if (WARN (!pll,
1084                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1085                 return;
1086
1087         val = I915_READ(pll->pll_reg);
1088         cur_state = !!(val & DPLL_VCO_ENABLE);
1089         WARN(cur_state != state,
1090              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091              pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093         /* Make sure the selected PLL is correctly attached to the transcoder */
1094         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1095                 u32 pch_dpll;
1096
1097                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1098                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1101                           cur_state, crtc->pipe, pch_dpll)) {
1102                         cur_state = !!(val >> (4*crtc->pipe + 3));
1103                         WARN(cur_state != state,
1104                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1105                              pll->pll_reg == _PCH_DPLL_B,
1106                              state_string(state),
1107                              crtc->pipe,
1108                              val);
1109                 }
1110         }
1111 }
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1114
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116                           enum pipe pipe, bool state)
1117 {
1118         int reg;
1119         u32 val;
1120         bool cur_state;
1121         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122                                                                       pipe);
1123
1124         if (HAS_DDI(dev_priv->dev)) {
1125                 /* DDI does not have a specific FDI_TX register */
1126                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129         } else {
1130                 reg = FDI_TX_CTL(pipe);
1131                 val = I915_READ(reg);
1132                 cur_state = !!(val & FDI_TX_ENABLE);
1133         }
1134         WARN(cur_state != state,
1135              "FDI TX state assertion failure (expected %s, current %s)\n",
1136              state_string(state), state_string(cur_state));
1137 }
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142                           enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX state assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159                                       enum pipe pipe)
1160 {
1161         int reg;
1162         u32 val;
1163
1164         /* ILK FDI PLL is always enabled */
1165         if (dev_priv->info->gen == 5)
1166                 return;
1167
1168         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169         if (HAS_DDI(dev_priv->dev))
1170                 return;
1171
1172         reg = FDI_TX_CTL(pipe);
1173         val = I915_READ(reg);
1174         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178                                       enum pipe pipe)
1179 {
1180         int reg;
1181         u32 val;
1182
1183         reg = FDI_RX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189                                   enum pipe pipe)
1190 {
1191         int pp_reg, lvds_reg;
1192         u32 val;
1193         enum pipe panel_pipe = PIPE_A;
1194         bool locked = true;
1195
1196         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197                 pp_reg = PCH_PP_CONTROL;
1198                 lvds_reg = PCH_LVDS;
1199         } else {
1200                 pp_reg = PP_CONTROL;
1201                 lvds_reg = LVDS;
1202         }
1203
1204         val = I915_READ(pp_reg);
1205         if (!(val & PANEL_POWER_ON) ||
1206             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207                 locked = false;
1208
1209         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210                 panel_pipe = PIPE_B;
1211
1212         WARN(panel_pipe == pipe && locked,
1213              "panel assertion failure, pipe %c regs locked\n",
1214              pipe_name(pipe));
1215 }
1216
1217 void assert_pipe(struct drm_i915_private *dev_priv,
1218                  enum pipe pipe, bool state)
1219 {
1220         int reg;
1221         u32 val;
1222         bool cur_state;
1223         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224                                                                       pipe);
1225
1226         /* if we need the pipe A quirk it must be always on */
1227         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228                 state = true;
1229
1230         if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231             !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         int reg, i;
1266         u32 val;
1267         int cur_pipe;
1268
1269         /* Planes are fixed to pipes on ILK+ */
1270         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1271                 reg = DSPCNTR(pipe);
1272                 val = I915_READ(reg);
1273                 WARN((val & DISPLAY_PLANE_ENABLE),
1274                      "plane %c assertion failure, should be disabled but not\n",
1275                      plane_name(pipe));
1276                 return;
1277         }
1278
1279         /* Need to check both planes against the pipe */
1280         for (i = 0; i < 2; i++) {
1281                 reg = DSPCNTR(i);
1282                 val = I915_READ(reg);
1283                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284                         DISPPLANE_SEL_PIPE_SHIFT;
1285                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1286                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287                      plane_name(i), pipe_name(pipe));
1288         }
1289 }
1290
1291 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1292 {
1293         u32 val;
1294         bool enabled;
1295
1296         if (HAS_PCH_LPT(dev_priv->dev)) {
1297                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1298                 return;
1299         }
1300
1301         val = I915_READ(PCH_DREF_CONTROL);
1302         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1303                             DREF_SUPERSPREAD_SOURCE_MASK));
1304         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1305 }
1306
1307 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1308                                        enum pipe pipe)
1309 {
1310         int reg;
1311         u32 val;
1312         bool enabled;
1313
1314         reg = TRANSCONF(pipe);
1315         val = I915_READ(reg);
1316         enabled = !!(val & TRANS_ENABLE);
1317         WARN(enabled,
1318              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1319              pipe_name(pipe));
1320 }
1321
1322 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1323                             enum pipe pipe, u32 port_sel, u32 val)
1324 {
1325         if ((val & DP_PORT_EN) == 0)
1326                 return false;
1327
1328         if (HAS_PCH_CPT(dev_priv->dev)) {
1329                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1330                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1331                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1332                         return false;
1333         } else {
1334                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum pipe pipe, u32 val)
1342 {
1343         if ((val & SDVO_ENABLE) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum pipe pipe, u32 val)
1358 {
1359         if ((val & LVDS_PORT_EN) == 0)
1360                 return false;
1361
1362         if (HAS_PCH_CPT(dev_priv->dev)) {
1363                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364                         return false;
1365         } else {
1366                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1367                         return false;
1368         }
1369         return true;
1370 }
1371
1372 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1373                               enum pipe pipe, u32 val)
1374 {
1375         if ((val & ADPA_DAC_ENABLE) == 0)
1376                 return false;
1377         if (HAS_PCH_CPT(dev_priv->dev)) {
1378                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379                         return false;
1380         } else {
1381                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1382                         return false;
1383         }
1384         return true;
1385 }
1386
1387 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1388                                    enum pipe pipe, int reg, u32 port_sel)
1389 {
1390         u32 val = I915_READ(reg);
1391         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1392              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1393              reg, pipe_name(pipe));
1394
1395         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1396              && (val & DP_PIPEB_SELECT),
1397              "IBX PCH dp port still using transcoder B\n");
1398 }
1399
1400 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1401                                      enum pipe pipe, int reg)
1402 {
1403         u32 val = I915_READ(reg);
1404         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1405              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1406              reg, pipe_name(pipe));
1407
1408         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1409              && (val & SDVO_PIPE_B_SELECT),
1410              "IBX PCH hdmi port still using transcoder B\n");
1411 }
1412
1413 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1414                                       enum pipe pipe)
1415 {
1416         int reg;
1417         u32 val;
1418
1419         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1420         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1421         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1422
1423         reg = PCH_ADPA;
1424         val = I915_READ(reg);
1425         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1426              "PCH VGA enabled on transcoder %c, should be disabled\n",
1427              pipe_name(pipe));
1428
1429         reg = PCH_LVDS;
1430         val = I915_READ(reg);
1431         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1432              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1433              pipe_name(pipe));
1434
1435         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1436         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1437         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1438 }
1439
1440 /**
1441  * intel_enable_pll - enable a PLL
1442  * @dev_priv: i915 private structure
1443  * @pipe: pipe PLL to enable
1444  *
1445  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1446  * make sure the PLL reg is writable first though, since the panel write
1447  * protect mechanism may be enabled.
1448  *
1449  * Note!  This is for pre-ILK only.
1450  *
1451  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1452  */
1453 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1454 {
1455         int reg;
1456         u32 val;
1457
1458         /* No really, not for ILK+ */
1459         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1460
1461         /* PLL is protected by panel, make sure we can write it */
1462         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1463                 assert_panel_unlocked(dev_priv, pipe);
1464
1465         reg = DPLL(pipe);
1466         val = I915_READ(reg);
1467         val |= DPLL_VCO_ENABLE;
1468
1469         /* We do this three times for luck */
1470         I915_WRITE(reg, val);
1471         POSTING_READ(reg);
1472         udelay(150); /* wait for warmup */
1473         I915_WRITE(reg, val);
1474         POSTING_READ(reg);
1475         udelay(150); /* wait for warmup */
1476         I915_WRITE(reg, val);
1477         POSTING_READ(reg);
1478         udelay(150); /* wait for warmup */
1479 }
1480
1481 /**
1482  * intel_disable_pll - disable a PLL
1483  * @dev_priv: i915 private structure
1484  * @pipe: pipe PLL to disable
1485  *
1486  * Disable the PLL for @pipe, making sure the pipe is off first.
1487  *
1488  * Note!  This is for pre-ILK only.
1489  */
1490 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1491 {
1492         int reg;
1493         u32 val;
1494
1495         /* Don't disable pipe A or pipe A PLLs if needed */
1496         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497                 return;
1498
1499         /* Make sure the pipe isn't still relying on us */
1500         assert_pipe_disabled(dev_priv, pipe);
1501
1502         reg = DPLL(pipe);
1503         val = I915_READ(reg);
1504         val &= ~DPLL_VCO_ENABLE;
1505         I915_WRITE(reg, val);
1506         POSTING_READ(reg);
1507 }
1508
1509 /* SBI access */
1510 static void
1511 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1512                 enum intel_sbi_destination destination)
1513 {
1514         u32 tmp;
1515
1516         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1517
1518         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1519                                 100)) {
1520                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1521                 return;
1522         }
1523
1524         I915_WRITE(SBI_ADDR, (reg << 16));
1525         I915_WRITE(SBI_DATA, value);
1526
1527         if (destination == SBI_ICLK)
1528                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1529         else
1530                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1531         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1532
1533         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1534                                 100)) {
1535                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1536                 return;
1537         }
1538 }
1539
1540 static u32
1541 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542                enum intel_sbi_destination destination)
1543 {
1544         u32 value = 0;
1545         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1546
1547         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1548                                 100)) {
1549                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1550                 return 0;
1551         }
1552
1553         I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555         if (destination == SBI_ICLK)
1556                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557         else
1558                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1560
1561         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1562                                 100)) {
1563                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1564                 return 0;
1565         }
1566
1567         return I915_READ(SBI_DATA);
1568 }
1569
1570 /**
1571  * ironlake_enable_pch_pll - enable PCH PLL
1572  * @dev_priv: i915 private structure
1573  * @pipe: pipe PLL to enable
1574  *
1575  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576  * drives the transcoder clock.
1577  */
1578 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1579 {
1580         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1581         struct intel_pch_pll *pll;
1582         int reg;
1583         u32 val;
1584
1585         /* PCH PLLs only available on ILK, SNB and IVB */
1586         BUG_ON(dev_priv->info->gen < 5);
1587         pll = intel_crtc->pch_pll;
1588         if (pll == NULL)
1589                 return;
1590
1591         if (WARN_ON(pll->refcount == 0))
1592                 return;
1593
1594         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595                       pll->pll_reg, pll->active, pll->on,
1596                       intel_crtc->base.base.id);
1597
1598         /* PCH refclock must be enabled first */
1599         assert_pch_refclk_enabled(dev_priv);
1600
1601         if (pll->active++ && pll->on) {
1602                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1603                 return;
1604         }
1605
1606         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608         reg = pll->pll_reg;
1609         val = I915_READ(reg);
1610         val |= DPLL_VCO_ENABLE;
1611         I915_WRITE(reg, val);
1612         POSTING_READ(reg);
1613         udelay(200);
1614
1615         pll->on = true;
1616 }
1617
1618 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1619 {
1620         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1622         int reg;
1623         u32 val;
1624
1625         /* PCH only available on ILK+ */
1626         BUG_ON(dev_priv->info->gen < 5);
1627         if (pll == NULL)
1628                return;
1629
1630         if (WARN_ON(pll->refcount == 0))
1631                 return;
1632
1633         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634                       pll->pll_reg, pll->active, pll->on,
1635                       intel_crtc->base.base.id);
1636
1637         if (WARN_ON(pll->active == 0)) {
1638                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1639                 return;
1640         }
1641
1642         if (--pll->active) {
1643                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1644                 return;
1645         }
1646
1647         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649         /* Make sure transcoder isn't still depending on us */
1650         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1651
1652         reg = pll->pll_reg;
1653         val = I915_READ(reg);
1654         val &= ~DPLL_VCO_ENABLE;
1655         I915_WRITE(reg, val);
1656         POSTING_READ(reg);
1657         udelay(200);
1658
1659         pll->on = false;
1660 }
1661
1662 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663                                            enum pipe pipe)
1664 {
1665         struct drm_device *dev = dev_priv->dev;
1666         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1667         uint32_t reg, val, pipeconf_val;
1668
1669         /* PCH only available on ILK+ */
1670         BUG_ON(dev_priv->info->gen < 5);
1671
1672         /* Make sure PCH DPLL is enabled */
1673         assert_pch_pll_enabled(dev_priv,
1674                                to_intel_crtc(crtc)->pch_pll,
1675                                to_intel_crtc(crtc));
1676
1677         /* FDI must be feeding us bits for PCH ports */
1678         assert_fdi_tx_enabled(dev_priv, pipe);
1679         assert_fdi_rx_enabled(dev_priv, pipe);
1680
1681         if (HAS_PCH_CPT(dev)) {
1682                 /* Workaround: Set the timing override bit before enabling the
1683                  * pch transcoder. */
1684                 reg = TRANS_CHICKEN2(pipe);
1685                 val = I915_READ(reg);
1686                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687                 I915_WRITE(reg, val);
1688         }
1689
1690         reg = TRANSCONF(pipe);
1691         val = I915_READ(reg);
1692         pipeconf_val = I915_READ(PIPECONF(pipe));
1693
1694         if (HAS_PCH_IBX(dev_priv->dev)) {
1695                 /*
1696                  * make the BPC in transcoder be consistent with
1697                  * that in pipeconf reg.
1698                  */
1699                 val &= ~PIPECONF_BPC_MASK;
1700                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1701         }
1702
1703         val &= ~TRANS_INTERLACE_MASK;
1704         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1705                 if (HAS_PCH_IBX(dev_priv->dev) &&
1706                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707                         val |= TRANS_LEGACY_INTERLACED_ILK;
1708                 else
1709                         val |= TRANS_INTERLACED;
1710         else
1711                 val |= TRANS_PROGRESSIVE;
1712
1713         I915_WRITE(reg, val | TRANS_ENABLE);
1714         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716 }
1717
1718 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1719                                       enum transcoder cpu_transcoder)
1720 {
1721         u32 val, pipeconf_val;
1722
1723         /* PCH only available on ILK+ */
1724         BUG_ON(dev_priv->info->gen < 5);
1725
1726         /* FDI must be feeding us bits for PCH ports */
1727         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1728         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1729
1730         /* Workaround: set timing override bit. */
1731         val = I915_READ(_TRANSA_CHICKEN2);
1732         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1733         I915_WRITE(_TRANSA_CHICKEN2, val);
1734
1735         val = TRANS_ENABLE;
1736         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1737
1738         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739             PIPECONF_INTERLACED_ILK)
1740                 val |= TRANS_INTERLACED;
1741         else
1742                 val |= TRANS_PROGRESSIVE;
1743
1744         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1745         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746                 DRM_ERROR("Failed to enable PCH transcoder\n");
1747 }
1748
1749 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750                                             enum pipe pipe)
1751 {
1752         struct drm_device *dev = dev_priv->dev;
1753         uint32_t reg, val;
1754
1755         /* FDI relies on the transcoder */
1756         assert_fdi_tx_disabled(dev_priv, pipe);
1757         assert_fdi_rx_disabled(dev_priv, pipe);
1758
1759         /* Ports must be off as well */
1760         assert_pch_ports_disabled(dev_priv, pipe);
1761
1762         reg = TRANSCONF(pipe);
1763         val = I915_READ(reg);
1764         val &= ~TRANS_ENABLE;
1765         I915_WRITE(reg, val);
1766         /* wait for PCH transcoder off, transcoder state */
1767         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1768                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1769
1770         if (!HAS_PCH_IBX(dev)) {
1771                 /* Workaround: Clear the timing override chicken bit again. */
1772                 reg = TRANS_CHICKEN2(pipe);
1773                 val = I915_READ(reg);
1774                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775                 I915_WRITE(reg, val);
1776         }
1777 }
1778
1779 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1780 {
1781         u32 val;
1782
1783         val = I915_READ(_TRANSACONF);
1784         val &= ~TRANS_ENABLE;
1785         I915_WRITE(_TRANSACONF, val);
1786         /* wait for PCH transcoder off, transcoder state */
1787         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788                 DRM_ERROR("Failed to disable PCH transcoder\n");
1789
1790         /* Workaround: clear timing override bit. */
1791         val = I915_READ(_TRANSA_CHICKEN2);
1792         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1793         I915_WRITE(_TRANSA_CHICKEN2, val);
1794 }
1795
1796 /**
1797  * intel_enable_pipe - enable a pipe, asserting requirements
1798  * @dev_priv: i915 private structure
1799  * @pipe: pipe to enable
1800  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1801  *
1802  * Enable @pipe, making sure that various hardware specific requirements
1803  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804  *
1805  * @pipe should be %PIPE_A or %PIPE_B.
1806  *
1807  * Will wait until the pipe is actually running (i.e. first vblank) before
1808  * returning.
1809  */
1810 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811                               bool pch_port)
1812 {
1813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814                                                                       pipe);
1815         enum pipe pch_transcoder;
1816         int reg;
1817         u32 val;
1818
1819         if (HAS_PCH_LPT(dev_priv->dev))
1820                 pch_transcoder = TRANSCODER_A;
1821         else
1822                 pch_transcoder = pipe;
1823
1824         /*
1825          * A pipe without a PLL won't actually be able to drive bits from
1826          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1827          * need the check.
1828          */
1829         if (!HAS_PCH_SPLIT(dev_priv->dev))
1830                 assert_pll_enabled(dev_priv, pipe);
1831         else {
1832                 if (pch_port) {
1833                         /* if driving the PCH, we need FDI enabled */
1834                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1835                         assert_fdi_tx_pll_enabled(dev_priv,
1836                                                   (enum pipe) cpu_transcoder);
1837                 }
1838                 /* FIXME: assert CPU port conditions for SNB+ */
1839         }
1840
1841         reg = PIPECONF(cpu_transcoder);
1842         val = I915_READ(reg);
1843         if (val & PIPECONF_ENABLE)
1844                 return;
1845
1846         I915_WRITE(reg, val | PIPECONF_ENABLE);
1847         intel_wait_for_vblank(dev_priv->dev, pipe);
1848 }
1849
1850 /**
1851  * intel_disable_pipe - disable a pipe, asserting requirements
1852  * @dev_priv: i915 private structure
1853  * @pipe: pipe to disable
1854  *
1855  * Disable @pipe, making sure that various hardware specific requirements
1856  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1857  *
1858  * @pipe should be %PIPE_A or %PIPE_B.
1859  *
1860  * Will wait until the pipe has shut down before returning.
1861  */
1862 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1863                                enum pipe pipe)
1864 {
1865         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1866                                                                       pipe);
1867         int reg;
1868         u32 val;
1869
1870         /*
1871          * Make sure planes won't keep trying to pump pixels to us,
1872          * or we might hang the display.
1873          */
1874         assert_planes_disabled(dev_priv, pipe);
1875
1876         /* Don't disable pipe A or pipe A PLLs if needed */
1877         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1878                 return;
1879
1880         reg = PIPECONF(cpu_transcoder);
1881         val = I915_READ(reg);
1882         if ((val & PIPECONF_ENABLE) == 0)
1883                 return;
1884
1885         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1886         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1887 }
1888
1889 /*
1890  * Plane regs are double buffered, going from enabled->disabled needs a
1891  * trigger in order to latch.  The display address reg provides this.
1892  */
1893 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1894                                       enum plane plane)
1895 {
1896         if (dev_priv->info->gen >= 4)
1897                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1898         else
1899                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1900 }
1901
1902 /**
1903  * intel_enable_plane - enable a display plane on a given pipe
1904  * @dev_priv: i915 private structure
1905  * @plane: plane to enable
1906  * @pipe: pipe being fed
1907  *
1908  * Enable @plane on @pipe, making sure that @pipe is running first.
1909  */
1910 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1911                                enum plane plane, enum pipe pipe)
1912 {
1913         int reg;
1914         u32 val;
1915
1916         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917         assert_pipe_enabled(dev_priv, pipe);
1918
1919         reg = DSPCNTR(plane);
1920         val = I915_READ(reg);
1921         if (val & DISPLAY_PLANE_ENABLE)
1922                 return;
1923
1924         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1925         intel_flush_display_plane(dev_priv, plane);
1926         intel_wait_for_vblank(dev_priv->dev, pipe);
1927 }
1928
1929 /**
1930  * intel_disable_plane - disable a display plane
1931  * @dev_priv: i915 private structure
1932  * @plane: plane to disable
1933  * @pipe: pipe consuming the data
1934  *
1935  * Disable @plane; should be an independent operation.
1936  */
1937 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1938                                 enum plane plane, enum pipe pipe)
1939 {
1940         int reg;
1941         u32 val;
1942
1943         reg = DSPCNTR(plane);
1944         val = I915_READ(reg);
1945         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1946                 return;
1947
1948         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1949         intel_flush_display_plane(dev_priv, plane);
1950         intel_wait_for_vblank(dev_priv->dev, pipe);
1951 }
1952
1953 static bool need_vtd_wa(struct drm_device *dev)
1954 {
1955 #ifdef CONFIG_INTEL_IOMMU
1956         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1957                 return true;
1958 #endif
1959         return false;
1960 }
1961
1962 int
1963 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1964                            struct drm_i915_gem_object *obj,
1965                            struct intel_ring_buffer *pipelined)
1966 {
1967         struct drm_i915_private *dev_priv = dev->dev_private;
1968         u32 alignment;
1969         int ret;
1970
1971         switch (obj->tiling_mode) {
1972         case I915_TILING_NONE:
1973                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1974                         alignment = 128 * 1024;
1975                 else if (INTEL_INFO(dev)->gen >= 4)
1976                         alignment = 4 * 1024;
1977                 else
1978                         alignment = 64 * 1024;
1979                 break;
1980         case I915_TILING_X:
1981                 /* pin() will align the object as required by fence */
1982                 alignment = 0;
1983                 break;
1984         case I915_TILING_Y:
1985                 /* FIXME: Is this true? */
1986                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1987                 return -EINVAL;
1988         default:
1989                 BUG();
1990         }
1991
1992         /* Note that the w/a also requires 64 PTE of padding following the
1993          * bo. We currently fill all unused PTE with the shadow page and so
1994          * we should always have valid PTE following the scanout preventing
1995          * the VT-d warning.
1996          */
1997         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1998                 alignment = 256 * 1024;
1999
2000         dev_priv->mm.interruptible = false;
2001         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2002         if (ret)
2003                 goto err_interruptible;
2004
2005         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2006          * fence, whereas 965+ only requires a fence if using
2007          * framebuffer compression.  For simplicity, we always install
2008          * a fence as the cost is not that onerous.
2009          */
2010         ret = i915_gem_object_get_fence(obj);
2011         if (ret)
2012                 goto err_unpin;
2013
2014         i915_gem_object_pin_fence(obj);
2015
2016         dev_priv->mm.interruptible = true;
2017         return 0;
2018
2019 err_unpin:
2020         i915_gem_object_unpin(obj);
2021 err_interruptible:
2022         dev_priv->mm.interruptible = true;
2023         return ret;
2024 }
2025
2026 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2027 {
2028         i915_gem_object_unpin_fence(obj);
2029         i915_gem_object_unpin(obj);
2030 }
2031
2032 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2033  * is assumed to be a power-of-two. */
2034 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2035                                              unsigned int tiling_mode,
2036                                              unsigned int cpp,
2037                                              unsigned int pitch)
2038 {
2039         if (tiling_mode != I915_TILING_NONE) {
2040                 unsigned int tile_rows, tiles;
2041
2042                 tile_rows = *y / 8;
2043                 *y %= 8;
2044
2045                 tiles = *x / (512/cpp);
2046                 *x %= 512/cpp;
2047
2048                 return tile_rows * pitch * 8 + tiles * 4096;
2049         } else {
2050                 unsigned int offset;
2051
2052                 offset = *y * pitch + *x * cpp;
2053                 *y = 0;
2054                 *x = (offset & 4095) / cpp;
2055                 return offset & -4096;
2056         }
2057 }
2058
2059 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2060                              int x, int y)
2061 {
2062         struct drm_device *dev = crtc->dev;
2063         struct drm_i915_private *dev_priv = dev->dev_private;
2064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2065         struct intel_framebuffer *intel_fb;
2066         struct drm_i915_gem_object *obj;
2067         int plane = intel_crtc->plane;
2068         unsigned long linear_offset;
2069         u32 dspcntr;
2070         u32 reg;
2071
2072         switch (plane) {
2073         case 0:
2074         case 1:
2075                 break;
2076         default:
2077                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2078                 return -EINVAL;
2079         }
2080
2081         intel_fb = to_intel_framebuffer(fb);
2082         obj = intel_fb->obj;
2083
2084         reg = DSPCNTR(plane);
2085         dspcntr = I915_READ(reg);
2086         /* Mask out pixel format bits in case we change it */
2087         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2088         switch (fb->pixel_format) {
2089         case DRM_FORMAT_C8:
2090                 dspcntr |= DISPPLANE_8BPP;
2091                 break;
2092         case DRM_FORMAT_XRGB1555:
2093         case DRM_FORMAT_ARGB1555:
2094                 dspcntr |= DISPPLANE_BGRX555;
2095                 break;
2096         case DRM_FORMAT_RGB565:
2097                 dspcntr |= DISPPLANE_BGRX565;
2098                 break;
2099         case DRM_FORMAT_XRGB8888:
2100         case DRM_FORMAT_ARGB8888:
2101                 dspcntr |= DISPPLANE_BGRX888;
2102                 break;
2103         case DRM_FORMAT_XBGR8888:
2104         case DRM_FORMAT_ABGR8888:
2105                 dspcntr |= DISPPLANE_RGBX888;
2106                 break;
2107         case DRM_FORMAT_XRGB2101010:
2108         case DRM_FORMAT_ARGB2101010:
2109                 dspcntr |= DISPPLANE_BGRX101010;
2110                 break;
2111         case DRM_FORMAT_XBGR2101010:
2112         case DRM_FORMAT_ABGR2101010:
2113                 dspcntr |= DISPPLANE_RGBX101010;
2114                 break;
2115         default:
2116                 BUG();
2117         }
2118
2119         if (INTEL_INFO(dev)->gen >= 4) {
2120                 if (obj->tiling_mode != I915_TILING_NONE)
2121                         dspcntr |= DISPPLANE_TILED;
2122                 else
2123                         dspcntr &= ~DISPPLANE_TILED;
2124         }
2125
2126         I915_WRITE(reg, dspcntr);
2127
2128         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2129
2130         if (INTEL_INFO(dev)->gen >= 4) {
2131                 intel_crtc->dspaddr_offset =
2132                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2133                                                        fb->bits_per_pixel / 8,
2134                                                        fb->pitches[0]);
2135                 linear_offset -= intel_crtc->dspaddr_offset;
2136         } else {
2137                 intel_crtc->dspaddr_offset = linear_offset;
2138         }
2139
2140         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2141                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2142         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2143         if (INTEL_INFO(dev)->gen >= 4) {
2144                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2145                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2146                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2147                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2148         } else
2149                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2150         POSTING_READ(reg);
2151
2152         return 0;
2153 }
2154
2155 static int ironlake_update_plane(struct drm_crtc *crtc,
2156                                  struct drm_framebuffer *fb, int x, int y)
2157 {
2158         struct drm_device *dev = crtc->dev;
2159         struct drm_i915_private *dev_priv = dev->dev_private;
2160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2161         struct intel_framebuffer *intel_fb;
2162         struct drm_i915_gem_object *obj;
2163         int plane = intel_crtc->plane;
2164         unsigned long linear_offset;
2165         u32 dspcntr;
2166         u32 reg;
2167
2168         switch (plane) {
2169         case 0:
2170         case 1:
2171         case 2:
2172                 break;
2173         default:
2174                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2175                 return -EINVAL;
2176         }
2177
2178         intel_fb = to_intel_framebuffer(fb);
2179         obj = intel_fb->obj;
2180
2181         reg = DSPCNTR(plane);
2182         dspcntr = I915_READ(reg);
2183         /* Mask out pixel format bits in case we change it */
2184         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2185         switch (fb->pixel_format) {
2186         case DRM_FORMAT_C8:
2187                 dspcntr |= DISPPLANE_8BPP;
2188                 break;
2189         case DRM_FORMAT_RGB565:
2190                 dspcntr |= DISPPLANE_BGRX565;
2191                 break;
2192         case DRM_FORMAT_XRGB8888:
2193         case DRM_FORMAT_ARGB8888:
2194                 dspcntr |= DISPPLANE_BGRX888;
2195                 break;
2196         case DRM_FORMAT_XBGR8888:
2197         case DRM_FORMAT_ABGR8888:
2198                 dspcntr |= DISPPLANE_RGBX888;
2199                 break;
2200         case DRM_FORMAT_XRGB2101010:
2201         case DRM_FORMAT_ARGB2101010:
2202                 dspcntr |= DISPPLANE_BGRX101010;
2203                 break;
2204         case DRM_FORMAT_XBGR2101010:
2205         case DRM_FORMAT_ABGR2101010:
2206                 dspcntr |= DISPPLANE_RGBX101010;
2207                 break;
2208         default:
2209                 BUG();
2210         }
2211
2212         if (obj->tiling_mode != I915_TILING_NONE)
2213                 dspcntr |= DISPPLANE_TILED;
2214         else
2215                 dspcntr &= ~DISPPLANE_TILED;
2216
2217         /* must disable */
2218         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2219
2220         I915_WRITE(reg, dspcntr);
2221
2222         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2223         intel_crtc->dspaddr_offset =
2224                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2225                                                fb->bits_per_pixel / 8,
2226                                                fb->pitches[0]);
2227         linear_offset -= intel_crtc->dspaddr_offset;
2228
2229         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2230                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2231         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2232         I915_MODIFY_DISPBASE(DSPSURF(plane),
2233                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2234         if (IS_HASWELL(dev)) {
2235                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2236         } else {
2237                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2238                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2239         }
2240         POSTING_READ(reg);
2241
2242         return 0;
2243 }
2244
2245 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2246 static int
2247 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2248                            int x, int y, enum mode_set_atomic state)
2249 {
2250         struct drm_device *dev = crtc->dev;
2251         struct drm_i915_private *dev_priv = dev->dev_private;
2252
2253         if (dev_priv->display.disable_fbc)
2254                 dev_priv->display.disable_fbc(dev);
2255         intel_increase_pllclock(crtc);
2256
2257         return dev_priv->display.update_plane(crtc, fb, x, y);
2258 }
2259
2260 void intel_display_handle_reset(struct drm_device *dev)
2261 {
2262         struct drm_i915_private *dev_priv = dev->dev_private;
2263         struct drm_crtc *crtc;
2264
2265         /*
2266          * Flips in the rings have been nuked by the reset,
2267          * so complete all pending flips so that user space
2268          * will get its events and not get stuck.
2269          *
2270          * Also update the base address of all primary
2271          * planes to the the last fb to make sure we're
2272          * showing the correct fb after a reset.
2273          *
2274          * Need to make two loops over the crtcs so that we
2275          * don't try to grab a crtc mutex before the
2276          * pending_flip_queue really got woken up.
2277          */
2278
2279         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2280                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281                 enum plane plane = intel_crtc->plane;
2282
2283                 intel_prepare_page_flip(dev, plane);
2284                 intel_finish_page_flip_plane(dev, plane);
2285         }
2286
2287         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2288                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289
2290                 mutex_lock(&crtc->mutex);
2291                 if (intel_crtc->active)
2292                         dev_priv->display.update_plane(crtc, crtc->fb,
2293                                                        crtc->x, crtc->y);
2294                 mutex_unlock(&crtc->mutex);
2295         }
2296 }
2297
2298 static int
2299 intel_finish_fb(struct drm_framebuffer *old_fb)
2300 {
2301         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2302         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2303         bool was_interruptible = dev_priv->mm.interruptible;
2304         int ret;
2305
2306         /* Big Hammer, we also need to ensure that any pending
2307          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2308          * current scanout is retired before unpinning the old
2309          * framebuffer.
2310          *
2311          * This should only fail upon a hung GPU, in which case we
2312          * can safely continue.
2313          */
2314         dev_priv->mm.interruptible = false;
2315         ret = i915_gem_object_finish_gpu(obj);
2316         dev_priv->mm.interruptible = was_interruptible;
2317
2318         return ret;
2319 }
2320
2321 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2322 {
2323         struct drm_device *dev = crtc->dev;
2324         struct drm_i915_master_private *master_priv;
2325         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2326
2327         if (!dev->primary->master)
2328                 return;
2329
2330         master_priv = dev->primary->master->driver_priv;
2331         if (!master_priv->sarea_priv)
2332                 return;
2333
2334         switch (intel_crtc->pipe) {
2335         case 0:
2336                 master_priv->sarea_priv->pipeA_x = x;
2337                 master_priv->sarea_priv->pipeA_y = y;
2338                 break;
2339         case 1:
2340                 master_priv->sarea_priv->pipeB_x = x;
2341                 master_priv->sarea_priv->pipeB_y = y;
2342                 break;
2343         default:
2344                 break;
2345         }
2346 }
2347
2348 static int
2349 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2350                     struct drm_framebuffer *fb)
2351 {
2352         struct drm_device *dev = crtc->dev;
2353         struct drm_i915_private *dev_priv = dev->dev_private;
2354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2355         struct drm_framebuffer *old_fb;
2356         int ret;
2357
2358         /* no fb bound */
2359         if (!fb) {
2360                 DRM_ERROR("No FB bound\n");
2361                 return 0;
2362         }
2363
2364         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2365                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2366                                 intel_crtc->plane,
2367                                 INTEL_INFO(dev)->num_pipes);
2368                 return -EINVAL;
2369         }
2370
2371         mutex_lock(&dev->struct_mutex);
2372         ret = intel_pin_and_fence_fb_obj(dev,
2373                                          to_intel_framebuffer(fb)->obj,
2374                                          NULL);
2375         if (ret != 0) {
2376                 mutex_unlock(&dev->struct_mutex);
2377                 DRM_ERROR("pin & fence failed\n");
2378                 return ret;
2379         }
2380
2381         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2382         if (ret) {
2383                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2384                 mutex_unlock(&dev->struct_mutex);
2385                 DRM_ERROR("failed to update base address\n");
2386                 return ret;
2387         }
2388
2389         old_fb = crtc->fb;
2390         crtc->fb = fb;
2391         crtc->x = x;
2392         crtc->y = y;
2393
2394         if (old_fb) {
2395                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2396                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2397         }
2398
2399         intel_update_fbc(dev);
2400         mutex_unlock(&dev->struct_mutex);
2401
2402         intel_crtc_update_sarea_pos(crtc, x, y);
2403
2404         return 0;
2405 }
2406
2407 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2408 {
2409         struct drm_device *dev = crtc->dev;
2410         struct drm_i915_private *dev_priv = dev->dev_private;
2411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412         int pipe = intel_crtc->pipe;
2413         u32 reg, temp;
2414
2415         /* enable normal train */
2416         reg = FDI_TX_CTL(pipe);
2417         temp = I915_READ(reg);
2418         if (IS_IVYBRIDGE(dev)) {
2419                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2420                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2421         } else {
2422                 temp &= ~FDI_LINK_TRAIN_NONE;
2423                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2424         }
2425         I915_WRITE(reg, temp);
2426
2427         reg = FDI_RX_CTL(pipe);
2428         temp = I915_READ(reg);
2429         if (HAS_PCH_CPT(dev)) {
2430                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2431                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2432         } else {
2433                 temp &= ~FDI_LINK_TRAIN_NONE;
2434                 temp |= FDI_LINK_TRAIN_NONE;
2435         }
2436         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2437
2438         /* wait one idle pattern time */
2439         POSTING_READ(reg);
2440         udelay(1000);
2441
2442         /* IVB wants error correction enabled */
2443         if (IS_IVYBRIDGE(dev))
2444                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2445                            FDI_FE_ERRC_ENABLE);
2446 }
2447
2448 static void ivb_modeset_global_resources(struct drm_device *dev)
2449 {
2450         struct drm_i915_private *dev_priv = dev->dev_private;
2451         struct intel_crtc *pipe_B_crtc =
2452                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2453         struct intel_crtc *pipe_C_crtc =
2454                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2455         uint32_t temp;
2456
2457         /* When everything is off disable fdi C so that we could enable fdi B
2458          * with all lanes. XXX: This misses the case where a pipe is not using
2459          * any pch resources and so doesn't need any fdi lanes. */
2460         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2461                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2462                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2463
2464                 temp = I915_READ(SOUTH_CHICKEN1);
2465                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2466                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2467                 I915_WRITE(SOUTH_CHICKEN1, temp);
2468         }
2469 }
2470
2471 /* The FDI link training functions for ILK/Ibexpeak. */
2472 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2473 {
2474         struct drm_device *dev = crtc->dev;
2475         struct drm_i915_private *dev_priv = dev->dev_private;
2476         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2477         int pipe = intel_crtc->pipe;
2478         int plane = intel_crtc->plane;
2479         u32 reg, temp, tries;
2480
2481         /* FDI needs bits from pipe & plane first */
2482         assert_pipe_enabled(dev_priv, pipe);
2483         assert_plane_enabled(dev_priv, plane);
2484
2485         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2486            for train result */
2487         reg = FDI_RX_IMR(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~FDI_RX_SYMBOL_LOCK;
2490         temp &= ~FDI_RX_BIT_LOCK;
2491         I915_WRITE(reg, temp);
2492         I915_READ(reg);
2493         udelay(150);
2494
2495         /* enable CPU FDI TX and PCH FDI RX */
2496         reg = FDI_TX_CTL(pipe);
2497         temp = I915_READ(reg);
2498         temp &= ~(7 << 19);
2499         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2500         temp &= ~FDI_LINK_TRAIN_NONE;
2501         temp |= FDI_LINK_TRAIN_PATTERN_1;
2502         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2503
2504         reg = FDI_RX_CTL(pipe);
2505         temp = I915_READ(reg);
2506         temp &= ~FDI_LINK_TRAIN_NONE;
2507         temp |= FDI_LINK_TRAIN_PATTERN_1;
2508         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2509
2510         POSTING_READ(reg);
2511         udelay(150);
2512
2513         /* Ironlake workaround, enable clock pointer after FDI enable*/
2514         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2515         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2516                    FDI_RX_PHASE_SYNC_POINTER_EN);
2517
2518         reg = FDI_RX_IIR(pipe);
2519         for (tries = 0; tries < 5; tries++) {
2520                 temp = I915_READ(reg);
2521                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522
2523                 if ((temp & FDI_RX_BIT_LOCK)) {
2524                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2525                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2526                         break;
2527                 }
2528         }
2529         if (tries == 5)
2530                 DRM_ERROR("FDI train 1 fail!\n");
2531
2532         /* Train 2 */
2533         reg = FDI_TX_CTL(pipe);
2534         temp = I915_READ(reg);
2535         temp &= ~FDI_LINK_TRAIN_NONE;
2536         temp |= FDI_LINK_TRAIN_PATTERN_2;
2537         I915_WRITE(reg, temp);
2538
2539         reg = FDI_RX_CTL(pipe);
2540         temp = I915_READ(reg);
2541         temp &= ~FDI_LINK_TRAIN_NONE;
2542         temp |= FDI_LINK_TRAIN_PATTERN_2;
2543         I915_WRITE(reg, temp);
2544
2545         POSTING_READ(reg);
2546         udelay(150);
2547
2548         reg = FDI_RX_IIR(pipe);
2549         for (tries = 0; tries < 5; tries++) {
2550                 temp = I915_READ(reg);
2551                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2552
2553                 if (temp & FDI_RX_SYMBOL_LOCK) {
2554                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2555                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2556                         break;
2557                 }
2558         }
2559         if (tries == 5)
2560                 DRM_ERROR("FDI train 2 fail!\n");
2561
2562         DRM_DEBUG_KMS("FDI train done\n");
2563
2564 }
2565
2566 static const int snb_b_fdi_train_param[] = {
2567         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2568         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2569         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2570         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2571 };
2572
2573 /* The FDI link training functions for SNB/Cougarpoint. */
2574 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2575 {
2576         struct drm_device *dev = crtc->dev;
2577         struct drm_i915_private *dev_priv = dev->dev_private;
2578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2579         int pipe = intel_crtc->pipe;
2580         u32 reg, temp, i, retry;
2581
2582         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2583            for train result */
2584         reg = FDI_RX_IMR(pipe);
2585         temp = I915_READ(reg);
2586         temp &= ~FDI_RX_SYMBOL_LOCK;
2587         temp &= ~FDI_RX_BIT_LOCK;
2588         I915_WRITE(reg, temp);
2589
2590         POSTING_READ(reg);
2591         udelay(150);
2592
2593         /* enable CPU FDI TX and PCH FDI RX */
2594         reg = FDI_TX_CTL(pipe);
2595         temp = I915_READ(reg);
2596         temp &= ~(7 << 19);
2597         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2598         temp &= ~FDI_LINK_TRAIN_NONE;
2599         temp |= FDI_LINK_TRAIN_PATTERN_1;
2600         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2601         /* SNB-B */
2602         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2603         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2604
2605         I915_WRITE(FDI_RX_MISC(pipe),
2606                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2607
2608         reg = FDI_RX_CTL(pipe);
2609         temp = I915_READ(reg);
2610         if (HAS_PCH_CPT(dev)) {
2611                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2612                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2613         } else {
2614                 temp &= ~FDI_LINK_TRAIN_NONE;
2615                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2616         }
2617         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2618
2619         POSTING_READ(reg);
2620         udelay(150);
2621
2622         for (i = 0; i < 4; i++) {
2623                 reg = FDI_TX_CTL(pipe);
2624                 temp = I915_READ(reg);
2625                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626                 temp |= snb_b_fdi_train_param[i];
2627                 I915_WRITE(reg, temp);
2628
2629                 POSTING_READ(reg);
2630                 udelay(500);
2631
2632                 for (retry = 0; retry < 5; retry++) {
2633                         reg = FDI_RX_IIR(pipe);
2634                         temp = I915_READ(reg);
2635                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2636                         if (temp & FDI_RX_BIT_LOCK) {
2637                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2638                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2639                                 break;
2640                         }
2641                         udelay(50);
2642                 }
2643                 if (retry < 5)
2644                         break;
2645         }
2646         if (i == 4)
2647                 DRM_ERROR("FDI train 1 fail!\n");
2648
2649         /* Train 2 */
2650         reg = FDI_TX_CTL(pipe);
2651         temp = I915_READ(reg);
2652         temp &= ~FDI_LINK_TRAIN_NONE;
2653         temp |= FDI_LINK_TRAIN_PATTERN_2;
2654         if (IS_GEN6(dev)) {
2655                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2656                 /* SNB-B */
2657                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2658         }
2659         I915_WRITE(reg, temp);
2660
2661         reg = FDI_RX_CTL(pipe);
2662         temp = I915_READ(reg);
2663         if (HAS_PCH_CPT(dev)) {
2664                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2665                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2666         } else {
2667                 temp &= ~FDI_LINK_TRAIN_NONE;
2668                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2669         }
2670         I915_WRITE(reg, temp);
2671
2672         POSTING_READ(reg);
2673         udelay(150);
2674
2675         for (i = 0; i < 4; i++) {
2676                 reg = FDI_TX_CTL(pipe);
2677                 temp = I915_READ(reg);
2678                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2679                 temp |= snb_b_fdi_train_param[i];
2680                 I915_WRITE(reg, temp);
2681
2682                 POSTING_READ(reg);
2683                 udelay(500);
2684
2685                 for (retry = 0; retry < 5; retry++) {
2686                         reg = FDI_RX_IIR(pipe);
2687                         temp = I915_READ(reg);
2688                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2689                         if (temp & FDI_RX_SYMBOL_LOCK) {
2690                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2691                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2692                                 break;
2693                         }
2694                         udelay(50);
2695                 }
2696                 if (retry < 5)
2697                         break;
2698         }
2699         if (i == 4)
2700                 DRM_ERROR("FDI train 2 fail!\n");
2701
2702         DRM_DEBUG_KMS("FDI train done.\n");
2703 }
2704
2705 /* Manual link training for Ivy Bridge A0 parts */
2706 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2707 {
2708         struct drm_device *dev = crtc->dev;
2709         struct drm_i915_private *dev_priv = dev->dev_private;
2710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2711         int pipe = intel_crtc->pipe;
2712         u32 reg, temp, i;
2713
2714         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2715            for train result */
2716         reg = FDI_RX_IMR(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~FDI_RX_SYMBOL_LOCK;
2719         temp &= ~FDI_RX_BIT_LOCK;
2720         I915_WRITE(reg, temp);
2721
2722         POSTING_READ(reg);
2723         udelay(150);
2724
2725         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2726                       I915_READ(FDI_RX_IIR(pipe)));
2727
2728         /* enable CPU FDI TX and PCH FDI RX */
2729         reg = FDI_TX_CTL(pipe);
2730         temp = I915_READ(reg);
2731         temp &= ~(7 << 19);
2732         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2733         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2734         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2735         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2736         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2737         temp |= FDI_COMPOSITE_SYNC;
2738         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2739
2740         I915_WRITE(FDI_RX_MISC(pipe),
2741                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2742
2743         reg = FDI_RX_CTL(pipe);
2744         temp = I915_READ(reg);
2745         temp &= ~FDI_LINK_TRAIN_AUTO;
2746         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2747         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2748         temp |= FDI_COMPOSITE_SYNC;
2749         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2750
2751         POSTING_READ(reg);
2752         udelay(150);
2753
2754         for (i = 0; i < 4; i++) {
2755                 reg = FDI_TX_CTL(pipe);
2756                 temp = I915_READ(reg);
2757                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758                 temp |= snb_b_fdi_train_param[i];
2759                 I915_WRITE(reg, temp);
2760
2761                 POSTING_READ(reg);
2762                 udelay(500);
2763
2764                 reg = FDI_RX_IIR(pipe);
2765                 temp = I915_READ(reg);
2766                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2767
2768                 if (temp & FDI_RX_BIT_LOCK ||
2769                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2770                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2771                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2772                         break;
2773                 }
2774         }
2775         if (i == 4)
2776                 DRM_ERROR("FDI train 1 fail!\n");
2777
2778         /* Train 2 */
2779         reg = FDI_TX_CTL(pipe);
2780         temp = I915_READ(reg);
2781         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2782         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2783         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2784         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2785         I915_WRITE(reg, temp);
2786
2787         reg = FDI_RX_CTL(pipe);
2788         temp = I915_READ(reg);
2789         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2790         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2791         I915_WRITE(reg, temp);
2792
2793         POSTING_READ(reg);
2794         udelay(150);
2795
2796         for (i = 0; i < 4; i++) {
2797                 reg = FDI_TX_CTL(pipe);
2798                 temp = I915_READ(reg);
2799                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2800                 temp |= snb_b_fdi_train_param[i];
2801                 I915_WRITE(reg, temp);
2802
2803                 POSTING_READ(reg);
2804                 udelay(500);
2805
2806                 reg = FDI_RX_IIR(pipe);
2807                 temp = I915_READ(reg);
2808                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2809
2810                 if (temp & FDI_RX_SYMBOL_LOCK) {
2811                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2812                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2813                         break;
2814                 }
2815         }
2816         if (i == 4)
2817                 DRM_ERROR("FDI train 2 fail!\n");
2818
2819         DRM_DEBUG_KMS("FDI train done.\n");
2820 }
2821
2822 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2823 {
2824         struct drm_device *dev = intel_crtc->base.dev;
2825         struct drm_i915_private *dev_priv = dev->dev_private;
2826         int pipe = intel_crtc->pipe;
2827         u32 reg, temp;
2828
2829
2830         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2831         reg = FDI_RX_CTL(pipe);
2832         temp = I915_READ(reg);
2833         temp &= ~((0x7 << 19) | (0x7 << 16));
2834         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2835         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2836         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2837
2838         POSTING_READ(reg);
2839         udelay(200);
2840
2841         /* Switch from Rawclk to PCDclk */
2842         temp = I915_READ(reg);
2843         I915_WRITE(reg, temp | FDI_PCDCLK);
2844
2845         POSTING_READ(reg);
2846         udelay(200);
2847
2848         /* Enable CPU FDI TX PLL, always on for Ironlake */
2849         reg = FDI_TX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2852                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2853
2854                 POSTING_READ(reg);
2855                 udelay(100);
2856         }
2857 }
2858
2859 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2860 {
2861         struct drm_device *dev = intel_crtc->base.dev;
2862         struct drm_i915_private *dev_priv = dev->dev_private;
2863         int pipe = intel_crtc->pipe;
2864         u32 reg, temp;
2865
2866         /* Switch from PCDclk to Rawclk */
2867         reg = FDI_RX_CTL(pipe);
2868         temp = I915_READ(reg);
2869         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2870
2871         /* Disable CPU FDI TX PLL */
2872         reg = FDI_TX_CTL(pipe);
2873         temp = I915_READ(reg);
2874         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2875
2876         POSTING_READ(reg);
2877         udelay(100);
2878
2879         reg = FDI_RX_CTL(pipe);
2880         temp = I915_READ(reg);
2881         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2882
2883         /* Wait for the clocks to turn off. */
2884         POSTING_READ(reg);
2885         udelay(100);
2886 }
2887
2888 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2889 {
2890         struct drm_device *dev = crtc->dev;
2891         struct drm_i915_private *dev_priv = dev->dev_private;
2892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2893         int pipe = intel_crtc->pipe;
2894         u32 reg, temp;
2895
2896         /* disable CPU FDI tx and PCH FDI rx */
2897         reg = FDI_TX_CTL(pipe);
2898         temp = I915_READ(reg);
2899         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2900         POSTING_READ(reg);
2901
2902         reg = FDI_RX_CTL(pipe);
2903         temp = I915_READ(reg);
2904         temp &= ~(0x7 << 16);
2905         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2906         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2907
2908         POSTING_READ(reg);
2909         udelay(100);
2910
2911         /* Ironlake workaround, disable clock pointer after downing FDI */
2912         if (HAS_PCH_IBX(dev)) {
2913                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2914         }
2915
2916         /* still set train pattern 1 */
2917         reg = FDI_TX_CTL(pipe);
2918         temp = I915_READ(reg);
2919         temp &= ~FDI_LINK_TRAIN_NONE;
2920         temp |= FDI_LINK_TRAIN_PATTERN_1;
2921         I915_WRITE(reg, temp);
2922
2923         reg = FDI_RX_CTL(pipe);
2924         temp = I915_READ(reg);
2925         if (HAS_PCH_CPT(dev)) {
2926                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2927                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2928         } else {
2929                 temp &= ~FDI_LINK_TRAIN_NONE;
2930                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2931         }
2932         /* BPC in FDI rx is consistent with that in PIPECONF */
2933         temp &= ~(0x07 << 16);
2934         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2935         I915_WRITE(reg, temp);
2936
2937         POSTING_READ(reg);
2938         udelay(100);
2939 }
2940
2941 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2942 {
2943         struct drm_device *dev = crtc->dev;
2944         struct drm_i915_private *dev_priv = dev->dev_private;
2945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2946         unsigned long flags;
2947         bool pending;
2948
2949         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2950             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2951                 return false;
2952
2953         spin_lock_irqsave(&dev->event_lock, flags);
2954         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2955         spin_unlock_irqrestore(&dev->event_lock, flags);
2956
2957         return pending;
2958 }
2959
2960 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2961 {
2962         struct drm_device *dev = crtc->dev;
2963         struct drm_i915_private *dev_priv = dev->dev_private;
2964
2965         if (crtc->fb == NULL)
2966                 return;
2967
2968         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2969
2970         wait_event(dev_priv->pending_flip_queue,
2971                    !intel_crtc_has_pending_flip(crtc));
2972
2973         mutex_lock(&dev->struct_mutex);
2974         intel_finish_fb(crtc->fb);
2975         mutex_unlock(&dev->struct_mutex);
2976 }
2977
2978 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2979 {
2980         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2981 }
2982
2983 /* Program iCLKIP clock to the desired frequency */
2984 static void lpt_program_iclkip(struct drm_crtc *crtc)
2985 {
2986         struct drm_device *dev = crtc->dev;
2987         struct drm_i915_private *dev_priv = dev->dev_private;
2988         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2989         u32 temp;
2990
2991         mutex_lock(&dev_priv->dpio_lock);
2992
2993         /* It is necessary to ungate the pixclk gate prior to programming
2994          * the divisors, and gate it back when it is done.
2995          */
2996         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2997
2998         /* Disable SSCCTL */
2999         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3000                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3001                                 SBI_SSCCTL_DISABLE,
3002                         SBI_ICLK);
3003
3004         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3005         if (crtc->mode.clock == 20000) {
3006                 auxdiv = 1;
3007                 divsel = 0x41;
3008                 phaseinc = 0x20;
3009         } else {
3010                 /* The iCLK virtual clock root frequency is in MHz,
3011                  * but the crtc->mode.clock in in KHz. To get the divisors,
3012                  * it is necessary to divide one by another, so we
3013                  * convert the virtual clock precision to KHz here for higher
3014                  * precision.
3015                  */
3016                 u32 iclk_virtual_root_freq = 172800 * 1000;
3017                 u32 iclk_pi_range = 64;
3018                 u32 desired_divisor, msb_divisor_value, pi_value;
3019
3020                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3021                 msb_divisor_value = desired_divisor / iclk_pi_range;
3022                 pi_value = desired_divisor % iclk_pi_range;
3023
3024                 auxdiv = 0;
3025                 divsel = msb_divisor_value - 2;
3026                 phaseinc = pi_value;
3027         }
3028
3029         /* This should not happen with any sane values */
3030         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3031                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3032         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3033                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3034
3035         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3036                         crtc->mode.clock,
3037                         auxdiv,
3038                         divsel,
3039                         phasedir,
3040                         phaseinc);
3041
3042         /* Program SSCDIVINTPHASE6 */
3043         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3044         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3045         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3046         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3047         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3048         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3049         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3050         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3051
3052         /* Program SSCAUXDIV */
3053         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3054         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3055         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3056         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3057
3058         /* Enable modulator and associated divider */
3059         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3060         temp &= ~SBI_SSCCTL_DISABLE;
3061         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3062
3063         /* Wait for initialization time */
3064         udelay(24);
3065
3066         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3067
3068         mutex_unlock(&dev_priv->dpio_lock);
3069 }
3070
3071 /*
3072  * Enable PCH resources required for PCH ports:
3073  *   - PCH PLLs
3074  *   - FDI training & RX/TX
3075  *   - update transcoder timings
3076  *   - DP transcoding bits
3077  *   - transcoder
3078  */
3079 static void ironlake_pch_enable(struct drm_crtc *crtc)
3080 {
3081         struct drm_device *dev = crtc->dev;
3082         struct drm_i915_private *dev_priv = dev->dev_private;
3083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084         int pipe = intel_crtc->pipe;
3085         u32 reg, temp;
3086
3087         assert_transcoder_disabled(dev_priv, pipe);
3088
3089         /* Write the TU size bits before fdi link training, so that error
3090          * detection works. */
3091         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3092                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3093
3094         /* For PCH output, training FDI link */
3095         dev_priv->display.fdi_link_train(crtc);
3096
3097         /* XXX: pch pll's can be enabled any time before we enable the PCH
3098          * transcoder, and we actually should do this to not upset any PCH
3099          * transcoder that already use the clock when we share it.
3100          *
3101          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3102          * unconditionally resets the pll - we need that to have the right LVDS
3103          * enable sequence. */
3104         ironlake_enable_pch_pll(intel_crtc);
3105
3106         if (HAS_PCH_CPT(dev)) {
3107                 u32 sel;
3108
3109                 temp = I915_READ(PCH_DPLL_SEL);
3110                 switch (pipe) {
3111                 default:
3112                 case 0:
3113                         temp |= TRANSA_DPLL_ENABLE;
3114                         sel = TRANSA_DPLLB_SEL;
3115                         break;
3116                 case 1:
3117                         temp |= TRANSB_DPLL_ENABLE;
3118                         sel = TRANSB_DPLLB_SEL;
3119                         break;
3120                 case 2:
3121                         temp |= TRANSC_DPLL_ENABLE;
3122                         sel = TRANSC_DPLLB_SEL;
3123                         break;
3124                 }
3125                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3126                         temp |= sel;
3127                 else
3128                         temp &= ~sel;
3129                 I915_WRITE(PCH_DPLL_SEL, temp);
3130         }
3131
3132         /* set transcoder timing, panel must allow it */
3133         assert_panel_unlocked(dev_priv, pipe);
3134         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3135         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3136         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3137
3138         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3139         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3140         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3141         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3142
3143         intel_fdi_normal_train(crtc);
3144
3145         /* For PCH DP, enable TRANS_DP_CTL */
3146         if (HAS_PCH_CPT(dev) &&
3147             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3148              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3149                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3150                 reg = TRANS_DP_CTL(pipe);
3151                 temp = I915_READ(reg);
3152                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3153                           TRANS_DP_SYNC_MASK |
3154                           TRANS_DP_BPC_MASK);
3155                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3156                          TRANS_DP_ENH_FRAMING);
3157                 temp |= bpc << 9; /* same format but at 11:9 */
3158
3159                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3160                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3161                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3162                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3163
3164                 switch (intel_trans_dp_port_sel(crtc)) {
3165                 case PCH_DP_B:
3166                         temp |= TRANS_DP_PORT_SEL_B;
3167                         break;
3168                 case PCH_DP_C:
3169                         temp |= TRANS_DP_PORT_SEL_C;
3170                         break;
3171                 case PCH_DP_D:
3172                         temp |= TRANS_DP_PORT_SEL_D;
3173                         break;
3174                 default:
3175                         BUG();
3176                 }
3177
3178                 I915_WRITE(reg, temp);
3179         }
3180
3181         ironlake_enable_pch_transcoder(dev_priv, pipe);
3182 }
3183
3184 static void lpt_pch_enable(struct drm_crtc *crtc)
3185 {
3186         struct drm_device *dev = crtc->dev;
3187         struct drm_i915_private *dev_priv = dev->dev_private;
3188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3190
3191         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3192
3193         lpt_program_iclkip(crtc);
3194
3195         /* Set transcoder timing. */
3196         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3197         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3198         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3199
3200         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3201         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3202         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3203         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3204
3205         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3206 }
3207
3208 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3209 {
3210         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3211
3212         if (pll == NULL)
3213                 return;
3214
3215         if (pll->refcount == 0) {
3216                 WARN(1, "bad PCH PLL refcount\n");
3217                 return;
3218         }
3219
3220         --pll->refcount;
3221         intel_crtc->pch_pll = NULL;
3222 }
3223
3224 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3225 {
3226         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3227         struct intel_pch_pll *pll;
3228         int i;
3229
3230         pll = intel_crtc->pch_pll;
3231         if (pll) {
3232                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3233                               intel_crtc->base.base.id, pll->pll_reg);
3234                 goto prepare;
3235         }
3236
3237         if (HAS_PCH_IBX(dev_priv->dev)) {
3238                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3239                 i = intel_crtc->pipe;
3240                 pll = &dev_priv->pch_plls[i];
3241
3242                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3243                               intel_crtc->base.base.id, pll->pll_reg);
3244
3245                 goto found;
3246         }
3247
3248         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3249                 pll = &dev_priv->pch_plls[i];
3250
3251                 /* Only want to check enabled timings first */
3252                 if (pll->refcount == 0)
3253                         continue;
3254
3255                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3256                     fp == I915_READ(pll->fp0_reg)) {
3257                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3258                                       intel_crtc->base.base.id,
3259                                       pll->pll_reg, pll->refcount, pll->active);
3260
3261                         goto found;
3262                 }
3263         }
3264
3265         /* Ok no matching timings, maybe there's a free one? */
3266         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3267                 pll = &dev_priv->pch_plls[i];
3268                 if (pll->refcount == 0) {
3269                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3270                                       intel_crtc->base.base.id, pll->pll_reg);
3271                         goto found;
3272                 }
3273         }
3274
3275         return NULL;
3276
3277 found:
3278         intel_crtc->pch_pll = pll;
3279         pll->refcount++;
3280         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3281 prepare: /* separate function? */
3282         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3283
3284         /* Wait for the clocks to stabilize before rewriting the regs */
3285         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3286         POSTING_READ(pll->pll_reg);
3287         udelay(150);
3288
3289         I915_WRITE(pll->fp0_reg, fp);
3290         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3291         pll->on = false;
3292         return pll;
3293 }
3294
3295 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3296 {
3297         struct drm_i915_private *dev_priv = dev->dev_private;
3298         int dslreg = PIPEDSL(pipe);
3299         u32 temp;
3300
3301         temp = I915_READ(dslreg);
3302         udelay(500);
3303         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3304                 if (wait_for(I915_READ(dslreg) != temp, 5))
3305                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3306         }
3307 }
3308
3309 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3310 {
3311         struct drm_device *dev = crtc->dev;
3312         struct drm_i915_private *dev_priv = dev->dev_private;
3313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3314         struct intel_encoder *encoder;
3315         int pipe = intel_crtc->pipe;
3316         int plane = intel_crtc->plane;
3317         u32 temp;
3318
3319         WARN_ON(!crtc->enabled);
3320
3321         if (intel_crtc->active)
3322                 return;
3323
3324         intel_crtc->active = true;
3325         intel_update_watermarks(dev);
3326
3327         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3328                 temp = I915_READ(PCH_LVDS);
3329                 if ((temp & LVDS_PORT_EN) == 0)
3330                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3331         }
3332
3333
3334         if (intel_crtc->config.has_pch_encoder) {
3335                 /* Note: FDI PLL enabling _must_ be done before we enable the
3336                  * cpu pipes, hence this is separate from all the other fdi/pch
3337                  * enabling. */
3338                 ironlake_fdi_pll_enable(intel_crtc);
3339         } else {
3340                 assert_fdi_tx_disabled(dev_priv, pipe);
3341                 assert_fdi_rx_disabled(dev_priv, pipe);
3342         }
3343
3344         for_each_encoder_on_crtc(dev, crtc, encoder)
3345                 if (encoder->pre_enable)
3346                         encoder->pre_enable(encoder);
3347
3348         /* Enable panel fitting for LVDS */
3349         if (dev_priv->pch_pf_size &&
3350             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3351              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3352                 /* Force use of hard-coded filter coefficients
3353                  * as some pre-programmed values are broken,
3354                  * e.g. x201.
3355                  */
3356                 if (IS_IVYBRIDGE(dev))
3357                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3358                                                  PF_PIPE_SEL_IVB(pipe));
3359                 else
3360                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3361                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3362                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3363         }
3364
3365         /*
3366          * On ILK+ LUT must be loaded before the pipe is running but with
3367          * clocks enabled
3368          */
3369         intel_crtc_load_lut(crtc);
3370
3371         intel_enable_pipe(dev_priv, pipe,
3372                           intel_crtc->config.has_pch_encoder);
3373         intel_enable_plane(dev_priv, plane, pipe);
3374
3375         if (intel_crtc->config.has_pch_encoder)
3376                 ironlake_pch_enable(crtc);
3377
3378         mutex_lock(&dev->struct_mutex);
3379         intel_update_fbc(dev);
3380         mutex_unlock(&dev->struct_mutex);
3381
3382         intel_crtc_update_cursor(crtc, true);
3383
3384         for_each_encoder_on_crtc(dev, crtc, encoder)
3385                 encoder->enable(encoder);
3386
3387         if (HAS_PCH_CPT(dev))
3388                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3389
3390         /*
3391          * There seems to be a race in PCH platform hw (at least on some
3392          * outputs) where an enabled pipe still completes any pageflip right
3393          * away (as if the pipe is off) instead of waiting for vblank. As soon
3394          * as the first vblank happend, everything works as expected. Hence just
3395          * wait for one vblank before returning to avoid strange things
3396          * happening.
3397          */
3398         intel_wait_for_vblank(dev, intel_crtc->pipe);
3399 }
3400
3401 static void haswell_crtc_enable(struct drm_crtc *crtc)
3402 {
3403         struct drm_device *dev = crtc->dev;
3404         struct drm_i915_private *dev_priv = dev->dev_private;
3405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3406         struct intel_encoder *encoder;
3407         int pipe = intel_crtc->pipe;
3408         int plane = intel_crtc->plane;
3409
3410         WARN_ON(!crtc->enabled);
3411
3412         if (intel_crtc->active)
3413                 return;
3414
3415         intel_crtc->active = true;
3416         intel_update_watermarks(dev);
3417
3418         if (intel_crtc->config.has_pch_encoder)
3419                 dev_priv->display.fdi_link_train(crtc);
3420
3421         for_each_encoder_on_crtc(dev, crtc, encoder)
3422                 if (encoder->pre_enable)
3423                         encoder->pre_enable(encoder);
3424
3425         intel_ddi_enable_pipe_clock(intel_crtc);
3426
3427         /* Enable panel fitting for eDP */
3428         if (dev_priv->pch_pf_size &&
3429             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3430                 /* Force use of hard-coded filter coefficients
3431                  * as some pre-programmed values are broken,
3432                  * e.g. x201.
3433                  */
3434                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3435                                          PF_PIPE_SEL_IVB(pipe));
3436                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3437                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3438         }
3439
3440         /*
3441          * On ILK+ LUT must be loaded before the pipe is running but with
3442          * clocks enabled
3443          */
3444         intel_crtc_load_lut(crtc);
3445
3446         intel_ddi_set_pipe_settings(crtc);
3447         intel_ddi_enable_transcoder_func(crtc);
3448
3449         intel_enable_pipe(dev_priv, pipe,
3450                           intel_crtc->config.has_pch_encoder);
3451         intel_enable_plane(dev_priv, plane, pipe);
3452
3453         if (intel_crtc->config.has_pch_encoder)
3454                 lpt_pch_enable(crtc);
3455
3456         mutex_lock(&dev->struct_mutex);
3457         intel_update_fbc(dev);
3458         mutex_unlock(&dev->struct_mutex);
3459
3460         intel_crtc_update_cursor(crtc, true);
3461
3462         for_each_encoder_on_crtc(dev, crtc, encoder)
3463                 encoder->enable(encoder);
3464
3465         /*
3466          * There seems to be a race in PCH platform hw (at least on some
3467          * outputs) where an enabled pipe still completes any pageflip right
3468          * away (as if the pipe is off) instead of waiting for vblank. As soon
3469          * as the first vblank happend, everything works as expected. Hence just
3470          * wait for one vblank before returning to avoid strange things
3471          * happening.
3472          */
3473         intel_wait_for_vblank(dev, intel_crtc->pipe);
3474 }
3475
3476 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3477 {
3478         struct drm_device *dev = crtc->dev;
3479         struct drm_i915_private *dev_priv = dev->dev_private;
3480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3481         struct intel_encoder *encoder;
3482         int pipe = intel_crtc->pipe;
3483         int plane = intel_crtc->plane;
3484         u32 reg, temp;
3485
3486
3487         if (!intel_crtc->active)
3488                 return;
3489
3490         for_each_encoder_on_crtc(dev, crtc, encoder)
3491                 encoder->disable(encoder);
3492
3493         intel_crtc_wait_for_pending_flips(crtc);
3494         drm_vblank_off(dev, pipe);
3495         intel_crtc_update_cursor(crtc, false);
3496
3497         intel_disable_plane(dev_priv, plane, pipe);
3498
3499         if (dev_priv->cfb_plane == plane)
3500                 intel_disable_fbc(dev);
3501
3502         intel_disable_pipe(dev_priv, pipe);
3503
3504         /* Disable PF */
3505         I915_WRITE(PF_CTL(pipe), 0);
3506         I915_WRITE(PF_WIN_SZ(pipe), 0);
3507
3508         for_each_encoder_on_crtc(dev, crtc, encoder)
3509                 if (encoder->post_disable)
3510                         encoder->post_disable(encoder);
3511
3512         ironlake_fdi_disable(crtc);
3513
3514         ironlake_disable_pch_transcoder(dev_priv, pipe);
3515
3516         if (HAS_PCH_CPT(dev)) {
3517                 /* disable TRANS_DP_CTL */
3518                 reg = TRANS_DP_CTL(pipe);
3519                 temp = I915_READ(reg);
3520                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3521                 temp |= TRANS_DP_PORT_SEL_NONE;
3522                 I915_WRITE(reg, temp);
3523
3524                 /* disable DPLL_SEL */
3525                 temp = I915_READ(PCH_DPLL_SEL);
3526                 switch (pipe) {
3527                 case 0:
3528                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3529                         break;
3530                 case 1:
3531                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3532                         break;
3533                 case 2:
3534                         /* C shares PLL A or B */
3535                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3536                         break;
3537                 default:
3538                         BUG(); /* wtf */
3539                 }
3540                 I915_WRITE(PCH_DPLL_SEL, temp);
3541         }
3542
3543         /* disable PCH DPLL */
3544         intel_disable_pch_pll(intel_crtc);
3545
3546         ironlake_fdi_pll_disable(intel_crtc);
3547
3548         intel_crtc->active = false;
3549         intel_update_watermarks(dev);
3550
3551         mutex_lock(&dev->struct_mutex);
3552         intel_update_fbc(dev);
3553         mutex_unlock(&dev->struct_mutex);
3554 }
3555
3556 static void haswell_crtc_disable(struct drm_crtc *crtc)
3557 {
3558         struct drm_device *dev = crtc->dev;
3559         struct drm_i915_private *dev_priv = dev->dev_private;
3560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3561         struct intel_encoder *encoder;
3562         int pipe = intel_crtc->pipe;
3563         int plane = intel_crtc->plane;
3564         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3565         bool is_pch_port;
3566
3567         if (!intel_crtc->active)
3568                 return;
3569
3570         is_pch_port = haswell_crtc_driving_pch(crtc);
3571
3572         for_each_encoder_on_crtc(dev, crtc, encoder)
3573                 encoder->disable(encoder);
3574
3575         intel_crtc_wait_for_pending_flips(crtc);
3576         drm_vblank_off(dev, pipe);
3577         intel_crtc_update_cursor(crtc, false);
3578
3579         intel_disable_plane(dev_priv, plane, pipe);
3580
3581         if (dev_priv->cfb_plane == plane)
3582                 intel_disable_fbc(dev);
3583
3584         intel_disable_pipe(dev_priv, pipe);
3585
3586         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3587
3588         /* Disable PF */
3589         I915_WRITE(PF_CTL(pipe), 0);
3590         I915_WRITE(PF_WIN_SZ(pipe), 0);
3591
3592         intel_ddi_disable_pipe_clock(intel_crtc);
3593
3594         for_each_encoder_on_crtc(dev, crtc, encoder)
3595                 if (encoder->post_disable)
3596                         encoder->post_disable(encoder);
3597
3598         if (is_pch_port) {
3599                 lpt_disable_pch_transcoder(dev_priv);
3600                 intel_ddi_fdi_disable(crtc);
3601         }
3602
3603         intel_crtc->active = false;
3604         intel_update_watermarks(dev);
3605
3606         mutex_lock(&dev->struct_mutex);
3607         intel_update_fbc(dev);
3608         mutex_unlock(&dev->struct_mutex);
3609 }
3610
3611 static void ironlake_crtc_off(struct drm_crtc *crtc)
3612 {
3613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614         intel_put_pch_pll(intel_crtc);
3615 }
3616
3617 static void haswell_crtc_off(struct drm_crtc *crtc)
3618 {
3619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3620
3621         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3622          * start using it. */
3623         intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3624
3625         intel_ddi_put_crtc_pll(crtc);
3626 }
3627
3628 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3629 {
3630         if (!enable && intel_crtc->overlay) {
3631                 struct drm_device *dev = intel_crtc->base.dev;
3632                 struct drm_i915_private *dev_priv = dev->dev_private;
3633
3634                 mutex_lock(&dev->struct_mutex);
3635                 dev_priv->mm.interruptible = false;
3636                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3637                 dev_priv->mm.interruptible = true;
3638                 mutex_unlock(&dev->struct_mutex);
3639         }
3640
3641         /* Let userspace switch the overlay on again. In most cases userspace
3642          * has to recompute where to put it anyway.
3643          */
3644 }
3645
3646 /**
3647  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3648  * cursor plane briefly if not already running after enabling the display
3649  * plane.
3650  * This workaround avoids occasional blank screens when self refresh is
3651  * enabled.
3652  */
3653 static void
3654 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3655 {
3656         u32 cntl = I915_READ(CURCNTR(pipe));
3657
3658         if ((cntl & CURSOR_MODE) == 0) {
3659                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3660
3661                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3662                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3663                 intel_wait_for_vblank(dev_priv->dev, pipe);
3664                 I915_WRITE(CURCNTR(pipe), cntl);
3665                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3666                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3667         }
3668 }
3669
3670 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3671 {
3672         struct drm_device *dev = crtc->dev;
3673         struct drm_i915_private *dev_priv = dev->dev_private;
3674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3675         struct intel_encoder *encoder;
3676         int pipe = intel_crtc->pipe;
3677         int plane = intel_crtc->plane;
3678
3679         WARN_ON(!crtc->enabled);
3680
3681         if (intel_crtc->active)
3682                 return;
3683
3684         intel_crtc->active = true;
3685         intel_update_watermarks(dev);
3686
3687         intel_enable_pll(dev_priv, pipe);
3688
3689         for_each_encoder_on_crtc(dev, crtc, encoder)
3690                 if (encoder->pre_enable)
3691                         encoder->pre_enable(encoder);
3692
3693         intel_enable_pipe(dev_priv, pipe, false);
3694         intel_enable_plane(dev_priv, plane, pipe);
3695         if (IS_G4X(dev))
3696                 g4x_fixup_plane(dev_priv, pipe);
3697
3698         intel_crtc_load_lut(crtc);
3699         intel_update_fbc(dev);
3700
3701         /* Give the overlay scaler a chance to enable if it's on this pipe */
3702         intel_crtc_dpms_overlay(intel_crtc, true);
3703         intel_crtc_update_cursor(crtc, true);
3704
3705         for_each_encoder_on_crtc(dev, crtc, encoder)
3706                 encoder->enable(encoder);
3707 }
3708
3709 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3710 {
3711         struct drm_device *dev = crtc->dev;
3712         struct drm_i915_private *dev_priv = dev->dev_private;
3713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3714         struct intel_encoder *encoder;
3715         int pipe = intel_crtc->pipe;
3716         int plane = intel_crtc->plane;
3717         u32 pctl;
3718
3719
3720         if (!intel_crtc->active)
3721                 return;
3722
3723         for_each_encoder_on_crtc(dev, crtc, encoder)
3724                 encoder->disable(encoder);
3725
3726         /* Give the overlay scaler a chance to disable if it's on this pipe */
3727         intel_crtc_wait_for_pending_flips(crtc);
3728         drm_vblank_off(dev, pipe);
3729         intel_crtc_dpms_overlay(intel_crtc, false);
3730         intel_crtc_update_cursor(crtc, false);
3731
3732         if (dev_priv->cfb_plane == plane)
3733                 intel_disable_fbc(dev);
3734
3735         intel_disable_plane(dev_priv, plane, pipe);
3736         intel_disable_pipe(dev_priv, pipe);
3737
3738         /* Disable pannel fitter if it is on this pipe. */
3739         pctl = I915_READ(PFIT_CONTROL);
3740         if ((pctl & PFIT_ENABLE) &&
3741             ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3742                 I915_WRITE(PFIT_CONTROL, 0);
3743
3744         intel_disable_pll(dev_priv, pipe);
3745
3746         intel_crtc->active = false;
3747         intel_update_fbc(dev);
3748         intel_update_watermarks(dev);
3749 }
3750
3751 static void i9xx_crtc_off(struct drm_crtc *crtc)
3752 {
3753 }
3754
3755 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3756                                     bool enabled)
3757 {
3758         struct drm_device *dev = crtc->dev;
3759         struct drm_i915_master_private *master_priv;
3760         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3761         int pipe = intel_crtc->pipe;
3762
3763         if (!dev->primary->master)
3764                 return;
3765
3766         master_priv = dev->primary->master->driver_priv;
3767         if (!master_priv->sarea_priv)
3768                 return;
3769
3770         switch (pipe) {
3771         case 0:
3772                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3773                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3774                 break;
3775         case 1:
3776                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3777                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3778                 break;
3779         default:
3780                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3781                 break;
3782         }
3783 }
3784
3785 /**
3786  * Sets the power management mode of the pipe and plane.
3787  */
3788 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3789 {
3790         struct drm_device *dev = crtc->dev;
3791         struct drm_i915_private *dev_priv = dev->dev_private;
3792         struct intel_encoder *intel_encoder;
3793         bool enable = false;
3794
3795         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3796                 enable |= intel_encoder->connectors_active;
3797
3798         if (enable)
3799                 dev_priv->display.crtc_enable(crtc);
3800         else
3801                 dev_priv->display.crtc_disable(crtc);
3802
3803         intel_crtc_update_sarea(crtc, enable);
3804 }
3805
3806 static void intel_crtc_disable(struct drm_crtc *crtc)
3807 {
3808         struct drm_device *dev = crtc->dev;
3809         struct drm_connector *connector;
3810         struct drm_i915_private *dev_priv = dev->dev_private;
3811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3812
3813         /* crtc should still be enabled when we disable it. */
3814         WARN_ON(!crtc->enabled);
3815
3816         intel_crtc->eld_vld = false;
3817         dev_priv->display.crtc_disable(crtc);
3818         intel_crtc_update_sarea(crtc, false);
3819         dev_priv->display.off(crtc);
3820
3821         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3822         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3823
3824         if (crtc->fb) {
3825                 mutex_lock(&dev->struct_mutex);
3826                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3827                 mutex_unlock(&dev->struct_mutex);
3828                 crtc->fb = NULL;
3829         }
3830
3831         /* Update computed state. */
3832         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3833                 if (!connector->encoder || !connector->encoder->crtc)
3834                         continue;
3835
3836                 if (connector->encoder->crtc != crtc)
3837                         continue;
3838
3839                 connector->dpms = DRM_MODE_DPMS_OFF;
3840                 to_intel_encoder(connector->encoder)->connectors_active = false;
3841         }
3842 }
3843
3844 void intel_modeset_disable(struct drm_device *dev)
3845 {
3846         struct drm_crtc *crtc;
3847
3848         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3849                 if (crtc->enabled)
3850                         intel_crtc_disable(crtc);
3851         }
3852 }
3853
3854 void intel_encoder_destroy(struct drm_encoder *encoder)
3855 {
3856         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3857
3858         drm_encoder_cleanup(encoder);
3859         kfree(intel_encoder);
3860 }
3861
3862 /* Simple dpms helper for encodres with just one connector, no cloning and only
3863  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3864  * state of the entire output pipe. */
3865 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3866 {
3867         if (mode == DRM_MODE_DPMS_ON) {
3868                 encoder->connectors_active = true;
3869
3870                 intel_crtc_update_dpms(encoder->base.crtc);
3871         } else {
3872                 encoder->connectors_active = false;
3873
3874                 intel_crtc_update_dpms(encoder->base.crtc);
3875         }
3876 }
3877
3878 /* Cross check the actual hw state with our own modeset state tracking (and it's
3879  * internal consistency). */
3880 static void intel_connector_check_state(struct intel_connector *connector)
3881 {
3882         if (connector->get_hw_state(connector)) {
3883                 struct intel_encoder *encoder = connector->encoder;
3884                 struct drm_crtc *crtc;
3885                 bool encoder_enabled;
3886                 enum pipe pipe;
3887
3888                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3889                               connector->base.base.id,
3890                               drm_get_connector_name(&connector->base));
3891
3892                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3893                      "wrong connector dpms state\n");
3894                 WARN(connector->base.encoder != &encoder->base,
3895                      "active connector not linked to encoder\n");
3896                 WARN(!encoder->connectors_active,
3897                      "encoder->connectors_active not set\n");
3898
3899                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3900                 WARN(!encoder_enabled, "encoder not enabled\n");
3901                 if (WARN_ON(!encoder->base.crtc))
3902                         return;
3903
3904                 crtc = encoder->base.crtc;
3905
3906                 WARN(!crtc->enabled, "crtc not enabled\n");
3907                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3908                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3909                      "encoder active on the wrong pipe\n");
3910         }
3911 }
3912
3913 /* Even simpler default implementation, if there's really no special case to
3914  * consider. */
3915 void intel_connector_dpms(struct drm_connector *connector, int mode)
3916 {
3917         struct intel_encoder *encoder = intel_attached_encoder(connector);
3918
3919         /* All the simple cases only support two dpms states. */
3920         if (mode != DRM_MODE_DPMS_ON)
3921                 mode = DRM_MODE_DPMS_OFF;
3922
3923         if (mode == connector->dpms)
3924                 return;
3925
3926         connector->dpms = mode;
3927
3928         /* Only need to change hw state when actually enabled */
3929         if (encoder->base.crtc)
3930                 intel_encoder_dpms(encoder, mode);
3931         else
3932                 WARN_ON(encoder->connectors_active != false);
3933
3934         intel_modeset_check_state(connector->dev);
3935 }
3936
3937 /* Simple connector->get_hw_state implementation for encoders that support only
3938  * one connector and no cloning and hence the encoder state determines the state
3939  * of the connector. */
3940 bool intel_connector_get_hw_state(struct intel_connector *connector)
3941 {
3942         enum pipe pipe = 0;
3943         struct intel_encoder *encoder = connector->encoder;
3944
3945         return encoder->get_hw_state(encoder, &pipe);
3946 }
3947
3948 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3949                                       struct intel_crtc_config *pipe_config)
3950 {
3951         struct drm_device *dev = crtc->dev;
3952         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3953
3954         if (HAS_PCH_SPLIT(dev)) {
3955                 /* FDI link clock is fixed at 2.7G */
3956                 if (pipe_config->requested_mode.clock * 3
3957                     > IRONLAKE_FDI_FREQ * 4)
3958                         return false;
3959         }
3960
3961         /* All interlaced capable intel hw wants timings in frames. Note though
3962          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3963          * timings, so we need to be careful not to clobber these.*/
3964         if (!pipe_config->timings_set)
3965                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3966
3967         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3968          * with a hsync front porch of 0.
3969          */
3970         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3971                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3972                 return false;
3973
3974         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3975                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3976         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3977                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3978                  * for lvds. */
3979                 pipe_config->pipe_bpp = 8*3;
3980         }
3981
3982         return true;
3983 }
3984
3985 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3986 {
3987         return 400000; /* FIXME */
3988 }
3989
3990 static int i945_get_display_clock_speed(struct drm_device *dev)
3991 {
3992         return 400000;
3993 }
3994
3995 static int i915_get_display_clock_speed(struct drm_device *dev)
3996 {
3997         return 333000;
3998 }
3999
4000 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4001 {
4002         return 200000;
4003 }
4004
4005 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4006 {
4007         u16 gcfgc = 0;
4008
4009         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4010
4011         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4012                 return 133000;
4013         else {
4014                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4015                 case GC_DISPLAY_CLOCK_333_MHZ:
4016                         return 333000;
4017                 default:
4018                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4019                         return 190000;
4020                 }
4021         }
4022 }
4023
4024 static int i865_get_display_clock_speed(struct drm_device *dev)
4025 {
4026         return 266000;
4027 }
4028
4029 static int i855_get_display_clock_speed(struct drm_device *dev)
4030 {
4031         u16 hpllcc = 0;
4032         /* Assume that the hardware is in the high speed state.  This
4033          * should be the default.
4034          */
4035         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4036         case GC_CLOCK_133_200:
4037         case GC_CLOCK_100_200:
4038                 return 200000;
4039         case GC_CLOCK_166_250:
4040                 return 250000;
4041         case GC_CLOCK_100_133:
4042                 return 133000;
4043         }
4044
4045         /* Shouldn't happen */
4046         return 0;
4047 }
4048
4049 static int i830_get_display_clock_speed(struct drm_device *dev)
4050 {
4051         return 133000;
4052 }
4053
4054 static void
4055 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4056 {
4057         while (*num > 0xffffff || *den > 0xffffff) {
4058                 *num >>= 1;
4059                 *den >>= 1;
4060         }
4061 }
4062
4063 void
4064 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4065                        int pixel_clock, int link_clock,
4066                        struct intel_link_m_n *m_n)
4067 {
4068         m_n->tu = 64;
4069         m_n->gmch_m = bits_per_pixel * pixel_clock;
4070         m_n->gmch_n = link_clock * nlanes * 8;
4071         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4072         m_n->link_m = pixel_clock;
4073         m_n->link_n = link_clock;
4074         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4075 }
4076
4077 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4078 {
4079         if (i915_panel_use_ssc >= 0)
4080                 return i915_panel_use_ssc != 0;
4081         return dev_priv->lvds_use_ssc
4082                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4083 }
4084
4085 static int vlv_get_refclk(struct drm_crtc *crtc)
4086 {
4087         struct drm_device *dev = crtc->dev;
4088         struct drm_i915_private *dev_priv = dev->dev_private;
4089         int refclk = 27000; /* for DP & HDMI */
4090
4091         return 100000; /* only one validated so far */
4092
4093         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4094                 refclk = 96000;
4095         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4096                 if (intel_panel_use_ssc(dev_priv))
4097                         refclk = 100000;
4098                 else
4099                         refclk = 96000;
4100         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4101                 refclk = 100000;
4102         }
4103
4104         return refclk;
4105 }
4106
4107 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4108 {
4109         struct drm_device *dev = crtc->dev;
4110         struct drm_i915_private *dev_priv = dev->dev_private;
4111         int refclk;
4112
4113         if (IS_VALLEYVIEW(dev)) {
4114                 refclk = vlv_get_refclk(crtc);
4115         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4116             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4117                 refclk = dev_priv->lvds_ssc_freq * 1000;
4118                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4119                               refclk / 1000);
4120         } else if (!IS_GEN2(dev)) {
4121                 refclk = 96000;
4122         } else {
4123                 refclk = 48000;
4124         }
4125
4126         return refclk;
4127 }
4128
4129 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4130                                       intel_clock_t *clock)
4131 {
4132         /* SDVO TV has fixed PLL values depend on its clock range,
4133            this mirrors vbios setting. */
4134         if (adjusted_mode->clock >= 100000
4135             && adjusted_mode->clock < 140500) {
4136                 clock->p1 = 2;
4137                 clock->p2 = 10;
4138                 clock->n = 3;
4139                 clock->m1 = 16;
4140                 clock->m2 = 8;
4141         } else if (adjusted_mode->clock >= 140500
4142                    && adjusted_mode->clock <= 200000) {
4143                 clock->p1 = 1;
4144                 clock->p2 = 10;
4145                 clock->n = 6;
4146                 clock->m1 = 12;
4147                 clock->m2 = 8;
4148         }
4149 }
4150
4151 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4152                                      intel_clock_t *clock,
4153                                      intel_clock_t *reduced_clock)
4154 {
4155         struct drm_device *dev = crtc->dev;
4156         struct drm_i915_private *dev_priv = dev->dev_private;
4157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4158         int pipe = intel_crtc->pipe;
4159         u32 fp, fp2 = 0;
4160
4161         if (IS_PINEVIEW(dev)) {
4162                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4163                 if (reduced_clock)
4164                         fp2 = (1 << reduced_clock->n) << 16 |
4165                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4166         } else {
4167                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4168                 if (reduced_clock)
4169                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4170                                 reduced_clock->m2;
4171         }
4172
4173         I915_WRITE(FP0(pipe), fp);
4174
4175         intel_crtc->lowfreq_avail = false;
4176         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4177             reduced_clock && i915_powersave) {
4178                 I915_WRITE(FP1(pipe), fp2);
4179                 intel_crtc->lowfreq_avail = true;
4180         } else {
4181                 I915_WRITE(FP1(pipe), fp);
4182         }
4183 }
4184
4185 static void vlv_update_pll(struct drm_crtc *crtc,
4186                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4187                            int num_connectors)
4188 {
4189         struct drm_device *dev = crtc->dev;
4190         struct drm_i915_private *dev_priv = dev->dev_private;
4191         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4192         struct drm_display_mode *adjusted_mode =
4193                 &intel_crtc->config.adjusted_mode;
4194         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4195         int pipe = intel_crtc->pipe;
4196         u32 dpll, mdiv, pdiv;
4197         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4198         bool is_sdvo;
4199         u32 temp;
4200
4201         mutex_lock(&dev_priv->dpio_lock);
4202
4203         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4204                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4205
4206         dpll = DPLL_VGA_MODE_DIS;
4207         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4208         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4209         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4210
4211         I915_WRITE(DPLL(pipe), dpll);
4212         POSTING_READ(DPLL(pipe));
4213
4214         bestn = clock->n;
4215         bestm1 = clock->m1;
4216         bestm2 = clock->m2;
4217         bestp1 = clock->p1;
4218         bestp2 = clock->p2;
4219
4220         /*
4221          * In Valleyview PLL and program lane counter registers are exposed
4222          * through DPIO interface
4223          */
4224         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4225         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4226         mdiv |= ((bestn << DPIO_N_SHIFT));
4227         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4228         mdiv |= (1 << DPIO_K_SHIFT);
4229         mdiv |= DPIO_ENABLE_CALIBRATION;
4230         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4231
4232         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4233
4234         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4235                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4236                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4237                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4238         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4239
4240         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4241
4242         dpll |= DPLL_VCO_ENABLE;
4243         I915_WRITE(DPLL(pipe), dpll);
4244         POSTING_READ(DPLL(pipe));
4245         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4246                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4247
4248         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4249
4250         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4251                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4252
4253         I915_WRITE(DPLL(pipe), dpll);
4254
4255         /* Wait for the clocks to stabilize. */
4256         POSTING_READ(DPLL(pipe));
4257         udelay(150);
4258
4259         temp = 0;
4260         if (is_sdvo) {
4261                 temp = 0;
4262                 if (intel_crtc->config.pixel_multiplier > 1) {
4263                         temp = (intel_crtc->config.pixel_multiplier - 1)
4264                                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4265                 }
4266         }
4267         I915_WRITE(DPLL_MD(pipe), temp);
4268         POSTING_READ(DPLL_MD(pipe));
4269
4270         /* Now program lane control registers */
4271         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4272                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4273         {
4274                 temp = 0x1000C4;
4275                 if(pipe == 1)
4276                         temp |= (1 << 21);
4277                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4278         }
4279         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4280         {
4281                 temp = 0x1000C4;
4282                 if(pipe == 1)
4283                         temp |= (1 << 21);
4284                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4285         }
4286
4287         mutex_unlock(&dev_priv->dpio_lock);
4288 }
4289
4290 static void i9xx_update_pll(struct drm_crtc *crtc,
4291                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4292                             int num_connectors)
4293 {
4294         struct drm_device *dev = crtc->dev;
4295         struct drm_i915_private *dev_priv = dev->dev_private;
4296         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4297         struct drm_display_mode *adjusted_mode =
4298                 &intel_crtc->config.adjusted_mode;
4299         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4300         struct intel_encoder *encoder;
4301         int pipe = intel_crtc->pipe;
4302         u32 dpll;
4303         bool is_sdvo;
4304
4305         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4306
4307         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4308                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4309
4310         dpll = DPLL_VGA_MODE_DIS;
4311
4312         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4313                 dpll |= DPLLB_MODE_LVDS;
4314         else
4315                 dpll |= DPLLB_MODE_DAC_SERIAL;
4316
4317         if (is_sdvo) {
4318                 if ((intel_crtc->config.pixel_multiplier > 1) &&
4319                     (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4320                         dpll |= (intel_crtc->config.pixel_multiplier - 1)
4321                                 << SDVO_MULTIPLIER_SHIFT_HIRES;
4322                 }
4323                 dpll |= DPLL_DVO_HIGH_SPEED;
4324         }
4325         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4326                 dpll |= DPLL_DVO_HIGH_SPEED;
4327
4328         /* compute bitmask from p1 value */
4329         if (IS_PINEVIEW(dev))
4330                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4331         else {
4332                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4333                 if (IS_G4X(dev) && reduced_clock)
4334                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4335         }
4336         switch (clock->p2) {
4337         case 5:
4338                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4339                 break;
4340         case 7:
4341                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4342                 break;
4343         case 10:
4344                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4345                 break;
4346         case 14:
4347                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4348                 break;
4349         }
4350         if (INTEL_INFO(dev)->gen >= 4)
4351                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4352
4353         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4354                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4355         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4356                 /* XXX: just matching BIOS for now */
4357                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4358                 dpll |= 3;
4359         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4360                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4361                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4362         else
4363                 dpll |= PLL_REF_INPUT_DREFCLK;
4364
4365         dpll |= DPLL_VCO_ENABLE;
4366         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4367         POSTING_READ(DPLL(pipe));
4368         udelay(150);
4369
4370         for_each_encoder_on_crtc(dev, crtc, encoder)
4371                 if (encoder->pre_pll_enable)
4372                         encoder->pre_pll_enable(encoder);
4373
4374         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4375                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4376
4377         I915_WRITE(DPLL(pipe), dpll);
4378
4379         /* Wait for the clocks to stabilize. */
4380         POSTING_READ(DPLL(pipe));
4381         udelay(150);
4382
4383         if (INTEL_INFO(dev)->gen >= 4) {
4384                 u32 temp = 0;
4385                 if (is_sdvo) {
4386                         temp = 0;
4387                         if (intel_crtc->config.pixel_multiplier > 1) {
4388                                 temp = (intel_crtc->config.pixel_multiplier - 1)
4389                                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4390                         }
4391                 }
4392                 I915_WRITE(DPLL_MD(pipe), temp);
4393         } else {
4394                 /* The pixel multiplier can only be updated once the
4395                  * DPLL is enabled and the clocks are stable.
4396                  *
4397                  * So write it again.
4398                  */
4399                 I915_WRITE(DPLL(pipe), dpll);
4400         }
4401 }
4402
4403 static void i8xx_update_pll(struct drm_crtc *crtc,
4404                             struct drm_display_mode *adjusted_mode,
4405                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4406                             int num_connectors)
4407 {
4408         struct drm_device *dev = crtc->dev;
4409         struct drm_i915_private *dev_priv = dev->dev_private;
4410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4411         struct intel_encoder *encoder;
4412         int pipe = intel_crtc->pipe;
4413         u32 dpll;
4414
4415         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4416
4417         dpll = DPLL_VGA_MODE_DIS;
4418
4419         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4420                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4421         } else {
4422                 if (clock->p1 == 2)
4423                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4424                 else
4425                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4426                 if (clock->p2 == 4)
4427                         dpll |= PLL_P2_DIVIDE_BY_4;
4428         }
4429
4430         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4431                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4432                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4433         else
4434                 dpll |= PLL_REF_INPUT_DREFCLK;
4435
4436         dpll |= DPLL_VCO_ENABLE;
4437         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4438         POSTING_READ(DPLL(pipe));
4439         udelay(150);
4440
4441         for_each_encoder_on_crtc(dev, crtc, encoder)
4442                 if (encoder->pre_pll_enable)
4443                         encoder->pre_pll_enable(encoder);
4444
4445         I915_WRITE(DPLL(pipe), dpll);
4446
4447         /* Wait for the clocks to stabilize. */
4448         POSTING_READ(DPLL(pipe));
4449         udelay(150);
4450
4451         /* The pixel multiplier can only be updated once the
4452          * DPLL is enabled and the clocks are stable.
4453          *
4454          * So write it again.
4455          */
4456         I915_WRITE(DPLL(pipe), dpll);
4457 }
4458
4459 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4460                                    struct drm_display_mode *mode,
4461                                    struct drm_display_mode *adjusted_mode)
4462 {
4463         struct drm_device *dev = intel_crtc->base.dev;
4464         struct drm_i915_private *dev_priv = dev->dev_private;
4465         enum pipe pipe = intel_crtc->pipe;
4466         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4467         uint32_t vsyncshift;
4468
4469         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4470                 /* the chip adds 2 halflines automatically */
4471                 adjusted_mode->crtc_vtotal -= 1;
4472                 adjusted_mode->crtc_vblank_end -= 1;
4473                 vsyncshift = adjusted_mode->crtc_hsync_start
4474                              - adjusted_mode->crtc_htotal / 2;
4475         } else {
4476                 vsyncshift = 0;
4477         }
4478
4479         if (INTEL_INFO(dev)->gen > 3)
4480                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4481
4482         I915_WRITE(HTOTAL(cpu_transcoder),
4483                    (adjusted_mode->crtc_hdisplay - 1) |
4484                    ((adjusted_mode->crtc_htotal - 1) << 16));
4485         I915_WRITE(HBLANK(cpu_transcoder),
4486                    (adjusted_mode->crtc_hblank_start - 1) |
4487                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4488         I915_WRITE(HSYNC(cpu_transcoder),
4489                    (adjusted_mode->crtc_hsync_start - 1) |
4490                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4491
4492         I915_WRITE(VTOTAL(cpu_transcoder),
4493                    (adjusted_mode->crtc_vdisplay - 1) |
4494                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4495         I915_WRITE(VBLANK(cpu_transcoder),
4496                    (adjusted_mode->crtc_vblank_start - 1) |
4497                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4498         I915_WRITE(VSYNC(cpu_transcoder),
4499                    (adjusted_mode->crtc_vsync_start - 1) |
4500                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4501
4502         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4503          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4504          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4505          * bits. */
4506         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4507             (pipe == PIPE_B || pipe == PIPE_C))
4508                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4509
4510         /* pipesrc controls the size that is scaled from, which should
4511          * always be the user's requested size.
4512          */
4513         I915_WRITE(PIPESRC(pipe),
4514                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4515 }
4516
4517 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4518                               int x, int y,
4519                               struct drm_framebuffer *fb)
4520 {
4521         struct drm_device *dev = crtc->dev;
4522         struct drm_i915_private *dev_priv = dev->dev_private;
4523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4524         struct drm_display_mode *adjusted_mode =
4525                 &intel_crtc->config.adjusted_mode;
4526         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4527         int pipe = intel_crtc->pipe;
4528         int plane = intel_crtc->plane;
4529         int refclk, num_connectors = 0;
4530         intel_clock_t clock, reduced_clock;
4531         u32 dspcntr, pipeconf;
4532         bool ok, has_reduced_clock = false, is_sdvo = false;
4533         bool is_lvds = false, is_tv = false, is_dp = false;
4534         struct intel_encoder *encoder;
4535         const intel_limit_t *limit;
4536         int ret;
4537
4538         for_each_encoder_on_crtc(dev, crtc, encoder) {
4539                 switch (encoder->type) {
4540                 case INTEL_OUTPUT_LVDS:
4541                         is_lvds = true;
4542                         break;
4543                 case INTEL_OUTPUT_SDVO:
4544                 case INTEL_OUTPUT_HDMI:
4545                         is_sdvo = true;
4546                         if (encoder->needs_tv_clock)
4547                                 is_tv = true;
4548                         break;
4549                 case INTEL_OUTPUT_TVOUT:
4550                         is_tv = true;
4551                         break;
4552                 case INTEL_OUTPUT_DISPLAYPORT:
4553                         is_dp = true;
4554                         break;
4555                 }
4556
4557                 num_connectors++;
4558         }
4559
4560         refclk = i9xx_get_refclk(crtc, num_connectors);
4561
4562         /*
4563          * Returns a set of divisors for the desired target clock with the given
4564          * refclk, or FALSE.  The returned values represent the clock equation:
4565          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4566          */
4567         limit = intel_limit(crtc, refclk);
4568         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4569                              &clock);
4570         if (!ok) {
4571                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4572                 return -EINVAL;
4573         }
4574
4575         /* Ensure that the cursor is valid for the new mode before changing... */
4576         intel_crtc_update_cursor(crtc, true);
4577
4578         if (is_lvds && dev_priv->lvds_downclock_avail) {
4579                 /*
4580                  * Ensure we match the reduced clock's P to the target clock.
4581                  * If the clocks don't match, we can't switch the display clock
4582                  * by using the FP0/FP1. In such case we will disable the LVDS
4583                  * downclock feature.
4584                 */
4585                 has_reduced_clock = limit->find_pll(limit, crtc,
4586                                                     dev_priv->lvds_downclock,
4587                                                     refclk,
4588                                                     &clock,
4589                                                     &reduced_clock);
4590         }
4591
4592         if (is_sdvo && is_tv)
4593                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4594
4595         if (IS_GEN2(dev))
4596                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4597                                 has_reduced_clock ? &reduced_clock : NULL,
4598                                 num_connectors);
4599         else if (IS_VALLEYVIEW(dev))
4600                 vlv_update_pll(crtc, &clock,
4601                                 has_reduced_clock ? &reduced_clock : NULL,
4602                                 num_connectors);
4603         else
4604                 i9xx_update_pll(crtc, &clock,
4605                                 has_reduced_clock ? &reduced_clock : NULL,
4606                                 num_connectors);
4607
4608         /* setup pipeconf */
4609         pipeconf = I915_READ(PIPECONF(pipe));
4610
4611         /* Set up the display plane register */
4612         dspcntr = DISPPLANE_GAMMA_ENABLE;
4613
4614         if (!IS_VALLEYVIEW(dev)) {
4615                 if (pipe == 0)
4616                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4617                 else
4618                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4619         }
4620
4621         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4622                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4623                  * core speed.
4624                  *
4625                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4626                  * pipe == 0 check?
4627                  */
4628                 if (mode->clock >
4629                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4630                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4631                 else
4632                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4633         }
4634
4635         /* default to 8bpc */
4636         pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4637         if (is_dp) {
4638                 if (intel_crtc->config.dither) {
4639                         pipeconf |= PIPECONF_6BPC |
4640                                     PIPECONF_DITHER_EN |
4641                                     PIPECONF_DITHER_TYPE_SP;
4642                 }
4643         }
4644
4645         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4646                 if (intel_crtc->config.dither) {
4647                         pipeconf |= PIPECONF_6BPC |
4648                                         PIPECONF_ENABLE |
4649                                         I965_PIPECONF_ACTIVE;
4650                 }
4651         }
4652
4653         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4654         drm_mode_debug_printmodeline(mode);
4655
4656         if (HAS_PIPE_CXSR(dev)) {
4657                 if (intel_crtc->lowfreq_avail) {
4658                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4659                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4660                 } else {
4661                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4662                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4663                 }
4664         }
4665
4666         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4667         if (!IS_GEN2(dev) &&
4668             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4669                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4670         else
4671                 pipeconf |= PIPECONF_PROGRESSIVE;
4672
4673         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4674
4675         /* pipesrc and dspsize control the size that is scaled from,
4676          * which should always be the user's requested size.
4677          */
4678         I915_WRITE(DSPSIZE(plane),
4679                    ((mode->vdisplay - 1) << 16) |
4680                    (mode->hdisplay - 1));
4681         I915_WRITE(DSPPOS(plane), 0);
4682
4683         I915_WRITE(PIPECONF(pipe), pipeconf);
4684         POSTING_READ(PIPECONF(pipe));
4685         intel_enable_pipe(dev_priv, pipe, false);
4686
4687         intel_wait_for_vblank(dev, pipe);
4688
4689         I915_WRITE(DSPCNTR(plane), dspcntr);
4690         POSTING_READ(DSPCNTR(plane));
4691
4692         ret = intel_pipe_set_base(crtc, x, y, fb);
4693
4694         intel_update_watermarks(dev);
4695
4696         return ret;
4697 }
4698
4699 static void ironlake_init_pch_refclk(struct drm_device *dev)
4700 {
4701         struct drm_i915_private *dev_priv = dev->dev_private;
4702         struct drm_mode_config *mode_config = &dev->mode_config;
4703         struct intel_encoder *encoder;
4704         u32 temp;
4705         bool has_lvds = false;
4706         bool has_cpu_edp = false;
4707         bool has_pch_edp = false;
4708         bool has_panel = false;
4709         bool has_ck505 = false;
4710         bool can_ssc = false;
4711
4712         /* We need to take the global config into account */
4713         list_for_each_entry(encoder, &mode_config->encoder_list,
4714                             base.head) {
4715                 switch (encoder->type) {
4716                 case INTEL_OUTPUT_LVDS:
4717                         has_panel = true;
4718                         has_lvds = true;
4719                         break;
4720                 case INTEL_OUTPUT_EDP:
4721                         has_panel = true;
4722                         if (intel_encoder_is_pch_edp(&encoder->base))
4723                                 has_pch_edp = true;
4724                         else
4725                                 has_cpu_edp = true;
4726                         break;
4727                 }
4728         }
4729
4730         if (HAS_PCH_IBX(dev)) {
4731                 has_ck505 = dev_priv->display_clock_mode;
4732                 can_ssc = has_ck505;
4733         } else {
4734                 has_ck505 = false;
4735                 can_ssc = true;
4736         }
4737
4738         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4739                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4740                       has_ck505);
4741
4742         /* Ironlake: try to setup display ref clock before DPLL
4743          * enabling. This is only under driver's control after
4744          * PCH B stepping, previous chipset stepping should be
4745          * ignoring this setting.
4746          */
4747         temp = I915_READ(PCH_DREF_CONTROL);
4748         /* Always enable nonspread source */
4749         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4750
4751         if (has_ck505)
4752                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4753         else
4754                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4755
4756         if (has_panel) {
4757                 temp &= ~DREF_SSC_SOURCE_MASK;
4758                 temp |= DREF_SSC_SOURCE_ENABLE;
4759
4760                 /* SSC must be turned on before enabling the CPU output  */
4761                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4762                         DRM_DEBUG_KMS("Using SSC on panel\n");
4763                         temp |= DREF_SSC1_ENABLE;
4764                 } else
4765                         temp &= ~DREF_SSC1_ENABLE;
4766
4767                 /* Get SSC going before enabling the outputs */
4768                 I915_WRITE(PCH_DREF_CONTROL, temp);
4769                 POSTING_READ(PCH_DREF_CONTROL);
4770                 udelay(200);
4771
4772                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4773
4774                 /* Enable CPU source on CPU attached eDP */
4775                 if (has_cpu_edp) {
4776                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4777                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4778                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4779                         }
4780                         else
4781                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4782                 } else
4783                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4784
4785                 I915_WRITE(PCH_DREF_CONTROL, temp);
4786                 POSTING_READ(PCH_DREF_CONTROL);
4787                 udelay(200);
4788         } else {
4789                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4790
4791                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4792
4793                 /* Turn off CPU output */
4794                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4795
4796                 I915_WRITE(PCH_DREF_CONTROL, temp);
4797                 POSTING_READ(PCH_DREF_CONTROL);
4798                 udelay(200);
4799
4800                 /* Turn off the SSC source */
4801                 temp &= ~DREF_SSC_SOURCE_MASK;
4802                 temp |= DREF_SSC_SOURCE_DISABLE;
4803
4804                 /* Turn off SSC1 */
4805                 temp &= ~ DREF_SSC1_ENABLE;
4806
4807                 I915_WRITE(PCH_DREF_CONTROL, temp);
4808                 POSTING_READ(PCH_DREF_CONTROL);
4809                 udelay(200);
4810         }
4811 }
4812
4813 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4814 static void lpt_init_pch_refclk(struct drm_device *dev)
4815 {
4816         struct drm_i915_private *dev_priv = dev->dev_private;
4817         struct drm_mode_config *mode_config = &dev->mode_config;
4818         struct intel_encoder *encoder;
4819         bool has_vga = false;
4820         bool is_sdv = false;
4821         u32 tmp;
4822
4823         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4824                 switch (encoder->type) {
4825                 case INTEL_OUTPUT_ANALOG:
4826                         has_vga = true;
4827                         break;
4828                 }
4829         }
4830
4831         if (!has_vga)
4832                 return;
4833
4834         mutex_lock(&dev_priv->dpio_lock);
4835
4836         /* XXX: Rip out SDV support once Haswell ships for real. */
4837         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4838                 is_sdv = true;
4839
4840         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4841         tmp &= ~SBI_SSCCTL_DISABLE;
4842         tmp |= SBI_SSCCTL_PATHALT;
4843         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4844
4845         udelay(24);
4846
4847         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4848         tmp &= ~SBI_SSCCTL_PATHALT;
4849         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4850
4851         if (!is_sdv) {
4852                 tmp = I915_READ(SOUTH_CHICKEN2);
4853                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4854                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4855
4856                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4857                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4858                         DRM_ERROR("FDI mPHY reset assert timeout\n");
4859
4860                 tmp = I915_READ(SOUTH_CHICKEN2);
4861                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4862                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4863
4864                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4865                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4866                                        100))
4867                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4868         }
4869
4870         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4871         tmp &= ~(0xFF << 24);
4872         tmp |= (0x12 << 24);
4873         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4874
4875         if (!is_sdv) {
4876                 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4877                 tmp &= ~(0x3 << 6);
4878                 tmp |= (1 << 6) | (1 << 0);
4879                 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4880         }
4881
4882         if (is_sdv) {
4883                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4884                 tmp |= 0x7FFF;
4885                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4886         }
4887
4888         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4889         tmp |= (1 << 11);
4890         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4891
4892         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4893         tmp |= (1 << 11);
4894         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4895
4896         if (is_sdv) {
4897                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4898                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4899                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4900
4901                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4902                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4903                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4904
4905                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4906                 tmp |= (0x3F << 8);
4907                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4908
4909                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4910                 tmp |= (0x3F << 8);
4911                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4912         }
4913
4914         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4915         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4916         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4917
4918         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4919         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4920         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4921
4922         if (!is_sdv) {
4923                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4924                 tmp &= ~(7 << 13);
4925                 tmp |= (5 << 13);
4926                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4927
4928                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4929                 tmp &= ~(7 << 13);
4930                 tmp |= (5 << 13);
4931                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4932         }
4933
4934         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4935         tmp &= ~0xFF;
4936         tmp |= 0x1C;
4937         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4938
4939         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4940         tmp &= ~0xFF;
4941         tmp |= 0x1C;
4942         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
4943
4944         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
4945         tmp &= ~(0xFF << 16);
4946         tmp |= (0x1C << 16);
4947         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
4948
4949         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
4950         tmp &= ~(0xFF << 16);
4951         tmp |= (0x1C << 16);
4952         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
4953
4954         if (!is_sdv) {
4955                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
4956                 tmp |= (1 << 27);
4957                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
4958
4959                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
4960                 tmp |= (1 << 27);
4961                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
4962
4963                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
4964                 tmp &= ~(0xF << 28);
4965                 tmp |= (4 << 28);
4966                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
4967
4968                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
4969                 tmp &= ~(0xF << 28);
4970                 tmp |= (4 << 28);
4971                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
4972         }
4973
4974         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
4975         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
4976         tmp |= SBI_DBUFF0_ENABLE;
4977         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
4978
4979         mutex_unlock(&dev_priv->dpio_lock);
4980 }
4981
4982 /*
4983  * Initialize reference clocks when the driver loads
4984  */
4985 void intel_init_pch_refclk(struct drm_device *dev)
4986 {
4987         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4988                 ironlake_init_pch_refclk(dev);
4989         else if (HAS_PCH_LPT(dev))
4990                 lpt_init_pch_refclk(dev);
4991 }
4992
4993 static int ironlake_get_refclk(struct drm_crtc *crtc)
4994 {
4995         struct drm_device *dev = crtc->dev;
4996         struct drm_i915_private *dev_priv = dev->dev_private;
4997         struct intel_encoder *encoder;
4998         struct intel_encoder *edp_encoder = NULL;
4999         int num_connectors = 0;
5000         bool is_lvds = false;
5001
5002         for_each_encoder_on_crtc(dev, crtc, encoder) {
5003                 switch (encoder->type) {
5004                 case INTEL_OUTPUT_LVDS:
5005                         is_lvds = true;
5006                         break;
5007                 case INTEL_OUTPUT_EDP:
5008                         edp_encoder = encoder;
5009                         break;
5010                 }
5011                 num_connectors++;
5012         }
5013
5014         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5015                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5016                               dev_priv->lvds_ssc_freq);
5017                 return dev_priv->lvds_ssc_freq * 1000;
5018         }
5019
5020         return 120000;
5021 }
5022
5023 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5024                                   struct drm_display_mode *adjusted_mode,
5025                                   bool dither)
5026 {
5027         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5029         int pipe = intel_crtc->pipe;
5030         uint32_t val;
5031
5032         val = I915_READ(PIPECONF(pipe));
5033
5034         val &= ~PIPECONF_BPC_MASK;
5035         switch (intel_crtc->config.pipe_bpp) {
5036         case 18:
5037                 val |= PIPECONF_6BPC;
5038                 break;
5039         case 24:
5040                 val |= PIPECONF_8BPC;
5041                 break;
5042         case 30:
5043                 val |= PIPECONF_10BPC;
5044                 break;
5045         case 36:
5046                 val |= PIPECONF_12BPC;
5047                 break;
5048         default:
5049                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5050                 BUG();
5051         }
5052
5053         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5054         if (dither)
5055                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5056
5057         val &= ~PIPECONF_INTERLACE_MASK;
5058         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5059                 val |= PIPECONF_INTERLACED_ILK;
5060         else
5061                 val |= PIPECONF_PROGRESSIVE;
5062
5063         if (intel_crtc->config.limited_color_range)
5064                 val |= PIPECONF_COLOR_RANGE_SELECT;
5065         else
5066                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5067
5068         I915_WRITE(PIPECONF(pipe), val);
5069         POSTING_READ(PIPECONF(pipe));
5070 }
5071
5072 /*
5073  * Set up the pipe CSC unit.
5074  *
5075  * Currently only full range RGB to limited range RGB conversion
5076  * is supported, but eventually this should handle various
5077  * RGB<->YCbCr scenarios as well.
5078  */
5079 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5080 {
5081         struct drm_device *dev = crtc->dev;
5082         struct drm_i915_private *dev_priv = dev->dev_private;
5083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5084         int pipe = intel_crtc->pipe;
5085         uint16_t coeff = 0x7800; /* 1.0 */
5086
5087         /*
5088          * TODO: Check what kind of values actually come out of the pipe
5089          * with these coeff/postoff values and adjust to get the best
5090          * accuracy. Perhaps we even need to take the bpc value into
5091          * consideration.
5092          */
5093
5094         if (intel_crtc->config.limited_color_range)
5095                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5096
5097         /*
5098          * GY/GU and RY/RU should be the other way around according
5099          * to BSpec, but reality doesn't agree. Just set them up in
5100          * a way that results in the correct picture.
5101          */
5102         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5103         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5104
5105         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5106         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5107
5108         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5109         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5110
5111         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5112         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5113         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5114
5115         if (INTEL_INFO(dev)->gen > 6) {
5116                 uint16_t postoff = 0;
5117
5118                 if (intel_crtc->config.limited_color_range)
5119                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5120
5121                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5122                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5123                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5124
5125                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5126         } else {
5127                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5128
5129                 if (intel_crtc->config.limited_color_range)
5130                         mode |= CSC_BLACK_SCREEN_OFFSET;
5131
5132                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5133         }
5134 }
5135
5136 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5137                                  struct drm_display_mode *adjusted_mode,
5138                                  bool dither)
5139 {
5140         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5141         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5142         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5143         uint32_t val;
5144
5145         val = I915_READ(PIPECONF(cpu_transcoder));
5146
5147         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5148         if (dither)
5149                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5150
5151         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5152         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5153                 val |= PIPECONF_INTERLACED_ILK;
5154         else
5155                 val |= PIPECONF_PROGRESSIVE;
5156
5157         I915_WRITE(PIPECONF(cpu_transcoder), val);
5158         POSTING_READ(PIPECONF(cpu_transcoder));
5159 }
5160
5161 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5162                                     struct drm_display_mode *adjusted_mode,
5163                                     intel_clock_t *clock,
5164                                     bool *has_reduced_clock,
5165                                     intel_clock_t *reduced_clock)
5166 {
5167         struct drm_device *dev = crtc->dev;
5168         struct drm_i915_private *dev_priv = dev->dev_private;
5169         struct intel_encoder *intel_encoder;
5170         int refclk;
5171         const intel_limit_t *limit;
5172         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5173
5174         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5175                 switch (intel_encoder->type) {
5176                 case INTEL_OUTPUT_LVDS:
5177                         is_lvds = true;
5178                         break;
5179                 case INTEL_OUTPUT_SDVO:
5180                 case INTEL_OUTPUT_HDMI:
5181                         is_sdvo = true;
5182                         if (intel_encoder->needs_tv_clock)
5183                                 is_tv = true;
5184                         break;
5185                 case INTEL_OUTPUT_TVOUT:
5186                         is_tv = true;
5187                         break;
5188                 }
5189         }
5190
5191         refclk = ironlake_get_refclk(crtc);
5192
5193         /*
5194          * Returns a set of divisors for the desired target clock with the given
5195          * refclk, or FALSE.  The returned values represent the clock equation:
5196          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5197          */
5198         limit = intel_limit(crtc, refclk);
5199         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5200                               clock);
5201         if (!ret)
5202                 return false;
5203
5204         if (is_lvds && dev_priv->lvds_downclock_avail) {
5205                 /*
5206                  * Ensure we match the reduced clock's P to the target clock.
5207                  * If the clocks don't match, we can't switch the display clock
5208                  * by using the FP0/FP1. In such case we will disable the LVDS
5209                  * downclock feature.
5210                 */
5211                 *has_reduced_clock = limit->find_pll(limit, crtc,
5212                                                      dev_priv->lvds_downclock,
5213                                                      refclk,
5214                                                      clock,
5215                                                      reduced_clock);
5216         }
5217
5218         if (is_sdvo && is_tv)
5219                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5220
5221         return true;
5222 }
5223
5224 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5225 {
5226         struct drm_i915_private *dev_priv = dev->dev_private;
5227         uint32_t temp;
5228
5229         temp = I915_READ(SOUTH_CHICKEN1);
5230         if (temp & FDI_BC_BIFURCATION_SELECT)
5231                 return;
5232
5233         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5234         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5235
5236         temp |= FDI_BC_BIFURCATION_SELECT;
5237         DRM_DEBUG_KMS("enabling fdi C rx\n");
5238         I915_WRITE(SOUTH_CHICKEN1, temp);
5239         POSTING_READ(SOUTH_CHICKEN1);
5240 }
5241
5242 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5243 {
5244         struct drm_device *dev = intel_crtc->base.dev;
5245         struct drm_i915_private *dev_priv = dev->dev_private;
5246         struct intel_crtc *pipe_B_crtc =
5247                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5248
5249         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5250                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5251         if (intel_crtc->fdi_lanes > 4) {
5252                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5253                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5254                 /* Clamp lanes to avoid programming the hw with bogus values. */
5255                 intel_crtc->fdi_lanes = 4;
5256
5257                 return false;
5258         }
5259
5260         if (INTEL_INFO(dev)->num_pipes == 2)
5261                 return true;
5262
5263         switch (intel_crtc->pipe) {
5264         case PIPE_A:
5265                 return true;
5266         case PIPE_B:
5267                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5268                     intel_crtc->fdi_lanes > 2) {
5269                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5270                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5271                         /* Clamp lanes to avoid programming the hw with bogus values. */
5272                         intel_crtc->fdi_lanes = 2;
5273
5274                         return false;
5275                 }
5276
5277                 if (intel_crtc->fdi_lanes > 2)
5278                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5279                 else
5280                         cpt_enable_fdi_bc_bifurcation(dev);
5281
5282                 return true;
5283         case PIPE_C:
5284                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5285                         if (intel_crtc->fdi_lanes > 2) {
5286                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5287                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5288                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5289                                 intel_crtc->fdi_lanes = 2;
5290
5291                                 return false;
5292                         }
5293                 } else {
5294                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5295                         return false;
5296                 }
5297
5298                 cpt_enable_fdi_bc_bifurcation(dev);
5299
5300                 return true;
5301         default:
5302                 BUG();
5303         }
5304 }
5305
5306 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5307 {
5308         /*
5309          * Account for spread spectrum to avoid
5310          * oversubscribing the link. Max center spread
5311          * is 2.5%; use 5% for safety's sake.
5312          */
5313         u32 bps = target_clock * bpp * 21 / 20;
5314         return bps / (link_bw * 8) + 1;
5315 }
5316
5317 static void ironlake_set_m_n(struct drm_crtc *crtc)
5318 {
5319         struct drm_device *dev = crtc->dev;
5320         struct drm_i915_private *dev_priv = dev->dev_private;
5321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5322         struct drm_display_mode *adjusted_mode =
5323                 &intel_crtc->config.adjusted_mode;
5324         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5325         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5326         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5327         struct intel_link_m_n m_n = {0};
5328         int target_clock, lane, link_bw;
5329         bool is_dp = false, is_cpu_edp = false;
5330
5331         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5332                 switch (intel_encoder->type) {
5333                 case INTEL_OUTPUT_DISPLAYPORT:
5334                         is_dp = true;
5335                         break;
5336                 case INTEL_OUTPUT_EDP:
5337                         is_dp = true;
5338                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5339                                 is_cpu_edp = true;
5340                         edp_encoder = intel_encoder;
5341                         break;
5342                 }
5343         }
5344
5345         /* FDI link */
5346         lane = 0;
5347         /* CPU eDP doesn't require FDI link, so just set DP M/N
5348            according to current link config */
5349         if (is_cpu_edp) {
5350                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5351         } else {
5352                 /* FDI is a binary signal running at ~2.7GHz, encoding
5353                  * each output octet as 10 bits. The actual frequency
5354                  * is stored as a divider into a 100MHz clock, and the
5355                  * mode pixel clock is stored in units of 1KHz.
5356                  * Hence the bw of each lane in terms of the mode signal
5357                  * is:
5358                  */
5359                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5360         }
5361
5362         /* [e]DP over FDI requires target mode clock instead of link clock. */
5363         if (edp_encoder)
5364                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5365         else if (is_dp)
5366                 target_clock = mode->clock;
5367         else
5368                 target_clock = adjusted_mode->clock;
5369
5370         if (!lane)
5371                 lane = ironlake_get_lanes_required(target_clock, link_bw,
5372                                                    intel_crtc->config.pipe_bpp);
5373
5374         intel_crtc->fdi_lanes = lane;
5375
5376         if (intel_crtc->config.pixel_multiplier > 1)
5377                 link_bw *= intel_crtc->config.pixel_multiplier;
5378         intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5379                                link_bw, &m_n);
5380
5381         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5382         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5383         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5384         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5385 }
5386
5387 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5388                                       intel_clock_t *clock, u32 fp)
5389 {
5390         struct drm_crtc *crtc = &intel_crtc->base;
5391         struct drm_device *dev = crtc->dev;
5392         struct drm_i915_private *dev_priv = dev->dev_private;
5393         struct intel_encoder *intel_encoder;
5394         uint32_t dpll;
5395         int factor, num_connectors = 0;
5396         bool is_lvds = false, is_sdvo = false, is_tv = false;
5397         bool is_dp = false, is_cpu_edp = false;
5398
5399         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5400                 switch (intel_encoder->type) {
5401                 case INTEL_OUTPUT_LVDS:
5402                         is_lvds = true;
5403                         break;
5404                 case INTEL_OUTPUT_SDVO:
5405                 case INTEL_OUTPUT_HDMI:
5406                         is_sdvo = true;
5407                         if (intel_encoder->needs_tv_clock)
5408                                 is_tv = true;
5409                         break;
5410                 case INTEL_OUTPUT_TVOUT:
5411                         is_tv = true;
5412                         break;
5413                 case INTEL_OUTPUT_DISPLAYPORT:
5414                         is_dp = true;
5415                         break;
5416                 case INTEL_OUTPUT_EDP:
5417                         is_dp = true;
5418                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5419                                 is_cpu_edp = true;
5420                         break;
5421                 }
5422
5423                 num_connectors++;
5424         }
5425
5426         /* Enable autotuning of the PLL clock (if permissible) */
5427         factor = 21;
5428         if (is_lvds) {
5429                 if ((intel_panel_use_ssc(dev_priv) &&
5430                      dev_priv->lvds_ssc_freq == 100) ||
5431                     intel_is_dual_link_lvds(dev))
5432                         factor = 25;
5433         } else if (is_sdvo && is_tv)
5434                 factor = 20;
5435
5436         if (clock->m < factor * clock->n)
5437                 fp |= FP_CB_TUNE;
5438
5439         dpll = 0;
5440
5441         if (is_lvds)
5442                 dpll |= DPLLB_MODE_LVDS;
5443         else
5444                 dpll |= DPLLB_MODE_DAC_SERIAL;
5445         if (is_sdvo) {
5446                 if (intel_crtc->config.pixel_multiplier > 1) {
5447                         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5448                                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5449                 }
5450                 dpll |= DPLL_DVO_HIGH_SPEED;
5451         }
5452         if (is_dp && !is_cpu_edp)
5453                 dpll |= DPLL_DVO_HIGH_SPEED;
5454
5455         /* compute bitmask from p1 value */
5456         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5457         /* also FPA1 */
5458         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5459
5460         switch (clock->p2) {
5461         case 5:
5462                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5463                 break;
5464         case 7:
5465                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5466                 break;
5467         case 10:
5468                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5469                 break;
5470         case 14:
5471                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5472                 break;
5473         }
5474
5475         if (is_sdvo && is_tv)
5476                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5477         else if (is_tv)
5478                 /* XXX: just matching BIOS for now */
5479                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5480                 dpll |= 3;
5481         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5482                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5483         else
5484                 dpll |= PLL_REF_INPUT_DREFCLK;
5485
5486         return dpll;
5487 }
5488
5489 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5490                                   int x, int y,
5491                                   struct drm_framebuffer *fb)
5492 {
5493         struct drm_device *dev = crtc->dev;
5494         struct drm_i915_private *dev_priv = dev->dev_private;
5495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5496         struct drm_display_mode *adjusted_mode =
5497                 &intel_crtc->config.adjusted_mode;
5498         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5499         int pipe = intel_crtc->pipe;
5500         int plane = intel_crtc->plane;
5501         int num_connectors = 0;
5502         intel_clock_t clock, reduced_clock;
5503         u32 dpll, fp = 0, fp2 = 0;
5504         bool ok, has_reduced_clock = false;
5505         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5506         struct intel_encoder *encoder;
5507         int ret;
5508         bool dither, fdi_config_ok;
5509
5510         for_each_encoder_on_crtc(dev, crtc, encoder) {
5511                 switch (encoder->type) {
5512                 case INTEL_OUTPUT_LVDS:
5513                         is_lvds = true;
5514                         break;
5515                 case INTEL_OUTPUT_DISPLAYPORT:
5516                         is_dp = true;
5517                         break;
5518                 case INTEL_OUTPUT_EDP:
5519                         is_dp = true;
5520                         if (!intel_encoder_is_pch_edp(&encoder->base))
5521                                 is_cpu_edp = true;
5522                         break;
5523                 }
5524
5525                 num_connectors++;
5526         }
5527
5528         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5529              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5530
5531         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5532                                      &has_reduced_clock, &reduced_clock);
5533         if (!ok) {
5534                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5535                 return -EINVAL;
5536         }
5537
5538         /* Ensure that the cursor is valid for the new mode before changing... */
5539         intel_crtc_update_cursor(crtc, true);
5540
5541         /* determine panel color depth */
5542         dither = intel_crtc->config.dither;
5543         if (is_lvds && dev_priv->lvds_dither)
5544                 dither = true;
5545
5546         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5547         if (has_reduced_clock)
5548                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5549                         reduced_clock.m2;
5550
5551         dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
5552
5553         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5554         drm_mode_debug_printmodeline(mode);
5555
5556         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5557         if (!is_cpu_edp) {
5558                 struct intel_pch_pll *pll;
5559
5560                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5561                 if (pll == NULL) {
5562                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5563                                          pipe);
5564                         return -EINVAL;
5565                 }
5566         } else
5567                 intel_put_pch_pll(intel_crtc);
5568
5569         if (is_dp && !is_cpu_edp)
5570                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5571
5572         for_each_encoder_on_crtc(dev, crtc, encoder)
5573                 if (encoder->pre_pll_enable)
5574                         encoder->pre_pll_enable(encoder);
5575
5576         if (intel_crtc->pch_pll) {
5577                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5578
5579                 /* Wait for the clocks to stabilize. */
5580                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5581                 udelay(150);
5582
5583                 /* The pixel multiplier can only be updated once the
5584                  * DPLL is enabled and the clocks are stable.
5585                  *
5586                  * So write it again.
5587                  */
5588                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5589         }
5590
5591         intel_crtc->lowfreq_avail = false;
5592         if (intel_crtc->pch_pll) {
5593                 if (is_lvds && has_reduced_clock && i915_powersave) {
5594                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5595                         intel_crtc->lowfreq_avail = true;
5596                 } else {
5597                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5598                 }
5599         }
5600
5601         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5602
5603         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5604          * ironlake_check_fdi_lanes. */
5605         ironlake_set_m_n(crtc);
5606
5607         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5608
5609         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5610
5611         intel_wait_for_vblank(dev, pipe);
5612
5613         /* Set up the display plane register */
5614         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5615         POSTING_READ(DSPCNTR(plane));
5616
5617         ret = intel_pipe_set_base(crtc, x, y, fb);
5618
5619         intel_update_watermarks(dev);
5620
5621         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5622
5623         return fdi_config_ok ? ret : -EINVAL;
5624 }
5625
5626 static void haswell_modeset_global_resources(struct drm_device *dev)
5627 {
5628         struct drm_i915_private *dev_priv = dev->dev_private;
5629         bool enable = false;
5630         struct intel_crtc *crtc;
5631         struct intel_encoder *encoder;
5632
5633         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5634                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5635                         enable = true;
5636                 /* XXX: Should check for edp transcoder here, but thanks to init
5637                  * sequence that's not yet available. Just in case desktop eDP
5638                  * on PORT D is possible on haswell, too. */
5639         }
5640
5641         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5642                             base.head) {
5643                 if (encoder->type != INTEL_OUTPUT_EDP &&
5644                     encoder->connectors_active)
5645                         enable = true;
5646         }
5647
5648         /* Even the eDP panel fitter is outside the always-on well. */
5649         if (dev_priv->pch_pf_size)
5650                 enable = true;
5651
5652         intel_set_power_well(dev, enable);
5653 }
5654
5655 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5656                                  int x, int y,
5657                                  struct drm_framebuffer *fb)
5658 {
5659         struct drm_device *dev = crtc->dev;
5660         struct drm_i915_private *dev_priv = dev->dev_private;
5661         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5662         struct drm_display_mode *adjusted_mode =
5663                 &intel_crtc->config.adjusted_mode;
5664         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5665         int pipe = intel_crtc->pipe;
5666         int plane = intel_crtc->plane;
5667         int num_connectors = 0;
5668         bool is_dp = false, is_cpu_edp = false;
5669         struct intel_encoder *encoder;
5670         int ret;
5671         bool dither;
5672
5673         for_each_encoder_on_crtc(dev, crtc, encoder) {
5674                 switch (encoder->type) {
5675                 case INTEL_OUTPUT_DISPLAYPORT:
5676                         is_dp = true;
5677                         break;
5678                 case INTEL_OUTPUT_EDP:
5679                         is_dp = true;
5680                         if (!intel_encoder_is_pch_edp(&encoder->base))
5681                                 is_cpu_edp = true;
5682                         break;
5683                 }
5684
5685                 num_connectors++;
5686         }
5687
5688         /* We are not sure yet this won't happen. */
5689         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5690              INTEL_PCH_TYPE(dev));
5691
5692         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5693              num_connectors, pipe_name(pipe));
5694
5695         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5696                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5697
5698         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5699
5700         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5701                 return -EINVAL;
5702
5703         /* Ensure that the cursor is valid for the new mode before changing... */
5704         intel_crtc_update_cursor(crtc, true);
5705
5706         /* determine panel color depth */
5707         dither = intel_crtc->config.dither;
5708
5709         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5710         drm_mode_debug_printmodeline(mode);
5711
5712         if (is_dp && !is_cpu_edp)
5713                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5714
5715         intel_crtc->lowfreq_avail = false;
5716
5717         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5718
5719         if (!is_dp || is_cpu_edp)
5720                 ironlake_set_m_n(crtc);
5721
5722         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5723
5724         intel_set_pipe_csc(crtc);
5725
5726         /* Set up the display plane register */
5727         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5728         POSTING_READ(DSPCNTR(plane));
5729
5730         ret = intel_pipe_set_base(crtc, x, y, fb);
5731
5732         intel_update_watermarks(dev);
5733
5734         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5735
5736         return ret;
5737 }
5738
5739 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5740                                int x, int y,
5741                                struct drm_framebuffer *fb)
5742 {
5743         struct drm_device *dev = crtc->dev;
5744         struct drm_i915_private *dev_priv = dev->dev_private;
5745         struct drm_encoder_helper_funcs *encoder_funcs;
5746         struct intel_encoder *encoder;
5747         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5748         struct drm_display_mode *adjusted_mode =
5749                 &intel_crtc->config.adjusted_mode;
5750         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5751         int pipe = intel_crtc->pipe;
5752         int ret;
5753
5754         if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5755                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5756         else
5757                 intel_crtc->cpu_transcoder = pipe;
5758
5759         drm_vblank_pre_modeset(dev, pipe);
5760
5761         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5762
5763         drm_vblank_post_modeset(dev, pipe);
5764
5765         if (ret != 0)
5766                 return ret;
5767
5768         for_each_encoder_on_crtc(dev, crtc, encoder) {
5769                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5770                         encoder->base.base.id,
5771                         drm_get_encoder_name(&encoder->base),
5772                         mode->base.id, mode->name);
5773                 if (encoder->mode_set) {
5774                         encoder->mode_set(encoder);
5775                 } else {
5776                         encoder_funcs = encoder->base.helper_private;
5777                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5778                 }
5779         }
5780
5781         return 0;
5782 }
5783
5784 static bool intel_eld_uptodate(struct drm_connector *connector,
5785                                int reg_eldv, uint32_t bits_eldv,
5786                                int reg_elda, uint32_t bits_elda,
5787                                int reg_edid)
5788 {
5789         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5790         uint8_t *eld = connector->eld;
5791         uint32_t i;
5792
5793         i = I915_READ(reg_eldv);
5794         i &= bits_eldv;
5795
5796         if (!eld[0])
5797                 return !i;
5798
5799         if (!i)
5800                 return false;
5801
5802         i = I915_READ(reg_elda);
5803         i &= ~bits_elda;
5804         I915_WRITE(reg_elda, i);
5805
5806         for (i = 0; i < eld[2]; i++)
5807                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5808                         return false;
5809
5810         return true;
5811 }
5812
5813 static void g4x_write_eld(struct drm_connector *connector,
5814                           struct drm_crtc *crtc)
5815 {
5816         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5817         uint8_t *eld = connector->eld;
5818         uint32_t eldv;
5819         uint32_t len;
5820         uint32_t i;
5821
5822         i = I915_READ(G4X_AUD_VID_DID);
5823
5824         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5825                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5826         else
5827                 eldv = G4X_ELDV_DEVCTG;
5828
5829         if (intel_eld_uptodate(connector,
5830                                G4X_AUD_CNTL_ST, eldv,
5831                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5832                                G4X_HDMIW_HDMIEDID))
5833                 return;
5834
5835         i = I915_READ(G4X_AUD_CNTL_ST);
5836         i &= ~(eldv | G4X_ELD_ADDR);
5837         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5838         I915_WRITE(G4X_AUD_CNTL_ST, i);
5839
5840         if (!eld[0])
5841                 return;
5842
5843         len = min_t(uint8_t, eld[2], len);
5844         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5845         for (i = 0; i < len; i++)
5846                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5847
5848         i = I915_READ(G4X_AUD_CNTL_ST);
5849         i |= eldv;
5850         I915_WRITE(G4X_AUD_CNTL_ST, i);
5851 }
5852
5853 static void haswell_write_eld(struct drm_connector *connector,
5854                                      struct drm_crtc *crtc)
5855 {
5856         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5857         uint8_t *eld = connector->eld;
5858         struct drm_device *dev = crtc->dev;
5859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5860         uint32_t eldv;
5861         uint32_t i;
5862         int len;
5863         int pipe = to_intel_crtc(crtc)->pipe;
5864         int tmp;
5865
5866         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5867         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5868         int aud_config = HSW_AUD_CFG(pipe);
5869         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5870
5871
5872         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5873
5874         /* Audio output enable */
5875         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5876         tmp = I915_READ(aud_cntrl_st2);
5877         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5878         I915_WRITE(aud_cntrl_st2, tmp);
5879
5880         /* Wait for 1 vertical blank */
5881         intel_wait_for_vblank(dev, pipe);
5882
5883         /* Set ELD valid state */
5884         tmp = I915_READ(aud_cntrl_st2);
5885         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5886         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5887         I915_WRITE(aud_cntrl_st2, tmp);
5888         tmp = I915_READ(aud_cntrl_st2);
5889         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5890
5891         /* Enable HDMI mode */
5892         tmp = I915_READ(aud_config);
5893         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5894         /* clear N_programing_enable and N_value_index */
5895         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5896         I915_WRITE(aud_config, tmp);
5897
5898         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5899
5900         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5901         intel_crtc->eld_vld = true;
5902
5903         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5904                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5905                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5906                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5907         } else
5908                 I915_WRITE(aud_config, 0);
5909
5910         if (intel_eld_uptodate(connector,
5911                                aud_cntrl_st2, eldv,
5912                                aud_cntl_st, IBX_ELD_ADDRESS,
5913                                hdmiw_hdmiedid))
5914                 return;
5915
5916         i = I915_READ(aud_cntrl_st2);
5917         i &= ~eldv;
5918         I915_WRITE(aud_cntrl_st2, i);
5919
5920         if (!eld[0])
5921                 return;
5922
5923         i = I915_READ(aud_cntl_st);
5924         i &= ~IBX_ELD_ADDRESS;
5925         I915_WRITE(aud_cntl_st, i);
5926         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5927         DRM_DEBUG_DRIVER("port num:%d\n", i);
5928
5929         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5930         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5931         for (i = 0; i < len; i++)
5932                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5933
5934         i = I915_READ(aud_cntrl_st2);
5935         i |= eldv;
5936         I915_WRITE(aud_cntrl_st2, i);
5937
5938 }
5939
5940 static void ironlake_write_eld(struct drm_connector *connector,
5941                                      struct drm_crtc *crtc)
5942 {
5943         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5944         uint8_t *eld = connector->eld;
5945         uint32_t eldv;
5946         uint32_t i;
5947         int len;
5948         int hdmiw_hdmiedid;
5949         int aud_config;
5950         int aud_cntl_st;
5951         int aud_cntrl_st2;
5952         int pipe = to_intel_crtc(crtc)->pipe;
5953
5954         if (HAS_PCH_IBX(connector->dev)) {
5955                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5956                 aud_config = IBX_AUD_CFG(pipe);
5957                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5958                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5959         } else {
5960                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5961                 aud_config = CPT_AUD_CFG(pipe);
5962                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5963                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5964         }
5965
5966         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5967
5968         i = I915_READ(aud_cntl_st);
5969         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5970         if (!i) {
5971                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5972                 /* operate blindly on all ports */
5973                 eldv = IBX_ELD_VALIDB;
5974                 eldv |= IBX_ELD_VALIDB << 4;
5975                 eldv |= IBX_ELD_VALIDB << 8;
5976         } else {
5977                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5978                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5979         }
5980
5981         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5982                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5983                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5984                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5985         } else
5986                 I915_WRITE(aud_config, 0);
5987
5988         if (intel_eld_uptodate(connector,
5989                                aud_cntrl_st2, eldv,
5990                                aud_cntl_st, IBX_ELD_ADDRESS,
5991                                hdmiw_hdmiedid))
5992                 return;
5993
5994         i = I915_READ(aud_cntrl_st2);
5995         i &= ~eldv;
5996         I915_WRITE(aud_cntrl_st2, i);
5997
5998         if (!eld[0])
5999                 return;
6000
6001         i = I915_READ(aud_cntl_st);
6002         i &= ~IBX_ELD_ADDRESS;
6003         I915_WRITE(aud_cntl_st, i);
6004
6005         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6006         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6007         for (i = 0; i < len; i++)
6008                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6009
6010         i = I915_READ(aud_cntrl_st2);
6011         i |= eldv;
6012         I915_WRITE(aud_cntrl_st2, i);
6013 }
6014
6015 void intel_write_eld(struct drm_encoder *encoder,
6016                      struct drm_display_mode *mode)
6017 {
6018         struct drm_crtc *crtc = encoder->crtc;
6019         struct drm_connector *connector;
6020         struct drm_device *dev = encoder->dev;
6021         struct drm_i915_private *dev_priv = dev->dev_private;
6022
6023         connector = drm_select_eld(encoder, mode);
6024         if (!connector)
6025                 return;
6026
6027         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6028                          connector->base.id,
6029                          drm_get_connector_name(connector),
6030                          connector->encoder->base.id,
6031                          drm_get_encoder_name(connector->encoder));
6032
6033         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6034
6035         if (dev_priv->display.write_eld)
6036                 dev_priv->display.write_eld(connector, crtc);
6037 }
6038
6039 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6040 void intel_crtc_load_lut(struct drm_crtc *crtc)
6041 {
6042         struct drm_device *dev = crtc->dev;
6043         struct drm_i915_private *dev_priv = dev->dev_private;
6044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6045         int palreg = PALETTE(intel_crtc->pipe);
6046         int i;
6047
6048         /* The clocks have to be on to load the palette. */
6049         if (!crtc->enabled || !intel_crtc->active)
6050                 return;
6051
6052         /* use legacy palette for Ironlake */
6053         if (HAS_PCH_SPLIT(dev))
6054                 palreg = LGC_PALETTE(intel_crtc->pipe);
6055
6056         for (i = 0; i < 256; i++) {
6057                 I915_WRITE(palreg + 4 * i,
6058                            (intel_crtc->lut_r[i] << 16) |
6059                            (intel_crtc->lut_g[i] << 8) |
6060                            intel_crtc->lut_b[i]);
6061         }
6062 }
6063
6064 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6065 {
6066         struct drm_device *dev = crtc->dev;
6067         struct drm_i915_private *dev_priv = dev->dev_private;
6068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6069         bool visible = base != 0;
6070         u32 cntl;
6071
6072         if (intel_crtc->cursor_visible == visible)
6073                 return;
6074
6075         cntl = I915_READ(_CURACNTR);
6076         if (visible) {
6077                 /* On these chipsets we can only modify the base whilst
6078                  * the cursor is disabled.
6079                  */
6080                 I915_WRITE(_CURABASE, base);
6081
6082                 cntl &= ~(CURSOR_FORMAT_MASK);
6083                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6084                 cntl |= CURSOR_ENABLE |
6085                         CURSOR_GAMMA_ENABLE |
6086                         CURSOR_FORMAT_ARGB;
6087         } else
6088                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6089         I915_WRITE(_CURACNTR, cntl);
6090
6091         intel_crtc->cursor_visible = visible;
6092 }
6093
6094 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6095 {
6096         struct drm_device *dev = crtc->dev;
6097         struct drm_i915_private *dev_priv = dev->dev_private;
6098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6099         int pipe = intel_crtc->pipe;
6100         bool visible = base != 0;
6101
6102         if (intel_crtc->cursor_visible != visible) {
6103                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6104                 if (base) {
6105                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6106                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6107                         cntl |= pipe << 28; /* Connect to correct pipe */
6108                 } else {
6109                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6110                         cntl |= CURSOR_MODE_DISABLE;
6111                 }
6112                 I915_WRITE(CURCNTR(pipe), cntl);
6113
6114                 intel_crtc->cursor_visible = visible;
6115         }
6116         /* and commit changes on next vblank */
6117         I915_WRITE(CURBASE(pipe), base);
6118 }
6119
6120 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6121 {
6122         struct drm_device *dev = crtc->dev;
6123         struct drm_i915_private *dev_priv = dev->dev_private;
6124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6125         int pipe = intel_crtc->pipe;
6126         bool visible = base != 0;
6127
6128         if (intel_crtc->cursor_visible != visible) {
6129                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6130                 if (base) {
6131                         cntl &= ~CURSOR_MODE;
6132                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6133                 } else {
6134                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6135                         cntl |= CURSOR_MODE_DISABLE;
6136                 }
6137                 if (IS_HASWELL(dev))
6138                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6139                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6140
6141                 intel_crtc->cursor_visible = visible;
6142         }
6143         /* and commit changes on next vblank */
6144         I915_WRITE(CURBASE_IVB(pipe), base);
6145 }
6146
6147 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6148 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6149                                      bool on)
6150 {
6151         struct drm_device *dev = crtc->dev;
6152         struct drm_i915_private *dev_priv = dev->dev_private;
6153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6154         int pipe = intel_crtc->pipe;
6155         int x = intel_crtc->cursor_x;
6156         int y = intel_crtc->cursor_y;
6157         u32 base, pos;
6158         bool visible;
6159
6160         pos = 0;
6161
6162         if (on && crtc->enabled && crtc->fb) {
6163                 base = intel_crtc->cursor_addr;
6164                 if (x > (int) crtc->fb->width)
6165                         base = 0;
6166
6167                 if (y > (int) crtc->fb->height)
6168                         base = 0;
6169         } else
6170                 base = 0;
6171
6172         if (x < 0) {
6173                 if (x + intel_crtc->cursor_width < 0)
6174                         base = 0;
6175
6176                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6177                 x = -x;
6178         }
6179         pos |= x << CURSOR_X_SHIFT;
6180
6181         if (y < 0) {
6182                 if (y + intel_crtc->cursor_height < 0)
6183                         base = 0;
6184
6185                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6186                 y = -y;
6187         }
6188         pos |= y << CURSOR_Y_SHIFT;
6189
6190         visible = base != 0;
6191         if (!visible && !intel_crtc->cursor_visible)
6192                 return;
6193
6194         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6195                 I915_WRITE(CURPOS_IVB(pipe), pos);
6196                 ivb_update_cursor(crtc, base);
6197         } else {
6198                 I915_WRITE(CURPOS(pipe), pos);
6199                 if (IS_845G(dev) || IS_I865G(dev))
6200                         i845_update_cursor(crtc, base);
6201                 else
6202                         i9xx_update_cursor(crtc, base);
6203         }
6204 }
6205
6206 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6207                                  struct drm_file *file,
6208                                  uint32_t handle,
6209                                  uint32_t width, uint32_t height)
6210 {
6211         struct drm_device *dev = crtc->dev;
6212         struct drm_i915_private *dev_priv = dev->dev_private;
6213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6214         struct drm_i915_gem_object *obj;
6215         uint32_t addr;
6216         int ret;
6217
6218         /* if we want to turn off the cursor ignore width and height */
6219         if (!handle) {
6220                 DRM_DEBUG_KMS("cursor off\n");
6221                 addr = 0;
6222                 obj = NULL;
6223                 mutex_lock(&dev->struct_mutex);
6224                 goto finish;
6225         }
6226
6227         /* Currently we only support 64x64 cursors */
6228         if (width != 64 || height != 64) {
6229                 DRM_ERROR("we currently only support 64x64 cursors\n");
6230                 return -EINVAL;
6231         }
6232
6233         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6234         if (&obj->base == NULL)
6235                 return -ENOENT;
6236
6237         if (obj->base.size < width * height * 4) {
6238                 DRM_ERROR("buffer is to small\n");
6239                 ret = -ENOMEM;
6240                 goto fail;
6241         }
6242
6243         /* we only need to pin inside GTT if cursor is non-phy */
6244         mutex_lock(&dev->struct_mutex);
6245         if (!dev_priv->info->cursor_needs_physical) {
6246                 unsigned alignment;
6247
6248                 if (obj->tiling_mode) {
6249                         DRM_ERROR("cursor cannot be tiled\n");
6250                         ret = -EINVAL;
6251                         goto fail_locked;
6252                 }
6253
6254                 /* Note that the w/a also requires 2 PTE of padding following
6255                  * the bo. We currently fill all unused PTE with the shadow
6256                  * page and so we should always have valid PTE following the
6257                  * cursor preventing the VT-d warning.
6258                  */
6259                 alignment = 0;
6260                 if (need_vtd_wa(dev))
6261                         alignment = 64*1024;
6262
6263                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6264                 if (ret) {
6265                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6266                         goto fail_locked;
6267                 }
6268
6269                 ret = i915_gem_object_put_fence(obj);
6270                 if (ret) {
6271                         DRM_ERROR("failed to release fence for cursor");
6272                         goto fail_unpin;
6273                 }
6274
6275                 addr = obj->gtt_offset;
6276         } else {
6277                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6278                 ret = i915_gem_attach_phys_object(dev, obj,
6279                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6280                                                   align);
6281                 if (ret) {
6282                         DRM_ERROR("failed to attach phys object\n");
6283                         goto fail_locked;
6284                 }
6285                 addr = obj->phys_obj->handle->busaddr;
6286         }
6287
6288         if (IS_GEN2(dev))
6289                 I915_WRITE(CURSIZE, (height << 12) | width);
6290
6291  finish:
6292         if (intel_crtc->cursor_bo) {
6293                 if (dev_priv->info->cursor_needs_physical) {
6294                         if (intel_crtc->cursor_bo != obj)
6295                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6296                 } else
6297                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6298                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6299         }
6300
6301         mutex_unlock(&dev->struct_mutex);
6302
6303         intel_crtc->cursor_addr = addr;
6304         intel_crtc->cursor_bo = obj;
6305         intel_crtc->cursor_width = width;
6306         intel_crtc->cursor_height = height;
6307
6308         intel_crtc_update_cursor(crtc, true);
6309
6310         return 0;
6311 fail_unpin:
6312         i915_gem_object_unpin(obj);
6313 fail_locked:
6314         mutex_unlock(&dev->struct_mutex);
6315 fail:
6316         drm_gem_object_unreference_unlocked(&obj->base);
6317         return ret;
6318 }
6319
6320 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6321 {
6322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6323
6324         intel_crtc->cursor_x = x;
6325         intel_crtc->cursor_y = y;
6326
6327         intel_crtc_update_cursor(crtc, true);
6328
6329         return 0;
6330 }
6331
6332 /** Sets the color ramps on behalf of RandR */
6333 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6334                                  u16 blue, int regno)
6335 {
6336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6337
6338         intel_crtc->lut_r[regno] = red >> 8;
6339         intel_crtc->lut_g[regno] = green >> 8;
6340         intel_crtc->lut_b[regno] = blue >> 8;
6341 }
6342
6343 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6344                              u16 *blue, int regno)
6345 {
6346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6347
6348         *red = intel_crtc->lut_r[regno] << 8;
6349         *green = intel_crtc->lut_g[regno] << 8;
6350         *blue = intel_crtc->lut_b[regno] << 8;
6351 }
6352
6353 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6354                                  u16 *blue, uint32_t start, uint32_t size)
6355 {
6356         int end = (start + size > 256) ? 256 : start + size, i;
6357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358
6359         for (i = start; i < end; i++) {
6360                 intel_crtc->lut_r[i] = red[i] >> 8;
6361                 intel_crtc->lut_g[i] = green[i] >> 8;
6362                 intel_crtc->lut_b[i] = blue[i] >> 8;
6363         }
6364
6365         intel_crtc_load_lut(crtc);
6366 }
6367
6368 /* VESA 640x480x72Hz mode to set on the pipe */
6369 static struct drm_display_mode load_detect_mode = {
6370         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6371                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6372 };
6373
6374 static struct drm_framebuffer *
6375 intel_framebuffer_create(struct drm_device *dev,
6376                          struct drm_mode_fb_cmd2 *mode_cmd,
6377                          struct drm_i915_gem_object *obj)
6378 {
6379         struct intel_framebuffer *intel_fb;
6380         int ret;
6381
6382         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6383         if (!intel_fb) {
6384                 drm_gem_object_unreference_unlocked(&obj->base);
6385                 return ERR_PTR(-ENOMEM);
6386         }
6387
6388         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6389         if (ret) {
6390                 drm_gem_object_unreference_unlocked(&obj->base);
6391                 kfree(intel_fb);
6392                 return ERR_PTR(ret);
6393         }
6394
6395         return &intel_fb->base;
6396 }
6397
6398 static u32
6399 intel_framebuffer_pitch_for_width(int width, int bpp)
6400 {
6401         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6402         return ALIGN(pitch, 64);
6403 }
6404
6405 static u32
6406 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6407 {
6408         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6409         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6410 }
6411
6412 static struct drm_framebuffer *
6413 intel_framebuffer_create_for_mode(struct drm_device *dev,
6414                                   struct drm_display_mode *mode,
6415                                   int depth, int bpp)
6416 {
6417         struct drm_i915_gem_object *obj;
6418         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6419
6420         obj = i915_gem_alloc_object(dev,
6421                                     intel_framebuffer_size_for_mode(mode, bpp));
6422         if (obj == NULL)
6423                 return ERR_PTR(-ENOMEM);
6424
6425         mode_cmd.width = mode->hdisplay;
6426         mode_cmd.height = mode->vdisplay;
6427         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6428                                                                 bpp);
6429         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6430
6431         return intel_framebuffer_create(dev, &mode_cmd, obj);
6432 }
6433
6434 static struct drm_framebuffer *
6435 mode_fits_in_fbdev(struct drm_device *dev,
6436                    struct drm_display_mode *mode)
6437 {
6438         struct drm_i915_private *dev_priv = dev->dev_private;
6439         struct drm_i915_gem_object *obj;
6440         struct drm_framebuffer *fb;
6441
6442         if (dev_priv->fbdev == NULL)
6443                 return NULL;
6444
6445         obj = dev_priv->fbdev->ifb.obj;
6446         if (obj == NULL)
6447                 return NULL;
6448
6449         fb = &dev_priv->fbdev->ifb.base;
6450         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6451                                                                fb->bits_per_pixel))
6452                 return NULL;
6453
6454         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6455                 return NULL;
6456
6457         return fb;
6458 }
6459
6460 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6461                                 struct drm_display_mode *mode,
6462                                 struct intel_load_detect_pipe *old)
6463 {
6464         struct intel_crtc *intel_crtc;
6465         struct intel_encoder *intel_encoder =
6466                 intel_attached_encoder(connector);
6467         struct drm_crtc *possible_crtc;
6468         struct drm_encoder *encoder = &intel_encoder->base;
6469         struct drm_crtc *crtc = NULL;
6470         struct drm_device *dev = encoder->dev;
6471         struct drm_framebuffer *fb;
6472         int i = -1;
6473
6474         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6475                       connector->base.id, drm_get_connector_name(connector),
6476                       encoder->base.id, drm_get_encoder_name(encoder));
6477
6478         /*
6479          * Algorithm gets a little messy:
6480          *
6481          *   - if the connector already has an assigned crtc, use it (but make
6482          *     sure it's on first)
6483          *
6484          *   - try to find the first unused crtc that can drive this connector,
6485          *     and use that if we find one
6486          */
6487
6488         /* See if we already have a CRTC for this connector */
6489         if (encoder->crtc) {
6490                 crtc = encoder->crtc;
6491
6492                 mutex_lock(&crtc->mutex);
6493
6494                 old->dpms_mode = connector->dpms;
6495                 old->load_detect_temp = false;
6496
6497                 /* Make sure the crtc and connector are running */
6498                 if (connector->dpms != DRM_MODE_DPMS_ON)
6499                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6500
6501                 return true;
6502         }
6503
6504         /* Find an unused one (if possible) */
6505         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6506                 i++;
6507                 if (!(encoder->possible_crtcs & (1 << i)))
6508                         continue;
6509                 if (!possible_crtc->enabled) {
6510                         crtc = possible_crtc;
6511                         break;
6512                 }
6513         }
6514
6515         /*
6516          * If we didn't find an unused CRTC, don't use any.
6517          */
6518         if (!crtc) {
6519                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6520                 return false;
6521         }
6522
6523         mutex_lock(&crtc->mutex);
6524         intel_encoder->new_crtc = to_intel_crtc(crtc);
6525         to_intel_connector(connector)->new_encoder = intel_encoder;
6526
6527         intel_crtc = to_intel_crtc(crtc);
6528         old->dpms_mode = connector->dpms;
6529         old->load_detect_temp = true;
6530         old->release_fb = NULL;
6531
6532         if (!mode)
6533                 mode = &load_detect_mode;
6534
6535         /* We need a framebuffer large enough to accommodate all accesses
6536          * that the plane may generate whilst we perform load detection.
6537          * We can not rely on the fbcon either being present (we get called
6538          * during its initialisation to detect all boot displays, or it may
6539          * not even exist) or that it is large enough to satisfy the
6540          * requested mode.
6541          */
6542         fb = mode_fits_in_fbdev(dev, mode);
6543         if (fb == NULL) {
6544                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6545                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6546                 old->release_fb = fb;
6547         } else
6548                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6549         if (IS_ERR(fb)) {
6550                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6551                 mutex_unlock(&crtc->mutex);
6552                 return false;
6553         }
6554
6555         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6556                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6557                 if (old->release_fb)
6558                         old->release_fb->funcs->destroy(old->release_fb);
6559                 mutex_unlock(&crtc->mutex);
6560                 return false;
6561         }
6562
6563         /* let the connector get through one full cycle before testing */
6564         intel_wait_for_vblank(dev, intel_crtc->pipe);
6565         return true;
6566 }
6567
6568 void intel_release_load_detect_pipe(struct drm_connector *connector,
6569                                     struct intel_load_detect_pipe *old)
6570 {
6571         struct intel_encoder *intel_encoder =
6572                 intel_attached_encoder(connector);
6573         struct drm_encoder *encoder = &intel_encoder->base;
6574         struct drm_crtc *crtc = encoder->crtc;
6575
6576         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6577                       connector->base.id, drm_get_connector_name(connector),
6578                       encoder->base.id, drm_get_encoder_name(encoder));
6579
6580         if (old->load_detect_temp) {
6581                 to_intel_connector(connector)->new_encoder = NULL;
6582                 intel_encoder->new_crtc = NULL;
6583                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6584
6585                 if (old->release_fb) {
6586                         drm_framebuffer_unregister_private(old->release_fb);
6587                         drm_framebuffer_unreference(old->release_fb);
6588                 }
6589
6590                 mutex_unlock(&crtc->mutex);
6591                 return;
6592         }
6593
6594         /* Switch crtc and encoder back off if necessary */
6595         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6596                 connector->funcs->dpms(connector, old->dpms_mode);
6597
6598         mutex_unlock(&crtc->mutex);
6599 }
6600
6601 /* Returns the clock of the currently programmed mode of the given pipe. */
6602 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6603 {
6604         struct drm_i915_private *dev_priv = dev->dev_private;
6605         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6606         int pipe = intel_crtc->pipe;
6607         u32 dpll = I915_READ(DPLL(pipe));
6608         u32 fp;
6609         intel_clock_t clock;
6610
6611         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6612                 fp = I915_READ(FP0(pipe));
6613         else
6614                 fp = I915_READ(FP1(pipe));
6615
6616         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6617         if (IS_PINEVIEW(dev)) {
6618                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6619                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6620         } else {
6621                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6622                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6623         }
6624
6625         if (!IS_GEN2(dev)) {
6626                 if (IS_PINEVIEW(dev))
6627                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6628                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6629                 else
6630                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6631                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6632
6633                 switch (dpll & DPLL_MODE_MASK) {
6634                 case DPLLB_MODE_DAC_SERIAL:
6635                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6636                                 5 : 10;
6637                         break;
6638                 case DPLLB_MODE_LVDS:
6639                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6640                                 7 : 14;
6641                         break;
6642                 default:
6643                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6644                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6645                         return 0;
6646                 }
6647
6648                 /* XXX: Handle the 100Mhz refclk */
6649                 intel_clock(dev, 96000, &clock);
6650         } else {
6651                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6652
6653                 if (is_lvds) {
6654                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6655                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6656                         clock.p2 = 14;
6657
6658                         if ((dpll & PLL_REF_INPUT_MASK) ==
6659                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6660                                 /* XXX: might not be 66MHz */
6661                                 intel_clock(dev, 66000, &clock);
6662                         } else
6663                                 intel_clock(dev, 48000, &clock);
6664                 } else {
6665                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6666                                 clock.p1 = 2;
6667                         else {
6668                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6669                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6670                         }
6671                         if (dpll & PLL_P2_DIVIDE_BY_4)
6672                                 clock.p2 = 4;
6673                         else
6674                                 clock.p2 = 2;
6675
6676                         intel_clock(dev, 48000, &clock);
6677                 }
6678         }
6679
6680         /* XXX: It would be nice to validate the clocks, but we can't reuse
6681          * i830PllIsValid() because it relies on the xf86_config connector
6682          * configuration being accurate, which it isn't necessarily.
6683          */
6684
6685         return clock.dot;
6686 }
6687
6688 /** Returns the currently programmed mode of the given pipe. */
6689 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6690                                              struct drm_crtc *crtc)
6691 {
6692         struct drm_i915_private *dev_priv = dev->dev_private;
6693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6694         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6695         struct drm_display_mode *mode;
6696         int htot = I915_READ(HTOTAL(cpu_transcoder));
6697         int hsync = I915_READ(HSYNC(cpu_transcoder));
6698         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6699         int vsync = I915_READ(VSYNC(cpu_transcoder));
6700
6701         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6702         if (!mode)
6703                 return NULL;
6704
6705         mode->clock = intel_crtc_clock_get(dev, crtc);
6706         mode->hdisplay = (htot & 0xffff) + 1;
6707         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6708         mode->hsync_start = (hsync & 0xffff) + 1;
6709         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6710         mode->vdisplay = (vtot & 0xffff) + 1;
6711         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6712         mode->vsync_start = (vsync & 0xffff) + 1;
6713         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6714
6715         drm_mode_set_name(mode);
6716
6717         return mode;
6718 }
6719
6720 static void intel_increase_pllclock(struct drm_crtc *crtc)
6721 {
6722         struct drm_device *dev = crtc->dev;
6723         drm_i915_private_t *dev_priv = dev->dev_private;
6724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6725         int pipe = intel_crtc->pipe;
6726         int dpll_reg = DPLL(pipe);
6727         int dpll;
6728
6729         if (HAS_PCH_SPLIT(dev))
6730                 return;
6731
6732         if (!dev_priv->lvds_downclock_avail)
6733                 return;
6734
6735         dpll = I915_READ(dpll_reg);
6736         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6737                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6738
6739                 assert_panel_unlocked(dev_priv, pipe);
6740
6741                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6742                 I915_WRITE(dpll_reg, dpll);
6743                 intel_wait_for_vblank(dev, pipe);
6744
6745                 dpll = I915_READ(dpll_reg);
6746                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6747                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6748         }
6749 }
6750
6751 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6752 {
6753         struct drm_device *dev = crtc->dev;
6754         drm_i915_private_t *dev_priv = dev->dev_private;
6755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6756
6757         if (HAS_PCH_SPLIT(dev))
6758                 return;
6759
6760         if (!dev_priv->lvds_downclock_avail)
6761                 return;
6762
6763         /*
6764          * Since this is called by a timer, we should never get here in
6765          * the manual case.
6766          */
6767         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6768                 int pipe = intel_crtc->pipe;
6769                 int dpll_reg = DPLL(pipe);
6770                 int dpll;
6771
6772                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6773
6774                 assert_panel_unlocked(dev_priv, pipe);
6775
6776                 dpll = I915_READ(dpll_reg);
6777                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6778                 I915_WRITE(dpll_reg, dpll);
6779                 intel_wait_for_vblank(dev, pipe);
6780                 dpll = I915_READ(dpll_reg);
6781                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6782                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6783         }
6784
6785 }
6786
6787 void intel_mark_busy(struct drm_device *dev)
6788 {
6789         i915_update_gfx_val(dev->dev_private);
6790 }
6791
6792 void intel_mark_idle(struct drm_device *dev)
6793 {
6794         struct drm_crtc *crtc;
6795
6796         if (!i915_powersave)
6797                 return;
6798
6799         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6800                 if (!crtc->fb)
6801                         continue;
6802
6803                 intel_decrease_pllclock(crtc);
6804         }
6805 }
6806
6807 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6808 {
6809         struct drm_device *dev = obj->base.dev;
6810         struct drm_crtc *crtc;
6811
6812         if (!i915_powersave)
6813                 return;
6814
6815         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6816                 if (!crtc->fb)
6817                         continue;
6818
6819                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6820                         intel_increase_pllclock(crtc);
6821         }
6822 }
6823
6824 static void intel_crtc_destroy(struct drm_crtc *crtc)
6825 {
6826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6827         struct drm_device *dev = crtc->dev;
6828         struct intel_unpin_work *work;
6829         unsigned long flags;
6830
6831         spin_lock_irqsave(&dev->event_lock, flags);
6832         work = intel_crtc->unpin_work;
6833         intel_crtc->unpin_work = NULL;
6834         spin_unlock_irqrestore(&dev->event_lock, flags);
6835
6836         if (work) {
6837                 cancel_work_sync(&work->work);
6838                 kfree(work);
6839         }
6840
6841         drm_crtc_cleanup(crtc);
6842
6843         kfree(intel_crtc);
6844 }
6845
6846 static void intel_unpin_work_fn(struct work_struct *__work)
6847 {
6848         struct intel_unpin_work *work =
6849                 container_of(__work, struct intel_unpin_work, work);
6850         struct drm_device *dev = work->crtc->dev;
6851
6852         mutex_lock(&dev->struct_mutex);
6853         intel_unpin_fb_obj(work->old_fb_obj);
6854         drm_gem_object_unreference(&work->pending_flip_obj->base);
6855         drm_gem_object_unreference(&work->old_fb_obj->base);
6856
6857         intel_update_fbc(dev);
6858         mutex_unlock(&dev->struct_mutex);
6859
6860         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6861         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6862
6863         kfree(work);
6864 }
6865
6866 static void do_intel_finish_page_flip(struct drm_device *dev,
6867                                       struct drm_crtc *crtc)
6868 {
6869         drm_i915_private_t *dev_priv = dev->dev_private;
6870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6871         struct intel_unpin_work *work;
6872         unsigned long flags;
6873
6874         /* Ignore early vblank irqs */
6875         if (intel_crtc == NULL)
6876                 return;
6877
6878         spin_lock_irqsave(&dev->event_lock, flags);
6879         work = intel_crtc->unpin_work;
6880
6881         /* Ensure we don't miss a work->pending update ... */
6882         smp_rmb();
6883
6884         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6885                 spin_unlock_irqrestore(&dev->event_lock, flags);
6886                 return;
6887         }
6888
6889         /* and that the unpin work is consistent wrt ->pending. */
6890         smp_rmb();
6891
6892         intel_crtc->unpin_work = NULL;
6893
6894         if (work->event)
6895                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6896
6897         drm_vblank_put(dev, intel_crtc->pipe);
6898
6899         spin_unlock_irqrestore(&dev->event_lock, flags);
6900
6901         wake_up_all(&dev_priv->pending_flip_queue);
6902
6903         queue_work(dev_priv->wq, &work->work);
6904
6905         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6906 }
6907
6908 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6909 {
6910         drm_i915_private_t *dev_priv = dev->dev_private;
6911         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6912
6913         do_intel_finish_page_flip(dev, crtc);
6914 }
6915
6916 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6917 {
6918         drm_i915_private_t *dev_priv = dev->dev_private;
6919         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6920
6921         do_intel_finish_page_flip(dev, crtc);
6922 }
6923
6924 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6925 {
6926         drm_i915_private_t *dev_priv = dev->dev_private;
6927         struct intel_crtc *intel_crtc =
6928                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6929         unsigned long flags;
6930
6931         /* NB: An MMIO update of the plane base pointer will also
6932          * generate a page-flip completion irq, i.e. every modeset
6933          * is also accompanied by a spurious intel_prepare_page_flip().
6934          */
6935         spin_lock_irqsave(&dev->event_lock, flags);
6936         if (intel_crtc->unpin_work)
6937                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6938         spin_unlock_irqrestore(&dev->event_lock, flags);
6939 }
6940
6941 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6942 {
6943         /* Ensure that the work item is consistent when activating it ... */
6944         smp_wmb();
6945         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
6946         /* and that it is marked active as soon as the irq could fire. */
6947         smp_wmb();
6948 }
6949
6950 static int intel_gen2_queue_flip(struct drm_device *dev,
6951                                  struct drm_crtc *crtc,
6952                                  struct drm_framebuffer *fb,
6953                                  struct drm_i915_gem_object *obj)
6954 {
6955         struct drm_i915_private *dev_priv = dev->dev_private;
6956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6957         u32 flip_mask;
6958         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6959         int ret;
6960
6961         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6962         if (ret)
6963                 goto err;
6964
6965         ret = intel_ring_begin(ring, 6);
6966         if (ret)
6967                 goto err_unpin;
6968
6969         /* Can't queue multiple flips, so wait for the previous
6970          * one to finish before executing the next.
6971          */
6972         if (intel_crtc->plane)
6973                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6974         else
6975                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6976         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6977         intel_ring_emit(ring, MI_NOOP);
6978         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6979                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6980         intel_ring_emit(ring, fb->pitches[0]);
6981         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6982         intel_ring_emit(ring, 0); /* aux display base address, unused */
6983
6984         intel_mark_page_flip_active(intel_crtc);
6985         intel_ring_advance(ring);
6986         return 0;
6987
6988 err_unpin:
6989         intel_unpin_fb_obj(obj);
6990 err:
6991         return ret;
6992 }
6993
6994 static int intel_gen3_queue_flip(struct drm_device *dev,
6995                                  struct drm_crtc *crtc,
6996                                  struct drm_framebuffer *fb,
6997                                  struct drm_i915_gem_object *obj)
6998 {
6999         struct drm_i915_private *dev_priv = dev->dev_private;
7000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7001         u32 flip_mask;
7002         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7003         int ret;
7004
7005         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7006         if (ret)
7007                 goto err;
7008
7009         ret = intel_ring_begin(ring, 6);
7010         if (ret)
7011                 goto err_unpin;
7012
7013         if (intel_crtc->plane)
7014                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7015         else
7016                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7017         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7018         intel_ring_emit(ring, MI_NOOP);
7019         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7020                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7021         intel_ring_emit(ring, fb->pitches[0]);
7022         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7023         intel_ring_emit(ring, MI_NOOP);
7024
7025         intel_mark_page_flip_active(intel_crtc);
7026         intel_ring_advance(ring);
7027         return 0;
7028
7029 err_unpin:
7030         intel_unpin_fb_obj(obj);
7031 err:
7032         return ret;
7033 }
7034
7035 static int intel_gen4_queue_flip(struct drm_device *dev,
7036                                  struct drm_crtc *crtc,
7037                                  struct drm_framebuffer *fb,
7038                                  struct drm_i915_gem_object *obj)
7039 {
7040         struct drm_i915_private *dev_priv = dev->dev_private;
7041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7042         uint32_t pf, pipesrc;
7043         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7044         int ret;
7045
7046         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7047         if (ret)
7048                 goto err;
7049
7050         ret = intel_ring_begin(ring, 4);
7051         if (ret)
7052                 goto err_unpin;
7053
7054         /* i965+ uses the linear or tiled offsets from the
7055          * Display Registers (which do not change across a page-flip)
7056          * so we need only reprogram the base address.
7057          */
7058         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7059                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7060         intel_ring_emit(ring, fb->pitches[0]);
7061         intel_ring_emit(ring,
7062                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7063                         obj->tiling_mode);
7064
7065         /* XXX Enabling the panel-fitter across page-flip is so far
7066          * untested on non-native modes, so ignore it for now.
7067          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7068          */
7069         pf = 0;
7070         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7071         intel_ring_emit(ring, pf | pipesrc);
7072
7073         intel_mark_page_flip_active(intel_crtc);
7074         intel_ring_advance(ring);
7075         return 0;
7076
7077 err_unpin:
7078         intel_unpin_fb_obj(obj);
7079 err:
7080         return ret;
7081 }
7082
7083 static int intel_gen6_queue_flip(struct drm_device *dev,
7084                                  struct drm_crtc *crtc,
7085                                  struct drm_framebuffer *fb,
7086                                  struct drm_i915_gem_object *obj)
7087 {
7088         struct drm_i915_private *dev_priv = dev->dev_private;
7089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7090         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7091         uint32_t pf, pipesrc;
7092         int ret;
7093
7094         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7095         if (ret)
7096                 goto err;
7097
7098         ret = intel_ring_begin(ring, 4);
7099         if (ret)
7100                 goto err_unpin;
7101
7102         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7103                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7104         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7105         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7106
7107         /* Contrary to the suggestions in the documentation,
7108          * "Enable Panel Fitter" does not seem to be required when page
7109          * flipping with a non-native mode, and worse causes a normal
7110          * modeset to fail.
7111          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7112          */
7113         pf = 0;
7114         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7115         intel_ring_emit(ring, pf | pipesrc);
7116
7117         intel_mark_page_flip_active(intel_crtc);
7118         intel_ring_advance(ring);
7119         return 0;
7120
7121 err_unpin:
7122         intel_unpin_fb_obj(obj);
7123 err:
7124         return ret;
7125 }
7126
7127 /*
7128  * On gen7 we currently use the blit ring because (in early silicon at least)
7129  * the render ring doesn't give us interrpts for page flip completion, which
7130  * means clients will hang after the first flip is queued.  Fortunately the
7131  * blit ring generates interrupts properly, so use it instead.
7132  */
7133 static int intel_gen7_queue_flip(struct drm_device *dev,
7134                                  struct drm_crtc *crtc,
7135                                  struct drm_framebuffer *fb,
7136                                  struct drm_i915_gem_object *obj)
7137 {
7138         struct drm_i915_private *dev_priv = dev->dev_private;
7139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7140         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7141         uint32_t plane_bit = 0;
7142         int ret;
7143
7144         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7145         if (ret)
7146                 goto err;
7147
7148         switch(intel_crtc->plane) {
7149         case PLANE_A:
7150                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7151                 break;
7152         case PLANE_B:
7153                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7154                 break;
7155         case PLANE_C:
7156                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7157                 break;
7158         default:
7159                 WARN_ONCE(1, "unknown plane in flip command\n");
7160                 ret = -ENODEV;
7161                 goto err_unpin;
7162         }
7163
7164         ret = intel_ring_begin(ring, 4);
7165         if (ret)
7166                 goto err_unpin;
7167
7168         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7169         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7170         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7171         intel_ring_emit(ring, (MI_NOOP));
7172
7173         intel_mark_page_flip_active(intel_crtc);
7174         intel_ring_advance(ring);
7175         return 0;
7176
7177 err_unpin:
7178         intel_unpin_fb_obj(obj);
7179 err:
7180         return ret;
7181 }
7182
7183 static int intel_default_queue_flip(struct drm_device *dev,
7184                                     struct drm_crtc *crtc,
7185                                     struct drm_framebuffer *fb,
7186                                     struct drm_i915_gem_object *obj)
7187 {
7188         return -ENODEV;
7189 }
7190
7191 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7192                                 struct drm_framebuffer *fb,
7193                                 struct drm_pending_vblank_event *event)
7194 {
7195         struct drm_device *dev = crtc->dev;
7196         struct drm_i915_private *dev_priv = dev->dev_private;
7197         struct drm_framebuffer *old_fb = crtc->fb;
7198         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7200         struct intel_unpin_work *work;
7201         unsigned long flags;
7202         int ret;
7203
7204         /* Can't change pixel format via MI display flips. */
7205         if (fb->pixel_format != crtc->fb->pixel_format)
7206                 return -EINVAL;
7207
7208         /*
7209          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7210          * Note that pitch changes could also affect these register.
7211          */
7212         if (INTEL_INFO(dev)->gen > 3 &&
7213             (fb->offsets[0] != crtc->fb->offsets[0] ||
7214              fb->pitches[0] != crtc->fb->pitches[0]))
7215                 return -EINVAL;
7216
7217         work = kzalloc(sizeof *work, GFP_KERNEL);
7218         if (work == NULL)
7219                 return -ENOMEM;
7220
7221         work->event = event;
7222         work->crtc = crtc;
7223         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7224         INIT_WORK(&work->work, intel_unpin_work_fn);
7225
7226         ret = drm_vblank_get(dev, intel_crtc->pipe);
7227         if (ret)
7228                 goto free_work;
7229
7230         /* We borrow the event spin lock for protecting unpin_work */
7231         spin_lock_irqsave(&dev->event_lock, flags);
7232         if (intel_crtc->unpin_work) {
7233                 spin_unlock_irqrestore(&dev->event_lock, flags);
7234                 kfree(work);
7235                 drm_vblank_put(dev, intel_crtc->pipe);
7236
7237                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7238                 return -EBUSY;
7239         }
7240         intel_crtc->unpin_work = work;
7241         spin_unlock_irqrestore(&dev->event_lock, flags);
7242
7243         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7244                 flush_workqueue(dev_priv->wq);
7245
7246         ret = i915_mutex_lock_interruptible(dev);
7247         if (ret)
7248                 goto cleanup;
7249
7250         /* Reference the objects for the scheduled work. */
7251         drm_gem_object_reference(&work->old_fb_obj->base);
7252         drm_gem_object_reference(&obj->base);
7253
7254         crtc->fb = fb;
7255
7256         work->pending_flip_obj = obj;
7257
7258         work->enable_stall_check = true;
7259
7260         atomic_inc(&intel_crtc->unpin_work_count);
7261         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7262
7263         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7264         if (ret)
7265                 goto cleanup_pending;
7266
7267         intel_disable_fbc(dev);
7268         intel_mark_fb_busy(obj);
7269         mutex_unlock(&dev->struct_mutex);
7270
7271         trace_i915_flip_request(intel_crtc->plane, obj);
7272
7273         return 0;
7274
7275 cleanup_pending:
7276         atomic_dec(&intel_crtc->unpin_work_count);
7277         crtc->fb = old_fb;
7278         drm_gem_object_unreference(&work->old_fb_obj->base);
7279         drm_gem_object_unreference(&obj->base);
7280         mutex_unlock(&dev->struct_mutex);
7281
7282 cleanup:
7283         spin_lock_irqsave(&dev->event_lock, flags);
7284         intel_crtc->unpin_work = NULL;
7285         spin_unlock_irqrestore(&dev->event_lock, flags);
7286
7287         drm_vblank_put(dev, intel_crtc->pipe);
7288 free_work:
7289         kfree(work);
7290
7291         return ret;
7292 }
7293
7294 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7295         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7296         .load_lut = intel_crtc_load_lut,
7297 };
7298
7299 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7300 {
7301         struct intel_encoder *other_encoder;
7302         struct drm_crtc *crtc = &encoder->new_crtc->base;
7303
7304         if (WARN_ON(!crtc))
7305                 return false;
7306
7307         list_for_each_entry(other_encoder,
7308                             &crtc->dev->mode_config.encoder_list,
7309                             base.head) {
7310
7311                 if (&other_encoder->new_crtc->base != crtc ||
7312                     encoder == other_encoder)
7313                         continue;
7314                 else
7315                         return true;
7316         }
7317
7318         return false;
7319 }
7320
7321 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7322                                   struct drm_crtc *crtc)
7323 {
7324         struct drm_device *dev;
7325         struct drm_crtc *tmp;
7326         int crtc_mask = 1;
7327
7328         WARN(!crtc, "checking null crtc?\n");
7329
7330         dev = crtc->dev;
7331
7332         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7333                 if (tmp == crtc)
7334                         break;
7335                 crtc_mask <<= 1;
7336         }
7337
7338         if (encoder->possible_crtcs & crtc_mask)
7339                 return true;
7340         return false;
7341 }
7342
7343 /**
7344  * intel_modeset_update_staged_output_state
7345  *
7346  * Updates the staged output configuration state, e.g. after we've read out the
7347  * current hw state.
7348  */
7349 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7350 {
7351         struct intel_encoder *encoder;
7352         struct intel_connector *connector;
7353
7354         list_for_each_entry(connector, &dev->mode_config.connector_list,
7355                             base.head) {
7356                 connector->new_encoder =
7357                         to_intel_encoder(connector->base.encoder);
7358         }
7359
7360         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7361                             base.head) {
7362                 encoder->new_crtc =
7363                         to_intel_crtc(encoder->base.crtc);
7364         }
7365 }
7366
7367 /**
7368  * intel_modeset_commit_output_state
7369  *
7370  * This function copies the stage display pipe configuration to the real one.
7371  */
7372 static void intel_modeset_commit_output_state(struct drm_device *dev)
7373 {
7374         struct intel_encoder *encoder;
7375         struct intel_connector *connector;
7376
7377         list_for_each_entry(connector, &dev->mode_config.connector_list,
7378                             base.head) {
7379                 connector->base.encoder = &connector->new_encoder->base;
7380         }
7381
7382         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7383                             base.head) {
7384                 encoder->base.crtc = &encoder->new_crtc->base;
7385         }
7386 }
7387
7388 static int
7389 pipe_config_set_bpp(struct drm_crtc *crtc,
7390                     struct drm_framebuffer *fb,
7391                     struct intel_crtc_config *pipe_config)
7392 {
7393         struct drm_device *dev = crtc->dev;
7394         struct drm_connector *connector;
7395         int bpp;
7396
7397         switch (fb->depth) {
7398         case 8:
7399                 bpp = 8*3; /* since we go through a colormap */
7400                 break;
7401         case 15:
7402         case 16:
7403                 bpp = 6*3; /* min is 18bpp */
7404                 break;
7405         case 24:
7406                 bpp = 8*3;
7407                 break;
7408         case 30:
7409                 if (INTEL_INFO(dev)->gen < 4) {
7410                         DRM_DEBUG_KMS("10 bpc not supported on gen2/3\n");
7411                         return -EINVAL;
7412                 }
7413
7414                 bpp = 10*3;
7415                 break;
7416         /* TODO: gen4+ supports 16 bpc floating point, too. */
7417         default:
7418                 DRM_DEBUG_KMS("unsupported depth\n");
7419                 return -EINVAL;
7420         }
7421
7422         pipe_config->pipe_bpp = bpp;
7423
7424         /* Clamp display bpp to EDID value */
7425         list_for_each_entry(connector, &dev->mode_config.connector_list,
7426                             head) {
7427                 if (connector->encoder && connector->encoder->crtc != crtc)
7428                         continue;
7429
7430                 /* Don't use an invalid EDID bpc value */
7431                 if (connector->display_info.bpc &&
7432                     connector->display_info.bpc * 3 < bpp) {
7433                         DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7434                                       bpp, connector->display_info.bpc*3);
7435                         pipe_config->pipe_bpp = connector->display_info.bpc*3;
7436                 }
7437         }
7438
7439         return bpp;
7440 }
7441
7442 static struct intel_crtc_config *
7443 intel_modeset_pipe_config(struct drm_crtc *crtc,
7444                           struct drm_framebuffer *fb,
7445                           struct drm_display_mode *mode)
7446 {
7447         struct drm_device *dev = crtc->dev;
7448         struct drm_encoder_helper_funcs *encoder_funcs;
7449         struct intel_encoder *encoder;
7450         struct intel_crtc_config *pipe_config;
7451         int plane_bpp;
7452
7453         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7454         if (!pipe_config)
7455                 return ERR_PTR(-ENOMEM);
7456
7457         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7458         drm_mode_copy(&pipe_config->requested_mode, mode);
7459
7460         plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7461         if (plane_bpp < 0)
7462                 goto fail;
7463
7464         /* Pass our mode to the connectors and the CRTC to give them a chance to
7465          * adjust it according to limitations or connector properties, and also
7466          * a chance to reject the mode entirely.
7467          */
7468         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7469                             base.head) {
7470
7471                 if (&encoder->new_crtc->base != crtc)
7472                         continue;
7473
7474                 if (encoder->compute_config) {
7475                         if (!(encoder->compute_config(encoder, pipe_config))) {
7476                                 DRM_DEBUG_KMS("Encoder config failure\n");
7477                                 goto fail;
7478                         }
7479
7480                         continue;
7481                 }
7482
7483                 encoder_funcs = encoder->base.helper_private;
7484                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7485                                                 &pipe_config->requested_mode,
7486                                                 &pipe_config->adjusted_mode))) {
7487                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7488                         goto fail;
7489                 }
7490         }
7491
7492         if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7493                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7494                 goto fail;
7495         }
7496         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7497
7498         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7499         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7500                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7501
7502         return pipe_config;
7503 fail:
7504         kfree(pipe_config);
7505         return ERR_PTR(-EINVAL);
7506 }
7507
7508 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7509  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7510 static void
7511 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7512                              unsigned *prepare_pipes, unsigned *disable_pipes)
7513 {
7514         struct intel_crtc *intel_crtc;
7515         struct drm_device *dev = crtc->dev;
7516         struct intel_encoder *encoder;
7517         struct intel_connector *connector;
7518         struct drm_crtc *tmp_crtc;
7519
7520         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7521
7522         /* Check which crtcs have changed outputs connected to them, these need
7523          * to be part of the prepare_pipes mask. We don't (yet) support global
7524          * modeset across multiple crtcs, so modeset_pipes will only have one
7525          * bit set at most. */
7526         list_for_each_entry(connector, &dev->mode_config.connector_list,
7527                             base.head) {
7528                 if (connector->base.encoder == &connector->new_encoder->base)
7529                         continue;
7530
7531                 if (connector->base.encoder) {
7532                         tmp_crtc = connector->base.encoder->crtc;
7533
7534                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7535                 }
7536
7537                 if (connector->new_encoder)
7538                         *prepare_pipes |=
7539                                 1 << connector->new_encoder->new_crtc->pipe;
7540         }
7541
7542         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7543                             base.head) {
7544                 if (encoder->base.crtc == &encoder->new_crtc->base)
7545                         continue;
7546
7547                 if (encoder->base.crtc) {
7548                         tmp_crtc = encoder->base.crtc;
7549
7550                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7551                 }
7552
7553                 if (encoder->new_crtc)
7554                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7555         }
7556
7557         /* Check for any pipes that will be fully disabled ... */
7558         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7559                             base.head) {
7560                 bool used = false;
7561
7562                 /* Don't try to disable disabled crtcs. */
7563                 if (!intel_crtc->base.enabled)
7564                         continue;
7565
7566                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7567                                     base.head) {
7568                         if (encoder->new_crtc == intel_crtc)
7569                                 used = true;
7570                 }
7571
7572                 if (!used)
7573                         *disable_pipes |= 1 << intel_crtc->pipe;
7574         }
7575
7576
7577         /* set_mode is also used to update properties on life display pipes. */
7578         intel_crtc = to_intel_crtc(crtc);
7579         if (crtc->enabled)
7580                 *prepare_pipes |= 1 << intel_crtc->pipe;
7581
7582         /* We only support modeset on one single crtc, hence we need to do that
7583          * only for the passed in crtc iff we change anything else than just
7584          * disable crtcs.
7585          *
7586          * This is actually not true, to be fully compatible with the old crtc
7587          * helper we automatically disable _any_ output (i.e. doesn't need to be
7588          * connected to the crtc we're modesetting on) if it's disconnected.
7589          * Which is a rather nutty api (since changed the output configuration
7590          * without userspace's explicit request can lead to confusion), but
7591          * alas. Hence we currently need to modeset on all pipes we prepare. */
7592         if (*prepare_pipes)
7593                 *modeset_pipes = *prepare_pipes;
7594
7595         /* ... and mask these out. */
7596         *modeset_pipes &= ~(*disable_pipes);
7597         *prepare_pipes &= ~(*disable_pipes);
7598 }
7599
7600 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7601 {
7602         struct drm_encoder *encoder;
7603         struct drm_device *dev = crtc->dev;
7604
7605         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7606                 if (encoder->crtc == crtc)
7607                         return true;
7608
7609         return false;
7610 }
7611
7612 static void
7613 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7614 {
7615         struct intel_encoder *intel_encoder;
7616         struct intel_crtc *intel_crtc;
7617         struct drm_connector *connector;
7618
7619         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7620                             base.head) {
7621                 if (!intel_encoder->base.crtc)
7622                         continue;
7623
7624                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7625
7626                 if (prepare_pipes & (1 << intel_crtc->pipe))
7627                         intel_encoder->connectors_active = false;
7628         }
7629
7630         intel_modeset_commit_output_state(dev);
7631
7632         /* Update computed state. */
7633         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7634                             base.head) {
7635                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7636         }
7637
7638         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7639                 if (!connector->encoder || !connector->encoder->crtc)
7640                         continue;
7641
7642                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7643
7644                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7645                         struct drm_property *dpms_property =
7646                                 dev->mode_config.dpms_property;
7647
7648                         connector->dpms = DRM_MODE_DPMS_ON;
7649                         drm_object_property_set_value(&connector->base,
7650                                                          dpms_property,
7651                                                          DRM_MODE_DPMS_ON);
7652
7653                         intel_encoder = to_intel_encoder(connector->encoder);
7654                         intel_encoder->connectors_active = true;
7655                 }
7656         }
7657
7658 }
7659
7660 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7661         list_for_each_entry((intel_crtc), \
7662                             &(dev)->mode_config.crtc_list, \
7663                             base.head) \
7664                 if (mask & (1 <<(intel_crtc)->pipe)) \
7665
7666 void
7667 intel_modeset_check_state(struct drm_device *dev)
7668 {
7669         struct intel_crtc *crtc;
7670         struct intel_encoder *encoder;
7671         struct intel_connector *connector;
7672
7673         list_for_each_entry(connector, &dev->mode_config.connector_list,
7674                             base.head) {
7675                 /* This also checks the encoder/connector hw state with the
7676                  * ->get_hw_state callbacks. */
7677                 intel_connector_check_state(connector);
7678
7679                 WARN(&connector->new_encoder->base != connector->base.encoder,
7680                      "connector's staged encoder doesn't match current encoder\n");
7681         }
7682
7683         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7684                             base.head) {
7685                 bool enabled = false;
7686                 bool active = false;
7687                 enum pipe pipe, tracked_pipe;
7688
7689                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7690                               encoder->base.base.id,
7691                               drm_get_encoder_name(&encoder->base));
7692
7693                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7694                      "encoder's stage crtc doesn't match current crtc\n");
7695                 WARN(encoder->connectors_active && !encoder->base.crtc,
7696                      "encoder's active_connectors set, but no crtc\n");
7697
7698                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7699                                     base.head) {
7700                         if (connector->base.encoder != &encoder->base)
7701                                 continue;
7702                         enabled = true;
7703                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7704                                 active = true;
7705                 }
7706                 WARN(!!encoder->base.crtc != enabled,
7707                      "encoder's enabled state mismatch "
7708                      "(expected %i, found %i)\n",
7709                      !!encoder->base.crtc, enabled);
7710                 WARN(active && !encoder->base.crtc,
7711                      "active encoder with no crtc\n");
7712
7713                 WARN(encoder->connectors_active != active,
7714                      "encoder's computed active state doesn't match tracked active state "
7715                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7716
7717                 active = encoder->get_hw_state(encoder, &pipe);
7718                 WARN(active != encoder->connectors_active,
7719                      "encoder's hw state doesn't match sw tracking "
7720                      "(expected %i, found %i)\n",
7721                      encoder->connectors_active, active);
7722
7723                 if (!encoder->base.crtc)
7724                         continue;
7725
7726                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7727                 WARN(active && pipe != tracked_pipe,
7728                      "active encoder's pipe doesn't match"
7729                      "(expected %i, found %i)\n",
7730                      tracked_pipe, pipe);
7731
7732         }
7733
7734         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7735                             base.head) {
7736                 bool enabled = false;
7737                 bool active = false;
7738
7739                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7740                               crtc->base.base.id);
7741
7742                 WARN(crtc->active && !crtc->base.enabled,
7743                      "active crtc, but not enabled in sw tracking\n");
7744
7745                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7746                                     base.head) {
7747                         if (encoder->base.crtc != &crtc->base)
7748                                 continue;
7749                         enabled = true;
7750                         if (encoder->connectors_active)
7751                                 active = true;
7752                 }
7753                 WARN(active != crtc->active,
7754                      "crtc's computed active state doesn't match tracked active state "
7755                      "(expected %i, found %i)\n", active, crtc->active);
7756                 WARN(enabled != crtc->base.enabled,
7757                      "crtc's computed enabled state doesn't match tracked enabled state "
7758                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7759
7760                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7761         }
7762 }
7763
7764 int intel_set_mode(struct drm_crtc *crtc,
7765                    struct drm_display_mode *mode,
7766                    int x, int y, struct drm_framebuffer *fb)
7767 {
7768         struct drm_device *dev = crtc->dev;
7769         drm_i915_private_t *dev_priv = dev->dev_private;
7770         struct drm_display_mode *saved_mode, *saved_hwmode;
7771         struct intel_crtc_config *pipe_config = NULL;
7772         struct intel_crtc *intel_crtc;
7773         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7774         int ret = 0;
7775
7776         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7777         if (!saved_mode)
7778                 return -ENOMEM;
7779         saved_hwmode = saved_mode + 1;
7780
7781         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7782                                      &prepare_pipes, &disable_pipes);
7783
7784         *saved_hwmode = crtc->hwmode;
7785         *saved_mode = crtc->mode;
7786
7787         /* Hack: Because we don't (yet) support global modeset on multiple
7788          * crtcs, we don't keep track of the new mode for more than one crtc.
7789          * Hence simply check whether any bit is set in modeset_pipes in all the
7790          * pieces of code that are not yet converted to deal with mutliple crtcs
7791          * changing their mode at the same time. */
7792         if (modeset_pipes) {
7793                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
7794                 if (IS_ERR(pipe_config)) {
7795                         ret = PTR_ERR(pipe_config);
7796                         pipe_config = NULL;
7797
7798                         goto out;
7799                 }
7800         }
7801
7802         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7803                       modeset_pipes, prepare_pipes, disable_pipes);
7804
7805         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7806                 intel_crtc_disable(&intel_crtc->base);
7807
7808         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7809                 if (intel_crtc->base.enabled)
7810                         dev_priv->display.crtc_disable(&intel_crtc->base);
7811         }
7812
7813         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7814          * to set it here already despite that we pass it down the callchain.
7815          */
7816         if (modeset_pipes) {
7817                 crtc->mode = *mode;
7818                 /* mode_set/enable/disable functions rely on a correct pipe
7819                  * config. */
7820                 to_intel_crtc(crtc)->config = *pipe_config;
7821         }
7822
7823         /* Only after disabling all output pipelines that will be changed can we
7824          * update the the output configuration. */
7825         intel_modeset_update_state(dev, prepare_pipes);
7826
7827         if (dev_priv->display.modeset_global_resources)
7828                 dev_priv->display.modeset_global_resources(dev);
7829
7830         /* Set up the DPLL and any encoders state that needs to adjust or depend
7831          * on the DPLL.
7832          */
7833         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7834                 ret = intel_crtc_mode_set(&intel_crtc->base,
7835                                           x, y, fb);
7836                 if (ret)
7837                         goto done;
7838         }
7839
7840         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7841         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7842                 dev_priv->display.crtc_enable(&intel_crtc->base);
7843
7844         if (modeset_pipes) {
7845                 /* Store real post-adjustment hardware mode. */
7846                 crtc->hwmode = pipe_config->adjusted_mode;
7847
7848                 /* Calculate and store various constants which
7849                  * are later needed by vblank and swap-completion
7850                  * timestamping. They are derived from true hwmode.
7851                  */
7852                 drm_calc_timestamping_constants(crtc);
7853         }
7854
7855         /* FIXME: add subpixel order */
7856 done:
7857         if (ret && crtc->enabled) {
7858                 crtc->hwmode = *saved_hwmode;
7859                 crtc->mode = *saved_mode;
7860         } else {
7861                 intel_modeset_check_state(dev);
7862         }
7863
7864 out:
7865         kfree(pipe_config);
7866         kfree(saved_mode);
7867         return ret;
7868 }
7869
7870 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7871 {
7872         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7873 }
7874
7875 #undef for_each_intel_crtc_masked
7876
7877 static void intel_set_config_free(struct intel_set_config *config)
7878 {
7879         if (!config)
7880                 return;
7881
7882         kfree(config->save_connector_encoders);
7883         kfree(config->save_encoder_crtcs);
7884         kfree(config);
7885 }
7886
7887 static int intel_set_config_save_state(struct drm_device *dev,
7888                                        struct intel_set_config *config)
7889 {
7890         struct drm_encoder *encoder;
7891         struct drm_connector *connector;
7892         int count;
7893
7894         config->save_encoder_crtcs =
7895                 kcalloc(dev->mode_config.num_encoder,
7896                         sizeof(struct drm_crtc *), GFP_KERNEL);
7897         if (!config->save_encoder_crtcs)
7898                 return -ENOMEM;
7899
7900         config->save_connector_encoders =
7901                 kcalloc(dev->mode_config.num_connector,
7902                         sizeof(struct drm_encoder *), GFP_KERNEL);
7903         if (!config->save_connector_encoders)
7904                 return -ENOMEM;
7905
7906         /* Copy data. Note that driver private data is not affected.
7907          * Should anything bad happen only the expected state is
7908          * restored, not the drivers personal bookkeeping.
7909          */
7910         count = 0;
7911         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7912                 config->save_encoder_crtcs[count++] = encoder->crtc;
7913         }
7914
7915         count = 0;
7916         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7917                 config->save_connector_encoders[count++] = connector->encoder;
7918         }
7919
7920         return 0;
7921 }
7922
7923 static void intel_set_config_restore_state(struct drm_device *dev,
7924                                            struct intel_set_config *config)
7925 {
7926         struct intel_encoder *encoder;
7927         struct intel_connector *connector;
7928         int count;
7929
7930         count = 0;
7931         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7932                 encoder->new_crtc =
7933                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7934         }
7935
7936         count = 0;
7937         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7938                 connector->new_encoder =
7939                         to_intel_encoder(config->save_connector_encoders[count++]);
7940         }
7941 }
7942
7943 static void
7944 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7945                                       struct intel_set_config *config)
7946 {
7947
7948         /* We should be able to check here if the fb has the same properties
7949          * and then just flip_or_move it */
7950         if (set->crtc->fb != set->fb) {
7951                 /* If we have no fb then treat it as a full mode set */
7952                 if (set->crtc->fb == NULL) {
7953                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7954                         config->mode_changed = true;
7955                 } else if (set->fb == NULL) {
7956                         config->mode_changed = true;
7957                 } else if (set->fb->pixel_format !=
7958                            set->crtc->fb->pixel_format) {
7959                         config->mode_changed = true;
7960                 } else
7961                         config->fb_changed = true;
7962         }
7963
7964         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7965                 config->fb_changed = true;
7966
7967         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7968                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7969                 drm_mode_debug_printmodeline(&set->crtc->mode);
7970                 drm_mode_debug_printmodeline(set->mode);
7971                 config->mode_changed = true;
7972         }
7973 }
7974
7975 static int
7976 intel_modeset_stage_output_state(struct drm_device *dev,
7977                                  struct drm_mode_set *set,
7978                                  struct intel_set_config *config)
7979 {
7980         struct drm_crtc *new_crtc;
7981         struct intel_connector *connector;
7982         struct intel_encoder *encoder;
7983         int count, ro;
7984
7985         /* The upper layers ensure that we either disable a crtc or have a list
7986          * of connectors. For paranoia, double-check this. */
7987         WARN_ON(!set->fb && (set->num_connectors != 0));
7988         WARN_ON(set->fb && (set->num_connectors == 0));
7989
7990         count = 0;
7991         list_for_each_entry(connector, &dev->mode_config.connector_list,
7992                             base.head) {
7993                 /* Otherwise traverse passed in connector list and get encoders
7994                  * for them. */
7995                 for (ro = 0; ro < set->num_connectors; ro++) {
7996                         if (set->connectors[ro] == &connector->base) {
7997                                 connector->new_encoder = connector->encoder;
7998                                 break;
7999                         }
8000                 }
8001
8002                 /* If we disable the crtc, disable all its connectors. Also, if
8003                  * the connector is on the changing crtc but not on the new
8004                  * connector list, disable it. */
8005                 if ((!set->fb || ro == set->num_connectors) &&
8006                     connector->base.encoder &&
8007                     connector->base.encoder->crtc == set->crtc) {
8008                         connector->new_encoder = NULL;
8009
8010                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8011                                 connector->base.base.id,
8012                                 drm_get_connector_name(&connector->base));
8013                 }
8014
8015
8016                 if (&connector->new_encoder->base != connector->base.encoder) {
8017                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8018                         config->mode_changed = true;
8019                 }
8020         }
8021         /* connector->new_encoder is now updated for all connectors. */
8022
8023         /* Update crtc of enabled connectors. */
8024         count = 0;
8025         list_for_each_entry(connector, &dev->mode_config.connector_list,
8026                             base.head) {
8027                 if (!connector->new_encoder)
8028                         continue;
8029
8030                 new_crtc = connector->new_encoder->base.crtc;
8031
8032                 for (ro = 0; ro < set->num_connectors; ro++) {
8033                         if (set->connectors[ro] == &connector->base)
8034                                 new_crtc = set->crtc;
8035                 }
8036
8037                 /* Make sure the new CRTC will work with the encoder */
8038                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8039                                            new_crtc)) {
8040                         return -EINVAL;
8041                 }
8042                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8043
8044                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8045                         connector->base.base.id,
8046                         drm_get_connector_name(&connector->base),
8047                         new_crtc->base.id);
8048         }
8049
8050         /* Check for any encoders that needs to be disabled. */
8051         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8052                             base.head) {
8053                 list_for_each_entry(connector,
8054                                     &dev->mode_config.connector_list,
8055                                     base.head) {
8056                         if (connector->new_encoder == encoder) {
8057                                 WARN_ON(!connector->new_encoder->new_crtc);
8058
8059                                 goto next_encoder;
8060                         }
8061                 }
8062                 encoder->new_crtc = NULL;
8063 next_encoder:
8064                 /* Only now check for crtc changes so we don't miss encoders
8065                  * that will be disabled. */
8066                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8067                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8068                         config->mode_changed = true;
8069                 }
8070         }
8071         /* Now we've also updated encoder->new_crtc for all encoders. */
8072
8073         return 0;
8074 }
8075
8076 static int intel_crtc_set_config(struct drm_mode_set *set)
8077 {
8078         struct drm_device *dev;
8079         struct drm_mode_set save_set;
8080         struct intel_set_config *config;
8081         int ret;
8082
8083         BUG_ON(!set);
8084         BUG_ON(!set->crtc);
8085         BUG_ON(!set->crtc->helper_private);
8086
8087         /* Enforce sane interface api - has been abused by the fb helper. */
8088         BUG_ON(!set->mode && set->fb);
8089         BUG_ON(set->fb && set->num_connectors == 0);
8090
8091         if (set->fb) {
8092                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8093                                 set->crtc->base.id, set->fb->base.id,
8094                                 (int)set->num_connectors, set->x, set->y);
8095         } else {
8096                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8097         }
8098
8099         dev = set->crtc->dev;
8100
8101         ret = -ENOMEM;
8102         config = kzalloc(sizeof(*config), GFP_KERNEL);
8103         if (!config)
8104                 goto out_config;
8105
8106         ret = intel_set_config_save_state(dev, config);
8107         if (ret)
8108                 goto out_config;
8109
8110         save_set.crtc = set->crtc;
8111         save_set.mode = &set->crtc->mode;
8112         save_set.x = set->crtc->x;
8113         save_set.y = set->crtc->y;
8114         save_set.fb = set->crtc->fb;
8115
8116         /* Compute whether we need a full modeset, only an fb base update or no
8117          * change at all. In the future we might also check whether only the
8118          * mode changed, e.g. for LVDS where we only change the panel fitter in
8119          * such cases. */
8120         intel_set_config_compute_mode_changes(set, config);
8121
8122         ret = intel_modeset_stage_output_state(dev, set, config);
8123         if (ret)
8124                 goto fail;
8125
8126         if (config->mode_changed) {
8127                 if (set->mode) {
8128                         DRM_DEBUG_KMS("attempting to set mode from"
8129                                         " userspace\n");
8130                         drm_mode_debug_printmodeline(set->mode);
8131                 }
8132
8133                 ret = intel_set_mode(set->crtc, set->mode,
8134                                      set->x, set->y, set->fb);
8135                 if (ret) {
8136                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8137                                   set->crtc->base.id, ret);
8138                         goto fail;
8139                 }
8140         } else if (config->fb_changed) {
8141                 intel_crtc_wait_for_pending_flips(set->crtc);
8142
8143                 ret = intel_pipe_set_base(set->crtc,
8144                                           set->x, set->y, set->fb);
8145         }
8146
8147         intel_set_config_free(config);
8148
8149         return 0;
8150
8151 fail:
8152         intel_set_config_restore_state(dev, config);
8153
8154         /* Try to restore the config */
8155         if (config->mode_changed &&
8156             intel_set_mode(save_set.crtc, save_set.mode,
8157                            save_set.x, save_set.y, save_set.fb))
8158                 DRM_ERROR("failed to restore config after modeset failure\n");
8159
8160 out_config:
8161         intel_set_config_free(config);
8162         return ret;
8163 }
8164
8165 static const struct drm_crtc_funcs intel_crtc_funcs = {
8166         .cursor_set = intel_crtc_cursor_set,
8167         .cursor_move = intel_crtc_cursor_move,
8168         .gamma_set = intel_crtc_gamma_set,
8169         .set_config = intel_crtc_set_config,
8170         .destroy = intel_crtc_destroy,
8171         .page_flip = intel_crtc_page_flip,
8172 };
8173
8174 static void intel_cpu_pll_init(struct drm_device *dev)
8175 {
8176         if (HAS_DDI(dev))
8177                 intel_ddi_pll_init(dev);
8178 }
8179
8180 static void intel_pch_pll_init(struct drm_device *dev)
8181 {
8182         drm_i915_private_t *dev_priv = dev->dev_private;
8183         int i;
8184
8185         if (dev_priv->num_pch_pll == 0) {
8186                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8187                 return;
8188         }
8189
8190         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8191                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8192                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8193                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8194         }
8195 }
8196
8197 static void intel_crtc_init(struct drm_device *dev, int pipe)
8198 {
8199         drm_i915_private_t *dev_priv = dev->dev_private;
8200         struct intel_crtc *intel_crtc;
8201         int i;
8202
8203         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8204         if (intel_crtc == NULL)
8205                 return;
8206
8207         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8208
8209         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8210         for (i = 0; i < 256; i++) {
8211                 intel_crtc->lut_r[i] = i;
8212                 intel_crtc->lut_g[i] = i;
8213                 intel_crtc->lut_b[i] = i;
8214         }
8215
8216         /* Swap pipes & planes for FBC on pre-965 */
8217         intel_crtc->pipe = pipe;
8218         intel_crtc->plane = pipe;
8219         intel_crtc->cpu_transcoder = pipe;
8220         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8221                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8222                 intel_crtc->plane = !pipe;
8223         }
8224
8225         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8226                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8227         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8228         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8229
8230         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8231 }
8232
8233 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8234                                 struct drm_file *file)
8235 {
8236         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8237         struct drm_mode_object *drmmode_obj;
8238         struct intel_crtc *crtc;
8239
8240         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8241                 return -ENODEV;
8242
8243         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8244                         DRM_MODE_OBJECT_CRTC);
8245
8246         if (!drmmode_obj) {
8247                 DRM_ERROR("no such CRTC id\n");
8248                 return -EINVAL;
8249         }
8250
8251         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8252         pipe_from_crtc_id->pipe = crtc->pipe;
8253
8254         return 0;
8255 }
8256
8257 static int intel_encoder_clones(struct intel_encoder *encoder)
8258 {
8259         struct drm_device *dev = encoder->base.dev;
8260         struct intel_encoder *source_encoder;
8261         int index_mask = 0;
8262         int entry = 0;
8263
8264         list_for_each_entry(source_encoder,
8265                             &dev->mode_config.encoder_list, base.head) {
8266
8267                 if (encoder == source_encoder)
8268                         index_mask |= (1 << entry);
8269
8270                 /* Intel hw has only one MUX where enocoders could be cloned. */
8271                 if (encoder->cloneable && source_encoder->cloneable)
8272                         index_mask |= (1 << entry);
8273
8274                 entry++;
8275         }
8276
8277         return index_mask;
8278 }
8279
8280 static bool has_edp_a(struct drm_device *dev)
8281 {
8282         struct drm_i915_private *dev_priv = dev->dev_private;
8283
8284         if (!IS_MOBILE(dev))
8285                 return false;
8286
8287         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8288                 return false;
8289
8290         if (IS_GEN5(dev) &&
8291             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8292                 return false;
8293
8294         return true;
8295 }
8296
8297 static void intel_setup_outputs(struct drm_device *dev)
8298 {
8299         struct drm_i915_private *dev_priv = dev->dev_private;
8300         struct intel_encoder *encoder;
8301         bool dpd_is_edp = false;
8302         bool has_lvds;
8303
8304         has_lvds = intel_lvds_init(dev);
8305         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8306                 /* disable the panel fitter on everything but LVDS */
8307                 I915_WRITE(PFIT_CONTROL, 0);
8308         }
8309
8310         if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8311                 intel_crt_init(dev);
8312
8313         if (HAS_DDI(dev)) {
8314                 int found;
8315
8316                 /* Haswell uses DDI functions to detect digital outputs */
8317                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8318                 /* DDI A only supports eDP */
8319                 if (found)
8320                         intel_ddi_init(dev, PORT_A);
8321
8322                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8323                  * register */
8324                 found = I915_READ(SFUSE_STRAP);
8325
8326                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8327                         intel_ddi_init(dev, PORT_B);
8328                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8329                         intel_ddi_init(dev, PORT_C);
8330                 if (found & SFUSE_STRAP_DDID_DETECTED)
8331                         intel_ddi_init(dev, PORT_D);
8332         } else if (HAS_PCH_SPLIT(dev)) {
8333                 int found;
8334                 dpd_is_edp = intel_dpd_is_edp(dev);
8335
8336                 if (has_edp_a(dev))
8337                         intel_dp_init(dev, DP_A, PORT_A);
8338
8339                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8340                         /* PCH SDVOB multiplex with HDMIB */
8341                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8342                         if (!found)
8343                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8344                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8345                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8346                 }
8347
8348                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8349                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8350
8351                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8352                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8353
8354                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8355                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8356
8357                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8358                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8359         } else if (IS_VALLEYVIEW(dev)) {
8360                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8361                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8362                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8363
8364                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8365                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8366                                         PORT_B);
8367                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8368                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8369                 }
8370         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8371                 bool found = false;
8372
8373                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8374                         DRM_DEBUG_KMS("probing SDVOB\n");
8375                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8376                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8377                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8378                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8379                         }
8380
8381                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8382                                 DRM_DEBUG_KMS("probing DP_B\n");
8383                                 intel_dp_init(dev, DP_B, PORT_B);
8384                         }
8385                 }
8386
8387                 /* Before G4X SDVOC doesn't have its own detect register */
8388
8389                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8390                         DRM_DEBUG_KMS("probing SDVOC\n");
8391                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8392                 }
8393
8394                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8395
8396                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8397                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8398                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8399                         }
8400                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8401                                 DRM_DEBUG_KMS("probing DP_C\n");
8402                                 intel_dp_init(dev, DP_C, PORT_C);
8403                         }
8404                 }
8405
8406                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8407                     (I915_READ(DP_D) & DP_DETECTED)) {
8408                         DRM_DEBUG_KMS("probing DP_D\n");
8409                         intel_dp_init(dev, DP_D, PORT_D);
8410                 }
8411         } else if (IS_GEN2(dev))
8412                 intel_dvo_init(dev);
8413
8414         if (SUPPORTS_TV(dev))
8415                 intel_tv_init(dev);
8416
8417         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8418                 encoder->base.possible_crtcs = encoder->crtc_mask;
8419                 encoder->base.possible_clones =
8420                         intel_encoder_clones(encoder);
8421         }
8422
8423         intel_init_pch_refclk(dev);
8424
8425         drm_helper_move_panel_connectors_to_head(dev);
8426 }
8427
8428 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8429 {
8430         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8431
8432         drm_framebuffer_cleanup(fb);
8433         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8434
8435         kfree(intel_fb);
8436 }
8437
8438 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8439                                                 struct drm_file *file,
8440                                                 unsigned int *handle)
8441 {
8442         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8443         struct drm_i915_gem_object *obj = intel_fb->obj;
8444
8445         return drm_gem_handle_create(file, &obj->base, handle);
8446 }
8447
8448 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8449         .destroy = intel_user_framebuffer_destroy,
8450         .create_handle = intel_user_framebuffer_create_handle,
8451 };
8452
8453 int intel_framebuffer_init(struct drm_device *dev,
8454                            struct intel_framebuffer *intel_fb,
8455                            struct drm_mode_fb_cmd2 *mode_cmd,
8456                            struct drm_i915_gem_object *obj)
8457 {
8458         int ret;
8459
8460         if (obj->tiling_mode == I915_TILING_Y) {
8461                 DRM_DEBUG("hardware does not support tiling Y\n");
8462                 return -EINVAL;
8463         }
8464
8465         if (mode_cmd->pitches[0] & 63) {
8466                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8467                           mode_cmd->pitches[0]);
8468                 return -EINVAL;
8469         }
8470
8471         /* FIXME <= Gen4 stride limits are bit unclear */
8472         if (mode_cmd->pitches[0] > 32768) {
8473                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8474                           mode_cmd->pitches[0]);
8475                 return -EINVAL;
8476         }
8477
8478         if (obj->tiling_mode != I915_TILING_NONE &&
8479             mode_cmd->pitches[0] != obj->stride) {
8480                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8481                           mode_cmd->pitches[0], obj->stride);
8482                 return -EINVAL;
8483         }
8484
8485         /* Reject formats not supported by any plane early. */
8486         switch (mode_cmd->pixel_format) {
8487         case DRM_FORMAT_C8:
8488         case DRM_FORMAT_RGB565:
8489         case DRM_FORMAT_XRGB8888:
8490         case DRM_FORMAT_ARGB8888:
8491                 break;
8492         case DRM_FORMAT_XRGB1555:
8493         case DRM_FORMAT_ARGB1555:
8494                 if (INTEL_INFO(dev)->gen > 3) {
8495                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8496                         return -EINVAL;
8497                 }
8498                 break;
8499         case DRM_FORMAT_XBGR8888:
8500         case DRM_FORMAT_ABGR8888:
8501         case DRM_FORMAT_XRGB2101010:
8502         case DRM_FORMAT_ARGB2101010:
8503         case DRM_FORMAT_XBGR2101010:
8504         case DRM_FORMAT_ABGR2101010:
8505                 if (INTEL_INFO(dev)->gen < 4) {
8506                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8507                         return -EINVAL;
8508                 }
8509                 break;
8510         case DRM_FORMAT_YUYV:
8511         case DRM_FORMAT_UYVY:
8512         case DRM_FORMAT_YVYU:
8513         case DRM_FORMAT_VYUY:
8514                 if (INTEL_INFO(dev)->gen < 5) {
8515                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8516                         return -EINVAL;
8517                 }
8518                 break;
8519         default:
8520                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8521                 return -EINVAL;
8522         }
8523
8524         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8525         if (mode_cmd->offsets[0] != 0)
8526                 return -EINVAL;
8527
8528         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8529         intel_fb->obj = obj;
8530
8531         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8532         if (ret) {
8533                 DRM_ERROR("framebuffer init failed %d\n", ret);
8534                 return ret;
8535         }
8536
8537         return 0;
8538 }
8539
8540 static struct drm_framebuffer *
8541 intel_user_framebuffer_create(struct drm_device *dev,
8542                               struct drm_file *filp,
8543                               struct drm_mode_fb_cmd2 *mode_cmd)
8544 {
8545         struct drm_i915_gem_object *obj;
8546
8547         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8548                                                 mode_cmd->handles[0]));
8549         if (&obj->base == NULL)
8550                 return ERR_PTR(-ENOENT);
8551
8552         return intel_framebuffer_create(dev, mode_cmd, obj);
8553 }
8554
8555 static const struct drm_mode_config_funcs intel_mode_funcs = {
8556         .fb_create = intel_user_framebuffer_create,
8557         .output_poll_changed = intel_fb_output_poll_changed,
8558 };
8559
8560 /* Set up chip specific display functions */
8561 static void intel_init_display(struct drm_device *dev)
8562 {
8563         struct drm_i915_private *dev_priv = dev->dev_private;
8564
8565         if (HAS_DDI(dev)) {
8566                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8567                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8568                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8569                 dev_priv->display.off = haswell_crtc_off;
8570                 dev_priv->display.update_plane = ironlake_update_plane;
8571         } else if (HAS_PCH_SPLIT(dev)) {
8572                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8573                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8574                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8575                 dev_priv->display.off = ironlake_crtc_off;
8576                 dev_priv->display.update_plane = ironlake_update_plane;
8577         } else {
8578                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8579                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8580                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8581                 dev_priv->display.off = i9xx_crtc_off;
8582                 dev_priv->display.update_plane = i9xx_update_plane;
8583         }
8584
8585         /* Returns the core display clock speed */
8586         if (IS_VALLEYVIEW(dev))
8587                 dev_priv->display.get_display_clock_speed =
8588                         valleyview_get_display_clock_speed;
8589         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8590                 dev_priv->display.get_display_clock_speed =
8591                         i945_get_display_clock_speed;
8592         else if (IS_I915G(dev))
8593                 dev_priv->display.get_display_clock_speed =
8594                         i915_get_display_clock_speed;
8595         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8596                 dev_priv->display.get_display_clock_speed =
8597                         i9xx_misc_get_display_clock_speed;
8598         else if (IS_I915GM(dev))
8599                 dev_priv->display.get_display_clock_speed =
8600                         i915gm_get_display_clock_speed;
8601         else if (IS_I865G(dev))
8602                 dev_priv->display.get_display_clock_speed =
8603                         i865_get_display_clock_speed;
8604         else if (IS_I85X(dev))
8605                 dev_priv->display.get_display_clock_speed =
8606                         i855_get_display_clock_speed;
8607         else /* 852, 830 */
8608                 dev_priv->display.get_display_clock_speed =
8609                         i830_get_display_clock_speed;
8610
8611         if (HAS_PCH_SPLIT(dev)) {
8612                 if (IS_GEN5(dev)) {
8613                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8614                         dev_priv->display.write_eld = ironlake_write_eld;
8615                 } else if (IS_GEN6(dev)) {
8616                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8617                         dev_priv->display.write_eld = ironlake_write_eld;
8618                 } else if (IS_IVYBRIDGE(dev)) {
8619                         /* FIXME: detect B0+ stepping and use auto training */
8620                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8621                         dev_priv->display.write_eld = ironlake_write_eld;
8622                         dev_priv->display.modeset_global_resources =
8623                                 ivb_modeset_global_resources;
8624                 } else if (IS_HASWELL(dev)) {
8625                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8626                         dev_priv->display.write_eld = haswell_write_eld;
8627                         dev_priv->display.modeset_global_resources =
8628                                 haswell_modeset_global_resources;
8629                 }
8630         } else if (IS_G4X(dev)) {
8631                 dev_priv->display.write_eld = g4x_write_eld;
8632         }
8633
8634         /* Default just returns -ENODEV to indicate unsupported */
8635         dev_priv->display.queue_flip = intel_default_queue_flip;
8636
8637         switch (INTEL_INFO(dev)->gen) {
8638         case 2:
8639                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8640                 break;
8641
8642         case 3:
8643                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8644                 break;
8645
8646         case 4:
8647         case 5:
8648                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8649                 break;
8650
8651         case 6:
8652                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8653                 break;
8654         case 7:
8655                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8656                 break;
8657         }
8658 }
8659
8660 /*
8661  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8662  * resume, or other times.  This quirk makes sure that's the case for
8663  * affected systems.
8664  */
8665 static void quirk_pipea_force(struct drm_device *dev)
8666 {
8667         struct drm_i915_private *dev_priv = dev->dev_private;
8668
8669         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8670         DRM_INFO("applying pipe a force quirk\n");
8671 }
8672
8673 /*
8674  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8675  */
8676 static void quirk_ssc_force_disable(struct drm_device *dev)
8677 {
8678         struct drm_i915_private *dev_priv = dev->dev_private;
8679         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8680         DRM_INFO("applying lvds SSC disable quirk\n");
8681 }
8682
8683 /*
8684  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8685  * brightness value
8686  */
8687 static void quirk_invert_brightness(struct drm_device *dev)
8688 {
8689         struct drm_i915_private *dev_priv = dev->dev_private;
8690         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8691         DRM_INFO("applying inverted panel brightness quirk\n");
8692 }
8693
8694 struct intel_quirk {
8695         int device;
8696         int subsystem_vendor;
8697         int subsystem_device;
8698         void (*hook)(struct drm_device *dev);
8699 };
8700
8701 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8702 struct intel_dmi_quirk {
8703         void (*hook)(struct drm_device *dev);
8704         const struct dmi_system_id (*dmi_id_list)[];
8705 };
8706
8707 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8708 {
8709         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8710         return 1;
8711 }
8712
8713 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8714         {
8715                 .dmi_id_list = &(const struct dmi_system_id[]) {
8716                         {
8717                                 .callback = intel_dmi_reverse_brightness,
8718                                 .ident = "NCR Corporation",
8719                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8720                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8721                                 },
8722                         },
8723                         { }  /* terminating entry */
8724                 },
8725                 .hook = quirk_invert_brightness,
8726         },
8727 };
8728
8729 static struct intel_quirk intel_quirks[] = {
8730         /* HP Mini needs pipe A force quirk (LP: #322104) */
8731         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8732
8733         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8734         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8735
8736         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8737         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8738
8739         /* 830/845 need to leave pipe A & dpll A up */
8740         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8741         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8742
8743         /* Lenovo U160 cannot use SSC on LVDS */
8744         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8745
8746         /* Sony Vaio Y cannot use SSC on LVDS */
8747         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8748
8749         /* Acer Aspire 5734Z must invert backlight brightness */
8750         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8751
8752         /* Acer/eMachines G725 */
8753         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8754
8755         /* Acer/eMachines e725 */
8756         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8757
8758         /* Acer/Packard Bell NCL20 */
8759         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8760
8761         /* Acer Aspire 4736Z */
8762         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8763 };
8764
8765 static void intel_init_quirks(struct drm_device *dev)
8766 {
8767         struct pci_dev *d = dev->pdev;
8768         int i;
8769
8770         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8771                 struct intel_quirk *q = &intel_quirks[i];
8772
8773                 if (d->device == q->device &&
8774                     (d->subsystem_vendor == q->subsystem_vendor ||
8775                      q->subsystem_vendor == PCI_ANY_ID) &&
8776                     (d->subsystem_device == q->subsystem_device ||
8777                      q->subsystem_device == PCI_ANY_ID))
8778                         q->hook(dev);
8779         }
8780         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8781                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8782                         intel_dmi_quirks[i].hook(dev);
8783         }
8784 }
8785
8786 /* Disable the VGA plane that we never use */
8787 static void i915_disable_vga(struct drm_device *dev)
8788 {
8789         struct drm_i915_private *dev_priv = dev->dev_private;
8790         u8 sr1;
8791         u32 vga_reg = i915_vgacntrl_reg(dev);
8792
8793         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8794         outb(SR01, VGA_SR_INDEX);
8795         sr1 = inb(VGA_SR_DATA);
8796         outb(sr1 | 1<<5, VGA_SR_DATA);
8797         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8798         udelay(300);
8799
8800         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8801         POSTING_READ(vga_reg);
8802 }
8803
8804 void intel_modeset_init_hw(struct drm_device *dev)
8805 {
8806         intel_init_power_well(dev);
8807
8808         intel_prepare_ddi(dev);
8809
8810         intel_init_clock_gating(dev);
8811
8812         mutex_lock(&dev->struct_mutex);
8813         intel_enable_gt_powersave(dev);
8814         mutex_unlock(&dev->struct_mutex);
8815 }
8816
8817 void intel_modeset_init(struct drm_device *dev)
8818 {
8819         struct drm_i915_private *dev_priv = dev->dev_private;
8820         int i, ret;
8821
8822         drm_mode_config_init(dev);
8823
8824         dev->mode_config.min_width = 0;
8825         dev->mode_config.min_height = 0;
8826
8827         dev->mode_config.preferred_depth = 24;
8828         dev->mode_config.prefer_shadow = 1;
8829
8830         dev->mode_config.funcs = &intel_mode_funcs;
8831
8832         intel_init_quirks(dev);
8833
8834         intel_init_pm(dev);
8835
8836         intel_init_display(dev);
8837
8838         if (IS_GEN2(dev)) {
8839                 dev->mode_config.max_width = 2048;
8840                 dev->mode_config.max_height = 2048;
8841         } else if (IS_GEN3(dev)) {
8842                 dev->mode_config.max_width = 4096;
8843                 dev->mode_config.max_height = 4096;
8844         } else {
8845                 dev->mode_config.max_width = 8192;
8846                 dev->mode_config.max_height = 8192;
8847         }
8848         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8849
8850         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8851                       INTEL_INFO(dev)->num_pipes,
8852                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
8853
8854         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
8855                 intel_crtc_init(dev, i);
8856                 ret = intel_plane_init(dev, i);
8857                 if (ret)
8858                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8859         }
8860
8861         intel_cpu_pll_init(dev);
8862         intel_pch_pll_init(dev);
8863
8864         /* Just disable it once at startup */
8865         i915_disable_vga(dev);
8866         intel_setup_outputs(dev);
8867
8868         /* Just in case the BIOS is doing something questionable. */
8869         intel_disable_fbc(dev);
8870 }
8871
8872 static void
8873 intel_connector_break_all_links(struct intel_connector *connector)
8874 {
8875         connector->base.dpms = DRM_MODE_DPMS_OFF;
8876         connector->base.encoder = NULL;
8877         connector->encoder->connectors_active = false;
8878         connector->encoder->base.crtc = NULL;
8879 }
8880
8881 static void intel_enable_pipe_a(struct drm_device *dev)
8882 {
8883         struct intel_connector *connector;
8884         struct drm_connector *crt = NULL;
8885         struct intel_load_detect_pipe load_detect_temp;
8886
8887         /* We can't just switch on the pipe A, we need to set things up with a
8888          * proper mode and output configuration. As a gross hack, enable pipe A
8889          * by enabling the load detect pipe once. */
8890         list_for_each_entry(connector,
8891                             &dev->mode_config.connector_list,
8892                             base.head) {
8893                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8894                         crt = &connector->base;
8895                         break;
8896                 }
8897         }
8898
8899         if (!crt)
8900                 return;
8901
8902         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8903                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8904
8905
8906 }
8907
8908 static bool
8909 intel_check_plane_mapping(struct intel_crtc *crtc)
8910 {
8911         struct drm_device *dev = crtc->base.dev;
8912         struct drm_i915_private *dev_priv = dev->dev_private;
8913         u32 reg, val;
8914
8915         if (INTEL_INFO(dev)->num_pipes == 1)
8916                 return true;
8917
8918         reg = DSPCNTR(!crtc->plane);
8919         val = I915_READ(reg);
8920
8921         if ((val & DISPLAY_PLANE_ENABLE) &&
8922             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8923                 return false;
8924
8925         return true;
8926 }
8927
8928 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8929 {
8930         struct drm_device *dev = crtc->base.dev;
8931         struct drm_i915_private *dev_priv = dev->dev_private;
8932         u32 reg;
8933
8934         /* Clear any frame start delays used for debugging left by the BIOS */
8935         reg = PIPECONF(crtc->cpu_transcoder);
8936         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8937
8938         /* We need to sanitize the plane -> pipe mapping first because this will
8939          * disable the crtc (and hence change the state) if it is wrong. Note
8940          * that gen4+ has a fixed plane -> pipe mapping.  */
8941         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8942                 struct intel_connector *connector;
8943                 bool plane;
8944
8945                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8946                               crtc->base.base.id);
8947
8948                 /* Pipe has the wrong plane attached and the plane is active.
8949                  * Temporarily change the plane mapping and disable everything
8950                  * ...  */
8951                 plane = crtc->plane;
8952                 crtc->plane = !plane;
8953                 dev_priv->display.crtc_disable(&crtc->base);
8954                 crtc->plane = plane;
8955
8956                 /* ... and break all links. */
8957                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8958                                     base.head) {
8959                         if (connector->encoder->base.crtc != &crtc->base)
8960                                 continue;
8961
8962                         intel_connector_break_all_links(connector);
8963                 }
8964
8965                 WARN_ON(crtc->active);
8966                 crtc->base.enabled = false;
8967         }
8968
8969         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8970             crtc->pipe == PIPE_A && !crtc->active) {
8971                 /* BIOS forgot to enable pipe A, this mostly happens after
8972                  * resume. Force-enable the pipe to fix this, the update_dpms
8973                  * call below we restore the pipe to the right state, but leave
8974                  * the required bits on. */
8975                 intel_enable_pipe_a(dev);
8976         }
8977
8978         /* Adjust the state of the output pipe according to whether we
8979          * have active connectors/encoders. */
8980         intel_crtc_update_dpms(&crtc->base);
8981
8982         if (crtc->active != crtc->base.enabled) {
8983                 struct intel_encoder *encoder;
8984
8985                 /* This can happen either due to bugs in the get_hw_state
8986                  * functions or because the pipe is force-enabled due to the
8987                  * pipe A quirk. */
8988                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8989                               crtc->base.base.id,
8990                               crtc->base.enabled ? "enabled" : "disabled",
8991                               crtc->active ? "enabled" : "disabled");
8992
8993                 crtc->base.enabled = crtc->active;
8994
8995                 /* Because we only establish the connector -> encoder ->
8996                  * crtc links if something is active, this means the
8997                  * crtc is now deactivated. Break the links. connector
8998                  * -> encoder links are only establish when things are
8999                  *  actually up, hence no need to break them. */
9000                 WARN_ON(crtc->active);
9001
9002                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9003                         WARN_ON(encoder->connectors_active);
9004                         encoder->base.crtc = NULL;
9005                 }
9006         }
9007 }
9008
9009 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9010 {
9011         struct intel_connector *connector;
9012         struct drm_device *dev = encoder->base.dev;
9013
9014         /* We need to check both for a crtc link (meaning that the
9015          * encoder is active and trying to read from a pipe) and the
9016          * pipe itself being active. */
9017         bool has_active_crtc = encoder->base.crtc &&
9018                 to_intel_crtc(encoder->base.crtc)->active;
9019
9020         if (encoder->connectors_active && !has_active_crtc) {
9021                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9022                               encoder->base.base.id,
9023                               drm_get_encoder_name(&encoder->base));
9024
9025                 /* Connector is active, but has no active pipe. This is
9026                  * fallout from our resume register restoring. Disable
9027                  * the encoder manually again. */
9028                 if (encoder->base.crtc) {
9029                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9030                                       encoder->base.base.id,
9031                                       drm_get_encoder_name(&encoder->base));
9032                         encoder->disable(encoder);
9033                 }
9034
9035                 /* Inconsistent output/port/pipe state happens presumably due to
9036                  * a bug in one of the get_hw_state functions. Or someplace else
9037                  * in our code, like the register restore mess on resume. Clamp
9038                  * things to off as a safer default. */
9039                 list_for_each_entry(connector,
9040                                     &dev->mode_config.connector_list,
9041                                     base.head) {
9042                         if (connector->encoder != encoder)
9043                                 continue;
9044
9045                         intel_connector_break_all_links(connector);
9046                 }
9047         }
9048         /* Enabled encoders without active connectors will be fixed in
9049          * the crtc fixup. */
9050 }
9051
9052 void i915_redisable_vga(struct drm_device *dev)
9053 {
9054         struct drm_i915_private *dev_priv = dev->dev_private;
9055         u32 vga_reg = i915_vgacntrl_reg(dev);
9056
9057         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9058                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9059                 i915_disable_vga(dev);
9060         }
9061 }
9062
9063 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9064  * and i915 state tracking structures. */
9065 void intel_modeset_setup_hw_state(struct drm_device *dev,
9066                                   bool force_restore)
9067 {
9068         struct drm_i915_private *dev_priv = dev->dev_private;
9069         enum pipe pipe;
9070         u32 tmp;
9071         struct drm_plane *plane;
9072         struct intel_crtc *crtc;
9073         struct intel_encoder *encoder;
9074         struct intel_connector *connector;
9075
9076         if (HAS_DDI(dev)) {
9077                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9078
9079                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9080                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9081                         case TRANS_DDI_EDP_INPUT_A_ON:
9082                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9083                                 pipe = PIPE_A;
9084                                 break;
9085                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9086                                 pipe = PIPE_B;
9087                                 break;
9088                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9089                                 pipe = PIPE_C;
9090                                 break;
9091                         default:
9092                                 /* A bogus value has been programmed, disable
9093                                  * the transcoder */
9094                                 WARN(1, "Bogus eDP source %08x\n", tmp);
9095                                 intel_ddi_disable_transcoder_func(dev_priv,
9096                                                 TRANSCODER_EDP);
9097                                 goto setup_pipes;
9098                         }
9099
9100                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9101                         crtc->cpu_transcoder = TRANSCODER_EDP;
9102
9103                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9104                                       pipe_name(pipe));
9105                 }
9106         }
9107
9108 setup_pipes:
9109         for_each_pipe(pipe) {
9110                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9111
9112                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9113                 if (tmp & PIPECONF_ENABLE)
9114                         crtc->active = true;
9115                 else
9116                         crtc->active = false;
9117
9118                 crtc->base.enabled = crtc->active;
9119
9120                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9121                               crtc->base.base.id,
9122                               crtc->active ? "enabled" : "disabled");
9123         }
9124
9125         if (HAS_DDI(dev))
9126                 intel_ddi_setup_hw_pll_state(dev);
9127
9128         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9129                             base.head) {
9130                 pipe = 0;
9131
9132                 if (encoder->get_hw_state(encoder, &pipe)) {
9133                         encoder->base.crtc =
9134                                 dev_priv->pipe_to_crtc_mapping[pipe];
9135                 } else {
9136                         encoder->base.crtc = NULL;
9137                 }
9138
9139                 encoder->connectors_active = false;
9140                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9141                               encoder->base.base.id,
9142                               drm_get_encoder_name(&encoder->base),
9143                               encoder->base.crtc ? "enabled" : "disabled",
9144                               pipe);
9145         }
9146
9147         list_for_each_entry(connector, &dev->mode_config.connector_list,
9148                             base.head) {
9149                 if (connector->get_hw_state(connector)) {
9150                         connector->base.dpms = DRM_MODE_DPMS_ON;
9151                         connector->encoder->connectors_active = true;
9152                         connector->base.encoder = &connector->encoder->base;
9153                 } else {
9154                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9155                         connector->base.encoder = NULL;
9156                 }
9157                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9158                               connector->base.base.id,
9159                               drm_get_connector_name(&connector->base),
9160                               connector->base.encoder ? "enabled" : "disabled");
9161         }
9162
9163         /* HW state is read out, now we need to sanitize this mess. */
9164         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9165                             base.head) {
9166                 intel_sanitize_encoder(encoder);
9167         }
9168
9169         for_each_pipe(pipe) {
9170                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9171                 intel_sanitize_crtc(crtc);
9172         }
9173
9174         if (force_restore) {
9175                 for_each_pipe(pipe) {
9176                         struct drm_crtc *crtc =
9177                                 dev_priv->pipe_to_crtc_mapping[pipe];
9178                         intel_crtc_restore_mode(crtc);
9179                 }
9180                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9181                         intel_plane_restore(plane);
9182
9183                 i915_redisable_vga(dev);
9184         } else {
9185                 intel_modeset_update_staged_output_state(dev);
9186         }
9187
9188         intel_modeset_check_state(dev);
9189
9190         drm_mode_config_reset(dev);
9191 }
9192
9193 void intel_modeset_gem_init(struct drm_device *dev)
9194 {
9195         intel_modeset_init_hw(dev);
9196
9197         intel_setup_overlay(dev);
9198
9199         intel_modeset_setup_hw_state(dev, false);
9200 }
9201
9202 void intel_modeset_cleanup(struct drm_device *dev)
9203 {
9204         struct drm_i915_private *dev_priv = dev->dev_private;
9205         struct drm_crtc *crtc;
9206         struct intel_crtc *intel_crtc;
9207
9208         drm_kms_helper_poll_fini(dev);
9209         mutex_lock(&dev->struct_mutex);
9210
9211         intel_unregister_dsm_handler();
9212
9213
9214         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9215                 /* Skip inactive CRTCs */
9216                 if (!crtc->fb)
9217                         continue;
9218
9219                 intel_crtc = to_intel_crtc(crtc);
9220                 intel_increase_pllclock(crtc);
9221         }
9222
9223         intel_disable_fbc(dev);
9224
9225         intel_disable_gt_powersave(dev);
9226
9227         ironlake_teardown_rc6(dev);
9228
9229         if (IS_VALLEYVIEW(dev))
9230                 vlv_init_dpio(dev);
9231
9232         mutex_unlock(&dev->struct_mutex);
9233
9234         /* Disable the irq before mode object teardown, for the irq might
9235          * enqueue unpin/hotplug work. */
9236         drm_irq_uninstall(dev);
9237         cancel_work_sync(&dev_priv->hotplug_work);
9238         cancel_work_sync(&dev_priv->rps.work);
9239
9240         /* flush any delayed tasks or pending work */
9241         flush_scheduled_work();
9242
9243         drm_mode_config_cleanup(dev);
9244
9245         intel_cleanup_overlay(dev);
9246 }
9247
9248 /*
9249  * Return which encoder is currently attached for connector.
9250  */
9251 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9252 {
9253         return &intel_attached_encoder(connector)->base;
9254 }
9255
9256 void intel_connector_attach_encoder(struct intel_connector *connector,
9257                                     struct intel_encoder *encoder)
9258 {
9259         connector->encoder = encoder;
9260         drm_mode_connector_attach_encoder(&connector->base,
9261                                           &encoder->base);
9262 }
9263
9264 /*
9265  * set vga decode state - true == enable VGA decode
9266  */
9267 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9268 {
9269         struct drm_i915_private *dev_priv = dev->dev_private;
9270         u16 gmch_ctrl;
9271
9272         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9273         if (state)
9274                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9275         else
9276                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9277         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9278         return 0;
9279 }
9280
9281 #ifdef CONFIG_DEBUG_FS
9282 #include <linux/seq_file.h>
9283
9284 struct intel_display_error_state {
9285         struct intel_cursor_error_state {
9286                 u32 control;
9287                 u32 position;
9288                 u32 base;
9289                 u32 size;
9290         } cursor[I915_MAX_PIPES];
9291
9292         struct intel_pipe_error_state {
9293                 u32 conf;
9294                 u32 source;
9295
9296                 u32 htotal;
9297                 u32 hblank;
9298                 u32 hsync;
9299                 u32 vtotal;
9300                 u32 vblank;
9301                 u32 vsync;
9302         } pipe[I915_MAX_PIPES];
9303
9304         struct intel_plane_error_state {
9305                 u32 control;
9306                 u32 stride;
9307                 u32 size;
9308                 u32 pos;
9309                 u32 addr;
9310                 u32 surface;
9311                 u32 tile_offset;
9312         } plane[I915_MAX_PIPES];
9313 };
9314
9315 struct intel_display_error_state *
9316 intel_display_capture_error_state(struct drm_device *dev)
9317 {
9318         drm_i915_private_t *dev_priv = dev->dev_private;
9319         struct intel_display_error_state *error;
9320         enum transcoder cpu_transcoder;
9321         int i;
9322
9323         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9324         if (error == NULL)
9325                 return NULL;
9326
9327         for_each_pipe(i) {
9328                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9329
9330                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9331                         error->cursor[i].control = I915_READ(CURCNTR(i));
9332                         error->cursor[i].position = I915_READ(CURPOS(i));
9333                         error->cursor[i].base = I915_READ(CURBASE(i));
9334                 } else {
9335                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9336                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9337                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9338                 }
9339
9340                 error->plane[i].control = I915_READ(DSPCNTR(i));
9341                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9342                 if (INTEL_INFO(dev)->gen <= 3) {
9343                         error->plane[i].size = I915_READ(DSPSIZE(i));
9344                         error->plane[i].pos = I915_READ(DSPPOS(i));
9345                 }
9346                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9347                         error->plane[i].addr = I915_READ(DSPADDR(i));
9348                 if (INTEL_INFO(dev)->gen >= 4) {
9349                         error->plane[i].surface = I915_READ(DSPSURF(i));
9350                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9351                 }
9352
9353                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9354                 error->pipe[i].source = I915_READ(PIPESRC(i));
9355                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9356                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9357                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9358                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9359                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9360                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9361         }
9362
9363         return error;
9364 }
9365
9366 void
9367 intel_display_print_error_state(struct seq_file *m,
9368                                 struct drm_device *dev,
9369                                 struct intel_display_error_state *error)
9370 {
9371         int i;
9372
9373         seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9374         for_each_pipe(i) {
9375                 seq_printf(m, "Pipe [%d]:\n", i);
9376                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9377                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9378                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9379                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9380                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9381                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9382                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9383                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9384
9385                 seq_printf(m, "Plane [%d]:\n", i);
9386                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9387                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9388                 if (INTEL_INFO(dev)->gen <= 3) {
9389                         seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9390                         seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9391                 }
9392                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9393                         seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9394                 if (INTEL_INFO(dev)->gen >= 4) {
9395                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9396                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9397                 }
9398
9399                 seq_printf(m, "Cursor [%d]:\n", i);
9400                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9401                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9402                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9403         }
9404 }
9405 #endif