drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include "drmP.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "drm_dp_helper.h"
  38
  39 #include "drm_crtc_helper.h"
  40
  41 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  42
  43 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  44 static void intel_update_watermarks(struct drm_device *dev);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  46
  47 typedef struct {
  48     /* given values */
  49     int n;
  50     int m1, m2;
  51     int p1, p2;
  52     /* derived values */
  53     int dot;
  54     int vco;
  55     int m;
  56     int p;
  57 } intel_clock_t;
  58
  59 typedef struct {
  60     int min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64     int dot_limit;
  65     int p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 #define INTEL_P2_NUM                  2
  69 typedef struct intel_limit intel_limit_t;
  70 struct intel_limit {
  71     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  72     intel_p2_t      p2;
  73     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  74                       int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define PINEVIEW_VCO_MIN                1700000
 106 #define PINEVIEW_VCO_MAX                3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* Pineview's Ncounter is a ring counter */
 110 #define PINEVIEW_N_MIN                3
 111 #define PINEVIEW_N_MAX                6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define PINEVIEW_M_MIN                2
 115 #define PINEVIEW_M_MAX              256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* Pineview M1 is reserved, and must be 0 */
 121 #define PINEVIEW_M1_MIN               0
 122 #define PINEVIEW_M1_MAX               0
 123 #define PINEVIEW_M2_MIN               0
 124 #define PINEVIEW_M2_MAX               254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define PINEVIEW_P_LVDS_MIN                   7
 130 #define PINEVIEW_P_LVDS_MAX                  112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* Ironlake / Sandybridge */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IRONLAKE_DOT_MIN         25000
 242 #define IRONLAKE_DOT_MAX         350000
 243 #define IRONLAKE_VCO_MIN         1760000
 244 #define IRONLAKE_VCO_MAX         3510000
 245 #define IRONLAKE_M1_MIN          12
 246 #define IRONLAKE_M1_MAX          22
 247 #define IRONLAKE_M2_MIN          5
 248 #define IRONLAKE_M2_MAX          9
 249 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 250
 251 /* We have parameter ranges for different type of outputs. */
 252
 253 /* DAC & HDMI Refclk 120Mhz */
 254 #define IRONLAKE_DAC_N_MIN      1
 255 #define IRONLAKE_DAC_N_MAX      5
 256 #define IRONLAKE_DAC_M_MIN      79
 257 #define IRONLAKE_DAC_M_MAX      127
 258 #define IRONLAKE_DAC_P_MIN      5
 259 #define IRONLAKE_DAC_P_MAX      80
 260 #define IRONLAKE_DAC_P1_MIN     1
 261 #define IRONLAKE_DAC_P1_MAX     8
 262 #define IRONLAKE_DAC_P2_SLOW    10
 263 #define IRONLAKE_DAC_P2_FAST    5
 264
 265 /* LVDS single-channel 120Mhz refclk */
 266 #define IRONLAKE_LVDS_S_N_MIN   1
 267 #define IRONLAKE_LVDS_S_N_MAX   3
 268 #define IRONLAKE_LVDS_S_M_MIN   79
 269 #define IRONLAKE_LVDS_S_M_MAX   118
 270 #define IRONLAKE_LVDS_S_P_MIN   28
 271 #define IRONLAKE_LVDS_S_P_MAX   112
 272 #define IRONLAKE_LVDS_S_P1_MIN  2
 273 #define IRONLAKE_LVDS_S_P1_MAX  8
 274 #define IRONLAKE_LVDS_S_P2_SLOW 14
 275 #define IRONLAKE_LVDS_S_P2_FAST 14
 276
 277 /* LVDS dual-channel 120Mhz refclk */
 278 #define IRONLAKE_LVDS_D_N_MIN   1
 279 #define IRONLAKE_LVDS_D_N_MAX   3
 280 #define IRONLAKE_LVDS_D_M_MIN   79
 281 #define IRONLAKE_LVDS_D_M_MAX   127
 282 #define IRONLAKE_LVDS_D_P_MIN   14
 283 #define IRONLAKE_LVDS_D_P_MAX   56
 284 #define IRONLAKE_LVDS_D_P1_MIN  2
 285 #define IRONLAKE_LVDS_D_P1_MAX  8
 286 #define IRONLAKE_LVDS_D_P2_SLOW 7
 287 #define IRONLAKE_LVDS_D_P2_FAST 7
 288
 289 /* LVDS single-channel 100Mhz refclk */
 290 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 291 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 292 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 293 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 294 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 295 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 296 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 297 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 298 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 299 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 300
 301 /* LVDS dual-channel 100Mhz refclk */
 302 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 303 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 304 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 305 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 306 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 307 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 308 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 309 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 310 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 311 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 312
 313 /* DisplayPort */
 314 #define IRONLAKE_DP_N_MIN               1
 315 #define IRONLAKE_DP_N_MAX               2
 316 #define IRONLAKE_DP_M_MIN               81
 317 #define IRONLAKE_DP_M_MAX               90
 318 #define IRONLAKE_DP_P_MIN               10
 319 #define IRONLAKE_DP_P_MAX               20
 320 #define IRONLAKE_DP_P2_FAST             10
 321 #define IRONLAKE_DP_P2_SLOW             10
 322 #define IRONLAKE_DP_P2_LIMIT            0
 323 #define IRONLAKE_DP_P1_MIN              1
 324 #define IRONLAKE_DP_P1_MAX              2
 325
 326 /* FDI */
 327 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 328
 329 static bool
 330 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 331                     int target, int refclk, intel_clock_t *best_clock);
 332 static bool
 333 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 334                         int target, int refclk, intel_clock_t *best_clock);
 335
 336 static bool
 337 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 338                       int target, int refclk, intel_clock_t *best_clock);
 339 static bool
 340 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 341                            int target, int refclk, intel_clock_t *best_clock);
 342
 343 static const intel_limit_t intel_limits_i8xx_dvo = {
 344         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 345         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 346         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 347         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 348         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 349         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 350         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 351         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 352         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 353                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 354         .find_pll = intel_find_best_PLL,
 355 };
 356
 357 static const intel_limit_t intel_limits_i8xx_lvds = {
 358         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 359         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 360         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 361         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 362         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 363         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 364         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 365         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 366         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 367                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 368         .find_pll = intel_find_best_PLL,
 369 };
 370
 371 static const intel_limit_t intel_limits_i9xx_sdvo = {
 372         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 373         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 374         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 375         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 376         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 377         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 378         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 379         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 380         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 381                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 382         .find_pll = intel_find_best_PLL,
 383 };
 384
 385 static const intel_limit_t intel_limits_i9xx_lvds = {
 386         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 387         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 388         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 389         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 390         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 391         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 392         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 393         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 394         /* The single-channel range is 25-112Mhz, and dual-channel
 395          * is 80-224Mhz.  Prefer single channel as much as possible.
 396          */
 397         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 398                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 399         .find_pll = intel_find_best_PLL,
 400 };
 401
 402     /* below parameter and function is for G4X Chipset Family*/
 403 static const intel_limit_t intel_limits_g4x_sdvo = {
 404         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 405         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 406         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 407         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 408         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 409         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 410         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 411         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 412         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 413                  .p2_slow = G4X_P2_SDVO_SLOW,
 414                  .p2_fast = G4X_P2_SDVO_FAST
 415         },
 416         .find_pll = intel_g4x_find_best_PLL,
 417 };
 418
 419 static const intel_limit_t intel_limits_g4x_hdmi = {
 420         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 421         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 422         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 423         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 424         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 425         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 426         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 427         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 428         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 429                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 430                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 431         },
 432         .find_pll = intel_g4x_find_best_PLL,
 433 };
 434
 435 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 436         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 437                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 438         .vco = { .min = G4X_VCO_MIN,
 439                  .max = G4X_VCO_MAX },
 440         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 441                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 442         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 443                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 444         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 445                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 446         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 447                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 448         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 450         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 451                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 452         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 453                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 454                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 455         },
 456         .find_pll = intel_g4x_find_best_PLL,
 457 };
 458
 459 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 460         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 461                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 462         .vco = { .min = G4X_VCO_MIN,
 463                  .max = G4X_VCO_MAX },
 464         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 465                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 466         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 467                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 468         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 469                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 470         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 471                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 472         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 474         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 475                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 476         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 477                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 478                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 479         },
 480         .find_pll = intel_g4x_find_best_PLL,
 481 };
 482
 483 static const intel_limit_t intel_limits_g4x_display_port = {
 484         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 485                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 486         .vco = { .min = G4X_VCO_MIN,
 487                  .max = G4X_VCO_MAX},
 488         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 489                  .max = G4X_N_DISPLAY_PORT_MAX },
 490         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 491                  .max = G4X_M_DISPLAY_PORT_MAX },
 492         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 493                  .max = G4X_M1_DISPLAY_PORT_MAX },
 494         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 495                  .max = G4X_M2_DISPLAY_PORT_MAX },
 496         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 497                  .max = G4X_P_DISPLAY_PORT_MAX },
 498         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 499                  .max = G4X_P1_DISPLAY_PORT_MAX},
 500         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 501                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 502                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 503         .find_pll = intel_find_pll_g4x_dp,
 504 };
 505
 506 static const intel_limit_t intel_limits_pineview_sdvo = {
 507         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 508         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 509         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 510         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 511         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 512         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 513         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 514         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 515         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 516                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 517         .find_pll = intel_find_best_PLL,
 518 };
 519
 520 static const intel_limit_t intel_limits_pineview_lvds = {
 521         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 522         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 523         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 524         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 525         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 526         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 527         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 528         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 529         /* Pineview only supports single-channel mode. */
 530         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 531                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 532         .find_pll = intel_find_best_PLL,
 533 };
 534
 535 static const intel_limit_t intel_limits_ironlake_dac = {
 536         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 537         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 538         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 539         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 540         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 541         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 542         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 543         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 544         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 545                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 546                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 547         .find_pll = intel_g4x_find_best_PLL,
 548 };
 549
 550 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 551         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 552         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 553         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 554         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 555         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 556         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 557         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 558         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 559         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 560                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 561                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 562         .find_pll = intel_g4x_find_best_PLL,
 563 };
 564
 565 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 566         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 567         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 568         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 569         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 570         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 571         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 572         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 573         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 574         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 575                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 576                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 577         .find_pll = intel_g4x_find_best_PLL,
 578 };
 579
 580 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 581         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 582         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 583         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 584         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 585         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 586         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 587         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 588         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 589         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 590                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 591                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 592         .find_pll = intel_g4x_find_best_PLL,
 593 };
 594
 595 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 596         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 597         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 598         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 599         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 600         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 601         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 602         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 603         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 604         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 605                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 606                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 607         .find_pll = intel_g4x_find_best_PLL,
 608 };
 609
 610 static const intel_limit_t intel_limits_ironlake_display_port = {
 611         .dot = { .min = IRONLAKE_DOT_MIN,
 612                  .max = IRONLAKE_DOT_MAX },
 613         .vco = { .min = IRONLAKE_VCO_MIN,
 614                  .max = IRONLAKE_VCO_MAX},
 615         .n   = { .min = IRONLAKE_DP_N_MIN,
 616                  .max = IRONLAKE_DP_N_MAX },
 617         .m   = { .min = IRONLAKE_DP_M_MIN,
 618                  .max = IRONLAKE_DP_M_MAX },
 619         .m1  = { .min = IRONLAKE_M1_MIN,
 620                  .max = IRONLAKE_M1_MAX },
 621         .m2  = { .min = IRONLAKE_M2_MIN,
 622                  .max = IRONLAKE_M2_MAX },
 623         .p   = { .min = IRONLAKE_DP_P_MIN,
 624                  .max = IRONLAKE_DP_P_MAX },
 625         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 626                  .max = IRONLAKE_DP_P1_MAX},
 627         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 628                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 629                  .p2_fast = IRONLAKE_DP_P2_FAST },
 630         .find_pll = intel_find_pll_ironlake_dp,
 631 };
 632
 633 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 634 {
 635         struct drm_device *dev = crtc->dev;
 636         struct drm_i915_private *dev_priv = dev->dev_private;
 637         const intel_limit_t *limit;
 638         int refclk = 120;
 639
 640         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 641                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 642                         refclk = 100;
 643
 644                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 645                     LVDS_CLKB_POWER_UP) {
 646                         /* LVDS dual channel */
 647                         if (refclk == 100)
 648                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 649                         else
 650                                 limit = &intel_limits_ironlake_dual_lvds;
 651                 } else {
 652                         if (refclk == 100)
 653                                 limit = &intel_limits_ironlake_single_lvds_100m;
 654                         else
 655                                 limit = &intel_limits_ironlake_single_lvds;
 656                 }
 657         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 658                         HAS_eDP)
 659                 limit = &intel_limits_ironlake_display_port;
 660         else
 661                 limit = &intel_limits_ironlake_dac;
 662
 663         return limit;
 664 }
 665
 666 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 667 {
 668         struct drm_device *dev = crtc->dev;
 669         struct drm_i915_private *dev_priv = dev->dev_private;
 670         const intel_limit_t *limit;
 671
 672         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 673                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 674                     LVDS_CLKB_POWER_UP)
 675                         /* LVDS with dual channel */
 676                         limit = &intel_limits_g4x_dual_channel_lvds;
 677                 else
 678                         /* LVDS with dual channel */
 679                         limit = &intel_limits_g4x_single_channel_lvds;
 680         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 681                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 682                 limit = &intel_limits_g4x_hdmi;
 683         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 684                 limit = &intel_limits_g4x_sdvo;
 685         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 686                 limit = &intel_limits_g4x_display_port;
 687         } else /* The option is for other outputs */
 688                 limit = &intel_limits_i9xx_sdvo;
 689
 690         return limit;
 691 }
 692
 693 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 694 {
 695         struct drm_device *dev = crtc->dev;
 696         const intel_limit_t *limit;
 697
 698         if (HAS_PCH_SPLIT(dev))
 699                 limit = intel_ironlake_limit(crtc);
 700         else if (IS_G4X(dev)) {
 701                 limit = intel_g4x_limit(crtc);
 702         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 703                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 704                         limit = &intel_limits_i9xx_lvds;
 705                 else
 706                         limit = &intel_limits_i9xx_sdvo;
 707         } else if (IS_PINEVIEW(dev)) {
 708                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 709                         limit = &intel_limits_pineview_lvds;
 710                 else
 711                         limit = &intel_limits_pineview_sdvo;
 712         } else {
 713                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 714                         limit = &intel_limits_i8xx_lvds;
 715                 else
 716                         limit = &intel_limits_i8xx_dvo;
 717         }
 718         return limit;
 719 }
 720
 721 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 722 static void pineview_clock(int refclk, intel_clock_t *clock)
 723 {
 724         clock->m = clock->m2 + 2;
 725         clock->p = clock->p1 * clock->p2;
 726         clock->vco = refclk * clock->m / clock->n;
 727         clock->dot = clock->vco / clock->p;
 728 }
 729
 730 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 731 {
 732         if (IS_PINEVIEW(dev)) {
 733                 pineview_clock(refclk, clock);
 734                 return;
 735         }
 736         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 737         clock->p = clock->p1 * clock->p2;
 738         clock->vco = refclk * clock->m / (clock->n + 2);
 739         clock->dot = clock->vco / clock->p;
 740 }
 741
 742 /**
 743  * Returns whether any output on the specified pipe is of the specified type
 744  */
 745 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 746 {
 747     struct drm_device *dev = crtc->dev;
 748     struct drm_mode_config *mode_config = &dev->mode_config;
 749     struct drm_encoder *l_entry;
 750
 751     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 752             if (l_entry && l_entry->crtc == crtc) {
 753                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 754                     if (intel_encoder->type == type)
 755                             return true;
 756             }
 757     }
 758     return false;
 759 }
 760
 761 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 762 /**
 763  * Returns whether the given set of divisors are valid for a given refclk with
 764  * the given connectors.
 765  */
 766
 767 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 768 {
 769         const intel_limit_t *limit = intel_limit (crtc);
 770         struct drm_device *dev = crtc->dev;
 771
 772         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 773                 INTELPllInvalid ("p1 out of range\n");
 774         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 775                 INTELPllInvalid ("p out of range\n");
 776         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 777                 INTELPllInvalid ("m2 out of range\n");
 778         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 779                 INTELPllInvalid ("m1 out of range\n");
 780         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 781                 INTELPllInvalid ("m1 <= m2\n");
 782         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 783                 INTELPllInvalid ("m out of range\n");
 784         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 785                 INTELPllInvalid ("n out of range\n");
 786         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 787                 INTELPllInvalid ("vco out of range\n");
 788         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 789          * connector, etc., rather than just a single range.
 790          */
 791         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 792                 INTELPllInvalid ("dot out of range\n");
 793
 794         return true;
 795 }
 796
 797 static bool
 798 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 799                     int target, int refclk, intel_clock_t *best_clock)
 800
 801 {
 802         struct drm_device *dev = crtc->dev;
 803         struct drm_i915_private *dev_priv = dev->dev_private;
 804         intel_clock_t clock;
 805         int err = target;
 806
 807         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 808             (I915_READ(LVDS)) != 0) {
 809                 /*
 810                  * For LVDS, if the panel is on, just rely on its current
 811                  * settings for dual-channel.  We haven't figured out how to
 812                  * reliably set up different single/dual channel state, if we
 813                  * even can.
 814                  */
 815                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 816                     LVDS_CLKB_POWER_UP)
 817                         clock.p2 = limit->p2.p2_fast;
 818                 else
 819                         clock.p2 = limit->p2.p2_slow;
 820         } else {
 821                 if (target < limit->p2.dot_limit)
 822                         clock.p2 = limit->p2.p2_slow;
 823                 else
 824                         clock.p2 = limit->p2.p2_fast;
 825         }
 826
 827         memset (best_clock, 0, sizeof (*best_clock));
 828
 829         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 830              clock.m1++) {
 831                 for (clock.m2 = limit->m2.min;
 832                      clock.m2 <= limit->m2.max; clock.m2++) {
 833                         /* m1 is always 0 in Pineview */
 834                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 835                                 break;
 836                         for (clock.n = limit->n.min;
 837                              clock.n <= limit->n.max; clock.n++) {
 838                                 for (clock.p1 = limit->p1.min;
 839                                         clock.p1 <= limit->p1.max; clock.p1++) {
 840                                         int this_err;
 841
 842                                         intel_clock(dev, refclk, &clock);
 843
 844                                         if (!intel_PLL_is_valid(crtc, &clock))
 845                                                 continue;
 846
 847                                         this_err = abs(clock.dot - target);
 848                                         if (this_err < err) {
 849                                                 *best_clock = clock;
 850                                                 err = this_err;
 851                                         }
 852                                 }
 853                         }
 854                 }
 855         }
 856
 857         return (err != target);
 858 }
 859
 860 static bool
 861 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 862                         int target, int refclk, intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc->dev;
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         intel_clock_t clock;
 867         int max_n;
 868         bool found;
 869         /* approximately equals target * 0.00585 */
 870         int err_most = (target >> 8) + (target >> 9);
 871         found = false;
 872
 873         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 874                 int lvds_reg;
 875
 876                 if (HAS_PCH_SPLIT(dev))
 877                         lvds_reg = PCH_LVDS;
 878                 else
 879                         lvds_reg = LVDS;
 880                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 881                     LVDS_CLKB_POWER_UP)
 882                         clock.p2 = limit->p2.p2_fast;
 883                 else
 884                         clock.p2 = limit->p2.p2_slow;
 885         } else {
 886                 if (target < limit->p2.dot_limit)
 887                         clock.p2 = limit->p2.p2_slow;
 888                 else
 889                         clock.p2 = limit->p2.p2_fast;
 890         }
 891
 892         memset(best_clock, 0, sizeof(*best_clock));
 893         max_n = limit->n.max;
 894         /* based on hardware requirement, prefer smaller n to precision */
 895         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 896                 /* based on hardware requirement, prefere larger m1,m2 */
 897                 for (clock.m1 = limit->m1.max;
 898                      clock.m1 >= limit->m1.min; clock.m1--) {
 899                         for (clock.m2 = limit->m2.max;
 900                              clock.m2 >= limit->m2.min; clock.m2--) {
 901                                 for (clock.p1 = limit->p1.max;
 902                                      clock.p1 >= limit->p1.min; clock.p1--) {
 903                                         int this_err;
 904
 905                                         intel_clock(dev, refclk, &clock);
 906                                         if (!intel_PLL_is_valid(crtc, &clock))
 907                                                 continue;
 908                                         this_err = abs(clock.dot - target) ;
 909                                         if (this_err < err_most) {
 910                                                 *best_clock = clock;
 911                                                 err_most = this_err;
 912                                                 max_n = clock.n;
 913                                                 found = true;
 914                                         }
 915                                 }
 916                         }
 917                 }
 918         }
 919         return found;
 920 }
 921
 922 static bool
 923 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 924                            int target, int refclk, intel_clock_t *best_clock)
 925 {
 926         struct drm_device *dev = crtc->dev;
 927         intel_clock_t clock;
 928
 929         /* return directly when it is eDP */
 930         if (HAS_eDP)
 931                 return true;
 932
 933         if (target < 200000) {
 934                 clock.n = 1;
 935                 clock.p1 = 2;
 936                 clock.p2 = 10;
 937                 clock.m1 = 12;
 938                 clock.m2 = 9;
 939         } else {
 940                 clock.n = 2;
 941                 clock.p1 = 1;
 942                 clock.p2 = 10;
 943                 clock.m1 = 14;
 944                 clock.m2 = 8;
 945         }
 946         intel_clock(dev, refclk, &clock);
 947         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 948         return true;
 949 }
 950
 951 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 952 static bool
 953 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 954                       int target, int refclk, intel_clock_t *best_clock)
 955 {
 956     intel_clock_t clock;
 957     if (target < 200000) {
 958         clock.p1 = 2;
 959         clock.p2 = 10;
 960         clock.n = 2;
 961         clock.m1 = 23;
 962         clock.m2 = 8;
 963     } else {
 964         clock.p1 = 1;
 965         clock.p2 = 10;
 966         clock.n = 1;
 967         clock.m1 = 14;
 968         clock.m2 = 2;
 969     }
 970     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 971     clock.p = (clock.p1 * clock.p2);
 972     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 973     clock.vco = 0;
 974     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 975     return true;
 976 }
 977
 978 void
 979 intel_wait_for_vblank(struct drm_device *dev)
 980 {
 981         /* Wait for 20ms, i.e. one cycle at 50hz. */
 982         msleep(20);
 983 }
 984
 985 /* Parameters have changed, update FBC info */
 986 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 987 {
 988         struct drm_device *dev = crtc->dev;
 989         struct drm_i915_private *dev_priv = dev->dev_private;
 990         struct drm_framebuffer *fb = crtc->fb;
 991         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 992         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
 993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 994         int plane, i;
 995         u32 fbc_ctl, fbc_ctl2;
 996
 997         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 998
 999         if (fb->pitch < dev_priv->cfb_pitch)
1000                 dev_priv->cfb_pitch = fb->pitch;
1001
1002         /* FBC_CTL wants 64B units */
1003         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1004         dev_priv->cfb_fence = obj_priv->fence_reg;
1005         dev_priv->cfb_plane = intel_crtc->plane;
1006         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1007
1008         /* Clear old tags */
1009         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1010                 I915_WRITE(FBC_TAG + (i * 4), 0);
1011
1012         /* Set it up... */
1013         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1014         if (obj_priv->tiling_mode != I915_TILING_NONE)
1015                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1016         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1017         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1018
1019         /* enable it... */
1020         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1021         if (IS_I945GM(dev))
1022                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1023         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1024         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1025         if (obj_priv->tiling_mode != I915_TILING_NONE)
1026                 fbc_ctl |= dev_priv->cfb_fence;
1027         I915_WRITE(FBC_CONTROL, fbc_ctl);
1028
1029         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1030                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1031 }
1032
1033 void i8xx_disable_fbc(struct drm_device *dev)
1034 {
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1037         u32 fbc_ctl;
1038
1039         if (!I915_HAS_FBC(dev))
1040                 return;
1041
1042         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1043                 return; /* Already off, just return */
1044
1045         /* Disable compression */
1046         fbc_ctl = I915_READ(FBC_CONTROL);
1047         fbc_ctl &= ~FBC_CTL_EN;
1048         I915_WRITE(FBC_CONTROL, fbc_ctl);
1049
1050         /* Wait for compressing bit to clear */
1051         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1052                 if (time_after(jiffies, timeout)) {
1053                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1054                         break;
1055                 }
1056                 ; /* do nothing */
1057         }
1058
1059         intel_wait_for_vblank(dev);
1060
1061         DRM_DEBUG_KMS("disabled FBC\n");
1062 }
1063
1064 static bool i8xx_fbc_enabled(struct drm_device *dev)
1065 {
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067
1068         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1069 }
1070
1071 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1072 {
1073         struct drm_device *dev = crtc->dev;
1074         struct drm_i915_private *dev_priv = dev->dev_private;
1075         struct drm_framebuffer *fb = crtc->fb;
1076         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1077         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1079         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1080                      DPFC_CTL_PLANEB);
1081         unsigned long stall_watermark = 200;
1082         u32 dpfc_ctl;
1083
1084         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1085         dev_priv->cfb_fence = obj_priv->fence_reg;
1086         dev_priv->cfb_plane = intel_crtc->plane;
1087
1088         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1089         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1090                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1091                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1092         } else {
1093                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1094         }
1095
1096         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1097         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1098                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1099                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1100         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1101
1102         /* enable it... */
1103         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1104
1105         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1106 }
1107
1108 void g4x_disable_fbc(struct drm_device *dev)
1109 {
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         u32 dpfc_ctl;
1112
1113         /* Disable compression */
1114         dpfc_ctl = I915_READ(DPFC_CONTROL);
1115         dpfc_ctl &= ~DPFC_CTL_EN;
1116         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1117         intel_wait_for_vblank(dev);
1118
1119         DRM_DEBUG_KMS("disabled FBC\n");
1120 }
1121
1122 static bool g4x_fbc_enabled(struct drm_device *dev)
1123 {
1124         struct drm_i915_private *dev_priv = dev->dev_private;
1125
1126         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1127 }
1128
1129 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1130 {
1131         struct drm_device *dev = crtc->dev;
1132         struct drm_i915_private *dev_priv = dev->dev_private;
1133         struct drm_framebuffer *fb = crtc->fb;
1134         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1135         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1137         int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1138                                                DPFC_CTL_PLANEB;
1139         unsigned long stall_watermark = 200;
1140         u32 dpfc_ctl;
1141
1142         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1143         dev_priv->cfb_fence = obj_priv->fence_reg;
1144         dev_priv->cfb_plane = intel_crtc->plane;
1145
1146         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1147         dpfc_ctl &= DPFC_RESERVED;
1148         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1149         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1150                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1151                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1152         } else {
1153                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1154         }
1155
1156         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1157         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1158                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1159                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1160         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1161         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1162         /* enable it... */
1163         I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1164                    DPFC_CTL_EN);
1165
1166         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1167 }
1168
1169 void ironlake_disable_fbc(struct drm_device *dev)
1170 {
1171         struct drm_i915_private *dev_priv = dev->dev_private;
1172         u32 dpfc_ctl;
1173
1174         /* Disable compression */
1175         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1176         dpfc_ctl &= ~DPFC_CTL_EN;
1177         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1178         intel_wait_for_vblank(dev);
1179
1180         DRM_DEBUG_KMS("disabled FBC\n");
1181 }
1182
1183 static bool ironlake_fbc_enabled(struct drm_device *dev)
1184 {
1185         struct drm_i915_private *dev_priv = dev->dev_private;
1186
1187         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1188 }
1189
1190 bool intel_fbc_enabled(struct drm_device *dev)
1191 {
1192         struct drm_i915_private *dev_priv = dev->dev_private;
1193
1194         if (!dev_priv->display.fbc_enabled)
1195                 return false;
1196
1197         return dev_priv->display.fbc_enabled(dev);
1198 }
1199
1200 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1201 {
1202         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1203
1204         if (!dev_priv->display.enable_fbc)
1205                 return;
1206
1207         dev_priv->display.enable_fbc(crtc, interval);
1208 }
1209
1210 void intel_disable_fbc(struct drm_device *dev)
1211 {
1212         struct drm_i915_private *dev_priv = dev->dev_private;
1213
1214         if (!dev_priv->display.disable_fbc)
1215                 return;
1216
1217         dev_priv->display.disable_fbc(dev);
1218 }
1219
1220 /**
1221  * intel_update_fbc - enable/disable FBC as needed
1222  * @crtc: CRTC to point the compressor at
1223  * @mode: mode in use
1224  *
1225  * Set up the framebuffer compression hardware at mode set time.  We
1226  * enable it if possible:
1227  *   - plane A only (on pre-965)
1228  *   - no pixel mulitply/line duplication
1229  *   - no alpha buffer discard
1230  *   - no dual wide
1231  *   - framebuffer <= 2048 in width, 1536 in height
1232  *
1233  * We can't assume that any compression will take place (worst case),
1234  * so the compressed buffer has to be the same size as the uncompressed
1235  * one.  It also must reside (along with the line length buffer) in
1236  * stolen memory.
1237  *
1238  * We need to enable/disable FBC on a global basis.
1239  */
1240 static void intel_update_fbc(struct drm_crtc *crtc,
1241                              struct drm_display_mode *mode)
1242 {
1243         struct drm_device *dev = crtc->dev;
1244         struct drm_i915_private *dev_priv = dev->dev_private;
1245         struct drm_framebuffer *fb = crtc->fb;
1246         struct intel_framebuffer *intel_fb;
1247         struct drm_i915_gem_object *obj_priv;
1248         struct drm_crtc *tmp_crtc;
1249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1250         int plane = intel_crtc->plane;
1251         int crtcs_enabled = 0;
1252
1253         DRM_DEBUG_KMS("\n");
1254
1255         if (!i915_powersave)
1256                 return;
1257
1258         if (!I915_HAS_FBC(dev))
1259                 return;
1260
1261         if (!crtc->fb)
1262                 return;
1263
1264         intel_fb = to_intel_framebuffer(fb);
1265         obj_priv = to_intel_bo(intel_fb->obj);
1266
1267         /*
1268          * If FBC is already on, we just have to verify that we can
1269          * keep it that way...
1270          * Need to disable if:
1271          *   - more than one pipe is active
1272          *   - changing FBC params (stride, fence, mode)
1273          *   - new fb is too large to fit in compressed buffer
1274          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1275          */
1276         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1277                 if (tmp_crtc->enabled)
1278                         crtcs_enabled++;
1279         }
1280         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1281         if (crtcs_enabled > 1) {
1282                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1283                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1284                 goto out_disable;
1285         }
1286         if (intel_fb->obj->size > dev_priv->cfb_size) {
1287                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1288                                 "compression\n");
1289                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1290                 goto out_disable;
1291         }
1292         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1293             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1294                 DRM_DEBUG_KMS("mode incompatible with compression, "
1295                                 "disabling\n");
1296                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1297                 goto out_disable;
1298         }
1299         if ((mode->hdisplay > 2048) ||
1300             (mode->vdisplay > 1536)) {
1301                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1302                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1303                 goto out_disable;
1304         }
1305         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1306                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1307                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1308                 goto out_disable;
1309         }
1310         if (obj_priv->tiling_mode != I915_TILING_X) {
1311                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1312                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1313                 goto out_disable;
1314         }
1315
1316         if (intel_fbc_enabled(dev)) {
1317                 /* We can re-enable it in this case, but need to update pitch */
1318                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1319                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1320                     (plane != dev_priv->cfb_plane))
1321                         intel_disable_fbc(dev);
1322         }
1323
1324         /* Now try to turn it back on if possible */
1325         if (!intel_fbc_enabled(dev))
1326                 intel_enable_fbc(crtc, 500);
1327
1328         return;
1329
1330 out_disable:
1331         /* Multiple disables should be harmless */
1332         if (intel_fbc_enabled(dev)) {
1333                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1334                 intel_disable_fbc(dev);
1335         }
1336 }
1337
1338 int
1339 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1340 {
1341         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1342         u32 alignment;
1343         int ret;
1344
1345         switch (obj_priv->tiling_mode) {
1346         case I915_TILING_NONE:
1347                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1348                         alignment = 128 * 1024;
1349                 else if (IS_I965G(dev))
1350                         alignment = 4 * 1024;
1351                 else
1352                         alignment = 64 * 1024;
1353                 break;
1354         case I915_TILING_X:
1355                 /* pin() will align the object as required by fence */
1356                 alignment = 0;
1357                 break;
1358         case I915_TILING_Y:
1359                 /* FIXME: Is this true? */
1360                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1361                 return -EINVAL;
1362         default:
1363                 BUG();
1364         }
1365
1366         ret = i915_gem_object_pin(obj, alignment);
1367         if (ret != 0)
1368                 return ret;
1369
1370         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1371          * fence, whereas 965+ only requires a fence if using
1372          * framebuffer compression.  For simplicity, we always install
1373          * a fence as the cost is not that onerous.
1374          */
1375         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1376             obj_priv->tiling_mode != I915_TILING_NONE) {
1377                 ret = i915_gem_object_get_fence_reg(obj);
1378                 if (ret != 0) {
1379                         i915_gem_object_unpin(obj);
1380                         return ret;
1381                 }
1382         }
1383
1384         return 0;
1385 }
1386
1387 static int
1388 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1389                     struct drm_framebuffer *old_fb)
1390 {
1391         struct drm_device *dev = crtc->dev;
1392         struct drm_i915_private *dev_priv = dev->dev_private;
1393         struct drm_i915_master_private *master_priv;
1394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1395         struct intel_framebuffer *intel_fb;
1396         struct drm_i915_gem_object *obj_priv;
1397         struct drm_gem_object *obj;
1398         int pipe = intel_crtc->pipe;
1399         int plane = intel_crtc->plane;
1400         unsigned long Start, Offset;
1401         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1402         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1403         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1404         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1405         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1406         u32 dspcntr;
1407         int ret;
1408
1409         /* no fb bound */
1410         if (!crtc->fb) {
1411                 DRM_DEBUG_KMS("No FB bound\n");
1412                 return 0;
1413         }
1414
1415         switch (plane) {
1416         case 0:
1417         case 1:
1418                 break;
1419         default:
1420                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1421                 return -EINVAL;
1422         }
1423
1424         intel_fb = to_intel_framebuffer(crtc->fb);
1425         obj = intel_fb->obj;
1426         obj_priv = to_intel_bo(obj);
1427
1428         mutex_lock(&dev->struct_mutex);
1429         ret = intel_pin_and_fence_fb_obj(dev, obj);
1430         if (ret != 0) {
1431                 mutex_unlock(&dev->struct_mutex);
1432                 return ret;
1433         }
1434
1435         ret = i915_gem_object_set_to_display_plane(obj);
1436         if (ret != 0) {
1437                 i915_gem_object_unpin(obj);
1438                 mutex_unlock(&dev->struct_mutex);
1439                 return ret;
1440         }
1441
1442         dspcntr = I915_READ(dspcntr_reg);
1443         /* Mask out pixel format bits in case we change it */
1444         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1445         switch (crtc->fb->bits_per_pixel) {
1446         case 8:
1447                 dspcntr |= DISPPLANE_8BPP;
1448                 break;
1449         case 16:
1450                 if (crtc->fb->depth == 15)
1451                         dspcntr |= DISPPLANE_15_16BPP;
1452                 else
1453                         dspcntr |= DISPPLANE_16BPP;
1454                 break;
1455         case 24:
1456         case 32:
1457                 if (crtc->fb->depth == 30)
1458                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1459                 else
1460                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1461                 break;
1462         default:
1463                 DRM_ERROR("Unknown color depth\n");
1464                 i915_gem_object_unpin(obj);
1465                 mutex_unlock(&dev->struct_mutex);
1466                 return -EINVAL;
1467         }
1468         if (IS_I965G(dev)) {
1469                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1470                         dspcntr |= DISPPLANE_TILED;
1471                 else
1472                         dspcntr &= ~DISPPLANE_TILED;
1473         }
1474
1475         if (HAS_PCH_SPLIT(dev))
1476                 /* must disable */
1477                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1478
1479         I915_WRITE(dspcntr_reg, dspcntr);
1480
1481         Start = obj_priv->gtt_offset;
1482         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1483
1484         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1485                       Start, Offset, x, y, crtc->fb->pitch);
1486         I915_WRITE(dspstride, crtc->fb->pitch);
1487         if (IS_I965G(dev)) {
1488                 I915_WRITE(dspbase, Offset);
1489                 I915_READ(dspbase);
1490                 I915_WRITE(dspsurf, Start);
1491                 I915_READ(dspsurf);
1492                 I915_WRITE(dsptileoff, (y << 16) | x);
1493         } else {
1494                 I915_WRITE(dspbase, Start + Offset);
1495                 I915_READ(dspbase);
1496         }
1497
1498         if ((IS_I965G(dev) || plane == 0))
1499                 intel_update_fbc(crtc, &crtc->mode);
1500
1501         intel_wait_for_vblank(dev);
1502
1503         if (old_fb) {
1504                 intel_fb = to_intel_framebuffer(old_fb);
1505                 obj_priv = to_intel_bo(intel_fb->obj);
1506                 i915_gem_object_unpin(intel_fb->obj);
1507         }
1508         intel_increase_pllclock(crtc, true);
1509
1510         mutex_unlock(&dev->struct_mutex);
1511
1512         if (!dev->primary->master)
1513                 return 0;
1514
1515         master_priv = dev->primary->master->driver_priv;
1516         if (!master_priv->sarea_priv)
1517                 return 0;
1518
1519         if (pipe) {
1520                 master_priv->sarea_priv->pipeB_x = x;
1521                 master_priv->sarea_priv->pipeB_y = y;
1522         } else {
1523                 master_priv->sarea_priv->pipeA_x = x;
1524                 master_priv->sarea_priv->pipeA_y = y;
1525         }
1526
1527         return 0;
1528 }
1529
1530 /* Disable the VGA plane that we never use */
1531 static void i915_disable_vga (struct drm_device *dev)
1532 {
1533         struct drm_i915_private *dev_priv = dev->dev_private;
1534         u8 sr1;
1535         u32 vga_reg;
1536
1537         if (HAS_PCH_SPLIT(dev))
1538                 vga_reg = CPU_VGACNTRL;
1539         else
1540                 vga_reg = VGACNTRL;
1541
1542         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1543                 return;
1544
1545         I915_WRITE8(VGA_SR_INDEX, 1);
1546         sr1 = I915_READ8(VGA_SR_DATA);
1547         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1548         udelay(100);
1549
1550         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1551 }
1552
1553 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1554 {
1555         struct drm_device *dev = crtc->dev;
1556         struct drm_i915_private *dev_priv = dev->dev_private;
1557         u32 dpa_ctl;
1558
1559         DRM_DEBUG_KMS("\n");
1560         dpa_ctl = I915_READ(DP_A);
1561         dpa_ctl &= ~DP_PLL_ENABLE;
1562         I915_WRITE(DP_A, dpa_ctl);
1563 }
1564
1565 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1566 {
1567         struct drm_device *dev = crtc->dev;
1568         struct drm_i915_private *dev_priv = dev->dev_private;
1569         u32 dpa_ctl;
1570
1571         dpa_ctl = I915_READ(DP_A);
1572         dpa_ctl |= DP_PLL_ENABLE;
1573         I915_WRITE(DP_A, dpa_ctl);
1574         udelay(200);
1575 }
1576
1577
1578 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1579 {
1580         struct drm_device *dev = crtc->dev;
1581         struct drm_i915_private *dev_priv = dev->dev_private;
1582         u32 dpa_ctl;
1583
1584         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1585         dpa_ctl = I915_READ(DP_A);
1586         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1587
1588         if (clock < 200000) {
1589                 u32 temp;
1590                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1591                 /* workaround for 160Mhz:
1592                    1) program 0x4600c bits 15:0 = 0x8124
1593                    2) program 0x46010 bit 0 = 1
1594                    3) program 0x46034 bit 24 = 1
1595                    4) program 0x64000 bit 14 = 1
1596                    */
1597                 temp = I915_READ(0x4600c);
1598                 temp &= 0xffff0000;
1599                 I915_WRITE(0x4600c, temp | 0x8124);
1600
1601                 temp = I915_READ(0x46010);
1602                 I915_WRITE(0x46010, temp | 1);
1603
1604                 temp = I915_READ(0x46034);
1605                 I915_WRITE(0x46034, temp | (1 << 24));
1606         } else {
1607                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1608         }
1609         I915_WRITE(DP_A, dpa_ctl);
1610
1611         udelay(500);
1612 }
1613
1614 /* The FDI link training functions for ILK/Ibexpeak. */
1615 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1616 {
1617         struct drm_device *dev = crtc->dev;
1618         struct drm_i915_private *dev_priv = dev->dev_private;
1619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1620         int pipe = intel_crtc->pipe;
1621         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1622         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1623         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1624         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1625         u32 temp, tries = 0;
1626
1627         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1628            for train result */
1629         temp = I915_READ(fdi_rx_imr_reg);
1630         temp &= ~FDI_RX_SYMBOL_LOCK;
1631         temp &= ~FDI_RX_BIT_LOCK;
1632         I915_WRITE(fdi_rx_imr_reg, temp);
1633         I915_READ(fdi_rx_imr_reg);
1634         udelay(150);
1635
1636         /* enable CPU FDI TX and PCH FDI RX */
1637         temp = I915_READ(fdi_tx_reg);
1638         temp |= FDI_TX_ENABLE;
1639         temp &= ~(7 << 19);
1640         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1641         temp &= ~FDI_LINK_TRAIN_NONE;
1642         temp |= FDI_LINK_TRAIN_PATTERN_1;
1643         I915_WRITE(fdi_tx_reg, temp);
1644         I915_READ(fdi_tx_reg);
1645
1646         temp = I915_READ(fdi_rx_reg);
1647         temp &= ~FDI_LINK_TRAIN_NONE;
1648         temp |= FDI_LINK_TRAIN_PATTERN_1;
1649         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1650         I915_READ(fdi_rx_reg);
1651         udelay(150);
1652
1653         for (tries = 0; tries < 5; tries++) {
1654                 temp = I915_READ(fdi_rx_iir_reg);
1655                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1656
1657                 if ((temp & FDI_RX_BIT_LOCK)) {
1658                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1659                         I915_WRITE(fdi_rx_iir_reg,
1660                                    temp | FDI_RX_BIT_LOCK);
1661                         break;
1662                 }
1663         }
1664         if (tries == 5)
1665                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1666
1667         /* Train 2 */
1668         temp = I915_READ(fdi_tx_reg);
1669         temp &= ~FDI_LINK_TRAIN_NONE;
1670         temp |= FDI_LINK_TRAIN_PATTERN_2;
1671         I915_WRITE(fdi_tx_reg, temp);
1672
1673         temp = I915_READ(fdi_rx_reg);
1674         temp &= ~FDI_LINK_TRAIN_NONE;
1675         temp |= FDI_LINK_TRAIN_PATTERN_2;
1676         I915_WRITE(fdi_rx_reg, temp);
1677         udelay(150);
1678
1679         tries = 0;
1680
1681         for (tries = 0; tries < 5; tries++) {
1682                 temp = I915_READ(fdi_rx_iir_reg);
1683                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1684
1685                 if (temp & FDI_RX_SYMBOL_LOCK) {
1686                         I915_WRITE(fdi_rx_iir_reg,
1687                                    temp | FDI_RX_SYMBOL_LOCK);
1688                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1689                         break;
1690                 }
1691         }
1692         if (tries == 5)
1693                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1694
1695         DRM_DEBUG_KMS("FDI train done\n");
1696 }
1697
1698 static int snb_b_fdi_train_param [] = {
1699         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1700         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1701         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1702         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1703 };
1704
1705 /* The FDI link training functions for SNB/Cougarpoint. */
1706 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1707 {
1708         struct drm_device *dev = crtc->dev;
1709         struct drm_i915_private *dev_priv = dev->dev_private;
1710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1711         int pipe = intel_crtc->pipe;
1712         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1713         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1714         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1715         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1716         u32 temp, i;
1717
1718         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1719            for train result */
1720         temp = I915_READ(fdi_rx_imr_reg);
1721         temp &= ~FDI_RX_SYMBOL_LOCK;
1722         temp &= ~FDI_RX_BIT_LOCK;
1723         I915_WRITE(fdi_rx_imr_reg, temp);
1724         I915_READ(fdi_rx_imr_reg);
1725         udelay(150);
1726
1727         /* enable CPU FDI TX and PCH FDI RX */
1728         temp = I915_READ(fdi_tx_reg);
1729         temp |= FDI_TX_ENABLE;
1730         temp &= ~(7 << 19);
1731         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1732         temp &= ~FDI_LINK_TRAIN_NONE;
1733         temp |= FDI_LINK_TRAIN_PATTERN_1;
1734         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1735         /* SNB-B */
1736         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1737         I915_WRITE(fdi_tx_reg, temp);
1738         I915_READ(fdi_tx_reg);
1739
1740         temp = I915_READ(fdi_rx_reg);
1741         if (HAS_PCH_CPT(dev)) {
1742                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1743                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1744         } else {
1745                 temp &= ~FDI_LINK_TRAIN_NONE;
1746                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1747         }
1748         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1749         I915_READ(fdi_rx_reg);
1750         udelay(150);
1751
1752         for (i = 0; i < 4; i++ ) {
1753                 temp = I915_READ(fdi_tx_reg);
1754                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1755                 temp |= snb_b_fdi_train_param[i];
1756                 I915_WRITE(fdi_tx_reg, temp);
1757                 udelay(500);
1758
1759                 temp = I915_READ(fdi_rx_iir_reg);
1760                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1761
1762                 if (temp & FDI_RX_BIT_LOCK) {
1763                         I915_WRITE(fdi_rx_iir_reg,
1764                                    temp | FDI_RX_BIT_LOCK);
1765                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1766                         break;
1767                 }
1768         }
1769         if (i == 4)
1770                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1771
1772         /* Train 2 */
1773         temp = I915_READ(fdi_tx_reg);
1774         temp &= ~FDI_LINK_TRAIN_NONE;
1775         temp |= FDI_LINK_TRAIN_PATTERN_2;
1776         if (IS_GEN6(dev)) {
1777                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1778                 /* SNB-B */
1779                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1780         }
1781         I915_WRITE(fdi_tx_reg, temp);
1782
1783         temp = I915_READ(fdi_rx_reg);
1784         if (HAS_PCH_CPT(dev)) {
1785                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1786                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1787         } else {
1788                 temp &= ~FDI_LINK_TRAIN_NONE;
1789                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1790         }
1791         I915_WRITE(fdi_rx_reg, temp);
1792         udelay(150);
1793
1794         for (i = 0; i < 4; i++ ) {
1795                 temp = I915_READ(fdi_tx_reg);
1796                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1797                 temp |= snb_b_fdi_train_param[i];
1798                 I915_WRITE(fdi_tx_reg, temp);
1799                 udelay(500);
1800
1801                 temp = I915_READ(fdi_rx_iir_reg);
1802                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1803
1804                 if (temp & FDI_RX_SYMBOL_LOCK) {
1805                         I915_WRITE(fdi_rx_iir_reg,
1806                                    temp | FDI_RX_SYMBOL_LOCK);
1807                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1808                         break;
1809                 }
1810         }
1811         if (i == 4)
1812                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1813
1814         DRM_DEBUG_KMS("FDI train done.\n");
1815 }
1816
1817 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1818 {
1819         struct drm_device *dev = crtc->dev;
1820         struct drm_i915_private *dev_priv = dev->dev_private;
1821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1822         int pipe = intel_crtc->pipe;
1823         int plane = intel_crtc->plane;
1824         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1825         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1826         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1827         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1828         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1829         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1830         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1831         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1832         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1833         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1834         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1835         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1836         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1837         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1838         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1839         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1840         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1841         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1842         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1843         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1844         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1845         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1846         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1847         u32 temp;
1848         int n;
1849         u32 pipe_bpc;
1850
1851         temp = I915_READ(pipeconf_reg);
1852         pipe_bpc = temp & PIPE_BPC_MASK;
1853
1854         /* XXX: When our outputs are all unaware of DPMS modes other than off
1855          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1856          */
1857         switch (mode) {
1858         case DRM_MODE_DPMS_ON:
1859         case DRM_MODE_DPMS_STANDBY:
1860         case DRM_MODE_DPMS_SUSPEND:
1861                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1862
1863                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1864                         temp = I915_READ(PCH_LVDS);
1865                         if ((temp & LVDS_PORT_EN) == 0) {
1866                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1867                                 POSTING_READ(PCH_LVDS);
1868                         }
1869                 }
1870
1871                 if (HAS_eDP) {
1872                         /* enable eDP PLL */
1873                         ironlake_enable_pll_edp(crtc);
1874                 } else {
1875
1876                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1877                         temp = I915_READ(fdi_rx_reg);
1878                         /*
1879                          * make the BPC in FDI Rx be consistent with that in
1880                          * pipeconf reg.
1881                          */
1882                         temp &= ~(0x7 << 16);
1883                         temp |= (pipe_bpc << 11);
1884                         temp &= ~(7 << 19);
1885                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1886                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1887                         I915_READ(fdi_rx_reg);
1888                         udelay(200);
1889
1890                         /* Switch from Rawclk to PCDclk */
1891                         temp = I915_READ(fdi_rx_reg);
1892                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1893                         I915_READ(fdi_rx_reg);
1894                         udelay(200);
1895
1896                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1897                         temp = I915_READ(fdi_tx_reg);
1898                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1899                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1900                                 I915_READ(fdi_tx_reg);
1901                                 udelay(100);
1902                         }
1903                 }
1904
1905                 /* Enable panel fitting for LVDS */
1906                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1907                         temp = I915_READ(pf_ctl_reg);
1908                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1909
1910                         /* currently full aspect */
1911                         I915_WRITE(pf_win_pos, 0);
1912
1913                         I915_WRITE(pf_win_size,
1914                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1915                                    (dev_priv->panel_fixed_mode->vdisplay));
1916                 }
1917
1918                 /* Enable CPU pipe */
1919                 temp = I915_READ(pipeconf_reg);
1920                 if ((temp & PIPEACONF_ENABLE) == 0) {
1921                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1922                         I915_READ(pipeconf_reg);
1923                         udelay(100);
1924                 }
1925
1926                 /* configure and enable CPU plane */
1927                 temp = I915_READ(dspcntr_reg);
1928                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1929                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1930                         /* Flush the plane changes */
1931                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1932                 }
1933
1934                 if (!HAS_eDP) {
1935                         /* For PCH output, training FDI link */
1936                         if (IS_GEN6(dev))
1937                                 gen6_fdi_link_train(crtc);
1938                         else
1939                                 ironlake_fdi_link_train(crtc);
1940
1941                         /* enable PCH DPLL */
1942                         temp = I915_READ(pch_dpll_reg);
1943                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1944                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1945                                 I915_READ(pch_dpll_reg);
1946                         }
1947                         udelay(200);
1948
1949                         if (HAS_PCH_CPT(dev)) {
1950                                 /* Be sure PCH DPLL SEL is set */
1951                                 temp = I915_READ(PCH_DPLL_SEL);
1952                                 if (trans_dpll_sel == 0 &&
1953                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1954                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1955                                 else if (trans_dpll_sel == 1 &&
1956                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1957                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1958                                 I915_WRITE(PCH_DPLL_SEL, temp);
1959                                 I915_READ(PCH_DPLL_SEL);
1960                         }
1961
1962                         /* set transcoder timing */
1963                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1964                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1965                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1966
1967                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1968                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1969                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1970
1971                         /* enable normal train */
1972                         temp = I915_READ(fdi_tx_reg);
1973                         temp &= ~FDI_LINK_TRAIN_NONE;
1974                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1975                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1976                         I915_READ(fdi_tx_reg);
1977
1978                         temp = I915_READ(fdi_rx_reg);
1979                         if (HAS_PCH_CPT(dev)) {
1980                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1981                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1982                         } else {
1983                                 temp &= ~FDI_LINK_TRAIN_NONE;
1984                                 temp |= FDI_LINK_TRAIN_NONE;
1985                         }
1986                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1987                         I915_READ(fdi_rx_reg);
1988
1989                         /* wait one idle pattern time */
1990                         udelay(100);
1991
1992                         /* For PCH DP, enable TRANS_DP_CTL */
1993                         if (HAS_PCH_CPT(dev) &&
1994                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1995                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1996                                 int reg;
1997
1998                                 reg = I915_READ(trans_dp_ctl);
1999                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
2000                                 reg = TRANS_DP_OUTPUT_ENABLE |
2001                                       TRANS_DP_ENH_FRAMING |
2002                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
2003                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
2004
2005                                 switch (intel_trans_dp_port_sel(crtc)) {
2006                                 case PCH_DP_B:
2007                                         reg |= TRANS_DP_PORT_SEL_B;
2008                                         break;
2009                                 case PCH_DP_C:
2010                                         reg |= TRANS_DP_PORT_SEL_C;
2011                                         break;
2012                                 case PCH_DP_D:
2013                                         reg |= TRANS_DP_PORT_SEL_D;
2014                                         break;
2015                                 default:
2016                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2017                                         reg |= TRANS_DP_PORT_SEL_B;
2018                                         break;
2019                                 }
2020
2021                                 I915_WRITE(trans_dp_ctl, reg);
2022                                 POSTING_READ(trans_dp_ctl);
2023                         }
2024
2025                         /* enable PCH transcoder */
2026                         temp = I915_READ(transconf_reg);
2027                         /*
2028                          * make the BPC in transcoder be consistent with
2029                          * that in pipeconf reg.
2030                          */
2031                         temp &= ~PIPE_BPC_MASK;
2032                         temp |= pipe_bpc;
2033                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2034                         I915_READ(transconf_reg);
2035
2036                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
2037                                 ;
2038
2039                 }
2040
2041                 intel_crtc_load_lut(crtc);
2042
2043                 intel_update_fbc(crtc, &crtc->mode);
2044
2045         break;
2046         case DRM_MODE_DPMS_OFF:
2047                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
2048
2049                 drm_vblank_off(dev, pipe);
2050                 /* Disable display plane */
2051                 temp = I915_READ(dspcntr_reg);
2052                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2053                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2054                         /* Flush the plane changes */
2055                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2056                         I915_READ(dspbase_reg);
2057                 }
2058
2059                 if (dev_priv->cfb_plane == plane &&
2060                     dev_priv->display.disable_fbc)
2061                         dev_priv->display.disable_fbc(dev);
2062
2063                 i915_disable_vga(dev);
2064
2065                 /* disable cpu pipe, disable after all planes disabled */
2066                 temp = I915_READ(pipeconf_reg);
2067                 if ((temp & PIPEACONF_ENABLE) != 0) {
2068                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2069                         I915_READ(pipeconf_reg);
2070                         n = 0;
2071                         /* wait for cpu pipe off, pipe state */
2072                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2073                                 n++;
2074                                 if (n < 60) {
2075                                         udelay(500);
2076                                         continue;
2077                                 } else {
2078                                         DRM_DEBUG_KMS("pipe %d off delay\n",
2079                                                                 pipe);
2080                                         break;
2081                                 }
2082                         }
2083                 } else
2084                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2085
2086                 udelay(100);
2087
2088                 /* Disable PF */
2089                 temp = I915_READ(pf_ctl_reg);
2090                 if ((temp & PF_ENABLE) != 0) {
2091                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2092                         I915_READ(pf_ctl_reg);
2093                 }
2094                 I915_WRITE(pf_win_size, 0);
2095                 POSTING_READ(pf_win_size);
2096
2097
2098                 /* disable CPU FDI tx and PCH FDI rx */
2099                 temp = I915_READ(fdi_tx_reg);
2100                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2101                 I915_READ(fdi_tx_reg);
2102
2103                 temp = I915_READ(fdi_rx_reg);
2104                 /* BPC in FDI rx is consistent with that in pipeconf */
2105                 temp &= ~(0x07 << 16);
2106                 temp |= (pipe_bpc << 11);
2107                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2108                 I915_READ(fdi_rx_reg);
2109
2110                 udelay(100);
2111
2112                 /* still set train pattern 1 */
2113                 temp = I915_READ(fdi_tx_reg);
2114                 temp &= ~FDI_LINK_TRAIN_NONE;
2115                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2116                 I915_WRITE(fdi_tx_reg, temp);
2117                 POSTING_READ(fdi_tx_reg);
2118
2119                 temp = I915_READ(fdi_rx_reg);
2120                 if (HAS_PCH_CPT(dev)) {
2121                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2122                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2123                 } else {
2124                         temp &= ~FDI_LINK_TRAIN_NONE;
2125                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2126                 }
2127                 I915_WRITE(fdi_rx_reg, temp);
2128                 POSTING_READ(fdi_rx_reg);
2129
2130                 udelay(100);
2131
2132                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2133                         temp = I915_READ(PCH_LVDS);
2134                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2135                         I915_READ(PCH_LVDS);
2136                         udelay(100);
2137                 }
2138
2139                 /* disable PCH transcoder */
2140                 temp = I915_READ(transconf_reg);
2141                 if ((temp & TRANS_ENABLE) != 0) {
2142                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2143                         I915_READ(transconf_reg);
2144                         n = 0;
2145                         /* wait for PCH transcoder off, transcoder state */
2146                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2147                                 n++;
2148                                 if (n < 60) {
2149                                         udelay(500);
2150                                         continue;
2151                                 } else {
2152                                         DRM_DEBUG_KMS("transcoder %d off "
2153                                                         "delay\n", pipe);
2154                                         break;
2155                                 }
2156                         }
2157                 }
2158
2159                 temp = I915_READ(transconf_reg);
2160                 /* BPC in transcoder is consistent with that in pipeconf */
2161                 temp &= ~PIPE_BPC_MASK;
2162                 temp |= pipe_bpc;
2163                 I915_WRITE(transconf_reg, temp);
2164                 I915_READ(transconf_reg);
2165                 udelay(100);
2166
2167                 if (HAS_PCH_CPT(dev)) {
2168                         /* disable TRANS_DP_CTL */
2169                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2170                         int reg;
2171
2172                         reg = I915_READ(trans_dp_ctl);
2173                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2174                         I915_WRITE(trans_dp_ctl, reg);
2175                         POSTING_READ(trans_dp_ctl);
2176
2177                         /* disable DPLL_SEL */
2178                         temp = I915_READ(PCH_DPLL_SEL);
2179                         if (trans_dpll_sel == 0)
2180                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2181                         else
2182                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2183                         I915_WRITE(PCH_DPLL_SEL, temp);
2184                         I915_READ(PCH_DPLL_SEL);
2185
2186                 }
2187
2188                 /* disable PCH DPLL */
2189                 temp = I915_READ(pch_dpll_reg);
2190                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2191                 I915_READ(pch_dpll_reg);
2192
2193                 if (HAS_eDP) {
2194                         ironlake_disable_pll_edp(crtc);
2195                 }
2196
2197                 /* Switch from PCDclk to Rawclk */
2198                 temp = I915_READ(fdi_rx_reg);
2199                 temp &= ~FDI_SEL_PCDCLK;
2200                 I915_WRITE(fdi_rx_reg, temp);
2201                 I915_READ(fdi_rx_reg);
2202
2203                 /* Disable CPU FDI TX PLL */
2204                 temp = I915_READ(fdi_tx_reg);
2205                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2206                 I915_READ(fdi_tx_reg);
2207                 udelay(100);
2208
2209                 temp = I915_READ(fdi_rx_reg);
2210                 temp &= ~FDI_RX_PLL_ENABLE;
2211                 I915_WRITE(fdi_rx_reg, temp);
2212                 I915_READ(fdi_rx_reg);
2213
2214                 /* Wait for the clocks to turn off. */
2215                 udelay(100);
2216                 break;
2217         }
2218 }
2219
2220 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2221 {
2222         struct intel_overlay *overlay;
2223         int ret;
2224
2225         if (!enable && intel_crtc->overlay) {
2226                 overlay = intel_crtc->overlay;
2227                 mutex_lock(&overlay->dev->struct_mutex);
2228                 for (;;) {
2229                         ret = intel_overlay_switch_off(overlay);
2230                         if (ret == 0)
2231                                 break;
2232
2233                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2234                         if (ret != 0) {
2235                                 /* overlay doesn't react anymore. Usually
2236                                  * results in a black screen and an unkillable
2237                                  * X server. */
2238                                 BUG();
2239                                 overlay->hw_wedged = HW_WEDGED;
2240                                 break;
2241                         }
2242                 }
2243                 mutex_unlock(&overlay->dev->struct_mutex);
2244         }
2245         /* Let userspace switch the overlay on again. In most cases userspace
2246          * has to recompute where to put it anyway. */
2247
2248         return;
2249 }
2250
2251 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2252 {
2253         struct drm_device *dev = crtc->dev;
2254         struct drm_i915_private *dev_priv = dev->dev_private;
2255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2256         int pipe = intel_crtc->pipe;
2257         int plane = intel_crtc->plane;
2258         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2259         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2260         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2261         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2262         u32 temp;
2263
2264         /* XXX: When our outputs are all unaware of DPMS modes other than off
2265          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2266          */
2267         switch (mode) {
2268         case DRM_MODE_DPMS_ON:
2269         case DRM_MODE_DPMS_STANDBY:
2270         case DRM_MODE_DPMS_SUSPEND:
2271                 intel_update_watermarks(dev);
2272
2273                 /* Enable the DPLL */
2274                 temp = I915_READ(dpll_reg);
2275                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2276                         I915_WRITE(dpll_reg, temp);
2277                         I915_READ(dpll_reg);
2278                         /* Wait for the clocks to stabilize. */
2279                         udelay(150);
2280                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2281                         I915_READ(dpll_reg);
2282                         /* Wait for the clocks to stabilize. */
2283                         udelay(150);
2284                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2285                         I915_READ(dpll_reg);
2286                         /* Wait for the clocks to stabilize. */
2287                         udelay(150);
2288                 }
2289
2290                 /* Enable the pipe */
2291                 temp = I915_READ(pipeconf_reg);
2292                 if ((temp & PIPEACONF_ENABLE) == 0)
2293                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2294
2295                 /* Enable the plane */
2296                 temp = I915_READ(dspcntr_reg);
2297                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2298                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2299                         /* Flush the plane changes */
2300                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2301                 }
2302
2303                 intel_crtc_load_lut(crtc);
2304
2305                 if ((IS_I965G(dev) || plane == 0))
2306                         intel_update_fbc(crtc, &crtc->mode);
2307
2308                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2309                 intel_crtc_dpms_overlay(intel_crtc, true);
2310         break;
2311         case DRM_MODE_DPMS_OFF:
2312                 intel_update_watermarks(dev);
2313
2314                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2315                 intel_crtc_dpms_overlay(intel_crtc, false);
2316                 drm_vblank_off(dev, pipe);
2317
2318                 if (dev_priv->cfb_plane == plane &&
2319                     dev_priv->display.disable_fbc)
2320                         dev_priv->display.disable_fbc(dev);
2321
2322                 /* Disable the VGA plane that we never use */
2323                 i915_disable_vga(dev);
2324
2325                 /* Disable display plane */
2326                 temp = I915_READ(dspcntr_reg);
2327                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2328                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2329                         /* Flush the plane changes */
2330                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2331                         I915_READ(dspbase_reg);
2332                 }
2333
2334                 if (!IS_I9XX(dev)) {
2335                         /* Wait for vblank for the disable to take effect */
2336                         intel_wait_for_vblank(dev);
2337                 }
2338
2339                 /* Don't disable pipe A or pipe A PLLs if needed */
2340                 if (pipeconf_reg == PIPEACONF &&
2341                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2342                         goto skip_pipe_off;
2343
2344                 /* Next, disable display pipes */
2345                 temp = I915_READ(pipeconf_reg);
2346                 if ((temp & PIPEACONF_ENABLE) != 0) {
2347                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2348                         I915_READ(pipeconf_reg);
2349                 }
2350
2351                 /* Wait for vblank for the disable to take effect. */
2352                 intel_wait_for_vblank(dev);
2353
2354                 temp = I915_READ(dpll_reg);
2355                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2356                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2357                         I915_READ(dpll_reg);
2358                 }
2359         skip_pipe_off:
2360                 /* Wait for the clocks to turn off. */
2361                 udelay(150);
2362                 break;
2363         }
2364 }
2365
2366 /**
2367  * Sets the power management mode of the pipe and plane.
2368  *
2369  * This code should probably grow support for turning the cursor off and back
2370  * on appropriately at the same time as we're turning the pipe off/on.
2371  */
2372 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2373 {
2374         struct drm_device *dev = crtc->dev;
2375         struct drm_i915_private *dev_priv = dev->dev_private;
2376         struct drm_i915_master_private *master_priv;
2377         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2378         int pipe = intel_crtc->pipe;
2379         bool enabled;
2380
2381         dev_priv->display.dpms(crtc, mode);
2382
2383         intel_crtc->dpms_mode = mode;
2384
2385         if (!dev->primary->master)
2386                 return;
2387
2388         master_priv = dev->primary->master->driver_priv;
2389         if (!master_priv->sarea_priv)
2390                 return;
2391
2392         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2393
2394         switch (pipe) {
2395         case 0:
2396                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2397                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2398                 break;
2399         case 1:
2400                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2401                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2402                 break;
2403         default:
2404                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2405                 break;
2406         }
2407 }
2408
2409 static void intel_crtc_prepare (struct drm_crtc *crtc)
2410 {
2411         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2412         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2413 }
2414
2415 static void intel_crtc_commit (struct drm_crtc *crtc)
2416 {
2417         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2418         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2419 }
2420
2421 void intel_encoder_prepare (struct drm_encoder *encoder)
2422 {
2423         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2424         /* lvds has its own version of prepare see intel_lvds_prepare */
2425         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2426 }
2427
2428 void intel_encoder_commit (struct drm_encoder *encoder)
2429 {
2430         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2431         /* lvds has its own version of commit see intel_lvds_commit */
2432         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2433 }
2434
2435 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2436                                   struct drm_display_mode *mode,
2437                                   struct drm_display_mode *adjusted_mode)
2438 {
2439         struct drm_device *dev = crtc->dev;
2440         if (HAS_PCH_SPLIT(dev)) {
2441                 /* FDI link clock is fixed at 2.7G */
2442                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2443                         return false;
2444         }
2445         return true;
2446 }
2447
2448 static int i945_get_display_clock_speed(struct drm_device *dev)
2449 {
2450         return 400000;
2451 }
2452
2453 static int i915_get_display_clock_speed(struct drm_device *dev)
2454 {
2455         return 333000;
2456 }
2457
2458 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2459 {
2460         return 200000;
2461 }
2462
2463 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2464 {
2465         u16 gcfgc = 0;
2466
2467         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2468
2469         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2470                 return 133000;
2471         else {
2472                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2473                 case GC_DISPLAY_CLOCK_333_MHZ:
2474                         return 333000;
2475                 default:
2476                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2477                         return 190000;
2478                 }
2479         }
2480 }
2481
2482 static int i865_get_display_clock_speed(struct drm_device *dev)
2483 {
2484         return 266000;
2485 }
2486
2487 static int i855_get_display_clock_speed(struct drm_device *dev)
2488 {
2489         u16 hpllcc = 0;
2490         /* Assume that the hardware is in the high speed state.  This
2491          * should be the default.
2492          */
2493         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2494         case GC_CLOCK_133_200:
2495         case GC_CLOCK_100_200:
2496                 return 200000;
2497         case GC_CLOCK_166_250:
2498                 return 250000;
2499         case GC_CLOCK_100_133:
2500                 return 133000;
2501         }
2502
2503         /* Shouldn't happen */
2504         return 0;
2505 }
2506
2507 static int i830_get_display_clock_speed(struct drm_device *dev)
2508 {
2509         return 133000;
2510 }
2511
2512 /**
2513  * Return the pipe currently connected to the panel fitter,
2514  * or -1 if the panel fitter is not present or not in use
2515  */
2516 int intel_panel_fitter_pipe (struct drm_device *dev)
2517 {
2518         struct drm_i915_private *dev_priv = dev->dev_private;
2519         u32  pfit_control;
2520
2521         /* i830 doesn't have a panel fitter */
2522         if (IS_I830(dev))
2523                 return -1;
2524
2525         pfit_control = I915_READ(PFIT_CONTROL);
2526
2527         /* See if the panel fitter is in use */
2528         if ((pfit_control & PFIT_ENABLE) == 0)
2529                 return -1;
2530
2531         /* 965 can place panel fitter on either pipe */
2532         if (IS_I965G(dev))
2533                 return (pfit_control >> 29) & 0x3;
2534
2535         /* older chips can only use pipe 1 */
2536         return 1;
2537 }
2538
2539 struct fdi_m_n {
2540         u32        tu;
2541         u32        gmch_m;
2542         u32        gmch_n;
2543         u32        link_m;
2544         u32        link_n;
2545 };
2546
2547 static void
2548 fdi_reduce_ratio(u32 *num, u32 *den)
2549 {
2550         while (*num > 0xffffff || *den > 0xffffff) {
2551                 *num >>= 1;
2552                 *den >>= 1;
2553         }
2554 }
2555
2556 #define DATA_N 0x800000
2557 #define LINK_N 0x80000
2558
2559 static void
2560 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2561                      int link_clock, struct fdi_m_n *m_n)
2562 {
2563         u64 temp;
2564
2565         m_n->tu = 64; /* default size */
2566
2567         temp = (u64) DATA_N * pixel_clock;
2568         temp = div_u64(temp, link_clock);
2569         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2570         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2571         m_n->gmch_n = DATA_N;
2572         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2573
2574         temp = (u64) LINK_N * pixel_clock;
2575         m_n->link_m = div_u64(temp, link_clock);
2576         m_n->link_n = LINK_N;
2577         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2578 }
2579
2580
2581 struct intel_watermark_params {
2582         unsigned long fifo_size;
2583         unsigned long max_wm;
2584         unsigned long default_wm;
2585         unsigned long guard_size;
2586         unsigned long cacheline_size;
2587 };
2588
2589 /* Pineview has different values for various configs */
2590 static struct intel_watermark_params pineview_display_wm = {
2591         PINEVIEW_DISPLAY_FIFO,
2592         PINEVIEW_MAX_WM,
2593         PINEVIEW_DFT_WM,
2594         PINEVIEW_GUARD_WM,
2595         PINEVIEW_FIFO_LINE_SIZE
2596 };
2597 static struct intel_watermark_params pineview_display_hplloff_wm = {
2598         PINEVIEW_DISPLAY_FIFO,
2599         PINEVIEW_MAX_WM,
2600         PINEVIEW_DFT_HPLLOFF_WM,
2601         PINEVIEW_GUARD_WM,
2602         PINEVIEW_FIFO_LINE_SIZE
2603 };
2604 static struct intel_watermark_params pineview_cursor_wm = {
2605         PINEVIEW_CURSOR_FIFO,
2606         PINEVIEW_CURSOR_MAX_WM,
2607         PINEVIEW_CURSOR_DFT_WM,
2608         PINEVIEW_CURSOR_GUARD_WM,
2609         PINEVIEW_FIFO_LINE_SIZE,
2610 };
2611 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2612         PINEVIEW_CURSOR_FIFO,
2613         PINEVIEW_CURSOR_MAX_WM,
2614         PINEVIEW_CURSOR_DFT_WM,
2615         PINEVIEW_CURSOR_GUARD_WM,
2616         PINEVIEW_FIFO_LINE_SIZE
2617 };
2618 static struct intel_watermark_params g4x_wm_info = {
2619         G4X_FIFO_SIZE,
2620         G4X_MAX_WM,
2621         G4X_MAX_WM,
2622         2,
2623         G4X_FIFO_LINE_SIZE,
2624 };
2625 static struct intel_watermark_params g4x_cursor_wm_info = {
2626         I965_CURSOR_FIFO,
2627         I965_CURSOR_MAX_WM,
2628         I965_CURSOR_DFT_WM,
2629         2,
2630         G4X_FIFO_LINE_SIZE,
2631 };
2632 static struct intel_watermark_params i965_cursor_wm_info = {
2633         I965_CURSOR_FIFO,
2634         I965_CURSOR_MAX_WM,
2635         I965_CURSOR_DFT_WM,
2636         2,
2637         I915_FIFO_LINE_SIZE,
2638 };
2639 static struct intel_watermark_params i945_wm_info = {
2640         I945_FIFO_SIZE,
2641         I915_MAX_WM,
2642         1,
2643         2,
2644         I915_FIFO_LINE_SIZE
2645 };
2646 static struct intel_watermark_params i915_wm_info = {
2647         I915_FIFO_SIZE,
2648         I915_MAX_WM,
2649         1,
2650         2,
2651         I915_FIFO_LINE_SIZE
2652 };
2653 static struct intel_watermark_params i855_wm_info = {
2654         I855GM_FIFO_SIZE,
2655         I915_MAX_WM,
2656         1,
2657         2,
2658         I830_FIFO_LINE_SIZE
2659 };
2660 static struct intel_watermark_params i830_wm_info = {
2661         I830_FIFO_SIZE,
2662         I915_MAX_WM,
2663         1,
2664         2,
2665         I830_FIFO_LINE_SIZE
2666 };
2667
2668 static struct intel_watermark_params ironlake_display_wm_info = {
2669         ILK_DISPLAY_FIFO,
2670         ILK_DISPLAY_MAXWM,
2671         ILK_DISPLAY_DFTWM,
2672         2,
2673         ILK_FIFO_LINE_SIZE
2674 };
2675
2676 static struct intel_watermark_params ironlake_cursor_wm_info = {
2677         ILK_CURSOR_FIFO,
2678         ILK_CURSOR_MAXWM,
2679         ILK_CURSOR_DFTWM,
2680         2,
2681         ILK_FIFO_LINE_SIZE
2682 };
2683
2684 static struct intel_watermark_params ironlake_display_srwm_info = {
2685         ILK_DISPLAY_SR_FIFO,
2686         ILK_DISPLAY_MAX_SRWM,
2687         ILK_DISPLAY_DFT_SRWM,
2688         2,
2689         ILK_FIFO_LINE_SIZE
2690 };
2691
2692 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2693         ILK_CURSOR_SR_FIFO,
2694         ILK_CURSOR_MAX_SRWM,
2695         ILK_CURSOR_DFT_SRWM,
2696         2,
2697         ILK_FIFO_LINE_SIZE
2698 };
2699
2700 /**
2701  * intel_calculate_wm - calculate watermark level
2702  * @clock_in_khz: pixel clock
2703  * @wm: chip FIFO params
2704  * @pixel_size: display pixel size
2705  * @latency_ns: memory latency for the platform
2706  *
2707  * Calculate the watermark level (the level at which the display plane will
2708  * start fetching from memory again).  Each chip has a different display
2709  * FIFO size and allocation, so the caller needs to figure that out and pass
2710  * in the correct intel_watermark_params structure.
2711  *
2712  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2713  * on the pixel size.  When it reaches the watermark level, it'll start
2714  * fetching FIFO line sized based chunks from memory until the FIFO fills
2715  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2716  * will occur, and a display engine hang could result.
2717  */
2718 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2719                                         struct intel_watermark_params *wm,
2720                                         int pixel_size,
2721                                         unsigned long latency_ns)
2722 {
2723         long entries_required, wm_size;
2724
2725         /*
2726          * Note: we need to make sure we don't overflow for various clock &
2727          * latency values.
2728          * clocks go from a few thousand to several hundred thousand.
2729          * latency is usually a few thousand
2730          */
2731         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2732                 1000;
2733         entries_required /= wm->cacheline_size;
2734
2735         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2736
2737         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2738
2739         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2740
2741         /* Don't promote wm_size to unsigned... */
2742         if (wm_size > (long)wm->max_wm)
2743                 wm_size = wm->max_wm;
2744         if (wm_size <= 0)
2745                 wm_size = wm->default_wm;
2746         return wm_size;
2747 }
2748
2749 struct cxsr_latency {
2750         int is_desktop;
2751         int is_ddr3;
2752         unsigned long fsb_freq;
2753         unsigned long mem_freq;
2754         unsigned long display_sr;
2755         unsigned long display_hpll_disable;
2756         unsigned long cursor_sr;
2757         unsigned long cursor_hpll_disable;
2758 };
2759
2760 static struct cxsr_latency cxsr_latency_table[] = {
2761         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2762         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2763         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2764         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2765         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2766
2767         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2768         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2769         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2770         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2771         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2772
2773         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2774         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2775         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2776         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2777         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2778
2779         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2780         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2781         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2782         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2783         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2784
2785         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2786         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2787         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2788         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2789         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2790
2791         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2792         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2793         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2794         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2795         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2796 };
2797
2798 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2799                                                    int fsb, int mem)
2800 {
2801         int i;
2802         struct cxsr_latency *latency;
2803
2804         if (fsb == 0 || mem == 0)
2805                 return NULL;
2806
2807         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2808                 latency = &cxsr_latency_table[i];
2809                 if (is_desktop == latency->is_desktop &&
2810                     is_ddr3 == latency->is_ddr3 &&
2811                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2812                         return latency;
2813         }
2814
2815         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2816
2817         return NULL;
2818 }
2819
2820 static void pineview_disable_cxsr(struct drm_device *dev)
2821 {
2822         struct drm_i915_private *dev_priv = dev->dev_private;
2823         u32 reg;
2824
2825         /* deactivate cxsr */
2826         reg = I915_READ(DSPFW3);
2827         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2828         I915_WRITE(DSPFW3, reg);
2829         DRM_INFO("Big FIFO is disabled\n");
2830 }
2831
2832 /*
2833  * Latency for FIFO fetches is dependent on several factors:
2834  *   - memory configuration (speed, channels)
2835  *   - chipset
2836  *   - current MCH state
2837  * It can be fairly high in some situations, so here we assume a fairly
2838  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2839  * set this value too high, the FIFO will fetch frequently to stay full)
2840  * and power consumption (set it too low to save power and we might see
2841  * FIFO underruns and display "flicker").
2842  *
2843  * A value of 5us seems to be a good balance; safe for very low end
2844  * platforms but not overly aggressive on lower latency configs.
2845  */
2846 static const int latency_ns = 5000;
2847
2848 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2849 {
2850         struct drm_i915_private *dev_priv = dev->dev_private;
2851         uint32_t dsparb = I915_READ(DSPARB);
2852         int size;
2853
2854         if (plane == 0)
2855                 size = dsparb & 0x7f;
2856         else
2857                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2858                         (dsparb & 0x7f);
2859
2860         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2861                         plane ? "B" : "A", size);
2862
2863         return size;
2864 }
2865
2866 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2867 {
2868         struct drm_i915_private *dev_priv = dev->dev_private;
2869         uint32_t dsparb = I915_READ(DSPARB);
2870         int size;
2871
2872         if (plane == 0)
2873                 size = dsparb & 0x1ff;
2874         else
2875                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2876                         (dsparb & 0x1ff);
2877         size >>= 1; /* Convert to cachelines */
2878
2879         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2880                         plane ? "B" : "A", size);
2881
2882         return size;
2883 }
2884
2885 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2886 {
2887         struct drm_i915_private *dev_priv = dev->dev_private;
2888         uint32_t dsparb = I915_READ(DSPARB);
2889         int size;
2890
2891         size = dsparb & 0x7f;
2892         size >>= 2; /* Convert to cachelines */
2893
2894         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2895                         plane ? "B" : "A",
2896                   size);
2897
2898         return size;
2899 }
2900
2901 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2902 {
2903         struct drm_i915_private *dev_priv = dev->dev_private;
2904         uint32_t dsparb = I915_READ(DSPARB);
2905         int size;
2906
2907         size = dsparb & 0x7f;
2908         size >>= 1; /* Convert to cachelines */
2909
2910         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2911                         plane ? "B" : "A", size);
2912
2913         return size;
2914 }
2915
2916 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2917                           int planeb_clock, int sr_hdisplay, int unused,
2918                           int pixel_size)
2919 {
2920         struct drm_i915_private *dev_priv = dev->dev_private;
2921         u32 reg;
2922         unsigned long wm;
2923         struct cxsr_latency *latency;
2924         int sr_clock;
2925
2926         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2927                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2928         if (!latency) {
2929                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2930                 pineview_disable_cxsr(dev);
2931                 return;
2932         }
2933
2934         if (!planea_clock || !planeb_clock) {
2935                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2936
2937                 /* Display SR */
2938                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2939                                         pixel_size, latency->display_sr);
2940                 reg = I915_READ(DSPFW1);
2941                 reg &= ~DSPFW_SR_MASK;
2942                 reg |= wm << DSPFW_SR_SHIFT;
2943                 I915_WRITE(DSPFW1, reg);
2944                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2945
2946                 /* cursor SR */
2947                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2948                                         pixel_size, latency->cursor_sr);
2949                 reg = I915_READ(DSPFW3);
2950                 reg &= ~DSPFW_CURSOR_SR_MASK;
2951                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2952                 I915_WRITE(DSPFW3, reg);
2953
2954                 /* Display HPLL off SR */
2955                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2956                                         pixel_size, latency->display_hpll_disable);
2957                 reg = I915_READ(DSPFW3);
2958                 reg &= ~DSPFW_HPLL_SR_MASK;
2959                 reg |= wm & DSPFW_HPLL_SR_MASK;
2960                 I915_WRITE(DSPFW3, reg);
2961
2962                 /* cursor HPLL off SR */
2963                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2964                                         pixel_size, latency->cursor_hpll_disable);
2965                 reg = I915_READ(DSPFW3);
2966                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2967                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2968                 I915_WRITE(DSPFW3, reg);
2969                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2970
2971                 /* activate cxsr */
2972                 reg = I915_READ(DSPFW3);
2973                 reg |= PINEVIEW_SELF_REFRESH_EN;
2974                 I915_WRITE(DSPFW3, reg);
2975                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2976         } else {
2977                 pineview_disable_cxsr(dev);
2978                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2979         }
2980 }
2981
2982 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2983                           int planeb_clock, int sr_hdisplay, int sr_htotal,
2984                           int pixel_size)
2985 {
2986         struct drm_i915_private *dev_priv = dev->dev_private;
2987         int total_size, cacheline_size;
2988         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2989         struct intel_watermark_params planea_params, planeb_params;
2990         unsigned long line_time_us;
2991         int sr_clock, sr_entries = 0, entries_required;
2992
2993         /* Create copies of the base settings for each pipe */
2994         planea_params = planeb_params = g4x_wm_info;
2995
2996         /* Grab a couple of global values before we overwrite them */
2997         total_size = planea_params.fifo_size;
2998         cacheline_size = planea_params.cacheline_size;
2999
3000         /*
3001          * Note: we need to make sure we don't overflow for various clock &
3002          * latency values.
3003          * clocks go from a few thousand to several hundred thousand.
3004          * latency is usually a few thousand
3005          */
3006         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3007                 1000;
3008         entries_required /= G4X_FIFO_LINE_SIZE;
3009         planea_wm = entries_required + planea_params.guard_size;
3010
3011         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3012                 1000;
3013         entries_required /= G4X_FIFO_LINE_SIZE;
3014         planeb_wm = entries_required + planeb_params.guard_size;
3015
3016         cursora_wm = cursorb_wm = 16;
3017         cursor_sr = 32;
3018
3019         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3020
3021         /* Calc sr entries for one plane configs */
3022         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3023                 /* self-refresh has much higher latency */
3024                 static const int sr_latency_ns = 12000;
3025
3026                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3027                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3028
3029                 /* Use ns/us then divide to preserve precision */
3030                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3031                               pixel_size * sr_hdisplay;
3032                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3033
3034                 entries_required = (((sr_latency_ns / line_time_us) +
3035                                      1000) / 1000) * pixel_size * 64;
3036                 entries_required = roundup(entries_required /
3037                                            g4x_cursor_wm_info.cacheline_size, 1);
3038                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3039
3040                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3041                         cursor_sr = g4x_cursor_wm_info.max_wm;
3042                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3043                               "cursor %d\n", sr_entries, cursor_sr);
3044
3045                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3046         } else {
3047                 /* Turn off self refresh if both pipes are enabled */
3048                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3049                                         & ~FW_BLC_SELF_EN);
3050         }
3051
3052         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3053                   planea_wm, planeb_wm, sr_entries);
3054
3055         planea_wm &= 0x3f;
3056         planeb_wm &= 0x3f;
3057
3058         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3059                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3060                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3061         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3062                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3063         /* HPLL off in SR has some issues on G4x... disable it */
3064         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3065                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3066 }
3067
3068 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3069                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3070                            int pixel_size)
3071 {
3072         struct drm_i915_private *dev_priv = dev->dev_private;
3073         unsigned long line_time_us;
3074         int sr_clock, sr_entries, srwm = 1;
3075         int cursor_sr = 16;
3076
3077         /* Calc sr entries for one plane configs */
3078         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3079                 /* self-refresh has much higher latency */
3080                 static const int sr_latency_ns = 12000;
3081
3082                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3083                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3084
3085                 /* Use ns/us then divide to preserve precision */
3086                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3087                               pixel_size * sr_hdisplay;
3088                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
3089                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3090                 srwm = I965_FIFO_SIZE - sr_entries;
3091                 if (srwm < 0)
3092                         srwm = 1;
3093                 srwm &= 0x1ff;
3094
3095                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3096                              pixel_size * 64;
3097                 sr_entries = roundup(sr_entries /
3098                                      i965_cursor_wm_info.cacheline_size, 1);
3099                 cursor_sr = i965_cursor_wm_info.fifo_size -
3100                             (sr_entries + i965_cursor_wm_info.guard_size);
3101
3102                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3103                         cursor_sr = i965_cursor_wm_info.max_wm;
3104
3105                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3106                               "cursor %d\n", srwm, cursor_sr);
3107
3108                 if (IS_I965GM(dev))
3109                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3110         } else {
3111                 /* Turn off self refresh if both pipes are enabled */
3112                 if (IS_I965GM(dev))
3113                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3114                                    & ~FW_BLC_SELF_EN);
3115         }
3116
3117         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3118                       srwm);
3119
3120         /* 965 has limitations... */
3121         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3122                    (8 << 0));
3123         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3124         /* update cursor SR watermark */
3125         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3126 }
3127
3128 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3129                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3130                            int pixel_size)
3131 {
3132         struct drm_i915_private *dev_priv = dev->dev_private;
3133         uint32_t fwater_lo;
3134         uint32_t fwater_hi;
3135         int total_size, cacheline_size, cwm, srwm = 1;
3136         int planea_wm, planeb_wm;
3137         struct intel_watermark_params planea_params, planeb_params;
3138         unsigned long line_time_us;
3139         int sr_clock, sr_entries = 0;
3140
3141         /* Create copies of the base settings for each pipe */
3142         if (IS_I965GM(dev) || IS_I945GM(dev))
3143                 planea_params = planeb_params = i945_wm_info;
3144         else if (IS_I9XX(dev))
3145                 planea_params = planeb_params = i915_wm_info;
3146         else
3147                 planea_params = planeb_params = i855_wm_info;
3148
3149         /* Grab a couple of global values before we overwrite them */
3150         total_size = planea_params.fifo_size;
3151         cacheline_size = planea_params.cacheline_size;
3152
3153         /* Update per-plane FIFO sizes */
3154         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3155         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3156
3157         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3158                                        pixel_size, latency_ns);
3159         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3160                                        pixel_size, latency_ns);
3161         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3162
3163         /*
3164          * Overlay gets an aggressive default since video jitter is bad.
3165          */
3166         cwm = 2;
3167
3168         /* Calc sr entries for one plane configs */
3169         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3170             (!planea_clock || !planeb_clock)) {
3171                 /* self-refresh has much higher latency */
3172                 static const int sr_latency_ns = 6000;
3173
3174                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3175                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3176
3177                 /* Use ns/us then divide to preserve precision */
3178                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3179                               pixel_size * sr_hdisplay;
3180                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3181                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3182                 srwm = total_size - sr_entries;
3183                 if (srwm < 0)
3184                         srwm = 1;
3185
3186                 if (IS_I945G(dev) || IS_I945GM(dev))
3187                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3188                 else if (IS_I915GM(dev)) {
3189                         /* 915M has a smaller SRWM field */
3190                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3191                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3192                 }
3193         } else {
3194                 /* Turn off self refresh if both pipes are enabled */
3195                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3196                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3197                                    & ~FW_BLC_SELF_EN);
3198                 } else if (IS_I915GM(dev)) {
3199                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3200                 }
3201         }
3202
3203         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3204                   planea_wm, planeb_wm, cwm, srwm);
3205
3206         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3207         fwater_hi = (cwm & 0x1f);
3208
3209         /* Set request length to 8 cachelines per fetch */
3210         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3211         fwater_hi = fwater_hi | (1 << 8);
3212
3213         I915_WRITE(FW_BLC, fwater_lo);
3214         I915_WRITE(FW_BLC2, fwater_hi);
3215 }
3216
3217 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3218                            int unused2, int unused3, int pixel_size)
3219 {
3220         struct drm_i915_private *dev_priv = dev->dev_private;
3221         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3222         int planea_wm;
3223
3224         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3225
3226         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3227                                        pixel_size, latency_ns);
3228         fwater_lo |= (3<<8) | planea_wm;
3229
3230         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3231
3232         I915_WRITE(FW_BLC, fwater_lo);
3233 }
3234
3235 #define ILK_LP0_PLANE_LATENCY           700
3236 #define ILK_LP0_CURSOR_LATENCY          1300
3237
3238 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3239                        int planeb_clock, int sr_hdisplay, int sr_htotal,
3240                        int pixel_size)
3241 {
3242         struct drm_i915_private *dev_priv = dev->dev_private;
3243         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3244         int sr_wm, cursor_wm;
3245         unsigned long line_time_us;
3246         int sr_clock, entries_required;
3247         u32 reg_value;
3248         int line_count;
3249         int planea_htotal = 0, planeb_htotal = 0;
3250         struct drm_crtc *crtc;
3251         struct intel_crtc *intel_crtc;
3252
3253         /* Need htotal for all active display plane */
3254         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3255                 intel_crtc = to_intel_crtc(crtc);
3256                 if (crtc->enabled) {
3257                         if (intel_crtc->plane == 0)
3258                                 planea_htotal = crtc->mode.htotal;
3259                         else
3260                                 planeb_htotal = crtc->mode.htotal;
3261                 }
3262         }
3263
3264         /* Calculate and update the watermark for plane A */
3265         if (planea_clock) {
3266                 entries_required = ((planea_clock / 1000) * pixel_size *
3267                                      ILK_LP0_PLANE_LATENCY) / 1000;
3268                 entries_required = DIV_ROUND_UP(entries_required,
3269                                    ironlake_display_wm_info.cacheline_size);
3270                 planea_wm = entries_required +
3271                             ironlake_display_wm_info.guard_size;
3272
3273                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3274                         planea_wm = ironlake_display_wm_info.max_wm;
3275
3276                 /* Use the large buffer method to calculate cursor watermark */
3277                 line_time_us = (planea_htotal * 1000) / planea_clock;
3278
3279                 /* Use ns/us then divide to preserve precision */
3280                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3281
3282                 /* calculate the cursor watermark for cursor A */
3283                 entries_required = line_count * 64 * pixel_size;
3284                 entries_required = DIV_ROUND_UP(entries_required,
3285                                                 ironlake_cursor_wm_info.cacheline_size);
3286                 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3287                 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3288                         cursora_wm = ironlake_cursor_wm_info.max_wm;
3289
3290                 reg_value = I915_READ(WM0_PIPEA_ILK);
3291                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3292                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3293                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3294                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3295                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3296                                 "cursor: %d\n", planea_wm, cursora_wm);
3297         }
3298         /* Calculate and update the watermark for plane B */
3299         if (planeb_clock) {
3300                 entries_required = ((planeb_clock / 1000) * pixel_size *
3301                                      ILK_LP0_PLANE_LATENCY) / 1000;
3302                 entries_required = DIV_ROUND_UP(entries_required,
3303                                    ironlake_display_wm_info.cacheline_size);
3304                 planeb_wm = entries_required +
3305                             ironlake_display_wm_info.guard_size;
3306
3307                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3308                         planeb_wm = ironlake_display_wm_info.max_wm;
3309
3310                 /* Use the large buffer method to calculate cursor watermark */
3311                 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3312
3313                 /* Use ns/us then divide to preserve precision */
3314                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3315
3316                 /* calculate the cursor watermark for cursor B */
3317                 entries_required = line_count * 64 * pixel_size;
3318                 entries_required = DIV_ROUND_UP(entries_required,
3319                                                 ironlake_cursor_wm_info.cacheline_size);
3320                 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3321                 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3322                         cursorb_wm = ironlake_cursor_wm_info.max_wm;
3323
3324                 reg_value = I915_READ(WM0_PIPEB_ILK);
3325                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3326                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3327                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3328                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3329                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3330                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3331         }
3332
3333         /*
3334          * Calculate and update the self-refresh watermark only when one
3335          * display plane is used.
3336          */
3337         if (!planea_clock || !planeb_clock) {
3338
3339                 /* Read the self-refresh latency. The unit is 0.5us */
3340                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3341
3342                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3343                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3344
3345                 /* Use ns/us then divide to preserve precision */
3346                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3347                                / 1000;
3348
3349                 /* calculate the self-refresh watermark for display plane */
3350                 entries_required = line_count * sr_hdisplay * pixel_size;
3351                 entries_required = DIV_ROUND_UP(entries_required,
3352                                    ironlake_display_srwm_info.cacheline_size);
3353                 sr_wm = entries_required +
3354                         ironlake_display_srwm_info.guard_size;
3355
3356                 /* calculate the self-refresh watermark for display cursor */
3357                 entries_required = line_count * pixel_size * 64;
3358                 entries_required = DIV_ROUND_UP(entries_required,
3359                                    ironlake_cursor_srwm_info.cacheline_size);
3360                 cursor_wm = entries_required +
3361                             ironlake_cursor_srwm_info.guard_size;
3362
3363                 /* configure watermark and enable self-refresh */
3364                 reg_value = I915_READ(WM1_LP_ILK);
3365                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3366                                WM1_LP_CURSOR_MASK);
3367                 reg_value |= WM1_LP_SR_EN |
3368                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3369                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3370
3371                 I915_WRITE(WM1_LP_ILK, reg_value);
3372                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3373                                 "cursor %d\n", sr_wm, cursor_wm);
3374
3375         } else {
3376                 /* Turn off self refresh if both pipes are enabled */
3377                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3378         }
3379 }
3380 /**
3381  * intel_update_watermarks - update FIFO watermark values based on current modes
3382  *
3383  * Calculate watermark values for the various WM regs based on current mode
3384  * and plane configuration.
3385  *
3386  * There are several cases to deal with here:
3387  *   - normal (i.e. non-self-refresh)
3388  *   - self-refresh (SR) mode
3389  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3390  *   - lines are small relative to FIFO size (buffer can hold more than 2
3391  *     lines), so need to account for TLB latency
3392  *
3393  *   The normal calculation is:
3394  *     watermark = dotclock * bytes per pixel * latency
3395  *   where latency is platform & configuration dependent (we assume pessimal
3396  *   values here).
3397  *
3398  *   The SR calculation is:
3399  *     watermark = (trunc(latency/line time)+1) * surface width *
3400  *       bytes per pixel
3401  *   where
3402  *     line time = htotal / dotclock
3403  *     surface width = hdisplay for normal plane and 64 for cursor
3404  *   and latency is assumed to be high, as above.
3405  *
3406  * The final value programmed to the register should always be rounded up,
3407  * and include an extra 2 entries to account for clock crossings.
3408  *
3409  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3410  * to set the non-SR watermarks to 8.
3411   */
3412 static void intel_update_watermarks(struct drm_device *dev)
3413 {
3414         struct drm_i915_private *dev_priv = dev->dev_private;
3415         struct drm_crtc *crtc;
3416         struct intel_crtc *intel_crtc;
3417         int sr_hdisplay = 0;
3418         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3419         int enabled = 0, pixel_size = 0;
3420         int sr_htotal = 0;
3421
3422         if (!dev_priv->display.update_wm)
3423                 return;
3424
3425         /* Get the clock config from both planes */
3426         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3427                 intel_crtc = to_intel_crtc(crtc);
3428                 if (crtc->enabled) {
3429                         enabled++;
3430                         if (intel_crtc->plane == 0) {
3431                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3432                                           intel_crtc->pipe, crtc->mode.clock);
3433                                 planea_clock = crtc->mode.clock;
3434                         } else {
3435                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3436                                           intel_crtc->pipe, crtc->mode.clock);
3437                                 planeb_clock = crtc->mode.clock;
3438                         }
3439                         sr_hdisplay = crtc->mode.hdisplay;
3440                         sr_clock = crtc->mode.clock;
3441                         sr_htotal = crtc->mode.htotal;
3442                         if (crtc->fb)
3443                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3444                         else
3445                                 pixel_size = 4; /* by default */
3446                 }
3447         }
3448
3449         if (enabled <= 0)
3450                 return;
3451
3452         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3453                                     sr_hdisplay, sr_htotal, pixel_size);
3454 }
3455
3456 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3457                                struct drm_display_mode *mode,
3458                                struct drm_display_mode *adjusted_mode,
3459                                int x, int y,
3460                                struct drm_framebuffer *old_fb)
3461 {
3462         struct drm_device *dev = crtc->dev;
3463         struct drm_i915_private *dev_priv = dev->dev_private;
3464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3465         int pipe = intel_crtc->pipe;
3466         int plane = intel_crtc->plane;
3467         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3468         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3469         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3470         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3471         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3472         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3473         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3474         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3475         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3476         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3477         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3478         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3479         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3480         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3481         int refclk, num_connectors = 0;
3482         intel_clock_t clock, reduced_clock;
3483         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3484         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3485         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3486         bool is_edp = false;
3487         struct drm_mode_config *mode_config = &dev->mode_config;
3488         struct drm_encoder *encoder;
3489         struct intel_encoder *intel_encoder = NULL;
3490         const intel_limit_t *limit;
3491         int ret;
3492         struct fdi_m_n m_n = {0};
3493         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3494         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3495         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3496         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3497         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3498         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3499         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3500         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3501         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3502         int lvds_reg = LVDS;
3503         u32 temp;
3504         int sdvo_pixel_multiply;
3505         int target_clock;
3506
3507         drm_vblank_pre_modeset(dev, pipe);
3508
3509         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3510
3511                 if (!encoder || encoder->crtc != crtc)
3512                         continue;
3513
3514                 intel_encoder = enc_to_intel_encoder(encoder);
3515
3516                 switch (intel_encoder->type) {
3517                 case INTEL_OUTPUT_LVDS:
3518                         is_lvds = true;
3519                         break;
3520                 case INTEL_OUTPUT_SDVO:
3521                 case INTEL_OUTPUT_HDMI:
3522                         is_sdvo = true;
3523                         if (intel_encoder->needs_tv_clock)
3524                                 is_tv = true;
3525                         break;
3526                 case INTEL_OUTPUT_DVO:
3527                         is_dvo = true;
3528                         break;
3529                 case INTEL_OUTPUT_TVOUT:
3530                         is_tv = true;
3531                         break;
3532                 case INTEL_OUTPUT_ANALOG:
3533                         is_crt = true;
3534                         break;
3535                 case INTEL_OUTPUT_DISPLAYPORT:
3536                         is_dp = true;
3537                         break;
3538                 case INTEL_OUTPUT_EDP:
3539                         is_edp = true;
3540                         break;
3541                 }
3542
3543                 num_connectors++;
3544         }
3545
3546         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3547                 refclk = dev_priv->lvds_ssc_freq * 1000;
3548                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3549                                         refclk / 1000);
3550         } else if (IS_I9XX(dev)) {
3551                 refclk = 96000;
3552                 if (HAS_PCH_SPLIT(dev))
3553                         refclk = 120000; /* 120Mhz refclk */
3554         } else {
3555                 refclk = 48000;
3556         }
3557
3558
3559         /*
3560          * Returns a set of divisors for the desired target clock with the given
3561          * refclk, or FALSE.  The returned values represent the clock equation:
3562          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3563          */
3564         limit = intel_limit(crtc);
3565         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3566         if (!ok) {
3567                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3568                 drm_vblank_post_modeset(dev, pipe);
3569                 return -EINVAL;
3570         }
3571
3572         if (is_lvds && dev_priv->lvds_downclock_avail) {
3573                 has_reduced_clock = limit->find_pll(limit, crtc,
3574                                                             dev_priv->lvds_downclock,
3575                                                             refclk,
3576                                                             &reduced_clock);
3577                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3578                         /*
3579                          * If the different P is found, it means that we can't
3580                          * switch the display clock by using the FP0/FP1.
3581                          * In such case we will disable the LVDS downclock
3582                          * feature.
3583                          */
3584                         DRM_DEBUG_KMS("Different P is found for "
3585                                                 "LVDS clock/downclock\n");
3586                         has_reduced_clock = 0;
3587                 }
3588         }
3589         /* SDVO TV has fixed PLL values depend on its clock range,
3590            this mirrors vbios setting. */
3591         if (is_sdvo && is_tv) {
3592                 if (adjusted_mode->clock >= 100000
3593                                 && adjusted_mode->clock < 140500) {
3594                         clock.p1 = 2;
3595                         clock.p2 = 10;
3596                         clock.n = 3;
3597                         clock.m1 = 16;
3598                         clock.m2 = 8;
3599                 } else if (adjusted_mode->clock >= 140500
3600                                 && adjusted_mode->clock <= 200000) {
3601                         clock.p1 = 1;
3602                         clock.p2 = 10;
3603                         clock.n = 6;
3604                         clock.m1 = 12;
3605                         clock.m2 = 8;
3606                 }
3607         }
3608
3609         /* FDI link */
3610         if (HAS_PCH_SPLIT(dev)) {
3611                 int lane = 0, link_bw, bpp;
3612                 /* eDP doesn't require FDI link, so just set DP M/N
3613                    according to current link config */
3614                 if (is_edp) {
3615                         target_clock = mode->clock;
3616                         intel_edp_link_config(intel_encoder,
3617                                         &lane, &link_bw);
3618                 } else {
3619                         /* DP over FDI requires target mode clock
3620                            instead of link clock */
3621                         if (is_dp)
3622                                 target_clock = mode->clock;
3623                         else
3624                                 target_clock = adjusted_mode->clock;
3625                         link_bw = 270000;
3626                 }
3627
3628                 /* determine panel color depth */
3629                 temp = I915_READ(pipeconf_reg);
3630                 temp &= ~PIPE_BPC_MASK;
3631                 if (is_lvds) {
3632                         int lvds_reg = I915_READ(PCH_LVDS);
3633                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3634                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3635                                 temp |= PIPE_8BPC;
3636                         else
3637                                 temp |= PIPE_6BPC;
3638                 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3639                         switch (dev_priv->edp_bpp/3) {
3640                         case 8:
3641                                 temp |= PIPE_8BPC;
3642                                 break;
3643                         case 10:
3644                                 temp |= PIPE_10BPC;
3645                                 break;
3646                         case 6:
3647                                 temp |= PIPE_6BPC;
3648                                 break;
3649                         case 12:
3650                                 temp |= PIPE_12BPC;
3651                                 break;
3652                         }
3653                 } else
3654                         temp |= PIPE_8BPC;
3655                 I915_WRITE(pipeconf_reg, temp);
3656                 I915_READ(pipeconf_reg);
3657
3658                 switch (temp & PIPE_BPC_MASK) {
3659                 case PIPE_8BPC:
3660                         bpp = 24;
3661                         break;
3662                 case PIPE_10BPC:
3663                         bpp = 30;
3664                         break;
3665                 case PIPE_6BPC:
3666                         bpp = 18;
3667                         break;
3668                 case PIPE_12BPC:
3669                         bpp = 36;
3670                         break;
3671                 default:
3672                         DRM_ERROR("unknown pipe bpc value\n");
3673                         bpp = 24;
3674                 }
3675
3676                 if (!lane) {
3677                         /*
3678                          * Account for spread spectrum to avoid
3679                          * oversubscribing the link. Max center spread
3680                          * is 2.5%; use 5% for safety's sake.
3681                          */
3682                         u32 bps = target_clock * bpp * 21 / 20;
3683                         lane = bps / (link_bw * 8) + 1;
3684                 }
3685
3686                 intel_crtc->fdi_lanes = lane;
3687
3688                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3689         }
3690
3691         /* Ironlake: try to setup display ref clock before DPLL
3692          * enabling. This is only under driver's control after
3693          * PCH B stepping, previous chipset stepping should be
3694          * ignoring this setting.
3695          */
3696         if (HAS_PCH_SPLIT(dev)) {
3697                 temp = I915_READ(PCH_DREF_CONTROL);
3698                 /* Always enable nonspread source */
3699                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3700                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3701                 I915_WRITE(PCH_DREF_CONTROL, temp);
3702                 POSTING_READ(PCH_DREF_CONTROL);
3703
3704                 temp &= ~DREF_SSC_SOURCE_MASK;
3705                 temp |= DREF_SSC_SOURCE_ENABLE;
3706                 I915_WRITE(PCH_DREF_CONTROL, temp);
3707                 POSTING_READ(PCH_DREF_CONTROL);
3708
3709                 udelay(200);
3710
3711                 if (is_edp) {
3712                         if (dev_priv->lvds_use_ssc) {
3713                                 temp |= DREF_SSC1_ENABLE;
3714                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3715                                 POSTING_READ(PCH_DREF_CONTROL);
3716
3717                                 udelay(200);
3718
3719                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3720                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3721                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3722                                 POSTING_READ(PCH_DREF_CONTROL);
3723                         } else {
3724                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3725                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3726                                 POSTING_READ(PCH_DREF_CONTROL);
3727                         }
3728                 }
3729         }
3730
3731         if (IS_PINEVIEW(dev)) {
3732                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3733                 if (has_reduced_clock)
3734                         fp2 = (1 << reduced_clock.n) << 16 |
3735                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3736         } else {
3737                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3738                 if (has_reduced_clock)
3739                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3740                                 reduced_clock.m2;
3741         }
3742
3743         if (!HAS_PCH_SPLIT(dev))
3744                 dpll = DPLL_VGA_MODE_DIS;
3745
3746         if (IS_I9XX(dev)) {
3747                 if (is_lvds)
3748                         dpll |= DPLLB_MODE_LVDS;
3749                 else
3750                         dpll |= DPLLB_MODE_DAC_SERIAL;
3751                 if (is_sdvo) {
3752                         dpll |= DPLL_DVO_HIGH_SPEED;
3753                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3754                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3755                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3756                         else if (HAS_PCH_SPLIT(dev))
3757                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3758                 }
3759                 if (is_dp)
3760                         dpll |= DPLL_DVO_HIGH_SPEED;
3761
3762                 /* compute bitmask from p1 value */
3763                 if (IS_PINEVIEW(dev))
3764                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3765                 else {
3766                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3767                         /* also FPA1 */
3768                         if (HAS_PCH_SPLIT(dev))
3769                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3770                         if (IS_G4X(dev) && has_reduced_clock)
3771                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3772                 }
3773                 switch (clock.p2) {
3774                 case 5:
3775                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3776                         break;
3777                 case 7:
3778                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3779                         break;
3780                 case 10:
3781                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3782                         break;
3783                 case 14:
3784                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3785                         break;
3786                 }
3787                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3788                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3789         } else {
3790                 if (is_lvds) {
3791                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3792                 } else {
3793                         if (clock.p1 == 2)
3794                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3795                         else
3796                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3797                         if (clock.p2 == 4)
3798                                 dpll |= PLL_P2_DIVIDE_BY_4;
3799                 }
3800         }
3801
3802         if (is_sdvo && is_tv)
3803                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3804         else if (is_tv)
3805                 /* XXX: just matching BIOS for now */
3806                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3807                 dpll |= 3;
3808         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3809                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3810         else
3811                 dpll |= PLL_REF_INPUT_DREFCLK;
3812
3813         /* setup pipeconf */
3814         pipeconf = I915_READ(pipeconf_reg);
3815
3816         /* Set up the display plane register */
3817         dspcntr = DISPPLANE_GAMMA_ENABLE;
3818
3819         /* Ironlake's plane is forced to pipe, bit 24 is to
3820            enable color space conversion */
3821         if (!HAS_PCH_SPLIT(dev)) {
3822                 if (pipe == 0)
3823                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3824                 else
3825                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3826         }
3827
3828         if (pipe == 0 && !IS_I965G(dev)) {
3829                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3830                  * core speed.
3831                  *
3832                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3833                  * pipe == 0 check?
3834                  */
3835                 if (mode->clock >
3836                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3837                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3838                 else
3839                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3840         }
3841
3842         dspcntr |= DISPLAY_PLANE_ENABLE;
3843         pipeconf |= PIPEACONF_ENABLE;
3844         dpll |= DPLL_VCO_ENABLE;
3845
3846
3847         /* Disable the panel fitter if it was on our pipe */
3848         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3849                 I915_WRITE(PFIT_CONTROL, 0);
3850
3851         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3852         drm_mode_debug_printmodeline(mode);
3853
3854         /* assign to Ironlake registers */
3855         if (HAS_PCH_SPLIT(dev)) {
3856                 fp_reg = pch_fp_reg;
3857                 dpll_reg = pch_dpll_reg;
3858         }
3859
3860         if (is_edp) {
3861                 ironlake_disable_pll_edp(crtc);
3862         } else if ((dpll & DPLL_VCO_ENABLE)) {
3863                 I915_WRITE(fp_reg, fp);
3864                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3865                 I915_READ(dpll_reg);
3866                 udelay(150);
3867         }
3868
3869         /* enable transcoder DPLL */
3870         if (HAS_PCH_CPT(dev)) {
3871                 temp = I915_READ(PCH_DPLL_SEL);
3872                 if (trans_dpll_sel == 0)
3873                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3874                 else
3875                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3876                 I915_WRITE(PCH_DPLL_SEL, temp);
3877                 I915_READ(PCH_DPLL_SEL);
3878                 udelay(150);
3879         }
3880
3881         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3882          * This is an exception to the general rule that mode_set doesn't turn
3883          * things on.
3884          */
3885         if (is_lvds) {
3886                 u32 lvds;
3887
3888                 if (HAS_PCH_SPLIT(dev))
3889                         lvds_reg = PCH_LVDS;
3890
3891                 lvds = I915_READ(lvds_reg);
3892                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3893                 if (pipe == 1) {
3894                         if (HAS_PCH_CPT(dev))
3895                                 lvds |= PORT_TRANS_B_SEL_CPT;
3896                         else
3897                                 lvds |= LVDS_PIPEB_SELECT;
3898                 } else {
3899                         if (HAS_PCH_CPT(dev))
3900                                 lvds &= ~PORT_TRANS_SEL_MASK;
3901                         else
3902                                 lvds &= ~LVDS_PIPEB_SELECT;
3903                 }
3904                 /* set the corresponsding LVDS_BORDER bit */
3905                 lvds |= dev_priv->lvds_border_bits;
3906                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3907                  * set the DPLLs for dual-channel mode or not.
3908                  */
3909                 if (clock.p2 == 7)
3910                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3911                 else
3912                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3913
3914                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3915                  * appropriately here, but we need to look more thoroughly into how
3916                  * panels behave in the two modes.
3917                  */
3918                 /* set the dithering flag */
3919                 if (IS_I965G(dev)) {
3920                         if (dev_priv->lvds_dither) {
3921                                 if (HAS_PCH_SPLIT(dev)) {
3922                                         pipeconf |= PIPE_ENABLE_DITHER;
3923                                         pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3924                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
3925                                 } else
3926                                         lvds |= LVDS_ENABLE_DITHER;
3927                         } else {
3928                                 if (HAS_PCH_SPLIT(dev)) {
3929                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3930                                         pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3931                                 } else
3932                                         lvds &= ~LVDS_ENABLE_DITHER;
3933                         }
3934                 }
3935                 I915_WRITE(lvds_reg, lvds);
3936                 I915_READ(lvds_reg);
3937         }
3938         if (is_dp)
3939                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3940         else if (HAS_PCH_SPLIT(dev)) {
3941                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3942                 if (pipe == 0) {
3943                         I915_WRITE(TRANSA_DATA_M1, 0);
3944                         I915_WRITE(TRANSA_DATA_N1, 0);
3945                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3946                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3947                 } else {
3948                         I915_WRITE(TRANSB_DATA_M1, 0);
3949                         I915_WRITE(TRANSB_DATA_N1, 0);
3950                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3951                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3952                 }
3953         }
3954
3955         if (!is_edp) {
3956                 I915_WRITE(fp_reg, fp);
3957                 I915_WRITE(dpll_reg, dpll);
3958                 I915_READ(dpll_reg);
3959                 /* Wait for the clocks to stabilize. */
3960                 udelay(150);
3961
3962                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3963                         if (is_sdvo) {
3964                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3965                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3966                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3967                         } else
3968                                 I915_WRITE(dpll_md_reg, 0);
3969                 } else {
3970                         /* write it again -- the BIOS does, after all */
3971                         I915_WRITE(dpll_reg, dpll);
3972                 }
3973                 I915_READ(dpll_reg);
3974                 /* Wait for the clocks to stabilize. */
3975                 udelay(150);
3976         }
3977
3978         if (is_lvds && has_reduced_clock && i915_powersave) {
3979                 I915_WRITE(fp_reg + 4, fp2);
3980                 intel_crtc->lowfreq_avail = true;
3981                 if (HAS_PIPE_CXSR(dev)) {
3982                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3983                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3984                 }
3985         } else {
3986                 I915_WRITE(fp_reg + 4, fp);
3987                 intel_crtc->lowfreq_avail = false;
3988                 if (HAS_PIPE_CXSR(dev)) {
3989                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3990                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3991                 }
3992         }
3993
3994         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3995                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3996                 /* the chip adds 2 halflines automatically */
3997                 adjusted_mode->crtc_vdisplay -= 1;
3998                 adjusted_mode->crtc_vtotal -= 1;
3999                 adjusted_mode->crtc_vblank_start -= 1;
4000                 adjusted_mode->crtc_vblank_end -= 1;
4001                 adjusted_mode->crtc_vsync_end -= 1;
4002                 adjusted_mode->crtc_vsync_start -= 1;
4003         } else
4004                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4005
4006         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4007                    ((adjusted_mode->crtc_htotal - 1) << 16));
4008         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4009                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4010         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4011                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4012         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4013                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4014         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4015                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4016         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4017                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4018         /* pipesrc and dspsize control the size that is scaled from, which should
4019          * always be the user's requested size.
4020          */
4021         if (!HAS_PCH_SPLIT(dev)) {
4022                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4023                                 (mode->hdisplay - 1));
4024                 I915_WRITE(dsppos_reg, 0);
4025         }
4026         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4027
4028         if (HAS_PCH_SPLIT(dev)) {
4029                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4030                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4031                 I915_WRITE(link_m1_reg, m_n.link_m);
4032                 I915_WRITE(link_n1_reg, m_n.link_n);
4033
4034                 if (is_edp) {
4035                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4036                 } else {
4037                         /* enable FDI RX PLL too */
4038                         temp = I915_READ(fdi_rx_reg);
4039                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4040                         I915_READ(fdi_rx_reg);
4041                         udelay(200);
4042
4043                         /* enable FDI TX PLL too */
4044                         temp = I915_READ(fdi_tx_reg);
4045                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4046                         I915_READ(fdi_tx_reg);
4047
4048                         /* enable FDI RX PCDCLK */
4049                         temp = I915_READ(fdi_rx_reg);
4050                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4051                         I915_READ(fdi_rx_reg);
4052                         udelay(200);
4053                 }
4054         }
4055
4056         I915_WRITE(pipeconf_reg, pipeconf);
4057         I915_READ(pipeconf_reg);
4058
4059         intel_wait_for_vblank(dev);
4060
4061         if (IS_IRONLAKE(dev)) {
4062                 /* enable address swizzle for tiling buffer */
4063                 temp = I915_READ(DISP_ARB_CTL);
4064                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4065         }
4066
4067         I915_WRITE(dspcntr_reg, dspcntr);
4068
4069         /* Flush the plane changes */
4070         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4071
4072         if ((IS_I965G(dev) || plane == 0))
4073                 intel_update_fbc(crtc, &crtc->mode);
4074
4075         intel_update_watermarks(dev);
4076
4077         drm_vblank_post_modeset(dev, pipe);
4078
4079         return ret;
4080 }
4081
4082 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4083 void intel_crtc_load_lut(struct drm_crtc *crtc)
4084 {
4085         struct drm_device *dev = crtc->dev;
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4088         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4089         int i;
4090
4091         /* The clocks have to be on to load the palette. */
4092         if (!crtc->enabled)
4093                 return;
4094
4095         /* use legacy palette for Ironlake */
4096         if (HAS_PCH_SPLIT(dev))
4097                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4098                                                    LGC_PALETTE_B;
4099
4100         for (i = 0; i < 256; i++) {
4101                 I915_WRITE(palreg + 4 * i,
4102                            (intel_crtc->lut_r[i] << 16) |
4103                            (intel_crtc->lut_g[i] << 8) |
4104                            intel_crtc->lut_b[i]);
4105         }
4106 }
4107
4108 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4109                                  struct drm_file *file_priv,
4110                                  uint32_t handle,
4111                                  uint32_t width, uint32_t height)
4112 {
4113         struct drm_device *dev = crtc->dev;
4114         struct drm_i915_private *dev_priv = dev->dev_private;
4115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4116         struct drm_gem_object *bo;
4117         struct drm_i915_gem_object *obj_priv;
4118         int pipe = intel_crtc->pipe;
4119         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
4120         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
4121         uint32_t temp = I915_READ(control);
4122         size_t addr;
4123         int ret;
4124
4125         DRM_DEBUG_KMS("\n");
4126
4127         /* if we want to turn off the cursor ignore width and height */
4128         if (!handle) {
4129                 DRM_DEBUG_KMS("cursor off\n");
4130                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4131                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4132                         temp |= CURSOR_MODE_DISABLE;
4133                 } else {
4134                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4135                 }
4136                 addr = 0;
4137                 bo = NULL;
4138                 mutex_lock(&dev->struct_mutex);
4139                 goto finish;
4140         }
4141
4142         /* Currently we only support 64x64 cursors */
4143         if (width != 64 || height != 64) {
4144                 DRM_ERROR("we currently only support 64x64 cursors\n");
4145                 return -EINVAL;
4146         }
4147
4148         bo = drm_gem_object_lookup(dev, file_priv, handle);
4149         if (!bo)
4150                 return -ENOENT;
4151
4152         obj_priv = to_intel_bo(bo);
4153
4154         if (bo->size < width * height * 4) {
4155                 DRM_ERROR("buffer is to small\n");
4156                 ret = -ENOMEM;
4157                 goto fail;
4158         }
4159
4160         /* we only need to pin inside GTT if cursor is non-phy */
4161         mutex_lock(&dev->struct_mutex);
4162         if (!dev_priv->info->cursor_needs_physical) {
4163                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4164                 if (ret) {
4165                         DRM_ERROR("failed to pin cursor bo\n");
4166                         goto fail_locked;
4167                 }
4168
4169                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4170                 if (ret) {
4171                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4172                         goto fail_unpin;
4173                 }
4174
4175                 addr = obj_priv->gtt_offset;
4176         } else {
4177                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
4178                 if (ret) {
4179                         DRM_ERROR("failed to attach phys object\n");
4180                         goto fail_locked;
4181                 }
4182                 addr = obj_priv->phys_obj->handle->busaddr;
4183         }
4184
4185         if (!IS_I9XX(dev))
4186                 I915_WRITE(CURSIZE, (height << 12) | width);
4187
4188         /* Hooray for CUR*CNTR differences */
4189         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4190                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4191                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4192                 temp |= (pipe << 28); /* Connect to correct pipe */
4193         } else {
4194                 temp &= ~(CURSOR_FORMAT_MASK);
4195                 temp |= CURSOR_ENABLE;
4196                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4197         }
4198
4199  finish:
4200         I915_WRITE(control, temp);
4201         I915_WRITE(base, addr);
4202
4203         if (intel_crtc->cursor_bo) {
4204                 if (dev_priv->info->cursor_needs_physical) {
4205                         if (intel_crtc->cursor_bo != bo)
4206                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4207                 } else
4208                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4209                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4210         }
4211
4212         mutex_unlock(&dev->struct_mutex);
4213
4214         intel_crtc->cursor_addr = addr;
4215         intel_crtc->cursor_bo = bo;
4216
4217         return 0;
4218 fail_unpin:
4219         i915_gem_object_unpin(bo);
4220 fail_locked:
4221         mutex_unlock(&dev->struct_mutex);
4222 fail:
4223         drm_gem_object_unreference_unlocked(bo);
4224         return ret;
4225 }
4226
4227 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4228 {
4229         struct drm_device *dev = crtc->dev;
4230         struct drm_i915_private *dev_priv = dev->dev_private;
4231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4232         struct intel_framebuffer *intel_fb;
4233         int pipe = intel_crtc->pipe;
4234         uint32_t temp = 0;
4235         uint32_t adder;
4236
4237         if (crtc->fb) {
4238                 intel_fb = to_intel_framebuffer(crtc->fb);
4239                 intel_mark_busy(dev, intel_fb->obj);
4240         }
4241
4242         if (x < 0) {
4243                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4244                 x = -x;
4245         }
4246         if (y < 0) {
4247                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4248                 y = -y;
4249         }
4250
4251         temp |= x << CURSOR_X_SHIFT;
4252         temp |= y << CURSOR_Y_SHIFT;
4253
4254         adder = intel_crtc->cursor_addr;
4255         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
4256         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
4257
4258         return 0;
4259 }
4260
4261 /** Sets the color ramps on behalf of RandR */
4262 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4263                                  u16 blue, int regno)
4264 {
4265         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4266
4267         intel_crtc->lut_r[regno] = red >> 8;
4268         intel_crtc->lut_g[regno] = green >> 8;
4269         intel_crtc->lut_b[regno] = blue >> 8;
4270 }
4271
4272 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4273                              u16 *blue, int regno)
4274 {
4275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4276
4277         *red = intel_crtc->lut_r[regno] << 8;
4278         *green = intel_crtc->lut_g[regno] << 8;
4279         *blue = intel_crtc->lut_b[regno] << 8;
4280 }
4281
4282 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4283                                  u16 *blue, uint32_t size)
4284 {
4285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4286         int i;
4287
4288         if (size != 256)
4289                 return;
4290
4291         for (i = 0; i < 256; i++) {
4292                 intel_crtc->lut_r[i] = red[i] >> 8;
4293                 intel_crtc->lut_g[i] = green[i] >> 8;
4294                 intel_crtc->lut_b[i] = blue[i] >> 8;
4295         }
4296
4297         intel_crtc_load_lut(crtc);
4298 }
4299
4300 /**
4301  * Get a pipe with a simple mode set on it for doing load-based monitor
4302  * detection.
4303  *
4304  * It will be up to the load-detect code to adjust the pipe as appropriate for
4305  * its requirements.  The pipe will be connected to no other encoders.
4306  *
4307  * Currently this code will only succeed if there is a pipe with no encoders
4308  * configured for it.  In the future, it could choose to temporarily disable
4309  * some outputs to free up a pipe for its use.
4310  *
4311  * \return crtc, or NULL if no pipes are available.
4312  */
4313
4314 /* VESA 640x480x72Hz mode to set on the pipe */
4315 static struct drm_display_mode load_detect_mode = {
4316         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4317                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4318 };
4319
4320 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4321                                             struct drm_connector *connector,
4322                                             struct drm_display_mode *mode,
4323                                             int *dpms_mode)
4324 {
4325         struct intel_crtc *intel_crtc;
4326         struct drm_crtc *possible_crtc;
4327         struct drm_crtc *supported_crtc =NULL;
4328         struct drm_encoder *encoder = &intel_encoder->enc;
4329         struct drm_crtc *crtc = NULL;
4330         struct drm_device *dev = encoder->dev;
4331         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4332         struct drm_crtc_helper_funcs *crtc_funcs;
4333         int i = -1;
4334
4335         /*
4336          * Algorithm gets a little messy:
4337          *   - if the connector already has an assigned crtc, use it (but make
4338          *     sure it's on first)
4339          *   - try to find the first unused crtc that can drive this connector,
4340          *     and use that if we find one
4341          *   - if there are no unused crtcs available, try to use the first
4342          *     one we found that supports the connector
4343          */
4344
4345         /* See if we already have a CRTC for this connector */
4346         if (encoder->crtc) {
4347                 crtc = encoder->crtc;
4348                 /* Make sure the crtc and connector are running */
4349                 intel_crtc = to_intel_crtc(crtc);
4350                 *dpms_mode = intel_crtc->dpms_mode;
4351                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4352                         crtc_funcs = crtc->helper_private;
4353                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4354                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4355                 }
4356                 return crtc;
4357         }
4358
4359         /* Find an unused one (if possible) */
4360         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4361                 i++;
4362                 if (!(encoder->possible_crtcs & (1 << i)))
4363                         continue;
4364                 if (!possible_crtc->enabled) {
4365                         crtc = possible_crtc;
4366                         break;
4367                 }
4368                 if (!supported_crtc)
4369                         supported_crtc = possible_crtc;
4370         }
4371
4372         /*
4373          * If we didn't find an unused CRTC, don't use any.
4374          */
4375         if (!crtc) {
4376                 return NULL;
4377         }
4378
4379         encoder->crtc = crtc;
4380         connector->encoder = encoder;
4381         intel_encoder->load_detect_temp = true;
4382
4383         intel_crtc = to_intel_crtc(crtc);
4384         *dpms_mode = intel_crtc->dpms_mode;
4385
4386         if (!crtc->enabled) {
4387                 if (!mode)
4388                         mode = &load_detect_mode;
4389                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4390         } else {
4391                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4392                         crtc_funcs = crtc->helper_private;
4393                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4394                 }
4395
4396                 /* Add this connector to the crtc */
4397                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4398                 encoder_funcs->commit(encoder);
4399         }
4400         /* let the connector get through one full cycle before testing */
4401         intel_wait_for_vblank(dev);
4402
4403         return crtc;
4404 }
4405
4406 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4407                                     struct drm_connector *connector, int dpms_mode)
4408 {
4409         struct drm_encoder *encoder = &intel_encoder->enc;
4410         struct drm_device *dev = encoder->dev;
4411         struct drm_crtc *crtc = encoder->crtc;
4412         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4413         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4414
4415         if (intel_encoder->load_detect_temp) {
4416                 encoder->crtc = NULL;
4417                 connector->encoder = NULL;
4418                 intel_encoder->load_detect_temp = false;
4419                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4420                 drm_helper_disable_unused_functions(dev);
4421         }
4422
4423         /* Switch crtc and encoder back off if necessary */
4424         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4425                 if (encoder->crtc == crtc)
4426                         encoder_funcs->dpms(encoder, dpms_mode);
4427                 crtc_funcs->dpms(crtc, dpms_mode);
4428         }
4429 }
4430
4431 /* Returns the clock of the currently programmed mode of the given pipe. */
4432 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4433 {
4434         struct drm_i915_private *dev_priv = dev->dev_private;
4435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4436         int pipe = intel_crtc->pipe;
4437         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4438         u32 fp;
4439         intel_clock_t clock;
4440
4441         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4442                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4443         else
4444                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4445
4446         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4447         if (IS_PINEVIEW(dev)) {
4448                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4449                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4450         } else {
4451                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4452                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4453         }
4454
4455         if (IS_I9XX(dev)) {
4456                 if (IS_PINEVIEW(dev))
4457                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4458                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4459                 else
4460                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4461                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4462
4463                 switch (dpll & DPLL_MODE_MASK) {
4464                 case DPLLB_MODE_DAC_SERIAL:
4465                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4466                                 5 : 10;
4467                         break;
4468                 case DPLLB_MODE_LVDS:
4469                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4470                                 7 : 14;
4471                         break;
4472                 default:
4473                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4474                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4475                         return 0;
4476                 }
4477
4478                 /* XXX: Handle the 100Mhz refclk */
4479                 intel_clock(dev, 96000, &clock);
4480         } else {
4481                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4482
4483                 if (is_lvds) {
4484                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4485                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4486                         clock.p2 = 14;
4487
4488                         if ((dpll & PLL_REF_INPUT_MASK) ==
4489                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4490                                 /* XXX: might not be 66MHz */
4491                                 intel_clock(dev, 66000, &clock);
4492                         } else
4493                                 intel_clock(dev, 48000, &clock);
4494                 } else {
4495                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4496                                 clock.p1 = 2;
4497                         else {
4498                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4499                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4500                         }
4501                         if (dpll & PLL_P2_DIVIDE_BY_4)
4502                                 clock.p2 = 4;
4503                         else
4504                                 clock.p2 = 2;
4505
4506                         intel_clock(dev, 48000, &clock);
4507                 }
4508         }
4509
4510         /* XXX: It would be nice to validate the clocks, but we can't reuse
4511          * i830PllIsValid() because it relies on the xf86_config connector
4512          * configuration being accurate, which it isn't necessarily.
4513          */
4514
4515         return clock.dot;
4516 }
4517
4518 /** Returns the currently programmed mode of the given pipe. */
4519 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4520                                              struct drm_crtc *crtc)
4521 {
4522         struct drm_i915_private *dev_priv = dev->dev_private;
4523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4524         int pipe = intel_crtc->pipe;
4525         struct drm_display_mode *mode;
4526         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4527         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4528         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4529         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4530
4531         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4532         if (!mode)
4533                 return NULL;
4534
4535         mode->clock = intel_crtc_clock_get(dev, crtc);
4536         mode->hdisplay = (htot & 0xffff) + 1;
4537         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4538         mode->hsync_start = (hsync & 0xffff) + 1;
4539         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4540         mode->vdisplay = (vtot & 0xffff) + 1;
4541         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4542         mode->vsync_start = (vsync & 0xffff) + 1;
4543         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4544
4545         drm_mode_set_name(mode);
4546         drm_mode_set_crtcinfo(mode, 0);
4547
4548         return mode;
4549 }
4550
4551 #define GPU_IDLE_TIMEOUT 500 /* ms */
4552
4553 /* When this timer fires, we've been idle for awhile */
4554 static void intel_gpu_idle_timer(unsigned long arg)
4555 {
4556         struct drm_device *dev = (struct drm_device *)arg;
4557         drm_i915_private_t *dev_priv = dev->dev_private;
4558
4559         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4560
4561         dev_priv->busy = false;
4562
4563         queue_work(dev_priv->wq, &dev_priv->idle_work);
4564 }
4565
4566 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4567
4568 static void intel_crtc_idle_timer(unsigned long arg)
4569 {
4570         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4571         struct drm_crtc *crtc = &intel_crtc->base;
4572         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4573
4574         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4575
4576         intel_crtc->busy = false;
4577
4578         queue_work(dev_priv->wq, &dev_priv->idle_work);
4579 }
4580
4581 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4582 {
4583         struct drm_device *dev = crtc->dev;
4584         drm_i915_private_t *dev_priv = dev->dev_private;
4585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4586         int pipe = intel_crtc->pipe;
4587         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4588         int dpll = I915_READ(dpll_reg);
4589
4590         if (HAS_PCH_SPLIT(dev))
4591                 return;
4592
4593         if (!dev_priv->lvds_downclock_avail)
4594                 return;
4595
4596         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4597                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4598
4599                 /* Unlock panel regs */
4600                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4601                            PANEL_UNLOCK_REGS);
4602
4603                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4604                 I915_WRITE(dpll_reg, dpll);
4605                 dpll = I915_READ(dpll_reg);
4606                 intel_wait_for_vblank(dev);
4607                 dpll = I915_READ(dpll_reg);
4608                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4609                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4610
4611                 /* ...and lock them again */
4612                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4613         }
4614
4615         /* Schedule downclock */
4616         if (schedule)
4617                 mod_timer(&intel_crtc->idle_timer, jiffies +
4618                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4619 }
4620
4621 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4622 {
4623         struct drm_device *dev = crtc->dev;
4624         drm_i915_private_t *dev_priv = dev->dev_private;
4625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626         int pipe = intel_crtc->pipe;
4627         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4628         int dpll = I915_READ(dpll_reg);
4629
4630         if (HAS_PCH_SPLIT(dev))
4631                 return;
4632
4633         if (!dev_priv->lvds_downclock_avail)
4634                 return;
4635
4636         /*
4637          * Since this is called by a timer, we should never get here in
4638          * the manual case.
4639          */
4640         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4641                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4642
4643                 /* Unlock panel regs */
4644                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4645                            PANEL_UNLOCK_REGS);
4646
4647                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4648                 I915_WRITE(dpll_reg, dpll);
4649                 dpll = I915_READ(dpll_reg);
4650                 intel_wait_for_vblank(dev);
4651                 dpll = I915_READ(dpll_reg);
4652                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4653                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4654
4655                 /* ...and lock them again */
4656                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4657         }
4658
4659 }
4660
4661 /**
4662  * intel_idle_update - adjust clocks for idleness
4663  * @work: work struct
4664  *
4665  * Either the GPU or display (or both) went idle.  Check the busy status
4666  * here and adjust the CRTC and GPU clocks as necessary.
4667  */
4668 static void intel_idle_update(struct work_struct *work)
4669 {
4670         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4671                                                     idle_work);
4672         struct drm_device *dev = dev_priv->dev;
4673         struct drm_crtc *crtc;
4674         struct intel_crtc *intel_crtc;
4675         int enabled = 0;
4676
4677         if (!i915_powersave)
4678                 return;
4679
4680         mutex_lock(&dev->struct_mutex);
4681
4682         i915_update_gfx_val(dev_priv);
4683
4684         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4685                 /* Skip inactive CRTCs */
4686                 if (!crtc->fb)
4687                         continue;
4688
4689                 enabled++;
4690                 intel_crtc = to_intel_crtc(crtc);
4691                 if (!intel_crtc->busy)
4692                         intel_decrease_pllclock(crtc);
4693         }
4694
4695         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4696                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4697                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4698         }
4699
4700         mutex_unlock(&dev->struct_mutex);
4701 }
4702
4703 /**
4704  * intel_mark_busy - mark the GPU and possibly the display busy
4705  * @dev: drm device
4706  * @obj: object we're operating on
4707  *
4708  * Callers can use this function to indicate that the GPU is busy processing
4709  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4710  * buffer), we'll also mark the display as busy, so we know to increase its
4711  * clock frequency.
4712  */
4713 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4714 {
4715         drm_i915_private_t *dev_priv = dev->dev_private;
4716         struct drm_crtc *crtc = NULL;
4717         struct intel_framebuffer *intel_fb;
4718         struct intel_crtc *intel_crtc;
4719
4720         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4721                 return;
4722
4723         if (!dev_priv->busy) {
4724                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4725                         u32 fw_blc_self;
4726
4727                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4728                         fw_blc_self = I915_READ(FW_BLC_SELF);
4729                         fw_blc_self &= ~FW_BLC_SELF_EN;
4730                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4731                 }
4732                 dev_priv->busy = true;
4733         } else
4734                 mod_timer(&dev_priv->idle_timer, jiffies +
4735                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4736
4737         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4738                 if (!crtc->fb)
4739                         continue;
4740
4741                 intel_crtc = to_intel_crtc(crtc);
4742                 intel_fb = to_intel_framebuffer(crtc->fb);
4743                 if (intel_fb->obj == obj) {
4744                         if (!intel_crtc->busy) {
4745                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4746                                         u32 fw_blc_self;
4747
4748                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4749                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4750                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4751                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4752                                 }
4753                                 /* Non-busy -> busy, upclock */
4754                                 intel_increase_pllclock(crtc, true);
4755                                 intel_crtc->busy = true;
4756                         } else {
4757                                 /* Busy -> busy, put off timer */
4758                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4759                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4760                         }
4761                 }
4762         }
4763 }
4764
4765 static void intel_crtc_destroy(struct drm_crtc *crtc)
4766 {
4767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4768
4769         drm_crtc_cleanup(crtc);
4770         kfree(intel_crtc);
4771 }
4772
4773 struct intel_unpin_work {
4774         struct work_struct work;
4775         struct drm_device *dev;
4776         struct drm_gem_object *old_fb_obj;
4777         struct drm_gem_object *pending_flip_obj;
4778         struct drm_pending_vblank_event *event;
4779         int pending;
4780 };
4781
4782 static void intel_unpin_work_fn(struct work_struct *__work)
4783 {
4784         struct intel_unpin_work *work =
4785                 container_of(__work, struct intel_unpin_work, work);
4786
4787         mutex_lock(&work->dev->struct_mutex);
4788         i915_gem_object_unpin(work->old_fb_obj);
4789         drm_gem_object_unreference(work->pending_flip_obj);
4790         drm_gem_object_unreference(work->old_fb_obj);
4791         mutex_unlock(&work->dev->struct_mutex);
4792         kfree(work);
4793 }
4794
4795 static void do_intel_finish_page_flip(struct drm_device *dev,
4796                                       struct drm_crtc *crtc)
4797 {
4798         drm_i915_private_t *dev_priv = dev->dev_private;
4799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4800         struct intel_unpin_work *work;
4801         struct drm_i915_gem_object *obj_priv;
4802         struct drm_pending_vblank_event *e;
4803         struct timeval now;
4804         unsigned long flags;
4805
4806         /* Ignore early vblank irqs */
4807         if (intel_crtc == NULL)
4808                 return;
4809
4810         spin_lock_irqsave(&dev->event_lock, flags);
4811         work = intel_crtc->unpin_work;
4812         if (work == NULL || !work->pending) {
4813                 spin_unlock_irqrestore(&dev->event_lock, flags);
4814                 return;
4815         }
4816
4817         intel_crtc->unpin_work = NULL;
4818         drm_vblank_put(dev, intel_crtc->pipe);
4819
4820         if (work->event) {
4821                 e = work->event;
4822                 do_gettimeofday(&now);
4823                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4824                 e->event.tv_sec = now.tv_sec;
4825                 e->event.tv_usec = now.tv_usec;
4826                 list_add_tail(&e->base.link,
4827                               &e->base.file_priv->event_list);
4828                 wake_up_interruptible(&e->base.file_priv->event_wait);
4829         }
4830
4831         spin_unlock_irqrestore(&dev->event_lock, flags);
4832
4833         obj_priv = to_intel_bo(work->pending_flip_obj);
4834
4835         /* Initial scanout buffer will have a 0 pending flip count */
4836         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4837             atomic_dec_and_test(&obj_priv->pending_flip))
4838                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4839         schedule_work(&work->work);
4840
4841         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4842 }
4843
4844 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4845 {
4846         drm_i915_private_t *dev_priv = dev->dev_private;
4847         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4848
4849         do_intel_finish_page_flip(dev, crtc);
4850 }
4851
4852 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4853 {
4854         drm_i915_private_t *dev_priv = dev->dev_private;
4855         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4856
4857         do_intel_finish_page_flip(dev, crtc);
4858 }
4859
4860 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4861 {
4862         drm_i915_private_t *dev_priv = dev->dev_private;
4863         struct intel_crtc *intel_crtc =
4864                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4865         unsigned long flags;
4866
4867         spin_lock_irqsave(&dev->event_lock, flags);
4868         if (intel_crtc->unpin_work) {
4869                 intel_crtc->unpin_work->pending = 1;
4870         } else {
4871                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4872         }
4873         spin_unlock_irqrestore(&dev->event_lock, flags);
4874 }
4875
4876 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4877                                 struct drm_framebuffer *fb,
4878                                 struct drm_pending_vblank_event *event)
4879 {
4880         struct drm_device *dev = crtc->dev;
4881         struct drm_i915_private *dev_priv = dev->dev_private;
4882         struct intel_framebuffer *intel_fb;
4883         struct drm_i915_gem_object *obj_priv;
4884         struct drm_gem_object *obj;
4885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4886         struct intel_unpin_work *work;
4887         unsigned long flags, offset;
4888         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4889         int ret, pipesrc;
4890         u32 flip_mask;
4891
4892         work = kzalloc(sizeof *work, GFP_KERNEL);
4893         if (work == NULL)
4894                 return -ENOMEM;
4895
4896         work->event = event;
4897         work->dev = crtc->dev;
4898         intel_fb = to_intel_framebuffer(crtc->fb);
4899         work->old_fb_obj = intel_fb->obj;
4900         INIT_WORK(&work->work, intel_unpin_work_fn);
4901
4902         /* We borrow the event spin lock for protecting unpin_work */
4903         spin_lock_irqsave(&dev->event_lock, flags);
4904         if (intel_crtc->unpin_work) {
4905                 spin_unlock_irqrestore(&dev->event_lock, flags);
4906                 kfree(work);
4907
4908                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4909                 return -EBUSY;
4910         }
4911         intel_crtc->unpin_work = work;
4912         spin_unlock_irqrestore(&dev->event_lock, flags);
4913
4914         intel_fb = to_intel_framebuffer(fb);
4915         obj = intel_fb->obj;
4916
4917         mutex_lock(&dev->struct_mutex);
4918         ret = intel_pin_and_fence_fb_obj(dev, obj);
4919         if (ret)
4920                 goto cleanup_work;
4921
4922         /* Reference the objects for the scheduled work. */
4923         drm_gem_object_reference(work->old_fb_obj);
4924         drm_gem_object_reference(obj);
4925
4926         crtc->fb = fb;
4927         ret = i915_gem_object_flush_write_domain(obj);
4928         if (ret)
4929                 goto cleanup_objs;
4930
4931         ret = drm_vblank_get(dev, intel_crtc->pipe);
4932         if (ret)
4933                 goto cleanup_objs;
4934
4935         obj_priv = to_intel_bo(obj);
4936         atomic_inc(&obj_priv->pending_flip);
4937         work->pending_flip_obj = obj;
4938
4939         if (intel_crtc->plane)
4940                 flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4941         else
4942                 flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
4943
4944         /* Wait for any previous flip to finish */
4945         if (IS_GEN3(dev))
4946                 while (I915_READ(ISR) & flip_mask)
4947                         ;
4948
4949         /* Offset into the new buffer for cases of shared fbs between CRTCs */
4950         offset = obj_priv->gtt_offset;
4951         offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
4952
4953         BEGIN_LP_RING(4);
4954         if (IS_I965G(dev)) {
4955                 OUT_RING(MI_DISPLAY_FLIP |
4956                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4957                 OUT_RING(fb->pitch);
4958                 OUT_RING(offset | obj_priv->tiling_mode);
4959                 pipesrc = I915_READ(pipesrc_reg);
4960                 OUT_RING(pipesrc & 0x0fff0fff);
4961         } else {
4962                 OUT_RING(MI_DISPLAY_FLIP_I915 |
4963                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4964                 OUT_RING(fb->pitch);
4965                 OUT_RING(offset);
4966                 OUT_RING(MI_NOOP);
4967         }
4968         ADVANCE_LP_RING();
4969
4970         mutex_unlock(&dev->struct_mutex);
4971
4972         trace_i915_flip_request(intel_crtc->plane, obj);
4973
4974         return 0;
4975
4976 cleanup_objs:
4977         drm_gem_object_unreference(work->old_fb_obj);
4978         drm_gem_object_unreference(obj);
4979 cleanup_work:
4980         mutex_unlock(&dev->struct_mutex);
4981
4982         spin_lock_irqsave(&dev->event_lock, flags);
4983         intel_crtc->unpin_work = NULL;
4984         spin_unlock_irqrestore(&dev->event_lock, flags);
4985
4986         kfree(work);
4987
4988         return ret;
4989 }
4990
4991 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4992         .dpms = intel_crtc_dpms,
4993         .mode_fixup = intel_crtc_mode_fixup,
4994         .mode_set = intel_crtc_mode_set,
4995         .mode_set_base = intel_pipe_set_base,
4996         .prepare = intel_crtc_prepare,
4997         .commit = intel_crtc_commit,
4998         .load_lut = intel_crtc_load_lut,
4999 };
5000
5001 static const struct drm_crtc_funcs intel_crtc_funcs = {
5002         .cursor_set = intel_crtc_cursor_set,
5003         .cursor_move = intel_crtc_cursor_move,
5004         .gamma_set = intel_crtc_gamma_set,
5005         .set_config = drm_crtc_helper_set_config,
5006         .destroy = intel_crtc_destroy,
5007         .page_flip = intel_crtc_page_flip,
5008 };
5009
5010
5011 static void intel_crtc_init(struct drm_device *dev, int pipe)
5012 {
5013         drm_i915_private_t *dev_priv = dev->dev_private;
5014         struct intel_crtc *intel_crtc;
5015         int i;
5016
5017         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5018         if (intel_crtc == NULL)
5019                 return;
5020
5021         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5022
5023         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5024         intel_crtc->pipe = pipe;
5025         intel_crtc->plane = pipe;
5026         for (i = 0; i < 256; i++) {
5027                 intel_crtc->lut_r[i] = i;
5028                 intel_crtc->lut_g[i] = i;
5029                 intel_crtc->lut_b[i] = i;
5030         }
5031
5032         /* Swap pipes & planes for FBC on pre-965 */
5033         intel_crtc->pipe = pipe;
5034         intel_crtc->plane = pipe;
5035         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5036                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5037                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5038         }
5039
5040         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5041                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5042         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5043         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5044
5045         intel_crtc->cursor_addr = 0;
5046         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5047         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5048
5049         intel_crtc->busy = false;
5050
5051         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5052                     (unsigned long)intel_crtc);
5053 }
5054
5055 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5056                                 struct drm_file *file_priv)
5057 {
5058         drm_i915_private_t *dev_priv = dev->dev_private;
5059         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5060         struct drm_mode_object *drmmode_obj;
5061         struct intel_crtc *crtc;
5062
5063         if (!dev_priv) {
5064                 DRM_ERROR("called with no initialization\n");
5065                 return -EINVAL;
5066         }
5067
5068         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5069                         DRM_MODE_OBJECT_CRTC);
5070
5071         if (!drmmode_obj) {
5072                 DRM_ERROR("no such CRTC id\n");
5073                 return -EINVAL;
5074         }
5075
5076         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5077         pipe_from_crtc_id->pipe = crtc->pipe;
5078
5079         return 0;
5080 }
5081
5082 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5083 {
5084         struct drm_crtc *crtc = NULL;
5085
5086         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5087                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5088                 if (intel_crtc->pipe == pipe)
5089                         break;
5090         }
5091         return crtc;
5092 }
5093
5094 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5095 {
5096         int index_mask = 0;
5097         struct drm_encoder *encoder;
5098         int entry = 0;
5099
5100         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5101                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5102                 if (type_mask & intel_encoder->clone_mask)
5103                         index_mask |= (1 << entry);
5104                 entry++;
5105         }
5106         return index_mask;
5107 }
5108
5109
5110 static void intel_setup_outputs(struct drm_device *dev)
5111 {
5112         struct drm_i915_private *dev_priv = dev->dev_private;
5113         struct drm_encoder *encoder;
5114
5115         intel_crt_init(dev);
5116
5117         /* Set up integrated LVDS */
5118         if (IS_MOBILE(dev) && !IS_I830(dev))
5119                 intel_lvds_init(dev);
5120
5121         if (HAS_PCH_SPLIT(dev)) {
5122                 int found;
5123
5124                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5125                         intel_dp_init(dev, DP_A);
5126
5127                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5128                         /* PCH SDVOB multiplex with HDMIB */
5129                         found = intel_sdvo_init(dev, PCH_SDVOB);
5130                         if (!found)
5131                                 intel_hdmi_init(dev, HDMIB);
5132                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5133                                 intel_dp_init(dev, PCH_DP_B);
5134                 }
5135
5136                 if (I915_READ(HDMIC) & PORT_DETECTED)
5137                         intel_hdmi_init(dev, HDMIC);
5138
5139                 if (I915_READ(HDMID) & PORT_DETECTED)
5140                         intel_hdmi_init(dev, HDMID);
5141
5142                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5143                         intel_dp_init(dev, PCH_DP_C);
5144
5145                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
5146                         intel_dp_init(dev, PCH_DP_D);
5147
5148         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5149                 bool found = false;
5150
5151                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5152                         DRM_DEBUG_KMS("probing SDVOB\n");
5153                         found = intel_sdvo_init(dev, SDVOB);
5154                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5155                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5156                                 intel_hdmi_init(dev, SDVOB);
5157                         }
5158
5159                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5160                                 DRM_DEBUG_KMS("probing DP_B\n");
5161                                 intel_dp_init(dev, DP_B);
5162                         }
5163                 }
5164
5165                 /* Before G4X SDVOC doesn't have its own detect register */
5166
5167                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5168                         DRM_DEBUG_KMS("probing SDVOC\n");
5169                         found = intel_sdvo_init(dev, SDVOC);
5170                 }
5171
5172                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5173
5174                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5175                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5176                                 intel_hdmi_init(dev, SDVOC);
5177                         }
5178                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5179                                 DRM_DEBUG_KMS("probing DP_C\n");
5180                                 intel_dp_init(dev, DP_C);
5181                         }
5182                 }
5183
5184                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5185                     (I915_READ(DP_D) & DP_DETECTED)) {
5186                         DRM_DEBUG_KMS("probing DP_D\n");
5187                         intel_dp_init(dev, DP_D);
5188                 }
5189         } else if (IS_GEN2(dev))
5190                 intel_dvo_init(dev);
5191
5192         if (SUPPORTS_TV(dev))
5193                 intel_tv_init(dev);
5194
5195         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5196                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5197
5198                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5199                 encoder->possible_clones = intel_encoder_clones(dev,
5200                                                 intel_encoder->clone_mask);
5201         }
5202 }
5203
5204 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5205 {
5206         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5207
5208         drm_framebuffer_cleanup(fb);
5209         drm_gem_object_unreference_unlocked(intel_fb->obj);
5210
5211         kfree(intel_fb);
5212 }
5213
5214 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5215                                                 struct drm_file *file_priv,
5216                                                 unsigned int *handle)
5217 {
5218         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5219         struct drm_gem_object *object = intel_fb->obj;
5220
5221         return drm_gem_handle_create(file_priv, object, handle);
5222 }
5223
5224 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5225         .destroy = intel_user_framebuffer_destroy,
5226         .create_handle = intel_user_framebuffer_create_handle,
5227 };
5228
5229 int intel_framebuffer_init(struct drm_device *dev,
5230                            struct intel_framebuffer *intel_fb,
5231                            struct drm_mode_fb_cmd *mode_cmd,
5232                            struct drm_gem_object *obj)
5233 {
5234         int ret;
5235
5236         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5237         if (ret) {
5238                 DRM_ERROR("framebuffer init failed %d\n", ret);
5239                 return ret;
5240         }
5241
5242         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5243         intel_fb->obj = obj;
5244         return 0;
5245 }
5246
5247 static struct drm_framebuffer *
5248 intel_user_framebuffer_create(struct drm_device *dev,
5249                               struct drm_file *filp,
5250                               struct drm_mode_fb_cmd *mode_cmd)
5251 {
5252         struct drm_gem_object *obj;
5253         struct intel_framebuffer *intel_fb;
5254         int ret;
5255
5256         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5257         if (!obj)
5258                 return NULL;
5259
5260         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5261         if (!intel_fb)
5262                 return NULL;
5263
5264         ret = intel_framebuffer_init(dev, intel_fb,
5265                                      mode_cmd, obj);
5266         if (ret) {
5267                 drm_gem_object_unreference_unlocked(obj);
5268                 kfree(intel_fb);
5269                 return NULL;
5270         }
5271
5272         return &intel_fb->base;
5273 }
5274
5275 static const struct drm_mode_config_funcs intel_mode_funcs = {
5276         .fb_create = intel_user_framebuffer_create,
5277         .output_poll_changed = intel_fb_output_poll_changed,
5278 };
5279
5280 static struct drm_gem_object *
5281 intel_alloc_power_context(struct drm_device *dev)
5282 {
5283         struct drm_gem_object *pwrctx;
5284         int ret;
5285
5286         pwrctx = i915_gem_alloc_object(dev, 4096);
5287         if (!pwrctx) {
5288                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5289                 return NULL;
5290         }
5291
5292         mutex_lock(&dev->struct_mutex);
5293         ret = i915_gem_object_pin(pwrctx, 4096);
5294         if (ret) {
5295                 DRM_ERROR("failed to pin power context: %d\n", ret);
5296                 goto err_unref;
5297         }
5298
5299         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5300         if (ret) {
5301                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5302                 goto err_unpin;
5303         }
5304         mutex_unlock(&dev->struct_mutex);
5305
5306         return pwrctx;
5307
5308 err_unpin:
5309         i915_gem_object_unpin(pwrctx);
5310 err_unref:
5311         drm_gem_object_unreference(pwrctx);
5312         mutex_unlock(&dev->struct_mutex);
5313         return NULL;
5314 }
5315
5316 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5317 {
5318         struct drm_i915_private *dev_priv = dev->dev_private;
5319         u16 rgvswctl;
5320
5321         rgvswctl = I915_READ16(MEMSWCTL);
5322         if (rgvswctl & MEMCTL_CMD_STS) {
5323                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5324                 return false; /* still busy with another command */
5325         }
5326
5327         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5328                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5329         I915_WRITE16(MEMSWCTL, rgvswctl);
5330         POSTING_READ16(MEMSWCTL);
5331
5332         rgvswctl |= MEMCTL_CMD_STS;
5333         I915_WRITE16(MEMSWCTL, rgvswctl);
5334
5335         return true;
5336 }
5337
5338 void ironlake_enable_drps(struct drm_device *dev)
5339 {
5340         struct drm_i915_private *dev_priv = dev->dev_private;
5341         u32 rgvmodectl = I915_READ(MEMMODECTL);
5342         u8 fmax, fmin, fstart, vstart;
5343         int i = 0;
5344
5345         /* 100ms RC evaluation intervals */
5346         I915_WRITE(RCUPEI, 100000);
5347         I915_WRITE(RCDNEI, 100000);
5348
5349         /* Set max/min thresholds to 90ms and 80ms respectively */
5350         I915_WRITE(RCBMAXAVG, 90000);
5351         I915_WRITE(RCBMINAVG, 80000);
5352
5353         I915_WRITE(MEMIHYST, 1);
5354
5355         /* Set up min, max, and cur for interrupt handling */
5356         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5357         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5358         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5359                 MEMMODE_FSTART_SHIFT;
5360         fstart = fmax;
5361
5362         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5363                 PXVFREQ_PX_SHIFT;
5364
5365         dev_priv->fmax = fstart; /* IPS callback will increase this */
5366         dev_priv->fstart = fstart;
5367
5368         dev_priv->max_delay = fmax;
5369         dev_priv->min_delay = fmin;
5370         dev_priv->cur_delay = fstart;
5371
5372         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5373                          fstart);
5374
5375         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5376
5377         /*
5378          * Interrupts will be enabled in ironlake_irq_postinstall
5379          */
5380
5381         I915_WRITE(VIDSTART, vstart);
5382         POSTING_READ(VIDSTART);
5383
5384         rgvmodectl |= MEMMODE_SWMODE_EN;
5385         I915_WRITE(MEMMODECTL, rgvmodectl);
5386
5387         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5388                 if (i++ > 100) {
5389                         DRM_ERROR("stuck trying to change perf mode\n");
5390                         break;
5391                 }
5392                 msleep(1);
5393         }
5394         msleep(1);
5395
5396         ironlake_set_drps(dev, fstart);
5397
5398         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5399                 I915_READ(0x112e0);
5400         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5401         dev_priv->last_count2 = I915_READ(0x112f4);
5402         getrawmonotonic(&dev_priv->last_time2);
5403 }
5404
5405 void ironlake_disable_drps(struct drm_device *dev)
5406 {
5407         struct drm_i915_private *dev_priv = dev->dev_private;
5408         u16 rgvswctl = I915_READ16(MEMSWCTL);
5409
5410         /* Ack interrupts, disable EFC interrupt */
5411         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5412         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5413         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5414         I915_WRITE(DEIIR, DE_PCU_EVENT);
5415         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5416
5417         /* Go back to the starting frequency */
5418         ironlake_set_drps(dev, dev_priv->fstart);
5419         msleep(1);
5420         rgvswctl |= MEMCTL_CMD_STS;
5421         I915_WRITE(MEMSWCTL, rgvswctl);
5422         msleep(1);
5423
5424 }
5425
5426 static unsigned long intel_pxfreq(u32 vidfreq)
5427 {
5428         unsigned long freq;
5429         int div = (vidfreq & 0x3f0000) >> 16;
5430         int post = (vidfreq & 0x3000) >> 12;
5431         int pre = (vidfreq & 0x7);
5432
5433         if (!pre)
5434                 return 0;
5435
5436         freq = ((div * 133333) / ((1<<post) * pre));
5437
5438         return freq;
5439 }
5440
5441 void intel_init_emon(struct drm_device *dev)
5442 {
5443         struct drm_i915_private *dev_priv = dev->dev_private;
5444         u32 lcfuse;
5445         u8 pxw[16];
5446         int i;
5447
5448         /* Disable to program */
5449         I915_WRITE(ECR, 0);
5450         POSTING_READ(ECR);
5451
5452         /* Program energy weights for various events */
5453         I915_WRITE(SDEW, 0x15040d00);
5454         I915_WRITE(CSIEW0, 0x007f0000);
5455         I915_WRITE(CSIEW1, 0x1e220004);
5456         I915_WRITE(CSIEW2, 0x04000004);
5457
5458         for (i = 0; i < 5; i++)
5459                 I915_WRITE(PEW + (i * 4), 0);
5460         for (i = 0; i < 3; i++)
5461                 I915_WRITE(DEW + (i * 4), 0);
5462
5463         /* Program P-state weights to account for frequency power adjustment */
5464         for (i = 0; i < 16; i++) {
5465                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5466                 unsigned long freq = intel_pxfreq(pxvidfreq);
5467                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5468                         PXVFREQ_PX_SHIFT;
5469                 unsigned long val;
5470
5471                 val = vid * vid;
5472                 val *= (freq / 1000);
5473                 val *= 255;
5474                 val /= (127*127*900);
5475                 if (val > 0xff)
5476                         DRM_ERROR("bad pxval: %ld\n", val);
5477                 pxw[i] = val;
5478         }
5479         /* Render standby states get 0 weight */
5480         pxw[14] = 0;
5481         pxw[15] = 0;
5482
5483         for (i = 0; i < 4; i++) {
5484                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5485                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5486                 I915_WRITE(PXW + (i * 4), val);
5487         }
5488
5489         /* Adjust magic regs to magic values (more experimental results) */
5490         I915_WRITE(OGW0, 0);
5491         I915_WRITE(OGW1, 0);
5492         I915_WRITE(EG0, 0x00007f00);
5493         I915_WRITE(EG1, 0x0000000e);
5494         I915_WRITE(EG2, 0x000e0000);
5495         I915_WRITE(EG3, 0x68000300);
5496         I915_WRITE(EG4, 0x42000000);
5497         I915_WRITE(EG5, 0x00140031);
5498         I915_WRITE(EG6, 0);
5499         I915_WRITE(EG7, 0);
5500
5501         for (i = 0; i < 8; i++)
5502                 I915_WRITE(PXWL + (i * 4), 0);
5503
5504         /* Enable PMON + select events */
5505         I915_WRITE(ECR, 0x80000019);
5506
5507         lcfuse = I915_READ(LCFUSE02);
5508
5509         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5510 }
5511
5512 void intel_init_clock_gating(struct drm_device *dev)
5513 {
5514         struct drm_i915_private *dev_priv = dev->dev_private;
5515
5516         /*
5517          * Disable clock gating reported to work incorrectly according to the
5518          * specs, but enable as much else as we can.
5519          */
5520         if (HAS_PCH_SPLIT(dev)) {
5521                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5522
5523                 if (IS_IRONLAKE(dev)) {
5524                         /* Required for FBC */
5525                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5526                         /* Required for CxSR */
5527                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5528
5529                         I915_WRITE(PCH_3DCGDIS0,
5530                                    MARIUNIT_CLOCK_GATE_DISABLE |
5531                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5532                 }
5533
5534                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5535
5536                 /*
5537                  * According to the spec the following bits should be set in
5538                  * order to enable memory self-refresh
5539                  * The bit 22/21 of 0x42004
5540                  * The bit 5 of 0x42020
5541                  * The bit 15 of 0x45000
5542                  */
5543                 if (IS_IRONLAKE(dev)) {
5544                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5545                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5546                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5547                         I915_WRITE(ILK_DSPCLK_GATE,
5548                                         (I915_READ(ILK_DSPCLK_GATE) |
5549                                                 ILK_DPARB_CLK_GATE));
5550                         I915_WRITE(DISP_ARB_CTL,
5551                                         (I915_READ(DISP_ARB_CTL) |
5552                                                 DISP_FBC_WM_DIS));
5553                 }
5554                 /*
5555                  * Based on the document from hardware guys the following bits
5556                  * should be set unconditionally in order to enable FBC.
5557                  * The bit 22 of 0x42000
5558                  * The bit 22 of 0x42004
5559                  * The bit 7,8,9 of 0x42020.
5560                  */
5561                 if (IS_IRONLAKE_M(dev)) {
5562                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5563                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5564                                    ILK_FBCQ_DIS);
5565                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5566                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5567                                    ILK_DPARB_GATE);
5568                         I915_WRITE(ILK_DSPCLK_GATE,
5569                                    I915_READ(ILK_DSPCLK_GATE) |
5570                                    ILK_DPFC_DIS1 |
5571                                    ILK_DPFC_DIS2 |
5572                                    ILK_CLK_FBC);
5573                 }
5574                 return;
5575         } else if (IS_G4X(dev)) {
5576                 uint32_t dspclk_gate;
5577                 I915_WRITE(RENCLK_GATE_D1, 0);
5578                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5579                        GS_UNIT_CLOCK_GATE_DISABLE |
5580                        CL_UNIT_CLOCK_GATE_DISABLE);
5581                 I915_WRITE(RAMCLK_GATE_D, 0);
5582                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5583                         OVRUNIT_CLOCK_GATE_DISABLE |
5584                         OVCUNIT_CLOCK_GATE_DISABLE;
5585                 if (IS_GM45(dev))
5586                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5587                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5588         } else if (IS_I965GM(dev)) {
5589                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5590                 I915_WRITE(RENCLK_GATE_D2, 0);
5591                 I915_WRITE(DSPCLK_GATE_D, 0);
5592                 I915_WRITE(RAMCLK_GATE_D, 0);
5593                 I915_WRITE16(DEUC, 0);
5594         } else if (IS_I965G(dev)) {
5595                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5596                        I965_RCC_CLOCK_GATE_DISABLE |
5597                        I965_RCPB_CLOCK_GATE_DISABLE |
5598                        I965_ISC_CLOCK_GATE_DISABLE |
5599                        I965_FBC_CLOCK_GATE_DISABLE);
5600                 I915_WRITE(RENCLK_GATE_D2, 0);
5601         } else if (IS_I9XX(dev)) {
5602                 u32 dstate = I915_READ(D_STATE);
5603
5604                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5605                         DSTATE_DOT_CLOCK_GATING;
5606                 I915_WRITE(D_STATE, dstate);
5607         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5608                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5609         } else if (IS_I830(dev)) {
5610                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5611         }
5612
5613         /*
5614          * GPU can automatically power down the render unit if given a page
5615          * to save state.
5616          */
5617         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5618                 struct drm_i915_gem_object *obj_priv = NULL;
5619
5620                 if (dev_priv->pwrctx) {
5621                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5622                 } else {
5623                         struct drm_gem_object *pwrctx;
5624
5625                         pwrctx = intel_alloc_power_context(dev);
5626                         if (pwrctx) {
5627                                 dev_priv->pwrctx = pwrctx;
5628                                 obj_priv = to_intel_bo(pwrctx);
5629                         }
5630                 }
5631
5632                 if (obj_priv) {
5633                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5634                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5635                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5636                 }
5637         }
5638 }
5639
5640 /* Set up chip specific display functions */
5641 static void intel_init_display(struct drm_device *dev)
5642 {
5643         struct drm_i915_private *dev_priv = dev->dev_private;
5644
5645         /* We always want a DPMS function */
5646         if (HAS_PCH_SPLIT(dev))
5647                 dev_priv->display.dpms = ironlake_crtc_dpms;
5648         else
5649                 dev_priv->display.dpms = i9xx_crtc_dpms;
5650
5651         if (I915_HAS_FBC(dev)) {
5652                 if (IS_IRONLAKE_M(dev)) {
5653                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5654                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5655                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5656                 } else if (IS_GM45(dev)) {
5657                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5658                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5659                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5660                 } else if (IS_I965GM(dev)) {
5661                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5662                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5663                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5664                 }
5665                 /* 855GM needs testing */
5666         }
5667
5668         /* Returns the core display clock speed */
5669         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5670                 dev_priv->display.get_display_clock_speed =
5671                         i945_get_display_clock_speed;
5672         else if (IS_I915G(dev))
5673                 dev_priv->display.get_display_clock_speed =
5674                         i915_get_display_clock_speed;
5675         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5676                 dev_priv->display.get_display_clock_speed =
5677                         i9xx_misc_get_display_clock_speed;
5678         else if (IS_I915GM(dev))
5679                 dev_priv->display.get_display_clock_speed =
5680                         i915gm_get_display_clock_speed;
5681         else if (IS_I865G(dev))
5682                 dev_priv->display.get_display_clock_speed =
5683                         i865_get_display_clock_speed;
5684         else if (IS_I85X(dev))
5685                 dev_priv->display.get_display_clock_speed =
5686                         i855_get_display_clock_speed;
5687         else /* 852, 830 */
5688                 dev_priv->display.get_display_clock_speed =
5689                         i830_get_display_clock_speed;
5690
5691         /* For FIFO watermark updates */
5692         if (HAS_PCH_SPLIT(dev)) {
5693                 if (IS_IRONLAKE(dev)) {
5694                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5695                                 dev_priv->display.update_wm = ironlake_update_wm;
5696                         else {
5697                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5698                                               "Disable CxSR\n");
5699                                 dev_priv->display.update_wm = NULL;
5700                         }
5701                 } else
5702                         dev_priv->display.update_wm = NULL;
5703         } else if (IS_PINEVIEW(dev)) {
5704                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5705                                             dev_priv->is_ddr3,
5706                                             dev_priv->fsb_freq,
5707                                             dev_priv->mem_freq)) {
5708                         DRM_INFO("failed to find known CxSR latency "
5709                                  "(found ddr%s fsb freq %d, mem freq %d), "
5710                                  "disabling CxSR\n",
5711                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5712                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5713                         /* Disable CxSR and never update its watermark again */
5714                         pineview_disable_cxsr(dev);
5715                         dev_priv->display.update_wm = NULL;
5716                 } else
5717                         dev_priv->display.update_wm = pineview_update_wm;
5718         } else if (IS_G4X(dev))
5719                 dev_priv->display.update_wm = g4x_update_wm;
5720         else if (IS_I965G(dev))
5721                 dev_priv->display.update_wm = i965_update_wm;
5722         else if (IS_I9XX(dev)) {
5723                 dev_priv->display.update_wm = i9xx_update_wm;
5724                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5725         } else if (IS_I85X(dev)) {
5726                 dev_priv->display.update_wm = i9xx_update_wm;
5727                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5728         } else {
5729                 dev_priv->display.update_wm = i830_update_wm;
5730                 if (IS_845G(dev))
5731                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5732                 else
5733                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5734         }
5735 }
5736
5737 /*
5738  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5739  * resume, or other times.  This quirk makes sure that's the case for
5740  * affected systems.
5741  */
5742 static void quirk_pipea_force (struct drm_device *dev)
5743 {
5744         struct drm_i915_private *dev_priv = dev->dev_private;
5745
5746         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5747         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5748 }
5749
5750 struct intel_quirk {
5751         int device;
5752         int subsystem_vendor;
5753         int subsystem_device;
5754         void (*hook)(struct drm_device *dev);
5755 };
5756
5757 struct intel_quirk intel_quirks[] = {
5758         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5759         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5760         /* HP Mini needs pipe A force quirk (LP: #322104) */
5761         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5762
5763         /* Thinkpad R31 needs pipe A force quirk */
5764         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5765         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5766         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5767
5768         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5769         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5770         /* ThinkPad X40 needs pipe A force quirk */
5771
5772         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5773         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5774
5775         /* 855 & before need to leave pipe A & dpll A up */
5776         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5777         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5778 };
5779
5780 static void intel_init_quirks(struct drm_device *dev)
5781 {
5782         struct pci_dev *d = dev->pdev;
5783         int i;
5784
5785         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5786                 struct intel_quirk *q = &intel_quirks[i];
5787
5788                 if (d->device == q->device &&
5789                     (d->subsystem_vendor == q->subsystem_vendor ||
5790                      q->subsystem_vendor == PCI_ANY_ID) &&
5791                     (d->subsystem_device == q->subsystem_device ||
5792                      q->subsystem_device == PCI_ANY_ID))
5793                         q->hook(dev);
5794         }
5795 }
5796
5797 void intel_modeset_init(struct drm_device *dev)
5798 {
5799         struct drm_i915_private *dev_priv = dev->dev_private;
5800         int i;
5801
5802         drm_mode_config_init(dev);
5803
5804         dev->mode_config.min_width = 0;
5805         dev->mode_config.min_height = 0;
5806
5807         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5808
5809         intel_init_quirks(dev);
5810
5811         intel_init_display(dev);
5812
5813         if (IS_I965G(dev)) {
5814                 dev->mode_config.max_width = 8192;
5815                 dev->mode_config.max_height = 8192;
5816         } else if (IS_I9XX(dev)) {
5817                 dev->mode_config.max_width = 4096;
5818                 dev->mode_config.max_height = 4096;
5819         } else {
5820                 dev->mode_config.max_width = 2048;
5821                 dev->mode_config.max_height = 2048;
5822         }
5823
5824         /* set memory base */
5825         if (IS_I9XX(dev))
5826                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5827         else
5828                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5829
5830         if (IS_MOBILE(dev) || IS_I9XX(dev))
5831                 dev_priv->num_pipe = 2;
5832         else
5833                 dev_priv->num_pipe = 1;
5834         DRM_DEBUG_KMS("%d display pipe%s available.\n",
5835                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
5836
5837         for (i = 0; i < dev_priv->num_pipe; i++) {
5838                 intel_crtc_init(dev, i);
5839         }
5840
5841         intel_setup_outputs(dev);
5842
5843         intel_init_clock_gating(dev);
5844
5845         if (IS_IRONLAKE_M(dev)) {
5846                 ironlake_enable_drps(dev);
5847                 intel_init_emon(dev);
5848         }
5849
5850         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5851         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5852                     (unsigned long)dev);
5853
5854         intel_setup_overlay(dev);
5855 }
5856
5857 void intel_modeset_cleanup(struct drm_device *dev)
5858 {
5859         struct drm_i915_private *dev_priv = dev->dev_private;
5860         struct drm_crtc *crtc;
5861         struct intel_crtc *intel_crtc;
5862
5863         mutex_lock(&dev->struct_mutex);
5864
5865         drm_kms_helper_poll_fini(dev);
5866         intel_fbdev_fini(dev);
5867
5868         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5869                 /* Skip inactive CRTCs */
5870                 if (!crtc->fb)
5871                         continue;
5872
5873                 intel_crtc = to_intel_crtc(crtc);
5874                 intel_increase_pllclock(crtc, false);
5875                 del_timer_sync(&intel_crtc->idle_timer);
5876         }
5877
5878         del_timer_sync(&dev_priv->idle_timer);
5879
5880         if (dev_priv->display.disable_fbc)
5881                 dev_priv->display.disable_fbc(dev);
5882
5883         if (dev_priv->pwrctx) {
5884                 struct drm_i915_gem_object *obj_priv;
5885
5886                 obj_priv = to_intel_bo(dev_priv->pwrctx);
5887                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5888                 I915_READ(PWRCTXA);
5889                 i915_gem_object_unpin(dev_priv->pwrctx);
5890                 drm_gem_object_unreference(dev_priv->pwrctx);
5891         }
5892
5893         if (IS_IRONLAKE_M(dev))
5894                 ironlake_disable_drps(dev);
5895
5896         mutex_unlock(&dev->struct_mutex);
5897
5898         drm_mode_config_cleanup(dev);
5899 }
5900
5901
5902 /*
5903  * Return which encoder is currently attached for connector.
5904  */
5905 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5906 {
5907         struct drm_mode_object *obj;
5908         struct drm_encoder *encoder;
5909         int i;
5910
5911         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5912                 if (connector->encoder_ids[i] == 0)
5913                         break;
5914
5915                 obj = drm_mode_object_find(connector->dev,
5916                                            connector->encoder_ids[i],
5917                                            DRM_MODE_OBJECT_ENCODER);
5918                 if (!obj)
5919                         continue;
5920
5921                 encoder = obj_to_encoder(obj);
5922                 return encoder;
5923         }
5924         return NULL;
5925 }
5926
5927 /*
5928  * set vga decode state - true == enable VGA decode
5929  */
5930 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5931 {
5932         struct drm_i915_private *dev_priv = dev->dev_private;
5933         u16 gmch_ctrl;
5934
5935         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5936         if (state)
5937                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5938         else
5939                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5940         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5941         return 0;
5942 }