drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75         DRM_FORMAT_YUYV,
  76         DRM_FORMAT_YVYU,
  77         DRM_FORMAT_UYVY,
  78         DRM_FORMAT_VYUY,
  79 };
  80
  81 /* Cursor formats */
  82 static const uint32_t intel_cursor_formats[] = {
  83         DRM_FORMAT_ARGB8888,
  84 };
  85
  86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119
 120 typedef struct {
 121         int     min, max;
 122 } intel_range_t;
 123
 124 typedef struct {
 125         int     dot_limit;
 126         int     p2_slow, p2_fast;
 127 } intel_p2_t;
 128
 129 typedef struct intel_limit intel_limit_t;
 130 struct intel_limit {
 131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 132         intel_p2_t          p2;
 133 };
 134
 135 /* returns HPLL frequency in kHz */
 136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 137 {
 138         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 139
 140         /* Obtain SKU information */
 141         mutex_lock(&dev_priv->sb_lock);
 142         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 143                 CCK_FUSE_HPLL_FREQ_MASK;
 144         mutex_unlock(&dev_priv->sb_lock);
 145
 146         return vco_freq[hpll_freq] * 1000;
 147 }
 148
 149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 150                                   const char *name, u32 reg)
 151 {
 152         u32 val;
 153         int divider;
 154
 155         if (dev_priv->hpll_freq == 0)
 156                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 157
 158         mutex_lock(&dev_priv->sb_lock);
 159         val = vlv_cck_read(dev_priv, reg);
 160         mutex_unlock(&dev_priv->sb_lock);
 161
 162         divider = val & CCK_FREQUENCY_VALUES;
 163
 164         WARN((val & CCK_FREQUENCY_STATUS) !=
 165              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 166              "%s change in progress\n", name);
 167
 168         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 169 }
 170
 171 int
 172 intel_pch_rawclk(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175
 176         WARN_ON(!HAS_PCH_SPLIT(dev));
 177
 178         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 179 }
 180
 181 /* hrawclock is 1/4 the FSB frequency */
 182 int intel_hrawclk(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         uint32_t clkcfg;
 186
 187         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 188         if (IS_VALLEYVIEW(dev))
 189                 return 200;
 190
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100;
 195         case CLKCFG_FSB_533:
 196                 return 133;
 197         case CLKCFG_FSB_667:
 198                 return 166;
 199         case CLKCFG_FSB_800:
 200                 return 200;
 201         case CLKCFG_FSB_1067:
 202                 return 266;
 203         case CLKCFG_FSB_1333:
 204                 return 333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400;
 209         default:
 210                 return 133;
 211         }
 212 }
 213
 214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (!IS_VALLEYVIEW(dev_priv))
 217                 return;
 218
 219         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 220                                                       CCK_CZ_CLOCK_CONTROL);
 221
 222         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 223 }
 224
 225 static inline u32 /* units of 100MHz */
 226 intel_fdi_link_freq(struct drm_device *dev)
 227 {
 228         if (IS_GEN5(dev)) {
 229                 struct drm_i915_private *dev_priv = dev->dev_private;
 230                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 231         } else
 232                 return 27;
 233 }
 234
 235 static const intel_limit_t intel_limits_i8xx_dac = {
 236         .dot = { .min = 25000, .max = 350000 },
 237         .vco = { .min = 908000, .max = 1512000 },
 238         .n = { .min = 2, .max = 16 },
 239         .m = { .min = 96, .max = 140 },
 240         .m1 = { .min = 18, .max = 26 },
 241         .m2 = { .min = 6, .max = 16 },
 242         .p = { .min = 4, .max = 128 },
 243         .p1 = { .min = 2, .max = 33 },
 244         .p2 = { .dot_limit = 165000,
 245                 .p2_slow = 4, .p2_fast = 2 },
 246 };
 247
 248 static const intel_limit_t intel_limits_i8xx_dvo = {
 249         .dot = { .min = 25000, .max = 350000 },
 250         .vco = { .min = 908000, .max = 1512000 },
 251         .n = { .min = 2, .max = 16 },
 252         .m = { .min = 96, .max = 140 },
 253         .m1 = { .min = 18, .max = 26 },
 254         .m2 = { .min = 6, .max = 16 },
 255         .p = { .min = 4, .max = 128 },
 256         .p1 = { .min = 2, .max = 33 },
 257         .p2 = { .dot_limit = 165000,
 258                 .p2_slow = 4, .p2_fast = 4 },
 259 };
 260
 261 static const intel_limit_t intel_limits_i8xx_lvds = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 908000, .max = 1512000 },
 264         .n = { .min = 2, .max = 16 },
 265         .m = { .min = 96, .max = 140 },
 266         .m1 = { .min = 18, .max = 26 },
 267         .m2 = { .min = 6, .max = 16 },
 268         .p = { .min = 4, .max = 128 },
 269         .p1 = { .min = 1, .max = 6 },
 270         .p2 = { .dot_limit = 165000,
 271                 .p2_slow = 14, .p2_fast = 7 },
 272 };
 273
 274 static const intel_limit_t intel_limits_i9xx_sdvo = {
 275         .dot = { .min = 20000, .max = 400000 },
 276         .vco = { .min = 1400000, .max = 2800000 },
 277         .n = { .min = 1, .max = 6 },
 278         .m = { .min = 70, .max = 120 },
 279         .m1 = { .min = 8, .max = 18 },
 280         .m2 = { .min = 3, .max = 7 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 200000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285 };
 286
 287 static const intel_limit_t intel_limits_i9xx_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1400000, .max = 2800000 },
 290         .n = { .min = 1, .max = 6 },
 291         .m = { .min = 70, .max = 120 },
 292         .m1 = { .min = 8, .max = 18 },
 293         .m2 = { .min = 3, .max = 7 },
 294         .p = { .min = 7, .max = 98 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 7 },
 298 };
 299
 300
 301 static const intel_limit_t intel_limits_g4x_sdvo = {
 302         .dot = { .min = 25000, .max = 270000 },
 303         .vco = { .min = 1750000, .max = 3500000},
 304         .n = { .min = 1, .max = 4 },
 305         .m = { .min = 104, .max = 138 },
 306         .m1 = { .min = 17, .max = 23 },
 307         .m2 = { .min = 5, .max = 11 },
 308         .p = { .min = 10, .max = 30 },
 309         .p1 = { .min = 1, .max = 3},
 310         .p2 = { .dot_limit = 270000,
 311                 .p2_slow = 10,
 312                 .p2_fast = 10
 313         },
 314 };
 315
 316 static const intel_limit_t intel_limits_g4x_hdmi = {
 317         .dot = { .min = 22000, .max = 400000 },
 318         .vco = { .min = 1750000, .max = 3500000},
 319         .n = { .min = 1, .max = 4 },
 320         .m = { .min = 104, .max = 138 },
 321         .m1 = { .min = 16, .max = 23 },
 322         .m2 = { .min = 5, .max = 11 },
 323         .p = { .min = 5, .max = 80 },
 324         .p1 = { .min = 1, .max = 8},
 325         .p2 = { .dot_limit = 165000,
 326                 .p2_slow = 10, .p2_fast = 5 },
 327 };
 328
 329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 330         .dot = { .min = 20000, .max = 115000 },
 331         .vco = { .min = 1750000, .max = 3500000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 28, .max = 112 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 0,
 339                 .p2_slow = 14, .p2_fast = 14
 340         },
 341 };
 342
 343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 344         .dot = { .min = 80000, .max = 224000 },
 345         .vco = { .min = 1750000, .max = 3500000 },
 346         .n = { .min = 1, .max = 3 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 17, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 14, .max = 42 },
 351         .p1 = { .min = 2, .max = 6 },
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 7, .p2_fast = 7
 354         },
 355 };
 356
 357 static const intel_limit_t intel_limits_pineview_sdvo = {
 358         .dot = { .min = 20000, .max = 400000},
 359         .vco = { .min = 1700000, .max = 3500000 },
 360         /* Pineview's Ncounter is a ring counter */
 361         .n = { .min = 3, .max = 6 },
 362         .m = { .min = 2, .max = 256 },
 363         /* Pineview only has one combined m divider, which we treat as m2. */
 364         .m1 = { .min = 0, .max = 0 },
 365         .m2 = { .min = 0, .max = 254 },
 366         .p = { .min = 5, .max = 80 },
 367         .p1 = { .min = 1, .max = 8 },
 368         .p2 = { .dot_limit = 200000,
 369                 .p2_slow = 10, .p2_fast = 5 },
 370 };
 371
 372 static const intel_limit_t intel_limits_pineview_lvds = {
 373         .dot = { .min = 20000, .max = 400000 },
 374         .vco = { .min = 1700000, .max = 3500000 },
 375         .n = { .min = 3, .max = 6 },
 376         .m = { .min = 2, .max = 256 },
 377         .m1 = { .min = 0, .max = 0 },
 378         .m2 = { .min = 0, .max = 254 },
 379         .p = { .min = 7, .max = 112 },
 380         .p1 = { .min = 1, .max = 8 },
 381         .p2 = { .dot_limit = 112000,
 382                 .p2_slow = 14, .p2_fast = 14 },
 383 };
 384
 385 /* Ironlake / Sandybridge
 386  *
 387  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 388  * the range value for them is (actual_value - 2).
 389  */
 390 static const intel_limit_t intel_limits_ironlake_dac = {
 391         .dot = { .min = 25000, .max = 350000 },
 392         .vco = { .min = 1760000, .max = 3510000 },
 393         .n = { .min = 1, .max = 5 },
 394         .m = { .min = 79, .max = 127 },
 395         .m1 = { .min = 12, .max = 22 },
 396         .m2 = { .min = 5, .max = 9 },
 397         .p = { .min = 5, .max = 80 },
 398         .p1 = { .min = 1, .max = 8 },
 399         .p2 = { .dot_limit = 225000,
 400                 .p2_slow = 10, .p2_fast = 5 },
 401 };
 402
 403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 404         .dot = { .min = 25000, .max = 350000 },
 405         .vco = { .min = 1760000, .max = 3510000 },
 406         .n = { .min = 1, .max = 3 },
 407         .m = { .min = 79, .max = 118 },
 408         .m1 = { .min = 12, .max = 22 },
 409         .m2 = { .min = 5, .max = 9 },
 410         .p = { .min = 28, .max = 112 },
 411         .p1 = { .min = 2, .max = 8 },
 412         .p2 = { .dot_limit = 225000,
 413                 .p2_slow = 14, .p2_fast = 14 },
 414 };
 415
 416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 417         .dot = { .min = 25000, .max = 350000 },
 418         .vco = { .min = 1760000, .max = 3510000 },
 419         .n = { .min = 1, .max = 3 },
 420         .m = { .min = 79, .max = 127 },
 421         .m1 = { .min = 12, .max = 22 },
 422         .m2 = { .min = 5, .max = 9 },
 423         .p = { .min = 14, .max = 56 },
 424         .p1 = { .min = 2, .max = 8 },
 425         .p2 = { .dot_limit = 225000,
 426                 .p2_slow = 7, .p2_fast = 7 },
 427 };
 428
 429 /* LVDS 100mhz refclk limits. */
 430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 2 },
 434         .m = { .min = 79, .max = 126 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 126 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 42 },
 451         .p1 = { .min = 2, .max = 6 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 static const intel_limit_t intel_limits_vlv = {
 457          /*
 458           * These are the data rate limits (measured in fast clocks)
 459           * since those are the strictest limits we have. The fast
 460           * clock and actual rate limits are more relaxed, so checking
 461           * them would make no difference.
 462           */
 463         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 464         .vco = { .min = 4000000, .max = 6000000 },
 465         .n = { .min = 1, .max = 7 },
 466         .m1 = { .min = 2, .max = 3 },
 467         .m2 = { .min = 11, .max = 156 },
 468         .p1 = { .min = 2, .max = 3 },
 469         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 470 };
 471
 472 static const intel_limit_t intel_limits_chv = {
 473         /*
 474          * These are the data rate limits (measured in fast clocks)
 475          * since those are the strictest limits we have.  The fast
 476          * clock and actual rate limits are more relaxed, so checking
 477          * them would make no difference.
 478          */
 479         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 480         .vco = { .min = 4800000, .max = 6480000 },
 481         .n = { .min = 1, .max = 1 },
 482         .m1 = { .min = 2, .max = 2 },
 483         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 484         .p1 = { .min = 2, .max = 4 },
 485         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 486 };
 487
 488 static const intel_limit_t intel_limits_bxt = {
 489         /* FIXME: find real dot limits */
 490         .dot = { .min = 0, .max = INT_MAX },
 491         .vco = { .min = 4800000, .max = 6700000 },
 492         .n = { .min = 1, .max = 1 },
 493         .m1 = { .min = 2, .max = 2 },
 494         /* FIXME: find real m2 limits */
 495         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 496         .p1 = { .min = 2, .max = 4 },
 497         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 498 };
 499
 500 static bool
 501 needs_modeset(struct drm_crtc_state *state)
 502 {
 503         return drm_atomic_crtc_needs_modeset(state);
 504 }
 505
 506 /**
 507  * Returns whether any output on the specified pipe is of the specified type
 508  */
 509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 510 {
 511         struct drm_device *dev = crtc->base.dev;
 512         struct intel_encoder *encoder;
 513
 514         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 515                 if (encoder->type == type)
 516                         return true;
 517
 518         return false;
 519 }
 520
 521 /**
 522  * Returns whether any output on the specified pipe will have the specified
 523  * type after a staged modeset is complete, i.e., the same as
 524  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 525  * encoder->crtc.
 526  */
 527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 528                                       int type)
 529 {
 530         struct drm_atomic_state *state = crtc_state->base.state;
 531         struct drm_connector *connector;
 532         struct drm_connector_state *connector_state;
 533         struct intel_encoder *encoder;
 534         int i, num_connectors = 0;
 535
 536         for_each_connector_in_state(state, connector, connector_state, i) {
 537                 if (connector_state->crtc != crtc_state->base.crtc)
 538                         continue;
 539
 540                 num_connectors++;
 541
 542                 encoder = to_intel_encoder(connector_state->best_encoder);
 543                 if (encoder->type == type)
 544                         return true;
 545         }
 546
 547         WARN_ON(num_connectors == 0);
 548
 549         return false;
 550 }
 551
 552 static const intel_limit_t *
 553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 554 {
 555         struct drm_device *dev = crtc_state->base.crtc->dev;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 559                 if (intel_is_dual_link_lvds(dev)) {
 560                         if (refclk == 100000)
 561                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 562                         else
 563                                 limit = &intel_limits_ironlake_dual_lvds;
 564                 } else {
 565                         if (refclk == 100000)
 566                                 limit = &intel_limits_ironlake_single_lvds_100m;
 567                         else
 568                                 limit = &intel_limits_ironlake_single_lvds;
 569                 }
 570         } else
 571                 limit = &intel_limits_ironlake_dac;
 572
 573         return limit;
 574 }
 575
 576 static const intel_limit_t *
 577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 578 {
 579         struct drm_device *dev = crtc_state->base.crtc->dev;
 580         const intel_limit_t *limit;
 581
 582         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 583                 if (intel_is_dual_link_lvds(dev))
 584                         limit = &intel_limits_g4x_dual_channel_lvds;
 585                 else
 586                         limit = &intel_limits_g4x_single_channel_lvds;
 587         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 588                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 589                 limit = &intel_limits_g4x_hdmi;
 590         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 591                 limit = &intel_limits_g4x_sdvo;
 592         } else /* The option is for other outputs */
 593                 limit = &intel_limits_i9xx_sdvo;
 594
 595         return limit;
 596 }
 597
 598 static const intel_limit_t *
 599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 600 {
 601         struct drm_device *dev = crtc_state->base.crtc->dev;
 602         const intel_limit_t *limit;
 603
 604         if (IS_BROXTON(dev))
 605                 limit = &intel_limits_bxt;
 606         else if (HAS_PCH_SPLIT(dev))
 607                 limit = intel_ironlake_limit(crtc_state, refclk);
 608         else if (IS_G4X(dev)) {
 609                 limit = intel_g4x_limit(crtc_state);
 610         } else if (IS_PINEVIEW(dev)) {
 611                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 612                         limit = &intel_limits_pineview_lvds;
 613                 else
 614                         limit = &intel_limits_pineview_sdvo;
 615         } else if (IS_CHERRYVIEW(dev)) {
 616                 limit = &intel_limits_chv;
 617         } else if (IS_VALLEYVIEW(dev)) {
 618                 limit = &intel_limits_vlv;
 619         } else if (!IS_GEN2(dev)) {
 620                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 621                         limit = &intel_limits_i9xx_lvds;
 622                 else
 623                         limit = &intel_limits_i9xx_sdvo;
 624         } else {
 625                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 626                         limit = &intel_limits_i8xx_lvds;
 627                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 628                         limit = &intel_limits_i8xx_dvo;
 629                 else
 630                         limit = &intel_limits_i8xx_dac;
 631         }
 632         return limit;
 633 }
 634
 635 /*
 636  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 637  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 638  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 639  * The helpers' return value is the rate of the clock that is fed to the
 640  * display engine's pipe which can be the above fast dot clock rate or a
 641  * divided-down version of it.
 642  */
 643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 645 {
 646         clock->m = clock->m2 + 2;
 647         clock->p = clock->p1 * clock->p2;
 648         if (WARN_ON(clock->n == 0 || clock->p == 0))
 649                 return 0;
 650         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 651         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 652
 653         return clock->dot;
 654 }
 655
 656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 657 {
 658         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 659 }
 660
 661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 662 {
 663         clock->m = i9xx_dpll_compute_m(clock);
 664         clock->p = clock->p1 * clock->p2;
 665         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 666                 return 0;
 667         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 668         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 669
 670         return clock->dot;
 671 }
 672
 673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 674 {
 675         clock->m = clock->m1 * clock->m2;
 676         clock->p = clock->p1 * clock->p2;
 677         if (WARN_ON(clock->n == 0 || clock->p == 0))
 678                 return 0;
 679         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 680         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 681
 682         return clock->dot / 5;
 683 }
 684
 685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 686 {
 687         clock->m = clock->m1 * clock->m2;
 688         clock->p = clock->p1 * clock->p2;
 689         if (WARN_ON(clock->n == 0 || clock->p == 0))
 690                 return 0;
 691         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 692                         clock->n << 22);
 693         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 694
 695         return clock->dot / 5;
 696 }
 697
 698 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 699 /**
 700  * Returns whether the given set of divisors are valid for a given refclk with
 701  * the given connectors.
 702  */
 703
 704 static bool intel_PLL_is_valid(struct drm_device *dev,
 705                                const intel_limit_t *limit,
 706                                const intel_clock_t *clock)
 707 {
 708         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 709                 INTELPllInvalid("n out of range\n");
 710         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 711                 INTELPllInvalid("p1 out of range\n");
 712         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 713                 INTELPllInvalid("m2 out of range\n");
 714         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 715                 INTELPllInvalid("m1 out of range\n");
 716
 717         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 718                 if (clock->m1 <= clock->m2)
 719                         INTELPllInvalid("m1 <= m2\n");
 720
 721         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 722                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 723                         INTELPllInvalid("p out of range\n");
 724                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 725                         INTELPllInvalid("m out of range\n");
 726         }
 727
 728         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 729                 INTELPllInvalid("vco out of range\n");
 730         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 731          * connector, etc., rather than just a single range.
 732          */
 733         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 734                 INTELPllInvalid("dot out of range\n");
 735
 736         return true;
 737 }
 738
 739 static int
 740 i9xx_select_p2_div(const intel_limit_t *limit,
 741                    const struct intel_crtc_state *crtc_state,
 742                    int target)
 743 {
 744         struct drm_device *dev = crtc_state->base.crtc->dev;
 745
 746         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 747                 /*
 748                  * For LVDS just rely on its current settings for dual-channel.
 749                  * We haven't figured out how to reliably set up different
 750                  * single/dual channel state, if we even can.
 751                  */
 752                 if (intel_is_dual_link_lvds(dev))
 753                         return limit->p2.p2_fast;
 754                 else
 755                         return limit->p2.p2_slow;
 756         } else {
 757                 if (target < limit->p2.dot_limit)
 758                         return limit->p2.p2_slow;
 759                 else
 760                         return limit->p2.p2_fast;
 761         }
 762 }
 763
 764 static bool
 765 i9xx_find_best_dpll(const intel_limit_t *limit,
 766                     struct intel_crtc_state *crtc_state,
 767                     int target, int refclk, intel_clock_t *match_clock,
 768                     intel_clock_t *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->base.crtc->dev;
 771         intel_clock_t clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         if (clock.m2 >= clock.m1)
 783                                 break;
 784                         for (clock.n = limit->n.min;
 785                              clock.n <= limit->n.max; clock.n++) {
 786                                 for (clock.p1 = limit->p1.min;
 787                                         clock.p1 <= limit->p1.max; clock.p1++) {
 788                                         int this_err;
 789
 790                                         i9xx_calc_dpll_params(refclk, &clock);
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794                                         if (match_clock &&
 795                                             clock.p != match_clock->p)
 796                                                 continue;
 797
 798                                         this_err = abs(clock.dot - target);
 799                                         if (this_err < err) {
 800                                                 *best_clock = clock;
 801                                                 err = this_err;
 802                                         }
 803                                 }
 804                         }
 805                 }
 806         }
 807
 808         return (err != target);
 809 }
 810
 811 static bool
 812 pnv_find_best_dpll(const intel_limit_t *limit,
 813                    struct intel_crtc_state *crtc_state,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc_state->base.crtc->dev;
 818         intel_clock_t clock;
 819         int err = target;
 820
 821         memset(best_clock, 0, sizeof(*best_clock));
 822
 823         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 824
 825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 826              clock.m1++) {
 827                 for (clock.m2 = limit->m2.min;
 828                      clock.m2 <= limit->m2.max; clock.m2++) {
 829                         for (clock.n = limit->n.min;
 830                              clock.n <= limit->n.max; clock.n++) {
 831                                 for (clock.p1 = limit->p1.min;
 832                                         clock.p1 <= limit->p1.max; clock.p1++) {
 833                                         int this_err;
 834
 835                                         pnv_calc_dpll_params(refclk, &clock);
 836                                         if (!intel_PLL_is_valid(dev, limit,
 837                                                                 &clock))
 838                                                 continue;
 839                                         if (match_clock &&
 840                                             clock.p != match_clock->p)
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err) {
 845                                                 *best_clock = clock;
 846                                                 err = this_err;
 847                                         }
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         return (err != target);
 854 }
 855
 856 static bool
 857 g4x_find_best_dpll(const intel_limit_t *limit,
 858                    struct intel_crtc_state *crtc_state,
 859                    int target, int refclk, intel_clock_t *match_clock,
 860                    intel_clock_t *best_clock)
 861 {
 862         struct drm_device *dev = crtc_state->base.crtc->dev;
 863         intel_clock_t clock;
 864         int max_n;
 865         bool found = false;
 866         /* approximately equals target * 0.00585 */
 867         int err_most = (target >> 8) + (target >> 9);
 868
 869         memset(best_clock, 0, sizeof(*best_clock));
 870
 871         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 872
 873         max_n = limit->n.max;
 874         /* based on hardware requirement, prefer smaller n to precision */
 875         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 876                 /* based on hardware requirement, prefere larger m1,m2 */
 877                 for (clock.m1 = limit->m1.max;
 878                      clock.m1 >= limit->m1.min; clock.m1--) {
 879                         for (clock.m2 = limit->m2.max;
 880                              clock.m2 >= limit->m2.min; clock.m2--) {
 881                                 for (clock.p1 = limit->p1.max;
 882                                      clock.p1 >= limit->p1.min; clock.p1--) {
 883                                         int this_err;
 884
 885                                         i9xx_calc_dpll_params(refclk, &clock);
 886                                         if (!intel_PLL_is_valid(dev, limit,
 887                                                                 &clock))
 888                                                 continue;
 889
 890                                         this_err = abs(clock.dot - target);
 891                                         if (this_err < err_most) {
 892                                                 *best_clock = clock;
 893                                                 err_most = this_err;
 894                                                 max_n = clock.n;
 895                                                 found = true;
 896                                         }
 897                                 }
 898                         }
 899                 }
 900         }
 901         return found;
 902 }
 903
 904 /*
 905  * Check if the calculated PLL configuration is more optimal compared to the
 906  * best configuration and error found so far. Return the calculated error.
 907  */
 908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 909                                const intel_clock_t *calculated_clock,
 910                                const intel_clock_t *best_clock,
 911                                unsigned int best_error_ppm,
 912                                unsigned int *error_ppm)
 913 {
 914         /*
 915          * For CHV ignore the error and consider only the P value.
 916          * Prefer a bigger P value based on HW requirements.
 917          */
 918         if (IS_CHERRYVIEW(dev)) {
 919                 *error_ppm = 0;
 920
 921                 return calculated_clock->p > best_clock->p;
 922         }
 923
 924         if (WARN_ON_ONCE(!target_freq))
 925                 return false;
 926
 927         *error_ppm = div_u64(1000000ULL *
 928                                 abs(target_freq - calculated_clock->dot),
 929                              target_freq);
 930         /*
 931          * Prefer a better P value over a better (smaller) error if the error
 932          * is small. Ensure this preference for future configurations too by
 933          * setting the error to 0.
 934          */
 935         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 936                 *error_ppm = 0;
 937
 938                 return true;
 939         }
 940
 941         return *error_ppm + 10 < best_error_ppm;
 942 }
 943
 944 static bool
 945 vlv_find_best_dpll(const intel_limit_t *limit,
 946                    struct intel_crtc_state *crtc_state,
 947                    int target, int refclk, intel_clock_t *match_clock,
 948                    intel_clock_t *best_clock)
 949 {
 950         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 951         struct drm_device *dev = crtc->base.dev;
 952         intel_clock_t clock;
 953         unsigned int bestppm = 1000000;
 954         /* min update 19.2 MHz */
 955         int max_n = min(limit->n.max, refclk / 19200);
 956         bool found = false;
 957
 958         target *= 5; /* fast clock */
 959
 960         memset(best_clock, 0, sizeof(*best_clock));
 961
 962         /* based on hardware requirement, prefer smaller n to precision */
 963         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 964                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 965                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 966                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 967                                 clock.p = clock.p1 * clock.p2;
 968                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 969                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 970                                         unsigned int ppm;
 971
 972                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 973                                                                      refclk * clock.m1);
 974
 975                                         vlv_calc_dpll_params(refclk, &clock);
 976
 977                                         if (!intel_PLL_is_valid(dev, limit,
 978                                                                 &clock))
 979                                                 continue;
 980
 981                                         if (!vlv_PLL_is_optimal(dev, target,
 982                                                                 &clock,
 983                                                                 best_clock,
 984                                                                 bestppm, &ppm))
 985                                                 continue;
 986
 987                                         *best_clock = clock;
 988                                         bestppm = ppm;
 989                                         found = true;
 990                                 }
 991                         }
 992                 }
 993         }
 994
 995         return found;
 996 }
 997
 998 static bool
 999 chv_find_best_dpll(const intel_limit_t *limit,
1000                    struct intel_crtc_state *crtc_state,
1001                    int target, int refclk, intel_clock_t *match_clock,
1002                    intel_clock_t *best_clock)
1003 {
1004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005         struct drm_device *dev = crtc->base.dev;
1006         unsigned int best_error_ppm;
1007         intel_clock_t clock;
1008         uint64_t m2;
1009         int found = false;
1010
1011         memset(best_clock, 0, sizeof(*best_clock));
1012         best_error_ppm = 1000000;
1013
1014         /*
1015          * Based on hardware doc, the n always set to 1, and m1 always
1016          * set to 2.  If requires to support 200Mhz refclk, we need to
1017          * revisit this because n may not 1 anymore.
1018          */
1019         clock.n = 1, clock.m1 = 2;
1020         target *= 5;    /* fast clock */
1021
1022         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023                 for (clock.p2 = limit->p2.p2_fast;
1024                                 clock.p2 >= limit->p2.p2_slow;
1025                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026                         unsigned int error_ppm;
1027
1028                         clock.p = clock.p1 * clock.p2;
1029
1030                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031                                         clock.n) << 22, refclk * clock.m1);
1032
1033                         if (m2 > INT_MAX/clock.m1)
1034                                 continue;
1035
1036                         clock.m2 = m2;
1037
1038                         chv_calc_dpll_params(refclk, &clock);
1039
1040                         if (!intel_PLL_is_valid(dev, limit, &clock))
1041                                 continue;
1042
1043                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044                                                 best_error_ppm, &error_ppm))
1045                                 continue;
1046
1047                         *best_clock = clock;
1048                         best_error_ppm = error_ppm;
1049                         found = true;
1050                 }
1051         }
1052
1053         return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057                         intel_clock_t *best_clock)
1058 {
1059         int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062                                   target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069         /* Be paranoid as we can arrive here with only partial
1070          * state retrieved from the hardware during setup.
1071          *
1072          * We can ditch the adjusted_mode.crtc_clock check as soon
1073          * as Haswell has gained clock readout/fastboot support.
1074          *
1075          * We can ditch the crtc->primary->fb check as soon as we can
1076          * properly reconstruct framebuffers.
1077          *
1078          * FIXME: The intel_crtc->active here should be switched to
1079          * crtc->state->active once we have proper CRTC states wired up
1080          * for atomic.
1081          */
1082         return intel_crtc->active && crtc->primary->state->fb &&
1083                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087                                              enum pipe pipe)
1088 {
1089         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092         return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         u32 reg = PIPEDSL(pipe);
1099         u32 line1, line2;
1100         u32 line_mask;
1101
1102         if (IS_GEN2(dev))
1103                 line_mask = DSL_LINEMASK_GEN2;
1104         else
1105                 line_mask = DSL_LINEMASK_GEN3;
1106
1107         line1 = I915_READ(reg) & line_mask;
1108         msleep(5);
1109         line2 = I915_READ(reg) & line_mask;
1110
1111         return line1 == line2;
1112 }
1113
1114 /*
1115  * intel_wait_for_pipe_off - wait for pipe to turn off
1116  * @crtc: crtc whose pipe to wait for
1117  *
1118  * After disabling a pipe, we can't wait for vblank in the usual way,
1119  * spinning on the vblank interrupt status bit, since we won't actually
1120  * see an interrupt when the pipe is disabled.
1121  *
1122  * On Gen4 and above:
1123  *   wait for the pipe register state bit to turn off
1124  *
1125  * Otherwise:
1126  *   wait for the display line value to settle (it usually
1127  *   ends up stopping at the start of the next frame).
1128  *
1129  */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132         struct drm_device *dev = crtc->base.dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135         enum pipe pipe = crtc->pipe;
1136
1137         if (INTEL_INFO(dev)->gen >= 4) {
1138                 int reg = PIPECONF(cpu_transcoder);
1139
1140                 /* Wait for the Pipe State to go off */
1141                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142                              100))
1143                         WARN(1, "pipe_off wait timed out\n");
1144         } else {
1145                 /* Wait for the display line to settle */
1146                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147                         WARN(1, "pipe_off wait timed out\n");
1148         }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153         return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158                 enum pipe pipe, bool state)
1159 {
1160         u32 val;
1161         bool cur_state;
1162
1163         val = I915_READ(DPLL(pipe));
1164         cur_state = !!(val & DPLL_VCO_ENABLE);
1165         I915_STATE_WARN(cur_state != state,
1166              "PLL state assertion failure (expected %s, current %s)\n",
1167              state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173         u32 val;
1174         bool cur_state;
1175
1176         mutex_lock(&dev_priv->sb_lock);
1177         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178         mutex_unlock(&dev_priv->sb_lock);
1179
1180         cur_state = val & DSI_PLL_VCO_EN;
1181         I915_STATE_WARN(cur_state != state,
1182              "DSI PLL state assertion failure (expected %s, current %s)\n",
1183              state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193         if (crtc->config->shared_dpll < 0)
1194                 return NULL;
1195
1196         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201                         struct intel_shared_dpll *pll,
1202                         bool state)
1203 {
1204         bool cur_state;
1205         struct intel_dpll_hw_state hw_state;
1206
1207         if (WARN (!pll,
1208                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1209                 return;
1210
1211         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212         I915_STATE_WARN(cur_state != state,
1213              "%s assertion failure (expected %s, current %s)\n",
1214              pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218                           enum pipe pipe, bool state)
1219 {
1220         bool cur_state;
1221         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222                                                                       pipe);
1223
1224         if (HAS_DDI(dev_priv->dev)) {
1225                 /* DDI does not have a specific FDI_TX register */
1226                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228         } else {
1229                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230                 cur_state = !!(val & FDI_TX_ENABLE);
1231         }
1232         I915_STATE_WARN(cur_state != state,
1233              "FDI TX state assertion failure (expected %s, current %s)\n",
1234              state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240                           enum pipe pipe, bool state)
1241 {
1242         u32 val;
1243         bool cur_state;
1244
1245         val = I915_READ(FDI_RX_CTL(pipe));
1246         cur_state = !!(val & FDI_RX_ENABLE);
1247         I915_STATE_WARN(cur_state != state,
1248              "FDI RX state assertion failure (expected %s, current %s)\n",
1249              state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255                                       enum pipe pipe)
1256 {
1257         u32 val;
1258
1259         /* ILK FDI PLL is always enabled */
1260         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261                 return;
1262
1263         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264         if (HAS_DDI(dev_priv->dev))
1265                 return;
1266
1267         val = I915_READ(FDI_TX_CTL(pipe));
1268         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272                        enum pipe pipe, bool state)
1273 {
1274         u32 val;
1275         bool cur_state;
1276
1277         val = I915_READ(FDI_RX_CTL(pipe));
1278         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279         I915_STATE_WARN(cur_state != state,
1280              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281              state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285                            enum pipe pipe)
1286 {
1287         struct drm_device *dev = dev_priv->dev;
1288         int pp_reg;
1289         u32 val;
1290         enum pipe panel_pipe = PIPE_A;
1291         bool locked = true;
1292
1293         if (WARN_ON(HAS_DDI(dev)))
1294                 return;
1295
1296         if (HAS_PCH_SPLIT(dev)) {
1297                 u32 port_sel;
1298
1299                 pp_reg = PCH_PP_CONTROL;
1300                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304                         panel_pipe = PIPE_B;
1305                 /* XXX: else fix for eDP */
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 /* presumably write lock depends on pipe, not port select */
1308                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309                 panel_pipe = pipe;
1310         } else {
1311                 pp_reg = PP_CONTROL;
1312                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313                         panel_pipe = PIPE_B;
1314         }
1315
1316         val = I915_READ(pp_reg);
1317         if (!(val & PANEL_POWER_ON) ||
1318             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319                 locked = false;
1320
1321         I915_STATE_WARN(panel_pipe == pipe && locked,
1322              "panel assertion failure, pipe %c regs locked\n",
1323              pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327                           enum pipe pipe, bool state)
1328 {
1329         struct drm_device *dev = dev_priv->dev;
1330         bool cur_state;
1331
1332         if (IS_845G(dev) || IS_I865G(dev))
1333                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334         else
1335                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337         I915_STATE_WARN(cur_state != state,
1338              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339              pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345                  enum pipe pipe, bool state)
1346 {
1347         bool cur_state;
1348         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349                                                                       pipe);
1350
1351         /* if we need the pipe quirk it must be always on */
1352         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354                 state = true;
1355
1356         if (!intel_display_power_is_enabled(dev_priv,
1357                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358                 cur_state = false;
1359         } else {
1360                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361                 cur_state = !!(val & PIPECONF_ENABLE);
1362         }
1363
1364         I915_STATE_WARN(cur_state != state,
1365              "pipe %c assertion failure (expected %s, current %s)\n",
1366              pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370                          enum plane plane, bool state)
1371 {
1372         u32 val;
1373         bool cur_state;
1374
1375         val = I915_READ(DSPCNTR(plane));
1376         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377         I915_STATE_WARN(cur_state != state,
1378              "plane %c assertion failure (expected %s, current %s)\n",
1379              plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386                                    enum pipe pipe)
1387 {
1388         struct drm_device *dev = dev_priv->dev;
1389         int i;
1390
1391         /* Primary planes are fixed to pipes on gen4+ */
1392         if (INTEL_INFO(dev)->gen >= 4) {
1393                 u32 val = I915_READ(DSPCNTR(pipe));
1394                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395                      "plane %c assertion failure, should be disabled but not\n",
1396                      plane_name(pipe));
1397                 return;
1398         }
1399
1400         /* Need to check both planes against the pipe */
1401         for_each_pipe(dev_priv, i) {
1402                 u32 val = I915_READ(DSPCNTR(i));
1403                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404                         DISPPLANE_SEL_PIPE_SHIFT;
1405                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407                      plane_name(i), pipe_name(pipe));
1408         }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412                                     enum pipe pipe)
1413 {
1414         struct drm_device *dev = dev_priv->dev;
1415         int sprite;
1416
1417         if (INTEL_INFO(dev)->gen >= 9) {
1418                 for_each_sprite(dev_priv, pipe, sprite) {
1419                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422                              sprite, pipe_name(pipe));
1423                 }
1424         } else if (IS_VALLEYVIEW(dev)) {
1425                 for_each_sprite(dev_priv, pipe, sprite) {
1426                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1427                         I915_STATE_WARN(val & SP_ENABLE,
1428                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429                              sprite_name(pipe, sprite), pipe_name(pipe));
1430                 }
1431         } else if (INTEL_INFO(dev)->gen >= 7) {
1432                 u32 val = I915_READ(SPRCTL(pipe));
1433                 I915_STATE_WARN(val & SPRITE_ENABLE,
1434                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435                      plane_name(pipe), pipe_name(pipe));
1436         } else if (INTEL_INFO(dev)->gen >= 5) {
1437                 u32 val = I915_READ(DVSCNTR(pipe));
1438                 I915_STATE_WARN(val & DVS_ENABLE,
1439                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440                      plane_name(pipe), pipe_name(pipe));
1441         }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447                 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452         u32 val;
1453         bool enabled;
1454
1455         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457         val = I915_READ(PCH_DREF_CONTROL);
1458         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459                             DREF_SUPERSPREAD_SOURCE_MASK));
1460         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464                                            enum pipe pipe)
1465 {
1466         u32 val;
1467         bool enabled;
1468
1469         val = I915_READ(PCH_TRANSCONF(pipe));
1470         enabled = !!(val & TRANS_ENABLE);
1471         I915_STATE_WARN(enabled,
1472              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473              pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477                             enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479         if ((val & DP_PORT_EN) == 0)
1480                 return false;
1481
1482         if (HAS_PCH_CPT(dev_priv->dev)) {
1483                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486                         return false;
1487         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489                         return false;
1490         } else {
1491                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492                         return false;
1493         }
1494         return true;
1495 }
1496
1497 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498                               enum pipe pipe, u32 val)
1499 {
1500         if ((val & SDVO_ENABLE) == 0)
1501                 return false;
1502
1503         if (HAS_PCH_CPT(dev_priv->dev)) {
1504                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1505                         return false;
1506         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508                         return false;
1509         } else {
1510                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1511                         return false;
1512         }
1513         return true;
1514 }
1515
1516 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517                               enum pipe pipe, u32 val)
1518 {
1519         if ((val & LVDS_PORT_EN) == 0)
1520                 return false;
1521
1522         if (HAS_PCH_CPT(dev_priv->dev)) {
1523                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524                         return false;
1525         } else {
1526                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527                         return false;
1528         }
1529         return true;
1530 }
1531
1532 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533                               enum pipe pipe, u32 val)
1534 {
1535         if ((val & ADPA_DAC_ENABLE) == 0)
1536                 return false;
1537         if (HAS_PCH_CPT(dev_priv->dev)) {
1538                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539                         return false;
1540         } else {
1541                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542                         return false;
1543         }
1544         return true;
1545 }
1546
1547 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1548                                    enum pipe pipe, int reg, u32 port_sel)
1549 {
1550         u32 val = I915_READ(reg);
1551         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553              reg, pipe_name(pipe));
1554
1555         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556              && (val & DP_PIPEB_SELECT),
1557              "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561                                      enum pipe pipe, int reg)
1562 {
1563         u32 val = I915_READ(reg);
1564         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566              reg, pipe_name(pipe));
1567
1568         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569              && (val & SDVO_PIPE_B_SELECT),
1570              "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574                                       enum pipe pipe)
1575 {
1576         u32 val;
1577
1578         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582         val = I915_READ(PCH_ADPA);
1583         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584              "PCH VGA enabled on transcoder %c, should be disabled\n",
1585              pipe_name(pipe));
1586
1587         val = I915_READ(PCH_LVDS);
1588         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590              pipe_name(pipe));
1591
1592         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598                            const struct intel_crtc_state *pipe_config)
1599 {
1600         struct drm_device *dev = crtc->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         int reg = DPLL(crtc->pipe);
1603         u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605         assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607         /* No really, not for ILK+ */
1608         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610         /* PLL is protected by panel, make sure we can write it */
1611         if (IS_MOBILE(dev_priv->dev))
1612                 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150);
1617
1618         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622         POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624         /* We do this three times for luck */
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150); /* wait for warmup */
1628         I915_WRITE(reg, dpll);
1629         POSTING_READ(reg);
1630         udelay(150); /* wait for warmup */
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637                            const struct intel_crtc_state *pipe_config)
1638 {
1639         struct drm_device *dev = crtc->base.dev;
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         int pipe = crtc->pipe;
1642         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643         u32 tmp;
1644
1645         assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649         mutex_lock(&dev_priv->sb_lock);
1650
1651         /* Enable back the 10bit clock to display controller */
1652         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653         tmp |= DPIO_DCLKP_EN;
1654         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656         mutex_unlock(&dev_priv->sb_lock);
1657
1658         /*
1659          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660          */
1661         udelay(1);
1662
1663         /* Enable PLL */
1664         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666         /* Check PLL is locked */
1667         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670         /* not sure when this should be written */
1671         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672         POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677         struct intel_crtc *crtc;
1678         int count = 0;
1679
1680         for_each_intel_crtc(dev, crtc)
1681                 count += crtc->base.state->active &&
1682                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684         return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689         struct drm_device *dev = crtc->base.dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         int reg = DPLL(crtc->pipe);
1692         u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694         assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696         /* No really, not for ILK+ */
1697         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699         /* PLL is protected by panel, make sure we can write it */
1700         if (IS_MOBILE(dev) && !IS_I830(dev))
1701                 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703         /* Enable DVO 2x clock on both PLLs if necessary */
1704         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705                 /*
1706                  * It appears to be important that we don't enable this
1707                  * for the current pipe before otherwise configuring the
1708                  * PLL. No idea how this should be handled if multiple
1709                  * DVO outputs are enabled simultaneosly.
1710                  */
1711                 dpll |= DPLL_DVO_2X_MODE;
1712                 I915_WRITE(DPLL(!crtc->pipe),
1713                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714         }
1715
1716         /*
1717          * Apparently we need to have VGA mode enabled prior to changing
1718          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1719          * dividers, even though the register value does change.
1720          */
1721         I915_WRITE(reg, 0);
1722
1723         I915_WRITE(reg, dpll);
1724
1725         /* Wait for the clocks to stabilize. */
1726         POSTING_READ(reg);
1727         udelay(150);
1728
1729         if (INTEL_INFO(dev)->gen >= 4) {
1730                 I915_WRITE(DPLL_MD(crtc->pipe),
1731                            crtc->config->dpll_hw_state.dpll_md);
1732         } else {
1733                 /* The pixel multiplier can only be updated once the
1734                  * DPLL is enabled and the clocks are stable.
1735                  *
1736                  * So write it again.
1737                  */
1738                 I915_WRITE(reg, dpll);
1739         }
1740
1741         /* We do this three times for luck */
1742         I915_WRITE(reg, dpll);
1743         POSTING_READ(reg);
1744         udelay(150); /* wait for warmup */
1745         I915_WRITE(reg, dpll);
1746         POSTING_READ(reg);
1747         udelay(150); /* wait for warmup */
1748         I915_WRITE(reg, dpll);
1749         POSTING_READ(reg);
1750         udelay(150); /* wait for warmup */
1751 }
1752
1753 /**
1754  * i9xx_disable_pll - disable a PLL
1755  * @dev_priv: i915 private structure
1756  * @pipe: pipe PLL to disable
1757  *
1758  * Disable the PLL for @pipe, making sure the pipe is off first.
1759  *
1760  * Note!  This is for pre-ILK only.
1761  */
1762 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 {
1764         struct drm_device *dev = crtc->base.dev;
1765         struct drm_i915_private *dev_priv = dev->dev_private;
1766         enum pipe pipe = crtc->pipe;
1767
1768         /* Disable DVO 2x clock on both PLLs if necessary */
1769         if (IS_I830(dev) &&
1770             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1771             !intel_num_dvo_pipes(dev)) {
1772                 I915_WRITE(DPLL(PIPE_B),
1773                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1774                 I915_WRITE(DPLL(PIPE_A),
1775                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1776         }
1777
1778         /* Don't disable pipe or pipe PLLs if needed */
1779         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1780             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1781                 return;
1782
1783         /* Make sure the pipe isn't still relying on us */
1784         assert_pipe_disabled(dev_priv, pipe);
1785
1786         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1787         POSTING_READ(DPLL(pipe));
1788 }
1789
1790 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1791 {
1792         u32 val;
1793
1794         /* Make sure the pipe isn't still relying on us */
1795         assert_pipe_disabled(dev_priv, pipe);
1796
1797         /*
1798          * Leave integrated clock source and reference clock enabled for pipe B.
1799          * The latter is needed for VGA hotplug / manual detection.
1800          */
1801         val = DPLL_VGA_MODE_DIS;
1802         if (pipe == PIPE_B)
1803                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1804         I915_WRITE(DPLL(pipe), val);
1805         POSTING_READ(DPLL(pipe));
1806
1807 }
1808
1809 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 {
1811         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1812         u32 val;
1813
1814         /* Make sure the pipe isn't still relying on us */
1815         assert_pipe_disabled(dev_priv, pipe);
1816
1817         /* Set PLL en = 0 */
1818         val = DPLL_SSC_REF_CLK_CHV |
1819                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820         if (pipe != PIPE_A)
1821                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822         I915_WRITE(DPLL(pipe), val);
1823         POSTING_READ(DPLL(pipe));
1824
1825         mutex_lock(&dev_priv->sb_lock);
1826
1827         /* Disable 10bit clock to display controller */
1828         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829         val &= ~DPIO_DCLKP_EN;
1830         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832         mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836                          struct intel_digital_port *dport,
1837                          unsigned int expected_mask)
1838 {
1839         u32 port_mask;
1840         int dpll_reg;
1841
1842         switch (dport->port) {
1843         case PORT_B:
1844                 port_mask = DPLL_PORTB_READY_MASK;
1845                 dpll_reg = DPLL(0);
1846                 break;
1847         case PORT_C:
1848                 port_mask = DPLL_PORTC_READY_MASK;
1849                 dpll_reg = DPLL(0);
1850                 expected_mask <<= 4;
1851                 break;
1852         case PORT_D:
1853                 port_mask = DPLL_PORTD_READY_MASK;
1854                 dpll_reg = DPIO_PHY_STATUS;
1855                 break;
1856         default:
1857                 BUG();
1858         }
1859
1860         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867         struct drm_device *dev = crtc->base.dev;
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871         if (WARN_ON(pll == NULL))
1872                 return;
1873
1874         WARN_ON(!pll->config.crtc_mask);
1875         if (pll->active == 0) {
1876                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877                 WARN_ON(pll->on);
1878                 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880                 pll->mode_set(dev_priv, pll);
1881         }
1882 }
1883
1884 /**
1885  * intel_enable_shared_dpll - enable PCH PLL
1886  * @dev_priv: i915 private structure
1887  * @pipe: pipe PLL to enable
1888  *
1889  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890  * drives the transcoder clock.
1891  */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894         struct drm_device *dev = crtc->base.dev;
1895         struct drm_i915_private *dev_priv = dev->dev_private;
1896         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898         if (WARN_ON(pll == NULL))
1899                 return;
1900
1901         if (WARN_ON(pll->config.crtc_mask == 0))
1902                 return;
1903
1904         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905                       pll->name, pll->active, pll->on,
1906                       crtc->base.base.id);
1907
1908         if (pll->active++) {
1909                 WARN_ON(!pll->on);
1910                 assert_shared_dpll_enabled(dev_priv, pll);
1911                 return;
1912         }
1913         WARN_ON(pll->on);
1914
1915         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918         pll->enable(dev_priv, pll);
1919         pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924         struct drm_device *dev = crtc->base.dev;
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928         /* PCH only available on ILK+ */
1929         if (INTEL_INFO(dev)->gen < 5)
1930                 return;
1931
1932         if (pll == NULL)
1933                 return;
1934
1935         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1936                 return;
1937
1938         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1939                       pll->name, pll->active, pll->on,
1940                       crtc->base.base.id);
1941
1942         if (WARN_ON(pll->active == 0)) {
1943                 assert_shared_dpll_disabled(dev_priv, pll);
1944                 return;
1945         }
1946
1947         assert_shared_dpll_enabled(dev_priv, pll);
1948         WARN_ON(!pll->on);
1949         if (--pll->active)
1950                 return;
1951
1952         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1953         pll->disable(dev_priv, pll);
1954         pll->on = false;
1955
1956         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1957 }
1958
1959 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1960                                            enum pipe pipe)
1961 {
1962         struct drm_device *dev = dev_priv->dev;
1963         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965         uint32_t reg, val, pipeconf_val;
1966
1967         /* PCH only available on ILK+ */
1968         BUG_ON(!HAS_PCH_SPLIT(dev));
1969
1970         /* Make sure PCH DPLL is enabled */
1971         assert_shared_dpll_enabled(dev_priv,
1972                                    intel_crtc_to_shared_dpll(intel_crtc));
1973
1974         /* FDI must be feeding us bits for PCH ports */
1975         assert_fdi_tx_enabled(dev_priv, pipe);
1976         assert_fdi_rx_enabled(dev_priv, pipe);
1977
1978         if (HAS_PCH_CPT(dev)) {
1979                 /* Workaround: Set the timing override bit before enabling the
1980                  * pch transcoder. */
1981                 reg = TRANS_CHICKEN2(pipe);
1982                 val = I915_READ(reg);
1983                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1984                 I915_WRITE(reg, val);
1985         }
1986
1987         reg = PCH_TRANSCONF(pipe);
1988         val = I915_READ(reg);
1989         pipeconf_val = I915_READ(PIPECONF(pipe));
1990
1991         if (HAS_PCH_IBX(dev_priv->dev)) {
1992                 /*
1993                  * Make the BPC in transcoder be consistent with
1994                  * that in pipeconf reg. For HDMI we must use 8bpc
1995                  * here for both 8bpc and 12bpc.
1996                  */
1997                 val &= ~PIPECONF_BPC_MASK;
1998                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1999                         val |= PIPECONF_8BPC;
2000                 else
2001                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2002         }
2003
2004         val &= ~TRANS_INTERLACE_MASK;
2005         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2006                 if (HAS_PCH_IBX(dev_priv->dev) &&
2007                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2008                         val |= TRANS_LEGACY_INTERLACED_ILK;
2009                 else
2010                         val |= TRANS_INTERLACED;
2011         else
2012                 val |= TRANS_PROGRESSIVE;
2013
2014         I915_WRITE(reg, val | TRANS_ENABLE);
2015         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2016                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2017 }
2018
2019 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2020                                       enum transcoder cpu_transcoder)
2021 {
2022         u32 val, pipeconf_val;
2023
2024         /* PCH only available on ILK+ */
2025         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2026
2027         /* FDI must be feeding us bits for PCH ports */
2028         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2029         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2030
2031         /* Workaround: set timing override bit. */
2032         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2033         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2034         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2035
2036         val = TRANS_ENABLE;
2037         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2038
2039         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2040             PIPECONF_INTERLACED_ILK)
2041                 val |= TRANS_INTERLACED;
2042         else
2043                 val |= TRANS_PROGRESSIVE;
2044
2045         I915_WRITE(LPT_TRANSCONF, val);
2046         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2047                 DRM_ERROR("Failed to enable PCH transcoder\n");
2048 }
2049
2050 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2051                                             enum pipe pipe)
2052 {
2053         struct drm_device *dev = dev_priv->dev;
2054         uint32_t reg, val;
2055
2056         /* FDI relies on the transcoder */
2057         assert_fdi_tx_disabled(dev_priv, pipe);
2058         assert_fdi_rx_disabled(dev_priv, pipe);
2059
2060         /* Ports must be off as well */
2061         assert_pch_ports_disabled(dev_priv, pipe);
2062
2063         reg = PCH_TRANSCONF(pipe);
2064         val = I915_READ(reg);
2065         val &= ~TRANS_ENABLE;
2066         I915_WRITE(reg, val);
2067         /* wait for PCH transcoder off, transcoder state */
2068         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2069                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2070
2071         if (!HAS_PCH_IBX(dev)) {
2072                 /* Workaround: Clear the timing override chicken bit again. */
2073                 reg = TRANS_CHICKEN2(pipe);
2074                 val = I915_READ(reg);
2075                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2076                 I915_WRITE(reg, val);
2077         }
2078 }
2079
2080 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2081 {
2082         u32 val;
2083
2084         val = I915_READ(LPT_TRANSCONF);
2085         val &= ~TRANS_ENABLE;
2086         I915_WRITE(LPT_TRANSCONF, val);
2087         /* wait for PCH transcoder off, transcoder state */
2088         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2089                 DRM_ERROR("Failed to disable PCH transcoder\n");
2090
2091         /* Workaround: clear timing override bit. */
2092         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2093         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2095 }
2096
2097 /**
2098  * intel_enable_pipe - enable a pipe, asserting requirements
2099  * @crtc: crtc responsible for the pipe
2100  *
2101  * Enable @crtc's pipe, making sure that various hardware specific requirements
2102  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2103  */
2104 static void intel_enable_pipe(struct intel_crtc *crtc)
2105 {
2106         struct drm_device *dev = crtc->base.dev;
2107         struct drm_i915_private *dev_priv = dev->dev_private;
2108         enum pipe pipe = crtc->pipe;
2109         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2110                                                                       pipe);
2111         enum pipe pch_transcoder;
2112         int reg;
2113         u32 val;
2114
2115         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2116
2117         assert_planes_disabled(dev_priv, pipe);
2118         assert_cursor_disabled(dev_priv, pipe);
2119         assert_sprites_disabled(dev_priv, pipe);
2120
2121         if (HAS_PCH_LPT(dev_priv->dev))
2122                 pch_transcoder = TRANSCODER_A;
2123         else
2124                 pch_transcoder = pipe;
2125
2126         /*
2127          * A pipe without a PLL won't actually be able to drive bits from
2128          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2129          * need the check.
2130          */
2131         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2132                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2133                         assert_dsi_pll_enabled(dev_priv);
2134                 else
2135                         assert_pll_enabled(dev_priv, pipe);
2136         else {
2137                 if (crtc->config->has_pch_encoder) {
2138                         /* if driving the PCH, we need FDI enabled */
2139                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2140                         assert_fdi_tx_pll_enabled(dev_priv,
2141                                                   (enum pipe) cpu_transcoder);
2142                 }
2143                 /* FIXME: assert CPU port conditions for SNB+ */
2144         }
2145
2146         reg = PIPECONF(cpu_transcoder);
2147         val = I915_READ(reg);
2148         if (val & PIPECONF_ENABLE) {
2149                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2150                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2151                 return;
2152         }
2153
2154         I915_WRITE(reg, val | PIPECONF_ENABLE);
2155         POSTING_READ(reg);
2156 }
2157
2158 /**
2159  * intel_disable_pipe - disable a pipe, asserting requirements
2160  * @crtc: crtc whose pipes is to be disabled
2161  *
2162  * Disable the pipe of @crtc, making sure that various hardware
2163  * specific requirements are met, if applicable, e.g. plane
2164  * disabled, panel fitter off, etc.
2165  *
2166  * Will wait until the pipe has shut down before returning.
2167  */
2168 static void intel_disable_pipe(struct intel_crtc *crtc)
2169 {
2170         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2171         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2172         enum pipe pipe = crtc->pipe;
2173         int reg;
2174         u32 val;
2175
2176         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2177
2178         /*
2179          * Make sure planes won't keep trying to pump pixels to us,
2180          * or we might hang the display.
2181          */
2182         assert_planes_disabled(dev_priv, pipe);
2183         assert_cursor_disabled(dev_priv, pipe);
2184         assert_sprites_disabled(dev_priv, pipe);
2185
2186         reg = PIPECONF(cpu_transcoder);
2187         val = I915_READ(reg);
2188         if ((val & PIPECONF_ENABLE) == 0)
2189                 return;
2190
2191         /*
2192          * Double wide has implications for planes
2193          * so best keep it disabled when not needed.
2194          */
2195         if (crtc->config->double_wide)
2196                 val &= ~PIPECONF_DOUBLE_WIDE;
2197
2198         /* Don't disable pipe or pipe PLLs if needed */
2199         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2200             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2201                 val &= ~PIPECONF_ENABLE;
2202
2203         I915_WRITE(reg, val);
2204         if ((val & PIPECONF_ENABLE) == 0)
2205                 intel_wait_for_pipe_off(crtc);
2206 }
2207
2208 static bool need_vtd_wa(struct drm_device *dev)
2209 {
2210 #ifdef CONFIG_INTEL_IOMMU
2211         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2212                 return true;
2213 #endif
2214         return false;
2215 }
2216
2217 unsigned int
2218 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2219                   uint64_t fb_format_modifier, unsigned int plane)
2220 {
2221         unsigned int tile_height;
2222         uint32_t pixel_bytes;
2223
2224         switch (fb_format_modifier) {
2225         case DRM_FORMAT_MOD_NONE:
2226                 tile_height = 1;
2227                 break;
2228         case I915_FORMAT_MOD_X_TILED:
2229                 tile_height = IS_GEN2(dev) ? 16 : 8;
2230                 break;
2231         case I915_FORMAT_MOD_Y_TILED:
2232                 tile_height = 32;
2233                 break;
2234         case I915_FORMAT_MOD_Yf_TILED:
2235                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2236                 switch (pixel_bytes) {
2237                 default:
2238                 case 1:
2239                         tile_height = 64;
2240                         break;
2241                 case 2:
2242                 case 4:
2243                         tile_height = 32;
2244                         break;
2245                 case 8:
2246                         tile_height = 16;
2247                         break;
2248                 case 16:
2249                         WARN_ONCE(1,
2250                                   "128-bit pixels are not supported for display!");
2251                         tile_height = 16;
2252                         break;
2253                 }
2254                 break;
2255         default:
2256                 MISSING_CASE(fb_format_modifier);
2257                 tile_height = 1;
2258                 break;
2259         }
2260
2261         return tile_height;
2262 }
2263
2264 unsigned int
2265 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2266                       uint32_t pixel_format, uint64_t fb_format_modifier)
2267 {
2268         return ALIGN(height, intel_tile_height(dev, pixel_format,
2269                                                fb_format_modifier, 0));
2270 }
2271
2272 static int
2273 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2274                         const struct drm_plane_state *plane_state)
2275 {
2276         struct intel_rotation_info *info = &view->rotation_info;
2277         unsigned int tile_height, tile_pitch;
2278
2279         *view = i915_ggtt_view_normal;
2280
2281         if (!plane_state)
2282                 return 0;
2283
2284         if (!intel_rotation_90_or_270(plane_state->rotation))
2285                 return 0;
2286
2287         *view = i915_ggtt_view_rotated;
2288
2289         info->height = fb->height;
2290         info->pixel_format = fb->pixel_format;
2291         info->pitch = fb->pitches[0];
2292         info->uv_offset = fb->offsets[1];
2293         info->fb_modifier = fb->modifier[0];
2294
2295         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2296                                         fb->modifier[0], 0);
2297         tile_pitch = PAGE_SIZE / tile_height;
2298         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2299         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2300         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2301
2302         if (info->pixel_format == DRM_FORMAT_NV12) {
2303                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2304                                                 fb->modifier[0], 1);
2305                 tile_pitch = PAGE_SIZE / tile_height;
2306                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2307                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2308                                                      tile_height);
2309                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2310                                 PAGE_SIZE;
2311         }
2312
2313         return 0;
2314 }
2315
2316 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2317 {
2318         if (INTEL_INFO(dev_priv)->gen >= 9)
2319                 return 256 * 1024;
2320         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2321                  IS_VALLEYVIEW(dev_priv))
2322                 return 128 * 1024;
2323         else if (INTEL_INFO(dev_priv)->gen >= 4)
2324                 return 4 * 1024;
2325         else
2326                 return 0;
2327 }
2328
2329 int
2330 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2331                            struct drm_framebuffer *fb,
2332                            const struct drm_plane_state *plane_state,
2333                            struct intel_engine_cs *pipelined,
2334                            struct drm_i915_gem_request **pipelined_request)
2335 {
2336         struct drm_device *dev = fb->dev;
2337         struct drm_i915_private *dev_priv = dev->dev_private;
2338         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2339         struct i915_ggtt_view view;
2340         u32 alignment;
2341         int ret;
2342
2343         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2344
2345         switch (fb->modifier[0]) {
2346         case DRM_FORMAT_MOD_NONE:
2347                 alignment = intel_linear_alignment(dev_priv);
2348                 break;
2349         case I915_FORMAT_MOD_X_TILED:
2350                 if (INTEL_INFO(dev)->gen >= 9)
2351                         alignment = 256 * 1024;
2352                 else {
2353                         /* pin() will align the object as required by fence */
2354                         alignment = 0;
2355                 }
2356                 break;
2357         case I915_FORMAT_MOD_Y_TILED:
2358         case I915_FORMAT_MOD_Yf_TILED:
2359                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360                           "Y tiling bo slipped through, driver bug!\n"))
2361                         return -EINVAL;
2362                 alignment = 1 * 1024 * 1024;
2363                 break;
2364         default:
2365                 MISSING_CASE(fb->modifier[0]);
2366                 return -EINVAL;
2367         }
2368
2369         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370         if (ret)
2371                 return ret;
2372
2373         /* Note that the w/a also requires 64 PTE of padding following the
2374          * bo. We currently fill all unused PTE with the shadow page and so
2375          * we should always have valid PTE following the scanout preventing
2376          * the VT-d warning.
2377          */
2378         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379                 alignment = 256 * 1024;
2380
2381         /*
2382          * Global gtt pte registers are special registers which actually forward
2383          * writes to a chunk of system memory. Which means that there is no risk
2384          * that the register values disappear as soon as we call
2385          * intel_runtime_pm_put(), so it is correct to wrap only the
2386          * pin/unpin/fence and not more.
2387          */
2388         intel_runtime_pm_get(dev_priv);
2389
2390         dev_priv->mm.interruptible = false;
2391         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2392                                                    pipelined_request, &view);
2393         if (ret)
2394                 goto err_interruptible;
2395
2396         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397          * fence, whereas 965+ only requires a fence if using
2398          * framebuffer compression.  For simplicity, we always install
2399          * a fence as the cost is not that onerous.
2400          */
2401         if (view.type == I915_GGTT_VIEW_NORMAL) {
2402                 ret = i915_gem_object_get_fence(obj);
2403                 if (ret == -EDEADLK) {
2404                         /*
2405                          * -EDEADLK means there are no free fences
2406                          * no pending flips.
2407                          *
2408                          * This is propagated to atomic, but it uses
2409                          * -EDEADLK to force a locking recovery, so
2410                          * change the returned error to -EBUSY.
2411                          */
2412                         ret = -EBUSY;
2413                         goto err_unpin;
2414                 } else if (ret)
2415                         goto err_unpin;
2416
2417                 i915_gem_object_pin_fence(obj);
2418         }
2419
2420         dev_priv->mm.interruptible = true;
2421         intel_runtime_pm_put(dev_priv);
2422         return 0;
2423
2424 err_unpin:
2425         i915_gem_object_unpin_from_display_plane(obj, &view);
2426 err_interruptible:
2427         dev_priv->mm.interruptible = true;
2428         intel_runtime_pm_put(dev_priv);
2429         return ret;
2430 }
2431
2432 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2433                                const struct drm_plane_state *plane_state)
2434 {
2435         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2436         struct i915_ggtt_view view;
2437         int ret;
2438
2439         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2440
2441         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2442         WARN_ONCE(ret, "Couldn't get view from plane state!");
2443
2444         if (view.type == I915_GGTT_VIEW_NORMAL)
2445                 i915_gem_object_unpin_fence(obj);
2446
2447         i915_gem_object_unpin_from_display_plane(obj, &view);
2448 }
2449
2450 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2451  * is assumed to be a power-of-two. */
2452 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2453                                              int *x, int *y,
2454                                              unsigned int tiling_mode,
2455                                              unsigned int cpp,
2456                                              unsigned int pitch)
2457 {
2458         if (tiling_mode != I915_TILING_NONE) {
2459                 unsigned int tile_rows, tiles;
2460
2461                 tile_rows = *y / 8;
2462                 *y %= 8;
2463
2464                 tiles = *x / (512/cpp);
2465                 *x %= 512/cpp;
2466
2467                 return tile_rows * pitch * 8 + tiles * 4096;
2468         } else {
2469                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2470                 unsigned int offset;
2471
2472                 offset = *y * pitch + *x * cpp;
2473                 *y = (offset & alignment) / pitch;
2474                 *x = ((offset & alignment) - *y * pitch) / cpp;
2475                 return offset & ~alignment;
2476         }
2477 }
2478
2479 static int i9xx_format_to_fourcc(int format)
2480 {
2481         switch (format) {
2482         case DISPPLANE_8BPP:
2483                 return DRM_FORMAT_C8;
2484         case DISPPLANE_BGRX555:
2485                 return DRM_FORMAT_XRGB1555;
2486         case DISPPLANE_BGRX565:
2487                 return DRM_FORMAT_RGB565;
2488         default:
2489         case DISPPLANE_BGRX888:
2490                 return DRM_FORMAT_XRGB8888;
2491         case DISPPLANE_RGBX888:
2492                 return DRM_FORMAT_XBGR8888;
2493         case DISPPLANE_BGRX101010:
2494                 return DRM_FORMAT_XRGB2101010;
2495         case DISPPLANE_RGBX101010:
2496                 return DRM_FORMAT_XBGR2101010;
2497         }
2498 }
2499
2500 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2501 {
2502         switch (format) {
2503         case PLANE_CTL_FORMAT_RGB_565:
2504                 return DRM_FORMAT_RGB565;
2505         default:
2506         case PLANE_CTL_FORMAT_XRGB_8888:
2507                 if (rgb_order) {
2508                         if (alpha)
2509                                 return DRM_FORMAT_ABGR8888;
2510                         else
2511                                 return DRM_FORMAT_XBGR8888;
2512                 } else {
2513                         if (alpha)
2514                                 return DRM_FORMAT_ARGB8888;
2515                         else
2516                                 return DRM_FORMAT_XRGB8888;
2517                 }
2518         case PLANE_CTL_FORMAT_XRGB_2101010:
2519                 if (rgb_order)
2520                         return DRM_FORMAT_XBGR2101010;
2521                 else
2522                         return DRM_FORMAT_XRGB2101010;
2523         }
2524 }
2525
2526 static bool
2527 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2528                               struct intel_initial_plane_config *plane_config)
2529 {
2530         struct drm_device *dev = crtc->base.dev;
2531         struct drm_i915_private *dev_priv = to_i915(dev);
2532         struct drm_i915_gem_object *obj = NULL;
2533         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2534         struct drm_framebuffer *fb = &plane_config->fb->base;
2535         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2536         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2537                                     PAGE_SIZE);
2538
2539         size_aligned -= base_aligned;
2540
2541         if (plane_config->size == 0)
2542                 return false;
2543
2544         /* If the FB is too big, just don't use it since fbdev is not very
2545          * important and we should probably use that space with FBC or other
2546          * features. */
2547         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2548                 return false;
2549
2550         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2551                                                              base_aligned,
2552                                                              base_aligned,
2553                                                              size_aligned);
2554         if (!obj)
2555                 return false;
2556
2557         obj->tiling_mode = plane_config->tiling;
2558         if (obj->tiling_mode == I915_TILING_X)
2559                 obj->stride = fb->pitches[0];
2560
2561         mode_cmd.pixel_format = fb->pixel_format;
2562         mode_cmd.width = fb->width;
2563         mode_cmd.height = fb->height;
2564         mode_cmd.pitches[0] = fb->pitches[0];
2565         mode_cmd.modifier[0] = fb->modifier[0];
2566         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2567
2568         mutex_lock(&dev->struct_mutex);
2569         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2570                                    &mode_cmd, obj)) {
2571                 DRM_DEBUG_KMS("intel fb init failed\n");
2572                 goto out_unref_obj;
2573         }
2574         mutex_unlock(&dev->struct_mutex);
2575
2576         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2577         return true;
2578
2579 out_unref_obj:
2580         drm_gem_object_unreference(&obj->base);
2581         mutex_unlock(&dev->struct_mutex);
2582         return false;
2583 }
2584
2585 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2586 static void
2587 update_state_fb(struct drm_plane *plane)
2588 {
2589         if (plane->fb == plane->state->fb)
2590                 return;
2591
2592         if (plane->state->fb)
2593                 drm_framebuffer_unreference(plane->state->fb);
2594         plane->state->fb = plane->fb;
2595         if (plane->state->fb)
2596                 drm_framebuffer_reference(plane->state->fb);
2597 }
2598
2599 static void
2600 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2601                              struct intel_initial_plane_config *plane_config)
2602 {
2603         struct drm_device *dev = intel_crtc->base.dev;
2604         struct drm_i915_private *dev_priv = dev->dev_private;
2605         struct drm_crtc *c;
2606         struct intel_crtc *i;
2607         struct drm_i915_gem_object *obj;
2608         struct drm_plane *primary = intel_crtc->base.primary;
2609         struct drm_plane_state *plane_state = primary->state;
2610         struct drm_framebuffer *fb;
2611
2612         if (!plane_config->fb)
2613                 return;
2614
2615         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2616                 fb = &plane_config->fb->base;
2617                 goto valid_fb;
2618         }
2619
2620         kfree(plane_config->fb);
2621
2622         /*
2623          * Failed to alloc the obj, check to see if we should share
2624          * an fb with another CRTC instead
2625          */
2626         for_each_crtc(dev, c) {
2627                 i = to_intel_crtc(c);
2628
2629                 if (c == &intel_crtc->base)
2630                         continue;
2631
2632                 if (!i->active)
2633                         continue;
2634
2635                 fb = c->primary->fb;
2636                 if (!fb)
2637                         continue;
2638
2639                 obj = intel_fb_obj(fb);
2640                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2641                         drm_framebuffer_reference(fb);
2642                         goto valid_fb;
2643                 }
2644         }
2645
2646         return;
2647
2648 valid_fb:
2649         plane_state->src_x = 0;
2650         plane_state->src_y = 0;
2651         plane_state->src_w = fb->width << 16;
2652         plane_state->src_h = fb->height << 16;
2653
2654         plane_state->crtc_x = 0;
2655         plane_state->crtc_y = 0;
2656         plane_state->crtc_w = fb->width;
2657         plane_state->crtc_h = fb->height;
2658
2659         obj = intel_fb_obj(fb);
2660         if (obj->tiling_mode != I915_TILING_NONE)
2661                 dev_priv->preserve_bios_swizzle = true;
2662
2663         drm_framebuffer_reference(fb);
2664         primary->fb = primary->state->fb = fb;
2665         primary->crtc = primary->state->crtc = &intel_crtc->base;
2666         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2667         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2668 }
2669
2670 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2671                                       struct drm_framebuffer *fb,
2672                                       int x, int y)
2673 {
2674         struct drm_device *dev = crtc->dev;
2675         struct drm_i915_private *dev_priv = dev->dev_private;
2676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2677         struct drm_plane *primary = crtc->primary;
2678         bool visible = to_intel_plane_state(primary->state)->visible;
2679         struct drm_i915_gem_object *obj;
2680         int plane = intel_crtc->plane;
2681         unsigned long linear_offset;
2682         u32 dspcntr;
2683         u32 reg = DSPCNTR(plane);
2684         int pixel_size;
2685
2686         if (!visible || !fb) {
2687                 I915_WRITE(reg, 0);
2688                 if (INTEL_INFO(dev)->gen >= 4)
2689                         I915_WRITE(DSPSURF(plane), 0);
2690                 else
2691                         I915_WRITE(DSPADDR(plane), 0);
2692                 POSTING_READ(reg);
2693                 return;
2694         }
2695
2696         obj = intel_fb_obj(fb);
2697         if (WARN_ON(obj == NULL))
2698                 return;
2699
2700         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2701
2702         dspcntr = DISPPLANE_GAMMA_ENABLE;
2703
2704         dspcntr |= DISPLAY_PLANE_ENABLE;
2705
2706         if (INTEL_INFO(dev)->gen < 4) {
2707                 if (intel_crtc->pipe == PIPE_B)
2708                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2709
2710                 /* pipesrc and dspsize control the size that is scaled from,
2711                  * which should always be the user's requested size.
2712                  */
2713                 I915_WRITE(DSPSIZE(plane),
2714                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2715                            (intel_crtc->config->pipe_src_w - 1));
2716                 I915_WRITE(DSPPOS(plane), 0);
2717         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2718                 I915_WRITE(PRIMSIZE(plane),
2719                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2720                            (intel_crtc->config->pipe_src_w - 1));
2721                 I915_WRITE(PRIMPOS(plane), 0);
2722                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2723         }
2724
2725         switch (fb->pixel_format) {
2726         case DRM_FORMAT_C8:
2727                 dspcntr |= DISPPLANE_8BPP;
2728                 break;
2729         case DRM_FORMAT_XRGB1555:
2730                 dspcntr |= DISPPLANE_BGRX555;
2731                 break;
2732         case DRM_FORMAT_RGB565:
2733                 dspcntr |= DISPPLANE_BGRX565;
2734                 break;
2735         case DRM_FORMAT_XRGB8888:
2736                 dspcntr |= DISPPLANE_BGRX888;
2737                 break;
2738         case DRM_FORMAT_XBGR8888:
2739                 dspcntr |= DISPPLANE_RGBX888;
2740                 break;
2741         case DRM_FORMAT_XRGB2101010:
2742                 dspcntr |= DISPPLANE_BGRX101010;
2743                 break;
2744         case DRM_FORMAT_XBGR2101010:
2745                 dspcntr |= DISPPLANE_RGBX101010;
2746                 break;
2747         default:
2748                 BUG();
2749         }
2750
2751         if (INTEL_INFO(dev)->gen >= 4 &&
2752             obj->tiling_mode != I915_TILING_NONE)
2753                 dspcntr |= DISPPLANE_TILED;
2754
2755         if (IS_G4X(dev))
2756                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2757
2758         linear_offset = y * fb->pitches[0] + x * pixel_size;
2759
2760         if (INTEL_INFO(dev)->gen >= 4) {
2761                 intel_crtc->dspaddr_offset =
2762                         intel_gen4_compute_page_offset(dev_priv,
2763                                                        &x, &y, obj->tiling_mode,
2764                                                        pixel_size,
2765                                                        fb->pitches[0]);
2766                 linear_offset -= intel_crtc->dspaddr_offset;
2767         } else {
2768                 intel_crtc->dspaddr_offset = linear_offset;
2769         }
2770
2771         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2772                 dspcntr |= DISPPLANE_ROTATE_180;
2773
2774                 x += (intel_crtc->config->pipe_src_w - 1);
2775                 y += (intel_crtc->config->pipe_src_h - 1);
2776
2777                 /* Finding the last pixel of the last line of the display
2778                 data and adding to linear_offset*/
2779                 linear_offset +=
2780                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2781                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2782         }
2783
2784         intel_crtc->adjusted_x = x;
2785         intel_crtc->adjusted_y = y;
2786
2787         I915_WRITE(reg, dspcntr);
2788
2789         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2790         if (INTEL_INFO(dev)->gen >= 4) {
2791                 I915_WRITE(DSPSURF(plane),
2792                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2793                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2794                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2795         } else
2796                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2797         POSTING_READ(reg);
2798 }
2799
2800 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2801                                           struct drm_framebuffer *fb,
2802                                           int x, int y)
2803 {
2804         struct drm_device *dev = crtc->dev;
2805         struct drm_i915_private *dev_priv = dev->dev_private;
2806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2807         struct drm_plane *primary = crtc->primary;
2808         bool visible = to_intel_plane_state(primary->state)->visible;
2809         struct drm_i915_gem_object *obj;
2810         int plane = intel_crtc->plane;
2811         unsigned long linear_offset;
2812         u32 dspcntr;
2813         u32 reg = DSPCNTR(plane);
2814         int pixel_size;
2815
2816         if (!visible || !fb) {
2817                 I915_WRITE(reg, 0);
2818                 I915_WRITE(DSPSURF(plane), 0);
2819                 POSTING_READ(reg);
2820                 return;
2821         }
2822
2823         obj = intel_fb_obj(fb);
2824         if (WARN_ON(obj == NULL))
2825                 return;
2826
2827         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2828
2829         dspcntr = DISPPLANE_GAMMA_ENABLE;
2830
2831         dspcntr |= DISPLAY_PLANE_ENABLE;
2832
2833         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2834                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2835
2836         switch (fb->pixel_format) {
2837         case DRM_FORMAT_C8:
2838                 dspcntr |= DISPPLANE_8BPP;
2839                 break;
2840         case DRM_FORMAT_RGB565:
2841                 dspcntr |= DISPPLANE_BGRX565;
2842                 break;
2843         case DRM_FORMAT_XRGB8888:
2844                 dspcntr |= DISPPLANE_BGRX888;
2845                 break;
2846         case DRM_FORMAT_XBGR8888:
2847                 dspcntr |= DISPPLANE_RGBX888;
2848                 break;
2849         case DRM_FORMAT_XRGB2101010:
2850                 dspcntr |= DISPPLANE_BGRX101010;
2851                 break;
2852         case DRM_FORMAT_XBGR2101010:
2853                 dspcntr |= DISPPLANE_RGBX101010;
2854                 break;
2855         default:
2856                 BUG();
2857         }
2858
2859         if (obj->tiling_mode != I915_TILING_NONE)
2860                 dspcntr |= DISPPLANE_TILED;
2861
2862         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2863                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2864
2865         linear_offset = y * fb->pitches[0] + x * pixel_size;
2866         intel_crtc->dspaddr_offset =
2867                 intel_gen4_compute_page_offset(dev_priv,
2868                                                &x, &y, obj->tiling_mode,
2869                                                pixel_size,
2870                                                fb->pitches[0]);
2871         linear_offset -= intel_crtc->dspaddr_offset;
2872         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2873                 dspcntr |= DISPPLANE_ROTATE_180;
2874
2875                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2876                         x += (intel_crtc->config->pipe_src_w - 1);
2877                         y += (intel_crtc->config->pipe_src_h - 1);
2878
2879                         /* Finding the last pixel of the last line of the display
2880                         data and adding to linear_offset*/
2881                         linear_offset +=
2882                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2883                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2884                 }
2885         }
2886
2887         intel_crtc->adjusted_x = x;
2888         intel_crtc->adjusted_y = y;
2889
2890         I915_WRITE(reg, dspcntr);
2891
2892         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2893         I915_WRITE(DSPSURF(plane),
2894                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2895         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2896                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2897         } else {
2898                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2899                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2900         }
2901         POSTING_READ(reg);
2902 }
2903
2904 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2905                               uint32_t pixel_format)
2906 {
2907         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2908
2909         /*
2910          * The stride is either expressed as a multiple of 64 bytes
2911          * chunks for linear buffers or in number of tiles for tiled
2912          * buffers.
2913          */
2914         switch (fb_modifier) {
2915         case DRM_FORMAT_MOD_NONE:
2916                 return 64;
2917         case I915_FORMAT_MOD_X_TILED:
2918                 if (INTEL_INFO(dev)->gen == 2)
2919                         return 128;
2920                 return 512;
2921         case I915_FORMAT_MOD_Y_TILED:
2922                 /* No need to check for old gens and Y tiling since this is
2923                  * about the display engine and those will be blocked before
2924                  * we get here.
2925                  */
2926                 return 128;
2927         case I915_FORMAT_MOD_Yf_TILED:
2928                 if (bits_per_pixel == 8)
2929                         return 64;
2930                 else
2931                         return 128;
2932         default:
2933                 MISSING_CASE(fb_modifier);
2934                 return 64;
2935         }
2936 }
2937
2938 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2939                                      struct drm_i915_gem_object *obj,
2940                                      unsigned int plane)
2941 {
2942         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2943         struct i915_vma *vma;
2944         unsigned char *offset;
2945
2946         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2947                 view = &i915_ggtt_view_rotated;
2948
2949         vma = i915_gem_obj_to_ggtt_view(obj, view);
2950         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2951                 view->type))
2952                 return -1;
2953
2954         offset = (unsigned char *)vma->node.start;
2955
2956         if (plane == 1) {
2957                 offset += vma->ggtt_view.rotation_info.uv_start_page *
2958                           PAGE_SIZE;
2959         }
2960
2961         return (unsigned long)offset;
2962 }
2963
2964 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2965 {
2966         struct drm_device *dev = intel_crtc->base.dev;
2967         struct drm_i915_private *dev_priv = dev->dev_private;
2968
2969         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2970         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2971         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2972 }
2973
2974 /*
2975  * This function detaches (aka. unbinds) unused scalers in hardware
2976  */
2977 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2978 {
2979         struct intel_crtc_scaler_state *scaler_state;
2980         int i;
2981
2982         scaler_state = &intel_crtc->config->scaler_state;
2983
2984         /* loop through and disable scalers that aren't in use */
2985         for (i = 0; i < intel_crtc->num_scalers; i++) {
2986                 if (!scaler_state->scalers[i].in_use)
2987                         skl_detach_scaler(intel_crtc, i);
2988         }
2989 }
2990
2991 u32 skl_plane_ctl_format(uint32_t pixel_format)
2992 {
2993         switch (pixel_format) {
2994         case DRM_FORMAT_C8:
2995                 return PLANE_CTL_FORMAT_INDEXED;
2996         case DRM_FORMAT_RGB565:
2997                 return PLANE_CTL_FORMAT_RGB_565;
2998         case DRM_FORMAT_XBGR8888:
2999                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3000         case DRM_FORMAT_XRGB8888:
3001                 return PLANE_CTL_FORMAT_XRGB_8888;
3002         /*
3003          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3004          * to be already pre-multiplied. We need to add a knob (or a different
3005          * DRM_FORMAT) for user-space to configure that.
3006          */
3007         case DRM_FORMAT_ABGR8888:
3008                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3009                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3010         case DRM_FORMAT_ARGB8888:
3011                 return PLANE_CTL_FORMAT_XRGB_8888 |
3012                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3013         case DRM_FORMAT_XRGB2101010:
3014                 return PLANE_CTL_FORMAT_XRGB_2101010;
3015         case DRM_FORMAT_XBGR2101010:
3016                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3017         case DRM_FORMAT_YUYV:
3018                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3019         case DRM_FORMAT_YVYU:
3020                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3021         case DRM_FORMAT_UYVY:
3022                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3023         case DRM_FORMAT_VYUY:
3024                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3025         default:
3026                 MISSING_CASE(pixel_format);
3027         }
3028
3029         return 0;
3030 }
3031
3032 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3033 {
3034         switch (fb_modifier) {
3035         case DRM_FORMAT_MOD_NONE:
3036                 break;
3037         case I915_FORMAT_MOD_X_TILED:
3038                 return PLANE_CTL_TILED_X;
3039         case I915_FORMAT_MOD_Y_TILED:
3040                 return PLANE_CTL_TILED_Y;
3041         case I915_FORMAT_MOD_Yf_TILED:
3042                 return PLANE_CTL_TILED_YF;
3043         default:
3044                 MISSING_CASE(fb_modifier);
3045         }
3046
3047         return 0;
3048 }
3049
3050 u32 skl_plane_ctl_rotation(unsigned int rotation)
3051 {
3052         switch (rotation) {
3053         case BIT(DRM_ROTATE_0):
3054                 break;
3055         /*
3056          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3057          * while i915 HW rotation is clockwise, thats why this swapping.
3058          */
3059         case BIT(DRM_ROTATE_90):
3060                 return PLANE_CTL_ROTATE_270;
3061         case BIT(DRM_ROTATE_180):
3062                 return PLANE_CTL_ROTATE_180;
3063         case BIT(DRM_ROTATE_270):
3064                 return PLANE_CTL_ROTATE_90;
3065         default:
3066                 MISSING_CASE(rotation);
3067         }
3068
3069         return 0;
3070 }
3071
3072 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3073                                          struct drm_framebuffer *fb,
3074                                          int x, int y)
3075 {
3076         struct drm_device *dev = crtc->dev;
3077         struct drm_i915_private *dev_priv = dev->dev_private;
3078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3079         struct drm_plane *plane = crtc->primary;
3080         bool visible = to_intel_plane_state(plane->state)->visible;
3081         struct drm_i915_gem_object *obj;
3082         int pipe = intel_crtc->pipe;
3083         u32 plane_ctl, stride_div, stride;
3084         u32 tile_height, plane_offset, plane_size;
3085         unsigned int rotation;
3086         int x_offset, y_offset;
3087         unsigned long surf_addr;
3088         struct intel_crtc_state *crtc_state = intel_crtc->config;
3089         struct intel_plane_state *plane_state;
3090         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3091         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3092         int scaler_id = -1;
3093
3094         plane_state = to_intel_plane_state(plane->state);
3095
3096         if (!visible || !fb) {
3097                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3098                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3099                 POSTING_READ(PLANE_CTL(pipe, 0));
3100                 return;
3101         }
3102
3103         plane_ctl = PLANE_CTL_ENABLE |
3104                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3105                     PLANE_CTL_PIPE_CSC_ENABLE;
3106
3107         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3108         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3109         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3110
3111         rotation = plane->state->rotation;
3112         plane_ctl |= skl_plane_ctl_rotation(rotation);
3113
3114         obj = intel_fb_obj(fb);
3115         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3116                                                fb->pixel_format);
3117         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3118
3119         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3120
3121         scaler_id = plane_state->scaler_id;
3122         src_x = plane_state->src.x1 >> 16;
3123         src_y = plane_state->src.y1 >> 16;
3124         src_w = drm_rect_width(&plane_state->src) >> 16;
3125         src_h = drm_rect_height(&plane_state->src) >> 16;
3126         dst_x = plane_state->dst.x1;
3127         dst_y = plane_state->dst.y1;
3128         dst_w = drm_rect_width(&plane_state->dst);
3129         dst_h = drm_rect_height(&plane_state->dst);
3130
3131         WARN_ON(x != src_x || y != src_y);
3132
3133         if (intel_rotation_90_or_270(rotation)) {
3134                 /* stride = Surface height in tiles */
3135                 tile_height = intel_tile_height(dev, fb->pixel_format,
3136                                                 fb->modifier[0], 0);
3137                 stride = DIV_ROUND_UP(fb->height, tile_height);
3138                 x_offset = stride * tile_height - y - src_h;
3139                 y_offset = x;
3140                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3141         } else {
3142                 stride = fb->pitches[0] / stride_div;
3143                 x_offset = x;
3144                 y_offset = y;
3145                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3146         }
3147         plane_offset = y_offset << 16 | x_offset;
3148
3149         intel_crtc->adjusted_x = x_offset;
3150         intel_crtc->adjusted_y = y_offset;
3151
3152         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3153         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3154         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3155         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3156
3157         if (scaler_id >= 0) {
3158                 uint32_t ps_ctrl = 0;
3159
3160                 WARN_ON(!dst_w || !dst_h);
3161                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3162                         crtc_state->scaler_state.scalers[scaler_id].mode;
3163                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3164                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3165                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3166                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3167                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3168         } else {
3169                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3170         }
3171
3172         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3173
3174         POSTING_READ(PLANE_SURF(pipe, 0));
3175 }
3176
3177 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3178 static int
3179 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3180                            int x, int y, enum mode_set_atomic state)
3181 {
3182         struct drm_device *dev = crtc->dev;
3183         struct drm_i915_private *dev_priv = dev->dev_private;
3184
3185         if (dev_priv->fbc.disable_fbc)
3186                 dev_priv->fbc.disable_fbc(dev_priv);
3187
3188         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3189
3190         return 0;
3191 }
3192
3193 static void intel_complete_page_flips(struct drm_device *dev)
3194 {
3195         struct drm_crtc *crtc;
3196
3197         for_each_crtc(dev, crtc) {
3198                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3199                 enum plane plane = intel_crtc->plane;
3200
3201                 intel_prepare_page_flip(dev, plane);
3202                 intel_finish_page_flip_plane(dev, plane);
3203         }
3204 }
3205
3206 static void intel_update_primary_planes(struct drm_device *dev)
3207 {
3208         struct drm_crtc *crtc;
3209
3210         for_each_crtc(dev, crtc) {
3211                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3212                 struct intel_plane_state *plane_state;
3213
3214                 drm_modeset_lock_crtc(crtc, &plane->base);
3215
3216                 plane_state = to_intel_plane_state(plane->base.state);
3217
3218                 if (plane_state->base.fb)
3219                         plane->commit_plane(&plane->base, plane_state);
3220
3221                 drm_modeset_unlock_crtc(crtc);
3222         }
3223 }
3224
3225 void intel_prepare_reset(struct drm_device *dev)
3226 {
3227         /* no reset support for gen2 */
3228         if (IS_GEN2(dev))
3229                 return;
3230
3231         /* reset doesn't touch the display */
3232         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3233                 return;
3234
3235         drm_modeset_lock_all(dev);
3236         /*
3237          * Disabling the crtcs gracefully seems nicer. Also the
3238          * g33 docs say we should at least disable all the planes.
3239          */
3240         intel_display_suspend(dev);
3241 }
3242
3243 void intel_finish_reset(struct drm_device *dev)
3244 {
3245         struct drm_i915_private *dev_priv = to_i915(dev);
3246
3247         /*
3248          * Flips in the rings will be nuked by the reset,
3249          * so complete all pending flips so that user space
3250          * will get its events and not get stuck.
3251          */
3252         intel_complete_page_flips(dev);
3253
3254         /* no reset support for gen2 */
3255         if (IS_GEN2(dev))
3256                 return;
3257
3258         /* reset doesn't touch the display */
3259         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3260                 /*
3261                  * Flips in the rings have been nuked by the reset,
3262                  * so update the base address of all primary
3263                  * planes to the the last fb to make sure we're
3264                  * showing the correct fb after a reset.
3265                  *
3266                  * FIXME: Atomic will make this obsolete since we won't schedule
3267                  * CS-based flips (which might get lost in gpu resets) any more.
3268                  */
3269                 intel_update_primary_planes(dev);
3270                 return;
3271         }
3272
3273         /*
3274          * The display has been reset as well,
3275          * so need a full re-initialization.
3276          */
3277         intel_runtime_pm_disable_interrupts(dev_priv);
3278         intel_runtime_pm_enable_interrupts(dev_priv);
3279
3280         intel_modeset_init_hw(dev);
3281
3282         spin_lock_irq(&dev_priv->irq_lock);
3283         if (dev_priv->display.hpd_irq_setup)
3284                 dev_priv->display.hpd_irq_setup(dev);
3285         spin_unlock_irq(&dev_priv->irq_lock);
3286
3287         intel_display_resume(dev);
3288
3289         intel_hpd_init(dev_priv);
3290
3291         drm_modeset_unlock_all(dev);
3292 }
3293
3294 static void
3295 intel_finish_fb(struct drm_framebuffer *old_fb)
3296 {
3297         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3298         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3299         bool was_interruptible = dev_priv->mm.interruptible;
3300         int ret;
3301
3302         /* Big Hammer, we also need to ensure that any pending
3303          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3304          * current scanout is retired before unpinning the old
3305          * framebuffer. Note that we rely on userspace rendering
3306          * into the buffer attached to the pipe they are waiting
3307          * on. If not, userspace generates a GPU hang with IPEHR
3308          * point to the MI_WAIT_FOR_EVENT.
3309          *
3310          * This should only fail upon a hung GPU, in which case we
3311          * can safely continue.
3312          */
3313         dev_priv->mm.interruptible = false;
3314         ret = i915_gem_object_wait_rendering(obj, true);
3315         dev_priv->mm.interruptible = was_interruptible;
3316
3317         WARN_ON(ret);
3318 }
3319
3320 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3321 {
3322         struct drm_device *dev = crtc->dev;
3323         struct drm_i915_private *dev_priv = dev->dev_private;
3324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3325         bool pending;
3326
3327         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3328             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3329                 return false;
3330
3331         spin_lock_irq(&dev->event_lock);
3332         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3333         spin_unlock_irq(&dev->event_lock);
3334
3335         return pending;
3336 }
3337
3338 static void intel_update_pipe_config(struct intel_crtc *crtc,
3339                                      struct intel_crtc_state *old_crtc_state)
3340 {
3341         struct drm_device *dev = crtc->base.dev;
3342         struct drm_i915_private *dev_priv = dev->dev_private;
3343         struct intel_crtc_state *pipe_config =
3344                 to_intel_crtc_state(crtc->base.state);
3345
3346         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3347         crtc->base.mode = crtc->base.state->mode;
3348
3349         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3350                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3351                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3352
3353         if (HAS_DDI(dev))
3354                 intel_set_pipe_csc(&crtc->base);
3355
3356         /*
3357          * Update pipe size and adjust fitter if needed: the reason for this is
3358          * that in compute_mode_changes we check the native mode (not the pfit
3359          * mode) to see if we can flip rather than do a full mode set. In the
3360          * fastboot case, we'll flip, but if we don't update the pipesrc and
3361          * pfit state, we'll end up with a big fb scanned out into the wrong
3362          * sized surface.
3363          */
3364
3365         I915_WRITE(PIPESRC(crtc->pipe),
3366                    ((pipe_config->pipe_src_w - 1) << 16) |
3367                    (pipe_config->pipe_src_h - 1));
3368
3369         /* on skylake this is done by detaching scalers */
3370         if (INTEL_INFO(dev)->gen >= 9) {
3371                 skl_detach_scalers(crtc);
3372
3373                 if (pipe_config->pch_pfit.enabled)
3374                         skylake_pfit_enable(crtc);
3375         } else if (HAS_PCH_SPLIT(dev)) {
3376                 if (pipe_config->pch_pfit.enabled)
3377                         ironlake_pfit_enable(crtc);
3378                 else if (old_crtc_state->pch_pfit.enabled)
3379                         ironlake_pfit_disable(crtc, true);
3380         }
3381 }
3382
3383 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3384 {
3385         struct drm_device *dev = crtc->dev;
3386         struct drm_i915_private *dev_priv = dev->dev_private;
3387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3388         int pipe = intel_crtc->pipe;
3389         u32 reg, temp;
3390
3391         /* enable normal train */
3392         reg = FDI_TX_CTL(pipe);
3393         temp = I915_READ(reg);
3394         if (IS_IVYBRIDGE(dev)) {
3395                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3396                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3397         } else {
3398                 temp &= ~FDI_LINK_TRAIN_NONE;
3399                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3400         }
3401         I915_WRITE(reg, temp);
3402
3403         reg = FDI_RX_CTL(pipe);
3404         temp = I915_READ(reg);
3405         if (HAS_PCH_CPT(dev)) {
3406                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3407                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3408         } else {
3409                 temp &= ~FDI_LINK_TRAIN_NONE;
3410                 temp |= FDI_LINK_TRAIN_NONE;
3411         }
3412         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3413
3414         /* wait one idle pattern time */
3415         POSTING_READ(reg);
3416         udelay(1000);
3417
3418         /* IVB wants error correction enabled */
3419         if (IS_IVYBRIDGE(dev))
3420                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3421                            FDI_FE_ERRC_ENABLE);
3422 }
3423
3424 /* The FDI link training functions for ILK/Ibexpeak. */
3425 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3426 {
3427         struct drm_device *dev = crtc->dev;
3428         struct drm_i915_private *dev_priv = dev->dev_private;
3429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3430         int pipe = intel_crtc->pipe;
3431         u32 reg, temp, tries;
3432
3433         /* FDI needs bits from pipe first */
3434         assert_pipe_enabled(dev_priv, pipe);
3435
3436         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3437            for train result */
3438         reg = FDI_RX_IMR(pipe);
3439         temp = I915_READ(reg);
3440         temp &= ~FDI_RX_SYMBOL_LOCK;
3441         temp &= ~FDI_RX_BIT_LOCK;
3442         I915_WRITE(reg, temp);
3443         I915_READ(reg);
3444         udelay(150);
3445
3446         /* enable CPU FDI TX and PCH FDI RX */
3447         reg = FDI_TX_CTL(pipe);
3448         temp = I915_READ(reg);
3449         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3450         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3451         temp &= ~FDI_LINK_TRAIN_NONE;
3452         temp |= FDI_LINK_TRAIN_PATTERN_1;
3453         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3454
3455         reg = FDI_RX_CTL(pipe);
3456         temp = I915_READ(reg);
3457         temp &= ~FDI_LINK_TRAIN_NONE;
3458         temp |= FDI_LINK_TRAIN_PATTERN_1;
3459         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3460
3461         POSTING_READ(reg);
3462         udelay(150);
3463
3464         /* Ironlake workaround, enable clock pointer after FDI enable*/
3465         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3466         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3467                    FDI_RX_PHASE_SYNC_POINTER_EN);
3468
3469         reg = FDI_RX_IIR(pipe);
3470         for (tries = 0; tries < 5; tries++) {
3471                 temp = I915_READ(reg);
3472                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3473
3474                 if ((temp & FDI_RX_BIT_LOCK)) {
3475                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3476                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3477                         break;
3478                 }
3479         }
3480         if (tries == 5)
3481                 DRM_ERROR("FDI train 1 fail!\n");
3482
3483         /* Train 2 */
3484         reg = FDI_TX_CTL(pipe);
3485         temp = I915_READ(reg);
3486         temp &= ~FDI_LINK_TRAIN_NONE;
3487         temp |= FDI_LINK_TRAIN_PATTERN_2;
3488         I915_WRITE(reg, temp);
3489
3490         reg = FDI_RX_CTL(pipe);
3491         temp = I915_READ(reg);
3492         temp &= ~FDI_LINK_TRAIN_NONE;
3493         temp |= FDI_LINK_TRAIN_PATTERN_2;
3494         I915_WRITE(reg, temp);
3495
3496         POSTING_READ(reg);
3497         udelay(150);
3498
3499         reg = FDI_RX_IIR(pipe);
3500         for (tries = 0; tries < 5; tries++) {
3501                 temp = I915_READ(reg);
3502                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3503
3504                 if (temp & FDI_RX_SYMBOL_LOCK) {
3505                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3506                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3507                         break;
3508                 }
3509         }
3510         if (tries == 5)
3511                 DRM_ERROR("FDI train 2 fail!\n");
3512
3513         DRM_DEBUG_KMS("FDI train done\n");
3514
3515 }
3516
3517 static const int snb_b_fdi_train_param[] = {
3518         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3519         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3520         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3521         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3522 };
3523
3524 /* The FDI link training functions for SNB/Cougarpoint. */
3525 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3526 {
3527         struct drm_device *dev = crtc->dev;
3528         struct drm_i915_private *dev_priv = dev->dev_private;
3529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3530         int pipe = intel_crtc->pipe;
3531         u32 reg, temp, i, retry;
3532
3533         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3534            for train result */
3535         reg = FDI_RX_IMR(pipe);
3536         temp = I915_READ(reg);
3537         temp &= ~FDI_RX_SYMBOL_LOCK;
3538         temp &= ~FDI_RX_BIT_LOCK;
3539         I915_WRITE(reg, temp);
3540
3541         POSTING_READ(reg);
3542         udelay(150);
3543
3544         /* enable CPU FDI TX and PCH FDI RX */
3545         reg = FDI_TX_CTL(pipe);
3546         temp = I915_READ(reg);
3547         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3548         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3549         temp &= ~FDI_LINK_TRAIN_NONE;
3550         temp |= FDI_LINK_TRAIN_PATTERN_1;
3551         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3552         /* SNB-B */
3553         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3554         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3555
3556         I915_WRITE(FDI_RX_MISC(pipe),
3557                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3558
3559         reg = FDI_RX_CTL(pipe);
3560         temp = I915_READ(reg);
3561         if (HAS_PCH_CPT(dev)) {
3562                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3563                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3564         } else {
3565                 temp &= ~FDI_LINK_TRAIN_NONE;
3566                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3567         }
3568         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3569
3570         POSTING_READ(reg);
3571         udelay(150);
3572
3573         for (i = 0; i < 4; i++) {
3574                 reg = FDI_TX_CTL(pipe);
3575                 temp = I915_READ(reg);
3576                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3577                 temp |= snb_b_fdi_train_param[i];
3578                 I915_WRITE(reg, temp);
3579
3580                 POSTING_READ(reg);
3581                 udelay(500);
3582
3583                 for (retry = 0; retry < 5; retry++) {
3584                         reg = FDI_RX_IIR(pipe);
3585                         temp = I915_READ(reg);
3586                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3587                         if (temp & FDI_RX_BIT_LOCK) {
3588                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3589                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3590                                 break;
3591                         }
3592                         udelay(50);
3593                 }
3594                 if (retry < 5)
3595                         break;
3596         }
3597         if (i == 4)
3598                 DRM_ERROR("FDI train 1 fail!\n");
3599
3600         /* Train 2 */
3601         reg = FDI_TX_CTL(pipe);
3602         temp = I915_READ(reg);
3603         temp &= ~FDI_LINK_TRAIN_NONE;
3604         temp |= FDI_LINK_TRAIN_PATTERN_2;
3605         if (IS_GEN6(dev)) {
3606                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3607                 /* SNB-B */
3608                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3609         }
3610         I915_WRITE(reg, temp);
3611
3612         reg = FDI_RX_CTL(pipe);
3613         temp = I915_READ(reg);
3614         if (HAS_PCH_CPT(dev)) {
3615                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3616                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3617         } else {
3618                 temp &= ~FDI_LINK_TRAIN_NONE;
3619                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3620         }
3621         I915_WRITE(reg, temp);
3622
3623         POSTING_READ(reg);
3624         udelay(150);
3625
3626         for (i = 0; i < 4; i++) {
3627                 reg = FDI_TX_CTL(pipe);
3628                 temp = I915_READ(reg);
3629                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3630                 temp |= snb_b_fdi_train_param[i];
3631                 I915_WRITE(reg, temp);
3632
3633                 POSTING_READ(reg);
3634                 udelay(500);
3635
3636                 for (retry = 0; retry < 5; retry++) {
3637                         reg = FDI_RX_IIR(pipe);
3638                         temp = I915_READ(reg);
3639                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3640                         if (temp & FDI_RX_SYMBOL_LOCK) {
3641                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3642                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3643                                 break;
3644                         }
3645                         udelay(50);
3646                 }
3647                 if (retry < 5)
3648                         break;
3649         }
3650         if (i == 4)
3651                 DRM_ERROR("FDI train 2 fail!\n");
3652
3653         DRM_DEBUG_KMS("FDI train done.\n");
3654 }
3655
3656 /* Manual link training for Ivy Bridge A0 parts */
3657 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3658 {
3659         struct drm_device *dev = crtc->dev;
3660         struct drm_i915_private *dev_priv = dev->dev_private;
3661         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3662         int pipe = intel_crtc->pipe;
3663         u32 reg, temp, i, j;
3664
3665         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3666            for train result */
3667         reg = FDI_RX_IMR(pipe);
3668         temp = I915_READ(reg);
3669         temp &= ~FDI_RX_SYMBOL_LOCK;
3670         temp &= ~FDI_RX_BIT_LOCK;
3671         I915_WRITE(reg, temp);
3672
3673         POSTING_READ(reg);
3674         udelay(150);
3675
3676         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3677                       I915_READ(FDI_RX_IIR(pipe)));
3678
3679         /* Try each vswing and preemphasis setting twice before moving on */
3680         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3681                 /* disable first in case we need to retry */
3682                 reg = FDI_TX_CTL(pipe);
3683                 temp = I915_READ(reg);
3684                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3685                 temp &= ~FDI_TX_ENABLE;
3686                 I915_WRITE(reg, temp);
3687
3688                 reg = FDI_RX_CTL(pipe);
3689                 temp = I915_READ(reg);
3690                 temp &= ~FDI_LINK_TRAIN_AUTO;
3691                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3692                 temp &= ~FDI_RX_ENABLE;
3693                 I915_WRITE(reg, temp);
3694
3695                 /* enable CPU FDI TX and PCH FDI RX */
3696                 reg = FDI_TX_CTL(pipe);
3697                 temp = I915_READ(reg);
3698                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3699                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3700                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3701                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3702                 temp |= snb_b_fdi_train_param[j/2];
3703                 temp |= FDI_COMPOSITE_SYNC;
3704                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3705
3706                 I915_WRITE(FDI_RX_MISC(pipe),
3707                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3708
3709                 reg = FDI_RX_CTL(pipe);
3710                 temp = I915_READ(reg);
3711                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3712                 temp |= FDI_COMPOSITE_SYNC;
3713                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3714
3715                 POSTING_READ(reg);
3716                 udelay(1); /* should be 0.5us */
3717
3718                 for (i = 0; i < 4; i++) {
3719                         reg = FDI_RX_IIR(pipe);
3720                         temp = I915_READ(reg);
3721                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3722
3723                         if (temp & FDI_RX_BIT_LOCK ||
3724                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3725                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3726                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3727                                               i);
3728                                 break;
3729                         }
3730                         udelay(1); /* should be 0.5us */
3731                 }
3732                 if (i == 4) {
3733                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3734                         continue;
3735                 }
3736
3737                 /* Train 2 */
3738                 reg = FDI_TX_CTL(pipe);
3739                 temp = I915_READ(reg);
3740                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3741                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3742                 I915_WRITE(reg, temp);
3743
3744                 reg = FDI_RX_CTL(pipe);
3745                 temp = I915_READ(reg);
3746                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3747                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3748                 I915_WRITE(reg, temp);
3749
3750                 POSTING_READ(reg);
3751                 udelay(2); /* should be 1.5us */
3752
3753                 for (i = 0; i < 4; i++) {
3754                         reg = FDI_RX_IIR(pipe);
3755                         temp = I915_READ(reg);
3756                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3757
3758                         if (temp & FDI_RX_SYMBOL_LOCK ||
3759                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3760                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3761                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3762                                               i);
3763                                 goto train_done;
3764                         }
3765                         udelay(2); /* should be 1.5us */
3766                 }
3767                 if (i == 4)
3768                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3769         }
3770
3771 train_done:
3772         DRM_DEBUG_KMS("FDI train done.\n");
3773 }
3774
3775 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3776 {
3777         struct drm_device *dev = intel_crtc->base.dev;
3778         struct drm_i915_private *dev_priv = dev->dev_private;
3779         int pipe = intel_crtc->pipe;
3780         u32 reg, temp;
3781
3782
3783         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3784         reg = FDI_RX_CTL(pipe);
3785         temp = I915_READ(reg);
3786         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3787         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3788         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3789         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3790
3791         POSTING_READ(reg);
3792         udelay(200);
3793
3794         /* Switch from Rawclk to PCDclk */
3795         temp = I915_READ(reg);
3796         I915_WRITE(reg, temp | FDI_PCDCLK);
3797
3798         POSTING_READ(reg);
3799         udelay(200);
3800
3801         /* Enable CPU FDI TX PLL, always on for Ironlake */
3802         reg = FDI_TX_CTL(pipe);
3803         temp = I915_READ(reg);
3804         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3805                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3806
3807                 POSTING_READ(reg);
3808                 udelay(100);
3809         }
3810 }
3811
3812 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3813 {
3814         struct drm_device *dev = intel_crtc->base.dev;
3815         struct drm_i915_private *dev_priv = dev->dev_private;
3816         int pipe = intel_crtc->pipe;
3817         u32 reg, temp;
3818
3819         /* Switch from PCDclk to Rawclk */
3820         reg = FDI_RX_CTL(pipe);
3821         temp = I915_READ(reg);
3822         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3823
3824         /* Disable CPU FDI TX PLL */
3825         reg = FDI_TX_CTL(pipe);
3826         temp = I915_READ(reg);
3827         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3828
3829         POSTING_READ(reg);
3830         udelay(100);
3831
3832         reg = FDI_RX_CTL(pipe);
3833         temp = I915_READ(reg);
3834         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3835
3836         /* Wait for the clocks to turn off. */
3837         POSTING_READ(reg);
3838         udelay(100);
3839 }
3840
3841 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3842 {
3843         struct drm_device *dev = crtc->dev;
3844         struct drm_i915_private *dev_priv = dev->dev_private;
3845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3846         int pipe = intel_crtc->pipe;
3847         u32 reg, temp;
3848
3849         /* disable CPU FDI tx and PCH FDI rx */
3850         reg = FDI_TX_CTL(pipe);
3851         temp = I915_READ(reg);
3852         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3853         POSTING_READ(reg);
3854
3855         reg = FDI_RX_CTL(pipe);
3856         temp = I915_READ(reg);
3857         temp &= ~(0x7 << 16);
3858         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3859         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3860
3861         POSTING_READ(reg);
3862         udelay(100);
3863
3864         /* Ironlake workaround, disable clock pointer after downing FDI */
3865         if (HAS_PCH_IBX(dev))
3866                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3867
3868         /* still set train pattern 1 */
3869         reg = FDI_TX_CTL(pipe);
3870         temp = I915_READ(reg);
3871         temp &= ~FDI_LINK_TRAIN_NONE;
3872         temp |= FDI_LINK_TRAIN_PATTERN_1;
3873         I915_WRITE(reg, temp);
3874
3875         reg = FDI_RX_CTL(pipe);
3876         temp = I915_READ(reg);
3877         if (HAS_PCH_CPT(dev)) {
3878                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3879                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3880         } else {
3881                 temp &= ~FDI_LINK_TRAIN_NONE;
3882                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3883         }
3884         /* BPC in FDI rx is consistent with that in PIPECONF */
3885         temp &= ~(0x07 << 16);
3886         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3887         I915_WRITE(reg, temp);
3888
3889         POSTING_READ(reg);
3890         udelay(100);
3891 }
3892
3893 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3894 {
3895         struct intel_crtc *crtc;
3896
3897         /* Note that we don't need to be called with mode_config.lock here
3898          * as our list of CRTC objects is static for the lifetime of the
3899          * device and so cannot disappear as we iterate. Similarly, we can
3900          * happily treat the predicates as racy, atomic checks as userspace
3901          * cannot claim and pin a new fb without at least acquring the
3902          * struct_mutex and so serialising with us.
3903          */
3904         for_each_intel_crtc(dev, crtc) {
3905                 if (atomic_read(&crtc->unpin_work_count) == 0)
3906                         continue;
3907
3908                 if (crtc->unpin_work)
3909                         intel_wait_for_vblank(dev, crtc->pipe);
3910
3911                 return true;
3912         }
3913
3914         return false;
3915 }
3916
3917 static void page_flip_completed(struct intel_crtc *intel_crtc)
3918 {
3919         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3920         struct intel_unpin_work *work = intel_crtc->unpin_work;
3921
3922         /* ensure that the unpin work is consistent wrt ->pending. */
3923         smp_rmb();
3924         intel_crtc->unpin_work = NULL;
3925
3926         if (work->event)
3927                 drm_send_vblank_event(intel_crtc->base.dev,
3928                                       intel_crtc->pipe,
3929                                       work->event);
3930
3931         drm_crtc_vblank_put(&intel_crtc->base);
3932
3933         wake_up_all(&dev_priv->pending_flip_queue);
3934         queue_work(dev_priv->wq, &work->work);
3935
3936         trace_i915_flip_complete(intel_crtc->plane,
3937                                  work->pending_flip_obj);
3938 }
3939
3940 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3941 {
3942         struct drm_device *dev = crtc->dev;
3943         struct drm_i915_private *dev_priv = dev->dev_private;
3944
3945         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3946         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3947                                        !intel_crtc_has_pending_flip(crtc),
3948                                        60*HZ) == 0)) {
3949                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3950
3951                 spin_lock_irq(&dev->event_lock);
3952                 if (intel_crtc->unpin_work) {
3953                         WARN_ONCE(1, "Removing stuck page flip\n");
3954                         page_flip_completed(intel_crtc);
3955                 }
3956                 spin_unlock_irq(&dev->event_lock);
3957         }
3958
3959         if (crtc->primary->fb) {
3960                 mutex_lock(&dev->struct_mutex);
3961                 intel_finish_fb(crtc->primary->fb);
3962                 mutex_unlock(&dev->struct_mutex);
3963         }
3964 }
3965
3966 /* Program iCLKIP clock to the desired frequency */
3967 static void lpt_program_iclkip(struct drm_crtc *crtc)
3968 {
3969         struct drm_device *dev = crtc->dev;
3970         struct drm_i915_private *dev_priv = dev->dev_private;
3971         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3972         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3973         u32 temp;
3974
3975         mutex_lock(&dev_priv->sb_lock);
3976
3977         /* It is necessary to ungate the pixclk gate prior to programming
3978          * the divisors, and gate it back when it is done.
3979          */
3980         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3981
3982         /* Disable SSCCTL */
3983         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3984                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3985                                 SBI_SSCCTL_DISABLE,
3986                         SBI_ICLK);
3987
3988         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3989         if (clock == 20000) {
3990                 auxdiv = 1;
3991                 divsel = 0x41;
3992                 phaseinc = 0x20;
3993         } else {
3994                 /* The iCLK virtual clock root frequency is in MHz,
3995                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3996                  * divisors, it is necessary to divide one by another, so we
3997                  * convert the virtual clock precision to KHz here for higher
3998                  * precision.
3999                  */
4000                 u32 iclk_virtual_root_freq = 172800 * 1000;
4001                 u32 iclk_pi_range = 64;
4002                 u32 desired_divisor, msb_divisor_value, pi_value;
4003
4004                 desired_divisor = (iclk_virtual_root_freq / clock);
4005                 msb_divisor_value = desired_divisor / iclk_pi_range;
4006                 pi_value = desired_divisor % iclk_pi_range;
4007
4008                 auxdiv = 0;
4009                 divsel = msb_divisor_value - 2;
4010                 phaseinc = pi_value;
4011         }
4012
4013         /* This should not happen with any sane values */
4014         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4015                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4016         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4017                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4018
4019         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4020                         clock,
4021                         auxdiv,
4022                         divsel,
4023                         phasedir,
4024                         phaseinc);
4025
4026         /* Program SSCDIVINTPHASE6 */
4027         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4028         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4029         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4030         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4031         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4032         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4033         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4034         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4035
4036         /* Program SSCAUXDIV */
4037         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4038         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4039         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4040         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4041
4042         /* Enable modulator and associated divider */
4043         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4044         temp &= ~SBI_SSCCTL_DISABLE;
4045         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4046
4047         /* Wait for initialization time */
4048         udelay(24);
4049
4050         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4051
4052         mutex_unlock(&dev_priv->sb_lock);
4053 }
4054
4055 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4056                                                 enum pipe pch_transcoder)
4057 {
4058         struct drm_device *dev = crtc->base.dev;
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4061
4062         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4063                    I915_READ(HTOTAL(cpu_transcoder)));
4064         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4065                    I915_READ(HBLANK(cpu_transcoder)));
4066         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4067                    I915_READ(HSYNC(cpu_transcoder)));
4068
4069         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4070                    I915_READ(VTOTAL(cpu_transcoder)));
4071         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4072                    I915_READ(VBLANK(cpu_transcoder)));
4073         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4074                    I915_READ(VSYNC(cpu_transcoder)));
4075         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4076                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4077 }
4078
4079 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4080 {
4081         struct drm_i915_private *dev_priv = dev->dev_private;
4082         uint32_t temp;
4083
4084         temp = I915_READ(SOUTH_CHICKEN1);
4085         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4086                 return;
4087
4088         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4089         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4090
4091         temp &= ~FDI_BC_BIFURCATION_SELECT;
4092         if (enable)
4093                 temp |= FDI_BC_BIFURCATION_SELECT;
4094
4095         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4096         I915_WRITE(SOUTH_CHICKEN1, temp);
4097         POSTING_READ(SOUTH_CHICKEN1);
4098 }
4099
4100 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4101 {
4102         struct drm_device *dev = intel_crtc->base.dev;
4103
4104         switch (intel_crtc->pipe) {
4105         case PIPE_A:
4106                 break;
4107         case PIPE_B:
4108                 if (intel_crtc->config->fdi_lanes > 2)
4109                         cpt_set_fdi_bc_bifurcation(dev, false);
4110                 else
4111                         cpt_set_fdi_bc_bifurcation(dev, true);
4112
4113                 break;
4114         case PIPE_C:
4115                 cpt_set_fdi_bc_bifurcation(dev, true);
4116
4117                 break;
4118         default:
4119                 BUG();
4120         }
4121 }
4122
4123 /*
4124  * Enable PCH resources required for PCH ports:
4125  *   - PCH PLLs
4126  *   - FDI training & RX/TX
4127  *   - update transcoder timings
4128  *   - DP transcoding bits
4129  *   - transcoder
4130  */
4131 static void ironlake_pch_enable(struct drm_crtc *crtc)
4132 {
4133         struct drm_device *dev = crtc->dev;
4134         struct drm_i915_private *dev_priv = dev->dev_private;
4135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4136         int pipe = intel_crtc->pipe;
4137         u32 reg, temp;
4138
4139         assert_pch_transcoder_disabled(dev_priv, pipe);
4140
4141         if (IS_IVYBRIDGE(dev))
4142                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4143
4144         /* Write the TU size bits before fdi link training, so that error
4145          * detection works. */
4146         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4147                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4148
4149         /* For PCH output, training FDI link */
4150         dev_priv->display.fdi_link_train(crtc);
4151
4152         /* We need to program the right clock selection before writing the pixel
4153          * mutliplier into the DPLL. */
4154         if (HAS_PCH_CPT(dev)) {
4155                 u32 sel;
4156
4157                 temp = I915_READ(PCH_DPLL_SEL);
4158                 temp |= TRANS_DPLL_ENABLE(pipe);
4159                 sel = TRANS_DPLLB_SEL(pipe);
4160                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4161                         temp |= sel;
4162                 else
4163                         temp &= ~sel;
4164                 I915_WRITE(PCH_DPLL_SEL, temp);
4165         }
4166
4167         /* XXX: pch pll's can be enabled any time before we enable the PCH
4168          * transcoder, and we actually should do this to not upset any PCH
4169          * transcoder that already use the clock when we share it.
4170          *
4171          * Note that enable_shared_dpll tries to do the right thing, but
4172          * get_shared_dpll unconditionally resets the pll - we need that to have
4173          * the right LVDS enable sequence. */
4174         intel_enable_shared_dpll(intel_crtc);
4175
4176         /* set transcoder timing, panel must allow it */
4177         assert_panel_unlocked(dev_priv, pipe);
4178         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4179
4180         intel_fdi_normal_train(crtc);
4181
4182         /* For PCH DP, enable TRANS_DP_CTL */
4183         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4184                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4185                 reg = TRANS_DP_CTL(pipe);
4186                 temp = I915_READ(reg);
4187                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4188                           TRANS_DP_SYNC_MASK |
4189                           TRANS_DP_BPC_MASK);
4190                 temp |= TRANS_DP_OUTPUT_ENABLE;
4191                 temp |= bpc << 9; /* same format but at 11:9 */
4192
4193                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4194                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4195                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4196                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4197
4198                 switch (intel_trans_dp_port_sel(crtc)) {
4199                 case PCH_DP_B:
4200                         temp |= TRANS_DP_PORT_SEL_B;
4201                         break;
4202                 case PCH_DP_C:
4203                         temp |= TRANS_DP_PORT_SEL_C;
4204                         break;
4205                 case PCH_DP_D:
4206                         temp |= TRANS_DP_PORT_SEL_D;
4207                         break;
4208                 default:
4209                         BUG();
4210                 }
4211
4212                 I915_WRITE(reg, temp);
4213         }
4214
4215         ironlake_enable_pch_transcoder(dev_priv, pipe);
4216 }
4217
4218 static void lpt_pch_enable(struct drm_crtc *crtc)
4219 {
4220         struct drm_device *dev = crtc->dev;
4221         struct drm_i915_private *dev_priv = dev->dev_private;
4222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4223         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4224
4225         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4226
4227         lpt_program_iclkip(crtc);
4228
4229         /* Set transcoder timing. */
4230         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4231
4232         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4233 }
4234
4235 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4236                                                 struct intel_crtc_state *crtc_state)
4237 {
4238         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4239         struct intel_shared_dpll *pll;
4240         struct intel_shared_dpll_config *shared_dpll;
4241         enum intel_dpll_id i;
4242         int max = dev_priv->num_shared_dpll;
4243
4244         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4245
4246         if (HAS_PCH_IBX(dev_priv->dev)) {
4247                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4248                 i = (enum intel_dpll_id) crtc->pipe;
4249                 pll = &dev_priv->shared_dplls[i];
4250
4251                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4252                               crtc->base.base.id, pll->name);
4253
4254                 WARN_ON(shared_dpll[i].crtc_mask);
4255
4256                 goto found;
4257         }
4258
4259         if (IS_BROXTON(dev_priv->dev)) {
4260                 /* PLL is attached to port in bxt */
4261                 struct intel_encoder *encoder;
4262                 struct intel_digital_port *intel_dig_port;
4263
4264                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4265                 if (WARN_ON(!encoder))
4266                         return NULL;
4267
4268                 intel_dig_port = enc_to_dig_port(&encoder->base);
4269                 /* 1:1 mapping between ports and PLLs */
4270                 i = (enum intel_dpll_id)intel_dig_port->port;
4271                 pll = &dev_priv->shared_dplls[i];
4272                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4273                         crtc->base.base.id, pll->name);
4274                 WARN_ON(shared_dpll[i].crtc_mask);
4275
4276                 goto found;
4277         } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4278                 /* Do not consider SPLL */
4279                 max = 2;
4280
4281         for (i = 0; i < max; i++) {
4282                 pll = &dev_priv->shared_dplls[i];
4283
4284                 /* Only want to check enabled timings first */
4285                 if (shared_dpll[i].crtc_mask == 0)
4286                         continue;
4287
4288                 if (memcmp(&crtc_state->dpll_hw_state,
4289                            &shared_dpll[i].hw_state,
4290                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4291                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4292                                       crtc->base.base.id, pll->name,
4293                                       shared_dpll[i].crtc_mask,
4294                                       pll->active);
4295                         goto found;
4296                 }
4297         }
4298
4299         /* Ok no matching timings, maybe there's a free one? */
4300         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4301                 pll = &dev_priv->shared_dplls[i];
4302                 if (shared_dpll[i].crtc_mask == 0) {
4303                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4304                                       crtc->base.base.id, pll->name);
4305                         goto found;
4306                 }
4307         }
4308
4309         return NULL;
4310
4311 found:
4312         if (shared_dpll[i].crtc_mask == 0)
4313                 shared_dpll[i].hw_state =
4314                         crtc_state->dpll_hw_state;
4315
4316         crtc_state->shared_dpll = i;
4317         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4318                          pipe_name(crtc->pipe));
4319
4320         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4321
4322         return pll;
4323 }
4324
4325 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4326 {
4327         struct drm_i915_private *dev_priv = to_i915(state->dev);
4328         struct intel_shared_dpll_config *shared_dpll;
4329         struct intel_shared_dpll *pll;
4330         enum intel_dpll_id i;
4331
4332         if (!to_intel_atomic_state(state)->dpll_set)
4333                 return;
4334
4335         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4336         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4337                 pll = &dev_priv->shared_dplls[i];
4338                 pll->config = shared_dpll[i];
4339         }
4340 }
4341
4342 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4343 {
4344         struct drm_i915_private *dev_priv = dev->dev_private;
4345         int dslreg = PIPEDSL(pipe);
4346         u32 temp;
4347
4348         temp = I915_READ(dslreg);
4349         udelay(500);
4350         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4351                 if (wait_for(I915_READ(dslreg) != temp, 5))
4352                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4353         }
4354 }
4355
4356 static int
4357 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4358                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4359                   int src_w, int src_h, int dst_w, int dst_h)
4360 {
4361         struct intel_crtc_scaler_state *scaler_state =
4362                 &crtc_state->scaler_state;
4363         struct intel_crtc *intel_crtc =
4364                 to_intel_crtc(crtc_state->base.crtc);
4365         int need_scaling;
4366
4367         need_scaling = intel_rotation_90_or_270(rotation) ?
4368                 (src_h != dst_w || src_w != dst_h):
4369                 (src_w != dst_w || src_h != dst_h);
4370
4371         /*
4372          * if plane is being disabled or scaler is no more required or force detach
4373          *  - free scaler binded to this plane/crtc
4374          *  - in order to do this, update crtc->scaler_usage
4375          *
4376          * Here scaler state in crtc_state is set free so that
4377          * scaler can be assigned to other user. Actual register
4378          * update to free the scaler is done in plane/panel-fit programming.
4379          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4380          */
4381         if (force_detach || !need_scaling) {
4382                 if (*scaler_id >= 0) {
4383                         scaler_state->scaler_users &= ~(1 << scaler_user);
4384                         scaler_state->scalers[*scaler_id].in_use = 0;
4385
4386                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4387                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4388                                 intel_crtc->pipe, scaler_user, *scaler_id,
4389                                 scaler_state->scaler_users);
4390                         *scaler_id = -1;
4391                 }
4392                 return 0;
4393         }
4394
4395         /* range checks */
4396         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4397                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4398
4399                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4400                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4401                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4402                         "size is out of scaler range\n",
4403                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4404                 return -EINVAL;
4405         }
4406
4407         /* mark this plane as a scaler user in crtc_state */
4408         scaler_state->scaler_users |= (1 << scaler_user);
4409         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4410                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4411                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4412                 scaler_state->scaler_users);
4413
4414         return 0;
4415 }
4416
4417 /**
4418  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4419  *
4420  * @state: crtc's scaler state
4421  *
4422  * Return
4423  *     0 - scaler_usage updated successfully
4424  *    error - requested scaling cannot be supported or other error condition
4425  */
4426 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4427 {
4428         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4429         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4430
4431         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4432                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4433
4434         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4435                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4436                 state->pipe_src_w, state->pipe_src_h,
4437                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4438 }
4439
4440 /**
4441  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4442  *
4443  * @state: crtc's scaler state
4444  * @plane_state: atomic plane state to update
4445  *
4446  * Return
4447  *     0 - scaler_usage updated successfully
4448  *    error - requested scaling cannot be supported or other error condition
4449  */
4450 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4451                                    struct intel_plane_state *plane_state)
4452 {
4453
4454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4455         struct intel_plane *intel_plane =
4456                 to_intel_plane(plane_state->base.plane);
4457         struct drm_framebuffer *fb = plane_state->base.fb;
4458         int ret;
4459
4460         bool force_detach = !fb || !plane_state->visible;
4461
4462         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4463                       intel_plane->base.base.id, intel_crtc->pipe,
4464                       drm_plane_index(&intel_plane->base));
4465
4466         ret = skl_update_scaler(crtc_state, force_detach,
4467                                 drm_plane_index(&intel_plane->base),
4468                                 &plane_state->scaler_id,
4469                                 plane_state->base.rotation,
4470                                 drm_rect_width(&plane_state->src) >> 16,
4471                                 drm_rect_height(&plane_state->src) >> 16,
4472                                 drm_rect_width(&plane_state->dst),
4473                                 drm_rect_height(&plane_state->dst));
4474
4475         if (ret || plane_state->scaler_id < 0)
4476                 return ret;
4477
4478         /* check colorkey */
4479         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4480                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4481                               intel_plane->base.base.id);
4482                 return -EINVAL;
4483         }
4484
4485         /* Check src format */
4486         switch (fb->pixel_format) {
4487         case DRM_FORMAT_RGB565:
4488         case DRM_FORMAT_XBGR8888:
4489         case DRM_FORMAT_XRGB8888:
4490         case DRM_FORMAT_ABGR8888:
4491         case DRM_FORMAT_ARGB8888:
4492         case DRM_FORMAT_XRGB2101010:
4493         case DRM_FORMAT_XBGR2101010:
4494         case DRM_FORMAT_YUYV:
4495         case DRM_FORMAT_YVYU:
4496         case DRM_FORMAT_UYVY:
4497         case DRM_FORMAT_VYUY:
4498                 break;
4499         default:
4500                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4501                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4502                 return -EINVAL;
4503         }
4504
4505         return 0;
4506 }
4507
4508 static void skylake_scaler_disable(struct intel_crtc *crtc)
4509 {
4510         int i;
4511
4512         for (i = 0; i < crtc->num_scalers; i++)
4513                 skl_detach_scaler(crtc, i);
4514 }
4515
4516 static void skylake_pfit_enable(struct intel_crtc *crtc)
4517 {
4518         struct drm_device *dev = crtc->base.dev;
4519         struct drm_i915_private *dev_priv = dev->dev_private;
4520         int pipe = crtc->pipe;
4521         struct intel_crtc_scaler_state *scaler_state =
4522                 &crtc->config->scaler_state;
4523
4524         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4525
4526         if (crtc->config->pch_pfit.enabled) {
4527                 int id;
4528
4529                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4530                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4531                         return;
4532                 }
4533
4534                 id = scaler_state->scaler_id;
4535                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4536                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4537                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4538                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4539
4540                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4541         }
4542 }
4543
4544 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4545 {
4546         struct drm_device *dev = crtc->base.dev;
4547         struct drm_i915_private *dev_priv = dev->dev_private;
4548         int pipe = crtc->pipe;
4549
4550         if (crtc->config->pch_pfit.enabled) {
4551                 /* Force use of hard-coded filter coefficients
4552                  * as some pre-programmed values are broken,
4553                  * e.g. x201.
4554                  */
4555                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4556                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4557                                                  PF_PIPE_SEL_IVB(pipe));
4558                 else
4559                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4560                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4561                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4562         }
4563 }
4564
4565 void hsw_enable_ips(struct intel_crtc *crtc)
4566 {
4567         struct drm_device *dev = crtc->base.dev;
4568         struct drm_i915_private *dev_priv = dev->dev_private;
4569
4570         if (!crtc->config->ips_enabled)
4571                 return;
4572
4573         /* We can only enable IPS after we enable a plane and wait for a vblank */
4574         intel_wait_for_vblank(dev, crtc->pipe);
4575
4576         assert_plane_enabled(dev_priv, crtc->plane);
4577         if (IS_BROADWELL(dev)) {
4578                 mutex_lock(&dev_priv->rps.hw_lock);
4579                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4580                 mutex_unlock(&dev_priv->rps.hw_lock);
4581                 /* Quoting Art Runyan: "its not safe to expect any particular
4582                  * value in IPS_CTL bit 31 after enabling IPS through the
4583                  * mailbox." Moreover, the mailbox may return a bogus state,
4584                  * so we need to just enable it and continue on.
4585                  */
4586         } else {
4587                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4588                 /* The bit only becomes 1 in the next vblank, so this wait here
4589                  * is essentially intel_wait_for_vblank. If we don't have this
4590                  * and don't wait for vblanks until the end of crtc_enable, then
4591                  * the HW state readout code will complain that the expected
4592                  * IPS_CTL value is not the one we read. */
4593                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4594                         DRM_ERROR("Timed out waiting for IPS enable\n");
4595         }
4596 }
4597
4598 void hsw_disable_ips(struct intel_crtc *crtc)
4599 {
4600         struct drm_device *dev = crtc->base.dev;
4601         struct drm_i915_private *dev_priv = dev->dev_private;
4602
4603         if (!crtc->config->ips_enabled)
4604                 return;
4605
4606         assert_plane_enabled(dev_priv, crtc->plane);
4607         if (IS_BROADWELL(dev)) {
4608                 mutex_lock(&dev_priv->rps.hw_lock);
4609                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4610                 mutex_unlock(&dev_priv->rps.hw_lock);
4611                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4612                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4613                         DRM_ERROR("Timed out waiting for IPS disable\n");
4614         } else {
4615                 I915_WRITE(IPS_CTL, 0);
4616                 POSTING_READ(IPS_CTL);
4617         }
4618
4619         /* We need to wait for a vblank before we can disable the plane. */
4620         intel_wait_for_vblank(dev, crtc->pipe);
4621 }
4622
4623 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4624 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4625 {
4626         struct drm_device *dev = crtc->dev;
4627         struct drm_i915_private *dev_priv = dev->dev_private;
4628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629         enum pipe pipe = intel_crtc->pipe;
4630         int i;
4631         bool reenable_ips = false;
4632
4633         /* The clocks have to be on to load the palette. */
4634         if (!crtc->state->active)
4635                 return;
4636
4637         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4638                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4639                         assert_dsi_pll_enabled(dev_priv);
4640                 else
4641                         assert_pll_enabled(dev_priv, pipe);
4642         }
4643
4644         /* Workaround : Do not read or write the pipe palette/gamma data while
4645          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4646          */
4647         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4648             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4649              GAMMA_MODE_MODE_SPLIT)) {
4650                 hsw_disable_ips(intel_crtc);
4651                 reenable_ips = true;
4652         }
4653
4654         for (i = 0; i < 256; i++) {
4655                 u32 palreg;
4656
4657                 if (HAS_GMCH_DISPLAY(dev))
4658                         palreg = PALETTE(pipe, i);
4659                 else
4660                         palreg = LGC_PALETTE(pipe, i);
4661
4662                 I915_WRITE(palreg,
4663                            (intel_crtc->lut_r[i] << 16) |
4664                            (intel_crtc->lut_g[i] << 8) |
4665                            intel_crtc->lut_b[i]);
4666         }
4667
4668         if (reenable_ips)
4669                 hsw_enable_ips(intel_crtc);
4670 }
4671
4672 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4673 {
4674         if (intel_crtc->overlay) {
4675                 struct drm_device *dev = intel_crtc->base.dev;
4676                 struct drm_i915_private *dev_priv = dev->dev_private;
4677
4678                 mutex_lock(&dev->struct_mutex);
4679                 dev_priv->mm.interruptible = false;
4680                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4681                 dev_priv->mm.interruptible = true;
4682                 mutex_unlock(&dev->struct_mutex);
4683         }
4684
4685         /* Let userspace switch the overlay on again. In most cases userspace
4686          * has to recompute where to put it anyway.
4687          */
4688 }
4689
4690 /**
4691  * intel_post_enable_primary - Perform operations after enabling primary plane
4692  * @crtc: the CRTC whose primary plane was just enabled
4693  *
4694  * Performs potentially sleeping operations that must be done after the primary
4695  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4696  * called due to an explicit primary plane update, or due to an implicit
4697  * re-enable that is caused when a sprite plane is updated to no longer
4698  * completely hide the primary plane.
4699  */
4700 static void
4701 intel_post_enable_primary(struct drm_crtc *crtc)
4702 {
4703         struct drm_device *dev = crtc->dev;
4704         struct drm_i915_private *dev_priv = dev->dev_private;
4705         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4706         int pipe = intel_crtc->pipe;
4707
4708         /*
4709          * BDW signals flip done immediately if the plane
4710          * is disabled, even if the plane enable is already
4711          * armed to occur at the next vblank :(
4712          */
4713         if (IS_BROADWELL(dev))
4714                 intel_wait_for_vblank(dev, pipe);
4715
4716         /*
4717          * FIXME IPS should be fine as long as one plane is
4718          * enabled, but in practice it seems to have problems
4719          * when going from primary only to sprite only and vice
4720          * versa.
4721          */
4722         hsw_enable_ips(intel_crtc);
4723
4724         /*
4725          * Gen2 reports pipe underruns whenever all planes are disabled.
4726          * So don't enable underrun reporting before at least some planes
4727          * are enabled.
4728          * FIXME: Need to fix the logic to work when we turn off all planes
4729          * but leave the pipe running.
4730          */
4731         if (IS_GEN2(dev))
4732                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4733
4734         /* Underruns don't raise interrupts, so check manually. */
4735         if (HAS_GMCH_DISPLAY(dev))
4736                 i9xx_check_fifo_underruns(dev_priv);
4737 }
4738
4739 /**
4740  * intel_pre_disable_primary - Perform operations before disabling primary plane
4741  * @crtc: the CRTC whose primary plane is to be disabled
4742  *
4743  * Performs potentially sleeping operations that must be done before the
4744  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4745  * be called due to an explicit primary plane update, or due to an implicit
4746  * disable that is caused when a sprite plane completely hides the primary
4747  * plane.
4748  */
4749 static void
4750 intel_pre_disable_primary(struct drm_crtc *crtc)
4751 {
4752         struct drm_device *dev = crtc->dev;
4753         struct drm_i915_private *dev_priv = dev->dev_private;
4754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4755         int pipe = intel_crtc->pipe;
4756
4757         /*
4758          * Gen2 reports pipe underruns whenever all planes are disabled.
4759          * So diasble underrun reporting before all the planes get disabled.
4760          * FIXME: Need to fix the logic to work when we turn off all planes
4761          * but leave the pipe running.
4762          */
4763         if (IS_GEN2(dev))
4764                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4765
4766         /*
4767          * Vblank time updates from the shadow to live plane control register
4768          * are blocked if the memory self-refresh mode is active at that
4769          * moment. So to make sure the plane gets truly disabled, disable
4770          * first the self-refresh mode. The self-refresh enable bit in turn
4771          * will be checked/applied by the HW only at the next frame start
4772          * event which is after the vblank start event, so we need to have a
4773          * wait-for-vblank between disabling the plane and the pipe.
4774          */
4775         if (HAS_GMCH_DISPLAY(dev)) {
4776                 intel_set_memory_cxsr(dev_priv, false);
4777                 dev_priv->wm.vlv.cxsr = false;
4778                 intel_wait_for_vblank(dev, pipe);
4779         }
4780
4781         /*
4782          * FIXME IPS should be fine as long as one plane is
4783          * enabled, but in practice it seems to have problems
4784          * when going from primary only to sprite only and vice
4785          * versa.
4786          */
4787         hsw_disable_ips(intel_crtc);
4788 }
4789
4790 static void intel_post_plane_update(struct intel_crtc *crtc)
4791 {
4792         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4793         struct drm_device *dev = crtc->base.dev;
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795         struct drm_plane *plane;
4796
4797         if (atomic->wait_vblank)
4798                 intel_wait_for_vblank(dev, crtc->pipe);
4799
4800         intel_frontbuffer_flip(dev, atomic->fb_bits);
4801
4802         if (atomic->disable_cxsr)
4803                 crtc->wm.cxsr_allowed = true;
4804
4805         if (crtc->atomic.update_wm_post)
4806                 intel_update_watermarks(&crtc->base);
4807
4808         if (atomic->update_fbc)
4809                 intel_fbc_update(dev_priv);
4810
4811         if (atomic->post_enable_primary)
4812                 intel_post_enable_primary(&crtc->base);
4813
4814         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4815                 intel_update_sprite_watermarks(plane, &crtc->base,
4816                                                0, 0, 0, false, false);
4817
4818         memset(atomic, 0, sizeof(*atomic));
4819 }
4820
4821 static void intel_pre_plane_update(struct intel_crtc *crtc)
4822 {
4823         struct drm_device *dev = crtc->base.dev;
4824         struct drm_i915_private *dev_priv = dev->dev_private;
4825         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4826         struct drm_plane *p;
4827
4828         /* Track fb's for any planes being disabled */
4829         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4830                 struct intel_plane *plane = to_intel_plane(p);
4831
4832                 mutex_lock(&dev->struct_mutex);
4833                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4834                                   plane->frontbuffer_bit);
4835                 mutex_unlock(&dev->struct_mutex);
4836         }
4837
4838         if (atomic->wait_for_flips)
4839                 intel_crtc_wait_for_pending_flips(&crtc->base);
4840
4841         if (atomic->disable_fbc)
4842                 intel_fbc_disable_crtc(crtc);
4843
4844         if (crtc->atomic.disable_ips)
4845                 hsw_disable_ips(crtc);
4846
4847         if (atomic->pre_disable_primary)
4848                 intel_pre_disable_primary(&crtc->base);
4849
4850         if (atomic->disable_cxsr) {
4851                 crtc->wm.cxsr_allowed = false;
4852                 intel_set_memory_cxsr(dev_priv, false);
4853         }
4854 }
4855
4856 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4857 {
4858         struct drm_device *dev = crtc->dev;
4859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4860         struct drm_plane *p;
4861         int pipe = intel_crtc->pipe;
4862
4863         intel_crtc_dpms_overlay_disable(intel_crtc);
4864
4865         drm_for_each_plane_mask(p, dev, plane_mask)
4866                 to_intel_plane(p)->disable_plane(p, crtc);
4867
4868         /*
4869          * FIXME: Once we grow proper nuclear flip support out of this we need
4870          * to compute the mask of flip planes precisely. For the time being
4871          * consider this a flip to a NULL plane.
4872          */
4873         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4874 }
4875
4876 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4877 {
4878         struct drm_device *dev = crtc->dev;
4879         struct drm_i915_private *dev_priv = dev->dev_private;
4880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4881         struct intel_encoder *encoder;
4882         int pipe = intel_crtc->pipe;
4883
4884         if (WARN_ON(intel_crtc->active))
4885                 return;
4886
4887         if (intel_crtc->config->has_pch_encoder)
4888                 intel_prepare_shared_dpll(intel_crtc);
4889
4890         if (intel_crtc->config->has_dp_encoder)
4891                 intel_dp_set_m_n(intel_crtc, M1_N1);
4892
4893         intel_set_pipe_timings(intel_crtc);
4894
4895         if (intel_crtc->config->has_pch_encoder) {
4896                 intel_cpu_transcoder_set_m_n(intel_crtc,
4897                                      &intel_crtc->config->fdi_m_n, NULL);
4898         }
4899
4900         ironlake_set_pipeconf(crtc);
4901
4902         intel_crtc->active = true;
4903
4904         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4905         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4906
4907         for_each_encoder_on_crtc(dev, crtc, encoder)
4908                 if (encoder->pre_enable)
4909                         encoder->pre_enable(encoder);
4910
4911         if (intel_crtc->config->has_pch_encoder) {
4912                 /* Note: FDI PLL enabling _must_ be done before we enable the
4913                  * cpu pipes, hence this is separate from all the other fdi/pch
4914                  * enabling. */
4915                 ironlake_fdi_pll_enable(intel_crtc);
4916         } else {
4917                 assert_fdi_tx_disabled(dev_priv, pipe);
4918                 assert_fdi_rx_disabled(dev_priv, pipe);
4919         }
4920
4921         ironlake_pfit_enable(intel_crtc);
4922
4923         /*
4924          * On ILK+ LUT must be loaded before the pipe is running but with
4925          * clocks enabled
4926          */
4927         intel_crtc_load_lut(crtc);
4928
4929         intel_update_watermarks(crtc);
4930         intel_enable_pipe(intel_crtc);
4931
4932         if (intel_crtc->config->has_pch_encoder)
4933                 ironlake_pch_enable(crtc);
4934
4935         assert_vblank_disabled(crtc);
4936         drm_crtc_vblank_on(crtc);
4937
4938         for_each_encoder_on_crtc(dev, crtc, encoder)
4939                 encoder->enable(encoder);
4940
4941         if (HAS_PCH_CPT(dev))
4942                 cpt_verify_modeset(dev, intel_crtc->pipe);
4943 }
4944
4945 /* IPS only exists on ULT machines and is tied to pipe A. */
4946 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4947 {
4948         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4949 }
4950
4951 static void haswell_crtc_enable(struct drm_crtc *crtc)
4952 {
4953         struct drm_device *dev = crtc->dev;
4954         struct drm_i915_private *dev_priv = dev->dev_private;
4955         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4956         struct intel_encoder *encoder;
4957         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4958         struct intel_crtc_state *pipe_config =
4959                 to_intel_crtc_state(crtc->state);
4960         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4961
4962         if (WARN_ON(intel_crtc->active))
4963                 return;
4964
4965         if (intel_crtc_to_shared_dpll(intel_crtc))
4966                 intel_enable_shared_dpll(intel_crtc);
4967
4968         if (intel_crtc->config->has_dp_encoder)
4969                 intel_dp_set_m_n(intel_crtc, M1_N1);
4970
4971         intel_set_pipe_timings(intel_crtc);
4972
4973         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4974                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4975                            intel_crtc->config->pixel_multiplier - 1);
4976         }
4977
4978         if (intel_crtc->config->has_pch_encoder) {
4979                 intel_cpu_transcoder_set_m_n(intel_crtc,
4980                                      &intel_crtc->config->fdi_m_n, NULL);
4981         }
4982
4983         haswell_set_pipeconf(crtc);
4984
4985         intel_set_pipe_csc(crtc);
4986
4987         intel_crtc->active = true;
4988
4989         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4990         for_each_encoder_on_crtc(dev, crtc, encoder) {
4991                 if (encoder->pre_pll_enable)
4992                         encoder->pre_pll_enable(encoder);
4993                 if (encoder->pre_enable)
4994                         encoder->pre_enable(encoder);
4995         }
4996
4997         if (intel_crtc->config->has_pch_encoder) {
4998                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4999                                                       true);
5000                 dev_priv->display.fdi_link_train(crtc);
5001         }
5002
5003         if (!is_dsi)
5004                 intel_ddi_enable_pipe_clock(intel_crtc);
5005
5006         if (INTEL_INFO(dev)->gen >= 9)
5007                 skylake_pfit_enable(intel_crtc);
5008         else
5009                 ironlake_pfit_enable(intel_crtc);
5010
5011         /*
5012          * On ILK+ LUT must be loaded before the pipe is running but with
5013          * clocks enabled
5014          */
5015         intel_crtc_load_lut(crtc);
5016
5017         intel_ddi_set_pipe_settings(crtc);
5018         if (!is_dsi)
5019                 intel_ddi_enable_transcoder_func(crtc);
5020
5021         intel_update_watermarks(crtc);
5022         intel_enable_pipe(intel_crtc);
5023
5024         if (intel_crtc->config->has_pch_encoder)
5025                 lpt_pch_enable(crtc);
5026
5027         if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5028                 intel_ddi_set_vc_payload_alloc(crtc, true);
5029
5030         assert_vblank_disabled(crtc);
5031         drm_crtc_vblank_on(crtc);
5032
5033         for_each_encoder_on_crtc(dev, crtc, encoder) {
5034                 encoder->enable(encoder);
5035                 intel_opregion_notify_encoder(encoder, true);
5036         }
5037
5038         /* If we change the relative order between pipe/planes enabling, we need
5039          * to change the workaround. */
5040         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5041         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5042                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5043                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5044         }
5045 }
5046
5047 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5048 {
5049         struct drm_device *dev = crtc->base.dev;
5050         struct drm_i915_private *dev_priv = dev->dev_private;
5051         int pipe = crtc->pipe;
5052
5053         /* To avoid upsetting the power well on haswell only disable the pfit if
5054          * it's in use. The hw state code will make sure we get this right. */
5055         if (force || crtc->config->pch_pfit.enabled) {
5056                 I915_WRITE(PF_CTL(pipe), 0);
5057                 I915_WRITE(PF_WIN_POS(pipe), 0);
5058                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5059         }
5060 }
5061
5062 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5063 {
5064         struct drm_device *dev = crtc->dev;
5065         struct drm_i915_private *dev_priv = dev->dev_private;
5066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5067         struct intel_encoder *encoder;
5068         int pipe = intel_crtc->pipe;
5069         u32 reg, temp;
5070
5071         for_each_encoder_on_crtc(dev, crtc, encoder)
5072                 encoder->disable(encoder);
5073
5074         drm_crtc_vblank_off(crtc);
5075         assert_vblank_disabled(crtc);
5076
5077         if (intel_crtc->config->has_pch_encoder)
5078                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5079
5080         intel_disable_pipe(intel_crtc);
5081
5082         ironlake_pfit_disable(intel_crtc, false);
5083
5084         if (intel_crtc->config->has_pch_encoder)
5085                 ironlake_fdi_disable(crtc);
5086
5087         for_each_encoder_on_crtc(dev, crtc, encoder)
5088                 if (encoder->post_disable)
5089                         encoder->post_disable(encoder);
5090
5091         if (intel_crtc->config->has_pch_encoder) {
5092                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5093
5094                 if (HAS_PCH_CPT(dev)) {
5095                         /* disable TRANS_DP_CTL */
5096                         reg = TRANS_DP_CTL(pipe);
5097                         temp = I915_READ(reg);
5098                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5099                                   TRANS_DP_PORT_SEL_MASK);
5100                         temp |= TRANS_DP_PORT_SEL_NONE;
5101                         I915_WRITE(reg, temp);
5102
5103                         /* disable DPLL_SEL */
5104                         temp = I915_READ(PCH_DPLL_SEL);
5105                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5106                         I915_WRITE(PCH_DPLL_SEL, temp);
5107                 }
5108
5109                 ironlake_fdi_pll_disable(intel_crtc);
5110         }
5111 }
5112
5113 static void haswell_crtc_disable(struct drm_crtc *crtc)
5114 {
5115         struct drm_device *dev = crtc->dev;
5116         struct drm_i915_private *dev_priv = dev->dev_private;
5117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5118         struct intel_encoder *encoder;
5119         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5120         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5121
5122         for_each_encoder_on_crtc(dev, crtc, encoder) {
5123                 intel_opregion_notify_encoder(encoder, false);
5124                 encoder->disable(encoder);
5125         }
5126
5127         drm_crtc_vblank_off(crtc);
5128         assert_vblank_disabled(crtc);
5129
5130         if (intel_crtc->config->has_pch_encoder)
5131                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5132                                                       false);
5133         intel_disable_pipe(intel_crtc);
5134
5135         if (intel_crtc->config->dp_encoder_is_mst)
5136                 intel_ddi_set_vc_payload_alloc(crtc, false);
5137
5138         if (!is_dsi)
5139                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5140
5141         if (INTEL_INFO(dev)->gen >= 9)
5142                 skylake_scaler_disable(intel_crtc);
5143         else
5144                 ironlake_pfit_disable(intel_crtc, false);
5145
5146         if (!is_dsi)
5147                 intel_ddi_disable_pipe_clock(intel_crtc);
5148
5149         if (intel_crtc->config->has_pch_encoder) {
5150                 lpt_disable_pch_transcoder(dev_priv);
5151                 intel_ddi_fdi_disable(crtc);
5152         }
5153
5154         for_each_encoder_on_crtc(dev, crtc, encoder)
5155                 if (encoder->post_disable)
5156                         encoder->post_disable(encoder);
5157 }
5158
5159 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5160 {
5161         struct drm_device *dev = crtc->base.dev;
5162         struct drm_i915_private *dev_priv = dev->dev_private;
5163         struct intel_crtc_state *pipe_config = crtc->config;
5164
5165         if (!pipe_config->gmch_pfit.control)
5166                 return;
5167
5168         /*
5169          * The panel fitter should only be adjusted whilst the pipe is disabled,
5170          * according to register description and PRM.
5171          */
5172         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5173         assert_pipe_disabled(dev_priv, crtc->pipe);
5174
5175         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5176         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5177
5178         /* Border color in case we don't scale up to the full screen. Black by
5179          * default, change to something else for debugging. */
5180         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5181 }
5182
5183 static enum intel_display_power_domain port_to_power_domain(enum port port)
5184 {
5185         switch (port) {
5186         case PORT_A:
5187                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5188         case PORT_B:
5189                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5190         case PORT_C:
5191                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5192         case PORT_D:
5193                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5194         case PORT_E:
5195                 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5196         default:
5197                 WARN_ON_ONCE(1);
5198                 return POWER_DOMAIN_PORT_OTHER;
5199         }
5200 }
5201
5202 #define for_each_power_domain(domain, mask)                             \
5203         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5204                 if ((1 << (domain)) & (mask))
5205
5206 enum intel_display_power_domain
5207 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5208 {
5209         struct drm_device *dev = intel_encoder->base.dev;
5210         struct intel_digital_port *intel_dig_port;
5211
5212         switch (intel_encoder->type) {
5213         case INTEL_OUTPUT_UNKNOWN:
5214                 /* Only DDI platforms should ever use this output type */
5215                 WARN_ON_ONCE(!HAS_DDI(dev));
5216         case INTEL_OUTPUT_DISPLAYPORT:
5217         case INTEL_OUTPUT_HDMI:
5218         case INTEL_OUTPUT_EDP:
5219                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5220                 return port_to_power_domain(intel_dig_port->port);
5221         case INTEL_OUTPUT_DP_MST:
5222                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5223                 return port_to_power_domain(intel_dig_port->port);
5224         case INTEL_OUTPUT_ANALOG:
5225                 return POWER_DOMAIN_PORT_CRT;
5226         case INTEL_OUTPUT_DSI:
5227                 return POWER_DOMAIN_PORT_DSI;
5228         default:
5229                 return POWER_DOMAIN_PORT_OTHER;
5230         }
5231 }
5232
5233 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5234 {
5235         struct drm_device *dev = crtc->dev;
5236         struct intel_encoder *intel_encoder;
5237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238         enum pipe pipe = intel_crtc->pipe;
5239         unsigned long mask;
5240         enum transcoder transcoder;
5241
5242         if (!crtc->state->active)
5243                 return 0;
5244
5245         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5246
5247         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5248         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5249         if (intel_crtc->config->pch_pfit.enabled ||
5250             intel_crtc->config->pch_pfit.force_thru)
5251                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5252
5253         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5254                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5255
5256         return mask;
5257 }
5258
5259 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5260 {
5261         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5263         enum intel_display_power_domain domain;
5264         unsigned long domains, new_domains, old_domains;
5265
5266         old_domains = intel_crtc->enabled_power_domains;
5267         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5268
5269         domains = new_domains & ~old_domains;
5270
5271         for_each_power_domain(domain, domains)
5272                 intel_display_power_get(dev_priv, domain);
5273
5274         return old_domains & ~new_domains;
5275 }
5276
5277 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5278                                       unsigned long domains)
5279 {
5280         enum intel_display_power_domain domain;
5281
5282         for_each_power_domain(domain, domains)
5283                 intel_display_power_put(dev_priv, domain);
5284 }
5285
5286 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5287 {
5288         struct drm_device *dev = state->dev;
5289         struct drm_i915_private *dev_priv = dev->dev_private;
5290         unsigned long put_domains[I915_MAX_PIPES] = {};
5291         struct drm_crtc_state *crtc_state;
5292         struct drm_crtc *crtc;
5293         int i;
5294
5295         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5296                 if (needs_modeset(crtc->state))
5297                         put_domains[to_intel_crtc(crtc)->pipe] =
5298                                 modeset_get_crtc_power_domains(crtc);
5299         }
5300
5301         if (dev_priv->display.modeset_commit_cdclk) {
5302                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5303
5304                 if (cdclk != dev_priv->cdclk_freq &&
5305                     !WARN_ON(!state->allow_modeset))
5306                         dev_priv->display.modeset_commit_cdclk(state);
5307         }
5308
5309         for (i = 0; i < I915_MAX_PIPES; i++)
5310                 if (put_domains[i])
5311                         modeset_put_power_domains(dev_priv, put_domains[i]);
5312 }
5313
5314 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5315 {
5316         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5317
5318         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5319             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5320                 return max_cdclk_freq;
5321         else if (IS_CHERRYVIEW(dev_priv))
5322                 return max_cdclk_freq*95/100;
5323         else if (INTEL_INFO(dev_priv)->gen < 4)
5324                 return 2*max_cdclk_freq*90/100;
5325         else
5326                 return max_cdclk_freq*90/100;
5327 }
5328
5329 static void intel_update_max_cdclk(struct drm_device *dev)
5330 {
5331         struct drm_i915_private *dev_priv = dev->dev_private;
5332
5333         if (IS_SKYLAKE(dev)) {
5334                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5335
5336                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5337                         dev_priv->max_cdclk_freq = 675000;
5338                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5339                         dev_priv->max_cdclk_freq = 540000;
5340                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5341                         dev_priv->max_cdclk_freq = 450000;
5342                 else
5343                         dev_priv->max_cdclk_freq = 337500;
5344         } else if (IS_BROADWELL(dev))  {
5345                 /*
5346                  * FIXME with extra cooling we can allow
5347                  * 540 MHz for ULX and 675 Mhz for ULT.
5348                  * How can we know if extra cooling is
5349                  * available? PCI ID, VTB, something else?
5350                  */
5351                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5352                         dev_priv->max_cdclk_freq = 450000;
5353                 else if (IS_BDW_ULX(dev))
5354                         dev_priv->max_cdclk_freq = 450000;
5355                 else if (IS_BDW_ULT(dev))
5356                         dev_priv->max_cdclk_freq = 540000;
5357                 else
5358                         dev_priv->max_cdclk_freq = 675000;
5359         } else if (IS_CHERRYVIEW(dev)) {
5360                 dev_priv->max_cdclk_freq = 320000;
5361         } else if (IS_VALLEYVIEW(dev)) {
5362                 dev_priv->max_cdclk_freq = 400000;
5363         } else {
5364                 /* otherwise assume cdclk is fixed */
5365                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5366         }
5367
5368         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5369
5370         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5371                          dev_priv->max_cdclk_freq);
5372
5373         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5374                          dev_priv->max_dotclk_freq);
5375 }
5376
5377 static void intel_update_cdclk(struct drm_device *dev)
5378 {
5379         struct drm_i915_private *dev_priv = dev->dev_private;
5380
5381         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5382         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5383                          dev_priv->cdclk_freq);
5384
5385         /*
5386          * Program the gmbus_freq based on the cdclk frequency.
5387          * BSpec erroneously claims we should aim for 4MHz, but
5388          * in fact 1MHz is the correct frequency.
5389          */
5390         if (IS_VALLEYVIEW(dev)) {
5391                 /*
5392                  * Program the gmbus_freq based on the cdclk frequency.
5393                  * BSpec erroneously claims we should aim for 4MHz, but
5394                  * in fact 1MHz is the correct frequency.
5395                  */
5396                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5397         }
5398
5399         if (dev_priv->max_cdclk_freq == 0)
5400                 intel_update_max_cdclk(dev);
5401 }
5402
5403 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5404 {
5405         struct drm_i915_private *dev_priv = dev->dev_private;
5406         uint32_t divider;
5407         uint32_t ratio;
5408         uint32_t current_freq;
5409         int ret;
5410
5411         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5412         switch (frequency) {
5413         case 144000:
5414                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5415                 ratio = BXT_DE_PLL_RATIO(60);
5416                 break;
5417         case 288000:
5418                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5419                 ratio = BXT_DE_PLL_RATIO(60);
5420                 break;
5421         case 384000:
5422                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5423                 ratio = BXT_DE_PLL_RATIO(60);
5424                 break;
5425         case 576000:
5426                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5427                 ratio = BXT_DE_PLL_RATIO(60);
5428                 break;
5429         case 624000:
5430                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5431                 ratio = BXT_DE_PLL_RATIO(65);
5432                 break;
5433         case 19200:
5434                 /*
5435                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5436                  * to suppress GCC warning.
5437                  */
5438                 ratio = 0;
5439                 divider = 0;
5440                 break;
5441         default:
5442                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5443
5444                 return;
5445         }
5446
5447         mutex_lock(&dev_priv->rps.hw_lock);
5448         /* Inform power controller of upcoming frequency change */
5449         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5450                                       0x80000000);
5451         mutex_unlock(&dev_priv->rps.hw_lock);
5452
5453         if (ret) {
5454                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5455                           ret, frequency);
5456                 return;
5457         }
5458
5459         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5460         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5461         current_freq = current_freq * 500 + 1000;
5462
5463         /*
5464          * DE PLL has to be disabled when
5465          * - setting to 19.2MHz (bypass, PLL isn't used)
5466          * - before setting to 624MHz (PLL needs toggling)
5467          * - before setting to any frequency from 624MHz (PLL needs toggling)
5468          */
5469         if (frequency == 19200 || frequency == 624000 ||
5470             current_freq == 624000) {
5471                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5472                 /* Timeout 200us */
5473                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5474                              1))
5475                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5476         }
5477
5478         if (frequency != 19200) {
5479                 uint32_t val;
5480
5481                 val = I915_READ(BXT_DE_PLL_CTL);
5482                 val &= ~BXT_DE_PLL_RATIO_MASK;
5483                 val |= ratio;
5484                 I915_WRITE(BXT_DE_PLL_CTL, val);
5485
5486                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5487                 /* Timeout 200us */
5488                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5489                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5490
5491                 val = I915_READ(CDCLK_CTL);
5492                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5493                 val |= divider;
5494                 /*
5495                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5496                  * enable otherwise.
5497                  */
5498                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5499                 if (frequency >= 500000)
5500                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5501
5502                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5503                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5504                 val |= (frequency - 1000) / 500;
5505                 I915_WRITE(CDCLK_CTL, val);
5506         }
5507
5508         mutex_lock(&dev_priv->rps.hw_lock);
5509         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5510                                       DIV_ROUND_UP(frequency, 25000));
5511         mutex_unlock(&dev_priv->rps.hw_lock);
5512
5513         if (ret) {
5514                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5515                           ret, frequency);
5516                 return;
5517         }
5518
5519         intel_update_cdclk(dev);
5520 }
5521
5522 void broxton_init_cdclk(struct drm_device *dev)
5523 {
5524         struct drm_i915_private *dev_priv = dev->dev_private;
5525         uint32_t val;
5526
5527         /*
5528          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5529          * or else the reset will hang because there is no PCH to respond.
5530          * Move the handshake programming to initialization sequence.
5531          * Previously was left up to BIOS.
5532          */
5533         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5534         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5535         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5536
5537         /* Enable PG1 for cdclk */
5538         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5539
5540         /* check if cd clock is enabled */
5541         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5542                 DRM_DEBUG_KMS("Display already initialized\n");
5543                 return;
5544         }
5545
5546         /*
5547          * FIXME:
5548          * - The initial CDCLK needs to be read from VBT.
5549          *   Need to make this change after VBT has changes for BXT.
5550          * - check if setting the max (or any) cdclk freq is really necessary
5551          *   here, it belongs to modeset time
5552          */
5553         broxton_set_cdclk(dev, 624000);
5554
5555         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5556         POSTING_READ(DBUF_CTL);
5557
5558         udelay(10);
5559
5560         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5561                 DRM_ERROR("DBuf power enable timeout!\n");
5562 }
5563
5564 void broxton_uninit_cdclk(struct drm_device *dev)
5565 {
5566         struct drm_i915_private *dev_priv = dev->dev_private;
5567
5568         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5569         POSTING_READ(DBUF_CTL);
5570
5571         udelay(10);
5572
5573         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5574                 DRM_ERROR("DBuf power disable timeout!\n");
5575
5576         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5577         broxton_set_cdclk(dev, 19200);
5578
5579         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5580 }
5581
5582 static const struct skl_cdclk_entry {
5583         unsigned int freq;
5584         unsigned int vco;
5585 } skl_cdclk_frequencies[] = {
5586         { .freq = 308570, .vco = 8640 },
5587         { .freq = 337500, .vco = 8100 },
5588         { .freq = 432000, .vco = 8640 },
5589         { .freq = 450000, .vco = 8100 },
5590         { .freq = 540000, .vco = 8100 },
5591         { .freq = 617140, .vco = 8640 },
5592         { .freq = 675000, .vco = 8100 },
5593 };
5594
5595 static unsigned int skl_cdclk_decimal(unsigned int freq)
5596 {
5597         return (freq - 1000) / 500;
5598 }
5599
5600 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5601 {
5602         unsigned int i;
5603
5604         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5605                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5606
5607                 if (e->freq == freq)
5608                         return e->vco;
5609         }
5610
5611         return 8100;
5612 }
5613
5614 static void
5615 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5616 {
5617         unsigned int min_freq;
5618         u32 val;
5619
5620         /* select the minimum CDCLK before enabling DPLL 0 */
5621         val = I915_READ(CDCLK_CTL);
5622         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5623         val |= CDCLK_FREQ_337_308;
5624
5625         if (required_vco == 8640)
5626                 min_freq = 308570;
5627         else
5628                 min_freq = 337500;
5629
5630         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5631
5632         I915_WRITE(CDCLK_CTL, val);
5633         POSTING_READ(CDCLK_CTL);
5634
5635         /*
5636          * We always enable DPLL0 with the lowest link rate possible, but still
5637          * taking into account the VCO required to operate the eDP panel at the
5638          * desired frequency. The usual DP link rates operate with a VCO of
5639          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5640          * The modeset code is responsible for the selection of the exact link
5641          * rate later on, with the constraint of choosing a frequency that
5642          * works with required_vco.
5643          */
5644         val = I915_READ(DPLL_CTRL1);
5645
5646         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5647                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5648         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5649         if (required_vco == 8640)
5650                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5651                                             SKL_DPLL0);
5652         else
5653                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5654                                             SKL_DPLL0);
5655
5656         I915_WRITE(DPLL_CTRL1, val);
5657         POSTING_READ(DPLL_CTRL1);
5658
5659         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5660
5661         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5662                 DRM_ERROR("DPLL0 not locked\n");
5663 }
5664
5665 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5666 {
5667         int ret;
5668         u32 val;
5669
5670         /* inform PCU we want to change CDCLK */
5671         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5672         mutex_lock(&dev_priv->rps.hw_lock);
5673         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5674         mutex_unlock(&dev_priv->rps.hw_lock);
5675
5676         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5677 }
5678
5679 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5680 {
5681         unsigned int i;
5682
5683         for (i = 0; i < 15; i++) {
5684                 if (skl_cdclk_pcu_ready(dev_priv))
5685                         return true;
5686                 udelay(10);
5687         }
5688
5689         return false;
5690 }
5691
5692 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5693 {
5694         struct drm_device *dev = dev_priv->dev;
5695         u32 freq_select, pcu_ack;
5696
5697         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5698
5699         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5700                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5701                 return;
5702         }
5703
5704         /* set CDCLK_CTL */
5705         switch(freq) {
5706         case 450000:
5707         case 432000:
5708                 freq_select = CDCLK_FREQ_450_432;
5709                 pcu_ack = 1;
5710                 break;
5711         case 540000:
5712                 freq_select = CDCLK_FREQ_540;
5713                 pcu_ack = 2;
5714                 break;
5715         case 308570:
5716         case 337500:
5717         default:
5718                 freq_select = CDCLK_FREQ_337_308;
5719                 pcu_ack = 0;
5720                 break;
5721         case 617140:
5722         case 675000:
5723                 freq_select = CDCLK_FREQ_675_617;
5724                 pcu_ack = 3;
5725                 break;
5726         }
5727
5728         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5729         POSTING_READ(CDCLK_CTL);
5730
5731         /* inform PCU of the change */
5732         mutex_lock(&dev_priv->rps.hw_lock);
5733         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5734         mutex_unlock(&dev_priv->rps.hw_lock);
5735
5736         intel_update_cdclk(dev);
5737 }
5738
5739 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5740 {
5741         /* disable DBUF power */
5742         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5743         POSTING_READ(DBUF_CTL);
5744
5745         udelay(10);
5746
5747         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5748                 DRM_ERROR("DBuf power disable timeout\n");
5749
5750         /*
5751          * DMC assumes ownership of LCPLL and will get confused if we touch it.
5752          */
5753         if (dev_priv->csr.dmc_payload) {
5754                 /* disable DPLL0 */
5755                 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5756                                         ~LCPLL_PLL_ENABLE);
5757                 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5758                         DRM_ERROR("Couldn't disable DPLL0\n");
5759         }
5760
5761         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5762 }
5763
5764 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5765 {
5766         u32 val;
5767         unsigned int required_vco;
5768
5769         /* enable PCH reset handshake */
5770         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5771         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5772
5773         /* enable PG1 and Misc I/O */
5774         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5775
5776         /* DPLL0 not enabled (happens on early BIOS versions) */
5777         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5778                 /* enable DPLL0 */
5779                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5780                 skl_dpll0_enable(dev_priv, required_vco);
5781         }
5782
5783         /* set CDCLK to the frequency the BIOS chose */
5784         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5785
5786         /* enable DBUF power */
5787         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5788         POSTING_READ(DBUF_CTL);
5789
5790         udelay(10);
5791
5792         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5793                 DRM_ERROR("DBuf power enable timeout\n");
5794 }
5795
5796 /* Adjust CDclk dividers to allow high res or save power if possible */
5797 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5798 {
5799         struct drm_i915_private *dev_priv = dev->dev_private;
5800         u32 val, cmd;
5801
5802         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5803                                         != dev_priv->cdclk_freq);
5804
5805         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5806                 cmd = 2;
5807         else if (cdclk == 266667)
5808                 cmd = 1;
5809         else
5810                 cmd = 0;
5811
5812         mutex_lock(&dev_priv->rps.hw_lock);
5813         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5814         val &= ~DSPFREQGUAR_MASK;
5815         val |= (cmd << DSPFREQGUAR_SHIFT);
5816         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5817         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5818                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5819                      50)) {
5820                 DRM_ERROR("timed out waiting for CDclk change\n");
5821         }
5822         mutex_unlock(&dev_priv->rps.hw_lock);
5823
5824         mutex_lock(&dev_priv->sb_lock);
5825
5826         if (cdclk == 400000) {
5827                 u32 divider;
5828
5829                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5830
5831                 /* adjust cdclk divider */
5832                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5833                 val &= ~CCK_FREQUENCY_VALUES;
5834                 val |= divider;
5835                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5836
5837                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5838                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5839                              50))
5840                         DRM_ERROR("timed out waiting for CDclk change\n");
5841         }
5842
5843         /* adjust self-refresh exit latency value */
5844         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5845         val &= ~0x7f;
5846
5847         /*
5848          * For high bandwidth configs, we set a higher latency in the bunit
5849          * so that the core display fetch happens in time to avoid underruns.
5850          */
5851         if (cdclk == 400000)
5852                 val |= 4500 / 250; /* 4.5 usec */
5853         else
5854                 val |= 3000 / 250; /* 3.0 usec */
5855         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5856
5857         mutex_unlock(&dev_priv->sb_lock);
5858
5859         intel_update_cdclk(dev);
5860 }
5861
5862 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5863 {
5864         struct drm_i915_private *dev_priv = dev->dev_private;
5865         u32 val, cmd;
5866
5867         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5868                                                 != dev_priv->cdclk_freq);
5869
5870         switch (cdclk) {
5871         case 333333:
5872         case 320000:
5873         case 266667:
5874         case 200000:
5875                 break;
5876         default:
5877                 MISSING_CASE(cdclk);
5878                 return;
5879         }
5880
5881         /*
5882          * Specs are full of misinformation, but testing on actual
5883          * hardware has shown that we just need to write the desired
5884          * CCK divider into the Punit register.
5885          */
5886         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5887
5888         mutex_lock(&dev_priv->rps.hw_lock);
5889         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5890         val &= ~DSPFREQGUAR_MASK_CHV;
5891         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5892         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5893         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5894                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5895                      50)) {
5896                 DRM_ERROR("timed out waiting for CDclk change\n");
5897         }
5898         mutex_unlock(&dev_priv->rps.hw_lock);
5899
5900         intel_update_cdclk(dev);
5901 }
5902
5903 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5904                                  int max_pixclk)
5905 {
5906         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5907         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5908
5909         /*
5910          * Really only a few cases to deal with, as only 4 CDclks are supported:
5911          *   200MHz
5912          *   267MHz
5913          *   320/333MHz (depends on HPLL freq)
5914          *   400MHz (VLV only)
5915          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5916          * of the lower bin and adjust if needed.
5917          *
5918          * We seem to get an unstable or solid color picture at 200MHz.
5919          * Not sure what's wrong. For now use 200MHz only when all pipes
5920          * are off.
5921          */
5922         if (!IS_CHERRYVIEW(dev_priv) &&
5923             max_pixclk > freq_320*limit/100)
5924                 return 400000;
5925         else if (max_pixclk > 266667*limit/100)
5926                 return freq_320;
5927         else if (max_pixclk > 0)
5928                 return 266667;
5929         else
5930                 return 200000;
5931 }
5932
5933 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5934                               int max_pixclk)
5935 {
5936         /*
5937          * FIXME:
5938          * - remove the guardband, it's not needed on BXT
5939          * - set 19.2MHz bypass frequency if there are no active pipes
5940          */
5941         if (max_pixclk > 576000*9/10)
5942                 return 624000;
5943         else if (max_pixclk > 384000*9/10)
5944                 return 576000;
5945         else if (max_pixclk > 288000*9/10)
5946                 return 384000;
5947         else if (max_pixclk > 144000*9/10)
5948                 return 288000;
5949         else
5950                 return 144000;
5951 }
5952
5953 /* Compute the max pixel clock for new configuration. Uses atomic state if
5954  * that's non-NULL, look at current state otherwise. */
5955 static int intel_mode_max_pixclk(struct drm_device *dev,
5956                                  struct drm_atomic_state *state)
5957 {
5958         struct intel_crtc *intel_crtc;
5959         struct intel_crtc_state *crtc_state;
5960         int max_pixclk = 0;
5961
5962         for_each_intel_crtc(dev, intel_crtc) {
5963                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5964                 if (IS_ERR(crtc_state))
5965                         return PTR_ERR(crtc_state);
5966
5967                 if (!crtc_state->base.enable)
5968                         continue;
5969
5970                 max_pixclk = max(max_pixclk,
5971                                  crtc_state->base.adjusted_mode.crtc_clock);
5972         }
5973
5974         return max_pixclk;
5975 }
5976
5977 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5978 {
5979         struct drm_device *dev = state->dev;
5980         struct drm_i915_private *dev_priv = dev->dev_private;
5981         int max_pixclk = intel_mode_max_pixclk(dev, state);
5982
5983         if (max_pixclk < 0)
5984                 return max_pixclk;
5985
5986         to_intel_atomic_state(state)->cdclk =
5987                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5988
5989         return 0;
5990 }
5991
5992 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5993 {
5994         struct drm_device *dev = state->dev;
5995         struct drm_i915_private *dev_priv = dev->dev_private;
5996         int max_pixclk = intel_mode_max_pixclk(dev, state);
5997
5998         if (max_pixclk < 0)
5999                 return max_pixclk;
6000
6001         to_intel_atomic_state(state)->cdclk =
6002                 broxton_calc_cdclk(dev_priv, max_pixclk);
6003
6004         return 0;
6005 }
6006
6007 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6008 {
6009         unsigned int credits, default_credits;
6010
6011         if (IS_CHERRYVIEW(dev_priv))
6012                 default_credits = PFI_CREDIT(12);
6013         else
6014                 default_credits = PFI_CREDIT(8);
6015
6016         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6017                 /* CHV suggested value is 31 or 63 */
6018                 if (IS_CHERRYVIEW(dev_priv))
6019                         credits = PFI_CREDIT_63;
6020                 else
6021                         credits = PFI_CREDIT(15);
6022         } else {
6023                 credits = default_credits;
6024         }
6025
6026         /*
6027          * WA - write default credits before re-programming
6028          * FIXME: should we also set the resend bit here?
6029          */
6030         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6031                    default_credits);
6032
6033         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6034                    credits | PFI_CREDIT_RESEND);
6035
6036         /*
6037          * FIXME is this guaranteed to clear
6038          * immediately or should we poll for it?
6039          */
6040         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6041 }
6042
6043 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6044 {
6045         struct drm_device *dev = old_state->dev;
6046         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6047         struct drm_i915_private *dev_priv = dev->dev_private;
6048
6049         /*
6050          * FIXME: We can end up here with all power domains off, yet
6051          * with a CDCLK frequency other than the minimum. To account
6052          * for this take the PIPE-A power domain, which covers the HW
6053          * blocks needed for the following programming. This can be
6054          * removed once it's guaranteed that we get here either with
6055          * the minimum CDCLK set, or the required power domains
6056          * enabled.
6057          */
6058         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6059
6060         if (IS_CHERRYVIEW(dev))
6061                 cherryview_set_cdclk(dev, req_cdclk);
6062         else
6063                 valleyview_set_cdclk(dev, req_cdclk);
6064
6065         vlv_program_pfi_credits(dev_priv);
6066
6067         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6068 }
6069
6070 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6071 {
6072         struct drm_device *dev = crtc->dev;
6073         struct drm_i915_private *dev_priv = to_i915(dev);
6074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6075         struct intel_encoder *encoder;
6076         int pipe = intel_crtc->pipe;
6077         bool is_dsi;
6078
6079         if (WARN_ON(intel_crtc->active))
6080                 return;
6081
6082         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6083
6084         if (intel_crtc->config->has_dp_encoder)
6085                 intel_dp_set_m_n(intel_crtc, M1_N1);
6086
6087         intel_set_pipe_timings(intel_crtc);
6088
6089         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6090                 struct drm_i915_private *dev_priv = dev->dev_private;
6091
6092                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6093                 I915_WRITE(CHV_CANVAS(pipe), 0);
6094         }
6095
6096         i9xx_set_pipeconf(intel_crtc);
6097
6098         intel_crtc->active = true;
6099
6100         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6101
6102         for_each_encoder_on_crtc(dev, crtc, encoder)
6103                 if (encoder->pre_pll_enable)
6104                         encoder->pre_pll_enable(encoder);
6105
6106         if (!is_dsi) {
6107                 if (IS_CHERRYVIEW(dev)) {
6108                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6109                         chv_enable_pll(intel_crtc, intel_crtc->config);
6110                 } else {
6111                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6112                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6113                 }
6114         }
6115
6116         for_each_encoder_on_crtc(dev, crtc, encoder)
6117                 if (encoder->pre_enable)
6118                         encoder->pre_enable(encoder);
6119
6120         i9xx_pfit_enable(intel_crtc);
6121
6122         intel_crtc_load_lut(crtc);
6123
6124         intel_enable_pipe(intel_crtc);
6125
6126         assert_vblank_disabled(crtc);
6127         drm_crtc_vblank_on(crtc);
6128
6129         for_each_encoder_on_crtc(dev, crtc, encoder)
6130                 encoder->enable(encoder);
6131 }
6132
6133 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6134 {
6135         struct drm_device *dev = crtc->base.dev;
6136         struct drm_i915_private *dev_priv = dev->dev_private;
6137
6138         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6139         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6140 }
6141
6142 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6143 {
6144         struct drm_device *dev = crtc->dev;
6145         struct drm_i915_private *dev_priv = to_i915(dev);
6146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6147         struct intel_encoder *encoder;
6148         int pipe = intel_crtc->pipe;
6149
6150         if (WARN_ON(intel_crtc->active))
6151                 return;
6152
6153         i9xx_set_pll_dividers(intel_crtc);
6154
6155         if (intel_crtc->config->has_dp_encoder)
6156                 intel_dp_set_m_n(intel_crtc, M1_N1);
6157
6158         intel_set_pipe_timings(intel_crtc);
6159
6160         i9xx_set_pipeconf(intel_crtc);
6161
6162         intel_crtc->active = true;
6163
6164         if (!IS_GEN2(dev))
6165                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6166
6167         for_each_encoder_on_crtc(dev, crtc, encoder)
6168                 if (encoder->pre_enable)
6169                         encoder->pre_enable(encoder);
6170
6171         i9xx_enable_pll(intel_crtc);
6172
6173         i9xx_pfit_enable(intel_crtc);
6174
6175         intel_crtc_load_lut(crtc);
6176
6177         intel_update_watermarks(crtc);
6178         intel_enable_pipe(intel_crtc);
6179
6180         assert_vblank_disabled(crtc);
6181         drm_crtc_vblank_on(crtc);
6182
6183         for_each_encoder_on_crtc(dev, crtc, encoder)
6184                 encoder->enable(encoder);
6185 }
6186
6187 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6188 {
6189         struct drm_device *dev = crtc->base.dev;
6190         struct drm_i915_private *dev_priv = dev->dev_private;
6191
6192         if (!crtc->config->gmch_pfit.control)
6193                 return;
6194
6195         assert_pipe_disabled(dev_priv, crtc->pipe);
6196
6197         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6198                          I915_READ(PFIT_CONTROL));
6199         I915_WRITE(PFIT_CONTROL, 0);
6200 }
6201
6202 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6203 {
6204         struct drm_device *dev = crtc->dev;
6205         struct drm_i915_private *dev_priv = dev->dev_private;
6206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6207         struct intel_encoder *encoder;
6208         int pipe = intel_crtc->pipe;
6209
6210         /*
6211          * On gen2 planes are double buffered but the pipe isn't, so we must
6212          * wait for planes to fully turn off before disabling the pipe.
6213          * We also need to wait on all gmch platforms because of the
6214          * self-refresh mode constraint explained above.
6215          */
6216         intel_wait_for_vblank(dev, pipe);
6217
6218         for_each_encoder_on_crtc(dev, crtc, encoder)
6219                 encoder->disable(encoder);
6220
6221         drm_crtc_vblank_off(crtc);
6222         assert_vblank_disabled(crtc);
6223
6224         intel_disable_pipe(intel_crtc);
6225
6226         i9xx_pfit_disable(intel_crtc);
6227
6228         for_each_encoder_on_crtc(dev, crtc, encoder)
6229                 if (encoder->post_disable)
6230                         encoder->post_disable(encoder);
6231
6232         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6233                 if (IS_CHERRYVIEW(dev))
6234                         chv_disable_pll(dev_priv, pipe);
6235                 else if (IS_VALLEYVIEW(dev))
6236                         vlv_disable_pll(dev_priv, pipe);
6237                 else
6238                         i9xx_disable_pll(intel_crtc);
6239         }
6240
6241         for_each_encoder_on_crtc(dev, crtc, encoder)
6242                 if (encoder->post_pll_disable)
6243                         encoder->post_pll_disable(encoder);
6244
6245         if (!IS_GEN2(dev))
6246                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6247 }
6248
6249 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6250 {
6251         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6252         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6253         enum intel_display_power_domain domain;
6254         unsigned long domains;
6255
6256         if (!intel_crtc->active)
6257                 return;
6258
6259         if (to_intel_plane_state(crtc->primary->state)->visible) {
6260                 intel_crtc_wait_for_pending_flips(crtc);
6261                 intel_pre_disable_primary(crtc);
6262         }
6263
6264         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6265         dev_priv->display.crtc_disable(crtc);
6266         intel_crtc->active = false;
6267         intel_update_watermarks(crtc);
6268         intel_disable_shared_dpll(intel_crtc);
6269
6270         domains = intel_crtc->enabled_power_domains;
6271         for_each_power_domain(domain, domains)
6272                 intel_display_power_put(dev_priv, domain);
6273         intel_crtc->enabled_power_domains = 0;
6274 }
6275
6276 /*
6277  * turn all crtc's off, but do not adjust state
6278  * This has to be paired with a call to intel_modeset_setup_hw_state.
6279  */
6280 int intel_display_suspend(struct drm_device *dev)
6281 {
6282         struct drm_mode_config *config = &dev->mode_config;
6283         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6284         struct drm_atomic_state *state;
6285         struct drm_crtc *crtc;
6286         unsigned crtc_mask = 0;
6287         int ret = 0;
6288
6289         if (WARN_ON(!ctx))
6290                 return 0;
6291
6292         lockdep_assert_held(&ctx->ww_ctx);
6293         state = drm_atomic_state_alloc(dev);
6294         if (WARN_ON(!state))
6295                 return -ENOMEM;
6296
6297         state->acquire_ctx = ctx;
6298         state->allow_modeset = true;
6299
6300         for_each_crtc(dev, crtc) {
6301                 struct drm_crtc_state *crtc_state =
6302                         drm_atomic_get_crtc_state(state, crtc);
6303
6304                 ret = PTR_ERR_OR_ZERO(crtc_state);
6305                 if (ret)
6306                         goto free;
6307
6308                 if (!crtc_state->active)
6309                         continue;
6310
6311                 crtc_state->active = false;
6312                 crtc_mask |= 1 << drm_crtc_index(crtc);
6313         }
6314
6315         if (crtc_mask) {
6316                 ret = drm_atomic_commit(state);
6317
6318                 if (!ret) {
6319                         for_each_crtc(dev, crtc)
6320                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6321                                         crtc->state->active = true;
6322
6323                         return ret;
6324                 }
6325         }
6326
6327 free:
6328         if (ret)
6329                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6330         drm_atomic_state_free(state);
6331         return ret;
6332 }
6333
6334 void intel_encoder_destroy(struct drm_encoder *encoder)
6335 {
6336         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6337
6338         drm_encoder_cleanup(encoder);
6339         kfree(intel_encoder);
6340 }
6341
6342 /* Cross check the actual hw state with our own modeset state tracking (and it's
6343  * internal consistency). */
6344 static void intel_connector_check_state(struct intel_connector *connector)
6345 {
6346         struct drm_crtc *crtc = connector->base.state->crtc;
6347
6348         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6349                       connector->base.base.id,
6350                       connector->base.name);
6351
6352         if (connector->get_hw_state(connector)) {
6353                 struct intel_encoder *encoder = connector->encoder;
6354                 struct drm_connector_state *conn_state = connector->base.state;
6355
6356                 I915_STATE_WARN(!crtc,
6357                          "connector enabled without attached crtc\n");
6358
6359                 if (!crtc)
6360                         return;
6361
6362                 I915_STATE_WARN(!crtc->state->active,
6363                       "connector is active, but attached crtc isn't\n");
6364
6365                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6366                         return;
6367
6368                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6369                         "atomic encoder doesn't match attached encoder\n");
6370
6371                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6372                         "attached encoder crtc differs from connector crtc\n");
6373         } else {
6374                 I915_STATE_WARN(crtc && crtc->state->active,
6375                         "attached crtc is active, but connector isn't\n");
6376                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6377                         "best encoder set without crtc!\n");
6378         }
6379 }
6380
6381 int intel_connector_init(struct intel_connector *connector)
6382 {
6383         struct drm_connector_state *connector_state;
6384
6385         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6386         if (!connector_state)
6387                 return -ENOMEM;
6388
6389         connector->base.state = connector_state;
6390         return 0;
6391 }
6392
6393 struct intel_connector *intel_connector_alloc(void)
6394 {
6395         struct intel_connector *connector;
6396
6397         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6398         if (!connector)
6399                 return NULL;
6400
6401         if (intel_connector_init(connector) < 0) {
6402                 kfree(connector);
6403                 return NULL;
6404         }
6405
6406         return connector;
6407 }
6408
6409 /* Simple connector->get_hw_state implementation for encoders that support only
6410  * one connector and no cloning and hence the encoder state determines the state
6411  * of the connector. */
6412 bool intel_connector_get_hw_state(struct intel_connector *connector)
6413 {
6414         enum pipe pipe = 0;
6415         struct intel_encoder *encoder = connector->encoder;
6416
6417         return encoder->get_hw_state(encoder, &pipe);
6418 }
6419
6420 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6421 {
6422         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6423                 return crtc_state->fdi_lanes;
6424
6425         return 0;
6426 }
6427
6428 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6429                                      struct intel_crtc_state *pipe_config)
6430 {
6431         struct drm_atomic_state *state = pipe_config->base.state;
6432         struct intel_crtc *other_crtc;
6433         struct intel_crtc_state *other_crtc_state;
6434
6435         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6436                       pipe_name(pipe), pipe_config->fdi_lanes);
6437         if (pipe_config->fdi_lanes > 4) {
6438                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6439                               pipe_name(pipe), pipe_config->fdi_lanes);
6440                 return -EINVAL;
6441         }
6442
6443         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6444                 if (pipe_config->fdi_lanes > 2) {
6445                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6446                                       pipe_config->fdi_lanes);
6447                         return -EINVAL;
6448                 } else {
6449                         return 0;
6450                 }
6451         }
6452
6453         if (INTEL_INFO(dev)->num_pipes == 2)
6454                 return 0;
6455
6456         /* Ivybridge 3 pipe is really complicated */
6457         switch (pipe) {
6458         case PIPE_A:
6459                 return 0;
6460         case PIPE_B:
6461                 if (pipe_config->fdi_lanes <= 2)
6462                         return 0;
6463
6464                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6465                 other_crtc_state =
6466                         intel_atomic_get_crtc_state(state, other_crtc);
6467                 if (IS_ERR(other_crtc_state))
6468                         return PTR_ERR(other_crtc_state);
6469
6470                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6471                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6472                                       pipe_name(pipe), pipe_config->fdi_lanes);
6473                         return -EINVAL;
6474                 }
6475                 return 0;
6476         case PIPE_C:
6477                 if (pipe_config->fdi_lanes > 2) {
6478                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6479                                       pipe_name(pipe), pipe_config->fdi_lanes);
6480                         return -EINVAL;
6481                 }
6482
6483                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6484                 other_crtc_state =
6485                         intel_atomic_get_crtc_state(state, other_crtc);
6486                 if (IS_ERR(other_crtc_state))
6487                         return PTR_ERR(other_crtc_state);
6488
6489                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6490                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6491                         return -EINVAL;
6492                 }
6493                 return 0;
6494         default:
6495                 BUG();
6496         }
6497 }
6498
6499 #define RETRY 1
6500 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6501                                        struct intel_crtc_state *pipe_config)
6502 {
6503         struct drm_device *dev = intel_crtc->base.dev;
6504         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6505         int lane, link_bw, fdi_dotclock, ret;
6506         bool needs_recompute = false;
6507
6508 retry:
6509         /* FDI is a binary signal running at ~2.7GHz, encoding
6510          * each output octet as 10 bits. The actual frequency
6511          * is stored as a divider into a 100MHz clock, and the
6512          * mode pixel clock is stored in units of 1KHz.
6513          * Hence the bw of each lane in terms of the mode signal
6514          * is:
6515          */
6516         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6517
6518         fdi_dotclock = adjusted_mode->crtc_clock;
6519
6520         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6521                                            pipe_config->pipe_bpp);
6522
6523         pipe_config->fdi_lanes = lane;
6524
6525         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6526                                link_bw, &pipe_config->fdi_m_n);
6527
6528         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6529                                        intel_crtc->pipe, pipe_config);
6530         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6531                 pipe_config->pipe_bpp -= 2*3;
6532                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6533                               pipe_config->pipe_bpp);
6534                 needs_recompute = true;
6535                 pipe_config->bw_constrained = true;
6536
6537                 goto retry;
6538         }
6539
6540         if (needs_recompute)
6541                 return RETRY;
6542
6543         return ret;
6544 }
6545
6546 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6547                                      struct intel_crtc_state *pipe_config)
6548 {
6549         if (pipe_config->pipe_bpp > 24)
6550                 return false;
6551
6552         /* HSW can handle pixel rate up to cdclk? */
6553         if (IS_HASWELL(dev_priv->dev))
6554                 return true;
6555
6556         /*
6557          * We compare against max which means we must take
6558          * the increased cdclk requirement into account when
6559          * calculating the new cdclk.
6560          *
6561          * Should measure whether using a lower cdclk w/o IPS
6562          */
6563         return ilk_pipe_pixel_rate(pipe_config) <=
6564                 dev_priv->max_cdclk_freq * 95 / 100;
6565 }
6566
6567 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6568                                    struct intel_crtc_state *pipe_config)
6569 {
6570         struct drm_device *dev = crtc->base.dev;
6571         struct drm_i915_private *dev_priv = dev->dev_private;
6572
6573         pipe_config->ips_enabled = i915.enable_ips &&
6574                 hsw_crtc_supports_ips(crtc) &&
6575                 pipe_config_supports_ips(dev_priv, pipe_config);
6576 }
6577
6578 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6579                                      struct intel_crtc_state *pipe_config)
6580 {
6581         struct drm_device *dev = crtc->base.dev;
6582         struct drm_i915_private *dev_priv = dev->dev_private;
6583         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6584
6585         /* FIXME should check pixel clock limits on all platforms */
6586         if (INTEL_INFO(dev)->gen < 4) {
6587                 int clock_limit = dev_priv->max_cdclk_freq;
6588
6589                 /*
6590                  * Enable pixel doubling when the dot clock
6591                  * is > 90% of the (display) core speed.
6592                  *
6593                  * GDG double wide on either pipe,
6594                  * otherwise pipe A only.
6595                  */
6596                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6597                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6598                         clock_limit *= 2;
6599                         pipe_config->double_wide = true;
6600                 }
6601
6602                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6603                         return -EINVAL;
6604         }
6605
6606         /*
6607          * Pipe horizontal size must be even in:
6608          * - DVO ganged mode
6609          * - LVDS dual channel mode
6610          * - Double wide pipe
6611          */
6612         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6613              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6614                 pipe_config->pipe_src_w &= ~1;
6615
6616         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6617          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6618          */
6619         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6620                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6621                 return -EINVAL;
6622
6623         if (HAS_IPS(dev))
6624                 hsw_compute_ips_config(crtc, pipe_config);
6625
6626         if (pipe_config->has_pch_encoder)
6627                 return ironlake_fdi_compute_config(crtc, pipe_config);
6628
6629         return 0;
6630 }
6631
6632 static int skylake_get_display_clock_speed(struct drm_device *dev)
6633 {
6634         struct drm_i915_private *dev_priv = to_i915(dev);
6635         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6636         uint32_t cdctl = I915_READ(CDCLK_CTL);
6637         uint32_t linkrate;
6638
6639         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6640                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6641
6642         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6643                 return 540000;
6644
6645         linkrate = (I915_READ(DPLL_CTRL1) &
6646                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6647
6648         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6649             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6650                 /* vco 8640 */
6651                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6652                 case CDCLK_FREQ_450_432:
6653                         return 432000;
6654                 case CDCLK_FREQ_337_308:
6655                         return 308570;
6656                 case CDCLK_FREQ_675_617:
6657                         return 617140;
6658                 default:
6659                         WARN(1, "Unknown cd freq selection\n");
6660                 }
6661         } else {
6662                 /* vco 8100 */
6663                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6664                 case CDCLK_FREQ_450_432:
6665                         return 450000;
6666                 case CDCLK_FREQ_337_308:
6667                         return 337500;
6668                 case CDCLK_FREQ_675_617:
6669                         return 675000;
6670                 default:
6671                         WARN(1, "Unknown cd freq selection\n");
6672                 }
6673         }
6674
6675         /* error case, do as if DPLL0 isn't enabled */
6676         return 24000;
6677 }
6678
6679 static int broxton_get_display_clock_speed(struct drm_device *dev)
6680 {
6681         struct drm_i915_private *dev_priv = to_i915(dev);
6682         uint32_t cdctl = I915_READ(CDCLK_CTL);
6683         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6684         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6685         int cdclk;
6686
6687         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6688                 return 19200;
6689
6690         cdclk = 19200 * pll_ratio / 2;
6691
6692         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6693         case BXT_CDCLK_CD2X_DIV_SEL_1:
6694                 return cdclk;  /* 576MHz or 624MHz */
6695         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6696                 return cdclk * 2 / 3; /* 384MHz */
6697         case BXT_CDCLK_CD2X_DIV_SEL_2:
6698                 return cdclk / 2; /* 288MHz */
6699         case BXT_CDCLK_CD2X_DIV_SEL_4:
6700                 return cdclk / 4; /* 144MHz */
6701         }
6702
6703         /* error case, do as if DE PLL isn't enabled */
6704         return 19200;
6705 }
6706
6707 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6708 {
6709         struct drm_i915_private *dev_priv = dev->dev_private;
6710         uint32_t lcpll = I915_READ(LCPLL_CTL);
6711         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6712
6713         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6714                 return 800000;
6715         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6716                 return 450000;
6717         else if (freq == LCPLL_CLK_FREQ_450)
6718                 return 450000;
6719         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6720                 return 540000;
6721         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6722                 return 337500;
6723         else
6724                 return 675000;
6725 }
6726
6727 static int haswell_get_display_clock_speed(struct drm_device *dev)
6728 {
6729         struct drm_i915_private *dev_priv = dev->dev_private;
6730         uint32_t lcpll = I915_READ(LCPLL_CTL);
6731         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6732
6733         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6734                 return 800000;
6735         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6736                 return 450000;
6737         else if (freq == LCPLL_CLK_FREQ_450)
6738                 return 450000;
6739         else if (IS_HSW_ULT(dev))
6740                 return 337500;
6741         else
6742                 return 540000;
6743 }
6744
6745 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6746 {
6747         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6748                                       CCK_DISPLAY_CLOCK_CONTROL);
6749 }
6750
6751 static int ilk_get_display_clock_speed(struct drm_device *dev)
6752 {
6753         return 450000;
6754 }
6755
6756 static int i945_get_display_clock_speed(struct drm_device *dev)
6757 {
6758         return 400000;
6759 }
6760
6761 static int i915_get_display_clock_speed(struct drm_device *dev)
6762 {
6763         return 333333;
6764 }
6765
6766 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6767 {
6768         return 200000;
6769 }
6770
6771 static int pnv_get_display_clock_speed(struct drm_device *dev)
6772 {
6773         u16 gcfgc = 0;
6774
6775         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6776
6777         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6778         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6779                 return 266667;
6780         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6781                 return 333333;
6782         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6783                 return 444444;
6784         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6785                 return 200000;
6786         default:
6787                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6788         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6789                 return 133333;
6790         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6791                 return 166667;
6792         }
6793 }
6794
6795 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6796 {
6797         u16 gcfgc = 0;
6798
6799         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6800
6801         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6802                 return 133333;
6803         else {
6804                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6805                 case GC_DISPLAY_CLOCK_333_MHZ:
6806                         return 333333;
6807                 default:
6808                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6809                         return 190000;
6810                 }
6811         }
6812 }
6813
6814 static int i865_get_display_clock_speed(struct drm_device *dev)
6815 {
6816         return 266667;
6817 }
6818
6819 static int i85x_get_display_clock_speed(struct drm_device *dev)
6820 {
6821         u16 hpllcc = 0;
6822
6823         /*
6824          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6825          * encoding is different :(
6826          * FIXME is this the right way to detect 852GM/852GMV?
6827          */
6828         if (dev->pdev->revision == 0x1)
6829                 return 133333;
6830
6831         pci_bus_read_config_word(dev->pdev->bus,
6832                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6833
6834         /* Assume that the hardware is in the high speed state.  This
6835          * should be the default.
6836          */
6837         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6838         case GC_CLOCK_133_200:
6839         case GC_CLOCK_133_200_2:
6840         case GC_CLOCK_100_200:
6841                 return 200000;
6842         case GC_CLOCK_166_250:
6843                 return 250000;
6844         case GC_CLOCK_100_133:
6845                 return 133333;
6846         case GC_CLOCK_133_266:
6847         case GC_CLOCK_133_266_2:
6848         case GC_CLOCK_166_266:
6849                 return 266667;
6850         }
6851
6852         /* Shouldn't happen */
6853         return 0;
6854 }
6855
6856 static int i830_get_display_clock_speed(struct drm_device *dev)
6857 {
6858         return 133333;
6859 }
6860
6861 static unsigned int intel_hpll_vco(struct drm_device *dev)
6862 {
6863         struct drm_i915_private *dev_priv = dev->dev_private;
6864         static const unsigned int blb_vco[8] = {
6865                 [0] = 3200000,
6866                 [1] = 4000000,
6867                 [2] = 5333333,
6868                 [3] = 4800000,
6869                 [4] = 6400000,
6870         };
6871         static const unsigned int pnv_vco[8] = {
6872                 [0] = 3200000,
6873                 [1] = 4000000,
6874                 [2] = 5333333,
6875                 [3] = 4800000,
6876                 [4] = 2666667,
6877         };
6878         static const unsigned int cl_vco[8] = {
6879                 [0] = 3200000,
6880                 [1] = 4000000,
6881                 [2] = 5333333,
6882                 [3] = 6400000,
6883                 [4] = 3333333,
6884                 [5] = 3566667,
6885                 [6] = 4266667,
6886         };
6887         static const unsigned int elk_vco[8] = {
6888                 [0] = 3200000,
6889                 [1] = 4000000,
6890                 [2] = 5333333,
6891                 [3] = 4800000,
6892         };
6893         static const unsigned int ctg_vco[8] = {
6894                 [0] = 3200000,
6895                 [1] = 4000000,
6896                 [2] = 5333333,
6897                 [3] = 6400000,
6898                 [4] = 2666667,
6899                 [5] = 4266667,
6900         };
6901         const unsigned int *vco_table;
6902         unsigned int vco;
6903         uint8_t tmp = 0;
6904
6905         /* FIXME other chipsets? */
6906         if (IS_GM45(dev))
6907                 vco_table = ctg_vco;
6908         else if (IS_G4X(dev))
6909                 vco_table = elk_vco;
6910         else if (IS_CRESTLINE(dev))
6911                 vco_table = cl_vco;
6912         else if (IS_PINEVIEW(dev))
6913                 vco_table = pnv_vco;
6914         else if (IS_G33(dev))
6915                 vco_table = blb_vco;
6916         else
6917                 return 0;
6918
6919         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6920
6921         vco = vco_table[tmp & 0x7];
6922         if (vco == 0)
6923                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6924         else
6925                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6926
6927         return vco;
6928 }
6929
6930 static int gm45_get_display_clock_speed(struct drm_device *dev)
6931 {
6932         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6933         uint16_t tmp = 0;
6934
6935         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6936
6937         cdclk_sel = (tmp >> 12) & 0x1;
6938
6939         switch (vco) {
6940         case 2666667:
6941         case 4000000:
6942         case 5333333:
6943                 return cdclk_sel ? 333333 : 222222;
6944         case 3200000:
6945                 return cdclk_sel ? 320000 : 228571;
6946         default:
6947                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6948                 return 222222;
6949         }
6950 }
6951
6952 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6953 {
6954         static const uint8_t div_3200[] = { 16, 10,  8 };
6955         static const uint8_t div_4000[] = { 20, 12, 10 };
6956         static const uint8_t div_5333[] = { 24, 16, 14 };
6957         const uint8_t *div_table;
6958         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6959         uint16_t tmp = 0;
6960
6961         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6962
6963         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6964
6965         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6966                 goto fail;
6967
6968         switch (vco) {
6969         case 3200000:
6970                 div_table = div_3200;
6971                 break;
6972         case 4000000:
6973                 div_table = div_4000;
6974                 break;
6975         case 5333333:
6976                 div_table = div_5333;
6977                 break;
6978         default:
6979                 goto fail;
6980         }
6981
6982         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6983
6984 fail:
6985         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6986         return 200000;
6987 }
6988
6989 static int g33_get_display_clock_speed(struct drm_device *dev)
6990 {
6991         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6992         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6993         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6994         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6995         const uint8_t *div_table;
6996         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6997         uint16_t tmp = 0;
6998
6999         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7000
7001         cdclk_sel = (tmp >> 4) & 0x7;
7002
7003         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7004                 goto fail;
7005
7006         switch (vco) {
7007         case 3200000:
7008                 div_table = div_3200;
7009                 break;
7010         case 4000000:
7011                 div_table = div_4000;
7012                 break;
7013         case 4800000:
7014                 div_table = div_4800;
7015                 break;
7016         case 5333333:
7017                 div_table = div_5333;
7018                 break;
7019         default:
7020                 goto fail;
7021         }
7022
7023         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7024
7025 fail:
7026         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7027         return 190476;
7028 }
7029
7030 static void
7031 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7032 {
7033         while (*num > DATA_LINK_M_N_MASK ||
7034                *den > DATA_LINK_M_N_MASK) {
7035                 *num >>= 1;
7036                 *den >>= 1;
7037         }
7038 }
7039
7040 static void compute_m_n(unsigned int m, unsigned int n,
7041                         uint32_t *ret_m, uint32_t *ret_n)
7042 {
7043         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7044         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7045         intel_reduce_m_n_ratio(ret_m, ret_n);
7046 }
7047
7048 void
7049 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7050                        int pixel_clock, int link_clock,
7051                        struct intel_link_m_n *m_n)
7052 {
7053         m_n->tu = 64;
7054
7055         compute_m_n(bits_per_pixel * pixel_clock,
7056                     link_clock * nlanes * 8,
7057                     &m_n->gmch_m, &m_n->gmch_n);
7058
7059         compute_m_n(pixel_clock, link_clock,
7060                     &m_n->link_m, &m_n->link_n);
7061 }
7062
7063 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7064 {
7065         if (i915.panel_use_ssc >= 0)
7066                 return i915.panel_use_ssc != 0;
7067         return dev_priv->vbt.lvds_use_ssc
7068                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7069 }
7070
7071 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7072                            int num_connectors)
7073 {
7074         struct drm_device *dev = crtc_state->base.crtc->dev;
7075         struct drm_i915_private *dev_priv = dev->dev_private;
7076         int refclk;
7077
7078         WARN_ON(!crtc_state->base.state);
7079
7080         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7081                 refclk = 100000;
7082         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7083             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7084                 refclk = dev_priv->vbt.lvds_ssc_freq;
7085                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7086         } else if (!IS_GEN2(dev)) {
7087                 refclk = 96000;
7088         } else {
7089                 refclk = 48000;
7090         }
7091
7092         return refclk;
7093 }
7094
7095 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7096 {
7097         return (1 << dpll->n) << 16 | dpll->m2;
7098 }
7099
7100 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7101 {
7102         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7103 }
7104
7105 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7106                                      struct intel_crtc_state *crtc_state,
7107                                      intel_clock_t *reduced_clock)
7108 {
7109         struct drm_device *dev = crtc->base.dev;
7110         u32 fp, fp2 = 0;
7111
7112         if (IS_PINEVIEW(dev)) {
7113                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7114                 if (reduced_clock)
7115                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7116         } else {
7117                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7118                 if (reduced_clock)
7119                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7120         }
7121
7122         crtc_state->dpll_hw_state.fp0 = fp;
7123
7124         crtc->lowfreq_avail = false;
7125         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7126             reduced_clock) {
7127                 crtc_state->dpll_hw_state.fp1 = fp2;
7128                 crtc->lowfreq_avail = true;
7129         } else {
7130                 crtc_state->dpll_hw_state.fp1 = fp;
7131         }
7132 }
7133
7134 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7135                 pipe)
7136 {
7137         u32 reg_val;
7138
7139         /*
7140          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7141          * and set it to a reasonable value instead.
7142          */
7143         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7144         reg_val &= 0xffffff00;
7145         reg_val |= 0x00000030;
7146         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7147
7148         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7149         reg_val &= 0x8cffffff;
7150         reg_val = 0x8c000000;
7151         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7152
7153         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7154         reg_val &= 0xffffff00;
7155         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7156
7157         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7158         reg_val &= 0x00ffffff;
7159         reg_val |= 0xb0000000;
7160         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7161 }
7162
7163 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7164                                          struct intel_link_m_n *m_n)
7165 {
7166         struct drm_device *dev = crtc->base.dev;
7167         struct drm_i915_private *dev_priv = dev->dev_private;
7168         int pipe = crtc->pipe;
7169
7170         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7171         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7172         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7173         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7174 }
7175
7176 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7177                                          struct intel_link_m_n *m_n,
7178                                          struct intel_link_m_n *m2_n2)
7179 {
7180         struct drm_device *dev = crtc->base.dev;
7181         struct drm_i915_private *dev_priv = dev->dev_private;
7182         int pipe = crtc->pipe;
7183         enum transcoder transcoder = crtc->config->cpu_transcoder;
7184
7185         if (INTEL_INFO(dev)->gen >= 5) {
7186                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7187                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7188                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7189                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7190                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7191                  * for gen < 8) and if DRRS is supported (to make sure the
7192                  * registers are not unnecessarily accessed).
7193                  */
7194                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7195                         crtc->config->has_drrs) {
7196                         I915_WRITE(PIPE_DATA_M2(transcoder),
7197                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7198                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7199                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7200                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7201                 }
7202         } else {
7203                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7204                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7205                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7206                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7207         }
7208 }
7209
7210 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7211 {
7212         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7213
7214         if (m_n == M1_N1) {
7215                 dp_m_n = &crtc->config->dp_m_n;
7216                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7217         } else if (m_n == M2_N2) {
7218
7219                 /*
7220                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7221                  * needs to be programmed into M1_N1.
7222                  */
7223                 dp_m_n = &crtc->config->dp_m2_n2;
7224         } else {
7225                 DRM_ERROR("Unsupported divider value\n");
7226                 return;
7227         }
7228
7229         if (crtc->config->has_pch_encoder)
7230                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7231         else
7232                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7233 }
7234
7235 static void vlv_compute_dpll(struct intel_crtc *crtc,
7236                              struct intel_crtc_state *pipe_config)
7237 {
7238         u32 dpll, dpll_md;
7239
7240         /*
7241          * Enable DPIO clock input. We should never disable the reference
7242          * clock for pipe B, since VGA hotplug / manual detection depends
7243          * on it.
7244          */
7245         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7246                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7247         /* We should never disable this, set it here for state tracking */
7248         if (crtc->pipe == PIPE_B)
7249                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7250         dpll |= DPLL_VCO_ENABLE;
7251         pipe_config->dpll_hw_state.dpll = dpll;
7252
7253         dpll_md = (pipe_config->pixel_multiplier - 1)
7254                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7255         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7256 }
7257
7258 static void vlv_prepare_pll(struct intel_crtc *crtc,
7259                             const struct intel_crtc_state *pipe_config)
7260 {
7261         struct drm_device *dev = crtc->base.dev;
7262         struct drm_i915_private *dev_priv = dev->dev_private;
7263         int pipe = crtc->pipe;
7264         u32 mdiv;
7265         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7266         u32 coreclk, reg_val;
7267
7268         mutex_lock(&dev_priv->sb_lock);
7269
7270         bestn = pipe_config->dpll.n;
7271         bestm1 = pipe_config->dpll.m1;
7272         bestm2 = pipe_config->dpll.m2;
7273         bestp1 = pipe_config->dpll.p1;
7274         bestp2 = pipe_config->dpll.p2;
7275
7276         /* See eDP HDMI DPIO driver vbios notes doc */
7277
7278         /* PLL B needs special handling */
7279         if (pipe == PIPE_B)
7280                 vlv_pllb_recal_opamp(dev_priv, pipe);
7281
7282         /* Set up Tx target for periodic Rcomp update */
7283         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7284
7285         /* Disable target IRef on PLL */
7286         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7287         reg_val &= 0x00ffffff;
7288         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7289
7290         /* Disable fast lock */
7291         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7292
7293         /* Set idtafcrecal before PLL is enabled */
7294         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7295         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7296         mdiv |= ((bestn << DPIO_N_SHIFT));
7297         mdiv |= (1 << DPIO_K_SHIFT);
7298
7299         /*
7300          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7301          * but we don't support that).
7302          * Note: don't use the DAC post divider as it seems unstable.
7303          */
7304         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7305         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7306
7307         mdiv |= DPIO_ENABLE_CALIBRATION;
7308         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7309
7310         /* Set HBR and RBR LPF coefficients */
7311         if (pipe_config->port_clock == 162000 ||
7312             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7313             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7314                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7315                                  0x009f0003);
7316         else
7317                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7318                                  0x00d0000f);
7319
7320         if (pipe_config->has_dp_encoder) {
7321                 /* Use SSC source */
7322                 if (pipe == PIPE_A)
7323                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7324                                          0x0df40000);
7325                 else
7326                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7327                                          0x0df70000);
7328         } else { /* HDMI or VGA */
7329                 /* Use bend source */
7330                 if (pipe == PIPE_A)
7331                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7332                                          0x0df70000);
7333                 else
7334                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7335                                          0x0df40000);
7336         }
7337
7338         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7339         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7341             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7342                 coreclk |= 0x01000000;
7343         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7344
7345         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7346         mutex_unlock(&dev_priv->sb_lock);
7347 }
7348
7349 static void chv_compute_dpll(struct intel_crtc *crtc,
7350                              struct intel_crtc_state *pipe_config)
7351 {
7352         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7353                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7354                 DPLL_VCO_ENABLE;
7355         if (crtc->pipe != PIPE_A)
7356                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7357
7358         pipe_config->dpll_hw_state.dpll_md =
7359                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7360 }
7361
7362 static void chv_prepare_pll(struct intel_crtc *crtc,
7363                             const struct intel_crtc_state *pipe_config)
7364 {
7365         struct drm_device *dev = crtc->base.dev;
7366         struct drm_i915_private *dev_priv = dev->dev_private;
7367         int pipe = crtc->pipe;
7368         int dpll_reg = DPLL(crtc->pipe);
7369         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7370         u32 loopfilter, tribuf_calcntr;
7371         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7372         u32 dpio_val;
7373         int vco;
7374
7375         bestn = pipe_config->dpll.n;
7376         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7377         bestm1 = pipe_config->dpll.m1;
7378         bestm2 = pipe_config->dpll.m2 >> 22;
7379         bestp1 = pipe_config->dpll.p1;
7380         bestp2 = pipe_config->dpll.p2;
7381         vco = pipe_config->dpll.vco;
7382         dpio_val = 0;
7383         loopfilter = 0;
7384
7385         /*
7386          * Enable Refclk and SSC
7387          */
7388         I915_WRITE(dpll_reg,
7389                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7390
7391         mutex_lock(&dev_priv->sb_lock);
7392
7393         /* p1 and p2 divider */
7394         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7395                         5 << DPIO_CHV_S1_DIV_SHIFT |
7396                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7397                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7398                         1 << DPIO_CHV_K_DIV_SHIFT);
7399
7400         /* Feedback post-divider - m2 */
7401         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7402
7403         /* Feedback refclk divider - n and m1 */
7404         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7405                         DPIO_CHV_M1_DIV_BY_2 |
7406                         1 << DPIO_CHV_N_DIV_SHIFT);
7407
7408         /* M2 fraction division */
7409         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7410
7411         /* M2 fraction division enable */
7412         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7413         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7414         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7415         if (bestm2_frac)
7416                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7417         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7418
7419         /* Program digital lock detect threshold */
7420         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7421         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7422                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7423         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7424         if (!bestm2_frac)
7425                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7426         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7427
7428         /* Loop filter */
7429         if (vco == 5400000) {
7430                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7431                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7432                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7433                 tribuf_calcntr = 0x9;
7434         } else if (vco <= 6200000) {
7435                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7436                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7437                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7438                 tribuf_calcntr = 0x9;
7439         } else if (vco <= 6480000) {
7440                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7441                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7442                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7443                 tribuf_calcntr = 0x8;
7444         } else {
7445                 /* Not supported. Apply the same limits as in the max case */
7446                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7447                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7448                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7449                 tribuf_calcntr = 0;
7450         }
7451         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7452
7453         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7454         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7455         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7456         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7457
7458         /* AFC Recal */
7459         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7460                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7461                         DPIO_AFC_RECAL);
7462
7463         mutex_unlock(&dev_priv->sb_lock);
7464 }
7465
7466 /**
7467  * vlv_force_pll_on - forcibly enable just the PLL
7468  * @dev_priv: i915 private structure
7469  * @pipe: pipe PLL to enable
7470  * @dpll: PLL configuration
7471  *
7472  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7473  * in cases where we need the PLL enabled even when @pipe is not going to
7474  * be enabled.
7475  */
7476 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7477                       const struct dpll *dpll)
7478 {
7479         struct intel_crtc *crtc =
7480                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7481         struct intel_crtc_state pipe_config = {
7482                 .base.crtc = &crtc->base,
7483                 .pixel_multiplier = 1,
7484                 .dpll = *dpll,
7485         };
7486
7487         if (IS_CHERRYVIEW(dev)) {
7488                 chv_compute_dpll(crtc, &pipe_config);
7489                 chv_prepare_pll(crtc, &pipe_config);
7490                 chv_enable_pll(crtc, &pipe_config);
7491         } else {
7492                 vlv_compute_dpll(crtc, &pipe_config);
7493                 vlv_prepare_pll(crtc, &pipe_config);
7494                 vlv_enable_pll(crtc, &pipe_config);
7495         }
7496 }
7497
7498 /**
7499  * vlv_force_pll_off - forcibly disable just the PLL
7500  * @dev_priv: i915 private structure
7501  * @pipe: pipe PLL to disable
7502  *
7503  * Disable the PLL for @pipe. To be used in cases where we need
7504  * the PLL enabled even when @pipe is not going to be enabled.
7505  */
7506 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7507 {
7508         if (IS_CHERRYVIEW(dev))
7509                 chv_disable_pll(to_i915(dev), pipe);
7510         else
7511                 vlv_disable_pll(to_i915(dev), pipe);
7512 }
7513
7514 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7515                               struct intel_crtc_state *crtc_state,
7516                               intel_clock_t *reduced_clock,
7517                               int num_connectors)
7518 {
7519         struct drm_device *dev = crtc->base.dev;
7520         struct drm_i915_private *dev_priv = dev->dev_private;
7521         u32 dpll;
7522         bool is_sdvo;
7523         struct dpll *clock = &crtc_state->dpll;
7524
7525         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7526
7527         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7528                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7529
7530         dpll = DPLL_VGA_MODE_DIS;
7531
7532         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7533                 dpll |= DPLLB_MODE_LVDS;
7534         else
7535                 dpll |= DPLLB_MODE_DAC_SERIAL;
7536
7537         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7538                 dpll |= (crtc_state->pixel_multiplier - 1)
7539                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7540         }
7541
7542         if (is_sdvo)
7543                 dpll |= DPLL_SDVO_HIGH_SPEED;
7544
7545         if (crtc_state->has_dp_encoder)
7546                 dpll |= DPLL_SDVO_HIGH_SPEED;
7547
7548         /* compute bitmask from p1 value */
7549         if (IS_PINEVIEW(dev))
7550                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7551         else {
7552                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7553                 if (IS_G4X(dev) && reduced_clock)
7554                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7555         }
7556         switch (clock->p2) {
7557         case 5:
7558                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7559                 break;
7560         case 7:
7561                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7562                 break;
7563         case 10:
7564                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7565                 break;
7566         case 14:
7567                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7568                 break;
7569         }
7570         if (INTEL_INFO(dev)->gen >= 4)
7571                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7572
7573         if (crtc_state->sdvo_tv_clock)
7574                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7575         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7576                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7577                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7578         else
7579                 dpll |= PLL_REF_INPUT_DREFCLK;
7580
7581         dpll |= DPLL_VCO_ENABLE;
7582         crtc_state->dpll_hw_state.dpll = dpll;
7583
7584         if (INTEL_INFO(dev)->gen >= 4) {
7585                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7586                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7587                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7588         }
7589 }
7590
7591 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7592                               struct intel_crtc_state *crtc_state,
7593                               intel_clock_t *reduced_clock,
7594                               int num_connectors)
7595 {
7596         struct drm_device *dev = crtc->base.dev;
7597         struct drm_i915_private *dev_priv = dev->dev_private;
7598         u32 dpll;
7599         struct dpll *clock = &crtc_state->dpll;
7600
7601         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7602
7603         dpll = DPLL_VGA_MODE_DIS;
7604
7605         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7606                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7607         } else {
7608                 if (clock->p1 == 2)
7609                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7610                 else
7611                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7612                 if (clock->p2 == 4)
7613                         dpll |= PLL_P2_DIVIDE_BY_4;
7614         }
7615
7616         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7617                 dpll |= DPLL_DVO_2X_MODE;
7618
7619         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7620                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7621                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7622         else
7623                 dpll |= PLL_REF_INPUT_DREFCLK;
7624
7625         dpll |= DPLL_VCO_ENABLE;
7626         crtc_state->dpll_hw_state.dpll = dpll;
7627 }
7628
7629 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7630 {
7631         struct drm_device *dev = intel_crtc->base.dev;
7632         struct drm_i915_private *dev_priv = dev->dev_private;
7633         enum pipe pipe = intel_crtc->pipe;
7634         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7635         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7636         uint32_t crtc_vtotal, crtc_vblank_end;
7637         int vsyncshift = 0;
7638
7639         /* We need to be careful not to changed the adjusted mode, for otherwise
7640          * the hw state checker will get angry at the mismatch. */
7641         crtc_vtotal = adjusted_mode->crtc_vtotal;
7642         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7643
7644         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7645                 /* the chip adds 2 halflines automatically */
7646                 crtc_vtotal -= 1;
7647                 crtc_vblank_end -= 1;
7648
7649                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7650                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7651                 else
7652                         vsyncshift = adjusted_mode->crtc_hsync_start -
7653                                 adjusted_mode->crtc_htotal / 2;
7654                 if (vsyncshift < 0)
7655                         vsyncshift += adjusted_mode->crtc_htotal;
7656         }
7657
7658         if (INTEL_INFO(dev)->gen > 3)
7659                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7660
7661         I915_WRITE(HTOTAL(cpu_transcoder),
7662                    (adjusted_mode->crtc_hdisplay - 1) |
7663                    ((adjusted_mode->crtc_htotal - 1) << 16));
7664         I915_WRITE(HBLANK(cpu_transcoder),
7665                    (adjusted_mode->crtc_hblank_start - 1) |
7666                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7667         I915_WRITE(HSYNC(cpu_transcoder),
7668                    (adjusted_mode->crtc_hsync_start - 1) |
7669                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7670
7671         I915_WRITE(VTOTAL(cpu_transcoder),
7672                    (adjusted_mode->crtc_vdisplay - 1) |
7673                    ((crtc_vtotal - 1) << 16));
7674         I915_WRITE(VBLANK(cpu_transcoder),
7675                    (adjusted_mode->crtc_vblank_start - 1) |
7676                    ((crtc_vblank_end - 1) << 16));
7677         I915_WRITE(VSYNC(cpu_transcoder),
7678                    (adjusted_mode->crtc_vsync_start - 1) |
7679                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7680
7681         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7682          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7683          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7684          * bits. */
7685         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7686             (pipe == PIPE_B || pipe == PIPE_C))
7687                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7688
7689         /* pipesrc controls the size that is scaled from, which should
7690          * always be the user's requested size.
7691          */
7692         I915_WRITE(PIPESRC(pipe),
7693                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7694                    (intel_crtc->config->pipe_src_h - 1));
7695 }
7696
7697 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7698                                    struct intel_crtc_state *pipe_config)
7699 {
7700         struct drm_device *dev = crtc->base.dev;
7701         struct drm_i915_private *dev_priv = dev->dev_private;
7702         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7703         uint32_t tmp;
7704
7705         tmp = I915_READ(HTOTAL(cpu_transcoder));
7706         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7707         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7708         tmp = I915_READ(HBLANK(cpu_transcoder));
7709         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7710         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7711         tmp = I915_READ(HSYNC(cpu_transcoder));
7712         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7713         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7714
7715         tmp = I915_READ(VTOTAL(cpu_transcoder));
7716         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7717         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7718         tmp = I915_READ(VBLANK(cpu_transcoder));
7719         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7720         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7721         tmp = I915_READ(VSYNC(cpu_transcoder));
7722         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7723         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7724
7725         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7726                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7727                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7728                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7729         }
7730
7731         tmp = I915_READ(PIPESRC(crtc->pipe));
7732         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7733         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7734
7735         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7736         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7737 }
7738
7739 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7740                                  struct intel_crtc_state *pipe_config)
7741 {
7742         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7743         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7744         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7745         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7746
7747         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7748         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7749         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7750         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7751
7752         mode->flags = pipe_config->base.adjusted_mode.flags;
7753         mode->type = DRM_MODE_TYPE_DRIVER;
7754
7755         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7756         mode->flags |= pipe_config->base.adjusted_mode.flags;
7757
7758         mode->hsync = drm_mode_hsync(mode);
7759         mode->vrefresh = drm_mode_vrefresh(mode);
7760         drm_mode_set_name(mode);
7761 }
7762
7763 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7764 {
7765         struct drm_device *dev = intel_crtc->base.dev;
7766         struct drm_i915_private *dev_priv = dev->dev_private;
7767         uint32_t pipeconf;
7768
7769         pipeconf = 0;
7770
7771         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7772             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7773                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7774
7775         if (intel_crtc->config->double_wide)
7776                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7777
7778         /* only g4x and later have fancy bpc/dither controls */
7779         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7780                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7781                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7782                         pipeconf |= PIPECONF_DITHER_EN |
7783                                     PIPECONF_DITHER_TYPE_SP;
7784
7785                 switch (intel_crtc->config->pipe_bpp) {
7786                 case 18:
7787                         pipeconf |= PIPECONF_6BPC;
7788                         break;
7789                 case 24:
7790                         pipeconf |= PIPECONF_8BPC;
7791                         break;
7792                 case 30:
7793                         pipeconf |= PIPECONF_10BPC;
7794                         break;
7795                 default:
7796                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7797                         BUG();
7798                 }
7799         }
7800
7801         if (HAS_PIPE_CXSR(dev)) {
7802                 if (intel_crtc->lowfreq_avail) {
7803                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7804                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7805                 } else {
7806                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7807                 }
7808         }
7809
7810         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7811                 if (INTEL_INFO(dev)->gen < 4 ||
7812                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7813                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7814                 else
7815                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7816         } else
7817                 pipeconf |= PIPECONF_PROGRESSIVE;
7818
7819         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7820                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7821
7822         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7823         POSTING_READ(PIPECONF(intel_crtc->pipe));
7824 }
7825
7826 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7827                                    struct intel_crtc_state *crtc_state)
7828 {
7829         struct drm_device *dev = crtc->base.dev;
7830         struct drm_i915_private *dev_priv = dev->dev_private;
7831         int refclk, num_connectors = 0;
7832         intel_clock_t clock;
7833         bool ok;
7834         bool is_dsi = false;
7835         struct intel_encoder *encoder;
7836         const intel_limit_t *limit;
7837         struct drm_atomic_state *state = crtc_state->base.state;
7838         struct drm_connector *connector;
7839         struct drm_connector_state *connector_state;
7840         int i;
7841
7842         memset(&crtc_state->dpll_hw_state, 0,
7843                sizeof(crtc_state->dpll_hw_state));
7844
7845         for_each_connector_in_state(state, connector, connector_state, i) {
7846                 if (connector_state->crtc != &crtc->base)
7847                         continue;
7848
7849                 encoder = to_intel_encoder(connector_state->best_encoder);
7850
7851                 switch (encoder->type) {
7852                 case INTEL_OUTPUT_DSI:
7853                         is_dsi = true;
7854                         break;
7855                 default:
7856                         break;
7857                 }
7858
7859                 num_connectors++;
7860         }
7861
7862         if (is_dsi)
7863                 return 0;
7864
7865         if (!crtc_state->clock_set) {
7866                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7867
7868                 /*
7869                  * Returns a set of divisors for the desired target clock with
7870                  * the given refclk, or FALSE.  The returned values represent
7871                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7872                  * 2) / p1 / p2.
7873                  */
7874                 limit = intel_limit(crtc_state, refclk);
7875                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7876                                                  crtc_state->port_clock,
7877                                                  refclk, NULL, &clock);
7878                 if (!ok) {
7879                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7880                         return -EINVAL;
7881                 }
7882
7883                 /* Compat-code for transition, will disappear. */
7884                 crtc_state->dpll.n = clock.n;
7885                 crtc_state->dpll.m1 = clock.m1;
7886                 crtc_state->dpll.m2 = clock.m2;
7887                 crtc_state->dpll.p1 = clock.p1;
7888                 crtc_state->dpll.p2 = clock.p2;
7889         }
7890
7891         if (IS_GEN2(dev)) {
7892                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7893                                   num_connectors);
7894         } else if (IS_CHERRYVIEW(dev)) {
7895                 chv_compute_dpll(crtc, crtc_state);
7896         } else if (IS_VALLEYVIEW(dev)) {
7897                 vlv_compute_dpll(crtc, crtc_state);
7898         } else {
7899                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7900                                   num_connectors);
7901         }
7902
7903         return 0;
7904 }
7905
7906 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7907                                  struct intel_crtc_state *pipe_config)
7908 {
7909         struct drm_device *dev = crtc->base.dev;
7910         struct drm_i915_private *dev_priv = dev->dev_private;
7911         uint32_t tmp;
7912
7913         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7914                 return;
7915
7916         tmp = I915_READ(PFIT_CONTROL);
7917         if (!(tmp & PFIT_ENABLE))
7918                 return;
7919
7920         /* Check whether the pfit is attached to our pipe. */
7921         if (INTEL_INFO(dev)->gen < 4) {
7922                 if (crtc->pipe != PIPE_B)
7923                         return;
7924         } else {
7925                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7926                         return;
7927         }
7928
7929         pipe_config->gmch_pfit.control = tmp;
7930         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7931         if (INTEL_INFO(dev)->gen < 5)
7932                 pipe_config->gmch_pfit.lvds_border_bits =
7933                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7934 }
7935
7936 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7937                                struct intel_crtc_state *pipe_config)
7938 {
7939         struct drm_device *dev = crtc->base.dev;
7940         struct drm_i915_private *dev_priv = dev->dev_private;
7941         int pipe = pipe_config->cpu_transcoder;
7942         intel_clock_t clock;
7943         u32 mdiv;
7944         int refclk = 100000;
7945
7946         /* In case of MIPI DPLL will not even be used */
7947         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7948                 return;
7949
7950         mutex_lock(&dev_priv->sb_lock);
7951         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7952         mutex_unlock(&dev_priv->sb_lock);
7953
7954         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7955         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7956         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7957         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7958         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7959
7960         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7961 }
7962
7963 static void
7964 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7965                               struct intel_initial_plane_config *plane_config)
7966 {
7967         struct drm_device *dev = crtc->base.dev;
7968         struct drm_i915_private *dev_priv = dev->dev_private;
7969         u32 val, base, offset;
7970         int pipe = crtc->pipe, plane = crtc->plane;
7971         int fourcc, pixel_format;
7972         unsigned int aligned_height;
7973         struct drm_framebuffer *fb;
7974         struct intel_framebuffer *intel_fb;
7975
7976         val = I915_READ(DSPCNTR(plane));
7977         if (!(val & DISPLAY_PLANE_ENABLE))
7978                 return;
7979
7980         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7981         if (!intel_fb) {
7982                 DRM_DEBUG_KMS("failed to alloc fb\n");
7983                 return;
7984         }
7985
7986         fb = &intel_fb->base;
7987
7988         if (INTEL_INFO(dev)->gen >= 4) {
7989                 if (val & DISPPLANE_TILED) {
7990                         plane_config->tiling = I915_TILING_X;
7991                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7992                 }
7993         }
7994
7995         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7996         fourcc = i9xx_format_to_fourcc(pixel_format);
7997         fb->pixel_format = fourcc;
7998         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7999
8000         if (INTEL_INFO(dev)->gen >= 4) {
8001                 if (plane_config->tiling)
8002                         offset = I915_READ(DSPTILEOFF(plane));
8003                 else
8004                         offset = I915_READ(DSPLINOFF(plane));
8005                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8006         } else {
8007                 base = I915_READ(DSPADDR(plane));
8008         }
8009         plane_config->base = base;
8010
8011         val = I915_READ(PIPESRC(pipe));
8012         fb->width = ((val >> 16) & 0xfff) + 1;
8013         fb->height = ((val >> 0) & 0xfff) + 1;
8014
8015         val = I915_READ(DSPSTRIDE(pipe));
8016         fb->pitches[0] = val & 0xffffffc0;
8017
8018         aligned_height = intel_fb_align_height(dev, fb->height,
8019                                                fb->pixel_format,
8020                                                fb->modifier[0]);
8021
8022         plane_config->size = fb->pitches[0] * aligned_height;
8023
8024         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8025                       pipe_name(pipe), plane, fb->width, fb->height,
8026                       fb->bits_per_pixel, base, fb->pitches[0],
8027                       plane_config->size);
8028
8029         plane_config->fb = intel_fb;
8030 }
8031
8032 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8033                                struct intel_crtc_state *pipe_config)
8034 {
8035         struct drm_device *dev = crtc->base.dev;
8036         struct drm_i915_private *dev_priv = dev->dev_private;
8037         int pipe = pipe_config->cpu_transcoder;
8038         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8039         intel_clock_t clock;
8040         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8041         int refclk = 100000;
8042
8043         mutex_lock(&dev_priv->sb_lock);
8044         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8045         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8046         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8047         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8048         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8049         mutex_unlock(&dev_priv->sb_lock);
8050
8051         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8052         clock.m2 = (pll_dw0 & 0xff) << 22;
8053         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8054                 clock.m2 |= pll_dw2 & 0x3fffff;
8055         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8056         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8057         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8058
8059         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8060 }
8061
8062 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8063                                  struct intel_crtc_state *pipe_config)
8064 {
8065         struct drm_device *dev = crtc->base.dev;
8066         struct drm_i915_private *dev_priv = dev->dev_private;
8067         uint32_t tmp;
8068
8069         if (!intel_display_power_is_enabled(dev_priv,
8070                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8071                 return false;
8072
8073         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8074         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8075
8076         tmp = I915_READ(PIPECONF(crtc->pipe));
8077         if (!(tmp & PIPECONF_ENABLE))
8078                 return false;
8079
8080         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8081                 switch (tmp & PIPECONF_BPC_MASK) {
8082                 case PIPECONF_6BPC:
8083                         pipe_config->pipe_bpp = 18;
8084                         break;
8085                 case PIPECONF_8BPC:
8086                         pipe_config->pipe_bpp = 24;
8087                         break;
8088                 case PIPECONF_10BPC:
8089                         pipe_config->pipe_bpp = 30;
8090                         break;
8091                 default:
8092                         break;
8093                 }
8094         }
8095
8096         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8097                 pipe_config->limited_color_range = true;
8098
8099         if (INTEL_INFO(dev)->gen < 4)
8100                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8101
8102         intel_get_pipe_timings(crtc, pipe_config);
8103
8104         i9xx_get_pfit_config(crtc, pipe_config);
8105
8106         if (INTEL_INFO(dev)->gen >= 4) {
8107                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8108                 pipe_config->pixel_multiplier =
8109                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8110                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8111                 pipe_config->dpll_hw_state.dpll_md = tmp;
8112         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8113                 tmp = I915_READ(DPLL(crtc->pipe));
8114                 pipe_config->pixel_multiplier =
8115                         ((tmp & SDVO_MULTIPLIER_MASK)
8116                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8117         } else {
8118                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8119                  * port and will be fixed up in the encoder->get_config
8120                  * function. */
8121                 pipe_config->pixel_multiplier = 1;
8122         }
8123         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8124         if (!IS_VALLEYVIEW(dev)) {
8125                 /*
8126                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8127                  * on 830. Filter it out here so that we don't
8128                  * report errors due to that.
8129                  */
8130                 if (IS_I830(dev))
8131                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8132
8133                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8134                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8135         } else {
8136                 /* Mask out read-only status bits. */
8137                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8138                                                      DPLL_PORTC_READY_MASK |
8139                                                      DPLL_PORTB_READY_MASK);
8140         }
8141
8142         if (IS_CHERRYVIEW(dev))
8143                 chv_crtc_clock_get(crtc, pipe_config);
8144         else if (IS_VALLEYVIEW(dev))
8145                 vlv_crtc_clock_get(crtc, pipe_config);
8146         else
8147                 i9xx_crtc_clock_get(crtc, pipe_config);
8148
8149         /*
8150          * Normally the dotclock is filled in by the encoder .get_config()
8151          * but in case the pipe is enabled w/o any ports we need a sane
8152          * default.
8153          */
8154         pipe_config->base.adjusted_mode.crtc_clock =
8155                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8156
8157         return true;
8158 }
8159
8160 static void ironlake_init_pch_refclk(struct drm_device *dev)
8161 {
8162         struct drm_i915_private *dev_priv = dev->dev_private;
8163         struct intel_encoder *encoder;
8164         u32 val, final;
8165         bool has_lvds = false;
8166         bool has_cpu_edp = false;
8167         bool has_panel = false;
8168         bool has_ck505 = false;
8169         bool can_ssc = false;
8170
8171         /* We need to take the global config into account */
8172         for_each_intel_encoder(dev, encoder) {
8173                 switch (encoder->type) {
8174                 case INTEL_OUTPUT_LVDS:
8175                         has_panel = true;
8176                         has_lvds = true;
8177                         break;
8178                 case INTEL_OUTPUT_EDP:
8179                         has_panel = true;
8180                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8181                                 has_cpu_edp = true;
8182                         break;
8183                 default:
8184                         break;
8185                 }
8186         }
8187
8188         if (HAS_PCH_IBX(dev)) {
8189                 has_ck505 = dev_priv->vbt.display_clock_mode;
8190                 can_ssc = has_ck505;
8191         } else {
8192                 has_ck505 = false;
8193                 can_ssc = true;
8194         }
8195
8196         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8197                       has_panel, has_lvds, has_ck505);
8198
8199         /* Ironlake: try to setup display ref clock before DPLL
8200          * enabling. This is only under driver's control after
8201          * PCH B stepping, previous chipset stepping should be
8202          * ignoring this setting.
8203          */
8204         val = I915_READ(PCH_DREF_CONTROL);
8205
8206         /* As we must carefully and slowly disable/enable each source in turn,
8207          * compute the final state we want first and check if we need to
8208          * make any changes at all.
8209          */
8210         final = val;
8211         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8212         if (has_ck505)
8213                 final |= DREF_NONSPREAD_CK505_ENABLE;
8214         else
8215                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8216
8217         final &= ~DREF_SSC_SOURCE_MASK;
8218         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8219         final &= ~DREF_SSC1_ENABLE;
8220
8221         if (has_panel) {
8222                 final |= DREF_SSC_SOURCE_ENABLE;
8223
8224                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8225                         final |= DREF_SSC1_ENABLE;
8226
8227                 if (has_cpu_edp) {
8228                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8229                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8230                         else
8231                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8232                 } else
8233                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8234         } else {
8235                 final |= DREF_SSC_SOURCE_DISABLE;
8236                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8237         }
8238
8239         if (final == val)
8240                 return;
8241
8242         /* Always enable nonspread source */
8243         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8244
8245         if (has_ck505)
8246                 val |= DREF_NONSPREAD_CK505_ENABLE;
8247         else
8248                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8249
8250         if (has_panel) {
8251                 val &= ~DREF_SSC_SOURCE_MASK;
8252                 val |= DREF_SSC_SOURCE_ENABLE;
8253
8254                 /* SSC must be turned on before enabling the CPU output  */
8255                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8256                         DRM_DEBUG_KMS("Using SSC on panel\n");
8257                         val |= DREF_SSC1_ENABLE;
8258                 } else
8259                         val &= ~DREF_SSC1_ENABLE;
8260
8261                 /* Get SSC going before enabling the outputs */
8262                 I915_WRITE(PCH_DREF_CONTROL, val);
8263                 POSTING_READ(PCH_DREF_CONTROL);
8264                 udelay(200);
8265
8266                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8267
8268                 /* Enable CPU source on CPU attached eDP */
8269                 if (has_cpu_edp) {
8270                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8271                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8272                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8273                         } else
8274                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8275                 } else
8276                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8277
8278                 I915_WRITE(PCH_DREF_CONTROL, val);
8279                 POSTING_READ(PCH_DREF_CONTROL);
8280                 udelay(200);
8281         } else {
8282                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8283
8284                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8285
8286                 /* Turn off CPU output */
8287                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8288
8289                 I915_WRITE(PCH_DREF_CONTROL, val);
8290                 POSTING_READ(PCH_DREF_CONTROL);
8291                 udelay(200);
8292
8293                 /* Turn off the SSC source */
8294                 val &= ~DREF_SSC_SOURCE_MASK;
8295                 val |= DREF_SSC_SOURCE_DISABLE;
8296
8297                 /* Turn off SSC1 */
8298                 val &= ~DREF_SSC1_ENABLE;
8299
8300                 I915_WRITE(PCH_DREF_CONTROL, val);
8301                 POSTING_READ(PCH_DREF_CONTROL);
8302                 udelay(200);
8303         }
8304
8305         BUG_ON(val != final);
8306 }
8307
8308 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8309 {
8310         uint32_t tmp;
8311
8312         tmp = I915_READ(SOUTH_CHICKEN2);
8313         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8314         I915_WRITE(SOUTH_CHICKEN2, tmp);
8315
8316         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8317                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8318                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8319
8320         tmp = I915_READ(SOUTH_CHICKEN2);
8321         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8322         I915_WRITE(SOUTH_CHICKEN2, tmp);
8323
8324         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8325                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8326                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8327 }
8328
8329 /* WaMPhyProgramming:hsw */
8330 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8331 {
8332         uint32_t tmp;
8333
8334         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8335         tmp &= ~(0xFF << 24);
8336         tmp |= (0x12 << 24);
8337         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8338
8339         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8340         tmp |= (1 << 11);
8341         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8342
8343         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8344         tmp |= (1 << 11);
8345         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8346
8347         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8348         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8349         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8350
8351         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8352         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8353         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8354
8355         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8356         tmp &= ~(7 << 13);
8357         tmp |= (5 << 13);
8358         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8359
8360         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8361         tmp &= ~(7 << 13);
8362         tmp |= (5 << 13);
8363         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8364
8365         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8366         tmp &= ~0xFF;
8367         tmp |= 0x1C;
8368         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8369
8370         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8371         tmp &= ~0xFF;
8372         tmp |= 0x1C;
8373         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8374
8375         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8376         tmp &= ~(0xFF << 16);
8377         tmp |= (0x1C << 16);
8378         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8379
8380         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8381         tmp &= ~(0xFF << 16);
8382         tmp |= (0x1C << 16);
8383         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8384
8385         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8386         tmp |= (1 << 27);
8387         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8388
8389         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8390         tmp |= (1 << 27);
8391         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8392
8393         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8394         tmp &= ~(0xF << 28);
8395         tmp |= (4 << 28);
8396         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8397
8398         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8399         tmp &= ~(0xF << 28);
8400         tmp |= (4 << 28);
8401         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8402 }
8403
8404 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8405  * Programming" based on the parameters passed:
8406  * - Sequence to enable CLKOUT_DP
8407  * - Sequence to enable CLKOUT_DP without spread
8408  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8409  */
8410 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8411                                  bool with_fdi)
8412 {
8413         struct drm_i915_private *dev_priv = dev->dev_private;
8414         uint32_t reg, tmp;
8415
8416         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8417                 with_spread = true;
8418         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8419                 with_fdi = false;
8420
8421         mutex_lock(&dev_priv->sb_lock);
8422
8423         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8424         tmp &= ~SBI_SSCCTL_DISABLE;
8425         tmp |= SBI_SSCCTL_PATHALT;
8426         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8427
8428         udelay(24);
8429
8430         if (with_spread) {
8431                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8432                 tmp &= ~SBI_SSCCTL_PATHALT;
8433                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8434
8435                 if (with_fdi) {
8436                         lpt_reset_fdi_mphy(dev_priv);
8437                         lpt_program_fdi_mphy(dev_priv);
8438                 }
8439         }
8440
8441         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8442         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8443         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8444         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8445
8446         mutex_unlock(&dev_priv->sb_lock);
8447 }
8448
8449 /* Sequence to disable CLKOUT_DP */
8450 static void lpt_disable_clkout_dp(struct drm_device *dev)
8451 {
8452         struct drm_i915_private *dev_priv = dev->dev_private;
8453         uint32_t reg, tmp;
8454
8455         mutex_lock(&dev_priv->sb_lock);
8456
8457         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8458         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8459         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8460         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8461
8462         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8463         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8464                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8465                         tmp |= SBI_SSCCTL_PATHALT;
8466                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8467                         udelay(32);
8468                 }
8469                 tmp |= SBI_SSCCTL_DISABLE;
8470                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8471         }
8472
8473         mutex_unlock(&dev_priv->sb_lock);
8474 }
8475
8476 static void lpt_init_pch_refclk(struct drm_device *dev)
8477 {
8478         struct intel_encoder *encoder;
8479         bool has_vga = false;
8480
8481         for_each_intel_encoder(dev, encoder) {
8482                 switch (encoder->type) {
8483                 case INTEL_OUTPUT_ANALOG:
8484                         has_vga = true;
8485                         break;
8486                 default:
8487                         break;
8488                 }
8489         }
8490
8491         if (has_vga)
8492                 lpt_enable_clkout_dp(dev, true, true);
8493         else
8494                 lpt_disable_clkout_dp(dev);
8495 }
8496
8497 /*
8498  * Initialize reference clocks when the driver loads
8499  */
8500 void intel_init_pch_refclk(struct drm_device *dev)
8501 {
8502         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8503                 ironlake_init_pch_refclk(dev);
8504         else if (HAS_PCH_LPT(dev))
8505                 lpt_init_pch_refclk(dev);
8506 }
8507
8508 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8509 {
8510         struct drm_device *dev = crtc_state->base.crtc->dev;
8511         struct drm_i915_private *dev_priv = dev->dev_private;
8512         struct drm_atomic_state *state = crtc_state->base.state;
8513         struct drm_connector *connector;
8514         struct drm_connector_state *connector_state;
8515         struct intel_encoder *encoder;
8516         int num_connectors = 0, i;
8517         bool is_lvds = false;
8518
8519         for_each_connector_in_state(state, connector, connector_state, i) {
8520                 if (connector_state->crtc != crtc_state->base.crtc)
8521                         continue;
8522
8523                 encoder = to_intel_encoder(connector_state->best_encoder);
8524
8525                 switch (encoder->type) {
8526                 case INTEL_OUTPUT_LVDS:
8527                         is_lvds = true;
8528                         break;
8529                 default:
8530                         break;
8531                 }
8532                 num_connectors++;
8533         }
8534
8535         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8536                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8537                               dev_priv->vbt.lvds_ssc_freq);
8538                 return dev_priv->vbt.lvds_ssc_freq;
8539         }
8540
8541         return 120000;
8542 }
8543
8544 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8545 {
8546         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8548         int pipe = intel_crtc->pipe;
8549         uint32_t val;
8550
8551         val = 0;
8552
8553         switch (intel_crtc->config->pipe_bpp) {
8554         case 18:
8555                 val |= PIPECONF_6BPC;
8556                 break;
8557         case 24:
8558                 val |= PIPECONF_8BPC;
8559                 break;
8560         case 30:
8561                 val |= PIPECONF_10BPC;
8562                 break;
8563         case 36:
8564                 val |= PIPECONF_12BPC;
8565                 break;
8566         default:
8567                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8568                 BUG();
8569         }
8570
8571         if (intel_crtc->config->dither)
8572                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8573
8574         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8575                 val |= PIPECONF_INTERLACED_ILK;
8576         else
8577                 val |= PIPECONF_PROGRESSIVE;
8578
8579         if (intel_crtc->config->limited_color_range)
8580                 val |= PIPECONF_COLOR_RANGE_SELECT;
8581
8582         I915_WRITE(PIPECONF(pipe), val);
8583         POSTING_READ(PIPECONF(pipe));
8584 }
8585
8586 /*
8587  * Set up the pipe CSC unit.
8588  *
8589  * Currently only full range RGB to limited range RGB conversion
8590  * is supported, but eventually this should handle various
8591  * RGB<->YCbCr scenarios as well.
8592  */
8593 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8594 {
8595         struct drm_device *dev = crtc->dev;
8596         struct drm_i915_private *dev_priv = dev->dev_private;
8597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8598         int pipe = intel_crtc->pipe;
8599         uint16_t coeff = 0x7800; /* 1.0 */
8600
8601         /*
8602          * TODO: Check what kind of values actually come out of the pipe
8603          * with these coeff/postoff values and adjust to get the best
8604          * accuracy. Perhaps we even need to take the bpc value into
8605          * consideration.
8606          */
8607
8608         if (intel_crtc->config->limited_color_range)
8609                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8610
8611         /*
8612          * GY/GU and RY/RU should be the other way around according
8613          * to BSpec, but reality doesn't agree. Just set them up in
8614          * a way that results in the correct picture.
8615          */
8616         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8617         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8618
8619         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8620         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8621
8622         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8623         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8624
8625         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8626         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8627         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8628
8629         if (INTEL_INFO(dev)->gen > 6) {
8630                 uint16_t postoff = 0;
8631
8632                 if (intel_crtc->config->limited_color_range)
8633                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8634
8635                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8636                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8637                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8638
8639                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8640         } else {
8641                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8642
8643                 if (intel_crtc->config->limited_color_range)
8644                         mode |= CSC_BLACK_SCREEN_OFFSET;
8645
8646                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8647         }
8648 }
8649
8650 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8651 {
8652         struct drm_device *dev = crtc->dev;
8653         struct drm_i915_private *dev_priv = dev->dev_private;
8654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8655         enum pipe pipe = intel_crtc->pipe;
8656         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8657         uint32_t val;
8658
8659         val = 0;
8660
8661         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8662                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8663
8664         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8665                 val |= PIPECONF_INTERLACED_ILK;
8666         else
8667                 val |= PIPECONF_PROGRESSIVE;
8668
8669         I915_WRITE(PIPECONF(cpu_transcoder), val);
8670         POSTING_READ(PIPECONF(cpu_transcoder));
8671
8672         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8673         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8674
8675         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8676                 val = 0;
8677
8678                 switch (intel_crtc->config->pipe_bpp) {
8679                 case 18:
8680                         val |= PIPEMISC_DITHER_6_BPC;
8681                         break;
8682                 case 24:
8683                         val |= PIPEMISC_DITHER_8_BPC;
8684                         break;
8685                 case 30:
8686                         val |= PIPEMISC_DITHER_10_BPC;
8687                         break;
8688                 case 36:
8689                         val |= PIPEMISC_DITHER_12_BPC;
8690                         break;
8691                 default:
8692                         /* Case prevented by pipe_config_set_bpp. */
8693                         BUG();
8694                 }
8695
8696                 if (intel_crtc->config->dither)
8697                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8698
8699                 I915_WRITE(PIPEMISC(pipe), val);
8700         }
8701 }
8702
8703 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8704                                     struct intel_crtc_state *crtc_state,
8705                                     intel_clock_t *clock,
8706                                     bool *has_reduced_clock,
8707                                     intel_clock_t *reduced_clock)
8708 {
8709         struct drm_device *dev = crtc->dev;
8710         struct drm_i915_private *dev_priv = dev->dev_private;
8711         int refclk;
8712         const intel_limit_t *limit;
8713         bool ret;
8714
8715         refclk = ironlake_get_refclk(crtc_state);
8716
8717         /*
8718          * Returns a set of divisors for the desired target clock with the given
8719          * refclk, or FALSE.  The returned values represent the clock equation:
8720          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8721          */
8722         limit = intel_limit(crtc_state, refclk);
8723         ret = dev_priv->display.find_dpll(limit, crtc_state,
8724                                           crtc_state->port_clock,
8725                                           refclk, NULL, clock);
8726         if (!ret)
8727                 return false;
8728
8729         return true;
8730 }
8731
8732 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8733 {
8734         /*
8735          * Account for spread spectrum to avoid
8736          * oversubscribing the link. Max center spread
8737          * is 2.5%; use 5% for safety's sake.
8738          */
8739         u32 bps = target_clock * bpp * 21 / 20;
8740         return DIV_ROUND_UP(bps, link_bw * 8);
8741 }
8742
8743 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8744 {
8745         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8746 }
8747
8748 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8749                                       struct intel_crtc_state *crtc_state,
8750                                       u32 *fp,
8751                                       intel_clock_t *reduced_clock, u32 *fp2)
8752 {
8753         struct drm_crtc *crtc = &intel_crtc->base;
8754         struct drm_device *dev = crtc->dev;
8755         struct drm_i915_private *dev_priv = dev->dev_private;
8756         struct drm_atomic_state *state = crtc_state->base.state;
8757         struct drm_connector *connector;
8758         struct drm_connector_state *connector_state;
8759         struct intel_encoder *encoder;
8760         uint32_t dpll;
8761         int factor, num_connectors = 0, i;
8762         bool is_lvds = false, is_sdvo = false;
8763
8764         for_each_connector_in_state(state, connector, connector_state, i) {
8765                 if (connector_state->crtc != crtc_state->base.crtc)
8766                         continue;
8767
8768                 encoder = to_intel_encoder(connector_state->best_encoder);
8769
8770                 switch (encoder->type) {
8771                 case INTEL_OUTPUT_LVDS:
8772                         is_lvds = true;
8773                         break;
8774                 case INTEL_OUTPUT_SDVO:
8775                 case INTEL_OUTPUT_HDMI:
8776                         is_sdvo = true;
8777                         break;
8778                 default:
8779                         break;
8780                 }
8781
8782                 num_connectors++;
8783         }
8784
8785         /* Enable autotuning of the PLL clock (if permissible) */
8786         factor = 21;
8787         if (is_lvds) {
8788                 if ((intel_panel_use_ssc(dev_priv) &&
8789                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8790                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8791                         factor = 25;
8792         } else if (crtc_state->sdvo_tv_clock)
8793                 factor = 20;
8794
8795         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8796                 *fp |= FP_CB_TUNE;
8797
8798         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8799                 *fp2 |= FP_CB_TUNE;
8800
8801         dpll = 0;
8802
8803         if (is_lvds)
8804                 dpll |= DPLLB_MODE_LVDS;
8805         else
8806                 dpll |= DPLLB_MODE_DAC_SERIAL;
8807
8808         dpll |= (crtc_state->pixel_multiplier - 1)
8809                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8810
8811         if (is_sdvo)
8812                 dpll |= DPLL_SDVO_HIGH_SPEED;
8813         if (crtc_state->has_dp_encoder)
8814                 dpll |= DPLL_SDVO_HIGH_SPEED;
8815
8816         /* compute bitmask from p1 value */
8817         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8818         /* also FPA1 */
8819         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8820
8821         switch (crtc_state->dpll.p2) {
8822         case 5:
8823                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8824                 break;
8825         case 7:
8826                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8827                 break;
8828         case 10:
8829                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8830                 break;
8831         case 14:
8832                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8833                 break;
8834         }
8835
8836         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8837                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8838         else
8839                 dpll |= PLL_REF_INPUT_DREFCLK;
8840
8841         return dpll | DPLL_VCO_ENABLE;
8842 }
8843
8844 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8845                                        struct intel_crtc_state *crtc_state)
8846 {
8847         struct drm_device *dev = crtc->base.dev;
8848         intel_clock_t clock, reduced_clock;
8849         u32 dpll = 0, fp = 0, fp2 = 0;
8850         bool ok, has_reduced_clock = false;
8851         bool is_lvds = false;
8852         struct intel_shared_dpll *pll;
8853
8854         memset(&crtc_state->dpll_hw_state, 0,
8855                sizeof(crtc_state->dpll_hw_state));
8856
8857         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8858
8859         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8860              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8861
8862         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8863                                      &has_reduced_clock, &reduced_clock);
8864         if (!ok && !crtc_state->clock_set) {
8865                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8866                 return -EINVAL;
8867         }
8868         /* Compat-code for transition, will disappear. */
8869         if (!crtc_state->clock_set) {
8870                 crtc_state->dpll.n = clock.n;
8871                 crtc_state->dpll.m1 = clock.m1;
8872                 crtc_state->dpll.m2 = clock.m2;
8873                 crtc_state->dpll.p1 = clock.p1;
8874                 crtc_state->dpll.p2 = clock.p2;
8875         }
8876
8877         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8878         if (crtc_state->has_pch_encoder) {
8879                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8880                 if (has_reduced_clock)
8881                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8882
8883                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8884                                              &fp, &reduced_clock,
8885                                              has_reduced_clock ? &fp2 : NULL);
8886
8887                 crtc_state->dpll_hw_state.dpll = dpll;
8888                 crtc_state->dpll_hw_state.fp0 = fp;
8889                 if (has_reduced_clock)
8890                         crtc_state->dpll_hw_state.fp1 = fp2;
8891                 else
8892                         crtc_state->dpll_hw_state.fp1 = fp;
8893
8894                 pll = intel_get_shared_dpll(crtc, crtc_state);
8895                 if (pll == NULL) {
8896                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8897                                          pipe_name(crtc->pipe));
8898                         return -EINVAL;
8899                 }
8900         }
8901
8902         if (is_lvds && has_reduced_clock)
8903                 crtc->lowfreq_avail = true;
8904         else
8905                 crtc->lowfreq_avail = false;
8906
8907         return 0;
8908 }
8909
8910 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8911                                          struct intel_link_m_n *m_n)
8912 {
8913         struct drm_device *dev = crtc->base.dev;
8914         struct drm_i915_private *dev_priv = dev->dev_private;
8915         enum pipe pipe = crtc->pipe;
8916
8917         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8918         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8919         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8920                 & ~TU_SIZE_MASK;
8921         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8922         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8923                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8924 }
8925
8926 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8927                                          enum transcoder transcoder,
8928                                          struct intel_link_m_n *m_n,
8929                                          struct intel_link_m_n *m2_n2)
8930 {
8931         struct drm_device *dev = crtc->base.dev;
8932         struct drm_i915_private *dev_priv = dev->dev_private;
8933         enum pipe pipe = crtc->pipe;
8934
8935         if (INTEL_INFO(dev)->gen >= 5) {
8936                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8937                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8938                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8939                         & ~TU_SIZE_MASK;
8940                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8941                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8942                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8943                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8944                  * gen < 8) and if DRRS is supported (to make sure the
8945                  * registers are not unnecessarily read).
8946                  */
8947                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8948                         crtc->config->has_drrs) {
8949                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8950                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8951                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8952                                         & ~TU_SIZE_MASK;
8953                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8954                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8955                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8956                 }
8957         } else {
8958                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8959                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8960                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8961                         & ~TU_SIZE_MASK;
8962                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8963                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8964                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8965         }
8966 }
8967
8968 void intel_dp_get_m_n(struct intel_crtc *crtc,
8969                       struct intel_crtc_state *pipe_config)
8970 {
8971         if (pipe_config->has_pch_encoder)
8972                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8973         else
8974                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8975                                              &pipe_config->dp_m_n,
8976                                              &pipe_config->dp_m2_n2);
8977 }
8978
8979 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8980                                         struct intel_crtc_state *pipe_config)
8981 {
8982         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8983                                      &pipe_config->fdi_m_n, NULL);
8984 }
8985
8986 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8987                                     struct intel_crtc_state *pipe_config)
8988 {
8989         struct drm_device *dev = crtc->base.dev;
8990         struct drm_i915_private *dev_priv = dev->dev_private;
8991         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8992         uint32_t ps_ctrl = 0;
8993         int id = -1;
8994         int i;
8995
8996         /* find scaler attached to this pipe */
8997         for (i = 0; i < crtc->num_scalers; i++) {
8998                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8999                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9000                         id = i;
9001                         pipe_config->pch_pfit.enabled = true;
9002                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9003                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9004                         break;
9005                 }
9006         }
9007
9008         scaler_state->scaler_id = id;
9009         if (id >= 0) {
9010                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9011         } else {
9012                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9013         }
9014 }
9015
9016 static void
9017 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9018                                  struct intel_initial_plane_config *plane_config)
9019 {
9020         struct drm_device *dev = crtc->base.dev;
9021         struct drm_i915_private *dev_priv = dev->dev_private;
9022         u32 val, base, offset, stride_mult, tiling;
9023         int pipe = crtc->pipe;
9024         int fourcc, pixel_format;
9025         unsigned int aligned_height;
9026         struct drm_framebuffer *fb;
9027         struct intel_framebuffer *intel_fb;
9028
9029         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9030         if (!intel_fb) {
9031                 DRM_DEBUG_KMS("failed to alloc fb\n");
9032                 return;
9033         }
9034
9035         fb = &intel_fb->base;
9036
9037         val = I915_READ(PLANE_CTL(pipe, 0));
9038         if (!(val & PLANE_CTL_ENABLE))
9039                 goto error;
9040
9041         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9042         fourcc = skl_format_to_fourcc(pixel_format,
9043                                       val & PLANE_CTL_ORDER_RGBX,
9044                                       val & PLANE_CTL_ALPHA_MASK);
9045         fb->pixel_format = fourcc;
9046         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9047
9048         tiling = val & PLANE_CTL_TILED_MASK;
9049         switch (tiling) {
9050         case PLANE_CTL_TILED_LINEAR:
9051                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9052                 break;
9053         case PLANE_CTL_TILED_X:
9054                 plane_config->tiling = I915_TILING_X;
9055                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9056                 break;
9057         case PLANE_CTL_TILED_Y:
9058                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9059                 break;
9060         case PLANE_CTL_TILED_YF:
9061                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9062                 break;
9063         default:
9064                 MISSING_CASE(tiling);
9065                 goto error;
9066         }
9067
9068         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9069         plane_config->base = base;
9070
9071         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9072
9073         val = I915_READ(PLANE_SIZE(pipe, 0));
9074         fb->height = ((val >> 16) & 0xfff) + 1;
9075         fb->width = ((val >> 0) & 0x1fff) + 1;
9076
9077         val = I915_READ(PLANE_STRIDE(pipe, 0));
9078         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9079                                                 fb->pixel_format);
9080         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9081
9082         aligned_height = intel_fb_align_height(dev, fb->height,
9083                                                fb->pixel_format,
9084                                                fb->modifier[0]);
9085
9086         plane_config->size = fb->pitches[0] * aligned_height;
9087
9088         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9089                       pipe_name(pipe), fb->width, fb->height,
9090                       fb->bits_per_pixel, base, fb->pitches[0],
9091                       plane_config->size);
9092
9093         plane_config->fb = intel_fb;
9094         return;
9095
9096 error:
9097         kfree(fb);
9098 }
9099
9100 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9101                                      struct intel_crtc_state *pipe_config)
9102 {
9103         struct drm_device *dev = crtc->base.dev;
9104         struct drm_i915_private *dev_priv = dev->dev_private;
9105         uint32_t tmp;
9106
9107         tmp = I915_READ(PF_CTL(crtc->pipe));
9108
9109         if (tmp & PF_ENABLE) {
9110                 pipe_config->pch_pfit.enabled = true;
9111                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9112                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9113
9114                 /* We currently do not free assignements of panel fitters on
9115                  * ivb/hsw (since we don't use the higher upscaling modes which
9116                  * differentiates them) so just WARN about this case for now. */
9117                 if (IS_GEN7(dev)) {
9118                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9119                                 PF_PIPE_SEL_IVB(crtc->pipe));
9120                 }
9121         }
9122 }
9123
9124 static void
9125 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9126                                   struct intel_initial_plane_config *plane_config)
9127 {
9128         struct drm_device *dev = crtc->base.dev;
9129         struct drm_i915_private *dev_priv = dev->dev_private;
9130         u32 val, base, offset;
9131         int pipe = crtc->pipe;
9132         int fourcc, pixel_format;
9133         unsigned int aligned_height;
9134         struct drm_framebuffer *fb;
9135         struct intel_framebuffer *intel_fb;
9136
9137         val = I915_READ(DSPCNTR(pipe));
9138         if (!(val & DISPLAY_PLANE_ENABLE))
9139                 return;
9140
9141         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9142         if (!intel_fb) {
9143                 DRM_DEBUG_KMS("failed to alloc fb\n");
9144                 return;
9145         }
9146
9147         fb = &intel_fb->base;
9148
9149         if (INTEL_INFO(dev)->gen >= 4) {
9150                 if (val & DISPPLANE_TILED) {
9151                         plane_config->tiling = I915_TILING_X;
9152                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9153                 }
9154         }
9155
9156         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9157         fourcc = i9xx_format_to_fourcc(pixel_format);
9158         fb->pixel_format = fourcc;
9159         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9160
9161         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9162         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9163                 offset = I915_READ(DSPOFFSET(pipe));
9164         } else {
9165                 if (plane_config->tiling)
9166                         offset = I915_READ(DSPTILEOFF(pipe));
9167                 else
9168                         offset = I915_READ(DSPLINOFF(pipe));
9169         }
9170         plane_config->base = base;
9171
9172         val = I915_READ(PIPESRC(pipe));
9173         fb->width = ((val >> 16) & 0xfff) + 1;
9174         fb->height = ((val >> 0) & 0xfff) + 1;
9175
9176         val = I915_READ(DSPSTRIDE(pipe));
9177         fb->pitches[0] = val & 0xffffffc0;
9178
9179         aligned_height = intel_fb_align_height(dev, fb->height,
9180                                                fb->pixel_format,
9181                                                fb->modifier[0]);
9182
9183         plane_config->size = fb->pitches[0] * aligned_height;
9184
9185         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9186                       pipe_name(pipe), fb->width, fb->height,
9187                       fb->bits_per_pixel, base, fb->pitches[0],
9188                       plane_config->size);
9189
9190         plane_config->fb = intel_fb;
9191 }
9192
9193 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9194                                      struct intel_crtc_state *pipe_config)
9195 {
9196         struct drm_device *dev = crtc->base.dev;
9197         struct drm_i915_private *dev_priv = dev->dev_private;
9198         uint32_t tmp;
9199
9200         if (!intel_display_power_is_enabled(dev_priv,
9201                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9202                 return false;
9203
9204         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9205         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9206
9207         tmp = I915_READ(PIPECONF(crtc->pipe));
9208         if (!(tmp & PIPECONF_ENABLE))
9209                 return false;
9210
9211         switch (tmp & PIPECONF_BPC_MASK) {
9212         case PIPECONF_6BPC:
9213                 pipe_config->pipe_bpp = 18;
9214                 break;
9215         case PIPECONF_8BPC:
9216                 pipe_config->pipe_bpp = 24;
9217                 break;
9218         case PIPECONF_10BPC:
9219                 pipe_config->pipe_bpp = 30;
9220                 break;
9221         case PIPECONF_12BPC:
9222                 pipe_config->pipe_bpp = 36;
9223                 break;
9224         default:
9225                 break;
9226         }
9227
9228         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9229                 pipe_config->limited_color_range = true;
9230
9231         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9232                 struct intel_shared_dpll *pll;
9233
9234                 pipe_config->has_pch_encoder = true;
9235
9236                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9237                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9238                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9239
9240                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9241
9242                 if (HAS_PCH_IBX(dev_priv->dev)) {
9243                         pipe_config->shared_dpll =
9244                                 (enum intel_dpll_id) crtc->pipe;
9245                 } else {
9246                         tmp = I915_READ(PCH_DPLL_SEL);
9247                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9248                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9249                         else
9250                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9251                 }
9252
9253                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9254
9255                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9256                                            &pipe_config->dpll_hw_state));
9257
9258                 tmp = pipe_config->dpll_hw_state.dpll;
9259                 pipe_config->pixel_multiplier =
9260                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9261                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9262
9263                 ironlake_pch_clock_get(crtc, pipe_config);
9264         } else {
9265                 pipe_config->pixel_multiplier = 1;
9266         }
9267
9268         intel_get_pipe_timings(crtc, pipe_config);
9269
9270         ironlake_get_pfit_config(crtc, pipe_config);
9271
9272         return true;
9273 }
9274
9275 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9276 {
9277         struct drm_device *dev = dev_priv->dev;
9278         struct intel_crtc *crtc;
9279
9280         for_each_intel_crtc(dev, crtc)
9281                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9282                      pipe_name(crtc->pipe));
9283
9284         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9285         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9286         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9287         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9288         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9289         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9290              "CPU PWM1 enabled\n");
9291         if (IS_HASWELL(dev))
9292                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9293                      "CPU PWM2 enabled\n");
9294         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9295              "PCH PWM1 enabled\n");
9296         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9297              "Utility pin enabled\n");
9298         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9299
9300         /*
9301          * In theory we can still leave IRQs enabled, as long as only the HPD
9302          * interrupts remain enabled. We used to check for that, but since it's
9303          * gen-specific and since we only disable LCPLL after we fully disable
9304          * the interrupts, the check below should be enough.
9305          */
9306         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9307 }
9308
9309 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9310 {
9311         struct drm_device *dev = dev_priv->dev;
9312
9313         if (IS_HASWELL(dev))
9314                 return I915_READ(D_COMP_HSW);
9315         else
9316                 return I915_READ(D_COMP_BDW);
9317 }
9318
9319 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9320 {
9321         struct drm_device *dev = dev_priv->dev;
9322
9323         if (IS_HASWELL(dev)) {
9324                 mutex_lock(&dev_priv->rps.hw_lock);
9325                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9326                                             val))
9327                         DRM_ERROR("Failed to write to D_COMP\n");
9328                 mutex_unlock(&dev_priv->rps.hw_lock);
9329         } else {
9330                 I915_WRITE(D_COMP_BDW, val);
9331                 POSTING_READ(D_COMP_BDW);
9332         }
9333 }
9334
9335 /*
9336  * This function implements pieces of two sequences from BSpec:
9337  * - Sequence for display software to disable LCPLL
9338  * - Sequence for display software to allow package C8+
9339  * The steps implemented here are just the steps that actually touch the LCPLL
9340  * register. Callers should take care of disabling all the display engine
9341  * functions, doing the mode unset, fixing interrupts, etc.
9342  */
9343 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9344                               bool switch_to_fclk, bool allow_power_down)
9345 {
9346         uint32_t val;
9347
9348         assert_can_disable_lcpll(dev_priv);
9349
9350         val = I915_READ(LCPLL_CTL);
9351
9352         if (switch_to_fclk) {
9353                 val |= LCPLL_CD_SOURCE_FCLK;
9354                 I915_WRITE(LCPLL_CTL, val);
9355
9356                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9357                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9358                         DRM_ERROR("Switching to FCLK failed\n");
9359
9360                 val = I915_READ(LCPLL_CTL);
9361         }
9362
9363         val |= LCPLL_PLL_DISABLE;
9364         I915_WRITE(LCPLL_CTL, val);
9365         POSTING_READ(LCPLL_CTL);
9366
9367         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9368                 DRM_ERROR("LCPLL still locked\n");
9369
9370         val = hsw_read_dcomp(dev_priv);
9371         val |= D_COMP_COMP_DISABLE;
9372         hsw_write_dcomp(dev_priv, val);
9373         ndelay(100);
9374
9375         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9376                      1))
9377                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9378
9379         if (allow_power_down) {
9380                 val = I915_READ(LCPLL_CTL);
9381                 val |= LCPLL_POWER_DOWN_ALLOW;
9382                 I915_WRITE(LCPLL_CTL, val);
9383                 POSTING_READ(LCPLL_CTL);
9384         }
9385 }
9386
9387 /*
9388  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9389  * source.
9390  */
9391 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9392 {
9393         uint32_t val;
9394
9395         val = I915_READ(LCPLL_CTL);
9396
9397         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9398                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9399                 return;
9400
9401         /*
9402          * Make sure we're not on PC8 state before disabling PC8, otherwise
9403          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9404          */
9405         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9406
9407         if (val & LCPLL_POWER_DOWN_ALLOW) {
9408                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9409                 I915_WRITE(LCPLL_CTL, val);
9410                 POSTING_READ(LCPLL_CTL);
9411         }
9412
9413         val = hsw_read_dcomp(dev_priv);
9414         val |= D_COMP_COMP_FORCE;
9415         val &= ~D_COMP_COMP_DISABLE;
9416         hsw_write_dcomp(dev_priv, val);
9417
9418         val = I915_READ(LCPLL_CTL);
9419         val &= ~LCPLL_PLL_DISABLE;
9420         I915_WRITE(LCPLL_CTL, val);
9421
9422         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9423                 DRM_ERROR("LCPLL not locked yet\n");
9424
9425         if (val & LCPLL_CD_SOURCE_FCLK) {
9426                 val = I915_READ(LCPLL_CTL);
9427                 val &= ~LCPLL_CD_SOURCE_FCLK;
9428                 I915_WRITE(LCPLL_CTL, val);
9429
9430                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9431                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9432                         DRM_ERROR("Switching back to LCPLL failed\n");
9433         }
9434
9435         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9436         intel_update_cdclk(dev_priv->dev);
9437 }
9438
9439 /*
9440  * Package states C8 and deeper are really deep PC states that can only be
9441  * reached when all the devices on the system allow it, so even if the graphics
9442  * device allows PC8+, it doesn't mean the system will actually get to these
9443  * states. Our driver only allows PC8+ when going into runtime PM.
9444  *
9445  * The requirements for PC8+ are that all the outputs are disabled, the power
9446  * well is disabled and most interrupts are disabled, and these are also
9447  * requirements for runtime PM. When these conditions are met, we manually do
9448  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9449  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9450  * hang the machine.
9451  *
9452  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9453  * the state of some registers, so when we come back from PC8+ we need to
9454  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9455  * need to take care of the registers kept by RC6. Notice that this happens even
9456  * if we don't put the device in PCI D3 state (which is what currently happens
9457  * because of the runtime PM support).
9458  *
9459  * For more, read "Display Sequences for Package C8" on the hardware
9460  * documentation.
9461  */
9462 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9463 {
9464         struct drm_device *dev = dev_priv->dev;
9465         uint32_t val;
9466
9467         DRM_DEBUG_KMS("Enabling package C8+\n");
9468
9469         if (HAS_PCH_LPT_LP(dev)) {
9470                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9471                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9472                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9473         }
9474
9475         lpt_disable_clkout_dp(dev);
9476         hsw_disable_lcpll(dev_priv, true, true);
9477 }
9478
9479 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9480 {
9481         struct drm_device *dev = dev_priv->dev;
9482         uint32_t val;
9483
9484         DRM_DEBUG_KMS("Disabling package C8+\n");
9485
9486         hsw_restore_lcpll(dev_priv);
9487         lpt_init_pch_refclk(dev);
9488
9489         if (HAS_PCH_LPT_LP(dev)) {
9490                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9491                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9492                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9493         }
9494
9495         intel_prepare_ddi(dev);
9496 }
9497
9498 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9499 {
9500         struct drm_device *dev = old_state->dev;
9501         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9502
9503         broxton_set_cdclk(dev, req_cdclk);
9504 }
9505
9506 /* compute the max rate for new configuration */
9507 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9508 {
9509         struct intel_crtc *intel_crtc;
9510         struct intel_crtc_state *crtc_state;
9511         int max_pixel_rate = 0;
9512
9513         for_each_intel_crtc(state->dev, intel_crtc) {
9514                 int pixel_rate;
9515
9516                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9517                 if (IS_ERR(crtc_state))
9518                         return PTR_ERR(crtc_state);
9519
9520                 if (!crtc_state->base.enable)
9521                         continue;
9522
9523                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9524
9525                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9526                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9527                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9528
9529                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9530         }
9531
9532         return max_pixel_rate;
9533 }
9534
9535 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9536 {
9537         struct drm_i915_private *dev_priv = dev->dev_private;
9538         uint32_t val, data;
9539         int ret;
9540
9541         if (WARN((I915_READ(LCPLL_CTL) &
9542                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9543                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9544                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9545                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9546                  "trying to change cdclk frequency with cdclk not enabled\n"))
9547                 return;
9548
9549         mutex_lock(&dev_priv->rps.hw_lock);
9550         ret = sandybridge_pcode_write(dev_priv,
9551                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9552         mutex_unlock(&dev_priv->rps.hw_lock);
9553         if (ret) {
9554                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9555                 return;
9556         }
9557
9558         val = I915_READ(LCPLL_CTL);
9559         val |= LCPLL_CD_SOURCE_FCLK;
9560         I915_WRITE(LCPLL_CTL, val);
9561
9562         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9563                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9564                 DRM_ERROR("Switching to FCLK failed\n");
9565
9566         val = I915_READ(LCPLL_CTL);
9567         val &= ~LCPLL_CLK_FREQ_MASK;
9568
9569         switch (cdclk) {
9570         case 450000:
9571                 val |= LCPLL_CLK_FREQ_450;
9572                 data = 0;
9573                 break;
9574         case 540000:
9575                 val |= LCPLL_CLK_FREQ_54O_BDW;
9576                 data = 1;
9577                 break;
9578         case 337500:
9579                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9580                 data = 2;
9581                 break;
9582         case 675000:
9583                 val |= LCPLL_CLK_FREQ_675_BDW;
9584                 data = 3;
9585                 break;
9586         default:
9587                 WARN(1, "invalid cdclk frequency\n");
9588                 return;
9589         }
9590
9591         I915_WRITE(LCPLL_CTL, val);
9592
9593         val = I915_READ(LCPLL_CTL);
9594         val &= ~LCPLL_CD_SOURCE_FCLK;
9595         I915_WRITE(LCPLL_CTL, val);
9596
9597         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9598                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9599                 DRM_ERROR("Switching back to LCPLL failed\n");
9600
9601         mutex_lock(&dev_priv->rps.hw_lock);
9602         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9603         mutex_unlock(&dev_priv->rps.hw_lock);
9604
9605         intel_update_cdclk(dev);
9606
9607         WARN(cdclk != dev_priv->cdclk_freq,
9608              "cdclk requested %d kHz but got %d kHz\n",
9609              cdclk, dev_priv->cdclk_freq);
9610 }
9611
9612 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9613 {
9614         struct drm_i915_private *dev_priv = to_i915(state->dev);
9615         int max_pixclk = ilk_max_pixel_rate(state);
9616         int cdclk;
9617
9618         /*
9619          * FIXME should also account for plane ratio
9620          * once 64bpp pixel formats are supported.
9621          */
9622         if (max_pixclk > 540000)
9623                 cdclk = 675000;
9624         else if (max_pixclk > 450000)
9625                 cdclk = 540000;
9626         else if (max_pixclk > 337500)
9627                 cdclk = 450000;
9628         else
9629                 cdclk = 337500;
9630
9631         /*
9632          * FIXME move the cdclk caclulation to
9633          * compute_config() so we can fail gracegully.
9634          */
9635         if (cdclk > dev_priv->max_cdclk_freq) {
9636                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9637                           cdclk, dev_priv->max_cdclk_freq);
9638                 cdclk = dev_priv->max_cdclk_freq;
9639         }
9640
9641         to_intel_atomic_state(state)->cdclk = cdclk;
9642
9643         return 0;
9644 }
9645
9646 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9647 {
9648         struct drm_device *dev = old_state->dev;
9649         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9650
9651         broadwell_set_cdclk(dev, req_cdclk);
9652 }
9653
9654 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9655                                       struct intel_crtc_state *crtc_state)
9656 {
9657         if (!intel_ddi_pll_select(crtc, crtc_state))
9658                 return -EINVAL;
9659
9660         crtc->lowfreq_avail = false;
9661
9662         return 0;
9663 }
9664
9665 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9666                                 enum port port,
9667                                 struct intel_crtc_state *pipe_config)
9668 {
9669         switch (port) {
9670         case PORT_A:
9671                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9672                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9673                 break;
9674         case PORT_B:
9675                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9676                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9677                 break;
9678         case PORT_C:
9679                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9680                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9681                 break;
9682         default:
9683                 DRM_ERROR("Incorrect port type\n");
9684         }
9685 }
9686
9687 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9688                                 enum port port,
9689                                 struct intel_crtc_state *pipe_config)
9690 {
9691         u32 temp, dpll_ctl1;
9692
9693         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9694         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9695
9696         switch (pipe_config->ddi_pll_sel) {
9697         case SKL_DPLL0:
9698                 /*
9699                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9700                  * of the shared DPLL framework and thus needs to be read out
9701                  * separately
9702                  */
9703                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9704                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9705                 break;
9706         case SKL_DPLL1:
9707                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9708                 break;
9709         case SKL_DPLL2:
9710                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9711                 break;
9712         case SKL_DPLL3:
9713                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9714                 break;
9715         }
9716 }
9717
9718 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9719                                 enum port port,
9720                                 struct intel_crtc_state *pipe_config)
9721 {
9722         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9723
9724         switch (pipe_config->ddi_pll_sel) {
9725         case PORT_CLK_SEL_WRPLL1:
9726                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9727                 break;
9728         case PORT_CLK_SEL_WRPLL2:
9729                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9730                 break;
9731         case PORT_CLK_SEL_SPLL:
9732                 pipe_config->shared_dpll = DPLL_ID_SPLL;
9733         }
9734 }
9735
9736 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9737                                        struct intel_crtc_state *pipe_config)
9738 {
9739         struct drm_device *dev = crtc->base.dev;
9740         struct drm_i915_private *dev_priv = dev->dev_private;
9741         struct intel_shared_dpll *pll;
9742         enum port port;
9743         uint32_t tmp;
9744
9745         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9746
9747         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9748
9749         if (IS_SKYLAKE(dev))
9750                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9751         else if (IS_BROXTON(dev))
9752                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9753         else
9754                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9755
9756         if (pipe_config->shared_dpll >= 0) {
9757                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9758
9759                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9760                                            &pipe_config->dpll_hw_state));
9761         }
9762
9763         /*
9764          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9765          * DDI E. So just check whether this pipe is wired to DDI E and whether
9766          * the PCH transcoder is on.
9767          */
9768         if (INTEL_INFO(dev)->gen < 9 &&
9769             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9770                 pipe_config->has_pch_encoder = true;
9771
9772                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9773                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9774                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9775
9776                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9777         }
9778 }
9779
9780 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9781                                     struct intel_crtc_state *pipe_config)
9782 {
9783         struct drm_device *dev = crtc->base.dev;
9784         struct drm_i915_private *dev_priv = dev->dev_private;
9785         enum intel_display_power_domain pfit_domain;
9786         uint32_t tmp;
9787
9788         if (!intel_display_power_is_enabled(dev_priv,
9789                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9790                 return false;
9791
9792         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9793         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9794
9795         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9796         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9797                 enum pipe trans_edp_pipe;
9798                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9799                 default:
9800                         WARN(1, "unknown pipe linked to edp transcoder\n");
9801                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9802                 case TRANS_DDI_EDP_INPUT_A_ON:
9803                         trans_edp_pipe = PIPE_A;
9804                         break;
9805                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9806                         trans_edp_pipe = PIPE_B;
9807                         break;
9808                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9809                         trans_edp_pipe = PIPE_C;
9810                         break;
9811                 }
9812
9813                 if (trans_edp_pipe == crtc->pipe)
9814                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9815         }
9816
9817         if (!intel_display_power_is_enabled(dev_priv,
9818                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9819                 return false;
9820
9821         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9822         if (!(tmp & PIPECONF_ENABLE))
9823                 return false;
9824
9825         haswell_get_ddi_port_state(crtc, pipe_config);
9826
9827         intel_get_pipe_timings(crtc, pipe_config);
9828
9829         if (INTEL_INFO(dev)->gen >= 9) {
9830                 skl_init_scalers(dev, crtc, pipe_config);
9831         }
9832
9833         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9834
9835         if (INTEL_INFO(dev)->gen >= 9) {
9836                 pipe_config->scaler_state.scaler_id = -1;
9837                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9838         }
9839
9840         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9841                 if (INTEL_INFO(dev)->gen >= 9)
9842                         skylake_get_pfit_config(crtc, pipe_config);
9843                 else
9844                         ironlake_get_pfit_config(crtc, pipe_config);
9845         }
9846
9847         if (IS_HASWELL(dev))
9848                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9849                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9850
9851         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9852                 pipe_config->pixel_multiplier =
9853                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9854         } else {
9855                 pipe_config->pixel_multiplier = 1;
9856         }
9857
9858         return true;
9859 }
9860
9861 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9862 {
9863         struct drm_device *dev = crtc->dev;
9864         struct drm_i915_private *dev_priv = dev->dev_private;
9865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9866         uint32_t cntl = 0, size = 0;
9867
9868         if (base) {
9869                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9870                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9871                 unsigned int stride = roundup_pow_of_two(width) * 4;
9872
9873                 switch (stride) {
9874                 default:
9875                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9876                                   width, stride);
9877                         stride = 256;
9878                         /* fallthrough */
9879                 case 256:
9880                 case 512:
9881                 case 1024:
9882                 case 2048:
9883                         break;
9884                 }
9885
9886                 cntl |= CURSOR_ENABLE |
9887                         CURSOR_GAMMA_ENABLE |
9888                         CURSOR_FORMAT_ARGB |
9889                         CURSOR_STRIDE(stride);
9890
9891                 size = (height << 12) | width;
9892         }
9893
9894         if (intel_crtc->cursor_cntl != 0 &&
9895             (intel_crtc->cursor_base != base ||
9896              intel_crtc->cursor_size != size ||
9897              intel_crtc->cursor_cntl != cntl)) {
9898                 /* On these chipsets we can only modify the base/size/stride
9899                  * whilst the cursor is disabled.
9900                  */
9901                 I915_WRITE(CURCNTR(PIPE_A), 0);
9902                 POSTING_READ(CURCNTR(PIPE_A));
9903                 intel_crtc->cursor_cntl = 0;
9904         }
9905
9906         if (intel_crtc->cursor_base != base) {
9907                 I915_WRITE(CURBASE(PIPE_A), base);
9908                 intel_crtc->cursor_base = base;
9909         }
9910
9911         if (intel_crtc->cursor_size != size) {
9912                 I915_WRITE(CURSIZE, size);
9913                 intel_crtc->cursor_size = size;
9914         }
9915
9916         if (intel_crtc->cursor_cntl != cntl) {
9917                 I915_WRITE(CURCNTR(PIPE_A), cntl);
9918                 POSTING_READ(CURCNTR(PIPE_A));
9919                 intel_crtc->cursor_cntl = cntl;
9920         }
9921 }
9922
9923 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9924 {
9925         struct drm_device *dev = crtc->dev;
9926         struct drm_i915_private *dev_priv = dev->dev_private;
9927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9928         int pipe = intel_crtc->pipe;
9929         uint32_t cntl;
9930
9931         cntl = 0;
9932         if (base) {
9933                 cntl = MCURSOR_GAMMA_ENABLE;
9934                 switch (intel_crtc->base.cursor->state->crtc_w) {
9935                         case 64:
9936                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9937                                 break;
9938                         case 128:
9939                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9940                                 break;
9941                         case 256:
9942                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9943                                 break;
9944                         default:
9945                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9946                                 return;
9947                 }
9948                 cntl |= pipe << 28; /* Connect to correct pipe */
9949
9950                 if (HAS_DDI(dev))
9951                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9952         }
9953
9954         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9955                 cntl |= CURSOR_ROTATE_180;
9956
9957         if (intel_crtc->cursor_cntl != cntl) {
9958                 I915_WRITE(CURCNTR(pipe), cntl);
9959                 POSTING_READ(CURCNTR(pipe));
9960                 intel_crtc->cursor_cntl = cntl;
9961         }
9962
9963         /* and commit changes on next vblank */
9964         I915_WRITE(CURBASE(pipe), base);
9965         POSTING_READ(CURBASE(pipe));
9966
9967         intel_crtc->cursor_base = base;
9968 }
9969
9970 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9971 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9972                                      bool on)
9973 {
9974         struct drm_device *dev = crtc->dev;
9975         struct drm_i915_private *dev_priv = dev->dev_private;
9976         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9977         int pipe = intel_crtc->pipe;
9978         struct drm_plane_state *cursor_state = crtc->cursor->state;
9979         int x = cursor_state->crtc_x;
9980         int y = cursor_state->crtc_y;
9981         u32 base = 0, pos = 0;
9982
9983         if (on)
9984                 base = intel_crtc->cursor_addr;
9985
9986         if (x >= intel_crtc->config->pipe_src_w)
9987                 base = 0;
9988
9989         if (y >= intel_crtc->config->pipe_src_h)
9990                 base = 0;
9991
9992         if (x < 0) {
9993                 if (x + cursor_state->crtc_w <= 0)
9994                         base = 0;
9995
9996                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9997                 x = -x;
9998         }
9999         pos |= x << CURSOR_X_SHIFT;
10000
10001         if (y < 0) {
10002                 if (y + cursor_state->crtc_h <= 0)
10003                         base = 0;
10004
10005                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10006                 y = -y;
10007         }
10008         pos |= y << CURSOR_Y_SHIFT;
10009
10010         if (base == 0 && intel_crtc->cursor_base == 0)
10011                 return;
10012
10013         I915_WRITE(CURPOS(pipe), pos);
10014
10015         /* ILK+ do this automagically */
10016         if (HAS_GMCH_DISPLAY(dev) &&
10017             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10018                 base += (cursor_state->crtc_h *
10019                          cursor_state->crtc_w - 1) * 4;
10020         }
10021
10022         if (IS_845G(dev) || IS_I865G(dev))
10023                 i845_update_cursor(crtc, base);
10024         else
10025                 i9xx_update_cursor(crtc, base);
10026 }
10027
10028 static bool cursor_size_ok(struct drm_device *dev,
10029                            uint32_t width, uint32_t height)
10030 {
10031         if (width == 0 || height == 0)
10032                 return false;
10033
10034         /*
10035          * 845g/865g are special in that they are only limited by
10036          * the width of their cursors, the height is arbitrary up to
10037          * the precision of the register. Everything else requires
10038          * square cursors, limited to a few power-of-two sizes.
10039          */
10040         if (IS_845G(dev) || IS_I865G(dev)) {
10041                 if ((width & 63) != 0)
10042                         return false;
10043
10044                 if (width > (IS_845G(dev) ? 64 : 512))
10045                         return false;
10046
10047                 if (height > 1023)
10048                         return false;
10049         } else {
10050                 switch (width | height) {
10051                 case 256:
10052                 case 128:
10053                         if (IS_GEN2(dev))
10054                                 return false;
10055                 case 64:
10056                         break;
10057                 default:
10058                         return false;
10059                 }
10060         }
10061
10062         return true;
10063 }
10064
10065 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10066                                  u16 *blue, uint32_t start, uint32_t size)
10067 {
10068         int end = (start + size > 256) ? 256 : start + size, i;
10069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10070
10071         for (i = start; i < end; i++) {
10072                 intel_crtc->lut_r[i] = red[i] >> 8;
10073                 intel_crtc->lut_g[i] = green[i] >> 8;
10074                 intel_crtc->lut_b[i] = blue[i] >> 8;
10075         }
10076
10077         intel_crtc_load_lut(crtc);
10078 }
10079
10080 /* VESA 640x480x72Hz mode to set on the pipe */
10081 static struct drm_display_mode load_detect_mode = {
10082         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10083                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10084 };
10085
10086 struct drm_framebuffer *
10087 __intel_framebuffer_create(struct drm_device *dev,
10088                            struct drm_mode_fb_cmd2 *mode_cmd,
10089                            struct drm_i915_gem_object *obj)
10090 {
10091         struct intel_framebuffer *intel_fb;
10092         int ret;
10093
10094         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10095         if (!intel_fb) {
10096                 drm_gem_object_unreference(&obj->base);
10097                 return ERR_PTR(-ENOMEM);
10098         }
10099
10100         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10101         if (ret)
10102                 goto err;
10103
10104         return &intel_fb->base;
10105 err:
10106         drm_gem_object_unreference(&obj->base);
10107         kfree(intel_fb);
10108
10109         return ERR_PTR(ret);
10110 }
10111
10112 static struct drm_framebuffer *
10113 intel_framebuffer_create(struct drm_device *dev,
10114                          struct drm_mode_fb_cmd2 *mode_cmd,
10115                          struct drm_i915_gem_object *obj)
10116 {
10117         struct drm_framebuffer *fb;
10118         int ret;
10119
10120         ret = i915_mutex_lock_interruptible(dev);
10121         if (ret)
10122                 return ERR_PTR(ret);
10123         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10124         mutex_unlock(&dev->struct_mutex);
10125
10126         return fb;
10127 }
10128
10129 static u32
10130 intel_framebuffer_pitch_for_width(int width, int bpp)
10131 {
10132         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10133         return ALIGN(pitch, 64);
10134 }
10135
10136 static u32
10137 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10138 {
10139         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10140         return PAGE_ALIGN(pitch * mode->vdisplay);
10141 }
10142
10143 static struct drm_framebuffer *
10144 intel_framebuffer_create_for_mode(struct drm_device *dev,
10145                                   struct drm_display_mode *mode,
10146                                   int depth, int bpp)
10147 {
10148         struct drm_i915_gem_object *obj;
10149         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10150
10151         obj = i915_gem_alloc_object(dev,
10152                                     intel_framebuffer_size_for_mode(mode, bpp));
10153         if (obj == NULL)
10154                 return ERR_PTR(-ENOMEM);
10155
10156         mode_cmd.width = mode->hdisplay;
10157         mode_cmd.height = mode->vdisplay;
10158         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10159                                                                 bpp);
10160         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10161
10162         return intel_framebuffer_create(dev, &mode_cmd, obj);
10163 }
10164
10165 static struct drm_framebuffer *
10166 mode_fits_in_fbdev(struct drm_device *dev,
10167                    struct drm_display_mode *mode)
10168 {
10169 #ifdef CONFIG_DRM_FBDEV_EMULATION
10170         struct drm_i915_private *dev_priv = dev->dev_private;
10171         struct drm_i915_gem_object *obj;
10172         struct drm_framebuffer *fb;
10173
10174         if (!dev_priv->fbdev)
10175                 return NULL;
10176
10177         if (!dev_priv->fbdev->fb)
10178                 return NULL;
10179
10180         obj = dev_priv->fbdev->fb->obj;
10181         BUG_ON(!obj);
10182
10183         fb = &dev_priv->fbdev->fb->base;
10184         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10185                                                                fb->bits_per_pixel))
10186                 return NULL;
10187
10188         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10189                 return NULL;
10190
10191         return fb;
10192 #else
10193         return NULL;
10194 #endif
10195 }
10196
10197 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10198                                            struct drm_crtc *crtc,
10199                                            struct drm_display_mode *mode,
10200                                            struct drm_framebuffer *fb,
10201                                            int x, int y)
10202 {
10203         struct drm_plane_state *plane_state;
10204         int hdisplay, vdisplay;
10205         int ret;
10206
10207         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10208         if (IS_ERR(plane_state))
10209                 return PTR_ERR(plane_state);
10210
10211         if (mode)
10212                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10213         else
10214                 hdisplay = vdisplay = 0;
10215
10216         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10217         if (ret)
10218                 return ret;
10219         drm_atomic_set_fb_for_plane(plane_state, fb);
10220         plane_state->crtc_x = 0;
10221         plane_state->crtc_y = 0;
10222         plane_state->crtc_w = hdisplay;
10223         plane_state->crtc_h = vdisplay;
10224         plane_state->src_x = x << 16;
10225         plane_state->src_y = y << 16;
10226         plane_state->src_w = hdisplay << 16;
10227         plane_state->src_h = vdisplay << 16;
10228
10229         return 0;
10230 }
10231
10232 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10233                                 struct drm_display_mode *mode,
10234                                 struct intel_load_detect_pipe *old,
10235                                 struct drm_modeset_acquire_ctx *ctx)
10236 {
10237         struct intel_crtc *intel_crtc;
10238         struct intel_encoder *intel_encoder =
10239                 intel_attached_encoder(connector);
10240         struct drm_crtc *possible_crtc;
10241         struct drm_encoder *encoder = &intel_encoder->base;
10242         struct drm_crtc *crtc = NULL;
10243         struct drm_device *dev = encoder->dev;
10244         struct drm_framebuffer *fb;
10245         struct drm_mode_config *config = &dev->mode_config;
10246         struct drm_atomic_state *state = NULL;
10247         struct drm_connector_state *connector_state;
10248         struct intel_crtc_state *crtc_state;
10249         int ret, i = -1;
10250
10251         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10252                       connector->base.id, connector->name,
10253                       encoder->base.id, encoder->name);
10254
10255 retry:
10256         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10257         if (ret)
10258                 goto fail;
10259
10260         /*
10261          * Algorithm gets a little messy:
10262          *
10263          *   - if the connector already has an assigned crtc, use it (but make
10264          *     sure it's on first)
10265          *
10266          *   - try to find the first unused crtc that can drive this connector,
10267          *     and use that if we find one
10268          */
10269
10270         /* See if we already have a CRTC for this connector */
10271         if (encoder->crtc) {
10272                 crtc = encoder->crtc;
10273
10274                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10275                 if (ret)
10276                         goto fail;
10277                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10278                 if (ret)
10279                         goto fail;
10280
10281                 old->dpms_mode = connector->dpms;
10282                 old->load_detect_temp = false;
10283
10284                 /* Make sure the crtc and connector are running */
10285                 if (connector->dpms != DRM_MODE_DPMS_ON)
10286                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10287
10288                 return true;
10289         }
10290
10291         /* Find an unused one (if possible) */
10292         for_each_crtc(dev, possible_crtc) {
10293                 i++;
10294                 if (!(encoder->possible_crtcs & (1 << i)))
10295                         continue;
10296                 if (possible_crtc->state->enable)
10297                         continue;
10298
10299                 crtc = possible_crtc;
10300                 break;
10301         }
10302
10303         /*
10304          * If we didn't find an unused CRTC, don't use any.
10305          */
10306         if (!crtc) {
10307                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10308                 goto fail;
10309         }
10310
10311         ret = drm_modeset_lock(&crtc->mutex, ctx);
10312         if (ret)
10313                 goto fail;
10314         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10315         if (ret)
10316                 goto fail;
10317
10318         intel_crtc = to_intel_crtc(crtc);
10319         old->dpms_mode = connector->dpms;
10320         old->load_detect_temp = true;
10321         old->release_fb = NULL;
10322
10323         state = drm_atomic_state_alloc(dev);
10324         if (!state)
10325                 return false;
10326
10327         state->acquire_ctx = ctx;
10328
10329         connector_state = drm_atomic_get_connector_state(state, connector);
10330         if (IS_ERR(connector_state)) {
10331                 ret = PTR_ERR(connector_state);
10332                 goto fail;
10333         }
10334
10335         connector_state->crtc = crtc;
10336         connector_state->best_encoder = &intel_encoder->base;
10337
10338         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10339         if (IS_ERR(crtc_state)) {
10340                 ret = PTR_ERR(crtc_state);
10341                 goto fail;
10342         }
10343
10344         crtc_state->base.active = crtc_state->base.enable = true;
10345
10346         if (!mode)
10347                 mode = &load_detect_mode;
10348
10349         /* We need a framebuffer large enough to accommodate all accesses
10350          * that the plane may generate whilst we perform load detection.
10351          * We can not rely on the fbcon either being present (we get called
10352          * during its initialisation to detect all boot displays, or it may
10353          * not even exist) or that it is large enough to satisfy the
10354          * requested mode.
10355          */
10356         fb = mode_fits_in_fbdev(dev, mode);
10357         if (fb == NULL) {
10358                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10359                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10360                 old->release_fb = fb;
10361         } else
10362                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10363         if (IS_ERR(fb)) {
10364                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10365                 goto fail;
10366         }
10367
10368         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10369         if (ret)
10370                 goto fail;
10371
10372         drm_mode_copy(&crtc_state->base.mode, mode);
10373
10374         if (drm_atomic_commit(state)) {
10375                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10376                 if (old->release_fb)
10377                         old->release_fb->funcs->destroy(old->release_fb);
10378                 goto fail;
10379         }
10380         crtc->primary->crtc = crtc;
10381
10382         /* let the connector get through one full cycle before testing */
10383         intel_wait_for_vblank(dev, intel_crtc->pipe);
10384         return true;
10385
10386 fail:
10387         drm_atomic_state_free(state);
10388         state = NULL;
10389
10390         if (ret == -EDEADLK) {
10391                 drm_modeset_backoff(ctx);
10392                 goto retry;
10393         }
10394
10395         return false;
10396 }
10397
10398 void intel_release_load_detect_pipe(struct drm_connector *connector,
10399                                     struct intel_load_detect_pipe *old,
10400                                     struct drm_modeset_acquire_ctx *ctx)
10401 {
10402         struct drm_device *dev = connector->dev;
10403         struct intel_encoder *intel_encoder =
10404                 intel_attached_encoder(connector);
10405         struct drm_encoder *encoder = &intel_encoder->base;
10406         struct drm_crtc *crtc = encoder->crtc;
10407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10408         struct drm_atomic_state *state;
10409         struct drm_connector_state *connector_state;
10410         struct intel_crtc_state *crtc_state;
10411         int ret;
10412
10413         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10414                       connector->base.id, connector->name,
10415                       encoder->base.id, encoder->name);
10416
10417         if (old->load_detect_temp) {
10418                 state = drm_atomic_state_alloc(dev);
10419                 if (!state)
10420                         goto fail;
10421
10422                 state->acquire_ctx = ctx;
10423
10424                 connector_state = drm_atomic_get_connector_state(state, connector);
10425                 if (IS_ERR(connector_state))
10426                         goto fail;
10427
10428                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10429                 if (IS_ERR(crtc_state))
10430                         goto fail;
10431
10432                 connector_state->best_encoder = NULL;
10433                 connector_state->crtc = NULL;
10434
10435                 crtc_state->base.enable = crtc_state->base.active = false;
10436
10437                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10438                                                       0, 0);
10439                 if (ret)
10440                         goto fail;
10441
10442                 ret = drm_atomic_commit(state);
10443                 if (ret)
10444                         goto fail;
10445
10446                 if (old->release_fb) {
10447                         drm_framebuffer_unregister_private(old->release_fb);
10448                         drm_framebuffer_unreference(old->release_fb);
10449                 }
10450
10451                 return;
10452         }
10453
10454         /* Switch crtc and encoder back off if necessary */
10455         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10456                 connector->funcs->dpms(connector, old->dpms_mode);
10457
10458         return;
10459 fail:
10460         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10461         drm_atomic_state_free(state);
10462 }
10463
10464 static int i9xx_pll_refclk(struct drm_device *dev,
10465                            const struct intel_crtc_state *pipe_config)
10466 {
10467         struct drm_i915_private *dev_priv = dev->dev_private;
10468         u32 dpll = pipe_config->dpll_hw_state.dpll;
10469
10470         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10471                 return dev_priv->vbt.lvds_ssc_freq;
10472         else if (HAS_PCH_SPLIT(dev))
10473                 return 120000;
10474         else if (!IS_GEN2(dev))
10475                 return 96000;
10476         else
10477                 return 48000;
10478 }
10479
10480 /* Returns the clock of the currently programmed mode of the given pipe. */
10481 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10482                                 struct intel_crtc_state *pipe_config)
10483 {
10484         struct drm_device *dev = crtc->base.dev;
10485         struct drm_i915_private *dev_priv = dev->dev_private;
10486         int pipe = pipe_config->cpu_transcoder;
10487         u32 dpll = pipe_config->dpll_hw_state.dpll;
10488         u32 fp;
10489         intel_clock_t clock;
10490         int port_clock;
10491         int refclk = i9xx_pll_refclk(dev, pipe_config);
10492
10493         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10494                 fp = pipe_config->dpll_hw_state.fp0;
10495         else
10496                 fp = pipe_config->dpll_hw_state.fp1;
10497
10498         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10499         if (IS_PINEVIEW(dev)) {
10500                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10501                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10502         } else {
10503                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10504                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10505         }
10506
10507         if (!IS_GEN2(dev)) {
10508                 if (IS_PINEVIEW(dev))
10509                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10510                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10511                 else
10512                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10513                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10514
10515                 switch (dpll & DPLL_MODE_MASK) {
10516                 case DPLLB_MODE_DAC_SERIAL:
10517                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10518                                 5 : 10;
10519                         break;
10520                 case DPLLB_MODE_LVDS:
10521                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10522                                 7 : 14;
10523                         break;
10524                 default:
10525                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10526                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10527                         return;
10528                 }
10529
10530                 if (IS_PINEVIEW(dev))
10531                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10532                 else
10533                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10534         } else {
10535                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10536                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10537
10538                 if (is_lvds) {
10539                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10540                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10541
10542                         if (lvds & LVDS_CLKB_POWER_UP)
10543                                 clock.p2 = 7;
10544                         else
10545                                 clock.p2 = 14;
10546                 } else {
10547                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10548                                 clock.p1 = 2;
10549                         else {
10550                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10551                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10552                         }
10553                         if (dpll & PLL_P2_DIVIDE_BY_4)
10554                                 clock.p2 = 4;
10555                         else
10556                                 clock.p2 = 2;
10557                 }
10558
10559                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10560         }
10561
10562         /*
10563          * This value includes pixel_multiplier. We will use
10564          * port_clock to compute adjusted_mode.crtc_clock in the
10565          * encoder's get_config() function.
10566          */
10567         pipe_config->port_clock = port_clock;
10568 }
10569
10570 int intel_dotclock_calculate(int link_freq,
10571                              const struct intel_link_m_n *m_n)
10572 {
10573         /*
10574          * The calculation for the data clock is:
10575          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10576          * But we want to avoid losing precison if possible, so:
10577          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10578          *
10579          * and the link clock is simpler:
10580          * link_clock = (m * link_clock) / n
10581          */
10582
10583         if (!m_n->link_n)
10584                 return 0;
10585
10586         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10587 }
10588
10589 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10590                                    struct intel_crtc_state *pipe_config)
10591 {
10592         struct drm_device *dev = crtc->base.dev;
10593
10594         /* read out port_clock from the DPLL */
10595         i9xx_crtc_clock_get(crtc, pipe_config);
10596
10597         /*
10598          * This value does not include pixel_multiplier.
10599          * We will check that port_clock and adjusted_mode.crtc_clock
10600          * agree once we know their relationship in the encoder's
10601          * get_config() function.
10602          */
10603         pipe_config->base.adjusted_mode.crtc_clock =
10604                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10605                                          &pipe_config->fdi_m_n);
10606 }
10607
10608 /** Returns the currently programmed mode of the given pipe. */
10609 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10610                                              struct drm_crtc *crtc)
10611 {
10612         struct drm_i915_private *dev_priv = dev->dev_private;
10613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10614         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10615         struct drm_display_mode *mode;
10616         struct intel_crtc_state pipe_config;
10617         int htot = I915_READ(HTOTAL(cpu_transcoder));
10618         int hsync = I915_READ(HSYNC(cpu_transcoder));
10619         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10620         int vsync = I915_READ(VSYNC(cpu_transcoder));
10621         enum pipe pipe = intel_crtc->pipe;
10622
10623         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10624         if (!mode)
10625                 return NULL;
10626
10627         /*
10628          * Construct a pipe_config sufficient for getting the clock info
10629          * back out of crtc_clock_get.
10630          *
10631          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10632          * to use a real value here instead.
10633          */
10634         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10635         pipe_config.pixel_multiplier = 1;
10636         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10637         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10638         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10639         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10640
10641         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10642         mode->hdisplay = (htot & 0xffff) + 1;
10643         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10644         mode->hsync_start = (hsync & 0xffff) + 1;
10645         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10646         mode->vdisplay = (vtot & 0xffff) + 1;
10647         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10648         mode->vsync_start = (vsync & 0xffff) + 1;
10649         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10650
10651         drm_mode_set_name(mode);
10652
10653         return mode;
10654 }
10655
10656 void intel_mark_busy(struct drm_device *dev)
10657 {
10658         struct drm_i915_private *dev_priv = dev->dev_private;
10659
10660         if (dev_priv->mm.busy)
10661                 return;
10662
10663         intel_runtime_pm_get(dev_priv);
10664         i915_update_gfx_val(dev_priv);
10665         if (INTEL_INFO(dev)->gen >= 6)
10666                 gen6_rps_busy(dev_priv);
10667         dev_priv->mm.busy = true;
10668 }
10669
10670 void intel_mark_idle(struct drm_device *dev)
10671 {
10672         struct drm_i915_private *dev_priv = dev->dev_private;
10673
10674         if (!dev_priv->mm.busy)
10675                 return;
10676
10677         dev_priv->mm.busy = false;
10678
10679         if (INTEL_INFO(dev)->gen >= 6)
10680                 gen6_rps_idle(dev->dev_private);
10681
10682         intel_runtime_pm_put(dev_priv);
10683 }
10684
10685 static void intel_crtc_destroy(struct drm_crtc *crtc)
10686 {
10687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10688         struct drm_device *dev = crtc->dev;
10689         struct intel_unpin_work *work;
10690
10691         spin_lock_irq(&dev->event_lock);
10692         work = intel_crtc->unpin_work;
10693         intel_crtc->unpin_work = NULL;
10694         spin_unlock_irq(&dev->event_lock);
10695
10696         if (work) {
10697                 cancel_work_sync(&work->work);
10698                 kfree(work);
10699         }
10700
10701         drm_crtc_cleanup(crtc);
10702
10703         kfree(intel_crtc);
10704 }
10705
10706 static void intel_unpin_work_fn(struct work_struct *__work)
10707 {
10708         struct intel_unpin_work *work =
10709                 container_of(__work, struct intel_unpin_work, work);
10710         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10711         struct drm_device *dev = crtc->base.dev;
10712         struct drm_plane *primary = crtc->base.primary;
10713
10714         mutex_lock(&dev->struct_mutex);
10715         intel_unpin_fb_obj(work->old_fb, primary->state);
10716         drm_gem_object_unreference(&work->pending_flip_obj->base);
10717
10718         if (work->flip_queued_req)
10719                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10720         mutex_unlock(&dev->struct_mutex);
10721
10722         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10723         drm_framebuffer_unreference(work->old_fb);
10724
10725         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10726         atomic_dec(&crtc->unpin_work_count);
10727
10728         kfree(work);
10729 }
10730
10731 static void do_intel_finish_page_flip(struct drm_device *dev,
10732                                       struct drm_crtc *crtc)
10733 {
10734         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10735         struct intel_unpin_work *work;
10736         unsigned long flags;
10737
10738         /* Ignore early vblank irqs */
10739         if (intel_crtc == NULL)
10740                 return;
10741
10742         /*
10743          * This is called both by irq handlers and the reset code (to complete
10744          * lost pageflips) so needs the full irqsave spinlocks.
10745          */
10746         spin_lock_irqsave(&dev->event_lock, flags);
10747         work = intel_crtc->unpin_work;
10748
10749         /* Ensure we don't miss a work->pending update ... */
10750         smp_rmb();
10751
10752         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10753                 spin_unlock_irqrestore(&dev->event_lock, flags);
10754                 return;
10755         }
10756
10757         page_flip_completed(intel_crtc);
10758
10759         spin_unlock_irqrestore(&dev->event_lock, flags);
10760 }
10761
10762 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10763 {
10764         struct drm_i915_private *dev_priv = dev->dev_private;
10765         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10766
10767         do_intel_finish_page_flip(dev, crtc);
10768 }
10769
10770 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10771 {
10772         struct drm_i915_private *dev_priv = dev->dev_private;
10773         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10774
10775         do_intel_finish_page_flip(dev, crtc);
10776 }
10777
10778 /* Is 'a' after or equal to 'b'? */
10779 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10780 {
10781         return !((a - b) & 0x80000000);
10782 }
10783
10784 static bool page_flip_finished(struct intel_crtc *crtc)
10785 {
10786         struct drm_device *dev = crtc->base.dev;
10787         struct drm_i915_private *dev_priv = dev->dev_private;
10788
10789         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10790             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10791                 return true;
10792
10793         /*
10794          * The relevant registers doen't exist on pre-ctg.
10795          * As the flip done interrupt doesn't trigger for mmio
10796          * flips on gmch platforms, a flip count check isn't
10797          * really needed there. But since ctg has the registers,
10798          * include it in the check anyway.
10799          */
10800         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10801                 return true;
10802
10803         /*
10804          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10805          * used the same base address. In that case the mmio flip might
10806          * have completed, but the CS hasn't even executed the flip yet.
10807          *
10808          * A flip count check isn't enough as the CS might have updated
10809          * the base address just after start of vblank, but before we
10810          * managed to process the interrupt. This means we'd complete the
10811          * CS flip too soon.
10812          *
10813          * Combining both checks should get us a good enough result. It may
10814          * still happen that the CS flip has been executed, but has not
10815          * yet actually completed. But in case the base address is the same
10816          * anyway, we don't really care.
10817          */
10818         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10819                 crtc->unpin_work->gtt_offset &&
10820                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10821                                     crtc->unpin_work->flip_count);
10822 }
10823
10824 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10825 {
10826         struct drm_i915_private *dev_priv = dev->dev_private;
10827         struct intel_crtc *intel_crtc =
10828                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10829         unsigned long flags;
10830
10831
10832         /*
10833          * This is called both by irq handlers and the reset code (to complete
10834          * lost pageflips) so needs the full irqsave spinlocks.
10835          *
10836          * NB: An MMIO update of the plane base pointer will also
10837          * generate a page-flip completion irq, i.e. every modeset
10838          * is also accompanied by a spurious intel_prepare_page_flip().
10839          */
10840         spin_lock_irqsave(&dev->event_lock, flags);
10841         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10842                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10843         spin_unlock_irqrestore(&dev->event_lock, flags);
10844 }
10845
10846 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10847 {
10848         /* Ensure that the work item is consistent when activating it ... */
10849         smp_wmb();
10850         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10851         /* and that it is marked active as soon as the irq could fire. */
10852         smp_wmb();
10853 }
10854
10855 static int intel_gen2_queue_flip(struct drm_device *dev,
10856                                  struct drm_crtc *crtc,
10857                                  struct drm_framebuffer *fb,
10858                                  struct drm_i915_gem_object *obj,
10859                                  struct drm_i915_gem_request *req,
10860                                  uint32_t flags)
10861 {
10862         struct intel_engine_cs *ring = req->ring;
10863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10864         u32 flip_mask;
10865         int ret;
10866
10867         ret = intel_ring_begin(req, 6);
10868         if (ret)
10869                 return ret;
10870
10871         /* Can't queue multiple flips, so wait for the previous
10872          * one to finish before executing the next.
10873          */
10874         if (intel_crtc->plane)
10875                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10876         else
10877                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10878         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10879         intel_ring_emit(ring, MI_NOOP);
10880         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10881                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10882         intel_ring_emit(ring, fb->pitches[0]);
10883         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10884         intel_ring_emit(ring, 0); /* aux display base address, unused */
10885
10886         intel_mark_page_flip_active(intel_crtc->unpin_work);
10887         return 0;
10888 }
10889
10890 static int intel_gen3_queue_flip(struct drm_device *dev,
10891                                  struct drm_crtc *crtc,
10892                                  struct drm_framebuffer *fb,
10893                                  struct drm_i915_gem_object *obj,
10894                                  struct drm_i915_gem_request *req,
10895                                  uint32_t flags)
10896 {
10897         struct intel_engine_cs *ring = req->ring;
10898         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10899         u32 flip_mask;
10900         int ret;
10901
10902         ret = intel_ring_begin(req, 6);
10903         if (ret)
10904                 return ret;
10905
10906         if (intel_crtc->plane)
10907                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10908         else
10909                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10910         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10911         intel_ring_emit(ring, MI_NOOP);
10912         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10913                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10914         intel_ring_emit(ring, fb->pitches[0]);
10915         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10916         intel_ring_emit(ring, MI_NOOP);
10917
10918         intel_mark_page_flip_active(intel_crtc->unpin_work);
10919         return 0;
10920 }
10921
10922 static int intel_gen4_queue_flip(struct drm_device *dev,
10923                                  struct drm_crtc *crtc,
10924                                  struct drm_framebuffer *fb,
10925                                  struct drm_i915_gem_object *obj,
10926                                  struct drm_i915_gem_request *req,
10927                                  uint32_t flags)
10928 {
10929         struct intel_engine_cs *ring = req->ring;
10930         struct drm_i915_private *dev_priv = dev->dev_private;
10931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10932         uint32_t pf, pipesrc;
10933         int ret;
10934
10935         ret = intel_ring_begin(req, 4);
10936         if (ret)
10937                 return ret;
10938
10939         /* i965+ uses the linear or tiled offsets from the
10940          * Display Registers (which do not change across a page-flip)
10941          * so we need only reprogram the base address.
10942          */
10943         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10944                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10945         intel_ring_emit(ring, fb->pitches[0]);
10946         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10947                         obj->tiling_mode);
10948
10949         /* XXX Enabling the panel-fitter across page-flip is so far
10950          * untested on non-native modes, so ignore it for now.
10951          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10952          */
10953         pf = 0;
10954         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10955         intel_ring_emit(ring, pf | pipesrc);
10956
10957         intel_mark_page_flip_active(intel_crtc->unpin_work);
10958         return 0;
10959 }
10960
10961 static int intel_gen6_queue_flip(struct drm_device *dev,
10962                                  struct drm_crtc *crtc,
10963                                  struct drm_framebuffer *fb,
10964                                  struct drm_i915_gem_object *obj,
10965                                  struct drm_i915_gem_request *req,
10966                                  uint32_t flags)
10967 {
10968         struct intel_engine_cs *ring = req->ring;
10969         struct drm_i915_private *dev_priv = dev->dev_private;
10970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10971         uint32_t pf, pipesrc;
10972         int ret;
10973
10974         ret = intel_ring_begin(req, 4);
10975         if (ret)
10976                 return ret;
10977
10978         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10979                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10980         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10981         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10982
10983         /* Contrary to the suggestions in the documentation,
10984          * "Enable Panel Fitter" does not seem to be required when page
10985          * flipping with a non-native mode, and worse causes a normal
10986          * modeset to fail.
10987          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10988          */
10989         pf = 0;
10990         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10991         intel_ring_emit(ring, pf | pipesrc);
10992
10993         intel_mark_page_flip_active(intel_crtc->unpin_work);
10994         return 0;
10995 }
10996
10997 static int intel_gen7_queue_flip(struct drm_device *dev,
10998                                  struct drm_crtc *crtc,
10999                                  struct drm_framebuffer *fb,
11000                                  struct drm_i915_gem_object *obj,
11001                                  struct drm_i915_gem_request *req,
11002                                  uint32_t flags)
11003 {
11004         struct intel_engine_cs *ring = req->ring;
11005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11006         uint32_t plane_bit = 0;
11007         int len, ret;
11008
11009         switch (intel_crtc->plane) {
11010         case PLANE_A:
11011                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11012                 break;
11013         case PLANE_B:
11014                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11015                 break;
11016         case PLANE_C:
11017                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11018                 break;
11019         default:
11020                 WARN_ONCE(1, "unknown plane in flip command\n");
11021                 return -ENODEV;
11022         }
11023
11024         len = 4;
11025         if (ring->id == RCS) {
11026                 len += 6;
11027                 /*
11028                  * On Gen 8, SRM is now taking an extra dword to accommodate
11029                  * 48bits addresses, and we need a NOOP for the batch size to
11030                  * stay even.
11031                  */
11032                 if (IS_GEN8(dev))
11033                         len += 2;
11034         }
11035
11036         /*
11037          * BSpec MI_DISPLAY_FLIP for IVB:
11038          * "The full packet must be contained within the same cache line."
11039          *
11040          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11041          * cacheline, if we ever start emitting more commands before
11042          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11043          * then do the cacheline alignment, and finally emit the
11044          * MI_DISPLAY_FLIP.
11045          */
11046         ret = intel_ring_cacheline_align(req);
11047         if (ret)
11048                 return ret;
11049
11050         ret = intel_ring_begin(req, len);
11051         if (ret)
11052                 return ret;
11053
11054         /* Unmask the flip-done completion message. Note that the bspec says that
11055          * we should do this for both the BCS and RCS, and that we must not unmask
11056          * more than one flip event at any time (or ensure that one flip message
11057          * can be sent by waiting for flip-done prior to queueing new flips).
11058          * Experimentation says that BCS works despite DERRMR masking all
11059          * flip-done completion events and that unmasking all planes at once
11060          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11061          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11062          */
11063         if (ring->id == RCS) {
11064                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11065                 intel_ring_emit(ring, DERRMR);
11066                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11067                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11068                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11069                 if (IS_GEN8(dev))
11070                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11071                                               MI_SRM_LRM_GLOBAL_GTT);
11072                 else
11073                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11074                                               MI_SRM_LRM_GLOBAL_GTT);
11075                 intel_ring_emit(ring, DERRMR);
11076                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11077                 if (IS_GEN8(dev)) {
11078                         intel_ring_emit(ring, 0);
11079                         intel_ring_emit(ring, MI_NOOP);
11080                 }
11081         }
11082
11083         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11084         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11085         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11086         intel_ring_emit(ring, (MI_NOOP));
11087
11088         intel_mark_page_flip_active(intel_crtc->unpin_work);
11089         return 0;
11090 }
11091
11092 static bool use_mmio_flip(struct intel_engine_cs *ring,
11093                           struct drm_i915_gem_object *obj)
11094 {
11095         /*
11096          * This is not being used for older platforms, because
11097          * non-availability of flip done interrupt forces us to use
11098          * CS flips. Older platforms derive flip done using some clever
11099          * tricks involving the flip_pending status bits and vblank irqs.
11100          * So using MMIO flips there would disrupt this mechanism.
11101          */
11102
11103         if (ring == NULL)
11104                 return true;
11105
11106         if (INTEL_INFO(ring->dev)->gen < 5)
11107                 return false;
11108
11109         if (i915.use_mmio_flip < 0)
11110                 return false;
11111         else if (i915.use_mmio_flip > 0)
11112                 return true;
11113         else if (i915.enable_execlists)
11114                 return true;
11115         else
11116                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11117 }
11118
11119 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11120                              struct intel_unpin_work *work)
11121 {
11122         struct drm_device *dev = intel_crtc->base.dev;
11123         struct drm_i915_private *dev_priv = dev->dev_private;
11124         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11125         const enum pipe pipe = intel_crtc->pipe;
11126         u32 ctl, stride;
11127
11128         ctl = I915_READ(PLANE_CTL(pipe, 0));
11129         ctl &= ~PLANE_CTL_TILED_MASK;
11130         switch (fb->modifier[0]) {
11131         case DRM_FORMAT_MOD_NONE:
11132                 break;
11133         case I915_FORMAT_MOD_X_TILED:
11134                 ctl |= PLANE_CTL_TILED_X;
11135                 break;
11136         case I915_FORMAT_MOD_Y_TILED:
11137                 ctl |= PLANE_CTL_TILED_Y;
11138                 break;
11139         case I915_FORMAT_MOD_Yf_TILED:
11140                 ctl |= PLANE_CTL_TILED_YF;
11141                 break;
11142         default:
11143                 MISSING_CASE(fb->modifier[0]);
11144         }
11145
11146         /*
11147          * The stride is either expressed as a multiple of 64 bytes chunks for
11148          * linear buffers or in number of tiles for tiled buffers.
11149          */
11150         stride = fb->pitches[0] /
11151                  intel_fb_stride_alignment(dev, fb->modifier[0],
11152                                            fb->pixel_format);
11153
11154         /*
11155          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11156          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11157          */
11158         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11159         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11160
11161         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11162         POSTING_READ(PLANE_SURF(pipe, 0));
11163 }
11164
11165 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11166                              struct intel_unpin_work *work)
11167 {
11168         struct drm_device *dev = intel_crtc->base.dev;
11169         struct drm_i915_private *dev_priv = dev->dev_private;
11170         struct intel_framebuffer *intel_fb =
11171                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11172         struct drm_i915_gem_object *obj = intel_fb->obj;
11173         u32 dspcntr;
11174         u32 reg;
11175
11176         reg = DSPCNTR(intel_crtc->plane);
11177         dspcntr = I915_READ(reg);
11178
11179         if (obj->tiling_mode != I915_TILING_NONE)
11180                 dspcntr |= DISPPLANE_TILED;
11181         else
11182                 dspcntr &= ~DISPPLANE_TILED;
11183
11184         I915_WRITE(reg, dspcntr);
11185
11186         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11187         POSTING_READ(DSPSURF(intel_crtc->plane));
11188 }
11189
11190 /*
11191  * XXX: This is the temporary way to update the plane registers until we get
11192  * around to using the usual plane update functions for MMIO flips
11193  */
11194 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11195 {
11196         struct intel_crtc *crtc = mmio_flip->crtc;
11197         struct intel_unpin_work *work;
11198
11199         spin_lock_irq(&crtc->base.dev->event_lock);
11200         work = crtc->unpin_work;
11201         spin_unlock_irq(&crtc->base.dev->event_lock);
11202         if (work == NULL)
11203                 return;
11204
11205         intel_mark_page_flip_active(work);
11206
11207         intel_pipe_update_start(crtc);
11208
11209         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11210                 skl_do_mmio_flip(crtc, work);
11211         else
11212                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11213                 ilk_do_mmio_flip(crtc, work);
11214
11215         intel_pipe_update_end(crtc);
11216 }
11217
11218 static void intel_mmio_flip_work_func(struct work_struct *work)
11219 {
11220         struct intel_mmio_flip *mmio_flip =
11221                 container_of(work, struct intel_mmio_flip, work);
11222
11223         if (mmio_flip->req) {
11224                 WARN_ON(__i915_wait_request(mmio_flip->req,
11225                                             mmio_flip->crtc->reset_counter,
11226                                             false, NULL,
11227                                             &mmio_flip->i915->rps.mmioflips));
11228                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11229         }
11230
11231         intel_do_mmio_flip(mmio_flip);
11232         kfree(mmio_flip);
11233 }
11234
11235 static int intel_queue_mmio_flip(struct drm_device *dev,
11236                                  struct drm_crtc *crtc,
11237                                  struct drm_framebuffer *fb,
11238                                  struct drm_i915_gem_object *obj,
11239                                  struct intel_engine_cs *ring,
11240                                  uint32_t flags)
11241 {
11242         struct intel_mmio_flip *mmio_flip;
11243
11244         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11245         if (mmio_flip == NULL)
11246                 return -ENOMEM;
11247
11248         mmio_flip->i915 = to_i915(dev);
11249         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11250         mmio_flip->crtc = to_intel_crtc(crtc);
11251
11252         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11253         schedule_work(&mmio_flip->work);
11254
11255         return 0;
11256 }
11257
11258 static int intel_default_queue_flip(struct drm_device *dev,
11259                                     struct drm_crtc *crtc,
11260                                     struct drm_framebuffer *fb,
11261                                     struct drm_i915_gem_object *obj,
11262                                     struct drm_i915_gem_request *req,
11263                                     uint32_t flags)
11264 {
11265         return -ENODEV;
11266 }
11267
11268 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11269                                          struct drm_crtc *crtc)
11270 {
11271         struct drm_i915_private *dev_priv = dev->dev_private;
11272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11273         struct intel_unpin_work *work = intel_crtc->unpin_work;
11274         u32 addr;
11275
11276         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11277                 return true;
11278
11279         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11280                 return false;
11281
11282         if (!work->enable_stall_check)
11283                 return false;
11284
11285         if (work->flip_ready_vblank == 0) {
11286                 if (work->flip_queued_req &&
11287                     !i915_gem_request_completed(work->flip_queued_req, true))
11288                         return false;
11289
11290                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11291         }
11292
11293         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11294                 return false;
11295
11296         /* Potential stall - if we see that the flip has happened,
11297          * assume a missed interrupt. */
11298         if (INTEL_INFO(dev)->gen >= 4)
11299                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11300         else
11301                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11302
11303         /* There is a potential issue here with a false positive after a flip
11304          * to the same address. We could address this by checking for a
11305          * non-incrementing frame counter.
11306          */
11307         return addr == work->gtt_offset;
11308 }
11309
11310 void intel_check_page_flip(struct drm_device *dev, int pipe)
11311 {
11312         struct drm_i915_private *dev_priv = dev->dev_private;
11313         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11315         struct intel_unpin_work *work;
11316
11317         WARN_ON(!in_interrupt());
11318
11319         if (crtc == NULL)
11320                 return;
11321
11322         spin_lock(&dev->event_lock);
11323         work = intel_crtc->unpin_work;
11324         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11325                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11326                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11327                 page_flip_completed(intel_crtc);
11328                 work = NULL;
11329         }
11330         if (work != NULL &&
11331             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11332                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11333         spin_unlock(&dev->event_lock);
11334 }
11335
11336 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11337                                 struct drm_framebuffer *fb,
11338                                 struct drm_pending_vblank_event *event,
11339                                 uint32_t page_flip_flags)
11340 {
11341         struct drm_device *dev = crtc->dev;
11342         struct drm_i915_private *dev_priv = dev->dev_private;
11343         struct drm_framebuffer *old_fb = crtc->primary->fb;
11344         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11346         struct drm_plane *primary = crtc->primary;
11347         enum pipe pipe = intel_crtc->pipe;
11348         struct intel_unpin_work *work;
11349         struct intel_engine_cs *ring;
11350         bool mmio_flip;
11351         struct drm_i915_gem_request *request = NULL;
11352         int ret;
11353
11354         /*
11355          * drm_mode_page_flip_ioctl() should already catch this, but double
11356          * check to be safe.  In the future we may enable pageflipping from
11357          * a disabled primary plane.
11358          */
11359         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11360                 return -EBUSY;
11361
11362         /* Can't change pixel format via MI display flips. */
11363         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11364                 return -EINVAL;
11365
11366         /*
11367          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11368          * Note that pitch changes could also affect these register.
11369          */
11370         if (INTEL_INFO(dev)->gen > 3 &&
11371             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11372              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11373                 return -EINVAL;
11374
11375         if (i915_terminally_wedged(&dev_priv->gpu_error))
11376                 goto out_hang;
11377
11378         work = kzalloc(sizeof(*work), GFP_KERNEL);
11379         if (work == NULL)
11380                 return -ENOMEM;
11381
11382         work->event = event;
11383         work->crtc = crtc;
11384         work->old_fb = old_fb;
11385         INIT_WORK(&work->work, intel_unpin_work_fn);
11386
11387         ret = drm_crtc_vblank_get(crtc);
11388         if (ret)
11389                 goto free_work;
11390
11391         /* We borrow the event spin lock for protecting unpin_work */
11392         spin_lock_irq(&dev->event_lock);
11393         if (intel_crtc->unpin_work) {
11394                 /* Before declaring the flip queue wedged, check if
11395                  * the hardware completed the operation behind our backs.
11396                  */
11397                 if (__intel_pageflip_stall_check(dev, crtc)) {
11398                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11399                         page_flip_completed(intel_crtc);
11400                 } else {
11401                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11402                         spin_unlock_irq(&dev->event_lock);
11403
11404                         drm_crtc_vblank_put(crtc);
11405                         kfree(work);
11406                         return -EBUSY;
11407                 }
11408         }
11409         intel_crtc->unpin_work = work;
11410         spin_unlock_irq(&dev->event_lock);
11411
11412         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11413                 flush_workqueue(dev_priv->wq);
11414
11415         /* Reference the objects for the scheduled work. */
11416         drm_framebuffer_reference(work->old_fb);
11417         drm_gem_object_reference(&obj->base);
11418
11419         crtc->primary->fb = fb;
11420         update_state_fb(crtc->primary);
11421
11422         work->pending_flip_obj = obj;
11423
11424         ret = i915_mutex_lock_interruptible(dev);
11425         if (ret)
11426                 goto cleanup;
11427
11428         atomic_inc(&intel_crtc->unpin_work_count);
11429         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11430
11431         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11432                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11433
11434         if (IS_VALLEYVIEW(dev)) {
11435                 ring = &dev_priv->ring[BCS];
11436                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11437                         /* vlv: DISPLAY_FLIP fails to change tiling */
11438                         ring = NULL;
11439         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11440                 ring = &dev_priv->ring[BCS];
11441         } else if (INTEL_INFO(dev)->gen >= 7) {
11442                 ring = i915_gem_request_get_ring(obj->last_write_req);
11443                 if (ring == NULL || ring->id != RCS)
11444                         ring = &dev_priv->ring[BCS];
11445         } else {
11446                 ring = &dev_priv->ring[RCS];
11447         }
11448
11449         mmio_flip = use_mmio_flip(ring, obj);
11450
11451         /* When using CS flips, we want to emit semaphores between rings.
11452          * However, when using mmio flips we will create a task to do the
11453          * synchronisation, so all we want here is to pin the framebuffer
11454          * into the display plane and skip any waits.
11455          */
11456         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11457                                          crtc->primary->state,
11458                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11459         if (ret)
11460                 goto cleanup_pending;
11461
11462         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11463                                                   obj, 0);
11464         work->gtt_offset += intel_crtc->dspaddr_offset;
11465
11466         if (mmio_flip) {
11467                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11468                                             page_flip_flags);
11469                 if (ret)
11470                         goto cleanup_unpin;
11471
11472                 i915_gem_request_assign(&work->flip_queued_req,
11473                                         obj->last_write_req);
11474         } else {
11475                 if (!request) {
11476                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11477                         if (ret)
11478                                 goto cleanup_unpin;
11479                 }
11480
11481                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11482                                                    page_flip_flags);
11483                 if (ret)
11484                         goto cleanup_unpin;
11485
11486                 i915_gem_request_assign(&work->flip_queued_req, request);
11487         }
11488
11489         if (request)
11490                 i915_add_request_no_flush(request);
11491
11492         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11493         work->enable_stall_check = true;
11494
11495         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11496                           to_intel_plane(primary)->frontbuffer_bit);
11497         mutex_unlock(&dev->struct_mutex);
11498
11499         intel_fbc_disable_crtc(intel_crtc);
11500         intel_frontbuffer_flip_prepare(dev,
11501                                        to_intel_plane(primary)->frontbuffer_bit);
11502
11503         trace_i915_flip_request(intel_crtc->plane, obj);
11504
11505         return 0;
11506
11507 cleanup_unpin:
11508         intel_unpin_fb_obj(fb, crtc->primary->state);
11509 cleanup_pending:
11510         if (request)
11511                 i915_gem_request_cancel(request);
11512         atomic_dec(&intel_crtc->unpin_work_count);
11513         mutex_unlock(&dev->struct_mutex);
11514 cleanup:
11515         crtc->primary->fb = old_fb;
11516         update_state_fb(crtc->primary);
11517
11518         drm_gem_object_unreference_unlocked(&obj->base);
11519         drm_framebuffer_unreference(work->old_fb);
11520
11521         spin_lock_irq(&dev->event_lock);
11522         intel_crtc->unpin_work = NULL;
11523         spin_unlock_irq(&dev->event_lock);
11524
11525         drm_crtc_vblank_put(crtc);
11526 free_work:
11527         kfree(work);
11528
11529         if (ret == -EIO) {
11530                 struct drm_atomic_state *state;
11531                 struct drm_plane_state *plane_state;
11532
11533 out_hang:
11534                 state = drm_atomic_state_alloc(dev);
11535                 if (!state)
11536                         return -ENOMEM;
11537                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11538
11539 retry:
11540                 plane_state = drm_atomic_get_plane_state(state, primary);
11541                 ret = PTR_ERR_OR_ZERO(plane_state);
11542                 if (!ret) {
11543                         drm_atomic_set_fb_for_plane(plane_state, fb);
11544
11545                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11546                         if (!ret)
11547                                 ret = drm_atomic_commit(state);
11548                 }
11549
11550                 if (ret == -EDEADLK) {
11551                         drm_modeset_backoff(state->acquire_ctx);
11552                         drm_atomic_state_clear(state);
11553                         goto retry;
11554                 }
11555
11556                 if (ret)
11557                         drm_atomic_state_free(state);
11558
11559                 if (ret == 0 && event) {
11560                         spin_lock_irq(&dev->event_lock);
11561                         drm_send_vblank_event(dev, pipe, event);
11562                         spin_unlock_irq(&dev->event_lock);
11563                 }
11564         }
11565         return ret;
11566 }
11567
11568
11569 /**
11570  * intel_wm_need_update - Check whether watermarks need updating
11571  * @plane: drm plane
11572  * @state: new plane state
11573  *
11574  * Check current plane state versus the new one to determine whether
11575  * watermarks need to be recalculated.
11576  *
11577  * Returns true or false.
11578  */
11579 static bool intel_wm_need_update(struct drm_plane *plane,
11580                                  struct drm_plane_state *state)
11581 {
11582         /* Update watermarks on tiling changes. */
11583         if (!plane->state->fb || !state->fb ||
11584             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11585             plane->state->rotation != state->rotation)
11586                 return true;
11587
11588         if (plane->state->crtc_w != state->crtc_w)
11589                 return true;
11590
11591         return false;
11592 }
11593
11594 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11595                                     struct drm_plane_state *plane_state)
11596 {
11597         struct drm_crtc *crtc = crtc_state->crtc;
11598         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11599         struct drm_plane *plane = plane_state->plane;
11600         struct drm_device *dev = crtc->dev;
11601         struct drm_i915_private *dev_priv = dev->dev_private;
11602         struct intel_plane_state *old_plane_state =
11603                 to_intel_plane_state(plane->state);
11604         int idx = intel_crtc->base.base.id, ret;
11605         int i = drm_plane_index(plane);
11606         bool mode_changed = needs_modeset(crtc_state);
11607         bool was_crtc_enabled = crtc->state->active;
11608         bool is_crtc_enabled = crtc_state->active;
11609
11610         bool turn_off, turn_on, visible, was_visible;
11611         struct drm_framebuffer *fb = plane_state->fb;
11612
11613         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11614             plane->type != DRM_PLANE_TYPE_CURSOR) {
11615                 ret = skl_update_scaler_plane(
11616                         to_intel_crtc_state(crtc_state),
11617                         to_intel_plane_state(plane_state));
11618                 if (ret)
11619                         return ret;
11620         }
11621
11622         /*
11623          * Disabling a plane is always okay; we just need to update
11624          * fb tracking in a special way since cleanup_fb() won't
11625          * get called by the plane helpers.
11626          */
11627         if (old_plane_state->base.fb && !fb)
11628                 intel_crtc->atomic.disabled_planes |= 1 << i;
11629
11630         was_visible = old_plane_state->visible;
11631         visible = to_intel_plane_state(plane_state)->visible;
11632
11633         if (!was_crtc_enabled && WARN_ON(was_visible))
11634                 was_visible = false;
11635
11636         if (!is_crtc_enabled && WARN_ON(visible))
11637                 visible = false;
11638
11639         if (!was_visible && !visible)
11640                 return 0;
11641
11642         turn_off = was_visible && (!visible || mode_changed);
11643         turn_on = visible && (!was_visible || mode_changed);
11644
11645         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11646                          plane->base.id, fb ? fb->base.id : -1);
11647
11648         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11649                          plane->base.id, was_visible, visible,
11650                          turn_off, turn_on, mode_changed);
11651
11652         if (turn_on) {
11653                 intel_crtc->atomic.update_wm_pre = true;
11654                 /* must disable cxsr around plane enable/disable */
11655                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11656                         intel_crtc->atomic.disable_cxsr = true;
11657                         /* to potentially re-enable cxsr */
11658                         intel_crtc->atomic.wait_vblank = true;
11659                         intel_crtc->atomic.update_wm_post = true;
11660                 }
11661         } else if (turn_off) {
11662                 intel_crtc->atomic.update_wm_post = true;
11663                 /* must disable cxsr around plane enable/disable */
11664                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11665                         if (is_crtc_enabled)
11666                                 intel_crtc->atomic.wait_vblank = true;
11667                         intel_crtc->atomic.disable_cxsr = true;
11668                 }
11669         } else if (intel_wm_need_update(plane, plane_state)) {
11670                 intel_crtc->atomic.update_wm_pre = true;
11671         }
11672
11673         if (visible || was_visible)
11674                 intel_crtc->atomic.fb_bits |=
11675                         to_intel_plane(plane)->frontbuffer_bit;
11676
11677         switch (plane->type) {
11678         case DRM_PLANE_TYPE_PRIMARY:
11679                 intel_crtc->atomic.wait_for_flips = true;
11680                 intel_crtc->atomic.pre_disable_primary = turn_off;
11681                 intel_crtc->atomic.post_enable_primary = turn_on;
11682
11683                 if (turn_off) {
11684                         /*
11685                          * FIXME: Actually if we will still have any other
11686                          * plane enabled on the pipe we could let IPS enabled
11687                          * still, but for now lets consider that when we make
11688                          * primary invisible by setting DSPCNTR to 0 on
11689                          * update_primary_plane function IPS needs to be
11690                          * disable.
11691                          */
11692                         intel_crtc->atomic.disable_ips = true;
11693
11694                         intel_crtc->atomic.disable_fbc = true;
11695                 }
11696
11697                 /*
11698                  * FBC does not work on some platforms for rotated
11699                  * planes, so disable it when rotation is not 0 and
11700                  * update it when rotation is set back to 0.
11701                  *
11702                  * FIXME: This is redundant with the fbc update done in
11703                  * the primary plane enable function except that that
11704                  * one is done too late. We eventually need to unify
11705                  * this.
11706                  */
11707
11708                 if (visible &&
11709                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11710                     dev_priv->fbc.crtc == intel_crtc &&
11711                     plane_state->rotation != BIT(DRM_ROTATE_0))
11712                         intel_crtc->atomic.disable_fbc = true;
11713
11714                 /*
11715                  * BDW signals flip done immediately if the plane
11716                  * is disabled, even if the plane enable is already
11717                  * armed to occur at the next vblank :(
11718                  */
11719                 if (turn_on && IS_BROADWELL(dev))
11720                         intel_crtc->atomic.wait_vblank = true;
11721
11722                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11723                 break;
11724         case DRM_PLANE_TYPE_CURSOR:
11725                 break;
11726         case DRM_PLANE_TYPE_OVERLAY:
11727                 if (turn_off && !mode_changed) {
11728                         intel_crtc->atomic.wait_vblank = true;
11729                         intel_crtc->atomic.update_sprite_watermarks |=
11730                                 1 << i;
11731                 }
11732         }
11733         return 0;
11734 }
11735
11736 static bool encoders_cloneable(const struct intel_encoder *a,
11737                                const struct intel_encoder *b)
11738 {
11739         /* masks could be asymmetric, so check both ways */
11740         return a == b || (a->cloneable & (1 << b->type) &&
11741                           b->cloneable & (1 << a->type));
11742 }
11743
11744 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11745                                          struct intel_crtc *crtc,
11746                                          struct intel_encoder *encoder)
11747 {
11748         struct intel_encoder *source_encoder;
11749         struct drm_connector *connector;
11750         struct drm_connector_state *connector_state;
11751         int i;
11752
11753         for_each_connector_in_state(state, connector, connector_state, i) {
11754                 if (connector_state->crtc != &crtc->base)
11755                         continue;
11756
11757                 source_encoder =
11758                         to_intel_encoder(connector_state->best_encoder);
11759                 if (!encoders_cloneable(encoder, source_encoder))
11760                         return false;
11761         }
11762
11763         return true;
11764 }
11765
11766 static bool check_encoder_cloning(struct drm_atomic_state *state,
11767                                   struct intel_crtc *crtc)
11768 {
11769         struct intel_encoder *encoder;
11770         struct drm_connector *connector;
11771         struct drm_connector_state *connector_state;
11772         int i;
11773
11774         for_each_connector_in_state(state, connector, connector_state, i) {
11775                 if (connector_state->crtc != &crtc->base)
11776                         continue;
11777
11778                 encoder = to_intel_encoder(connector_state->best_encoder);
11779                 if (!check_single_encoder_cloning(state, crtc, encoder))
11780                         return false;
11781         }
11782
11783         return true;
11784 }
11785
11786 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11787                                    struct drm_crtc_state *crtc_state)
11788 {
11789         struct drm_device *dev = crtc->dev;
11790         struct drm_i915_private *dev_priv = dev->dev_private;
11791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11792         struct intel_crtc_state *pipe_config =
11793                 to_intel_crtc_state(crtc_state);
11794         struct drm_atomic_state *state = crtc_state->state;
11795         int ret;
11796         bool mode_changed = needs_modeset(crtc_state);
11797
11798         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11799                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11800                 return -EINVAL;
11801         }
11802
11803         if (mode_changed && !crtc_state->active)
11804                 intel_crtc->atomic.update_wm_post = true;
11805
11806         if (mode_changed && crtc_state->enable &&
11807             dev_priv->display.crtc_compute_clock &&
11808             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11809                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11810                                                            pipe_config);
11811                 if (ret)
11812                         return ret;
11813         }
11814
11815         ret = 0;
11816         if (INTEL_INFO(dev)->gen >= 9) {
11817                 if (mode_changed)
11818                         ret = skl_update_scaler_crtc(pipe_config);
11819
11820                 if (!ret)
11821                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11822                                                          pipe_config);
11823         }
11824
11825         return ret;
11826 }
11827
11828 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11829         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11830         .load_lut = intel_crtc_load_lut,
11831         .atomic_begin = intel_begin_crtc_commit,
11832         .atomic_flush = intel_finish_crtc_commit,
11833         .atomic_check = intel_crtc_atomic_check,
11834 };
11835
11836 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11837 {
11838         struct intel_connector *connector;
11839
11840         for_each_intel_connector(dev, connector) {
11841                 if (connector->base.encoder) {
11842                         connector->base.state->best_encoder =
11843                                 connector->base.encoder;
11844                         connector->base.state->crtc =
11845                                 connector->base.encoder->crtc;
11846                 } else {
11847                         connector->base.state->best_encoder = NULL;
11848                         connector->base.state->crtc = NULL;
11849                 }
11850         }
11851 }
11852
11853 static void
11854 connected_sink_compute_bpp(struct intel_connector *connector,
11855                            struct intel_crtc_state *pipe_config)
11856 {
11857         int bpp = pipe_config->pipe_bpp;
11858
11859         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11860                 connector->base.base.id,
11861                 connector->base.name);
11862
11863         /* Don't use an invalid EDID bpc value */
11864         if (connector->base.display_info.bpc &&
11865             connector->base.display_info.bpc * 3 < bpp) {
11866                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11867                               bpp, connector->base.display_info.bpc*3);
11868                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11869         }
11870
11871         /* Clamp bpp to 8 on screens without EDID 1.4 */
11872         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11873                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11874                               bpp);
11875                 pipe_config->pipe_bpp = 24;
11876         }
11877 }
11878
11879 static int
11880 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11881                           struct intel_crtc_state *pipe_config)
11882 {
11883         struct drm_device *dev = crtc->base.dev;
11884         struct drm_atomic_state *state;
11885         struct drm_connector *connector;
11886         struct drm_connector_state *connector_state;
11887         int bpp, i;
11888
11889         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11890                 bpp = 10*3;
11891         else if (INTEL_INFO(dev)->gen >= 5)
11892                 bpp = 12*3;
11893         else
11894                 bpp = 8*3;
11895
11896
11897         pipe_config->pipe_bpp = bpp;
11898
11899         state = pipe_config->base.state;
11900
11901         /* Clamp display bpp to EDID value */
11902         for_each_connector_in_state(state, connector, connector_state, i) {
11903                 if (connector_state->crtc != &crtc->base)
11904                         continue;
11905
11906                 connected_sink_compute_bpp(to_intel_connector(connector),
11907                                            pipe_config);
11908         }
11909
11910         return bpp;
11911 }
11912
11913 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11914 {
11915         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11916                         "type: 0x%x flags: 0x%x\n",
11917                 mode->crtc_clock,
11918                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11919                 mode->crtc_hsync_end, mode->crtc_htotal,
11920                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11921                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11922 }
11923
11924 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11925                                    struct intel_crtc_state *pipe_config,
11926                                    const char *context)
11927 {
11928         struct drm_device *dev = crtc->base.dev;
11929         struct drm_plane *plane;
11930         struct intel_plane *intel_plane;
11931         struct intel_plane_state *state;
11932         struct drm_framebuffer *fb;
11933
11934         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11935                       context, pipe_config, pipe_name(crtc->pipe));
11936
11937         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11938         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11939                       pipe_config->pipe_bpp, pipe_config->dither);
11940         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11941                       pipe_config->has_pch_encoder,
11942                       pipe_config->fdi_lanes,
11943                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11944                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11945                       pipe_config->fdi_m_n.tu);
11946         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11947                       pipe_config->has_dp_encoder,
11948                       pipe_config->lane_count,
11949                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11950                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11951                       pipe_config->dp_m_n.tu);
11952
11953         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11954                       pipe_config->has_dp_encoder,
11955                       pipe_config->lane_count,
11956                       pipe_config->dp_m2_n2.gmch_m,
11957                       pipe_config->dp_m2_n2.gmch_n,
11958                       pipe_config->dp_m2_n2.link_m,
11959                       pipe_config->dp_m2_n2.link_n,
11960                       pipe_config->dp_m2_n2.tu);
11961
11962         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11963                       pipe_config->has_audio,
11964                       pipe_config->has_infoframe);
11965
11966         DRM_DEBUG_KMS("requested mode:\n");
11967         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11968         DRM_DEBUG_KMS("adjusted mode:\n");
11969         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11970         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11971         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11972         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11973                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11974         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11975                       crtc->num_scalers,
11976                       pipe_config->scaler_state.scaler_users,
11977                       pipe_config->scaler_state.scaler_id);
11978         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11979                       pipe_config->gmch_pfit.control,
11980                       pipe_config->gmch_pfit.pgm_ratios,
11981                       pipe_config->gmch_pfit.lvds_border_bits);
11982         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11983                       pipe_config->pch_pfit.pos,
11984                       pipe_config->pch_pfit.size,
11985                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11986         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11987         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11988
11989         if (IS_BROXTON(dev)) {
11990                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11991                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11992                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11993                               pipe_config->ddi_pll_sel,
11994                               pipe_config->dpll_hw_state.ebb0,
11995                               pipe_config->dpll_hw_state.ebb4,
11996                               pipe_config->dpll_hw_state.pll0,
11997                               pipe_config->dpll_hw_state.pll1,
11998                               pipe_config->dpll_hw_state.pll2,
11999                               pipe_config->dpll_hw_state.pll3,
12000                               pipe_config->dpll_hw_state.pll6,
12001                               pipe_config->dpll_hw_state.pll8,
12002                               pipe_config->dpll_hw_state.pll9,
12003                               pipe_config->dpll_hw_state.pll10,
12004                               pipe_config->dpll_hw_state.pcsdw12);
12005         } else if (IS_SKYLAKE(dev)) {
12006                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12007                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12008                               pipe_config->ddi_pll_sel,
12009                               pipe_config->dpll_hw_state.ctrl1,
12010                               pipe_config->dpll_hw_state.cfgcr1,
12011                               pipe_config->dpll_hw_state.cfgcr2);
12012         } else if (HAS_DDI(dev)) {
12013                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12014                               pipe_config->ddi_pll_sel,
12015                               pipe_config->dpll_hw_state.wrpll,
12016                               pipe_config->dpll_hw_state.spll);
12017         } else {
12018                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12019                               "fp0: 0x%x, fp1: 0x%x\n",
12020                               pipe_config->dpll_hw_state.dpll,
12021                               pipe_config->dpll_hw_state.dpll_md,
12022                               pipe_config->dpll_hw_state.fp0,
12023                               pipe_config->dpll_hw_state.fp1);
12024         }
12025
12026         DRM_DEBUG_KMS("planes on this crtc\n");
12027         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12028                 intel_plane = to_intel_plane(plane);
12029                 if (intel_plane->pipe != crtc->pipe)
12030                         continue;
12031
12032                 state = to_intel_plane_state(plane->state);
12033                 fb = state->base.fb;
12034                 if (!fb) {
12035                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12036                                 "disabled, scaler_id = %d\n",
12037                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12038                                 plane->base.id, intel_plane->pipe,
12039                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12040                                 drm_plane_index(plane), state->scaler_id);
12041                         continue;
12042                 }
12043
12044                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12045                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12046                         plane->base.id, intel_plane->pipe,
12047                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12048                         drm_plane_index(plane));
12049                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12050                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12051                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12052                         state->scaler_id,
12053                         state->src.x1 >> 16, state->src.y1 >> 16,
12054                         drm_rect_width(&state->src) >> 16,
12055                         drm_rect_height(&state->src) >> 16,
12056                         state->dst.x1, state->dst.y1,
12057                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12058         }
12059 }
12060
12061 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12062 {
12063         struct drm_device *dev = state->dev;
12064         struct intel_encoder *encoder;
12065         struct drm_connector *connector;
12066         struct drm_connector_state *connector_state;
12067         unsigned int used_ports = 0;
12068         int i;
12069
12070         /*
12071          * Walk the connector list instead of the encoder
12072          * list to detect the problem on ddi platforms
12073          * where there's just one encoder per digital port.
12074          */
12075         for_each_connector_in_state(state, connector, connector_state, i) {
12076                 if (!connector_state->best_encoder)
12077                         continue;
12078
12079                 encoder = to_intel_encoder(connector_state->best_encoder);
12080
12081                 WARN_ON(!connector_state->crtc);
12082
12083                 switch (encoder->type) {
12084                         unsigned int port_mask;
12085                 case INTEL_OUTPUT_UNKNOWN:
12086                         if (WARN_ON(!HAS_DDI(dev)))
12087                                 break;
12088                 case INTEL_OUTPUT_DISPLAYPORT:
12089                 case INTEL_OUTPUT_HDMI:
12090                 case INTEL_OUTPUT_EDP:
12091                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12092
12093                         /* the same port mustn't appear more than once */
12094                         if (used_ports & port_mask)
12095                                 return false;
12096
12097                         used_ports |= port_mask;
12098                 default:
12099                         break;
12100                 }
12101         }
12102
12103         return true;
12104 }
12105
12106 static void
12107 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12108 {
12109         struct drm_crtc_state tmp_state;
12110         struct intel_crtc_scaler_state scaler_state;
12111         struct intel_dpll_hw_state dpll_hw_state;
12112         enum intel_dpll_id shared_dpll;
12113         uint32_t ddi_pll_sel;
12114         bool force_thru;
12115
12116         /* FIXME: before the switch to atomic started, a new pipe_config was
12117          * kzalloc'd. Code that depends on any field being zero should be
12118          * fixed, so that the crtc_state can be safely duplicated. For now,
12119          * only fields that are know to not cause problems are preserved. */
12120
12121         tmp_state = crtc_state->base;
12122         scaler_state = crtc_state->scaler_state;
12123         shared_dpll = crtc_state->shared_dpll;
12124         dpll_hw_state = crtc_state->dpll_hw_state;
12125         ddi_pll_sel = crtc_state->ddi_pll_sel;
12126         force_thru = crtc_state->pch_pfit.force_thru;
12127
12128         memset(crtc_state, 0, sizeof *crtc_state);
12129
12130         crtc_state->base = tmp_state;
12131         crtc_state->scaler_state = scaler_state;
12132         crtc_state->shared_dpll = shared_dpll;
12133         crtc_state->dpll_hw_state = dpll_hw_state;
12134         crtc_state->ddi_pll_sel = ddi_pll_sel;
12135         crtc_state->pch_pfit.force_thru = force_thru;
12136 }
12137
12138 static int
12139 intel_modeset_pipe_config(struct drm_crtc *crtc,
12140                           struct intel_crtc_state *pipe_config)
12141 {
12142         struct drm_atomic_state *state = pipe_config->base.state;
12143         struct intel_encoder *encoder;
12144         struct drm_connector *connector;
12145         struct drm_connector_state *connector_state;
12146         int base_bpp, ret = -EINVAL;
12147         int i;
12148         bool retry = true;
12149
12150         clear_intel_crtc_state(pipe_config);
12151
12152         pipe_config->cpu_transcoder =
12153                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12154
12155         /*
12156          * Sanitize sync polarity flags based on requested ones. If neither
12157          * positive or negative polarity is requested, treat this as meaning
12158          * negative polarity.
12159          */
12160         if (!(pipe_config->base.adjusted_mode.flags &
12161               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12162                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12163
12164         if (!(pipe_config->base.adjusted_mode.flags &
12165               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12166                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12167
12168         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12169                                              pipe_config);
12170         if (base_bpp < 0)
12171                 goto fail;
12172
12173         /*
12174          * Determine the real pipe dimensions. Note that stereo modes can
12175          * increase the actual pipe size due to the frame doubling and
12176          * insertion of additional space for blanks between the frame. This
12177          * is stored in the crtc timings. We use the requested mode to do this
12178          * computation to clearly distinguish it from the adjusted mode, which
12179          * can be changed by the connectors in the below retry loop.
12180          */
12181         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12182                                &pipe_config->pipe_src_w,
12183                                &pipe_config->pipe_src_h);
12184
12185 encoder_retry:
12186         /* Ensure the port clock defaults are reset when retrying. */
12187         pipe_config->port_clock = 0;
12188         pipe_config->pixel_multiplier = 1;
12189
12190         /* Fill in default crtc timings, allow encoders to overwrite them. */
12191         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12192                               CRTC_STEREO_DOUBLE);
12193
12194         /* Pass our mode to the connectors and the CRTC to give them a chance to
12195          * adjust it according to limitations or connector properties, and also
12196          * a chance to reject the mode entirely.
12197          */
12198         for_each_connector_in_state(state, connector, connector_state, i) {
12199                 if (connector_state->crtc != crtc)
12200                         continue;
12201
12202                 encoder = to_intel_encoder(connector_state->best_encoder);
12203
12204                 if (!(encoder->compute_config(encoder, pipe_config))) {
12205                         DRM_DEBUG_KMS("Encoder config failure\n");
12206                         goto fail;
12207                 }
12208         }
12209
12210         /* Set default port clock if not overwritten by the encoder. Needs to be
12211          * done afterwards in case the encoder adjusts the mode. */
12212         if (!pipe_config->port_clock)
12213                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12214                         * pipe_config->pixel_multiplier;
12215
12216         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12217         if (ret < 0) {
12218                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12219                 goto fail;
12220         }
12221
12222         if (ret == RETRY) {
12223                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12224                         ret = -EINVAL;
12225                         goto fail;
12226                 }
12227
12228                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12229                 retry = false;
12230                 goto encoder_retry;
12231         }
12232
12233         /* Dithering seems to not pass-through bits correctly when it should, so
12234          * only enable it on 6bpc panels. */
12235         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12236         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12237                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12238
12239 fail:
12240         return ret;
12241 }
12242
12243 static void
12244 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12245 {
12246         struct drm_crtc *crtc;
12247         struct drm_crtc_state *crtc_state;
12248         int i;
12249
12250         /* Double check state. */
12251         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12252                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12253
12254                 /* Update hwmode for vblank functions */
12255                 if (crtc->state->active)
12256                         crtc->hwmode = crtc->state->adjusted_mode;
12257                 else
12258                         crtc->hwmode.crtc_clock = 0;
12259         }
12260 }
12261
12262 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12263 {
12264         int diff;
12265
12266         if (clock1 == clock2)
12267                 return true;
12268
12269         if (!clock1 || !clock2)
12270                 return false;
12271
12272         diff = abs(clock1 - clock2);
12273
12274         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12275                 return true;
12276
12277         return false;
12278 }
12279
12280 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12281         list_for_each_entry((intel_crtc), \
12282                             &(dev)->mode_config.crtc_list, \
12283                             base.head) \
12284                 if (mask & (1 <<(intel_crtc)->pipe))
12285
12286 static bool
12287 intel_compare_m_n(unsigned int m, unsigned int n,
12288                   unsigned int m2, unsigned int n2,
12289                   bool exact)
12290 {
12291         if (m == m2 && n == n2)
12292                 return true;
12293
12294         if (exact || !m || !n || !m2 || !n2)
12295                 return false;
12296
12297         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12298
12299         if (m > m2) {
12300                 while (m > m2) {
12301                         m2 <<= 1;
12302                         n2 <<= 1;
12303                 }
12304         } else if (m < m2) {
12305                 while (m < m2) {
12306                         m <<= 1;
12307                         n <<= 1;
12308                 }
12309         }
12310
12311         return m == m2 && n == n2;
12312 }
12313
12314 static bool
12315 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12316                        struct intel_link_m_n *m2_n2,
12317                        bool adjust)
12318 {
12319         if (m_n->tu == m2_n2->tu &&
12320             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12321                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12322             intel_compare_m_n(m_n->link_m, m_n->link_n,
12323                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12324                 if (adjust)
12325                         *m2_n2 = *m_n;
12326
12327                 return true;
12328         }
12329
12330         return false;
12331 }
12332
12333 static bool
12334 intel_pipe_config_compare(struct drm_device *dev,
12335                           struct intel_crtc_state *current_config,
12336                           struct intel_crtc_state *pipe_config,
12337                           bool adjust)
12338 {
12339         bool ret = true;
12340
12341 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12342         do { \
12343                 if (!adjust) \
12344                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12345                 else \
12346                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12347         } while (0)
12348
12349 #define PIPE_CONF_CHECK_X(name) \
12350         if (current_config->name != pipe_config->name) { \
12351                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12352                           "(expected 0x%08x, found 0x%08x)\n", \
12353                           current_config->name, \
12354                           pipe_config->name); \
12355                 ret = false; \
12356         }
12357
12358 #define PIPE_CONF_CHECK_I(name) \
12359         if (current_config->name != pipe_config->name) { \
12360                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12361                           "(expected %i, found %i)\n", \
12362                           current_config->name, \
12363                           pipe_config->name); \
12364                 ret = false; \
12365         }
12366
12367 #define PIPE_CONF_CHECK_M_N(name) \
12368         if (!intel_compare_link_m_n(&current_config->name, \
12369                                     &pipe_config->name,\
12370                                     adjust)) { \
12371                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12372                           "(expected tu %i gmch %i/%i link %i/%i, " \
12373                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12374                           current_config->name.tu, \
12375                           current_config->name.gmch_m, \
12376                           current_config->name.gmch_n, \
12377                           current_config->name.link_m, \
12378                           current_config->name.link_n, \
12379                           pipe_config->name.tu, \
12380                           pipe_config->name.gmch_m, \
12381                           pipe_config->name.gmch_n, \
12382                           pipe_config->name.link_m, \
12383                           pipe_config->name.link_n); \
12384                 ret = false; \
12385         }
12386
12387 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12388         if (!intel_compare_link_m_n(&current_config->name, \
12389                                     &pipe_config->name, adjust) && \
12390             !intel_compare_link_m_n(&current_config->alt_name, \
12391                                     &pipe_config->name, adjust)) { \
12392                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12393                           "(expected tu %i gmch %i/%i link %i/%i, " \
12394                           "or tu %i gmch %i/%i link %i/%i, " \
12395                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12396                           current_config->name.tu, \
12397                           current_config->name.gmch_m, \
12398                           current_config->name.gmch_n, \
12399                           current_config->name.link_m, \
12400                           current_config->name.link_n, \
12401                           current_config->alt_name.tu, \
12402                           current_config->alt_name.gmch_m, \
12403                           current_config->alt_name.gmch_n, \
12404                           current_config->alt_name.link_m, \
12405                           current_config->alt_name.link_n, \
12406                           pipe_config->name.tu, \
12407                           pipe_config->name.gmch_m, \
12408                           pipe_config->name.gmch_n, \
12409                           pipe_config->name.link_m, \
12410                           pipe_config->name.link_n); \
12411                 ret = false; \
12412         }
12413
12414 /* This is required for BDW+ where there is only one set of registers for
12415  * switching between high and low RR.
12416  * This macro can be used whenever a comparison has to be made between one
12417  * hw state and multiple sw state variables.
12418  */
12419 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12420         if ((current_config->name != pipe_config->name) && \
12421                 (current_config->alt_name != pipe_config->name)) { \
12422                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12423                                   "(expected %i or %i, found %i)\n", \
12424                                   current_config->name, \
12425                                   current_config->alt_name, \
12426                                   pipe_config->name); \
12427                         ret = false; \
12428         }
12429
12430 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12431         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12432                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12433                           "(expected %i, found %i)\n", \
12434                           current_config->name & (mask), \
12435                           pipe_config->name & (mask)); \
12436                 ret = false; \
12437         }
12438
12439 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12440         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12441                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12442                           "(expected %i, found %i)\n", \
12443                           current_config->name, \
12444                           pipe_config->name); \
12445                 ret = false; \
12446         }
12447
12448 #define PIPE_CONF_QUIRK(quirk)  \
12449         ((current_config->quirks | pipe_config->quirks) & (quirk))
12450
12451         PIPE_CONF_CHECK_I(cpu_transcoder);
12452
12453         PIPE_CONF_CHECK_I(has_pch_encoder);
12454         PIPE_CONF_CHECK_I(fdi_lanes);
12455         PIPE_CONF_CHECK_M_N(fdi_m_n);
12456
12457         PIPE_CONF_CHECK_I(has_dp_encoder);
12458         PIPE_CONF_CHECK_I(lane_count);
12459
12460         if (INTEL_INFO(dev)->gen < 8) {
12461                 PIPE_CONF_CHECK_M_N(dp_m_n);
12462
12463                 PIPE_CONF_CHECK_I(has_drrs);
12464                 if (current_config->has_drrs)
12465                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12466         } else
12467                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12468
12469         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12470         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12471         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12472         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12473         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12474         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12475
12476         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12477         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12478         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12479         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12480         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12481         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12482
12483         PIPE_CONF_CHECK_I(pixel_multiplier);
12484         PIPE_CONF_CHECK_I(has_hdmi_sink);
12485         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12486             IS_VALLEYVIEW(dev))
12487                 PIPE_CONF_CHECK_I(limited_color_range);
12488         PIPE_CONF_CHECK_I(has_infoframe);
12489
12490         PIPE_CONF_CHECK_I(has_audio);
12491
12492         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12493                               DRM_MODE_FLAG_INTERLACE);
12494
12495         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12496                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12497                                       DRM_MODE_FLAG_PHSYNC);
12498                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12499                                       DRM_MODE_FLAG_NHSYNC);
12500                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12501                                       DRM_MODE_FLAG_PVSYNC);
12502                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12503                                       DRM_MODE_FLAG_NVSYNC);
12504         }
12505
12506         PIPE_CONF_CHECK_X(gmch_pfit.control);
12507         /* pfit ratios are autocomputed by the hw on gen4+ */
12508         if (INTEL_INFO(dev)->gen < 4)
12509                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12510         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12511
12512         if (!adjust) {
12513                 PIPE_CONF_CHECK_I(pipe_src_w);
12514                 PIPE_CONF_CHECK_I(pipe_src_h);
12515
12516                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12517                 if (current_config->pch_pfit.enabled) {
12518                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12519                         PIPE_CONF_CHECK_X(pch_pfit.size);
12520                 }
12521
12522                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12523         }
12524
12525         /* BDW+ don't expose a synchronous way to read the state */
12526         if (IS_HASWELL(dev))
12527                 PIPE_CONF_CHECK_I(ips_enabled);
12528
12529         PIPE_CONF_CHECK_I(double_wide);
12530
12531         PIPE_CONF_CHECK_X(ddi_pll_sel);
12532
12533         PIPE_CONF_CHECK_I(shared_dpll);
12534         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12535         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12536         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12537         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12538         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12539         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12540         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12541         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12542         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12543
12544         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12545                 PIPE_CONF_CHECK_I(pipe_bpp);
12546
12547         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12548         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12549
12550 #undef PIPE_CONF_CHECK_X
12551 #undef PIPE_CONF_CHECK_I
12552 #undef PIPE_CONF_CHECK_I_ALT
12553 #undef PIPE_CONF_CHECK_FLAGS
12554 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12555 #undef PIPE_CONF_QUIRK
12556 #undef INTEL_ERR_OR_DBG_KMS
12557
12558         return ret;
12559 }
12560
12561 static void check_wm_state(struct drm_device *dev)
12562 {
12563         struct drm_i915_private *dev_priv = dev->dev_private;
12564         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12565         struct intel_crtc *intel_crtc;
12566         int plane;
12567
12568         if (INTEL_INFO(dev)->gen < 9)
12569                 return;
12570
12571         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12572         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12573
12574         for_each_intel_crtc(dev, intel_crtc) {
12575                 struct skl_ddb_entry *hw_entry, *sw_entry;
12576                 const enum pipe pipe = intel_crtc->pipe;
12577
12578                 if (!intel_crtc->active)
12579                         continue;
12580
12581                 /* planes */
12582                 for_each_plane(dev_priv, pipe, plane) {
12583                         hw_entry = &hw_ddb.plane[pipe][plane];
12584                         sw_entry = &sw_ddb->plane[pipe][plane];
12585
12586                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12587                                 continue;
12588
12589                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12590                                   "(expected (%u,%u), found (%u,%u))\n",
12591                                   pipe_name(pipe), plane + 1,
12592                                   sw_entry->start, sw_entry->end,
12593                                   hw_entry->start, hw_entry->end);
12594                 }
12595
12596                 /* cursor */
12597                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12598                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12599
12600                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12601                         continue;
12602
12603                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12604                           "(expected (%u,%u), found (%u,%u))\n",
12605                           pipe_name(pipe),
12606                           sw_entry->start, sw_entry->end,
12607                           hw_entry->start, hw_entry->end);
12608         }
12609 }
12610
12611 static void
12612 check_connector_state(struct drm_device *dev,
12613                       struct drm_atomic_state *old_state)
12614 {
12615         struct drm_connector_state *old_conn_state;
12616         struct drm_connector *connector;
12617         int i;
12618
12619         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12620                 struct drm_encoder *encoder = connector->encoder;
12621                 struct drm_connector_state *state = connector->state;
12622
12623                 /* This also checks the encoder/connector hw state with the
12624                  * ->get_hw_state callbacks. */
12625                 intel_connector_check_state(to_intel_connector(connector));
12626
12627                 I915_STATE_WARN(state->best_encoder != encoder,
12628                      "connector's atomic encoder doesn't match legacy encoder\n");
12629         }
12630 }
12631
12632 static void
12633 check_encoder_state(struct drm_device *dev)
12634 {
12635         struct intel_encoder *encoder;
12636         struct intel_connector *connector;
12637
12638         for_each_intel_encoder(dev, encoder) {
12639                 bool enabled = false;
12640                 enum pipe pipe;
12641
12642                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12643                               encoder->base.base.id,
12644                               encoder->base.name);
12645
12646                 for_each_intel_connector(dev, connector) {
12647                         if (connector->base.state->best_encoder != &encoder->base)
12648                                 continue;
12649                         enabled = true;
12650
12651                         I915_STATE_WARN(connector->base.state->crtc !=
12652                                         encoder->base.crtc,
12653                              "connector's crtc doesn't match encoder crtc\n");
12654                 }
12655
12656                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12657                      "encoder's enabled state mismatch "
12658                      "(expected %i, found %i)\n",
12659                      !!encoder->base.crtc, enabled);
12660
12661                 if (!encoder->base.crtc) {
12662                         bool active;
12663
12664                         active = encoder->get_hw_state(encoder, &pipe);
12665                         I915_STATE_WARN(active,
12666                              "encoder detached but still enabled on pipe %c.\n",
12667                              pipe_name(pipe));
12668                 }
12669         }
12670 }
12671
12672 static void
12673 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12674 {
12675         struct drm_i915_private *dev_priv = dev->dev_private;
12676         struct intel_encoder *encoder;
12677         struct drm_crtc_state *old_crtc_state;
12678         struct drm_crtc *crtc;
12679         int i;
12680
12681         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12682                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12683                 struct intel_crtc_state *pipe_config, *sw_config;
12684                 bool active;
12685
12686                 if (!needs_modeset(crtc->state) &&
12687                     !to_intel_crtc_state(crtc->state)->update_pipe)
12688                         continue;
12689
12690                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12691                 pipe_config = to_intel_crtc_state(old_crtc_state);
12692                 memset(pipe_config, 0, sizeof(*pipe_config));
12693                 pipe_config->base.crtc = crtc;
12694                 pipe_config->base.state = old_state;
12695
12696                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12697                               crtc->base.id);
12698
12699                 active = dev_priv->display.get_pipe_config(intel_crtc,
12700                                                            pipe_config);
12701
12702                 /* hw state is inconsistent with the pipe quirk */
12703                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12704                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12705                         active = crtc->state->active;
12706
12707                 I915_STATE_WARN(crtc->state->active != active,
12708                      "crtc active state doesn't match with hw state "
12709                      "(expected %i, found %i)\n", crtc->state->active, active);
12710
12711                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12712                      "transitional active state does not match atomic hw state "
12713                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12714
12715                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12716                         enum pipe pipe;
12717
12718                         active = encoder->get_hw_state(encoder, &pipe);
12719                         I915_STATE_WARN(active != crtc->state->active,
12720                                 "[ENCODER:%i] active %i with crtc active %i\n",
12721                                 encoder->base.base.id, active, crtc->state->active);
12722
12723                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12724                                         "Encoder connected to wrong pipe %c\n",
12725                                         pipe_name(pipe));
12726
12727                         if (active)
12728                                 encoder->get_config(encoder, pipe_config);
12729                 }
12730
12731                 if (!crtc->state->active)
12732                         continue;
12733
12734                 sw_config = to_intel_crtc_state(crtc->state);
12735                 if (!intel_pipe_config_compare(dev, sw_config,
12736                                                pipe_config, false)) {
12737                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12738                         intel_dump_pipe_config(intel_crtc, pipe_config,
12739                                                "[hw state]");
12740                         intel_dump_pipe_config(intel_crtc, sw_config,
12741                                                "[sw state]");
12742                 }
12743         }
12744 }
12745
12746 static void
12747 check_shared_dpll_state(struct drm_device *dev)
12748 {
12749         struct drm_i915_private *dev_priv = dev->dev_private;
12750         struct intel_crtc *crtc;
12751         struct intel_dpll_hw_state dpll_hw_state;
12752         int i;
12753
12754         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12755                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12756                 int enabled_crtcs = 0, active_crtcs = 0;
12757                 bool active;
12758
12759                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12760
12761                 DRM_DEBUG_KMS("%s\n", pll->name);
12762
12763                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12764
12765                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12766                      "more active pll users than references: %i vs %i\n",
12767                      pll->active, hweight32(pll->config.crtc_mask));
12768                 I915_STATE_WARN(pll->active && !pll->on,
12769                      "pll in active use but not on in sw tracking\n");
12770                 I915_STATE_WARN(pll->on && !pll->active,
12771                      "pll in on but not on in use in sw tracking\n");
12772                 I915_STATE_WARN(pll->on != active,
12773                      "pll on state mismatch (expected %i, found %i)\n",
12774                      pll->on, active);
12775
12776                 for_each_intel_crtc(dev, crtc) {
12777                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12778                                 enabled_crtcs++;
12779                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12780                                 active_crtcs++;
12781                 }
12782                 I915_STATE_WARN(pll->active != active_crtcs,
12783                      "pll active crtcs mismatch (expected %i, found %i)\n",
12784                      pll->active, active_crtcs);
12785                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12786                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12787                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12788
12789                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12790                                        sizeof(dpll_hw_state)),
12791                      "pll hw state mismatch\n");
12792         }
12793 }
12794
12795 static void
12796 intel_modeset_check_state(struct drm_device *dev,
12797                           struct drm_atomic_state *old_state)
12798 {
12799         check_wm_state(dev);
12800         check_connector_state(dev, old_state);
12801         check_encoder_state(dev);
12802         check_crtc_state(dev, old_state);
12803         check_shared_dpll_state(dev);
12804 }
12805
12806 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12807                                      int dotclock)
12808 {
12809         /*
12810          * FDI already provided one idea for the dotclock.
12811          * Yell if the encoder disagrees.
12812          */
12813         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12814              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12815              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12816 }
12817
12818 static void update_scanline_offset(struct intel_crtc *crtc)
12819 {
12820         struct drm_device *dev = crtc->base.dev;
12821
12822         /*
12823          * The scanline counter increments at the leading edge of hsync.
12824          *
12825          * On most platforms it starts counting from vtotal-1 on the
12826          * first active line. That means the scanline counter value is
12827          * always one less than what we would expect. Ie. just after
12828          * start of vblank, which also occurs at start of hsync (on the
12829          * last active line), the scanline counter will read vblank_start-1.
12830          *
12831          * On gen2 the scanline counter starts counting from 1 instead
12832          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12833          * to keep the value positive), instead of adding one.
12834          *
12835          * On HSW+ the behaviour of the scanline counter depends on the output
12836          * type. For DP ports it behaves like most other platforms, but on HDMI
12837          * there's an extra 1 line difference. So we need to add two instead of
12838          * one to the value.
12839          */
12840         if (IS_GEN2(dev)) {
12841                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12842                 int vtotal;
12843
12844                 vtotal = adjusted_mode->crtc_vtotal;
12845                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12846                         vtotal /= 2;
12847
12848                 crtc->scanline_offset = vtotal - 1;
12849         } else if (HAS_DDI(dev) &&
12850                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12851                 crtc->scanline_offset = 2;
12852         } else
12853                 crtc->scanline_offset = 1;
12854 }
12855
12856 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12857 {
12858         struct drm_device *dev = state->dev;
12859         struct drm_i915_private *dev_priv = to_i915(dev);
12860         struct intel_shared_dpll_config *shared_dpll = NULL;
12861         struct intel_crtc *intel_crtc;
12862         struct intel_crtc_state *intel_crtc_state;
12863         struct drm_crtc *crtc;
12864         struct drm_crtc_state *crtc_state;
12865         int i;
12866
12867         if (!dev_priv->display.crtc_compute_clock)
12868                 return;
12869
12870         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12871                 int dpll;
12872
12873                 intel_crtc = to_intel_crtc(crtc);
12874                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12875                 dpll = intel_crtc_state->shared_dpll;
12876
12877                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12878                         continue;
12879
12880                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12881
12882                 if (!shared_dpll)
12883                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12884
12885                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12886         }
12887 }
12888
12889 /*
12890  * This implements the workaround described in the "notes" section of the mode
12891  * set sequence documentation. When going from no pipes or single pipe to
12892  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12893  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12894  */
12895 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12896 {
12897         struct drm_crtc_state *crtc_state;
12898         struct intel_crtc *intel_crtc;
12899         struct drm_crtc *crtc;
12900         struct intel_crtc_state *first_crtc_state = NULL;
12901         struct intel_crtc_state *other_crtc_state = NULL;
12902         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12903         int i;
12904
12905         /* look at all crtc's that are going to be enabled in during modeset */
12906         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12907                 intel_crtc = to_intel_crtc(crtc);
12908
12909                 if (!crtc_state->active || !needs_modeset(crtc_state))
12910                         continue;
12911
12912                 if (first_crtc_state) {
12913                         other_crtc_state = to_intel_crtc_state(crtc_state);
12914                         break;
12915                 } else {
12916                         first_crtc_state = to_intel_crtc_state(crtc_state);
12917                         first_pipe = intel_crtc->pipe;
12918                 }
12919         }
12920
12921         /* No workaround needed? */
12922         if (!first_crtc_state)
12923                 return 0;
12924
12925         /* w/a possibly needed, check how many crtc's are already enabled. */
12926         for_each_intel_crtc(state->dev, intel_crtc) {
12927                 struct intel_crtc_state *pipe_config;
12928
12929                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12930                 if (IS_ERR(pipe_config))
12931                         return PTR_ERR(pipe_config);
12932
12933                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12934
12935                 if (!pipe_config->base.active ||
12936                     needs_modeset(&pipe_config->base))
12937                         continue;
12938
12939                 /* 2 or more enabled crtcs means no need for w/a */
12940                 if (enabled_pipe != INVALID_PIPE)
12941                         return 0;
12942
12943                 enabled_pipe = intel_crtc->pipe;
12944         }
12945
12946         if (enabled_pipe != INVALID_PIPE)
12947                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12948         else if (other_crtc_state)
12949                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12950
12951         return 0;
12952 }
12953
12954 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12955 {
12956         struct drm_crtc *crtc;
12957         struct drm_crtc_state *crtc_state;
12958         int ret = 0;
12959
12960         /* add all active pipes to the state */
12961         for_each_crtc(state->dev, crtc) {
12962                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12963                 if (IS_ERR(crtc_state))
12964                         return PTR_ERR(crtc_state);
12965
12966                 if (!crtc_state->active || needs_modeset(crtc_state))
12967                         continue;
12968
12969                 crtc_state->mode_changed = true;
12970
12971                 ret = drm_atomic_add_affected_connectors(state, crtc);
12972                 if (ret)
12973                         break;
12974
12975                 ret = drm_atomic_add_affected_planes(state, crtc);
12976                 if (ret)
12977                         break;
12978         }
12979
12980         return ret;
12981 }
12982
12983 static int intel_modeset_checks(struct drm_atomic_state *state)
12984 {
12985         struct drm_device *dev = state->dev;
12986         struct drm_i915_private *dev_priv = dev->dev_private;
12987         int ret;
12988
12989         if (!check_digital_port_conflicts(state)) {
12990                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12991                 return -EINVAL;
12992         }
12993
12994         /*
12995          * See if the config requires any additional preparation, e.g.
12996          * to adjust global state with pipes off.  We need to do this
12997          * here so we can get the modeset_pipe updated config for the new
12998          * mode set on this crtc.  For other crtcs we need to use the
12999          * adjusted_mode bits in the crtc directly.
13000          */
13001         if (dev_priv->display.modeset_calc_cdclk) {
13002                 unsigned int cdclk;
13003
13004                 ret = dev_priv->display.modeset_calc_cdclk(state);
13005
13006                 cdclk = to_intel_atomic_state(state)->cdclk;
13007                 if (!ret && cdclk != dev_priv->cdclk_freq)
13008                         ret = intel_modeset_all_pipes(state);
13009
13010                 if (ret < 0)
13011                         return ret;
13012         } else
13013                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13014
13015         intel_modeset_clear_plls(state);
13016
13017         if (IS_HASWELL(dev))
13018                 return haswell_mode_set_planes_workaround(state);
13019
13020         return 0;
13021 }
13022
13023 /**
13024  * intel_atomic_check - validate state object
13025  * @dev: drm device
13026  * @state: state to validate
13027  */
13028 static int intel_atomic_check(struct drm_device *dev,
13029                               struct drm_atomic_state *state)
13030 {
13031         struct drm_crtc *crtc;
13032         struct drm_crtc_state *crtc_state;
13033         int ret, i;
13034         bool any_ms = false;
13035
13036         ret = drm_atomic_helper_check_modeset(dev, state);
13037         if (ret)
13038                 return ret;
13039
13040         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13041                 struct intel_crtc_state *pipe_config =
13042                         to_intel_crtc_state(crtc_state);
13043
13044                 memset(&to_intel_crtc(crtc)->atomic, 0,
13045                        sizeof(struct intel_crtc_atomic_commit));
13046
13047                 /* Catch I915_MODE_FLAG_INHERITED */
13048                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13049                         crtc_state->mode_changed = true;
13050
13051                 if (!crtc_state->enable) {
13052                         if (needs_modeset(crtc_state))
13053                                 any_ms = true;
13054                         continue;
13055                 }
13056
13057                 if (!needs_modeset(crtc_state))
13058                         continue;
13059
13060                 /* FIXME: For only active_changed we shouldn't need to do any
13061                  * state recomputation at all. */
13062
13063                 ret = drm_atomic_add_affected_connectors(state, crtc);
13064                 if (ret)
13065                         return ret;
13066
13067                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13068                 if (ret)
13069                         return ret;
13070
13071                 if (intel_pipe_config_compare(state->dev,
13072                                         to_intel_crtc_state(crtc->state),
13073                                         pipe_config, true)) {
13074                         crtc_state->mode_changed = false;
13075                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13076                 }
13077
13078                 if (needs_modeset(crtc_state)) {
13079                         any_ms = true;
13080
13081                         ret = drm_atomic_add_affected_planes(state, crtc);
13082                         if (ret)
13083                                 return ret;
13084                 }
13085
13086                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13087                                        needs_modeset(crtc_state) ?
13088                                        "[modeset]" : "[fastset]");
13089         }
13090
13091         if (any_ms) {
13092                 ret = intel_modeset_checks(state);
13093
13094                 if (ret)
13095                         return ret;
13096         } else
13097                 to_intel_atomic_state(state)->cdclk =
13098                         to_i915(state->dev)->cdclk_freq;
13099
13100         return drm_atomic_helper_check_planes(state->dev, state);
13101 }
13102
13103 /**
13104  * intel_atomic_commit - commit validated state object
13105  * @dev: DRM device
13106  * @state: the top-level driver state object
13107  * @async: asynchronous commit
13108  *
13109  * This function commits a top-level state object that has been validated
13110  * with drm_atomic_helper_check().
13111  *
13112  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13113  * we can only handle plane-related operations and do not yet support
13114  * asynchronous commit.
13115  *
13116  * RETURNS
13117  * Zero for success or -errno.
13118  */
13119 static int intel_atomic_commit(struct drm_device *dev,
13120                                struct drm_atomic_state *state,
13121                                bool async)
13122 {
13123         struct drm_i915_private *dev_priv = dev->dev_private;
13124         struct drm_crtc *crtc;
13125         struct drm_crtc_state *crtc_state;
13126         int ret = 0;
13127         int i;
13128         bool any_ms = false;
13129
13130         if (async) {
13131                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13132                 return -EINVAL;
13133         }
13134
13135         ret = drm_atomic_helper_prepare_planes(dev, state);
13136         if (ret)
13137                 return ret;
13138
13139         drm_atomic_helper_swap_state(dev, state);
13140
13141         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13142                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13143
13144                 if (!needs_modeset(crtc->state))
13145                         continue;
13146
13147                 any_ms = true;
13148                 intel_pre_plane_update(intel_crtc);
13149
13150                 if (crtc_state->active) {
13151                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13152                         dev_priv->display.crtc_disable(crtc);
13153                         intel_crtc->active = false;
13154                         intel_disable_shared_dpll(intel_crtc);
13155                 }
13156         }
13157
13158         /* Only after disabling all output pipelines that will be changed can we
13159          * update the the output configuration. */
13160         intel_modeset_update_crtc_state(state);
13161
13162         if (any_ms) {
13163                 intel_shared_dpll_commit(state);
13164
13165                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13166                 modeset_update_crtc_power_domains(state);
13167         }
13168
13169         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13170         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13171                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13172                 bool modeset = needs_modeset(crtc->state);
13173                 bool update_pipe = !modeset &&
13174                         to_intel_crtc_state(crtc->state)->update_pipe;
13175                 unsigned long put_domains = 0;
13176
13177                 if (modeset && crtc->state->active) {
13178                         update_scanline_offset(to_intel_crtc(crtc));
13179                         dev_priv->display.crtc_enable(crtc);
13180                 }
13181
13182                 if (update_pipe) {
13183                         put_domains = modeset_get_crtc_power_domains(crtc);
13184
13185                         /* make sure intel_modeset_check_state runs */
13186                         any_ms = true;
13187                 }
13188
13189                 if (!modeset)
13190                         intel_pre_plane_update(intel_crtc);
13191
13192                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13193
13194                 if (put_domains)
13195                         modeset_put_power_domains(dev_priv, put_domains);
13196
13197                 intel_post_plane_update(intel_crtc);
13198         }
13199
13200         /* FIXME: add subpixel order */
13201
13202         drm_atomic_helper_wait_for_vblanks(dev, state);
13203         drm_atomic_helper_cleanup_planes(dev, state);
13204
13205         if (any_ms)
13206                 intel_modeset_check_state(dev, state);
13207
13208         drm_atomic_state_free(state);
13209
13210         return 0;
13211 }
13212
13213 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13214 {
13215         struct drm_device *dev = crtc->dev;
13216         struct drm_atomic_state *state;
13217         struct drm_crtc_state *crtc_state;
13218         int ret;
13219
13220         state = drm_atomic_state_alloc(dev);
13221         if (!state) {
13222                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13223                               crtc->base.id);
13224                 return;
13225         }
13226
13227         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13228
13229 retry:
13230         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13231         ret = PTR_ERR_OR_ZERO(crtc_state);
13232         if (!ret) {
13233                 if (!crtc_state->active)
13234                         goto out;
13235
13236                 crtc_state->mode_changed = true;
13237                 ret = drm_atomic_commit(state);
13238         }
13239
13240         if (ret == -EDEADLK) {
13241                 drm_atomic_state_clear(state);
13242                 drm_modeset_backoff(state->acquire_ctx);
13243                 goto retry;
13244         }
13245
13246         if (ret)
13247 out:
13248                 drm_atomic_state_free(state);
13249 }
13250
13251 #undef for_each_intel_crtc_masked
13252
13253 static const struct drm_crtc_funcs intel_crtc_funcs = {
13254         .gamma_set = intel_crtc_gamma_set,
13255         .set_config = drm_atomic_helper_set_config,
13256         .destroy = intel_crtc_destroy,
13257         .page_flip = intel_crtc_page_flip,
13258         .atomic_duplicate_state = intel_crtc_duplicate_state,
13259         .atomic_destroy_state = intel_crtc_destroy_state,
13260 };
13261
13262 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13263                                       struct intel_shared_dpll *pll,
13264                                       struct intel_dpll_hw_state *hw_state)
13265 {
13266         uint32_t val;
13267
13268         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13269                 return false;
13270
13271         val = I915_READ(PCH_DPLL(pll->id));
13272         hw_state->dpll = val;
13273         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13274         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13275
13276         return val & DPLL_VCO_ENABLE;
13277 }
13278
13279 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13280                                   struct intel_shared_dpll *pll)
13281 {
13282         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13283         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13284 }
13285
13286 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13287                                 struct intel_shared_dpll *pll)
13288 {
13289         /* PCH refclock must be enabled first */
13290         ibx_assert_pch_refclk_enabled(dev_priv);
13291
13292         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13293
13294         /* Wait for the clocks to stabilize. */
13295         POSTING_READ(PCH_DPLL(pll->id));
13296         udelay(150);
13297
13298         /* The pixel multiplier can only be updated once the
13299          * DPLL is enabled and the clocks are stable.
13300          *
13301          * So write it again.
13302          */
13303         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13304         POSTING_READ(PCH_DPLL(pll->id));
13305         udelay(200);
13306 }
13307
13308 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13309                                  struct intel_shared_dpll *pll)
13310 {
13311         struct drm_device *dev = dev_priv->dev;
13312         struct intel_crtc *crtc;
13313
13314         /* Make sure no transcoder isn't still depending on us. */
13315         for_each_intel_crtc(dev, crtc) {
13316                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13317                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13318         }
13319
13320         I915_WRITE(PCH_DPLL(pll->id), 0);
13321         POSTING_READ(PCH_DPLL(pll->id));
13322         udelay(200);
13323 }
13324
13325 static char *ibx_pch_dpll_names[] = {
13326         "PCH DPLL A",
13327         "PCH DPLL B",
13328 };
13329
13330 static void ibx_pch_dpll_init(struct drm_device *dev)
13331 {
13332         struct drm_i915_private *dev_priv = dev->dev_private;
13333         int i;
13334
13335         dev_priv->num_shared_dpll = 2;
13336
13337         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13338                 dev_priv->shared_dplls[i].id = i;
13339                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13340                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13341                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13342                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13343                 dev_priv->shared_dplls[i].get_hw_state =
13344                         ibx_pch_dpll_get_hw_state;
13345         }
13346 }
13347
13348 static void intel_shared_dpll_init(struct drm_device *dev)
13349 {
13350         struct drm_i915_private *dev_priv = dev->dev_private;
13351
13352         if (HAS_DDI(dev))
13353                 intel_ddi_pll_init(dev);
13354         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13355                 ibx_pch_dpll_init(dev);
13356         else
13357                 dev_priv->num_shared_dpll = 0;
13358
13359         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13360 }
13361
13362 /**
13363  * intel_prepare_plane_fb - Prepare fb for usage on plane
13364  * @plane: drm plane to prepare for
13365  * @fb: framebuffer to prepare for presentation
13366  *
13367  * Prepares a framebuffer for usage on a display plane.  Generally this
13368  * involves pinning the underlying object and updating the frontbuffer tracking
13369  * bits.  Some older platforms need special physical address handling for
13370  * cursor planes.
13371  *
13372  * Returns 0 on success, negative error code on failure.
13373  */
13374 int
13375 intel_prepare_plane_fb(struct drm_plane *plane,
13376                        const struct drm_plane_state *new_state)
13377 {
13378         struct drm_device *dev = plane->dev;
13379         struct drm_framebuffer *fb = new_state->fb;
13380         struct intel_plane *intel_plane = to_intel_plane(plane);
13381         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13382         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13383         int ret = 0;
13384
13385         if (!obj)
13386                 return 0;
13387
13388         mutex_lock(&dev->struct_mutex);
13389
13390         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13391             INTEL_INFO(dev)->cursor_needs_physical) {
13392                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13393                 ret = i915_gem_object_attach_phys(obj, align);
13394                 if (ret)
13395                         DRM_DEBUG_KMS("failed to attach phys object\n");
13396         } else {
13397                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13398         }
13399
13400         if (ret == 0)
13401                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13402
13403         mutex_unlock(&dev->struct_mutex);
13404
13405         return ret;
13406 }
13407
13408 /**
13409  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13410  * @plane: drm plane to clean up for
13411  * @fb: old framebuffer that was on plane
13412  *
13413  * Cleans up a framebuffer that has just been removed from a plane.
13414  */
13415 void
13416 intel_cleanup_plane_fb(struct drm_plane *plane,
13417                        const struct drm_plane_state *old_state)
13418 {
13419         struct drm_device *dev = plane->dev;
13420         struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13421
13422         if (!obj)
13423                 return;
13424
13425         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13426             !INTEL_INFO(dev)->cursor_needs_physical) {
13427                 mutex_lock(&dev->struct_mutex);
13428                 intel_unpin_fb_obj(old_state->fb, old_state);
13429                 mutex_unlock(&dev->struct_mutex);
13430         }
13431 }
13432
13433 int
13434 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13435 {
13436         int max_scale;
13437         struct drm_device *dev;
13438         struct drm_i915_private *dev_priv;
13439         int crtc_clock, cdclk;
13440
13441         if (!intel_crtc || !crtc_state)
13442                 return DRM_PLANE_HELPER_NO_SCALING;
13443
13444         dev = intel_crtc->base.dev;
13445         dev_priv = dev->dev_private;
13446         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13447         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13448
13449         if (!crtc_clock || !cdclk)
13450                 return DRM_PLANE_HELPER_NO_SCALING;
13451
13452         /*
13453          * skl max scale is lower of:
13454          *    close to 3 but not 3, -1 is for that purpose
13455          *            or
13456          *    cdclk/crtc_clock
13457          */
13458         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13459
13460         return max_scale;
13461 }
13462
13463 static int
13464 intel_check_primary_plane(struct drm_plane *plane,
13465                           struct intel_crtc_state *crtc_state,
13466                           struct intel_plane_state *state)
13467 {
13468         struct drm_crtc *crtc = state->base.crtc;
13469         struct drm_framebuffer *fb = state->base.fb;
13470         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13471         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13472         bool can_position = false;
13473
13474         /* use scaler when colorkey is not required */
13475         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13476             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13477                 min_scale = 1;
13478                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13479                 can_position = true;
13480         }
13481
13482         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13483                                              &state->dst, &state->clip,
13484                                              min_scale, max_scale,
13485                                              can_position, true,
13486                                              &state->visible);
13487 }
13488
13489 static void
13490 intel_commit_primary_plane(struct drm_plane *plane,
13491                            struct intel_plane_state *state)
13492 {
13493         struct drm_crtc *crtc = state->base.crtc;
13494         struct drm_framebuffer *fb = state->base.fb;
13495         struct drm_device *dev = plane->dev;
13496         struct drm_i915_private *dev_priv = dev->dev_private;
13497         struct intel_crtc *intel_crtc;
13498         struct drm_rect *src = &state->src;
13499
13500         crtc = crtc ? crtc : plane->crtc;
13501         intel_crtc = to_intel_crtc(crtc);
13502
13503         plane->fb = fb;
13504         crtc->x = src->x1 >> 16;
13505         crtc->y = src->y1 >> 16;
13506
13507         if (!crtc->state->active)
13508                 return;
13509
13510         dev_priv->display.update_primary_plane(crtc, fb,
13511                                                state->src.x1 >> 16,
13512                                                state->src.y1 >> 16);
13513 }
13514
13515 static void
13516 intel_disable_primary_plane(struct drm_plane *plane,
13517                             struct drm_crtc *crtc)
13518 {
13519         struct drm_device *dev = plane->dev;
13520         struct drm_i915_private *dev_priv = dev->dev_private;
13521
13522         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13523 }
13524
13525 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13526                                     struct drm_crtc_state *old_crtc_state)
13527 {
13528         struct drm_device *dev = crtc->dev;
13529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13530         struct intel_crtc_state *old_intel_state =
13531                 to_intel_crtc_state(old_crtc_state);
13532         bool modeset = needs_modeset(crtc->state);
13533
13534         if (intel_crtc->atomic.update_wm_pre)
13535                 intel_update_watermarks(crtc);
13536
13537         /* Perform vblank evasion around commit operation */
13538         if (crtc->state->active)
13539                 intel_pipe_update_start(intel_crtc);
13540
13541         if (modeset)
13542                 return;
13543
13544         if (to_intel_crtc_state(crtc->state)->update_pipe)
13545                 intel_update_pipe_config(intel_crtc, old_intel_state);
13546         else if (INTEL_INFO(dev)->gen >= 9)
13547                 skl_detach_scalers(intel_crtc);
13548 }
13549
13550 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13551                                      struct drm_crtc_state *old_crtc_state)
13552 {
13553         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13554
13555         if (crtc->state->active)
13556                 intel_pipe_update_end(intel_crtc);
13557 }
13558
13559 /**
13560  * intel_plane_destroy - destroy a plane
13561  * @plane: plane to destroy
13562  *
13563  * Common destruction function for all types of planes (primary, cursor,
13564  * sprite).
13565  */
13566 void intel_plane_destroy(struct drm_plane *plane)
13567 {
13568         struct intel_plane *intel_plane = to_intel_plane(plane);
13569         drm_plane_cleanup(plane);
13570         kfree(intel_plane);
13571 }
13572
13573 const struct drm_plane_funcs intel_plane_funcs = {
13574         .update_plane = drm_atomic_helper_update_plane,
13575         .disable_plane = drm_atomic_helper_disable_plane,
13576         .destroy = intel_plane_destroy,
13577         .set_property = drm_atomic_helper_plane_set_property,
13578         .atomic_get_property = intel_plane_atomic_get_property,
13579         .atomic_set_property = intel_plane_atomic_set_property,
13580         .atomic_duplicate_state = intel_plane_duplicate_state,
13581         .atomic_destroy_state = intel_plane_destroy_state,
13582
13583 };
13584
13585 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13586                                                     int pipe)
13587 {
13588         struct intel_plane *primary;
13589         struct intel_plane_state *state;
13590         const uint32_t *intel_primary_formats;
13591         unsigned int num_formats;
13592
13593         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13594         if (primary == NULL)
13595                 return NULL;
13596
13597         state = intel_create_plane_state(&primary->base);
13598         if (!state) {
13599                 kfree(primary);
13600                 return NULL;
13601         }
13602         primary->base.state = &state->base;
13603
13604         primary->can_scale = false;
13605         primary->max_downscale = 1;
13606         if (INTEL_INFO(dev)->gen >= 9) {
13607                 primary->can_scale = true;
13608                 state->scaler_id = -1;
13609         }
13610         primary->pipe = pipe;
13611         primary->plane = pipe;
13612         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13613         primary->check_plane = intel_check_primary_plane;
13614         primary->commit_plane = intel_commit_primary_plane;
13615         primary->disable_plane = intel_disable_primary_plane;
13616         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13617                 primary->plane = !pipe;
13618
13619         if (INTEL_INFO(dev)->gen >= 9) {
13620                 intel_primary_formats = skl_primary_formats;
13621                 num_formats = ARRAY_SIZE(skl_primary_formats);
13622         } else if (INTEL_INFO(dev)->gen >= 4) {
13623                 intel_primary_formats = i965_primary_formats;
13624                 num_formats = ARRAY_SIZE(i965_primary_formats);
13625         } else {
13626                 intel_primary_formats = i8xx_primary_formats;
13627                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13628         }
13629
13630         drm_universal_plane_init(dev, &primary->base, 0,
13631                                  &intel_plane_funcs,
13632                                  intel_primary_formats, num_formats,
13633                                  DRM_PLANE_TYPE_PRIMARY);
13634
13635         if (INTEL_INFO(dev)->gen >= 4)
13636                 intel_create_rotation_property(dev, primary);
13637
13638         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13639
13640         return &primary->base;
13641 }
13642
13643 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13644 {
13645         if (!dev->mode_config.rotation_property) {
13646                 unsigned long flags = BIT(DRM_ROTATE_0) |
13647                         BIT(DRM_ROTATE_180);
13648
13649                 if (INTEL_INFO(dev)->gen >= 9)
13650                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13651
13652                 dev->mode_config.rotation_property =
13653                         drm_mode_create_rotation_property(dev, flags);
13654         }
13655         if (dev->mode_config.rotation_property)
13656                 drm_object_attach_property(&plane->base.base,
13657                                 dev->mode_config.rotation_property,
13658                                 plane->base.state->rotation);
13659 }
13660
13661 static int
13662 intel_check_cursor_plane(struct drm_plane *plane,
13663                          struct intel_crtc_state *crtc_state,
13664                          struct intel_plane_state *state)
13665 {
13666         struct drm_crtc *crtc = crtc_state->base.crtc;
13667         struct drm_framebuffer *fb = state->base.fb;
13668         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13669         unsigned stride;
13670         int ret;
13671
13672         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13673                                             &state->dst, &state->clip,
13674                                             DRM_PLANE_HELPER_NO_SCALING,
13675                                             DRM_PLANE_HELPER_NO_SCALING,
13676                                             true, true, &state->visible);
13677         if (ret)
13678                 return ret;
13679
13680         /* if we want to turn off the cursor ignore width and height */
13681         if (!obj)
13682                 return 0;
13683
13684         /* Check for which cursor types we support */
13685         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13686                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13687                           state->base.crtc_w, state->base.crtc_h);
13688                 return -EINVAL;
13689         }
13690
13691         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13692         if (obj->base.size < stride * state->base.crtc_h) {
13693                 DRM_DEBUG_KMS("buffer is too small\n");
13694                 return -ENOMEM;
13695         }
13696
13697         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13698                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13699                 return -EINVAL;
13700         }
13701
13702         return 0;
13703 }
13704
13705 static void
13706 intel_disable_cursor_plane(struct drm_plane *plane,
13707                            struct drm_crtc *crtc)
13708 {
13709         intel_crtc_update_cursor(crtc, false);
13710 }
13711
13712 static void
13713 intel_commit_cursor_plane(struct drm_plane *plane,
13714                           struct intel_plane_state *state)
13715 {
13716         struct drm_crtc *crtc = state->base.crtc;
13717         struct drm_device *dev = plane->dev;
13718         struct intel_crtc *intel_crtc;
13719         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13720         uint32_t addr;
13721
13722         crtc = crtc ? crtc : plane->crtc;
13723         intel_crtc = to_intel_crtc(crtc);
13724
13725         if (intel_crtc->cursor_bo == obj)
13726                 goto update;
13727
13728         if (!obj)
13729                 addr = 0;
13730         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13731                 addr = i915_gem_obj_ggtt_offset(obj);
13732         else
13733                 addr = obj->phys_handle->busaddr;
13734
13735         intel_crtc->cursor_addr = addr;
13736         intel_crtc->cursor_bo = obj;
13737
13738 update:
13739         if (crtc->state->active)
13740                 intel_crtc_update_cursor(crtc, state->visible);
13741 }
13742
13743 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13744                                                    int pipe)
13745 {
13746         struct intel_plane *cursor;
13747         struct intel_plane_state *state;
13748
13749         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13750         if (cursor == NULL)
13751                 return NULL;
13752
13753         state = intel_create_plane_state(&cursor->base);
13754         if (!state) {
13755                 kfree(cursor);
13756                 return NULL;
13757         }
13758         cursor->base.state = &state->base;
13759
13760         cursor->can_scale = false;
13761         cursor->max_downscale = 1;
13762         cursor->pipe = pipe;
13763         cursor->plane = pipe;
13764         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13765         cursor->check_plane = intel_check_cursor_plane;
13766         cursor->commit_plane = intel_commit_cursor_plane;
13767         cursor->disable_plane = intel_disable_cursor_plane;
13768
13769         drm_universal_plane_init(dev, &cursor->base, 0,
13770                                  &intel_plane_funcs,
13771                                  intel_cursor_formats,
13772                                  ARRAY_SIZE(intel_cursor_formats),
13773                                  DRM_PLANE_TYPE_CURSOR);
13774
13775         if (INTEL_INFO(dev)->gen >= 4) {
13776                 if (!dev->mode_config.rotation_property)
13777                         dev->mode_config.rotation_property =
13778                                 drm_mode_create_rotation_property(dev,
13779                                                         BIT(DRM_ROTATE_0) |
13780                                                         BIT(DRM_ROTATE_180));
13781                 if (dev->mode_config.rotation_property)
13782                         drm_object_attach_property(&cursor->base.base,
13783                                 dev->mode_config.rotation_property,
13784                                 state->base.rotation);
13785         }
13786
13787         if (INTEL_INFO(dev)->gen >=9)
13788                 state->scaler_id = -1;
13789
13790         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13791
13792         return &cursor->base;
13793 }
13794
13795 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13796         struct intel_crtc_state *crtc_state)
13797 {
13798         int i;
13799         struct intel_scaler *intel_scaler;
13800         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13801
13802         for (i = 0; i < intel_crtc->num_scalers; i++) {
13803                 intel_scaler = &scaler_state->scalers[i];
13804                 intel_scaler->in_use = 0;
13805                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13806         }
13807
13808         scaler_state->scaler_id = -1;
13809 }
13810
13811 static void intel_crtc_init(struct drm_device *dev, int pipe)
13812 {
13813         struct drm_i915_private *dev_priv = dev->dev_private;
13814         struct intel_crtc *intel_crtc;
13815         struct intel_crtc_state *crtc_state = NULL;
13816         struct drm_plane *primary = NULL;
13817         struct drm_plane *cursor = NULL;
13818         int i, ret;
13819
13820         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13821         if (intel_crtc == NULL)
13822                 return;
13823
13824         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13825         if (!crtc_state)
13826                 goto fail;
13827         intel_crtc->config = crtc_state;
13828         intel_crtc->base.state = &crtc_state->base;
13829         crtc_state->base.crtc = &intel_crtc->base;
13830
13831         /* initialize shared scalers */
13832         if (INTEL_INFO(dev)->gen >= 9) {
13833                 if (pipe == PIPE_C)
13834                         intel_crtc->num_scalers = 1;
13835                 else
13836                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13837
13838                 skl_init_scalers(dev, intel_crtc, crtc_state);
13839         }
13840
13841         primary = intel_primary_plane_create(dev, pipe);
13842         if (!primary)
13843                 goto fail;
13844
13845         cursor = intel_cursor_plane_create(dev, pipe);
13846         if (!cursor)
13847                 goto fail;
13848
13849         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13850                                         cursor, &intel_crtc_funcs);
13851         if (ret)
13852                 goto fail;
13853
13854         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13855         for (i = 0; i < 256; i++) {
13856                 intel_crtc->lut_r[i] = i;
13857                 intel_crtc->lut_g[i] = i;
13858                 intel_crtc->lut_b[i] = i;
13859         }
13860
13861         /*
13862          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13863          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13864          */
13865         intel_crtc->pipe = pipe;
13866         intel_crtc->plane = pipe;
13867         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13868                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13869                 intel_crtc->plane = !pipe;
13870         }
13871
13872         intel_crtc->cursor_base = ~0;
13873         intel_crtc->cursor_cntl = ~0;
13874         intel_crtc->cursor_size = ~0;
13875
13876         intel_crtc->wm.cxsr_allowed = true;
13877
13878         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13879                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13880         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13881         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13882
13883         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13884
13885         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13886         return;
13887
13888 fail:
13889         if (primary)
13890                 drm_plane_cleanup(primary);
13891         if (cursor)
13892                 drm_plane_cleanup(cursor);
13893         kfree(crtc_state);
13894         kfree(intel_crtc);
13895 }
13896
13897 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13898 {
13899         struct drm_encoder *encoder = connector->base.encoder;
13900         struct drm_device *dev = connector->base.dev;
13901
13902         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13903
13904         if (!encoder || WARN_ON(!encoder->crtc))
13905                 return INVALID_PIPE;
13906
13907         return to_intel_crtc(encoder->crtc)->pipe;
13908 }
13909
13910 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13911                                 struct drm_file *file)
13912 {
13913         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13914         struct drm_crtc *drmmode_crtc;
13915         struct intel_crtc *crtc;
13916
13917         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13918
13919         if (!drmmode_crtc) {
13920                 DRM_ERROR("no such CRTC id\n");
13921                 return -ENOENT;
13922         }
13923
13924         crtc = to_intel_crtc(drmmode_crtc);
13925         pipe_from_crtc_id->pipe = crtc->pipe;
13926
13927         return 0;
13928 }
13929
13930 static int intel_encoder_clones(struct intel_encoder *encoder)
13931 {
13932         struct drm_device *dev = encoder->base.dev;
13933         struct intel_encoder *source_encoder;
13934         int index_mask = 0;
13935         int entry = 0;
13936
13937         for_each_intel_encoder(dev, source_encoder) {
13938                 if (encoders_cloneable(encoder, source_encoder))
13939                         index_mask |= (1 << entry);
13940
13941                 entry++;
13942         }
13943
13944         return index_mask;
13945 }
13946
13947 static bool has_edp_a(struct drm_device *dev)
13948 {
13949         struct drm_i915_private *dev_priv = dev->dev_private;
13950
13951         if (!IS_MOBILE(dev))
13952                 return false;
13953
13954         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13955                 return false;
13956
13957         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13958                 return false;
13959
13960         return true;
13961 }
13962
13963 static bool intel_crt_present(struct drm_device *dev)
13964 {
13965         struct drm_i915_private *dev_priv = dev->dev_private;
13966
13967         if (INTEL_INFO(dev)->gen >= 9)
13968                 return false;
13969
13970         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13971                 return false;
13972
13973         if (IS_CHERRYVIEW(dev))
13974                 return false;
13975
13976         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13977                 return false;
13978
13979         return true;
13980 }
13981
13982 static void intel_setup_outputs(struct drm_device *dev)
13983 {
13984         struct drm_i915_private *dev_priv = dev->dev_private;
13985         struct intel_encoder *encoder;
13986         bool dpd_is_edp = false;
13987
13988         intel_lvds_init(dev);
13989
13990         if (intel_crt_present(dev))
13991                 intel_crt_init(dev);
13992
13993         if (IS_BROXTON(dev)) {
13994                 /*
13995                  * FIXME: Broxton doesn't support port detection via the
13996                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13997                  * detect the ports.
13998                  */
13999                 intel_ddi_init(dev, PORT_A);
14000                 intel_ddi_init(dev, PORT_B);
14001                 intel_ddi_init(dev, PORT_C);
14002         } else if (HAS_DDI(dev)) {
14003                 int found;
14004
14005                 /*
14006                  * Haswell uses DDI functions to detect digital outputs.
14007                  * On SKL pre-D0 the strap isn't connected, so we assume
14008                  * it's there.
14009                  */
14010                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14011                 /* WaIgnoreDDIAStrap: skl */
14012                 if (found || IS_SKYLAKE(dev))
14013                         intel_ddi_init(dev, PORT_A);
14014
14015                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14016                  * register */
14017                 found = I915_READ(SFUSE_STRAP);
14018
14019                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14020                         intel_ddi_init(dev, PORT_B);
14021                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14022                         intel_ddi_init(dev, PORT_C);
14023                 if (found & SFUSE_STRAP_DDID_DETECTED)
14024                         intel_ddi_init(dev, PORT_D);
14025                 /*
14026                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14027                  */
14028                 if (IS_SKYLAKE(dev) &&
14029                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14030                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14031                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14032                         intel_ddi_init(dev, PORT_E);
14033
14034         } else if (HAS_PCH_SPLIT(dev)) {
14035                 int found;
14036                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14037
14038                 if (has_edp_a(dev))
14039                         intel_dp_init(dev, DP_A, PORT_A);
14040
14041                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14042                         /* PCH SDVOB multiplex with HDMIB */
14043                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14044                         if (!found)
14045                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14046                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14047                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14048                 }
14049
14050                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14051                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14052
14053                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14054                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14055
14056                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14057                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14058
14059                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14060                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14061         } else if (IS_VALLEYVIEW(dev)) {
14062                 /*
14063                  * The DP_DETECTED bit is the latched state of the DDC
14064                  * SDA pin at boot. However since eDP doesn't require DDC
14065                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14066                  * eDP ports may have been muxed to an alternate function.
14067                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14068                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14069                  * detect eDP ports.
14070                  */
14071                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14072                     !intel_dp_is_edp(dev, PORT_B))
14073                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14074                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14075                     intel_dp_is_edp(dev, PORT_B))
14076                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14077
14078                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14079                     !intel_dp_is_edp(dev, PORT_C))
14080                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14081                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14082                     intel_dp_is_edp(dev, PORT_C))
14083                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14084
14085                 if (IS_CHERRYVIEW(dev)) {
14086                         /* eDP not supported on port D, so don't check VBT */
14087                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14088                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14089                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14090                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14091                 }
14092
14093                 intel_dsi_init(dev);
14094         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14095                 bool found = false;
14096
14097                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14098                         DRM_DEBUG_KMS("probing SDVOB\n");
14099                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14100                         if (!found && IS_G4X(dev)) {
14101                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14102                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14103                         }
14104
14105                         if (!found && IS_G4X(dev))
14106                                 intel_dp_init(dev, DP_B, PORT_B);
14107                 }
14108
14109                 /* Before G4X SDVOC doesn't have its own detect register */
14110
14111                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14112                         DRM_DEBUG_KMS("probing SDVOC\n");
14113                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14114                 }
14115
14116                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14117
14118                         if (IS_G4X(dev)) {
14119                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14120                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14121                         }
14122                         if (IS_G4X(dev))
14123                                 intel_dp_init(dev, DP_C, PORT_C);
14124                 }
14125
14126                 if (IS_G4X(dev) &&
14127                     (I915_READ(DP_D) & DP_DETECTED))
14128                         intel_dp_init(dev, DP_D, PORT_D);
14129         } else if (IS_GEN2(dev))
14130                 intel_dvo_init(dev);
14131
14132         if (SUPPORTS_TV(dev))
14133                 intel_tv_init(dev);
14134
14135         intel_psr_init(dev);
14136
14137         for_each_intel_encoder(dev, encoder) {
14138                 encoder->base.possible_crtcs = encoder->crtc_mask;
14139                 encoder->base.possible_clones =
14140                         intel_encoder_clones(encoder);
14141         }
14142
14143         intel_init_pch_refclk(dev);
14144
14145         drm_helper_move_panel_connectors_to_head(dev);
14146 }
14147
14148 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14149 {
14150         struct drm_device *dev = fb->dev;
14151         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14152
14153         drm_framebuffer_cleanup(fb);
14154         mutex_lock(&dev->struct_mutex);
14155         WARN_ON(!intel_fb->obj->framebuffer_references--);
14156         drm_gem_object_unreference(&intel_fb->obj->base);
14157         mutex_unlock(&dev->struct_mutex);
14158         kfree(intel_fb);
14159 }
14160
14161 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14162                                                 struct drm_file *file,
14163                                                 unsigned int *handle)
14164 {
14165         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14166         struct drm_i915_gem_object *obj = intel_fb->obj;
14167
14168         if (obj->userptr.mm) {
14169                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14170                 return -EINVAL;
14171         }
14172
14173         return drm_gem_handle_create(file, &obj->base, handle);
14174 }
14175
14176 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14177                                         struct drm_file *file,
14178                                         unsigned flags, unsigned color,
14179                                         struct drm_clip_rect *clips,
14180                                         unsigned num_clips)
14181 {
14182         struct drm_device *dev = fb->dev;
14183         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14184         struct drm_i915_gem_object *obj = intel_fb->obj;
14185
14186         mutex_lock(&dev->struct_mutex);
14187         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14188         mutex_unlock(&dev->struct_mutex);
14189
14190         return 0;
14191 }
14192
14193 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14194         .destroy = intel_user_framebuffer_destroy,
14195         .create_handle = intel_user_framebuffer_create_handle,
14196         .dirty = intel_user_framebuffer_dirty,
14197 };
14198
14199 static
14200 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14201                          uint32_t pixel_format)
14202 {
14203         u32 gen = INTEL_INFO(dev)->gen;
14204
14205         if (gen >= 9) {
14206                 /* "The stride in bytes must not exceed the of the size of 8K
14207                  *  pixels and 32K bytes."
14208                  */
14209                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14210         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14211                 return 32*1024;
14212         } else if (gen >= 4) {
14213                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14214                         return 16*1024;
14215                 else
14216                         return 32*1024;
14217         } else if (gen >= 3) {
14218                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14219                         return 8*1024;
14220                 else
14221                         return 16*1024;
14222         } else {
14223                 /* XXX DSPC is limited to 4k tiled */
14224                 return 8*1024;
14225         }
14226 }
14227
14228 static int intel_framebuffer_init(struct drm_device *dev,
14229                                   struct intel_framebuffer *intel_fb,
14230                                   struct drm_mode_fb_cmd2 *mode_cmd,
14231                                   struct drm_i915_gem_object *obj)
14232 {
14233         unsigned int aligned_height;
14234         int ret;
14235         u32 pitch_limit, stride_alignment;
14236
14237         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14238
14239         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14240                 /* Enforce that fb modifier and tiling mode match, but only for
14241                  * X-tiled. This is needed for FBC. */
14242                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14243                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14244                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14245                         return -EINVAL;
14246                 }
14247         } else {
14248                 if (obj->tiling_mode == I915_TILING_X)
14249                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14250                 else if (obj->tiling_mode == I915_TILING_Y) {
14251                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14252                         return -EINVAL;
14253                 }
14254         }
14255
14256         /* Passed in modifier sanity checking. */
14257         switch (mode_cmd->modifier[0]) {
14258         case I915_FORMAT_MOD_Y_TILED:
14259         case I915_FORMAT_MOD_Yf_TILED:
14260                 if (INTEL_INFO(dev)->gen < 9) {
14261                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14262                                   mode_cmd->modifier[0]);
14263                         return -EINVAL;
14264                 }
14265         case DRM_FORMAT_MOD_NONE:
14266         case I915_FORMAT_MOD_X_TILED:
14267                 break;
14268         default:
14269                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14270                           mode_cmd->modifier[0]);
14271                 return -EINVAL;
14272         }
14273
14274         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14275                                                      mode_cmd->pixel_format);
14276         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14277                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14278                           mode_cmd->pitches[0], stride_alignment);
14279                 return -EINVAL;
14280         }
14281
14282         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14283                                            mode_cmd->pixel_format);
14284         if (mode_cmd->pitches[0] > pitch_limit) {
14285                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14286                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14287                           "tiled" : "linear",
14288                           mode_cmd->pitches[0], pitch_limit);
14289                 return -EINVAL;
14290         }
14291
14292         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14293             mode_cmd->pitches[0] != obj->stride) {
14294                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14295                           mode_cmd->pitches[0], obj->stride);
14296                 return -EINVAL;
14297         }
14298
14299         /* Reject formats not supported by any plane early. */
14300         switch (mode_cmd->pixel_format) {
14301         case DRM_FORMAT_C8:
14302         case DRM_FORMAT_RGB565:
14303         case DRM_FORMAT_XRGB8888:
14304         case DRM_FORMAT_ARGB8888:
14305                 break;
14306         case DRM_FORMAT_XRGB1555:
14307                 if (INTEL_INFO(dev)->gen > 3) {
14308                         DRM_DEBUG("unsupported pixel format: %s\n",
14309                                   drm_get_format_name(mode_cmd->pixel_format));
14310                         return -EINVAL;
14311                 }
14312                 break;
14313         case DRM_FORMAT_ABGR8888:
14314                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14315                         DRM_DEBUG("unsupported pixel format: %s\n",
14316                                   drm_get_format_name(mode_cmd->pixel_format));
14317                         return -EINVAL;
14318                 }
14319                 break;
14320         case DRM_FORMAT_XBGR8888:
14321         case DRM_FORMAT_XRGB2101010:
14322         case DRM_FORMAT_XBGR2101010:
14323                 if (INTEL_INFO(dev)->gen < 4) {
14324                         DRM_DEBUG("unsupported pixel format: %s\n",
14325                                   drm_get_format_name(mode_cmd->pixel_format));
14326                         return -EINVAL;
14327                 }
14328                 break;
14329         case DRM_FORMAT_ABGR2101010:
14330                 if (!IS_VALLEYVIEW(dev)) {
14331                         DRM_DEBUG("unsupported pixel format: %s\n",
14332                                   drm_get_format_name(mode_cmd->pixel_format));
14333                         return -EINVAL;
14334                 }
14335                 break;
14336         case DRM_FORMAT_YUYV:
14337         case DRM_FORMAT_UYVY:
14338         case DRM_FORMAT_YVYU:
14339         case DRM_FORMAT_VYUY:
14340                 if (INTEL_INFO(dev)->gen < 5) {
14341                         DRM_DEBUG("unsupported pixel format: %s\n",
14342                                   drm_get_format_name(mode_cmd->pixel_format));
14343                         return -EINVAL;
14344                 }
14345                 break;
14346         default:
14347                 DRM_DEBUG("unsupported pixel format: %s\n",
14348                           drm_get_format_name(mode_cmd->pixel_format));
14349                 return -EINVAL;
14350         }
14351
14352         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14353         if (mode_cmd->offsets[0] != 0)
14354                 return -EINVAL;
14355
14356         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14357                                                mode_cmd->pixel_format,
14358                                                mode_cmd->modifier[0]);
14359         /* FIXME drm helper for size checks (especially planar formats)? */
14360         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14361                 return -EINVAL;
14362
14363         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14364         intel_fb->obj = obj;
14365         intel_fb->obj->framebuffer_references++;
14366
14367         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14368         if (ret) {
14369                 DRM_ERROR("framebuffer init failed %d\n", ret);
14370                 return ret;
14371         }
14372
14373         return 0;
14374 }
14375
14376 static struct drm_framebuffer *
14377 intel_user_framebuffer_create(struct drm_device *dev,
14378                               struct drm_file *filp,
14379                               struct drm_mode_fb_cmd2 *user_mode_cmd)
14380 {
14381         struct drm_i915_gem_object *obj;
14382         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14383
14384         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14385                                                 mode_cmd.handles[0]));
14386         if (&obj->base == NULL)
14387                 return ERR_PTR(-ENOENT);
14388
14389         return intel_framebuffer_create(dev, &mode_cmd, obj);
14390 }
14391
14392 #ifndef CONFIG_DRM_FBDEV_EMULATION
14393 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14394 {
14395 }
14396 #endif
14397
14398 static const struct drm_mode_config_funcs intel_mode_funcs = {
14399         .fb_create = intel_user_framebuffer_create,
14400         .output_poll_changed = intel_fbdev_output_poll_changed,
14401         .atomic_check = intel_atomic_check,
14402         .atomic_commit = intel_atomic_commit,
14403         .atomic_state_alloc = intel_atomic_state_alloc,
14404         .atomic_state_clear = intel_atomic_state_clear,
14405 };
14406
14407 /* Set up chip specific display functions */
14408 static void intel_init_display(struct drm_device *dev)
14409 {
14410         struct drm_i915_private *dev_priv = dev->dev_private;
14411
14412         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14413                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14414         else if (IS_CHERRYVIEW(dev))
14415                 dev_priv->display.find_dpll = chv_find_best_dpll;
14416         else if (IS_VALLEYVIEW(dev))
14417                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14418         else if (IS_PINEVIEW(dev))
14419                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14420         else
14421                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14422
14423         if (INTEL_INFO(dev)->gen >= 9) {
14424                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14425                 dev_priv->display.get_initial_plane_config =
14426                         skylake_get_initial_plane_config;
14427                 dev_priv->display.crtc_compute_clock =
14428                         haswell_crtc_compute_clock;
14429                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14430                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14431                 dev_priv->display.update_primary_plane =
14432                         skylake_update_primary_plane;
14433         } else if (HAS_DDI(dev)) {
14434                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14435                 dev_priv->display.get_initial_plane_config =
14436                         ironlake_get_initial_plane_config;
14437                 dev_priv->display.crtc_compute_clock =
14438                         haswell_crtc_compute_clock;
14439                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14440                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14441                 dev_priv->display.update_primary_plane =
14442                         ironlake_update_primary_plane;
14443         } else if (HAS_PCH_SPLIT(dev)) {
14444                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14445                 dev_priv->display.get_initial_plane_config =
14446                         ironlake_get_initial_plane_config;
14447                 dev_priv->display.crtc_compute_clock =
14448                         ironlake_crtc_compute_clock;
14449                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14450                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14451                 dev_priv->display.update_primary_plane =
14452                         ironlake_update_primary_plane;
14453         } else if (IS_VALLEYVIEW(dev)) {
14454                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14455                 dev_priv->display.get_initial_plane_config =
14456                         i9xx_get_initial_plane_config;
14457                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14458                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14459                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14460                 dev_priv->display.update_primary_plane =
14461                         i9xx_update_primary_plane;
14462         } else {
14463                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14464                 dev_priv->display.get_initial_plane_config =
14465                         i9xx_get_initial_plane_config;
14466                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14467                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14468                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14469                 dev_priv->display.update_primary_plane =
14470                         i9xx_update_primary_plane;
14471         }
14472
14473         /* Returns the core display clock speed */
14474         if (IS_SKYLAKE(dev))
14475                 dev_priv->display.get_display_clock_speed =
14476                         skylake_get_display_clock_speed;
14477         else if (IS_BROXTON(dev))
14478                 dev_priv->display.get_display_clock_speed =
14479                         broxton_get_display_clock_speed;
14480         else if (IS_BROADWELL(dev))
14481                 dev_priv->display.get_display_clock_speed =
14482                         broadwell_get_display_clock_speed;
14483         else if (IS_HASWELL(dev))
14484                 dev_priv->display.get_display_clock_speed =
14485                         haswell_get_display_clock_speed;
14486         else if (IS_VALLEYVIEW(dev))
14487                 dev_priv->display.get_display_clock_speed =
14488                         valleyview_get_display_clock_speed;
14489         else if (IS_GEN5(dev))
14490                 dev_priv->display.get_display_clock_speed =
14491                         ilk_get_display_clock_speed;
14492         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14493                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14494                 dev_priv->display.get_display_clock_speed =
14495                         i945_get_display_clock_speed;
14496         else if (IS_GM45(dev))
14497                 dev_priv->display.get_display_clock_speed =
14498                         gm45_get_display_clock_speed;
14499         else if (IS_CRESTLINE(dev))
14500                 dev_priv->display.get_display_clock_speed =
14501                         i965gm_get_display_clock_speed;
14502         else if (IS_PINEVIEW(dev))
14503                 dev_priv->display.get_display_clock_speed =
14504                         pnv_get_display_clock_speed;
14505         else if (IS_G33(dev) || IS_G4X(dev))
14506                 dev_priv->display.get_display_clock_speed =
14507                         g33_get_display_clock_speed;
14508         else if (IS_I915G(dev))
14509                 dev_priv->display.get_display_clock_speed =
14510                         i915_get_display_clock_speed;
14511         else if (IS_I945GM(dev) || IS_845G(dev))
14512                 dev_priv->display.get_display_clock_speed =
14513                         i9xx_misc_get_display_clock_speed;
14514         else if (IS_PINEVIEW(dev))
14515                 dev_priv->display.get_display_clock_speed =
14516                         pnv_get_display_clock_speed;
14517         else if (IS_I915GM(dev))
14518                 dev_priv->display.get_display_clock_speed =
14519                         i915gm_get_display_clock_speed;
14520         else if (IS_I865G(dev))
14521                 dev_priv->display.get_display_clock_speed =
14522                         i865_get_display_clock_speed;
14523         else if (IS_I85X(dev))
14524                 dev_priv->display.get_display_clock_speed =
14525                         i85x_get_display_clock_speed;
14526         else { /* 830 */
14527                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14528                 dev_priv->display.get_display_clock_speed =
14529                         i830_get_display_clock_speed;
14530         }
14531
14532         if (IS_GEN5(dev)) {
14533                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14534         } else if (IS_GEN6(dev)) {
14535                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14536         } else if (IS_IVYBRIDGE(dev)) {
14537                 /* FIXME: detect B0+ stepping and use auto training */
14538                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14539         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14540                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14541                 if (IS_BROADWELL(dev)) {
14542                         dev_priv->display.modeset_commit_cdclk =
14543                                 broadwell_modeset_commit_cdclk;
14544                         dev_priv->display.modeset_calc_cdclk =
14545                                 broadwell_modeset_calc_cdclk;
14546                 }
14547         } else if (IS_VALLEYVIEW(dev)) {
14548                 dev_priv->display.modeset_commit_cdclk =
14549                         valleyview_modeset_commit_cdclk;
14550                 dev_priv->display.modeset_calc_cdclk =
14551                         valleyview_modeset_calc_cdclk;
14552         } else if (IS_BROXTON(dev)) {
14553                 dev_priv->display.modeset_commit_cdclk =
14554                         broxton_modeset_commit_cdclk;
14555                 dev_priv->display.modeset_calc_cdclk =
14556                         broxton_modeset_calc_cdclk;
14557         }
14558
14559         switch (INTEL_INFO(dev)->gen) {
14560         case 2:
14561                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14562                 break;
14563
14564         case 3:
14565                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14566                 break;
14567
14568         case 4:
14569         case 5:
14570                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14571                 break;
14572
14573         case 6:
14574                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14575                 break;
14576         case 7:
14577         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14578                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14579                 break;
14580         case 9:
14581                 /* Drop through - unsupported since execlist only. */
14582         default:
14583                 /* Default just returns -ENODEV to indicate unsupported */
14584                 dev_priv->display.queue_flip = intel_default_queue_flip;
14585         }
14586
14587         mutex_init(&dev_priv->pps_mutex);
14588 }
14589
14590 /*
14591  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14592  * resume, or other times.  This quirk makes sure that's the case for
14593  * affected systems.
14594  */
14595 static void quirk_pipea_force(struct drm_device *dev)
14596 {
14597         struct drm_i915_private *dev_priv = dev->dev_private;
14598
14599         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14600         DRM_INFO("applying pipe a force quirk\n");
14601 }
14602
14603 static void quirk_pipeb_force(struct drm_device *dev)
14604 {
14605         struct drm_i915_private *dev_priv = dev->dev_private;
14606
14607         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14608         DRM_INFO("applying pipe b force quirk\n");
14609 }
14610
14611 /*
14612  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14613  */
14614 static void quirk_ssc_force_disable(struct drm_device *dev)
14615 {
14616         struct drm_i915_private *dev_priv = dev->dev_private;
14617         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14618         DRM_INFO("applying lvds SSC disable quirk\n");
14619 }
14620
14621 /*
14622  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14623  * brightness value
14624  */
14625 static void quirk_invert_brightness(struct drm_device *dev)
14626 {
14627         struct drm_i915_private *dev_priv = dev->dev_private;
14628         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14629         DRM_INFO("applying inverted panel brightness quirk\n");
14630 }
14631
14632 /* Some VBT's incorrectly indicate no backlight is present */
14633 static void quirk_backlight_present(struct drm_device *dev)
14634 {
14635         struct drm_i915_private *dev_priv = dev->dev_private;
14636         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14637         DRM_INFO("applying backlight present quirk\n");
14638 }
14639
14640 struct intel_quirk {
14641         int device;
14642         int subsystem_vendor;
14643         int subsystem_device;
14644         void (*hook)(struct drm_device *dev);
14645 };
14646
14647 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14648 struct intel_dmi_quirk {
14649         void (*hook)(struct drm_device *dev);
14650         const struct dmi_system_id (*dmi_id_list)[];
14651 };
14652
14653 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14654 {
14655         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14656         return 1;
14657 }
14658
14659 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14660         {
14661                 .dmi_id_list = &(const struct dmi_system_id[]) {
14662                         {
14663                                 .callback = intel_dmi_reverse_brightness,
14664                                 .ident = "NCR Corporation",
14665                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14666                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14667                                 },
14668                         },
14669                         { }  /* terminating entry */
14670                 },
14671                 .hook = quirk_invert_brightness,
14672         },
14673 };
14674
14675 static struct intel_quirk intel_quirks[] = {
14676         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14677         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14678
14679         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14680         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14681
14682         /* 830 needs to leave pipe A & dpll A up */
14683         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14684
14685         /* 830 needs to leave pipe B & dpll B up */
14686         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14687
14688         /* Lenovo U160 cannot use SSC on LVDS */
14689         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14690
14691         /* Sony Vaio Y cannot use SSC on LVDS */
14692         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14693
14694         /* Acer Aspire 5734Z must invert backlight brightness */
14695         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14696
14697         /* Acer/eMachines G725 */
14698         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14699
14700         /* Acer/eMachines e725 */
14701         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14702
14703         /* Acer/Packard Bell NCL20 */
14704         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14705
14706         /* Acer Aspire 4736Z */
14707         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14708
14709         /* Acer Aspire 5336 */
14710         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14711
14712         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14713         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14714
14715         /* Acer C720 Chromebook (Core i3 4005U) */
14716         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14717
14718         /* Apple Macbook 2,1 (Core 2 T7400) */
14719         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14720
14721         /* Apple Macbook 4,1 */
14722         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14723
14724         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14725         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14726
14727         /* HP Chromebook 14 (Celeron 2955U) */
14728         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14729
14730         /* Dell Chromebook 11 */
14731         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14732
14733         /* Dell Chromebook 11 (2015 version) */
14734         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14735 };
14736
14737 static void intel_init_quirks(struct drm_device *dev)
14738 {
14739         struct pci_dev *d = dev->pdev;
14740         int i;
14741
14742         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14743                 struct intel_quirk *q = &intel_quirks[i];
14744
14745                 if (d->device == q->device &&
14746                     (d->subsystem_vendor == q->subsystem_vendor ||
14747                      q->subsystem_vendor == PCI_ANY_ID) &&
14748                     (d->subsystem_device == q->subsystem_device ||
14749                      q->subsystem_device == PCI_ANY_ID))
14750                         q->hook(dev);
14751         }
14752         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14753                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14754                         intel_dmi_quirks[i].hook(dev);
14755         }
14756 }
14757
14758 /* Disable the VGA plane that we never use */
14759 static void i915_disable_vga(struct drm_device *dev)
14760 {
14761         struct drm_i915_private *dev_priv = dev->dev_private;
14762         u8 sr1;
14763         u32 vga_reg = i915_vgacntrl_reg(dev);
14764
14765         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14766         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14767         outb(SR01, VGA_SR_INDEX);
14768         sr1 = inb(VGA_SR_DATA);
14769         outb(sr1 | 1<<5, VGA_SR_DATA);
14770         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14771         udelay(300);
14772
14773         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14774         POSTING_READ(vga_reg);
14775 }
14776
14777 void intel_modeset_init_hw(struct drm_device *dev)
14778 {
14779         intel_update_cdclk(dev);
14780         intel_prepare_ddi(dev);
14781         intel_init_clock_gating(dev);
14782         intel_enable_gt_powersave(dev);
14783 }
14784
14785 void intel_modeset_init(struct drm_device *dev)
14786 {
14787         struct drm_i915_private *dev_priv = dev->dev_private;
14788         int sprite, ret;
14789         enum pipe pipe;
14790         struct intel_crtc *crtc;
14791
14792         drm_mode_config_init(dev);
14793
14794         dev->mode_config.min_width = 0;
14795         dev->mode_config.min_height = 0;
14796
14797         dev->mode_config.preferred_depth = 24;
14798         dev->mode_config.prefer_shadow = 1;
14799
14800         dev->mode_config.allow_fb_modifiers = true;
14801
14802         dev->mode_config.funcs = &intel_mode_funcs;
14803
14804         intel_init_quirks(dev);
14805
14806         intel_init_pm(dev);
14807
14808         if (INTEL_INFO(dev)->num_pipes == 0)
14809                 return;
14810
14811         /*
14812          * There may be no VBT; and if the BIOS enabled SSC we can
14813          * just keep using it to avoid unnecessary flicker.  Whereas if the
14814          * BIOS isn't using it, don't assume it will work even if the VBT
14815          * indicates as much.
14816          */
14817         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14818                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14819                                             DREF_SSC1_ENABLE);
14820
14821                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14822                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14823                                      bios_lvds_use_ssc ? "en" : "dis",
14824                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14825                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14826                 }
14827         }
14828
14829         intel_init_display(dev);
14830         intel_init_audio(dev);
14831
14832         if (IS_GEN2(dev)) {
14833                 dev->mode_config.max_width = 2048;
14834                 dev->mode_config.max_height = 2048;
14835         } else if (IS_GEN3(dev)) {
14836                 dev->mode_config.max_width = 4096;
14837                 dev->mode_config.max_height = 4096;
14838         } else {
14839                 dev->mode_config.max_width = 8192;
14840                 dev->mode_config.max_height = 8192;
14841         }
14842
14843         if (IS_845G(dev) || IS_I865G(dev)) {
14844                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14845                 dev->mode_config.cursor_height = 1023;
14846         } else if (IS_GEN2(dev)) {
14847                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14848                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14849         } else {
14850                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14851                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14852         }
14853
14854         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14855
14856         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14857                       INTEL_INFO(dev)->num_pipes,
14858                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14859
14860         for_each_pipe(dev_priv, pipe) {
14861                 intel_crtc_init(dev, pipe);
14862                 for_each_sprite(dev_priv, pipe, sprite) {
14863                         ret = intel_plane_init(dev, pipe, sprite);
14864                         if (ret)
14865                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14866                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14867                 }
14868         }
14869
14870         intel_update_czclk(dev_priv);
14871         intel_update_cdclk(dev);
14872
14873         intel_shared_dpll_init(dev);
14874
14875         /* Just disable it once at startup */
14876         i915_disable_vga(dev);
14877         intel_setup_outputs(dev);
14878
14879         /* Just in case the BIOS is doing something questionable. */
14880         intel_fbc_disable(dev_priv);
14881
14882         drm_modeset_lock_all(dev);
14883         intel_modeset_setup_hw_state(dev);
14884         drm_modeset_unlock_all(dev);
14885
14886         for_each_intel_crtc(dev, crtc) {
14887                 struct intel_initial_plane_config plane_config = {};
14888
14889                 if (!crtc->active)
14890                         continue;
14891
14892                 /*
14893                  * Note that reserving the BIOS fb up front prevents us
14894                  * from stuffing other stolen allocations like the ring
14895                  * on top.  This prevents some ugliness at boot time, and
14896                  * can even allow for smooth boot transitions if the BIOS
14897                  * fb is large enough for the active pipe configuration.
14898                  */
14899                 dev_priv->display.get_initial_plane_config(crtc,
14900                                                            &plane_config);
14901
14902                 /*
14903                  * If the fb is shared between multiple heads, we'll
14904                  * just get the first one.
14905                  */
14906                 intel_find_initial_plane_obj(crtc, &plane_config);
14907         }
14908 }
14909
14910 static void intel_enable_pipe_a(struct drm_device *dev)
14911 {
14912         struct intel_connector *connector;
14913         struct drm_connector *crt = NULL;
14914         struct intel_load_detect_pipe load_detect_temp;
14915         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14916
14917         /* We can't just switch on the pipe A, we need to set things up with a
14918          * proper mode and output configuration. As a gross hack, enable pipe A
14919          * by enabling the load detect pipe once. */
14920         for_each_intel_connector(dev, connector) {
14921                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14922                         crt = &connector->base;
14923                         break;
14924                 }
14925         }
14926
14927         if (!crt)
14928                 return;
14929
14930         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14931                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14932 }
14933
14934 static bool
14935 intel_check_plane_mapping(struct intel_crtc *crtc)
14936 {
14937         struct drm_device *dev = crtc->base.dev;
14938         struct drm_i915_private *dev_priv = dev->dev_private;
14939         u32 val;
14940
14941         if (INTEL_INFO(dev)->num_pipes == 1)
14942                 return true;
14943
14944         val = I915_READ(DSPCNTR(!crtc->plane));
14945
14946         if ((val & DISPLAY_PLANE_ENABLE) &&
14947             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14948                 return false;
14949
14950         return true;
14951 }
14952
14953 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14954 {
14955         struct drm_device *dev = crtc->base.dev;
14956         struct intel_encoder *encoder;
14957
14958         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14959                 return true;
14960
14961         return false;
14962 }
14963
14964 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14965 {
14966         struct drm_device *dev = crtc->base.dev;
14967         struct drm_i915_private *dev_priv = dev->dev_private;
14968         u32 reg;
14969
14970         /* Clear any frame start delays used for debugging left by the BIOS */
14971         reg = PIPECONF(crtc->config->cpu_transcoder);
14972         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14973
14974         /* restore vblank interrupts to correct state */
14975         drm_crtc_vblank_reset(&crtc->base);
14976         if (crtc->active) {
14977                 struct intel_plane *plane;
14978
14979                 drm_crtc_vblank_on(&crtc->base);
14980
14981                 /* Disable everything but the primary plane */
14982                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14983                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14984                                 continue;
14985
14986                         plane->disable_plane(&plane->base, &crtc->base);
14987                 }
14988         }
14989
14990         /* We need to sanitize the plane -> pipe mapping first because this will
14991          * disable the crtc (and hence change the state) if it is wrong. Note
14992          * that gen4+ has a fixed plane -> pipe mapping.  */
14993         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14994                 bool plane;
14995
14996                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14997                               crtc->base.base.id);
14998
14999                 /* Pipe has the wrong plane attached and the plane is active.
15000                  * Temporarily change the plane mapping and disable everything
15001                  * ...  */
15002                 plane = crtc->plane;
15003                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15004                 crtc->plane = !plane;
15005                 intel_crtc_disable_noatomic(&crtc->base);
15006                 crtc->plane = plane;
15007         }
15008
15009         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15010             crtc->pipe == PIPE_A && !crtc->active) {
15011                 /* BIOS forgot to enable pipe A, this mostly happens after
15012                  * resume. Force-enable the pipe to fix this, the update_dpms
15013                  * call below we restore the pipe to the right state, but leave
15014                  * the required bits on. */
15015                 intel_enable_pipe_a(dev);
15016         }
15017
15018         /* Adjust the state of the output pipe according to whether we
15019          * have active connectors/encoders. */
15020         if (!intel_crtc_has_encoders(crtc))
15021                 intel_crtc_disable_noatomic(&crtc->base);
15022
15023         if (crtc->active != crtc->base.state->active) {
15024                 struct intel_encoder *encoder;
15025
15026                 /* This can happen either due to bugs in the get_hw_state
15027                  * functions or because of calls to intel_crtc_disable_noatomic,
15028                  * or because the pipe is force-enabled due to the
15029                  * pipe A quirk. */
15030                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15031                               crtc->base.base.id,
15032                               crtc->base.state->enable ? "enabled" : "disabled",
15033                               crtc->active ? "enabled" : "disabled");
15034
15035                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15036                 crtc->base.state->active = crtc->active;
15037                 crtc->base.enabled = crtc->active;
15038
15039                 /* Because we only establish the connector -> encoder ->
15040                  * crtc links if something is active, this means the
15041                  * crtc is now deactivated. Break the links. connector
15042                  * -> encoder links are only establish when things are
15043                  *  actually up, hence no need to break them. */
15044                 WARN_ON(crtc->active);
15045
15046                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15047                         encoder->base.crtc = NULL;
15048         }
15049
15050         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15051                 /*
15052                  * We start out with underrun reporting disabled to avoid races.
15053                  * For correct bookkeeping mark this on active crtcs.
15054                  *
15055                  * Also on gmch platforms we dont have any hardware bits to
15056                  * disable the underrun reporting. Which means we need to start
15057                  * out with underrun reporting disabled also on inactive pipes,
15058                  * since otherwise we'll complain about the garbage we read when
15059                  * e.g. coming up after runtime pm.
15060                  *
15061                  * No protection against concurrent access is required - at
15062                  * worst a fifo underrun happens which also sets this to false.
15063                  */
15064                 crtc->cpu_fifo_underrun_disabled = true;
15065                 crtc->pch_fifo_underrun_disabled = true;
15066         }
15067 }
15068
15069 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15070 {
15071         struct intel_connector *connector;
15072         struct drm_device *dev = encoder->base.dev;
15073         bool active = false;
15074
15075         /* We need to check both for a crtc link (meaning that the
15076          * encoder is active and trying to read from a pipe) and the
15077          * pipe itself being active. */
15078         bool has_active_crtc = encoder->base.crtc &&
15079                 to_intel_crtc(encoder->base.crtc)->active;
15080
15081         for_each_intel_connector(dev, connector) {
15082                 if (connector->base.encoder != &encoder->base)
15083                         continue;
15084
15085                 active = true;
15086                 break;
15087         }
15088
15089         if (active && !has_active_crtc) {
15090                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15091                               encoder->base.base.id,
15092                               encoder->base.name);
15093
15094                 /* Connector is active, but has no active pipe. This is
15095                  * fallout from our resume register restoring. Disable
15096                  * the encoder manually again. */
15097                 if (encoder->base.crtc) {
15098                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15099                                       encoder->base.base.id,
15100                                       encoder->base.name);
15101                         encoder->disable(encoder);
15102                         if (encoder->post_disable)
15103                                 encoder->post_disable(encoder);
15104                 }
15105                 encoder->base.crtc = NULL;
15106
15107                 /* Inconsistent output/port/pipe state happens presumably due to
15108                  * a bug in one of the get_hw_state functions. Or someplace else
15109                  * in our code, like the register restore mess on resume. Clamp
15110                  * things to off as a safer default. */
15111                 for_each_intel_connector(dev, connector) {
15112                         if (connector->encoder != encoder)
15113                                 continue;
15114                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15115                         connector->base.encoder = NULL;
15116                 }
15117         }
15118         /* Enabled encoders without active connectors will be fixed in
15119          * the crtc fixup. */
15120 }
15121
15122 void i915_redisable_vga_power_on(struct drm_device *dev)
15123 {
15124         struct drm_i915_private *dev_priv = dev->dev_private;
15125         u32 vga_reg = i915_vgacntrl_reg(dev);
15126
15127         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15128                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15129                 i915_disable_vga(dev);
15130         }
15131 }
15132
15133 void i915_redisable_vga(struct drm_device *dev)
15134 {
15135         struct drm_i915_private *dev_priv = dev->dev_private;
15136
15137         /* This function can be called both from intel_modeset_setup_hw_state or
15138          * at a very early point in our resume sequence, where the power well
15139          * structures are not yet restored. Since this function is at a very
15140          * paranoid "someone might have enabled VGA while we were not looking"
15141          * level, just check if the power well is enabled instead of trying to
15142          * follow the "don't touch the power well if we don't need it" policy
15143          * the rest of the driver uses. */
15144         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15145                 return;
15146
15147         i915_redisable_vga_power_on(dev);
15148 }
15149
15150 static bool primary_get_hw_state(struct intel_plane *plane)
15151 {
15152         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15153
15154         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15155 }
15156
15157 /* FIXME read out full plane state for all planes */
15158 static void readout_plane_state(struct intel_crtc *crtc)
15159 {
15160         struct drm_plane *primary = crtc->base.primary;
15161         struct intel_plane_state *plane_state =
15162                 to_intel_plane_state(primary->state);
15163
15164         plane_state->visible =
15165                 primary_get_hw_state(to_intel_plane(primary));
15166
15167         if (plane_state->visible)
15168                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15169 }
15170
15171 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15172 {
15173         struct drm_i915_private *dev_priv = dev->dev_private;
15174         enum pipe pipe;
15175         struct intel_crtc *crtc;
15176         struct intel_encoder *encoder;
15177         struct intel_connector *connector;
15178         int i;
15179
15180         for_each_intel_crtc(dev, crtc) {
15181                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15182                 memset(crtc->config, 0, sizeof(*crtc->config));
15183                 crtc->config->base.crtc = &crtc->base;
15184
15185                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15186                                                                  crtc->config);
15187
15188                 crtc->base.state->active = crtc->active;
15189                 crtc->base.enabled = crtc->active;
15190
15191                 readout_plane_state(crtc);
15192
15193                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15194                               crtc->base.base.id,
15195                               crtc->active ? "enabled" : "disabled");
15196         }
15197
15198         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15199                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15200
15201                 pll->on = pll->get_hw_state(dev_priv, pll,
15202                                             &pll->config.hw_state);
15203                 pll->active = 0;
15204                 pll->config.crtc_mask = 0;
15205                 for_each_intel_crtc(dev, crtc) {
15206                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15207                                 pll->active++;
15208                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15209                         }
15210                 }
15211
15212                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15213                               pll->name, pll->config.crtc_mask, pll->on);
15214
15215                 if (pll->config.crtc_mask)
15216                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15217         }
15218
15219         for_each_intel_encoder(dev, encoder) {
15220                 pipe = 0;
15221
15222                 if (encoder->get_hw_state(encoder, &pipe)) {
15223                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15224                         encoder->base.crtc = &crtc->base;
15225                         encoder->get_config(encoder, crtc->config);
15226                 } else {
15227                         encoder->base.crtc = NULL;
15228                 }
15229
15230                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15231                               encoder->base.base.id,
15232                               encoder->base.name,
15233                               encoder->base.crtc ? "enabled" : "disabled",
15234                               pipe_name(pipe));
15235         }
15236
15237         for_each_intel_connector(dev, connector) {
15238                 if (connector->get_hw_state(connector)) {
15239                         connector->base.dpms = DRM_MODE_DPMS_ON;
15240                         connector->base.encoder = &connector->encoder->base;
15241                 } else {
15242                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15243                         connector->base.encoder = NULL;
15244                 }
15245                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15246                               connector->base.base.id,
15247                               connector->base.name,
15248                               connector->base.encoder ? "enabled" : "disabled");
15249         }
15250
15251         for_each_intel_crtc(dev, crtc) {
15252                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15253
15254                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15255                 if (crtc->base.state->active) {
15256                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15257                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15258                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15259
15260                         /*
15261                          * The initial mode needs to be set in order to keep
15262                          * the atomic core happy. It wants a valid mode if the
15263                          * crtc's enabled, so we do the above call.
15264                          *
15265                          * At this point some state updated by the connectors
15266                          * in their ->detect() callback has not run yet, so
15267                          * no recalculation can be done yet.
15268                          *
15269                          * Even if we could do a recalculation and modeset
15270                          * right now it would cause a double modeset if
15271                          * fbdev or userspace chooses a different initial mode.
15272                          *
15273                          * If that happens, someone indicated they wanted a
15274                          * mode change, which means it's safe to do a full
15275                          * recalculation.
15276                          */
15277                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15278
15279                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15280                         update_scanline_offset(crtc);
15281                 }
15282         }
15283 }
15284
15285 /* Scan out the current hw modeset state,
15286  * and sanitizes it to the current state
15287  */
15288 static void
15289 intel_modeset_setup_hw_state(struct drm_device *dev)
15290 {
15291         struct drm_i915_private *dev_priv = dev->dev_private;
15292         enum pipe pipe;
15293         struct intel_crtc *crtc;
15294         struct intel_encoder *encoder;
15295         int i;
15296
15297         intel_modeset_readout_hw_state(dev);
15298
15299         /* HW state is read out, now we need to sanitize this mess. */
15300         for_each_intel_encoder(dev, encoder) {
15301                 intel_sanitize_encoder(encoder);
15302         }
15303
15304         for_each_pipe(dev_priv, pipe) {
15305                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15306                 intel_sanitize_crtc(crtc);
15307                 intel_dump_pipe_config(crtc, crtc->config,
15308                                        "[setup_hw_state]");
15309         }
15310
15311         intel_modeset_update_connector_atomic_state(dev);
15312
15313         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15314                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15315
15316                 if (!pll->on || pll->active)
15317                         continue;
15318
15319                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15320
15321                 pll->disable(dev_priv, pll);
15322                 pll->on = false;
15323         }
15324
15325         if (IS_VALLEYVIEW(dev))
15326                 vlv_wm_get_hw_state(dev);
15327         else if (IS_GEN9(dev))
15328                 skl_wm_get_hw_state(dev);
15329         else if (HAS_PCH_SPLIT(dev))
15330                 ilk_wm_get_hw_state(dev);
15331
15332         for_each_intel_crtc(dev, crtc) {
15333                 unsigned long put_domains;
15334
15335                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15336                 if (WARN_ON(put_domains))
15337                         modeset_put_power_domains(dev_priv, put_domains);
15338         }
15339         intel_display_set_init_power(dev_priv, false);
15340 }
15341
15342 void intel_display_resume(struct drm_device *dev)
15343 {
15344         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15345         struct intel_connector *conn;
15346         struct intel_plane *plane;
15347         struct drm_crtc *crtc;
15348         int ret;
15349
15350         if (!state)
15351                 return;
15352
15353         state->acquire_ctx = dev->mode_config.acquire_ctx;
15354
15355         /* preserve complete old state, including dpll */
15356         intel_atomic_get_shared_dpll_state(state);
15357
15358         for_each_crtc(dev, crtc) {
15359                 struct drm_crtc_state *crtc_state =
15360                         drm_atomic_get_crtc_state(state, crtc);
15361
15362                 ret = PTR_ERR_OR_ZERO(crtc_state);
15363                 if (ret)
15364                         goto err;
15365
15366                 /* force a restore */
15367                 crtc_state->mode_changed = true;
15368         }
15369
15370         for_each_intel_plane(dev, plane) {
15371                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15372                 if (ret)
15373                         goto err;
15374         }
15375
15376         for_each_intel_connector(dev, conn) {
15377                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15378                 if (ret)
15379                         goto err;
15380         }
15381
15382         intel_modeset_setup_hw_state(dev);
15383
15384         i915_redisable_vga(dev);
15385         ret = drm_atomic_commit(state);
15386         if (!ret)
15387                 return;
15388
15389 err:
15390         DRM_ERROR("Restoring old state failed with %i\n", ret);
15391         drm_atomic_state_free(state);
15392 }
15393
15394 void intel_modeset_gem_init(struct drm_device *dev)
15395 {
15396         struct drm_crtc *c;
15397         struct drm_i915_gem_object *obj;
15398         int ret;
15399
15400         mutex_lock(&dev->struct_mutex);
15401         intel_init_gt_powersave(dev);
15402         mutex_unlock(&dev->struct_mutex);
15403
15404         intel_modeset_init_hw(dev);
15405
15406         intel_setup_overlay(dev);
15407
15408         /*
15409          * Make sure any fbs we allocated at startup are properly
15410          * pinned & fenced.  When we do the allocation it's too early
15411          * for this.
15412          */
15413         for_each_crtc(dev, c) {
15414                 obj = intel_fb_obj(c->primary->fb);
15415                 if (obj == NULL)
15416                         continue;
15417
15418                 mutex_lock(&dev->struct_mutex);
15419                 ret = intel_pin_and_fence_fb_obj(c->primary,
15420                                                  c->primary->fb,
15421                                                  c->primary->state,
15422                                                  NULL, NULL);
15423                 mutex_unlock(&dev->struct_mutex);
15424                 if (ret) {
15425                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15426                                   to_intel_crtc(c)->pipe);
15427                         drm_framebuffer_unreference(c->primary->fb);
15428                         c->primary->fb = NULL;
15429                         c->primary->crtc = c->primary->state->crtc = NULL;
15430                         update_state_fb(c->primary);
15431                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15432                 }
15433         }
15434
15435         intel_backlight_register(dev);
15436 }
15437
15438 void intel_connector_unregister(struct intel_connector *intel_connector)
15439 {
15440         struct drm_connector *connector = &intel_connector->base;
15441
15442         intel_panel_destroy_backlight(connector);
15443         drm_connector_unregister(connector);
15444 }
15445
15446 void intel_modeset_cleanup(struct drm_device *dev)
15447 {
15448         struct drm_i915_private *dev_priv = dev->dev_private;
15449         struct drm_connector *connector;
15450
15451         intel_disable_gt_powersave(dev);
15452
15453         intel_backlight_unregister(dev);
15454
15455         /*
15456          * Interrupts and polling as the first thing to avoid creating havoc.
15457          * Too much stuff here (turning of connectors, ...) would
15458          * experience fancy races otherwise.
15459          */
15460         intel_irq_uninstall(dev_priv);
15461
15462         /*
15463          * Due to the hpd irq storm handling the hotplug work can re-arm the
15464          * poll handlers. Hence disable polling after hpd handling is shut down.
15465          */
15466         drm_kms_helper_poll_fini(dev);
15467
15468         intel_unregister_dsm_handler();
15469
15470         intel_fbc_disable(dev_priv);
15471
15472         /* flush any delayed tasks or pending work */
15473         flush_scheduled_work();
15474
15475         /* destroy the backlight and sysfs files before encoders/connectors */
15476         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15477                 struct intel_connector *intel_connector;
15478
15479                 intel_connector = to_intel_connector(connector);
15480                 intel_connector->unregister(intel_connector);
15481         }
15482
15483         drm_mode_config_cleanup(dev);
15484
15485         intel_cleanup_overlay(dev);
15486
15487         mutex_lock(&dev->struct_mutex);
15488         intel_cleanup_gt_powersave(dev);
15489         mutex_unlock(&dev->struct_mutex);
15490 }
15491
15492 /*
15493  * Return which encoder is currently attached for connector.
15494  */
15495 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15496 {
15497         return &intel_attached_encoder(connector)->base;
15498 }
15499
15500 void intel_connector_attach_encoder(struct intel_connector *connector,
15501                                     struct intel_encoder *encoder)
15502 {
15503         connector->encoder = encoder;
15504         drm_mode_connector_attach_encoder(&connector->base,
15505                                           &encoder->base);
15506 }
15507
15508 /*
15509  * set vga decode state - true == enable VGA decode
15510  */
15511 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15512 {
15513         struct drm_i915_private *dev_priv = dev->dev_private;
15514         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15515         u16 gmch_ctrl;
15516
15517         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15518                 DRM_ERROR("failed to read control word\n");
15519                 return -EIO;
15520         }
15521
15522         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15523                 return 0;
15524
15525         if (state)
15526                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15527         else
15528                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15529
15530         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15531                 DRM_ERROR("failed to write control word\n");
15532                 return -EIO;
15533         }
15534
15535         return 0;
15536 }
15537
15538 struct intel_display_error_state {
15539
15540         u32 power_well_driver;
15541
15542         int num_transcoders;
15543
15544         struct intel_cursor_error_state {
15545                 u32 control;
15546                 u32 position;
15547                 u32 base;
15548                 u32 size;
15549         } cursor[I915_MAX_PIPES];
15550
15551         struct intel_pipe_error_state {
15552                 bool power_domain_on;
15553                 u32 source;
15554                 u32 stat;
15555         } pipe[I915_MAX_PIPES];
15556
15557         struct intel_plane_error_state {
15558                 u32 control;
15559                 u32 stride;
15560                 u32 size;
15561                 u32 pos;
15562                 u32 addr;
15563                 u32 surface;
15564                 u32 tile_offset;
15565         } plane[I915_MAX_PIPES];
15566
15567         struct intel_transcoder_error_state {
15568                 bool power_domain_on;
15569                 enum transcoder cpu_transcoder;
15570
15571                 u32 conf;
15572
15573                 u32 htotal;
15574                 u32 hblank;
15575                 u32 hsync;
15576                 u32 vtotal;
15577                 u32 vblank;
15578                 u32 vsync;
15579         } transcoder[4];
15580 };
15581
15582 struct intel_display_error_state *
15583 intel_display_capture_error_state(struct drm_device *dev)
15584 {
15585         struct drm_i915_private *dev_priv = dev->dev_private;
15586         struct intel_display_error_state *error;
15587         int transcoders[] = {
15588                 TRANSCODER_A,
15589                 TRANSCODER_B,
15590                 TRANSCODER_C,
15591                 TRANSCODER_EDP,
15592         };
15593         int i;
15594
15595         if (INTEL_INFO(dev)->num_pipes == 0)
15596                 return NULL;
15597
15598         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15599         if (error == NULL)
15600                 return NULL;
15601
15602         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15603                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15604
15605         for_each_pipe(dev_priv, i) {
15606                 error->pipe[i].power_domain_on =
15607                         __intel_display_power_is_enabled(dev_priv,
15608                                                          POWER_DOMAIN_PIPE(i));
15609                 if (!error->pipe[i].power_domain_on)
15610                         continue;
15611
15612                 error->cursor[i].control = I915_READ(CURCNTR(i));
15613                 error->cursor[i].position = I915_READ(CURPOS(i));
15614                 error->cursor[i].base = I915_READ(CURBASE(i));
15615
15616                 error->plane[i].control = I915_READ(DSPCNTR(i));
15617                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15618                 if (INTEL_INFO(dev)->gen <= 3) {
15619                         error->plane[i].size = I915_READ(DSPSIZE(i));
15620                         error->plane[i].pos = I915_READ(DSPPOS(i));
15621                 }
15622                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15623                         error->plane[i].addr = I915_READ(DSPADDR(i));
15624                 if (INTEL_INFO(dev)->gen >= 4) {
15625                         error->plane[i].surface = I915_READ(DSPSURF(i));
15626                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15627                 }
15628
15629                 error->pipe[i].source = I915_READ(PIPESRC(i));
15630
15631                 if (HAS_GMCH_DISPLAY(dev))
15632                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15633         }
15634
15635         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15636         if (HAS_DDI(dev_priv->dev))
15637                 error->num_transcoders++; /* Account for eDP. */
15638
15639         for (i = 0; i < error->num_transcoders; i++) {
15640                 enum transcoder cpu_transcoder = transcoders[i];
15641
15642                 error->transcoder[i].power_domain_on =
15643                         __intel_display_power_is_enabled(dev_priv,
15644                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15645                 if (!error->transcoder[i].power_domain_on)
15646                         continue;
15647
15648                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15649
15650                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15651                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15652                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15653                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15654                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15655                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15656                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15657         }
15658
15659         return error;
15660 }
15661
15662 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15663
15664 void
15665 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15666                                 struct drm_device *dev,
15667                                 struct intel_display_error_state *error)
15668 {
15669         struct drm_i915_private *dev_priv = dev->dev_private;
15670         int i;
15671
15672         if (!error)
15673                 return;
15674
15675         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15676         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15677                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15678                            error->power_well_driver);
15679         for_each_pipe(dev_priv, i) {
15680                 err_printf(m, "Pipe [%d]:\n", i);
15681                 err_printf(m, "  Power: %s\n",
15682                            error->pipe[i].power_domain_on ? "on" : "off");
15683                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15684                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15685
15686                 err_printf(m, "Plane [%d]:\n", i);
15687                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15688                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15689                 if (INTEL_INFO(dev)->gen <= 3) {
15690                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15691                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15692                 }
15693                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15694                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15695                 if (INTEL_INFO(dev)->gen >= 4) {
15696                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15697                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15698                 }
15699
15700                 err_printf(m, "Cursor [%d]:\n", i);
15701                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15702                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15703                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15704         }
15705
15706         for (i = 0; i < error->num_transcoders; i++) {
15707                 err_printf(m, "CPU transcoder: %c\n",
15708                            transcoder_name(error->transcoder[i].cpu_transcoder));
15709                 err_printf(m, "  Power: %s\n",
15710                            error->transcoder[i].power_domain_on ? "on" : "off");
15711                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15712                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15713                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15714                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15715                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15716                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15717                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15718         }
15719 }
15720
15721 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15722 {
15723         struct intel_crtc *crtc;
15724
15725         for_each_intel_crtc(dev, crtc) {
15726                 struct intel_unpin_work *work;
15727
15728                 spin_lock_irq(&dev->event_lock);
15729
15730                 work = crtc->unpin_work;
15731
15732                 if (work && work->event &&
15733                     work->event->base.file_priv == file) {
15734                         kfree(work->event);
15735                         work->event = NULL;
15736                 }
15737
15738                 spin_unlock_irq(&dev->event_lock);
15739         }
15740 }