drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34 };
  35
  36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  37  * them for both DP and FDI transports, allowing those ports to
  38  * automatically adapt to HDMI connections as well
  39  */
  40 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  41         { 0x00FFFFFF, 0x0006000E },
  42         { 0x00D75FFF, 0x0005000A },
  43         { 0x00C30FFF, 0x00040006 },
  44         { 0x80AAAFFF, 0x000B0000 },
  45         { 0x00FFFFFF, 0x0005000A },
  46         { 0x00D75FFF, 0x000C0004 },
  47         { 0x80C30FFF, 0x000B0000 },
  48         { 0x00FFFFFF, 0x00040006 },
  49         { 0x80D75FFF, 0x000B0000 },
  50 };
  51
  52 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  53         { 0x00FFFFFF, 0x0007000E },
  54         { 0x00D75FFF, 0x000F000A },
  55         { 0x00C30FFF, 0x00060006 },
  56         { 0x00AAAFFF, 0x001E0000 },
  57         { 0x00FFFFFF, 0x000F000A },
  58         { 0x00D75FFF, 0x00160004 },
  59         { 0x00C30FFF, 0x001E0000 },
  60         { 0x00FFFFFF, 0x00060006 },
  61         { 0x00D75FFF, 0x001E0000 },
  62 };
  63
  64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  65                                         /* Idx  NT mV d T mV d  db      */
  66         { 0x00FFFFFF, 0x0006000E },     /* 0:   400     400     0       */
  67         { 0x00E79FFF, 0x000E000C },     /* 1:   400     500     2       */
  68         { 0x00D75FFF, 0x0005000A },     /* 2:   400     600     3.5     */
  69         { 0x00FFFFFF, 0x0005000A },     /* 3:   600     600     0       */
  70         { 0x00E79FFF, 0x001D0007 },     /* 4:   600     750     2       */
  71         { 0x00D75FFF, 0x000C0004 },     /* 5:   600     900     3.5     */
  72         { 0x00FFFFFF, 0x00040006 },     /* 6:   800     800     0       */
  73         { 0x80E79FFF, 0x00030002 },     /* 7:   800     1000    2       */
  74         { 0x00FFFFFF, 0x00140005 },     /* 8:   850     850     0       */
  75         { 0x00FFFFFF, 0x000C0004 },     /* 9:   900     900     0       */
  76         { 0x00FFFFFF, 0x001C0003 },     /* 10:  950     950     0       */
  77         { 0x80FFFFFF, 0x00030002 },     /* 11:  1000    1000    0       */
  78 };
  79
  80 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  81         { 0x00FFFFFF, 0x00000012 },
  82         { 0x00EBAFFF, 0x00020011 },
  83         { 0x00C71FFF, 0x0006000F },
  84         { 0x00AAAFFF, 0x000E000A },
  85         { 0x00FFFFFF, 0x00020011 },
  86         { 0x00DB6FFF, 0x0005000F },
  87         { 0x00BEEFFF, 0x000A000C },
  88         { 0x00FFFFFF, 0x0005000F },
  89         { 0x00DB6FFF, 0x000A000C },
  90 };
  91
  92 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
  93         { 0x00FFFFFF, 0x0007000E },
  94         { 0x00D75FFF, 0x000E000A },
  95         { 0x00BEFFFF, 0x00140006 },
  96         { 0x80B2CFFF, 0x001B0002 },
  97         { 0x00FFFFFF, 0x000E000A },
  98         { 0x00D75FFF, 0x00180004 },
  99         { 0x80CB2FFF, 0x001B0002 },
 100         { 0x00F7DFFF, 0x00180004 },
 101         { 0x80D75FFF, 0x001B0002 },
 102 };
 103
 104 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 105         { 0x00FFFFFF, 0x0001000E },
 106         { 0x00D75FFF, 0x0004000A },
 107         { 0x00C30FFF, 0x00070006 },
 108         { 0x00AAAFFF, 0x000C0000 },
 109         { 0x00FFFFFF, 0x0004000A },
 110         { 0x00D75FFF, 0x00090004 },
 111         { 0x00C30FFF, 0x000C0000 },
 112         { 0x00FFFFFF, 0x00070006 },
 113         { 0x00D75FFF, 0x000C0000 },
 114 };
 115
 116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 117                                         /* Idx  NT mV d T mV df db      */
 118         { 0x00FFFFFF, 0x0007000E },     /* 0:   400     400     0       */
 119         { 0x00D75FFF, 0x000E000A },     /* 1:   400     600     3.5     */
 120         { 0x00BEFFFF, 0x00140006 },     /* 2:   400     800     6       */
 121         { 0x00FFFFFF, 0x0009000D },     /* 3:   450     450     0       */
 122         { 0x00FFFFFF, 0x000E000A },     /* 4:   600     600     0       */
 123         { 0x00D7FFFF, 0x00140006 },     /* 5:   600     800     2.5     */
 124         { 0x80CB2FFF, 0x001B0002 },     /* 6:   600     1000    4.5     */
 125         { 0x00FFFFFF, 0x00140006 },     /* 7:   800     800     0       */
 126         { 0x80E79FFF, 0x001B0002 },     /* 8:   800     1000    2       */
 127         { 0x80FFFFFF, 0x001B0002 },     /* 9:   1000    1000    0       */
 128 };
 129
 130 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 131 {
 132         struct drm_encoder *encoder = &intel_encoder->base;
 133         int type = intel_encoder->type;
 134
 135         if (type == INTEL_OUTPUT_DP_MST) {
 136                 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
 137                 return intel_dig_port->port;
 138         } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 139             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 140                 struct intel_digital_port *intel_dig_port =
 141                         enc_to_dig_port(encoder);
 142                 return intel_dig_port->port;
 143
 144         } else if (type == INTEL_OUTPUT_ANALOG) {
 145                 return PORT_E;
 146
 147         } else {
 148                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
 149                 BUG();
 150         }
 151 }
 152
 153 /*
 154  * Starting with Haswell, DDI port buffers must be programmed with correct
 155  * values in advance. The buffer values are different for FDI and DP modes,
 156  * but the HDMI/DVI fields are shared among those. So we program the DDI
 157  * in either FDI or DP modes only, as HDMI connections will work with both
 158  * of those
 159  */
 160 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 161 {
 162         struct drm_i915_private *dev_priv = dev->dev_private;
 163         u32 reg;
 164         int i, n_hdmi_entries, hdmi_800mV_0dB;
 165         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 166         const struct ddi_buf_trans *ddi_translations_fdi;
 167         const struct ddi_buf_trans *ddi_translations_dp;
 168         const struct ddi_buf_trans *ddi_translations_edp;
 169         const struct ddi_buf_trans *ddi_translations_hdmi;
 170         const struct ddi_buf_trans *ddi_translations;
 171
 172         if (IS_BROADWELL(dev)) {
 173                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 174                 ddi_translations_dp = bdw_ddi_translations_dp;
 175                 ddi_translations_edp = bdw_ddi_translations_edp;
 176                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 177                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 178                 hdmi_800mV_0dB = 7;
 179         } else if (IS_HASWELL(dev)) {
 180                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 181                 ddi_translations_dp = hsw_ddi_translations_dp;
 182                 ddi_translations_edp = hsw_ddi_translations_dp;
 183                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 184                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 185                 hdmi_800mV_0dB = 6;
 186         } else {
 187                 WARN(1, "ddi translation table missing\n");
 188                 ddi_translations_edp = bdw_ddi_translations_dp;
 189                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 190                 ddi_translations_dp = bdw_ddi_translations_dp;
 191                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 192                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 193                 hdmi_800mV_0dB = 7;
 194         }
 195
 196         switch (port) {
 197         case PORT_A:
 198                 ddi_translations = ddi_translations_edp;
 199                 break;
 200         case PORT_B:
 201         case PORT_C:
 202                 ddi_translations = ddi_translations_dp;
 203                 break;
 204         case PORT_D:
 205                 if (intel_dp_is_edp(dev, PORT_D))
 206                         ddi_translations = ddi_translations_edp;
 207                 else
 208                         ddi_translations = ddi_translations_dp;
 209                 break;
 210         case PORT_E:
 211                 ddi_translations = ddi_translations_fdi;
 212                 break;
 213         default:
 214                 BUG();
 215         }
 216
 217         for (i = 0, reg = DDI_BUF_TRANS(port);
 218              i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 219                 I915_WRITE(reg, ddi_translations[i].trans1);
 220                 reg += 4;
 221                 I915_WRITE(reg, ddi_translations[i].trans2);
 222                 reg += 4;
 223         }
 224
 225         /* Choose a good default if VBT is badly populated */
 226         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 227             hdmi_level >= n_hdmi_entries)
 228                 hdmi_level = hdmi_800mV_0dB;
 229
 230         /* Entry 9 is for HDMI: */
 231         I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
 232         reg += 4;
 233         I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
 234         reg += 4;
 235 }
 236
 237 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 238  * mode and port E for FDI.
 239  */
 240 void intel_prepare_ddi(struct drm_device *dev)
 241 {
 242         int port;
 243
 244         if (!HAS_DDI(dev))
 245                 return;
 246
 247         for (port = PORT_A; port <= PORT_E; port++)
 248                 intel_prepare_ddi_buffers(dev, port);
 249 }
 250
 251 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 252                                     enum port port)
 253 {
 254         uint32_t reg = DDI_BUF_CTL(port);
 255         int i;
 256
 257         for (i = 0; i < 8; i++) {
 258                 udelay(1);
 259                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 260                         return;
 261         }
 262         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 263 }
 264
 265 /* Starting with Haswell, different DDI ports can work in FDI mode for
 266  * connection to the PCH-located connectors. For this, it is necessary to train
 267  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 268  *
 269  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 270  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 271  * DDI A (which is used for eDP)
 272  */
 273
 274 void hsw_fdi_link_train(struct drm_crtc *crtc)
 275 {
 276         struct drm_device *dev = crtc->dev;
 277         struct drm_i915_private *dev_priv = dev->dev_private;
 278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 279         u32 temp, i, rx_ctl_val;
 280
 281         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 282          * mode set "sequence for CRT port" document:
 283          * - TP1 to TP2 time with the default value
 284          * - FDI delay to 90h
 285          *
 286          * WaFDIAutoLinkSetTimingOverrride:hsw
 287          */
 288         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 289                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 290                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 291
 292         /* Enable the PCH Receiver FDI PLL */
 293         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 294                      FDI_RX_PLL_ENABLE |
 295                      FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
 296         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 297         POSTING_READ(_FDI_RXA_CTL);
 298         udelay(220);
 299
 300         /* Switch from Rawclk to PCDclk */
 301         rx_ctl_val |= FDI_PCDCLK;
 302         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 303
 304         /* Configure Port Clock Select */
 305         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
 306         WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
 307
 308         /* Start the training iterating through available voltages and emphasis,
 309          * testing each value twice. */
 310         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 311                 /* Configure DP_TP_CTL with auto-training */
 312                 I915_WRITE(DP_TP_CTL(PORT_E),
 313                                         DP_TP_CTL_FDI_AUTOTRAIN |
 314                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 315                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 316                                         DP_TP_CTL_ENABLE);
 317
 318                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 319                  * DDI E does not support port reversal, the functionality is
 320                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 321                  * port reversal bit */
 322                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 323                            DDI_BUF_CTL_ENABLE |
 324                            ((intel_crtc->config.fdi_lanes - 1) << 1) |
 325                            DDI_BUF_TRANS_SELECT(i / 2));
 326                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 327
 328                 udelay(600);
 329
 330                 /* Program PCH FDI Receiver TU */
 331                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 332
 333                 /* Enable PCH FDI Receiver with auto-training */
 334                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 335                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 336                 POSTING_READ(_FDI_RXA_CTL);
 337
 338                 /* Wait for FDI receiver lane calibration */
 339                 udelay(30);
 340
 341                 /* Unset FDI_RX_MISC pwrdn lanes */
 342                 temp = I915_READ(_FDI_RXA_MISC);
 343                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 344                 I915_WRITE(_FDI_RXA_MISC, temp);
 345                 POSTING_READ(_FDI_RXA_MISC);
 346
 347                 /* Wait for FDI auto training time */
 348                 udelay(5);
 349
 350                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 351                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 352                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 353
 354                         /* Enable normal pixel sending for FDI */
 355                         I915_WRITE(DP_TP_CTL(PORT_E),
 356                                    DP_TP_CTL_FDI_AUTOTRAIN |
 357                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 358                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 359                                    DP_TP_CTL_ENABLE);
 360
 361                         return;
 362                 }
 363
 364                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 365                 temp &= ~DDI_BUF_CTL_ENABLE;
 366                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 367                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 368
 369                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 370                 temp = I915_READ(DP_TP_CTL(PORT_E));
 371                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 372                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 373                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 374                 POSTING_READ(DP_TP_CTL(PORT_E));
 375
 376                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 377
 378                 rx_ctl_val &= ~FDI_RX_ENABLE;
 379                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 380                 POSTING_READ(_FDI_RXA_CTL);
 381
 382                 /* Reset FDI_RX_MISC pwrdn lanes */
 383                 temp = I915_READ(_FDI_RXA_MISC);
 384                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 385                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 386                 I915_WRITE(_FDI_RXA_MISC, temp);
 387                 POSTING_READ(_FDI_RXA_MISC);
 388         }
 389
 390         DRM_ERROR("FDI link training failed!\n");
 391 }
 392
 393 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 394 {
 395         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 396         struct intel_digital_port *intel_dig_port =
 397                 enc_to_dig_port(&encoder->base);
 398
 399         intel_dp->DP = intel_dig_port->saved_port_bits |
 400                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 401         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 402
 403 }
 404
 405 static struct intel_encoder *
 406 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 407 {
 408         struct drm_device *dev = crtc->dev;
 409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 410         struct intel_encoder *intel_encoder, *ret = NULL;
 411         int num_encoders = 0;
 412
 413         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 414                 ret = intel_encoder;
 415                 num_encoders++;
 416         }
 417
 418         if (num_encoders != 1)
 419                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 420                      pipe_name(intel_crtc->pipe));
 421
 422         BUG_ON(ret == NULL);
 423         return ret;
 424 }
 425
 426 #define LC_FREQ 2700
 427 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
 428
 429 #define P_MIN 2
 430 #define P_MAX 64
 431 #define P_INC 2
 432
 433 /* Constraints for PLL good behavior */
 434 #define REF_MIN 48
 435 #define REF_MAX 400
 436 #define VCO_MIN 2400
 437 #define VCO_MAX 4800
 438
 439 #define abs_diff(a, b) ({                       \
 440         typeof(a) __a = (a);                    \
 441         typeof(b) __b = (b);                    \
 442         (void) (&__a == &__b);                  \
 443         __a > __b ? (__a - __b) : (__b - __a); })
 444
 445 struct wrpll_rnp {
 446         unsigned p, n2, r2;
 447 };
 448
 449 static unsigned wrpll_get_budget_for_freq(int clock)
 450 {
 451         unsigned budget;
 452
 453         switch (clock) {
 454         case 25175000:
 455         case 25200000:
 456         case 27000000:
 457         case 27027000:
 458         case 37762500:
 459         case 37800000:
 460         case 40500000:
 461         case 40541000:
 462         case 54000000:
 463         case 54054000:
 464         case 59341000:
 465         case 59400000:
 466         case 72000000:
 467         case 74176000:
 468         case 74250000:
 469         case 81000000:
 470         case 81081000:
 471         case 89012000:
 472         case 89100000:
 473         case 108000000:
 474         case 108108000:
 475         case 111264000:
 476         case 111375000:
 477         case 148352000:
 478         case 148500000:
 479         case 162000000:
 480         case 162162000:
 481         case 222525000:
 482         case 222750000:
 483         case 296703000:
 484         case 297000000:
 485                 budget = 0;
 486                 break;
 487         case 233500000:
 488         case 245250000:
 489         case 247750000:
 490         case 253250000:
 491         case 298000000:
 492                 budget = 1500;
 493                 break;
 494         case 169128000:
 495         case 169500000:
 496         case 179500000:
 497         case 202000000:
 498                 budget = 2000;
 499                 break;
 500         case 256250000:
 501         case 262500000:
 502         case 270000000:
 503         case 272500000:
 504         case 273750000:
 505         case 280750000:
 506         case 281250000:
 507         case 286000000:
 508         case 291750000:
 509                 budget = 4000;
 510                 break;
 511         case 267250000:
 512         case 268500000:
 513                 budget = 5000;
 514                 break;
 515         default:
 516                 budget = 1000;
 517                 break;
 518         }
 519
 520         return budget;
 521 }
 522
 523 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 524                              unsigned r2, unsigned n2, unsigned p,
 525                              struct wrpll_rnp *best)
 526 {
 527         uint64_t a, b, c, d, diff, diff_best;
 528
 529         /* No best (r,n,p) yet */
 530         if (best->p == 0) {
 531                 best->p = p;
 532                 best->n2 = n2;
 533                 best->r2 = r2;
 534                 return;
 535         }
 536
 537         /*
 538          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 539          * freq2k.
 540          *
 541          * delta = 1e6 *
 542          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 543          *         freq2k;
 544          *
 545          * and we would like delta <= budget.
 546          *
 547          * If the discrepancy is above the PPM-based budget, always prefer to
 548          * improve upon the previous solution.  However, if you're within the
 549          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 550          */
 551         a = freq2k * budget * p * r2;
 552         b = freq2k * budget * best->p * best->r2;
 553         diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
 554         diff_best = abs_diff(freq2k * best->p * best->r2,
 555                              LC_FREQ_2K * best->n2);
 556         c = 1000000 * diff;
 557         d = 1000000 * diff_best;
 558
 559         if (a < c && b < d) {
 560                 /* If both are above the budget, pick the closer */
 561                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 562                         best->p = p;
 563                         best->n2 = n2;
 564                         best->r2 = r2;
 565                 }
 566         } else if (a >= c && b < d) {
 567                 /* If A is below the threshold but B is above it?  Update. */
 568                 best->p = p;
 569                 best->n2 = n2;
 570                 best->r2 = r2;
 571         } else if (a >= c && b >= d) {
 572                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 573                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 574                         best->p = p;
 575                         best->n2 = n2;
 576                         best->r2 = r2;
 577                 }
 578         }
 579         /* Otherwise a < c && b >= d, do nothing */
 580 }
 581
 582 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 583                                      int reg)
 584 {
 585         int refclk = LC_FREQ;
 586         int n, p, r;
 587         u32 wrpll;
 588
 589         wrpll = I915_READ(reg);
 590         switch (wrpll & WRPLL_PLL_REF_MASK) {
 591         case WRPLL_PLL_SSC:
 592         case WRPLL_PLL_NON_SSC:
 593                 /*
 594                  * We could calculate spread here, but our checking
 595                  * code only cares about 5% accuracy, and spread is a max of
 596                  * 0.5% downspread.
 597                  */
 598                 refclk = 135;
 599                 break;
 600         case WRPLL_PLL_LCPLL:
 601                 refclk = LC_FREQ;
 602                 break;
 603         default:
 604                 WARN(1, "bad wrpll refclk\n");
 605                 return 0;
 606         }
 607
 608         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 609         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 610         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 611
 612         /* Convert to KHz, p & r have a fixed point portion */
 613         return (refclk * n * 100) / (p * r);
 614 }
 615
 616 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 617                               struct intel_crtc_config *pipe_config)
 618 {
 619         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 620         int link_clock = 0;
 621         u32 val, pll;
 622
 623         val = pipe_config->ddi_pll_sel;
 624         switch (val & PORT_CLK_SEL_MASK) {
 625         case PORT_CLK_SEL_LCPLL_810:
 626                 link_clock = 81000;
 627                 break;
 628         case PORT_CLK_SEL_LCPLL_1350:
 629                 link_clock = 135000;
 630                 break;
 631         case PORT_CLK_SEL_LCPLL_2700:
 632                 link_clock = 270000;
 633                 break;
 634         case PORT_CLK_SEL_WRPLL1:
 635                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
 636                 break;
 637         case PORT_CLK_SEL_WRPLL2:
 638                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
 639                 break;
 640         case PORT_CLK_SEL_SPLL:
 641                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 642                 if (pll == SPLL_PLL_FREQ_810MHz)
 643                         link_clock = 81000;
 644                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 645                         link_clock = 135000;
 646                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 647                         link_clock = 270000;
 648                 else {
 649                         WARN(1, "bad spll freq\n");
 650                         return;
 651                 }
 652                 break;
 653         default:
 654                 WARN(1, "bad port clock sel\n");
 655                 return;
 656         }
 657
 658         pipe_config->port_clock = link_clock * 2;
 659
 660         if (pipe_config->has_pch_encoder)
 661                 pipe_config->adjusted_mode.crtc_clock =
 662                         intel_dotclock_calculate(pipe_config->port_clock,
 663                                                  &pipe_config->fdi_m_n);
 664         else if (pipe_config->has_dp_encoder)
 665                 pipe_config->adjusted_mode.crtc_clock =
 666                         intel_dotclock_calculate(pipe_config->port_clock,
 667                                                  &pipe_config->dp_m_n);
 668         else
 669                 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
 670 }
 671
 672 void intel_ddi_clock_get(struct intel_encoder *encoder,
 673                          struct intel_crtc_config *pipe_config)
 674 {
 675         hsw_ddi_clock_get(encoder, pipe_config);
 676 }
 677
 678 static void
 679 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 680                         unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 681 {
 682         uint64_t freq2k;
 683         unsigned p, n2, r2;
 684         struct wrpll_rnp best = { 0, 0, 0 };
 685         unsigned budget;
 686
 687         freq2k = clock / 100;
 688
 689         budget = wrpll_get_budget_for_freq(clock);
 690
 691         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 692          * and directly pass the LC PLL to it. */
 693         if (freq2k == 5400000) {
 694                 *n2_out = 2;
 695                 *p_out = 1;
 696                 *r2_out = 2;
 697                 return;
 698         }
 699
 700         /*
 701          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 702          * the WR PLL.
 703          *
 704          * We want R so that REF_MIN <= Ref <= REF_MAX.
 705          * Injecting R2 = 2 * R gives:
 706          *   REF_MAX * r2 > LC_FREQ * 2 and
 707          *   REF_MIN * r2 < LC_FREQ * 2
 708          *
 709          * Which means the desired boundaries for r2 are:
 710          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 711          *
 712          */
 713         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 714              r2 <= LC_FREQ * 2 / REF_MIN;
 715              r2++) {
 716
 717                 /*
 718                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 719                  *
 720                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 721                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 722                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 723                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 724                  *
 725                  * Which means the desired boundaries for n2 are:
 726                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 727                  */
 728                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 729                      n2 <= VCO_MAX * r2 / LC_FREQ;
 730                      n2++) {
 731
 732                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 733                                 wrpll_update_rnp(freq2k, budget,
 734                                                  r2, n2, p, &best);
 735                 }
 736         }
 737
 738         *n2_out = best.n2;
 739         *p_out = best.p;
 740         *r2_out = best.r2;
 741 }
 742
 743 static bool
 744 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 745                    struct intel_encoder *intel_encoder,
 746                    int clock)
 747 {
 748         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 749                 struct intel_shared_dpll *pll;
 750                 uint32_t val;
 751                 unsigned p, n2, r2;
 752
 753                 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 754
 755                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 756                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 757                       WRPLL_DIVIDER_POST(p);
 758
 759                 intel_crtc->config.dpll_hw_state.wrpll = val;
 760
 761                 pll = intel_get_shared_dpll(intel_crtc);
 762                 if (pll == NULL) {
 763                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 764                                          pipe_name(intel_crtc->pipe));
 765                         return false;
 766                 }
 767
 768                 intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
 769         }
 770
 771         return true;
 772 }
 773
 774
 775 /*
 776  * Tries to find a *shared* PLL for the CRTC and store it in
 777  * intel_crtc->ddi_pll_sel.
 778  *
 779  * For private DPLLs, compute_config() should do the selection for us. This
 780  * function should be folded into compute_config() eventually.
 781  */
 782 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 783 {
 784         struct drm_crtc *crtc = &intel_crtc->base;
 785         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 786         int clock = intel_crtc->config.port_clock;
 787
 788         intel_put_shared_dpll(intel_crtc);
 789
 790         return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
 791 }
 792
 793 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 794 {
 795         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 796         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 797         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 798         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 799         int type = intel_encoder->type;
 800         uint32_t temp;
 801
 802         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
 803                 temp = TRANS_MSA_SYNC_CLK;
 804                 switch (intel_crtc->config.pipe_bpp) {
 805                 case 18:
 806                         temp |= TRANS_MSA_6_BPC;
 807                         break;
 808                 case 24:
 809                         temp |= TRANS_MSA_8_BPC;
 810                         break;
 811                 case 30:
 812                         temp |= TRANS_MSA_10_BPC;
 813                         break;
 814                 case 36:
 815                         temp |= TRANS_MSA_12_BPC;
 816                         break;
 817                 default:
 818                         BUG();
 819                 }
 820                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 821         }
 822 }
 823
 824 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
 825 {
 826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 827         struct drm_device *dev = crtc->dev;
 828         struct drm_i915_private *dev_priv = dev->dev_private;
 829         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 830         uint32_t temp;
 831         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 832         if (state == true)
 833                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
 834         else
 835                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
 836         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 837 }
 838
 839 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 840 {
 841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 842         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 843         struct drm_encoder *encoder = &intel_encoder->base;
 844         struct drm_device *dev = crtc->dev;
 845         struct drm_i915_private *dev_priv = dev->dev_private;
 846         enum pipe pipe = intel_crtc->pipe;
 847         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 848         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 849         int type = intel_encoder->type;
 850         uint32_t temp;
 851
 852         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 853         temp = TRANS_DDI_FUNC_ENABLE;
 854         temp |= TRANS_DDI_SELECT_PORT(port);
 855
 856         switch (intel_crtc->config.pipe_bpp) {
 857         case 18:
 858                 temp |= TRANS_DDI_BPC_6;
 859                 break;
 860         case 24:
 861                 temp |= TRANS_DDI_BPC_8;
 862                 break;
 863         case 30:
 864                 temp |= TRANS_DDI_BPC_10;
 865                 break;
 866         case 36:
 867                 temp |= TRANS_DDI_BPC_12;
 868                 break;
 869         default:
 870                 BUG();
 871         }
 872
 873         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 874                 temp |= TRANS_DDI_PVSYNC;
 875         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 876                 temp |= TRANS_DDI_PHSYNC;
 877
 878         if (cpu_transcoder == TRANSCODER_EDP) {
 879                 switch (pipe) {
 880                 case PIPE_A:
 881                         /* On Haswell, can only use the always-on power well for
 882                          * eDP when not using the panel fitter, and when not
 883                          * using motion blur mitigation (which we don't
 884                          * support). */
 885                         if (IS_HASWELL(dev) &&
 886                             (intel_crtc->config.pch_pfit.enabled ||
 887                              intel_crtc->config.pch_pfit.force_thru))
 888                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 889                         else
 890                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 891                         break;
 892                 case PIPE_B:
 893                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 894                         break;
 895                 case PIPE_C:
 896                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 897                         break;
 898                 default:
 899                         BUG();
 900                         break;
 901                 }
 902         }
 903
 904         if (type == INTEL_OUTPUT_HDMI) {
 905                 if (intel_crtc->config.has_hdmi_sink)
 906                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 907                 else
 908                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 909
 910         } else if (type == INTEL_OUTPUT_ANALOG) {
 911                 temp |= TRANS_DDI_MODE_SELECT_FDI;
 912                 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
 913
 914         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
 915                    type == INTEL_OUTPUT_EDP) {
 916                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 917
 918                 if (intel_dp->is_mst) {
 919                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 920                 } else
 921                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 922
 923                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 924         } else if (type == INTEL_OUTPUT_DP_MST) {
 925                 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
 926
 927                 if (intel_dp->is_mst) {
 928                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 929                 } else
 930                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 931
 932                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 933         } else {
 934                 WARN(1, "Invalid encoder type %d for pipe %c\n",
 935                      intel_encoder->type, pipe_name(pipe));
 936         }
 937
 938         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 939 }
 940
 941 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 942                                        enum transcoder cpu_transcoder)
 943 {
 944         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 945         uint32_t val = I915_READ(reg);
 946
 947         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
 948         val |= TRANS_DDI_PORT_NONE;
 949         I915_WRITE(reg, val);
 950 }
 951
 952 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 953 {
 954         struct drm_device *dev = intel_connector->base.dev;
 955         struct drm_i915_private *dev_priv = dev->dev_private;
 956         struct intel_encoder *intel_encoder = intel_connector->encoder;
 957         int type = intel_connector->base.connector_type;
 958         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 959         enum pipe pipe = 0;
 960         enum transcoder cpu_transcoder;
 961         enum intel_display_power_domain power_domain;
 962         uint32_t tmp;
 963
 964         power_domain = intel_display_port_power_domain(intel_encoder);
 965         if (!intel_display_power_enabled(dev_priv, power_domain))
 966                 return false;
 967
 968         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
 969                 return false;
 970
 971         if (port == PORT_A)
 972                 cpu_transcoder = TRANSCODER_EDP;
 973         else
 974                 cpu_transcoder = (enum transcoder) pipe;
 975
 976         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 977
 978         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 979         case TRANS_DDI_MODE_SELECT_HDMI:
 980         case TRANS_DDI_MODE_SELECT_DVI:
 981                 return (type == DRM_MODE_CONNECTOR_HDMIA);
 982
 983         case TRANS_DDI_MODE_SELECT_DP_SST:
 984                 if (type == DRM_MODE_CONNECTOR_eDP)
 985                         return true;
 986                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
 987         case TRANS_DDI_MODE_SELECT_DP_MST:
 988                 /* if the transcoder is in MST state then
 989                  * connector isn't connected */
 990                 return false;
 991
 992         case TRANS_DDI_MODE_SELECT_FDI:
 993                 return (type == DRM_MODE_CONNECTOR_VGA);
 994
 995         default:
 996                 return false;
 997         }
 998 }
 999
1000 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1001                             enum pipe *pipe)
1002 {
1003         struct drm_device *dev = encoder->base.dev;
1004         struct drm_i915_private *dev_priv = dev->dev_private;
1005         enum port port = intel_ddi_get_encoder_port(encoder);
1006         enum intel_display_power_domain power_domain;
1007         u32 tmp;
1008         int i;
1009
1010         power_domain = intel_display_port_power_domain(encoder);
1011         if (!intel_display_power_enabled(dev_priv, power_domain))
1012                 return false;
1013
1014         tmp = I915_READ(DDI_BUF_CTL(port));
1015
1016         if (!(tmp & DDI_BUF_CTL_ENABLE))
1017                 return false;
1018
1019         if (port == PORT_A) {
1020                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1021
1022                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1023                 case TRANS_DDI_EDP_INPUT_A_ON:
1024                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1025                         *pipe = PIPE_A;
1026                         break;
1027                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1028                         *pipe = PIPE_B;
1029                         break;
1030                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1031                         *pipe = PIPE_C;
1032                         break;
1033                 }
1034
1035                 return true;
1036         } else {
1037                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1038                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1039
1040                         if ((tmp & TRANS_DDI_PORT_MASK)
1041                             == TRANS_DDI_SELECT_PORT(port)) {
1042                                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1043                                         return false;
1044
1045                                 *pipe = i;
1046                                 return true;
1047                         }
1048                 }
1049         }
1050
1051         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1052
1053         return false;
1054 }
1055
1056 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1057 {
1058         struct drm_crtc *crtc = &intel_crtc->base;
1059         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1060         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1061         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1062         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1063
1064         if (cpu_transcoder != TRANSCODER_EDP)
1065                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1066                            TRANS_CLK_SEL_PORT(port));
1067 }
1068
1069 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1070 {
1071         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1072         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1073
1074         if (cpu_transcoder != TRANSCODER_EDP)
1075                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1076                            TRANS_CLK_SEL_DISABLED);
1077 }
1078
1079 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1080 {
1081         struct drm_encoder *encoder = &intel_encoder->base;
1082         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1083         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1084         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1085         int type = intel_encoder->type;
1086
1087         if (crtc->config.has_audio) {
1088                 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
1089                                  pipe_name(crtc->pipe));
1090
1091                 /* write eld */
1092                 DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
1093                 intel_write_eld(encoder, &crtc->config.adjusted_mode);
1094         }
1095
1096         if (type == INTEL_OUTPUT_EDP) {
1097                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1098                 intel_edp_panel_on(intel_dp);
1099         }
1100
1101         WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1102         I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1103
1104         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1105                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1106
1107                 intel_ddi_init_dp_buf_reg(intel_encoder);
1108
1109                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1110                 intel_dp_start_link_train(intel_dp);
1111                 intel_dp_complete_link_train(intel_dp);
1112                 if (port != PORT_A)
1113                         intel_dp_stop_link_train(intel_dp);
1114         } else if (type == INTEL_OUTPUT_HDMI) {
1115                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1116
1117                 intel_hdmi->set_infoframes(encoder,
1118                                            crtc->config.has_hdmi_sink,
1119                                            &crtc->config.adjusted_mode);
1120         }
1121 }
1122
1123 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1124 {
1125         struct drm_encoder *encoder = &intel_encoder->base;
1126         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1127         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1128         int type = intel_encoder->type;
1129         uint32_t val;
1130         bool wait = false;
1131
1132         val = I915_READ(DDI_BUF_CTL(port));
1133         if (val & DDI_BUF_CTL_ENABLE) {
1134                 val &= ~DDI_BUF_CTL_ENABLE;
1135                 I915_WRITE(DDI_BUF_CTL(port), val);
1136                 wait = true;
1137         }
1138
1139         val = I915_READ(DP_TP_CTL(port));
1140         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1141         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1142         I915_WRITE(DP_TP_CTL(port), val);
1143
1144         if (wait)
1145                 intel_wait_ddi_buf_idle(dev_priv, port);
1146
1147         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1148                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1149                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1150                 intel_edp_panel_vdd_on(intel_dp);
1151                 intel_edp_panel_off(intel_dp);
1152         }
1153
1154         I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1155 }
1156
1157 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1158 {
1159         struct drm_encoder *encoder = &intel_encoder->base;
1160         struct drm_crtc *crtc = encoder->crtc;
1161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1162         int pipe = intel_crtc->pipe;
1163         struct drm_device *dev = encoder->dev;
1164         struct drm_i915_private *dev_priv = dev->dev_private;
1165         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1166         int type = intel_encoder->type;
1167         uint32_t tmp;
1168
1169         if (type == INTEL_OUTPUT_HDMI) {
1170                 struct intel_digital_port *intel_dig_port =
1171                         enc_to_dig_port(encoder);
1172
1173                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1174                  * are ignored so nothing special needs to be done besides
1175                  * enabling the port.
1176                  */
1177                 I915_WRITE(DDI_BUF_CTL(port),
1178                            intel_dig_port->saved_port_bits |
1179                            DDI_BUF_CTL_ENABLE);
1180         } else if (type == INTEL_OUTPUT_EDP) {
1181                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1182
1183                 if (port == PORT_A)
1184                         intel_dp_stop_link_train(intel_dp);
1185
1186                 intel_edp_backlight_on(intel_dp);
1187                 intel_edp_psr_enable(intel_dp);
1188         }
1189
1190         if (intel_crtc->config.has_audio) {
1191                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1192                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1193                 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1194                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1195         }
1196 }
1197
1198 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1199 {
1200         struct drm_encoder *encoder = &intel_encoder->base;
1201         struct drm_crtc *crtc = encoder->crtc;
1202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1203         int pipe = intel_crtc->pipe;
1204         int type = intel_encoder->type;
1205         struct drm_device *dev = encoder->dev;
1206         struct drm_i915_private *dev_priv = dev->dev_private;
1207         uint32_t tmp;
1208
1209         /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
1210          * register is part of the power well on Haswell. */
1211         if (intel_crtc->config.has_audio) {
1212                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1213                 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1214                          (pipe * 4));
1215                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1216                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1217         }
1218
1219         if (type == INTEL_OUTPUT_EDP) {
1220                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1221
1222                 intel_edp_psr_disable(intel_dp);
1223                 intel_edp_backlight_off(intel_dp);
1224         }
1225 }
1226
1227 static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1228 {
1229         uint32_t lcpll = I915_READ(LCPLL_CTL);
1230         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1231
1232         if (lcpll & LCPLL_CD_SOURCE_FCLK)
1233                 return 800000;
1234         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1235                 return 450000;
1236         else if (freq == LCPLL_CLK_FREQ_450)
1237                 return 450000;
1238         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1239                 return 540000;
1240         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1241                 return 337500;
1242         else
1243                 return 675000;
1244 }
1245
1246 static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1247 {
1248         struct drm_device *dev = dev_priv->dev;
1249         uint32_t lcpll = I915_READ(LCPLL_CTL);
1250         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1251
1252         if (lcpll & LCPLL_CD_SOURCE_FCLK)
1253                 return 800000;
1254         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1255                 return 450000;
1256         else if (freq == LCPLL_CLK_FREQ_450)
1257                 return 450000;
1258         else if (IS_ULT(dev))
1259                 return 337500;
1260         else
1261                 return 540000;
1262 }
1263
1264 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1265 {
1266         struct drm_device *dev = dev_priv->dev;
1267
1268         if (IS_BROADWELL(dev))
1269                 return bdw_get_cdclk_freq(dev_priv);
1270
1271         /* Haswell */
1272         return hsw_get_cdclk_freq(dev_priv);
1273 }
1274
1275 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1276                                struct intel_shared_dpll *pll)
1277 {
1278         I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll);
1279         POSTING_READ(WRPLL_CTL(pll->id));
1280         udelay(20);
1281 }
1282
1283 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1284                                 struct intel_shared_dpll *pll)
1285 {
1286         uint32_t val;
1287
1288         val = I915_READ(WRPLL_CTL(pll->id));
1289         I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1290         POSTING_READ(WRPLL_CTL(pll->id));
1291 }
1292
1293 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1294                                      struct intel_shared_dpll *pll,
1295                                      struct intel_dpll_hw_state *hw_state)
1296 {
1297         uint32_t val;
1298
1299         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
1300                 return false;
1301
1302         val = I915_READ(WRPLL_CTL(pll->id));
1303         hw_state->wrpll = val;
1304
1305         return val & WRPLL_PLL_ENABLE;
1306 }
1307
1308 static const char * const hsw_ddi_pll_names[] = {
1309         "WRPLL 1",
1310         "WRPLL 2",
1311 };
1312
1313 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1314 {
1315         int i;
1316
1317         dev_priv->num_shared_dpll = 2;
1318
1319         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1320                 dev_priv->shared_dplls[i].id = i;
1321                 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1322                 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1323                 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1324                 dev_priv->shared_dplls[i].get_hw_state =
1325                         hsw_ddi_pll_get_hw_state;
1326         }
1327 }
1328
1329 void intel_ddi_pll_init(struct drm_device *dev)
1330 {
1331         struct drm_i915_private *dev_priv = dev->dev_private;
1332         uint32_t val = I915_READ(LCPLL_CTL);
1333
1334         hsw_shared_dplls_init(dev_priv);
1335
1336         /* The LCPLL register should be turned on by the BIOS. For now let's
1337          * just check its state and print errors in case something is wrong.
1338          * Don't even try to turn it on.
1339          */
1340
1341         DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1342                       intel_ddi_get_cdclk_freq(dev_priv));
1343
1344         if (val & LCPLL_CD_SOURCE_FCLK)
1345                 DRM_ERROR("CDCLK source is not LCPLL\n");
1346
1347         if (val & LCPLL_PLL_DISABLE)
1348                 DRM_ERROR("LCPLL is disabled\n");
1349 }
1350
1351 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1352 {
1353         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1354         struct intel_dp *intel_dp = &intel_dig_port->dp;
1355         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1356         enum port port = intel_dig_port->port;
1357         uint32_t val;
1358         bool wait = false;
1359
1360         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1361                 val = I915_READ(DDI_BUF_CTL(port));
1362                 if (val & DDI_BUF_CTL_ENABLE) {
1363                         val &= ~DDI_BUF_CTL_ENABLE;
1364                         I915_WRITE(DDI_BUF_CTL(port), val);
1365                         wait = true;
1366                 }
1367
1368                 val = I915_READ(DP_TP_CTL(port));
1369                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1370                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1371                 I915_WRITE(DP_TP_CTL(port), val);
1372                 POSTING_READ(DP_TP_CTL(port));
1373
1374                 if (wait)
1375                         intel_wait_ddi_buf_idle(dev_priv, port);
1376         }
1377
1378         val = DP_TP_CTL_ENABLE |
1379               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1380         if (intel_dp->is_mst)
1381                 val |= DP_TP_CTL_MODE_MST;
1382         else {
1383                 val |= DP_TP_CTL_MODE_SST;
1384                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1385                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1386         }
1387         I915_WRITE(DP_TP_CTL(port), val);
1388         POSTING_READ(DP_TP_CTL(port));
1389
1390         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1391         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1392         POSTING_READ(DDI_BUF_CTL(port));
1393
1394         udelay(600);
1395 }
1396
1397 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1398 {
1399         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1400         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1401         uint32_t val;
1402
1403         intel_ddi_post_disable(intel_encoder);
1404
1405         val = I915_READ(_FDI_RXA_CTL);
1406         val &= ~FDI_RX_ENABLE;
1407         I915_WRITE(_FDI_RXA_CTL, val);
1408
1409         val = I915_READ(_FDI_RXA_MISC);
1410         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1411         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1412         I915_WRITE(_FDI_RXA_MISC, val);
1413
1414         val = I915_READ(_FDI_RXA_CTL);
1415         val &= ~FDI_PCDCLK;
1416         I915_WRITE(_FDI_RXA_CTL, val);
1417
1418         val = I915_READ(_FDI_RXA_CTL);
1419         val &= ~FDI_RX_PLL_ENABLE;
1420         I915_WRITE(_FDI_RXA_CTL, val);
1421 }
1422
1423 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1424 {
1425         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
1426         int type = intel_dig_port->base.type;
1427
1428         if (type != INTEL_OUTPUT_DISPLAYPORT &&
1429             type != INTEL_OUTPUT_EDP &&
1430             type != INTEL_OUTPUT_UNKNOWN) {
1431                 return;
1432         }
1433
1434         intel_dp_hot_plug(intel_encoder);
1435 }
1436
1437 void intel_ddi_get_config(struct intel_encoder *encoder,
1438                           struct intel_crtc_config *pipe_config)
1439 {
1440         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1441         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1442         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1443         u32 temp, flags = 0;
1444
1445         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1446         if (temp & TRANS_DDI_PHSYNC)
1447                 flags |= DRM_MODE_FLAG_PHSYNC;
1448         else
1449                 flags |= DRM_MODE_FLAG_NHSYNC;
1450         if (temp & TRANS_DDI_PVSYNC)
1451                 flags |= DRM_MODE_FLAG_PVSYNC;
1452         else
1453                 flags |= DRM_MODE_FLAG_NVSYNC;
1454
1455         pipe_config->adjusted_mode.flags |= flags;
1456
1457         switch (temp & TRANS_DDI_BPC_MASK) {
1458         case TRANS_DDI_BPC_6:
1459                 pipe_config->pipe_bpp = 18;
1460                 break;
1461         case TRANS_DDI_BPC_8:
1462                 pipe_config->pipe_bpp = 24;
1463                 break;
1464         case TRANS_DDI_BPC_10:
1465                 pipe_config->pipe_bpp = 30;
1466                 break;
1467         case TRANS_DDI_BPC_12:
1468                 pipe_config->pipe_bpp = 36;
1469                 break;
1470         default:
1471                 break;
1472         }
1473
1474         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1475         case TRANS_DDI_MODE_SELECT_HDMI:
1476                 pipe_config->has_hdmi_sink = true;
1477         case TRANS_DDI_MODE_SELECT_DVI:
1478         case TRANS_DDI_MODE_SELECT_FDI:
1479                 break;
1480         case TRANS_DDI_MODE_SELECT_DP_SST:
1481         case TRANS_DDI_MODE_SELECT_DP_MST:
1482                 pipe_config->has_dp_encoder = true;
1483                 intel_dp_get_m_n(intel_crtc, pipe_config);
1484                 break;
1485         default:
1486                 break;
1487         }
1488
1489         if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1490                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1491                 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
1492                         pipe_config->has_audio = true;
1493         }
1494
1495         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1496             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1497                 /*
1498                  * This is a big fat ugly hack.
1499                  *
1500                  * Some machines in UEFI boot mode provide us a VBT that has 18
1501                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1502                  * unknown we fail to light up. Yet the same BIOS boots up with
1503                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1504                  * max, not what it tells us to use.
1505                  *
1506                  * Note: This will still be broken if the eDP panel is not lit
1507                  * up by the BIOS, and thus we can't get the mode at module
1508                  * load.
1509                  */
1510                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1511                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1512                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1513         }
1514
1515         hsw_ddi_clock_get(encoder, pipe_config);
1516 }
1517
1518 static void intel_ddi_destroy(struct drm_encoder *encoder)
1519 {
1520         /* HDMI has nothing special to destroy, so we can go with this. */
1521         intel_dp_encoder_destroy(encoder);
1522 }
1523
1524 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1525                                      struct intel_crtc_config *pipe_config)
1526 {
1527         int type = encoder->type;
1528         int port = intel_ddi_get_encoder_port(encoder);
1529
1530         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1531
1532         if (port == PORT_A)
1533                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1534
1535         if (type == INTEL_OUTPUT_HDMI)
1536                 return intel_hdmi_compute_config(encoder, pipe_config);
1537         else
1538                 return intel_dp_compute_config(encoder, pipe_config);
1539 }
1540
1541 static const struct drm_encoder_funcs intel_ddi_funcs = {
1542         .destroy = intel_ddi_destroy,
1543 };
1544
1545 static struct intel_connector *
1546 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1547 {
1548         struct intel_connector *connector;
1549         enum port port = intel_dig_port->port;
1550
1551         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1552         if (!connector)
1553                 return NULL;
1554
1555         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1556         if (!intel_dp_init_connector(intel_dig_port, connector)) {
1557                 kfree(connector);
1558                 return NULL;
1559         }
1560
1561         return connector;
1562 }
1563
1564 static struct intel_connector *
1565 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1566 {
1567         struct intel_connector *connector;
1568         enum port port = intel_dig_port->port;
1569
1570         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1571         if (!connector)
1572                 return NULL;
1573
1574         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1575         intel_hdmi_init_connector(intel_dig_port, connector);
1576
1577         return connector;
1578 }
1579
1580 void intel_ddi_init(struct drm_device *dev, enum port port)
1581 {
1582         struct drm_i915_private *dev_priv = dev->dev_private;
1583         struct intel_digital_port *intel_dig_port;
1584         struct intel_encoder *intel_encoder;
1585         struct drm_encoder *encoder;
1586         bool init_hdmi, init_dp;
1587
1588         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1589                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1590         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1591         if (!init_dp && !init_hdmi) {
1592                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
1593                               port_name(port));
1594                 init_hdmi = true;
1595                 init_dp = true;
1596         }
1597
1598         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1599         if (!intel_dig_port)
1600                 return;
1601
1602         intel_encoder = &intel_dig_port->base;
1603         encoder = &intel_encoder->base;
1604
1605         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1606                          DRM_MODE_ENCODER_TMDS);
1607
1608         intel_encoder->compute_config = intel_ddi_compute_config;
1609         intel_encoder->enable = intel_enable_ddi;
1610         intel_encoder->pre_enable = intel_ddi_pre_enable;
1611         intel_encoder->disable = intel_disable_ddi;
1612         intel_encoder->post_disable = intel_ddi_post_disable;
1613         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1614         intel_encoder->get_config = intel_ddi_get_config;
1615
1616         intel_dig_port->port = port;
1617         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1618                                           (DDI_BUF_PORT_REVERSAL |
1619                                            DDI_A_4_LANES);
1620
1621         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1622         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1623         intel_encoder->cloneable = 0;
1624         intel_encoder->hot_plug = intel_ddi_hot_plug;
1625
1626         if (init_dp) {
1627                 if (!intel_ddi_init_dp_connector(intel_dig_port))
1628                         goto err;
1629
1630                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
1631                 dev_priv->hpd_irq_port[port] = intel_dig_port;
1632         }
1633
1634         /* In theory we don't need the encoder->type check, but leave it just in
1635          * case we have some really bad VBTs... */
1636         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
1637                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
1638                         goto err;
1639         }
1640
1641         return;
1642
1643 err:
1644         drm_encoder_cleanup(encoder);
1645         kfree(intel_dig_port);
1646 }