2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
131 /* Skylake H and S */
132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146 { 0x0000201B, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost level 0x1 */
150 { 0x0000201B, 0x0000009D, 0x0 },
151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
162 { 0x80009010, 0x000000C7, 0x3 }, /* Uses I_boost level 0x3 */
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
172 * eDP 1.4 low vswing translation parameters
174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
189 * eDP 1.4 low vswing translation parameters
191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
206 * eDP 1.4 low vswing translation parameters
208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
221 /* Skylake U, H and S */
222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */
248 { 0x00000018, 0x000000C7, 0x0 },
251 struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
256 bool default_index; /* true if the entry represents default value */
259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
287 /* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
304 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
305 enum port port, int type);
307 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
311 struct drm_encoder *encoder = &intel_encoder->base;
313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
318 case INTEL_OUTPUT_DISPLAYPORT:
319 case INTEL_OUTPUT_EDP:
320 case INTEL_OUTPUT_HDMI:
321 case INTEL_OUTPUT_UNKNOWN:
322 *dig_port = enc_to_dig_port(encoder);
323 *port = (*dig_port)->port;
325 case INTEL_OUTPUT_ANALOG:
330 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
335 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
337 struct intel_digital_port *dig_port;
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
346 intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
348 return intel_dig_port->hdmi.hdmi_reg;
351 static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
354 const struct ddi_buf_trans *ddi_translations;
356 if (IS_SKL_ULX(dev)) {
357 ddi_translations = skl_y_ddi_translations_dp;
358 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
359 } else if (IS_SKL_ULT(dev)) {
360 ddi_translations = skl_u_ddi_translations_dp;
361 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
363 ddi_translations = skl_ddi_translations_dp;
364 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
367 return ddi_translations;
370 static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
373 struct drm_i915_private *dev_priv = dev->dev_private;
374 const struct ddi_buf_trans *ddi_translations;
376 if (IS_SKL_ULX(dev)) {
377 if (dev_priv->edp_low_vswing) {
378 ddi_translations = skl_y_ddi_translations_edp;
379 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
381 ddi_translations = skl_y_ddi_translations_dp;
382 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
384 } else if (IS_SKL_ULT(dev)) {
385 if (dev_priv->edp_low_vswing) {
386 ddi_translations = skl_u_ddi_translations_edp;
387 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
389 ddi_translations = skl_u_ddi_translations_dp;
390 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
393 if (dev_priv->edp_low_vswing) {
394 ddi_translations = skl_ddi_translations_edp;
395 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
397 ddi_translations = skl_ddi_translations_dp;
398 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
402 return ddi_translations;
405 static const struct ddi_buf_trans *
406 skl_get_buf_trans_hdmi(struct drm_device *dev,
409 const struct ddi_buf_trans *ddi_translations;
411 if (IS_SKL_ULX(dev)) {
412 ddi_translations = skl_y_ddi_translations_hdmi;
413 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
415 ddi_translations = skl_ddi_translations_hdmi;
416 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
419 return ddi_translations;
423 * Starting with Haswell, DDI port buffers must be programmed with correct
424 * values in advance. The buffer values are different for FDI and DP modes,
425 * but the HDMI/DVI fields are shared among those. So we program the DDI
426 * in either FDI or DP modes only, as HDMI connections will work with both
429 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
432 struct drm_i915_private *dev_priv = dev->dev_private;
434 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
436 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
437 const struct ddi_buf_trans *ddi_translations_fdi;
438 const struct ddi_buf_trans *ddi_translations_dp;
439 const struct ddi_buf_trans *ddi_translations_edp;
440 const struct ddi_buf_trans *ddi_translations_hdmi;
441 const struct ddi_buf_trans *ddi_translations;
443 if (IS_BROXTON(dev)) {
447 /* Vswing programming for HDMI */
448 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
451 } else if (IS_SKYLAKE(dev)) {
452 ddi_translations_fdi = NULL;
453 ddi_translations_dp =
454 skl_get_buf_trans_dp(dev, &n_dp_entries);
455 ddi_translations_edp =
456 skl_get_buf_trans_edp(dev, &n_edp_entries);
457 ddi_translations_hdmi =
458 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
459 hdmi_default_entry = 8;
460 /* If we're boosting the current, set bit 31 of trans1 */
461 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
462 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
464 } else if (IS_BROADWELL(dev)) {
465 ddi_translations_fdi = bdw_ddi_translations_fdi;
466 ddi_translations_dp = bdw_ddi_translations_dp;
467 ddi_translations_edp = bdw_ddi_translations_edp;
468 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
469 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
470 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
471 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
472 hdmi_default_entry = 7;
473 } else if (IS_HASWELL(dev)) {
474 ddi_translations_fdi = hsw_ddi_translations_fdi;
475 ddi_translations_dp = hsw_ddi_translations_dp;
476 ddi_translations_edp = hsw_ddi_translations_dp;
477 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
478 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
479 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
480 hdmi_default_entry = 6;
482 WARN(1, "ddi translation table missing\n");
483 ddi_translations_edp = bdw_ddi_translations_dp;
484 ddi_translations_fdi = bdw_ddi_translations_fdi;
485 ddi_translations_dp = bdw_ddi_translations_dp;
486 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
487 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
488 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
489 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
490 hdmi_default_entry = 7;
495 ddi_translations = ddi_translations_edp;
496 size = n_edp_entries;
500 ddi_translations = ddi_translations_dp;
504 if (intel_dp_is_edp(dev, PORT_D)) {
505 ddi_translations = ddi_translations_edp;
506 size = n_edp_entries;
508 ddi_translations = ddi_translations_dp;
513 if (ddi_translations_fdi)
514 ddi_translations = ddi_translations_fdi;
516 ddi_translations = ddi_translations_dp;
523 for (i = 0; i < size; i++) {
524 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
525 ddi_translations[i].trans1 | iboost_bit);
526 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
527 ddi_translations[i].trans2);
533 /* Choose a good default if VBT is badly populated */
534 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
535 hdmi_level >= n_hdmi_entries)
536 hdmi_level = hdmi_default_entry;
538 /* Entry 9 is for HDMI: */
539 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
540 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
541 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
542 ddi_translations_hdmi[hdmi_level].trans2);
545 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
546 * mode and port E for FDI.
548 void intel_prepare_ddi(struct drm_device *dev)
550 struct intel_encoder *intel_encoder;
551 bool visited[I915_MAX_PORTS] = { 0, };
556 for_each_intel_encoder(dev, intel_encoder) {
557 struct intel_digital_port *intel_dig_port;
561 if (intel_encoder->type == INTEL_OUTPUT_DSI)
564 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
568 supports_hdmi = intel_dig_port &&
569 intel_dig_port_supports_hdmi(intel_dig_port);
571 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
572 visited[port] = true;
576 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
579 uint32_t reg = DDI_BUF_CTL(port);
582 for (i = 0; i < 16; i++) {
584 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
587 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
590 /* Starting with Haswell, different DDI ports can work in FDI mode for
591 * connection to the PCH-located connectors. For this, it is necessary to train
592 * both the DDI port and PCH receiver for the desired DDI buffer settings.
594 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
595 * please note that when FDI mode is active on DDI E, it shares 2 lines with
596 * DDI A (which is used for eDP)
599 void hsw_fdi_link_train(struct drm_crtc *crtc)
601 struct drm_device *dev = crtc->dev;
602 struct drm_i915_private *dev_priv = dev->dev_private;
603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
604 u32 temp, i, rx_ctl_val;
606 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
607 * mode set "sequence for CRT port" document:
608 * - TP1 to TP2 time with the default value
611 * WaFDIAutoLinkSetTimingOverrride:hsw
613 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
614 FDI_RX_PWRDN_LANE0_VAL(2) |
615 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
617 /* Enable the PCH Receiver FDI PLL */
618 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
620 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
621 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
622 POSTING_READ(FDI_RX_CTL(PIPE_A));
625 /* Switch from Rawclk to PCDclk */
626 rx_ctl_val |= FDI_PCDCLK;
627 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
629 /* Configure Port Clock Select */
630 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
631 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
633 /* Start the training iterating through available voltages and emphasis,
634 * testing each value twice. */
635 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
636 /* Configure DP_TP_CTL with auto-training */
637 I915_WRITE(DP_TP_CTL(PORT_E),
638 DP_TP_CTL_FDI_AUTOTRAIN |
639 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
640 DP_TP_CTL_LINK_TRAIN_PAT1 |
643 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
644 * DDI E does not support port reversal, the functionality is
645 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
646 * port reversal bit */
647 I915_WRITE(DDI_BUF_CTL(PORT_E),
649 ((intel_crtc->config->fdi_lanes - 1) << 1) |
650 DDI_BUF_TRANS_SELECT(i / 2));
651 POSTING_READ(DDI_BUF_CTL(PORT_E));
655 /* Program PCH FDI Receiver TU */
656 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
658 /* Enable PCH FDI Receiver with auto-training */
659 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
660 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
661 POSTING_READ(FDI_RX_CTL(PIPE_A));
663 /* Wait for FDI receiver lane calibration */
666 /* Unset FDI_RX_MISC pwrdn lanes */
667 temp = I915_READ(FDI_RX_MISC(PIPE_A));
668 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
669 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
670 POSTING_READ(FDI_RX_MISC(PIPE_A));
672 /* Wait for FDI auto training time */
675 temp = I915_READ(DP_TP_STATUS(PORT_E));
676 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
677 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
679 /* Enable normal pixel sending for FDI */
680 I915_WRITE(DP_TP_CTL(PORT_E),
681 DP_TP_CTL_FDI_AUTOTRAIN |
682 DP_TP_CTL_LINK_TRAIN_NORMAL |
683 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
689 temp = I915_READ(DDI_BUF_CTL(PORT_E));
690 temp &= ~DDI_BUF_CTL_ENABLE;
691 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
692 POSTING_READ(DDI_BUF_CTL(PORT_E));
694 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
695 temp = I915_READ(DP_TP_CTL(PORT_E));
696 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
697 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
698 I915_WRITE(DP_TP_CTL(PORT_E), temp);
699 POSTING_READ(DP_TP_CTL(PORT_E));
701 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
703 rx_ctl_val &= ~FDI_RX_ENABLE;
704 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
705 POSTING_READ(FDI_RX_CTL(PIPE_A));
707 /* Reset FDI_RX_MISC pwrdn lanes */
708 temp = I915_READ(FDI_RX_MISC(PIPE_A));
709 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
710 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
711 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
712 POSTING_READ(FDI_RX_MISC(PIPE_A));
715 DRM_ERROR("FDI link training failed!\n");
718 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
720 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
721 struct intel_digital_port *intel_dig_port =
722 enc_to_dig_port(&encoder->base);
724 intel_dp->DP = intel_dig_port->saved_port_bits |
725 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
726 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
729 static struct intel_encoder *
730 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
732 struct drm_device *dev = crtc->dev;
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734 struct intel_encoder *intel_encoder, *ret = NULL;
735 int num_encoders = 0;
737 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
742 if (num_encoders != 1)
743 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
744 pipe_name(intel_crtc->pipe));
750 struct intel_encoder *
751 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
753 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
754 struct intel_encoder *ret = NULL;
755 struct drm_atomic_state *state;
756 struct drm_connector *connector;
757 struct drm_connector_state *connector_state;
758 int num_encoders = 0;
761 state = crtc_state->base.state;
763 for_each_connector_in_state(state, connector, connector_state, i) {
764 if (connector_state->crtc != crtc_state->base.crtc)
767 ret = to_intel_encoder(connector_state->best_encoder);
771 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
772 pipe_name(crtc->pipe));
779 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
785 /* Constraints for PLL good behavior */
791 #define abs_diff(a, b) ({ \
792 typeof(a) __a = (a); \
793 typeof(b) __b = (b); \
794 (void) (&__a == &__b); \
795 __a > __b ? (__a - __b) : (__b - __a); })
797 struct hsw_wrpll_rnp {
801 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
875 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
876 unsigned r2, unsigned n2, unsigned p,
877 struct hsw_wrpll_rnp *best)
879 uint64_t a, b, c, d, diff, diff_best;
881 /* No best (r,n,p) yet */
890 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
894 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
897 * and we would like delta <= budget.
899 * If the discrepancy is above the PPM-based budget, always prefer to
900 * improve upon the previous solution. However, if you're within the
901 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
903 a = freq2k * budget * p * r2;
904 b = freq2k * budget * best->p * best->r2;
905 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
906 diff_best = abs_diff(freq2k * best->p * best->r2,
907 LC_FREQ_2K * best->n2);
909 d = 1000000 * diff_best;
911 if (a < c && b < d) {
912 /* If both are above the budget, pick the closer */
913 if (best->p * best->r2 * diff < p * r2 * diff_best) {
918 } else if (a >= c && b < d) {
919 /* If A is below the threshold but B is above it? Update. */
923 } else if (a >= c && b >= d) {
924 /* Both are below the limit, so pick the higher n2/(r2*r2) */
925 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
931 /* Otherwise a < c && b >= d, do nothing */
934 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
936 int refclk = LC_FREQ;
940 wrpll = I915_READ(reg);
941 switch (wrpll & WRPLL_PLL_REF_MASK) {
943 case WRPLL_PLL_NON_SSC:
945 * We could calculate spread here, but our checking
946 * code only cares about 5% accuracy, and spread is a max of
951 case WRPLL_PLL_LCPLL:
955 WARN(1, "bad wrpll refclk\n");
959 r = wrpll & WRPLL_DIVIDER_REF_MASK;
960 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
961 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
963 /* Convert to KHz, p & r have a fixed point portion */
964 return (refclk * n * 100) / (p * r);
967 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
970 uint32_t cfgcr1_reg, cfgcr2_reg;
971 uint32_t cfgcr1_val, cfgcr2_val;
972 uint32_t p0, p1, p2, dco_freq;
974 cfgcr1_reg = DPLL_CFGCR1(dpll);
975 cfgcr2_reg = DPLL_CFGCR2(dpll);
977 cfgcr1_val = I915_READ(cfgcr1_reg);
978 cfgcr2_val = I915_READ(cfgcr2_reg);
980 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
981 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
983 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
984 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
990 case DPLL_CFGCR2_PDIV_1:
993 case DPLL_CFGCR2_PDIV_2:
996 case DPLL_CFGCR2_PDIV_3:
999 case DPLL_CFGCR2_PDIV_7:
1005 case DPLL_CFGCR2_KDIV_5:
1008 case DPLL_CFGCR2_KDIV_2:
1011 case DPLL_CFGCR2_KDIV_3:
1014 case DPLL_CFGCR2_KDIV_1:
1019 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1021 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1024 return dco_freq / (p0 * p1 * p2 * 5);
1027 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1031 if (pipe_config->has_pch_encoder)
1032 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1033 &pipe_config->fdi_m_n);
1034 else if (pipe_config->has_dp_encoder)
1035 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1036 &pipe_config->dp_m_n);
1037 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1038 dotclock = pipe_config->port_clock * 2 / 3;
1040 dotclock = pipe_config->port_clock;
1042 if (pipe_config->pixel_multiplier)
1043 dotclock /= pipe_config->pixel_multiplier;
1045 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1048 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1049 struct intel_crtc_state *pipe_config)
1051 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1053 uint32_t dpll_ctl1, dpll;
1055 dpll = pipe_config->ddi_pll_sel;
1057 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1059 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1060 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1062 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1063 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1065 switch (link_clock) {
1066 case DPLL_CTRL1_LINK_RATE_810:
1069 case DPLL_CTRL1_LINK_RATE_1080:
1070 link_clock = 108000;
1072 case DPLL_CTRL1_LINK_RATE_1350:
1073 link_clock = 135000;
1075 case DPLL_CTRL1_LINK_RATE_1620:
1076 link_clock = 162000;
1078 case DPLL_CTRL1_LINK_RATE_2160:
1079 link_clock = 216000;
1081 case DPLL_CTRL1_LINK_RATE_2700:
1082 link_clock = 270000;
1085 WARN(1, "Unsupported link rate\n");
1091 pipe_config->port_clock = link_clock;
1093 ddi_dotclock_get(pipe_config);
1096 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1097 struct intel_crtc_state *pipe_config)
1099 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1103 val = pipe_config->ddi_pll_sel;
1104 switch (val & PORT_CLK_SEL_MASK) {
1105 case PORT_CLK_SEL_LCPLL_810:
1108 case PORT_CLK_SEL_LCPLL_1350:
1109 link_clock = 135000;
1111 case PORT_CLK_SEL_LCPLL_2700:
1112 link_clock = 270000;
1114 case PORT_CLK_SEL_WRPLL1:
1115 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
1117 case PORT_CLK_SEL_WRPLL2:
1118 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
1120 case PORT_CLK_SEL_SPLL:
1121 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1122 if (pll == SPLL_PLL_FREQ_810MHz)
1124 else if (pll == SPLL_PLL_FREQ_1350MHz)
1125 link_clock = 135000;
1126 else if (pll == SPLL_PLL_FREQ_2700MHz)
1127 link_clock = 270000;
1129 WARN(1, "bad spll freq\n");
1134 WARN(1, "bad port clock sel\n");
1138 pipe_config->port_clock = link_clock * 2;
1140 ddi_dotclock_get(pipe_config);
1143 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1144 enum intel_dpll_id dpll)
1146 struct intel_shared_dpll *pll;
1147 struct intel_dpll_hw_state *state;
1148 intel_clock_t clock;
1150 /* For DDI ports we always use a shared PLL. */
1151 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1154 pll = &dev_priv->shared_dplls[dpll];
1155 state = &pll->config.hw_state;
1158 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1159 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1160 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1161 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1162 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1163 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1165 return chv_calc_dpll_params(100000, &clock);
1168 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1169 struct intel_crtc_state *pipe_config)
1171 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1172 enum port port = intel_ddi_get_encoder_port(encoder);
1173 uint32_t dpll = port;
1175 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1177 ddi_dotclock_get(pipe_config);
1180 void intel_ddi_clock_get(struct intel_encoder *encoder,
1181 struct intel_crtc_state *pipe_config)
1183 struct drm_device *dev = encoder->base.dev;
1185 if (INTEL_INFO(dev)->gen <= 8)
1186 hsw_ddi_clock_get(encoder, pipe_config);
1187 else if (IS_SKYLAKE(dev))
1188 skl_ddi_clock_get(encoder, pipe_config);
1189 else if (IS_BROXTON(dev))
1190 bxt_ddi_clock_get(encoder, pipe_config);
1194 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1195 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1199 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1202 freq2k = clock / 100;
1204 budget = hsw_wrpll_get_budget_for_freq(clock);
1206 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1207 * and directly pass the LC PLL to it. */
1208 if (freq2k == 5400000) {
1216 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1219 * We want R so that REF_MIN <= Ref <= REF_MAX.
1220 * Injecting R2 = 2 * R gives:
1221 * REF_MAX * r2 > LC_FREQ * 2 and
1222 * REF_MIN * r2 < LC_FREQ * 2
1224 * Which means the desired boundaries for r2 are:
1225 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1228 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1229 r2 <= LC_FREQ * 2 / REF_MIN;
1233 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1235 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1236 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1237 * VCO_MAX * r2 > n2 * LC_FREQ and
1238 * VCO_MIN * r2 < n2 * LC_FREQ)
1240 * Which means the desired boundaries for n2 are:
1241 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1243 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1244 n2 <= VCO_MAX * r2 / LC_FREQ;
1247 for (p = P_MIN; p <= P_MAX; p += P_INC)
1248 hsw_wrpll_update_rnp(freq2k, budget,
1259 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1260 struct intel_crtc_state *crtc_state,
1261 struct intel_encoder *intel_encoder)
1263 int clock = crtc_state->port_clock;
1265 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1266 struct intel_shared_dpll *pll;
1270 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
1272 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
1273 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1274 WRPLL_DIVIDER_POST(p);
1276 memset(&crtc_state->dpll_hw_state, 0,
1277 sizeof(crtc_state->dpll_hw_state));
1279 crtc_state->dpll_hw_state.wrpll = val;
1281 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1283 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1284 pipe_name(intel_crtc->pipe));
1288 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
1289 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
1290 struct drm_atomic_state *state = crtc_state->base.state;
1291 struct intel_shared_dpll_config *spll =
1292 &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
1294 if (spll->crtc_mask &&
1295 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
1298 crtc_state->shared_dpll = DPLL_ID_SPLL;
1299 spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
1300 spll->crtc_mask |= 1 << intel_crtc->pipe;
1306 struct skl_wrpll_context {
1307 uint64_t min_deviation; /* current minimal deviation */
1308 uint64_t central_freq; /* chosen central freq */
1309 uint64_t dco_freq; /* chosen dco freq */
1310 unsigned int p; /* chosen divider */
1313 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1315 memset(ctx, 0, sizeof(*ctx));
1317 ctx->min_deviation = U64_MAX;
1320 /* DCO freq must be within +1%/-6% of the DCO central freq */
1321 #define SKL_DCO_MAX_PDEVIATION 100
1322 #define SKL_DCO_MAX_NDEVIATION 600
1324 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1325 uint64_t central_freq,
1327 unsigned int divider)
1331 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1334 /* positive deviation */
1335 if (dco_freq >= central_freq) {
1336 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1337 deviation < ctx->min_deviation) {
1338 ctx->min_deviation = deviation;
1339 ctx->central_freq = central_freq;
1340 ctx->dco_freq = dco_freq;
1343 /* negative deviation */
1344 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1345 deviation < ctx->min_deviation) {
1346 ctx->min_deviation = deviation;
1347 ctx->central_freq = central_freq;
1348 ctx->dco_freq = dco_freq;
1353 static void skl_wrpll_get_multipliers(unsigned int p,
1354 unsigned int *p0 /* out */,
1355 unsigned int *p1 /* out */,
1356 unsigned int *p2 /* out */)
1360 unsigned int half = p / 2;
1362 if (half == 1 || half == 2 || half == 3 || half == 5) {
1366 } else if (half % 2 == 0) {
1370 } else if (half % 3 == 0) {
1374 } else if (half % 7 == 0) {
1379 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1383 } else if (p == 5 || p == 7) {
1387 } else if (p == 15) {
1391 } else if (p == 21) {
1395 } else if (p == 35) {
1402 struct skl_wrpll_params {
1403 uint32_t dco_fraction;
1404 uint32_t dco_integer;
1405 uint32_t qdiv_ratio;
1409 uint32_t central_freq;
1412 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1414 uint64_t central_freq,
1415 uint32_t p0, uint32_t p1, uint32_t p2)
1419 switch (central_freq) {
1421 params->central_freq = 0;
1424 params->central_freq = 1;
1427 params->central_freq = 3;
1444 WARN(1, "Incorrect PDiv\n");
1461 WARN(1, "Incorrect KDiv\n");
1464 params->qdiv_ratio = p1;
1465 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1467 dco_freq = p0 * p1 * p2 * afe_clock;
1470 * Intermediate values are in Hz.
1471 * Divide by MHz to match bsepc
1473 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1474 params->dco_fraction =
1475 div_u64((div_u64(dco_freq, 24) -
1476 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1480 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1481 struct skl_wrpll_params *wrpll_params)
1483 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1484 uint64_t dco_central_freq[3] = {8400000000ULL,
1487 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1488 24, 28, 30, 32, 36, 40, 42, 44,
1489 48, 52, 54, 56, 60, 64, 66, 68,
1490 70, 72, 76, 78, 80, 84, 88, 90,
1492 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1493 static const struct {
1497 { even_dividers, ARRAY_SIZE(even_dividers) },
1498 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1500 struct skl_wrpll_context ctx;
1501 unsigned int dco, d, i;
1502 unsigned int p0, p1, p2;
1504 skl_wrpll_context_init(&ctx);
1506 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1507 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1508 for (i = 0; i < dividers[d].n_dividers; i++) {
1509 unsigned int p = dividers[d].list[i];
1510 uint64_t dco_freq = p * afe_clock;
1512 skl_wrpll_try_divider(&ctx,
1513 dco_central_freq[dco],
1517 * Skip the remaining dividers if we're sure to
1518 * have found the definitive divider, we can't
1519 * improve a 0 deviation.
1521 if (ctx.min_deviation == 0)
1522 goto skip_remaining_dividers;
1526 skip_remaining_dividers:
1528 * If a solution is found with an even divider, prefer
1531 if (d == 0 && ctx.p)
1536 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1541 * gcc incorrectly analyses that these can be used without being
1542 * initialized. To be fair, it's hard to guess.
1545 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1546 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1553 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1554 struct intel_crtc_state *crtc_state,
1555 struct intel_encoder *intel_encoder)
1557 struct intel_shared_dpll *pll;
1558 uint32_t ctrl1, cfgcr1, cfgcr2;
1559 int clock = crtc_state->port_clock;
1562 * See comment in intel_dpll_hw_state to understand why we always use 0
1563 * as the DPLL id in this function.
1566 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1568 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1569 struct skl_wrpll_params wrpll_params = { 0, };
1571 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1573 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1576 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1577 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1578 wrpll_params.dco_integer;
1580 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1581 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1582 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1583 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1584 wrpll_params.central_freq;
1585 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1586 intel_encoder->type == INTEL_OUTPUT_DP_MST) {
1587 switch (crtc_state->port_clock / 2) {
1589 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1592 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1595 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1599 cfgcr1 = cfgcr2 = 0;
1603 memset(&crtc_state->dpll_hw_state, 0,
1604 sizeof(crtc_state->dpll_hw_state));
1606 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1607 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1608 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1610 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1612 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1613 pipe_name(intel_crtc->pipe));
1617 /* shared DPLL id 0 is DPLL 1 */
1618 crtc_state->ddi_pll_sel = pll->id + 1;
1623 /* bxt clock parameters */
1624 struct bxt_clk_div {
1634 /* pre-calculated values for DP linkrates */
1635 static const struct bxt_clk_div bxt_dp_clk_val[] = {
1636 {162000, 4, 2, 32, 1677722, 1, 1},
1637 {270000, 4, 1, 27, 0, 0, 1},
1638 {540000, 2, 1, 27, 0, 0, 1},
1639 {216000, 3, 2, 32, 1677722, 1, 1},
1640 {243000, 4, 1, 24, 1258291, 1, 1},
1641 {324000, 4, 1, 32, 1677722, 1, 1},
1642 {432000, 3, 1, 32, 1677722, 1, 1}
1646 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1647 struct intel_crtc_state *crtc_state,
1648 struct intel_encoder *intel_encoder)
1650 struct intel_shared_dpll *pll;
1651 struct bxt_clk_div clk_div = {0};
1653 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1654 uint32_t lanestagger;
1655 int clock = crtc_state->port_clock;
1657 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1658 intel_clock_t best_clock;
1660 /* Calculate HDMI div */
1662 * FIXME: tie the following calculation into
1663 * i9xx_crtc_compute_clock
1665 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1666 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1667 clock, pipe_name(intel_crtc->pipe));
1671 clk_div.p1 = best_clock.p1;
1672 clk_div.p2 = best_clock.p2;
1673 WARN_ON(best_clock.m1 != 2);
1674 clk_div.n = best_clock.n;
1675 clk_div.m2_int = best_clock.m2 >> 22;
1676 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1677 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1679 vco = best_clock.vco;
1680 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1681 intel_encoder->type == INTEL_OUTPUT_EDP) {
1684 clk_div = bxt_dp_clk_val[0];
1685 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1686 if (bxt_dp_clk_val[i].clock == clock) {
1687 clk_div = bxt_dp_clk_val[i];
1691 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1694 if (vco >= 6200000 && vco <= 6700000) {
1699 } else if ((vco > 5400000 && vco < 6200000) ||
1700 (vco >= 4800000 && vco < 5400000)) {
1705 } else if (vco == 5400000) {
1711 DRM_ERROR("Invalid VCO\n");
1715 memset(&crtc_state->dpll_hw_state, 0,
1716 sizeof(crtc_state->dpll_hw_state));
1720 else if (clock > 135000)
1722 else if (clock > 67000)
1724 else if (clock > 33000)
1729 crtc_state->dpll_hw_state.ebb0 =
1730 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1731 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1732 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1733 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1735 if (clk_div.m2_frac_en)
1736 crtc_state->dpll_hw_state.pll3 =
1737 PORT_PLL_M2_FRAC_ENABLE;
1739 crtc_state->dpll_hw_state.pll6 =
1740 prop_coef | PORT_PLL_INT_COEFF(int_coef);
1741 crtc_state->dpll_hw_state.pll6 |=
1742 PORT_PLL_GAIN_CTL(gain_ctl);
1744 crtc_state->dpll_hw_state.pll8 = targ_cnt;
1746 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1748 crtc_state->dpll_hw_state.pll10 =
1749 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1750 | PORT_PLL_DCO_AMP_OVR_EN_H;
1752 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1754 crtc_state->dpll_hw_state.pcsdw12 =
1755 LANESTAGGER_STRAP_OVRD | lanestagger;
1757 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1759 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1760 pipe_name(intel_crtc->pipe));
1764 /* shared DPLL id 0 is DPLL A */
1765 crtc_state->ddi_pll_sel = pll->id;
1771 * Tries to find a *shared* PLL for the CRTC and store it in
1772 * intel_crtc->ddi_pll_sel.
1774 * For private DPLLs, compute_config() should do the selection for us. This
1775 * function should be folded into compute_config() eventually.
1777 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1778 struct intel_crtc_state *crtc_state)
1780 struct drm_device *dev = intel_crtc->base.dev;
1781 struct intel_encoder *intel_encoder =
1782 intel_ddi_get_crtc_new_encoder(crtc_state);
1784 if (IS_SKYLAKE(dev))
1785 return skl_ddi_pll_select(intel_crtc, crtc_state,
1787 else if (IS_BROXTON(dev))
1788 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1791 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1795 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1797 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1799 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1800 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1801 int type = intel_encoder->type;
1804 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1805 temp = TRANS_MSA_SYNC_CLK;
1806 switch (intel_crtc->config->pipe_bpp) {
1808 temp |= TRANS_MSA_6_BPC;
1811 temp |= TRANS_MSA_8_BPC;
1814 temp |= TRANS_MSA_10_BPC;
1817 temp |= TRANS_MSA_12_BPC;
1822 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1826 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1829 struct drm_device *dev = crtc->dev;
1830 struct drm_i915_private *dev_priv = dev->dev_private;
1831 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1833 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1835 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1837 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1838 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1841 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1844 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1845 struct drm_encoder *encoder = &intel_encoder->base;
1846 struct drm_device *dev = crtc->dev;
1847 struct drm_i915_private *dev_priv = dev->dev_private;
1848 enum pipe pipe = intel_crtc->pipe;
1849 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1850 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1851 int type = intel_encoder->type;
1854 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1855 temp = TRANS_DDI_FUNC_ENABLE;
1856 temp |= TRANS_DDI_SELECT_PORT(port);
1858 switch (intel_crtc->config->pipe_bpp) {
1860 temp |= TRANS_DDI_BPC_6;
1863 temp |= TRANS_DDI_BPC_8;
1866 temp |= TRANS_DDI_BPC_10;
1869 temp |= TRANS_DDI_BPC_12;
1875 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1876 temp |= TRANS_DDI_PVSYNC;
1877 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1878 temp |= TRANS_DDI_PHSYNC;
1880 if (cpu_transcoder == TRANSCODER_EDP) {
1883 /* On Haswell, can only use the always-on power well for
1884 * eDP when not using the panel fitter, and when not
1885 * using motion blur mitigation (which we don't
1887 if (IS_HASWELL(dev) &&
1888 (intel_crtc->config->pch_pfit.enabled ||
1889 intel_crtc->config->pch_pfit.force_thru))
1890 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1892 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1895 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1898 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1906 if (type == INTEL_OUTPUT_HDMI) {
1907 if (intel_crtc->config->has_hdmi_sink)
1908 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1910 temp |= TRANS_DDI_MODE_SELECT_DVI;
1912 } else if (type == INTEL_OUTPUT_ANALOG) {
1913 temp |= TRANS_DDI_MODE_SELECT_FDI;
1914 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1916 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1917 type == INTEL_OUTPUT_EDP) {
1918 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1920 if (intel_dp->is_mst) {
1921 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1923 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1925 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1926 } else if (type == INTEL_OUTPUT_DP_MST) {
1927 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1929 if (intel_dp->is_mst) {
1930 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1932 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1934 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1936 WARN(1, "Invalid encoder type %d for pipe %c\n",
1937 intel_encoder->type, pipe_name(pipe));
1940 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1943 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1944 enum transcoder cpu_transcoder)
1946 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1947 uint32_t val = I915_READ(reg);
1949 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1950 val |= TRANS_DDI_PORT_NONE;
1951 I915_WRITE(reg, val);
1954 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1956 struct drm_device *dev = intel_connector->base.dev;
1957 struct drm_i915_private *dev_priv = dev->dev_private;
1958 struct intel_encoder *intel_encoder = intel_connector->encoder;
1959 int type = intel_connector->base.connector_type;
1960 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1962 enum transcoder cpu_transcoder;
1963 enum intel_display_power_domain power_domain;
1966 power_domain = intel_display_port_power_domain(intel_encoder);
1967 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1970 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1974 cpu_transcoder = TRANSCODER_EDP;
1976 cpu_transcoder = (enum transcoder) pipe;
1978 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1980 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1981 case TRANS_DDI_MODE_SELECT_HDMI:
1982 case TRANS_DDI_MODE_SELECT_DVI:
1983 return (type == DRM_MODE_CONNECTOR_HDMIA);
1985 case TRANS_DDI_MODE_SELECT_DP_SST:
1986 if (type == DRM_MODE_CONNECTOR_eDP)
1988 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1989 case TRANS_DDI_MODE_SELECT_DP_MST:
1990 /* if the transcoder is in MST state then
1991 * connector isn't connected */
1994 case TRANS_DDI_MODE_SELECT_FDI:
1995 return (type == DRM_MODE_CONNECTOR_VGA);
2002 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2005 struct drm_device *dev = encoder->base.dev;
2006 struct drm_i915_private *dev_priv = dev->dev_private;
2007 enum port port = intel_ddi_get_encoder_port(encoder);
2008 enum intel_display_power_domain power_domain;
2012 power_domain = intel_display_port_power_domain(encoder);
2013 if (!intel_display_power_is_enabled(dev_priv, power_domain))
2016 tmp = I915_READ(DDI_BUF_CTL(port));
2018 if (!(tmp & DDI_BUF_CTL_ENABLE))
2021 if (port == PORT_A) {
2022 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2024 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2025 case TRANS_DDI_EDP_INPUT_A_ON:
2026 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2029 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2032 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2039 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2040 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2042 if ((tmp & TRANS_DDI_PORT_MASK)
2043 == TRANS_DDI_SELECT_PORT(port)) {
2044 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2053 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
2058 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2060 struct drm_crtc *crtc = &intel_crtc->base;
2061 struct drm_device *dev = crtc->dev;
2062 struct drm_i915_private *dev_priv = dev->dev_private;
2063 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2064 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2065 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2067 if (cpu_transcoder != TRANSCODER_EDP)
2068 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2069 TRANS_CLK_SEL_PORT(port));
2072 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2074 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2075 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2077 if (cpu_transcoder != TRANSCODER_EDP)
2078 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2079 TRANS_CLK_SEL_DISABLED);
2082 static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2083 enum port port, int type)
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 const struct ddi_buf_trans *ddi_translations;
2088 uint8_t dp_iboost, hdmi_iboost;
2092 /* VBT may override standard boost values */
2093 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2094 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2096 if (type == INTEL_OUTPUT_DISPLAYPORT) {
2100 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2101 iboost = ddi_translations[port].i_boost;
2103 } else if (type == INTEL_OUTPUT_EDP) {
2107 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2108 iboost = ddi_translations[port].i_boost;
2110 } else if (type == INTEL_OUTPUT_HDMI) {
2112 iboost = hdmi_iboost;
2114 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2115 iboost = ddi_translations[port].i_boost;
2121 /* Make sure that the requested I_boost is valid */
2122 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2123 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2127 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2128 reg &= ~BALANCE_LEG_MASK(port);
2129 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2132 reg |= iboost << BALANCE_LEG_SHIFT(port);
2134 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2136 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2139 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2140 enum port port, int type)
2142 struct drm_i915_private *dev_priv = dev->dev_private;
2143 const struct bxt_ddi_buf_trans *ddi_translations;
2147 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2148 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2149 ddi_translations = bxt_ddi_translations_edp;
2150 } else if (type == INTEL_OUTPUT_DISPLAYPORT
2151 || type == INTEL_OUTPUT_EDP) {
2152 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2153 ddi_translations = bxt_ddi_translations_dp;
2154 } else if (type == INTEL_OUTPUT_HDMI) {
2155 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2156 ddi_translations = bxt_ddi_translations_hdmi;
2158 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2163 /* Check if default value has to be used */
2164 if (level >= n_entries ||
2165 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2166 for (i = 0; i < n_entries; i++) {
2167 if (ddi_translations[i].default_index) {
2175 * While we write to the group register to program all lanes at once we
2176 * can read only lane registers and we pick lanes 0/1 for that.
2178 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2179 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2180 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2182 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2183 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2184 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2185 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2186 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2188 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2189 val &= ~SCALE_DCOMP_METHOD;
2190 if (ddi_translations[level].enable)
2191 val |= SCALE_DCOMP_METHOD;
2193 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2194 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2196 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2198 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2199 val &= ~DE_EMPHASIS;
2200 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2201 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2203 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2204 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2205 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2208 static uint32_t translate_signal_level(int signal_levels)
2212 switch (signal_levels) {
2214 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2254 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2256 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2257 struct drm_device *dev = dport->base.base.dev;
2258 struct intel_encoder *encoder = &dport->base;
2259 uint8_t train_set = intel_dp->train_set[0];
2260 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2261 DP_TRAIN_PRE_EMPHASIS_MASK);
2262 enum port port = dport->port;
2265 level = translate_signal_level(signal_levels);
2267 if (IS_SKYLAKE(dev))
2268 skl_ddi_set_iboost(dev, level, port, encoder->type);
2269 else if (IS_BROXTON(dev))
2270 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2272 return DDI_BUF_TRANS_SELECT(level);
2275 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
2277 struct drm_encoder *encoder = &intel_encoder->base;
2278 struct drm_device *dev = encoder->dev;
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
2281 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2282 int type = intel_encoder->type;
2285 if (type == INTEL_OUTPUT_EDP) {
2286 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2287 intel_edp_panel_on(intel_dp);
2290 if (IS_SKYLAKE(dev)) {
2291 uint32_t dpll = crtc->config->ddi_pll_sel;
2295 * DPLL0 is used for eDP and is the only "private" DPLL (as
2296 * opposed to shared) on SKL
2298 if (type == INTEL_OUTPUT_EDP) {
2299 WARN_ON(dpll != SKL_DPLL0);
2301 val = I915_READ(DPLL_CTRL1);
2303 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2304 DPLL_CTRL1_SSC(dpll) |
2305 DPLL_CTRL1_LINK_RATE_MASK(dpll));
2306 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
2308 I915_WRITE(DPLL_CTRL1, val);
2309 POSTING_READ(DPLL_CTRL1);
2312 /* DDI -> PLL mapping */
2313 val = I915_READ(DPLL_CTRL2);
2315 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2316 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2317 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2318 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2320 I915_WRITE(DPLL_CTRL2, val);
2322 } else if (INTEL_INFO(dev)->gen < 9) {
2323 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2324 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
2327 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2328 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2330 intel_dp_set_link_params(intel_dp, crtc->config);
2332 intel_ddi_init_dp_buf_reg(intel_encoder);
2334 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2335 intel_dp_start_link_train(intel_dp);
2336 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
2337 intel_dp_stop_link_train(intel_dp);
2338 } else if (type == INTEL_OUTPUT_HDMI) {
2339 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2341 if (IS_BROXTON(dev)) {
2342 hdmi_level = dev_priv->vbt.
2343 ddi_port_info[port].hdmi_level_shift;
2344 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2347 intel_hdmi->set_infoframes(encoder,
2348 crtc->config->has_hdmi_sink,
2349 &crtc->config->base.adjusted_mode);
2353 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
2355 struct drm_encoder *encoder = &intel_encoder->base;
2356 struct drm_device *dev = encoder->dev;
2357 struct drm_i915_private *dev_priv = dev->dev_private;
2358 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2359 int type = intel_encoder->type;
2363 val = I915_READ(DDI_BUF_CTL(port));
2364 if (val & DDI_BUF_CTL_ENABLE) {
2365 val &= ~DDI_BUF_CTL_ENABLE;
2366 I915_WRITE(DDI_BUF_CTL(port), val);
2370 val = I915_READ(DP_TP_CTL(port));
2371 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2372 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2373 I915_WRITE(DP_TP_CTL(port), val);
2376 intel_wait_ddi_buf_idle(dev_priv, port);
2378 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2379 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2380 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2381 intel_edp_panel_vdd_on(intel_dp);
2382 intel_edp_panel_off(intel_dp);
2385 if (IS_SKYLAKE(dev))
2386 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2387 DPLL_CTRL2_DDI_CLK_OFF(port)));
2388 else if (INTEL_INFO(dev)->gen < 9)
2389 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2392 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
2394 struct drm_encoder *encoder = &intel_encoder->base;
2395 struct drm_crtc *crtc = encoder->crtc;
2396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2397 struct drm_device *dev = encoder->dev;
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2399 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2400 int type = intel_encoder->type;
2402 if (type == INTEL_OUTPUT_HDMI) {
2403 struct intel_digital_port *intel_dig_port =
2404 enc_to_dig_port(encoder);
2406 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2407 * are ignored so nothing special needs to be done besides
2408 * enabling the port.
2410 I915_WRITE(DDI_BUF_CTL(port),
2411 intel_dig_port->saved_port_bits |
2412 DDI_BUF_CTL_ENABLE);
2413 } else if (type == INTEL_OUTPUT_EDP) {
2414 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2416 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
2417 intel_dp_stop_link_train(intel_dp);
2419 intel_edp_backlight_on(intel_dp);
2420 intel_psr_enable(intel_dp);
2421 intel_edp_drrs_enable(intel_dp);
2424 if (intel_crtc->config->has_audio) {
2425 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
2426 intel_audio_codec_enable(intel_encoder);
2430 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
2432 struct drm_encoder *encoder = &intel_encoder->base;
2433 struct drm_crtc *crtc = encoder->crtc;
2434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2435 int type = intel_encoder->type;
2436 struct drm_device *dev = encoder->dev;
2437 struct drm_i915_private *dev_priv = dev->dev_private;
2439 if (intel_crtc->config->has_audio) {
2440 intel_audio_codec_disable(intel_encoder);
2441 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2444 if (type == INTEL_OUTPUT_EDP) {
2445 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2447 intel_edp_drrs_disable(intel_dp);
2448 intel_psr_disable(intel_dp);
2449 intel_edp_backlight_off(intel_dp);
2453 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
2454 struct intel_shared_dpll *pll)
2456 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
2457 POSTING_READ(WRPLL_CTL(pll->id));
2461 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
2462 struct intel_shared_dpll *pll)
2464 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
2465 POSTING_READ(SPLL_CTL);
2469 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
2470 struct intel_shared_dpll *pll)
2474 val = I915_READ(WRPLL_CTL(pll->id));
2475 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2476 POSTING_READ(WRPLL_CTL(pll->id));
2479 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
2480 struct intel_shared_dpll *pll)
2484 val = I915_READ(SPLL_CTL);
2485 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
2486 POSTING_READ(SPLL_CTL);
2489 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
2490 struct intel_shared_dpll *pll,
2491 struct intel_dpll_hw_state *hw_state)
2495 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2498 val = I915_READ(WRPLL_CTL(pll->id));
2499 hw_state->wrpll = val;
2501 return val & WRPLL_PLL_ENABLE;
2504 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
2505 struct intel_shared_dpll *pll,
2506 struct intel_dpll_hw_state *hw_state)
2510 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2513 val = I915_READ(SPLL_CTL);
2514 hw_state->spll = val;
2516 return val & SPLL_PLL_ENABLE;
2520 static const char * const hsw_ddi_pll_names[] = {
2526 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
2530 dev_priv->num_shared_dpll = 3;
2532 for (i = 0; i < 2; i++) {
2533 dev_priv->shared_dplls[i].id = i;
2534 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2535 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
2536 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
2537 dev_priv->shared_dplls[i].get_hw_state =
2538 hsw_ddi_wrpll_get_hw_state;
2541 /* SPLL is special, but needs to be initialized anyway.. */
2542 dev_priv->shared_dplls[i].id = i;
2543 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2544 dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
2545 dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
2546 dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
2550 static const char * const skl_ddi_pll_names[] = {
2556 struct skl_dpll_regs {
2557 u32 ctl, cfgcr1, cfgcr2;
2560 /* this array is indexed by the *shared* pll id */
2561 static const struct skl_dpll_regs skl_dpll_regs[3] = {
2565 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2566 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
2571 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2572 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
2577 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2578 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
2582 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2583 struct intel_shared_dpll *pll)
2587 const struct skl_dpll_regs *regs = skl_dpll_regs;
2589 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2592 val = I915_READ(DPLL_CTRL1);
2594 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
2595 DPLL_CTRL1_LINK_RATE_MASK(dpll));
2596 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2598 I915_WRITE(DPLL_CTRL1, val);
2599 POSTING_READ(DPLL_CTRL1);
2601 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2602 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2603 POSTING_READ(regs[pll->id].cfgcr1);
2604 POSTING_READ(regs[pll->id].cfgcr2);
2606 /* the enable bit is always bit 31 */
2607 I915_WRITE(regs[pll->id].ctl,
2608 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2610 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2611 DRM_ERROR("DPLL %d not locked\n", dpll);
2614 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2615 struct intel_shared_dpll *pll)
2617 const struct skl_dpll_regs *regs = skl_dpll_regs;
2619 /* the enable bit is always bit 31 */
2620 I915_WRITE(regs[pll->id].ctl,
2621 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2622 POSTING_READ(regs[pll->id].ctl);
2625 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2626 struct intel_shared_dpll *pll,
2627 struct intel_dpll_hw_state *hw_state)
2631 const struct skl_dpll_regs *regs = skl_dpll_regs;
2633 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2636 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2639 val = I915_READ(regs[pll->id].ctl);
2640 if (!(val & LCPLL_PLL_ENABLE))
2643 val = I915_READ(DPLL_CTRL1);
2644 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2646 /* avoid reading back stale values if HDMI mode is not enabled */
2647 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2648 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2649 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2655 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2659 dev_priv->num_shared_dpll = 3;
2661 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2662 dev_priv->shared_dplls[i].id = i;
2663 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2664 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2665 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2666 dev_priv->shared_dplls[i].get_hw_state =
2667 skl_ddi_pll_get_hw_state;
2671 static void broxton_phy_init(struct drm_i915_private *dev_priv,
2677 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2678 val |= GT_DISPLAY_POWER_ON(phy);
2679 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2681 /* Considering 10ms timeout until BSpec is updated */
2682 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2683 DRM_ERROR("timeout during PHY%d power on\n", phy);
2685 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2686 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2689 for (lane = 0; lane < 4; lane++) {
2690 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2692 * Note that on CHV this flag is called UPAR, but has
2693 * the same function.
2695 val &= ~LATENCY_OPTIM;
2697 val |= LATENCY_OPTIM;
2699 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2703 /* Program PLL Rcomp code offset */
2704 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2705 val &= ~IREF0RC_OFFSET_MASK;
2706 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2707 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2709 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2710 val &= ~IREF1RC_OFFSET_MASK;
2711 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2712 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2714 /* Program power gating */
2715 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2716 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2718 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2720 if (phy == DPIO_PHY0) {
2721 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2722 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2723 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2726 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2727 val &= ~OCL2_LDOFUSE_PWR_DIS;
2729 * On PHY1 disable power on the second channel, since no port is
2730 * connected there. On PHY0 both channels have a port, so leave it
2732 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2733 * power down the second channel on PHY0 as well.
2735 if (phy == DPIO_PHY1)
2736 val |= OCL2_LDOFUSE_PWR_DIS;
2737 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2739 if (phy == DPIO_PHY0) {
2742 * PHY0 isn't connected to an RCOMP resistor so copy over
2743 * the corresponding calibrated value from PHY1, and disable
2744 * the automatic calibration on PHY0.
2746 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2748 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2750 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2751 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2752 grc_code = val << GRC_CODE_FAST_SHIFT |
2753 val << GRC_CODE_SLOW_SHIFT |
2755 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2757 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2758 val |= GRC_DIS | GRC_RDY_OVRD;
2759 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2762 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2763 val |= COMMON_RESET_DIS;
2764 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2767 void broxton_ddi_phy_init(struct drm_device *dev)
2769 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2770 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2771 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2774 static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2779 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2780 val &= ~COMMON_RESET_DIS;
2781 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2784 void broxton_ddi_phy_uninit(struct drm_device *dev)
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2788 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2789 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2791 /* FIXME: do this in broxton_phy_uninit per phy */
2792 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2795 static const char * const bxt_ddi_pll_names[] = {
2801 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2802 struct intel_shared_dpll *pll)
2805 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2807 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2808 temp &= ~PORT_PLL_REF_SEL;
2809 /* Non-SSC reference */
2810 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2812 /* Disable 10 bit clock */
2813 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2814 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2815 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2818 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2819 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2820 temp |= pll->config.hw_state.ebb0;
2821 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2823 /* Write M2 integer */
2824 temp = I915_READ(BXT_PORT_PLL(port, 0));
2825 temp &= ~PORT_PLL_M2_MASK;
2826 temp |= pll->config.hw_state.pll0;
2827 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2830 temp = I915_READ(BXT_PORT_PLL(port, 1));
2831 temp &= ~PORT_PLL_N_MASK;
2832 temp |= pll->config.hw_state.pll1;
2833 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2835 /* Write M2 fraction */
2836 temp = I915_READ(BXT_PORT_PLL(port, 2));
2837 temp &= ~PORT_PLL_M2_FRAC_MASK;
2838 temp |= pll->config.hw_state.pll2;
2839 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2841 /* Write M2 fraction enable */
2842 temp = I915_READ(BXT_PORT_PLL(port, 3));
2843 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2844 temp |= pll->config.hw_state.pll3;
2845 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2848 temp = I915_READ(BXT_PORT_PLL(port, 6));
2849 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2850 temp &= ~PORT_PLL_INT_COEFF_MASK;
2851 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2852 temp |= pll->config.hw_state.pll6;
2853 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2855 /* Write calibration val */
2856 temp = I915_READ(BXT_PORT_PLL(port, 8));
2857 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2858 temp |= pll->config.hw_state.pll8;
2859 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2861 temp = I915_READ(BXT_PORT_PLL(port, 9));
2862 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2863 temp |= pll->config.hw_state.pll9;
2864 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2866 temp = I915_READ(BXT_PORT_PLL(port, 10));
2867 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2868 temp &= ~PORT_PLL_DCO_AMP_MASK;
2869 temp |= pll->config.hw_state.pll10;
2870 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
2872 /* Recalibrate with new settings */
2873 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2874 temp |= PORT_PLL_RECALIBRATE;
2875 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2876 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2877 temp |= pll->config.hw_state.ebb4;
2878 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2881 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2882 temp |= PORT_PLL_ENABLE;
2883 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2884 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2886 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2887 PORT_PLL_LOCK), 200))
2888 DRM_ERROR("PLL %d not locked\n", port);
2891 * While we write to the group register to program all lanes at once we
2892 * can read only lane registers and we pick lanes 0/1 for that.
2894 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2895 temp &= ~LANE_STAGGER_MASK;
2896 temp &= ~LANESTAGGER_STRAP_OVRD;
2897 temp |= pll->config.hw_state.pcsdw12;
2898 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2901 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2902 struct intel_shared_dpll *pll)
2904 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2907 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2908 temp &= ~PORT_PLL_ENABLE;
2909 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2910 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2913 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2914 struct intel_shared_dpll *pll,
2915 struct intel_dpll_hw_state *hw_state)
2917 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2920 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2923 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2924 if (!(val & PORT_PLL_ENABLE))
2927 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2928 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2930 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2931 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2933 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2934 hw_state->pll0 &= PORT_PLL_M2_MASK;
2936 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2937 hw_state->pll1 &= PORT_PLL_N_MASK;
2939 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2940 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2942 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2943 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2945 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2946 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2947 PORT_PLL_INT_COEFF_MASK |
2948 PORT_PLL_GAIN_CTL_MASK;
2950 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
2951 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2953 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2954 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2956 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
2957 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2958 PORT_PLL_DCO_AMP_MASK;
2961 * While we write to the group register to program all lanes at once we
2962 * can read only lane registers. We configure all lanes the same way, so
2963 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2965 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2966 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
2967 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2969 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2970 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
2975 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2979 dev_priv->num_shared_dpll = 3;
2981 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2982 dev_priv->shared_dplls[i].id = i;
2983 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2984 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2985 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2986 dev_priv->shared_dplls[i].get_hw_state =
2987 bxt_ddi_pll_get_hw_state;
2991 void intel_ddi_pll_init(struct drm_device *dev)
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 uint32_t val = I915_READ(LCPLL_CTL);
2996 if (IS_SKYLAKE(dev))
2997 skl_shared_dplls_init(dev_priv);
2998 else if (IS_BROXTON(dev))
2999 bxt_shared_dplls_init(dev_priv);
3001 hsw_shared_dplls_init(dev_priv);
3003 if (IS_SKYLAKE(dev)) {
3006 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
3007 dev_priv->skl_boot_cdclk = cdclk_freq;
3008 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
3009 DRM_ERROR("LCPLL1 is disabled\n");
3011 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
3012 } else if (IS_BROXTON(dev)) {
3013 broxton_init_cdclk(dev);
3014 broxton_ddi_phy_init(dev);
3017 * The LCPLL register should be turned on by the BIOS. For now
3018 * let's just check its state and print errors in case
3019 * something is wrong. Don't even try to turn it on.
3022 if (val & LCPLL_CD_SOURCE_FCLK)
3023 DRM_ERROR("CDCLK source is not LCPLL\n");
3025 if (val & LCPLL_PLL_DISABLE)
3026 DRM_ERROR("LCPLL is disabled\n");
3030 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
3032 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3033 struct intel_dp *intel_dp = &intel_dig_port->dp;
3034 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
3035 enum port port = intel_dig_port->port;
3039 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3040 val = I915_READ(DDI_BUF_CTL(port));
3041 if (val & DDI_BUF_CTL_ENABLE) {
3042 val &= ~DDI_BUF_CTL_ENABLE;
3043 I915_WRITE(DDI_BUF_CTL(port), val);
3047 val = I915_READ(DP_TP_CTL(port));
3048 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3049 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3050 I915_WRITE(DP_TP_CTL(port), val);
3051 POSTING_READ(DP_TP_CTL(port));
3054 intel_wait_ddi_buf_idle(dev_priv, port);
3057 val = DP_TP_CTL_ENABLE |
3058 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3059 if (intel_dp->is_mst)
3060 val |= DP_TP_CTL_MODE_MST;
3062 val |= DP_TP_CTL_MODE_SST;
3063 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3064 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3066 I915_WRITE(DP_TP_CTL(port), val);
3067 POSTING_READ(DP_TP_CTL(port));
3069 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3070 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3071 POSTING_READ(DDI_BUF_CTL(port));
3076 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3078 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3079 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3082 intel_ddi_post_disable(intel_encoder);
3084 val = I915_READ(FDI_RX_CTL(PIPE_A));
3085 val &= ~FDI_RX_ENABLE;
3086 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3088 val = I915_READ(FDI_RX_MISC(PIPE_A));
3089 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3090 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3091 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3093 val = I915_READ(FDI_RX_CTL(PIPE_A));
3095 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3097 val = I915_READ(FDI_RX_CTL(PIPE_A));
3098 val &= ~FDI_RX_PLL_ENABLE;
3099 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3102 void intel_ddi_get_config(struct intel_encoder *encoder,
3103 struct intel_crtc_state *pipe_config)
3105 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3106 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
3107 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3108 struct intel_hdmi *intel_hdmi;
3109 u32 temp, flags = 0;
3111 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3112 if (temp & TRANS_DDI_PHSYNC)
3113 flags |= DRM_MODE_FLAG_PHSYNC;
3115 flags |= DRM_MODE_FLAG_NHSYNC;
3116 if (temp & TRANS_DDI_PVSYNC)
3117 flags |= DRM_MODE_FLAG_PVSYNC;
3119 flags |= DRM_MODE_FLAG_NVSYNC;
3121 pipe_config->base.adjusted_mode.flags |= flags;
3123 switch (temp & TRANS_DDI_BPC_MASK) {
3124 case TRANS_DDI_BPC_6:
3125 pipe_config->pipe_bpp = 18;
3127 case TRANS_DDI_BPC_8:
3128 pipe_config->pipe_bpp = 24;
3130 case TRANS_DDI_BPC_10:
3131 pipe_config->pipe_bpp = 30;
3133 case TRANS_DDI_BPC_12:
3134 pipe_config->pipe_bpp = 36;
3140 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3141 case TRANS_DDI_MODE_SELECT_HDMI:
3142 pipe_config->has_hdmi_sink = true;
3143 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3145 if (intel_hdmi->infoframe_enabled(&encoder->base))
3146 pipe_config->has_infoframe = true;
3148 case TRANS_DDI_MODE_SELECT_DVI:
3149 case TRANS_DDI_MODE_SELECT_FDI:
3151 case TRANS_DDI_MODE_SELECT_DP_SST:
3152 case TRANS_DDI_MODE_SELECT_DP_MST:
3153 pipe_config->has_dp_encoder = true;
3154 pipe_config->lane_count =
3155 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3156 intel_dp_get_m_n(intel_crtc, pipe_config);
3162 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3163 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
3164 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3165 pipe_config->has_audio = true;
3168 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3169 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3171 * This is a big fat ugly hack.
3173 * Some machines in UEFI boot mode provide us a VBT that has 18
3174 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3175 * unknown we fail to light up. Yet the same BIOS boots up with
3176 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3177 * max, not what it tells us to use.
3179 * Note: This will still be broken if the eDP panel is not lit
3180 * up by the BIOS, and thus we can't get the mode at module
3183 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3184 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3185 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3188 intel_ddi_clock_get(encoder, pipe_config);
3191 static void intel_ddi_destroy(struct drm_encoder *encoder)
3193 /* HDMI has nothing special to destroy, so we can go with this. */
3194 intel_dp_encoder_destroy(encoder);
3197 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3198 struct intel_crtc_state *pipe_config)
3200 int type = encoder->type;
3201 int port = intel_ddi_get_encoder_port(encoder);
3203 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
3206 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3208 if (type == INTEL_OUTPUT_HDMI)
3209 return intel_hdmi_compute_config(encoder, pipe_config);
3211 return intel_dp_compute_config(encoder, pipe_config);
3214 static const struct drm_encoder_funcs intel_ddi_funcs = {
3215 .destroy = intel_ddi_destroy,
3218 static struct intel_connector *
3219 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3221 struct intel_connector *connector;
3222 enum port port = intel_dig_port->port;
3224 connector = intel_connector_alloc();
3228 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3229 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3237 static struct intel_connector *
3238 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3240 struct intel_connector *connector;
3241 enum port port = intel_dig_port->port;
3243 connector = intel_connector_alloc();
3247 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3248 intel_hdmi_init_connector(intel_dig_port, connector);
3253 void intel_ddi_init(struct drm_device *dev, enum port port)
3255 struct drm_i915_private *dev_priv = dev->dev_private;
3256 struct intel_digital_port *intel_dig_port;
3257 struct intel_encoder *intel_encoder;
3258 struct drm_encoder *encoder;
3259 bool init_hdmi, init_dp;
3261 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3262 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3263 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3264 if (!init_dp && !init_hdmi) {
3265 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3270 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3271 if (!intel_dig_port)
3274 intel_encoder = &intel_dig_port->base;
3275 encoder = &intel_encoder->base;
3277 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3278 DRM_MODE_ENCODER_TMDS);
3280 intel_encoder->compute_config = intel_ddi_compute_config;
3281 intel_encoder->enable = intel_enable_ddi;
3282 intel_encoder->pre_enable = intel_ddi_pre_enable;
3283 intel_encoder->disable = intel_disable_ddi;
3284 intel_encoder->post_disable = intel_ddi_post_disable;
3285 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3286 intel_encoder->get_config = intel_ddi_get_config;
3288 intel_dig_port->port = port;
3289 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3290 (DDI_BUF_PORT_REVERSAL |
3293 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
3294 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3295 intel_encoder->cloneable = 0;
3298 if (!intel_ddi_init_dp_connector(intel_dig_port))
3301 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3303 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3304 * interrupts to check the external panel connection.
3306 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)
3308 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3310 dev_priv->hotplug.irq_port[port] = intel_dig_port;
3313 /* In theory we don't need the encoder->type check, but leave it just in
3314 * case we have some really bad VBTs... */
3315 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3316 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3323 drm_encoder_cleanup(encoder);
3324 kfree(intel_dig_port);