drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34 };
  35
  36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  37  * them for both DP and FDI transports, allowing those ports to
  38  * automatically adapt to HDMI connections as well
  39  */
  40 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  41         { 0x00FFFFFF, 0x0006000E },
  42         { 0x00D75FFF, 0x0005000A },
  43         { 0x00C30FFF, 0x00040006 },
  44         { 0x80AAAFFF, 0x000B0000 },
  45         { 0x00FFFFFF, 0x0005000A },
  46         { 0x00D75FFF, 0x000C0004 },
  47         { 0x80C30FFF, 0x000B0000 },
  48         { 0x00FFFFFF, 0x00040006 },
  49         { 0x80D75FFF, 0x000B0000 },
  50 };
  51
  52 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  53         { 0x00FFFFFF, 0x0007000E },
  54         { 0x00D75FFF, 0x000F000A },
  55         { 0x00C30FFF, 0x00060006 },
  56         { 0x00AAAFFF, 0x001E0000 },
  57         { 0x00FFFFFF, 0x000F000A },
  58         { 0x00D75FFF, 0x00160004 },
  59         { 0x00C30FFF, 0x001E0000 },
  60         { 0x00FFFFFF, 0x00060006 },
  61         { 0x00D75FFF, 0x001E0000 },
  62 };
  63
  64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  65                                         /* Idx  NT mV d T mV d  db      */
  66         { 0x00FFFFFF, 0x0006000E },     /* 0:   400     400     0       */
  67         { 0x00E79FFF, 0x000E000C },     /* 1:   400     500     2       */
  68         { 0x00D75FFF, 0x0005000A },     /* 2:   400     600     3.5     */
  69         { 0x00FFFFFF, 0x0005000A },     /* 3:   600     600     0       */
  70         { 0x00E79FFF, 0x001D0007 },     /* 4:   600     750     2       */
  71         { 0x00D75FFF, 0x000C0004 },     /* 5:   600     900     3.5     */
  72         { 0x00FFFFFF, 0x00040006 },     /* 6:   800     800     0       */
  73         { 0x80E79FFF, 0x00030002 },     /* 7:   800     1000    2       */
  74         { 0x00FFFFFF, 0x00140005 },     /* 8:   850     850     0       */
  75         { 0x00FFFFFF, 0x000C0004 },     /* 9:   900     900     0       */
  76         { 0x00FFFFFF, 0x001C0003 },     /* 10:  950     950     0       */
  77         { 0x80FFFFFF, 0x00030002 },     /* 11:  1000    1000    0       */
  78 };
  79
  80 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  81         { 0x00FFFFFF, 0x00000012 },
  82         { 0x00EBAFFF, 0x00020011 },
  83         { 0x00C71FFF, 0x0006000F },
  84         { 0x00AAAFFF, 0x000E000A },
  85         { 0x00FFFFFF, 0x00020011 },
  86         { 0x00DB6FFF, 0x0005000F },
  87         { 0x00BEEFFF, 0x000A000C },
  88         { 0x00FFFFFF, 0x0005000F },
  89         { 0x00DB6FFF, 0x000A000C },
  90 };
  91
  92 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
  93         { 0x00FFFFFF, 0x0007000E },
  94         { 0x00D75FFF, 0x000E000A },
  95         { 0x00BEFFFF, 0x00140006 },
  96         { 0x80B2CFFF, 0x001B0002 },
  97         { 0x00FFFFFF, 0x000E000A },
  98         { 0x00D75FFF, 0x00180004 },
  99         { 0x80CB2FFF, 0x001B0002 },
 100         { 0x00F7DFFF, 0x00180004 },
 101         { 0x80D75FFF, 0x001B0002 },
 102 };
 103
 104 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 105         { 0x00FFFFFF, 0x0001000E },
 106         { 0x00D75FFF, 0x0004000A },
 107         { 0x00C30FFF, 0x00070006 },
 108         { 0x00AAAFFF, 0x000C0000 },
 109         { 0x00FFFFFF, 0x0004000A },
 110         { 0x00D75FFF, 0x00090004 },
 111         { 0x00C30FFF, 0x000C0000 },
 112         { 0x00FFFFFF, 0x00070006 },
 113         { 0x00D75FFF, 0x000C0000 },
 114 };
 115
 116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 117                                         /* Idx  NT mV d T mV df db      */
 118         { 0x00FFFFFF, 0x0007000E },     /* 0:   400     400     0       */
 119         { 0x00D75FFF, 0x000E000A },     /* 1:   400     600     3.5     */
 120         { 0x00BEFFFF, 0x00140006 },     /* 2:   400     800     6       */
 121         { 0x00FFFFFF, 0x0009000D },     /* 3:   450     450     0       */
 122         { 0x00FFFFFF, 0x000E000A },     /* 4:   600     600     0       */
 123         { 0x00D7FFFF, 0x00140006 },     /* 5:   600     800     2.5     */
 124         { 0x80CB2FFF, 0x001B0002 },     /* 6:   600     1000    4.5     */
 125         { 0x00FFFFFF, 0x00140006 },     /* 7:   800     800     0       */
 126         { 0x80E79FFF, 0x001B0002 },     /* 8:   800     1000    2       */
 127         { 0x80FFFFFF, 0x001B0002 },     /* 9:   1000    1000    0       */
 128 };
 129
 130 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 131 {
 132         struct drm_encoder *encoder = &intel_encoder->base;
 133         int type = intel_encoder->type;
 134
 135         if (type == INTEL_OUTPUT_DP_MST) {
 136                 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
 137                 return intel_dig_port->port;
 138         } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 139             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 140                 struct intel_digital_port *intel_dig_port =
 141                         enc_to_dig_port(encoder);
 142                 return intel_dig_port->port;
 143
 144         } else if (type == INTEL_OUTPUT_ANALOG) {
 145                 return PORT_E;
 146
 147         } else {
 148                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
 149                 BUG();
 150         }
 151 }
 152
 153 /*
 154  * Starting with Haswell, DDI port buffers must be programmed with correct
 155  * values in advance. The buffer values are different for FDI and DP modes,
 156  * but the HDMI/DVI fields are shared among those. So we program the DDI
 157  * in either FDI or DP modes only, as HDMI connections will work with both
 158  * of those
 159  */
 160 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 161 {
 162         struct drm_i915_private *dev_priv = dev->dev_private;
 163         u32 reg;
 164         int i, n_hdmi_entries, hdmi_800mV_0dB;
 165         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 166         const struct ddi_buf_trans *ddi_translations_fdi;
 167         const struct ddi_buf_trans *ddi_translations_dp;
 168         const struct ddi_buf_trans *ddi_translations_edp;
 169         const struct ddi_buf_trans *ddi_translations_hdmi;
 170         const struct ddi_buf_trans *ddi_translations;
 171
 172         if (IS_BROADWELL(dev)) {
 173                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 174                 ddi_translations_dp = bdw_ddi_translations_dp;
 175                 ddi_translations_edp = bdw_ddi_translations_edp;
 176                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 177                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 178                 hdmi_800mV_0dB = 7;
 179         } else if (IS_HASWELL(dev)) {
 180                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 181                 ddi_translations_dp = hsw_ddi_translations_dp;
 182                 ddi_translations_edp = hsw_ddi_translations_dp;
 183                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 184                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 185                 hdmi_800mV_0dB = 6;
 186         } else {
 187                 WARN(1, "ddi translation table missing\n");
 188                 ddi_translations_edp = bdw_ddi_translations_dp;
 189                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 190                 ddi_translations_dp = bdw_ddi_translations_dp;
 191                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 192                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 193                 hdmi_800mV_0dB = 7;
 194         }
 195
 196         switch (port) {
 197         case PORT_A:
 198                 ddi_translations = ddi_translations_edp;
 199                 break;
 200         case PORT_B:
 201         case PORT_C:
 202                 ddi_translations = ddi_translations_dp;
 203                 break;
 204         case PORT_D:
 205                 if (intel_dp_is_edp(dev, PORT_D))
 206                         ddi_translations = ddi_translations_edp;
 207                 else
 208                         ddi_translations = ddi_translations_dp;
 209                 break;
 210         case PORT_E:
 211                 ddi_translations = ddi_translations_fdi;
 212                 break;
 213         default:
 214                 BUG();
 215         }
 216
 217         for (i = 0, reg = DDI_BUF_TRANS(port);
 218              i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 219                 I915_WRITE(reg, ddi_translations[i].trans1);
 220                 reg += 4;
 221                 I915_WRITE(reg, ddi_translations[i].trans2);
 222                 reg += 4;
 223         }
 224
 225         /* Choose a good default if VBT is badly populated */
 226         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 227             hdmi_level >= n_hdmi_entries)
 228                 hdmi_level = hdmi_800mV_0dB;
 229
 230         /* Entry 9 is for HDMI: */
 231         I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
 232         reg += 4;
 233         I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
 234         reg += 4;
 235 }
 236
 237 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 238  * mode and port E for FDI.
 239  */
 240 void intel_prepare_ddi(struct drm_device *dev)
 241 {
 242         int port;
 243
 244         if (!HAS_DDI(dev))
 245                 return;
 246
 247         for (port = PORT_A; port <= PORT_E; port++)
 248                 intel_prepare_ddi_buffers(dev, port);
 249 }
 250
 251 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 252                                     enum port port)
 253 {
 254         uint32_t reg = DDI_BUF_CTL(port);
 255         int i;
 256
 257         for (i = 0; i < 8; i++) {
 258                 udelay(1);
 259                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 260                         return;
 261         }
 262         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 263 }
 264
 265 /* Starting with Haswell, different DDI ports can work in FDI mode for
 266  * connection to the PCH-located connectors. For this, it is necessary to train
 267  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 268  *
 269  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 270  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 271  * DDI A (which is used for eDP)
 272  */
 273
 274 void hsw_fdi_link_train(struct drm_crtc *crtc)
 275 {
 276         struct drm_device *dev = crtc->dev;
 277         struct drm_i915_private *dev_priv = dev->dev_private;
 278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 279         u32 temp, i, rx_ctl_val;
 280
 281         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 282          * mode set "sequence for CRT port" document:
 283          * - TP1 to TP2 time with the default value
 284          * - FDI delay to 90h
 285          *
 286          * WaFDIAutoLinkSetTimingOverrride:hsw
 287          */
 288         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 289                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 290                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 291
 292         /* Enable the PCH Receiver FDI PLL */
 293         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 294                      FDI_RX_PLL_ENABLE |
 295                      FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
 296         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 297         POSTING_READ(_FDI_RXA_CTL);
 298         udelay(220);
 299
 300         /* Switch from Rawclk to PCDclk */
 301         rx_ctl_val |= FDI_PCDCLK;
 302         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 303
 304         /* Configure Port Clock Select */
 305         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
 306         WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
 307
 308         /* Start the training iterating through available voltages and emphasis,
 309          * testing each value twice. */
 310         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 311                 /* Configure DP_TP_CTL with auto-training */
 312                 I915_WRITE(DP_TP_CTL(PORT_E),
 313                                         DP_TP_CTL_FDI_AUTOTRAIN |
 314                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 315                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 316                                         DP_TP_CTL_ENABLE);
 317
 318                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 319                  * DDI E does not support port reversal, the functionality is
 320                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 321                  * port reversal bit */
 322                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 323                            DDI_BUF_CTL_ENABLE |
 324                            ((intel_crtc->config.fdi_lanes - 1) << 1) |
 325                            DDI_BUF_TRANS_SELECT(i / 2));
 326                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 327
 328                 udelay(600);
 329
 330                 /* Program PCH FDI Receiver TU */
 331                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 332
 333                 /* Enable PCH FDI Receiver with auto-training */
 334                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 335                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 336                 POSTING_READ(_FDI_RXA_CTL);
 337
 338                 /* Wait for FDI receiver lane calibration */
 339                 udelay(30);
 340
 341                 /* Unset FDI_RX_MISC pwrdn lanes */
 342                 temp = I915_READ(_FDI_RXA_MISC);
 343                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 344                 I915_WRITE(_FDI_RXA_MISC, temp);
 345                 POSTING_READ(_FDI_RXA_MISC);
 346
 347                 /* Wait for FDI auto training time */
 348                 udelay(5);
 349
 350                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 351                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 352                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 353
 354                         /* Enable normal pixel sending for FDI */
 355                         I915_WRITE(DP_TP_CTL(PORT_E),
 356                                    DP_TP_CTL_FDI_AUTOTRAIN |
 357                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 358                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 359                                    DP_TP_CTL_ENABLE);
 360
 361                         return;
 362                 }
 363
 364                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 365                 temp &= ~DDI_BUF_CTL_ENABLE;
 366                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 367                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 368
 369                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 370                 temp = I915_READ(DP_TP_CTL(PORT_E));
 371                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 372                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 373                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 374                 POSTING_READ(DP_TP_CTL(PORT_E));
 375
 376                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 377
 378                 rx_ctl_val &= ~FDI_RX_ENABLE;
 379                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 380                 POSTING_READ(_FDI_RXA_CTL);
 381
 382                 /* Reset FDI_RX_MISC pwrdn lanes */
 383                 temp = I915_READ(_FDI_RXA_MISC);
 384                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 385                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 386                 I915_WRITE(_FDI_RXA_MISC, temp);
 387                 POSTING_READ(_FDI_RXA_MISC);
 388         }
 389
 390         DRM_ERROR("FDI link training failed!\n");
 391 }
 392
 393 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 394 {
 395         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 396         struct intel_digital_port *intel_dig_port =
 397                 enc_to_dig_port(&encoder->base);
 398
 399         intel_dp->DP = intel_dig_port->saved_port_bits |
 400                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 401         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 402
 403 }
 404
 405 static struct intel_encoder *
 406 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 407 {
 408         struct drm_device *dev = crtc->dev;
 409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 410         struct intel_encoder *intel_encoder, *ret = NULL;
 411         int num_encoders = 0;
 412
 413         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 414                 ret = intel_encoder;
 415                 num_encoders++;
 416         }
 417
 418         if (num_encoders != 1)
 419                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 420                      pipe_name(intel_crtc->pipe));
 421
 422         BUG_ON(ret == NULL);
 423         return ret;
 424 }
 425
 426 #define LC_FREQ 2700
 427 #define LC_FREQ_2K (LC_FREQ * 2000)
 428
 429 #define P_MIN 2
 430 #define P_MAX 64
 431 #define P_INC 2
 432
 433 /* Constraints for PLL good behavior */
 434 #define REF_MIN 48
 435 #define REF_MAX 400
 436 #define VCO_MIN 2400
 437 #define VCO_MAX 4800
 438
 439 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
 440
 441 struct wrpll_rnp {
 442         unsigned p, n2, r2;
 443 };
 444
 445 static unsigned wrpll_get_budget_for_freq(int clock)
 446 {
 447         unsigned budget;
 448
 449         switch (clock) {
 450         case 25175000:
 451         case 25200000:
 452         case 27000000:
 453         case 27027000:
 454         case 37762500:
 455         case 37800000:
 456         case 40500000:
 457         case 40541000:
 458         case 54000000:
 459         case 54054000:
 460         case 59341000:
 461         case 59400000:
 462         case 72000000:
 463         case 74176000:
 464         case 74250000:
 465         case 81000000:
 466         case 81081000:
 467         case 89012000:
 468         case 89100000:
 469         case 108000000:
 470         case 108108000:
 471         case 111264000:
 472         case 111375000:
 473         case 148352000:
 474         case 148500000:
 475         case 162000000:
 476         case 162162000:
 477         case 222525000:
 478         case 222750000:
 479         case 296703000:
 480         case 297000000:
 481                 budget = 0;
 482                 break;
 483         case 233500000:
 484         case 245250000:
 485         case 247750000:
 486         case 253250000:
 487         case 298000000:
 488                 budget = 1500;
 489                 break;
 490         case 169128000:
 491         case 169500000:
 492         case 179500000:
 493         case 202000000:
 494                 budget = 2000;
 495                 break;
 496         case 256250000:
 497         case 262500000:
 498         case 270000000:
 499         case 272500000:
 500         case 273750000:
 501         case 280750000:
 502         case 281250000:
 503         case 286000000:
 504         case 291750000:
 505                 budget = 4000;
 506                 break;
 507         case 267250000:
 508         case 268500000:
 509                 budget = 5000;
 510                 break;
 511         default:
 512                 budget = 1000;
 513                 break;
 514         }
 515
 516         return budget;
 517 }
 518
 519 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 520                              unsigned r2, unsigned n2, unsigned p,
 521                              struct wrpll_rnp *best)
 522 {
 523         uint64_t a, b, c, d, diff, diff_best;
 524
 525         /* No best (r,n,p) yet */
 526         if (best->p == 0) {
 527                 best->p = p;
 528                 best->n2 = n2;
 529                 best->r2 = r2;
 530                 return;
 531         }
 532
 533         /*
 534          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 535          * freq2k.
 536          *
 537          * delta = 1e6 *
 538          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 539          *         freq2k;
 540          *
 541          * and we would like delta <= budget.
 542          *
 543          * If the discrepancy is above the PPM-based budget, always prefer to
 544          * improve upon the previous solution.  However, if you're within the
 545          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 546          */
 547         a = freq2k * budget * p * r2;
 548         b = freq2k * budget * best->p * best->r2;
 549         diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
 550         diff_best = ABS_DIFF((freq2k * best->p * best->r2),
 551                              (LC_FREQ_2K * best->n2));
 552         c = 1000000 * diff;
 553         d = 1000000 * diff_best;
 554
 555         if (a < c && b < d) {
 556                 /* If both are above the budget, pick the closer */
 557                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 558                         best->p = p;
 559                         best->n2 = n2;
 560                         best->r2 = r2;
 561                 }
 562         } else if (a >= c && b < d) {
 563                 /* If A is below the threshold but B is above it?  Update. */
 564                 best->p = p;
 565                 best->n2 = n2;
 566                 best->r2 = r2;
 567         } else if (a >= c && b >= d) {
 568                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 569                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 570                         best->p = p;
 571                         best->n2 = n2;
 572                         best->r2 = r2;
 573                 }
 574         }
 575         /* Otherwise a < c && b >= d, do nothing */
 576 }
 577
 578 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 579                                      int reg)
 580 {
 581         int refclk = LC_FREQ;
 582         int n, p, r;
 583         u32 wrpll;
 584
 585         wrpll = I915_READ(reg);
 586         switch (wrpll & WRPLL_PLL_REF_MASK) {
 587         case WRPLL_PLL_SSC:
 588         case WRPLL_PLL_NON_SSC:
 589                 /*
 590                  * We could calculate spread here, but our checking
 591                  * code only cares about 5% accuracy, and spread is a max of
 592                  * 0.5% downspread.
 593                  */
 594                 refclk = 135;
 595                 break;
 596         case WRPLL_PLL_LCPLL:
 597                 refclk = LC_FREQ;
 598                 break;
 599         default:
 600                 WARN(1, "bad wrpll refclk\n");
 601                 return 0;
 602         }
 603
 604         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 605         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 606         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 607
 608         /* Convert to KHz, p & r have a fixed point portion */
 609         return (refclk * n * 100) / (p * r);
 610 }
 611
 612 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 613                               struct intel_crtc_config *pipe_config)
 614 {
 615         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 616         int link_clock = 0;
 617         u32 val, pll;
 618
 619         val = pipe_config->ddi_pll_sel;
 620         switch (val & PORT_CLK_SEL_MASK) {
 621         case PORT_CLK_SEL_LCPLL_810:
 622                 link_clock = 81000;
 623                 break;
 624         case PORT_CLK_SEL_LCPLL_1350:
 625                 link_clock = 135000;
 626                 break;
 627         case PORT_CLK_SEL_LCPLL_2700:
 628                 link_clock = 270000;
 629                 break;
 630         case PORT_CLK_SEL_WRPLL1:
 631                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
 632                 break;
 633         case PORT_CLK_SEL_WRPLL2:
 634                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
 635                 break;
 636         case PORT_CLK_SEL_SPLL:
 637                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 638                 if (pll == SPLL_PLL_FREQ_810MHz)
 639                         link_clock = 81000;
 640                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 641                         link_clock = 135000;
 642                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 643                         link_clock = 270000;
 644                 else {
 645                         WARN(1, "bad spll freq\n");
 646                         return;
 647                 }
 648                 break;
 649         default:
 650                 WARN(1, "bad port clock sel\n");
 651                 return;
 652         }
 653
 654         pipe_config->port_clock = link_clock * 2;
 655
 656         if (pipe_config->has_pch_encoder)
 657                 pipe_config->adjusted_mode.crtc_clock =
 658                         intel_dotclock_calculate(pipe_config->port_clock,
 659                                                  &pipe_config->fdi_m_n);
 660         else if (pipe_config->has_dp_encoder)
 661                 pipe_config->adjusted_mode.crtc_clock =
 662                         intel_dotclock_calculate(pipe_config->port_clock,
 663                                                  &pipe_config->dp_m_n);
 664         else
 665                 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
 666 }
 667
 668 void intel_ddi_clock_get(struct intel_encoder *encoder,
 669                          struct intel_crtc_config *pipe_config)
 670 {
 671         hsw_ddi_clock_get(encoder, pipe_config);
 672 }
 673
 674 static void
 675 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 676                         unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 677 {
 678         uint64_t freq2k;
 679         unsigned p, n2, r2;
 680         struct wrpll_rnp best = { 0, 0, 0 };
 681         unsigned budget;
 682
 683         freq2k = clock / 100;
 684
 685         budget = wrpll_get_budget_for_freq(clock);
 686
 687         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 688          * and directly pass the LC PLL to it. */
 689         if (freq2k == 5400000) {
 690                 *n2_out = 2;
 691                 *p_out = 1;
 692                 *r2_out = 2;
 693                 return;
 694         }
 695
 696         /*
 697          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 698          * the WR PLL.
 699          *
 700          * We want R so that REF_MIN <= Ref <= REF_MAX.
 701          * Injecting R2 = 2 * R gives:
 702          *   REF_MAX * r2 > LC_FREQ * 2 and
 703          *   REF_MIN * r2 < LC_FREQ * 2
 704          *
 705          * Which means the desired boundaries for r2 are:
 706          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 707          *
 708          */
 709         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 710              r2 <= LC_FREQ * 2 / REF_MIN;
 711              r2++) {
 712
 713                 /*
 714                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 715                  *
 716                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 717                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 718                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 719                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 720                  *
 721                  * Which means the desired boundaries for n2 are:
 722                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 723                  */
 724                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 725                      n2 <= VCO_MAX * r2 / LC_FREQ;
 726                      n2++) {
 727
 728                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 729                                 wrpll_update_rnp(freq2k, budget,
 730                                                  r2, n2, p, &best);
 731                 }
 732         }
 733
 734         *n2_out = best.n2;
 735         *p_out = best.p;
 736         *r2_out = best.r2;
 737 }
 738
 739 static bool
 740 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 741                    struct intel_encoder *intel_encoder,
 742                    int clock)
 743 {
 744         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 745                 struct intel_shared_dpll *pll;
 746                 uint32_t val;
 747                 unsigned p, n2, r2;
 748
 749                 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 750
 751                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 752                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 753                       WRPLL_DIVIDER_POST(p);
 754
 755                 intel_crtc->config.dpll_hw_state.wrpll = val;
 756
 757                 pll = intel_get_shared_dpll(intel_crtc);
 758                 if (pll == NULL) {
 759                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 760                                          pipe_name(intel_crtc->pipe));
 761                         return false;
 762                 }
 763
 764                 intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
 765         }
 766
 767         return true;
 768 }
 769
 770
 771 /*
 772  * Tries to find a *shared* PLL for the CRTC and store it in
 773  * intel_crtc->ddi_pll_sel.
 774  *
 775  * For private DPLLs, compute_config() should do the selection for us. This
 776  * function should be folded into compute_config() eventually.
 777  */
 778 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 779 {
 780         struct drm_crtc *crtc = &intel_crtc->base;
 781         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 782         int clock = intel_crtc->config.port_clock;
 783
 784         intel_put_shared_dpll(intel_crtc);
 785
 786         return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
 787 }
 788
 789 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 790 {
 791         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 793         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 794         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 795         int type = intel_encoder->type;
 796         uint32_t temp;
 797
 798         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
 799                 temp = TRANS_MSA_SYNC_CLK;
 800                 switch (intel_crtc->config.pipe_bpp) {
 801                 case 18:
 802                         temp |= TRANS_MSA_6_BPC;
 803                         break;
 804                 case 24:
 805                         temp |= TRANS_MSA_8_BPC;
 806                         break;
 807                 case 30:
 808                         temp |= TRANS_MSA_10_BPC;
 809                         break;
 810                 case 36:
 811                         temp |= TRANS_MSA_12_BPC;
 812                         break;
 813                 default:
 814                         BUG();
 815                 }
 816                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 817         }
 818 }
 819
 820 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
 821 {
 822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 823         struct drm_device *dev = crtc->dev;
 824         struct drm_i915_private *dev_priv = dev->dev_private;
 825         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 826         uint32_t temp;
 827         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 828         if (state == true)
 829                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
 830         else
 831                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
 832         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 833 }
 834
 835 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 836 {
 837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 838         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 839         struct drm_encoder *encoder = &intel_encoder->base;
 840         struct drm_device *dev = crtc->dev;
 841         struct drm_i915_private *dev_priv = dev->dev_private;
 842         enum pipe pipe = intel_crtc->pipe;
 843         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 844         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 845         int type = intel_encoder->type;
 846         uint32_t temp;
 847
 848         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 849         temp = TRANS_DDI_FUNC_ENABLE;
 850         temp |= TRANS_DDI_SELECT_PORT(port);
 851
 852         switch (intel_crtc->config.pipe_bpp) {
 853         case 18:
 854                 temp |= TRANS_DDI_BPC_6;
 855                 break;
 856         case 24:
 857                 temp |= TRANS_DDI_BPC_8;
 858                 break;
 859         case 30:
 860                 temp |= TRANS_DDI_BPC_10;
 861                 break;
 862         case 36:
 863                 temp |= TRANS_DDI_BPC_12;
 864                 break;
 865         default:
 866                 BUG();
 867         }
 868
 869         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 870                 temp |= TRANS_DDI_PVSYNC;
 871         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 872                 temp |= TRANS_DDI_PHSYNC;
 873
 874         if (cpu_transcoder == TRANSCODER_EDP) {
 875                 switch (pipe) {
 876                 case PIPE_A:
 877                         /* On Haswell, can only use the always-on power well for
 878                          * eDP when not using the panel fitter, and when not
 879                          * using motion blur mitigation (which we don't
 880                          * support). */
 881                         if (IS_HASWELL(dev) &&
 882                             (intel_crtc->config.pch_pfit.enabled ||
 883                              intel_crtc->config.pch_pfit.force_thru))
 884                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 885                         else
 886                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 887                         break;
 888                 case PIPE_B:
 889                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 890                         break;
 891                 case PIPE_C:
 892                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 893                         break;
 894                 default:
 895                         BUG();
 896                         break;
 897                 }
 898         }
 899
 900         if (type == INTEL_OUTPUT_HDMI) {
 901                 if (intel_crtc->config.has_hdmi_sink)
 902                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 903                 else
 904                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 905
 906         } else if (type == INTEL_OUTPUT_ANALOG) {
 907                 temp |= TRANS_DDI_MODE_SELECT_FDI;
 908                 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
 909
 910         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
 911                    type == INTEL_OUTPUT_EDP) {
 912                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 913
 914                 if (intel_dp->is_mst) {
 915                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 916                 } else
 917                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 918
 919                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 920         } else if (type == INTEL_OUTPUT_DP_MST) {
 921                 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
 922
 923                 if (intel_dp->is_mst) {
 924                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 925                 } else
 926                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 927
 928                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 929         } else {
 930                 WARN(1, "Invalid encoder type %d for pipe %c\n",
 931                      intel_encoder->type, pipe_name(pipe));
 932         }
 933
 934         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 935 }
 936
 937 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 938                                        enum transcoder cpu_transcoder)
 939 {
 940         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 941         uint32_t val = I915_READ(reg);
 942
 943         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
 944         val |= TRANS_DDI_PORT_NONE;
 945         I915_WRITE(reg, val);
 946 }
 947
 948 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 949 {
 950         struct drm_device *dev = intel_connector->base.dev;
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         struct intel_encoder *intel_encoder = intel_connector->encoder;
 953         int type = intel_connector->base.connector_type;
 954         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 955         enum pipe pipe = 0;
 956         enum transcoder cpu_transcoder;
 957         enum intel_display_power_domain power_domain;
 958         uint32_t tmp;
 959
 960         power_domain = intel_display_port_power_domain(intel_encoder);
 961         if (!intel_display_power_enabled(dev_priv, power_domain))
 962                 return false;
 963
 964         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
 965                 return false;
 966
 967         if (port == PORT_A)
 968                 cpu_transcoder = TRANSCODER_EDP;
 969         else
 970                 cpu_transcoder = (enum transcoder) pipe;
 971
 972         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 973
 974         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 975         case TRANS_DDI_MODE_SELECT_HDMI:
 976         case TRANS_DDI_MODE_SELECT_DVI:
 977                 return (type == DRM_MODE_CONNECTOR_HDMIA);
 978
 979         case TRANS_DDI_MODE_SELECT_DP_SST:
 980                 if (type == DRM_MODE_CONNECTOR_eDP)
 981                         return true;
 982                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
 983         case TRANS_DDI_MODE_SELECT_DP_MST:
 984                 /* if the transcoder is in MST state then
 985                  * connector isn't connected */
 986                 return false;
 987
 988         case TRANS_DDI_MODE_SELECT_FDI:
 989                 return (type == DRM_MODE_CONNECTOR_VGA);
 990
 991         default:
 992                 return false;
 993         }
 994 }
 995
 996 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 997                             enum pipe *pipe)
 998 {
 999         struct drm_device *dev = encoder->base.dev;
1000         struct drm_i915_private *dev_priv = dev->dev_private;
1001         enum port port = intel_ddi_get_encoder_port(encoder);
1002         enum intel_display_power_domain power_domain;
1003         u32 tmp;
1004         int i;
1005
1006         power_domain = intel_display_port_power_domain(encoder);
1007         if (!intel_display_power_enabled(dev_priv, power_domain))
1008                 return false;
1009
1010         tmp = I915_READ(DDI_BUF_CTL(port));
1011
1012         if (!(tmp & DDI_BUF_CTL_ENABLE))
1013                 return false;
1014
1015         if (port == PORT_A) {
1016                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1017
1018                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1019                 case TRANS_DDI_EDP_INPUT_A_ON:
1020                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1021                         *pipe = PIPE_A;
1022                         break;
1023                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1024                         *pipe = PIPE_B;
1025                         break;
1026                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1027                         *pipe = PIPE_C;
1028                         break;
1029                 }
1030
1031                 return true;
1032         } else {
1033                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1034                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1035
1036                         if ((tmp & TRANS_DDI_PORT_MASK)
1037                             == TRANS_DDI_SELECT_PORT(port)) {
1038                                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1039                                         return false;
1040
1041                                 *pipe = i;
1042                                 return true;
1043                         }
1044                 }
1045         }
1046
1047         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1048
1049         return false;
1050 }
1051
1052 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1053 {
1054         struct drm_crtc *crtc = &intel_crtc->base;
1055         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1056         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1057         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1058         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1059
1060         if (cpu_transcoder != TRANSCODER_EDP)
1061                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1062                            TRANS_CLK_SEL_PORT(port));
1063 }
1064
1065 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1066 {
1067         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1068         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1069
1070         if (cpu_transcoder != TRANSCODER_EDP)
1071                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1072                            TRANS_CLK_SEL_DISABLED);
1073 }
1074
1075 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1076 {
1077         struct drm_encoder *encoder = &intel_encoder->base;
1078         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1079         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1080         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1081         int type = intel_encoder->type;
1082
1083         if (crtc->config.has_audio) {
1084                 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
1085                                  pipe_name(crtc->pipe));
1086
1087                 /* write eld */
1088                 DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
1089                 intel_write_eld(encoder, &crtc->config.adjusted_mode);
1090         }
1091
1092         if (type == INTEL_OUTPUT_EDP) {
1093                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1094                 intel_edp_panel_on(intel_dp);
1095         }
1096
1097         WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1098         I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1099
1100         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1101                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1102
1103                 intel_ddi_init_dp_buf_reg(intel_encoder);
1104
1105                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1106                 intel_dp_start_link_train(intel_dp);
1107                 intel_dp_complete_link_train(intel_dp);
1108                 if (port != PORT_A)
1109                         intel_dp_stop_link_train(intel_dp);
1110         } else if (type == INTEL_OUTPUT_HDMI) {
1111                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1112
1113                 intel_hdmi->set_infoframes(encoder,
1114                                            crtc->config.has_hdmi_sink,
1115                                            &crtc->config.adjusted_mode);
1116         }
1117 }
1118
1119 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1120 {
1121         struct drm_encoder *encoder = &intel_encoder->base;
1122         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1123         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1124         int type = intel_encoder->type;
1125         uint32_t val;
1126         bool wait = false;
1127
1128         val = I915_READ(DDI_BUF_CTL(port));
1129         if (val & DDI_BUF_CTL_ENABLE) {
1130                 val &= ~DDI_BUF_CTL_ENABLE;
1131                 I915_WRITE(DDI_BUF_CTL(port), val);
1132                 wait = true;
1133         }
1134
1135         val = I915_READ(DP_TP_CTL(port));
1136         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1137         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1138         I915_WRITE(DP_TP_CTL(port), val);
1139
1140         if (wait)
1141                 intel_wait_ddi_buf_idle(dev_priv, port);
1142
1143         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1144                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1145                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1146                 intel_edp_panel_vdd_on(intel_dp);
1147                 intel_edp_panel_off(intel_dp);
1148         }
1149
1150         I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1151 }
1152
1153 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1154 {
1155         struct drm_encoder *encoder = &intel_encoder->base;
1156         struct drm_crtc *crtc = encoder->crtc;
1157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1158         int pipe = intel_crtc->pipe;
1159         struct drm_device *dev = encoder->dev;
1160         struct drm_i915_private *dev_priv = dev->dev_private;
1161         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1162         int type = intel_encoder->type;
1163         uint32_t tmp;
1164
1165         if (type == INTEL_OUTPUT_HDMI) {
1166                 struct intel_digital_port *intel_dig_port =
1167                         enc_to_dig_port(encoder);
1168
1169                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1170                  * are ignored so nothing special needs to be done besides
1171                  * enabling the port.
1172                  */
1173                 I915_WRITE(DDI_BUF_CTL(port),
1174                            intel_dig_port->saved_port_bits |
1175                            DDI_BUF_CTL_ENABLE);
1176         } else if (type == INTEL_OUTPUT_EDP) {
1177                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1178
1179                 if (port == PORT_A)
1180                         intel_dp_stop_link_train(intel_dp);
1181
1182                 intel_edp_backlight_on(intel_dp);
1183                 intel_edp_psr_enable(intel_dp);
1184         }
1185
1186         if (intel_crtc->config.has_audio) {
1187                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1188                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1189                 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1190                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1191         }
1192 }
1193
1194 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1195 {
1196         struct drm_encoder *encoder = &intel_encoder->base;
1197         struct drm_crtc *crtc = encoder->crtc;
1198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1199         int pipe = intel_crtc->pipe;
1200         int type = intel_encoder->type;
1201         struct drm_device *dev = encoder->dev;
1202         struct drm_i915_private *dev_priv = dev->dev_private;
1203         uint32_t tmp;
1204
1205         /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
1206          * register is part of the power well on Haswell. */
1207         if (intel_crtc->config.has_audio) {
1208                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1209                 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1210                          (pipe * 4));
1211                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1212                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1213         }
1214
1215         if (type == INTEL_OUTPUT_EDP) {
1216                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1217
1218                 intel_edp_psr_disable(intel_dp);
1219                 intel_edp_backlight_off(intel_dp);
1220         }
1221 }
1222
1223 static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1224 {
1225         uint32_t lcpll = I915_READ(LCPLL_CTL);
1226         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1227
1228         if (lcpll & LCPLL_CD_SOURCE_FCLK)
1229                 return 800000;
1230         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1231                 return 450000;
1232         else if (freq == LCPLL_CLK_FREQ_450)
1233                 return 450000;
1234         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1235                 return 540000;
1236         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1237                 return 337500;
1238         else
1239                 return 675000;
1240 }
1241
1242 static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1243 {
1244         struct drm_device *dev = dev_priv->dev;
1245         uint32_t lcpll = I915_READ(LCPLL_CTL);
1246         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1247
1248         if (lcpll & LCPLL_CD_SOURCE_FCLK)
1249                 return 800000;
1250         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1251                 return 450000;
1252         else if (freq == LCPLL_CLK_FREQ_450)
1253                 return 450000;
1254         else if (IS_ULT(dev))
1255                 return 337500;
1256         else
1257                 return 540000;
1258 }
1259
1260 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1261 {
1262         struct drm_device *dev = dev_priv->dev;
1263
1264         if (IS_BROADWELL(dev))
1265                 return bdw_get_cdclk_freq(dev_priv);
1266
1267         /* Haswell */
1268         return hsw_get_cdclk_freq(dev_priv);
1269 }
1270
1271 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1272                                struct intel_shared_dpll *pll)
1273 {
1274         I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll);
1275         POSTING_READ(WRPLL_CTL(pll->id));
1276         udelay(20);
1277 }
1278
1279 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1280                                 struct intel_shared_dpll *pll)
1281 {
1282         uint32_t val;
1283
1284         val = I915_READ(WRPLL_CTL(pll->id));
1285         I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1286         POSTING_READ(WRPLL_CTL(pll->id));
1287 }
1288
1289 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1290                                      struct intel_shared_dpll *pll,
1291                                      struct intel_dpll_hw_state *hw_state)
1292 {
1293         uint32_t val;
1294
1295         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
1296                 return false;
1297
1298         val = I915_READ(WRPLL_CTL(pll->id));
1299         hw_state->wrpll = val;
1300
1301         return val & WRPLL_PLL_ENABLE;
1302 }
1303
1304 static const char * const hsw_ddi_pll_names[] = {
1305         "WRPLL 1",
1306         "WRPLL 2",
1307 };
1308
1309 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1310 {
1311         int i;
1312
1313         dev_priv->num_shared_dpll = 2;
1314
1315         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1316                 dev_priv->shared_dplls[i].id = i;
1317                 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1318                 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1319                 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1320                 dev_priv->shared_dplls[i].get_hw_state =
1321                         hsw_ddi_pll_get_hw_state;
1322         }
1323 }
1324
1325 void intel_ddi_pll_init(struct drm_device *dev)
1326 {
1327         struct drm_i915_private *dev_priv = dev->dev_private;
1328         uint32_t val = I915_READ(LCPLL_CTL);
1329
1330         hsw_shared_dplls_init(dev_priv);
1331
1332         /* The LCPLL register should be turned on by the BIOS. For now let's
1333          * just check its state and print errors in case something is wrong.
1334          * Don't even try to turn it on.
1335          */
1336
1337         DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1338                       intel_ddi_get_cdclk_freq(dev_priv));
1339
1340         if (val & LCPLL_CD_SOURCE_FCLK)
1341                 DRM_ERROR("CDCLK source is not LCPLL\n");
1342
1343         if (val & LCPLL_PLL_DISABLE)
1344                 DRM_ERROR("LCPLL is disabled\n");
1345 }
1346
1347 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1348 {
1349         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1350         struct intel_dp *intel_dp = &intel_dig_port->dp;
1351         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1352         enum port port = intel_dig_port->port;
1353         uint32_t val;
1354         bool wait = false;
1355
1356         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1357                 val = I915_READ(DDI_BUF_CTL(port));
1358                 if (val & DDI_BUF_CTL_ENABLE) {
1359                         val &= ~DDI_BUF_CTL_ENABLE;
1360                         I915_WRITE(DDI_BUF_CTL(port), val);
1361                         wait = true;
1362                 }
1363
1364                 val = I915_READ(DP_TP_CTL(port));
1365                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1366                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1367                 I915_WRITE(DP_TP_CTL(port), val);
1368                 POSTING_READ(DP_TP_CTL(port));
1369
1370                 if (wait)
1371                         intel_wait_ddi_buf_idle(dev_priv, port);
1372         }
1373
1374         val = DP_TP_CTL_ENABLE |
1375               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1376         if (intel_dp->is_mst)
1377                 val |= DP_TP_CTL_MODE_MST;
1378         else {
1379                 val |= DP_TP_CTL_MODE_SST;
1380                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1381                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1382         }
1383         I915_WRITE(DP_TP_CTL(port), val);
1384         POSTING_READ(DP_TP_CTL(port));
1385
1386         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1387         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1388         POSTING_READ(DDI_BUF_CTL(port));
1389
1390         udelay(600);
1391 }
1392
1393 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1394 {
1395         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1396         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1397         uint32_t val;
1398
1399         intel_ddi_post_disable(intel_encoder);
1400
1401         val = I915_READ(_FDI_RXA_CTL);
1402         val &= ~FDI_RX_ENABLE;
1403         I915_WRITE(_FDI_RXA_CTL, val);
1404
1405         val = I915_READ(_FDI_RXA_MISC);
1406         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1407         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1408         I915_WRITE(_FDI_RXA_MISC, val);
1409
1410         val = I915_READ(_FDI_RXA_CTL);
1411         val &= ~FDI_PCDCLK;
1412         I915_WRITE(_FDI_RXA_CTL, val);
1413
1414         val = I915_READ(_FDI_RXA_CTL);
1415         val &= ~FDI_RX_PLL_ENABLE;
1416         I915_WRITE(_FDI_RXA_CTL, val);
1417 }
1418
1419 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1420 {
1421         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
1422         int type = intel_dig_port->base.type;
1423
1424         if (type != INTEL_OUTPUT_DISPLAYPORT &&
1425             type != INTEL_OUTPUT_EDP &&
1426             type != INTEL_OUTPUT_UNKNOWN) {
1427                 return;
1428         }
1429
1430         intel_dp_hot_plug(intel_encoder);
1431 }
1432
1433 void intel_ddi_get_config(struct intel_encoder *encoder,
1434                           struct intel_crtc_config *pipe_config)
1435 {
1436         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1437         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1438         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1439         u32 temp, flags = 0;
1440
1441         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1442         if (temp & TRANS_DDI_PHSYNC)
1443                 flags |= DRM_MODE_FLAG_PHSYNC;
1444         else
1445                 flags |= DRM_MODE_FLAG_NHSYNC;
1446         if (temp & TRANS_DDI_PVSYNC)
1447                 flags |= DRM_MODE_FLAG_PVSYNC;
1448         else
1449                 flags |= DRM_MODE_FLAG_NVSYNC;
1450
1451         pipe_config->adjusted_mode.flags |= flags;
1452
1453         switch (temp & TRANS_DDI_BPC_MASK) {
1454         case TRANS_DDI_BPC_6:
1455                 pipe_config->pipe_bpp = 18;
1456                 break;
1457         case TRANS_DDI_BPC_8:
1458                 pipe_config->pipe_bpp = 24;
1459                 break;
1460         case TRANS_DDI_BPC_10:
1461                 pipe_config->pipe_bpp = 30;
1462                 break;
1463         case TRANS_DDI_BPC_12:
1464                 pipe_config->pipe_bpp = 36;
1465                 break;
1466         default:
1467                 break;
1468         }
1469
1470         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1471         case TRANS_DDI_MODE_SELECT_HDMI:
1472                 pipe_config->has_hdmi_sink = true;
1473         case TRANS_DDI_MODE_SELECT_DVI:
1474         case TRANS_DDI_MODE_SELECT_FDI:
1475                 break;
1476         case TRANS_DDI_MODE_SELECT_DP_SST:
1477         case TRANS_DDI_MODE_SELECT_DP_MST:
1478                 pipe_config->has_dp_encoder = true;
1479                 intel_dp_get_m_n(intel_crtc, pipe_config);
1480                 break;
1481         default:
1482                 break;
1483         }
1484
1485         if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1486                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1487                 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
1488                         pipe_config->has_audio = true;
1489         }
1490
1491         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1492             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1493                 /*
1494                  * This is a big fat ugly hack.
1495                  *
1496                  * Some machines in UEFI boot mode provide us a VBT that has 18
1497                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1498                  * unknown we fail to light up. Yet the same BIOS boots up with
1499                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1500                  * max, not what it tells us to use.
1501                  *
1502                  * Note: This will still be broken if the eDP panel is not lit
1503                  * up by the BIOS, and thus we can't get the mode at module
1504                  * load.
1505                  */
1506                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1507                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1508                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1509         }
1510
1511         hsw_ddi_clock_get(encoder, pipe_config);
1512 }
1513
1514 static void intel_ddi_destroy(struct drm_encoder *encoder)
1515 {
1516         /* HDMI has nothing special to destroy, so we can go with this. */
1517         intel_dp_encoder_destroy(encoder);
1518 }
1519
1520 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1521                                      struct intel_crtc_config *pipe_config)
1522 {
1523         int type = encoder->type;
1524         int port = intel_ddi_get_encoder_port(encoder);
1525
1526         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1527
1528         if (port == PORT_A)
1529                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1530
1531         if (type == INTEL_OUTPUT_HDMI)
1532                 return intel_hdmi_compute_config(encoder, pipe_config);
1533         else
1534                 return intel_dp_compute_config(encoder, pipe_config);
1535 }
1536
1537 static const struct drm_encoder_funcs intel_ddi_funcs = {
1538         .destroy = intel_ddi_destroy,
1539 };
1540
1541 static struct intel_connector *
1542 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1543 {
1544         struct intel_connector *connector;
1545         enum port port = intel_dig_port->port;
1546
1547         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1548         if (!connector)
1549                 return NULL;
1550
1551         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1552         if (!intel_dp_init_connector(intel_dig_port, connector)) {
1553                 kfree(connector);
1554                 return NULL;
1555         }
1556
1557         return connector;
1558 }
1559
1560 static struct intel_connector *
1561 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1562 {
1563         struct intel_connector *connector;
1564         enum port port = intel_dig_port->port;
1565
1566         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1567         if (!connector)
1568                 return NULL;
1569
1570         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1571         intel_hdmi_init_connector(intel_dig_port, connector);
1572
1573         return connector;
1574 }
1575
1576 void intel_ddi_init(struct drm_device *dev, enum port port)
1577 {
1578         struct drm_i915_private *dev_priv = dev->dev_private;
1579         struct intel_digital_port *intel_dig_port;
1580         struct intel_encoder *intel_encoder;
1581         struct drm_encoder *encoder;
1582         bool init_hdmi, init_dp;
1583
1584         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1585                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1586         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1587         if (!init_dp && !init_hdmi) {
1588                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
1589                               port_name(port));
1590                 init_hdmi = true;
1591                 init_dp = true;
1592         }
1593
1594         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1595         if (!intel_dig_port)
1596                 return;
1597
1598         intel_encoder = &intel_dig_port->base;
1599         encoder = &intel_encoder->base;
1600
1601         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1602                          DRM_MODE_ENCODER_TMDS);
1603
1604         intel_encoder->compute_config = intel_ddi_compute_config;
1605         intel_encoder->enable = intel_enable_ddi;
1606         intel_encoder->pre_enable = intel_ddi_pre_enable;
1607         intel_encoder->disable = intel_disable_ddi;
1608         intel_encoder->post_disable = intel_ddi_post_disable;
1609         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1610         intel_encoder->get_config = intel_ddi_get_config;
1611
1612         intel_dig_port->port = port;
1613         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1614                                           (DDI_BUF_PORT_REVERSAL |
1615                                            DDI_A_4_LANES);
1616
1617         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1618         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1619         intel_encoder->cloneable = 0;
1620         intel_encoder->hot_plug = intel_ddi_hot_plug;
1621
1622         if (init_dp) {
1623                 if (!intel_ddi_init_dp_connector(intel_dig_port))
1624                         goto err;
1625
1626                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
1627                 dev_priv->hpd_irq_port[port] = intel_dig_port;
1628         }
1629
1630         /* In theory we don't need the encoder->type check, but leave it just in
1631          * case we have some really bad VBTs... */
1632         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
1633                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
1634                         goto err;
1635         }
1636
1637         return;
1638
1639 err:
1640         drm_encoder_cleanup(encoder);
1641         kfree(intel_dig_port);
1642 }