drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34 };
  35
  36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  37  * them for both DP and FDI transports, allowing those ports to
  38  * automatically adapt to HDMI connections as well
  39  */
  40 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  41         { 0x00FFFFFF, 0x0006000E },
  42         { 0x00D75FFF, 0x0005000A },
  43         { 0x00C30FFF, 0x00040006 },
  44         { 0x80AAAFFF, 0x000B0000 },
  45         { 0x00FFFFFF, 0x0005000A },
  46         { 0x00D75FFF, 0x000C0004 },
  47         { 0x80C30FFF, 0x000B0000 },
  48         { 0x00FFFFFF, 0x00040006 },
  49         { 0x80D75FFF, 0x000B0000 },
  50 };
  51
  52 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  53         { 0x00FFFFFF, 0x0007000E },
  54         { 0x00D75FFF, 0x000F000A },
  55         { 0x00C30FFF, 0x00060006 },
  56         { 0x00AAAFFF, 0x001E0000 },
  57         { 0x00FFFFFF, 0x000F000A },
  58         { 0x00D75FFF, 0x00160004 },
  59         { 0x00C30FFF, 0x001E0000 },
  60         { 0x00FFFFFF, 0x00060006 },
  61         { 0x00D75FFF, 0x001E0000 },
  62 };
  63
  64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  65                                         /* Idx  NT mV d T mV d  db      */
  66         { 0x00FFFFFF, 0x0006000E },     /* 0:   400     400     0       */
  67         { 0x00E79FFF, 0x000E000C },     /* 1:   400     500     2       */
  68         { 0x00D75FFF, 0x0005000A },     /* 2:   400     600     3.5     */
  69         { 0x00FFFFFF, 0x0005000A },     /* 3:   600     600     0       */
  70         { 0x00E79FFF, 0x001D0007 },     /* 4:   600     750     2       */
  71         { 0x00D75FFF, 0x000C0004 },     /* 5:   600     900     3.5     */
  72         { 0x00FFFFFF, 0x00040006 },     /* 6:   800     800     0       */
  73         { 0x80E79FFF, 0x00030002 },     /* 7:   800     1000    2       */
  74         { 0x00FFFFFF, 0x00140005 },     /* 8:   850     850     0       */
  75         { 0x00FFFFFF, 0x000C0004 },     /* 9:   900     900     0       */
  76         { 0x00FFFFFF, 0x001C0003 },     /* 10:  950     950     0       */
  77         { 0x80FFFFFF, 0x00030002 },     /* 11:  1000    1000    0       */
  78 };
  79
  80 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  81         { 0x00FFFFFF, 0x00000012 },
  82         { 0x00EBAFFF, 0x00020011 },
  83         { 0x00C71FFF, 0x0006000F },
  84         { 0x00AAAFFF, 0x000E000A },
  85         { 0x00FFFFFF, 0x00020011 },
  86         { 0x00DB6FFF, 0x0005000F },
  87         { 0x00BEEFFF, 0x000A000C },
  88         { 0x00FFFFFF, 0x0005000F },
  89         { 0x00DB6FFF, 0x000A000C },
  90 };
  91
  92 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
  93         { 0x00FFFFFF, 0x0007000E },
  94         { 0x00D75FFF, 0x000E000A },
  95         { 0x00BEFFFF, 0x00140006 },
  96         { 0x80B2CFFF, 0x001B0002 },
  97         { 0x00FFFFFF, 0x000E000A },
  98         { 0x00DB6FFF, 0x00160005 },
  99         { 0x80C71FFF, 0x001A0002 },
 100         { 0x00F7DFFF, 0x00180004 },
 101         { 0x80D75FFF, 0x001B0002 },
 102 };
 103
 104 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 105         { 0x00FFFFFF, 0x0001000E },
 106         { 0x00D75FFF, 0x0004000A },
 107         { 0x00C30FFF, 0x00070006 },
 108         { 0x00AAAFFF, 0x000C0000 },
 109         { 0x00FFFFFF, 0x0004000A },
 110         { 0x00D75FFF, 0x00090004 },
 111         { 0x00C30FFF, 0x000C0000 },
 112         { 0x00FFFFFF, 0x00070006 },
 113         { 0x00D75FFF, 0x000C0000 },
 114 };
 115
 116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 117                                         /* Idx  NT mV d T mV df db      */
 118         { 0x00FFFFFF, 0x0007000E },     /* 0:   400     400     0       */
 119         { 0x00D75FFF, 0x000E000A },     /* 1:   400     600     3.5     */
 120         { 0x00BEFFFF, 0x00140006 },     /* 2:   400     800     6       */
 121         { 0x00FFFFFF, 0x0009000D },     /* 3:   450     450     0       */
 122         { 0x00FFFFFF, 0x000E000A },     /* 4:   600     600     0       */
 123         { 0x00D7FFFF, 0x00140006 },     /* 5:   600     800     2.5     */
 124         { 0x80CB2FFF, 0x001B0002 },     /* 6:   600     1000    4.5     */
 125         { 0x00FFFFFF, 0x00140006 },     /* 7:   800     800     0       */
 126         { 0x80E79FFF, 0x001B0002 },     /* 8:   800     1000    2       */
 127         { 0x80FFFFFF, 0x001B0002 },     /* 9:   1000    1000    0       */
 128 };
 129
 130 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 131         { 0x00000018, 0x000000a0 },
 132         { 0x00004014, 0x00000098 },
 133         { 0x00006012, 0x00000088 },
 134         { 0x00008010, 0x00000080 },
 135         { 0x00000018, 0x00000098 },
 136         { 0x00004014, 0x00000088 },
 137         { 0x00006012, 0x00000080 },
 138         { 0x00000018, 0x00000088 },
 139         { 0x00004014, 0x00000080 },
 140 };
 141
 142 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 143                                         /* Idx  NT mV   T mV    db  */
 144         { 0x00000018, 0x000000a0 },     /* 0:   400     400     0   */
 145         { 0x00004014, 0x00000098 },     /* 1:   400     600     3.5 */
 146         { 0x00006012, 0x00000088 },     /* 2:   400     800     6   */
 147         { 0x00000018, 0x0000003c },     /* 3:   450     450     0   */
 148         { 0x00000018, 0x00000098 },     /* 4:   600     600     0   */
 149         { 0x00003015, 0x00000088 },     /* 5:   600     800     2.5 */
 150         { 0x00005013, 0x00000080 },     /* 6:   600     1000    4.5 */
 151         { 0x00000018, 0x00000088 },     /* 7:   800     800     0   */
 152         { 0x00000096, 0x00000080 },     /* 8:   800     1000    2   */
 153         { 0x00000018, 0x00000080 },     /* 9:   1200    1200    0   */
 154 };
 155
 156 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 157 {
 158         struct drm_encoder *encoder = &intel_encoder->base;
 159         int type = intel_encoder->type;
 160
 161         if (type == INTEL_OUTPUT_DP_MST) {
 162                 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
 163                 return intel_dig_port->port;
 164         } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 165             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 166                 struct intel_digital_port *intel_dig_port =
 167                         enc_to_dig_port(encoder);
 168                 return intel_dig_port->port;
 169
 170         } else if (type == INTEL_OUTPUT_ANALOG) {
 171                 return PORT_E;
 172
 173         } else {
 174                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
 175                 BUG();
 176         }
 177 }
 178
 179 /*
 180  * Starting with Haswell, DDI port buffers must be programmed with correct
 181  * values in advance. The buffer values are different for FDI and DP modes,
 182  * but the HDMI/DVI fields are shared among those. So we program the DDI
 183  * in either FDI or DP modes only, as HDMI connections will work with both
 184  * of those
 185  */
 186 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 187 {
 188         struct drm_i915_private *dev_priv = dev->dev_private;
 189         u32 reg;
 190         int i, n_hdmi_entries, hdmi_800mV_0dB;
 191         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 192         const struct ddi_buf_trans *ddi_translations_fdi;
 193         const struct ddi_buf_trans *ddi_translations_dp;
 194         const struct ddi_buf_trans *ddi_translations_edp;
 195         const struct ddi_buf_trans *ddi_translations_hdmi;
 196         const struct ddi_buf_trans *ddi_translations;
 197
 198         if (IS_SKYLAKE(dev)) {
 199                 ddi_translations_fdi = NULL;
 200                 ddi_translations_dp = skl_ddi_translations_dp;
 201                 ddi_translations_edp = skl_ddi_translations_dp;
 202                 ddi_translations_hdmi = skl_ddi_translations_hdmi;
 203                 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 204                 hdmi_800mV_0dB = 7;
 205         } else if (IS_BROADWELL(dev)) {
 206                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 207                 ddi_translations_dp = bdw_ddi_translations_dp;
 208                 ddi_translations_edp = bdw_ddi_translations_edp;
 209                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 210                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 211                 hdmi_800mV_0dB = 7;
 212         } else if (IS_HASWELL(dev)) {
 213                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 214                 ddi_translations_dp = hsw_ddi_translations_dp;
 215                 ddi_translations_edp = hsw_ddi_translations_dp;
 216                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 217                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 218                 hdmi_800mV_0dB = 6;
 219         } else {
 220                 WARN(1, "ddi translation table missing\n");
 221                 ddi_translations_edp = bdw_ddi_translations_dp;
 222                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 223                 ddi_translations_dp = bdw_ddi_translations_dp;
 224                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 225                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 226                 hdmi_800mV_0dB = 7;
 227         }
 228
 229         switch (port) {
 230         case PORT_A:
 231                 ddi_translations = ddi_translations_edp;
 232                 break;
 233         case PORT_B:
 234         case PORT_C:
 235                 ddi_translations = ddi_translations_dp;
 236                 break;
 237         case PORT_D:
 238                 if (intel_dp_is_edp(dev, PORT_D))
 239                         ddi_translations = ddi_translations_edp;
 240                 else
 241                         ddi_translations = ddi_translations_dp;
 242                 break;
 243         case PORT_E:
 244                 if (ddi_translations_fdi)
 245                         ddi_translations = ddi_translations_fdi;
 246                 else
 247                         ddi_translations = ddi_translations_dp;
 248                 break;
 249         default:
 250                 BUG();
 251         }
 252
 253         for (i = 0, reg = DDI_BUF_TRANS(port);
 254              i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 255                 I915_WRITE(reg, ddi_translations[i].trans1);
 256                 reg += 4;
 257                 I915_WRITE(reg, ddi_translations[i].trans2);
 258                 reg += 4;
 259         }
 260
 261         /* Choose a good default if VBT is badly populated */
 262         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 263             hdmi_level >= n_hdmi_entries)
 264                 hdmi_level = hdmi_800mV_0dB;
 265
 266         /* Entry 9 is for HDMI: */
 267         I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
 268         reg += 4;
 269         I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
 270         reg += 4;
 271 }
 272
 273 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 274  * mode and port E for FDI.
 275  */
 276 void intel_prepare_ddi(struct drm_device *dev)
 277 {
 278         int port;
 279
 280         if (!HAS_DDI(dev))
 281                 return;
 282
 283         for (port = PORT_A; port <= PORT_E; port++)
 284                 intel_prepare_ddi_buffers(dev, port);
 285 }
 286
 287 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 288                                     enum port port)
 289 {
 290         uint32_t reg = DDI_BUF_CTL(port);
 291         int i;
 292
 293         for (i = 0; i < 8; i++) {
 294                 udelay(1);
 295                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 296                         return;
 297         }
 298         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 299 }
 300
 301 /* Starting with Haswell, different DDI ports can work in FDI mode for
 302  * connection to the PCH-located connectors. For this, it is necessary to train
 303  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 304  *
 305  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 306  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 307  * DDI A (which is used for eDP)
 308  */
 309
 310 void hsw_fdi_link_train(struct drm_crtc *crtc)
 311 {
 312         struct drm_device *dev = crtc->dev;
 313         struct drm_i915_private *dev_priv = dev->dev_private;
 314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 315         u32 temp, i, rx_ctl_val;
 316
 317         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 318          * mode set "sequence for CRT port" document:
 319          * - TP1 to TP2 time with the default value
 320          * - FDI delay to 90h
 321          *
 322          * WaFDIAutoLinkSetTimingOverrride:hsw
 323          */
 324         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 325                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 326                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 327
 328         /* Enable the PCH Receiver FDI PLL */
 329         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 330                      FDI_RX_PLL_ENABLE |
 331                      FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
 332         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 333         POSTING_READ(_FDI_RXA_CTL);
 334         udelay(220);
 335
 336         /* Switch from Rawclk to PCDclk */
 337         rx_ctl_val |= FDI_PCDCLK;
 338         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 339
 340         /* Configure Port Clock Select */
 341         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
 342         WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
 343
 344         /* Start the training iterating through available voltages and emphasis,
 345          * testing each value twice. */
 346         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 347                 /* Configure DP_TP_CTL with auto-training */
 348                 I915_WRITE(DP_TP_CTL(PORT_E),
 349                                         DP_TP_CTL_FDI_AUTOTRAIN |
 350                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 351                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 352                                         DP_TP_CTL_ENABLE);
 353
 354                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 355                  * DDI E does not support port reversal, the functionality is
 356                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 357                  * port reversal bit */
 358                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 359                            DDI_BUF_CTL_ENABLE |
 360                            ((intel_crtc->config.fdi_lanes - 1) << 1) |
 361                            DDI_BUF_TRANS_SELECT(i / 2));
 362                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 363
 364                 udelay(600);
 365
 366                 /* Program PCH FDI Receiver TU */
 367                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 368
 369                 /* Enable PCH FDI Receiver with auto-training */
 370                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 371                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 372                 POSTING_READ(_FDI_RXA_CTL);
 373
 374                 /* Wait for FDI receiver lane calibration */
 375                 udelay(30);
 376
 377                 /* Unset FDI_RX_MISC pwrdn lanes */
 378                 temp = I915_READ(_FDI_RXA_MISC);
 379                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 380                 I915_WRITE(_FDI_RXA_MISC, temp);
 381                 POSTING_READ(_FDI_RXA_MISC);
 382
 383                 /* Wait for FDI auto training time */
 384                 udelay(5);
 385
 386                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 387                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 388                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 389
 390                         /* Enable normal pixel sending for FDI */
 391                         I915_WRITE(DP_TP_CTL(PORT_E),
 392                                    DP_TP_CTL_FDI_AUTOTRAIN |
 393                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 394                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 395                                    DP_TP_CTL_ENABLE);
 396
 397                         return;
 398                 }
 399
 400                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 401                 temp &= ~DDI_BUF_CTL_ENABLE;
 402                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 403                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 404
 405                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 406                 temp = I915_READ(DP_TP_CTL(PORT_E));
 407                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 408                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 409                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 410                 POSTING_READ(DP_TP_CTL(PORT_E));
 411
 412                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 413
 414                 rx_ctl_val &= ~FDI_RX_ENABLE;
 415                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 416                 POSTING_READ(_FDI_RXA_CTL);
 417
 418                 /* Reset FDI_RX_MISC pwrdn lanes */
 419                 temp = I915_READ(_FDI_RXA_MISC);
 420                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 421                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 422                 I915_WRITE(_FDI_RXA_MISC, temp);
 423                 POSTING_READ(_FDI_RXA_MISC);
 424         }
 425
 426         DRM_ERROR("FDI link training failed!\n");
 427 }
 428
 429 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 430 {
 431         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 432         struct intel_digital_port *intel_dig_port =
 433                 enc_to_dig_port(&encoder->base);
 434
 435         intel_dp->DP = intel_dig_port->saved_port_bits |
 436                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 437         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 438
 439 }
 440
 441 static struct intel_encoder *
 442 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 443 {
 444         struct drm_device *dev = crtc->dev;
 445         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 446         struct intel_encoder *intel_encoder, *ret = NULL;
 447         int num_encoders = 0;
 448
 449         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 450                 ret = intel_encoder;
 451                 num_encoders++;
 452         }
 453
 454         if (num_encoders != 1)
 455                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 456                      pipe_name(intel_crtc->pipe));
 457
 458         BUG_ON(ret == NULL);
 459         return ret;
 460 }
 461
 462 static struct intel_encoder *
 463 intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
 464 {
 465         struct drm_device *dev = crtc->base.dev;
 466         struct intel_encoder *intel_encoder, *ret = NULL;
 467         int num_encoders = 0;
 468
 469         for_each_intel_encoder(dev, intel_encoder) {
 470                 if (intel_encoder->new_crtc == crtc) {
 471                         ret = intel_encoder;
 472                         num_encoders++;
 473                 }
 474         }
 475
 476         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
 477              pipe_name(crtc->pipe));
 478
 479         BUG_ON(ret == NULL);
 480         return ret;
 481 }
 482
 483 #define LC_FREQ 2700
 484 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
 485
 486 #define P_MIN 2
 487 #define P_MAX 64
 488 #define P_INC 2
 489
 490 /* Constraints for PLL good behavior */
 491 #define REF_MIN 48
 492 #define REF_MAX 400
 493 #define VCO_MIN 2400
 494 #define VCO_MAX 4800
 495
 496 #define abs_diff(a, b) ({                       \
 497         typeof(a) __a = (a);                    \
 498         typeof(b) __b = (b);                    \
 499         (void) (&__a == &__b);                  \
 500         __a > __b ? (__a - __b) : (__b - __a); })
 501
 502 struct wrpll_rnp {
 503         unsigned p, n2, r2;
 504 };
 505
 506 static unsigned wrpll_get_budget_for_freq(int clock)
 507 {
 508         unsigned budget;
 509
 510         switch (clock) {
 511         case 25175000:
 512         case 25200000:
 513         case 27000000:
 514         case 27027000:
 515         case 37762500:
 516         case 37800000:
 517         case 40500000:
 518         case 40541000:
 519         case 54000000:
 520         case 54054000:
 521         case 59341000:
 522         case 59400000:
 523         case 72000000:
 524         case 74176000:
 525         case 74250000:
 526         case 81000000:
 527         case 81081000:
 528         case 89012000:
 529         case 89100000:
 530         case 108000000:
 531         case 108108000:
 532         case 111264000:
 533         case 111375000:
 534         case 148352000:
 535         case 148500000:
 536         case 162000000:
 537         case 162162000:
 538         case 222525000:
 539         case 222750000:
 540         case 296703000:
 541         case 297000000:
 542                 budget = 0;
 543                 break;
 544         case 233500000:
 545         case 245250000:
 546         case 247750000:
 547         case 253250000:
 548         case 298000000:
 549                 budget = 1500;
 550                 break;
 551         case 169128000:
 552         case 169500000:
 553         case 179500000:
 554         case 202000000:
 555                 budget = 2000;
 556                 break;
 557         case 256250000:
 558         case 262500000:
 559         case 270000000:
 560         case 272500000:
 561         case 273750000:
 562         case 280750000:
 563         case 281250000:
 564         case 286000000:
 565         case 291750000:
 566                 budget = 4000;
 567                 break;
 568         case 267250000:
 569         case 268500000:
 570                 budget = 5000;
 571                 break;
 572         default:
 573                 budget = 1000;
 574                 break;
 575         }
 576
 577         return budget;
 578 }
 579
 580 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 581                              unsigned r2, unsigned n2, unsigned p,
 582                              struct wrpll_rnp *best)
 583 {
 584         uint64_t a, b, c, d, diff, diff_best;
 585
 586         /* No best (r,n,p) yet */
 587         if (best->p == 0) {
 588                 best->p = p;
 589                 best->n2 = n2;
 590                 best->r2 = r2;
 591                 return;
 592         }
 593
 594         /*
 595          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 596          * freq2k.
 597          *
 598          * delta = 1e6 *
 599          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 600          *         freq2k;
 601          *
 602          * and we would like delta <= budget.
 603          *
 604          * If the discrepancy is above the PPM-based budget, always prefer to
 605          * improve upon the previous solution.  However, if you're within the
 606          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 607          */
 608         a = freq2k * budget * p * r2;
 609         b = freq2k * budget * best->p * best->r2;
 610         diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
 611         diff_best = abs_diff(freq2k * best->p * best->r2,
 612                              LC_FREQ_2K * best->n2);
 613         c = 1000000 * diff;
 614         d = 1000000 * diff_best;
 615
 616         if (a < c && b < d) {
 617                 /* If both are above the budget, pick the closer */
 618                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 619                         best->p = p;
 620                         best->n2 = n2;
 621                         best->r2 = r2;
 622                 }
 623         } else if (a >= c && b < d) {
 624                 /* If A is below the threshold but B is above it?  Update. */
 625                 best->p = p;
 626                 best->n2 = n2;
 627                 best->r2 = r2;
 628         } else if (a >= c && b >= d) {
 629                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 630                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 631                         best->p = p;
 632                         best->n2 = n2;
 633                         best->r2 = r2;
 634                 }
 635         }
 636         /* Otherwise a < c && b >= d, do nothing */
 637 }
 638
 639 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 640                                      int reg)
 641 {
 642         int refclk = LC_FREQ;
 643         int n, p, r;
 644         u32 wrpll;
 645
 646         wrpll = I915_READ(reg);
 647         switch (wrpll & WRPLL_PLL_REF_MASK) {
 648         case WRPLL_PLL_SSC:
 649         case WRPLL_PLL_NON_SSC:
 650                 /*
 651                  * We could calculate spread here, but our checking
 652                  * code only cares about 5% accuracy, and spread is a max of
 653                  * 0.5% downspread.
 654                  */
 655                 refclk = 135;
 656                 break;
 657         case WRPLL_PLL_LCPLL:
 658                 refclk = LC_FREQ;
 659                 break;
 660         default:
 661                 WARN(1, "bad wrpll refclk\n");
 662                 return 0;
 663         }
 664
 665         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 666         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 667         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 668
 669         /* Convert to KHz, p & r have a fixed point portion */
 670         return (refclk * n * 100) / (p * r);
 671 }
 672
 673 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 674                                uint32_t dpll)
 675 {
 676         uint32_t cfgcr1_reg, cfgcr2_reg;
 677         uint32_t cfgcr1_val, cfgcr2_val;
 678         uint32_t p0, p1, p2, dco_freq;
 679
 680         cfgcr1_reg = GET_CFG_CR1_REG(dpll);
 681         cfgcr2_reg = GET_CFG_CR2_REG(dpll);
 682
 683         cfgcr1_val = I915_READ(cfgcr1_reg);
 684         cfgcr2_val = I915_READ(cfgcr2_reg);
 685
 686         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
 687         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
 688
 689         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
 690                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
 691         else
 692                 p1 = 1;
 693
 694
 695         switch (p0) {
 696         case DPLL_CFGCR2_PDIV_1:
 697                 p0 = 1;
 698                 break;
 699         case DPLL_CFGCR2_PDIV_2:
 700                 p0 = 2;
 701                 break;
 702         case DPLL_CFGCR2_PDIV_3:
 703                 p0 = 3;
 704                 break;
 705         case DPLL_CFGCR2_PDIV_7:
 706                 p0 = 7;
 707                 break;
 708         }
 709
 710         switch (p2) {
 711         case DPLL_CFGCR2_KDIV_5:
 712                 p2 = 5;
 713                 break;
 714         case DPLL_CFGCR2_KDIV_2:
 715                 p2 = 2;
 716                 break;
 717         case DPLL_CFGCR2_KDIV_3:
 718                 p2 = 3;
 719                 break;
 720         case DPLL_CFGCR2_KDIV_1:
 721                 p2 = 1;
 722                 break;
 723         }
 724
 725         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
 726
 727         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
 728                 1000) / 0x8000;
 729
 730         return dco_freq / (p0 * p1 * p2 * 5);
 731 }
 732
 733
 734 static void skl_ddi_clock_get(struct intel_encoder *encoder,
 735                                 struct intel_crtc_config *pipe_config)
 736 {
 737         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 738         enum port port = intel_ddi_get_encoder_port(encoder);
 739         int link_clock = 0;
 740         uint32_t dpll_ctl1, dpll;
 741
 742         /* FIXME: This should be tracked in the pipe config. */
 743         dpll = I915_READ(DPLL_CTRL2);
 744         dpll &= DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
 745         dpll >>= DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
 746
 747         dpll_ctl1 = I915_READ(DPLL_CTRL1);
 748
 749         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
 750                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
 751         } else {
 752                 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
 753                 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
 754
 755                 switch (link_clock) {
 756                 case DPLL_CRTL1_LINK_RATE_810:
 757                         link_clock = 81000;
 758                         break;
 759                 case DPLL_CRTL1_LINK_RATE_1350:
 760                         link_clock = 135000;
 761                         break;
 762                 case DPLL_CRTL1_LINK_RATE_2700:
 763                         link_clock = 270000;
 764                         break;
 765                 default:
 766                         WARN(1, "Unsupported link rate\n");
 767                         break;
 768                 }
 769                 link_clock *= 2;
 770         }
 771
 772         pipe_config->port_clock = link_clock;
 773
 774         if (pipe_config->has_dp_encoder)
 775                 pipe_config->adjusted_mode.crtc_clock =
 776                         intel_dotclock_calculate(pipe_config->port_clock,
 777                                                  &pipe_config->dp_m_n);
 778         else
 779                 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
 780 }
 781
 782 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 783                               struct intel_crtc_config *pipe_config)
 784 {
 785         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 786         int link_clock = 0;
 787         u32 val, pll;
 788
 789         val = pipe_config->ddi_pll_sel;
 790         switch (val & PORT_CLK_SEL_MASK) {
 791         case PORT_CLK_SEL_LCPLL_810:
 792                 link_clock = 81000;
 793                 break;
 794         case PORT_CLK_SEL_LCPLL_1350:
 795                 link_clock = 135000;
 796                 break;
 797         case PORT_CLK_SEL_LCPLL_2700:
 798                 link_clock = 270000;
 799                 break;
 800         case PORT_CLK_SEL_WRPLL1:
 801                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
 802                 break;
 803         case PORT_CLK_SEL_WRPLL2:
 804                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
 805                 break;
 806         case PORT_CLK_SEL_SPLL:
 807                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 808                 if (pll == SPLL_PLL_FREQ_810MHz)
 809                         link_clock = 81000;
 810                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 811                         link_clock = 135000;
 812                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 813                         link_clock = 270000;
 814                 else {
 815                         WARN(1, "bad spll freq\n");
 816                         return;
 817                 }
 818                 break;
 819         default:
 820                 WARN(1, "bad port clock sel\n");
 821                 return;
 822         }
 823
 824         pipe_config->port_clock = link_clock * 2;
 825
 826         if (pipe_config->has_pch_encoder)
 827                 pipe_config->adjusted_mode.crtc_clock =
 828                         intel_dotclock_calculate(pipe_config->port_clock,
 829                                                  &pipe_config->fdi_m_n);
 830         else if (pipe_config->has_dp_encoder)
 831                 pipe_config->adjusted_mode.crtc_clock =
 832                         intel_dotclock_calculate(pipe_config->port_clock,
 833                                                  &pipe_config->dp_m_n);
 834         else
 835                 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
 836 }
 837
 838 void intel_ddi_clock_get(struct intel_encoder *encoder,
 839                          struct intel_crtc_config *pipe_config)
 840 {
 841         hsw_ddi_clock_get(encoder, pipe_config);
 842 }
 843
 844 static void
 845 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 846                         unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 847 {
 848         uint64_t freq2k;
 849         unsigned p, n2, r2;
 850         struct wrpll_rnp best = { 0, 0, 0 };
 851         unsigned budget;
 852
 853         freq2k = clock / 100;
 854
 855         budget = wrpll_get_budget_for_freq(clock);
 856
 857         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 858          * and directly pass the LC PLL to it. */
 859         if (freq2k == 5400000) {
 860                 *n2_out = 2;
 861                 *p_out = 1;
 862                 *r2_out = 2;
 863                 return;
 864         }
 865
 866         /*
 867          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 868          * the WR PLL.
 869          *
 870          * We want R so that REF_MIN <= Ref <= REF_MAX.
 871          * Injecting R2 = 2 * R gives:
 872          *   REF_MAX * r2 > LC_FREQ * 2 and
 873          *   REF_MIN * r2 < LC_FREQ * 2
 874          *
 875          * Which means the desired boundaries for r2 are:
 876          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 877          *
 878          */
 879         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 880              r2 <= LC_FREQ * 2 / REF_MIN;
 881              r2++) {
 882
 883                 /*
 884                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 885                  *
 886                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 887                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 888                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 889                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 890                  *
 891                  * Which means the desired boundaries for n2 are:
 892                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 893                  */
 894                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 895                      n2 <= VCO_MAX * r2 / LC_FREQ;
 896                      n2++) {
 897
 898                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 899                                 wrpll_update_rnp(freq2k, budget,
 900                                                  r2, n2, p, &best);
 901                 }
 902         }
 903
 904         *n2_out = best.n2;
 905         *p_out = best.p;
 906         *r2_out = best.r2;
 907 }
 908
 909 static bool
 910 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 911                    struct intel_encoder *intel_encoder,
 912                    int clock)
 913 {
 914         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 915                 struct intel_shared_dpll *pll;
 916                 uint32_t val;
 917                 unsigned p, n2, r2;
 918
 919                 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 920
 921                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 922                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 923                       WRPLL_DIVIDER_POST(p);
 924
 925                 intel_crtc->new_config->dpll_hw_state.wrpll = val;
 926
 927                 pll = intel_get_shared_dpll(intel_crtc);
 928                 if (pll == NULL) {
 929                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 930                                          pipe_name(intel_crtc->pipe));
 931                         return false;
 932                 }
 933
 934                 intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
 935         }
 936
 937         return true;
 938 }
 939
 940 struct skl_wrpll_params {
 941         uint32_t        dco_fraction;
 942         uint32_t        dco_integer;
 943         uint32_t        qdiv_ratio;
 944         uint32_t        qdiv_mode;
 945         uint32_t        kdiv;
 946         uint32_t        pdiv;
 947         uint32_t        central_freq;
 948 };
 949
 950 static void
 951 skl_ddi_calculate_wrpll(int clock /* in Hz */,
 952                         struct skl_wrpll_params *wrpll_params)
 953 {
 954         uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
 955         uint64_t dco_central_freq[3] = {8400000000ULL,
 956                                         9000000000ULL,
 957                                         9600000000ULL};
 958         uint32_t min_dco_deviation = 400;
 959         uint32_t min_dco_index = 3;
 960         uint32_t P0[4] = {1, 2, 3, 7};
 961         uint32_t P2[4] = {1, 2, 3, 5};
 962         bool found = false;
 963         uint32_t candidate_p = 0;
 964         uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
 965         uint32_t candidate_p2[3] = {0};
 966         uint32_t dco_central_freq_deviation[3];
 967         uint32_t i, P1, k, dco_count;
 968         bool retry_with_odd = false;
 969         uint64_t dco_freq;
 970
 971         /* Determine P0, P1 or P2 */
 972         for (dco_count = 0; dco_count < 3; dco_count++) {
 973                 found = false;
 974                 candidate_p =
 975                         div64_u64(dco_central_freq[dco_count], afe_clock);
 976                 if (retry_with_odd == false)
 977                         candidate_p = (candidate_p % 2 == 0 ?
 978                                 candidate_p : candidate_p + 1);
 979
 980                 for (P1 = 1; P1 < candidate_p; P1++) {
 981                         for (i = 0; i < 4; i++) {
 982                                 if (!(P0[i] != 1 || P1 == 1))
 983                                         continue;
 984
 985                                 for (k = 0; k < 4; k++) {
 986                                         if (P1 != 1 && P2[k] != 2)
 987                                                 continue;
 988
 989                                         if (candidate_p == P0[i] * P1 * P2[k]) {
 990                                                 /* Found possible P0, P1, P2 */
 991                                                 found = true;
 992                                                 candidate_p0[dco_count] = P0[i];
 993                                                 candidate_p1[dco_count] = P1;
 994                                                 candidate_p2[dco_count] = P2[k];
 995                                                 goto found;
 996                                         }
 997
 998                                 }
 999                         }
1000                 }
1001
1002 found:
1003                 if (found) {
1004                         dco_central_freq_deviation[dco_count] =
1005                                 div64_u64(10000 *
1006                                           abs_diff((candidate_p * afe_clock),
1007                                                    dco_central_freq[dco_count]),
1008                                           dco_central_freq[dco_count]);
1009
1010                         if (dco_central_freq_deviation[dco_count] <
1011                                 min_dco_deviation) {
1012                                 min_dco_deviation =
1013                                         dco_central_freq_deviation[dco_count];
1014                                 min_dco_index = dco_count;
1015                         }
1016                 }
1017
1018                 if (min_dco_index > 2 && dco_count == 2) {
1019                         retry_with_odd = true;
1020                         dco_count = 0;
1021                 }
1022         }
1023
1024         if (min_dco_index > 2) {
1025                 WARN(1, "No valid values found for the given pixel clock\n");
1026         } else {
1027                  wrpll_params->central_freq = dco_central_freq[min_dco_index];
1028
1029                  switch (dco_central_freq[min_dco_index]) {
1030                  case 9600000000ULL:
1031                         wrpll_params->central_freq = 0;
1032                         break;
1033                  case 9000000000ULL:
1034                         wrpll_params->central_freq = 1;
1035                         break;
1036                  case 8400000000ULL:
1037                         wrpll_params->central_freq = 3;
1038                  }
1039
1040                  switch (candidate_p0[min_dco_index]) {
1041                  case 1:
1042                         wrpll_params->pdiv = 0;
1043                         break;
1044                  case 2:
1045                         wrpll_params->pdiv = 1;
1046                         break;
1047                  case 3:
1048                         wrpll_params->pdiv = 2;
1049                         break;
1050                  case 7:
1051                         wrpll_params->pdiv = 4;
1052                         break;
1053                  default:
1054                         WARN(1, "Incorrect PDiv\n");
1055                  }
1056
1057                  switch (candidate_p2[min_dco_index]) {
1058                  case 5:
1059                         wrpll_params->kdiv = 0;
1060                         break;
1061                  case 2:
1062                         wrpll_params->kdiv = 1;
1063                         break;
1064                  case 3:
1065                         wrpll_params->kdiv = 2;
1066                         break;
1067                  case 1:
1068                         wrpll_params->kdiv = 3;
1069                         break;
1070                  default:
1071                         WARN(1, "Incorrect KDiv\n");
1072                  }
1073
1074                  wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
1075                  wrpll_params->qdiv_mode =
1076                         (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
1077
1078                  dco_freq = candidate_p0[min_dco_index] *
1079                          candidate_p1[min_dco_index] *
1080                          candidate_p2[min_dco_index] * afe_clock;
1081
1082                 /*
1083                 * Intermediate values are in Hz.
1084                 * Divide by MHz to match bsepc
1085                 */
1086                  wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
1087                  wrpll_params->dco_fraction =
1088                          div_u64(((div_u64(dco_freq, 24) -
1089                                    wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
1090
1091         }
1092 }
1093
1094
1095 static bool
1096 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1097                    struct intel_encoder *intel_encoder,
1098                    int clock)
1099 {
1100         struct intel_shared_dpll *pll;
1101         uint32_t ctrl1, cfgcr1, cfgcr2;
1102
1103         /*
1104          * See comment in intel_dpll_hw_state to understand why we always use 0
1105          * as the DPLL id in this function.
1106          */
1107
1108         ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1109
1110         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1111                 struct skl_wrpll_params wrpll_params = { 0, };
1112
1113                 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1114
1115                 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
1116
1117                 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1118                          DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1119                          wrpll_params.dco_integer;
1120
1121                 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1122                          DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1123                          DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1124                          DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1125                          wrpll_params.central_freq;
1126         } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1127                 struct drm_encoder *encoder = &intel_encoder->base;
1128                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1129
1130                 switch (intel_dp->link_bw) {
1131                 case DP_LINK_BW_1_62:
1132                         ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
1133                         break;
1134                 case DP_LINK_BW_2_7:
1135                         ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
1136                         break;
1137                 case DP_LINK_BW_5_4:
1138                         ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
1139                         break;
1140                 }
1141
1142                 cfgcr1 = cfgcr2 = 0;
1143         } else /* eDP */
1144                 return true;
1145
1146         intel_crtc->new_config->dpll_hw_state.ctrl1 = ctrl1;
1147         intel_crtc->new_config->dpll_hw_state.cfgcr1 = cfgcr1;
1148         intel_crtc->new_config->dpll_hw_state.cfgcr2 = cfgcr2;
1149
1150         pll = intel_get_shared_dpll(intel_crtc);
1151         if (pll == NULL) {
1152                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1153                                  pipe_name(intel_crtc->pipe));
1154                 return false;
1155         }
1156
1157         /* shared DPLL id 0 is DPLL 1 */
1158         intel_crtc->new_config->ddi_pll_sel = pll->id + 1;
1159
1160         return true;
1161 }
1162
1163 /*
1164  * Tries to find a *shared* PLL for the CRTC and store it in
1165  * intel_crtc->ddi_pll_sel.
1166  *
1167  * For private DPLLs, compute_config() should do the selection for us. This
1168  * function should be folded into compute_config() eventually.
1169  */
1170 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
1171 {
1172         struct drm_device *dev = intel_crtc->base.dev;
1173         struct intel_encoder *intel_encoder =
1174                 intel_ddi_get_crtc_new_encoder(intel_crtc);
1175         int clock = intel_crtc->new_config->port_clock;
1176
1177         if (IS_SKYLAKE(dev))
1178                 return skl_ddi_pll_select(intel_crtc, intel_encoder, clock);
1179         else
1180                 return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
1181 }
1182
1183 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1184 {
1185         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1187         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1188         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1189         int type = intel_encoder->type;
1190         uint32_t temp;
1191
1192         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1193                 temp = TRANS_MSA_SYNC_CLK;
1194                 switch (intel_crtc->config.pipe_bpp) {
1195                 case 18:
1196                         temp |= TRANS_MSA_6_BPC;
1197                         break;
1198                 case 24:
1199                         temp |= TRANS_MSA_8_BPC;
1200                         break;
1201                 case 30:
1202                         temp |= TRANS_MSA_10_BPC;
1203                         break;
1204                 case 36:
1205                         temp |= TRANS_MSA_12_BPC;
1206                         break;
1207                 default:
1208                         BUG();
1209                 }
1210                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1211         }
1212 }
1213
1214 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1215 {
1216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1217         struct drm_device *dev = crtc->dev;
1218         struct drm_i915_private *dev_priv = dev->dev_private;
1219         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1220         uint32_t temp;
1221         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1222         if (state == true)
1223                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1224         else
1225                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1226         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1227 }
1228
1229 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1230 {
1231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1232         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1233         struct drm_encoder *encoder = &intel_encoder->base;
1234         struct drm_device *dev = crtc->dev;
1235         struct drm_i915_private *dev_priv = dev->dev_private;
1236         enum pipe pipe = intel_crtc->pipe;
1237         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1238         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1239         int type = intel_encoder->type;
1240         uint32_t temp;
1241
1242         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1243         temp = TRANS_DDI_FUNC_ENABLE;
1244         temp |= TRANS_DDI_SELECT_PORT(port);
1245
1246         switch (intel_crtc->config.pipe_bpp) {
1247         case 18:
1248                 temp |= TRANS_DDI_BPC_6;
1249                 break;
1250         case 24:
1251                 temp |= TRANS_DDI_BPC_8;
1252                 break;
1253         case 30:
1254                 temp |= TRANS_DDI_BPC_10;
1255                 break;
1256         case 36:
1257                 temp |= TRANS_DDI_BPC_12;
1258                 break;
1259         default:
1260                 BUG();
1261         }
1262
1263         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1264                 temp |= TRANS_DDI_PVSYNC;
1265         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1266                 temp |= TRANS_DDI_PHSYNC;
1267
1268         if (cpu_transcoder == TRANSCODER_EDP) {
1269                 switch (pipe) {
1270                 case PIPE_A:
1271                         /* On Haswell, can only use the always-on power well for
1272                          * eDP when not using the panel fitter, and when not
1273                          * using motion blur mitigation (which we don't
1274                          * support). */
1275                         if (IS_HASWELL(dev) &&
1276                             (intel_crtc->config.pch_pfit.enabled ||
1277                              intel_crtc->config.pch_pfit.force_thru))
1278                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1279                         else
1280                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1281                         break;
1282                 case PIPE_B:
1283                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1284                         break;
1285                 case PIPE_C:
1286                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1287                         break;
1288                 default:
1289                         BUG();
1290                         break;
1291                 }
1292         }
1293
1294         if (type == INTEL_OUTPUT_HDMI) {
1295                 if (intel_crtc->config.has_hdmi_sink)
1296                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1297                 else
1298                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1299
1300         } else if (type == INTEL_OUTPUT_ANALOG) {
1301                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1302                 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
1303
1304         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1305                    type == INTEL_OUTPUT_EDP) {
1306                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1307
1308                 if (intel_dp->is_mst) {
1309                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1310                 } else
1311                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1312
1313                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1314         } else if (type == INTEL_OUTPUT_DP_MST) {
1315                 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1316
1317                 if (intel_dp->is_mst) {
1318                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1319                 } else
1320                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1321
1322                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1323         } else {
1324                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1325                      intel_encoder->type, pipe_name(pipe));
1326         }
1327
1328         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1329 }
1330
1331 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1332                                        enum transcoder cpu_transcoder)
1333 {
1334         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1335         uint32_t val = I915_READ(reg);
1336
1337         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1338         val |= TRANS_DDI_PORT_NONE;
1339         I915_WRITE(reg, val);
1340 }
1341
1342 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1343 {
1344         struct drm_device *dev = intel_connector->base.dev;
1345         struct drm_i915_private *dev_priv = dev->dev_private;
1346         struct intel_encoder *intel_encoder = intel_connector->encoder;
1347         int type = intel_connector->base.connector_type;
1348         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1349         enum pipe pipe = 0;
1350         enum transcoder cpu_transcoder;
1351         enum intel_display_power_domain power_domain;
1352         uint32_t tmp;
1353
1354         power_domain = intel_display_port_power_domain(intel_encoder);
1355         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1356                 return false;
1357
1358         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1359                 return false;
1360
1361         if (port == PORT_A)
1362                 cpu_transcoder = TRANSCODER_EDP;
1363         else
1364                 cpu_transcoder = (enum transcoder) pipe;
1365
1366         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1367
1368         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1369         case TRANS_DDI_MODE_SELECT_HDMI:
1370         case TRANS_DDI_MODE_SELECT_DVI:
1371                 return (type == DRM_MODE_CONNECTOR_HDMIA);
1372
1373         case TRANS_DDI_MODE_SELECT_DP_SST:
1374                 if (type == DRM_MODE_CONNECTOR_eDP)
1375                         return true;
1376                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1377         case TRANS_DDI_MODE_SELECT_DP_MST:
1378                 /* if the transcoder is in MST state then
1379                  * connector isn't connected */
1380                 return false;
1381
1382         case TRANS_DDI_MODE_SELECT_FDI:
1383                 return (type == DRM_MODE_CONNECTOR_VGA);
1384
1385         default:
1386                 return false;
1387         }
1388 }
1389
1390 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1391                             enum pipe *pipe)
1392 {
1393         struct drm_device *dev = encoder->base.dev;
1394         struct drm_i915_private *dev_priv = dev->dev_private;
1395         enum port port = intel_ddi_get_encoder_port(encoder);
1396         enum intel_display_power_domain power_domain;
1397         u32 tmp;
1398         int i;
1399
1400         power_domain = intel_display_port_power_domain(encoder);
1401         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1402                 return false;
1403
1404         tmp = I915_READ(DDI_BUF_CTL(port));
1405
1406         if (!(tmp & DDI_BUF_CTL_ENABLE))
1407                 return false;
1408
1409         if (port == PORT_A) {
1410                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1411
1412                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1413                 case TRANS_DDI_EDP_INPUT_A_ON:
1414                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1415                         *pipe = PIPE_A;
1416                         break;
1417                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1418                         *pipe = PIPE_B;
1419                         break;
1420                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1421                         *pipe = PIPE_C;
1422                         break;
1423                 }
1424
1425                 return true;
1426         } else {
1427                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1428                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1429
1430                         if ((tmp & TRANS_DDI_PORT_MASK)
1431                             == TRANS_DDI_SELECT_PORT(port)) {
1432                                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1433                                         return false;
1434
1435                                 *pipe = i;
1436                                 return true;
1437                         }
1438                 }
1439         }
1440
1441         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1442
1443         return false;
1444 }
1445
1446 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1447 {
1448         struct drm_crtc *crtc = &intel_crtc->base;
1449         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1450         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1451         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1452         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1453
1454         if (cpu_transcoder != TRANSCODER_EDP)
1455                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1456                            TRANS_CLK_SEL_PORT(port));
1457 }
1458
1459 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1460 {
1461         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1462         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1463
1464         if (cpu_transcoder != TRANSCODER_EDP)
1465                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1466                            TRANS_CLK_SEL_DISABLED);
1467 }
1468
1469 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1470 {
1471         struct drm_encoder *encoder = &intel_encoder->base;
1472         struct drm_device *dev = encoder->dev;
1473         struct drm_i915_private *dev_priv = dev->dev_private;
1474         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1475         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1476         int type = intel_encoder->type;
1477
1478         if (type == INTEL_OUTPUT_EDP) {
1479                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1480                 intel_edp_panel_on(intel_dp);
1481         }
1482
1483         if (IS_SKYLAKE(dev)) {
1484                 uint32_t dpll = crtc->config.ddi_pll_sel;
1485                 uint32_t val;
1486
1487                 /*
1488                  * DPLL0 is used for eDP and is the only "private" DPLL (as
1489                  * opposed to shared) on SKL
1490                  */
1491                 if (type == INTEL_OUTPUT_EDP) {
1492                         WARN_ON(dpll != SKL_DPLL0);
1493
1494                         val = I915_READ(DPLL_CTRL1);
1495
1496                         val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1497                                  DPLL_CTRL1_SSC(dpll) |
1498                                  DPLL_CRTL1_LINK_RATE_MASK(dpll));
1499                         val |= crtc->config.dpll_hw_state.ctrl1 << (dpll * 6);
1500
1501                         I915_WRITE(DPLL_CTRL1, val);
1502                         POSTING_READ(DPLL_CTRL1);
1503                 }
1504
1505                 /* DDI -> PLL mapping  */
1506                 val = I915_READ(DPLL_CTRL2);
1507
1508                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1509                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1510                 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1511                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1512
1513                 I915_WRITE(DPLL_CTRL2, val);
1514
1515         } else {
1516                 WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1517                 I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1518         }
1519
1520         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1521                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1522
1523                 intel_ddi_init_dp_buf_reg(intel_encoder);
1524
1525                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1526                 intel_dp_start_link_train(intel_dp);
1527                 intel_dp_complete_link_train(intel_dp);
1528                 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
1529                         intel_dp_stop_link_train(intel_dp);
1530         } else if (type == INTEL_OUTPUT_HDMI) {
1531                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1532
1533                 intel_hdmi->set_infoframes(encoder,
1534                                            crtc->config.has_hdmi_sink,
1535                                            &crtc->config.adjusted_mode);
1536         }
1537 }
1538
1539 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1540 {
1541         struct drm_encoder *encoder = &intel_encoder->base;
1542         struct drm_device *dev = encoder->dev;
1543         struct drm_i915_private *dev_priv = dev->dev_private;
1544         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1545         int type = intel_encoder->type;
1546         uint32_t val;
1547         bool wait = false;
1548
1549         val = I915_READ(DDI_BUF_CTL(port));
1550         if (val & DDI_BUF_CTL_ENABLE) {
1551                 val &= ~DDI_BUF_CTL_ENABLE;
1552                 I915_WRITE(DDI_BUF_CTL(port), val);
1553                 wait = true;
1554         }
1555
1556         val = I915_READ(DP_TP_CTL(port));
1557         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1558         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1559         I915_WRITE(DP_TP_CTL(port), val);
1560
1561         if (wait)
1562                 intel_wait_ddi_buf_idle(dev_priv, port);
1563
1564         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1565                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1566                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1567                 intel_edp_panel_vdd_on(intel_dp);
1568                 intel_edp_panel_off(intel_dp);
1569         }
1570
1571         if (IS_SKYLAKE(dev))
1572                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1573                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
1574         else
1575                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1576 }
1577
1578 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1579 {
1580         struct drm_encoder *encoder = &intel_encoder->base;
1581         struct drm_crtc *crtc = encoder->crtc;
1582         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1583         struct drm_device *dev = encoder->dev;
1584         struct drm_i915_private *dev_priv = dev->dev_private;
1585         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1586         int type = intel_encoder->type;
1587
1588         if (type == INTEL_OUTPUT_HDMI) {
1589                 struct intel_digital_port *intel_dig_port =
1590                         enc_to_dig_port(encoder);
1591
1592                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1593                  * are ignored so nothing special needs to be done besides
1594                  * enabling the port.
1595                  */
1596                 I915_WRITE(DDI_BUF_CTL(port),
1597                            intel_dig_port->saved_port_bits |
1598                            DDI_BUF_CTL_ENABLE);
1599         } else if (type == INTEL_OUTPUT_EDP) {
1600                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1601
1602                 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1603                         intel_dp_stop_link_train(intel_dp);
1604
1605                 intel_edp_backlight_on(intel_dp);
1606                 intel_psr_enable(intel_dp);
1607         }
1608
1609         if (intel_crtc->config.has_audio) {
1610                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1611                 intel_audio_codec_enable(intel_encoder);
1612         }
1613 }
1614
1615 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1616 {
1617         struct drm_encoder *encoder = &intel_encoder->base;
1618         struct drm_crtc *crtc = encoder->crtc;
1619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1620         int type = intel_encoder->type;
1621         struct drm_device *dev = encoder->dev;
1622         struct drm_i915_private *dev_priv = dev->dev_private;
1623
1624         if (intel_crtc->config.has_audio) {
1625                 intel_audio_codec_disable(intel_encoder);
1626                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1627         }
1628
1629         if (type == INTEL_OUTPUT_EDP) {
1630                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1631
1632                 intel_psr_disable(intel_dp);
1633                 intel_edp_backlight_off(intel_dp);
1634         }
1635 }
1636
1637 static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
1638 {
1639         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
1640         uint32_t cdctl = I915_READ(CDCLK_CTL);
1641         uint32_t linkrate;
1642
1643         if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
1644                 WARN(1, "LCPLL1 not enabled\n");
1645                 return 24000; /* 24MHz is the cd freq with NSSC ref */
1646         }
1647
1648         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
1649                 return 540000;
1650
1651         linkrate = (I915_READ(DPLL_CTRL1) &
1652                     DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1653
1654         if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
1655             linkrate == DPLL_CRTL1_LINK_RATE_1080) {
1656                 /* vco 8640 */
1657                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1658                 case CDCLK_FREQ_450_432:
1659                         return 432000;
1660                 case CDCLK_FREQ_337_308:
1661                         return 308570;
1662                 case CDCLK_FREQ_675_617:
1663                         return 617140;
1664                 default:
1665                         WARN(1, "Unknown cd freq selection\n");
1666                 }
1667         } else {
1668                 /* vco 8100 */
1669                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1670                 case CDCLK_FREQ_450_432:
1671                         return 450000;
1672                 case CDCLK_FREQ_337_308:
1673                         return 337500;
1674                 case CDCLK_FREQ_675_617:
1675                         return 675000;
1676                 default:
1677                         WARN(1, "Unknown cd freq selection\n");
1678                 }
1679         }
1680
1681         /* error case, do as if DPLL0 isn't enabled */
1682         return 24000;
1683 }
1684
1685 static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1686 {
1687         uint32_t lcpll = I915_READ(LCPLL_CTL);
1688         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1689
1690         if (lcpll & LCPLL_CD_SOURCE_FCLK)
1691                 return 800000;
1692         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1693                 return 450000;
1694         else if (freq == LCPLL_CLK_FREQ_450)
1695                 return 450000;
1696         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1697                 return 540000;
1698         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1699                 return 337500;
1700         else
1701                 return 675000;
1702 }
1703
1704 static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1705 {
1706         struct drm_device *dev = dev_priv->dev;
1707         uint32_t lcpll = I915_READ(LCPLL_CTL);
1708         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1709
1710         if (lcpll & LCPLL_CD_SOURCE_FCLK)
1711                 return 800000;
1712         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1713                 return 450000;
1714         else if (freq == LCPLL_CLK_FREQ_450)
1715                 return 450000;
1716         else if (IS_HSW_ULT(dev))
1717                 return 337500;
1718         else
1719                 return 540000;
1720 }
1721
1722 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1723 {
1724         struct drm_device *dev = dev_priv->dev;
1725
1726         if (IS_SKYLAKE(dev))
1727                 return skl_get_cdclk_freq(dev_priv);
1728
1729         if (IS_BROADWELL(dev))
1730                 return bdw_get_cdclk_freq(dev_priv);
1731
1732         /* Haswell */
1733         return hsw_get_cdclk_freq(dev_priv);
1734 }
1735
1736 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1737                                struct intel_shared_dpll *pll)
1738 {
1739         I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
1740         POSTING_READ(WRPLL_CTL(pll->id));
1741         udelay(20);
1742 }
1743
1744 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1745                                 struct intel_shared_dpll *pll)
1746 {
1747         uint32_t val;
1748
1749         val = I915_READ(WRPLL_CTL(pll->id));
1750         I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1751         POSTING_READ(WRPLL_CTL(pll->id));
1752 }
1753
1754 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1755                                      struct intel_shared_dpll *pll,
1756                                      struct intel_dpll_hw_state *hw_state)
1757 {
1758         uint32_t val;
1759
1760         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1761                 return false;
1762
1763         val = I915_READ(WRPLL_CTL(pll->id));
1764         hw_state->wrpll = val;
1765
1766         return val & WRPLL_PLL_ENABLE;
1767 }
1768
1769 static const char * const hsw_ddi_pll_names[] = {
1770         "WRPLL 1",
1771         "WRPLL 2",
1772 };
1773
1774 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1775 {
1776         int i;
1777
1778         dev_priv->num_shared_dpll = 2;
1779
1780         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1781                 dev_priv->shared_dplls[i].id = i;
1782                 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1783                 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1784                 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1785                 dev_priv->shared_dplls[i].get_hw_state =
1786                         hsw_ddi_pll_get_hw_state;
1787         }
1788 }
1789
1790 static const char * const skl_ddi_pll_names[] = {
1791         "DPLL 1",
1792         "DPLL 2",
1793         "DPLL 3",
1794 };
1795
1796 struct skl_dpll_regs {
1797         u32 ctl, cfgcr1, cfgcr2;
1798 };
1799
1800 /* this array is indexed by the *shared* pll id */
1801 static const struct skl_dpll_regs skl_dpll_regs[3] = {
1802         {
1803                 /* DPLL 1 */
1804                 .ctl = LCPLL2_CTL,
1805                 .cfgcr1 = DPLL1_CFGCR1,
1806                 .cfgcr2 = DPLL1_CFGCR2,
1807         },
1808         {
1809                 /* DPLL 2 */
1810                 .ctl = WRPLL_CTL1,
1811                 .cfgcr1 = DPLL2_CFGCR1,
1812                 .cfgcr2 = DPLL2_CFGCR2,
1813         },
1814         {
1815                 /* DPLL 3 */
1816                 .ctl = WRPLL_CTL2,
1817                 .cfgcr1 = DPLL3_CFGCR1,
1818                 .cfgcr2 = DPLL3_CFGCR2,
1819         },
1820 };
1821
1822 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1823                                struct intel_shared_dpll *pll)
1824 {
1825         uint32_t val;
1826         unsigned int dpll;
1827         const struct skl_dpll_regs *regs = skl_dpll_regs;
1828
1829         /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1830         dpll = pll->id + 1;
1831
1832         val = I915_READ(DPLL_CTRL1);
1833
1834         val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
1835                  DPLL_CRTL1_LINK_RATE_MASK(dpll));
1836         val |= pll->config.hw_state.ctrl1 << (dpll * 6);
1837
1838         I915_WRITE(DPLL_CTRL1, val);
1839         POSTING_READ(DPLL_CTRL1);
1840
1841         I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
1842         I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
1843         POSTING_READ(regs[pll->id].cfgcr1);
1844         POSTING_READ(regs[pll->id].cfgcr2);
1845
1846         /* the enable bit is always bit 31 */
1847         I915_WRITE(regs[pll->id].ctl,
1848                    I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
1849
1850         if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
1851                 DRM_ERROR("DPLL %d not locked\n", dpll);
1852 }
1853
1854 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
1855                                 struct intel_shared_dpll *pll)
1856 {
1857         const struct skl_dpll_regs *regs = skl_dpll_regs;
1858
1859         /* the enable bit is always bit 31 */
1860         I915_WRITE(regs[pll->id].ctl,
1861                    I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
1862         POSTING_READ(regs[pll->id].ctl);
1863 }
1864
1865 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1866                                      struct intel_shared_dpll *pll,
1867                                      struct intel_dpll_hw_state *hw_state)
1868 {
1869         uint32_t val;
1870         unsigned int dpll;
1871         const struct skl_dpll_regs *regs = skl_dpll_regs;
1872
1873         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1874                 return false;
1875
1876         /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1877         dpll = pll->id + 1;
1878
1879         val = I915_READ(regs[pll->id].ctl);
1880         if (!(val & LCPLL_PLL_ENABLE))
1881                 return false;
1882
1883         val = I915_READ(DPLL_CTRL1);
1884         hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
1885
1886         /* avoid reading back stale values if HDMI mode is not enabled */
1887         if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
1888                 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
1889                 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
1890         }
1891
1892         return true;
1893 }
1894
1895 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
1896 {
1897         int i;
1898
1899         dev_priv->num_shared_dpll = 3;
1900
1901         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1902                 dev_priv->shared_dplls[i].id = i;
1903                 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
1904                 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
1905                 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
1906                 dev_priv->shared_dplls[i].get_hw_state =
1907                         skl_ddi_pll_get_hw_state;
1908         }
1909 }
1910
1911 void intel_ddi_pll_init(struct drm_device *dev)
1912 {
1913         struct drm_i915_private *dev_priv = dev->dev_private;
1914         uint32_t val = I915_READ(LCPLL_CTL);
1915
1916         if (IS_SKYLAKE(dev))
1917                 skl_shared_dplls_init(dev_priv);
1918         else
1919                 hsw_shared_dplls_init(dev_priv);
1920
1921         DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1922                       intel_ddi_get_cdclk_freq(dev_priv));
1923
1924         if (IS_SKYLAKE(dev)) {
1925                 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
1926                         DRM_ERROR("LCPLL1 is disabled\n");
1927         } else {
1928                 /*
1929                  * The LCPLL register should be turned on by the BIOS. For now
1930                  * let's just check its state and print errors in case
1931                  * something is wrong.  Don't even try to turn it on.
1932                  */
1933
1934                 if (val & LCPLL_CD_SOURCE_FCLK)
1935                         DRM_ERROR("CDCLK source is not LCPLL\n");
1936
1937                 if (val & LCPLL_PLL_DISABLE)
1938                         DRM_ERROR("LCPLL is disabled\n");
1939         }
1940 }
1941
1942 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1943 {
1944         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1945         struct intel_dp *intel_dp = &intel_dig_port->dp;
1946         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1947         enum port port = intel_dig_port->port;
1948         uint32_t val;
1949         bool wait = false;
1950
1951         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1952                 val = I915_READ(DDI_BUF_CTL(port));
1953                 if (val & DDI_BUF_CTL_ENABLE) {
1954                         val &= ~DDI_BUF_CTL_ENABLE;
1955                         I915_WRITE(DDI_BUF_CTL(port), val);
1956                         wait = true;
1957                 }
1958
1959                 val = I915_READ(DP_TP_CTL(port));
1960                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1961                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1962                 I915_WRITE(DP_TP_CTL(port), val);
1963                 POSTING_READ(DP_TP_CTL(port));
1964
1965                 if (wait)
1966                         intel_wait_ddi_buf_idle(dev_priv, port);
1967         }
1968
1969         val = DP_TP_CTL_ENABLE |
1970               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1971         if (intel_dp->is_mst)
1972                 val |= DP_TP_CTL_MODE_MST;
1973         else {
1974                 val |= DP_TP_CTL_MODE_SST;
1975                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1976                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1977         }
1978         I915_WRITE(DP_TP_CTL(port), val);
1979         POSTING_READ(DP_TP_CTL(port));
1980
1981         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1982         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1983         POSTING_READ(DDI_BUF_CTL(port));
1984
1985         udelay(600);
1986 }
1987
1988 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1989 {
1990         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1991         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1992         uint32_t val;
1993
1994         intel_ddi_post_disable(intel_encoder);
1995
1996         val = I915_READ(_FDI_RXA_CTL);
1997         val &= ~FDI_RX_ENABLE;
1998         I915_WRITE(_FDI_RXA_CTL, val);
1999
2000         val = I915_READ(_FDI_RXA_MISC);
2001         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2002         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2003         I915_WRITE(_FDI_RXA_MISC, val);
2004
2005         val = I915_READ(_FDI_RXA_CTL);
2006         val &= ~FDI_PCDCLK;
2007         I915_WRITE(_FDI_RXA_CTL, val);
2008
2009         val = I915_READ(_FDI_RXA_CTL);
2010         val &= ~FDI_RX_PLL_ENABLE;
2011         I915_WRITE(_FDI_RXA_CTL, val);
2012 }
2013
2014 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
2015 {
2016         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
2017         int type = intel_dig_port->base.type;
2018
2019         if (type != INTEL_OUTPUT_DISPLAYPORT &&
2020             type != INTEL_OUTPUT_EDP &&
2021             type != INTEL_OUTPUT_UNKNOWN) {
2022                 return;
2023         }
2024
2025         intel_dp_hot_plug(intel_encoder);
2026 }
2027
2028 void intel_ddi_get_config(struct intel_encoder *encoder,
2029                           struct intel_crtc_config *pipe_config)
2030 {
2031         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2032         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2033         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
2034         u32 temp, flags = 0;
2035         struct drm_device *dev = dev_priv->dev;
2036
2037         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2038         if (temp & TRANS_DDI_PHSYNC)
2039                 flags |= DRM_MODE_FLAG_PHSYNC;
2040         else
2041                 flags |= DRM_MODE_FLAG_NHSYNC;
2042         if (temp & TRANS_DDI_PVSYNC)
2043                 flags |= DRM_MODE_FLAG_PVSYNC;
2044         else
2045                 flags |= DRM_MODE_FLAG_NVSYNC;
2046
2047         pipe_config->adjusted_mode.flags |= flags;
2048
2049         switch (temp & TRANS_DDI_BPC_MASK) {
2050         case TRANS_DDI_BPC_6:
2051                 pipe_config->pipe_bpp = 18;
2052                 break;
2053         case TRANS_DDI_BPC_8:
2054                 pipe_config->pipe_bpp = 24;
2055                 break;
2056         case TRANS_DDI_BPC_10:
2057                 pipe_config->pipe_bpp = 30;
2058                 break;
2059         case TRANS_DDI_BPC_12:
2060                 pipe_config->pipe_bpp = 36;
2061                 break;
2062         default:
2063                 break;
2064         }
2065
2066         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2067         case TRANS_DDI_MODE_SELECT_HDMI:
2068                 pipe_config->has_hdmi_sink = true;
2069         case TRANS_DDI_MODE_SELECT_DVI:
2070         case TRANS_DDI_MODE_SELECT_FDI:
2071                 break;
2072         case TRANS_DDI_MODE_SELECT_DP_SST:
2073         case TRANS_DDI_MODE_SELECT_DP_MST:
2074                 pipe_config->has_dp_encoder = true;
2075                 intel_dp_get_m_n(intel_crtc, pipe_config);
2076                 break;
2077         default:
2078                 break;
2079         }
2080
2081         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2082                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2083                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2084                         pipe_config->has_audio = true;
2085         }
2086
2087         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2088             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2089                 /*
2090                  * This is a big fat ugly hack.
2091                  *
2092                  * Some machines in UEFI boot mode provide us a VBT that has 18
2093                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2094                  * unknown we fail to light up. Yet the same BIOS boots up with
2095                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2096                  * max, not what it tells us to use.
2097                  *
2098                  * Note: This will still be broken if the eDP panel is not lit
2099                  * up by the BIOS, and thus we can't get the mode at module
2100                  * load.
2101                  */
2102                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2103                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2104                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2105         }
2106
2107         if (INTEL_INFO(dev)->gen <= 8)
2108                 hsw_ddi_clock_get(encoder, pipe_config);
2109         else
2110                 skl_ddi_clock_get(encoder, pipe_config);
2111 }
2112
2113 static void intel_ddi_destroy(struct drm_encoder *encoder)
2114 {
2115         /* HDMI has nothing special to destroy, so we can go with this. */
2116         intel_dp_encoder_destroy(encoder);
2117 }
2118
2119 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2120                                      struct intel_crtc_config *pipe_config)
2121 {
2122         int type = encoder->type;
2123         int port = intel_ddi_get_encoder_port(encoder);
2124
2125         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2126
2127         if (port == PORT_A)
2128                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2129
2130         if (type == INTEL_OUTPUT_HDMI)
2131                 return intel_hdmi_compute_config(encoder, pipe_config);
2132         else
2133                 return intel_dp_compute_config(encoder, pipe_config);
2134 }
2135
2136 static const struct drm_encoder_funcs intel_ddi_funcs = {
2137         .destroy = intel_ddi_destroy,
2138 };
2139
2140 static struct intel_connector *
2141 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2142 {
2143         struct intel_connector *connector;
2144         enum port port = intel_dig_port->port;
2145
2146         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
2147         if (!connector)
2148                 return NULL;
2149
2150         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2151         if (!intel_dp_init_connector(intel_dig_port, connector)) {
2152                 kfree(connector);
2153                 return NULL;
2154         }
2155
2156         return connector;
2157 }
2158
2159 static struct intel_connector *
2160 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2161 {
2162         struct intel_connector *connector;
2163         enum port port = intel_dig_port->port;
2164
2165         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
2166         if (!connector)
2167                 return NULL;
2168
2169         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2170         intel_hdmi_init_connector(intel_dig_port, connector);
2171
2172         return connector;
2173 }
2174
2175 void intel_ddi_init(struct drm_device *dev, enum port port)
2176 {
2177         struct drm_i915_private *dev_priv = dev->dev_private;
2178         struct intel_digital_port *intel_dig_port;
2179         struct intel_encoder *intel_encoder;
2180         struct drm_encoder *encoder;
2181         bool init_hdmi, init_dp;
2182
2183         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2184                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2185         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2186         if (!init_dp && !init_hdmi) {
2187                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
2188                               port_name(port));
2189                 init_hdmi = true;
2190                 init_dp = true;
2191         }
2192
2193         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2194         if (!intel_dig_port)
2195                 return;
2196
2197         intel_encoder = &intel_dig_port->base;
2198         encoder = &intel_encoder->base;
2199
2200         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2201                          DRM_MODE_ENCODER_TMDS);
2202
2203         intel_encoder->compute_config = intel_ddi_compute_config;
2204         intel_encoder->enable = intel_enable_ddi;
2205         intel_encoder->pre_enable = intel_ddi_pre_enable;
2206         intel_encoder->disable = intel_disable_ddi;
2207         intel_encoder->post_disable = intel_ddi_post_disable;
2208         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2209         intel_encoder->get_config = intel_ddi_get_config;
2210
2211         intel_dig_port->port = port;
2212         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2213                                           (DDI_BUF_PORT_REVERSAL |
2214                                            DDI_A_4_LANES);
2215
2216         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2217         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2218         intel_encoder->cloneable = 0;
2219         intel_encoder->hot_plug = intel_ddi_hot_plug;
2220
2221         if (init_dp) {
2222                 if (!intel_ddi_init_dp_connector(intel_dig_port))
2223                         goto err;
2224
2225                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2226                 dev_priv->hpd_irq_port[port] = intel_dig_port;
2227         }
2228
2229         /* In theory we don't need the encoder->type check, but leave it just in
2230          * case we have some really bad VBTs... */
2231         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2232                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2233                         goto err;
2234         }
2235
2236         return;
2237
2238 err:
2239         drm_encoder_cleanup(encoder);
2240         kfree(intel_dig_port);
2241 }