drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  32  * them for both DP and FDI transports, allowing those ports to
  33  * automatically adapt to HDMI connections as well
  34  */
  35 static const u32 hsw_ddi_translations_dp[] = {
  36         0x00FFFFFF, 0x0006000E,         /* DP parameters */
  37         0x00D75FFF, 0x0005000A,
  38         0x00C30FFF, 0x00040006,
  39         0x80AAAFFF, 0x000B0000,
  40         0x00FFFFFF, 0x0005000A,
  41         0x00D75FFF, 0x000C0004,
  42         0x80C30FFF, 0x000B0000,
  43         0x00FFFFFF, 0x00040006,
  44         0x80D75FFF, 0x000B0000,
  45 };
  46
  47 static const u32 hsw_ddi_translations_fdi[] = {
  48         0x00FFFFFF, 0x0007000E,         /* FDI parameters */
  49         0x00D75FFF, 0x000F000A,
  50         0x00C30FFF, 0x00060006,
  51         0x00AAAFFF, 0x001E0000,
  52         0x00FFFFFF, 0x000F000A,
  53         0x00D75FFF, 0x00160004,
  54         0x00C30FFF, 0x001E0000,
  55         0x00FFFFFF, 0x00060006,
  56         0x00D75FFF, 0x001E0000,
  57 };
  58
  59 static const u32 hsw_ddi_translations_hdmi[] = {
  60                                 /* Idx  NT mV diff      T mV diff       db  */
  61         0x00FFFFFF, 0x0006000E, /* 0:   400             400             0   */
  62         0x00E79FFF, 0x000E000C, /* 1:   400             500             2   */
  63         0x00D75FFF, 0x0005000A, /* 2:   400             600             3.5 */
  64         0x00FFFFFF, 0x0005000A, /* 3:   600             600             0   */
  65         0x00E79FFF, 0x001D0007, /* 4:   600             750             2   */
  66         0x00D75FFF, 0x000C0004, /* 5:   600             900             3.5 */
  67         0x00FFFFFF, 0x00040006, /* 6:   800             800             0   */
  68         0x80E79FFF, 0x00030002, /* 7:   800             1000            2   */
  69         0x00FFFFFF, 0x00140005, /* 8:   850             850             0   */
  70         0x00FFFFFF, 0x000C0004, /* 9:   900             900             0   */
  71         0x00FFFFFF, 0x001C0003, /* 10:  950             950             0   */
  72         0x80FFFFFF, 0x00030002, /* 11:  1000            1000            0   */
  73 };
  74
  75 static const u32 bdw_ddi_translations_edp[] = {
  76         0x00FFFFFF, 0x00000012,         /* eDP parameters */
  77         0x00EBAFFF, 0x00020011,
  78         0x00C71FFF, 0x0006000F,
  79         0x00AAAFFF, 0x000E000A,
  80         0x00FFFFFF, 0x00020011,
  81         0x00DB6FFF, 0x0005000F,
  82         0x00BEEFFF, 0x000A000C,
  83         0x00FFFFFF, 0x0005000F,
  84         0x00DB6FFF, 0x000A000C,
  85         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
  86 };
  87
  88 static const u32 bdw_ddi_translations_dp[] = {
  89         0x00FFFFFF, 0x0007000E,         /* DP parameters */
  90         0x00D75FFF, 0x000E000A,
  91         0x00BEFFFF, 0x00140006,
  92         0x80B2CFFF, 0x001B0002,
  93         0x00FFFFFF, 0x000E000A,
  94         0x00D75FFF, 0x00180004,
  95         0x80CB2FFF, 0x001B0002,
  96         0x00F7DFFF, 0x00180004,
  97         0x80D75FFF, 0x001B0002,
  98         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
  99 };
 100
 101 static const u32 bdw_ddi_translations_fdi[] = {
 102         0x00FFFFFF, 0x0001000E,         /* FDI parameters */
 103         0x00D75FFF, 0x0004000A,
 104         0x00C30FFF, 0x00070006,
 105         0x00AAAFFF, 0x000C0000,
 106         0x00FFFFFF, 0x0004000A,
 107         0x00D75FFF, 0x00090004,
 108         0x00C30FFF, 0x000C0000,
 109         0x00FFFFFF, 0x00070006,
 110         0x00D75FFF, 0x000C0000,
 111         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
 112 };
 113
 114 static const u32 bdw_ddi_translations_hdmi[] = {
 115                                 /* Idx  NT mV diff      T mV diff       db  */
 116         0x00FFFFFF, 0x0007000E, /* 0:   400             400             0   */
 117         0x00D75FFF, 0x000E000A, /* 1:   400             600             3.5 */
 118         0x00BEFFFF, 0x00140006, /* 2:   400             800             6   */
 119         0x00FFFFFF, 0x0009000D, /* 3:   450             450             0   */
 120         0x00FFFFFF, 0x000E000A, /* 4:   600             600             0   */
 121         0x00D7FFFF, 0x00140006, /* 5:   600             800             2.5 */
 122         0x80CB2FFF, 0x001B0002, /* 6:   600             1000            4.5 */
 123         0x00FFFFFF, 0x00140006, /* 7:   800             800             0   */
 124         0x80E79FFF, 0x001B0002, /* 8:   800             1000            2   */
 125         0x80FFFFFF, 0x001B0002, /* 9:   1000            1000            0   */
 126 };
 127
 128 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 129 {
 130         struct drm_encoder *encoder = &intel_encoder->base;
 131         int type = intel_encoder->type;
 132
 133         if (type == INTEL_OUTPUT_DP_MST) {
 134                 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
 135                 return intel_dig_port->port;
 136         } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 137             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 138                 struct intel_digital_port *intel_dig_port =
 139                         enc_to_dig_port(encoder);
 140                 return intel_dig_port->port;
 141
 142         } else if (type == INTEL_OUTPUT_ANALOG) {
 143                 return PORT_E;
 144
 145         } else {
 146                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
 147                 BUG();
 148         }
 149 }
 150
 151 /*
 152  * Starting with Haswell, DDI port buffers must be programmed with correct
 153  * values in advance. The buffer values are different for FDI and DP modes,
 154  * but the HDMI/DVI fields are shared among those. So we program the DDI
 155  * in either FDI or DP modes only, as HDMI connections will work with both
 156  * of those
 157  */
 158 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 159 {
 160         struct drm_i915_private *dev_priv = dev->dev_private;
 161         u32 reg;
 162         int i, n_hdmi_entries, hdmi_800mV_0dB;
 163         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 164         const u32 *ddi_translations_fdi;
 165         const u32 *ddi_translations_dp;
 166         const u32 *ddi_translations_edp;
 167         const u32 *ddi_translations_hdmi;
 168         const u32 *ddi_translations;
 169
 170         if (IS_BROADWELL(dev)) {
 171                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 172                 ddi_translations_dp = bdw_ddi_translations_dp;
 173                 ddi_translations_edp = bdw_ddi_translations_edp;
 174                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 175                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 176                 hdmi_800mV_0dB = 7;
 177         } else if (IS_HASWELL(dev)) {
 178                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 179                 ddi_translations_dp = hsw_ddi_translations_dp;
 180                 ddi_translations_edp = hsw_ddi_translations_dp;
 181                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 182                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 183                 hdmi_800mV_0dB = 6;
 184         } else {
 185                 WARN(1, "ddi translation table missing\n");
 186                 ddi_translations_edp = bdw_ddi_translations_dp;
 187                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 188                 ddi_translations_dp = bdw_ddi_translations_dp;
 189                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 190                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 191                 hdmi_800mV_0dB = 7;
 192         }
 193
 194         switch (port) {
 195         case PORT_A:
 196                 ddi_translations = ddi_translations_edp;
 197                 break;
 198         case PORT_B:
 199         case PORT_C:
 200                 ddi_translations = ddi_translations_dp;
 201                 break;
 202         case PORT_D:
 203                 if (intel_dp_is_edp(dev, PORT_D))
 204                         ddi_translations = ddi_translations_edp;
 205                 else
 206                         ddi_translations = ddi_translations_dp;
 207                 break;
 208         case PORT_E:
 209                 ddi_translations = ddi_translations_fdi;
 210                 break;
 211         default:
 212                 BUG();
 213         }
 214
 215         for (i = 0, reg = DDI_BUF_TRANS(port);
 216              i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 217                 I915_WRITE(reg, ddi_translations[i]);
 218                 reg += 4;
 219         }
 220
 221         /* Choose a good default if VBT is badly populated */
 222         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 223             hdmi_level >= n_hdmi_entries)
 224                 hdmi_level = hdmi_800mV_0dB;
 225
 226         /* Entry 9 is for HDMI: */
 227         for (i = 0; i < 2; i++) {
 228                 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level * 2 + i]);
 229                 reg += 4;
 230         }
 231 }
 232
 233 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 234  * mode and port E for FDI.
 235  */
 236 void intel_prepare_ddi(struct drm_device *dev)
 237 {
 238         int port;
 239
 240         if (!HAS_DDI(dev))
 241                 return;
 242
 243         for (port = PORT_A; port <= PORT_E; port++)
 244                 intel_prepare_ddi_buffers(dev, port);
 245 }
 246
 247 static const long hsw_ddi_buf_ctl_values[] = {
 248         DDI_BUF_EMP_400MV_0DB_HSW,
 249         DDI_BUF_EMP_400MV_3_5DB_HSW,
 250         DDI_BUF_EMP_400MV_6DB_HSW,
 251         DDI_BUF_EMP_400MV_9_5DB_HSW,
 252         DDI_BUF_EMP_600MV_0DB_HSW,
 253         DDI_BUF_EMP_600MV_3_5DB_HSW,
 254         DDI_BUF_EMP_600MV_6DB_HSW,
 255         DDI_BUF_EMP_800MV_0DB_HSW,
 256         DDI_BUF_EMP_800MV_3_5DB_HSW
 257 };
 258
 259 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 260                                     enum port port)
 261 {
 262         uint32_t reg = DDI_BUF_CTL(port);
 263         int i;
 264
 265         for (i = 0; i < 8; i++) {
 266                 udelay(1);
 267                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 268                         return;
 269         }
 270         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 271 }
 272
 273 /* Starting with Haswell, different DDI ports can work in FDI mode for
 274  * connection to the PCH-located connectors. For this, it is necessary to train
 275  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 276  *
 277  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 278  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 279  * DDI A (which is used for eDP)
 280  */
 281
 282 void hsw_fdi_link_train(struct drm_crtc *crtc)
 283 {
 284         struct drm_device *dev = crtc->dev;
 285         struct drm_i915_private *dev_priv = dev->dev_private;
 286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 287         u32 temp, i, rx_ctl_val;
 288
 289         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 290          * mode set "sequence for CRT port" document:
 291          * - TP1 to TP2 time with the default value
 292          * - FDI delay to 90h
 293          *
 294          * WaFDIAutoLinkSetTimingOverrride:hsw
 295          */
 296         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 297                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 298                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 299
 300         /* Enable the PCH Receiver FDI PLL */
 301         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 302                      FDI_RX_PLL_ENABLE |
 303                      FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
 304         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 305         POSTING_READ(_FDI_RXA_CTL);
 306         udelay(220);
 307
 308         /* Switch from Rawclk to PCDclk */
 309         rx_ctl_val |= FDI_PCDCLK;
 310         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 311
 312         /* Configure Port Clock Select */
 313         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
 314         WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
 315
 316         /* Start the training iterating through available voltages and emphasis,
 317          * testing each value twice. */
 318         for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
 319                 /* Configure DP_TP_CTL with auto-training */
 320                 I915_WRITE(DP_TP_CTL(PORT_E),
 321                                         DP_TP_CTL_FDI_AUTOTRAIN |
 322                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 323                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 324                                         DP_TP_CTL_ENABLE);
 325
 326                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 327                  * DDI E does not support port reversal, the functionality is
 328                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 329                  * port reversal bit */
 330                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 331                            DDI_BUF_CTL_ENABLE |
 332                            ((intel_crtc->config.fdi_lanes - 1) << 1) |
 333                            hsw_ddi_buf_ctl_values[i / 2]);
 334                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 335
 336                 udelay(600);
 337
 338                 /* Program PCH FDI Receiver TU */
 339                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 340
 341                 /* Enable PCH FDI Receiver with auto-training */
 342                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 343                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 344                 POSTING_READ(_FDI_RXA_CTL);
 345
 346                 /* Wait for FDI receiver lane calibration */
 347                 udelay(30);
 348
 349                 /* Unset FDI_RX_MISC pwrdn lanes */
 350                 temp = I915_READ(_FDI_RXA_MISC);
 351                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 352                 I915_WRITE(_FDI_RXA_MISC, temp);
 353                 POSTING_READ(_FDI_RXA_MISC);
 354
 355                 /* Wait for FDI auto training time */
 356                 udelay(5);
 357
 358                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 359                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 360                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 361
 362                         /* Enable normal pixel sending for FDI */
 363                         I915_WRITE(DP_TP_CTL(PORT_E),
 364                                    DP_TP_CTL_FDI_AUTOTRAIN |
 365                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 366                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 367                                    DP_TP_CTL_ENABLE);
 368
 369                         return;
 370                 }
 371
 372                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 373                 temp &= ~DDI_BUF_CTL_ENABLE;
 374                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 375                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 376
 377                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 378                 temp = I915_READ(DP_TP_CTL(PORT_E));
 379                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 380                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 381                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 382                 POSTING_READ(DP_TP_CTL(PORT_E));
 383
 384                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 385
 386                 rx_ctl_val &= ~FDI_RX_ENABLE;
 387                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 388                 POSTING_READ(_FDI_RXA_CTL);
 389
 390                 /* Reset FDI_RX_MISC pwrdn lanes */
 391                 temp = I915_READ(_FDI_RXA_MISC);
 392                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 393                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 394                 I915_WRITE(_FDI_RXA_MISC, temp);
 395                 POSTING_READ(_FDI_RXA_MISC);
 396         }
 397
 398         DRM_ERROR("FDI link training failed!\n");
 399 }
 400
 401 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 402 {
 403         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 404         struct intel_digital_port *intel_dig_port =
 405                 enc_to_dig_port(&encoder->base);
 406
 407         intel_dp->DP = intel_dig_port->saved_port_bits |
 408                 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
 409         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 410
 411 }
 412
 413 static struct intel_encoder *
 414 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 415 {
 416         struct drm_device *dev = crtc->dev;
 417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 418         struct intel_encoder *intel_encoder, *ret = NULL;
 419         int num_encoders = 0;
 420
 421         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 422                 ret = intel_encoder;
 423                 num_encoders++;
 424         }
 425
 426         if (num_encoders != 1)
 427                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 428                      pipe_name(intel_crtc->pipe));
 429
 430         BUG_ON(ret == NULL);
 431         return ret;
 432 }
 433
 434 #define LC_FREQ 2700
 435 #define LC_FREQ_2K (LC_FREQ * 2000)
 436
 437 #define P_MIN 2
 438 #define P_MAX 64
 439 #define P_INC 2
 440
 441 /* Constraints for PLL good behavior */
 442 #define REF_MIN 48
 443 #define REF_MAX 400
 444 #define VCO_MIN 2400
 445 #define VCO_MAX 4800
 446
 447 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
 448
 449 struct wrpll_rnp {
 450         unsigned p, n2, r2;
 451 };
 452
 453 static unsigned wrpll_get_budget_for_freq(int clock)
 454 {
 455         unsigned budget;
 456
 457         switch (clock) {
 458         case 25175000:
 459         case 25200000:
 460         case 27000000:
 461         case 27027000:
 462         case 37762500:
 463         case 37800000:
 464         case 40500000:
 465         case 40541000:
 466         case 54000000:
 467         case 54054000:
 468         case 59341000:
 469         case 59400000:
 470         case 72000000:
 471         case 74176000:
 472         case 74250000:
 473         case 81000000:
 474         case 81081000:
 475         case 89012000:
 476         case 89100000:
 477         case 108000000:
 478         case 108108000:
 479         case 111264000:
 480         case 111375000:
 481         case 148352000:
 482         case 148500000:
 483         case 162000000:
 484         case 162162000:
 485         case 222525000:
 486         case 222750000:
 487         case 296703000:
 488         case 297000000:
 489                 budget = 0;
 490                 break;
 491         case 233500000:
 492         case 245250000:
 493         case 247750000:
 494         case 253250000:
 495         case 298000000:
 496                 budget = 1500;
 497                 break;
 498         case 169128000:
 499         case 169500000:
 500         case 179500000:
 501         case 202000000:
 502                 budget = 2000;
 503                 break;
 504         case 256250000:
 505         case 262500000:
 506         case 270000000:
 507         case 272500000:
 508         case 273750000:
 509         case 280750000:
 510         case 281250000:
 511         case 286000000:
 512         case 291750000:
 513                 budget = 4000;
 514                 break;
 515         case 267250000:
 516         case 268500000:
 517                 budget = 5000;
 518                 break;
 519         default:
 520                 budget = 1000;
 521                 break;
 522         }
 523
 524         return budget;
 525 }
 526
 527 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 528                              unsigned r2, unsigned n2, unsigned p,
 529                              struct wrpll_rnp *best)
 530 {
 531         uint64_t a, b, c, d, diff, diff_best;
 532
 533         /* No best (r,n,p) yet */
 534         if (best->p == 0) {
 535                 best->p = p;
 536                 best->n2 = n2;
 537                 best->r2 = r2;
 538                 return;
 539         }
 540
 541         /*
 542          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 543          * freq2k.
 544          *
 545          * delta = 1e6 *
 546          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 547          *         freq2k;
 548          *
 549          * and we would like delta <= budget.
 550          *
 551          * If the discrepancy is above the PPM-based budget, always prefer to
 552          * improve upon the previous solution.  However, if you're within the
 553          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 554          */
 555         a = freq2k * budget * p * r2;
 556         b = freq2k * budget * best->p * best->r2;
 557         diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
 558         diff_best = ABS_DIFF((freq2k * best->p * best->r2),
 559                              (LC_FREQ_2K * best->n2));
 560         c = 1000000 * diff;
 561         d = 1000000 * diff_best;
 562
 563         if (a < c && b < d) {
 564                 /* If both are above the budget, pick the closer */
 565                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 566                         best->p = p;
 567                         best->n2 = n2;
 568                         best->r2 = r2;
 569                 }
 570         } else if (a >= c && b < d) {
 571                 /* If A is below the threshold but B is above it?  Update. */
 572                 best->p = p;
 573                 best->n2 = n2;
 574                 best->r2 = r2;
 575         } else if (a >= c && b >= d) {
 576                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 577                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 578                         best->p = p;
 579                         best->n2 = n2;
 580                         best->r2 = r2;
 581                 }
 582         }
 583         /* Otherwise a < c && b >= d, do nothing */
 584 }
 585
 586 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 587                                      int reg)
 588 {
 589         int refclk = LC_FREQ;
 590         int n, p, r;
 591         u32 wrpll;
 592
 593         wrpll = I915_READ(reg);
 594         switch (wrpll & WRPLL_PLL_REF_MASK) {
 595         case WRPLL_PLL_SSC:
 596         case WRPLL_PLL_NON_SSC:
 597                 /*
 598                  * We could calculate spread here, but our checking
 599                  * code only cares about 5% accuracy, and spread is a max of
 600                  * 0.5% downspread.
 601                  */
 602                 refclk = 135;
 603                 break;
 604         case WRPLL_PLL_LCPLL:
 605                 refclk = LC_FREQ;
 606                 break;
 607         default:
 608                 WARN(1, "bad wrpll refclk\n");
 609                 return 0;
 610         }
 611
 612         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 613         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 614         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 615
 616         /* Convert to KHz, p & r have a fixed point portion */
 617         return (refclk * n * 100) / (p * r);
 618 }
 619
 620 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 621                               struct intel_crtc_config *pipe_config)
 622 {
 623         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 624         int link_clock = 0;
 625         u32 val, pll;
 626
 627         val = pipe_config->ddi_pll_sel;
 628         switch (val & PORT_CLK_SEL_MASK) {
 629         case PORT_CLK_SEL_LCPLL_810:
 630                 link_clock = 81000;
 631                 break;
 632         case PORT_CLK_SEL_LCPLL_1350:
 633                 link_clock = 135000;
 634                 break;
 635         case PORT_CLK_SEL_LCPLL_2700:
 636                 link_clock = 270000;
 637                 break;
 638         case PORT_CLK_SEL_WRPLL1:
 639                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
 640                 break;
 641         case PORT_CLK_SEL_WRPLL2:
 642                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
 643                 break;
 644         case PORT_CLK_SEL_SPLL:
 645                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 646                 if (pll == SPLL_PLL_FREQ_810MHz)
 647                         link_clock = 81000;
 648                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 649                         link_clock = 135000;
 650                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 651                         link_clock = 270000;
 652                 else {
 653                         WARN(1, "bad spll freq\n");
 654                         return;
 655                 }
 656                 break;
 657         default:
 658                 WARN(1, "bad port clock sel\n");
 659                 return;
 660         }
 661
 662         pipe_config->port_clock = link_clock * 2;
 663
 664         if (pipe_config->has_pch_encoder)
 665                 pipe_config->adjusted_mode.crtc_clock =
 666                         intel_dotclock_calculate(pipe_config->port_clock,
 667                                                  &pipe_config->fdi_m_n);
 668         else if (pipe_config->has_dp_encoder)
 669                 pipe_config->adjusted_mode.crtc_clock =
 670                         intel_dotclock_calculate(pipe_config->port_clock,
 671                                                  &pipe_config->dp_m_n);
 672         else
 673                 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
 674 }
 675
 676 void intel_ddi_clock_get(struct intel_encoder *encoder,
 677                          struct intel_crtc_config *pipe_config)
 678 {
 679         hsw_ddi_clock_get(encoder, pipe_config);
 680 }
 681
 682 static void
 683 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 684                         unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 685 {
 686         uint64_t freq2k;
 687         unsigned p, n2, r2;
 688         struct wrpll_rnp best = { 0, 0, 0 };
 689         unsigned budget;
 690
 691         freq2k = clock / 100;
 692
 693         budget = wrpll_get_budget_for_freq(clock);
 694
 695         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 696          * and directly pass the LC PLL to it. */
 697         if (freq2k == 5400000) {
 698                 *n2_out = 2;
 699                 *p_out = 1;
 700                 *r2_out = 2;
 701                 return;
 702         }
 703
 704         /*
 705          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 706          * the WR PLL.
 707          *
 708          * We want R so that REF_MIN <= Ref <= REF_MAX.
 709          * Injecting R2 = 2 * R gives:
 710          *   REF_MAX * r2 > LC_FREQ * 2 and
 711          *   REF_MIN * r2 < LC_FREQ * 2
 712          *
 713          * Which means the desired boundaries for r2 are:
 714          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 715          *
 716          */
 717         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 718              r2 <= LC_FREQ * 2 / REF_MIN;
 719              r2++) {
 720
 721                 /*
 722                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 723                  *
 724                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 725                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 726                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 727                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 728                  *
 729                  * Which means the desired boundaries for n2 are:
 730                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 731                  */
 732                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 733                      n2 <= VCO_MAX * r2 / LC_FREQ;
 734                      n2++) {
 735
 736                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 737                                 wrpll_update_rnp(freq2k, budget,
 738                                                  r2, n2, p, &best);
 739                 }
 740         }
 741
 742         *n2_out = best.n2;
 743         *p_out = best.p;
 744         *r2_out = best.r2;
 745 }
 746
 747 static bool
 748 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 749                    struct intel_encoder *intel_encoder,
 750                    int clock)
 751 {
 752         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 753                 struct intel_shared_dpll *pll;
 754                 uint32_t val;
 755                 unsigned p, n2, r2;
 756
 757                 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 758
 759                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 760                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 761                       WRPLL_DIVIDER_POST(p);
 762
 763                 intel_crtc->config.dpll_hw_state.wrpll = val;
 764
 765                 pll = intel_get_shared_dpll(intel_crtc);
 766                 if (pll == NULL) {
 767                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 768                                          pipe_name(intel_crtc->pipe));
 769                         return false;
 770                 }
 771
 772                 intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
 773         }
 774
 775         return true;
 776 }
 777
 778
 779 /*
 780  * Tries to find a *shared* PLL for the CRTC and store it in
 781  * intel_crtc->ddi_pll_sel.
 782  *
 783  * For private DPLLs, compute_config() should do the selection for us. This
 784  * function should be folded into compute_config() eventually.
 785  */
 786 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 787 {
 788         struct drm_crtc *crtc = &intel_crtc->base;
 789         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 790         int clock = intel_crtc->config.port_clock;
 791
 792         intel_put_shared_dpll(intel_crtc);
 793
 794         return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
 795 }
 796
 797 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 798 {
 799         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 801         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 802         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 803         int type = intel_encoder->type;
 804         uint32_t temp;
 805
 806         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
 807                 temp = TRANS_MSA_SYNC_CLK;
 808                 switch (intel_crtc->config.pipe_bpp) {
 809                 case 18:
 810                         temp |= TRANS_MSA_6_BPC;
 811                         break;
 812                 case 24:
 813                         temp |= TRANS_MSA_8_BPC;
 814                         break;
 815                 case 30:
 816                         temp |= TRANS_MSA_10_BPC;
 817                         break;
 818                 case 36:
 819                         temp |= TRANS_MSA_12_BPC;
 820                         break;
 821                 default:
 822                         BUG();
 823                 }
 824                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 825         }
 826 }
 827
 828 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
 829 {
 830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 831         struct drm_device *dev = crtc->dev;
 832         struct drm_i915_private *dev_priv = dev->dev_private;
 833         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 834         uint32_t temp;
 835         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 836         if (state == true)
 837                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
 838         else
 839                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
 840         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 841 }
 842
 843 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 844 {
 845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 846         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 847         struct drm_encoder *encoder = &intel_encoder->base;
 848         struct drm_device *dev = crtc->dev;
 849         struct drm_i915_private *dev_priv = dev->dev_private;
 850         enum pipe pipe = intel_crtc->pipe;
 851         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 852         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 853         int type = intel_encoder->type;
 854         uint32_t temp;
 855
 856         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 857         temp = TRANS_DDI_FUNC_ENABLE;
 858         temp |= TRANS_DDI_SELECT_PORT(port);
 859
 860         switch (intel_crtc->config.pipe_bpp) {
 861         case 18:
 862                 temp |= TRANS_DDI_BPC_6;
 863                 break;
 864         case 24:
 865                 temp |= TRANS_DDI_BPC_8;
 866                 break;
 867         case 30:
 868                 temp |= TRANS_DDI_BPC_10;
 869                 break;
 870         case 36:
 871                 temp |= TRANS_DDI_BPC_12;
 872                 break;
 873         default:
 874                 BUG();
 875         }
 876
 877         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 878                 temp |= TRANS_DDI_PVSYNC;
 879         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 880                 temp |= TRANS_DDI_PHSYNC;
 881
 882         if (cpu_transcoder == TRANSCODER_EDP) {
 883                 switch (pipe) {
 884                 case PIPE_A:
 885                         /* On Haswell, can only use the always-on power well for
 886                          * eDP when not using the panel fitter, and when not
 887                          * using motion blur mitigation (which we don't
 888                          * support). */
 889                         if (IS_HASWELL(dev) &&
 890                             (intel_crtc->config.pch_pfit.enabled ||
 891                              intel_crtc->config.pch_pfit.force_thru))
 892                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 893                         else
 894                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 895                         break;
 896                 case PIPE_B:
 897                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 898                         break;
 899                 case PIPE_C:
 900                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 901                         break;
 902                 default:
 903                         BUG();
 904                         break;
 905                 }
 906         }
 907
 908         if (type == INTEL_OUTPUT_HDMI) {
 909                 if (intel_crtc->config.has_hdmi_sink)
 910                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 911                 else
 912                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 913
 914         } else if (type == INTEL_OUTPUT_ANALOG) {
 915                 temp |= TRANS_DDI_MODE_SELECT_FDI;
 916                 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
 917
 918         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
 919                    type == INTEL_OUTPUT_EDP) {
 920                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 921
 922                 if (intel_dp->is_mst) {
 923                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 924                 } else
 925                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 926
 927                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 928         } else if (type == INTEL_OUTPUT_DP_MST) {
 929                 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
 930
 931                 if (intel_dp->is_mst) {
 932                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 933                 } else
 934                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 935
 936                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 937         } else {
 938                 WARN(1, "Invalid encoder type %d for pipe %c\n",
 939                      intel_encoder->type, pipe_name(pipe));
 940         }
 941
 942         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 943 }
 944
 945 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 946                                        enum transcoder cpu_transcoder)
 947 {
 948         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 949         uint32_t val = I915_READ(reg);
 950
 951         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
 952         val |= TRANS_DDI_PORT_NONE;
 953         I915_WRITE(reg, val);
 954 }
 955
 956 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 957 {
 958         struct drm_device *dev = intel_connector->base.dev;
 959         struct drm_i915_private *dev_priv = dev->dev_private;
 960         struct intel_encoder *intel_encoder = intel_connector->encoder;
 961         int type = intel_connector->base.connector_type;
 962         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 963         enum pipe pipe = 0;
 964         enum transcoder cpu_transcoder;
 965         enum intel_display_power_domain power_domain;
 966         uint32_t tmp;
 967
 968         power_domain = intel_display_port_power_domain(intel_encoder);
 969         if (!intel_display_power_enabled(dev_priv, power_domain))
 970                 return false;
 971
 972         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
 973                 return false;
 974
 975         if (port == PORT_A)
 976                 cpu_transcoder = TRANSCODER_EDP;
 977         else
 978                 cpu_transcoder = (enum transcoder) pipe;
 979
 980         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 981
 982         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 983         case TRANS_DDI_MODE_SELECT_HDMI:
 984         case TRANS_DDI_MODE_SELECT_DVI:
 985                 return (type == DRM_MODE_CONNECTOR_HDMIA);
 986
 987         case TRANS_DDI_MODE_SELECT_DP_SST:
 988                 if (type == DRM_MODE_CONNECTOR_eDP)
 989                         return true;
 990                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
 991         case TRANS_DDI_MODE_SELECT_DP_MST:
 992                 /* if the transcoder is in MST state then
 993                  * connector isn't connected */
 994                 return false;
 995
 996         case TRANS_DDI_MODE_SELECT_FDI:
 997                 return (type == DRM_MODE_CONNECTOR_VGA);
 998
 999         default:
1000                 return false;
1001         }
1002 }
1003
1004 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1005                             enum pipe *pipe)
1006 {
1007         struct drm_device *dev = encoder->base.dev;
1008         struct drm_i915_private *dev_priv = dev->dev_private;
1009         enum port port = intel_ddi_get_encoder_port(encoder);
1010         enum intel_display_power_domain power_domain;
1011         u32 tmp;
1012         int i;
1013
1014         power_domain = intel_display_port_power_domain(encoder);
1015         if (!intel_display_power_enabled(dev_priv, power_domain))
1016                 return false;
1017
1018         tmp = I915_READ(DDI_BUF_CTL(port));
1019
1020         if (!(tmp & DDI_BUF_CTL_ENABLE))
1021                 return false;
1022
1023         if (port == PORT_A) {
1024                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1025
1026                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1027                 case TRANS_DDI_EDP_INPUT_A_ON:
1028                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1029                         *pipe = PIPE_A;
1030                         break;
1031                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1032                         *pipe = PIPE_B;
1033                         break;
1034                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1035                         *pipe = PIPE_C;
1036                         break;
1037                 }
1038
1039                 return true;
1040         } else {
1041                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1042                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1043
1044                         if ((tmp & TRANS_DDI_PORT_MASK)
1045                             == TRANS_DDI_SELECT_PORT(port)) {
1046                                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1047                                         return false;
1048
1049                                 *pipe = i;
1050                                 return true;
1051                         }
1052                 }
1053         }
1054
1055         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1056
1057         return false;
1058 }
1059
1060 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1061 {
1062         struct drm_crtc *crtc = &intel_crtc->base;
1063         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1064         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1065         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1066         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1067
1068         if (cpu_transcoder != TRANSCODER_EDP)
1069                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1070                            TRANS_CLK_SEL_PORT(port));
1071 }
1072
1073 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1074 {
1075         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1076         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1077
1078         if (cpu_transcoder != TRANSCODER_EDP)
1079                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1080                            TRANS_CLK_SEL_DISABLED);
1081 }
1082
1083 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1084 {
1085         struct drm_encoder *encoder = &intel_encoder->base;
1086         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1087         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1088         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1089         int type = intel_encoder->type;
1090
1091         if (crtc->config.has_audio) {
1092                 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
1093                                  pipe_name(crtc->pipe));
1094
1095                 /* write eld */
1096                 DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
1097                 intel_write_eld(encoder, &crtc->config.adjusted_mode);
1098         }
1099
1100         if (type == INTEL_OUTPUT_EDP) {
1101                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1102                 intel_edp_panel_on(intel_dp);
1103         }
1104
1105         WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1106         I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1107
1108         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1109                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1110
1111                 intel_ddi_init_dp_buf_reg(intel_encoder);
1112
1113                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1114                 intel_dp_start_link_train(intel_dp);
1115                 intel_dp_complete_link_train(intel_dp);
1116                 if (port != PORT_A)
1117                         intel_dp_stop_link_train(intel_dp);
1118         } else if (type == INTEL_OUTPUT_HDMI) {
1119                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1120
1121                 intel_hdmi->set_infoframes(encoder,
1122                                            crtc->config.has_hdmi_sink,
1123                                            &crtc->config.adjusted_mode);
1124         }
1125 }
1126
1127 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1128 {
1129         struct drm_encoder *encoder = &intel_encoder->base;
1130         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1131         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1132         int type = intel_encoder->type;
1133         uint32_t val;
1134         bool wait = false;
1135
1136         val = I915_READ(DDI_BUF_CTL(port));
1137         if (val & DDI_BUF_CTL_ENABLE) {
1138                 val &= ~DDI_BUF_CTL_ENABLE;
1139                 I915_WRITE(DDI_BUF_CTL(port), val);
1140                 wait = true;
1141         }
1142
1143         val = I915_READ(DP_TP_CTL(port));
1144         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1145         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1146         I915_WRITE(DP_TP_CTL(port), val);
1147
1148         if (wait)
1149                 intel_wait_ddi_buf_idle(dev_priv, port);
1150
1151         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1152                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1153                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1154                 intel_edp_panel_vdd_on(intel_dp);
1155                 intel_edp_panel_off(intel_dp);
1156         }
1157
1158         I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1159 }
1160
1161 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1162 {
1163         struct drm_encoder *encoder = &intel_encoder->base;
1164         struct drm_crtc *crtc = encoder->crtc;
1165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1166         int pipe = intel_crtc->pipe;
1167         struct drm_device *dev = encoder->dev;
1168         struct drm_i915_private *dev_priv = dev->dev_private;
1169         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1170         int type = intel_encoder->type;
1171         uint32_t tmp;
1172
1173         if (type == INTEL_OUTPUT_HDMI) {
1174                 struct intel_digital_port *intel_dig_port =
1175                         enc_to_dig_port(encoder);
1176
1177                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1178                  * are ignored so nothing special needs to be done besides
1179                  * enabling the port.
1180                  */
1181                 I915_WRITE(DDI_BUF_CTL(port),
1182                            intel_dig_port->saved_port_bits |
1183                            DDI_BUF_CTL_ENABLE);
1184         } else if (type == INTEL_OUTPUT_EDP) {
1185                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1186
1187                 if (port == PORT_A)
1188                         intel_dp_stop_link_train(intel_dp);
1189
1190                 intel_edp_backlight_on(intel_dp);
1191                 intel_edp_psr_enable(intel_dp);
1192         }
1193
1194         if (intel_crtc->config.has_audio) {
1195                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1196                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1197                 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1198                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1199         }
1200 }
1201
1202 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1203 {
1204         struct drm_encoder *encoder = &intel_encoder->base;
1205         struct drm_crtc *crtc = encoder->crtc;
1206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1207         int pipe = intel_crtc->pipe;
1208         int type = intel_encoder->type;
1209         struct drm_device *dev = encoder->dev;
1210         struct drm_i915_private *dev_priv = dev->dev_private;
1211         uint32_t tmp;
1212
1213         /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
1214          * register is part of the power well on Haswell. */
1215         if (intel_crtc->config.has_audio) {
1216                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1217                 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1218                          (pipe * 4));
1219                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1220                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1221         }
1222
1223         if (type == INTEL_OUTPUT_EDP) {
1224                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1225
1226                 intel_edp_psr_disable(intel_dp);
1227                 intel_edp_backlight_off(intel_dp);
1228         }
1229 }
1230
1231 static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1232 {
1233         uint32_t lcpll = I915_READ(LCPLL_CTL);
1234         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1235
1236         if (lcpll & LCPLL_CD_SOURCE_FCLK)
1237                 return 800000;
1238         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1239                 return 450000;
1240         else if (freq == LCPLL_CLK_FREQ_450)
1241                 return 450000;
1242         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1243                 return 540000;
1244         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1245                 return 337500;
1246         else
1247                 return 675000;
1248 }
1249
1250 static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1251 {
1252         struct drm_device *dev = dev_priv->dev;
1253         uint32_t lcpll = I915_READ(LCPLL_CTL);
1254         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1255
1256         if (lcpll & LCPLL_CD_SOURCE_FCLK)
1257                 return 800000;
1258         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1259                 return 450000;
1260         else if (freq == LCPLL_CLK_FREQ_450)
1261                 return 450000;
1262         else if (IS_ULT(dev))
1263                 return 337500;
1264         else
1265                 return 540000;
1266 }
1267
1268 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1269 {
1270         struct drm_device *dev = dev_priv->dev;
1271
1272         if (IS_BROADWELL(dev))
1273                 return bdw_get_cdclk_freq(dev_priv);
1274
1275         /* Haswell */
1276         return hsw_get_cdclk_freq(dev_priv);
1277 }
1278
1279 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1280                                struct intel_shared_dpll *pll)
1281 {
1282         I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll);
1283         POSTING_READ(WRPLL_CTL(pll->id));
1284         udelay(20);
1285 }
1286
1287 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1288                                 struct intel_shared_dpll *pll)
1289 {
1290         uint32_t val;
1291
1292         val = I915_READ(WRPLL_CTL(pll->id));
1293         I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1294         POSTING_READ(WRPLL_CTL(pll->id));
1295 }
1296
1297 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1298                                      struct intel_shared_dpll *pll,
1299                                      struct intel_dpll_hw_state *hw_state)
1300 {
1301         uint32_t val;
1302
1303         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
1304                 return false;
1305
1306         val = I915_READ(WRPLL_CTL(pll->id));
1307         hw_state->wrpll = val;
1308
1309         return val & WRPLL_PLL_ENABLE;
1310 }
1311
1312 static const char * const hsw_ddi_pll_names[] = {
1313         "WRPLL 1",
1314         "WRPLL 2",
1315 };
1316
1317 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1318 {
1319         int i;
1320
1321         dev_priv->num_shared_dpll = 2;
1322
1323         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1324                 dev_priv->shared_dplls[i].id = i;
1325                 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1326                 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1327                 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1328                 dev_priv->shared_dplls[i].get_hw_state =
1329                         hsw_ddi_pll_get_hw_state;
1330         }
1331 }
1332
1333 void intel_ddi_pll_init(struct drm_device *dev)
1334 {
1335         struct drm_i915_private *dev_priv = dev->dev_private;
1336         uint32_t val = I915_READ(LCPLL_CTL);
1337
1338         hsw_shared_dplls_init(dev_priv);
1339
1340         /* The LCPLL register should be turned on by the BIOS. For now let's
1341          * just check its state and print errors in case something is wrong.
1342          * Don't even try to turn it on.
1343          */
1344
1345         DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1346                       intel_ddi_get_cdclk_freq(dev_priv));
1347
1348         if (val & LCPLL_CD_SOURCE_FCLK)
1349                 DRM_ERROR("CDCLK source is not LCPLL\n");
1350
1351         if (val & LCPLL_PLL_DISABLE)
1352                 DRM_ERROR("LCPLL is disabled\n");
1353 }
1354
1355 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1356 {
1357         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1358         struct intel_dp *intel_dp = &intel_dig_port->dp;
1359         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1360         enum port port = intel_dig_port->port;
1361         uint32_t val;
1362         bool wait = false;
1363
1364         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1365                 val = I915_READ(DDI_BUF_CTL(port));
1366                 if (val & DDI_BUF_CTL_ENABLE) {
1367                         val &= ~DDI_BUF_CTL_ENABLE;
1368                         I915_WRITE(DDI_BUF_CTL(port), val);
1369                         wait = true;
1370                 }
1371
1372                 val = I915_READ(DP_TP_CTL(port));
1373                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1374                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1375                 I915_WRITE(DP_TP_CTL(port), val);
1376                 POSTING_READ(DP_TP_CTL(port));
1377
1378                 if (wait)
1379                         intel_wait_ddi_buf_idle(dev_priv, port);
1380         }
1381
1382         val = DP_TP_CTL_ENABLE |
1383               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1384         if (intel_dp->is_mst)
1385                 val |= DP_TP_CTL_MODE_MST;
1386         else {
1387                 val |= DP_TP_CTL_MODE_SST;
1388                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1389                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1390         }
1391         I915_WRITE(DP_TP_CTL(port), val);
1392         POSTING_READ(DP_TP_CTL(port));
1393
1394         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1395         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1396         POSTING_READ(DDI_BUF_CTL(port));
1397
1398         udelay(600);
1399 }
1400
1401 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1402 {
1403         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1404         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1405         uint32_t val;
1406
1407         intel_ddi_post_disable(intel_encoder);
1408
1409         val = I915_READ(_FDI_RXA_CTL);
1410         val &= ~FDI_RX_ENABLE;
1411         I915_WRITE(_FDI_RXA_CTL, val);
1412
1413         val = I915_READ(_FDI_RXA_MISC);
1414         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1415         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1416         I915_WRITE(_FDI_RXA_MISC, val);
1417
1418         val = I915_READ(_FDI_RXA_CTL);
1419         val &= ~FDI_PCDCLK;
1420         I915_WRITE(_FDI_RXA_CTL, val);
1421
1422         val = I915_READ(_FDI_RXA_CTL);
1423         val &= ~FDI_RX_PLL_ENABLE;
1424         I915_WRITE(_FDI_RXA_CTL, val);
1425 }
1426
1427 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1428 {
1429         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
1430         int type = intel_dig_port->base.type;
1431
1432         if (type != INTEL_OUTPUT_DISPLAYPORT &&
1433             type != INTEL_OUTPUT_EDP &&
1434             type != INTEL_OUTPUT_UNKNOWN) {
1435                 return;
1436         }
1437
1438         intel_dp_hot_plug(intel_encoder);
1439 }
1440
1441 void intel_ddi_get_config(struct intel_encoder *encoder,
1442                           struct intel_crtc_config *pipe_config)
1443 {
1444         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1445         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1446         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1447         u32 temp, flags = 0;
1448
1449         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1450         if (temp & TRANS_DDI_PHSYNC)
1451                 flags |= DRM_MODE_FLAG_PHSYNC;
1452         else
1453                 flags |= DRM_MODE_FLAG_NHSYNC;
1454         if (temp & TRANS_DDI_PVSYNC)
1455                 flags |= DRM_MODE_FLAG_PVSYNC;
1456         else
1457                 flags |= DRM_MODE_FLAG_NVSYNC;
1458
1459         pipe_config->adjusted_mode.flags |= flags;
1460
1461         switch (temp & TRANS_DDI_BPC_MASK) {
1462         case TRANS_DDI_BPC_6:
1463                 pipe_config->pipe_bpp = 18;
1464                 break;
1465         case TRANS_DDI_BPC_8:
1466                 pipe_config->pipe_bpp = 24;
1467                 break;
1468         case TRANS_DDI_BPC_10:
1469                 pipe_config->pipe_bpp = 30;
1470                 break;
1471         case TRANS_DDI_BPC_12:
1472                 pipe_config->pipe_bpp = 36;
1473                 break;
1474         default:
1475                 break;
1476         }
1477
1478         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1479         case TRANS_DDI_MODE_SELECT_HDMI:
1480                 pipe_config->has_hdmi_sink = true;
1481         case TRANS_DDI_MODE_SELECT_DVI:
1482         case TRANS_DDI_MODE_SELECT_FDI:
1483                 break;
1484         case TRANS_DDI_MODE_SELECT_DP_SST:
1485         case TRANS_DDI_MODE_SELECT_DP_MST:
1486                 pipe_config->has_dp_encoder = true;
1487                 intel_dp_get_m_n(intel_crtc, pipe_config);
1488                 break;
1489         default:
1490                 break;
1491         }
1492
1493         if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1494                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1495                 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
1496                         pipe_config->has_audio = true;
1497         }
1498
1499         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1500             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1501                 /*
1502                  * This is a big fat ugly hack.
1503                  *
1504                  * Some machines in UEFI boot mode provide us a VBT that has 18
1505                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1506                  * unknown we fail to light up. Yet the same BIOS boots up with
1507                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1508                  * max, not what it tells us to use.
1509                  *
1510                  * Note: This will still be broken if the eDP panel is not lit
1511                  * up by the BIOS, and thus we can't get the mode at module
1512                  * load.
1513                  */
1514                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1515                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1516                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1517         }
1518
1519         hsw_ddi_clock_get(encoder, pipe_config);
1520 }
1521
1522 static void intel_ddi_destroy(struct drm_encoder *encoder)
1523 {
1524         /* HDMI has nothing special to destroy, so we can go with this. */
1525         intel_dp_encoder_destroy(encoder);
1526 }
1527
1528 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1529                                      struct intel_crtc_config *pipe_config)
1530 {
1531         int type = encoder->type;
1532         int port = intel_ddi_get_encoder_port(encoder);
1533
1534         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1535
1536         if (port == PORT_A)
1537                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1538
1539         if (type == INTEL_OUTPUT_HDMI)
1540                 return intel_hdmi_compute_config(encoder, pipe_config);
1541         else
1542                 return intel_dp_compute_config(encoder, pipe_config);
1543 }
1544
1545 static const struct drm_encoder_funcs intel_ddi_funcs = {
1546         .destroy = intel_ddi_destroy,
1547 };
1548
1549 static struct intel_connector *
1550 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1551 {
1552         struct intel_connector *connector;
1553         enum port port = intel_dig_port->port;
1554
1555         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1556         if (!connector)
1557                 return NULL;
1558
1559         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1560         if (!intel_dp_init_connector(intel_dig_port, connector)) {
1561                 kfree(connector);
1562                 return NULL;
1563         }
1564
1565         return connector;
1566 }
1567
1568 static struct intel_connector *
1569 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1570 {
1571         struct intel_connector *connector;
1572         enum port port = intel_dig_port->port;
1573
1574         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1575         if (!connector)
1576                 return NULL;
1577
1578         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1579         intel_hdmi_init_connector(intel_dig_port, connector);
1580
1581         return connector;
1582 }
1583
1584 void intel_ddi_init(struct drm_device *dev, enum port port)
1585 {
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         struct intel_digital_port *intel_dig_port;
1588         struct intel_encoder *intel_encoder;
1589         struct drm_encoder *encoder;
1590         bool init_hdmi, init_dp;
1591
1592         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1593                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1594         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1595         if (!init_dp && !init_hdmi) {
1596                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
1597                               port_name(port));
1598                 init_hdmi = true;
1599                 init_dp = true;
1600         }
1601
1602         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1603         if (!intel_dig_port)
1604                 return;
1605
1606         intel_encoder = &intel_dig_port->base;
1607         encoder = &intel_encoder->base;
1608
1609         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1610                          DRM_MODE_ENCODER_TMDS);
1611
1612         intel_encoder->compute_config = intel_ddi_compute_config;
1613         intel_encoder->enable = intel_enable_ddi;
1614         intel_encoder->pre_enable = intel_ddi_pre_enable;
1615         intel_encoder->disable = intel_disable_ddi;
1616         intel_encoder->post_disable = intel_ddi_post_disable;
1617         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1618         intel_encoder->get_config = intel_ddi_get_config;
1619
1620         intel_dig_port->port = port;
1621         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1622                                           (DDI_BUF_PORT_REVERSAL |
1623                                            DDI_A_4_LANES);
1624
1625         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1626         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1627         intel_encoder->cloneable = 0;
1628         intel_encoder->hot_plug = intel_ddi_hot_plug;
1629
1630         if (init_dp) {
1631                 if (!intel_ddi_init_dp_connector(intel_dig_port))
1632                         goto err;
1633
1634                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
1635                 dev_priv->hpd_irq_port[port] = intel_dig_port;
1636         }
1637
1638         /* In theory we don't need the encoder->type check, but leave it just in
1639          * case we have some really bad VBTs... */
1640         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
1641                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
1642                         goto err;
1643         }
1644
1645         return;
1646
1647 err:
1648         drm_encoder_cleanup(encoder);
1649         kfree(intel_dig_port);
1650 }