drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 /* Here's the desired hotplug mode */
  40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45                            ADPA_CRT_HOTPLUG_ENABLE)
  46
  47 struct intel_crt {
  48         struct intel_encoder base;
  49         /* DPMS state is stored in the connector, which we need in the
  50          * encoder's enable/disable callbacks */
  51         struct intel_connector *connector;
  52         bool force_hotplug_required;
  53         u32 adpa_reg;
  54 };
  55
  56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57 {
  58         return container_of(encoder, struct intel_crt, base);
  59 }
  60
  61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62 {
  63         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64 }
  65
  66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  67                                    enum pipe *pipe)
  68 {
  69         struct drm_device *dev = encoder->base.dev;
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  72         enum intel_display_power_domain power_domain;
  73         u32 tmp;
  74
  75         power_domain = intel_display_port_power_domain(encoder);
  76         if (!intel_display_power_is_enabled(dev_priv, power_domain))
  77                 return false;
  78
  79         tmp = I915_READ(crt->adpa_reg);
  80
  81         if (!(tmp & ADPA_DAC_ENABLE))
  82                 return false;
  83
  84         if (HAS_PCH_CPT(dev))
  85                 *pipe = PORT_TO_PIPE_CPT(tmp);
  86         else
  87                 *pipe = PORT_TO_PIPE(tmp);
  88
  89         return true;
  90 }
  91
  92 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
  93 {
  94         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  95         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  96         u32 tmp, flags = 0;
  97
  98         tmp = I915_READ(crt->adpa_reg);
  99
 100         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 101                 flags |= DRM_MODE_FLAG_PHSYNC;
 102         else
 103                 flags |= DRM_MODE_FLAG_NHSYNC;
 104
 105         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 106                 flags |= DRM_MODE_FLAG_PVSYNC;
 107         else
 108                 flags |= DRM_MODE_FLAG_NVSYNC;
 109
 110         return flags;
 111 }
 112
 113 static void intel_crt_get_config(struct intel_encoder *encoder,
 114                                  struct intel_crtc_state *pipe_config)
 115 {
 116         struct drm_device *dev = encoder->base.dev;
 117         int dotclock;
 118
 119         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 120
 121         dotclock = pipe_config->port_clock;
 122
 123         if (HAS_PCH_SPLIT(dev))
 124                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 125
 126         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 127 }
 128
 129 static void hsw_crt_get_config(struct intel_encoder *encoder,
 130                                struct intel_crtc_state *pipe_config)
 131 {
 132         intel_ddi_get_config(encoder, pipe_config);
 133
 134         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 135                                               DRM_MODE_FLAG_NHSYNC |
 136                                               DRM_MODE_FLAG_PVSYNC |
 137                                               DRM_MODE_FLAG_NVSYNC);
 138         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 139 }
 140
 141 static void hsw_crt_pre_enable(struct intel_encoder *encoder)
 142 {
 143         struct drm_device *dev = encoder->base.dev;
 144         struct drm_i915_private *dev_priv = dev->dev_private;
 145
 146         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n");
 147         I915_WRITE(SPLL_CTL,
 148                    SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC);
 149         POSTING_READ(SPLL_CTL);
 150         udelay(20);
 151 }
 152
 153 /* Note: The caller is required to filter out dpms modes not supported by the
 154  * platform. */
 155 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
 156 {
 157         struct drm_device *dev = encoder->base.dev;
 158         struct drm_i915_private *dev_priv = dev->dev_private;
 159         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 160         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 161         struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 162         u32 adpa;
 163
 164         if (INTEL_INFO(dev)->gen >= 5)
 165                 adpa = ADPA_HOTPLUG_BITS;
 166         else
 167                 adpa = 0;
 168
 169         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 170                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 171         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 172                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 173
 174         /* For CPT allow 3 pipe config, for others just use A or B */
 175         if (HAS_PCH_LPT(dev))
 176                 ; /* Those bits don't exist here */
 177         else if (HAS_PCH_CPT(dev))
 178                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
 179         else if (crtc->pipe == 0)
 180                 adpa |= ADPA_PIPE_A_SELECT;
 181         else
 182                 adpa |= ADPA_PIPE_B_SELECT;
 183
 184         if (!HAS_PCH_SPLIT(dev))
 185                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 186
 187         switch (mode) {
 188         case DRM_MODE_DPMS_ON:
 189                 adpa |= ADPA_DAC_ENABLE;
 190                 break;
 191         case DRM_MODE_DPMS_STANDBY:
 192                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 193                 break;
 194         case DRM_MODE_DPMS_SUSPEND:
 195                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 196                 break;
 197         case DRM_MODE_DPMS_OFF:
 198                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 199                 break;
 200         }
 201
 202         I915_WRITE(crt->adpa_reg, adpa);
 203 }
 204
 205 static void intel_disable_crt(struct intel_encoder *encoder)
 206 {
 207         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
 208 }
 209
 210 static void pch_disable_crt(struct intel_encoder *encoder)
 211 {
 212 }
 213
 214 static void pch_post_disable_crt(struct intel_encoder *encoder)
 215 {
 216         intel_disable_crt(encoder);
 217 }
 218
 219 static void hsw_crt_post_disable(struct intel_encoder *encoder)
 220 {
 221         struct drm_device *dev = encoder->base.dev;
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         uint32_t val;
 224
 225         DRM_DEBUG_KMS("Disabling SPLL\n");
 226         val = I915_READ(SPLL_CTL);
 227         WARN_ON(!(val & SPLL_PLL_ENABLE));
 228         I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
 229         POSTING_READ(SPLL_CTL);
 230 }
 231
 232 static void intel_enable_crt(struct intel_encoder *encoder)
 233 {
 234         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 235
 236         intel_crt_set_dpms(encoder, crt->connector->base.dpms);
 237 }
 238
 239 /* Special dpms function to support cloning between dvo/sdvo/crt. */
 240 static int intel_crt_dpms(struct drm_connector *connector, int mode)
 241 {
 242         struct drm_device *dev = connector->dev;
 243         struct intel_encoder *encoder = intel_attached_encoder(connector);
 244         struct drm_crtc *crtc;
 245         int old_dpms;
 246
 247         /* PCH platforms and VLV only support on/off. */
 248         if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
 249                 mode = DRM_MODE_DPMS_OFF;
 250
 251         if (mode == connector->dpms)
 252                 return 0;
 253
 254         old_dpms = connector->dpms;
 255         connector->dpms = mode;
 256
 257         /* Only need to change hw state when actually enabled */
 258         crtc = encoder->base.crtc;
 259         if (!crtc) {
 260                 encoder->connectors_active = false;
 261                 return 0;
 262         }
 263
 264         /* We need the pipe to run for anything but OFF. */
 265         if (mode == DRM_MODE_DPMS_OFF)
 266                 encoder->connectors_active = false;
 267         else
 268                 encoder->connectors_active = true;
 269
 270         /* We call connector dpms manually below in case pipe dpms doesn't
 271          * change due to cloning. */
 272         if (mode < old_dpms) {
 273                 /* From off to on, enable the pipe first. */
 274                 intel_crtc_update_dpms(crtc);
 275
 276                 intel_crt_set_dpms(encoder, mode);
 277         } else {
 278                 intel_crt_set_dpms(encoder, mode);
 279
 280                 intel_crtc_update_dpms(crtc);
 281         }
 282
 283         intel_modeset_check_state(connector->dev);
 284
 285         return 0;
 286 }
 287
 288 static enum drm_mode_status
 289 intel_crt_mode_valid(struct drm_connector *connector,
 290                      struct drm_display_mode *mode)
 291 {
 292         struct drm_device *dev = connector->dev;
 293
 294         int max_clock = 0;
 295         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 296                 return MODE_NO_DBLESCAN;
 297
 298         if (mode->clock < 25000)
 299                 return MODE_CLOCK_LOW;
 300
 301         if (IS_GEN2(dev))
 302                 max_clock = 350000;
 303         else
 304                 max_clock = 400000;
 305         if (mode->clock > max_clock)
 306                 return MODE_CLOCK_HIGH;
 307
 308         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 309         if (HAS_PCH_LPT(dev) &&
 310             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 311                 return MODE_CLOCK_HIGH;
 312
 313         return MODE_OK;
 314 }
 315
 316 static bool intel_crt_compute_config(struct intel_encoder *encoder,
 317                                      struct intel_crtc_state *pipe_config)
 318 {
 319         struct drm_device *dev = encoder->base.dev;
 320
 321         if (HAS_PCH_SPLIT(dev))
 322                 pipe_config->has_pch_encoder = true;
 323
 324         /* LPT FDI RX only supports 8bpc. */
 325         if (HAS_PCH_LPT(dev))
 326                 pipe_config->pipe_bpp = 24;
 327
 328         /* FDI must always be 2.7 GHz */
 329         if (HAS_DDI(dev)) {
 330                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
 331                 pipe_config->port_clock = 135000 * 2;
 332         }
 333
 334         return true;
 335 }
 336
 337 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 338 {
 339         struct drm_device *dev = connector->dev;
 340         struct intel_crt *crt = intel_attached_crt(connector);
 341         struct drm_i915_private *dev_priv = dev->dev_private;
 342         u32 adpa;
 343         bool ret;
 344
 345         /* The first time through, trigger an explicit detection cycle */
 346         if (crt->force_hotplug_required) {
 347                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
 348                 u32 save_adpa;
 349
 350                 crt->force_hotplug_required = 0;
 351
 352                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 353                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 354
 355                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 356                 if (turn_off_dac)
 357                         adpa &= ~ADPA_DAC_ENABLE;
 358
 359                 I915_WRITE(crt->adpa_reg, adpa);
 360
 361                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 362                              1000))
 363                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 364
 365                 if (turn_off_dac) {
 366                         I915_WRITE(crt->adpa_reg, save_adpa);
 367                         POSTING_READ(crt->adpa_reg);
 368                 }
 369         }
 370
 371         /* Check the status to see if both blue and green are on now */
 372         adpa = I915_READ(crt->adpa_reg);
 373         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 374                 ret = true;
 375         else
 376                 ret = false;
 377         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 378
 379         return ret;
 380 }
 381
 382 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 383 {
 384         struct drm_device *dev = connector->dev;
 385         struct intel_crt *crt = intel_attached_crt(connector);
 386         struct drm_i915_private *dev_priv = dev->dev_private;
 387         u32 adpa;
 388         bool ret;
 389         u32 save_adpa;
 390
 391         save_adpa = adpa = I915_READ(crt->adpa_reg);
 392         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 393
 394         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 395
 396         I915_WRITE(crt->adpa_reg, adpa);
 397
 398         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 399                      1000)) {
 400                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 401                 I915_WRITE(crt->adpa_reg, save_adpa);
 402         }
 403
 404         /* Check the status to see if both blue and green are on now */
 405         adpa = I915_READ(crt->adpa_reg);
 406         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 407                 ret = true;
 408         else
 409                 ret = false;
 410
 411         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 412
 413         return ret;
 414 }
 415
 416 /**
 417  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 418  *
 419  * Not for i915G/i915GM
 420  *
 421  * \return true if CRT is connected.
 422  * \return false if CRT is disconnected.
 423  */
 424 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 425 {
 426         struct drm_device *dev = connector->dev;
 427         struct drm_i915_private *dev_priv = dev->dev_private;
 428         u32 hotplug_en, orig, stat;
 429         bool ret = false;
 430         int i, tries = 0;
 431
 432         if (HAS_PCH_SPLIT(dev))
 433                 return intel_ironlake_crt_detect_hotplug(connector);
 434
 435         if (IS_VALLEYVIEW(dev))
 436                 return valleyview_crt_detect_hotplug(connector);
 437
 438         /*
 439          * On 4 series desktop, CRT detect sequence need to be done twice
 440          * to get a reliable result.
 441          */
 442
 443         if (IS_G4X(dev) && !IS_GM45(dev))
 444                 tries = 2;
 445         else
 446                 tries = 1;
 447         hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
 448         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
 449
 450         for (i = 0; i < tries ; i++) {
 451                 /* turn on the FORCE_DETECT */
 452                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
 453                 /* wait for FORCE_DETECT to go off */
 454                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
 455                               CRT_HOTPLUG_FORCE_DETECT) == 0,
 456                              1000))
 457                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 458         }
 459
 460         stat = I915_READ(PORT_HOTPLUG_STAT);
 461         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 462                 ret = true;
 463
 464         /* clear the interrupt we just generated, if any */
 465         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 466
 467         /* and put the bits back */
 468         I915_WRITE(PORT_HOTPLUG_EN, orig);
 469
 470         return ret;
 471 }
 472
 473 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 474                                 struct i2c_adapter *i2c)
 475 {
 476         struct edid *edid;
 477
 478         edid = drm_get_edid(connector, i2c);
 479
 480         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 481                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 482                 intel_gmbus_force_bit(i2c, true);
 483                 edid = drm_get_edid(connector, i2c);
 484                 intel_gmbus_force_bit(i2c, false);
 485         }
 486
 487         return edid;
 488 }
 489
 490 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 491 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 492                                 struct i2c_adapter *adapter)
 493 {
 494         struct edid *edid;
 495         int ret;
 496
 497         edid = intel_crt_get_edid(connector, adapter);
 498         if (!edid)
 499                 return 0;
 500
 501         ret = intel_connector_update_modes(connector, edid);
 502         kfree(edid);
 503
 504         return ret;
 505 }
 506
 507 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 508 {
 509         struct intel_crt *crt = intel_attached_crt(connector);
 510         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
 511         struct edid *edid;
 512         struct i2c_adapter *i2c;
 513
 514         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 515
 516         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 517         edid = intel_crt_get_edid(connector, i2c);
 518
 519         if (edid) {
 520                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 521
 522                 /*
 523                  * This may be a DVI-I connector with a shared DDC
 524                  * link between analog and digital outputs, so we
 525                  * have to check the EDID input spec of the attached device.
 526                  */
 527                 if (!is_digital) {
 528                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 529                         return true;
 530                 }
 531
 532                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 533         } else {
 534                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 535         }
 536
 537         kfree(edid);
 538
 539         return false;
 540 }
 541
 542 static enum drm_connector_status
 543 intel_crt_load_detect(struct intel_crt *crt)
 544 {
 545         struct drm_device *dev = crt->base.base.dev;
 546         struct drm_i915_private *dev_priv = dev->dev_private;
 547         uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
 548         uint32_t save_bclrpat;
 549         uint32_t save_vtotal;
 550         uint32_t vtotal, vactive;
 551         uint32_t vsample;
 552         uint32_t vblank, vblank_start, vblank_end;
 553         uint32_t dsl;
 554         uint32_t bclrpat_reg;
 555         uint32_t vtotal_reg;
 556         uint32_t vblank_reg;
 557         uint32_t vsync_reg;
 558         uint32_t pipeconf_reg;
 559         uint32_t pipe_dsl_reg;
 560         uint8_t st00;
 561         enum drm_connector_status status;
 562
 563         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 564
 565         bclrpat_reg = BCLRPAT(pipe);
 566         vtotal_reg = VTOTAL(pipe);
 567         vblank_reg = VBLANK(pipe);
 568         vsync_reg = VSYNC(pipe);
 569         pipeconf_reg = PIPECONF(pipe);
 570         pipe_dsl_reg = PIPEDSL(pipe);
 571
 572         save_bclrpat = I915_READ(bclrpat_reg);
 573         save_vtotal = I915_READ(vtotal_reg);
 574         vblank = I915_READ(vblank_reg);
 575
 576         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 577         vactive = (save_vtotal & 0x7ff) + 1;
 578
 579         vblank_start = (vblank & 0xfff) + 1;
 580         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 581
 582         /* Set the border color to purple. */
 583         I915_WRITE(bclrpat_reg, 0x500050);
 584
 585         if (!IS_GEN2(dev)) {
 586                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 587                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 588                 POSTING_READ(pipeconf_reg);
 589                 /* Wait for next Vblank to substitue
 590                  * border color for Color info */
 591                 intel_wait_for_vblank(dev, pipe);
 592                 st00 = I915_READ8(VGA_MSR_WRITE);
 593                 status = ((st00 & (1 << 4)) != 0) ?
 594                         connector_status_connected :
 595                         connector_status_disconnected;
 596
 597                 I915_WRITE(pipeconf_reg, pipeconf);
 598         } else {
 599                 bool restore_vblank = false;
 600                 int count, detect;
 601
 602                 /*
 603                 * If there isn't any border, add some.
 604                 * Yes, this will flicker
 605                 */
 606                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 607                         uint32_t vsync = I915_READ(vsync_reg);
 608                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 609
 610                         vblank_start = vsync_start;
 611                         I915_WRITE(vblank_reg,
 612                                    (vblank_start - 1) |
 613                                    ((vblank_end - 1) << 16));
 614                         restore_vblank = true;
 615                 }
 616                 /* sample in the vertical border, selecting the larger one */
 617                 if (vblank_start - vactive >= vtotal - vblank_end)
 618                         vsample = (vblank_start + vactive) >> 1;
 619                 else
 620                         vsample = (vtotal + vblank_end) >> 1;
 621
 622                 /*
 623                  * Wait for the border to be displayed
 624                  */
 625                 while (I915_READ(pipe_dsl_reg) >= vactive)
 626                         ;
 627                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 628                         ;
 629                 /*
 630                  * Watch ST00 for an entire scanline
 631                  */
 632                 detect = 0;
 633                 count = 0;
 634                 do {
 635                         count++;
 636                         /* Read the ST00 VGA status register */
 637                         st00 = I915_READ8(VGA_MSR_WRITE);
 638                         if (st00 & (1 << 4))
 639                                 detect++;
 640                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 641
 642                 /* restore vblank if necessary */
 643                 if (restore_vblank)
 644                         I915_WRITE(vblank_reg, vblank);
 645                 /*
 646                  * If more than 3/4 of the scanline detected a monitor,
 647                  * then it is assumed to be present. This works even on i830,
 648                  * where there isn't any way to force the border color across
 649                  * the screen
 650                  */
 651                 status = detect * 4 > count * 3 ?
 652                          connector_status_connected :
 653                          connector_status_disconnected;
 654         }
 655
 656         /* Restore previous settings */
 657         I915_WRITE(bclrpat_reg, save_bclrpat);
 658
 659         return status;
 660 }
 661
 662 static enum drm_connector_status
 663 intel_crt_detect(struct drm_connector *connector, bool force)
 664 {
 665         struct drm_device *dev = connector->dev;
 666         struct drm_i915_private *dev_priv = dev->dev_private;
 667         struct intel_crt *crt = intel_attached_crt(connector);
 668         struct intel_encoder *intel_encoder = &crt->base;
 669         enum intel_display_power_domain power_domain;
 670         enum drm_connector_status status;
 671         struct intel_load_detect_pipe tmp;
 672         struct drm_modeset_acquire_ctx ctx;
 673
 674         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 675                       connector->base.id, connector->name,
 676                       force);
 677
 678         power_domain = intel_display_port_power_domain(intel_encoder);
 679         intel_display_power_get(dev_priv, power_domain);
 680
 681         if (I915_HAS_HOTPLUG(dev)) {
 682                 /* We can not rely on the HPD pin always being correctly wired
 683                  * up, for example many KVM do not pass it through, and so
 684                  * only trust an assertion that the monitor is connected.
 685                  */
 686                 if (intel_crt_detect_hotplug(connector)) {
 687                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 688                         status = connector_status_connected;
 689                         goto out;
 690                 } else
 691                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 692         }
 693
 694         if (intel_crt_detect_ddc(connector)) {
 695                 status = connector_status_connected;
 696                 goto out;
 697         }
 698
 699         /* Load detection is broken on HPD capable machines. Whoever wants a
 700          * broken monitor (without edid) to work behind a broken kvm (that fails
 701          * to have the right resistors for HP detection) needs to fix this up.
 702          * For now just bail out. */
 703         if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
 704                 status = connector_status_disconnected;
 705                 goto out;
 706         }
 707
 708         if (!force) {
 709                 status = connector->status;
 710                 goto out;
 711         }
 712
 713         drm_modeset_acquire_init(&ctx, 0);
 714
 715         /* for pre-945g platforms use load detect */
 716         if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
 717                 if (intel_crt_detect_ddc(connector))
 718                         status = connector_status_connected;
 719                 else if (INTEL_INFO(dev)->gen < 4)
 720                         status = intel_crt_load_detect(crt);
 721                 else
 722                         status = connector_status_unknown;
 723                 intel_release_load_detect_pipe(connector, &tmp, &ctx);
 724         } else
 725                 status = connector_status_unknown;
 726
 727         drm_modeset_drop_locks(&ctx);
 728         drm_modeset_acquire_fini(&ctx);
 729
 730 out:
 731         intel_display_power_put(dev_priv, power_domain);
 732         return status;
 733 }
 734
 735 static void intel_crt_destroy(struct drm_connector *connector)
 736 {
 737         drm_connector_cleanup(connector);
 738         kfree(connector);
 739 }
 740
 741 static int intel_crt_get_modes(struct drm_connector *connector)
 742 {
 743         struct drm_device *dev = connector->dev;
 744         struct drm_i915_private *dev_priv = dev->dev_private;
 745         struct intel_crt *crt = intel_attached_crt(connector);
 746         struct intel_encoder *intel_encoder = &crt->base;
 747         enum intel_display_power_domain power_domain;
 748         int ret;
 749         struct i2c_adapter *i2c;
 750
 751         power_domain = intel_display_port_power_domain(intel_encoder);
 752         intel_display_power_get(dev_priv, power_domain);
 753
 754         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 755         ret = intel_crt_ddc_get_modes(connector, i2c);
 756         if (ret || !IS_G4X(dev))
 757                 goto out;
 758
 759         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 760         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 761         ret = intel_crt_ddc_get_modes(connector, i2c);
 762
 763 out:
 764         intel_display_power_put(dev_priv, power_domain);
 765
 766         return ret;
 767 }
 768
 769 static int intel_crt_set_property(struct drm_connector *connector,
 770                                   struct drm_property *property,
 771                                   uint64_t value)
 772 {
 773         return 0;
 774 }
 775
 776 static void intel_crt_reset(struct drm_connector *connector)
 777 {
 778         struct drm_device *dev = connector->dev;
 779         struct drm_i915_private *dev_priv = dev->dev_private;
 780         struct intel_crt *crt = intel_attached_crt(connector);
 781
 782         if (INTEL_INFO(dev)->gen >= 5) {
 783                 u32 adpa;
 784
 785                 adpa = I915_READ(crt->adpa_reg);
 786                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 787                 adpa |= ADPA_HOTPLUG_BITS;
 788                 I915_WRITE(crt->adpa_reg, adpa);
 789                 POSTING_READ(crt->adpa_reg);
 790
 791                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 792                 crt->force_hotplug_required = 1;
 793         }
 794
 795 }
 796
 797 /*
 798  * Routines for controlling stuff on the analog port
 799  */
 800
 801 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 802         .reset = intel_crt_reset,
 803         .dpms = intel_crt_dpms,
 804         .detect = intel_crt_detect,
 805         .fill_modes = drm_helper_probe_single_connector_modes,
 806         .destroy = intel_crt_destroy,
 807         .set_property = intel_crt_set_property,
 808         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 809         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 810         .atomic_get_property = intel_connector_atomic_get_property,
 811 };
 812
 813 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 814         .mode_valid = intel_crt_mode_valid,
 815         .get_modes = intel_crt_get_modes,
 816         .best_encoder = intel_best_encoder,
 817 };
 818
 819 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 820         .destroy = intel_encoder_destroy,
 821 };
 822
 823 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id)
 824 {
 825         DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
 826         return 1;
 827 }
 828
 829 static const struct dmi_system_id intel_no_crt[] = {
 830         {
 831                 .callback = intel_no_crt_dmi_callback,
 832                 .ident = "ACER ZGB",
 833                 .matches = {
 834                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 835                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 836                 },
 837         },
 838         {
 839                 .callback = intel_no_crt_dmi_callback,
 840                 .ident = "DELL XPS 8700",
 841                 .matches = {
 842                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 843                         DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"),
 844                 },
 845         },
 846         { }
 847 };
 848
 849 void intel_crt_init(struct drm_device *dev)
 850 {
 851         struct drm_connector *connector;
 852         struct intel_crt *crt;
 853         struct intel_connector *intel_connector;
 854         struct drm_i915_private *dev_priv = dev->dev_private;
 855
 856         /* Skip machines without VGA that falsely report hotplug events */
 857         if (dmi_check_system(intel_no_crt))
 858                 return;
 859
 860         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 861         if (!crt)
 862                 return;
 863
 864         intel_connector = intel_connector_alloc();
 865         if (!intel_connector) {
 866                 kfree(crt);
 867                 return;
 868         }
 869
 870         connector = &intel_connector->base;
 871         crt->connector = intel_connector;
 872         drm_connector_init(dev, &intel_connector->base,
 873                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 874
 875         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
 876                          DRM_MODE_ENCODER_DAC);
 877
 878         intel_connector_attach_encoder(intel_connector, &crt->base);
 879
 880         crt->base.type = INTEL_OUTPUT_ANALOG;
 881         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 882         if (IS_I830(dev))
 883                 crt->base.crtc_mask = (1 << 0);
 884         else
 885                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 886
 887         if (IS_GEN2(dev))
 888                 connector->interlace_allowed = 0;
 889         else
 890                 connector->interlace_allowed = 1;
 891         connector->doublescan_allowed = 0;
 892
 893         if (HAS_PCH_SPLIT(dev))
 894                 crt->adpa_reg = PCH_ADPA;
 895         else if (IS_VALLEYVIEW(dev))
 896                 crt->adpa_reg = VLV_ADPA;
 897         else
 898                 crt->adpa_reg = ADPA;
 899
 900         crt->base.compute_config = intel_crt_compute_config;
 901         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) {
 902                 crt->base.disable = pch_disable_crt;
 903                 crt->base.post_disable = pch_post_disable_crt;
 904         } else {
 905                 crt->base.disable = intel_disable_crt;
 906         }
 907         crt->base.enable = intel_enable_crt;
 908         if (I915_HAS_HOTPLUG(dev))
 909                 crt->base.hpd_pin = HPD_CRT;
 910         if (HAS_DDI(dev)) {
 911                 crt->base.get_config = hsw_crt_get_config;
 912                 crt->base.get_hw_state = intel_ddi_get_hw_state;
 913                 crt->base.pre_enable = hsw_crt_pre_enable;
 914                 crt->base.post_disable = hsw_crt_post_disable;
 915         } else {
 916                 crt->base.get_config = intel_crt_get_config;
 917                 crt->base.get_hw_state = intel_crt_get_hw_state;
 918         }
 919         intel_connector->get_hw_state = intel_connector_get_hw_state;
 920         intel_connector->unregister = intel_connector_unregister;
 921
 922         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 923
 924         drm_connector_register(connector);
 925
 926         if (!I915_HAS_HOTPLUG(dev))
 927                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 928
 929         /*
 930          * Configure the automatic hotplug detection stuff
 931          */
 932         crt->force_hotplug_required = 0;
 933
 934         /*
 935          * TODO: find a proper way to discover whether we need to set the the
 936          * polarity and link reversal bits or not, instead of relying on the
 937          * BIOS.
 938          */
 939         if (HAS_PCH_LPT(dev)) {
 940                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
 941                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
 942
 943                 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
 944         }
 945
 946         intel_crt_reset(connector);
 947 }