2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/kernel.h>
25 #include <linux/component.h>
26 #include <drm/i915_component.h>
27 #include "intel_drv.h"
30 #include <drm/drm_edid.h>
34 * DOC: High Definition Audio over HDMI and Display Port
36 * The graphics and audio drivers together support High Definition Audio over
37 * HDMI and Display Port. The audio programming sequences are divided into audio
38 * codec and controller enable and disable sequences. The graphics driver
39 * handles the audio codec sequences, while the audio driver handles the audio
40 * controller sequences.
42 * The disable sequences must be performed before disabling the transcoder or
43 * port. The enable sequences may only be performed after enabling the
44 * transcoder and port, and after completed link training. Therefore the audio
45 * enable/disable sequences are part of the modeset sequence.
47 * The codec and controller sequences could be done either parallel or serial,
48 * but generally the ELDV/PD change in the codec sequence indicates to the audio
49 * driver that the controller sequence should start. Indeed, most of the
50 * co-operation between the graphics and audio drivers is handled via audio
51 * related registers. (The notable exception is the power management, not
58 } hdmi_audio_clock[] = {
59 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
60 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
61 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
62 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
63 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
64 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
65 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
66 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
67 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
68 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
71 /* HDMI N/CTS table */
72 #define TMDS_297M 297000
73 #define TMDS_296M DIV_ROUND_UP(297000 * 1000, 1001)
80 { 44100, TMDS_296M, 4459, 234375 },
81 { 44100, TMDS_297M, 4704, 247500 },
82 { 48000, TMDS_296M, 5824, 281250 },
83 { 48000, TMDS_297M, 5120, 247500 },
84 { 32000, TMDS_296M, 5824, 421875 },
85 { 32000, TMDS_297M, 3072, 222750 },
86 { 88200, TMDS_296M, 8918, 234375 },
87 { 88200, TMDS_297M, 9408, 247500 },
88 { 96000, TMDS_296M, 11648, 281250 },
89 { 96000, TMDS_297M, 10240, 247500 },
90 { 176400, TMDS_296M, 17836, 234375 },
91 { 176400, TMDS_297M, 18816, 247500 },
92 { 192000, TMDS_296M, 23296, 281250 },
93 { 192000, TMDS_297M, 20480, 247500 },
96 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
97 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
101 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
102 if (mode->clock == hdmi_audio_clock[i].clock)
106 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
107 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
111 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
112 hdmi_audio_clock[i].clock,
113 hdmi_audio_clock[i].config);
115 return hdmi_audio_clock[i].config;
118 static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
122 for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
123 if ((rate == aud_ncts[i].sample_rate) &&
124 (mode->clock == aud_ncts[i].clock)) {
125 return aud_ncts[i].n;
131 static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
137 n_up = (n >> 12) & 0xff;
138 tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
139 tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
140 (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
141 AUD_CONFIG_N_PROG_ENABLE);
145 /* check whether N/CTS/M need be set manually */
146 static bool audio_rate_need_prog(struct intel_crtc *crtc,
147 struct drm_display_mode *mode)
149 if (((mode->clock == TMDS_297M) ||
150 (mode->clock == TMDS_296M)) &&
151 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
157 static bool intel_eld_uptodate(struct drm_connector *connector,
158 int reg_eldv, uint32_t bits_eldv,
159 int reg_elda, uint32_t bits_elda,
162 struct drm_i915_private *dev_priv = connector->dev->dev_private;
163 uint8_t *eld = connector->eld;
167 tmp = I915_READ(reg_eldv);
173 tmp = I915_READ(reg_elda);
175 I915_WRITE(reg_elda, tmp);
177 for (i = 0; i < drm_eld_size(eld) / 4; i++)
178 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
184 static void g4x_audio_codec_disable(struct intel_encoder *encoder)
186 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
189 DRM_DEBUG_KMS("Disable audio codec\n");
191 tmp = I915_READ(G4X_AUD_VID_DID);
192 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
193 eldv = G4X_ELDV_DEVCL_DEVBLC;
195 eldv = G4X_ELDV_DEVCTG;
198 tmp = I915_READ(G4X_AUD_CNTL_ST);
200 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
203 static void g4x_audio_codec_enable(struct drm_connector *connector,
204 struct intel_encoder *encoder,
205 struct drm_display_mode *mode)
207 struct drm_i915_private *dev_priv = connector->dev->dev_private;
208 uint8_t *eld = connector->eld;
213 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
215 tmp = I915_READ(G4X_AUD_VID_DID);
216 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
217 eldv = G4X_ELDV_DEVCL_DEVBLC;
219 eldv = G4X_ELDV_DEVCTG;
221 if (intel_eld_uptodate(connector,
222 G4X_AUD_CNTL_ST, eldv,
223 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
227 tmp = I915_READ(G4X_AUD_CNTL_ST);
228 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
229 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
230 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
232 len = min(drm_eld_size(eld) / 4, len);
233 DRM_DEBUG_DRIVER("ELD size %d\n", len);
234 for (i = 0; i < len; i++)
235 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
237 tmp = I915_READ(G4X_AUD_CNTL_ST);
239 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
242 static void hsw_audio_codec_disable(struct intel_encoder *encoder)
244 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
245 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
246 enum pipe pipe = intel_crtc->pipe;
249 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
251 mutex_lock(&dev_priv->av_mutex);
253 /* Disable timestamps */
254 tmp = I915_READ(HSW_AUD_CFG(pipe));
255 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
256 tmp |= AUD_CONFIG_N_PROG_ENABLE;
257 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
258 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
259 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
260 tmp |= AUD_CONFIG_N_VALUE_INDEX;
261 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
264 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
265 tmp &= ~AUDIO_ELD_VALID(pipe);
266 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
267 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
269 mutex_unlock(&dev_priv->av_mutex);
272 static void hsw_audio_codec_enable(struct drm_connector *connector,
273 struct intel_encoder *encoder,
274 struct drm_display_mode *mode)
276 struct drm_i915_private *dev_priv = connector->dev->dev_private;
277 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
278 enum pipe pipe = intel_crtc->pipe;
279 struct i915_audio_component *acomp = dev_priv->audio_component;
280 const uint8_t *eld = connector->eld;
281 struct intel_digital_port *intel_dig_port =
282 enc_to_dig_port(&encoder->base);
283 enum port port = intel_dig_port->port;
288 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
289 pipe_name(pipe), drm_eld_size(eld));
291 mutex_lock(&dev_priv->av_mutex);
293 /* Enable audio presence detect, invalidate ELD */
294 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
295 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
296 tmp &= ~AUDIO_ELD_VALID(pipe);
297 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
300 * FIXME: We're supposed to wait for vblank here, but we have vblanks
301 * disabled during the mode set. The proper fix would be to push the
302 * rest of the setup into a vblank work item, queued here, but the
303 * infrastructure is not there yet.
306 /* Reset ELD write address */
307 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
308 tmp &= ~IBX_ELD_ADDRESS_MASK;
309 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
311 /* Up to 84 bytes of hw ELD buffer */
312 len = min(drm_eld_size(eld), 84);
313 for (i = 0; i < len / 4; i++)
314 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
317 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
318 tmp |= AUDIO_ELD_VALID(pipe);
319 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
321 /* Enable timestamps */
322 tmp = I915_READ(HSW_AUD_CFG(pipe));
323 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
324 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
325 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
326 tmp |= AUD_CONFIG_N_VALUE_INDEX;
328 tmp |= audio_config_hdmi_pixel_clock(mode);
330 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
331 if (audio_rate_need_prog(intel_crtc, mode)) {
334 else if (port >= PORT_A && port <= PORT_E)
335 rate = acomp->aud_sample_rate[port];
337 DRM_ERROR("invalid port: %d\n", port);
340 n = audio_config_get_n(mode, rate);
342 tmp = audio_config_setup_n_reg(n, tmp);
344 DRM_DEBUG_KMS("no suitable N value is found\n");
347 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
349 mutex_unlock(&dev_priv->av_mutex);
352 static void ilk_audio_codec_disable(struct intel_encoder *encoder)
354 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
355 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
356 struct intel_digital_port *intel_dig_port =
357 enc_to_dig_port(&encoder->base);
358 enum port port = intel_dig_port->port;
359 enum pipe pipe = intel_crtc->pipe;
364 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
365 port_name(port), pipe_name(pipe));
367 if (WARN_ON(port == PORT_A))
370 if (HAS_PCH_IBX(dev_priv->dev)) {
371 aud_config = IBX_AUD_CFG(pipe);
372 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
373 } else if (IS_VALLEYVIEW(dev_priv)) {
374 aud_config = VLV_AUD_CFG(pipe);
375 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
377 aud_config = CPT_AUD_CFG(pipe);
378 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
381 /* Disable timestamps */
382 tmp = I915_READ(aud_config);
383 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
384 tmp |= AUD_CONFIG_N_PROG_ENABLE;
385 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
386 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
387 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
388 tmp |= AUD_CONFIG_N_VALUE_INDEX;
389 I915_WRITE(aud_config, tmp);
391 eldv = IBX_ELD_VALID(port);
394 tmp = I915_READ(aud_cntrl_st2);
396 I915_WRITE(aud_cntrl_st2, tmp);
399 static void ilk_audio_codec_enable(struct drm_connector *connector,
400 struct intel_encoder *encoder,
401 struct drm_display_mode *mode)
403 struct drm_i915_private *dev_priv = connector->dev->dev_private;
404 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
405 struct intel_digital_port *intel_dig_port =
406 enc_to_dig_port(&encoder->base);
407 enum port port = intel_dig_port->port;
408 enum pipe pipe = intel_crtc->pipe;
409 uint8_t *eld = connector->eld;
418 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
419 port_name(port), pipe_name(pipe), drm_eld_size(eld));
421 if (WARN_ON(port == PORT_A))
425 * FIXME: We're supposed to wait for vblank here, but we have vblanks
426 * disabled during the mode set. The proper fix would be to push the
427 * rest of the setup into a vblank work item, queued here, but the
428 * infrastructure is not there yet.
431 if (HAS_PCH_IBX(connector->dev)) {
432 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
433 aud_config = IBX_AUD_CFG(pipe);
434 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
435 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
436 } else if (IS_VALLEYVIEW(connector->dev)) {
437 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
438 aud_config = VLV_AUD_CFG(pipe);
439 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
440 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
442 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
443 aud_config = CPT_AUD_CFG(pipe);
444 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
445 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
448 eldv = IBX_ELD_VALID(port);
451 tmp = I915_READ(aud_cntrl_st2);
453 I915_WRITE(aud_cntrl_st2, tmp);
455 /* Reset ELD write address */
456 tmp = I915_READ(aud_cntl_st);
457 tmp &= ~IBX_ELD_ADDRESS_MASK;
458 I915_WRITE(aud_cntl_st, tmp);
460 /* Up to 84 bytes of hw ELD buffer */
461 len = min(drm_eld_size(eld), 84);
462 for (i = 0; i < len / 4; i++)
463 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
466 tmp = I915_READ(aud_cntrl_st2);
468 I915_WRITE(aud_cntrl_st2, tmp);
470 /* Enable timestamps */
471 tmp = I915_READ(aud_config);
472 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
473 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
474 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
475 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
476 tmp |= AUD_CONFIG_N_VALUE_INDEX;
478 tmp |= audio_config_hdmi_pixel_clock(mode);
479 I915_WRITE(aud_config, tmp);
483 * intel_audio_codec_enable - Enable the audio codec for HD audio
484 * @intel_encoder: encoder on which to enable audio
486 * The enable sequences may only be performed after enabling the transcoder and
487 * port, and after completed link training.
489 void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
491 struct drm_encoder *encoder = &intel_encoder->base;
492 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
493 struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
494 struct drm_connector *connector;
495 struct drm_device *dev = encoder->dev;
496 struct drm_i915_private *dev_priv = dev->dev_private;
497 struct i915_audio_component *acomp = dev_priv->audio_component;
498 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
499 enum port port = intel_dig_port->port;
501 connector = drm_select_eld(encoder, mode);
505 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
508 connector->encoder->base.id,
509 connector->encoder->name);
512 connector->eld[5] &= ~(3 << 2);
513 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
514 connector->eld[5] |= (1 << 2);
516 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
518 if (dev_priv->display.audio_codec_enable)
519 dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
521 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
522 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
526 * intel_audio_codec_disable - Disable the audio codec for HD audio
527 * @intel_encoder: encoder on which to disable audio
529 * The disable sequences must be performed before disabling the transcoder or
532 void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
534 struct drm_encoder *encoder = &intel_encoder->base;
535 struct drm_device *dev = encoder->dev;
536 struct drm_i915_private *dev_priv = dev->dev_private;
537 struct i915_audio_component *acomp = dev_priv->audio_component;
538 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
539 enum port port = intel_dig_port->port;
541 if (dev_priv->display.audio_codec_disable)
542 dev_priv->display.audio_codec_disable(intel_encoder);
544 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
545 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
549 * intel_init_audio - Set up chip specific audio functions
552 void intel_init_audio(struct drm_device *dev)
554 struct drm_i915_private *dev_priv = dev->dev_private;
557 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
558 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
559 } else if (IS_VALLEYVIEW(dev)) {
560 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
561 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
562 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
563 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
564 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
565 } else if (HAS_PCH_SPLIT(dev)) {
566 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
567 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
571 static void i915_audio_component_get_power(struct device *dev)
573 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
576 static void i915_audio_component_put_power(struct device *dev)
578 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
581 static void i915_audio_component_codec_wake_override(struct device *dev,
584 struct drm_i915_private *dev_priv = dev_to_i915(dev);
587 if (!IS_SKYLAKE(dev_priv))
591 * Enable/disable generating the codec wake signal, overriding the
592 * internal logic to generate the codec wake to controller.
594 tmp = I915_READ(HSW_AUD_CHICKENBIT);
595 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
596 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
597 usleep_range(1000, 1500);
600 tmp = I915_READ(HSW_AUD_CHICKENBIT);
601 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
602 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
603 usleep_range(1000, 1500);
607 /* Get CDCLK in kHz */
608 static int i915_audio_component_get_cdclk_freq(struct device *dev)
610 struct drm_i915_private *dev_priv = dev_to_i915(dev);
613 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
616 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
617 ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
619 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
624 static int i915_audio_component_sync_audio_rate(struct device *dev,
627 struct drm_i915_private *dev_priv = dev_to_i915(dev);
628 struct drm_device *drm_dev = dev_priv->dev;
629 struct intel_encoder *intel_encoder;
630 struct intel_digital_port *intel_dig_port;
631 struct intel_crtc *crtc;
632 struct drm_display_mode *mode;
633 struct i915_audio_component *acomp = dev_priv->audio_component;
638 /* HSW, BDW SKL need this fix */
639 if (!IS_SKYLAKE(dev_priv) &&
640 !IS_BROADWELL(dev_priv) &&
641 !IS_HASWELL(dev_priv))
644 mutex_lock(&dev_priv->av_mutex);
645 /* 1. get the pipe */
646 for_each_intel_encoder(drm_dev, intel_encoder) {
647 if (intel_encoder->type != INTEL_OUTPUT_HDMI)
649 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
650 if (port == intel_dig_port->port) {
651 crtc = to_intel_crtc(intel_encoder->base.crtc);
653 DRM_DEBUG_KMS("%s: crtc is NULL\n", __func__);
661 if (pipe == INVALID_PIPE) {
662 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
663 mutex_unlock(&dev_priv->av_mutex);
666 DRM_DEBUG_KMS("pipe %c connects port %c\n",
667 pipe_name(pipe), port_name(port));
668 mode = &crtc->config->base.adjusted_mode;
670 /* port must be valid now, otherwise the pipe will be invalid */
671 acomp->aud_sample_rate[port] = rate;
673 /* 2. check whether to set the N/CTS/M manually or not */
674 if (!audio_rate_need_prog(crtc, mode)) {
675 tmp = I915_READ(HSW_AUD_CFG(pipe));
676 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
677 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
678 mutex_unlock(&dev_priv->av_mutex);
682 n = audio_config_get_n(mode, rate);
684 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
686 tmp = I915_READ(HSW_AUD_CFG(pipe));
687 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
688 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
689 mutex_unlock(&dev_priv->av_mutex);
693 /* 3. set the N/CTS/M */
694 tmp = I915_READ(HSW_AUD_CFG(pipe));
695 tmp = audio_config_setup_n_reg(n, tmp);
696 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
698 mutex_unlock(&dev_priv->av_mutex);
702 static const struct i915_audio_component_ops i915_audio_component_ops = {
703 .owner = THIS_MODULE,
704 .get_power = i915_audio_component_get_power,
705 .put_power = i915_audio_component_put_power,
706 .codec_wake_override = i915_audio_component_codec_wake_override,
707 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
708 .sync_audio_rate = i915_audio_component_sync_audio_rate,
711 static int i915_audio_component_bind(struct device *i915_dev,
712 struct device *hda_dev, void *data)
714 struct i915_audio_component *acomp = data;
715 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
718 if (WARN_ON(acomp->ops || acomp->dev))
721 drm_modeset_lock_all(dev_priv->dev);
722 acomp->ops = &i915_audio_component_ops;
723 acomp->dev = i915_dev;
724 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
725 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
726 acomp->aud_sample_rate[i] = 0;
727 dev_priv->audio_component = acomp;
728 drm_modeset_unlock_all(dev_priv->dev);
733 static void i915_audio_component_unbind(struct device *i915_dev,
734 struct device *hda_dev, void *data)
736 struct i915_audio_component *acomp = data;
737 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
739 drm_modeset_lock_all(dev_priv->dev);
742 dev_priv->audio_component = NULL;
743 drm_modeset_unlock_all(dev_priv->dev);
746 static const struct component_ops i915_audio_component_bind_ops = {
747 .bind = i915_audio_component_bind,
748 .unbind = i915_audio_component_unbind,
752 * i915_audio_component_init - initialize and register the audio component
753 * @dev_priv: i915 device instance
755 * This will register with the component framework a child component which
756 * will bind dynamically to the snd_hda_intel driver's corresponding master
757 * component when the latter is registered. During binding the child
758 * initializes an instance of struct i915_audio_component which it receives
759 * from the master. The master can then start to use the interface defined by
760 * this struct. Each side can break the binding at any point by deregistering
761 * its own component after which each side's component unbind callback is
764 * We ignore any error during registration and continue with reduced
765 * functionality (i.e. without HDMI audio).
767 void i915_audio_component_init(struct drm_i915_private *dev_priv)
771 ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
773 DRM_ERROR("failed to add audio component (%d)\n", ret);
774 /* continue with reduced functionality */
778 dev_priv->audio_component_registered = true;
782 * i915_audio_component_cleanup - deregister the audio component
783 * @dev_priv: i915 device instance
785 * Deregisters the audio component, breaking any existing binding to the
786 * corresponding snd_hda_intel driver's master component.
788 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
790 if (!dev_priv->audio_component_registered)
793 component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
794 dev_priv->audio_component_registered = false;