2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/kernel.h>
25 #include <linux/component.h>
26 #include <drm/i915_component.h>
27 #include "intel_drv.h"
30 #include <drm/drm_edid.h>
34 * DOC: High Definition Audio over HDMI and Display Port
36 * The graphics and audio drivers together support High Definition Audio over
37 * HDMI and Display Port. The audio programming sequences are divided into audio
38 * codec and controller enable and disable sequences. The graphics driver
39 * handles the audio codec sequences, while the audio driver handles the audio
40 * controller sequences.
42 * The disable sequences must be performed before disabling the transcoder or
43 * port. The enable sequences may only be performed after enabling the
44 * transcoder and port, and after completed link training.
46 * The codec and controller sequences could be done either parallel or serial,
47 * but generally the ELDV/PD change in the codec sequence indicates to the audio
48 * driver that the controller sequence should start. Indeed, most of the
49 * co-operation between the graphics and audio drivers is handled via audio
50 * related registers. (The notable exception is the power management, not
57 } hdmi_audio_clock[] = {
58 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
59 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
60 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
61 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
62 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
63 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
64 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
65 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
66 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
67 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
70 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
71 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
75 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
76 if (mode->clock == hdmi_audio_clock[i].clock)
80 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
81 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
85 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
86 hdmi_audio_clock[i].clock,
87 hdmi_audio_clock[i].config);
89 return hdmi_audio_clock[i].config;
92 static bool intel_eld_uptodate(struct drm_connector *connector,
93 int reg_eldv, uint32_t bits_eldv,
94 int reg_elda, uint32_t bits_elda,
97 struct drm_i915_private *dev_priv = connector->dev->dev_private;
98 uint8_t *eld = connector->eld;
102 tmp = I915_READ(reg_eldv);
108 tmp = I915_READ(reg_elda);
110 I915_WRITE(reg_elda, tmp);
112 for (i = 0; i < drm_eld_size(eld) / 4; i++)
113 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
119 static void g4x_audio_codec_disable(struct intel_encoder *encoder)
121 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
124 DRM_DEBUG_KMS("Disable audio codec\n");
126 tmp = I915_READ(G4X_AUD_VID_DID);
127 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
128 eldv = G4X_ELDV_DEVCL_DEVBLC;
130 eldv = G4X_ELDV_DEVCTG;
133 tmp = I915_READ(G4X_AUD_CNTL_ST);
135 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
138 static void g4x_audio_codec_enable(struct drm_connector *connector,
139 struct intel_encoder *encoder,
140 struct drm_display_mode *mode)
142 struct drm_i915_private *dev_priv = connector->dev->dev_private;
143 uint8_t *eld = connector->eld;
148 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
150 tmp = I915_READ(G4X_AUD_VID_DID);
151 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
152 eldv = G4X_ELDV_DEVCL_DEVBLC;
154 eldv = G4X_ELDV_DEVCTG;
156 if (intel_eld_uptodate(connector,
157 G4X_AUD_CNTL_ST, eldv,
158 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
162 tmp = I915_READ(G4X_AUD_CNTL_ST);
163 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
164 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
165 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
167 len = min(drm_eld_size(eld) / 4, len);
168 DRM_DEBUG_DRIVER("ELD size %d\n", len);
169 for (i = 0; i < len; i++)
170 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
172 tmp = I915_READ(G4X_AUD_CNTL_ST);
174 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
177 static void hsw_audio_codec_disable(struct intel_encoder *encoder)
179 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
180 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
181 enum pipe pipe = intel_crtc->pipe;
184 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
186 /* Disable timestamps */
187 tmp = I915_READ(HSW_AUD_CFG(pipe));
188 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
189 tmp |= AUD_CONFIG_N_PROG_ENABLE;
190 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
191 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
192 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
193 tmp |= AUD_CONFIG_N_VALUE_INDEX;
194 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
197 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
198 tmp &= ~AUDIO_ELD_VALID(pipe);
199 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
200 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
203 static void hsw_audio_codec_enable(struct drm_connector *connector,
204 struct intel_encoder *encoder,
205 struct drm_display_mode *mode)
207 struct drm_i915_private *dev_priv = connector->dev->dev_private;
208 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
209 enum pipe pipe = intel_crtc->pipe;
210 const uint8_t *eld = connector->eld;
214 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
215 pipe_name(pipe), drm_eld_size(eld));
217 /* Enable audio presence detect, invalidate ELD */
218 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
219 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
220 tmp &= ~AUDIO_ELD_VALID(pipe);
221 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
224 * FIXME: We're supposed to wait for vblank here, but we have vblanks
225 * disabled during the mode set. The proper fix would be to push the
226 * rest of the setup into a vblank work item, queued here, but the
227 * infrastructure is not there yet.
230 /* Reset ELD write address */
231 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
232 tmp &= ~IBX_ELD_ADDRESS_MASK;
233 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
235 /* Up to 84 bytes of hw ELD buffer */
236 len = min(drm_eld_size(eld), 84);
237 for (i = 0; i < len / 4; i++)
238 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
241 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
242 tmp |= AUDIO_ELD_VALID(pipe);
243 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
245 /* Enable timestamps */
246 tmp = I915_READ(HSW_AUD_CFG(pipe));
247 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
248 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
249 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
250 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
251 tmp |= AUD_CONFIG_N_VALUE_INDEX;
253 tmp |= audio_config_hdmi_pixel_clock(mode);
254 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
257 static void ilk_audio_codec_disable(struct intel_encoder *encoder)
259 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
260 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
261 struct intel_digital_port *intel_dig_port =
262 enc_to_dig_port(&encoder->base);
263 enum port port = intel_dig_port->port;
264 enum pipe pipe = intel_crtc->pipe;
269 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
270 port_name(port), pipe_name(pipe));
272 if (WARN_ON(port == PORT_A))
275 if (HAS_PCH_IBX(dev_priv->dev)) {
276 aud_config = IBX_AUD_CFG(pipe);
277 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
278 } else if (IS_VALLEYVIEW(dev_priv)) {
279 aud_config = VLV_AUD_CFG(pipe);
280 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
282 aud_config = CPT_AUD_CFG(pipe);
283 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
286 /* Disable timestamps */
287 tmp = I915_READ(aud_config);
288 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
289 tmp |= AUD_CONFIG_N_PROG_ENABLE;
290 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
291 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
292 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
293 tmp |= AUD_CONFIG_N_VALUE_INDEX;
294 I915_WRITE(aud_config, tmp);
296 eldv = IBX_ELD_VALID(port);
299 tmp = I915_READ(aud_cntrl_st2);
301 I915_WRITE(aud_cntrl_st2, tmp);
304 static void ilk_audio_codec_enable(struct drm_connector *connector,
305 struct intel_encoder *encoder,
306 struct drm_display_mode *mode)
308 struct drm_i915_private *dev_priv = connector->dev->dev_private;
309 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
310 struct intel_digital_port *intel_dig_port =
311 enc_to_dig_port(&encoder->base);
312 enum port port = intel_dig_port->port;
313 enum pipe pipe = intel_crtc->pipe;
314 uint8_t *eld = connector->eld;
323 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
324 port_name(port), pipe_name(pipe), drm_eld_size(eld));
326 if (WARN_ON(port == PORT_A))
330 * FIXME: We're supposed to wait for vblank here, but we have vblanks
331 * disabled during the mode set. The proper fix would be to push the
332 * rest of the setup into a vblank work item, queued here, but the
333 * infrastructure is not there yet.
336 if (HAS_PCH_IBX(connector->dev)) {
337 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
338 aud_config = IBX_AUD_CFG(pipe);
339 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
340 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
341 } else if (IS_VALLEYVIEW(connector->dev)) {
342 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
343 aud_config = VLV_AUD_CFG(pipe);
344 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
345 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
347 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
348 aud_config = CPT_AUD_CFG(pipe);
349 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
350 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
353 eldv = IBX_ELD_VALID(port);
356 tmp = I915_READ(aud_cntrl_st2);
358 I915_WRITE(aud_cntrl_st2, tmp);
360 /* Reset ELD write address */
361 tmp = I915_READ(aud_cntl_st);
362 tmp &= ~IBX_ELD_ADDRESS_MASK;
363 I915_WRITE(aud_cntl_st, tmp);
365 /* Up to 84 bytes of hw ELD buffer */
366 len = min(drm_eld_size(eld), 84);
367 for (i = 0; i < len / 4; i++)
368 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
371 tmp = I915_READ(aud_cntrl_st2);
373 I915_WRITE(aud_cntrl_st2, tmp);
375 /* Enable timestamps */
376 tmp = I915_READ(aud_config);
377 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
378 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
379 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
380 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
381 tmp |= AUD_CONFIG_N_VALUE_INDEX;
383 tmp |= audio_config_hdmi_pixel_clock(mode);
384 I915_WRITE(aud_config, tmp);
388 * intel_audio_codec_enable - Enable the audio codec for HD audio
389 * @intel_encoder: encoder on which to enable audio
391 * The enable sequences may only be performed after enabling the transcoder and
392 * port, and after completed link training.
394 void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
396 struct drm_encoder *encoder = &intel_encoder->base;
397 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
398 struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
399 struct drm_connector *connector;
400 struct drm_device *dev = encoder->dev;
401 struct drm_i915_private *dev_priv = dev->dev_private;
402 struct i915_audio_component *acomp = dev_priv->audio_component;
403 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
404 enum port port = intel_dig_port->port;
406 connector = drm_select_eld(encoder, mode);
410 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
413 connector->encoder->base.id,
414 connector->encoder->name);
417 connector->eld[5] &= ~(3 << 2);
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
419 connector->eld[5] |= (1 << 2);
421 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
423 if (dev_priv->display.audio_codec_enable)
424 dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
426 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
427 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
431 * intel_audio_codec_disable - Disable the audio codec for HD audio
432 * @encoder: encoder on which to disable audio
434 * The disable sequences must be performed before disabling the transcoder or
437 void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
439 struct drm_encoder *encoder = &intel_encoder->base;
440 struct drm_device *dev = encoder->dev;
441 struct drm_i915_private *dev_priv = dev->dev_private;
442 struct i915_audio_component *acomp = dev_priv->audio_component;
443 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
444 enum port port = intel_dig_port->port;
446 if (dev_priv->display.audio_codec_disable)
447 dev_priv->display.audio_codec_disable(intel_encoder);
449 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
450 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
454 * intel_init_audio - Set up chip specific audio functions
457 void intel_init_audio(struct drm_device *dev)
459 struct drm_i915_private *dev_priv = dev->dev_private;
462 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
463 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
464 } else if (IS_VALLEYVIEW(dev)) {
465 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
466 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
467 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
468 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
469 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
470 } else if (HAS_PCH_SPLIT(dev)) {
471 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
472 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
476 static void i915_audio_component_get_power(struct device *dev)
478 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
481 static void i915_audio_component_put_power(struct device *dev)
483 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
486 static void i915_audio_component_codec_wake_override(struct device *dev,
489 struct drm_i915_private *dev_priv = dev_to_i915(dev);
492 if (!IS_SKYLAKE(dev_priv))
496 * Enable/disable generating the codec wake signal, overriding the
497 * internal logic to generate the codec wake to controller.
499 tmp = I915_READ(HSW_AUD_CHICKENBIT);
500 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
501 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
502 usleep_range(1000, 1500);
505 tmp = I915_READ(HSW_AUD_CHICKENBIT);
506 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
507 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
508 usleep_range(1000, 1500);
512 /* Get CDCLK in kHz */
513 static int i915_audio_component_get_cdclk_freq(struct device *dev)
515 struct drm_i915_private *dev_priv = dev_to_i915(dev);
518 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
521 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
522 ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
524 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
529 static const struct i915_audio_component_ops i915_audio_component_ops = {
530 .owner = THIS_MODULE,
531 .get_power = i915_audio_component_get_power,
532 .put_power = i915_audio_component_put_power,
533 .codec_wake_override = i915_audio_component_codec_wake_override,
534 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
537 static int i915_audio_component_bind(struct device *i915_dev,
538 struct device *hda_dev, void *data)
540 struct i915_audio_component *acomp = data;
541 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
543 if (WARN_ON(acomp->ops || acomp->dev))
546 acomp->ops = &i915_audio_component_ops;
547 acomp->dev = i915_dev;
548 dev_priv->audio_component = acomp;
553 static void i915_audio_component_unbind(struct device *i915_dev,
554 struct device *hda_dev, void *data)
556 struct i915_audio_component *acomp = data;
557 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
561 dev_priv->audio_component = NULL;
564 static const struct component_ops i915_audio_component_bind_ops = {
565 .bind = i915_audio_component_bind,
566 .unbind = i915_audio_component_unbind,
570 * i915_audio_component_init - initialize and register the audio component
571 * @dev_priv: i915 device instance
573 * This will register with the component framework a child component which
574 * will bind dynamically to the snd_hda_intel driver's corresponding master
575 * component when the latter is registered. During binding the child
576 * initializes an instance of struct i915_audio_component which it receives
577 * from the master. The master can then start to use the interface defined by
578 * this struct. Each side can break the binding at any point by deregistering
579 * its own component after which each side's component unbind callback is
582 * We ignore any error during registration and continue with reduced
583 * functionality (i.e. without HDMI audio).
585 void i915_audio_component_init(struct drm_i915_private *dev_priv)
589 ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
591 DRM_ERROR("failed to add audio component (%d)\n", ret);
592 /* continue with reduced functionality */
596 dev_priv->audio_component_registered = true;
600 * i915_audio_component_cleanup - deregister the audio component
601 * @dev_priv: i915 device instance
603 * Deregisters the audio component, breaking any existing binding to the
604 * corresponding snd_hda_intel driver's master component.
606 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
608 if (!dev_priv->audio_component_registered)
611 component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
612 dev_priv->audio_component_registered = false;