1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
40 static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
48 static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
56 static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
65 static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
83 /* IIR can theoretically queue up two events. Be paranoid. */
84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
94 #define GEN5_IRQ_RESET(type) do { \
95 I915_WRITE(type##IMR, 0xffffffff); \
96 POSTING_READ(type##IMR); \
97 I915_WRITE(type##IER, 0); \
98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
112 I915_WRITE((reg), 0xffffffff); \
114 I915_WRITE((reg), 0xffffffff); \
119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
133 /* For display hotplug interrupt */
135 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
137 assert_spin_locked(&dev_priv->irq_lock);
139 if (WARN_ON(dev_priv->pm.irqs_disabled))
142 if ((dev_priv->irq_mask & mask) != 0) {
143 dev_priv->irq_mask &= ~mask;
144 I915_WRITE(DEIMR, dev_priv->irq_mask);
150 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
152 assert_spin_locked(&dev_priv->irq_lock);
154 if (WARN_ON(dev_priv->pm.irqs_disabled))
157 if ((dev_priv->irq_mask & mask) != mask) {
158 dev_priv->irq_mask |= mask;
159 I915_WRITE(DEIMR, dev_priv->irq_mask);
165 * ilk_update_gt_irq - update GTIMR
166 * @dev_priv: driver private
167 * @interrupt_mask: mask of interrupt bits to update
168 * @enabled_irq_mask: mask of interrupt bits to enable
170 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
171 uint32_t interrupt_mask,
172 uint32_t enabled_irq_mask)
174 assert_spin_locked(&dev_priv->irq_lock);
176 if (WARN_ON(dev_priv->pm.irqs_disabled))
179 dev_priv->gt_irq_mask &= ~interrupt_mask;
180 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
181 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
185 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
187 ilk_update_gt_irq(dev_priv, mask, mask);
190 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
192 ilk_update_gt_irq(dev_priv, mask, 0);
196 * snb_update_pm_irq - update GEN6_PMIMR
197 * @dev_priv: driver private
198 * @interrupt_mask: mask of interrupt bits to update
199 * @enabled_irq_mask: mask of interrupt bits to enable
201 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
202 uint32_t interrupt_mask,
203 uint32_t enabled_irq_mask)
207 assert_spin_locked(&dev_priv->irq_lock);
209 if (WARN_ON(dev_priv->pm.irqs_disabled))
212 new_val = dev_priv->pm_irq_mask;
213 new_val &= ~interrupt_mask;
214 new_val |= (~enabled_irq_mask & interrupt_mask);
216 if (new_val != dev_priv->pm_irq_mask) {
217 dev_priv->pm_irq_mask = new_val;
218 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
219 POSTING_READ(GEN6_PMIMR);
223 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
225 snb_update_pm_irq(dev_priv, mask, mask);
228 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
230 snb_update_pm_irq(dev_priv, mask, 0);
233 static bool ivb_can_enable_err_int(struct drm_device *dev)
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 struct intel_crtc *crtc;
239 assert_spin_locked(&dev_priv->irq_lock);
241 for_each_pipe(pipe) {
242 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
244 if (crtc->cpu_fifo_underrun_disabled)
252 * bdw_update_pm_irq - update GT interrupt 2
253 * @dev_priv: driver private
254 * @interrupt_mask: mask of interrupt bits to update
255 * @enabled_irq_mask: mask of interrupt bits to enable
257 * Copied from the snb function, updated with relevant register offsets
259 static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
260 uint32_t interrupt_mask,
261 uint32_t enabled_irq_mask)
265 assert_spin_locked(&dev_priv->irq_lock);
267 if (WARN_ON(dev_priv->pm.irqs_disabled))
270 new_val = dev_priv->pm_irq_mask;
271 new_val &= ~interrupt_mask;
272 new_val |= (~enabled_irq_mask & interrupt_mask);
274 if (new_val != dev_priv->pm_irq_mask) {
275 dev_priv->pm_irq_mask = new_val;
276 I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
277 POSTING_READ(GEN8_GT_IMR(2));
281 void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
283 bdw_update_pm_irq(dev_priv, mask, mask);
286 void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
288 bdw_update_pm_irq(dev_priv, mask, 0);
291 static bool cpt_can_enable_serr_int(struct drm_device *dev)
293 struct drm_i915_private *dev_priv = dev->dev_private;
295 struct intel_crtc *crtc;
297 assert_spin_locked(&dev_priv->irq_lock);
299 for_each_pipe(pipe) {
300 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
302 if (crtc->pch_fifo_underrun_disabled)
309 void i9xx_check_fifo_underruns(struct drm_device *dev)
311 struct drm_i915_private *dev_priv = dev->dev_private;
312 struct intel_crtc *crtc;
315 spin_lock_irqsave(&dev_priv->irq_lock, flags);
317 for_each_intel_crtc(dev, crtc) {
318 u32 reg = PIPESTAT(crtc->pipe);
321 if (crtc->cpu_fifo_underrun_disabled)
324 pipestat = I915_READ(reg) & 0xffff0000;
325 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
328 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
331 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
334 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
337 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
339 bool enable, bool old)
341 struct drm_i915_private *dev_priv = dev->dev_private;
342 u32 reg = PIPESTAT(pipe);
343 u32 pipestat = I915_READ(reg) & 0xffff0000;
345 assert_spin_locked(&dev_priv->irq_lock);
348 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
351 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
352 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
356 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
357 enum pipe pipe, bool enable)
359 struct drm_i915_private *dev_priv = dev->dev_private;
360 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
361 DE_PIPEB_FIFO_UNDERRUN;
364 ironlake_enable_display_irq(dev_priv, bit);
366 ironlake_disable_display_irq(dev_priv, bit);
369 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
371 bool enable, bool old)
373 struct drm_i915_private *dev_priv = dev->dev_private;
375 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
377 if (!ivb_can_enable_err_int(dev))
380 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
382 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
385 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
386 DRM_ERROR("uncleared fifo underrun on pipe %c\n",
392 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
393 enum pipe pipe, bool enable)
395 struct drm_i915_private *dev_priv = dev->dev_private;
397 assert_spin_locked(&dev_priv->irq_lock);
400 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
402 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
403 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
404 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
408 * ibx_display_interrupt_update - update SDEIMR
409 * @dev_priv: driver private
410 * @interrupt_mask: mask of interrupt bits to update
411 * @enabled_irq_mask: mask of interrupt bits to enable
413 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
414 uint32_t interrupt_mask,
415 uint32_t enabled_irq_mask)
417 uint32_t sdeimr = I915_READ(SDEIMR);
418 sdeimr &= ~interrupt_mask;
419 sdeimr |= (~enabled_irq_mask & interrupt_mask);
421 assert_spin_locked(&dev_priv->irq_lock);
423 if (WARN_ON(dev_priv->pm.irqs_disabled))
426 I915_WRITE(SDEIMR, sdeimr);
427 POSTING_READ(SDEIMR);
429 #define ibx_enable_display_interrupt(dev_priv, bits) \
430 ibx_display_interrupt_update((dev_priv), (bits), (bits))
431 #define ibx_disable_display_interrupt(dev_priv, bits) \
432 ibx_display_interrupt_update((dev_priv), (bits), 0)
434 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
435 enum transcoder pch_transcoder,
438 struct drm_i915_private *dev_priv = dev->dev_private;
439 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
440 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
443 ibx_enable_display_interrupt(dev_priv, bit);
445 ibx_disable_display_interrupt(dev_priv, bit);
448 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
449 enum transcoder pch_transcoder,
450 bool enable, bool old)
452 struct drm_i915_private *dev_priv = dev->dev_private;
456 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
458 if (!cpt_can_enable_serr_int(dev))
461 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
463 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
465 if (old && I915_READ(SERR_INT) &
466 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
467 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
468 transcoder_name(pch_transcoder));
474 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
477 * @enable: true if we want to report FIFO underrun errors, false otherwise
479 * This function makes us disable or enable CPU fifo underruns for a specific
480 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
481 * reporting for one pipe may also disable all the other CPU error interruts for
482 * the other pipes, due to the fact that there's just one interrupt mask/enable
483 * bit for all the pipes.
485 * Returns the previous state of underrun reporting.
487 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
488 enum pipe pipe, bool enable)
490 struct drm_i915_private *dev_priv = dev->dev_private;
491 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
495 assert_spin_locked(&dev_priv->irq_lock);
497 old = !intel_crtc->cpu_fifo_underrun_disabled;
498 intel_crtc->cpu_fifo_underrun_disabled = !enable;
500 if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
501 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
502 else if (IS_GEN5(dev) || IS_GEN6(dev))
503 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
504 else if (IS_GEN7(dev))
505 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
506 else if (IS_GEN8(dev))
507 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
512 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
513 enum pipe pipe, bool enable)
515 struct drm_i915_private *dev_priv = dev->dev_private;
519 spin_lock_irqsave(&dev_priv->irq_lock, flags);
520 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
521 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
526 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
529 struct drm_i915_private *dev_priv = dev->dev_private;
530 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
533 return !intel_crtc->cpu_fifo_underrun_disabled;
537 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
539 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
540 * @enable: true if we want to report FIFO underrun errors, false otherwise
542 * This function makes us disable or enable PCH fifo underruns for a specific
543 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
544 * underrun reporting for one transcoder may also disable all the other PCH
545 * error interruts for the other transcoders, due to the fact that there's just
546 * one interrupt mask/enable bit for all the transcoders.
548 * Returns the previous state of underrun reporting.
550 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
551 enum transcoder pch_transcoder,
554 struct drm_i915_private *dev_priv = dev->dev_private;
555 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
561 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
562 * has only one pch transcoder A that all pipes can use. To avoid racy
563 * pch transcoder -> pipe lookups from interrupt code simply store the
564 * underrun statistics in crtc A. Since we never expose this anywhere
565 * nor use it outside of the fifo underrun code here using the "wrong"
566 * crtc on LPT won't cause issues.
569 spin_lock_irqsave(&dev_priv->irq_lock, flags);
571 old = !intel_crtc->pch_fifo_underrun_disabled;
572 intel_crtc->pch_fifo_underrun_disabled = !enable;
574 if (HAS_PCH_IBX(dev))
575 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
577 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);
579 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
585 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
586 u32 enable_mask, u32 status_mask)
588 u32 reg = PIPESTAT(pipe);
589 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
591 assert_spin_locked(&dev_priv->irq_lock);
593 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
594 status_mask & ~PIPESTAT_INT_STATUS_MASK,
595 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
596 pipe_name(pipe), enable_mask, status_mask))
599 if ((pipestat & enable_mask) == enable_mask)
602 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
604 /* Enable the interrupt, clear any pending status */
605 pipestat |= enable_mask | status_mask;
606 I915_WRITE(reg, pipestat);
611 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
612 u32 enable_mask, u32 status_mask)
614 u32 reg = PIPESTAT(pipe);
615 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
617 assert_spin_locked(&dev_priv->irq_lock);
619 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
620 status_mask & ~PIPESTAT_INT_STATUS_MASK,
621 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
622 pipe_name(pipe), enable_mask, status_mask))
625 if ((pipestat & enable_mask) == 0)
628 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
630 pipestat &= ~enable_mask;
631 I915_WRITE(reg, pipestat);
635 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
637 u32 enable_mask = status_mask << 16;
640 * On pipe A we don't support the PSR interrupt yet,
641 * on pipe B and C the same bit MBZ.
643 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
646 * On pipe B and C we don't support the PSR interrupt yet, on pipe
647 * A the same bit is for perf counters which we don't use either.
649 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
652 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
653 SPRITE0_FLIP_DONE_INT_EN_VLV |
654 SPRITE1_FLIP_DONE_INT_EN_VLV);
655 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
656 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
657 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
658 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
664 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
669 if (IS_VALLEYVIEW(dev_priv->dev))
670 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
673 enable_mask = status_mask << 16;
674 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
678 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
683 if (IS_VALLEYVIEW(dev_priv->dev))
684 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
687 enable_mask = status_mask << 16;
688 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
692 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
694 static void i915_enable_asle_pipestat(struct drm_device *dev)
696 struct drm_i915_private *dev_priv = dev->dev_private;
697 unsigned long irqflags;
699 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
702 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
704 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
705 if (INTEL_INFO(dev)->gen >= 4)
706 i915_enable_pipestat(dev_priv, PIPE_A,
707 PIPE_LEGACY_BLC_EVENT_STATUS);
709 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
713 * i915_pipe_enabled - check if a pipe is enabled
715 * @pipe: pipe to check
717 * Reading certain registers when the pipe is disabled can hang the chip.
718 * Use this routine to make sure the PLL is running and the pipe is active
719 * before reading such registers if unsure.
722 i915_pipe_enabled(struct drm_device *dev, int pipe)
724 struct drm_i915_private *dev_priv = dev->dev_private;
726 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
727 /* Locking is horribly broken here, but whatever. */
728 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
731 return intel_crtc->active;
733 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
738 * This timing diagram depicts the video signal in and
739 * around the vertical blanking period.
741 * Assumptions about the fictitious mode used in this example:
743 * vsync_start = vblank_start + 1
744 * vsync_end = vblank_start + 2
745 * vtotal = vblank_start + 3
748 * latch double buffered registers
749 * increment frame counter (ctg+)
750 * generate start of vblank interrupt (gen4+)
753 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
754 * | may be shifted forward 1-3 extra lines via PIPECONF
756 * | | start of vsync:
757 * | | generate vsync interrupt
759 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
760 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
761 * ----va---> <-----------------vb--------------------> <--------va-------------
762 * | | <----vs-----> |
763 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
764 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
765 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
767 * last visible pixel first visible pixel
768 * | increment frame counter (gen3/4)
769 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
771 * x = horizontal active
772 * _ = horizontal blanking
773 * hs = horizontal sync
774 * va = vertical active
775 * vb = vertical blanking
777 * vbs = vblank_start (number)
780 * - most events happen at the start of horizontal sync
781 * - frame start happens at the start of horizontal blank, 1-4 lines
782 * (depending on PIPECONF settings) after the start of vblank
783 * - gen3/4 pixel and frame counter are synchronized with the start
784 * of horizontal active on the first line of vertical active
787 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
789 /* Gen2 doesn't have a hardware frame counter */
793 /* Called from drm generic code, passed a 'crtc', which
794 * we use as a pipe index
796 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
798 struct drm_i915_private *dev_priv = dev->dev_private;
799 unsigned long high_frame;
800 unsigned long low_frame;
801 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
803 if (!i915_pipe_enabled(dev, pipe)) {
804 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
805 "pipe %c\n", pipe_name(pipe));
809 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
810 struct intel_crtc *intel_crtc =
811 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
812 const struct drm_display_mode *mode =
813 &intel_crtc->config.adjusted_mode;
815 htotal = mode->crtc_htotal;
816 hsync_start = mode->crtc_hsync_start;
817 vbl_start = mode->crtc_vblank_start;
818 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
819 vbl_start = DIV_ROUND_UP(vbl_start, 2);
821 enum transcoder cpu_transcoder = (enum transcoder) pipe;
823 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
824 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
825 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
826 if ((I915_READ(PIPECONF(cpu_transcoder)) &
827 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
828 vbl_start = DIV_ROUND_UP(vbl_start, 2);
831 /* Convert to pixel count */
834 /* Start of vblank event occurs at start of hsync */
835 vbl_start -= htotal - hsync_start;
837 high_frame = PIPEFRAME(pipe);
838 low_frame = PIPEFRAMEPIXEL(pipe);
841 * High & low register fields aren't synchronized, so make sure
842 * we get a low value that's stable across two reads of the high
846 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
847 low = I915_READ(low_frame);
848 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
849 } while (high1 != high2);
851 high1 >>= PIPE_FRAME_HIGH_SHIFT;
852 pixel = low & PIPE_PIXEL_MASK;
853 low >>= PIPE_FRAME_LOW_SHIFT;
856 * The frame counter increments at beginning of active.
857 * Cook up a vblank counter by also checking the pixel
858 * counter against vblank start.
860 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
863 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 int reg = PIPE_FRMCOUNT_GM45(pipe);
868 if (!i915_pipe_enabled(dev, pipe)) {
869 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
870 "pipe %c\n", pipe_name(pipe));
874 return I915_READ(reg);
877 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
878 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
880 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
882 struct drm_device *dev = crtc->base.dev;
883 struct drm_i915_private *dev_priv = dev->dev_private;
884 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
885 enum pipe pipe = crtc->pipe;
886 int position, vtotal;
888 vtotal = mode->crtc_vtotal;
889 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
893 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
895 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
898 * See update_scanline_offset() for the details on the
899 * scanline_offset adjustment.
901 return (position + crtc->scanline_offset) % vtotal;
904 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
905 unsigned int flags, int *vpos, int *hpos,
906 ktime_t *stime, ktime_t *etime)
908 struct drm_i915_private *dev_priv = dev->dev_private;
909 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
911 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
913 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
916 unsigned long irqflags;
918 if (!intel_crtc->active) {
919 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
920 "pipe %c\n", pipe_name(pipe));
924 htotal = mode->crtc_htotal;
925 hsync_start = mode->crtc_hsync_start;
926 vtotal = mode->crtc_vtotal;
927 vbl_start = mode->crtc_vblank_start;
928 vbl_end = mode->crtc_vblank_end;
930 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
931 vbl_start = DIV_ROUND_UP(vbl_start, 2);
936 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
939 * Lock uncore.lock, as we will do multiple timing critical raw
940 * register reads, potentially with preemption disabled, so the
941 * following code must not block on uncore.lock.
943 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
945 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
947 /* Get optional system timestamp before query. */
949 *stime = ktime_get();
951 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
952 /* No obvious pixelcount register. Only query vertical
953 * scanout position from Display scan line register.
955 position = __intel_get_crtc_scanline(intel_crtc);
957 /* Have access to pixelcount since start of frame.
958 * We can split this into vertical and horizontal
961 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
963 /* convert to pixel counts */
969 * In interlaced modes, the pixel counter counts all pixels,
970 * so one field will have htotal more pixels. In order to avoid
971 * the reported position from jumping backwards when the pixel
972 * counter is beyond the length of the shorter field, just
973 * clamp the position the length of the shorter field. This
974 * matches how the scanline counter based position works since
975 * the scanline counter doesn't count the two half lines.
977 if (position >= vtotal)
978 position = vtotal - 1;
981 * Start of vblank interrupt is triggered at start of hsync,
982 * just prior to the first active line of vblank. However we
983 * consider lines to start at the leading edge of horizontal
984 * active. So, should we get here before we've crossed into
985 * the horizontal active of the first line in vblank, we would
986 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
987 * always add htotal-hsync_start to the current pixel position.
989 position = (position + htotal - hsync_start) % vtotal;
992 /* Get optional system timestamp after query. */
994 *etime = ktime_get();
996 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
998 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1000 in_vbl = position >= vbl_start && position < vbl_end;
1003 * While in vblank, position will be negative
1004 * counting up towards 0 at vbl_end. And outside
1005 * vblank, position will be positive counting
1008 if (position >= vbl_start)
1009 position -= vbl_end;
1011 position += vtotal - vbl_end;
1013 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
1017 *vpos = position / htotal;
1018 *hpos = position - (*vpos * htotal);
1023 ret |= DRM_SCANOUTPOS_INVBL;
1028 int intel_get_crtc_scanline(struct intel_crtc *crtc)
1030 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1031 unsigned long irqflags;
1034 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1035 position = __intel_get_crtc_scanline(crtc);
1036 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1041 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
1043 struct timeval *vblank_time,
1046 struct drm_crtc *crtc;
1048 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
1049 DRM_ERROR("Invalid crtc %d\n", pipe);
1053 /* Get drm_crtc to timestamp: */
1054 crtc = intel_get_crtc_for_pipe(dev, pipe);
1056 DRM_ERROR("Invalid crtc %d\n", pipe);
1060 if (!crtc->enabled) {
1061 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1065 /* Helper routine in DRM core does all the work: */
1066 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
1069 &to_intel_crtc(crtc)->config.adjusted_mode);
1072 static bool intel_hpd_irq_event(struct drm_device *dev,
1073 struct drm_connector *connector)
1075 enum drm_connector_status old_status;
1077 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1078 old_status = connector->status;
1080 connector->status = connector->funcs->detect(connector, false);
1081 if (old_status == connector->status)
1084 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
1087 drm_get_connector_status_name(old_status),
1088 drm_get_connector_status_name(connector->status));
1094 * Handle hotplug events outside the interrupt handler proper.
1096 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
1098 static void i915_hotplug_work_func(struct work_struct *work)
1100 struct drm_i915_private *dev_priv =
1101 container_of(work, struct drm_i915_private, hotplug_work);
1102 struct drm_device *dev = dev_priv->dev;
1103 struct drm_mode_config *mode_config = &dev->mode_config;
1104 struct intel_connector *intel_connector;
1105 struct intel_encoder *intel_encoder;
1106 struct drm_connector *connector;
1107 unsigned long irqflags;
1108 bool hpd_disabled = false;
1109 bool changed = false;
1112 /* HPD irq before everything is fully set up. */
1113 if (!dev_priv->enable_hotplug_processing)
1116 mutex_lock(&mode_config->mutex);
1117 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1119 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1121 hpd_event_bits = dev_priv->hpd_event_bits;
1122 dev_priv->hpd_event_bits = 0;
1123 list_for_each_entry(connector, &mode_config->connector_list, head) {
1124 intel_connector = to_intel_connector(connector);
1125 intel_encoder = intel_connector->encoder;
1126 if (intel_encoder->hpd_pin > HPD_NONE &&
1127 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1128 connector->polled == DRM_CONNECTOR_POLL_HPD) {
1129 DRM_INFO("HPD interrupt storm detected on connector %s: "
1130 "switching from hotplug detection to polling\n",
1132 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1133 connector->polled = DRM_CONNECTOR_POLL_CONNECT
1134 | DRM_CONNECTOR_POLL_DISCONNECT;
1135 hpd_disabled = true;
1137 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1138 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1139 connector->name, intel_encoder->hpd_pin);
1142 /* if there were no outputs to poll, poll was disabled,
1143 * therefore make sure it's enabled when disabling HPD on
1144 * some connectors */
1146 drm_kms_helper_poll_enable(dev);
1147 mod_timer(&dev_priv->hotplug_reenable_timer,
1148 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1151 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1153 list_for_each_entry(connector, &mode_config->connector_list, head) {
1154 intel_connector = to_intel_connector(connector);
1155 intel_encoder = intel_connector->encoder;
1156 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1157 if (intel_encoder->hot_plug)
1158 intel_encoder->hot_plug(intel_encoder);
1159 if (intel_hpd_irq_event(dev, connector))
1163 mutex_unlock(&mode_config->mutex);
1166 drm_kms_helper_hotplug_event(dev);
1169 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1171 del_timer_sync(&dev_priv->hotplug_reenable_timer);
1174 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1177 u32 busy_up, busy_down, max_avg, min_avg;
1180 spin_lock(&mchdev_lock);
1182 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1184 new_delay = dev_priv->ips.cur_delay;
1186 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1187 busy_up = I915_READ(RCPREVBSYTUPAVG);
1188 busy_down = I915_READ(RCPREVBSYTDNAVG);
1189 max_avg = I915_READ(RCBMAXAVG);
1190 min_avg = I915_READ(RCBMINAVG);
1192 /* Handle RCS change request from hw */
1193 if (busy_up > max_avg) {
1194 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1195 new_delay = dev_priv->ips.cur_delay - 1;
1196 if (new_delay < dev_priv->ips.max_delay)
1197 new_delay = dev_priv->ips.max_delay;
1198 } else if (busy_down < min_avg) {
1199 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1200 new_delay = dev_priv->ips.cur_delay + 1;
1201 if (new_delay > dev_priv->ips.min_delay)
1202 new_delay = dev_priv->ips.min_delay;
1205 if (ironlake_set_drps(dev, new_delay))
1206 dev_priv->ips.cur_delay = new_delay;
1208 spin_unlock(&mchdev_lock);
1213 static void notify_ring(struct drm_device *dev,
1214 struct intel_engine_cs *ring)
1216 if (!intel_ring_initialized(ring))
1219 trace_i915_gem_request_complete(ring);
1221 wake_up_all(&ring->irq_queue);
1222 i915_queue_hangcheck(dev);
1225 static void gen6_pm_rps_work(struct work_struct *work)
1227 struct drm_i915_private *dev_priv =
1228 container_of(work, struct drm_i915_private, rps.work);
1232 spin_lock_irq(&dev_priv->irq_lock);
1233 pm_iir = dev_priv->rps.pm_iir;
1234 dev_priv->rps.pm_iir = 0;
1235 if (IS_BROADWELL(dev_priv->dev))
1236 bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1238 /* Make sure not to corrupt PMIMR state used by ringbuffer */
1239 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1241 spin_unlock_irq(&dev_priv->irq_lock);
1243 /* Make sure we didn't queue anything we're not going to process. */
1244 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1246 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1249 mutex_lock(&dev_priv->rps.hw_lock);
1251 adj = dev_priv->rps.last_adj;
1252 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1257 new_delay = dev_priv->rps.cur_freq + adj;
1260 * For better performance, jump directly
1261 * to RPe if we're below it.
1263 if (new_delay < dev_priv->rps.efficient_freq)
1264 new_delay = dev_priv->rps.efficient_freq;
1265 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1266 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1267 new_delay = dev_priv->rps.efficient_freq;
1269 new_delay = dev_priv->rps.min_freq_softlimit;
1271 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1276 new_delay = dev_priv->rps.cur_freq + adj;
1277 } else { /* unknown event */
1278 new_delay = dev_priv->rps.cur_freq;
1281 /* sysfs frequency interfaces may have snuck in while servicing the
1284 new_delay = clamp_t(int, new_delay,
1285 dev_priv->rps.min_freq_softlimit,
1286 dev_priv->rps.max_freq_softlimit);
1288 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1290 if (IS_VALLEYVIEW(dev_priv->dev))
1291 valleyview_set_rps(dev_priv->dev, new_delay);
1293 gen6_set_rps(dev_priv->dev, new_delay);
1295 mutex_unlock(&dev_priv->rps.hw_lock);
1300 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1302 * @work: workqueue struct
1304 * Doesn't actually do anything except notify userspace. As a consequence of
1305 * this event, userspace should try to remap the bad rows since statistically
1306 * it is likely the same row is more likely to go bad again.
1308 static void ivybridge_parity_work(struct work_struct *work)
1310 struct drm_i915_private *dev_priv =
1311 container_of(work, struct drm_i915_private, l3_parity.error_work);
1312 u32 error_status, row, bank, subbank;
1313 char *parity_event[6];
1315 unsigned long flags;
1318 /* We must turn off DOP level clock gating to access the L3 registers.
1319 * In order to prevent a get/put style interface, acquire struct mutex
1320 * any time we access those registers.
1322 mutex_lock(&dev_priv->dev->struct_mutex);
1324 /* If we've screwed up tracking, just let the interrupt fire again */
1325 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1328 misccpctl = I915_READ(GEN7_MISCCPCTL);
1329 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1330 POSTING_READ(GEN7_MISCCPCTL);
1332 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1336 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1339 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1341 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1343 error_status = I915_READ(reg);
1344 row = GEN7_PARITY_ERROR_ROW(error_status);
1345 bank = GEN7_PARITY_ERROR_BANK(error_status);
1346 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1348 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1351 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1352 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1353 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1354 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1355 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1356 parity_event[5] = NULL;
1358 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1359 KOBJ_CHANGE, parity_event);
1361 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1362 slice, row, bank, subbank);
1364 kfree(parity_event[4]);
1365 kfree(parity_event[3]);
1366 kfree(parity_event[2]);
1367 kfree(parity_event[1]);
1370 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1373 WARN_ON(dev_priv->l3_parity.which_slice);
1374 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1375 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1376 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1378 mutex_unlock(&dev_priv->dev->struct_mutex);
1381 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1383 struct drm_i915_private *dev_priv = dev->dev_private;
1385 if (!HAS_L3_DPF(dev))
1388 spin_lock(&dev_priv->irq_lock);
1389 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1390 spin_unlock(&dev_priv->irq_lock);
1392 iir &= GT_PARITY_ERROR(dev);
1393 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1394 dev_priv->l3_parity.which_slice |= 1 << 1;
1396 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1397 dev_priv->l3_parity.which_slice |= 1 << 0;
1399 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1402 static void ilk_gt_irq_handler(struct drm_device *dev,
1403 struct drm_i915_private *dev_priv,
1407 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1408 notify_ring(dev, &dev_priv->ring[RCS]);
1409 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1410 notify_ring(dev, &dev_priv->ring[VCS]);
1413 static void snb_gt_irq_handler(struct drm_device *dev,
1414 struct drm_i915_private *dev_priv,
1419 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1420 notify_ring(dev, &dev_priv->ring[RCS]);
1421 if (gt_iir & GT_BSD_USER_INTERRUPT)
1422 notify_ring(dev, &dev_priv->ring[VCS]);
1423 if (gt_iir & GT_BLT_USER_INTERRUPT)
1424 notify_ring(dev, &dev_priv->ring[BCS]);
1426 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1427 GT_BSD_CS_ERROR_INTERRUPT |
1428 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1429 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1433 if (gt_iir & GT_PARITY_ERROR(dev))
1434 ivybridge_parity_error_irq_handler(dev, gt_iir);
1437 static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1439 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1442 spin_lock(&dev_priv->irq_lock);
1443 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1444 bdw_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1445 spin_unlock(&dev_priv->irq_lock);
1447 queue_work(dev_priv->wq, &dev_priv->rps.work);
1450 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1451 struct drm_i915_private *dev_priv,
1456 irqreturn_t ret = IRQ_NONE;
1458 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1459 tmp = I915_READ(GEN8_GT_IIR(0));
1462 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1463 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1464 if (rcs & GT_RENDER_USER_INTERRUPT)
1465 notify_ring(dev, &dev_priv->ring[RCS]);
1466 if (bcs & GT_RENDER_USER_INTERRUPT)
1467 notify_ring(dev, &dev_priv->ring[BCS]);
1468 I915_WRITE(GEN8_GT_IIR(0), tmp);
1470 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1473 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1474 tmp = I915_READ(GEN8_GT_IIR(1));
1477 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1478 if (vcs & GT_RENDER_USER_INTERRUPT)
1479 notify_ring(dev, &dev_priv->ring[VCS]);
1480 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1481 if (vcs & GT_RENDER_USER_INTERRUPT)
1482 notify_ring(dev, &dev_priv->ring[VCS2]);
1483 I915_WRITE(GEN8_GT_IIR(1), tmp);
1485 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1488 if (master_ctl & GEN8_GT_PM_IRQ) {
1489 tmp = I915_READ(GEN8_GT_IIR(2));
1490 if (tmp & dev_priv->pm_rps_events) {
1492 gen8_rps_irq_handler(dev_priv, tmp);
1493 I915_WRITE(GEN8_GT_IIR(2),
1494 tmp & dev_priv->pm_rps_events);
1496 DRM_ERROR("The master control interrupt lied (PM)!\n");
1499 if (master_ctl & GEN8_GT_VECS_IRQ) {
1500 tmp = I915_READ(GEN8_GT_IIR(3));
1503 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1504 if (vcs & GT_RENDER_USER_INTERRUPT)
1505 notify_ring(dev, &dev_priv->ring[VECS]);
1506 I915_WRITE(GEN8_GT_IIR(3), tmp);
1508 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1514 #define HPD_STORM_DETECT_PERIOD 1000
1515 #define HPD_STORM_THRESHOLD 5
1517 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1518 u32 hotplug_trigger,
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1523 bool storm_detected = false;
1525 if (!hotplug_trigger)
1528 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1531 spin_lock(&dev_priv->irq_lock);
1532 for (i = 1; i < HPD_NUM_PINS; i++) {
1534 if (hpd[i] & hotplug_trigger &&
1535 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1537 * On GMCH platforms the interrupt mask bits only
1538 * prevent irq generation, not the setting of the
1539 * hotplug bits itself. So only WARN about unexpected
1540 * interrupts on saner platforms.
1542 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1543 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1544 hotplug_trigger, i, hpd[i]);
1549 if (!(hpd[i] & hotplug_trigger) ||
1550 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1553 dev_priv->hpd_event_bits |= (1 << i);
1554 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1555 dev_priv->hpd_stats[i].hpd_last_jiffies
1556 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1557 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1558 dev_priv->hpd_stats[i].hpd_cnt = 0;
1559 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1560 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1561 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1562 dev_priv->hpd_event_bits &= ~(1 << i);
1563 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1564 storm_detected = true;
1566 dev_priv->hpd_stats[i].hpd_cnt++;
1567 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1568 dev_priv->hpd_stats[i].hpd_cnt);
1573 dev_priv->display.hpd_irq_setup(dev);
1574 spin_unlock(&dev_priv->irq_lock);
1577 * Our hotplug handler can grab modeset locks (by calling down into the
1578 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1579 * queue for otherwise the flush_work in the pageflip code will
1582 schedule_work(&dev_priv->hotplug_work);
1585 static void gmbus_irq_handler(struct drm_device *dev)
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1589 wake_up_all(&dev_priv->gmbus_wait_queue);
1592 static void dp_aux_irq_handler(struct drm_device *dev)
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1596 wake_up_all(&dev_priv->gmbus_wait_queue);
1599 #if defined(CONFIG_DEBUG_FS)
1600 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1601 uint32_t crc0, uint32_t crc1,
1602 uint32_t crc2, uint32_t crc3,
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1607 struct intel_pipe_crc_entry *entry;
1610 spin_lock(&pipe_crc->lock);
1612 if (!pipe_crc->entries) {
1613 spin_unlock(&pipe_crc->lock);
1614 DRM_ERROR("spurious interrupt\n");
1618 head = pipe_crc->head;
1619 tail = pipe_crc->tail;
1621 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1622 spin_unlock(&pipe_crc->lock);
1623 DRM_ERROR("CRC buffer overflowing\n");
1627 entry = &pipe_crc->entries[head];
1629 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1630 entry->crc[0] = crc0;
1631 entry->crc[1] = crc1;
1632 entry->crc[2] = crc2;
1633 entry->crc[3] = crc3;
1634 entry->crc[4] = crc4;
1636 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1637 pipe_crc->head = head;
1639 spin_unlock(&pipe_crc->lock);
1641 wake_up_interruptible(&pipe_crc->wq);
1645 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1646 uint32_t crc0, uint32_t crc1,
1647 uint32_t crc2, uint32_t crc3,
1652 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1654 struct drm_i915_private *dev_priv = dev->dev_private;
1656 display_pipe_crc_irq_handler(dev, pipe,
1657 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1661 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1665 display_pipe_crc_irq_handler(dev, pipe,
1666 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1667 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1668 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1669 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1670 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1673 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676 uint32_t res1, res2;
1678 if (INTEL_INFO(dev)->gen >= 3)
1679 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1683 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1684 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1688 display_pipe_crc_irq_handler(dev, pipe,
1689 I915_READ(PIPE_CRC_RES_RED(pipe)),
1690 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1691 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1695 /* The RPS events need forcewake, so we add them to a work queue and mask their
1696 * IMR bits until the work is done. Other interrupts can be processed without
1697 * the work queue. */
1698 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1700 if (pm_iir & dev_priv->pm_rps_events) {
1701 spin_lock(&dev_priv->irq_lock);
1702 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1703 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1704 spin_unlock(&dev_priv->irq_lock);
1706 queue_work(dev_priv->wq, &dev_priv->rps.work);
1709 if (HAS_VEBOX(dev_priv->dev)) {
1710 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1711 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1713 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1714 i915_handle_error(dev_priv->dev, false,
1715 "VEBOX CS error interrupt 0x%08x",
1721 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1723 struct intel_crtc *crtc;
1725 if (!drm_handle_vblank(dev, pipe))
1728 crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1729 wake_up(&crtc->vbl_wait);
1734 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1736 struct drm_i915_private *dev_priv = dev->dev_private;
1737 u32 pipe_stats[I915_MAX_PIPES] = { };
1740 spin_lock(&dev_priv->irq_lock);
1741 for_each_pipe(pipe) {
1743 u32 mask, iir_bit = 0;
1746 * PIPESTAT bits get signalled even when the interrupt is
1747 * disabled with the mask bits, and some of the status bits do
1748 * not generate interrupts at all (like the underrun bit). Hence
1749 * we need to be careful that we only handle what we want to
1753 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1754 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1758 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1761 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1764 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1768 mask |= dev_priv->pipestat_irq_mask[pipe];
1773 reg = PIPESTAT(pipe);
1774 mask |= PIPESTAT_INT_ENABLE_MASK;
1775 pipe_stats[pipe] = I915_READ(reg) & mask;
1778 * Clear the PIPE*STAT regs before the IIR
1780 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1781 PIPESTAT_INT_STATUS_MASK))
1782 I915_WRITE(reg, pipe_stats[pipe]);
1784 spin_unlock(&dev_priv->irq_lock);
1786 for_each_pipe(pipe) {
1787 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1788 intel_pipe_handle_vblank(dev, pipe);
1790 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1791 intel_prepare_page_flip(dev, pipe);
1792 intel_finish_page_flip(dev, pipe);
1795 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1796 i9xx_pipe_crc_irq_handler(dev, pipe);
1798 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1799 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1800 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1803 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1804 gmbus_irq_handler(dev);
1807 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1813 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1815 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
1817 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1819 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1822 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1823 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1824 dp_aux_irq_handler(dev);
1826 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1828 * Make sure hotplug status is cleared before we clear IIR, or else we
1829 * may miss hotplug events.
1831 POSTING_READ(PORT_HOTPLUG_STAT);
1834 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1836 struct drm_device *dev = arg;
1837 struct drm_i915_private *dev_priv = dev->dev_private;
1838 u32 iir, gt_iir, pm_iir;
1839 irqreturn_t ret = IRQ_NONE;
1842 iir = I915_READ(VLV_IIR);
1843 gt_iir = I915_READ(GTIIR);
1844 pm_iir = I915_READ(GEN6_PMIIR);
1846 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1851 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1853 valleyview_pipestat_irq_handler(dev, iir);
1855 /* Consume port. Then clear IIR or we'll miss events */
1856 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1857 i9xx_hpd_irq_handler(dev);
1860 gen6_rps_irq_handler(dev_priv, pm_iir);
1862 I915_WRITE(GTIIR, gt_iir);
1863 I915_WRITE(GEN6_PMIIR, pm_iir);
1864 I915_WRITE(VLV_IIR, iir);
1871 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1873 struct drm_device *dev = arg;
1874 struct drm_i915_private *dev_priv = dev->dev_private;
1875 u32 master_ctl, iir;
1876 irqreturn_t ret = IRQ_NONE;
1879 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1880 iir = I915_READ(VLV_IIR);
1882 if (master_ctl == 0 && iir == 0)
1885 I915_WRITE(GEN8_MASTER_IRQ, 0);
1887 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1889 valleyview_pipestat_irq_handler(dev, iir);
1891 /* Consume port. Then clear IIR or we'll miss events */
1892 i9xx_hpd_irq_handler(dev);
1894 I915_WRITE(VLV_IIR, iir);
1896 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1897 POSTING_READ(GEN8_MASTER_IRQ);
1905 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1907 struct drm_i915_private *dev_priv = dev->dev_private;
1909 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1911 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1913 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1914 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1915 SDE_AUDIO_POWER_SHIFT);
1916 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1920 if (pch_iir & SDE_AUX_MASK)
1921 dp_aux_irq_handler(dev);
1923 if (pch_iir & SDE_GMBUS)
1924 gmbus_irq_handler(dev);
1926 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1927 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1929 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1930 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1932 if (pch_iir & SDE_POISON)
1933 DRM_ERROR("PCH poison interrupt\n");
1935 if (pch_iir & SDE_FDI_MASK)
1937 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1939 I915_READ(FDI_RX_IIR(pipe)));
1941 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1942 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1944 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1945 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1947 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1948 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1950 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1952 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1953 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1955 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1958 static void ivb_err_int_handler(struct drm_device *dev)
1960 struct drm_i915_private *dev_priv = dev->dev_private;
1961 u32 err_int = I915_READ(GEN7_ERR_INT);
1964 if (err_int & ERR_INT_POISON)
1965 DRM_ERROR("Poison interrupt\n");
1967 for_each_pipe(pipe) {
1968 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1969 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1971 DRM_ERROR("Pipe %c FIFO underrun\n",
1975 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1976 if (IS_IVYBRIDGE(dev))
1977 ivb_pipe_crc_irq_handler(dev, pipe);
1979 hsw_pipe_crc_irq_handler(dev, pipe);
1983 I915_WRITE(GEN7_ERR_INT, err_int);
1986 static void cpt_serr_int_handler(struct drm_device *dev)
1988 struct drm_i915_private *dev_priv = dev->dev_private;
1989 u32 serr_int = I915_READ(SERR_INT);
1991 if (serr_int & SERR_INT_POISON)
1992 DRM_ERROR("PCH poison interrupt\n");
1994 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1995 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1997 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1999 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2000 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
2002 DRM_ERROR("PCH transcoder B FIFO underrun\n");
2004 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2005 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
2007 DRM_ERROR("PCH transcoder C FIFO underrun\n");
2009 I915_WRITE(SERR_INT, serr_int);
2012 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2016 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2018 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
2020 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2021 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2022 SDE_AUDIO_POWER_SHIFT_CPT);
2023 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2027 if (pch_iir & SDE_AUX_MASK_CPT)
2028 dp_aux_irq_handler(dev);
2030 if (pch_iir & SDE_GMBUS_CPT)
2031 gmbus_irq_handler(dev);
2033 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2034 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2036 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2037 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2039 if (pch_iir & SDE_FDI_MASK_CPT)
2041 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2043 I915_READ(FDI_RX_IIR(pipe)));
2045 if (pch_iir & SDE_ERROR_CPT)
2046 cpt_serr_int_handler(dev);
2049 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2054 if (de_iir & DE_AUX_CHANNEL_A)
2055 dp_aux_irq_handler(dev);
2057 if (de_iir & DE_GSE)
2058 intel_opregion_asle_intr(dev);
2060 if (de_iir & DE_POISON)
2061 DRM_ERROR("Poison interrupt\n");
2063 for_each_pipe(pipe) {
2064 if (de_iir & DE_PIPE_VBLANK(pipe))
2065 intel_pipe_handle_vblank(dev, pipe);
2067 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2068 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
2069 DRM_ERROR("Pipe %c FIFO underrun\n",
2072 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2073 i9xx_pipe_crc_irq_handler(dev, pipe);
2075 /* plane/pipes map 1:1 on ilk+ */
2076 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2077 intel_prepare_page_flip(dev, pipe);
2078 intel_finish_page_flip_plane(dev, pipe);
2082 /* check event from PCH */
2083 if (de_iir & DE_PCH_EVENT) {
2084 u32 pch_iir = I915_READ(SDEIIR);
2086 if (HAS_PCH_CPT(dev))
2087 cpt_irq_handler(dev, pch_iir);
2089 ibx_irq_handler(dev, pch_iir);
2091 /* should clear PCH hotplug event before clear CPU irq */
2092 I915_WRITE(SDEIIR, pch_iir);
2095 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2096 ironlake_rps_change_irq_handler(dev);
2099 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2101 struct drm_i915_private *dev_priv = dev->dev_private;
2104 if (de_iir & DE_ERR_INT_IVB)
2105 ivb_err_int_handler(dev);
2107 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2108 dp_aux_irq_handler(dev);
2110 if (de_iir & DE_GSE_IVB)
2111 intel_opregion_asle_intr(dev);
2113 for_each_pipe(pipe) {
2114 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2115 intel_pipe_handle_vblank(dev, pipe);
2117 /* plane/pipes map 1:1 on ilk+ */
2118 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2119 intel_prepare_page_flip(dev, pipe);
2120 intel_finish_page_flip_plane(dev, pipe);
2124 /* check event from PCH */
2125 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2126 u32 pch_iir = I915_READ(SDEIIR);
2128 cpt_irq_handler(dev, pch_iir);
2130 /* clear PCH hotplug event before clear CPU irq */
2131 I915_WRITE(SDEIIR, pch_iir);
2135 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2137 struct drm_device *dev = arg;
2138 struct drm_i915_private *dev_priv = dev->dev_private;
2139 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2140 irqreturn_t ret = IRQ_NONE;
2142 /* We get interrupts on unclaimed registers, so check for this before we
2143 * do any I915_{READ,WRITE}. */
2144 intel_uncore_check_errors(dev);
2146 /* disable master interrupt before clearing iir */
2147 de_ier = I915_READ(DEIER);
2148 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2149 POSTING_READ(DEIER);
2151 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2152 * interrupts will will be stored on its back queue, and then we'll be
2153 * able to process them after we restore SDEIER (as soon as we restore
2154 * it, we'll get an interrupt if SDEIIR still has something to process
2155 * due to its back queue). */
2156 if (!HAS_PCH_NOP(dev)) {
2157 sde_ier = I915_READ(SDEIER);
2158 I915_WRITE(SDEIER, 0);
2159 POSTING_READ(SDEIER);
2162 gt_iir = I915_READ(GTIIR);
2164 if (INTEL_INFO(dev)->gen >= 6)
2165 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2167 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2168 I915_WRITE(GTIIR, gt_iir);
2172 de_iir = I915_READ(DEIIR);
2174 if (INTEL_INFO(dev)->gen >= 7)
2175 ivb_display_irq_handler(dev, de_iir);
2177 ilk_display_irq_handler(dev, de_iir);
2178 I915_WRITE(DEIIR, de_iir);
2182 if (INTEL_INFO(dev)->gen >= 6) {
2183 u32 pm_iir = I915_READ(GEN6_PMIIR);
2185 gen6_rps_irq_handler(dev_priv, pm_iir);
2186 I915_WRITE(GEN6_PMIIR, pm_iir);
2191 I915_WRITE(DEIER, de_ier);
2192 POSTING_READ(DEIER);
2193 if (!HAS_PCH_NOP(dev)) {
2194 I915_WRITE(SDEIER, sde_ier);
2195 POSTING_READ(SDEIER);
2201 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2203 struct drm_device *dev = arg;
2204 struct drm_i915_private *dev_priv = dev->dev_private;
2206 irqreturn_t ret = IRQ_NONE;
2210 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2211 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2215 I915_WRITE(GEN8_MASTER_IRQ, 0);
2216 POSTING_READ(GEN8_MASTER_IRQ);
2218 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2220 if (master_ctl & GEN8_DE_MISC_IRQ) {
2221 tmp = I915_READ(GEN8_DE_MISC_IIR);
2222 if (tmp & GEN8_DE_MISC_GSE)
2223 intel_opregion_asle_intr(dev);
2225 DRM_ERROR("Unexpected DE Misc interrupt\n");
2227 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2230 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2235 if (master_ctl & GEN8_DE_PORT_IRQ) {
2236 tmp = I915_READ(GEN8_DE_PORT_IIR);
2237 if (tmp & GEN8_AUX_CHANNEL_A)
2238 dp_aux_irq_handler(dev);
2240 DRM_ERROR("Unexpected DE Port interrupt\n");
2242 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2245 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2250 for_each_pipe(pipe) {
2253 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2256 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2257 if (pipe_iir & GEN8_PIPE_VBLANK)
2258 intel_pipe_handle_vblank(dev, pipe);
2260 if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) {
2261 intel_prepare_page_flip(dev, pipe);
2262 intel_finish_page_flip_plane(dev, pipe);
2265 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2266 hsw_pipe_crc_irq_handler(dev, pipe);
2268 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2269 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2271 DRM_ERROR("Pipe %c FIFO underrun\n",
2275 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2276 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2278 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2283 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2285 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2288 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2290 * FIXME(BDW): Assume for now that the new interrupt handling
2291 * scheme also closed the SDE interrupt handling race we've seen
2292 * on older pch-split platforms. But this needs testing.
2294 u32 pch_iir = I915_READ(SDEIIR);
2296 cpt_irq_handler(dev, pch_iir);
2299 I915_WRITE(SDEIIR, pch_iir);
2304 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2305 POSTING_READ(GEN8_MASTER_IRQ);
2310 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2311 bool reset_completed)
2313 struct intel_engine_cs *ring;
2317 * Notify all waiters for GPU completion events that reset state has
2318 * been changed, and that they need to restart their wait after
2319 * checking for potential errors (and bail out to drop locks if there is
2320 * a gpu reset pending so that i915_error_work_func can acquire them).
2323 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2324 for_each_ring(ring, dev_priv, i)
2325 wake_up_all(&ring->irq_queue);
2327 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2328 wake_up_all(&dev_priv->pending_flip_queue);
2331 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2332 * reset state is cleared.
2334 if (reset_completed)
2335 wake_up_all(&dev_priv->gpu_error.reset_queue);
2339 * i915_error_work_func - do process context error handling work
2340 * @work: work struct
2342 * Fire an error uevent so userspace can see that a hang or error
2345 static void i915_error_work_func(struct work_struct *work)
2347 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2349 struct drm_i915_private *dev_priv =
2350 container_of(error, struct drm_i915_private, gpu_error);
2351 struct drm_device *dev = dev_priv->dev;
2352 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2353 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2354 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2357 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2360 * Note that there's only one work item which does gpu resets, so we
2361 * need not worry about concurrent gpu resets potentially incrementing
2362 * error->reset_counter twice. We only need to take care of another
2363 * racing irq/hangcheck declaring the gpu dead for a second time. A
2364 * quick check for that is good enough: schedule_work ensures the
2365 * correct ordering between hang detection and this work item, and since
2366 * the reset in-progress bit is only ever set by code outside of this
2367 * work we don't need to worry about any other races.
2369 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2370 DRM_DEBUG_DRIVER("resetting chip\n");
2371 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2375 * In most cases it's guaranteed that we get here with an RPM
2376 * reference held, for example because there is a pending GPU
2377 * request that won't finish until the reset is done. This
2378 * isn't the case at least when we get here by doing a
2379 * simulated reset via debugs, so get an RPM reference.
2381 intel_runtime_pm_get(dev_priv);
2383 * All state reset _must_ be completed before we update the
2384 * reset counter, for otherwise waiters might miss the reset
2385 * pending state and not properly drop locks, resulting in
2386 * deadlocks with the reset work.
2388 ret = i915_reset(dev);
2390 intel_display_handle_reset(dev);
2392 intel_runtime_pm_put(dev_priv);
2396 * After all the gem state is reset, increment the reset
2397 * counter and wake up everyone waiting for the reset to
2400 * Since unlock operations are a one-sided barrier only,
2401 * we need to insert a barrier here to order any seqno
2403 * the counter increment.
2405 smp_mb__before_atomic();
2406 atomic_inc(&dev_priv->gpu_error.reset_counter);
2408 kobject_uevent_env(&dev->primary->kdev->kobj,
2409 KOBJ_CHANGE, reset_done_event);
2411 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2415 * Note: The wake_up also serves as a memory barrier so that
2416 * waiters see the update value of the reset counter atomic_t.
2418 i915_error_wake_up(dev_priv, true);
2422 static void i915_report_and_clear_eir(struct drm_device *dev)
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 uint32_t instdone[I915_NUM_INSTDONE_REG];
2426 u32 eir = I915_READ(EIR);
2432 pr_err("render error detected, EIR: 0x%08x\n", eir);
2434 i915_get_extra_instdone(dev, instdone);
2437 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2438 u32 ipeir = I915_READ(IPEIR_I965);
2440 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2441 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2442 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2443 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2444 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2445 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2446 I915_WRITE(IPEIR_I965, ipeir);
2447 POSTING_READ(IPEIR_I965);
2449 if (eir & GM45_ERROR_PAGE_TABLE) {
2450 u32 pgtbl_err = I915_READ(PGTBL_ER);
2451 pr_err("page table error\n");
2452 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2453 I915_WRITE(PGTBL_ER, pgtbl_err);
2454 POSTING_READ(PGTBL_ER);
2458 if (!IS_GEN2(dev)) {
2459 if (eir & I915_ERROR_PAGE_TABLE) {
2460 u32 pgtbl_err = I915_READ(PGTBL_ER);
2461 pr_err("page table error\n");
2462 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2463 I915_WRITE(PGTBL_ER, pgtbl_err);
2464 POSTING_READ(PGTBL_ER);
2468 if (eir & I915_ERROR_MEMORY_REFRESH) {
2469 pr_err("memory refresh error:\n");
2471 pr_err("pipe %c stat: 0x%08x\n",
2472 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2473 /* pipestat has already been acked */
2475 if (eir & I915_ERROR_INSTRUCTION) {
2476 pr_err("instruction error\n");
2477 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2478 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2479 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2480 if (INTEL_INFO(dev)->gen < 4) {
2481 u32 ipeir = I915_READ(IPEIR);
2483 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2484 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2485 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2486 I915_WRITE(IPEIR, ipeir);
2487 POSTING_READ(IPEIR);
2489 u32 ipeir = I915_READ(IPEIR_I965);
2491 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2492 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2493 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2494 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2495 I915_WRITE(IPEIR_I965, ipeir);
2496 POSTING_READ(IPEIR_I965);
2500 I915_WRITE(EIR, eir);
2502 eir = I915_READ(EIR);
2505 * some errors might have become stuck,
2508 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2509 I915_WRITE(EMR, I915_READ(EMR) | eir);
2510 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2515 * i915_handle_error - handle an error interrupt
2518 * Do some basic checking of regsiter state at error interrupt time and
2519 * dump it to the syslog. Also call i915_capture_error_state() to make
2520 * sure we get a record and make it available in debugfs. Fire a uevent
2521 * so userspace knows something bad happened (should trigger collection
2522 * of a ring dump etc.).
2524 void i915_handle_error(struct drm_device *dev, bool wedged,
2525 const char *fmt, ...)
2527 struct drm_i915_private *dev_priv = dev->dev_private;
2531 va_start(args, fmt);
2532 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2535 i915_capture_error_state(dev, wedged, error_msg);
2536 i915_report_and_clear_eir(dev);
2539 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2540 &dev_priv->gpu_error.reset_counter);
2543 * Wakeup waiting processes so that the reset work function
2544 * i915_error_work_func doesn't deadlock trying to grab various
2545 * locks. By bumping the reset counter first, the woken
2546 * processes will see a reset in progress and back off,
2547 * releasing their locks and then wait for the reset completion.
2548 * We must do this for _all_ gpu waiters that might hold locks
2549 * that the reset work needs to acquire.
2551 * Note: The wake_up serves as the required memory barrier to
2552 * ensure that the waiters see the updated value of the reset
2555 i915_error_wake_up(dev_priv, false);
2559 * Our reset work can grab modeset locks (since it needs to reset the
2560 * state of outstanding pagelips). Hence it must not be run on our own
2561 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2562 * code will deadlock.
2564 schedule_work(&dev_priv->gpu_error.work);
2567 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2569 struct drm_i915_private *dev_priv = dev->dev_private;
2570 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2572 struct drm_i915_gem_object *obj;
2573 struct intel_unpin_work *work;
2574 unsigned long flags;
2575 bool stall_detected;
2577 /* Ignore early vblank irqs */
2578 if (intel_crtc == NULL)
2581 spin_lock_irqsave(&dev->event_lock, flags);
2582 work = intel_crtc->unpin_work;
2585 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2586 !work->enable_stall_check) {
2587 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2588 spin_unlock_irqrestore(&dev->event_lock, flags);
2592 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2593 obj = work->pending_flip_obj;
2594 if (INTEL_INFO(dev)->gen >= 4) {
2595 int dspsurf = DSPSURF(intel_crtc->plane);
2596 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2597 i915_gem_obj_ggtt_offset(obj);
2599 int dspaddr = DSPADDR(intel_crtc->plane);
2600 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2601 crtc->y * crtc->primary->fb->pitches[0] +
2602 crtc->x * crtc->primary->fb->bits_per_pixel/8);
2605 spin_unlock_irqrestore(&dev->event_lock, flags);
2607 if (stall_detected) {
2608 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2609 intel_prepare_page_flip(dev, intel_crtc->plane);
2613 /* Called from drm generic code, passed 'crtc' which
2614 * we use as a pipe index
2616 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2618 struct drm_i915_private *dev_priv = dev->dev_private;
2619 unsigned long irqflags;
2621 if (!i915_pipe_enabled(dev, pipe))
2624 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2625 if (INTEL_INFO(dev)->gen >= 4)
2626 i915_enable_pipestat(dev_priv, pipe,
2627 PIPE_START_VBLANK_INTERRUPT_STATUS);
2629 i915_enable_pipestat(dev_priv, pipe,
2630 PIPE_VBLANK_INTERRUPT_STATUS);
2631 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2636 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2638 struct drm_i915_private *dev_priv = dev->dev_private;
2639 unsigned long irqflags;
2640 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2641 DE_PIPE_VBLANK(pipe);
2643 if (!i915_pipe_enabled(dev, pipe))
2646 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2647 ironlake_enable_display_irq(dev_priv, bit);
2648 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2653 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 unsigned long irqflags;
2658 if (!i915_pipe_enabled(dev, pipe))
2661 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2662 i915_enable_pipestat(dev_priv, pipe,
2663 PIPE_START_VBLANK_INTERRUPT_STATUS);
2664 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2669 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 unsigned long irqflags;
2674 if (!i915_pipe_enabled(dev, pipe))
2677 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2678 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2679 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2680 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2681 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2685 /* Called from drm generic code, passed 'crtc' which
2686 * we use as a pipe index
2688 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2690 struct drm_i915_private *dev_priv = dev->dev_private;
2691 unsigned long irqflags;
2693 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2694 i915_disable_pipestat(dev_priv, pipe,
2695 PIPE_VBLANK_INTERRUPT_STATUS |
2696 PIPE_START_VBLANK_INTERRUPT_STATUS);
2697 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2700 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2702 struct drm_i915_private *dev_priv = dev->dev_private;
2703 unsigned long irqflags;
2704 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2705 DE_PIPE_VBLANK(pipe);
2707 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2708 ironlake_disable_display_irq(dev_priv, bit);
2709 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2712 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 unsigned long irqflags;
2717 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2718 i915_disable_pipestat(dev_priv, pipe,
2719 PIPE_START_VBLANK_INTERRUPT_STATUS);
2720 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2723 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2725 struct drm_i915_private *dev_priv = dev->dev_private;
2726 unsigned long irqflags;
2728 if (!i915_pipe_enabled(dev, pipe))
2731 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2732 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2733 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2734 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2735 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2739 ring_last_seqno(struct intel_engine_cs *ring)
2741 return list_entry(ring->request_list.prev,
2742 struct drm_i915_gem_request, list)->seqno;
2746 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2748 return (list_empty(&ring->request_list) ||
2749 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2753 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2755 if (INTEL_INFO(dev)->gen >= 8) {
2757 * FIXME: gen8 semaphore support - currently we don't emit
2758 * semaphores on bdw anyway, but this needs to be addressed when
2759 * we merge that code.
2763 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2764 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2765 MI_SEMAPHORE_REGISTER);
2769 static struct intel_engine_cs *
2770 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr)
2772 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2773 struct intel_engine_cs *signaller;
2776 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2778 * FIXME: gen8 semaphore support - currently we don't emit
2779 * semaphores on bdw anyway, but this needs to be addressed when
2780 * we merge that code.
2784 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2786 for_each_ring(signaller, dev_priv, i) {
2787 if(ring == signaller)
2790 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2795 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2801 static struct intel_engine_cs *
2802 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2804 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2805 u32 cmd, ipehr, head;
2808 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2809 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2813 * HEAD is likely pointing to the dword after the actual command,
2814 * so scan backwards until we find the MBOX. But limit it to just 3
2815 * dwords. Note that we don't care about ACTHD here since that might
2816 * point at at batch, and semaphores are always emitted into the
2817 * ringbuffer itself.
2819 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2821 for (i = 4; i; --i) {
2823 * Be paranoid and presume the hw has gone off into the wild -
2824 * our ring is smaller than what the hardware (and hence
2825 * HEAD_ADDR) allows. Also handles wrap-around.
2827 head &= ring->buffer->size - 1;
2829 /* This here seems to blow up */
2830 cmd = ioread32(ring->buffer->virtual_start + head);
2840 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2841 return semaphore_wait_to_signaller_ring(ring, ipehr);
2844 static int semaphore_passed(struct intel_engine_cs *ring)
2846 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2847 struct intel_engine_cs *signaller;
2850 ring->hangcheck.deadlock = true;
2852 signaller = semaphore_waits_for(ring, &seqno);
2853 if (signaller == NULL || signaller->hangcheck.deadlock)
2856 /* cursory check for an unkickable deadlock */
2857 ctl = I915_READ_CTL(signaller);
2858 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2861 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2864 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2866 struct intel_engine_cs *ring;
2869 for_each_ring(ring, dev_priv, i)
2870 ring->hangcheck.deadlock = false;
2873 static enum intel_ring_hangcheck_action
2874 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2876 struct drm_device *dev = ring->dev;
2877 struct drm_i915_private *dev_priv = dev->dev_private;
2880 if (ring->hangcheck.acthd != acthd)
2881 return HANGCHECK_ACTIVE;
2884 return HANGCHECK_HUNG;
2886 /* Is the chip hanging on a WAIT_FOR_EVENT?
2887 * If so we can simply poke the RB_WAIT bit
2888 * and break the hang. This should work on
2889 * all but the second generation chipsets.
2891 tmp = I915_READ_CTL(ring);
2892 if (tmp & RING_WAIT) {
2893 i915_handle_error(dev, false,
2894 "Kicking stuck wait on %s",
2896 I915_WRITE_CTL(ring, tmp);
2897 return HANGCHECK_KICK;
2900 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2901 switch (semaphore_passed(ring)) {
2903 return HANGCHECK_HUNG;
2905 i915_handle_error(dev, false,
2906 "Kicking stuck semaphore on %s",
2908 I915_WRITE_CTL(ring, tmp);
2909 return HANGCHECK_KICK;
2911 return HANGCHECK_WAIT;
2915 return HANGCHECK_HUNG;
2919 * This is called when the chip hasn't reported back with completed
2920 * batchbuffers in a long time. We keep track per ring seqno progress and
2921 * if there are no progress, hangcheck score for that ring is increased.
2922 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2923 * we kick the ring. If we see no progress on three subsequent calls
2924 * we assume chip is wedged and try to fix it by resetting the chip.
2926 static void i915_hangcheck_elapsed(unsigned long data)
2928 struct drm_device *dev = (struct drm_device *)data;
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930 struct intel_engine_cs *ring;
2932 int busy_count = 0, rings_hung = 0;
2933 bool stuck[I915_NUM_RINGS] = { 0 };
2938 if (!i915.enable_hangcheck)
2941 for_each_ring(ring, dev_priv, i) {
2946 semaphore_clear_deadlocks(dev_priv);
2948 seqno = ring->get_seqno(ring, false);
2949 acthd = intel_ring_get_active_head(ring);
2951 if (ring->hangcheck.seqno == seqno) {
2952 if (ring_idle(ring, seqno)) {
2953 ring->hangcheck.action = HANGCHECK_IDLE;
2955 if (waitqueue_active(&ring->irq_queue)) {
2956 /* Issue a wake-up to catch stuck h/w. */
2957 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2958 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2959 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2962 DRM_INFO("Fake missed irq on %s\n",
2964 wake_up_all(&ring->irq_queue);
2966 /* Safeguard against driver failure */
2967 ring->hangcheck.score += BUSY;
2971 /* We always increment the hangcheck score
2972 * if the ring is busy and still processing
2973 * the same request, so that no single request
2974 * can run indefinitely (such as a chain of
2975 * batches). The only time we do not increment
2976 * the hangcheck score on this ring, if this
2977 * ring is in a legitimate wait for another
2978 * ring. In that case the waiting ring is a
2979 * victim and we want to be sure we catch the
2980 * right culprit. Then every time we do kick
2981 * the ring, add a small increment to the
2982 * score so that we can catch a batch that is
2983 * being repeatedly kicked and so responsible
2984 * for stalling the machine.
2986 ring->hangcheck.action = ring_stuck(ring,
2989 switch (ring->hangcheck.action) {
2990 case HANGCHECK_IDLE:
2991 case HANGCHECK_WAIT:
2993 case HANGCHECK_ACTIVE:
2994 ring->hangcheck.score += BUSY;
2996 case HANGCHECK_KICK:
2997 ring->hangcheck.score += KICK;
2999 case HANGCHECK_HUNG:
3000 ring->hangcheck.score += HUNG;
3006 ring->hangcheck.action = HANGCHECK_ACTIVE;
3008 /* Gradually reduce the count so that we catch DoS
3009 * attempts across multiple batches.
3011 if (ring->hangcheck.score > 0)
3012 ring->hangcheck.score--;
3015 ring->hangcheck.seqno = seqno;
3016 ring->hangcheck.acthd = acthd;
3020 for_each_ring(ring, dev_priv, i) {
3021 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3022 DRM_INFO("%s on %s\n",
3023 stuck[i] ? "stuck" : "no progress",
3030 return i915_handle_error(dev, true, "Ring hung");
3033 /* Reset timer case chip hangs without another request
3035 i915_queue_hangcheck(dev);
3038 void i915_queue_hangcheck(struct drm_device *dev)
3040 struct drm_i915_private *dev_priv = dev->dev_private;
3041 if (!i915.enable_hangcheck)
3044 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
3045 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3048 static void ibx_irq_reset(struct drm_device *dev)
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3052 if (HAS_PCH_NOP(dev))
3055 GEN5_IRQ_RESET(SDE);
3057 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3058 I915_WRITE(SERR_INT, 0xffffffff);
3062 * SDEIER is also touched by the interrupt handler to work around missed PCH
3063 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3064 * instead we unconditionally enable all PCH interrupt sources here, but then
3065 * only unmask them as needed with SDEIMR.
3067 * This function needs to be called before interrupts are enabled.
3069 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3071 struct drm_i915_private *dev_priv = dev->dev_private;
3073 if (HAS_PCH_NOP(dev))
3076 WARN_ON(I915_READ(SDEIER) != 0);
3077 I915_WRITE(SDEIER, 0xffffffff);
3078 POSTING_READ(SDEIER);
3081 static void gen5_gt_irq_reset(struct drm_device *dev)
3083 struct drm_i915_private *dev_priv = dev->dev_private;
3086 if (INTEL_INFO(dev)->gen >= 6)
3087 GEN5_IRQ_RESET(GEN6_PM);
3092 static void ironlake_irq_reset(struct drm_device *dev)
3094 struct drm_i915_private *dev_priv = dev->dev_private;
3096 I915_WRITE(HWSTAM, 0xffffffff);
3100 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3102 gen5_gt_irq_reset(dev);
3107 static void valleyview_irq_preinstall(struct drm_device *dev)
3109 struct drm_i915_private *dev_priv = dev->dev_private;
3113 I915_WRITE(VLV_IMR, 0);
3114 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3115 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3116 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3119 I915_WRITE(GTIIR, I915_READ(GTIIR));
3120 I915_WRITE(GTIIR, I915_READ(GTIIR));
3122 gen5_gt_irq_reset(dev);
3124 I915_WRITE(DPINVGTT, 0xff);
3126 I915_WRITE(PORT_HOTPLUG_EN, 0);
3127 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3129 I915_WRITE(PIPESTAT(pipe), 0xffff);
3130 I915_WRITE(VLV_IIR, 0xffffffff);
3131 I915_WRITE(VLV_IMR, 0xffffffff);
3132 I915_WRITE(VLV_IER, 0x0);
3133 POSTING_READ(VLV_IER);
3136 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3138 GEN8_IRQ_RESET_NDX(GT, 0);
3139 GEN8_IRQ_RESET_NDX(GT, 1);
3140 GEN8_IRQ_RESET_NDX(GT, 2);
3141 GEN8_IRQ_RESET_NDX(GT, 3);
3144 static void gen8_irq_reset(struct drm_device *dev)
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3149 I915_WRITE(GEN8_MASTER_IRQ, 0);
3150 POSTING_READ(GEN8_MASTER_IRQ);
3152 gen8_gt_irq_reset(dev_priv);
3155 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3157 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3158 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3159 GEN5_IRQ_RESET(GEN8_PCU_);
3164 static void cherryview_irq_preinstall(struct drm_device *dev)
3166 struct drm_i915_private *dev_priv = dev->dev_private;
3169 I915_WRITE(GEN8_MASTER_IRQ, 0);
3170 POSTING_READ(GEN8_MASTER_IRQ);
3172 gen8_gt_irq_reset(dev_priv);
3174 GEN5_IRQ_RESET(GEN8_PCU_);
3176 POSTING_READ(GEN8_PCU_IIR);
3178 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3180 I915_WRITE(PORT_HOTPLUG_EN, 0);
3181 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3184 I915_WRITE(PIPESTAT(pipe), 0xffff);
3186 I915_WRITE(VLV_IMR, 0xffffffff);
3187 I915_WRITE(VLV_IER, 0x0);
3188 I915_WRITE(VLV_IIR, 0xffffffff);
3189 POSTING_READ(VLV_IIR);
3192 static void ibx_hpd_irq_setup(struct drm_device *dev)
3194 struct drm_i915_private *dev_priv = dev->dev_private;
3195 struct drm_mode_config *mode_config = &dev->mode_config;
3196 struct intel_encoder *intel_encoder;
3197 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3199 if (HAS_PCH_IBX(dev)) {
3200 hotplug_irqs = SDE_HOTPLUG_MASK;
3201 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3202 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3203 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3205 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3206 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3207 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3208 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3211 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3214 * Enable digital hotplug on the PCH, and configure the DP short pulse
3215 * duration to 2ms (which is the minimum in the Display Port spec)
3217 * This register is the same on all known PCH chips.
3219 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3220 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3221 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3222 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3223 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3224 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3227 static void ibx_irq_postinstall(struct drm_device *dev)
3229 struct drm_i915_private *dev_priv = dev->dev_private;
3232 if (HAS_PCH_NOP(dev))
3235 if (HAS_PCH_IBX(dev))
3236 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3238 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3240 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3241 I915_WRITE(SDEIMR, ~mask);
3244 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 u32 pm_irqs, gt_irqs;
3249 pm_irqs = gt_irqs = 0;
3251 dev_priv->gt_irq_mask = ~0;
3252 if (HAS_L3_DPF(dev)) {
3253 /* L3 parity interrupt is always unmasked. */
3254 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3255 gt_irqs |= GT_PARITY_ERROR(dev);
3258 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3260 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3261 ILK_BSD_USER_INTERRUPT;
3263 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3266 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3268 if (INTEL_INFO(dev)->gen >= 6) {
3269 pm_irqs |= dev_priv->pm_rps_events;
3272 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3274 dev_priv->pm_irq_mask = 0xffffffff;
3275 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3279 static int ironlake_irq_postinstall(struct drm_device *dev)
3281 unsigned long irqflags;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 u32 display_mask, extra_mask;
3285 if (INTEL_INFO(dev)->gen >= 7) {
3286 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3287 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3288 DE_PLANEB_FLIP_DONE_IVB |
3289 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3290 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3291 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3293 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3294 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3296 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3298 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3299 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3302 dev_priv->irq_mask = ~display_mask;
3304 I915_WRITE(HWSTAM, 0xeffe);
3306 ibx_irq_pre_postinstall(dev);
3308 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3310 gen5_gt_irq_postinstall(dev);
3312 ibx_irq_postinstall(dev);
3314 if (IS_IRONLAKE_M(dev)) {
3315 /* Enable PCU event interrupts
3317 * spinlocking not required here for correctness since interrupt
3318 * setup is guaranteed to run in single-threaded context. But we
3319 * need it to make the assert_spin_locked happy. */
3320 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3321 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3322 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3328 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3333 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3334 PIPE_FIFO_UNDERRUN_STATUS;
3336 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3337 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3338 POSTING_READ(PIPESTAT(PIPE_A));
3340 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3341 PIPE_CRC_DONE_INTERRUPT_STATUS;
3343 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3344 PIPE_GMBUS_INTERRUPT_STATUS);
3345 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3347 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3348 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3349 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3350 dev_priv->irq_mask &= ~iir_mask;
3352 I915_WRITE(VLV_IIR, iir_mask);
3353 I915_WRITE(VLV_IIR, iir_mask);
3354 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3355 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3356 POSTING_READ(VLV_IER);
3359 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3364 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3365 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3366 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3368 dev_priv->irq_mask |= iir_mask;
3369 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3370 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3371 I915_WRITE(VLV_IIR, iir_mask);
3372 I915_WRITE(VLV_IIR, iir_mask);
3373 POSTING_READ(VLV_IIR);
3375 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3376 PIPE_CRC_DONE_INTERRUPT_STATUS;
3378 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3379 PIPE_GMBUS_INTERRUPT_STATUS);
3380 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3382 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3383 PIPE_FIFO_UNDERRUN_STATUS;
3384 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3385 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3386 POSTING_READ(PIPESTAT(PIPE_A));
3389 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3391 assert_spin_locked(&dev_priv->irq_lock);
3393 if (dev_priv->display_irqs_enabled)
3396 dev_priv->display_irqs_enabled = true;
3398 if (dev_priv->dev->irq_enabled)
3399 valleyview_display_irqs_install(dev_priv);
3402 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3404 assert_spin_locked(&dev_priv->irq_lock);
3406 if (!dev_priv->display_irqs_enabled)
3409 dev_priv->display_irqs_enabled = false;
3411 if (dev_priv->dev->irq_enabled)
3412 valleyview_display_irqs_uninstall(dev_priv);
3415 static int valleyview_irq_postinstall(struct drm_device *dev)
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3418 unsigned long irqflags;
3420 dev_priv->irq_mask = ~0;
3422 I915_WRITE(PORT_HOTPLUG_EN, 0);
3423 POSTING_READ(PORT_HOTPLUG_EN);
3425 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3426 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3427 I915_WRITE(VLV_IIR, 0xffffffff);
3428 POSTING_READ(VLV_IER);
3430 /* Interrupt setup is already guaranteed to be single-threaded, this is
3431 * just to make the assert_spin_locked check happy. */
3432 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3433 if (dev_priv->display_irqs_enabled)
3434 valleyview_display_irqs_install(dev_priv);
3435 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3437 I915_WRITE(VLV_IIR, 0xffffffff);
3438 I915_WRITE(VLV_IIR, 0xffffffff);
3440 gen5_gt_irq_postinstall(dev);
3442 /* ack & enable invalid PTE error interrupts */
3443 #if 0 /* FIXME: add support to irq handler for checking these bits */
3444 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3445 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3448 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3453 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3457 /* These are interrupts we'll toggle with the ring mask register */
3458 uint32_t gt_interrupts[] = {
3459 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3460 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3461 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3462 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3463 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3465 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3468 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
3469 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
3471 dev_priv->pm_irq_mask = 0xffffffff;
3474 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3476 struct drm_device *dev = dev_priv->dev;
3477 uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE |
3478 GEN8_PIPE_CDCLK_CRC_DONE |
3479 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3480 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3481 GEN8_PIPE_FIFO_UNDERRUN;
3483 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3484 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3485 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3488 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],
3491 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3494 static int gen8_irq_postinstall(struct drm_device *dev)
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3498 ibx_irq_pre_postinstall(dev);
3500 gen8_gt_irq_postinstall(dev_priv);
3501 gen8_de_irq_postinstall(dev_priv);
3503 ibx_irq_postinstall(dev);
3505 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3506 POSTING_READ(GEN8_MASTER_IRQ);
3511 static int cherryview_irq_postinstall(struct drm_device *dev)
3513 struct drm_i915_private *dev_priv = dev->dev_private;
3514 u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3515 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3516 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3517 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3518 u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3519 PIPE_CRC_DONE_INTERRUPT_STATUS;
3520 unsigned long irqflags;
3524 * Leave vblank interrupts masked initially. enable/disable will
3525 * toggle them based on usage.
3527 dev_priv->irq_mask = ~enable_mask;
3530 I915_WRITE(PIPESTAT(pipe), 0xffff);
3532 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3533 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3535 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3536 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3538 I915_WRITE(VLV_IIR, 0xffffffff);
3539 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3540 I915_WRITE(VLV_IER, enable_mask);
3542 gen8_gt_irq_postinstall(dev_priv);
3544 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3545 POSTING_READ(GEN8_MASTER_IRQ);
3550 static void gen8_irq_uninstall(struct drm_device *dev)
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3557 intel_hpd_irq_uninstall(dev_priv);
3559 gen8_irq_reset(dev);
3562 static void valleyview_irq_uninstall(struct drm_device *dev)
3564 struct drm_i915_private *dev_priv = dev->dev_private;
3565 unsigned long irqflags;
3571 I915_WRITE(VLV_MASTER_IER, 0);
3573 intel_hpd_irq_uninstall(dev_priv);
3576 I915_WRITE(PIPESTAT(pipe), 0xffff);
3578 I915_WRITE(HWSTAM, 0xffffffff);
3579 I915_WRITE(PORT_HOTPLUG_EN, 0);
3580 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3583 if (dev_priv->display_irqs_enabled)
3584 valleyview_display_irqs_uninstall(dev_priv);
3585 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3587 dev_priv->irq_mask = 0;
3589 I915_WRITE(VLV_IIR, 0xffffffff);
3590 I915_WRITE(VLV_IMR, 0xffffffff);
3591 I915_WRITE(VLV_IER, 0x0);
3592 POSTING_READ(VLV_IER);
3595 static void cherryview_irq_uninstall(struct drm_device *dev)
3597 struct drm_i915_private *dev_priv = dev->dev_private;
3603 I915_WRITE(GEN8_MASTER_IRQ, 0);
3604 POSTING_READ(GEN8_MASTER_IRQ);
3606 #define GEN8_IRQ_FINI_NDX(type, which) \
3608 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3609 I915_WRITE(GEN8_##type##_IER(which), 0); \
3610 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3611 POSTING_READ(GEN8_##type##_IIR(which)); \
3612 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3615 #define GEN8_IRQ_FINI(type) \
3617 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3618 I915_WRITE(GEN8_##type##_IER, 0); \
3619 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3620 POSTING_READ(GEN8_##type##_IIR); \
3621 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3624 GEN8_IRQ_FINI_NDX(GT, 0);
3625 GEN8_IRQ_FINI_NDX(GT, 1);
3626 GEN8_IRQ_FINI_NDX(GT, 2);
3627 GEN8_IRQ_FINI_NDX(GT, 3);
3631 #undef GEN8_IRQ_FINI
3632 #undef GEN8_IRQ_FINI_NDX
3634 I915_WRITE(PORT_HOTPLUG_EN, 0);
3635 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3638 I915_WRITE(PIPESTAT(pipe), 0xffff);
3640 I915_WRITE(VLV_IMR, 0xffffffff);
3641 I915_WRITE(VLV_IER, 0x0);
3642 I915_WRITE(VLV_IIR, 0xffffffff);
3643 POSTING_READ(VLV_IIR);
3646 static void ironlake_irq_uninstall(struct drm_device *dev)
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3653 intel_hpd_irq_uninstall(dev_priv);
3655 ironlake_irq_reset(dev);
3658 static void i8xx_irq_preinstall(struct drm_device * dev)
3660 struct drm_i915_private *dev_priv = dev->dev_private;
3664 I915_WRITE(PIPESTAT(pipe), 0);
3665 I915_WRITE16(IMR, 0xffff);
3666 I915_WRITE16(IER, 0x0);
3667 POSTING_READ16(IER);
3670 static int i8xx_irq_postinstall(struct drm_device *dev)
3672 struct drm_i915_private *dev_priv = dev->dev_private;
3673 unsigned long irqflags;
3676 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3678 /* Unmask the interrupts that we always want on. */
3679 dev_priv->irq_mask =
3680 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3681 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3682 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3683 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3684 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3685 I915_WRITE16(IMR, dev_priv->irq_mask);
3688 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3689 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3690 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3691 I915_USER_INTERRUPT);
3692 POSTING_READ16(IER);
3694 /* Interrupt setup is already guaranteed to be single-threaded, this is
3695 * just to make the assert_spin_locked check happy. */
3696 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3697 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3698 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3699 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3705 * Returns true when a page flip has completed.
3707 static bool i8xx_handle_vblank(struct drm_device *dev,
3708 int plane, int pipe, u32 iir)
3710 struct drm_i915_private *dev_priv = dev->dev_private;
3711 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3713 if (!intel_pipe_handle_vblank(dev, pipe))
3716 if ((iir & flip_pending) == 0)
3719 intel_prepare_page_flip(dev, plane);
3721 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3722 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3723 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3724 * the flip is completed (no longer pending). Since this doesn't raise
3725 * an interrupt per se, we watch for the change at vblank.
3727 if (I915_READ16(ISR) & flip_pending)
3730 intel_finish_page_flip(dev, pipe);
3735 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3737 struct drm_device *dev = arg;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3741 unsigned long irqflags;
3744 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3745 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3747 iir = I915_READ16(IIR);
3751 while (iir & ~flip_mask) {
3752 /* Can't rely on pipestat interrupt bit in iir as it might
3753 * have been cleared after the pipestat interrupt was received.
3754 * It doesn't set the bit in iir again, but it still produces
3755 * interrupts (for non-MSI).
3757 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3758 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3759 i915_handle_error(dev, false,
3760 "Command parser error, iir 0x%08x",
3763 for_each_pipe(pipe) {
3764 int reg = PIPESTAT(pipe);
3765 pipe_stats[pipe] = I915_READ(reg);
3768 * Clear the PIPE*STAT regs before the IIR
3770 if (pipe_stats[pipe] & 0x8000ffff)
3771 I915_WRITE(reg, pipe_stats[pipe]);
3773 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3775 I915_WRITE16(IIR, iir & ~flip_mask);
3776 new_iir = I915_READ16(IIR); /* Flush posted writes */
3778 i915_update_dri1_breadcrumb(dev);
3780 if (iir & I915_USER_INTERRUPT)
3781 notify_ring(dev, &dev_priv->ring[RCS]);
3783 for_each_pipe(pipe) {
3788 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3789 i8xx_handle_vblank(dev, plane, pipe, iir))
3790 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3792 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3793 i9xx_pipe_crc_irq_handler(dev, pipe);
3795 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3796 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3797 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3806 static void i8xx_irq_uninstall(struct drm_device * dev)
3808 struct drm_i915_private *dev_priv = dev->dev_private;
3811 for_each_pipe(pipe) {
3812 /* Clear enable bits; then clear status bits */
3813 I915_WRITE(PIPESTAT(pipe), 0);
3814 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3816 I915_WRITE16(IMR, 0xffff);
3817 I915_WRITE16(IER, 0x0);
3818 I915_WRITE16(IIR, I915_READ16(IIR));
3821 static void i915_irq_preinstall(struct drm_device * dev)
3823 struct drm_i915_private *dev_priv = dev->dev_private;
3826 if (I915_HAS_HOTPLUG(dev)) {
3827 I915_WRITE(PORT_HOTPLUG_EN, 0);
3828 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3831 I915_WRITE16(HWSTAM, 0xeffe);
3833 I915_WRITE(PIPESTAT(pipe), 0);
3834 I915_WRITE(IMR, 0xffffffff);
3835 I915_WRITE(IER, 0x0);
3839 static int i915_irq_postinstall(struct drm_device *dev)
3841 struct drm_i915_private *dev_priv = dev->dev_private;
3843 unsigned long irqflags;
3845 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3847 /* Unmask the interrupts that we always want on. */
3848 dev_priv->irq_mask =
3849 ~(I915_ASLE_INTERRUPT |
3850 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3851 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3852 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3853 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3854 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3857 I915_ASLE_INTERRUPT |
3858 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3859 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3860 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3861 I915_USER_INTERRUPT;
3863 if (I915_HAS_HOTPLUG(dev)) {
3864 I915_WRITE(PORT_HOTPLUG_EN, 0);
3865 POSTING_READ(PORT_HOTPLUG_EN);
3867 /* Enable in IER... */
3868 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3869 /* and unmask in IMR */
3870 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3873 I915_WRITE(IMR, dev_priv->irq_mask);
3874 I915_WRITE(IER, enable_mask);
3877 i915_enable_asle_pipestat(dev);
3879 /* Interrupt setup is already guaranteed to be single-threaded, this is
3880 * just to make the assert_spin_locked check happy. */
3881 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3882 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3883 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3884 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3890 * Returns true when a page flip has completed.
3892 static bool i915_handle_vblank(struct drm_device *dev,
3893 int plane, int pipe, u32 iir)
3895 struct drm_i915_private *dev_priv = dev->dev_private;
3896 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3898 if (!intel_pipe_handle_vblank(dev, pipe))
3901 if ((iir & flip_pending) == 0)
3904 intel_prepare_page_flip(dev, plane);
3906 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3907 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3908 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3909 * the flip is completed (no longer pending). Since this doesn't raise
3910 * an interrupt per se, we watch for the change at vblank.
3912 if (I915_READ(ISR) & flip_pending)
3915 intel_finish_page_flip(dev, pipe);
3920 static irqreturn_t i915_irq_handler(int irq, void *arg)
3922 struct drm_device *dev = arg;
3923 struct drm_i915_private *dev_priv = dev->dev_private;
3924 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3925 unsigned long irqflags;
3927 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3928 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3929 int pipe, ret = IRQ_NONE;
3931 iir = I915_READ(IIR);
3933 bool irq_received = (iir & ~flip_mask) != 0;
3934 bool blc_event = false;
3936 /* Can't rely on pipestat interrupt bit in iir as it might
3937 * have been cleared after the pipestat interrupt was received.
3938 * It doesn't set the bit in iir again, but it still produces
3939 * interrupts (for non-MSI).
3941 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3942 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3943 i915_handle_error(dev, false,
3944 "Command parser error, iir 0x%08x",
3947 for_each_pipe(pipe) {
3948 int reg = PIPESTAT(pipe);
3949 pipe_stats[pipe] = I915_READ(reg);
3951 /* Clear the PIPE*STAT regs before the IIR */
3952 if (pipe_stats[pipe] & 0x8000ffff) {
3953 I915_WRITE(reg, pipe_stats[pipe]);
3954 irq_received = true;
3957 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3962 /* Consume port. Then clear IIR or we'll miss events */
3963 if (I915_HAS_HOTPLUG(dev) &&
3964 iir & I915_DISPLAY_PORT_INTERRUPT)
3965 i9xx_hpd_irq_handler(dev);
3967 I915_WRITE(IIR, iir & ~flip_mask);
3968 new_iir = I915_READ(IIR); /* Flush posted writes */
3970 if (iir & I915_USER_INTERRUPT)
3971 notify_ring(dev, &dev_priv->ring[RCS]);
3973 for_each_pipe(pipe) {
3978 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3979 i915_handle_vblank(dev, plane, pipe, iir))
3980 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3982 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3985 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3986 i9xx_pipe_crc_irq_handler(dev, pipe);
3988 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3989 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3990 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3993 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3994 intel_opregion_asle_intr(dev);
3996 /* With MSI, interrupts are only generated when iir
3997 * transitions from zero to nonzero. If another bit got
3998 * set while we were handling the existing iir bits, then
3999 * we would never get another interrupt.
4001 * This is fine on non-MSI as well, as if we hit this path
4002 * we avoid exiting the interrupt handler only to generate
4005 * Note that for MSI this could cause a stray interrupt report
4006 * if an interrupt landed in the time between writing IIR and
4007 * the posting read. This should be rare enough to never
4008 * trigger the 99% of 100,000 interrupts test for disabling
4013 } while (iir & ~flip_mask);
4015 i915_update_dri1_breadcrumb(dev);
4020 static void i915_irq_uninstall(struct drm_device * dev)
4022 struct drm_i915_private *dev_priv = dev->dev_private;
4025 intel_hpd_irq_uninstall(dev_priv);
4027 if (I915_HAS_HOTPLUG(dev)) {
4028 I915_WRITE(PORT_HOTPLUG_EN, 0);
4029 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4032 I915_WRITE16(HWSTAM, 0xffff);
4033 for_each_pipe(pipe) {
4034 /* Clear enable bits; then clear status bits */
4035 I915_WRITE(PIPESTAT(pipe), 0);
4036 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4038 I915_WRITE(IMR, 0xffffffff);
4039 I915_WRITE(IER, 0x0);
4041 I915_WRITE(IIR, I915_READ(IIR));
4044 static void i965_irq_preinstall(struct drm_device * dev)
4046 struct drm_i915_private *dev_priv = dev->dev_private;
4049 I915_WRITE(PORT_HOTPLUG_EN, 0);
4050 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4052 I915_WRITE(HWSTAM, 0xeffe);
4054 I915_WRITE(PIPESTAT(pipe), 0);
4055 I915_WRITE(IMR, 0xffffffff);
4056 I915_WRITE(IER, 0x0);
4060 static int i965_irq_postinstall(struct drm_device *dev)
4062 struct drm_i915_private *dev_priv = dev->dev_private;
4065 unsigned long irqflags;
4067 /* Unmask the interrupts that we always want on. */
4068 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4069 I915_DISPLAY_PORT_INTERRUPT |
4070 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4071 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4072 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4073 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4074 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4076 enable_mask = ~dev_priv->irq_mask;
4077 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4078 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4079 enable_mask |= I915_USER_INTERRUPT;
4082 enable_mask |= I915_BSD_USER_INTERRUPT;
4084 /* Interrupt setup is already guaranteed to be single-threaded, this is
4085 * just to make the assert_spin_locked check happy. */
4086 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4087 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4088 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4089 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4090 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4093 * Enable some error detection, note the instruction error mask
4094 * bit is reserved, so we leave it masked.
4097 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4098 GM45_ERROR_MEM_PRIV |
4099 GM45_ERROR_CP_PRIV |
4100 I915_ERROR_MEMORY_REFRESH);
4102 error_mask = ~(I915_ERROR_PAGE_TABLE |
4103 I915_ERROR_MEMORY_REFRESH);
4105 I915_WRITE(EMR, error_mask);
4107 I915_WRITE(IMR, dev_priv->irq_mask);
4108 I915_WRITE(IER, enable_mask);
4111 I915_WRITE(PORT_HOTPLUG_EN, 0);
4112 POSTING_READ(PORT_HOTPLUG_EN);
4114 i915_enable_asle_pipestat(dev);
4119 static void i915_hpd_irq_setup(struct drm_device *dev)
4121 struct drm_i915_private *dev_priv = dev->dev_private;
4122 struct drm_mode_config *mode_config = &dev->mode_config;
4123 struct intel_encoder *intel_encoder;
4126 assert_spin_locked(&dev_priv->irq_lock);
4128 if (I915_HAS_HOTPLUG(dev)) {
4129 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4130 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4131 /* Note HDMI and DP share hotplug bits */
4132 /* enable bits are the same for all generations */
4133 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
4134 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4135 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4136 /* Programming the CRT detection parameters tends
4137 to generate a spurious hotplug event about three
4138 seconds later. So just do it once.
4141 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4142 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4143 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4145 /* Ignore TV since it's buggy */
4146 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4150 static irqreturn_t i965_irq_handler(int irq, void *arg)
4152 struct drm_device *dev = arg;
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4155 u32 pipe_stats[I915_MAX_PIPES];
4156 unsigned long irqflags;
4157 int ret = IRQ_NONE, pipe;
4159 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4160 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4162 iir = I915_READ(IIR);
4165 bool irq_received = (iir & ~flip_mask) != 0;
4166 bool blc_event = false;
4168 /* Can't rely on pipestat interrupt bit in iir as it might
4169 * have been cleared after the pipestat interrupt was received.
4170 * It doesn't set the bit in iir again, but it still produces
4171 * interrupts (for non-MSI).
4173 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4174 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4175 i915_handle_error(dev, false,
4176 "Command parser error, iir 0x%08x",
4179 for_each_pipe(pipe) {
4180 int reg = PIPESTAT(pipe);
4181 pipe_stats[pipe] = I915_READ(reg);
4184 * Clear the PIPE*STAT regs before the IIR
4186 if (pipe_stats[pipe] & 0x8000ffff) {
4187 I915_WRITE(reg, pipe_stats[pipe]);
4188 irq_received = true;
4191 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4198 /* Consume port. Then clear IIR or we'll miss events */
4199 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4200 i9xx_hpd_irq_handler(dev);
4202 I915_WRITE(IIR, iir & ~flip_mask);
4203 new_iir = I915_READ(IIR); /* Flush posted writes */
4205 if (iir & I915_USER_INTERRUPT)
4206 notify_ring(dev, &dev_priv->ring[RCS]);
4207 if (iir & I915_BSD_USER_INTERRUPT)
4208 notify_ring(dev, &dev_priv->ring[VCS]);
4210 for_each_pipe(pipe) {
4211 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4212 i915_handle_vblank(dev, pipe, pipe, iir))
4213 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4215 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4218 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4219 i9xx_pipe_crc_irq_handler(dev, pipe);
4221 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4222 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4223 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4226 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4227 intel_opregion_asle_intr(dev);
4229 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4230 gmbus_irq_handler(dev);
4232 /* With MSI, interrupts are only generated when iir
4233 * transitions from zero to nonzero. If another bit got
4234 * set while we were handling the existing iir bits, then
4235 * we would never get another interrupt.
4237 * This is fine on non-MSI as well, as if we hit this path
4238 * we avoid exiting the interrupt handler only to generate
4241 * Note that for MSI this could cause a stray interrupt report
4242 * if an interrupt landed in the time between writing IIR and
4243 * the posting read. This should be rare enough to never
4244 * trigger the 99% of 100,000 interrupts test for disabling
4250 i915_update_dri1_breadcrumb(dev);
4255 static void i965_irq_uninstall(struct drm_device * dev)
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4263 intel_hpd_irq_uninstall(dev_priv);
4265 I915_WRITE(PORT_HOTPLUG_EN, 0);
4266 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4268 I915_WRITE(HWSTAM, 0xffffffff);
4270 I915_WRITE(PIPESTAT(pipe), 0);
4271 I915_WRITE(IMR, 0xffffffff);
4272 I915_WRITE(IER, 0x0);
4275 I915_WRITE(PIPESTAT(pipe),
4276 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4277 I915_WRITE(IIR, I915_READ(IIR));
4280 static void intel_hpd_irq_reenable(unsigned long data)
4282 struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
4283 struct drm_device *dev = dev_priv->dev;
4284 struct drm_mode_config *mode_config = &dev->mode_config;
4285 unsigned long irqflags;
4288 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4289 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4290 struct drm_connector *connector;
4292 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4295 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4297 list_for_each_entry(connector, &mode_config->connector_list, head) {
4298 struct intel_connector *intel_connector = to_intel_connector(connector);
4300 if (intel_connector->encoder->hpd_pin == i) {
4301 if (connector->polled != intel_connector->polled)
4302 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4304 connector->polled = intel_connector->polled;
4305 if (!connector->polled)
4306 connector->polled = DRM_CONNECTOR_POLL_HPD;
4310 if (dev_priv->display.hpd_irq_setup)
4311 dev_priv->display.hpd_irq_setup(dev);
4312 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4315 void intel_irq_init(struct drm_device *dev)
4317 struct drm_i915_private *dev_priv = dev->dev_private;
4319 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4320 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4321 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4322 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4324 /* Let's track the enabled rps events */
4325 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4327 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4328 i915_hangcheck_elapsed,
4329 (unsigned long) dev);
4330 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4331 (unsigned long) dev_priv);
4333 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4336 dev->max_vblank_count = 0;
4337 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4338 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4339 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4340 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4342 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4343 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4346 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4347 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4348 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4351 if (IS_CHERRYVIEW(dev)) {
4352 dev->driver->irq_handler = cherryview_irq_handler;
4353 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4354 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4355 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4356 dev->driver->enable_vblank = valleyview_enable_vblank;
4357 dev->driver->disable_vblank = valleyview_disable_vblank;
4358 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4359 } else if (IS_VALLEYVIEW(dev)) {
4360 dev->driver->irq_handler = valleyview_irq_handler;
4361 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4362 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4363 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4364 dev->driver->enable_vblank = valleyview_enable_vblank;
4365 dev->driver->disable_vblank = valleyview_disable_vblank;
4366 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4367 } else if (IS_GEN8(dev)) {
4368 dev->driver->irq_handler = gen8_irq_handler;
4369 dev->driver->irq_preinstall = gen8_irq_reset;
4370 dev->driver->irq_postinstall = gen8_irq_postinstall;
4371 dev->driver->irq_uninstall = gen8_irq_uninstall;
4372 dev->driver->enable_vblank = gen8_enable_vblank;
4373 dev->driver->disable_vblank = gen8_disable_vblank;
4374 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4375 } else if (HAS_PCH_SPLIT(dev)) {
4376 dev->driver->irq_handler = ironlake_irq_handler;
4377 dev->driver->irq_preinstall = ironlake_irq_reset;
4378 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4379 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4380 dev->driver->enable_vblank = ironlake_enable_vblank;
4381 dev->driver->disable_vblank = ironlake_disable_vblank;
4382 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4384 if (INTEL_INFO(dev)->gen == 2) {
4385 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4386 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4387 dev->driver->irq_handler = i8xx_irq_handler;
4388 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4389 } else if (INTEL_INFO(dev)->gen == 3) {
4390 dev->driver->irq_preinstall = i915_irq_preinstall;
4391 dev->driver->irq_postinstall = i915_irq_postinstall;
4392 dev->driver->irq_uninstall = i915_irq_uninstall;
4393 dev->driver->irq_handler = i915_irq_handler;
4394 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4396 dev->driver->irq_preinstall = i965_irq_preinstall;
4397 dev->driver->irq_postinstall = i965_irq_postinstall;
4398 dev->driver->irq_uninstall = i965_irq_uninstall;
4399 dev->driver->irq_handler = i965_irq_handler;
4400 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4402 dev->driver->enable_vblank = i915_enable_vblank;
4403 dev->driver->disable_vblank = i915_disable_vblank;
4407 void intel_hpd_init(struct drm_device *dev)
4409 struct drm_i915_private *dev_priv = dev->dev_private;
4410 struct drm_mode_config *mode_config = &dev->mode_config;
4411 struct drm_connector *connector;
4412 unsigned long irqflags;
4415 for (i = 1; i < HPD_NUM_PINS; i++) {
4416 dev_priv->hpd_stats[i].hpd_cnt = 0;
4417 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4419 list_for_each_entry(connector, &mode_config->connector_list, head) {
4420 struct intel_connector *intel_connector = to_intel_connector(connector);
4421 connector->polled = intel_connector->polled;
4422 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4423 connector->polled = DRM_CONNECTOR_POLL_HPD;
4426 /* Interrupt setup is already guaranteed to be single-threaded, this is
4427 * just to make the assert_spin_locked checks happy. */
4428 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4429 if (dev_priv->display.hpd_irq_setup)
4430 dev_priv->display.hpd_irq_setup(dev);
4431 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4434 /* Disable interrupts so we can allow runtime PM. */
4435 void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
4437 struct drm_i915_private *dev_priv = dev->dev_private;
4439 dev->driver->irq_uninstall(dev);
4440 dev_priv->pm.irqs_disabled = true;
4443 /* Restore interrupts so we can recover from runtime PM. */
4444 void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
4446 struct drm_i915_private *dev_priv = dev->dev_private;
4448 dev_priv->pm.irqs_disabled = false;
4449 dev->driver->irq_preinstall(dev);
4450 dev->driver->irq_postinstall(dev);