drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /* For display hotplug interrupt */
  41 static void
  42 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  43 {
  44         if ((dev_priv->irq_mask & mask) != 0) {
  45                 dev_priv->irq_mask &= ~mask;
  46                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  47                 POSTING_READ(DEIMR);
  48         }
  49 }
  50
  51 static inline void
  52 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  53 {
  54         if ((dev_priv->irq_mask & mask) != mask) {
  55                 dev_priv->irq_mask |= mask;
  56                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  57                 POSTING_READ(DEIMR);
  58         }
  59 }
  60
  61 void
  62 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  63 {
  64         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  65                 u32 reg = PIPESTAT(pipe);
  66
  67                 dev_priv->pipestat[pipe] |= mask;
  68                 /* Enable the interrupt, clear any pending status */
  69                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  70                 POSTING_READ(reg);
  71         }
  72 }
  73
  74 void
  75 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  76 {
  77         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  78                 u32 reg = PIPESTAT(pipe);
  79
  80                 dev_priv->pipestat[pipe] &= ~mask;
  81                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
  82                 POSTING_READ(reg);
  83         }
  84 }
  85
  86 /**
  87  * intel_enable_asle - enable ASLE interrupt for OpRegion
  88  */
  89 void intel_enable_asle(struct drm_device *dev)
  90 {
  91         drm_i915_private_t *dev_priv = dev->dev_private;
  92         unsigned long irqflags;
  93
  94         /* FIXME: opregion/asle for VLV */
  95         if (IS_VALLEYVIEW(dev))
  96                 return;
  97
  98         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  99
 100         if (HAS_PCH_SPLIT(dev))
 101                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 102         else {
 103                 i915_enable_pipestat(dev_priv, 1,
 104                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 105                 if (INTEL_INFO(dev)->gen >= 4)
 106                         i915_enable_pipestat(dev_priv, 0,
 107                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 108         }
 109
 110         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 111 }
 112
 113 /**
 114  * i915_pipe_enabled - check if a pipe is enabled
 115  * @dev: DRM device
 116  * @pipe: pipe to check
 117  *
 118  * Reading certain registers when the pipe is disabled can hang the chip.
 119  * Use this routine to make sure the PLL is running and the pipe is active
 120  * before reading such registers if unsure.
 121  */
 122 static int
 123 i915_pipe_enabled(struct drm_device *dev, int pipe)
 124 {
 125         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 126         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 127 }
 128
 129 /* Called from drm generic code, passed a 'crtc', which
 130  * we use as a pipe index
 131  */
 132 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 133 {
 134         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 135         unsigned long high_frame;
 136         unsigned long low_frame;
 137         u32 high1, high2, low;
 138
 139         if (!i915_pipe_enabled(dev, pipe)) {
 140                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 141                                 "pipe %c\n", pipe_name(pipe));
 142                 return 0;
 143         }
 144
 145         high_frame = PIPEFRAME(pipe);
 146         low_frame = PIPEFRAMEPIXEL(pipe);
 147
 148         /*
 149          * High & low register fields aren't synchronized, so make sure
 150          * we get a low value that's stable across two reads of the high
 151          * register.
 152          */
 153         do {
 154                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 155                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 156                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 157         } while (high1 != high2);
 158
 159         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 160         low >>= PIPE_FRAME_LOW_SHIFT;
 161         return (high1 << 8) | low;
 162 }
 163
 164 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 165 {
 166         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 167         int reg = PIPE_FRMCOUNT_GM45(pipe);
 168
 169         if (!i915_pipe_enabled(dev, pipe)) {
 170                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 171                                  "pipe %c\n", pipe_name(pipe));
 172                 return 0;
 173         }
 174
 175         return I915_READ(reg);
 176 }
 177
 178 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 179                              int *vpos, int *hpos)
 180 {
 181         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 182         u32 vbl = 0, position = 0;
 183         int vbl_start, vbl_end, htotal, vtotal;
 184         bool in_vbl = true;
 185         int ret = 0;
 186
 187         if (!i915_pipe_enabled(dev, pipe)) {
 188                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 189                                  "pipe %c\n", pipe_name(pipe));
 190                 return 0;
 191         }
 192
 193         /* Get vtotal. */
 194         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 195
 196         if (INTEL_INFO(dev)->gen >= 4) {
 197                 /* No obvious pixelcount register. Only query vertical
 198                  * scanout position from Display scan line register.
 199                  */
 200                 position = I915_READ(PIPEDSL(pipe));
 201
 202                 /* Decode into vertical scanout position. Don't have
 203                  * horizontal scanout position.
 204                  */
 205                 *vpos = position & 0x1fff;
 206                 *hpos = 0;
 207         } else {
 208                 /* Have access to pixelcount since start of frame.
 209                  * We can split this into vertical and horizontal
 210                  * scanout position.
 211                  */
 212                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 213
 214                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 215                 *vpos = position / htotal;
 216                 *hpos = position - (*vpos * htotal);
 217         }
 218
 219         /* Query vblank area. */
 220         vbl = I915_READ(VBLANK(pipe));
 221
 222         /* Test position against vblank region. */
 223         vbl_start = vbl & 0x1fff;
 224         vbl_end = (vbl >> 16) & 0x1fff;
 225
 226         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 227                 in_vbl = false;
 228
 229         /* Inside "upper part" of vblank area? Apply corrective offset: */
 230         if (in_vbl && (*vpos >= vbl_start))
 231                 *vpos = *vpos - vtotal;
 232
 233         /* Readouts valid? */
 234         if (vbl > 0)
 235                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 236
 237         /* In vblank? */
 238         if (in_vbl)
 239                 ret |= DRM_SCANOUTPOS_INVBL;
 240
 241         return ret;
 242 }
 243
 244 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 245                               int *max_error,
 246                               struct timeval *vblank_time,
 247                               unsigned flags)
 248 {
 249         struct drm_i915_private *dev_priv = dev->dev_private;
 250         struct drm_crtc *crtc;
 251
 252         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 253                 DRM_ERROR("Invalid crtc %d\n", pipe);
 254                 return -EINVAL;
 255         }
 256
 257         /* Get drm_crtc to timestamp: */
 258         crtc = intel_get_crtc_for_pipe(dev, pipe);
 259         if (crtc == NULL) {
 260                 DRM_ERROR("Invalid crtc %d\n", pipe);
 261                 return -EINVAL;
 262         }
 263
 264         if (!crtc->enabled) {
 265                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 266                 return -EBUSY;
 267         }
 268
 269         /* Helper routine in DRM core does all the work: */
 270         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 271                                                      vblank_time, flags,
 272                                                      crtc);
 273 }
 274
 275 /*
 276  * Handle hotplug events outside the interrupt handler proper.
 277  */
 278 static void i915_hotplug_work_func(struct work_struct *work)
 279 {
 280         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 281                                                     hotplug_work);
 282         struct drm_device *dev = dev_priv->dev;
 283         struct drm_mode_config *mode_config = &dev->mode_config;
 284         struct intel_encoder *encoder;
 285
 286         mutex_lock(&mode_config->mutex);
 287         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 288
 289         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 290                 if (encoder->hot_plug)
 291                         encoder->hot_plug(encoder);
 292
 293         mutex_unlock(&mode_config->mutex);
 294
 295         /* Just fire off a uevent and let userspace tell us what to do */
 296         drm_helper_hpd_irq_event(dev);
 297 }
 298
 299 static void i915_handle_rps_change(struct drm_device *dev)
 300 {
 301         drm_i915_private_t *dev_priv = dev->dev_private;
 302         u32 busy_up, busy_down, max_avg, min_avg;
 303         u8 new_delay = dev_priv->cur_delay;
 304
 305         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 306         busy_up = I915_READ(RCPREVBSYTUPAVG);
 307         busy_down = I915_READ(RCPREVBSYTDNAVG);
 308         max_avg = I915_READ(RCBMAXAVG);
 309         min_avg = I915_READ(RCBMINAVG);
 310
 311         /* Handle RCS change request from hw */
 312         if (busy_up > max_avg) {
 313                 if (dev_priv->cur_delay != dev_priv->max_delay)
 314                         new_delay = dev_priv->cur_delay - 1;
 315                 if (new_delay < dev_priv->max_delay)
 316                         new_delay = dev_priv->max_delay;
 317         } else if (busy_down < min_avg) {
 318                 if (dev_priv->cur_delay != dev_priv->min_delay)
 319                         new_delay = dev_priv->cur_delay + 1;
 320                 if (new_delay > dev_priv->min_delay)
 321                         new_delay = dev_priv->min_delay;
 322         }
 323
 324         if (ironlake_set_drps(dev, new_delay))
 325                 dev_priv->cur_delay = new_delay;
 326
 327         return;
 328 }
 329
 330 static void notify_ring(struct drm_device *dev,
 331                         struct intel_ring_buffer *ring)
 332 {
 333         struct drm_i915_private *dev_priv = dev->dev_private;
 334
 335         if (ring->obj == NULL)
 336                 return;
 337
 338         trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
 339
 340         wake_up_all(&ring->irq_queue);
 341         if (i915_enable_hangcheck) {
 342                 dev_priv->hangcheck_count = 0;
 343                 mod_timer(&dev_priv->hangcheck_timer,
 344                           jiffies +
 345                           msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 346         }
 347 }
 348
 349 static void gen6_pm_rps_work(struct work_struct *work)
 350 {
 351         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 352                                                     rps_work);
 353         u32 pm_iir, pm_imr;
 354         u8 new_delay;
 355
 356         spin_lock_irq(&dev_priv->rps_lock);
 357         pm_iir = dev_priv->pm_iir;
 358         dev_priv->pm_iir = 0;
 359         pm_imr = I915_READ(GEN6_PMIMR);
 360         I915_WRITE(GEN6_PMIMR, 0);
 361         spin_unlock_irq(&dev_priv->rps_lock);
 362
 363         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 364                 return;
 365
 366         mutex_lock(&dev_priv->dev->struct_mutex);
 367
 368         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 369                 new_delay = dev_priv->cur_delay + 1;
 370         else
 371                 new_delay = dev_priv->cur_delay - 1;
 372
 373         gen6_set_rps(dev_priv->dev, new_delay);
 374
 375         mutex_unlock(&dev_priv->dev->struct_mutex);
 376 }
 377
 378 static void snb_gt_irq_handler(struct drm_device *dev,
 379                                struct drm_i915_private *dev_priv,
 380                                u32 gt_iir)
 381 {
 382
 383         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 384                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 385                 notify_ring(dev, &dev_priv->ring[RCS]);
 386         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 387                 notify_ring(dev, &dev_priv->ring[VCS]);
 388         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 389                 notify_ring(dev, &dev_priv->ring[BCS]);
 390
 391         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 392                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 393                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 394                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 395                 i915_handle_error(dev, false);
 396         }
 397 }
 398
 399 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 400                                 u32 pm_iir)
 401 {
 402         unsigned long flags;
 403
 404         /*
 405          * IIR bits should never already be set because IMR should
 406          * prevent an interrupt from being shown in IIR. The warning
 407          * displays a case where we've unsafely cleared
 408          * dev_priv->pm_iir. Although missing an interrupt of the same
 409          * type is not a problem, it displays a problem in the logic.
 410          *
 411          * The mask bit in IMR is cleared by rps_work.
 412          */
 413
 414         spin_lock_irqsave(&dev_priv->rps_lock, flags);
 415         WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 416         dev_priv->pm_iir |= pm_iir;
 417         I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 418         POSTING_READ(GEN6_PMIMR);
 419         spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 420
 421         queue_work(dev_priv->wq, &dev_priv->rps_work);
 422 }
 423
 424 static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
 425 {
 426         struct drm_device *dev = (struct drm_device *) arg;
 427         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 428         u32 iir, gt_iir, pm_iir;
 429         irqreturn_t ret = IRQ_NONE;
 430         unsigned long irqflags;
 431         int pipe;
 432         u32 pipe_stats[I915_MAX_PIPES];
 433         u32 vblank_status;
 434         int vblank = 0;
 435         bool blc_event;
 436
 437         atomic_inc(&dev_priv->irq_received);
 438
 439         vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
 440                 PIPE_VBLANK_INTERRUPT_STATUS;
 441
 442         while (true) {
 443                 iir = I915_READ(VLV_IIR);
 444                 gt_iir = I915_READ(GTIIR);
 445                 pm_iir = I915_READ(GEN6_PMIIR);
 446
 447                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 448                         goto out;
 449
 450                 ret = IRQ_HANDLED;
 451
 452                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 453
 454                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 455                 for_each_pipe(pipe) {
 456                         int reg = PIPESTAT(pipe);
 457                         pipe_stats[pipe] = I915_READ(reg);
 458
 459                         /*
 460                          * Clear the PIPE*STAT regs before the IIR
 461                          */
 462                         if (pipe_stats[pipe] & 0x8000ffff) {
 463                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 464                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 465                                                          pipe_name(pipe));
 466                                 I915_WRITE(reg, pipe_stats[pipe]);
 467                         }
 468                 }
 469                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 470
 471                 /* Consume port.  Then clear IIR or we'll miss events */
 472                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 473                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 474
 475                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 476                                          hotplug_status);
 477                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 478                                 queue_work(dev_priv->wq,
 479                                            &dev_priv->hotplug_work);
 480
 481                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 482                         I915_READ(PORT_HOTPLUG_STAT);
 483                 }
 484
 485
 486                 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
 487                         drm_handle_vblank(dev, 0);
 488                         vblank++;
 489                         intel_finish_page_flip(dev, 0);
 490                 }
 491
 492                 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
 493                         drm_handle_vblank(dev, 1);
 494                         vblank++;
 495                         intel_finish_page_flip(dev, 0);
 496                 }
 497
 498                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 499                         blc_event = true;
 500
 501                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 502                         gen6_queue_rps_work(dev_priv, pm_iir);
 503
 504                 I915_WRITE(GTIIR, gt_iir);
 505                 I915_WRITE(GEN6_PMIIR, pm_iir);
 506                 I915_WRITE(VLV_IIR, iir);
 507         }
 508
 509 out:
 510         return ret;
 511 }
 512
 513 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 514 {
 515         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 516         int pipe;
 517
 518         if (pch_iir & SDE_AUDIO_POWER_MASK)
 519                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 520                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 521                                  SDE_AUDIO_POWER_SHIFT);
 522
 523         if (pch_iir & SDE_GMBUS)
 524                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 525
 526         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 527                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 528
 529         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 530                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 531
 532         if (pch_iir & SDE_POISON)
 533                 DRM_ERROR("PCH poison interrupt\n");
 534
 535         if (pch_iir & SDE_FDI_MASK)
 536                 for_each_pipe(pipe)
 537                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 538                                          pipe_name(pipe),
 539                                          I915_READ(FDI_RX_IIR(pipe)));
 540
 541         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 542                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 543
 544         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 545                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 546
 547         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 548                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 549         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 550                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 551 }
 552
 553 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 554 {
 555         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 556         int pipe;
 557
 558         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 559                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 560                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 561                                  SDE_AUDIO_POWER_SHIFT_CPT);
 562
 563         if (pch_iir & SDE_AUX_MASK_CPT)
 564                 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
 565
 566         if (pch_iir & SDE_GMBUS_CPT)
 567                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 568
 569         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 570                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 571
 572         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 573                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 574
 575         if (pch_iir & SDE_FDI_MASK_CPT)
 576                 for_each_pipe(pipe)
 577                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 578                                          pipe_name(pipe),
 579                                          I915_READ(FDI_RX_IIR(pipe)));
 580 }
 581
 582 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 583 {
 584         struct drm_device *dev = (struct drm_device *) arg;
 585         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 586         u32 de_iir, gt_iir, de_ier, pm_iir;
 587         irqreturn_t ret = IRQ_NONE;
 588         int i;
 589
 590         atomic_inc(&dev_priv->irq_received);
 591
 592         /* disable master interrupt before clearing iir  */
 593         de_ier = I915_READ(DEIER);
 594         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 595
 596         gt_iir = I915_READ(GTIIR);
 597         if (gt_iir) {
 598                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 599                 I915_WRITE(GTIIR, gt_iir);
 600                 ret = IRQ_HANDLED;
 601         }
 602
 603         de_iir = I915_READ(DEIIR);
 604         if (de_iir) {
 605                 if (de_iir & DE_GSE_IVB)
 606                         intel_opregion_gse_intr(dev);
 607
 608                 for (i = 0; i < 3; i++) {
 609                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 610                                 intel_prepare_page_flip(dev, i);
 611                                 intel_finish_page_flip_plane(dev, i);
 612                         }
 613                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 614                                 drm_handle_vblank(dev, i);
 615                 }
 616
 617                 /* check event from PCH */
 618                 if (de_iir & DE_PCH_EVENT_IVB) {
 619                         u32 pch_iir = I915_READ(SDEIIR);
 620
 621                         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 622                                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 623                         cpt_irq_handler(dev, pch_iir);
 624
 625                         /* clear PCH hotplug event before clear CPU irq */
 626                         I915_WRITE(SDEIIR, pch_iir);
 627                 }
 628
 629                 I915_WRITE(DEIIR, de_iir);
 630                 ret = IRQ_HANDLED;
 631         }
 632
 633         pm_iir = I915_READ(GEN6_PMIIR);
 634         if (pm_iir) {
 635                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 636                         gen6_queue_rps_work(dev_priv, pm_iir);
 637                 I915_WRITE(GEN6_PMIIR, pm_iir);
 638                 ret = IRQ_HANDLED;
 639         }
 640
 641         I915_WRITE(DEIER, de_ier);
 642         POSTING_READ(DEIER);
 643
 644         return ret;
 645 }
 646
 647 static void ilk_gt_irq_handler(struct drm_device *dev,
 648                                struct drm_i915_private *dev_priv,
 649                                u32 gt_iir)
 650 {
 651         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 652                 notify_ring(dev, &dev_priv->ring[RCS]);
 653         if (gt_iir & GT_BSD_USER_INTERRUPT)
 654                 notify_ring(dev, &dev_priv->ring[VCS]);
 655 }
 656
 657 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 658 {
 659         struct drm_device *dev = (struct drm_device *) arg;
 660         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 661         int ret = IRQ_NONE;
 662         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 663         u32 hotplug_mask;
 664
 665         atomic_inc(&dev_priv->irq_received);
 666
 667         /* disable master interrupt before clearing iir  */
 668         de_ier = I915_READ(DEIER);
 669         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 670         POSTING_READ(DEIER);
 671
 672         de_iir = I915_READ(DEIIR);
 673         gt_iir = I915_READ(GTIIR);
 674         pch_iir = I915_READ(SDEIIR);
 675         pm_iir = I915_READ(GEN6_PMIIR);
 676
 677         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 678             (!IS_GEN6(dev) || pm_iir == 0))
 679                 goto done;
 680
 681         if (HAS_PCH_CPT(dev))
 682                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 683         else
 684                 hotplug_mask = SDE_HOTPLUG_MASK;
 685
 686         ret = IRQ_HANDLED;
 687
 688         if (IS_GEN5(dev))
 689                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 690         else
 691                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 692
 693         if (de_iir & DE_GSE)
 694                 intel_opregion_gse_intr(dev);
 695
 696         if (de_iir & DE_PLANEA_FLIP_DONE) {
 697                 intel_prepare_page_flip(dev, 0);
 698                 intel_finish_page_flip_plane(dev, 0);
 699         }
 700
 701         if (de_iir & DE_PLANEB_FLIP_DONE) {
 702                 intel_prepare_page_flip(dev, 1);
 703                 intel_finish_page_flip_plane(dev, 1);
 704         }
 705
 706         if (de_iir & DE_PIPEA_VBLANK)
 707                 drm_handle_vblank(dev, 0);
 708
 709         if (de_iir & DE_PIPEB_VBLANK)
 710                 drm_handle_vblank(dev, 1);
 711
 712         /* check event from PCH */
 713         if (de_iir & DE_PCH_EVENT) {
 714                 if (pch_iir & hotplug_mask)
 715                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 716                 if (HAS_PCH_CPT(dev))
 717                         cpt_irq_handler(dev, pch_iir);
 718                 else
 719                         ibx_irq_handler(dev, pch_iir);
 720         }
 721
 722         if (de_iir & DE_PCU_EVENT) {
 723                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 724                 i915_handle_rps_change(dev);
 725         }
 726
 727         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 728                 gen6_queue_rps_work(dev_priv, pm_iir);
 729
 730         /* should clear PCH hotplug event before clear CPU irq */
 731         I915_WRITE(SDEIIR, pch_iir);
 732         I915_WRITE(GTIIR, gt_iir);
 733         I915_WRITE(DEIIR, de_iir);
 734         I915_WRITE(GEN6_PMIIR, pm_iir);
 735
 736 done:
 737         I915_WRITE(DEIER, de_ier);
 738         POSTING_READ(DEIER);
 739
 740         return ret;
 741 }
 742
 743 /**
 744  * i915_error_work_func - do process context error handling work
 745  * @work: work struct
 746  *
 747  * Fire an error uevent so userspace can see that a hang or error
 748  * was detected.
 749  */
 750 static void i915_error_work_func(struct work_struct *work)
 751 {
 752         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 753                                                     error_work);
 754         struct drm_device *dev = dev_priv->dev;
 755         char *error_event[] = { "ERROR=1", NULL };
 756         char *reset_event[] = { "RESET=1", NULL };
 757         char *reset_done_event[] = { "ERROR=0", NULL };
 758
 759         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 760
 761         if (atomic_read(&dev_priv->mm.wedged)) {
 762                 DRM_DEBUG_DRIVER("resetting chip\n");
 763                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 764                 if (!i915_reset(dev)) {
 765                         atomic_set(&dev_priv->mm.wedged, 0);
 766                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 767                 }
 768                 complete_all(&dev_priv->error_completion);
 769         }
 770 }
 771
 772 #ifdef CONFIG_DEBUG_FS
 773 static struct drm_i915_error_object *
 774 i915_error_object_create(struct drm_i915_private *dev_priv,
 775                          struct drm_i915_gem_object *src)
 776 {
 777         struct drm_i915_error_object *dst;
 778         int page, page_count;
 779         u32 reloc_offset;
 780
 781         if (src == NULL || src->pages == NULL)
 782                 return NULL;
 783
 784         page_count = src->base.size / PAGE_SIZE;
 785
 786         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
 787         if (dst == NULL)
 788                 return NULL;
 789
 790         reloc_offset = src->gtt_offset;
 791         for (page = 0; page < page_count; page++) {
 792                 unsigned long flags;
 793                 void *d;
 794
 795                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 796                 if (d == NULL)
 797                         goto unwind;
 798
 799                 local_irq_save(flags);
 800                 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
 801                     src->has_global_gtt_mapping) {
 802                         void __iomem *s;
 803
 804                         /* Simply ignore tiling or any overlapping fence.
 805                          * It's part of the error state, and this hopefully
 806                          * captures what the GPU read.
 807                          */
 808
 809                         s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 810                                                      reloc_offset);
 811                         memcpy_fromio(d, s, PAGE_SIZE);
 812                         io_mapping_unmap_atomic(s);
 813                 } else {
 814                         void *s;
 815
 816                         drm_clflush_pages(&src->pages[page], 1);
 817
 818                         s = kmap_atomic(src->pages[page]);
 819                         memcpy(d, s, PAGE_SIZE);
 820                         kunmap_atomic(s);
 821
 822                         drm_clflush_pages(&src->pages[page], 1);
 823                 }
 824                 local_irq_restore(flags);
 825
 826                 dst->pages[page] = d;
 827
 828                 reloc_offset += PAGE_SIZE;
 829         }
 830         dst->page_count = page_count;
 831         dst->gtt_offset = src->gtt_offset;
 832
 833         return dst;
 834
 835 unwind:
 836         while (page--)
 837                 kfree(dst->pages[page]);
 838         kfree(dst);
 839         return NULL;
 840 }
 841
 842 static void
 843 i915_error_object_free(struct drm_i915_error_object *obj)
 844 {
 845         int page;
 846
 847         if (obj == NULL)
 848                 return;
 849
 850         for (page = 0; page < obj->page_count; page++)
 851                 kfree(obj->pages[page]);
 852
 853         kfree(obj);
 854 }
 855
 856 void
 857 i915_error_state_free(struct kref *error_ref)
 858 {
 859         struct drm_i915_error_state *error = container_of(error_ref,
 860                                                           typeof(*error), ref);
 861         int i;
 862
 863         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 864                 i915_error_object_free(error->ring[i].batchbuffer);
 865                 i915_error_object_free(error->ring[i].ringbuffer);
 866                 kfree(error->ring[i].requests);
 867         }
 868
 869         kfree(error->active_bo);
 870         kfree(error->overlay);
 871         kfree(error);
 872 }
 873 static void capture_bo(struct drm_i915_error_buffer *err,
 874                        struct drm_i915_gem_object *obj)
 875 {
 876         err->size = obj->base.size;
 877         err->name = obj->base.name;
 878         err->seqno = obj->last_rendering_seqno;
 879         err->gtt_offset = obj->gtt_offset;
 880         err->read_domains = obj->base.read_domains;
 881         err->write_domain = obj->base.write_domain;
 882         err->fence_reg = obj->fence_reg;
 883         err->pinned = 0;
 884         if (obj->pin_count > 0)
 885                 err->pinned = 1;
 886         if (obj->user_pin_count > 0)
 887                 err->pinned = -1;
 888         err->tiling = obj->tiling_mode;
 889         err->dirty = obj->dirty;
 890         err->purgeable = obj->madv != I915_MADV_WILLNEED;
 891         err->ring = obj->ring ? obj->ring->id : -1;
 892         err->cache_level = obj->cache_level;
 893 }
 894
 895 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
 896                              int count, struct list_head *head)
 897 {
 898         struct drm_i915_gem_object *obj;
 899         int i = 0;
 900
 901         list_for_each_entry(obj, head, mm_list) {
 902                 capture_bo(err++, obj);
 903                 if (++i == count)
 904                         break;
 905         }
 906
 907         return i;
 908 }
 909
 910 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
 911                              int count, struct list_head *head)
 912 {
 913         struct drm_i915_gem_object *obj;
 914         int i = 0;
 915
 916         list_for_each_entry(obj, head, gtt_list) {
 917                 if (obj->pin_count == 0)
 918                         continue;
 919
 920                 capture_bo(err++, obj);
 921                 if (++i == count)
 922                         break;
 923         }
 924
 925         return i;
 926 }
 927
 928 static void i915_gem_record_fences(struct drm_device *dev,
 929                                    struct drm_i915_error_state *error)
 930 {
 931         struct drm_i915_private *dev_priv = dev->dev_private;
 932         int i;
 933
 934         /* Fences */
 935         switch (INTEL_INFO(dev)->gen) {
 936         case 7:
 937         case 6:
 938                 for (i = 0; i < 16; i++)
 939                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 940                 break;
 941         case 5:
 942         case 4:
 943                 for (i = 0; i < 16; i++)
 944                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 945                 break;
 946         case 3:
 947                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 948                         for (i = 0; i < 8; i++)
 949                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 950         case 2:
 951                 for (i = 0; i < 8; i++)
 952                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 953                 break;
 954
 955         }
 956 }
 957
 958 static struct drm_i915_error_object *
 959 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 960                              struct intel_ring_buffer *ring)
 961 {
 962         struct drm_i915_gem_object *obj;
 963         u32 seqno;
 964
 965         if (!ring->get_seqno)
 966                 return NULL;
 967
 968         seqno = ring->get_seqno(ring);
 969         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 970                 if (obj->ring != ring)
 971                         continue;
 972
 973                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
 974                         continue;
 975
 976                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 977                         continue;
 978
 979                 /* We need to copy these to an anonymous buffer as the simplest
 980                  * method to avoid being overwritten by userspace.
 981                  */
 982                 return i915_error_object_create(dev_priv, obj);
 983         }
 984
 985         return NULL;
 986 }
 987
 988 static void i915_record_ring_state(struct drm_device *dev,
 989                                    struct drm_i915_error_state *error,
 990                                    struct intel_ring_buffer *ring)
 991 {
 992         struct drm_i915_private *dev_priv = dev->dev_private;
 993
 994         if (INTEL_INFO(dev)->gen >= 6) {
 995                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
 996                 error->semaphore_mboxes[ring->id][0]
 997                         = I915_READ(RING_SYNC_0(ring->mmio_base));
 998                 error->semaphore_mboxes[ring->id][1]
 999                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1000         }
1001
1002         if (INTEL_INFO(dev)->gen >= 4) {
1003                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1004                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1005                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1006                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1007                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1008                 if (ring->id == RCS) {
1009                         error->instdone1 = I915_READ(INSTDONE1);
1010                         error->bbaddr = I915_READ64(BB_ADDR);
1011                 }
1012         } else {
1013                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1014                 error->ipeir[ring->id] = I915_READ(IPEIR);
1015                 error->ipehr[ring->id] = I915_READ(IPEHR);
1016                 error->instdone[ring->id] = I915_READ(INSTDONE);
1017         }
1018
1019         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1020         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1021         error->seqno[ring->id] = ring->get_seqno(ring);
1022         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1023         error->head[ring->id] = I915_READ_HEAD(ring);
1024         error->tail[ring->id] = I915_READ_TAIL(ring);
1025
1026         error->cpu_ring_head[ring->id] = ring->head;
1027         error->cpu_ring_tail[ring->id] = ring->tail;
1028 }
1029
1030 static void i915_gem_record_rings(struct drm_device *dev,
1031                                   struct drm_i915_error_state *error)
1032 {
1033         struct drm_i915_private *dev_priv = dev->dev_private;
1034         struct intel_ring_buffer *ring;
1035         struct drm_i915_gem_request *request;
1036         int i, count;
1037
1038         for_each_ring(ring, dev_priv, i) {
1039                 i915_record_ring_state(dev, error, ring);
1040
1041                 error->ring[i].batchbuffer =
1042                         i915_error_first_batchbuffer(dev_priv, ring);
1043
1044                 error->ring[i].ringbuffer =
1045                         i915_error_object_create(dev_priv, ring->obj);
1046
1047                 count = 0;
1048                 list_for_each_entry(request, &ring->request_list, list)
1049                         count++;
1050
1051                 error->ring[i].num_requests = count;
1052                 error->ring[i].requests =
1053                         kmalloc(count*sizeof(struct drm_i915_error_request),
1054                                 GFP_ATOMIC);
1055                 if (error->ring[i].requests == NULL) {
1056                         error->ring[i].num_requests = 0;
1057                         continue;
1058                 }
1059
1060                 count = 0;
1061                 list_for_each_entry(request, &ring->request_list, list) {
1062                         struct drm_i915_error_request *erq;
1063
1064                         erq = &error->ring[i].requests[count++];
1065                         erq->seqno = request->seqno;
1066                         erq->jiffies = request->emitted_jiffies;
1067                         erq->tail = request->tail;
1068                 }
1069         }
1070 }
1071
1072 /**
1073  * i915_capture_error_state - capture an error record for later analysis
1074  * @dev: drm device
1075  *
1076  * Should be called when an error is detected (either a hang or an error
1077  * interrupt) to capture error state from the time of the error.  Fills
1078  * out a structure which becomes available in debugfs for user level tools
1079  * to pick up.
1080  */
1081 static void i915_capture_error_state(struct drm_device *dev)
1082 {
1083         struct drm_i915_private *dev_priv = dev->dev_private;
1084         struct drm_i915_gem_object *obj;
1085         struct drm_i915_error_state *error;
1086         unsigned long flags;
1087         int i, pipe;
1088
1089         spin_lock_irqsave(&dev_priv->error_lock, flags);
1090         error = dev_priv->first_error;
1091         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1092         if (error)
1093                 return;
1094
1095         /* Account for pipe specific data like PIPE*STAT */
1096         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1097         if (!error) {
1098                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1099                 return;
1100         }
1101
1102         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1103                  dev->primary->index);
1104
1105         kref_init(&error->ref);
1106         error->eir = I915_READ(EIR);
1107         error->pgtbl_er = I915_READ(PGTBL_ER);
1108
1109         if (HAS_PCH_SPLIT(dev))
1110                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1111         else if (IS_VALLEYVIEW(dev))
1112                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1113         else if (IS_GEN2(dev))
1114                 error->ier = I915_READ16(IER);
1115         else
1116                 error->ier = I915_READ(IER);
1117
1118         for_each_pipe(pipe)
1119                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1120
1121         if (INTEL_INFO(dev)->gen >= 6) {
1122                 error->error = I915_READ(ERROR_GEN6);
1123                 error->done_reg = I915_READ(DONE_REG);
1124         }
1125
1126         i915_gem_record_fences(dev, error);
1127         i915_gem_record_rings(dev, error);
1128
1129         /* Record buffers on the active and pinned lists. */
1130         error->active_bo = NULL;
1131         error->pinned_bo = NULL;
1132
1133         i = 0;
1134         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1135                 i++;
1136         error->active_bo_count = i;
1137         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1138                 if (obj->pin_count)
1139                         i++;
1140         error->pinned_bo_count = i - error->active_bo_count;
1141
1142         error->active_bo = NULL;
1143         error->pinned_bo = NULL;
1144         if (i) {
1145                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1146                                            GFP_ATOMIC);
1147                 if (error->active_bo)
1148                         error->pinned_bo =
1149                                 error->active_bo + error->active_bo_count;
1150         }
1151
1152         if (error->active_bo)
1153                 error->active_bo_count =
1154                         capture_active_bo(error->active_bo,
1155                                           error->active_bo_count,
1156                                           &dev_priv->mm.active_list);
1157
1158         if (error->pinned_bo)
1159                 error->pinned_bo_count =
1160                         capture_pinned_bo(error->pinned_bo,
1161                                           error->pinned_bo_count,
1162                                           &dev_priv->mm.gtt_list);
1163
1164         do_gettimeofday(&error->time);
1165
1166         error->overlay = intel_overlay_capture_error_state(dev);
1167         error->display = intel_display_capture_error_state(dev);
1168
1169         spin_lock_irqsave(&dev_priv->error_lock, flags);
1170         if (dev_priv->first_error == NULL) {
1171                 dev_priv->first_error = error;
1172                 error = NULL;
1173         }
1174         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1175
1176         if (error)
1177                 i915_error_state_free(&error->ref);
1178 }
1179
1180 void i915_destroy_error_state(struct drm_device *dev)
1181 {
1182         struct drm_i915_private *dev_priv = dev->dev_private;
1183         struct drm_i915_error_state *error;
1184         unsigned long flags;
1185
1186         spin_lock_irqsave(&dev_priv->error_lock, flags);
1187         error = dev_priv->first_error;
1188         dev_priv->first_error = NULL;
1189         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1190
1191         if (error)
1192                 kref_put(&error->ref, i915_error_state_free);
1193 }
1194 #else
1195 #define i915_capture_error_state(x)
1196 #endif
1197
1198 static void i915_report_and_clear_eir(struct drm_device *dev)
1199 {
1200         struct drm_i915_private *dev_priv = dev->dev_private;
1201         u32 eir = I915_READ(EIR);
1202         int pipe;
1203
1204         if (!eir)
1205                 return;
1206
1207         pr_err("render error detected, EIR: 0x%08x\n", eir);
1208
1209         if (IS_G4X(dev)) {
1210                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1211                         u32 ipeir = I915_READ(IPEIR_I965);
1212
1213                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1214                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1215                         pr_err("  INSTDONE: 0x%08x\n",
1216                                I915_READ(INSTDONE_I965));
1217                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1218                         pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1219                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1220                         I915_WRITE(IPEIR_I965, ipeir);
1221                         POSTING_READ(IPEIR_I965);
1222                 }
1223                 if (eir & GM45_ERROR_PAGE_TABLE) {
1224                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1225                         pr_err("page table error\n");
1226                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1227                         I915_WRITE(PGTBL_ER, pgtbl_err);
1228                         POSTING_READ(PGTBL_ER);
1229                 }
1230         }
1231
1232         if (!IS_GEN2(dev)) {
1233                 if (eir & I915_ERROR_PAGE_TABLE) {
1234                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1235                         pr_err("page table error\n");
1236                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1237                         I915_WRITE(PGTBL_ER, pgtbl_err);
1238                         POSTING_READ(PGTBL_ER);
1239                 }
1240         }
1241
1242         if (eir & I915_ERROR_MEMORY_REFRESH) {
1243                 pr_err("memory refresh error:\n");
1244                 for_each_pipe(pipe)
1245                         pr_err("pipe %c stat: 0x%08x\n",
1246                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1247                 /* pipestat has already been acked */
1248         }
1249         if (eir & I915_ERROR_INSTRUCTION) {
1250                 pr_err("instruction error\n");
1251                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1252                 if (INTEL_INFO(dev)->gen < 4) {
1253                         u32 ipeir = I915_READ(IPEIR);
1254
1255                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1256                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1257                         pr_err("  INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1258                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1259                         I915_WRITE(IPEIR, ipeir);
1260                         POSTING_READ(IPEIR);
1261                 } else {
1262                         u32 ipeir = I915_READ(IPEIR_I965);
1263
1264                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1265                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1266                         pr_err("  INSTDONE: 0x%08x\n",
1267                                I915_READ(INSTDONE_I965));
1268                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1269                         pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1270                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1271                         I915_WRITE(IPEIR_I965, ipeir);
1272                         POSTING_READ(IPEIR_I965);
1273                 }
1274         }
1275
1276         I915_WRITE(EIR, eir);
1277         POSTING_READ(EIR);
1278         eir = I915_READ(EIR);
1279         if (eir) {
1280                 /*
1281                  * some errors might have become stuck,
1282                  * mask them.
1283                  */
1284                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1285                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1286                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1287         }
1288 }
1289
1290 /**
1291  * i915_handle_error - handle an error interrupt
1292  * @dev: drm device
1293  *
1294  * Do some basic checking of regsiter state at error interrupt time and
1295  * dump it to the syslog.  Also call i915_capture_error_state() to make
1296  * sure we get a record and make it available in debugfs.  Fire a uevent
1297  * so userspace knows something bad happened (should trigger collection
1298  * of a ring dump etc.).
1299  */
1300 void i915_handle_error(struct drm_device *dev, bool wedged)
1301 {
1302         struct drm_i915_private *dev_priv = dev->dev_private;
1303         struct intel_ring_buffer *ring;
1304         int i;
1305
1306         i915_capture_error_state(dev);
1307         i915_report_and_clear_eir(dev);
1308
1309         if (wedged) {
1310                 INIT_COMPLETION(dev_priv->error_completion);
1311                 atomic_set(&dev_priv->mm.wedged, 1);
1312
1313                 /*
1314                  * Wakeup waiting processes so they don't hang
1315                  */
1316                 for_each_ring(ring, dev_priv, i)
1317                         wake_up_all(&ring->irq_queue);
1318         }
1319
1320         queue_work(dev_priv->wq, &dev_priv->error_work);
1321 }
1322
1323 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1324 {
1325         drm_i915_private_t *dev_priv = dev->dev_private;
1326         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1327         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1328         struct drm_i915_gem_object *obj;
1329         struct intel_unpin_work *work;
1330         unsigned long flags;
1331         bool stall_detected;
1332
1333         /* Ignore early vblank irqs */
1334         if (intel_crtc == NULL)
1335                 return;
1336
1337         spin_lock_irqsave(&dev->event_lock, flags);
1338         work = intel_crtc->unpin_work;
1339
1340         if (work == NULL || work->pending || !work->enable_stall_check) {
1341                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1342                 spin_unlock_irqrestore(&dev->event_lock, flags);
1343                 return;
1344         }
1345
1346         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1347         obj = work->pending_flip_obj;
1348         if (INTEL_INFO(dev)->gen >= 4) {
1349                 int dspsurf = DSPSURF(intel_crtc->plane);
1350                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1351                                         obj->gtt_offset;
1352         } else {
1353                 int dspaddr = DSPADDR(intel_crtc->plane);
1354                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1355                                                         crtc->y * crtc->fb->pitches[0] +
1356                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1357         }
1358
1359         spin_unlock_irqrestore(&dev->event_lock, flags);
1360
1361         if (stall_detected) {
1362                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1363                 intel_prepare_page_flip(dev, intel_crtc->plane);
1364         }
1365 }
1366
1367 /* Called from drm generic code, passed 'crtc' which
1368  * we use as a pipe index
1369  */
1370 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1371 {
1372         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1373         unsigned long irqflags;
1374
1375         if (!i915_pipe_enabled(dev, pipe))
1376                 return -EINVAL;
1377
1378         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1379         if (INTEL_INFO(dev)->gen >= 4)
1380                 i915_enable_pipestat(dev_priv, pipe,
1381                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1382         else
1383                 i915_enable_pipestat(dev_priv, pipe,
1384                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1385
1386         /* maintain vblank delivery even in deep C-states */
1387         if (dev_priv->info->gen == 3)
1388                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1389         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1390
1391         return 0;
1392 }
1393
1394 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1395 {
1396         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1397         unsigned long irqflags;
1398
1399         if (!i915_pipe_enabled(dev, pipe))
1400                 return -EINVAL;
1401
1402         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1403         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1404                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1405         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1406
1407         return 0;
1408 }
1409
1410 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1411 {
1412         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1413         unsigned long irqflags;
1414
1415         if (!i915_pipe_enabled(dev, pipe))
1416                 return -EINVAL;
1417
1418         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1419         ironlake_enable_display_irq(dev_priv,
1420                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1421         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1422
1423         return 0;
1424 }
1425
1426 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1427 {
1428         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1429         unsigned long irqflags;
1430         u32 dpfl, imr;
1431
1432         if (!i915_pipe_enabled(dev, pipe))
1433                 return -EINVAL;
1434
1435         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1436         dpfl = I915_READ(VLV_DPFLIPSTAT);
1437         imr = I915_READ(VLV_IMR);
1438         if (pipe == 0) {
1439                 dpfl |= PIPEA_VBLANK_INT_EN;
1440                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1441         } else {
1442                 dpfl |= PIPEA_VBLANK_INT_EN;
1443                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1444         }
1445         I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1446         I915_WRITE(VLV_IMR, imr);
1447         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1448
1449         return 0;
1450 }
1451
1452 /* Called from drm generic code, passed 'crtc' which
1453  * we use as a pipe index
1454  */
1455 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1456 {
1457         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1458         unsigned long irqflags;
1459
1460         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1461         if (dev_priv->info->gen == 3)
1462                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1463
1464         i915_disable_pipestat(dev_priv, pipe,
1465                               PIPE_VBLANK_INTERRUPT_ENABLE |
1466                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1467         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1468 }
1469
1470 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1471 {
1472         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1473         unsigned long irqflags;
1474
1475         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1476         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1477                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1478         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1479 }
1480
1481 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1482 {
1483         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1484         unsigned long irqflags;
1485
1486         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1487         ironlake_disable_display_irq(dev_priv,
1488                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1489         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1490 }
1491
1492 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1493 {
1494         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1495         unsigned long irqflags;
1496         u32 dpfl, imr;
1497
1498         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1499         dpfl = I915_READ(VLV_DPFLIPSTAT);
1500         imr = I915_READ(VLV_IMR);
1501         if (pipe == 0) {
1502                 dpfl &= ~PIPEA_VBLANK_INT_EN;
1503                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1504         } else {
1505                 dpfl &= ~PIPEB_VBLANK_INT_EN;
1506                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1507         }
1508         I915_WRITE(VLV_IMR, imr);
1509         I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1510         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1511 }
1512
1513 static u32
1514 ring_last_seqno(struct intel_ring_buffer *ring)
1515 {
1516         return list_entry(ring->request_list.prev,
1517                           struct drm_i915_gem_request, list)->seqno;
1518 }
1519
1520 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1521 {
1522         if (list_empty(&ring->request_list) ||
1523             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1524                 /* Issue a wake-up to catch stuck h/w. */
1525                 if (waitqueue_active(&ring->irq_queue)) {
1526                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1527                                   ring->name);
1528                         wake_up_all(&ring->irq_queue);
1529                         *err = true;
1530                 }
1531                 return true;
1532         }
1533         return false;
1534 }
1535
1536 static bool kick_ring(struct intel_ring_buffer *ring)
1537 {
1538         struct drm_device *dev = ring->dev;
1539         struct drm_i915_private *dev_priv = dev->dev_private;
1540         u32 tmp = I915_READ_CTL(ring);
1541         if (tmp & RING_WAIT) {
1542                 DRM_ERROR("Kicking stuck wait on %s\n",
1543                           ring->name);
1544                 I915_WRITE_CTL(ring, tmp);
1545                 return true;
1546         }
1547         return false;
1548 }
1549
1550 static bool i915_hangcheck_hung(struct drm_device *dev)
1551 {
1552         drm_i915_private_t *dev_priv = dev->dev_private;
1553
1554         if (dev_priv->hangcheck_count++ > 1) {
1555                 bool hung = true;
1556
1557                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1558                 i915_handle_error(dev, true);
1559
1560                 if (!IS_GEN2(dev)) {
1561                         struct intel_ring_buffer *ring;
1562                         int i;
1563
1564                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1565                          * If so we can simply poke the RB_WAIT bit
1566                          * and break the hang. This should work on
1567                          * all but the second generation chipsets.
1568                          */
1569                         for_each_ring(ring, dev_priv, i)
1570                                 hung &= !kick_ring(ring);
1571                 }
1572
1573                 return hung;
1574         }
1575
1576         return false;
1577 }
1578
1579 /**
1580  * This is called when the chip hasn't reported back with completed
1581  * batchbuffers in a long time. The first time this is called we simply record
1582  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1583  * again, we assume the chip is wedged and try to fix it.
1584  */
1585 void i915_hangcheck_elapsed(unsigned long data)
1586 {
1587         struct drm_device *dev = (struct drm_device *)data;
1588         drm_i915_private_t *dev_priv = dev->dev_private;
1589         uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1590         struct intel_ring_buffer *ring;
1591         bool err = false, idle;
1592         int i;
1593
1594         if (!i915_enable_hangcheck)
1595                 return;
1596
1597         memset(acthd, 0, sizeof(acthd));
1598         idle = true;
1599         for_each_ring(ring, dev_priv, i) {
1600             idle &= i915_hangcheck_ring_idle(ring, &err);
1601             acthd[i] = intel_ring_get_active_head(ring);
1602         }
1603
1604         /* If all work is done then ACTHD clearly hasn't advanced. */
1605         if (idle) {
1606                 if (err) {
1607                         if (i915_hangcheck_hung(dev))
1608                                 return;
1609
1610                         goto repeat;
1611                 }
1612
1613                 dev_priv->hangcheck_count = 0;
1614                 return;
1615         }
1616
1617         if (INTEL_INFO(dev)->gen < 4) {
1618                 instdone = I915_READ(INSTDONE);
1619                 instdone1 = 0;
1620         } else {
1621                 instdone = I915_READ(INSTDONE_I965);
1622                 instdone1 = I915_READ(INSTDONE1);
1623         }
1624
1625         if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1626             dev_priv->last_instdone == instdone &&
1627             dev_priv->last_instdone1 == instdone1) {
1628                 if (i915_hangcheck_hung(dev))
1629                         return;
1630         } else {
1631                 dev_priv->hangcheck_count = 0;
1632
1633                 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1634                 dev_priv->last_instdone = instdone;
1635                 dev_priv->last_instdone1 = instdone1;
1636         }
1637
1638 repeat:
1639         /* Reset timer case chip hangs without another request being added */
1640         mod_timer(&dev_priv->hangcheck_timer,
1641                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1642 }
1643
1644 /* drm_dma.h hooks
1645 */
1646 static void ironlake_irq_preinstall(struct drm_device *dev)
1647 {
1648         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1649
1650         atomic_set(&dev_priv->irq_received, 0);
1651
1652
1653         I915_WRITE(HWSTAM, 0xeffe);
1654
1655         /* XXX hotplug from PCH */
1656
1657         I915_WRITE(DEIMR, 0xffffffff);
1658         I915_WRITE(DEIER, 0x0);
1659         POSTING_READ(DEIER);
1660
1661         /* and GT */
1662         I915_WRITE(GTIMR, 0xffffffff);
1663         I915_WRITE(GTIER, 0x0);
1664         POSTING_READ(GTIER);
1665
1666         /* south display irq */
1667         I915_WRITE(SDEIMR, 0xffffffff);
1668         I915_WRITE(SDEIER, 0x0);
1669         POSTING_READ(SDEIER);
1670 }
1671
1672 static void valleyview_irq_preinstall(struct drm_device *dev)
1673 {
1674         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1675         int pipe;
1676
1677         atomic_set(&dev_priv->irq_received, 0);
1678
1679         /* VLV magic */
1680         I915_WRITE(VLV_IMR, 0);
1681         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1682         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1683         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1684
1685         /* and GT */
1686         I915_WRITE(GTIIR, I915_READ(GTIIR));
1687         I915_WRITE(GTIIR, I915_READ(GTIIR));
1688         I915_WRITE(GTIMR, 0xffffffff);
1689         I915_WRITE(GTIER, 0x0);
1690         POSTING_READ(GTIER);
1691
1692         I915_WRITE(DPINVGTT, 0xff);
1693
1694         I915_WRITE(PORT_HOTPLUG_EN, 0);
1695         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1696         for_each_pipe(pipe)
1697                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1698         I915_WRITE(VLV_IIR, 0xffffffff);
1699         I915_WRITE(VLV_IMR, 0xffffffff);
1700         I915_WRITE(VLV_IER, 0x0);
1701         POSTING_READ(VLV_IER);
1702 }
1703
1704 /*
1705  * Enable digital hotplug on the PCH, and configure the DP short pulse
1706  * duration to 2ms (which is the minimum in the Display Port spec)
1707  *
1708  * This register is the same on all known PCH chips.
1709  */
1710
1711 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1712 {
1713         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1714         u32     hotplug;
1715
1716         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1717         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1718         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1719         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1720         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1721         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1722 }
1723
1724 static int ironlake_irq_postinstall(struct drm_device *dev)
1725 {
1726         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1727         /* enable kind of interrupts always enabled */
1728         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1729                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1730         u32 render_irqs;
1731         u32 hotplug_mask;
1732
1733         dev_priv->irq_mask = ~display_mask;
1734
1735         /* should always can generate irq */
1736         I915_WRITE(DEIIR, I915_READ(DEIIR));
1737         I915_WRITE(DEIMR, dev_priv->irq_mask);
1738         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1739         POSTING_READ(DEIER);
1740
1741         dev_priv->gt_irq_mask = ~0;
1742
1743         I915_WRITE(GTIIR, I915_READ(GTIIR));
1744         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1745
1746         if (IS_GEN6(dev))
1747                 render_irqs =
1748                         GT_USER_INTERRUPT |
1749                         GEN6_BSD_USER_INTERRUPT |
1750                         GEN6_BLITTER_USER_INTERRUPT;
1751         else
1752                 render_irqs =
1753                         GT_USER_INTERRUPT |
1754                         GT_PIPE_NOTIFY |
1755                         GT_BSD_USER_INTERRUPT;
1756         I915_WRITE(GTIER, render_irqs);
1757         POSTING_READ(GTIER);
1758
1759         if (HAS_PCH_CPT(dev)) {
1760                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1761                                 SDE_PORTB_HOTPLUG_CPT |
1762                                 SDE_PORTC_HOTPLUG_CPT |
1763                                 SDE_PORTD_HOTPLUG_CPT);
1764         } else {
1765                 hotplug_mask = (SDE_CRT_HOTPLUG |
1766                                 SDE_PORTB_HOTPLUG |
1767                                 SDE_PORTC_HOTPLUG |
1768                                 SDE_PORTD_HOTPLUG |
1769                                 SDE_AUX_MASK);
1770         }
1771
1772         dev_priv->pch_irq_mask = ~hotplug_mask;
1773
1774         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1775         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1776         I915_WRITE(SDEIER, hotplug_mask);
1777         POSTING_READ(SDEIER);
1778
1779         ironlake_enable_pch_hotplug(dev);
1780
1781         if (IS_IRONLAKE_M(dev)) {
1782                 /* Clear & enable PCU event interrupts */
1783                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1784                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1785                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1786         }
1787
1788         return 0;
1789 }
1790
1791 static int ivybridge_irq_postinstall(struct drm_device *dev)
1792 {
1793         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1794         /* enable kind of interrupts always enabled */
1795         u32 display_mask =
1796                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1797                 DE_PLANEC_FLIP_DONE_IVB |
1798                 DE_PLANEB_FLIP_DONE_IVB |
1799                 DE_PLANEA_FLIP_DONE_IVB;
1800         u32 render_irqs;
1801         u32 hotplug_mask;
1802
1803         dev_priv->irq_mask = ~display_mask;
1804
1805         /* should always can generate irq */
1806         I915_WRITE(DEIIR, I915_READ(DEIIR));
1807         I915_WRITE(DEIMR, dev_priv->irq_mask);
1808         I915_WRITE(DEIER,
1809                    display_mask |
1810                    DE_PIPEC_VBLANK_IVB |
1811                    DE_PIPEB_VBLANK_IVB |
1812                    DE_PIPEA_VBLANK_IVB);
1813         POSTING_READ(DEIER);
1814
1815         dev_priv->gt_irq_mask = ~0;
1816
1817         I915_WRITE(GTIIR, I915_READ(GTIIR));
1818         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1819
1820         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1821                 GEN6_BLITTER_USER_INTERRUPT;
1822         I915_WRITE(GTIER, render_irqs);
1823         POSTING_READ(GTIER);
1824
1825         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1826                         SDE_PORTB_HOTPLUG_CPT |
1827                         SDE_PORTC_HOTPLUG_CPT |
1828                         SDE_PORTD_HOTPLUG_CPT);
1829         dev_priv->pch_irq_mask = ~hotplug_mask;
1830
1831         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1832         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1833         I915_WRITE(SDEIER, hotplug_mask);
1834         POSTING_READ(SDEIER);
1835
1836         ironlake_enable_pch_hotplug(dev);
1837
1838         return 0;
1839 }
1840
1841 static int valleyview_irq_postinstall(struct drm_device *dev)
1842 {
1843         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1844         u32 render_irqs;
1845         u32 enable_mask;
1846         u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1847         u16 msid;
1848
1849         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1850         enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1851                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1852
1853         dev_priv->irq_mask = ~enable_mask;
1854
1855         dev_priv->pipestat[0] = 0;
1856         dev_priv->pipestat[1] = 0;
1857
1858         /* Hack for broken MSIs on VLV */
1859         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1860         pci_read_config_word(dev->pdev, 0x98, &msid);
1861         msid &= 0xff; /* mask out delivery bits */
1862         msid |= (1<<14);
1863         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1864
1865         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1866         I915_WRITE(VLV_IER, enable_mask);
1867         I915_WRITE(VLV_IIR, 0xffffffff);
1868         I915_WRITE(PIPESTAT(0), 0xffff);
1869         I915_WRITE(PIPESTAT(1), 0xffff);
1870         POSTING_READ(VLV_IER);
1871
1872         I915_WRITE(VLV_IIR, 0xffffffff);
1873         I915_WRITE(VLV_IIR, 0xffffffff);
1874
1875         render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1876                 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1877                 GT_GEN6_BLT_USER_INTERRUPT |
1878                 GT_GEN6_BSD_USER_INTERRUPT |
1879                 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1880                 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1881                 GT_PIPE_NOTIFY |
1882                 GT_RENDER_CS_ERROR_INTERRUPT |
1883                 GT_SYNC_STATUS |
1884                 GT_USER_INTERRUPT;
1885
1886         dev_priv->gt_irq_mask = ~render_irqs;
1887
1888         I915_WRITE(GTIIR, I915_READ(GTIIR));
1889         I915_WRITE(GTIIR, I915_READ(GTIIR));
1890         I915_WRITE(GTIMR, 0);
1891         I915_WRITE(GTIER, render_irqs);
1892         POSTING_READ(GTIER);
1893
1894         /* ack & enable invalid PTE error interrupts */
1895 #if 0 /* FIXME: add support to irq handler for checking these bits */
1896         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1897         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1898 #endif
1899
1900         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1901 #if 0 /* FIXME: check register definitions; some have moved */
1902         /* Note HDMI and DP share bits */
1903         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1904                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1905         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1906                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1907         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1908                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1909         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1910                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1911         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1912                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1913         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1914                 hotplug_en |= CRT_HOTPLUG_INT_EN;
1915                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1916         }
1917 #endif
1918
1919         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1920
1921         return 0;
1922 }
1923
1924 static void valleyview_irq_uninstall(struct drm_device *dev)
1925 {
1926         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1927         int pipe;
1928
1929         if (!dev_priv)
1930                 return;
1931
1932         for_each_pipe(pipe)
1933                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1934
1935         I915_WRITE(HWSTAM, 0xffffffff);
1936         I915_WRITE(PORT_HOTPLUG_EN, 0);
1937         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1938         for_each_pipe(pipe)
1939                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1940         I915_WRITE(VLV_IIR, 0xffffffff);
1941         I915_WRITE(VLV_IMR, 0xffffffff);
1942         I915_WRITE(VLV_IER, 0x0);
1943         POSTING_READ(VLV_IER);
1944 }
1945
1946 static void ironlake_irq_uninstall(struct drm_device *dev)
1947 {
1948         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1949
1950         if (!dev_priv)
1951                 return;
1952
1953         I915_WRITE(HWSTAM, 0xffffffff);
1954
1955         I915_WRITE(DEIMR, 0xffffffff);
1956         I915_WRITE(DEIER, 0x0);
1957         I915_WRITE(DEIIR, I915_READ(DEIIR));
1958
1959         I915_WRITE(GTIMR, 0xffffffff);
1960         I915_WRITE(GTIER, 0x0);
1961         I915_WRITE(GTIIR, I915_READ(GTIIR));
1962
1963         I915_WRITE(SDEIMR, 0xffffffff);
1964         I915_WRITE(SDEIER, 0x0);
1965         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1966 }
1967
1968 static void i8xx_irq_preinstall(struct drm_device * dev)
1969 {
1970         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1971         int pipe;
1972
1973         atomic_set(&dev_priv->irq_received, 0);
1974
1975         for_each_pipe(pipe)
1976                 I915_WRITE(PIPESTAT(pipe), 0);
1977         I915_WRITE16(IMR, 0xffff);
1978         I915_WRITE16(IER, 0x0);
1979         POSTING_READ16(IER);
1980 }
1981
1982 static int i8xx_irq_postinstall(struct drm_device *dev)
1983 {
1984         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1985
1986         dev_priv->pipestat[0] = 0;
1987         dev_priv->pipestat[1] = 0;
1988
1989         I915_WRITE16(EMR,
1990                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
1991
1992         /* Unmask the interrupts that we always want on. */
1993         dev_priv->irq_mask =
1994                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1995                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1996                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
1997                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
1998                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1999         I915_WRITE16(IMR, dev_priv->irq_mask);
2000
2001         I915_WRITE16(IER,
2002                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2003                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2004                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2005                      I915_USER_INTERRUPT);
2006         POSTING_READ16(IER);
2007
2008         return 0;
2009 }
2010
2011 static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2012 {
2013         struct drm_device *dev = (struct drm_device *) arg;
2014         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2015         u16 iir, new_iir;
2016         u32 pipe_stats[2];
2017         unsigned long irqflags;
2018         int irq_received;
2019         int pipe;
2020         u16 flip_mask =
2021                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2022                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2023
2024         atomic_inc(&dev_priv->irq_received);
2025
2026         iir = I915_READ16(IIR);
2027         if (iir == 0)
2028                 return IRQ_NONE;
2029
2030         while (iir & ~flip_mask) {
2031                 /* Can't rely on pipestat interrupt bit in iir as it might
2032                  * have been cleared after the pipestat interrupt was received.
2033                  * It doesn't set the bit in iir again, but it still produces
2034                  * interrupts (for non-MSI).
2035                  */
2036                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2037                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2038                         i915_handle_error(dev, false);
2039
2040                 for_each_pipe(pipe) {
2041                         int reg = PIPESTAT(pipe);
2042                         pipe_stats[pipe] = I915_READ(reg);
2043
2044                         /*
2045                          * Clear the PIPE*STAT regs before the IIR
2046                          */
2047                         if (pipe_stats[pipe] & 0x8000ffff) {
2048                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2049                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2050                                                          pipe_name(pipe));
2051                                 I915_WRITE(reg, pipe_stats[pipe]);
2052                                 irq_received = 1;
2053                         }
2054                 }
2055                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2056
2057                 I915_WRITE16(IIR, iir & ~flip_mask);
2058                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2059
2060                 i915_update_dri1_breadcrumb(dev);
2061
2062                 if (iir & I915_USER_INTERRUPT)
2063                         notify_ring(dev, &dev_priv->ring[RCS]);
2064
2065                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2066                     drm_handle_vblank(dev, 0)) {
2067                         if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2068                                 intel_prepare_page_flip(dev, 0);
2069                                 intel_finish_page_flip(dev, 0);
2070                                 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2071                         }
2072                 }
2073
2074                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2075                     drm_handle_vblank(dev, 1)) {
2076                         if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2077                                 intel_prepare_page_flip(dev, 1);
2078                                 intel_finish_page_flip(dev, 1);
2079                                 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2080                         }
2081                 }
2082
2083                 iir = new_iir;
2084         }
2085
2086         return IRQ_HANDLED;
2087 }
2088
2089 static void i8xx_irq_uninstall(struct drm_device * dev)
2090 {
2091         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2092         int pipe;
2093
2094         for_each_pipe(pipe) {
2095                 /* Clear enable bits; then clear status bits */
2096                 I915_WRITE(PIPESTAT(pipe), 0);
2097                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2098         }
2099         I915_WRITE16(IMR, 0xffff);
2100         I915_WRITE16(IER, 0x0);
2101         I915_WRITE16(IIR, I915_READ16(IIR));
2102 }
2103
2104 static void i915_irq_preinstall(struct drm_device * dev)
2105 {
2106         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2107         int pipe;
2108
2109         atomic_set(&dev_priv->irq_received, 0);
2110
2111         if (I915_HAS_HOTPLUG(dev)) {
2112                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2113                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2114         }
2115
2116         I915_WRITE16(HWSTAM, 0xeffe);
2117         for_each_pipe(pipe)
2118                 I915_WRITE(PIPESTAT(pipe), 0);
2119         I915_WRITE(IMR, 0xffffffff);
2120         I915_WRITE(IER, 0x0);
2121         POSTING_READ(IER);
2122 }
2123
2124 static int i915_irq_postinstall(struct drm_device *dev)
2125 {
2126         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2127         u32 enable_mask;
2128
2129         dev_priv->pipestat[0] = 0;
2130         dev_priv->pipestat[1] = 0;
2131
2132         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2133
2134         /* Unmask the interrupts that we always want on. */
2135         dev_priv->irq_mask =
2136                 ~(I915_ASLE_INTERRUPT |
2137                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2138                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2139                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2140                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2141                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2142
2143         enable_mask =
2144                 I915_ASLE_INTERRUPT |
2145                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2146                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2147                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2148                 I915_USER_INTERRUPT;
2149
2150         if (I915_HAS_HOTPLUG(dev)) {
2151                 /* Enable in IER... */
2152                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2153                 /* and unmask in IMR */
2154                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2155         }
2156
2157         I915_WRITE(IMR, dev_priv->irq_mask);
2158         I915_WRITE(IER, enable_mask);
2159         POSTING_READ(IER);
2160
2161         if (I915_HAS_HOTPLUG(dev)) {
2162                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2163
2164                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2165                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2166                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2167                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2168                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2169                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2170                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2171                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2172                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2173                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2174                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2175                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2176                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2177                 }
2178
2179                 /* Ignore TV since it's buggy */
2180
2181                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2182         }
2183
2184         intel_opregion_enable_asle(dev);
2185
2186         return 0;
2187 }
2188
2189 static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2190 {
2191         struct drm_device *dev = (struct drm_device *) arg;
2192         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2193         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2194         unsigned long irqflags;
2195         u32 flip_mask =
2196                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2197                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2198         u32 flip[2] = {
2199                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2200                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2201         };
2202         int pipe, ret = IRQ_NONE;
2203
2204         atomic_inc(&dev_priv->irq_received);
2205
2206         iir = I915_READ(IIR);
2207         do {
2208                 bool irq_received = (iir & ~flip_mask) != 0;
2209                 bool blc_event = false;
2210
2211                 /* Can't rely on pipestat interrupt bit in iir as it might
2212                  * have been cleared after the pipestat interrupt was received.
2213                  * It doesn't set the bit in iir again, but it still produces
2214                  * interrupts (for non-MSI).
2215                  */
2216                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2217                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2218                         i915_handle_error(dev, false);
2219
2220                 for_each_pipe(pipe) {
2221                         int reg = PIPESTAT(pipe);
2222                         pipe_stats[pipe] = I915_READ(reg);
2223
2224                         /* Clear the PIPE*STAT regs before the IIR */
2225                         if (pipe_stats[pipe] & 0x8000ffff) {
2226                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2227                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2228                                                          pipe_name(pipe));
2229                                 I915_WRITE(reg, pipe_stats[pipe]);
2230                                 irq_received = true;
2231                         }
2232                 }
2233                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2234
2235                 if (!irq_received)
2236                         break;
2237
2238                 /* Consume port.  Then clear IIR or we'll miss events */
2239                 if ((I915_HAS_HOTPLUG(dev)) &&
2240                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2241                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2242
2243                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2244                                   hotplug_status);
2245                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2246                                 queue_work(dev_priv->wq,
2247                                            &dev_priv->hotplug_work);
2248
2249                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2250                         POSTING_READ(PORT_HOTPLUG_STAT);
2251                 }
2252
2253                 I915_WRITE(IIR, iir & ~flip_mask);
2254                 new_iir = I915_READ(IIR); /* Flush posted writes */
2255
2256                 if (iir & I915_USER_INTERRUPT)
2257                         notify_ring(dev, &dev_priv->ring[RCS]);
2258
2259                 for_each_pipe(pipe) {
2260                         int plane = pipe;
2261                         if (IS_MOBILE(dev))
2262                                 plane = !plane;
2263                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2264                             drm_handle_vblank(dev, pipe)) {
2265                                 if (iir & flip[plane]) {
2266                                         intel_prepare_page_flip(dev, plane);
2267                                         intel_finish_page_flip(dev, pipe);
2268                                         flip_mask &= ~flip[plane];
2269                                 }
2270                         }
2271
2272                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2273                                 blc_event = true;
2274                 }
2275
2276                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2277                         intel_opregion_asle_intr(dev);
2278
2279                 /* With MSI, interrupts are only generated when iir
2280                  * transitions from zero to nonzero.  If another bit got
2281                  * set while we were handling the existing iir bits, then
2282                  * we would never get another interrupt.
2283                  *
2284                  * This is fine on non-MSI as well, as if we hit this path
2285                  * we avoid exiting the interrupt handler only to generate
2286                  * another one.
2287                  *
2288                  * Note that for MSI this could cause a stray interrupt report
2289                  * if an interrupt landed in the time between writing IIR and
2290                  * the posting read.  This should be rare enough to never
2291                  * trigger the 99% of 100,000 interrupts test for disabling
2292                  * stray interrupts.
2293                  */
2294                 ret = IRQ_HANDLED;
2295                 iir = new_iir;
2296         } while (iir & ~flip_mask);
2297
2298         i915_update_dri1_breadcrumb(dev);
2299
2300         return ret;
2301 }
2302
2303 static void i915_irq_uninstall(struct drm_device * dev)
2304 {
2305         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2306         int pipe;
2307
2308         if (I915_HAS_HOTPLUG(dev)) {
2309                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2310                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2311         }
2312
2313         I915_WRITE16(HWSTAM, 0xffff);
2314         for_each_pipe(pipe) {
2315                 /* Clear enable bits; then clear status bits */
2316                 I915_WRITE(PIPESTAT(pipe), 0);
2317                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2318         }
2319         I915_WRITE(IMR, 0xffffffff);
2320         I915_WRITE(IER, 0x0);
2321
2322         I915_WRITE(IIR, I915_READ(IIR));
2323 }
2324
2325 static void i965_irq_preinstall(struct drm_device * dev)
2326 {
2327         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2328         int pipe;
2329
2330         atomic_set(&dev_priv->irq_received, 0);
2331
2332         if (I915_HAS_HOTPLUG(dev)) {
2333                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2334                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2335         }
2336
2337         I915_WRITE(HWSTAM, 0xeffe);
2338         for_each_pipe(pipe)
2339                 I915_WRITE(PIPESTAT(pipe), 0);
2340         I915_WRITE(IMR, 0xffffffff);
2341         I915_WRITE(IER, 0x0);
2342         POSTING_READ(IER);
2343 }
2344
2345 static int i965_irq_postinstall(struct drm_device *dev)
2346 {
2347         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2348         u32 enable_mask;
2349         u32 error_mask;
2350
2351         /* Unmask the interrupts that we always want on. */
2352         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2353                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2354                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2355                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2356                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2357                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2358
2359         enable_mask = ~dev_priv->irq_mask;
2360         enable_mask |= I915_USER_INTERRUPT;
2361
2362         if (IS_G4X(dev))
2363                 enable_mask |= I915_BSD_USER_INTERRUPT;
2364
2365         dev_priv->pipestat[0] = 0;
2366         dev_priv->pipestat[1] = 0;
2367
2368         if (I915_HAS_HOTPLUG(dev)) {
2369                 /* Enable in IER... */
2370                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2371                 /* and unmask in IMR */
2372                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2373         }
2374
2375         /*
2376          * Enable some error detection, note the instruction error mask
2377          * bit is reserved, so we leave it masked.
2378          */
2379         if (IS_G4X(dev)) {
2380                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2381                                GM45_ERROR_MEM_PRIV |
2382                                GM45_ERROR_CP_PRIV |
2383                                I915_ERROR_MEMORY_REFRESH);
2384         } else {
2385                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2386                                I915_ERROR_MEMORY_REFRESH);
2387         }
2388         I915_WRITE(EMR, error_mask);
2389
2390         I915_WRITE(IMR, dev_priv->irq_mask);
2391         I915_WRITE(IER, enable_mask);
2392         POSTING_READ(IER);
2393
2394         if (I915_HAS_HOTPLUG(dev)) {
2395                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2396
2397                 /* Note HDMI and DP share bits */
2398                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2399                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2400                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2401                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2402                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2403                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2404                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2405                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2406                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2407                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2408                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2409                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2410
2411                         /* Programming the CRT detection parameters tends
2412                            to generate a spurious hotplug event about three
2413                            seconds later.  So just do it once.
2414                         */
2415                         if (IS_G4X(dev))
2416                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2417                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2418                 }
2419
2420                 /* Ignore TV since it's buggy */
2421
2422                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2423         }
2424
2425         intel_opregion_enable_asle(dev);
2426
2427         return 0;
2428 }
2429
2430 static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2431 {
2432         struct drm_device *dev = (struct drm_device *) arg;
2433         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2434         u32 iir, new_iir;
2435         u32 pipe_stats[I915_MAX_PIPES];
2436         unsigned long irqflags;
2437         int irq_received;
2438         int ret = IRQ_NONE, pipe;
2439
2440         atomic_inc(&dev_priv->irq_received);
2441
2442         iir = I915_READ(IIR);
2443
2444         for (;;) {
2445                 bool blc_event = false;
2446
2447                 irq_received = iir != 0;
2448
2449                 /* Can't rely on pipestat interrupt bit in iir as it might
2450                  * have been cleared after the pipestat interrupt was received.
2451                  * It doesn't set the bit in iir again, but it still produces
2452                  * interrupts (for non-MSI).
2453                  */
2454                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2455                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2456                         i915_handle_error(dev, false);
2457
2458                 for_each_pipe(pipe) {
2459                         int reg = PIPESTAT(pipe);
2460                         pipe_stats[pipe] = I915_READ(reg);
2461
2462                         /*
2463                          * Clear the PIPE*STAT regs before the IIR
2464                          */
2465                         if (pipe_stats[pipe] & 0x8000ffff) {
2466                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2467                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2468                                                          pipe_name(pipe));
2469                                 I915_WRITE(reg, pipe_stats[pipe]);
2470                                 irq_received = 1;
2471                         }
2472                 }
2473                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2474
2475                 if (!irq_received)
2476                         break;
2477
2478                 ret = IRQ_HANDLED;
2479
2480                 /* Consume port.  Then clear IIR or we'll miss events */
2481                 if ((I915_HAS_HOTPLUG(dev)) &&
2482                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2483                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2484
2485                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2486                                   hotplug_status);
2487                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2488                                 queue_work(dev_priv->wq,
2489                                            &dev_priv->hotplug_work);
2490
2491                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2492                         I915_READ(PORT_HOTPLUG_STAT);
2493                 }
2494
2495                 I915_WRITE(IIR, iir);
2496                 new_iir = I915_READ(IIR); /* Flush posted writes */
2497
2498                 if (iir & I915_USER_INTERRUPT)
2499                         notify_ring(dev, &dev_priv->ring[RCS]);
2500                 if (iir & I915_BSD_USER_INTERRUPT)
2501                         notify_ring(dev, &dev_priv->ring[VCS]);
2502
2503                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2504                         intel_prepare_page_flip(dev, 0);
2505
2506                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2507                         intel_prepare_page_flip(dev, 1);
2508
2509                 for_each_pipe(pipe) {
2510                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2511                             drm_handle_vblank(dev, pipe)) {
2512                                 i915_pageflip_stall_check(dev, pipe);
2513                                 intel_finish_page_flip(dev, pipe);
2514                         }
2515
2516                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2517                                 blc_event = true;
2518                 }
2519
2520
2521                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2522                         intel_opregion_asle_intr(dev);
2523
2524                 /* With MSI, interrupts are only generated when iir
2525                  * transitions from zero to nonzero.  If another bit got
2526                  * set while we were handling the existing iir bits, then
2527                  * we would never get another interrupt.
2528                  *
2529                  * This is fine on non-MSI as well, as if we hit this path
2530                  * we avoid exiting the interrupt handler only to generate
2531                  * another one.
2532                  *
2533                  * Note that for MSI this could cause a stray interrupt report
2534                  * if an interrupt landed in the time between writing IIR and
2535                  * the posting read.  This should be rare enough to never
2536                  * trigger the 99% of 100,000 interrupts test for disabling
2537                  * stray interrupts.
2538                  */
2539                 iir = new_iir;
2540         }
2541
2542         i915_update_dri1_breadcrumb(dev);
2543
2544         return ret;
2545 }
2546
2547 static void i965_irq_uninstall(struct drm_device * dev)
2548 {
2549         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2550         int pipe;
2551
2552         if (!dev_priv)
2553                 return;
2554
2555         if (I915_HAS_HOTPLUG(dev)) {
2556                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2557                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2558         }
2559
2560         I915_WRITE(HWSTAM, 0xffffffff);
2561         for_each_pipe(pipe)
2562                 I915_WRITE(PIPESTAT(pipe), 0);
2563         I915_WRITE(IMR, 0xffffffff);
2564         I915_WRITE(IER, 0x0);
2565
2566         for_each_pipe(pipe)
2567                 I915_WRITE(PIPESTAT(pipe),
2568                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2569         I915_WRITE(IIR, I915_READ(IIR));
2570 }
2571
2572 void intel_irq_init(struct drm_device *dev)
2573 {
2574         struct drm_i915_private *dev_priv = dev->dev_private;
2575
2576         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2577         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2578         INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2579
2580         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2581         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2582         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2583                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2584                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2585         }
2586
2587         if (drm_core_check_feature(dev, DRIVER_MODESET))
2588                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2589         else
2590                 dev->driver->get_vblank_timestamp = NULL;
2591         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2592
2593         if (IS_VALLEYVIEW(dev)) {
2594                 dev->driver->irq_handler = valleyview_irq_handler;
2595                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2596                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2597                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2598                 dev->driver->enable_vblank = valleyview_enable_vblank;
2599                 dev->driver->disable_vblank = valleyview_disable_vblank;
2600         } else if (IS_IVYBRIDGE(dev)) {
2601                 /* Share pre & uninstall handlers with ILK/SNB */
2602                 dev->driver->irq_handler = ivybridge_irq_handler;
2603                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2604                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2605                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2606                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2607                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2608         } else if (IS_HASWELL(dev)) {
2609                 /* Share interrupts handling with IVB */
2610                 dev->driver->irq_handler = ivybridge_irq_handler;
2611                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2612                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2613                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2614                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2615                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2616         } else if (HAS_PCH_SPLIT(dev)) {
2617                 dev->driver->irq_handler = ironlake_irq_handler;
2618                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2619                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2620                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2621                 dev->driver->enable_vblank = ironlake_enable_vblank;
2622                 dev->driver->disable_vblank = ironlake_disable_vblank;
2623         } else {
2624                 if (INTEL_INFO(dev)->gen == 2) {
2625                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2626                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2627                         dev->driver->irq_handler = i8xx_irq_handler;
2628                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2629                 } else if (INTEL_INFO(dev)->gen == 3) {
2630                         /* IIR "flip pending" means done if this bit is set */
2631                         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2632
2633                         dev->driver->irq_preinstall = i915_irq_preinstall;
2634                         dev->driver->irq_postinstall = i915_irq_postinstall;
2635                         dev->driver->irq_uninstall = i915_irq_uninstall;
2636                         dev->driver->irq_handler = i915_irq_handler;
2637                 } else {
2638                         dev->driver->irq_preinstall = i965_irq_preinstall;
2639                         dev->driver->irq_postinstall = i965_irq_postinstall;
2640                         dev->driver->irq_uninstall = i965_irq_uninstall;
2641                         dev->driver->irq_handler = i965_irq_handler;
2642                 }
2643                 dev->driver->enable_vblank = i915_enable_vblank;
2644                 dev->driver->disable_vblank = i915_disable_vblank;
2645         }
2646 }