drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      I915_LEGACY_BLC_EVENT_ENABLE);
 175                 if (IS_I965G(dev))
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              I915_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 195
 196         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 197                 return 1;
 198
 199         return 0;
 200 }
 201
 202 /* Called from drm generic code, passed a 'crtc', which
 203  * we use as a pipe index
 204  */
 205 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 206 {
 207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 208         unsigned long high_frame;
 209         unsigned long low_frame;
 210         u32 high1, high2, low, count;
 211
 212         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 213         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 214
 215         if (!i915_pipe_enabled(dev, pipe)) {
 216                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 217                                 "pipe %d\n", pipe);
 218                 return 0;
 219         }
 220
 221         /*
 222          * High & low register fields aren't synchronized, so make sure
 223          * we get a low value that's stable across two reads of the high
 224          * register.
 225          */
 226         do {
 227                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 228                          PIPE_FRAME_HIGH_SHIFT);
 229                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 230                         PIPE_FRAME_LOW_SHIFT);
 231                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 232                          PIPE_FRAME_HIGH_SHIFT);
 233         } while (high1 != high2);
 234
 235         count = (high1 << 8) | low;
 236
 237         return count;
 238 }
 239
 240 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 241 {
 242         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 243         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 244
 245         if (!i915_pipe_enabled(dev, pipe)) {
 246                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 247                                         "pipe %d\n", pipe);
 248                 return 0;
 249         }
 250
 251         return I915_READ(reg);
 252 }
 253
 254 /*
 255  * Handle hotplug events outside the interrupt handler proper.
 256  */
 257 static void i915_hotplug_work_func(struct work_struct *work)
 258 {
 259         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 260                                                     hotplug_work);
 261         struct drm_device *dev = dev_priv->dev;
 262         struct drm_mode_config *mode_config = &dev->mode_config;
 263         struct drm_encoder *encoder;
 264
 265         if (mode_config->num_encoder) {
 266                 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 267                         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 268
 269                         if (intel_encoder->hot_plug)
 270                                 (*intel_encoder->hot_plug) (intel_encoder);
 271                 }
 272         }
 273         /* Just fire off a uevent and let userspace tell us what to do */
 274         drm_helper_hpd_irq_event(dev);
 275 }
 276
 277 static void i915_handle_rps_change(struct drm_device *dev)
 278 {
 279         drm_i915_private_t *dev_priv = dev->dev_private;
 280         u32 busy_up, busy_down, max_avg, min_avg;
 281         u16 rgvswctl;
 282         u8 new_delay = dev_priv->cur_delay;
 283
 284         I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
 285         busy_up = I915_READ(RCPREVBSYTUPAVG);
 286         busy_down = I915_READ(RCPREVBSYTDNAVG);
 287         max_avg = I915_READ(RCBMAXAVG);
 288         min_avg = I915_READ(RCBMINAVG);
 289
 290         /* Handle RCS change request from hw */
 291         if (busy_up > max_avg) {
 292                 if (dev_priv->cur_delay != dev_priv->max_delay)
 293                         new_delay = dev_priv->cur_delay - 1;
 294                 if (new_delay < dev_priv->max_delay)
 295                         new_delay = dev_priv->max_delay;
 296         } else if (busy_down < min_avg) {
 297                 if (dev_priv->cur_delay != dev_priv->min_delay)
 298                         new_delay = dev_priv->cur_delay + 1;
 299                 if (new_delay > dev_priv->min_delay)
 300                         new_delay = dev_priv->min_delay;
 301         }
 302
 303         DRM_DEBUG("rps change requested: %d -> %d\n",
 304                   dev_priv->cur_delay, new_delay);
 305
 306         rgvswctl = I915_READ(MEMSWCTL);
 307         if (rgvswctl & MEMCTL_CMD_STS) {
 308                 DRM_ERROR("gpu busy, RCS change rejected\n");
 309                 return; /* still busy with another command */
 310         }
 311
 312         /* Program the new state */
 313         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
 314                 (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
 315         I915_WRITE(MEMSWCTL, rgvswctl);
 316         POSTING_READ(MEMSWCTL);
 317
 318         rgvswctl |= MEMCTL_CMD_STS;
 319         I915_WRITE(MEMSWCTL, rgvswctl);
 320
 321         dev_priv->cur_delay = new_delay;
 322
 323         DRM_DEBUG("rps changed\n");
 324
 325         return;
 326 }
 327
 328 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 329 {
 330         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 331         int ret = IRQ_NONE;
 332         u32 de_iir, gt_iir, de_ier, pch_iir;
 333         struct drm_i915_master_private *master_priv;
 334         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 335
 336         /* disable master interrupt before clearing iir  */
 337         de_ier = I915_READ(DEIER);
 338         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 339         (void)I915_READ(DEIER);
 340
 341         de_iir = I915_READ(DEIIR);
 342         gt_iir = I915_READ(GTIIR);
 343         pch_iir = I915_READ(SDEIIR);
 344
 345         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 346                 goto done;
 347
 348         ret = IRQ_HANDLED;
 349
 350         if (dev->primary->master) {
 351                 master_priv = dev->primary->master->driver_priv;
 352                 if (master_priv->sarea_priv)
 353                         master_priv->sarea_priv->last_dispatch =
 354                                 READ_BREADCRUMB(dev_priv);
 355         }
 356
 357         if (gt_iir & GT_PIPE_NOTIFY) {
 358                 u32 seqno = render_ring->get_gem_seqno(dev, render_ring);
 359                 render_ring->irq_gem_seqno = seqno;
 360                 trace_i915_gem_request_complete(dev, seqno);
 361                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 362                 dev_priv->hangcheck_count = 0;
 363                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 364         }
 365
 366         if (de_iir & DE_GSE)
 367                 ironlake_opregion_gse_intr(dev);
 368
 369         if (de_iir & DE_PLANEA_FLIP_DONE) {
 370                 intel_prepare_page_flip(dev, 0);
 371                 intel_finish_page_flip(dev, 0);
 372         }
 373
 374         if (de_iir & DE_PLANEB_FLIP_DONE) {
 375                 intel_prepare_page_flip(dev, 1);
 376                 intel_finish_page_flip(dev, 1);
 377         }
 378
 379         if (de_iir & DE_PIPEA_VBLANK)
 380                 drm_handle_vblank(dev, 0);
 381
 382         if (de_iir & DE_PIPEB_VBLANK)
 383                 drm_handle_vblank(dev, 1);
 384
 385         /* check event from PCH */
 386         if ((de_iir & DE_PCH_EVENT) &&
 387             (pch_iir & SDE_HOTPLUG_MASK)) {
 388                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 389         }
 390
 391         if (de_iir & DE_PCU_EVENT) {
 392                 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS));
 393                 i915_handle_rps_change(dev);
 394         }
 395
 396         /* should clear PCH hotplug event before clear CPU irq */
 397         I915_WRITE(SDEIIR, pch_iir);
 398         I915_WRITE(GTIIR, gt_iir);
 399         I915_WRITE(DEIIR, de_iir);
 400
 401 done:
 402         I915_WRITE(DEIER, de_ier);
 403         (void)I915_READ(DEIER);
 404
 405         return ret;
 406 }
 407
 408 /**
 409  * i915_error_work_func - do process context error handling work
 410  * @work: work struct
 411  *
 412  * Fire an error uevent so userspace can see that a hang or error
 413  * was detected.
 414  */
 415 static void i915_error_work_func(struct work_struct *work)
 416 {
 417         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 418                                                     error_work);
 419         struct drm_device *dev = dev_priv->dev;
 420         char *error_event[] = { "ERROR=1", NULL };
 421         char *reset_event[] = { "RESET=1", NULL };
 422         char *reset_done_event[] = { "ERROR=0", NULL };
 423
 424         DRM_DEBUG_DRIVER("generating error event\n");
 425         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 426
 427         if (atomic_read(&dev_priv->mm.wedged)) {
 428                 if (IS_I965G(dev)) {
 429                         DRM_DEBUG_DRIVER("resetting chip\n");
 430                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 431                         if (!i965_reset(dev, GDRST_RENDER)) {
 432                                 atomic_set(&dev_priv->mm.wedged, 0);
 433                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 434                         }
 435                 } else {
 436                         DRM_DEBUG_DRIVER("reboot required\n");
 437                 }
 438         }
 439 }
 440
 441 static struct drm_i915_error_object *
 442 i915_error_object_create(struct drm_device *dev,
 443                          struct drm_gem_object *src)
 444 {
 445         struct drm_i915_error_object *dst;
 446         struct drm_i915_gem_object *src_priv;
 447         int page, page_count;
 448
 449         if (src == NULL)
 450                 return NULL;
 451
 452         src_priv = to_intel_bo(src);
 453         if (src_priv->pages == NULL)
 454                 return NULL;
 455
 456         page_count = src->size / PAGE_SIZE;
 457
 458         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 459         if (dst == NULL)
 460                 return NULL;
 461
 462         for (page = 0; page < page_count; page++) {
 463                 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 464                 unsigned long flags;
 465
 466                 if (d == NULL)
 467                         goto unwind;
 468                 local_irq_save(flags);
 469                 s = kmap_atomic(src_priv->pages[page], KM_IRQ0);
 470                 memcpy(d, s, PAGE_SIZE);
 471                 kunmap_atomic(s, KM_IRQ0);
 472                 local_irq_restore(flags);
 473                 dst->pages[page] = d;
 474         }
 475         dst->page_count = page_count;
 476         dst->gtt_offset = src_priv->gtt_offset;
 477
 478         return dst;
 479
 480 unwind:
 481         while (page--)
 482                 kfree(dst->pages[page]);
 483         kfree(dst);
 484         return NULL;
 485 }
 486
 487 static void
 488 i915_error_object_free(struct drm_i915_error_object *obj)
 489 {
 490         int page;
 491
 492         if (obj == NULL)
 493                 return;
 494
 495         for (page = 0; page < obj->page_count; page++)
 496                 kfree(obj->pages[page]);
 497
 498         kfree(obj);
 499 }
 500
 501 static void
 502 i915_error_state_free(struct drm_device *dev,
 503                       struct drm_i915_error_state *error)
 504 {
 505         i915_error_object_free(error->batchbuffer[0]);
 506         i915_error_object_free(error->batchbuffer[1]);
 507         i915_error_object_free(error->ringbuffer);
 508         kfree(error->active_bo);
 509         kfree(error);
 510 }
 511
 512 static u32
 513 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 514 {
 515         u32 cmd;
 516
 517         if (IS_I830(dev) || IS_845G(dev))
 518                 cmd = MI_BATCH_BUFFER;
 519         else if (IS_I965G(dev))
 520                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 521                        MI_BATCH_NON_SECURE_I965);
 522         else
 523                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 524
 525         return ring[0] == cmd ? ring[1] : 0;
 526 }
 527
 528 static u32
 529 i915_ringbuffer_last_batch(struct drm_device *dev)
 530 {
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         u32 head, bbaddr;
 533         u32 *ring;
 534
 535         /* Locate the current position in the ringbuffer and walk back
 536          * to find the most recently dispatched batch buffer.
 537          */
 538         bbaddr = 0;
 539         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 540         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 541
 542         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 543                 bbaddr = i915_get_bbaddr(dev, ring);
 544                 if (bbaddr)
 545                         break;
 546         }
 547
 548         if (bbaddr == 0) {
 549                 ring = (u32 *)(dev_priv->render_ring.virtual_start
 550                                 + dev_priv->render_ring.size);
 551                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 552                         bbaddr = i915_get_bbaddr(dev, ring);
 553                         if (bbaddr)
 554                                 break;
 555                 }
 556         }
 557
 558         return bbaddr;
 559 }
 560
 561 /**
 562  * i915_capture_error_state - capture an error record for later analysis
 563  * @dev: drm device
 564  *
 565  * Should be called when an error is detected (either a hang or an error
 566  * interrupt) to capture error state from the time of the error.  Fills
 567  * out a structure which becomes available in debugfs for user level tools
 568  * to pick up.
 569  */
 570 static void i915_capture_error_state(struct drm_device *dev)
 571 {
 572         struct drm_i915_private *dev_priv = dev->dev_private;
 573         struct drm_i915_gem_object *obj_priv;
 574         struct drm_i915_error_state *error;
 575         struct drm_gem_object *batchbuffer[2];
 576         unsigned long flags;
 577         u32 bbaddr;
 578         int count;
 579
 580         spin_lock_irqsave(&dev_priv->error_lock, flags);
 581         error = dev_priv->first_error;
 582         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 583         if (error)
 584                 return;
 585
 586         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 587         if (!error) {
 588                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 589                 return;
 590         }
 591
 592         error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring);
 593         error->eir = I915_READ(EIR);
 594         error->pgtbl_er = I915_READ(PGTBL_ER);
 595         error->pipeastat = I915_READ(PIPEASTAT);
 596         error->pipebstat = I915_READ(PIPEBSTAT);
 597         error->instpm = I915_READ(INSTPM);
 598         if (!IS_I965G(dev)) {
 599                 error->ipeir = I915_READ(IPEIR);
 600                 error->ipehr = I915_READ(IPEHR);
 601                 error->instdone = I915_READ(INSTDONE);
 602                 error->acthd = I915_READ(ACTHD);
 603                 error->bbaddr = 0;
 604         } else {
 605                 error->ipeir = I915_READ(IPEIR_I965);
 606                 error->ipehr = I915_READ(IPEHR_I965);
 607                 error->instdone = I915_READ(INSTDONE_I965);
 608                 error->instps = I915_READ(INSTPS);
 609                 error->instdone1 = I915_READ(INSTDONE1);
 610                 error->acthd = I915_READ(ACTHD_I965);
 611                 error->bbaddr = I915_READ64(BB_ADDR);
 612         }
 613
 614         bbaddr = i915_ringbuffer_last_batch(dev);
 615
 616         /* Grab the current batchbuffer, most likely to have crashed. */
 617         batchbuffer[0] = NULL;
 618         batchbuffer[1] = NULL;
 619         count = 0;
 620         list_for_each_entry(obj_priv,
 621                         &dev_priv->render_ring.active_list, list) {
 622
 623                 struct drm_gem_object *obj = &obj_priv->base;
 624
 625                 if (batchbuffer[0] == NULL &&
 626                     bbaddr >= obj_priv->gtt_offset &&
 627                     bbaddr < obj_priv->gtt_offset + obj->size)
 628                         batchbuffer[0] = obj;
 629
 630                 if (batchbuffer[1] == NULL &&
 631                     error->acthd >= obj_priv->gtt_offset &&
 632                     error->acthd < obj_priv->gtt_offset + obj->size &&
 633                     batchbuffer[0] != obj)
 634                         batchbuffer[1] = obj;
 635
 636                 count++;
 637         }
 638
 639         /* We need to copy these to an anonymous buffer as the simplest
 640          * method to avoid being overwritten by userpace.
 641          */
 642         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 643         error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 644
 645         /* Record the ringbuffer */
 646         error->ringbuffer = i915_error_object_create(dev,
 647                         dev_priv->render_ring.gem_object);
 648
 649         /* Record buffers on the active list. */
 650         error->active_bo = NULL;
 651         error->active_bo_count = 0;
 652
 653         if (count)
 654                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 655                                            GFP_ATOMIC);
 656
 657         if (error->active_bo) {
 658                 int i = 0;
 659                 list_for_each_entry(obj_priv,
 660                                 &dev_priv->render_ring.active_list, list) {
 661                         struct drm_gem_object *obj = &obj_priv->base;
 662
 663                         error->active_bo[i].size = obj->size;
 664                         error->active_bo[i].name = obj->name;
 665                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 666                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 667                         error->active_bo[i].read_domains = obj->read_domains;
 668                         error->active_bo[i].write_domain = obj->write_domain;
 669                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 670                         error->active_bo[i].pinned = 0;
 671                         if (obj_priv->pin_count > 0)
 672                                 error->active_bo[i].pinned = 1;
 673                         if (obj_priv->user_pin_count > 0)
 674                                 error->active_bo[i].pinned = -1;
 675                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 676                         error->active_bo[i].dirty = obj_priv->dirty;
 677                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 678
 679                         if (++i == count)
 680                                 break;
 681                 }
 682                 error->active_bo_count = i;
 683         }
 684
 685         do_gettimeofday(&error->time);
 686
 687         spin_lock_irqsave(&dev_priv->error_lock, flags);
 688         if (dev_priv->first_error == NULL) {
 689                 dev_priv->first_error = error;
 690                 error = NULL;
 691         }
 692         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 693
 694         if (error)
 695                 i915_error_state_free(dev, error);
 696 }
 697
 698 void i915_destroy_error_state(struct drm_device *dev)
 699 {
 700         struct drm_i915_private *dev_priv = dev->dev_private;
 701         struct drm_i915_error_state *error;
 702
 703         spin_lock(&dev_priv->error_lock);
 704         error = dev_priv->first_error;
 705         dev_priv->first_error = NULL;
 706         spin_unlock(&dev_priv->error_lock);
 707
 708         if (error)
 709                 i915_error_state_free(dev, error);
 710 }
 711
 712 /**
 713  * i915_handle_error - handle an error interrupt
 714  * @dev: drm device
 715  *
 716  * Do some basic checking of regsiter state at error interrupt time and
 717  * dump it to the syslog.  Also call i915_capture_error_state() to make
 718  * sure we get a record and make it available in debugfs.  Fire a uevent
 719  * so userspace knows something bad happened (should trigger collection
 720  * of a ring dump etc.).
 721  */
 722 static void i915_handle_error(struct drm_device *dev, bool wedged)
 723 {
 724         struct drm_i915_private *dev_priv = dev->dev_private;
 725         u32 eir = I915_READ(EIR);
 726         u32 pipea_stats = I915_READ(PIPEASTAT);
 727         u32 pipeb_stats = I915_READ(PIPEBSTAT);
 728
 729         i915_capture_error_state(dev);
 730
 731         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 732                eir);
 733
 734         if (IS_G4X(dev)) {
 735                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 736                         u32 ipeir = I915_READ(IPEIR_I965);
 737
 738                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 739                                I915_READ(IPEIR_I965));
 740                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 741                                I915_READ(IPEHR_I965));
 742                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 743                                I915_READ(INSTDONE_I965));
 744                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 745                                I915_READ(INSTPS));
 746                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 747                                I915_READ(INSTDONE1));
 748                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 749                                I915_READ(ACTHD_I965));
 750                         I915_WRITE(IPEIR_I965, ipeir);
 751                         (void)I915_READ(IPEIR_I965);
 752                 }
 753                 if (eir & GM45_ERROR_PAGE_TABLE) {
 754                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 755                         printk(KERN_ERR "page table error\n");
 756                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 757                                pgtbl_err);
 758                         I915_WRITE(PGTBL_ER, pgtbl_err);
 759                         (void)I915_READ(PGTBL_ER);
 760                 }
 761         }
 762
 763         if (IS_I9XX(dev)) {
 764                 if (eir & I915_ERROR_PAGE_TABLE) {
 765                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 766                         printk(KERN_ERR "page table error\n");
 767                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 768                                pgtbl_err);
 769                         I915_WRITE(PGTBL_ER, pgtbl_err);
 770                         (void)I915_READ(PGTBL_ER);
 771                 }
 772         }
 773
 774         if (eir & I915_ERROR_MEMORY_REFRESH) {
 775                 printk(KERN_ERR "memory refresh error\n");
 776                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 777                        pipea_stats);
 778                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 779                        pipeb_stats);
 780                 /* pipestat has already been acked */
 781         }
 782         if (eir & I915_ERROR_INSTRUCTION) {
 783                 printk(KERN_ERR "instruction error\n");
 784                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 785                        I915_READ(INSTPM));
 786                 if (!IS_I965G(dev)) {
 787                         u32 ipeir = I915_READ(IPEIR);
 788
 789                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 790                                I915_READ(IPEIR));
 791                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 792                                I915_READ(IPEHR));
 793                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 794                                I915_READ(INSTDONE));
 795                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 796                                I915_READ(ACTHD));
 797                         I915_WRITE(IPEIR, ipeir);
 798                         (void)I915_READ(IPEIR);
 799                 } else {
 800                         u32 ipeir = I915_READ(IPEIR_I965);
 801
 802                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 803                                I915_READ(IPEIR_I965));
 804                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 805                                I915_READ(IPEHR_I965));
 806                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 807                                I915_READ(INSTDONE_I965));
 808                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 809                                I915_READ(INSTPS));
 810                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 811                                I915_READ(INSTDONE1));
 812                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 813                                I915_READ(ACTHD_I965));
 814                         I915_WRITE(IPEIR_I965, ipeir);
 815                         (void)I915_READ(IPEIR_I965);
 816                 }
 817         }
 818
 819         I915_WRITE(EIR, eir);
 820         (void)I915_READ(EIR);
 821         eir = I915_READ(EIR);
 822         if (eir) {
 823                 /*
 824                  * some errors might have become stuck,
 825                  * mask them.
 826                  */
 827                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 828                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 829                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 830         }
 831
 832         if (wedged) {
 833                 atomic_set(&dev_priv->mm.wedged, 1);
 834
 835                 /*
 836                  * Wakeup waiting processes so they don't hang
 837                  */
 838                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 839         }
 840
 841         queue_work(dev_priv->wq, &dev_priv->error_work);
 842 }
 843
 844 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 845 {
 846         struct drm_device *dev = (struct drm_device *) arg;
 847         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 848         struct drm_i915_master_private *master_priv;
 849         u32 iir, new_iir;
 850         u32 pipea_stats, pipeb_stats;
 851         u32 vblank_status;
 852         u32 vblank_enable;
 853         int vblank = 0;
 854         unsigned long irqflags;
 855         int irq_received;
 856         int ret = IRQ_NONE;
 857         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 858
 859         atomic_inc(&dev_priv->irq_received);
 860
 861         if (HAS_PCH_SPLIT(dev))
 862                 return ironlake_irq_handler(dev);
 863
 864         iir = I915_READ(IIR);
 865
 866         if (IS_I965G(dev)) {
 867                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 868                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 869         } else {
 870                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 871                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 872         }
 873
 874         for (;;) {
 875                 irq_received = iir != 0;
 876
 877                 /* Can't rely on pipestat interrupt bit in iir as it might
 878                  * have been cleared after the pipestat interrupt was received.
 879                  * It doesn't set the bit in iir again, but it still produces
 880                  * interrupts (for non-MSI).
 881                  */
 882                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 883                 pipea_stats = I915_READ(PIPEASTAT);
 884                 pipeb_stats = I915_READ(PIPEBSTAT);
 885
 886                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 887                         i915_handle_error(dev, false);
 888
 889                 /*
 890                  * Clear the PIPE(A|B)STAT regs before the IIR
 891                  */
 892                 if (pipea_stats & 0x8000ffff) {
 893                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 894                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 895                         I915_WRITE(PIPEASTAT, pipea_stats);
 896                         irq_received = 1;
 897                 }
 898
 899                 if (pipeb_stats & 0x8000ffff) {
 900                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 901                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 902                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 903                         irq_received = 1;
 904                 }
 905                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 906
 907                 if (!irq_received)
 908                         break;
 909
 910                 ret = IRQ_HANDLED;
 911
 912                 /* Consume port.  Then clear IIR or we'll miss events */
 913                 if ((I915_HAS_HOTPLUG(dev)) &&
 914                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 915                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 916
 917                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 918                                   hotplug_status);
 919                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 920                                 queue_work(dev_priv->wq,
 921                                            &dev_priv->hotplug_work);
 922
 923                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 924                         I915_READ(PORT_HOTPLUG_STAT);
 925                 }
 926
 927                 I915_WRITE(IIR, iir);
 928                 new_iir = I915_READ(IIR); /* Flush posted writes */
 929
 930                 if (dev->primary->master) {
 931                         master_priv = dev->primary->master->driver_priv;
 932                         if (master_priv->sarea_priv)
 933                                 master_priv->sarea_priv->last_dispatch =
 934                                         READ_BREADCRUMB(dev_priv);
 935                 }
 936
 937                 if (iir & I915_USER_INTERRUPT) {
 938                         u32 seqno =
 939                                 render_ring->get_gem_seqno(dev, render_ring);
 940                         render_ring->irq_gem_seqno = seqno;
 941                         trace_i915_gem_request_complete(dev, seqno);
 942                         DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 943                         dev_priv->hangcheck_count = 0;
 944                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 945                 }
 946
 947                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
 948                         intel_prepare_page_flip(dev, 0);
 949
 950                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
 951                         intel_prepare_page_flip(dev, 1);
 952
 953                 if (pipea_stats & vblank_status) {
 954                         vblank++;
 955                         drm_handle_vblank(dev, 0);
 956                         intel_finish_page_flip(dev, 0);
 957                 }
 958
 959                 if (pipeb_stats & vblank_status) {
 960                         vblank++;
 961                         drm_handle_vblank(dev, 1);
 962                         intel_finish_page_flip(dev, 1);
 963                 }
 964
 965                 if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 966                     (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 967                     (iir & I915_ASLE_INTERRUPT))
 968                         opregion_asle_intr(dev);
 969
 970                 /* With MSI, interrupts are only generated when iir
 971                  * transitions from zero to nonzero.  If another bit got
 972                  * set while we were handling the existing iir bits, then
 973                  * we would never get another interrupt.
 974                  *
 975                  * This is fine on non-MSI as well, as if we hit this path
 976                  * we avoid exiting the interrupt handler only to generate
 977                  * another one.
 978                  *
 979                  * Note that for MSI this could cause a stray interrupt report
 980                  * if an interrupt landed in the time between writing IIR and
 981                  * the posting read.  This should be rare enough to never
 982                  * trigger the 99% of 100,000 interrupts test for disabling
 983                  * stray interrupts.
 984                  */
 985                 iir = new_iir;
 986         }
 987
 988         return ret;
 989 }
 990
 991 static int i915_emit_irq(struct drm_device * dev)
 992 {
 993         drm_i915_private_t *dev_priv = dev->dev_private;
 994         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 995
 996         i915_kernel_lost_context(dev);
 997
 998         DRM_DEBUG_DRIVER("\n");
 999
1000         dev_priv->counter++;
1001         if (dev_priv->counter > 0x7FFFFFFFUL)
1002                 dev_priv->counter = 1;
1003         if (master_priv->sarea_priv)
1004                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1005
1006         BEGIN_LP_RING(4);
1007         OUT_RING(MI_STORE_DWORD_INDEX);
1008         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1009         OUT_RING(dev_priv->counter);
1010         OUT_RING(MI_USER_INTERRUPT);
1011         ADVANCE_LP_RING();
1012
1013         return dev_priv->counter;
1014 }
1015
1016 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1017 {
1018         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1019         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1020
1021         if (dev_priv->trace_irq_seqno == 0)
1022                 render_ring->user_irq_get(dev, render_ring);
1023
1024         dev_priv->trace_irq_seqno = seqno;
1025 }
1026
1027 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1028 {
1029         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1030         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1031         int ret = 0;
1032         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1033
1034         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1035                   READ_BREADCRUMB(dev_priv));
1036
1037         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1038                 if (master_priv->sarea_priv)
1039                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1040                 return 0;
1041         }
1042
1043         if (master_priv->sarea_priv)
1044                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1045
1046         render_ring->user_irq_get(dev, render_ring);
1047         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1048                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1049         render_ring->user_irq_put(dev, render_ring);
1050
1051         if (ret == -EBUSY) {
1052                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1053                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1054         }
1055
1056         return ret;
1057 }
1058
1059 /* Needs the lock as it touches the ring.
1060  */
1061 int i915_irq_emit(struct drm_device *dev, void *data,
1062                          struct drm_file *file_priv)
1063 {
1064         drm_i915_private_t *dev_priv = dev->dev_private;
1065         drm_i915_irq_emit_t *emit = data;
1066         int result;
1067
1068         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1069                 DRM_ERROR("called with no initialization\n");
1070                 return -EINVAL;
1071         }
1072
1073         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1074
1075         mutex_lock(&dev->struct_mutex);
1076         result = i915_emit_irq(dev);
1077         mutex_unlock(&dev->struct_mutex);
1078
1079         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1080                 DRM_ERROR("copy_to_user\n");
1081                 return -EFAULT;
1082         }
1083
1084         return 0;
1085 }
1086
1087 /* Doesn't need the hardware lock.
1088  */
1089 int i915_irq_wait(struct drm_device *dev, void *data,
1090                          struct drm_file *file_priv)
1091 {
1092         drm_i915_private_t *dev_priv = dev->dev_private;
1093         drm_i915_irq_wait_t *irqwait = data;
1094
1095         if (!dev_priv) {
1096                 DRM_ERROR("called with no initialization\n");
1097                 return -EINVAL;
1098         }
1099
1100         return i915_wait_irq(dev, irqwait->irq_seq);
1101 }
1102
1103 /* Called from drm generic code, passed 'crtc' which
1104  * we use as a pipe index
1105  */
1106 int i915_enable_vblank(struct drm_device *dev, int pipe)
1107 {
1108         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1109         unsigned long irqflags;
1110         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1111         u32 pipeconf;
1112
1113         pipeconf = I915_READ(pipeconf_reg);
1114         if (!(pipeconf & PIPEACONF_ENABLE))
1115                 return -EINVAL;
1116
1117         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1118         if (HAS_PCH_SPLIT(dev))
1119                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1120                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1121         else if (IS_I965G(dev))
1122                 i915_enable_pipestat(dev_priv, pipe,
1123                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1124         else
1125                 i915_enable_pipestat(dev_priv, pipe,
1126                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1127         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1128         return 0;
1129 }
1130
1131 /* Called from drm generic code, passed 'crtc' which
1132  * we use as a pipe index
1133  */
1134 void i915_disable_vblank(struct drm_device *dev, int pipe)
1135 {
1136         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1137         unsigned long irqflags;
1138
1139         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1140         if (HAS_PCH_SPLIT(dev))
1141                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1142                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1143         else
1144                 i915_disable_pipestat(dev_priv, pipe,
1145                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1146                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1147         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1148 }
1149
1150 void i915_enable_interrupt (struct drm_device *dev)
1151 {
1152         struct drm_i915_private *dev_priv = dev->dev_private;
1153
1154         if (!HAS_PCH_SPLIT(dev))
1155                 opregion_enable_asle(dev);
1156         dev_priv->irq_enabled = 1;
1157 }
1158
1159
1160 /* Set the vblank monitor pipe
1161  */
1162 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1163                          struct drm_file *file_priv)
1164 {
1165         drm_i915_private_t *dev_priv = dev->dev_private;
1166
1167         if (!dev_priv) {
1168                 DRM_ERROR("called with no initialization\n");
1169                 return -EINVAL;
1170         }
1171
1172         return 0;
1173 }
1174
1175 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1176                          struct drm_file *file_priv)
1177 {
1178         drm_i915_private_t *dev_priv = dev->dev_private;
1179         drm_i915_vblank_pipe_t *pipe = data;
1180
1181         if (!dev_priv) {
1182                 DRM_ERROR("called with no initialization\n");
1183                 return -EINVAL;
1184         }
1185
1186         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1187
1188         return 0;
1189 }
1190
1191 /**
1192  * Schedule buffer swap at given vertical blank.
1193  */
1194 int i915_vblank_swap(struct drm_device *dev, void *data,
1195                      struct drm_file *file_priv)
1196 {
1197         /* The delayed swap mechanism was fundamentally racy, and has been
1198          * removed.  The model was that the client requested a delayed flip/swap
1199          * from the kernel, then waited for vblank before continuing to perform
1200          * rendering.  The problem was that the kernel might wake the client
1201          * up before it dispatched the vblank swap (since the lock has to be
1202          * held while touching the ringbuffer), in which case the client would
1203          * clear and start the next frame before the swap occurred, and
1204          * flicker would occur in addition to likely missing the vblank.
1205          *
1206          * In the absence of this ioctl, userland falls back to a correct path
1207          * of waiting for a vblank, then dispatching the swap on its own.
1208          * Context switching to userland and back is plenty fast enough for
1209          * meeting the requirements of vblank swapping.
1210          */
1211         return -EINVAL;
1212 }
1213
1214 struct drm_i915_gem_request *
1215 i915_get_tail_request(struct drm_device *dev)
1216 {
1217         drm_i915_private_t *dev_priv = dev->dev_private;
1218         return list_entry(dev_priv->render_ring.request_list.prev,
1219                         struct drm_i915_gem_request, list);
1220 }
1221
1222 /**
1223  * This is called when the chip hasn't reported back with completed
1224  * batchbuffers in a long time. The first time this is called we simply record
1225  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1226  * again, we assume the chip is wedged and try to fix it.
1227  */
1228 void i915_hangcheck_elapsed(unsigned long data)
1229 {
1230         struct drm_device *dev = (struct drm_device *)data;
1231         drm_i915_private_t *dev_priv = dev->dev_private;
1232         uint32_t acthd;
1233
1234         /* No reset support on this chip yet. */
1235         if (IS_GEN6(dev))
1236                 return;
1237
1238         if (!IS_I965G(dev))
1239                 acthd = I915_READ(ACTHD);
1240         else
1241                 acthd = I915_READ(ACTHD_I965);
1242
1243         /* If all work is done then ACTHD clearly hasn't advanced. */
1244         if (list_empty(&dev_priv->render_ring.request_list) ||
1245                 i915_seqno_passed(i915_get_gem_seqno(dev,
1246                                 &dev_priv->render_ring),
1247                         i915_get_tail_request(dev)->seqno)) {
1248                 dev_priv->hangcheck_count = 0;
1249                 return;
1250         }
1251
1252         if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1253                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1254                 i915_handle_error(dev, true);
1255                 return;
1256         }
1257
1258         /* Reset timer case chip hangs without another request being added */
1259         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1260
1261         if (acthd != dev_priv->last_acthd)
1262                 dev_priv->hangcheck_count = 0;
1263         else
1264                 dev_priv->hangcheck_count++;
1265
1266         dev_priv->last_acthd = acthd;
1267 }
1268
1269 /* drm_dma.h hooks
1270 */
1271 static void ironlake_irq_preinstall(struct drm_device *dev)
1272 {
1273         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1274
1275         I915_WRITE(HWSTAM, 0xeffe);
1276
1277         /* XXX hotplug from PCH */
1278
1279         I915_WRITE(DEIMR, 0xffffffff);
1280         I915_WRITE(DEIER, 0x0);
1281         (void) I915_READ(DEIER);
1282
1283         /* and GT */
1284         I915_WRITE(GTIMR, 0xffffffff);
1285         I915_WRITE(GTIER, 0x0);
1286         (void) I915_READ(GTIER);
1287
1288         /* south display irq */
1289         I915_WRITE(SDEIMR, 0xffffffff);
1290         I915_WRITE(SDEIER, 0x0);
1291         (void) I915_READ(SDEIER);
1292 }
1293
1294 static int ironlake_irq_postinstall(struct drm_device *dev)
1295 {
1296         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1297         /* enable kind of interrupts always enabled */
1298         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1299                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1300         u32 render_mask = GT_PIPE_NOTIFY;
1301         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1302                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1303
1304         dev_priv->irq_mask_reg = ~display_mask;
1305         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1306
1307         /* should always can generate irq */
1308         I915_WRITE(DEIIR, I915_READ(DEIIR));
1309         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1310         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1311         (void) I915_READ(DEIER);
1312
1313         /* user interrupt should be enabled, but masked initial */
1314         dev_priv->gt_irq_mask_reg = ~render_mask;
1315         dev_priv->gt_irq_enable_reg = render_mask;
1316
1317         I915_WRITE(GTIIR, I915_READ(GTIIR));
1318         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1319         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1320         (void) I915_READ(GTIER);
1321
1322         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1323         dev_priv->pch_irq_enable_reg = hotplug_mask;
1324
1325         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1326         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1327         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1328         (void) I915_READ(SDEIER);
1329
1330         if (IS_IRONLAKE_M(dev)) {
1331                 /* Clear & enable PCU event interrupts */
1332                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1333                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1334                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1335         }
1336
1337         return 0;
1338 }
1339
1340 void i915_driver_irq_preinstall(struct drm_device * dev)
1341 {
1342         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1343
1344         atomic_set(&dev_priv->irq_received, 0);
1345
1346         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1347         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1348
1349         if (HAS_PCH_SPLIT(dev)) {
1350                 ironlake_irq_preinstall(dev);
1351                 return;
1352         }
1353
1354         if (I915_HAS_HOTPLUG(dev)) {
1355                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1356                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1357         }
1358
1359         I915_WRITE(HWSTAM, 0xeffe);
1360         I915_WRITE(PIPEASTAT, 0);
1361         I915_WRITE(PIPEBSTAT, 0);
1362         I915_WRITE(IMR, 0xffffffff);
1363         I915_WRITE(IER, 0x0);
1364         (void) I915_READ(IER);
1365 }
1366
1367 /*
1368  * Must be called after intel_modeset_init or hotplug interrupts won't be
1369  * enabled correctly.
1370  */
1371 int i915_driver_irq_postinstall(struct drm_device *dev)
1372 {
1373         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1374         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1375         u32 error_mask;
1376
1377         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1378
1379         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1380
1381         if (HAS_PCH_SPLIT(dev))
1382                 return ironlake_irq_postinstall(dev);
1383
1384         /* Unmask the interrupts that we always want on. */
1385         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1386
1387         dev_priv->pipestat[0] = 0;
1388         dev_priv->pipestat[1] = 0;
1389
1390         if (I915_HAS_HOTPLUG(dev)) {
1391                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1392
1393                 /* Note HDMI and DP share bits */
1394                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1395                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1396                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1397                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1398                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1399                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1400                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1401                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1402                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1403                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1404                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1405                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1406                 /* Ignore TV since it's buggy */
1407
1408                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1409
1410                 /* Enable in IER... */
1411                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1412                 /* and unmask in IMR */
1413                 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1414         }
1415
1416         /*
1417          * Enable some error detection, note the instruction error mask
1418          * bit is reserved, so we leave it masked.
1419          */
1420         if (IS_G4X(dev)) {
1421                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1422                                GM45_ERROR_MEM_PRIV |
1423                                GM45_ERROR_CP_PRIV |
1424                                I915_ERROR_MEMORY_REFRESH);
1425         } else {
1426                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1427                                I915_ERROR_MEMORY_REFRESH);
1428         }
1429         I915_WRITE(EMR, error_mask);
1430
1431         /* Disable pipe interrupt enables, clear pending pipe status */
1432         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1433         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1434         /* Clear pending interrupt status */
1435         I915_WRITE(IIR, I915_READ(IIR));
1436
1437         I915_WRITE(IER, enable_mask);
1438         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1439         (void) I915_READ(IER);
1440
1441         opregion_enable_asle(dev);
1442
1443         return 0;
1444 }
1445
1446 static void ironlake_irq_uninstall(struct drm_device *dev)
1447 {
1448         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1449         I915_WRITE(HWSTAM, 0xffffffff);
1450
1451         I915_WRITE(DEIMR, 0xffffffff);
1452         I915_WRITE(DEIER, 0x0);
1453         I915_WRITE(DEIIR, I915_READ(DEIIR));
1454
1455         I915_WRITE(GTIMR, 0xffffffff);
1456         I915_WRITE(GTIER, 0x0);
1457         I915_WRITE(GTIIR, I915_READ(GTIIR));
1458 }
1459
1460 void i915_driver_irq_uninstall(struct drm_device * dev)
1461 {
1462         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1463
1464         if (!dev_priv)
1465                 return;
1466
1467         dev_priv->vblank_pipe = 0;
1468
1469         if (HAS_PCH_SPLIT(dev)) {
1470                 ironlake_irq_uninstall(dev);
1471                 return;
1472         }
1473
1474         if (I915_HAS_HOTPLUG(dev)) {
1475                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1476                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1477         }
1478
1479         I915_WRITE(HWSTAM, 0xffffffff);
1480         I915_WRITE(PIPEASTAT, 0);
1481         I915_WRITE(PIPEBSTAT, 0);
1482         I915_WRITE(IMR, 0xffffffff);
1483         I915_WRITE(IER, 0x0);
1484
1485         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1486         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1487         I915_WRITE(IIR, I915_READ(IIR));
1488 }