1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
61 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
69 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
70 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt[HPD_NUM_PINS] = {
77 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
78 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
85 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
94 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
143 u32 val = I915_READ(reg); \
145 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
147 I915_WRITE((reg), 0xffffffff); \
149 I915_WRITE((reg), 0xffffffff); \
154 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
155 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
156 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
157 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
158 POSTING_READ(GEN8_##type##_IMR(which)); \
161 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
162 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
163 I915_WRITE(type##IER, (ier_val)); \
164 I915_WRITE(type##IMR, (imr_val)); \
165 POSTING_READ(type##IMR); \
168 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
171 * ilk_update_display_irq - update DEIMR
172 * @dev_priv: driver private
173 * @interrupt_mask: mask of interrupt bits to update
174 * @enabled_irq_mask: mask of interrupt bits to enable
176 static void ilk_update_display_irq(struct drm_i915_private *dev_priv,
177 uint32_t interrupt_mask,
178 uint32_t enabled_irq_mask)
182 assert_spin_locked(&dev_priv->irq_lock);
184 WARN_ON(enabled_irq_mask & ~interrupt_mask);
186 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
189 new_val = dev_priv->irq_mask;
190 new_val &= ~interrupt_mask;
191 new_val |= (~enabled_irq_mask & interrupt_mask);
193 if (new_val != dev_priv->irq_mask) {
194 dev_priv->irq_mask = new_val;
195 I915_WRITE(DEIMR, dev_priv->irq_mask);
201 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
203 ilk_update_display_irq(dev_priv, mask, mask);
207 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
209 ilk_update_display_irq(dev_priv, mask, 0);
213 * ilk_update_gt_irq - update GTIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
218 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
219 uint32_t interrupt_mask,
220 uint32_t enabled_irq_mask)
222 assert_spin_locked(&dev_priv->irq_lock);
224 WARN_ON(enabled_irq_mask & ~interrupt_mask);
226 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
229 dev_priv->gt_irq_mask &= ~interrupt_mask;
230 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
231 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
235 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
237 ilk_update_gt_irq(dev_priv, mask, mask);
240 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
242 ilk_update_gt_irq(dev_priv, mask, 0);
245 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
247 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
250 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
252 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
255 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
257 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
261 * snb_update_pm_irq - update GEN6_PMIMR
262 * @dev_priv: driver private
263 * @interrupt_mask: mask of interrupt bits to update
264 * @enabled_irq_mask: mask of interrupt bits to enable
266 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
267 uint32_t interrupt_mask,
268 uint32_t enabled_irq_mask)
272 WARN_ON(enabled_irq_mask & ~interrupt_mask);
274 assert_spin_locked(&dev_priv->irq_lock);
276 new_val = dev_priv->pm_irq_mask;
277 new_val &= ~interrupt_mask;
278 new_val |= (~enabled_irq_mask & interrupt_mask);
280 if (new_val != dev_priv->pm_irq_mask) {
281 dev_priv->pm_irq_mask = new_val;
282 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
283 POSTING_READ(gen6_pm_imr(dev_priv));
287 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
289 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
292 snb_update_pm_irq(dev_priv, mask, mask);
295 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
298 snb_update_pm_irq(dev_priv, mask, 0);
301 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
303 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
306 __gen6_disable_pm_irq(dev_priv, mask);
309 void gen6_reset_rps_interrupts(struct drm_device *dev)
311 struct drm_i915_private *dev_priv = dev->dev_private;
312 uint32_t reg = gen6_pm_iir(dev_priv);
314 spin_lock_irq(&dev_priv->irq_lock);
315 I915_WRITE(reg, dev_priv->pm_rps_events);
316 I915_WRITE(reg, dev_priv->pm_rps_events);
318 dev_priv->rps.pm_iir = 0;
319 spin_unlock_irq(&dev_priv->irq_lock);
322 void gen6_enable_rps_interrupts(struct drm_device *dev)
324 struct drm_i915_private *dev_priv = dev->dev_private;
326 spin_lock_irq(&dev_priv->irq_lock);
328 WARN_ON(dev_priv->rps.pm_iir);
329 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
330 dev_priv->rps.interrupts_enabled = true;
331 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
332 dev_priv->pm_rps_events);
333 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
335 spin_unlock_irq(&dev_priv->irq_lock);
338 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
341 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
342 * if GEN6_PM_UP_EI_EXPIRED is masked.
344 * TODO: verify if this can be reproduced on VLV,CHV.
346 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
347 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
349 if (INTEL_INFO(dev_priv)->gen >= 8)
350 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
355 void gen6_disable_rps_interrupts(struct drm_device *dev)
357 struct drm_i915_private *dev_priv = dev->dev_private;
359 spin_lock_irq(&dev_priv->irq_lock);
360 dev_priv->rps.interrupts_enabled = false;
361 spin_unlock_irq(&dev_priv->irq_lock);
363 cancel_work_sync(&dev_priv->rps.work);
365 spin_lock_irq(&dev_priv->irq_lock);
367 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
369 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
370 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
371 ~dev_priv->pm_rps_events);
373 spin_unlock_irq(&dev_priv->irq_lock);
375 synchronize_irq(dev->irq);
379 * bdw_update_port_irq - update DE port interrupt
380 * @dev_priv: driver private
381 * @interrupt_mask: mask of interrupt bits to update
382 * @enabled_irq_mask: mask of interrupt bits to enable
384 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
385 uint32_t interrupt_mask,
386 uint32_t enabled_irq_mask)
391 assert_spin_locked(&dev_priv->irq_lock);
393 WARN_ON(enabled_irq_mask & ~interrupt_mask);
395 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
398 old_val = I915_READ(GEN8_DE_PORT_IMR);
401 new_val &= ~interrupt_mask;
402 new_val |= (~enabled_irq_mask & interrupt_mask);
404 if (new_val != old_val) {
405 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
406 POSTING_READ(GEN8_DE_PORT_IMR);
411 * ibx_display_interrupt_update - update SDEIMR
412 * @dev_priv: driver private
413 * @interrupt_mask: mask of interrupt bits to update
414 * @enabled_irq_mask: mask of interrupt bits to enable
416 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
417 uint32_t interrupt_mask,
418 uint32_t enabled_irq_mask)
420 uint32_t sdeimr = I915_READ(SDEIMR);
421 sdeimr &= ~interrupt_mask;
422 sdeimr |= (~enabled_irq_mask & interrupt_mask);
424 WARN_ON(enabled_irq_mask & ~interrupt_mask);
426 assert_spin_locked(&dev_priv->irq_lock);
428 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
431 I915_WRITE(SDEIMR, sdeimr);
432 POSTING_READ(SDEIMR);
436 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
437 u32 enable_mask, u32 status_mask)
439 u32 reg = PIPESTAT(pipe);
440 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
442 assert_spin_locked(&dev_priv->irq_lock);
443 WARN_ON(!intel_irqs_enabled(dev_priv));
445 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
446 status_mask & ~PIPESTAT_INT_STATUS_MASK,
447 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
448 pipe_name(pipe), enable_mask, status_mask))
451 if ((pipestat & enable_mask) == enable_mask)
454 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
456 /* Enable the interrupt, clear any pending status */
457 pipestat |= enable_mask | status_mask;
458 I915_WRITE(reg, pipestat);
463 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
464 u32 enable_mask, u32 status_mask)
466 u32 reg = PIPESTAT(pipe);
467 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
469 assert_spin_locked(&dev_priv->irq_lock);
470 WARN_ON(!intel_irqs_enabled(dev_priv));
472 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
473 status_mask & ~PIPESTAT_INT_STATUS_MASK,
474 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
475 pipe_name(pipe), enable_mask, status_mask))
478 if ((pipestat & enable_mask) == 0)
481 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
483 pipestat &= ~enable_mask;
484 I915_WRITE(reg, pipestat);
488 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
490 u32 enable_mask = status_mask << 16;
493 * On pipe A we don't support the PSR interrupt yet,
494 * on pipe B and C the same bit MBZ.
496 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
499 * On pipe B and C we don't support the PSR interrupt yet, on pipe
500 * A the same bit is for perf counters which we don't use either.
502 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
505 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
506 SPRITE0_FLIP_DONE_INT_EN_VLV |
507 SPRITE1_FLIP_DONE_INT_EN_VLV);
508 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
509 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
510 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
511 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
517 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
522 if (IS_VALLEYVIEW(dev_priv->dev))
523 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
526 enable_mask = status_mask << 16;
527 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
531 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
536 if (IS_VALLEYVIEW(dev_priv->dev))
537 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
540 enable_mask = status_mask << 16;
541 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
545 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
547 static void i915_enable_asle_pipestat(struct drm_device *dev)
549 struct drm_i915_private *dev_priv = dev->dev_private;
551 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
554 spin_lock_irq(&dev_priv->irq_lock);
556 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
557 if (INTEL_INFO(dev)->gen >= 4)
558 i915_enable_pipestat(dev_priv, PIPE_A,
559 PIPE_LEGACY_BLC_EVENT_STATUS);
561 spin_unlock_irq(&dev_priv->irq_lock);
565 * This timing diagram depicts the video signal in and
566 * around the vertical blanking period.
568 * Assumptions about the fictitious mode used in this example:
570 * vsync_start = vblank_start + 1
571 * vsync_end = vblank_start + 2
572 * vtotal = vblank_start + 3
575 * latch double buffered registers
576 * increment frame counter (ctg+)
577 * generate start of vblank interrupt (gen4+)
580 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
581 * | may be shifted forward 1-3 extra lines via PIPECONF
583 * | | start of vsync:
584 * | | generate vsync interrupt
586 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
587 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
588 * ----va---> <-----------------vb--------------------> <--------va-------------
589 * | | <----vs-----> |
590 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
591 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
592 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
594 * last visible pixel first visible pixel
595 * | increment frame counter (gen3/4)
596 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
598 * x = horizontal active
599 * _ = horizontal blanking
600 * hs = horizontal sync
601 * va = vertical active
602 * vb = vertical blanking
604 * vbs = vblank_start (number)
607 * - most events happen at the start of horizontal sync
608 * - frame start happens at the start of horizontal blank, 1-4 lines
609 * (depending on PIPECONF settings) after the start of vblank
610 * - gen3/4 pixel and frame counter are synchronized with the start
611 * of horizontal active on the first line of vertical active
614 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
616 /* Gen2 doesn't have a hardware frame counter */
620 /* Called from drm generic code, passed a 'crtc', which
621 * we use as a pipe index
623 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
625 struct drm_i915_private *dev_priv = dev->dev_private;
626 unsigned long high_frame;
627 unsigned long low_frame;
628 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
629 struct intel_crtc *intel_crtc =
630 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
631 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
633 htotal = mode->crtc_htotal;
634 hsync_start = mode->crtc_hsync_start;
635 vbl_start = mode->crtc_vblank_start;
636 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
637 vbl_start = DIV_ROUND_UP(vbl_start, 2);
639 /* Convert to pixel count */
642 /* Start of vblank event occurs at start of hsync */
643 vbl_start -= htotal - hsync_start;
645 high_frame = PIPEFRAME(pipe);
646 low_frame = PIPEFRAMEPIXEL(pipe);
649 * High & low register fields aren't synchronized, so make sure
650 * we get a low value that's stable across two reads of the high
654 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
655 low = I915_READ(low_frame);
656 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
657 } while (high1 != high2);
659 high1 >>= PIPE_FRAME_HIGH_SHIFT;
660 pixel = low & PIPE_PIXEL_MASK;
661 low >>= PIPE_FRAME_LOW_SHIFT;
664 * The frame counter increments at beginning of active.
665 * Cook up a vblank counter by also checking the pixel
666 * counter against vblank start.
668 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
671 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
673 struct drm_i915_private *dev_priv = dev->dev_private;
674 int reg = PIPE_FRMCOUNT_GM45(pipe);
676 return I915_READ(reg);
679 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
680 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
682 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
684 struct drm_device *dev = crtc->base.dev;
685 struct drm_i915_private *dev_priv = dev->dev_private;
686 const struct drm_display_mode *mode = &crtc->base.hwmode;
687 enum pipe pipe = crtc->pipe;
688 int position, vtotal;
690 vtotal = mode->crtc_vtotal;
691 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
695 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
697 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
700 * On HSW, the DSL reg (0x70000) appears to return 0 if we
701 * read it just before the start of vblank. So try it again
702 * so we don't accidentally end up spanning a vblank frame
703 * increment, causing the pipe_update_end() code to squak at us.
705 * The nature of this problem means we can't simply check the ISR
706 * bit and return the vblank start value; nor can we use the scanline
707 * debug register in the transcoder as it appears to have the same
708 * problem. We may need to extend this to include other platforms,
709 * but so far testing only shows the problem on HSW.
711 if (IS_HASWELL(dev) && !position) {
714 for (i = 0; i < 100; i++) {
716 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
718 if (temp != position) {
726 * See update_scanline_offset() for the details on the
727 * scanline_offset adjustment.
729 return (position + crtc->scanline_offset) % vtotal;
732 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
733 unsigned int flags, int *vpos, int *hpos,
734 ktime_t *stime, ktime_t *etime,
735 const struct drm_display_mode *mode)
737 struct drm_i915_private *dev_priv = dev->dev_private;
738 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
741 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
744 unsigned long irqflags;
746 if (WARN_ON(!mode->crtc_clock)) {
747 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
748 "pipe %c\n", pipe_name(pipe));
752 htotal = mode->crtc_htotal;
753 hsync_start = mode->crtc_hsync_start;
754 vtotal = mode->crtc_vtotal;
755 vbl_start = mode->crtc_vblank_start;
756 vbl_end = mode->crtc_vblank_end;
758 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
759 vbl_start = DIV_ROUND_UP(vbl_start, 2);
764 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
767 * Lock uncore.lock, as we will do multiple timing critical raw
768 * register reads, potentially with preemption disabled, so the
769 * following code must not block on uncore.lock.
771 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
773 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
775 /* Get optional system timestamp before query. */
777 *stime = ktime_get();
779 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
780 /* No obvious pixelcount register. Only query vertical
781 * scanout position from Display scan line register.
783 position = __intel_get_crtc_scanline(intel_crtc);
785 /* Have access to pixelcount since start of frame.
786 * We can split this into vertical and horizontal
789 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
791 /* convert to pixel counts */
797 * In interlaced modes, the pixel counter counts all pixels,
798 * so one field will have htotal more pixels. In order to avoid
799 * the reported position from jumping backwards when the pixel
800 * counter is beyond the length of the shorter field, just
801 * clamp the position the length of the shorter field. This
802 * matches how the scanline counter based position works since
803 * the scanline counter doesn't count the two half lines.
805 if (position >= vtotal)
806 position = vtotal - 1;
809 * Start of vblank interrupt is triggered at start of hsync,
810 * just prior to the first active line of vblank. However we
811 * consider lines to start at the leading edge of horizontal
812 * active. So, should we get here before we've crossed into
813 * the horizontal active of the first line in vblank, we would
814 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
815 * always add htotal-hsync_start to the current pixel position.
817 position = (position + htotal - hsync_start) % vtotal;
820 /* Get optional system timestamp after query. */
822 *etime = ktime_get();
824 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
826 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
828 in_vbl = position >= vbl_start && position < vbl_end;
831 * While in vblank, position will be negative
832 * counting up towards 0 at vbl_end. And outside
833 * vblank, position will be positive counting
836 if (position >= vbl_start)
839 position += vtotal - vbl_end;
841 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
845 *vpos = position / htotal;
846 *hpos = position - (*vpos * htotal);
851 ret |= DRM_SCANOUTPOS_IN_VBLANK;
856 int intel_get_crtc_scanline(struct intel_crtc *crtc)
858 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
859 unsigned long irqflags;
862 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
863 position = __intel_get_crtc_scanline(crtc);
864 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
869 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
871 struct timeval *vblank_time,
874 struct drm_crtc *crtc;
876 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
877 DRM_ERROR("Invalid crtc %d\n", pipe);
881 /* Get drm_crtc to timestamp: */
882 crtc = intel_get_crtc_for_pipe(dev, pipe);
884 DRM_ERROR("Invalid crtc %d\n", pipe);
888 if (!crtc->hwmode.crtc_clock) {
889 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
893 /* Helper routine in DRM core does all the work: */
894 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
899 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
901 struct drm_i915_private *dev_priv = dev->dev_private;
902 u32 busy_up, busy_down, max_avg, min_avg;
905 spin_lock(&mchdev_lock);
907 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
909 new_delay = dev_priv->ips.cur_delay;
911 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
912 busy_up = I915_READ(RCPREVBSYTUPAVG);
913 busy_down = I915_READ(RCPREVBSYTDNAVG);
914 max_avg = I915_READ(RCBMAXAVG);
915 min_avg = I915_READ(RCBMINAVG);
917 /* Handle RCS change request from hw */
918 if (busy_up > max_avg) {
919 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
920 new_delay = dev_priv->ips.cur_delay - 1;
921 if (new_delay < dev_priv->ips.max_delay)
922 new_delay = dev_priv->ips.max_delay;
923 } else if (busy_down < min_avg) {
924 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
925 new_delay = dev_priv->ips.cur_delay + 1;
926 if (new_delay > dev_priv->ips.min_delay)
927 new_delay = dev_priv->ips.min_delay;
930 if (ironlake_set_drps(dev, new_delay))
931 dev_priv->ips.cur_delay = new_delay;
933 spin_unlock(&mchdev_lock);
938 static void notify_ring(struct intel_engine_cs *ring)
940 if (!intel_ring_initialized(ring))
943 trace_i915_gem_request_notify(ring);
945 wake_up_all(&ring->irq_queue);
948 static void vlv_c0_read(struct drm_i915_private *dev_priv,
949 struct intel_rps_ei *ei)
951 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
952 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
953 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
956 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
957 const struct intel_rps_ei *old,
958 const struct intel_rps_ei *now,
963 if (old->cz_clock == 0)
966 time = now->cz_clock - old->cz_clock;
967 time *= threshold * dev_priv->mem_freq;
969 /* Workload can be split between render + media, e.g. SwapBuffers
970 * being blitted in X after being rendered in mesa. To account for
971 * this we need to combine both engines into our activity counter.
973 c0 = now->render_c0 - old->render_c0;
974 c0 += now->media_c0 - old->media_c0;
975 c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000;
980 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
982 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
983 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
986 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
988 struct intel_rps_ei now;
991 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
994 vlv_c0_read(dev_priv, &now);
995 if (now.cz_clock == 0)
998 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
999 if (!vlv_c0_above(dev_priv,
1000 &dev_priv->rps.down_ei, &now,
1001 dev_priv->rps.down_threshold))
1002 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1003 dev_priv->rps.down_ei = now;
1006 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1007 if (vlv_c0_above(dev_priv,
1008 &dev_priv->rps.up_ei, &now,
1009 dev_priv->rps.up_threshold))
1010 events |= GEN6_PM_RP_UP_THRESHOLD;
1011 dev_priv->rps.up_ei = now;
1017 static bool any_waiters(struct drm_i915_private *dev_priv)
1019 struct intel_engine_cs *ring;
1022 for_each_ring(ring, dev_priv, i)
1023 if (ring->irq_refcount)
1029 static void gen6_pm_rps_work(struct work_struct *work)
1031 struct drm_i915_private *dev_priv =
1032 container_of(work, struct drm_i915_private, rps.work);
1034 int new_delay, adj, min, max;
1037 spin_lock_irq(&dev_priv->irq_lock);
1038 /* Speed up work cancelation during disabling rps interrupts. */
1039 if (!dev_priv->rps.interrupts_enabled) {
1040 spin_unlock_irq(&dev_priv->irq_lock);
1043 pm_iir = dev_priv->rps.pm_iir;
1044 dev_priv->rps.pm_iir = 0;
1045 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1046 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1047 client_boost = dev_priv->rps.client_boost;
1048 dev_priv->rps.client_boost = false;
1049 spin_unlock_irq(&dev_priv->irq_lock);
1051 /* Make sure we didn't queue anything we're not going to process. */
1052 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1054 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1057 mutex_lock(&dev_priv->rps.hw_lock);
1059 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1061 adj = dev_priv->rps.last_adj;
1062 new_delay = dev_priv->rps.cur_freq;
1063 min = dev_priv->rps.min_freq_softlimit;
1064 max = dev_priv->rps.max_freq_softlimit;
1067 new_delay = dev_priv->rps.max_freq_softlimit;
1069 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1072 else /* CHV needs even encode values */
1073 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1075 * For better performance, jump directly
1076 * to RPe if we're below it.
1078 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1079 new_delay = dev_priv->rps.efficient_freq;
1082 } else if (any_waiters(dev_priv)) {
1084 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1085 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1086 new_delay = dev_priv->rps.efficient_freq;
1088 new_delay = dev_priv->rps.min_freq_softlimit;
1090 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1093 else /* CHV needs even encode values */
1094 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1095 } else { /* unknown event */
1099 dev_priv->rps.last_adj = adj;
1101 /* sysfs frequency interfaces may have snuck in while servicing the
1105 new_delay = clamp_t(int, new_delay, min, max);
1107 intel_set_rps(dev_priv->dev, new_delay);
1109 mutex_unlock(&dev_priv->rps.hw_lock);
1114 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1116 * @work: workqueue struct
1118 * Doesn't actually do anything except notify userspace. As a consequence of
1119 * this event, userspace should try to remap the bad rows since statistically
1120 * it is likely the same row is more likely to go bad again.
1122 static void ivybridge_parity_work(struct work_struct *work)
1124 struct drm_i915_private *dev_priv =
1125 container_of(work, struct drm_i915_private, l3_parity.error_work);
1126 u32 error_status, row, bank, subbank;
1127 char *parity_event[6];
1131 /* We must turn off DOP level clock gating to access the L3 registers.
1132 * In order to prevent a get/put style interface, acquire struct mutex
1133 * any time we access those registers.
1135 mutex_lock(&dev_priv->dev->struct_mutex);
1137 /* If we've screwed up tracking, just let the interrupt fire again */
1138 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1141 misccpctl = I915_READ(GEN7_MISCCPCTL);
1142 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1143 POSTING_READ(GEN7_MISCCPCTL);
1145 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1149 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1152 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1154 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1156 error_status = I915_READ(reg);
1157 row = GEN7_PARITY_ERROR_ROW(error_status);
1158 bank = GEN7_PARITY_ERROR_BANK(error_status);
1159 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1161 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1164 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1165 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1166 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1167 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1168 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1169 parity_event[5] = NULL;
1171 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1172 KOBJ_CHANGE, parity_event);
1174 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1175 slice, row, bank, subbank);
1177 kfree(parity_event[4]);
1178 kfree(parity_event[3]);
1179 kfree(parity_event[2]);
1180 kfree(parity_event[1]);
1183 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1186 WARN_ON(dev_priv->l3_parity.which_slice);
1187 spin_lock_irq(&dev_priv->irq_lock);
1188 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1189 spin_unlock_irq(&dev_priv->irq_lock);
1191 mutex_unlock(&dev_priv->dev->struct_mutex);
1194 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1196 struct drm_i915_private *dev_priv = dev->dev_private;
1198 if (!HAS_L3_DPF(dev))
1201 spin_lock(&dev_priv->irq_lock);
1202 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1203 spin_unlock(&dev_priv->irq_lock);
1205 iir &= GT_PARITY_ERROR(dev);
1206 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1207 dev_priv->l3_parity.which_slice |= 1 << 1;
1209 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1210 dev_priv->l3_parity.which_slice |= 1 << 0;
1212 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1215 static void ilk_gt_irq_handler(struct drm_device *dev,
1216 struct drm_i915_private *dev_priv,
1220 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1221 notify_ring(&dev_priv->ring[RCS]);
1222 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1223 notify_ring(&dev_priv->ring[VCS]);
1226 static void snb_gt_irq_handler(struct drm_device *dev,
1227 struct drm_i915_private *dev_priv,
1232 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1233 notify_ring(&dev_priv->ring[RCS]);
1234 if (gt_iir & GT_BSD_USER_INTERRUPT)
1235 notify_ring(&dev_priv->ring[VCS]);
1236 if (gt_iir & GT_BLT_USER_INTERRUPT)
1237 notify_ring(&dev_priv->ring[BCS]);
1239 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1240 GT_BSD_CS_ERROR_INTERRUPT |
1241 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1242 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1244 if (gt_iir & GT_PARITY_ERROR(dev))
1245 ivybridge_parity_error_irq_handler(dev, gt_iir);
1248 static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1251 irqreturn_t ret = IRQ_NONE;
1253 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1254 u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
1256 I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
1259 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1260 intel_lrc_irq_handler(&dev_priv->ring[RCS]);
1261 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1262 notify_ring(&dev_priv->ring[RCS]);
1264 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1265 intel_lrc_irq_handler(&dev_priv->ring[BCS]);
1266 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1267 notify_ring(&dev_priv->ring[BCS]);
1269 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1272 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1273 u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
1275 I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
1278 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1279 intel_lrc_irq_handler(&dev_priv->ring[VCS]);
1280 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1281 notify_ring(&dev_priv->ring[VCS]);
1283 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1284 intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
1285 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1286 notify_ring(&dev_priv->ring[VCS2]);
1288 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1291 if (master_ctl & GEN8_GT_VECS_IRQ) {
1292 u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
1294 I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
1297 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1298 intel_lrc_irq_handler(&dev_priv->ring[VECS]);
1299 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1300 notify_ring(&dev_priv->ring[VECS]);
1302 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1305 if (master_ctl & GEN8_GT_PM_IRQ) {
1306 u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
1307 if (tmp & dev_priv->pm_rps_events) {
1308 I915_WRITE_FW(GEN8_GT_IIR(2),
1309 tmp & dev_priv->pm_rps_events);
1311 gen6_rps_irq_handler(dev_priv, tmp);
1313 DRM_ERROR("The master control interrupt lied (PM)!\n");
1319 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1323 return val & PORTA_HOTPLUG_LONG_DETECT;
1325 return val & PORTB_HOTPLUG_LONG_DETECT;
1327 return val & PORTC_HOTPLUG_LONG_DETECT;
1333 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1337 return val & PORTE_HOTPLUG_LONG_DETECT;
1343 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1347 return val & PORTA_HOTPLUG_LONG_DETECT;
1349 return val & PORTB_HOTPLUG_LONG_DETECT;
1351 return val & PORTC_HOTPLUG_LONG_DETECT;
1353 return val & PORTD_HOTPLUG_LONG_DETECT;
1359 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1363 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1369 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1373 return val & PORTB_HOTPLUG_LONG_DETECT;
1375 return val & PORTC_HOTPLUG_LONG_DETECT;
1377 return val & PORTD_HOTPLUG_LONG_DETECT;
1383 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1387 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1389 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1391 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1398 * Get a bit mask of pins that have triggered, and which ones may be long.
1399 * This can be called multiple times with the same masks to accumulate
1400 * hotplug detection results from several registers.
1402 * Note that the caller is expected to zero out the masks initially.
1404 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1405 u32 hotplug_trigger, u32 dig_hotplug_reg,
1406 const u32 hpd[HPD_NUM_PINS],
1407 bool long_pulse_detect(enum port port, u32 val))
1412 for_each_hpd_pin(i) {
1413 if ((hpd[i] & hotplug_trigger) == 0)
1416 *pin_mask |= BIT(i);
1418 if (!intel_hpd_pin_to_port(i, &port))
1421 if (long_pulse_detect(port, dig_hotplug_reg))
1422 *long_mask |= BIT(i);
1425 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1426 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1430 static void gmbus_irq_handler(struct drm_device *dev)
1432 struct drm_i915_private *dev_priv = dev->dev_private;
1434 wake_up_all(&dev_priv->gmbus_wait_queue);
1437 static void dp_aux_irq_handler(struct drm_device *dev)
1439 struct drm_i915_private *dev_priv = dev->dev_private;
1441 wake_up_all(&dev_priv->gmbus_wait_queue);
1444 #if defined(CONFIG_DEBUG_FS)
1445 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1446 uint32_t crc0, uint32_t crc1,
1447 uint32_t crc2, uint32_t crc3,
1450 struct drm_i915_private *dev_priv = dev->dev_private;
1451 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1452 struct intel_pipe_crc_entry *entry;
1455 spin_lock(&pipe_crc->lock);
1457 if (!pipe_crc->entries) {
1458 spin_unlock(&pipe_crc->lock);
1459 DRM_DEBUG_KMS("spurious interrupt\n");
1463 head = pipe_crc->head;
1464 tail = pipe_crc->tail;
1466 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1467 spin_unlock(&pipe_crc->lock);
1468 DRM_ERROR("CRC buffer overflowing\n");
1472 entry = &pipe_crc->entries[head];
1474 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1475 entry->crc[0] = crc0;
1476 entry->crc[1] = crc1;
1477 entry->crc[2] = crc2;
1478 entry->crc[3] = crc3;
1479 entry->crc[4] = crc4;
1481 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1482 pipe_crc->head = head;
1484 spin_unlock(&pipe_crc->lock);
1486 wake_up_interruptible(&pipe_crc->wq);
1490 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1491 uint32_t crc0, uint32_t crc1,
1492 uint32_t crc2, uint32_t crc3,
1497 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1501 display_pipe_crc_irq_handler(dev, pipe,
1502 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1506 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1508 struct drm_i915_private *dev_priv = dev->dev_private;
1510 display_pipe_crc_irq_handler(dev, pipe,
1511 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1512 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1513 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1514 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1515 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1518 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1520 struct drm_i915_private *dev_priv = dev->dev_private;
1521 uint32_t res1, res2;
1523 if (INTEL_INFO(dev)->gen >= 3)
1524 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1528 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1529 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1533 display_pipe_crc_irq_handler(dev, pipe,
1534 I915_READ(PIPE_CRC_RES_RED(pipe)),
1535 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1536 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1540 /* The RPS events need forcewake, so we add them to a work queue and mask their
1541 * IMR bits until the work is done. Other interrupts can be processed without
1542 * the work queue. */
1543 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1545 if (pm_iir & dev_priv->pm_rps_events) {
1546 spin_lock(&dev_priv->irq_lock);
1547 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1548 if (dev_priv->rps.interrupts_enabled) {
1549 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1550 queue_work(dev_priv->wq, &dev_priv->rps.work);
1552 spin_unlock(&dev_priv->irq_lock);
1555 if (INTEL_INFO(dev_priv)->gen >= 8)
1558 if (HAS_VEBOX(dev_priv->dev)) {
1559 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1560 notify_ring(&dev_priv->ring[VECS]);
1562 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1563 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1567 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1569 if (!drm_handle_vblank(dev, pipe))
1575 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1578 u32 pipe_stats[I915_MAX_PIPES] = { };
1581 spin_lock(&dev_priv->irq_lock);
1582 for_each_pipe(dev_priv, pipe) {
1584 u32 mask, iir_bit = 0;
1587 * PIPESTAT bits get signalled even when the interrupt is
1588 * disabled with the mask bits, and some of the status bits do
1589 * not generate interrupts at all (like the underrun bit). Hence
1590 * we need to be careful that we only handle what we want to
1594 /* fifo underruns are filterered in the underrun handler. */
1595 mask = PIPE_FIFO_UNDERRUN_STATUS;
1599 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1602 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1605 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1609 mask |= dev_priv->pipestat_irq_mask[pipe];
1614 reg = PIPESTAT(pipe);
1615 mask |= PIPESTAT_INT_ENABLE_MASK;
1616 pipe_stats[pipe] = I915_READ(reg) & mask;
1619 * Clear the PIPE*STAT regs before the IIR
1621 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1622 PIPESTAT_INT_STATUS_MASK))
1623 I915_WRITE(reg, pipe_stats[pipe]);
1625 spin_unlock(&dev_priv->irq_lock);
1627 for_each_pipe(dev_priv, pipe) {
1628 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1629 intel_pipe_handle_vblank(dev, pipe))
1630 intel_check_page_flip(dev, pipe);
1632 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1633 intel_prepare_page_flip(dev, pipe);
1634 intel_finish_page_flip(dev, pipe);
1637 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1638 i9xx_pipe_crc_irq_handler(dev, pipe);
1640 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1641 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1644 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1645 gmbus_irq_handler(dev);
1648 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1652 u32 pin_mask = 0, long_mask = 0;
1654 if (!hotplug_status)
1657 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1659 * Make sure hotplug status is cleared before we clear IIR, or else we
1660 * may miss hotplug events.
1662 POSTING_READ(PORT_HOTPLUG_STAT);
1664 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
1665 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1667 if (hotplug_trigger) {
1668 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1669 hotplug_trigger, hpd_status_g4x,
1670 i9xx_port_hotplug_long_detect);
1672 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1675 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1676 dp_aux_irq_handler(dev);
1678 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1680 if (hotplug_trigger) {
1681 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1682 hotplug_trigger, hpd_status_i915,
1683 i9xx_port_hotplug_long_detect);
1685 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1690 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1692 struct drm_device *dev = arg;
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1694 u32 iir, gt_iir, pm_iir;
1695 irqreturn_t ret = IRQ_NONE;
1697 if (!intel_irqs_enabled(dev_priv))
1701 /* Find, clear, then process each source of interrupt */
1703 gt_iir = I915_READ(GTIIR);
1705 I915_WRITE(GTIIR, gt_iir);
1707 pm_iir = I915_READ(GEN6_PMIIR);
1709 I915_WRITE(GEN6_PMIIR, pm_iir);
1711 iir = I915_READ(VLV_IIR);
1713 /* Consume port before clearing IIR or we'll miss events */
1714 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1715 i9xx_hpd_irq_handler(dev);
1716 I915_WRITE(VLV_IIR, iir);
1719 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1725 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1727 gen6_rps_irq_handler(dev_priv, pm_iir);
1728 /* Call regardless, as some status bits might not be
1729 * signalled in iir */
1730 valleyview_pipestat_irq_handler(dev, iir);
1737 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1739 struct drm_device *dev = arg;
1740 struct drm_i915_private *dev_priv = dev->dev_private;
1741 u32 master_ctl, iir;
1742 irqreturn_t ret = IRQ_NONE;
1744 if (!intel_irqs_enabled(dev_priv))
1748 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1749 iir = I915_READ(VLV_IIR);
1751 if (master_ctl == 0 && iir == 0)
1756 I915_WRITE(GEN8_MASTER_IRQ, 0);
1758 /* Find, clear, then process each source of interrupt */
1761 /* Consume port before clearing IIR or we'll miss events */
1762 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1763 i9xx_hpd_irq_handler(dev);
1764 I915_WRITE(VLV_IIR, iir);
1767 gen8_gt_irq_handler(dev_priv, master_ctl);
1769 /* Call regardless, as some status bits might not be
1770 * signalled in iir */
1771 valleyview_pipestat_irq_handler(dev, iir);
1773 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1774 POSTING_READ(GEN8_MASTER_IRQ);
1780 static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
1781 const u32 hpd[HPD_NUM_PINS])
1783 struct drm_i915_private *dev_priv = to_i915(dev);
1784 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1786 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1787 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1789 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1790 dig_hotplug_reg, hpd,
1791 pch_port_hotplug_long_detect);
1793 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1796 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1798 struct drm_i915_private *dev_priv = dev->dev_private;
1800 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1802 if (hotplug_trigger)
1803 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1805 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1806 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1807 SDE_AUDIO_POWER_SHIFT);
1808 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1812 if (pch_iir & SDE_AUX_MASK)
1813 dp_aux_irq_handler(dev);
1815 if (pch_iir & SDE_GMBUS)
1816 gmbus_irq_handler(dev);
1818 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1819 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1821 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1822 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1824 if (pch_iir & SDE_POISON)
1825 DRM_ERROR("PCH poison interrupt\n");
1827 if (pch_iir & SDE_FDI_MASK)
1828 for_each_pipe(dev_priv, pipe)
1829 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1831 I915_READ(FDI_RX_IIR(pipe)));
1833 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1834 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1836 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1837 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1839 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1840 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1842 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1843 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1846 static void ivb_err_int_handler(struct drm_device *dev)
1848 struct drm_i915_private *dev_priv = dev->dev_private;
1849 u32 err_int = I915_READ(GEN7_ERR_INT);
1852 if (err_int & ERR_INT_POISON)
1853 DRM_ERROR("Poison interrupt\n");
1855 for_each_pipe(dev_priv, pipe) {
1856 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1857 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1859 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1860 if (IS_IVYBRIDGE(dev))
1861 ivb_pipe_crc_irq_handler(dev, pipe);
1863 hsw_pipe_crc_irq_handler(dev, pipe);
1867 I915_WRITE(GEN7_ERR_INT, err_int);
1870 static void cpt_serr_int_handler(struct drm_device *dev)
1872 struct drm_i915_private *dev_priv = dev->dev_private;
1873 u32 serr_int = I915_READ(SERR_INT);
1875 if (serr_int & SERR_INT_POISON)
1876 DRM_ERROR("PCH poison interrupt\n");
1878 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1879 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1881 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1882 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1884 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1885 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
1887 I915_WRITE(SERR_INT, serr_int);
1890 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1892 struct drm_i915_private *dev_priv = dev->dev_private;
1894 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1896 if (hotplug_trigger)
1897 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1899 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1900 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1901 SDE_AUDIO_POWER_SHIFT_CPT);
1902 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1906 if (pch_iir & SDE_AUX_MASK_CPT)
1907 dp_aux_irq_handler(dev);
1909 if (pch_iir & SDE_GMBUS_CPT)
1910 gmbus_irq_handler(dev);
1912 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1913 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1915 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1916 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1918 if (pch_iir & SDE_FDI_MASK_CPT)
1919 for_each_pipe(dev_priv, pipe)
1920 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1922 I915_READ(FDI_RX_IIR(pipe)));
1924 if (pch_iir & SDE_ERROR_CPT)
1925 cpt_serr_int_handler(dev);
1928 static void spt_irq_handler(struct drm_device *dev, u32 pch_iir)
1930 struct drm_i915_private *dev_priv = dev->dev_private;
1931 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1932 ~SDE_PORTE_HOTPLUG_SPT;
1933 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1934 u32 pin_mask = 0, long_mask = 0;
1936 if (hotplug_trigger) {
1937 u32 dig_hotplug_reg;
1939 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1940 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1942 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1943 dig_hotplug_reg, hpd_spt,
1944 spt_port_hotplug_long_detect);
1947 if (hotplug2_trigger) {
1948 u32 dig_hotplug_reg;
1950 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
1951 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
1953 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
1954 dig_hotplug_reg, hpd_spt,
1955 spt_port_hotplug2_long_detect);
1959 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1961 if (pch_iir & SDE_GMBUS_CPT)
1962 gmbus_irq_handler(dev);
1965 static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
1966 const u32 hpd[HPD_NUM_PINS])
1968 struct drm_i915_private *dev_priv = to_i915(dev);
1969 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1971 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
1972 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
1974 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1975 dig_hotplug_reg, hpd,
1976 ilk_port_hotplug_long_detect);
1978 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1981 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1983 struct drm_i915_private *dev_priv = dev->dev_private;
1985 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
1987 if (hotplug_trigger)
1988 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk);
1990 if (de_iir & DE_AUX_CHANNEL_A)
1991 dp_aux_irq_handler(dev);
1993 if (de_iir & DE_GSE)
1994 intel_opregion_asle_intr(dev);
1996 if (de_iir & DE_POISON)
1997 DRM_ERROR("Poison interrupt\n");
1999 for_each_pipe(dev_priv, pipe) {
2000 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2001 intel_pipe_handle_vblank(dev, pipe))
2002 intel_check_page_flip(dev, pipe);
2004 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2005 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2007 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2008 i9xx_pipe_crc_irq_handler(dev, pipe);
2010 /* plane/pipes map 1:1 on ilk+ */
2011 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2012 intel_prepare_page_flip(dev, pipe);
2013 intel_finish_page_flip_plane(dev, pipe);
2017 /* check event from PCH */
2018 if (de_iir & DE_PCH_EVENT) {
2019 u32 pch_iir = I915_READ(SDEIIR);
2021 if (HAS_PCH_CPT(dev))
2022 cpt_irq_handler(dev, pch_iir);
2024 ibx_irq_handler(dev, pch_iir);
2026 /* should clear PCH hotplug event before clear CPU irq */
2027 I915_WRITE(SDEIIR, pch_iir);
2030 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2031 ironlake_rps_change_irq_handler(dev);
2034 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2036 struct drm_i915_private *dev_priv = dev->dev_private;
2038 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2040 if (hotplug_trigger)
2041 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb);
2043 if (de_iir & DE_ERR_INT_IVB)
2044 ivb_err_int_handler(dev);
2046 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2047 dp_aux_irq_handler(dev);
2049 if (de_iir & DE_GSE_IVB)
2050 intel_opregion_asle_intr(dev);
2052 for_each_pipe(dev_priv, pipe) {
2053 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2054 intel_pipe_handle_vblank(dev, pipe))
2055 intel_check_page_flip(dev, pipe);
2057 /* plane/pipes map 1:1 on ilk+ */
2058 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2059 intel_prepare_page_flip(dev, pipe);
2060 intel_finish_page_flip_plane(dev, pipe);
2064 /* check event from PCH */
2065 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2066 u32 pch_iir = I915_READ(SDEIIR);
2068 cpt_irq_handler(dev, pch_iir);
2070 /* clear PCH hotplug event before clear CPU irq */
2071 I915_WRITE(SDEIIR, pch_iir);
2076 * To handle irqs with the minimum potential races with fresh interrupts, we:
2077 * 1 - Disable Master Interrupt Control.
2078 * 2 - Find the source(s) of the interrupt.
2079 * 3 - Clear the Interrupt Identity bits (IIR).
2080 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2081 * 5 - Re-enable Master Interrupt Control.
2083 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2085 struct drm_device *dev = arg;
2086 struct drm_i915_private *dev_priv = dev->dev_private;
2087 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2088 irqreturn_t ret = IRQ_NONE;
2090 if (!intel_irqs_enabled(dev_priv))
2093 /* We get interrupts on unclaimed registers, so check for this before we
2094 * do any I915_{READ,WRITE}. */
2095 intel_uncore_check_errors(dev);
2097 /* disable master interrupt before clearing iir */
2098 de_ier = I915_READ(DEIER);
2099 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2100 POSTING_READ(DEIER);
2102 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2103 * interrupts will will be stored on its back queue, and then we'll be
2104 * able to process them after we restore SDEIER (as soon as we restore
2105 * it, we'll get an interrupt if SDEIIR still has something to process
2106 * due to its back queue). */
2107 if (!HAS_PCH_NOP(dev)) {
2108 sde_ier = I915_READ(SDEIER);
2109 I915_WRITE(SDEIER, 0);
2110 POSTING_READ(SDEIER);
2113 /* Find, clear, then process each source of interrupt */
2115 gt_iir = I915_READ(GTIIR);
2117 I915_WRITE(GTIIR, gt_iir);
2119 if (INTEL_INFO(dev)->gen >= 6)
2120 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2122 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2125 de_iir = I915_READ(DEIIR);
2127 I915_WRITE(DEIIR, de_iir);
2129 if (INTEL_INFO(dev)->gen >= 7)
2130 ivb_display_irq_handler(dev, de_iir);
2132 ilk_display_irq_handler(dev, de_iir);
2135 if (INTEL_INFO(dev)->gen >= 6) {
2136 u32 pm_iir = I915_READ(GEN6_PMIIR);
2138 I915_WRITE(GEN6_PMIIR, pm_iir);
2140 gen6_rps_irq_handler(dev_priv, pm_iir);
2144 I915_WRITE(DEIER, de_ier);
2145 POSTING_READ(DEIER);
2146 if (!HAS_PCH_NOP(dev)) {
2147 I915_WRITE(SDEIER, sde_ier);
2148 POSTING_READ(SDEIER);
2154 static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2155 const u32 hpd[HPD_NUM_PINS])
2157 struct drm_i915_private *dev_priv = to_i915(dev);
2158 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2160 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2161 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2163 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2164 dig_hotplug_reg, hpd,
2165 bxt_port_hotplug_long_detect);
2167 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2170 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2172 struct drm_device *dev = arg;
2173 struct drm_i915_private *dev_priv = dev->dev_private;
2175 irqreturn_t ret = IRQ_NONE;
2178 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2180 if (!intel_irqs_enabled(dev_priv))
2183 if (INTEL_INFO(dev_priv)->gen >= 9)
2184 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2187 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2188 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2192 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2194 /* Find, clear, then process each source of interrupt */
2196 ret = gen8_gt_irq_handler(dev_priv, master_ctl);
2198 if (master_ctl & GEN8_DE_MISC_IRQ) {
2199 tmp = I915_READ(GEN8_DE_MISC_IIR);
2201 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2203 if (tmp & GEN8_DE_MISC_GSE)
2204 intel_opregion_asle_intr(dev);
2206 DRM_ERROR("Unexpected DE Misc interrupt\n");
2209 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2212 if (master_ctl & GEN8_DE_PORT_IRQ) {
2213 tmp = I915_READ(GEN8_DE_PORT_IIR);
2216 u32 hotplug_trigger = 0;
2218 if (IS_BROXTON(dev_priv))
2219 hotplug_trigger = tmp & BXT_DE_PORT_HOTPLUG_MASK;
2220 else if (IS_BROADWELL(dev_priv))
2221 hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG;
2223 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2226 if (tmp & aux_mask) {
2227 dp_aux_irq_handler(dev);
2231 if (hotplug_trigger) {
2232 if (IS_BROXTON(dev))
2233 bxt_hpd_irq_handler(dev, hotplug_trigger, hpd_bxt);
2235 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_bdw);
2239 if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
2240 gmbus_irq_handler(dev);
2245 DRM_ERROR("Unexpected DE Port interrupt\n");
2248 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2251 for_each_pipe(dev_priv, pipe) {
2252 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2254 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2257 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2260 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2262 if (pipe_iir & GEN8_PIPE_VBLANK &&
2263 intel_pipe_handle_vblank(dev, pipe))
2264 intel_check_page_flip(dev, pipe);
2266 if (INTEL_INFO(dev_priv)->gen >= 9)
2267 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2269 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2272 intel_prepare_page_flip(dev, pipe);
2273 intel_finish_page_flip_plane(dev, pipe);
2276 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2277 hsw_pipe_crc_irq_handler(dev, pipe);
2279 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2280 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2284 if (INTEL_INFO(dev_priv)->gen >= 9)
2285 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2287 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2290 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2292 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2294 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2297 if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
2298 master_ctl & GEN8_DE_PCH_IRQ) {
2300 * FIXME(BDW): Assume for now that the new interrupt handling
2301 * scheme also closed the SDE interrupt handling race we've seen
2302 * on older pch-split platforms. But this needs testing.
2304 u32 pch_iir = I915_READ(SDEIIR);
2306 I915_WRITE(SDEIIR, pch_iir);
2309 if (HAS_PCH_SPT(dev_priv))
2310 spt_irq_handler(dev, pch_iir);
2312 cpt_irq_handler(dev, pch_iir);
2314 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2318 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2319 POSTING_READ_FW(GEN8_MASTER_IRQ);
2324 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2325 bool reset_completed)
2327 struct intel_engine_cs *ring;
2331 * Notify all waiters for GPU completion events that reset state has
2332 * been changed, and that they need to restart their wait after
2333 * checking for potential errors (and bail out to drop locks if there is
2334 * a gpu reset pending so that i915_error_work_func can acquire them).
2337 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2338 for_each_ring(ring, dev_priv, i)
2339 wake_up_all(&ring->irq_queue);
2341 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2342 wake_up_all(&dev_priv->pending_flip_queue);
2345 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2346 * reset state is cleared.
2348 if (reset_completed)
2349 wake_up_all(&dev_priv->gpu_error.reset_queue);
2353 * i915_reset_and_wakeup - do process context error handling work
2355 * Fire an error uevent so userspace can see that a hang or error
2358 static void i915_reset_and_wakeup(struct drm_device *dev)
2360 struct drm_i915_private *dev_priv = to_i915(dev);
2361 struct i915_gpu_error *error = &dev_priv->gpu_error;
2362 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2363 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2364 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2367 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2370 * Note that there's only one work item which does gpu resets, so we
2371 * need not worry about concurrent gpu resets potentially incrementing
2372 * error->reset_counter twice. We only need to take care of another
2373 * racing irq/hangcheck declaring the gpu dead for a second time. A
2374 * quick check for that is good enough: schedule_work ensures the
2375 * correct ordering between hang detection and this work item, and since
2376 * the reset in-progress bit is only ever set by code outside of this
2377 * work we don't need to worry about any other races.
2379 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2380 DRM_DEBUG_DRIVER("resetting chip\n");
2381 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2385 * In most cases it's guaranteed that we get here with an RPM
2386 * reference held, for example because there is a pending GPU
2387 * request that won't finish until the reset is done. This
2388 * isn't the case at least when we get here by doing a
2389 * simulated reset via debugs, so get an RPM reference.
2391 intel_runtime_pm_get(dev_priv);
2393 intel_prepare_reset(dev);
2396 * All state reset _must_ be completed before we update the
2397 * reset counter, for otherwise waiters might miss the reset
2398 * pending state and not properly drop locks, resulting in
2399 * deadlocks with the reset work.
2401 ret = i915_reset(dev);
2403 intel_finish_reset(dev);
2405 intel_runtime_pm_put(dev_priv);
2409 * After all the gem state is reset, increment the reset
2410 * counter and wake up everyone waiting for the reset to
2413 * Since unlock operations are a one-sided barrier only,
2414 * we need to insert a barrier here to order any seqno
2416 * the counter increment.
2418 smp_mb__before_atomic();
2419 atomic_inc(&dev_priv->gpu_error.reset_counter);
2421 kobject_uevent_env(&dev->primary->kdev->kobj,
2422 KOBJ_CHANGE, reset_done_event);
2424 atomic_or(I915_WEDGED, &error->reset_counter);
2428 * Note: The wake_up also serves as a memory barrier so that
2429 * waiters see the update value of the reset counter atomic_t.
2431 i915_error_wake_up(dev_priv, true);
2435 static void i915_report_and_clear_eir(struct drm_device *dev)
2437 struct drm_i915_private *dev_priv = dev->dev_private;
2438 uint32_t instdone[I915_NUM_INSTDONE_REG];
2439 u32 eir = I915_READ(EIR);
2445 pr_err("render error detected, EIR: 0x%08x\n", eir);
2447 i915_get_extra_instdone(dev, instdone);
2450 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2451 u32 ipeir = I915_READ(IPEIR_I965);
2453 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2454 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2455 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2456 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2457 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2458 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2459 I915_WRITE(IPEIR_I965, ipeir);
2460 POSTING_READ(IPEIR_I965);
2462 if (eir & GM45_ERROR_PAGE_TABLE) {
2463 u32 pgtbl_err = I915_READ(PGTBL_ER);
2464 pr_err("page table error\n");
2465 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2466 I915_WRITE(PGTBL_ER, pgtbl_err);
2467 POSTING_READ(PGTBL_ER);
2471 if (!IS_GEN2(dev)) {
2472 if (eir & I915_ERROR_PAGE_TABLE) {
2473 u32 pgtbl_err = I915_READ(PGTBL_ER);
2474 pr_err("page table error\n");
2475 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2476 I915_WRITE(PGTBL_ER, pgtbl_err);
2477 POSTING_READ(PGTBL_ER);
2481 if (eir & I915_ERROR_MEMORY_REFRESH) {
2482 pr_err("memory refresh error:\n");
2483 for_each_pipe(dev_priv, pipe)
2484 pr_err("pipe %c stat: 0x%08x\n",
2485 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2486 /* pipestat has already been acked */
2488 if (eir & I915_ERROR_INSTRUCTION) {
2489 pr_err("instruction error\n");
2490 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2491 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2492 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2493 if (INTEL_INFO(dev)->gen < 4) {
2494 u32 ipeir = I915_READ(IPEIR);
2496 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2497 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2498 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2499 I915_WRITE(IPEIR, ipeir);
2500 POSTING_READ(IPEIR);
2502 u32 ipeir = I915_READ(IPEIR_I965);
2504 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2505 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2506 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2507 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2508 I915_WRITE(IPEIR_I965, ipeir);
2509 POSTING_READ(IPEIR_I965);
2513 I915_WRITE(EIR, eir);
2515 eir = I915_READ(EIR);
2518 * some errors might have become stuck,
2521 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2522 I915_WRITE(EMR, I915_READ(EMR) | eir);
2523 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2528 * i915_handle_error - handle a gpu error
2531 * Do some basic checking of regsiter state at error time and
2532 * dump it to the syslog. Also call i915_capture_error_state() to make
2533 * sure we get a record and make it available in debugfs. Fire a uevent
2534 * so userspace knows something bad happened (should trigger collection
2535 * of a ring dump etc.).
2537 void i915_handle_error(struct drm_device *dev, bool wedged,
2538 const char *fmt, ...)
2540 struct drm_i915_private *dev_priv = dev->dev_private;
2544 va_start(args, fmt);
2545 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2548 i915_capture_error_state(dev, wedged, error_msg);
2549 i915_report_and_clear_eir(dev);
2552 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2553 &dev_priv->gpu_error.reset_counter);
2556 * Wakeup waiting processes so that the reset function
2557 * i915_reset_and_wakeup doesn't deadlock trying to grab
2558 * various locks. By bumping the reset counter first, the woken
2559 * processes will see a reset in progress and back off,
2560 * releasing their locks and then wait for the reset completion.
2561 * We must do this for _all_ gpu waiters that might hold locks
2562 * that the reset work needs to acquire.
2564 * Note: The wake_up serves as the required memory barrier to
2565 * ensure that the waiters see the updated value of the reset
2568 i915_error_wake_up(dev_priv, false);
2571 i915_reset_and_wakeup(dev);
2574 /* Called from drm generic code, passed 'crtc' which
2575 * we use as a pipe index
2577 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580 unsigned long irqflags;
2582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2583 if (INTEL_INFO(dev)->gen >= 4)
2584 i915_enable_pipestat(dev_priv, pipe,
2585 PIPE_START_VBLANK_INTERRUPT_STATUS);
2587 i915_enable_pipestat(dev_priv, pipe,
2588 PIPE_VBLANK_INTERRUPT_STATUS);
2589 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2594 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2596 struct drm_i915_private *dev_priv = dev->dev_private;
2597 unsigned long irqflags;
2598 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2599 DE_PIPE_VBLANK(pipe);
2601 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2602 ironlake_enable_display_irq(dev_priv, bit);
2603 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2608 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2610 struct drm_i915_private *dev_priv = dev->dev_private;
2611 unsigned long irqflags;
2613 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2614 i915_enable_pipestat(dev_priv, pipe,
2615 PIPE_START_VBLANK_INTERRUPT_STATUS);
2616 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2621 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2623 struct drm_i915_private *dev_priv = dev->dev_private;
2624 unsigned long irqflags;
2626 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2627 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2628 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2629 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2630 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2634 /* Called from drm generic code, passed 'crtc' which
2635 * we use as a pipe index
2637 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2639 struct drm_i915_private *dev_priv = dev->dev_private;
2640 unsigned long irqflags;
2642 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2643 i915_disable_pipestat(dev_priv, pipe,
2644 PIPE_VBLANK_INTERRUPT_STATUS |
2645 PIPE_START_VBLANK_INTERRUPT_STATUS);
2646 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2649 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2651 struct drm_i915_private *dev_priv = dev->dev_private;
2652 unsigned long irqflags;
2653 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2654 DE_PIPE_VBLANK(pipe);
2656 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2657 ironlake_disable_display_irq(dev_priv, bit);
2658 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2661 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664 unsigned long irqflags;
2666 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2667 i915_disable_pipestat(dev_priv, pipe,
2668 PIPE_START_VBLANK_INTERRUPT_STATUS);
2669 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2672 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2674 struct drm_i915_private *dev_priv = dev->dev_private;
2675 unsigned long irqflags;
2677 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2678 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2679 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2680 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2681 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2685 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2687 return (list_empty(&ring->request_list) ||
2688 i915_seqno_passed(seqno, ring->last_submitted_seqno));
2692 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2694 if (INTEL_INFO(dev)->gen >= 8) {
2695 return (ipehr >> 23) == 0x1c;
2697 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2698 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2699 MI_SEMAPHORE_REGISTER);
2703 static struct intel_engine_cs *
2704 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2706 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2707 struct intel_engine_cs *signaller;
2710 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2711 for_each_ring(signaller, dev_priv, i) {
2712 if (ring == signaller)
2715 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2719 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2721 for_each_ring(signaller, dev_priv, i) {
2722 if(ring == signaller)
2725 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2730 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2731 ring->id, ipehr, offset);
2736 static struct intel_engine_cs *
2737 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2739 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2740 u32 cmd, ipehr, head;
2744 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2745 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2749 * HEAD is likely pointing to the dword after the actual command,
2750 * so scan backwards until we find the MBOX. But limit it to just 3
2751 * or 4 dwords depending on the semaphore wait command size.
2752 * Note that we don't care about ACTHD here since that might
2753 * point at at batch, and semaphores are always emitted into the
2754 * ringbuffer itself.
2756 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2757 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2759 for (i = backwards; i; --i) {
2761 * Be paranoid and presume the hw has gone off into the wild -
2762 * our ring is smaller than what the hardware (and hence
2763 * HEAD_ADDR) allows. Also handles wrap-around.
2765 head &= ring->buffer->size - 1;
2767 /* This here seems to blow up */
2768 cmd = ioread32(ring->buffer->virtual_start + head);
2778 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2779 if (INTEL_INFO(ring->dev)->gen >= 8) {
2780 offset = ioread32(ring->buffer->virtual_start + head + 12);
2782 offset = ioread32(ring->buffer->virtual_start + head + 8);
2784 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2787 static int semaphore_passed(struct intel_engine_cs *ring)
2789 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2790 struct intel_engine_cs *signaller;
2793 ring->hangcheck.deadlock++;
2795 signaller = semaphore_waits_for(ring, &seqno);
2796 if (signaller == NULL)
2799 /* Prevent pathological recursion due to driver bugs */
2800 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2803 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2806 /* cursory check for an unkickable deadlock */
2807 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2808 semaphore_passed(signaller) < 0)
2814 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2816 struct intel_engine_cs *ring;
2819 for_each_ring(ring, dev_priv, i)
2820 ring->hangcheck.deadlock = 0;
2823 static enum intel_ring_hangcheck_action
2824 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2826 struct drm_device *dev = ring->dev;
2827 struct drm_i915_private *dev_priv = dev->dev_private;
2830 if (acthd != ring->hangcheck.acthd) {
2831 if (acthd > ring->hangcheck.max_acthd) {
2832 ring->hangcheck.max_acthd = acthd;
2833 return HANGCHECK_ACTIVE;
2836 return HANGCHECK_ACTIVE_LOOP;
2840 return HANGCHECK_HUNG;
2842 /* Is the chip hanging on a WAIT_FOR_EVENT?
2843 * If so we can simply poke the RB_WAIT bit
2844 * and break the hang. This should work on
2845 * all but the second generation chipsets.
2847 tmp = I915_READ_CTL(ring);
2848 if (tmp & RING_WAIT) {
2849 i915_handle_error(dev, false,
2850 "Kicking stuck wait on %s",
2852 I915_WRITE_CTL(ring, tmp);
2853 return HANGCHECK_KICK;
2856 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2857 switch (semaphore_passed(ring)) {
2859 return HANGCHECK_HUNG;
2861 i915_handle_error(dev, false,
2862 "Kicking stuck semaphore on %s",
2864 I915_WRITE_CTL(ring, tmp);
2865 return HANGCHECK_KICK;
2867 return HANGCHECK_WAIT;
2871 return HANGCHECK_HUNG;
2875 * This is called when the chip hasn't reported back with completed
2876 * batchbuffers in a long time. We keep track per ring seqno progress and
2877 * if there are no progress, hangcheck score for that ring is increased.
2878 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2879 * we kick the ring. If we see no progress on three subsequent calls
2880 * we assume chip is wedged and try to fix it by resetting the chip.
2882 static void i915_hangcheck_elapsed(struct work_struct *work)
2884 struct drm_i915_private *dev_priv =
2885 container_of(work, typeof(*dev_priv),
2886 gpu_error.hangcheck_work.work);
2887 struct drm_device *dev = dev_priv->dev;
2888 struct intel_engine_cs *ring;
2890 int busy_count = 0, rings_hung = 0;
2891 bool stuck[I915_NUM_RINGS] = { 0 };
2896 if (!i915.enable_hangcheck)
2899 for_each_ring(ring, dev_priv, i) {
2904 semaphore_clear_deadlocks(dev_priv);
2906 seqno = ring->get_seqno(ring, false);
2907 acthd = intel_ring_get_active_head(ring);
2909 if (ring->hangcheck.seqno == seqno) {
2910 if (ring_idle(ring, seqno)) {
2911 ring->hangcheck.action = HANGCHECK_IDLE;
2913 if (waitqueue_active(&ring->irq_queue)) {
2914 /* Issue a wake-up to catch stuck h/w. */
2915 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2916 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2917 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2920 DRM_INFO("Fake missed irq on %s\n",
2922 wake_up_all(&ring->irq_queue);
2924 /* Safeguard against driver failure */
2925 ring->hangcheck.score += BUSY;
2929 /* We always increment the hangcheck score
2930 * if the ring is busy and still processing
2931 * the same request, so that no single request
2932 * can run indefinitely (such as a chain of
2933 * batches). The only time we do not increment
2934 * the hangcheck score on this ring, if this
2935 * ring is in a legitimate wait for another
2936 * ring. In that case the waiting ring is a
2937 * victim and we want to be sure we catch the
2938 * right culprit. Then every time we do kick
2939 * the ring, add a small increment to the
2940 * score so that we can catch a batch that is
2941 * being repeatedly kicked and so responsible
2942 * for stalling the machine.
2944 ring->hangcheck.action = ring_stuck(ring,
2947 switch (ring->hangcheck.action) {
2948 case HANGCHECK_IDLE:
2949 case HANGCHECK_WAIT:
2950 case HANGCHECK_ACTIVE:
2952 case HANGCHECK_ACTIVE_LOOP:
2953 ring->hangcheck.score += BUSY;
2955 case HANGCHECK_KICK:
2956 ring->hangcheck.score += KICK;
2958 case HANGCHECK_HUNG:
2959 ring->hangcheck.score += HUNG;
2965 ring->hangcheck.action = HANGCHECK_ACTIVE;
2967 /* Gradually reduce the count so that we catch DoS
2968 * attempts across multiple batches.
2970 if (ring->hangcheck.score > 0)
2971 ring->hangcheck.score--;
2973 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
2976 ring->hangcheck.seqno = seqno;
2977 ring->hangcheck.acthd = acthd;
2981 for_each_ring(ring, dev_priv, i) {
2982 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2983 DRM_INFO("%s on %s\n",
2984 stuck[i] ? "stuck" : "no progress",
2991 return i915_handle_error(dev, true, "Ring hung");
2994 /* Reset timer case chip hangs without another request
2996 i915_queue_hangcheck(dev);
2999 void i915_queue_hangcheck(struct drm_device *dev)
3001 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
3003 if (!i915.enable_hangcheck)
3006 /* Don't continually defer the hangcheck so that it is always run at
3007 * least once after work has been scheduled on any ring. Otherwise,
3008 * we will ignore a hung ring if a second ring is kept busy.
3011 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3012 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3015 static void ibx_irq_reset(struct drm_device *dev)
3017 struct drm_i915_private *dev_priv = dev->dev_private;
3019 if (HAS_PCH_NOP(dev))
3022 GEN5_IRQ_RESET(SDE);
3024 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3025 I915_WRITE(SERR_INT, 0xffffffff);
3029 * SDEIER is also touched by the interrupt handler to work around missed PCH
3030 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3031 * instead we unconditionally enable all PCH interrupt sources here, but then
3032 * only unmask them as needed with SDEIMR.
3034 * This function needs to be called before interrupts are enabled.
3036 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3038 struct drm_i915_private *dev_priv = dev->dev_private;
3040 if (HAS_PCH_NOP(dev))
3043 WARN_ON(I915_READ(SDEIER) != 0);
3044 I915_WRITE(SDEIER, 0xffffffff);
3045 POSTING_READ(SDEIER);
3048 static void gen5_gt_irq_reset(struct drm_device *dev)
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3053 if (INTEL_INFO(dev)->gen >= 6)
3054 GEN5_IRQ_RESET(GEN6_PM);
3059 static void ironlake_irq_reset(struct drm_device *dev)
3061 struct drm_i915_private *dev_priv = dev->dev_private;
3063 I915_WRITE(HWSTAM, 0xffffffff);
3067 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3069 gen5_gt_irq_reset(dev);
3074 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3078 I915_WRITE(PORT_HOTPLUG_EN, 0);
3079 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3081 for_each_pipe(dev_priv, pipe)
3082 I915_WRITE(PIPESTAT(pipe), 0xffff);
3084 GEN5_IRQ_RESET(VLV_);
3087 static void valleyview_irq_preinstall(struct drm_device *dev)
3089 struct drm_i915_private *dev_priv = dev->dev_private;
3092 I915_WRITE(VLV_IMR, 0);
3093 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3094 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3095 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3097 gen5_gt_irq_reset(dev);
3099 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3101 vlv_display_irq_reset(dev_priv);
3104 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3106 GEN8_IRQ_RESET_NDX(GT, 0);
3107 GEN8_IRQ_RESET_NDX(GT, 1);
3108 GEN8_IRQ_RESET_NDX(GT, 2);
3109 GEN8_IRQ_RESET_NDX(GT, 3);
3112 static void gen8_irq_reset(struct drm_device *dev)
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3117 I915_WRITE(GEN8_MASTER_IRQ, 0);
3118 POSTING_READ(GEN8_MASTER_IRQ);
3120 gen8_gt_irq_reset(dev_priv);
3122 for_each_pipe(dev_priv, pipe)
3123 if (intel_display_power_is_enabled(dev_priv,
3124 POWER_DOMAIN_PIPE(pipe)))
3125 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3127 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3128 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3129 GEN5_IRQ_RESET(GEN8_PCU_);
3131 if (HAS_PCH_SPLIT(dev))
3135 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3136 unsigned int pipe_mask)
3138 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3140 spin_lock_irq(&dev_priv->irq_lock);
3141 if (pipe_mask & 1 << PIPE_A)
3142 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
3143 dev_priv->de_irq_mask[PIPE_A],
3144 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
3145 if (pipe_mask & 1 << PIPE_B)
3146 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
3147 dev_priv->de_irq_mask[PIPE_B],
3148 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3149 if (pipe_mask & 1 << PIPE_C)
3150 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
3151 dev_priv->de_irq_mask[PIPE_C],
3152 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3153 spin_unlock_irq(&dev_priv->irq_lock);
3156 static void cherryview_irq_preinstall(struct drm_device *dev)
3158 struct drm_i915_private *dev_priv = dev->dev_private;
3160 I915_WRITE(GEN8_MASTER_IRQ, 0);
3161 POSTING_READ(GEN8_MASTER_IRQ);
3163 gen8_gt_irq_reset(dev_priv);
3165 GEN5_IRQ_RESET(GEN8_PCU_);
3167 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3169 vlv_display_irq_reset(dev_priv);
3172 static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
3173 const u32 hpd[HPD_NUM_PINS])
3175 struct drm_i915_private *dev_priv = to_i915(dev);
3176 struct intel_encoder *encoder;
3177 u32 enabled_irqs = 0;
3179 for_each_intel_encoder(dev, encoder)
3180 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3181 enabled_irqs |= hpd[encoder->hpd_pin];
3183 return enabled_irqs;
3186 static void ibx_hpd_irq_setup(struct drm_device *dev)
3188 struct drm_i915_private *dev_priv = dev->dev_private;
3189 u32 hotplug_irqs, hotplug, enabled_irqs;
3191 if (HAS_PCH_IBX(dev)) {
3192 hotplug_irqs = SDE_HOTPLUG_MASK;
3193 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx);
3195 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3196 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt);
3199 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3202 * Enable digital hotplug on the PCH, and configure the DP short pulse
3203 * duration to 2ms (which is the minimum in the Display Port spec).
3204 * The pulse duration bits are reserved on LPT+.
3206 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3207 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3208 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3209 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3210 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3212 * When CPU and PCH are on the same package, port A
3213 * HPD must be enabled in both north and south.
3215 if (HAS_PCH_LPT_LP(dev))
3216 hotplug |= PORTA_HOTPLUG_ENABLE;
3217 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3220 static void spt_hpd_irq_setup(struct drm_device *dev)
3222 struct drm_i915_private *dev_priv = dev->dev_private;
3223 u32 hotplug_irqs, hotplug, enabled_irqs;
3225 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3226 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt);
3228 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3230 /* Enable digital hotplug on the PCH */
3231 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3232 hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3233 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3234 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3236 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3237 hotplug |= PORTE_HOTPLUG_ENABLE;
3238 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3241 static void ilk_hpd_irq_setup(struct drm_device *dev)
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244 u32 hotplug_irqs, hotplug, enabled_irqs;
3246 if (INTEL_INFO(dev)->gen >= 8) {
3247 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3248 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw);
3250 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3251 } else if (INTEL_INFO(dev)->gen >= 7) {
3252 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3253 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb);
3255 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3257 hotplug_irqs = DE_DP_A_HOTPLUG;
3258 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk);
3260 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3264 * Enable digital hotplug on the CPU, and configure the DP short pulse
3265 * duration to 2ms (which is the minimum in the Display Port spec)
3266 * The pulse duration bits are reserved on HSW+.
3268 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3269 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3270 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3271 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3273 ibx_hpd_irq_setup(dev);
3276 static void bxt_hpd_irq_setup(struct drm_device *dev)
3278 struct drm_i915_private *dev_priv = dev->dev_private;
3279 u32 hotplug_irqs, hotplug, enabled_irqs;
3281 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt);
3282 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3284 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3286 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3287 hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3288 PORTA_HOTPLUG_ENABLE;
3289 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3292 static void ibx_irq_postinstall(struct drm_device *dev)
3294 struct drm_i915_private *dev_priv = dev->dev_private;
3297 if (HAS_PCH_NOP(dev))
3300 if (HAS_PCH_IBX(dev))
3301 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3303 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3305 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3306 I915_WRITE(SDEIMR, ~mask);
3309 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3311 struct drm_i915_private *dev_priv = dev->dev_private;
3312 u32 pm_irqs, gt_irqs;
3314 pm_irqs = gt_irqs = 0;
3316 dev_priv->gt_irq_mask = ~0;
3317 if (HAS_L3_DPF(dev)) {
3318 /* L3 parity interrupt is always unmasked. */
3319 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3320 gt_irqs |= GT_PARITY_ERROR(dev);
3323 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3325 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3326 ILK_BSD_USER_INTERRUPT;
3328 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3331 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3333 if (INTEL_INFO(dev)->gen >= 6) {
3335 * RPS interrupts will get enabled/disabled on demand when RPS
3336 * itself is enabled/disabled.
3339 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3341 dev_priv->pm_irq_mask = 0xffffffff;
3342 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3346 static int ironlake_irq_postinstall(struct drm_device *dev)
3348 struct drm_i915_private *dev_priv = dev->dev_private;
3349 u32 display_mask, extra_mask;
3351 if (INTEL_INFO(dev)->gen >= 7) {
3352 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3353 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3354 DE_PLANEB_FLIP_DONE_IVB |
3355 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3356 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3357 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3358 DE_DP_A_HOTPLUG_IVB);
3360 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3361 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3363 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3365 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3366 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3370 dev_priv->irq_mask = ~display_mask;
3372 I915_WRITE(HWSTAM, 0xeffe);
3374 ibx_irq_pre_postinstall(dev);
3376 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3378 gen5_gt_irq_postinstall(dev);
3380 ibx_irq_postinstall(dev);
3382 if (IS_IRONLAKE_M(dev)) {
3383 /* Enable PCU event interrupts
3385 * spinlocking not required here for correctness since interrupt
3386 * setup is guaranteed to run in single-threaded context. But we
3387 * need it to make the assert_spin_locked happy. */
3388 spin_lock_irq(&dev_priv->irq_lock);
3389 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3390 spin_unlock_irq(&dev_priv->irq_lock);
3396 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3402 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3403 PIPE_FIFO_UNDERRUN_STATUS;
3405 for_each_pipe(dev_priv, pipe)
3406 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3407 POSTING_READ(PIPESTAT(PIPE_A));
3409 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3410 PIPE_CRC_DONE_INTERRUPT_STATUS;
3412 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3413 for_each_pipe(dev_priv, pipe)
3414 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3416 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3417 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3418 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3419 if (IS_CHERRYVIEW(dev_priv))
3420 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3421 dev_priv->irq_mask &= ~iir_mask;
3423 I915_WRITE(VLV_IIR, iir_mask);
3424 I915_WRITE(VLV_IIR, iir_mask);
3425 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3426 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3427 POSTING_READ(VLV_IMR);
3430 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3436 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3437 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3438 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3439 if (IS_CHERRYVIEW(dev_priv))
3440 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3442 dev_priv->irq_mask |= iir_mask;
3443 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3444 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3445 I915_WRITE(VLV_IIR, iir_mask);
3446 I915_WRITE(VLV_IIR, iir_mask);
3447 POSTING_READ(VLV_IIR);
3449 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3450 PIPE_CRC_DONE_INTERRUPT_STATUS;
3452 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3453 for_each_pipe(dev_priv, pipe)
3454 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3456 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3457 PIPE_FIFO_UNDERRUN_STATUS;
3459 for_each_pipe(dev_priv, pipe)
3460 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3461 POSTING_READ(PIPESTAT(PIPE_A));
3464 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3466 assert_spin_locked(&dev_priv->irq_lock);
3468 if (dev_priv->display_irqs_enabled)
3471 dev_priv->display_irqs_enabled = true;
3473 if (intel_irqs_enabled(dev_priv))
3474 valleyview_display_irqs_install(dev_priv);
3477 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3479 assert_spin_locked(&dev_priv->irq_lock);
3481 if (!dev_priv->display_irqs_enabled)
3484 dev_priv->display_irqs_enabled = false;
3486 if (intel_irqs_enabled(dev_priv))
3487 valleyview_display_irqs_uninstall(dev_priv);
3490 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3492 dev_priv->irq_mask = ~0;
3494 I915_WRITE(PORT_HOTPLUG_EN, 0);
3495 POSTING_READ(PORT_HOTPLUG_EN);
3497 I915_WRITE(VLV_IIR, 0xffffffff);
3498 I915_WRITE(VLV_IIR, 0xffffffff);
3499 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3500 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3501 POSTING_READ(VLV_IMR);
3503 /* Interrupt setup is already guaranteed to be single-threaded, this is
3504 * just to make the assert_spin_locked check happy. */
3505 spin_lock_irq(&dev_priv->irq_lock);
3506 if (dev_priv->display_irqs_enabled)
3507 valleyview_display_irqs_install(dev_priv);
3508 spin_unlock_irq(&dev_priv->irq_lock);
3511 static int valleyview_irq_postinstall(struct drm_device *dev)
3513 struct drm_i915_private *dev_priv = dev->dev_private;
3515 vlv_display_irq_postinstall(dev_priv);
3517 gen5_gt_irq_postinstall(dev);
3519 /* ack & enable invalid PTE error interrupts */
3520 #if 0 /* FIXME: add support to irq handler for checking these bits */
3521 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3522 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3525 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3530 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3532 /* These are interrupts we'll toggle with the ring mask register */
3533 uint32_t gt_interrupts[] = {
3534 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3535 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3536 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3537 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3538 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3539 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3540 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3541 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3542 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3544 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3545 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3548 dev_priv->pm_irq_mask = 0xffffffff;
3549 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3550 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3552 * RPS interrupts will get enabled/disabled on demand when RPS itself
3553 * is enabled/disabled.
3555 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3556 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3559 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3561 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3562 uint32_t de_pipe_enables;
3563 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3564 u32 de_port_enables;
3567 if (INTEL_INFO(dev_priv)->gen >= 9) {
3568 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3569 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3570 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3572 if (IS_BROXTON(dev_priv))
3573 de_port_masked |= BXT_DE_PORT_GMBUS;
3575 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3576 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3579 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3580 GEN8_PIPE_FIFO_UNDERRUN;
3582 de_port_enables = de_port_masked;
3583 if (IS_BROXTON(dev_priv))
3584 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3585 else if (IS_BROADWELL(dev_priv))
3586 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3588 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3589 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3590 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3592 for_each_pipe(dev_priv, pipe)
3593 if (intel_display_power_is_enabled(dev_priv,
3594 POWER_DOMAIN_PIPE(pipe)))
3595 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3596 dev_priv->de_irq_mask[pipe],
3599 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3602 static int gen8_irq_postinstall(struct drm_device *dev)
3604 struct drm_i915_private *dev_priv = dev->dev_private;
3606 if (HAS_PCH_SPLIT(dev))
3607 ibx_irq_pre_postinstall(dev);
3609 gen8_gt_irq_postinstall(dev_priv);
3610 gen8_de_irq_postinstall(dev_priv);
3612 if (HAS_PCH_SPLIT(dev))
3613 ibx_irq_postinstall(dev);
3615 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3616 POSTING_READ(GEN8_MASTER_IRQ);
3621 static int cherryview_irq_postinstall(struct drm_device *dev)
3623 struct drm_i915_private *dev_priv = dev->dev_private;
3625 vlv_display_irq_postinstall(dev_priv);
3627 gen8_gt_irq_postinstall(dev_priv);
3629 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3630 POSTING_READ(GEN8_MASTER_IRQ);
3635 static void gen8_irq_uninstall(struct drm_device *dev)
3637 struct drm_i915_private *dev_priv = dev->dev_private;
3642 gen8_irq_reset(dev);
3645 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3647 /* Interrupt setup is already guaranteed to be single-threaded, this is
3648 * just to make the assert_spin_locked check happy. */
3649 spin_lock_irq(&dev_priv->irq_lock);
3650 if (dev_priv->display_irqs_enabled)
3651 valleyview_display_irqs_uninstall(dev_priv);
3652 spin_unlock_irq(&dev_priv->irq_lock);
3654 vlv_display_irq_reset(dev_priv);
3656 dev_priv->irq_mask = ~0;
3659 static void valleyview_irq_uninstall(struct drm_device *dev)
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3666 I915_WRITE(VLV_MASTER_IER, 0);
3668 gen5_gt_irq_reset(dev);
3670 I915_WRITE(HWSTAM, 0xffffffff);
3672 vlv_display_irq_uninstall(dev_priv);
3675 static void cherryview_irq_uninstall(struct drm_device *dev)
3677 struct drm_i915_private *dev_priv = dev->dev_private;
3682 I915_WRITE(GEN8_MASTER_IRQ, 0);
3683 POSTING_READ(GEN8_MASTER_IRQ);
3685 gen8_gt_irq_reset(dev_priv);
3687 GEN5_IRQ_RESET(GEN8_PCU_);
3689 vlv_display_irq_uninstall(dev_priv);
3692 static void ironlake_irq_uninstall(struct drm_device *dev)
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3699 ironlake_irq_reset(dev);
3702 static void i8xx_irq_preinstall(struct drm_device * dev)
3704 struct drm_i915_private *dev_priv = dev->dev_private;
3707 for_each_pipe(dev_priv, pipe)
3708 I915_WRITE(PIPESTAT(pipe), 0);
3709 I915_WRITE16(IMR, 0xffff);
3710 I915_WRITE16(IER, 0x0);
3711 POSTING_READ16(IER);
3714 static int i8xx_irq_postinstall(struct drm_device *dev)
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3719 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3721 /* Unmask the interrupts that we always want on. */
3722 dev_priv->irq_mask =
3723 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3724 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3725 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3726 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3727 I915_WRITE16(IMR, dev_priv->irq_mask);
3730 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3731 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3732 I915_USER_INTERRUPT);
3733 POSTING_READ16(IER);
3735 /* Interrupt setup is already guaranteed to be single-threaded, this is
3736 * just to make the assert_spin_locked check happy. */
3737 spin_lock_irq(&dev_priv->irq_lock);
3738 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3739 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3740 spin_unlock_irq(&dev_priv->irq_lock);
3746 * Returns true when a page flip has completed.
3748 static bool i8xx_handle_vblank(struct drm_device *dev,
3749 int plane, int pipe, u32 iir)
3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3754 if (!intel_pipe_handle_vblank(dev, pipe))
3757 if ((iir & flip_pending) == 0)
3758 goto check_page_flip;
3760 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3761 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3762 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3763 * the flip is completed (no longer pending). Since this doesn't raise
3764 * an interrupt per se, we watch for the change at vblank.
3766 if (I915_READ16(ISR) & flip_pending)
3767 goto check_page_flip;
3769 intel_prepare_page_flip(dev, plane);
3770 intel_finish_page_flip(dev, pipe);
3774 intel_check_page_flip(dev, pipe);
3778 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3780 struct drm_device *dev = arg;
3781 struct drm_i915_private *dev_priv = dev->dev_private;
3786 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3787 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3789 if (!intel_irqs_enabled(dev_priv))
3792 iir = I915_READ16(IIR);
3796 while (iir & ~flip_mask) {
3797 /* Can't rely on pipestat interrupt bit in iir as it might
3798 * have been cleared after the pipestat interrupt was received.
3799 * It doesn't set the bit in iir again, but it still produces
3800 * interrupts (for non-MSI).
3802 spin_lock(&dev_priv->irq_lock);
3803 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3804 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3806 for_each_pipe(dev_priv, pipe) {
3807 int reg = PIPESTAT(pipe);
3808 pipe_stats[pipe] = I915_READ(reg);
3811 * Clear the PIPE*STAT regs before the IIR
3813 if (pipe_stats[pipe] & 0x8000ffff)
3814 I915_WRITE(reg, pipe_stats[pipe]);
3816 spin_unlock(&dev_priv->irq_lock);
3818 I915_WRITE16(IIR, iir & ~flip_mask);
3819 new_iir = I915_READ16(IIR); /* Flush posted writes */
3821 if (iir & I915_USER_INTERRUPT)
3822 notify_ring(&dev_priv->ring[RCS]);
3824 for_each_pipe(dev_priv, pipe) {
3829 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3830 i8xx_handle_vblank(dev, plane, pipe, iir))
3831 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3833 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3834 i9xx_pipe_crc_irq_handler(dev, pipe);
3836 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3837 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3847 static void i8xx_irq_uninstall(struct drm_device * dev)
3849 struct drm_i915_private *dev_priv = dev->dev_private;
3852 for_each_pipe(dev_priv, pipe) {
3853 /* Clear enable bits; then clear status bits */
3854 I915_WRITE(PIPESTAT(pipe), 0);
3855 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3857 I915_WRITE16(IMR, 0xffff);
3858 I915_WRITE16(IER, 0x0);
3859 I915_WRITE16(IIR, I915_READ16(IIR));
3862 static void i915_irq_preinstall(struct drm_device * dev)
3864 struct drm_i915_private *dev_priv = dev->dev_private;
3867 if (I915_HAS_HOTPLUG(dev)) {
3868 I915_WRITE(PORT_HOTPLUG_EN, 0);
3869 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3872 I915_WRITE16(HWSTAM, 0xeffe);
3873 for_each_pipe(dev_priv, pipe)
3874 I915_WRITE(PIPESTAT(pipe), 0);
3875 I915_WRITE(IMR, 0xffffffff);
3876 I915_WRITE(IER, 0x0);
3880 static int i915_irq_postinstall(struct drm_device *dev)
3882 struct drm_i915_private *dev_priv = dev->dev_private;
3885 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3887 /* Unmask the interrupts that we always want on. */
3888 dev_priv->irq_mask =
3889 ~(I915_ASLE_INTERRUPT |
3890 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3891 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3892 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3893 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3896 I915_ASLE_INTERRUPT |
3897 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3898 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3899 I915_USER_INTERRUPT;
3901 if (I915_HAS_HOTPLUG(dev)) {
3902 I915_WRITE(PORT_HOTPLUG_EN, 0);
3903 POSTING_READ(PORT_HOTPLUG_EN);
3905 /* Enable in IER... */
3906 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3907 /* and unmask in IMR */
3908 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3911 I915_WRITE(IMR, dev_priv->irq_mask);
3912 I915_WRITE(IER, enable_mask);
3915 i915_enable_asle_pipestat(dev);
3917 /* Interrupt setup is already guaranteed to be single-threaded, this is
3918 * just to make the assert_spin_locked check happy. */
3919 spin_lock_irq(&dev_priv->irq_lock);
3920 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3921 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3922 spin_unlock_irq(&dev_priv->irq_lock);
3928 * Returns true when a page flip has completed.
3930 static bool i915_handle_vblank(struct drm_device *dev,
3931 int plane, int pipe, u32 iir)
3933 struct drm_i915_private *dev_priv = dev->dev_private;
3934 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3936 if (!intel_pipe_handle_vblank(dev, pipe))
3939 if ((iir & flip_pending) == 0)
3940 goto check_page_flip;
3942 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3943 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3944 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3945 * the flip is completed (no longer pending). Since this doesn't raise
3946 * an interrupt per se, we watch for the change at vblank.
3948 if (I915_READ(ISR) & flip_pending)
3949 goto check_page_flip;
3951 intel_prepare_page_flip(dev, plane);
3952 intel_finish_page_flip(dev, pipe);
3956 intel_check_page_flip(dev, pipe);
3960 static irqreturn_t i915_irq_handler(int irq, void *arg)
3962 struct drm_device *dev = arg;
3963 struct drm_i915_private *dev_priv = dev->dev_private;
3964 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3966 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3967 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3968 int pipe, ret = IRQ_NONE;
3970 if (!intel_irqs_enabled(dev_priv))
3973 iir = I915_READ(IIR);
3975 bool irq_received = (iir & ~flip_mask) != 0;
3976 bool blc_event = false;
3978 /* Can't rely on pipestat interrupt bit in iir as it might
3979 * have been cleared after the pipestat interrupt was received.
3980 * It doesn't set the bit in iir again, but it still produces
3981 * interrupts (for non-MSI).
3983 spin_lock(&dev_priv->irq_lock);
3984 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3985 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3987 for_each_pipe(dev_priv, pipe) {
3988 int reg = PIPESTAT(pipe);
3989 pipe_stats[pipe] = I915_READ(reg);
3991 /* Clear the PIPE*STAT regs before the IIR */
3992 if (pipe_stats[pipe] & 0x8000ffff) {
3993 I915_WRITE(reg, pipe_stats[pipe]);
3994 irq_received = true;
3997 spin_unlock(&dev_priv->irq_lock);
4002 /* Consume port. Then clear IIR or we'll miss events */
4003 if (I915_HAS_HOTPLUG(dev) &&
4004 iir & I915_DISPLAY_PORT_INTERRUPT)
4005 i9xx_hpd_irq_handler(dev);
4007 I915_WRITE(IIR, iir & ~flip_mask);
4008 new_iir = I915_READ(IIR); /* Flush posted writes */
4010 if (iir & I915_USER_INTERRUPT)
4011 notify_ring(&dev_priv->ring[RCS]);
4013 for_each_pipe(dev_priv, pipe) {
4018 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4019 i915_handle_vblank(dev, plane, pipe, iir))
4020 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4022 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4025 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4026 i9xx_pipe_crc_irq_handler(dev, pipe);
4028 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4029 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4033 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4034 intel_opregion_asle_intr(dev);
4036 /* With MSI, interrupts are only generated when iir
4037 * transitions from zero to nonzero. If another bit got
4038 * set while we were handling the existing iir bits, then
4039 * we would never get another interrupt.
4041 * This is fine on non-MSI as well, as if we hit this path
4042 * we avoid exiting the interrupt handler only to generate
4045 * Note that for MSI this could cause a stray interrupt report
4046 * if an interrupt landed in the time between writing IIR and
4047 * the posting read. This should be rare enough to never
4048 * trigger the 99% of 100,000 interrupts test for disabling
4053 } while (iir & ~flip_mask);
4058 static void i915_irq_uninstall(struct drm_device * dev)
4060 struct drm_i915_private *dev_priv = dev->dev_private;
4063 if (I915_HAS_HOTPLUG(dev)) {
4064 I915_WRITE(PORT_HOTPLUG_EN, 0);
4065 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4068 I915_WRITE16(HWSTAM, 0xffff);
4069 for_each_pipe(dev_priv, pipe) {
4070 /* Clear enable bits; then clear status bits */
4071 I915_WRITE(PIPESTAT(pipe), 0);
4072 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4074 I915_WRITE(IMR, 0xffffffff);
4075 I915_WRITE(IER, 0x0);
4077 I915_WRITE(IIR, I915_READ(IIR));
4080 static void i965_irq_preinstall(struct drm_device * dev)
4082 struct drm_i915_private *dev_priv = dev->dev_private;
4085 I915_WRITE(PORT_HOTPLUG_EN, 0);
4086 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4088 I915_WRITE(HWSTAM, 0xeffe);
4089 for_each_pipe(dev_priv, pipe)
4090 I915_WRITE(PIPESTAT(pipe), 0);
4091 I915_WRITE(IMR, 0xffffffff);
4092 I915_WRITE(IER, 0x0);
4096 static int i965_irq_postinstall(struct drm_device *dev)
4098 struct drm_i915_private *dev_priv = dev->dev_private;
4102 /* Unmask the interrupts that we always want on. */
4103 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4104 I915_DISPLAY_PORT_INTERRUPT |
4105 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4106 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4107 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4108 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4109 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4111 enable_mask = ~dev_priv->irq_mask;
4112 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4113 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4114 enable_mask |= I915_USER_INTERRUPT;
4117 enable_mask |= I915_BSD_USER_INTERRUPT;
4119 /* Interrupt setup is already guaranteed to be single-threaded, this is
4120 * just to make the assert_spin_locked check happy. */
4121 spin_lock_irq(&dev_priv->irq_lock);
4122 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4123 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4124 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4125 spin_unlock_irq(&dev_priv->irq_lock);
4128 * Enable some error detection, note the instruction error mask
4129 * bit is reserved, so we leave it masked.
4132 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4133 GM45_ERROR_MEM_PRIV |
4134 GM45_ERROR_CP_PRIV |
4135 I915_ERROR_MEMORY_REFRESH);
4137 error_mask = ~(I915_ERROR_PAGE_TABLE |
4138 I915_ERROR_MEMORY_REFRESH);
4140 I915_WRITE(EMR, error_mask);
4142 I915_WRITE(IMR, dev_priv->irq_mask);
4143 I915_WRITE(IER, enable_mask);
4146 I915_WRITE(PORT_HOTPLUG_EN, 0);
4147 POSTING_READ(PORT_HOTPLUG_EN);
4149 i915_enable_asle_pipestat(dev);
4154 static void i915_hpd_irq_setup(struct drm_device *dev)
4156 struct drm_i915_private *dev_priv = dev->dev_private;
4159 assert_spin_locked(&dev_priv->irq_lock);
4161 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4162 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4163 /* Note HDMI and DP share hotplug bits */
4164 /* enable bits are the same for all generations */
4165 hotplug_en |= intel_hpd_enabled_irqs(dev, hpd_mask_i915);
4166 /* Programming the CRT detection parameters tends
4167 to generate a spurious hotplug event about three
4168 seconds later. So just do it once.
4171 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4172 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4173 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4175 /* Ignore TV since it's buggy */
4176 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4179 static irqreturn_t i965_irq_handler(int irq, void *arg)
4181 struct drm_device *dev = arg;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4184 u32 pipe_stats[I915_MAX_PIPES];
4185 int ret = IRQ_NONE, pipe;
4187 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4188 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4190 if (!intel_irqs_enabled(dev_priv))
4193 iir = I915_READ(IIR);
4196 bool irq_received = (iir & ~flip_mask) != 0;
4197 bool blc_event = false;
4199 /* Can't rely on pipestat interrupt bit in iir as it might
4200 * have been cleared after the pipestat interrupt was received.
4201 * It doesn't set the bit in iir again, but it still produces
4202 * interrupts (for non-MSI).
4204 spin_lock(&dev_priv->irq_lock);
4205 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4206 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4208 for_each_pipe(dev_priv, pipe) {
4209 int reg = PIPESTAT(pipe);
4210 pipe_stats[pipe] = I915_READ(reg);
4213 * Clear the PIPE*STAT regs before the IIR
4215 if (pipe_stats[pipe] & 0x8000ffff) {
4216 I915_WRITE(reg, pipe_stats[pipe]);
4217 irq_received = true;
4220 spin_unlock(&dev_priv->irq_lock);
4227 /* Consume port. Then clear IIR or we'll miss events */
4228 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4229 i9xx_hpd_irq_handler(dev);
4231 I915_WRITE(IIR, iir & ~flip_mask);
4232 new_iir = I915_READ(IIR); /* Flush posted writes */
4234 if (iir & I915_USER_INTERRUPT)
4235 notify_ring(&dev_priv->ring[RCS]);
4236 if (iir & I915_BSD_USER_INTERRUPT)
4237 notify_ring(&dev_priv->ring[VCS]);
4239 for_each_pipe(dev_priv, pipe) {
4240 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4241 i915_handle_vblank(dev, pipe, pipe, iir))
4242 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4244 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4247 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4248 i9xx_pipe_crc_irq_handler(dev, pipe);
4250 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4251 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4254 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4255 intel_opregion_asle_intr(dev);
4257 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4258 gmbus_irq_handler(dev);
4260 /* With MSI, interrupts are only generated when iir
4261 * transitions from zero to nonzero. If another bit got
4262 * set while we were handling the existing iir bits, then
4263 * we would never get another interrupt.
4265 * This is fine on non-MSI as well, as if we hit this path
4266 * we avoid exiting the interrupt handler only to generate
4269 * Note that for MSI this could cause a stray interrupt report
4270 * if an interrupt landed in the time between writing IIR and
4271 * the posting read. This should be rare enough to never
4272 * trigger the 99% of 100,000 interrupts test for disabling
4281 static void i965_irq_uninstall(struct drm_device * dev)
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4289 I915_WRITE(PORT_HOTPLUG_EN, 0);
4290 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4292 I915_WRITE(HWSTAM, 0xffffffff);
4293 for_each_pipe(dev_priv, pipe)
4294 I915_WRITE(PIPESTAT(pipe), 0);
4295 I915_WRITE(IMR, 0xffffffff);
4296 I915_WRITE(IER, 0x0);
4298 for_each_pipe(dev_priv, pipe)
4299 I915_WRITE(PIPESTAT(pipe),
4300 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4301 I915_WRITE(IIR, I915_READ(IIR));
4305 * intel_irq_init - initializes irq support
4306 * @dev_priv: i915 device instance
4308 * This function initializes all the irq support including work items, timers
4309 * and all the vtables. It does not setup the interrupt itself though.
4311 void intel_irq_init(struct drm_i915_private *dev_priv)
4313 struct drm_device *dev = dev_priv->dev;
4315 intel_hpd_init_work(dev_priv);
4317 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4318 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4320 /* Let's track the enabled rps events */
4321 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4322 /* WaGsvRC0ResidencyMethod:vlv */
4323 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4325 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4327 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4328 i915_hangcheck_elapsed);
4330 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4332 if (IS_GEN2(dev_priv)) {
4333 dev->max_vblank_count = 0;
4334 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4335 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4336 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4337 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4339 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4340 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4344 * Opt out of the vblank disable timer on everything except gen2.
4345 * Gen2 doesn't have a hardware frame counter and so depends on
4346 * vblank interrupts to produce sane vblank seuquence numbers.
4348 if (!IS_GEN2(dev_priv))
4349 dev->vblank_disable_immediate = true;
4351 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4352 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4354 if (IS_CHERRYVIEW(dev_priv)) {
4355 dev->driver->irq_handler = cherryview_irq_handler;
4356 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4357 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4358 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4359 dev->driver->enable_vblank = valleyview_enable_vblank;
4360 dev->driver->disable_vblank = valleyview_disable_vblank;
4361 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4362 } else if (IS_VALLEYVIEW(dev_priv)) {
4363 dev->driver->irq_handler = valleyview_irq_handler;
4364 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4365 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4366 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4367 dev->driver->enable_vblank = valleyview_enable_vblank;
4368 dev->driver->disable_vblank = valleyview_disable_vblank;
4369 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4370 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4371 dev->driver->irq_handler = gen8_irq_handler;
4372 dev->driver->irq_preinstall = gen8_irq_reset;
4373 dev->driver->irq_postinstall = gen8_irq_postinstall;
4374 dev->driver->irq_uninstall = gen8_irq_uninstall;
4375 dev->driver->enable_vblank = gen8_enable_vblank;
4376 dev->driver->disable_vblank = gen8_disable_vblank;
4377 if (IS_BROXTON(dev))
4378 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4379 else if (HAS_PCH_SPT(dev))
4380 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4382 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4383 } else if (HAS_PCH_SPLIT(dev)) {
4384 dev->driver->irq_handler = ironlake_irq_handler;
4385 dev->driver->irq_preinstall = ironlake_irq_reset;
4386 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4387 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4388 dev->driver->enable_vblank = ironlake_enable_vblank;
4389 dev->driver->disable_vblank = ironlake_disable_vblank;
4390 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4392 if (INTEL_INFO(dev_priv)->gen == 2) {
4393 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4394 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4395 dev->driver->irq_handler = i8xx_irq_handler;
4396 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4397 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4398 dev->driver->irq_preinstall = i915_irq_preinstall;
4399 dev->driver->irq_postinstall = i915_irq_postinstall;
4400 dev->driver->irq_uninstall = i915_irq_uninstall;
4401 dev->driver->irq_handler = i915_irq_handler;
4403 dev->driver->irq_preinstall = i965_irq_preinstall;
4404 dev->driver->irq_postinstall = i965_irq_postinstall;
4405 dev->driver->irq_uninstall = i965_irq_uninstall;
4406 dev->driver->irq_handler = i965_irq_handler;
4408 if (I915_HAS_HOTPLUG(dev_priv))
4409 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4410 dev->driver->enable_vblank = i915_enable_vblank;
4411 dev->driver->disable_vblank = i915_disable_vblank;
4416 * intel_irq_install - enables the hardware interrupt
4417 * @dev_priv: i915 device instance
4419 * This function enables the hardware interrupt handling, but leaves the hotplug
4420 * handling still disabled. It is called after intel_irq_init().
4422 * In the driver load and resume code we need working interrupts in a few places
4423 * but don't want to deal with the hassle of concurrent probe and hotplug
4424 * workers. Hence the split into this two-stage approach.
4426 int intel_irq_install(struct drm_i915_private *dev_priv)
4429 * We enable some interrupt sources in our postinstall hooks, so mark
4430 * interrupts as enabled _before_ actually enabling them to avoid
4431 * special cases in our ordering checks.
4433 dev_priv->pm.irqs_enabled = true;
4435 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4439 * intel_irq_uninstall - finilizes all irq handling
4440 * @dev_priv: i915 device instance
4442 * This stops interrupt and hotplug handling and unregisters and frees all
4443 * resources acquired in the init functions.
4445 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4447 drm_irq_uninstall(dev_priv->dev);
4448 intel_hpd_cancel_work(dev_priv);
4449 dev_priv->pm.irqs_enabled = false;
4453 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4454 * @dev_priv: i915 device instance
4456 * This function is used to disable interrupts at runtime, both in the runtime
4457 * pm and the system suspend/resume code.
4459 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4461 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4462 dev_priv->pm.irqs_enabled = false;
4463 synchronize_irq(dev_priv->dev->irq);
4467 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4468 * @dev_priv: i915 device instance
4470 * This function is used to enable interrupts at runtime, both in the runtime
4471 * pm and the system suspend/resume code.
4473 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4475 dev_priv->pm.irqs_enabled = true;
4476 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4477 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);