1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
40 /* For display hotplug interrupt */
42 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
52 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
62 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
65 u32 reg = PIPESTAT(pipe);
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
75 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
78 u32 reg = PIPESTAT(pipe);
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
89 void intel_enable_asle(struct drm_device *dev)
91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
100 if (HAS_PCH_SPLIT(dev))
101 ironlake_enable_display_irq(dev_priv, DE_GSE);
103 i915_enable_pipestat(dev_priv, 1,
104 PIPE_LEGACY_BLC_EVENT_ENABLE);
105 if (INTEL_INFO(dev)->gen >= 4)
106 i915_enable_pipestat(dev_priv, 0,
107 PIPE_LEGACY_BLC_EVENT_ENABLE);
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
114 * i915_pipe_enabled - check if a pipe is enabled
116 * @pipe: pipe to check
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
123 i915_pipe_enabled(struct drm_device *dev, int pipe)
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
129 /* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
132 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
137 u32 high1, high2, low;
139 if (!i915_pipe_enabled(dev, pipe)) {
140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
141 "pipe %c\n", pipe_name(pipe));
145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
157 } while (high1 != high2);
159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
164 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
167 int reg = PIPE_FRMCOUNT_GM45(pipe);
169 if (!i915_pipe_enabled(dev, pipe)) {
170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
171 "pipe %c\n", pipe_name(pipe));
175 return I915_READ(reg);
178 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
179 int *vpos, int *hpos)
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
189 "pipe %c\n", pipe_name(pipe));
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
200 position = I915_READ(PIPEDSL(pipe));
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
205 *vpos = position & 0x1fff;
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
233 /* Readouts valid? */
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
239 ret |= DRM_SCANOUTPOS_INVBL;
244 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
246 struct timeval *vblank_time,
249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
257 /* Get drm_crtc to timestamp: */
258 crtc = intel_get_crtc_for_pipe(dev, pipe);
260 DRM_ERROR("Invalid crtc %d\n", pipe);
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
269 /* Helper routine in DRM core does all the work: */
270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
276 * Handle hotplug events outside the interrupt handler proper.
278 static void i915_hotplug_work_func(struct work_struct *work)
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
282 struct drm_device *dev = dev_priv->dev;
283 struct drm_mode_config *mode_config = &dev->mode_config;
284 struct intel_encoder *encoder;
286 mutex_lock(&mode_config->mutex);
287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
293 mutex_unlock(&mode_config->mutex);
295 /* Just fire off a uevent and let userspace tell us what to do */
296 drm_helper_hpd_irq_event(dev);
299 static void i915_handle_rps_change(struct drm_device *dev)
301 drm_i915_private_t *dev_priv = dev->dev_private;
302 u32 busy_up, busy_down, max_avg, min_avg;
303 u8 new_delay = dev_priv->cur_delay;
305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
311 /* Handle RCS change request from hw */
312 if (busy_up > max_avg) {
313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
317 } else if (busy_down < min_avg) {
318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
330 static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
333 struct drm_i915_private *dev_priv = dev->dev_private;
335 if (ring->obj == NULL)
338 trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
340 wake_up_all(&ring->irq_queue);
341 if (i915_enable_hangcheck) {
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer,
345 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
349 static void gen6_pm_rps_work(struct work_struct *work)
351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
356 spin_lock_irq(&dev_priv->rps_lock);
357 pm_iir = dev_priv->pm_iir;
358 dev_priv->pm_iir = 0;
359 pm_imr = I915_READ(GEN6_PMIMR);
360 I915_WRITE(GEN6_PMIMR, 0);
361 spin_unlock_irq(&dev_priv->rps_lock);
363 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
366 mutex_lock(&dev_priv->dev->struct_mutex);
368 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
369 new_delay = dev_priv->cur_delay + 1;
371 new_delay = dev_priv->cur_delay - 1;
373 gen6_set_rps(dev_priv->dev, new_delay);
375 mutex_unlock(&dev_priv->dev->struct_mutex);
380 * ivybridge_parity_work - Workqueue called when a parity error interrupt
382 * @work: workqueue struct
384 * Doesn't actually do anything except notify userspace. As a consequence of
385 * this event, userspace should try to remap the bad rows since statistically
386 * it is likely the same row is more likely to go bad again.
388 static void ivybridge_parity_work(struct work_struct *work)
390 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
392 u32 error_status, row, bank, subbank;
393 char *parity_event[5];
397 /* We must turn off DOP level clock gating to access the L3 registers.
398 * In order to prevent a get/put style interface, acquire struct mutex
399 * any time we access those registers.
401 mutex_lock(&dev_priv->dev->struct_mutex);
403 misccpctl = I915_READ(GEN7_MISCCPCTL);
404 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
405 POSTING_READ(GEN7_MISCCPCTL);
407 error_status = I915_READ(GEN7_L3CDERRST1);
408 row = GEN7_PARITY_ERROR_ROW(error_status);
409 bank = GEN7_PARITY_ERROR_BANK(error_status);
410 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
412 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
413 GEN7_L3CDERRST1_ENABLE);
414 POSTING_READ(GEN7_L3CDERRST1);
416 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
418 spin_lock_irqsave(&dev_priv->irq_lock, flags);
419 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
420 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
421 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
423 mutex_unlock(&dev_priv->dev->struct_mutex);
425 parity_event[0] = "L3_PARITY_ERROR=1";
426 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
427 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
428 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
429 parity_event[4] = NULL;
431 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
432 KOBJ_CHANGE, parity_event);
434 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
437 kfree(parity_event[3]);
438 kfree(parity_event[2]);
439 kfree(parity_event[1]);
442 static void ivybridge_handle_parity_error(struct drm_device *dev)
444 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
447 if (!IS_IVYBRIDGE(dev))
450 spin_lock_irqsave(&dev_priv->irq_lock, flags);
451 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
452 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
453 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
455 queue_work(dev_priv->wq, &dev_priv->parity_error_work);
458 static void snb_gt_irq_handler(struct drm_device *dev,
459 struct drm_i915_private *dev_priv,
463 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
464 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
465 notify_ring(dev, &dev_priv->ring[RCS]);
466 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
467 notify_ring(dev, &dev_priv->ring[VCS]);
468 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
469 notify_ring(dev, &dev_priv->ring[BCS]);
471 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
472 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
473 GT_RENDER_CS_ERROR_INTERRUPT)) {
474 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
475 i915_handle_error(dev, false);
478 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
479 ivybridge_handle_parity_error(dev);
482 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
488 * IIR bits should never already be set because IMR should
489 * prevent an interrupt from being shown in IIR. The warning
490 * displays a case where we've unsafely cleared
491 * dev_priv->pm_iir. Although missing an interrupt of the same
492 * type is not a problem, it displays a problem in the logic.
494 * The mask bit in IMR is cleared by rps_work.
497 spin_lock_irqsave(&dev_priv->rps_lock, flags);
498 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
499 dev_priv->pm_iir |= pm_iir;
500 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
501 POSTING_READ(GEN6_PMIMR);
502 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
504 queue_work(dev_priv->wq, &dev_priv->rps_work);
507 static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
509 struct drm_device *dev = (struct drm_device *) arg;
510 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
511 u32 iir, gt_iir, pm_iir;
512 irqreturn_t ret = IRQ_NONE;
513 unsigned long irqflags;
515 u32 pipe_stats[I915_MAX_PIPES];
520 atomic_inc(&dev_priv->irq_received);
522 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
523 PIPE_VBLANK_INTERRUPT_STATUS;
526 iir = I915_READ(VLV_IIR);
527 gt_iir = I915_READ(GTIIR);
528 pm_iir = I915_READ(GEN6_PMIIR);
530 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
535 snb_gt_irq_handler(dev, dev_priv, gt_iir);
537 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
538 for_each_pipe(pipe) {
539 int reg = PIPESTAT(pipe);
540 pipe_stats[pipe] = I915_READ(reg);
543 * Clear the PIPE*STAT regs before the IIR
545 if (pipe_stats[pipe] & 0x8000ffff) {
546 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
547 DRM_DEBUG_DRIVER("pipe %c underrun\n",
549 I915_WRITE(reg, pipe_stats[pipe]);
552 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
554 /* Consume port. Then clear IIR or we'll miss events */
555 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
556 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
558 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
560 if (hotplug_status & dev_priv->hotplug_supported_mask)
561 queue_work(dev_priv->wq,
562 &dev_priv->hotplug_work);
564 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
565 I915_READ(PORT_HOTPLUG_STAT);
569 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
570 drm_handle_vblank(dev, 0);
572 intel_finish_page_flip(dev, 0);
575 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
576 drm_handle_vblank(dev, 1);
578 intel_finish_page_flip(dev, 0);
581 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
584 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
585 gen6_queue_rps_work(dev_priv, pm_iir);
587 I915_WRITE(GTIIR, gt_iir);
588 I915_WRITE(GEN6_PMIIR, pm_iir);
589 I915_WRITE(VLV_IIR, iir);
596 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
598 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
601 if (pch_iir & SDE_AUDIO_POWER_MASK)
602 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
603 (pch_iir & SDE_AUDIO_POWER_MASK) >>
604 SDE_AUDIO_POWER_SHIFT);
606 if (pch_iir & SDE_GMBUS)
607 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
609 if (pch_iir & SDE_AUDIO_HDCP_MASK)
610 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
612 if (pch_iir & SDE_AUDIO_TRANS_MASK)
613 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
615 if (pch_iir & SDE_POISON)
616 DRM_ERROR("PCH poison interrupt\n");
618 if (pch_iir & SDE_FDI_MASK)
620 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
622 I915_READ(FDI_RX_IIR(pipe)));
624 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
625 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
627 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
628 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
630 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
631 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
632 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
633 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
636 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
638 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
641 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
642 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
643 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
644 SDE_AUDIO_POWER_SHIFT_CPT);
646 if (pch_iir & SDE_AUX_MASK_CPT)
647 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
649 if (pch_iir & SDE_GMBUS_CPT)
650 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
652 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
653 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
655 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
656 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
658 if (pch_iir & SDE_FDI_MASK_CPT)
660 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
662 I915_READ(FDI_RX_IIR(pipe)));
665 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
667 struct drm_device *dev = (struct drm_device *) arg;
668 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
669 u32 de_iir, gt_iir, de_ier, pm_iir;
670 irqreturn_t ret = IRQ_NONE;
673 atomic_inc(&dev_priv->irq_received);
675 /* disable master interrupt before clearing iir */
676 de_ier = I915_READ(DEIER);
677 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
679 gt_iir = I915_READ(GTIIR);
681 snb_gt_irq_handler(dev, dev_priv, gt_iir);
682 I915_WRITE(GTIIR, gt_iir);
686 de_iir = I915_READ(DEIIR);
688 if (de_iir & DE_GSE_IVB)
689 intel_opregion_gse_intr(dev);
691 for (i = 0; i < 3; i++) {
692 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
693 intel_prepare_page_flip(dev, i);
694 intel_finish_page_flip_plane(dev, i);
696 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
697 drm_handle_vblank(dev, i);
700 /* check event from PCH */
701 if (de_iir & DE_PCH_EVENT_IVB) {
702 u32 pch_iir = I915_READ(SDEIIR);
704 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
705 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
706 cpt_irq_handler(dev, pch_iir);
708 /* clear PCH hotplug event before clear CPU irq */
709 I915_WRITE(SDEIIR, pch_iir);
712 I915_WRITE(DEIIR, de_iir);
716 pm_iir = I915_READ(GEN6_PMIIR);
718 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
719 gen6_queue_rps_work(dev_priv, pm_iir);
720 I915_WRITE(GEN6_PMIIR, pm_iir);
724 I915_WRITE(DEIER, de_ier);
730 static void ilk_gt_irq_handler(struct drm_device *dev,
731 struct drm_i915_private *dev_priv,
734 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
735 notify_ring(dev, &dev_priv->ring[RCS]);
736 if (gt_iir & GT_BSD_USER_INTERRUPT)
737 notify_ring(dev, &dev_priv->ring[VCS]);
740 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
742 struct drm_device *dev = (struct drm_device *) arg;
743 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
745 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
748 atomic_inc(&dev_priv->irq_received);
750 /* disable master interrupt before clearing iir */
751 de_ier = I915_READ(DEIER);
752 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
755 de_iir = I915_READ(DEIIR);
756 gt_iir = I915_READ(GTIIR);
757 pch_iir = I915_READ(SDEIIR);
758 pm_iir = I915_READ(GEN6_PMIIR);
760 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
761 (!IS_GEN6(dev) || pm_iir == 0))
764 if (HAS_PCH_CPT(dev))
765 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
767 hotplug_mask = SDE_HOTPLUG_MASK;
772 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
774 snb_gt_irq_handler(dev, dev_priv, gt_iir);
777 intel_opregion_gse_intr(dev);
779 if (de_iir & DE_PLANEA_FLIP_DONE) {
780 intel_prepare_page_flip(dev, 0);
781 intel_finish_page_flip_plane(dev, 0);
784 if (de_iir & DE_PLANEB_FLIP_DONE) {
785 intel_prepare_page_flip(dev, 1);
786 intel_finish_page_flip_plane(dev, 1);
789 if (de_iir & DE_PIPEA_VBLANK)
790 drm_handle_vblank(dev, 0);
792 if (de_iir & DE_PIPEB_VBLANK)
793 drm_handle_vblank(dev, 1);
795 /* check event from PCH */
796 if (de_iir & DE_PCH_EVENT) {
797 if (pch_iir & hotplug_mask)
798 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
799 if (HAS_PCH_CPT(dev))
800 cpt_irq_handler(dev, pch_iir);
802 ibx_irq_handler(dev, pch_iir);
805 if (de_iir & DE_PCU_EVENT) {
806 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
807 i915_handle_rps_change(dev);
810 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
811 gen6_queue_rps_work(dev_priv, pm_iir);
813 /* should clear PCH hotplug event before clear CPU irq */
814 I915_WRITE(SDEIIR, pch_iir);
815 I915_WRITE(GTIIR, gt_iir);
816 I915_WRITE(DEIIR, de_iir);
817 I915_WRITE(GEN6_PMIIR, pm_iir);
820 I915_WRITE(DEIER, de_ier);
827 * i915_error_work_func - do process context error handling work
830 * Fire an error uevent so userspace can see that a hang or error
833 static void i915_error_work_func(struct work_struct *work)
835 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
837 struct drm_device *dev = dev_priv->dev;
838 char *error_event[] = { "ERROR=1", NULL };
839 char *reset_event[] = { "RESET=1", NULL };
840 char *reset_done_event[] = { "ERROR=0", NULL };
842 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
844 if (atomic_read(&dev_priv->mm.wedged)) {
845 DRM_DEBUG_DRIVER("resetting chip\n");
846 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
847 if (!i915_reset(dev)) {
848 atomic_set(&dev_priv->mm.wedged, 0);
849 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
851 complete_all(&dev_priv->error_completion);
855 #ifdef CONFIG_DEBUG_FS
856 static struct drm_i915_error_object *
857 i915_error_object_create(struct drm_i915_private *dev_priv,
858 struct drm_i915_gem_object *src)
860 struct drm_i915_error_object *dst;
861 int page, page_count;
864 if (src == NULL || src->pages == NULL)
867 page_count = src->base.size / PAGE_SIZE;
869 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
873 reloc_offset = src->gtt_offset;
874 for (page = 0; page < page_count; page++) {
878 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
882 local_irq_save(flags);
883 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
884 src->has_global_gtt_mapping) {
887 /* Simply ignore tiling or any overlapping fence.
888 * It's part of the error state, and this hopefully
889 * captures what the GPU read.
892 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
894 memcpy_fromio(d, s, PAGE_SIZE);
895 io_mapping_unmap_atomic(s);
899 drm_clflush_pages(&src->pages[page], 1);
901 s = kmap_atomic(src->pages[page]);
902 memcpy(d, s, PAGE_SIZE);
905 drm_clflush_pages(&src->pages[page], 1);
907 local_irq_restore(flags);
909 dst->pages[page] = d;
911 reloc_offset += PAGE_SIZE;
913 dst->page_count = page_count;
914 dst->gtt_offset = src->gtt_offset;
920 kfree(dst->pages[page]);
926 i915_error_object_free(struct drm_i915_error_object *obj)
933 for (page = 0; page < obj->page_count; page++)
934 kfree(obj->pages[page]);
940 i915_error_state_free(struct kref *error_ref)
942 struct drm_i915_error_state *error = container_of(error_ref,
943 typeof(*error), ref);
946 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
947 i915_error_object_free(error->ring[i].batchbuffer);
948 i915_error_object_free(error->ring[i].ringbuffer);
949 kfree(error->ring[i].requests);
952 kfree(error->active_bo);
953 kfree(error->overlay);
956 static void capture_bo(struct drm_i915_error_buffer *err,
957 struct drm_i915_gem_object *obj)
959 err->size = obj->base.size;
960 err->name = obj->base.name;
961 err->seqno = obj->last_rendering_seqno;
962 err->gtt_offset = obj->gtt_offset;
963 err->read_domains = obj->base.read_domains;
964 err->write_domain = obj->base.write_domain;
965 err->fence_reg = obj->fence_reg;
967 if (obj->pin_count > 0)
969 if (obj->user_pin_count > 0)
971 err->tiling = obj->tiling_mode;
972 err->dirty = obj->dirty;
973 err->purgeable = obj->madv != I915_MADV_WILLNEED;
974 err->ring = obj->ring ? obj->ring->id : -1;
975 err->cache_level = obj->cache_level;
978 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
979 int count, struct list_head *head)
981 struct drm_i915_gem_object *obj;
984 list_for_each_entry(obj, head, mm_list) {
985 capture_bo(err++, obj);
993 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
994 int count, struct list_head *head)
996 struct drm_i915_gem_object *obj;
999 list_for_each_entry(obj, head, gtt_list) {
1000 if (obj->pin_count == 0)
1003 capture_bo(err++, obj);
1011 static void i915_gem_record_fences(struct drm_device *dev,
1012 struct drm_i915_error_state *error)
1014 struct drm_i915_private *dev_priv = dev->dev_private;
1018 switch (INTEL_INFO(dev)->gen) {
1021 for (i = 0; i < 16; i++)
1022 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1026 for (i = 0; i < 16; i++)
1027 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1030 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1031 for (i = 0; i < 8; i++)
1032 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1034 for (i = 0; i < 8; i++)
1035 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1041 static struct drm_i915_error_object *
1042 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1043 struct intel_ring_buffer *ring)
1045 struct drm_i915_gem_object *obj;
1048 if (!ring->get_seqno)
1051 seqno = ring->get_seqno(ring);
1052 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1053 if (obj->ring != ring)
1056 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
1059 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1062 /* We need to copy these to an anonymous buffer as the simplest
1063 * method to avoid being overwritten by userspace.
1065 return i915_error_object_create(dev_priv, obj);
1071 static void i915_record_ring_state(struct drm_device *dev,
1072 struct drm_i915_error_state *error,
1073 struct intel_ring_buffer *ring)
1075 struct drm_i915_private *dev_priv = dev->dev_private;
1077 if (INTEL_INFO(dev)->gen >= 6) {
1078 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1079 error->semaphore_mboxes[ring->id][0]
1080 = I915_READ(RING_SYNC_0(ring->mmio_base));
1081 error->semaphore_mboxes[ring->id][1]
1082 = I915_READ(RING_SYNC_1(ring->mmio_base));
1085 if (INTEL_INFO(dev)->gen >= 4) {
1086 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1087 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1088 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1089 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1090 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1091 if (ring->id == RCS) {
1092 error->instdone1 = I915_READ(INSTDONE1);
1093 error->bbaddr = I915_READ64(BB_ADDR);
1096 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1097 error->ipeir[ring->id] = I915_READ(IPEIR);
1098 error->ipehr[ring->id] = I915_READ(IPEHR);
1099 error->instdone[ring->id] = I915_READ(INSTDONE);
1102 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1103 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1104 error->seqno[ring->id] = ring->get_seqno(ring);
1105 error->acthd[ring->id] = intel_ring_get_active_head(ring);
1106 error->head[ring->id] = I915_READ_HEAD(ring);
1107 error->tail[ring->id] = I915_READ_TAIL(ring);
1109 error->cpu_ring_head[ring->id] = ring->head;
1110 error->cpu_ring_tail[ring->id] = ring->tail;
1113 static void i915_gem_record_rings(struct drm_device *dev,
1114 struct drm_i915_error_state *error)
1116 struct drm_i915_private *dev_priv = dev->dev_private;
1117 struct intel_ring_buffer *ring;
1118 struct drm_i915_gem_request *request;
1121 for_each_ring(ring, dev_priv, i) {
1122 i915_record_ring_state(dev, error, ring);
1124 error->ring[i].batchbuffer =
1125 i915_error_first_batchbuffer(dev_priv, ring);
1127 error->ring[i].ringbuffer =
1128 i915_error_object_create(dev_priv, ring->obj);
1131 list_for_each_entry(request, &ring->request_list, list)
1134 error->ring[i].num_requests = count;
1135 error->ring[i].requests =
1136 kmalloc(count*sizeof(struct drm_i915_error_request),
1138 if (error->ring[i].requests == NULL) {
1139 error->ring[i].num_requests = 0;
1144 list_for_each_entry(request, &ring->request_list, list) {
1145 struct drm_i915_error_request *erq;
1147 erq = &error->ring[i].requests[count++];
1148 erq->seqno = request->seqno;
1149 erq->jiffies = request->emitted_jiffies;
1150 erq->tail = request->tail;
1156 * i915_capture_error_state - capture an error record for later analysis
1159 * Should be called when an error is detected (either a hang or an error
1160 * interrupt) to capture error state from the time of the error. Fills
1161 * out a structure which becomes available in debugfs for user level tools
1164 static void i915_capture_error_state(struct drm_device *dev)
1166 struct drm_i915_private *dev_priv = dev->dev_private;
1167 struct drm_i915_gem_object *obj;
1168 struct drm_i915_error_state *error;
1169 unsigned long flags;
1172 spin_lock_irqsave(&dev_priv->error_lock, flags);
1173 error = dev_priv->first_error;
1174 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1178 /* Account for pipe specific data like PIPE*STAT */
1179 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1181 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1185 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1186 dev->primary->index);
1188 kref_init(&error->ref);
1189 error->eir = I915_READ(EIR);
1190 error->pgtbl_er = I915_READ(PGTBL_ER);
1192 if (HAS_PCH_SPLIT(dev))
1193 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1194 else if (IS_VALLEYVIEW(dev))
1195 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1196 else if (IS_GEN2(dev))
1197 error->ier = I915_READ16(IER);
1199 error->ier = I915_READ(IER);
1202 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1204 if (INTEL_INFO(dev)->gen >= 6) {
1205 error->error = I915_READ(ERROR_GEN6);
1206 error->done_reg = I915_READ(DONE_REG);
1209 i915_gem_record_fences(dev, error);
1210 i915_gem_record_rings(dev, error);
1212 /* Record buffers on the active and pinned lists. */
1213 error->active_bo = NULL;
1214 error->pinned_bo = NULL;
1217 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1219 error->active_bo_count = i;
1220 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1223 error->pinned_bo_count = i - error->active_bo_count;
1225 error->active_bo = NULL;
1226 error->pinned_bo = NULL;
1228 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1230 if (error->active_bo)
1232 error->active_bo + error->active_bo_count;
1235 if (error->active_bo)
1236 error->active_bo_count =
1237 capture_active_bo(error->active_bo,
1238 error->active_bo_count,
1239 &dev_priv->mm.active_list);
1241 if (error->pinned_bo)
1242 error->pinned_bo_count =
1243 capture_pinned_bo(error->pinned_bo,
1244 error->pinned_bo_count,
1245 &dev_priv->mm.gtt_list);
1247 do_gettimeofday(&error->time);
1249 error->overlay = intel_overlay_capture_error_state(dev);
1250 error->display = intel_display_capture_error_state(dev);
1252 spin_lock_irqsave(&dev_priv->error_lock, flags);
1253 if (dev_priv->first_error == NULL) {
1254 dev_priv->first_error = error;
1257 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1260 i915_error_state_free(&error->ref);
1263 void i915_destroy_error_state(struct drm_device *dev)
1265 struct drm_i915_private *dev_priv = dev->dev_private;
1266 struct drm_i915_error_state *error;
1267 unsigned long flags;
1269 spin_lock_irqsave(&dev_priv->error_lock, flags);
1270 error = dev_priv->first_error;
1271 dev_priv->first_error = NULL;
1272 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1275 kref_put(&error->ref, i915_error_state_free);
1278 #define i915_capture_error_state(x)
1281 static void i915_report_and_clear_eir(struct drm_device *dev)
1283 struct drm_i915_private *dev_priv = dev->dev_private;
1284 u32 eir = I915_READ(EIR);
1290 pr_err("render error detected, EIR: 0x%08x\n", eir);
1293 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1294 u32 ipeir = I915_READ(IPEIR_I965);
1296 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1297 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1298 pr_err(" INSTDONE: 0x%08x\n",
1299 I915_READ(INSTDONE_I965));
1300 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1301 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1302 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1303 I915_WRITE(IPEIR_I965, ipeir);
1304 POSTING_READ(IPEIR_I965);
1306 if (eir & GM45_ERROR_PAGE_TABLE) {
1307 u32 pgtbl_err = I915_READ(PGTBL_ER);
1308 pr_err("page table error\n");
1309 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1310 I915_WRITE(PGTBL_ER, pgtbl_err);
1311 POSTING_READ(PGTBL_ER);
1315 if (!IS_GEN2(dev)) {
1316 if (eir & I915_ERROR_PAGE_TABLE) {
1317 u32 pgtbl_err = I915_READ(PGTBL_ER);
1318 pr_err("page table error\n");
1319 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1320 I915_WRITE(PGTBL_ER, pgtbl_err);
1321 POSTING_READ(PGTBL_ER);
1325 if (eir & I915_ERROR_MEMORY_REFRESH) {
1326 pr_err("memory refresh error:\n");
1328 pr_err("pipe %c stat: 0x%08x\n",
1329 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1330 /* pipestat has already been acked */
1332 if (eir & I915_ERROR_INSTRUCTION) {
1333 pr_err("instruction error\n");
1334 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
1335 if (INTEL_INFO(dev)->gen < 4) {
1336 u32 ipeir = I915_READ(IPEIR);
1338 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1339 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1340 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1341 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
1342 I915_WRITE(IPEIR, ipeir);
1343 POSTING_READ(IPEIR);
1345 u32 ipeir = I915_READ(IPEIR_I965);
1347 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1348 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1349 pr_err(" INSTDONE: 0x%08x\n",
1350 I915_READ(INSTDONE_I965));
1351 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1352 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1353 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1354 I915_WRITE(IPEIR_I965, ipeir);
1355 POSTING_READ(IPEIR_I965);
1359 I915_WRITE(EIR, eir);
1361 eir = I915_READ(EIR);
1364 * some errors might have become stuck,
1367 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1368 I915_WRITE(EMR, I915_READ(EMR) | eir);
1369 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1374 * i915_handle_error - handle an error interrupt
1377 * Do some basic checking of regsiter state at error interrupt time and
1378 * dump it to the syslog. Also call i915_capture_error_state() to make
1379 * sure we get a record and make it available in debugfs. Fire a uevent
1380 * so userspace knows something bad happened (should trigger collection
1381 * of a ring dump etc.).
1383 void i915_handle_error(struct drm_device *dev, bool wedged)
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 struct intel_ring_buffer *ring;
1389 i915_capture_error_state(dev);
1390 i915_report_and_clear_eir(dev);
1393 INIT_COMPLETION(dev_priv->error_completion);
1394 atomic_set(&dev_priv->mm.wedged, 1);
1397 * Wakeup waiting processes so they don't hang
1399 for_each_ring(ring, dev_priv, i)
1400 wake_up_all(&ring->irq_queue);
1403 queue_work(dev_priv->wq, &dev_priv->error_work);
1406 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1408 drm_i915_private_t *dev_priv = dev->dev_private;
1409 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1411 struct drm_i915_gem_object *obj;
1412 struct intel_unpin_work *work;
1413 unsigned long flags;
1414 bool stall_detected;
1416 /* Ignore early vblank irqs */
1417 if (intel_crtc == NULL)
1420 spin_lock_irqsave(&dev->event_lock, flags);
1421 work = intel_crtc->unpin_work;
1423 if (work == NULL || work->pending || !work->enable_stall_check) {
1424 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1425 spin_unlock_irqrestore(&dev->event_lock, flags);
1429 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1430 obj = work->pending_flip_obj;
1431 if (INTEL_INFO(dev)->gen >= 4) {
1432 int dspsurf = DSPSURF(intel_crtc->plane);
1433 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1436 int dspaddr = DSPADDR(intel_crtc->plane);
1437 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1438 crtc->y * crtc->fb->pitches[0] +
1439 crtc->x * crtc->fb->bits_per_pixel/8);
1442 spin_unlock_irqrestore(&dev->event_lock, flags);
1444 if (stall_detected) {
1445 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1446 intel_prepare_page_flip(dev, intel_crtc->plane);
1450 /* Called from drm generic code, passed 'crtc' which
1451 * we use as a pipe index
1453 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1455 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1456 unsigned long irqflags;
1458 if (!i915_pipe_enabled(dev, pipe))
1461 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1462 if (INTEL_INFO(dev)->gen >= 4)
1463 i915_enable_pipestat(dev_priv, pipe,
1464 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1466 i915_enable_pipestat(dev_priv, pipe,
1467 PIPE_VBLANK_INTERRUPT_ENABLE);
1469 /* maintain vblank delivery even in deep C-states */
1470 if (dev_priv->info->gen == 3)
1471 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1472 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1477 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1479 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1480 unsigned long irqflags;
1482 if (!i915_pipe_enabled(dev, pipe))
1485 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1486 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1487 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1488 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1493 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1495 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1496 unsigned long irqflags;
1498 if (!i915_pipe_enabled(dev, pipe))
1501 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1502 ironlake_enable_display_irq(dev_priv,
1503 DE_PIPEA_VBLANK_IVB << (5 * pipe));
1504 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1509 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1511 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1512 unsigned long irqflags;
1515 if (!i915_pipe_enabled(dev, pipe))
1518 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1519 dpfl = I915_READ(VLV_DPFLIPSTAT);
1520 imr = I915_READ(VLV_IMR);
1522 dpfl |= PIPEA_VBLANK_INT_EN;
1523 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1525 dpfl |= PIPEA_VBLANK_INT_EN;
1526 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1528 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1529 I915_WRITE(VLV_IMR, imr);
1530 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1535 /* Called from drm generic code, passed 'crtc' which
1536 * we use as a pipe index
1538 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1540 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1541 unsigned long irqflags;
1543 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1544 if (dev_priv->info->gen == 3)
1545 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1547 i915_disable_pipestat(dev_priv, pipe,
1548 PIPE_VBLANK_INTERRUPT_ENABLE |
1549 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1550 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1553 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1555 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1556 unsigned long irqflags;
1558 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1559 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1560 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1561 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1564 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1566 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1567 unsigned long irqflags;
1569 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1570 ironlake_disable_display_irq(dev_priv,
1571 DE_PIPEA_VBLANK_IVB << (pipe * 5));
1572 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1575 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1577 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1578 unsigned long irqflags;
1581 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1582 dpfl = I915_READ(VLV_DPFLIPSTAT);
1583 imr = I915_READ(VLV_IMR);
1585 dpfl &= ~PIPEA_VBLANK_INT_EN;
1586 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1588 dpfl &= ~PIPEB_VBLANK_INT_EN;
1589 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1591 I915_WRITE(VLV_IMR, imr);
1592 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1593 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1597 ring_last_seqno(struct intel_ring_buffer *ring)
1599 return list_entry(ring->request_list.prev,
1600 struct drm_i915_gem_request, list)->seqno;
1603 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1605 if (list_empty(&ring->request_list) ||
1606 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1607 /* Issue a wake-up to catch stuck h/w. */
1608 if (waitqueue_active(&ring->irq_queue)) {
1609 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1611 wake_up_all(&ring->irq_queue);
1619 static bool kick_ring(struct intel_ring_buffer *ring)
1621 struct drm_device *dev = ring->dev;
1622 struct drm_i915_private *dev_priv = dev->dev_private;
1623 u32 tmp = I915_READ_CTL(ring);
1624 if (tmp & RING_WAIT) {
1625 DRM_ERROR("Kicking stuck wait on %s\n",
1627 I915_WRITE_CTL(ring, tmp);
1633 static bool i915_hangcheck_hung(struct drm_device *dev)
1635 drm_i915_private_t *dev_priv = dev->dev_private;
1637 if (dev_priv->hangcheck_count++ > 1) {
1640 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1641 i915_handle_error(dev, true);
1643 if (!IS_GEN2(dev)) {
1644 struct intel_ring_buffer *ring;
1647 /* Is the chip hanging on a WAIT_FOR_EVENT?
1648 * If so we can simply poke the RB_WAIT bit
1649 * and break the hang. This should work on
1650 * all but the second generation chipsets.
1652 for_each_ring(ring, dev_priv, i)
1653 hung &= !kick_ring(ring);
1663 * This is called when the chip hasn't reported back with completed
1664 * batchbuffers in a long time. The first time this is called we simply record
1665 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1666 * again, we assume the chip is wedged and try to fix it.
1668 void i915_hangcheck_elapsed(unsigned long data)
1670 struct drm_device *dev = (struct drm_device *)data;
1671 drm_i915_private_t *dev_priv = dev->dev_private;
1672 uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1673 struct intel_ring_buffer *ring;
1674 bool err = false, idle;
1677 if (!i915_enable_hangcheck)
1680 memset(acthd, 0, sizeof(acthd));
1682 for_each_ring(ring, dev_priv, i) {
1683 idle &= i915_hangcheck_ring_idle(ring, &err);
1684 acthd[i] = intel_ring_get_active_head(ring);
1687 /* If all work is done then ACTHD clearly hasn't advanced. */
1690 if (i915_hangcheck_hung(dev))
1696 dev_priv->hangcheck_count = 0;
1700 if (INTEL_INFO(dev)->gen < 4) {
1701 instdone = I915_READ(INSTDONE);
1704 instdone = I915_READ(INSTDONE_I965);
1705 instdone1 = I915_READ(INSTDONE1);
1708 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1709 dev_priv->last_instdone == instdone &&
1710 dev_priv->last_instdone1 == instdone1) {
1711 if (i915_hangcheck_hung(dev))
1714 dev_priv->hangcheck_count = 0;
1716 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1717 dev_priv->last_instdone = instdone;
1718 dev_priv->last_instdone1 = instdone1;
1722 /* Reset timer case chip hangs without another request being added */
1723 mod_timer(&dev_priv->hangcheck_timer,
1724 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1729 static void ironlake_irq_preinstall(struct drm_device *dev)
1731 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1733 atomic_set(&dev_priv->irq_received, 0);
1735 I915_WRITE(HWSTAM, 0xeffe);
1737 /* XXX hotplug from PCH */
1739 I915_WRITE(DEIMR, 0xffffffff);
1740 I915_WRITE(DEIER, 0x0);
1741 POSTING_READ(DEIER);
1744 I915_WRITE(GTIMR, 0xffffffff);
1745 I915_WRITE(GTIER, 0x0);
1746 POSTING_READ(GTIER);
1748 /* south display irq */
1749 I915_WRITE(SDEIMR, 0xffffffff);
1750 I915_WRITE(SDEIER, 0x0);
1751 POSTING_READ(SDEIER);
1754 static void valleyview_irq_preinstall(struct drm_device *dev)
1756 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1759 atomic_set(&dev_priv->irq_received, 0);
1762 I915_WRITE(VLV_IMR, 0);
1763 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1764 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1765 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1768 I915_WRITE(GTIIR, I915_READ(GTIIR));
1769 I915_WRITE(GTIIR, I915_READ(GTIIR));
1770 I915_WRITE(GTIMR, 0xffffffff);
1771 I915_WRITE(GTIER, 0x0);
1772 POSTING_READ(GTIER);
1774 I915_WRITE(DPINVGTT, 0xff);
1776 I915_WRITE(PORT_HOTPLUG_EN, 0);
1777 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1779 I915_WRITE(PIPESTAT(pipe), 0xffff);
1780 I915_WRITE(VLV_IIR, 0xffffffff);
1781 I915_WRITE(VLV_IMR, 0xffffffff);
1782 I915_WRITE(VLV_IER, 0x0);
1783 POSTING_READ(VLV_IER);
1787 * Enable digital hotplug on the PCH, and configure the DP short pulse
1788 * duration to 2ms (which is the minimum in the Display Port spec)
1790 * This register is the same on all known PCH chips.
1793 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1795 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1798 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1799 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1800 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1801 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1802 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1803 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1806 static int ironlake_irq_postinstall(struct drm_device *dev)
1808 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1809 /* enable kind of interrupts always enabled */
1810 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1811 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1815 dev_priv->irq_mask = ~display_mask;
1817 /* should always can generate irq */
1818 I915_WRITE(DEIIR, I915_READ(DEIIR));
1819 I915_WRITE(DEIMR, dev_priv->irq_mask);
1820 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1821 POSTING_READ(DEIER);
1823 dev_priv->gt_irq_mask = ~0;
1825 I915_WRITE(GTIIR, I915_READ(GTIIR));
1826 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1831 GEN6_BSD_USER_INTERRUPT |
1832 GEN6_BLITTER_USER_INTERRUPT;
1837 GT_BSD_USER_INTERRUPT;
1838 I915_WRITE(GTIER, render_irqs);
1839 POSTING_READ(GTIER);
1841 if (HAS_PCH_CPT(dev)) {
1842 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1843 SDE_PORTB_HOTPLUG_CPT |
1844 SDE_PORTC_HOTPLUG_CPT |
1845 SDE_PORTD_HOTPLUG_CPT);
1847 hotplug_mask = (SDE_CRT_HOTPLUG |
1854 dev_priv->pch_irq_mask = ~hotplug_mask;
1856 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1857 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1858 I915_WRITE(SDEIER, hotplug_mask);
1859 POSTING_READ(SDEIER);
1861 ironlake_enable_pch_hotplug(dev);
1863 if (IS_IRONLAKE_M(dev)) {
1864 /* Clear & enable PCU event interrupts */
1865 I915_WRITE(DEIIR, DE_PCU_EVENT);
1866 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1867 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1873 static int ivybridge_irq_postinstall(struct drm_device *dev)
1875 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1876 /* enable kind of interrupts always enabled */
1878 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1879 DE_PLANEC_FLIP_DONE_IVB |
1880 DE_PLANEB_FLIP_DONE_IVB |
1881 DE_PLANEA_FLIP_DONE_IVB;
1885 dev_priv->irq_mask = ~display_mask;
1887 /* should always can generate irq */
1888 I915_WRITE(DEIIR, I915_READ(DEIIR));
1889 I915_WRITE(DEIMR, dev_priv->irq_mask);
1892 DE_PIPEC_VBLANK_IVB |
1893 DE_PIPEB_VBLANK_IVB |
1894 DE_PIPEA_VBLANK_IVB);
1895 POSTING_READ(DEIER);
1897 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1899 I915_WRITE(GTIIR, I915_READ(GTIIR));
1900 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1902 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1903 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1904 I915_WRITE(GTIER, render_irqs);
1905 POSTING_READ(GTIER);
1907 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1908 SDE_PORTB_HOTPLUG_CPT |
1909 SDE_PORTC_HOTPLUG_CPT |
1910 SDE_PORTD_HOTPLUG_CPT);
1911 dev_priv->pch_irq_mask = ~hotplug_mask;
1913 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1914 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1915 I915_WRITE(SDEIER, hotplug_mask);
1916 POSTING_READ(SDEIER);
1918 ironlake_enable_pch_hotplug(dev);
1923 static int valleyview_irq_postinstall(struct drm_device *dev)
1925 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1928 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1931 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1932 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1933 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1935 dev_priv->irq_mask = ~enable_mask;
1937 dev_priv->pipestat[0] = 0;
1938 dev_priv->pipestat[1] = 0;
1940 /* Hack for broken MSIs on VLV */
1941 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1942 pci_read_config_word(dev->pdev, 0x98, &msid);
1943 msid &= 0xff; /* mask out delivery bits */
1945 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1947 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1948 I915_WRITE(VLV_IER, enable_mask);
1949 I915_WRITE(VLV_IIR, 0xffffffff);
1950 I915_WRITE(PIPESTAT(0), 0xffff);
1951 I915_WRITE(PIPESTAT(1), 0xffff);
1952 POSTING_READ(VLV_IER);
1954 I915_WRITE(VLV_IIR, 0xffffffff);
1955 I915_WRITE(VLV_IIR, 0xffffffff);
1957 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1958 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1959 GT_GEN6_BLT_USER_INTERRUPT |
1960 GT_GEN6_BSD_USER_INTERRUPT |
1961 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1962 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1964 GT_RENDER_CS_ERROR_INTERRUPT |
1968 dev_priv->gt_irq_mask = ~render_irqs;
1970 I915_WRITE(GTIIR, I915_READ(GTIIR));
1971 I915_WRITE(GTIIR, I915_READ(GTIIR));
1972 I915_WRITE(GTIMR, 0);
1973 I915_WRITE(GTIER, render_irqs);
1974 POSTING_READ(GTIER);
1976 /* ack & enable invalid PTE error interrupts */
1977 #if 0 /* FIXME: add support to irq handler for checking these bits */
1978 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1979 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1982 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1983 #if 0 /* FIXME: check register definitions; some have moved */
1984 /* Note HDMI and DP share bits */
1985 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1986 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1987 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1988 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1989 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1990 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1991 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1992 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1993 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1994 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1995 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1996 hotplug_en |= CRT_HOTPLUG_INT_EN;
1997 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2001 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2006 static void valleyview_irq_uninstall(struct drm_device *dev)
2008 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2015 I915_WRITE(PIPESTAT(pipe), 0xffff);
2017 I915_WRITE(HWSTAM, 0xffffffff);
2018 I915_WRITE(PORT_HOTPLUG_EN, 0);
2019 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2021 I915_WRITE(PIPESTAT(pipe), 0xffff);
2022 I915_WRITE(VLV_IIR, 0xffffffff);
2023 I915_WRITE(VLV_IMR, 0xffffffff);
2024 I915_WRITE(VLV_IER, 0x0);
2025 POSTING_READ(VLV_IER);
2028 static void ironlake_irq_uninstall(struct drm_device *dev)
2030 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2035 I915_WRITE(HWSTAM, 0xffffffff);
2037 I915_WRITE(DEIMR, 0xffffffff);
2038 I915_WRITE(DEIER, 0x0);
2039 I915_WRITE(DEIIR, I915_READ(DEIIR));
2041 I915_WRITE(GTIMR, 0xffffffff);
2042 I915_WRITE(GTIER, 0x0);
2043 I915_WRITE(GTIIR, I915_READ(GTIIR));
2045 I915_WRITE(SDEIMR, 0xffffffff);
2046 I915_WRITE(SDEIER, 0x0);
2047 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2050 static void i8xx_irq_preinstall(struct drm_device * dev)
2052 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2055 atomic_set(&dev_priv->irq_received, 0);
2058 I915_WRITE(PIPESTAT(pipe), 0);
2059 I915_WRITE16(IMR, 0xffff);
2060 I915_WRITE16(IER, 0x0);
2061 POSTING_READ16(IER);
2064 static int i8xx_irq_postinstall(struct drm_device *dev)
2066 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2068 dev_priv->pipestat[0] = 0;
2069 dev_priv->pipestat[1] = 0;
2072 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2074 /* Unmask the interrupts that we always want on. */
2075 dev_priv->irq_mask =
2076 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2077 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2078 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2079 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2080 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2081 I915_WRITE16(IMR, dev_priv->irq_mask);
2084 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2085 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2086 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2087 I915_USER_INTERRUPT);
2088 POSTING_READ16(IER);
2093 static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2095 struct drm_device *dev = (struct drm_device *) arg;
2096 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2099 unsigned long irqflags;
2103 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2104 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2106 atomic_inc(&dev_priv->irq_received);
2108 iir = I915_READ16(IIR);
2112 while (iir & ~flip_mask) {
2113 /* Can't rely on pipestat interrupt bit in iir as it might
2114 * have been cleared after the pipestat interrupt was received.
2115 * It doesn't set the bit in iir again, but it still produces
2116 * interrupts (for non-MSI).
2118 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2119 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2120 i915_handle_error(dev, false);
2122 for_each_pipe(pipe) {
2123 int reg = PIPESTAT(pipe);
2124 pipe_stats[pipe] = I915_READ(reg);
2127 * Clear the PIPE*STAT regs before the IIR
2129 if (pipe_stats[pipe] & 0x8000ffff) {
2130 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2131 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2133 I915_WRITE(reg, pipe_stats[pipe]);
2137 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2139 I915_WRITE16(IIR, iir & ~flip_mask);
2140 new_iir = I915_READ16(IIR); /* Flush posted writes */
2142 i915_update_dri1_breadcrumb(dev);
2144 if (iir & I915_USER_INTERRUPT)
2145 notify_ring(dev, &dev_priv->ring[RCS]);
2147 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2148 drm_handle_vblank(dev, 0)) {
2149 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2150 intel_prepare_page_flip(dev, 0);
2151 intel_finish_page_flip(dev, 0);
2152 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2156 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2157 drm_handle_vblank(dev, 1)) {
2158 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2159 intel_prepare_page_flip(dev, 1);
2160 intel_finish_page_flip(dev, 1);
2161 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2171 static void i8xx_irq_uninstall(struct drm_device * dev)
2173 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2176 for_each_pipe(pipe) {
2177 /* Clear enable bits; then clear status bits */
2178 I915_WRITE(PIPESTAT(pipe), 0);
2179 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2181 I915_WRITE16(IMR, 0xffff);
2182 I915_WRITE16(IER, 0x0);
2183 I915_WRITE16(IIR, I915_READ16(IIR));
2186 static void i915_irq_preinstall(struct drm_device * dev)
2188 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2191 atomic_set(&dev_priv->irq_received, 0);
2193 if (I915_HAS_HOTPLUG(dev)) {
2194 I915_WRITE(PORT_HOTPLUG_EN, 0);
2195 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2198 I915_WRITE16(HWSTAM, 0xeffe);
2200 I915_WRITE(PIPESTAT(pipe), 0);
2201 I915_WRITE(IMR, 0xffffffff);
2202 I915_WRITE(IER, 0x0);
2206 static int i915_irq_postinstall(struct drm_device *dev)
2208 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2211 dev_priv->pipestat[0] = 0;
2212 dev_priv->pipestat[1] = 0;
2214 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2216 /* Unmask the interrupts that we always want on. */
2217 dev_priv->irq_mask =
2218 ~(I915_ASLE_INTERRUPT |
2219 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2220 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2221 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2222 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2223 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2226 I915_ASLE_INTERRUPT |
2227 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2228 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2229 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2230 I915_USER_INTERRUPT;
2232 if (I915_HAS_HOTPLUG(dev)) {
2233 /* Enable in IER... */
2234 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2235 /* and unmask in IMR */
2236 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2239 I915_WRITE(IMR, dev_priv->irq_mask);
2240 I915_WRITE(IER, enable_mask);
2243 if (I915_HAS_HOTPLUG(dev)) {
2244 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2246 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2247 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2248 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2249 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2250 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2251 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2252 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2253 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2254 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2255 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2256 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2257 hotplug_en |= CRT_HOTPLUG_INT_EN;
2258 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2261 /* Ignore TV since it's buggy */
2263 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2266 intel_opregion_enable_asle(dev);
2271 static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2273 struct drm_device *dev = (struct drm_device *) arg;
2274 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2275 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2276 unsigned long irqflags;
2278 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2279 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2281 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2282 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2284 int pipe, ret = IRQ_NONE;
2286 atomic_inc(&dev_priv->irq_received);
2288 iir = I915_READ(IIR);
2290 bool irq_received = (iir & ~flip_mask) != 0;
2291 bool blc_event = false;
2293 /* Can't rely on pipestat interrupt bit in iir as it might
2294 * have been cleared after the pipestat interrupt was received.
2295 * It doesn't set the bit in iir again, but it still produces
2296 * interrupts (for non-MSI).
2298 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2299 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2300 i915_handle_error(dev, false);
2302 for_each_pipe(pipe) {
2303 int reg = PIPESTAT(pipe);
2304 pipe_stats[pipe] = I915_READ(reg);
2306 /* Clear the PIPE*STAT regs before the IIR */
2307 if (pipe_stats[pipe] & 0x8000ffff) {
2308 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2309 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2311 I915_WRITE(reg, pipe_stats[pipe]);
2312 irq_received = true;
2315 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2320 /* Consume port. Then clear IIR or we'll miss events */
2321 if ((I915_HAS_HOTPLUG(dev)) &&
2322 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2323 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2325 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2327 if (hotplug_status & dev_priv->hotplug_supported_mask)
2328 queue_work(dev_priv->wq,
2329 &dev_priv->hotplug_work);
2331 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2332 POSTING_READ(PORT_HOTPLUG_STAT);
2335 I915_WRITE(IIR, iir & ~flip_mask);
2336 new_iir = I915_READ(IIR); /* Flush posted writes */
2338 if (iir & I915_USER_INTERRUPT)
2339 notify_ring(dev, &dev_priv->ring[RCS]);
2341 for_each_pipe(pipe) {
2345 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2346 drm_handle_vblank(dev, pipe)) {
2347 if (iir & flip[plane]) {
2348 intel_prepare_page_flip(dev, plane);
2349 intel_finish_page_flip(dev, pipe);
2350 flip_mask &= ~flip[plane];
2354 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2358 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2359 intel_opregion_asle_intr(dev);
2361 /* With MSI, interrupts are only generated when iir
2362 * transitions from zero to nonzero. If another bit got
2363 * set while we were handling the existing iir bits, then
2364 * we would never get another interrupt.
2366 * This is fine on non-MSI as well, as if we hit this path
2367 * we avoid exiting the interrupt handler only to generate
2370 * Note that for MSI this could cause a stray interrupt report
2371 * if an interrupt landed in the time between writing IIR and
2372 * the posting read. This should be rare enough to never
2373 * trigger the 99% of 100,000 interrupts test for disabling
2378 } while (iir & ~flip_mask);
2380 i915_update_dri1_breadcrumb(dev);
2385 static void i915_irq_uninstall(struct drm_device * dev)
2387 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2390 if (I915_HAS_HOTPLUG(dev)) {
2391 I915_WRITE(PORT_HOTPLUG_EN, 0);
2392 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2395 I915_WRITE16(HWSTAM, 0xffff);
2396 for_each_pipe(pipe) {
2397 /* Clear enable bits; then clear status bits */
2398 I915_WRITE(PIPESTAT(pipe), 0);
2399 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2401 I915_WRITE(IMR, 0xffffffff);
2402 I915_WRITE(IER, 0x0);
2404 I915_WRITE(IIR, I915_READ(IIR));
2407 static void i965_irq_preinstall(struct drm_device * dev)
2409 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2412 atomic_set(&dev_priv->irq_received, 0);
2414 I915_WRITE(PORT_HOTPLUG_EN, 0);
2415 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2417 I915_WRITE(HWSTAM, 0xeffe);
2419 I915_WRITE(PIPESTAT(pipe), 0);
2420 I915_WRITE(IMR, 0xffffffff);
2421 I915_WRITE(IER, 0x0);
2425 static int i965_irq_postinstall(struct drm_device *dev)
2427 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2432 /* Unmask the interrupts that we always want on. */
2433 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2434 I915_DISPLAY_PORT_INTERRUPT |
2435 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2436 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2437 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2438 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2439 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2441 enable_mask = ~dev_priv->irq_mask;
2442 enable_mask |= I915_USER_INTERRUPT;
2445 enable_mask |= I915_BSD_USER_INTERRUPT;
2447 dev_priv->pipestat[0] = 0;
2448 dev_priv->pipestat[1] = 0;
2451 * Enable some error detection, note the instruction error mask
2452 * bit is reserved, so we leave it masked.
2455 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2456 GM45_ERROR_MEM_PRIV |
2457 GM45_ERROR_CP_PRIV |
2458 I915_ERROR_MEMORY_REFRESH);
2460 error_mask = ~(I915_ERROR_PAGE_TABLE |
2461 I915_ERROR_MEMORY_REFRESH);
2463 I915_WRITE(EMR, error_mask);
2465 I915_WRITE(IMR, dev_priv->irq_mask);
2466 I915_WRITE(IER, enable_mask);
2469 /* Note HDMI and DP share hotplug bits */
2471 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2472 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2473 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2474 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2475 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2476 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2478 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2479 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2480 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2481 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2483 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2484 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2485 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2486 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2488 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2489 hotplug_en |= CRT_HOTPLUG_INT_EN;
2491 /* Programming the CRT detection parameters tends
2492 to generate a spurious hotplug event about three
2493 seconds later. So just do it once.
2496 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2497 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2500 /* Ignore TV since it's buggy */
2502 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2504 intel_opregion_enable_asle(dev);
2509 static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2511 struct drm_device *dev = (struct drm_device *) arg;
2512 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2514 u32 pipe_stats[I915_MAX_PIPES];
2515 unsigned long irqflags;
2517 int ret = IRQ_NONE, pipe;
2519 atomic_inc(&dev_priv->irq_received);
2521 iir = I915_READ(IIR);
2524 bool blc_event = false;
2526 irq_received = iir != 0;
2528 /* Can't rely on pipestat interrupt bit in iir as it might
2529 * have been cleared after the pipestat interrupt was received.
2530 * It doesn't set the bit in iir again, but it still produces
2531 * interrupts (for non-MSI).
2533 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2534 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2535 i915_handle_error(dev, false);
2537 for_each_pipe(pipe) {
2538 int reg = PIPESTAT(pipe);
2539 pipe_stats[pipe] = I915_READ(reg);
2542 * Clear the PIPE*STAT regs before the IIR
2544 if (pipe_stats[pipe] & 0x8000ffff) {
2545 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2546 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2548 I915_WRITE(reg, pipe_stats[pipe]);
2552 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2559 /* Consume port. Then clear IIR or we'll miss events */
2560 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2561 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2563 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2565 if (hotplug_status & dev_priv->hotplug_supported_mask)
2566 queue_work(dev_priv->wq,
2567 &dev_priv->hotplug_work);
2569 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2570 I915_READ(PORT_HOTPLUG_STAT);
2573 I915_WRITE(IIR, iir);
2574 new_iir = I915_READ(IIR); /* Flush posted writes */
2576 if (iir & I915_USER_INTERRUPT)
2577 notify_ring(dev, &dev_priv->ring[RCS]);
2578 if (iir & I915_BSD_USER_INTERRUPT)
2579 notify_ring(dev, &dev_priv->ring[VCS]);
2581 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2582 intel_prepare_page_flip(dev, 0);
2584 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2585 intel_prepare_page_flip(dev, 1);
2587 for_each_pipe(pipe) {
2588 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2589 drm_handle_vblank(dev, pipe)) {
2590 i915_pageflip_stall_check(dev, pipe);
2591 intel_finish_page_flip(dev, pipe);
2594 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2599 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2600 intel_opregion_asle_intr(dev);
2602 /* With MSI, interrupts are only generated when iir
2603 * transitions from zero to nonzero. If another bit got
2604 * set while we were handling the existing iir bits, then
2605 * we would never get another interrupt.
2607 * This is fine on non-MSI as well, as if we hit this path
2608 * we avoid exiting the interrupt handler only to generate
2611 * Note that for MSI this could cause a stray interrupt report
2612 * if an interrupt landed in the time between writing IIR and
2613 * the posting read. This should be rare enough to never
2614 * trigger the 99% of 100,000 interrupts test for disabling
2620 i915_update_dri1_breadcrumb(dev);
2625 static void i965_irq_uninstall(struct drm_device * dev)
2627 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2633 I915_WRITE(PORT_HOTPLUG_EN, 0);
2634 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2636 I915_WRITE(HWSTAM, 0xffffffff);
2638 I915_WRITE(PIPESTAT(pipe), 0);
2639 I915_WRITE(IMR, 0xffffffff);
2640 I915_WRITE(IER, 0x0);
2643 I915_WRITE(PIPESTAT(pipe),
2644 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2645 I915_WRITE(IIR, I915_READ(IIR));
2648 void intel_irq_init(struct drm_device *dev)
2650 struct drm_i915_private *dev_priv = dev->dev_private;
2652 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2653 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2654 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2655 INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
2657 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2658 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2659 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2660 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2661 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2664 if (drm_core_check_feature(dev, DRIVER_MODESET))
2665 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2667 dev->driver->get_vblank_timestamp = NULL;
2668 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2670 if (IS_VALLEYVIEW(dev)) {
2671 dev->driver->irq_handler = valleyview_irq_handler;
2672 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2673 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2674 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2675 dev->driver->enable_vblank = valleyview_enable_vblank;
2676 dev->driver->disable_vblank = valleyview_disable_vblank;
2677 } else if (IS_IVYBRIDGE(dev)) {
2678 /* Share pre & uninstall handlers with ILK/SNB */
2679 dev->driver->irq_handler = ivybridge_irq_handler;
2680 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2681 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2682 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2683 dev->driver->enable_vblank = ivybridge_enable_vblank;
2684 dev->driver->disable_vblank = ivybridge_disable_vblank;
2685 } else if (IS_HASWELL(dev)) {
2686 /* Share interrupts handling with IVB */
2687 dev->driver->irq_handler = ivybridge_irq_handler;
2688 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2689 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2690 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2691 dev->driver->enable_vblank = ivybridge_enable_vblank;
2692 dev->driver->disable_vblank = ivybridge_disable_vblank;
2693 } else if (HAS_PCH_SPLIT(dev)) {
2694 dev->driver->irq_handler = ironlake_irq_handler;
2695 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2696 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2697 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2698 dev->driver->enable_vblank = ironlake_enable_vblank;
2699 dev->driver->disable_vblank = ironlake_disable_vblank;
2701 if (INTEL_INFO(dev)->gen == 2) {
2702 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2703 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2704 dev->driver->irq_handler = i8xx_irq_handler;
2705 dev->driver->irq_uninstall = i8xx_irq_uninstall;
2706 } else if (INTEL_INFO(dev)->gen == 3) {
2707 /* IIR "flip pending" means done if this bit is set */
2708 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2710 dev->driver->irq_preinstall = i915_irq_preinstall;
2711 dev->driver->irq_postinstall = i915_irq_postinstall;
2712 dev->driver->irq_uninstall = i915_irq_uninstall;
2713 dev->driver->irq_handler = i915_irq_handler;
2715 dev->driver->irq_preinstall = i965_irq_preinstall;
2716 dev->driver->irq_postinstall = i965_irq_postinstall;
2717 dev->driver->irq_uninstall = i965_irq_uninstall;
2718 dev->driver->irq_handler = i965_irq_handler;
2720 dev->driver->enable_vblank = i915_enable_vblank;
2721 dev->driver->disable_vblank = i915_disable_vblank;