drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "intel_drv.h"
  38
  39 /* For display hotplug interrupt */
  40 static void
  41 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  42 {
  43         if ((dev_priv->irq_mask & mask) != 0) {
  44                 dev_priv->irq_mask &= ~mask;
  45                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  46                 POSTING_READ(DEIMR);
  47         }
  48 }
  49
  50 static inline void
  51 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  52 {
  53         if ((dev_priv->irq_mask & mask) != mask) {
  54                 dev_priv->irq_mask |= mask;
  55                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  56                 POSTING_READ(DEIMR);
  57         }
  58 }
  59
  60 void
  61 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  62 {
  63         u32 reg = PIPESTAT(pipe);
  64         u32 pipestat = I915_READ(reg) & 0x7fff0000;
  65
  66         if ((pipestat & mask) == mask)
  67                 return;
  68
  69         /* Enable the interrupt, clear any pending status */
  70         pipestat |= mask | (mask >> 16);
  71         I915_WRITE(reg, pipestat);
  72         POSTING_READ(reg);
  73 }
  74
  75 void
  76 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  77 {
  78         u32 reg = PIPESTAT(pipe);
  79         u32 pipestat = I915_READ(reg) & 0x7fff0000;
  80
  81         if ((pipestat & mask) == 0)
  82                 return;
  83
  84         pipestat &= ~mask;
  85         I915_WRITE(reg, pipestat);
  86         POSTING_READ(reg);
  87 }
  88
  89 /**
  90  * intel_enable_asle - enable ASLE interrupt for OpRegion
  91  */
  92 void intel_enable_asle(struct drm_device *dev)
  93 {
  94         drm_i915_private_t *dev_priv = dev->dev_private;
  95         unsigned long irqflags;
  96
  97         /* FIXME: opregion/asle for VLV */
  98         if (IS_VALLEYVIEW(dev))
  99                 return;
 100
 101         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 102
 103         if (HAS_PCH_SPLIT(dev))
 104                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 105         else {
 106                 i915_enable_pipestat(dev_priv, 1,
 107                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 108                 if (INTEL_INFO(dev)->gen >= 4)
 109                         i915_enable_pipestat(dev_priv, 0,
 110                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 111         }
 112
 113         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 114 }
 115
 116 /**
 117  * i915_pipe_enabled - check if a pipe is enabled
 118  * @dev: DRM device
 119  * @pipe: pipe to check
 120  *
 121  * Reading certain registers when the pipe is disabled can hang the chip.
 122  * Use this routine to make sure the PLL is running and the pipe is active
 123  * before reading such registers if unsure.
 124  */
 125 static int
 126 i915_pipe_enabled(struct drm_device *dev, int pipe)
 127 {
 128         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 129         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 130                                                                       pipe);
 131
 132         return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
 133 }
 134
 135 /* Called from drm generic code, passed a 'crtc', which
 136  * we use as a pipe index
 137  */
 138 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 139 {
 140         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 141         unsigned long high_frame;
 142         unsigned long low_frame;
 143         u32 high1, high2, low;
 144
 145         if (!i915_pipe_enabled(dev, pipe)) {
 146                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 147                                 "pipe %c\n", pipe_name(pipe));
 148                 return 0;
 149         }
 150
 151         high_frame = PIPEFRAME(pipe);
 152         low_frame = PIPEFRAMEPIXEL(pipe);
 153
 154         /*
 155          * High & low register fields aren't synchronized, so make sure
 156          * we get a low value that's stable across two reads of the high
 157          * register.
 158          */
 159         do {
 160                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 161                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 162                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 163         } while (high1 != high2);
 164
 165         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 166         low >>= PIPE_FRAME_LOW_SHIFT;
 167         return (high1 << 8) | low;
 168 }
 169
 170 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 171 {
 172         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 173         int reg = PIPE_FRMCOUNT_GM45(pipe);
 174
 175         if (!i915_pipe_enabled(dev, pipe)) {
 176                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 177                                  "pipe %c\n", pipe_name(pipe));
 178                 return 0;
 179         }
 180
 181         return I915_READ(reg);
 182 }
 183
 184 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 185                              int *vpos, int *hpos)
 186 {
 187         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 188         u32 vbl = 0, position = 0;
 189         int vbl_start, vbl_end, htotal, vtotal;
 190         bool in_vbl = true;
 191         int ret = 0;
 192         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 193                                                                       pipe);
 194
 195         if (!i915_pipe_enabled(dev, pipe)) {
 196                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 197                                  "pipe %c\n", pipe_name(pipe));
 198                 return 0;
 199         }
 200
 201         /* Get vtotal. */
 202         vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 203
 204         if (INTEL_INFO(dev)->gen >= 4) {
 205                 /* No obvious pixelcount register. Only query vertical
 206                  * scanout position from Display scan line register.
 207                  */
 208                 position = I915_READ(PIPEDSL(pipe));
 209
 210                 /* Decode into vertical scanout position. Don't have
 211                  * horizontal scanout position.
 212                  */
 213                 *vpos = position & 0x1fff;
 214                 *hpos = 0;
 215         } else {
 216                 /* Have access to pixelcount since start of frame.
 217                  * We can split this into vertical and horizontal
 218                  * scanout position.
 219                  */
 220                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 221
 222                 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 223                 *vpos = position / htotal;
 224                 *hpos = position - (*vpos * htotal);
 225         }
 226
 227         /* Query vblank area. */
 228         vbl = I915_READ(VBLANK(cpu_transcoder));
 229
 230         /* Test position against vblank region. */
 231         vbl_start = vbl & 0x1fff;
 232         vbl_end = (vbl >> 16) & 0x1fff;
 233
 234         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 235                 in_vbl = false;
 236
 237         /* Inside "upper part" of vblank area? Apply corrective offset: */
 238         if (in_vbl && (*vpos >= vbl_start))
 239                 *vpos = *vpos - vtotal;
 240
 241         /* Readouts valid? */
 242         if (vbl > 0)
 243                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 244
 245         /* In vblank? */
 246         if (in_vbl)
 247                 ret |= DRM_SCANOUTPOS_INVBL;
 248
 249         return ret;
 250 }
 251
 252 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 253                               int *max_error,
 254                               struct timeval *vblank_time,
 255                               unsigned flags)
 256 {
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         struct drm_crtc *crtc;
 259
 260         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 261                 DRM_ERROR("Invalid crtc %d\n", pipe);
 262                 return -EINVAL;
 263         }
 264
 265         /* Get drm_crtc to timestamp: */
 266         crtc = intel_get_crtc_for_pipe(dev, pipe);
 267         if (crtc == NULL) {
 268                 DRM_ERROR("Invalid crtc %d\n", pipe);
 269                 return -EINVAL;
 270         }
 271
 272         if (!crtc->enabled) {
 273                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 274                 return -EBUSY;
 275         }
 276
 277         /* Helper routine in DRM core does all the work: */
 278         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 279                                                      vblank_time, flags,
 280                                                      crtc);
 281 }
 282
 283 /*
 284  * Handle hotplug events outside the interrupt handler proper.
 285  */
 286 static void i915_hotplug_work_func(struct work_struct *work)
 287 {
 288         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 289                                                     hotplug_work);
 290         struct drm_device *dev = dev_priv->dev;
 291         struct drm_mode_config *mode_config = &dev->mode_config;
 292         struct intel_encoder *encoder;
 293
 294         /* HPD irq before everything is fully set up. */
 295         if (!dev_priv->enable_hotplug_processing)
 296                 return;
 297
 298         mutex_lock(&mode_config->mutex);
 299         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 300
 301         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 302                 if (encoder->hot_plug)
 303                         encoder->hot_plug(encoder);
 304
 305         mutex_unlock(&mode_config->mutex);
 306
 307         /* Just fire off a uevent and let userspace tell us what to do */
 308         drm_helper_hpd_irq_event(dev);
 309 }
 310
 311 static void ironlake_handle_rps_change(struct drm_device *dev)
 312 {
 313         drm_i915_private_t *dev_priv = dev->dev_private;
 314         u32 busy_up, busy_down, max_avg, min_avg;
 315         u8 new_delay;
 316         unsigned long flags;
 317
 318         spin_lock_irqsave(&mchdev_lock, flags);
 319
 320         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 321
 322         new_delay = dev_priv->ips.cur_delay;
 323
 324         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 325         busy_up = I915_READ(RCPREVBSYTUPAVG);
 326         busy_down = I915_READ(RCPREVBSYTDNAVG);
 327         max_avg = I915_READ(RCBMAXAVG);
 328         min_avg = I915_READ(RCBMINAVG);
 329
 330         /* Handle RCS change request from hw */
 331         if (busy_up > max_avg) {
 332                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 333                         new_delay = dev_priv->ips.cur_delay - 1;
 334                 if (new_delay < dev_priv->ips.max_delay)
 335                         new_delay = dev_priv->ips.max_delay;
 336         } else if (busy_down < min_avg) {
 337                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 338                         new_delay = dev_priv->ips.cur_delay + 1;
 339                 if (new_delay > dev_priv->ips.min_delay)
 340                         new_delay = dev_priv->ips.min_delay;
 341         }
 342
 343         if (ironlake_set_drps(dev, new_delay))
 344                 dev_priv->ips.cur_delay = new_delay;
 345
 346         spin_unlock_irqrestore(&mchdev_lock, flags);
 347
 348         return;
 349 }
 350
 351 static void notify_ring(struct drm_device *dev,
 352                         struct intel_ring_buffer *ring)
 353 {
 354         struct drm_i915_private *dev_priv = dev->dev_private;
 355
 356         if (ring->obj == NULL)
 357                 return;
 358
 359         trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 360
 361         wake_up_all(&ring->irq_queue);
 362         if (i915_enable_hangcheck) {
 363                 dev_priv->gpu_error.hangcheck_count = 0;
 364                 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
 365                           round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
 366         }
 367 }
 368
 369 static void gen6_pm_rps_work(struct work_struct *work)
 370 {
 371         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 372                                                     rps.work);
 373         u32 pm_iir, pm_imr;
 374         u8 new_delay;
 375
 376         spin_lock_irq(&dev_priv->rps.lock);
 377         pm_iir = dev_priv->rps.pm_iir;
 378         dev_priv->rps.pm_iir = 0;
 379         pm_imr = I915_READ(GEN6_PMIMR);
 380         I915_WRITE(GEN6_PMIMR, 0);
 381         spin_unlock_irq(&dev_priv->rps.lock);
 382
 383         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 384                 return;
 385
 386         mutex_lock(&dev_priv->rps.hw_lock);
 387
 388         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 389                 new_delay = dev_priv->rps.cur_delay + 1;
 390         else
 391                 new_delay = dev_priv->rps.cur_delay - 1;
 392
 393         /* sysfs frequency interfaces may have snuck in while servicing the
 394          * interrupt
 395          */
 396         if (!(new_delay > dev_priv->rps.max_delay ||
 397               new_delay < dev_priv->rps.min_delay)) {
 398                 gen6_set_rps(dev_priv->dev, new_delay);
 399         }
 400
 401         mutex_unlock(&dev_priv->rps.hw_lock);
 402 }
 403
 404
 405 /**
 406  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 407  * occurred.
 408  * @work: workqueue struct
 409  *
 410  * Doesn't actually do anything except notify userspace. As a consequence of
 411  * this event, userspace should try to remap the bad rows since statistically
 412  * it is likely the same row is more likely to go bad again.
 413  */
 414 static void ivybridge_parity_work(struct work_struct *work)
 415 {
 416         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 417                                                     l3_parity.error_work);
 418         u32 error_status, row, bank, subbank;
 419         char *parity_event[5];
 420         uint32_t misccpctl;
 421         unsigned long flags;
 422
 423         /* We must turn off DOP level clock gating to access the L3 registers.
 424          * In order to prevent a get/put style interface, acquire struct mutex
 425          * any time we access those registers.
 426          */
 427         mutex_lock(&dev_priv->dev->struct_mutex);
 428
 429         misccpctl = I915_READ(GEN7_MISCCPCTL);
 430         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 431         POSTING_READ(GEN7_MISCCPCTL);
 432
 433         error_status = I915_READ(GEN7_L3CDERRST1);
 434         row = GEN7_PARITY_ERROR_ROW(error_status);
 435         bank = GEN7_PARITY_ERROR_BANK(error_status);
 436         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 437
 438         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 439                                     GEN7_L3CDERRST1_ENABLE);
 440         POSTING_READ(GEN7_L3CDERRST1);
 441
 442         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 443
 444         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 445         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 446         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 447         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 448
 449         mutex_unlock(&dev_priv->dev->struct_mutex);
 450
 451         parity_event[0] = "L3_PARITY_ERROR=1";
 452         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 453         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 454         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 455         parity_event[4] = NULL;
 456
 457         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 458                            KOBJ_CHANGE, parity_event);
 459
 460         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 461                   row, bank, subbank);
 462
 463         kfree(parity_event[3]);
 464         kfree(parity_event[2]);
 465         kfree(parity_event[1]);
 466 }
 467
 468 static void ivybridge_handle_parity_error(struct drm_device *dev)
 469 {
 470         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 471         unsigned long flags;
 472
 473         if (!HAS_L3_GPU_CACHE(dev))
 474                 return;
 475
 476         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 477         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 478         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 479         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 480
 481         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 482 }
 483
 484 static void snb_gt_irq_handler(struct drm_device *dev,
 485                                struct drm_i915_private *dev_priv,
 486                                u32 gt_iir)
 487 {
 488
 489         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 490                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 491                 notify_ring(dev, &dev_priv->ring[RCS]);
 492         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 493                 notify_ring(dev, &dev_priv->ring[VCS]);
 494         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 495                 notify_ring(dev, &dev_priv->ring[BCS]);
 496
 497         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 498                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 499                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 500                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 501                 i915_handle_error(dev, false);
 502         }
 503
 504         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 505                 ivybridge_handle_parity_error(dev);
 506 }
 507
 508 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 509                                 u32 pm_iir)
 510 {
 511         unsigned long flags;
 512
 513         /*
 514          * IIR bits should never already be set because IMR should
 515          * prevent an interrupt from being shown in IIR. The warning
 516          * displays a case where we've unsafely cleared
 517          * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 518          * type is not a problem, it displays a problem in the logic.
 519          *
 520          * The mask bit in IMR is cleared by dev_priv->rps.work.
 521          */
 522
 523         spin_lock_irqsave(&dev_priv->rps.lock, flags);
 524         dev_priv->rps.pm_iir |= pm_iir;
 525         I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 526         POSTING_READ(GEN6_PMIMR);
 527         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 528
 529         queue_work(dev_priv->wq, &dev_priv->rps.work);
 530 }
 531
 532 static void gmbus_irq_handler(struct drm_device *dev)
 533 {
 534         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 535
 536         wake_up_all(&dev_priv->gmbus_wait_queue);
 537 }
 538
 539 static void dp_aux_irq_handler(struct drm_device *dev)
 540 {
 541         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 542
 543         wake_up_all(&dev_priv->gmbus_wait_queue);
 544 }
 545
 546 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 547 {
 548         struct drm_device *dev = (struct drm_device *) arg;
 549         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 550         u32 iir, gt_iir, pm_iir;
 551         irqreturn_t ret = IRQ_NONE;
 552         unsigned long irqflags;
 553         int pipe;
 554         u32 pipe_stats[I915_MAX_PIPES];
 555
 556         atomic_inc(&dev_priv->irq_received);
 557
 558         while (true) {
 559                 iir = I915_READ(VLV_IIR);
 560                 gt_iir = I915_READ(GTIIR);
 561                 pm_iir = I915_READ(GEN6_PMIIR);
 562
 563                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 564                         goto out;
 565
 566                 ret = IRQ_HANDLED;
 567
 568                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 569
 570                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 571                 for_each_pipe(pipe) {
 572                         int reg = PIPESTAT(pipe);
 573                         pipe_stats[pipe] = I915_READ(reg);
 574
 575                         /*
 576                          * Clear the PIPE*STAT regs before the IIR
 577                          */
 578                         if (pipe_stats[pipe] & 0x8000ffff) {
 579                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 580                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 581                                                          pipe_name(pipe));
 582                                 I915_WRITE(reg, pipe_stats[pipe]);
 583                         }
 584                 }
 585                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 586
 587                 for_each_pipe(pipe) {
 588                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 589                                 drm_handle_vblank(dev, pipe);
 590
 591                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 592                                 intel_prepare_page_flip(dev, pipe);
 593                                 intel_finish_page_flip(dev, pipe);
 594                         }
 595                 }
 596
 597                 /* Consume port.  Then clear IIR or we'll miss events */
 598                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 599                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 600
 601                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 602                                          hotplug_status);
 603                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 604                                 queue_work(dev_priv->wq,
 605                                            &dev_priv->hotplug_work);
 606
 607                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 608                         I915_READ(PORT_HOTPLUG_STAT);
 609                 }
 610
 611                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
 612                         gmbus_irq_handler(dev);
 613
 614                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 615                         gen6_queue_rps_work(dev_priv, pm_iir);
 616
 617                 I915_WRITE(GTIIR, gt_iir);
 618                 I915_WRITE(GEN6_PMIIR, pm_iir);
 619                 I915_WRITE(VLV_IIR, iir);
 620         }
 621
 622 out:
 623         return ret;
 624 }
 625
 626 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 627 {
 628         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 629         int pipe;
 630
 631         if (pch_iir & SDE_HOTPLUG_MASK)
 632                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 633
 634         if (pch_iir & SDE_AUDIO_POWER_MASK)
 635                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 636                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 637                                  SDE_AUDIO_POWER_SHIFT);
 638
 639         if (pch_iir & SDE_AUX_MASK)
 640                 dp_aux_irq_handler(dev);
 641
 642         if (pch_iir & SDE_GMBUS)
 643                 gmbus_irq_handler(dev);
 644
 645         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 646                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 647
 648         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 649                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 650
 651         if (pch_iir & SDE_POISON)
 652                 DRM_ERROR("PCH poison interrupt\n");
 653
 654         if (pch_iir & SDE_FDI_MASK)
 655                 for_each_pipe(pipe)
 656                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 657                                          pipe_name(pipe),
 658                                          I915_READ(FDI_RX_IIR(pipe)));
 659
 660         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 661                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 662
 663         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 664                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 665
 666         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 667                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 668         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 669                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 670 }
 671
 672 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 673 {
 674         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 675         int pipe;
 676
 677         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 678                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 679
 680         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 681                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 682                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 683                                  SDE_AUDIO_POWER_SHIFT_CPT);
 684
 685         if (pch_iir & SDE_AUX_MASK_CPT)
 686                 dp_aux_irq_handler(dev);
 687
 688         if (pch_iir & SDE_GMBUS_CPT)
 689                 gmbus_irq_handler(dev);
 690
 691         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 692                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 693
 694         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 695                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 696
 697         if (pch_iir & SDE_FDI_MASK_CPT)
 698                 for_each_pipe(pipe)
 699                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 700                                          pipe_name(pipe),
 701                                          I915_READ(FDI_RX_IIR(pipe)));
 702 }
 703
 704 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 705 {
 706         struct drm_device *dev = (struct drm_device *) arg;
 707         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 708         u32 de_iir, gt_iir, de_ier, pm_iir;
 709         irqreturn_t ret = IRQ_NONE;
 710         int i;
 711
 712         atomic_inc(&dev_priv->irq_received);
 713
 714         /* disable master interrupt before clearing iir  */
 715         de_ier = I915_READ(DEIER);
 716         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 717
 718         gt_iir = I915_READ(GTIIR);
 719         if (gt_iir) {
 720                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 721                 I915_WRITE(GTIIR, gt_iir);
 722                 ret = IRQ_HANDLED;
 723         }
 724
 725         de_iir = I915_READ(DEIIR);
 726         if (de_iir) {
 727                 if (de_iir & DE_AUX_CHANNEL_A_IVB)
 728                         dp_aux_irq_handler(dev);
 729
 730                 if (de_iir & DE_GSE_IVB)
 731                         intel_opregion_gse_intr(dev);
 732
 733                 for (i = 0; i < 3; i++) {
 734                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 735                                 drm_handle_vblank(dev, i);
 736                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 737                                 intel_prepare_page_flip(dev, i);
 738                                 intel_finish_page_flip_plane(dev, i);
 739                         }
 740                 }
 741
 742                 /* check event from PCH */
 743                 if (de_iir & DE_PCH_EVENT_IVB) {
 744                         u32 pch_iir = I915_READ(SDEIIR);
 745
 746                         cpt_irq_handler(dev, pch_iir);
 747
 748                         /* clear PCH hotplug event before clear CPU irq */
 749                         I915_WRITE(SDEIIR, pch_iir);
 750                 }
 751
 752                 I915_WRITE(DEIIR, de_iir);
 753                 ret = IRQ_HANDLED;
 754         }
 755
 756         pm_iir = I915_READ(GEN6_PMIIR);
 757         if (pm_iir) {
 758                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 759                         gen6_queue_rps_work(dev_priv, pm_iir);
 760                 I915_WRITE(GEN6_PMIIR, pm_iir);
 761                 ret = IRQ_HANDLED;
 762         }
 763
 764         I915_WRITE(DEIER, de_ier);
 765         POSTING_READ(DEIER);
 766
 767         return ret;
 768 }
 769
 770 static void ilk_gt_irq_handler(struct drm_device *dev,
 771                                struct drm_i915_private *dev_priv,
 772                                u32 gt_iir)
 773 {
 774         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 775                 notify_ring(dev, &dev_priv->ring[RCS]);
 776         if (gt_iir & GT_BSD_USER_INTERRUPT)
 777                 notify_ring(dev, &dev_priv->ring[VCS]);
 778 }
 779
 780 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 781 {
 782         struct drm_device *dev = (struct drm_device *) arg;
 783         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 784         int ret = IRQ_NONE;
 785         u32 de_iir, gt_iir, de_ier, pm_iir;
 786
 787         atomic_inc(&dev_priv->irq_received);
 788
 789         /* disable master interrupt before clearing iir  */
 790         de_ier = I915_READ(DEIER);
 791         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 792         POSTING_READ(DEIER);
 793
 794         de_iir = I915_READ(DEIIR);
 795         gt_iir = I915_READ(GTIIR);
 796         pm_iir = I915_READ(GEN6_PMIIR);
 797
 798         if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
 799                 goto done;
 800
 801         ret = IRQ_HANDLED;
 802
 803         if (IS_GEN5(dev))
 804                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 805         else
 806                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 807
 808         if (de_iir & DE_AUX_CHANNEL_A)
 809                 dp_aux_irq_handler(dev);
 810
 811         if (de_iir & DE_GSE)
 812                 intel_opregion_gse_intr(dev);
 813
 814         if (de_iir & DE_PIPEA_VBLANK)
 815                 drm_handle_vblank(dev, 0);
 816
 817         if (de_iir & DE_PIPEB_VBLANK)
 818                 drm_handle_vblank(dev, 1);
 819
 820         if (de_iir & DE_PLANEA_FLIP_DONE) {
 821                 intel_prepare_page_flip(dev, 0);
 822                 intel_finish_page_flip_plane(dev, 0);
 823         }
 824
 825         if (de_iir & DE_PLANEB_FLIP_DONE) {
 826                 intel_prepare_page_flip(dev, 1);
 827                 intel_finish_page_flip_plane(dev, 1);
 828         }
 829
 830         /* check event from PCH */
 831         if (de_iir & DE_PCH_EVENT) {
 832                 u32 pch_iir = I915_READ(SDEIIR);
 833
 834                 if (HAS_PCH_CPT(dev))
 835                         cpt_irq_handler(dev, pch_iir);
 836                 else
 837                         ibx_irq_handler(dev, pch_iir);
 838
 839                 /* should clear PCH hotplug event before clear CPU irq */
 840                 I915_WRITE(SDEIIR, pch_iir);
 841         }
 842
 843         if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
 844                 ironlake_handle_rps_change(dev);
 845
 846         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 847                 gen6_queue_rps_work(dev_priv, pm_iir);
 848
 849         I915_WRITE(GTIIR, gt_iir);
 850         I915_WRITE(DEIIR, de_iir);
 851         I915_WRITE(GEN6_PMIIR, pm_iir);
 852
 853 done:
 854         I915_WRITE(DEIER, de_ier);
 855         POSTING_READ(DEIER);
 856
 857         return ret;
 858 }
 859
 860 /**
 861  * i915_error_work_func - do process context error handling work
 862  * @work: work struct
 863  *
 864  * Fire an error uevent so userspace can see that a hang or error
 865  * was detected.
 866  */
 867 static void i915_error_work_func(struct work_struct *work)
 868 {
 869         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
 870                                                     work);
 871         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
 872                                                     gpu_error);
 873         struct drm_device *dev = dev_priv->dev;
 874         struct intel_ring_buffer *ring;
 875         char *error_event[] = { "ERROR=1", NULL };
 876         char *reset_event[] = { "RESET=1", NULL };
 877         char *reset_done_event[] = { "ERROR=0", NULL };
 878         int i, ret;
 879
 880         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 881
 882         /*
 883          * Note that there's only one work item which does gpu resets, so we
 884          * need not worry about concurrent gpu resets potentially incrementing
 885          * error->reset_counter twice. We only need to take care of another
 886          * racing irq/hangcheck declaring the gpu dead for a second time. A
 887          * quick check for that is good enough: schedule_work ensures the
 888          * correct ordering between hang detection and this work item, and since
 889          * the reset in-progress bit is only ever set by code outside of this
 890          * work we don't need to worry about any other races.
 891          */
 892         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
 893                 DRM_DEBUG_DRIVER("resetting chip\n");
 894                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
 895                                    reset_event);
 896
 897                 ret = i915_reset(dev);
 898
 899                 if (ret == 0) {
 900                         /*
 901                          * After all the gem state is reset, increment the reset
 902                          * counter and wake up everyone waiting for the reset to
 903                          * complete.
 904                          *
 905                          * Since unlock operations are a one-sided barrier only,
 906                          * we need to insert a barrier here to order any seqno
 907                          * updates before
 908                          * the counter increment.
 909                          */
 910                         smp_mb__before_atomic_inc();
 911                         atomic_inc(&dev_priv->gpu_error.reset_counter);
 912
 913                         kobject_uevent_env(&dev->primary->kdev.kobj,
 914                                            KOBJ_CHANGE, reset_done_event);
 915                 } else {
 916                         atomic_set(&error->reset_counter, I915_WEDGED);
 917                 }
 918
 919                 for_each_ring(ring, dev_priv, i)
 920                         wake_up_all(&ring->irq_queue);
 921
 922                 intel_display_handle_reset(dev);
 923
 924                 wake_up_all(&dev_priv->gpu_error.reset_queue);
 925         }
 926 }
 927
 928 /* NB: please notice the memset */
 929 static void i915_get_extra_instdone(struct drm_device *dev,
 930                                     uint32_t *instdone)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
 934
 935         switch(INTEL_INFO(dev)->gen) {
 936         case 2:
 937         case 3:
 938                 instdone[0] = I915_READ(INSTDONE);
 939                 break;
 940         case 4:
 941         case 5:
 942         case 6:
 943                 instdone[0] = I915_READ(INSTDONE_I965);
 944                 instdone[1] = I915_READ(INSTDONE1);
 945                 break;
 946         default:
 947                 WARN_ONCE(1, "Unsupported platform\n");
 948         case 7:
 949                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
 950                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
 951                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
 952                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
 953                 break;
 954         }
 955 }
 956
 957 #ifdef CONFIG_DEBUG_FS
 958 static struct drm_i915_error_object *
 959 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
 960                                struct drm_i915_gem_object *src,
 961                                const int num_pages)
 962 {
 963         struct drm_i915_error_object *dst;
 964         int i;
 965         u32 reloc_offset;
 966
 967         if (src == NULL || src->pages == NULL)
 968                 return NULL;
 969
 970         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
 971         if (dst == NULL)
 972                 return NULL;
 973
 974         reloc_offset = src->gtt_offset;
 975         for (i = 0; i < num_pages; i++) {
 976                 unsigned long flags;
 977                 void *d;
 978
 979                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 980                 if (d == NULL)
 981                         goto unwind;
 982
 983                 local_irq_save(flags);
 984                 if (reloc_offset < dev_priv->gtt.mappable_end &&
 985                     src->has_global_gtt_mapping) {
 986                         void __iomem *s;
 987
 988                         /* Simply ignore tiling or any overlapping fence.
 989                          * It's part of the error state, and this hopefully
 990                          * captures what the GPU read.
 991                          */
 992
 993                         s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
 994                                                      reloc_offset);
 995                         memcpy_fromio(d, s, PAGE_SIZE);
 996                         io_mapping_unmap_atomic(s);
 997                 } else if (src->stolen) {
 998                         unsigned long offset;
 999
1000                         offset = dev_priv->mm.stolen_base;
1001                         offset += src->stolen->start;
1002                         offset += i << PAGE_SHIFT;
1003
1004                         memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1005                 } else {
1006                         struct page *page;
1007                         void *s;
1008
1009                         page = i915_gem_object_get_page(src, i);
1010
1011                         drm_clflush_pages(&page, 1);
1012
1013                         s = kmap_atomic(page);
1014                         memcpy(d, s, PAGE_SIZE);
1015                         kunmap_atomic(s);
1016
1017                         drm_clflush_pages(&page, 1);
1018                 }
1019                 local_irq_restore(flags);
1020
1021                 dst->pages[i] = d;
1022
1023                 reloc_offset += PAGE_SIZE;
1024         }
1025         dst->page_count = num_pages;
1026         dst->gtt_offset = src->gtt_offset;
1027
1028         return dst;
1029
1030 unwind:
1031         while (i--)
1032                 kfree(dst->pages[i]);
1033         kfree(dst);
1034         return NULL;
1035 }
1036 #define i915_error_object_create(dev_priv, src) \
1037         i915_error_object_create_sized((dev_priv), (src), \
1038                                        (src)->base.size>>PAGE_SHIFT)
1039
1040 static void
1041 i915_error_object_free(struct drm_i915_error_object *obj)
1042 {
1043         int page;
1044
1045         if (obj == NULL)
1046                 return;
1047
1048         for (page = 0; page < obj->page_count; page++)
1049                 kfree(obj->pages[page]);
1050
1051         kfree(obj);
1052 }
1053
1054 void
1055 i915_error_state_free(struct kref *error_ref)
1056 {
1057         struct drm_i915_error_state *error = container_of(error_ref,
1058                                                           typeof(*error), ref);
1059         int i;
1060
1061         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1062                 i915_error_object_free(error->ring[i].batchbuffer);
1063                 i915_error_object_free(error->ring[i].ringbuffer);
1064                 kfree(error->ring[i].requests);
1065         }
1066
1067         kfree(error->active_bo);
1068         kfree(error->overlay);
1069         kfree(error);
1070 }
1071 static void capture_bo(struct drm_i915_error_buffer *err,
1072                        struct drm_i915_gem_object *obj)
1073 {
1074         err->size = obj->base.size;
1075         err->name = obj->base.name;
1076         err->rseqno = obj->last_read_seqno;
1077         err->wseqno = obj->last_write_seqno;
1078         err->gtt_offset = obj->gtt_offset;
1079         err->read_domains = obj->base.read_domains;
1080         err->write_domain = obj->base.write_domain;
1081         err->fence_reg = obj->fence_reg;
1082         err->pinned = 0;
1083         if (obj->pin_count > 0)
1084                 err->pinned = 1;
1085         if (obj->user_pin_count > 0)
1086                 err->pinned = -1;
1087         err->tiling = obj->tiling_mode;
1088         err->dirty = obj->dirty;
1089         err->purgeable = obj->madv != I915_MADV_WILLNEED;
1090         err->ring = obj->ring ? obj->ring->id : -1;
1091         err->cache_level = obj->cache_level;
1092 }
1093
1094 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1095                              int count, struct list_head *head)
1096 {
1097         struct drm_i915_gem_object *obj;
1098         int i = 0;
1099
1100         list_for_each_entry(obj, head, mm_list) {
1101                 capture_bo(err++, obj);
1102                 if (++i == count)
1103                         break;
1104         }
1105
1106         return i;
1107 }
1108
1109 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1110                              int count, struct list_head *head)
1111 {
1112         struct drm_i915_gem_object *obj;
1113         int i = 0;
1114
1115         list_for_each_entry(obj, head, gtt_list) {
1116                 if (obj->pin_count == 0)
1117                         continue;
1118
1119                 capture_bo(err++, obj);
1120                 if (++i == count)
1121                         break;
1122         }
1123
1124         return i;
1125 }
1126
1127 static void i915_gem_record_fences(struct drm_device *dev,
1128                                    struct drm_i915_error_state *error)
1129 {
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131         int i;
1132
1133         /* Fences */
1134         switch (INTEL_INFO(dev)->gen) {
1135         case 7:
1136         case 6:
1137                 for (i = 0; i < 16; i++)
1138                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1139                 break;
1140         case 5:
1141         case 4:
1142                 for (i = 0; i < 16; i++)
1143                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1144                 break;
1145         case 3:
1146                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1147                         for (i = 0; i < 8; i++)
1148                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1149         case 2:
1150                 for (i = 0; i < 8; i++)
1151                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1152                 break;
1153
1154         default:
1155                 BUG();
1156         }
1157 }
1158
1159 static struct drm_i915_error_object *
1160 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1161                              struct intel_ring_buffer *ring)
1162 {
1163         struct drm_i915_gem_object *obj;
1164         u32 seqno;
1165
1166         if (!ring->get_seqno)
1167                 return NULL;
1168
1169         if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1170                 u32 acthd = I915_READ(ACTHD);
1171
1172                 if (WARN_ON(ring->id != RCS))
1173                         return NULL;
1174
1175                 obj = ring->private;
1176                 if (acthd >= obj->gtt_offset &&
1177                     acthd < obj->gtt_offset + obj->base.size)
1178                         return i915_error_object_create(dev_priv, obj);
1179         }
1180
1181         seqno = ring->get_seqno(ring, false);
1182         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1183                 if (obj->ring != ring)
1184                         continue;
1185
1186                 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1187                         continue;
1188
1189                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1190                         continue;
1191
1192                 /* We need to copy these to an anonymous buffer as the simplest
1193                  * method to avoid being overwritten by userspace.
1194                  */
1195                 return i915_error_object_create(dev_priv, obj);
1196         }
1197
1198         return NULL;
1199 }
1200
1201 static void i915_record_ring_state(struct drm_device *dev,
1202                                    struct drm_i915_error_state *error,
1203                                    struct intel_ring_buffer *ring)
1204 {
1205         struct drm_i915_private *dev_priv = dev->dev_private;
1206
1207         if (INTEL_INFO(dev)->gen >= 6) {
1208                 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1209                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1210                 error->semaphore_mboxes[ring->id][0]
1211                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1212                 error->semaphore_mboxes[ring->id][1]
1213                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1214                 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1215                 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1216         }
1217
1218         if (INTEL_INFO(dev)->gen >= 4) {
1219                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1220                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1221                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1222                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1223                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1224                 if (ring->id == RCS)
1225                         error->bbaddr = I915_READ64(BB_ADDR);
1226         } else {
1227                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1228                 error->ipeir[ring->id] = I915_READ(IPEIR);
1229                 error->ipehr[ring->id] = I915_READ(IPEHR);
1230                 error->instdone[ring->id] = I915_READ(INSTDONE);
1231         }
1232
1233         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1234         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1235         error->seqno[ring->id] = ring->get_seqno(ring, false);
1236         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1237         error->head[ring->id] = I915_READ_HEAD(ring);
1238         error->tail[ring->id] = I915_READ_TAIL(ring);
1239         error->ctl[ring->id] = I915_READ_CTL(ring);
1240
1241         error->cpu_ring_head[ring->id] = ring->head;
1242         error->cpu_ring_tail[ring->id] = ring->tail;
1243 }
1244
1245
1246 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1247                                            struct drm_i915_error_state *error,
1248                                            struct drm_i915_error_ring *ering)
1249 {
1250         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1251         struct drm_i915_gem_object *obj;
1252
1253         /* Currently render ring is the only HW context user */
1254         if (ring->id != RCS || !error->ccid)
1255                 return;
1256
1257         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1258                 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1259                         ering->ctx = i915_error_object_create_sized(dev_priv,
1260                                                                     obj, 1);
1261                 }
1262         }
1263 }
1264
1265 static void i915_gem_record_rings(struct drm_device *dev,
1266                                   struct drm_i915_error_state *error)
1267 {
1268         struct drm_i915_private *dev_priv = dev->dev_private;
1269         struct intel_ring_buffer *ring;
1270         struct drm_i915_gem_request *request;
1271         int i, count;
1272
1273         for_each_ring(ring, dev_priv, i) {
1274                 i915_record_ring_state(dev, error, ring);
1275
1276                 error->ring[i].batchbuffer =
1277                         i915_error_first_batchbuffer(dev_priv, ring);
1278
1279                 error->ring[i].ringbuffer =
1280                         i915_error_object_create(dev_priv, ring->obj);
1281
1282
1283                 i915_gem_record_active_context(ring, error, &error->ring[i]);
1284
1285                 count = 0;
1286                 list_for_each_entry(request, &ring->request_list, list)
1287                         count++;
1288
1289                 error->ring[i].num_requests = count;
1290                 error->ring[i].requests =
1291                         kmalloc(count*sizeof(struct drm_i915_error_request),
1292                                 GFP_ATOMIC);
1293                 if (error->ring[i].requests == NULL) {
1294                         error->ring[i].num_requests = 0;
1295                         continue;
1296                 }
1297
1298                 count = 0;
1299                 list_for_each_entry(request, &ring->request_list, list) {
1300                         struct drm_i915_error_request *erq;
1301
1302                         erq = &error->ring[i].requests[count++];
1303                         erq->seqno = request->seqno;
1304                         erq->jiffies = request->emitted_jiffies;
1305                         erq->tail = request->tail;
1306                 }
1307         }
1308 }
1309
1310 /**
1311  * i915_capture_error_state - capture an error record for later analysis
1312  * @dev: drm device
1313  *
1314  * Should be called when an error is detected (either a hang or an error
1315  * interrupt) to capture error state from the time of the error.  Fills
1316  * out a structure which becomes available in debugfs for user level tools
1317  * to pick up.
1318  */
1319 static void i915_capture_error_state(struct drm_device *dev)
1320 {
1321         struct drm_i915_private *dev_priv = dev->dev_private;
1322         struct drm_i915_gem_object *obj;
1323         struct drm_i915_error_state *error;
1324         unsigned long flags;
1325         int i, pipe;
1326
1327         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1328         error = dev_priv->gpu_error.first_error;
1329         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1330         if (error)
1331                 return;
1332
1333         /* Account for pipe specific data like PIPE*STAT */
1334         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1335         if (!error) {
1336                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1337                 return;
1338         }
1339
1340         DRM_INFO("capturing error event; look for more information in "
1341                  "/sys/kernel/debug/dri/%d/i915_error_state\n",
1342                  dev->primary->index);
1343
1344         kref_init(&error->ref);
1345         error->eir = I915_READ(EIR);
1346         error->pgtbl_er = I915_READ(PGTBL_ER);
1347         if (HAS_HW_CONTEXTS(dev))
1348                 error->ccid = I915_READ(CCID);
1349
1350         if (HAS_PCH_SPLIT(dev))
1351                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1352         else if (IS_VALLEYVIEW(dev))
1353                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1354         else if (IS_GEN2(dev))
1355                 error->ier = I915_READ16(IER);
1356         else
1357                 error->ier = I915_READ(IER);
1358
1359         if (INTEL_INFO(dev)->gen >= 6)
1360                 error->derrmr = I915_READ(DERRMR);
1361
1362         if (IS_VALLEYVIEW(dev))
1363                 error->forcewake = I915_READ(FORCEWAKE_VLV);
1364         else if (INTEL_INFO(dev)->gen >= 7)
1365                 error->forcewake = I915_READ(FORCEWAKE_MT);
1366         else if (INTEL_INFO(dev)->gen == 6)
1367                 error->forcewake = I915_READ(FORCEWAKE);
1368
1369         for_each_pipe(pipe)
1370                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1371
1372         if (INTEL_INFO(dev)->gen >= 6) {
1373                 error->error = I915_READ(ERROR_GEN6);
1374                 error->done_reg = I915_READ(DONE_REG);
1375         }
1376
1377         if (INTEL_INFO(dev)->gen == 7)
1378                 error->err_int = I915_READ(GEN7_ERR_INT);
1379
1380         i915_get_extra_instdone(dev, error->extra_instdone);
1381
1382         i915_gem_record_fences(dev, error);
1383         i915_gem_record_rings(dev, error);
1384
1385         /* Record buffers on the active and pinned lists. */
1386         error->active_bo = NULL;
1387         error->pinned_bo = NULL;
1388
1389         i = 0;
1390         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1391                 i++;
1392         error->active_bo_count = i;
1393         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1394                 if (obj->pin_count)
1395                         i++;
1396         error->pinned_bo_count = i - error->active_bo_count;
1397
1398         error->active_bo = NULL;
1399         error->pinned_bo = NULL;
1400         if (i) {
1401                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1402                                            GFP_ATOMIC);
1403                 if (error->active_bo)
1404                         error->pinned_bo =
1405                                 error->active_bo + error->active_bo_count;
1406         }
1407
1408         if (error->active_bo)
1409                 error->active_bo_count =
1410                         capture_active_bo(error->active_bo,
1411                                           error->active_bo_count,
1412                                           &dev_priv->mm.active_list);
1413
1414         if (error->pinned_bo)
1415                 error->pinned_bo_count =
1416                         capture_pinned_bo(error->pinned_bo,
1417                                           error->pinned_bo_count,
1418                                           &dev_priv->mm.bound_list);
1419
1420         do_gettimeofday(&error->time);
1421
1422         error->overlay = intel_overlay_capture_error_state(dev);
1423         error->display = intel_display_capture_error_state(dev);
1424
1425         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1426         if (dev_priv->gpu_error.first_error == NULL) {
1427                 dev_priv->gpu_error.first_error = error;
1428                 error = NULL;
1429         }
1430         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1431
1432         if (error)
1433                 i915_error_state_free(&error->ref);
1434 }
1435
1436 void i915_destroy_error_state(struct drm_device *dev)
1437 {
1438         struct drm_i915_private *dev_priv = dev->dev_private;
1439         struct drm_i915_error_state *error;
1440         unsigned long flags;
1441
1442         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1443         error = dev_priv->gpu_error.first_error;
1444         dev_priv->gpu_error.first_error = NULL;
1445         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1446
1447         if (error)
1448                 kref_put(&error->ref, i915_error_state_free);
1449 }
1450 #else
1451 #define i915_capture_error_state(x)
1452 #endif
1453
1454 static void i915_report_and_clear_eir(struct drm_device *dev)
1455 {
1456         struct drm_i915_private *dev_priv = dev->dev_private;
1457         uint32_t instdone[I915_NUM_INSTDONE_REG];
1458         u32 eir = I915_READ(EIR);
1459         int pipe, i;
1460
1461         if (!eir)
1462                 return;
1463
1464         pr_err("render error detected, EIR: 0x%08x\n", eir);
1465
1466         i915_get_extra_instdone(dev, instdone);
1467
1468         if (IS_G4X(dev)) {
1469                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1470                         u32 ipeir = I915_READ(IPEIR_I965);
1471
1472                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1473                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1474                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1475                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1476                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1477                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1478                         I915_WRITE(IPEIR_I965, ipeir);
1479                         POSTING_READ(IPEIR_I965);
1480                 }
1481                 if (eir & GM45_ERROR_PAGE_TABLE) {
1482                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1483                         pr_err("page table error\n");
1484                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1485                         I915_WRITE(PGTBL_ER, pgtbl_err);
1486                         POSTING_READ(PGTBL_ER);
1487                 }
1488         }
1489
1490         if (!IS_GEN2(dev)) {
1491                 if (eir & I915_ERROR_PAGE_TABLE) {
1492                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1493                         pr_err("page table error\n");
1494                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1495                         I915_WRITE(PGTBL_ER, pgtbl_err);
1496                         POSTING_READ(PGTBL_ER);
1497                 }
1498         }
1499
1500         if (eir & I915_ERROR_MEMORY_REFRESH) {
1501                 pr_err("memory refresh error:\n");
1502                 for_each_pipe(pipe)
1503                         pr_err("pipe %c stat: 0x%08x\n",
1504                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1505                 /* pipestat has already been acked */
1506         }
1507         if (eir & I915_ERROR_INSTRUCTION) {
1508                 pr_err("instruction error\n");
1509                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1510                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1511                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1512                 if (INTEL_INFO(dev)->gen < 4) {
1513                         u32 ipeir = I915_READ(IPEIR);
1514
1515                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1516                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1517                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1518                         I915_WRITE(IPEIR, ipeir);
1519                         POSTING_READ(IPEIR);
1520                 } else {
1521                         u32 ipeir = I915_READ(IPEIR_I965);
1522
1523                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1524                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1525                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1526                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1527                         I915_WRITE(IPEIR_I965, ipeir);
1528                         POSTING_READ(IPEIR_I965);
1529                 }
1530         }
1531
1532         I915_WRITE(EIR, eir);
1533         POSTING_READ(EIR);
1534         eir = I915_READ(EIR);
1535         if (eir) {
1536                 /*
1537                  * some errors might have become stuck,
1538                  * mask them.
1539                  */
1540                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1541                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1542                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1543         }
1544 }
1545
1546 /**
1547  * i915_handle_error - handle an error interrupt
1548  * @dev: drm device
1549  *
1550  * Do some basic checking of regsiter state at error interrupt time and
1551  * dump it to the syslog.  Also call i915_capture_error_state() to make
1552  * sure we get a record and make it available in debugfs.  Fire a uevent
1553  * so userspace knows something bad happened (should trigger collection
1554  * of a ring dump etc.).
1555  */
1556 void i915_handle_error(struct drm_device *dev, bool wedged)
1557 {
1558         struct drm_i915_private *dev_priv = dev->dev_private;
1559         struct intel_ring_buffer *ring;
1560         int i;
1561
1562         i915_capture_error_state(dev);
1563         i915_report_and_clear_eir(dev);
1564
1565         if (wedged) {
1566                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1567                                 &dev_priv->gpu_error.reset_counter);
1568
1569                 /*
1570                  * Wakeup waiting processes so that the reset work item
1571                  * doesn't deadlock trying to grab various locks.
1572                  */
1573                 for_each_ring(ring, dev_priv, i)
1574                         wake_up_all(&ring->irq_queue);
1575         }
1576
1577         queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
1578 }
1579
1580 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1581 {
1582         drm_i915_private_t *dev_priv = dev->dev_private;
1583         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1585         struct drm_i915_gem_object *obj;
1586         struct intel_unpin_work *work;
1587         unsigned long flags;
1588         bool stall_detected;
1589
1590         /* Ignore early vblank irqs */
1591         if (intel_crtc == NULL)
1592                 return;
1593
1594         spin_lock_irqsave(&dev->event_lock, flags);
1595         work = intel_crtc->unpin_work;
1596
1597         if (work == NULL ||
1598             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1599             !work->enable_stall_check) {
1600                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1601                 spin_unlock_irqrestore(&dev->event_lock, flags);
1602                 return;
1603         }
1604
1605         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1606         obj = work->pending_flip_obj;
1607         if (INTEL_INFO(dev)->gen >= 4) {
1608                 int dspsurf = DSPSURF(intel_crtc->plane);
1609                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1610                                         obj->gtt_offset;
1611         } else {
1612                 int dspaddr = DSPADDR(intel_crtc->plane);
1613                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1614                                                         crtc->y * crtc->fb->pitches[0] +
1615                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1616         }
1617
1618         spin_unlock_irqrestore(&dev->event_lock, flags);
1619
1620         if (stall_detected) {
1621                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1622                 intel_prepare_page_flip(dev, intel_crtc->plane);
1623         }
1624 }
1625
1626 /* Called from drm generic code, passed 'crtc' which
1627  * we use as a pipe index
1628  */
1629 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1630 {
1631         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1632         unsigned long irqflags;
1633
1634         if (!i915_pipe_enabled(dev, pipe))
1635                 return -EINVAL;
1636
1637         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1638         if (INTEL_INFO(dev)->gen >= 4)
1639                 i915_enable_pipestat(dev_priv, pipe,
1640                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1641         else
1642                 i915_enable_pipestat(dev_priv, pipe,
1643                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1644
1645         /* maintain vblank delivery even in deep C-states */
1646         if (dev_priv->info->gen == 3)
1647                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1648         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1649
1650         return 0;
1651 }
1652
1653 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1654 {
1655         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1656         unsigned long irqflags;
1657
1658         if (!i915_pipe_enabled(dev, pipe))
1659                 return -EINVAL;
1660
1661         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1662         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1663                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1664         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1665
1666         return 0;
1667 }
1668
1669 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1670 {
1671         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1672         unsigned long irqflags;
1673
1674         if (!i915_pipe_enabled(dev, pipe))
1675                 return -EINVAL;
1676
1677         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1678         ironlake_enable_display_irq(dev_priv,
1679                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1680         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1681
1682         return 0;
1683 }
1684
1685 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1686 {
1687         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1688         unsigned long irqflags;
1689         u32 imr;
1690
1691         if (!i915_pipe_enabled(dev, pipe))
1692                 return -EINVAL;
1693
1694         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1695         imr = I915_READ(VLV_IMR);
1696         if (pipe == 0)
1697                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1698         else
1699                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1700         I915_WRITE(VLV_IMR, imr);
1701         i915_enable_pipestat(dev_priv, pipe,
1702                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1703         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1704
1705         return 0;
1706 }
1707
1708 /* Called from drm generic code, passed 'crtc' which
1709  * we use as a pipe index
1710  */
1711 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1712 {
1713         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1714         unsigned long irqflags;
1715
1716         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1717         if (dev_priv->info->gen == 3)
1718                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1719
1720         i915_disable_pipestat(dev_priv, pipe,
1721                               PIPE_VBLANK_INTERRUPT_ENABLE |
1722                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1723         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1724 }
1725
1726 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1727 {
1728         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1729         unsigned long irqflags;
1730
1731         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1732         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1733                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1734         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1735 }
1736
1737 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1738 {
1739         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1740         unsigned long irqflags;
1741
1742         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1743         ironlake_disable_display_irq(dev_priv,
1744                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1745         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1746 }
1747
1748 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1749 {
1750         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1751         unsigned long irqflags;
1752         u32 imr;
1753
1754         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1755         i915_disable_pipestat(dev_priv, pipe,
1756                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1757         imr = I915_READ(VLV_IMR);
1758         if (pipe == 0)
1759                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1760         else
1761                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1762         I915_WRITE(VLV_IMR, imr);
1763         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1764 }
1765
1766 static u32
1767 ring_last_seqno(struct intel_ring_buffer *ring)
1768 {
1769         return list_entry(ring->request_list.prev,
1770                           struct drm_i915_gem_request, list)->seqno;
1771 }
1772
1773 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1774 {
1775         if (list_empty(&ring->request_list) ||
1776             i915_seqno_passed(ring->get_seqno(ring, false),
1777                               ring_last_seqno(ring))) {
1778                 /* Issue a wake-up to catch stuck h/w. */
1779                 if (waitqueue_active(&ring->irq_queue)) {
1780                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1781                                   ring->name);
1782                         wake_up_all(&ring->irq_queue);
1783                         *err = true;
1784                 }
1785                 return true;
1786         }
1787         return false;
1788 }
1789
1790 static bool semaphore_passed(struct intel_ring_buffer *ring)
1791 {
1792         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1793         u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1794         struct intel_ring_buffer *signaller;
1795         u32 cmd, ipehr, acthd_min;
1796
1797         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1798         if ((ipehr & ~(0x3 << 16)) !=
1799             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1800                 return false;
1801
1802         /* ACTHD is likely pointing to the dword after the actual command,
1803          * so scan backwards until we find the MBOX.
1804          */
1805         acthd_min = max((int)acthd - 3 * 4, 0);
1806         do {
1807                 cmd = ioread32(ring->virtual_start + acthd);
1808                 if (cmd == ipehr)
1809                         break;
1810
1811                 acthd -= 4;
1812                 if (acthd < acthd_min)
1813                         return false;
1814         } while (1);
1815
1816         signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1817         return i915_seqno_passed(signaller->get_seqno(signaller, false),
1818                                  ioread32(ring->virtual_start+acthd+4)+1);
1819 }
1820
1821 static bool kick_ring(struct intel_ring_buffer *ring)
1822 {
1823         struct drm_device *dev = ring->dev;
1824         struct drm_i915_private *dev_priv = dev->dev_private;
1825         u32 tmp = I915_READ_CTL(ring);
1826         if (tmp & RING_WAIT) {
1827                 DRM_ERROR("Kicking stuck wait on %s\n",
1828                           ring->name);
1829                 I915_WRITE_CTL(ring, tmp);
1830                 return true;
1831         }
1832
1833         if (INTEL_INFO(dev)->gen >= 6 &&
1834             tmp & RING_WAIT_SEMAPHORE &&
1835             semaphore_passed(ring)) {
1836                 DRM_ERROR("Kicking stuck semaphore on %s\n",
1837                           ring->name);
1838                 I915_WRITE_CTL(ring, tmp);
1839                 return true;
1840         }
1841         return false;
1842 }
1843
1844 static bool i915_hangcheck_hung(struct drm_device *dev)
1845 {
1846         drm_i915_private_t *dev_priv = dev->dev_private;
1847
1848         if (dev_priv->gpu_error.hangcheck_count++ > 1) {
1849                 bool hung = true;
1850
1851                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1852                 i915_handle_error(dev, true);
1853
1854                 if (!IS_GEN2(dev)) {
1855                         struct intel_ring_buffer *ring;
1856                         int i;
1857
1858                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1859                          * If so we can simply poke the RB_WAIT bit
1860                          * and break the hang. This should work on
1861                          * all but the second generation chipsets.
1862                          */
1863                         for_each_ring(ring, dev_priv, i)
1864                                 hung &= !kick_ring(ring);
1865                 }
1866
1867                 return hung;
1868         }
1869
1870         return false;
1871 }
1872
1873 /**
1874  * This is called when the chip hasn't reported back with completed
1875  * batchbuffers in a long time. The first time this is called we simply record
1876  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1877  * again, we assume the chip is wedged and try to fix it.
1878  */
1879 void i915_hangcheck_elapsed(unsigned long data)
1880 {
1881         struct drm_device *dev = (struct drm_device *)data;
1882         drm_i915_private_t *dev_priv = dev->dev_private;
1883         uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
1884         struct intel_ring_buffer *ring;
1885         bool err = false, idle;
1886         int i;
1887
1888         if (!i915_enable_hangcheck)
1889                 return;
1890
1891         memset(acthd, 0, sizeof(acthd));
1892         idle = true;
1893         for_each_ring(ring, dev_priv, i) {
1894             idle &= i915_hangcheck_ring_idle(ring, &err);
1895             acthd[i] = intel_ring_get_active_head(ring);
1896         }
1897
1898         /* If all work is done then ACTHD clearly hasn't advanced. */
1899         if (idle) {
1900                 if (err) {
1901                         if (i915_hangcheck_hung(dev))
1902                                 return;
1903
1904                         goto repeat;
1905                 }
1906
1907                 dev_priv->gpu_error.hangcheck_count = 0;
1908                 return;
1909         }
1910
1911         i915_get_extra_instdone(dev, instdone);
1912         if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1913                    sizeof(acthd)) == 0 &&
1914             memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1915                    sizeof(instdone)) == 0) {
1916                 if (i915_hangcheck_hung(dev))
1917                         return;
1918         } else {
1919                 dev_priv->gpu_error.hangcheck_count = 0;
1920
1921                 memcpy(dev_priv->gpu_error.last_acthd, acthd,
1922                        sizeof(acthd));
1923                 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
1924                        sizeof(instdone));
1925         }
1926
1927 repeat:
1928         /* Reset timer case chip hangs without another request being added */
1929         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
1930                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1931 }
1932
1933 /* drm_dma.h hooks
1934 */
1935 static void ironlake_irq_preinstall(struct drm_device *dev)
1936 {
1937         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1938
1939         atomic_set(&dev_priv->irq_received, 0);
1940
1941         I915_WRITE(HWSTAM, 0xeffe);
1942
1943         /* XXX hotplug from PCH */
1944
1945         I915_WRITE(DEIMR, 0xffffffff);
1946         I915_WRITE(DEIER, 0x0);
1947         POSTING_READ(DEIER);
1948
1949         /* and GT */
1950         I915_WRITE(GTIMR, 0xffffffff);
1951         I915_WRITE(GTIER, 0x0);
1952         POSTING_READ(GTIER);
1953
1954         /* south display irq */
1955         I915_WRITE(SDEIMR, 0xffffffff);
1956         I915_WRITE(SDEIER, 0x0);
1957         POSTING_READ(SDEIER);
1958 }
1959
1960 static void valleyview_irq_preinstall(struct drm_device *dev)
1961 {
1962         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1963         int pipe;
1964
1965         atomic_set(&dev_priv->irq_received, 0);
1966
1967         /* VLV magic */
1968         I915_WRITE(VLV_IMR, 0);
1969         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1970         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1971         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1972
1973         /* and GT */
1974         I915_WRITE(GTIIR, I915_READ(GTIIR));
1975         I915_WRITE(GTIIR, I915_READ(GTIIR));
1976         I915_WRITE(GTIMR, 0xffffffff);
1977         I915_WRITE(GTIER, 0x0);
1978         POSTING_READ(GTIER);
1979
1980         I915_WRITE(DPINVGTT, 0xff);
1981
1982         I915_WRITE(PORT_HOTPLUG_EN, 0);
1983         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1984         for_each_pipe(pipe)
1985                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1986         I915_WRITE(VLV_IIR, 0xffffffff);
1987         I915_WRITE(VLV_IMR, 0xffffffff);
1988         I915_WRITE(VLV_IER, 0x0);
1989         POSTING_READ(VLV_IER);
1990 }
1991
1992 /*
1993  * Enable digital hotplug on the PCH, and configure the DP short pulse
1994  * duration to 2ms (which is the minimum in the Display Port spec)
1995  *
1996  * This register is the same on all known PCH chips.
1997  */
1998
1999 static void ibx_enable_hotplug(struct drm_device *dev)
2000 {
2001         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2002         u32     hotplug;
2003
2004         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2005         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2006         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2007         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2008         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2009         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2010 }
2011
2012 static void ibx_irq_postinstall(struct drm_device *dev)
2013 {
2014         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2015         u32 mask;
2016
2017         if (HAS_PCH_IBX(dev))
2018                 mask = SDE_HOTPLUG_MASK |
2019                        SDE_GMBUS |
2020                        SDE_AUX_MASK;
2021         else
2022                 mask = SDE_HOTPLUG_MASK_CPT |
2023                        SDE_GMBUS_CPT |
2024                        SDE_AUX_MASK_CPT;
2025
2026         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2027         I915_WRITE(SDEIMR, ~mask);
2028         I915_WRITE(SDEIER, mask);
2029         POSTING_READ(SDEIER);
2030
2031         ibx_enable_hotplug(dev);
2032 }
2033
2034 static int ironlake_irq_postinstall(struct drm_device *dev)
2035 {
2036         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2037         /* enable kind of interrupts always enabled */
2038         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2039                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2040                            DE_AUX_CHANNEL_A;
2041         u32 render_irqs;
2042
2043         dev_priv->irq_mask = ~display_mask;
2044
2045         /* should always can generate irq */
2046         I915_WRITE(DEIIR, I915_READ(DEIIR));
2047         I915_WRITE(DEIMR, dev_priv->irq_mask);
2048         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
2049         POSTING_READ(DEIER);
2050
2051         dev_priv->gt_irq_mask = ~0;
2052
2053         I915_WRITE(GTIIR, I915_READ(GTIIR));
2054         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2055
2056         if (IS_GEN6(dev))
2057                 render_irqs =
2058                         GT_USER_INTERRUPT |
2059                         GEN6_BSD_USER_INTERRUPT |
2060                         GEN6_BLITTER_USER_INTERRUPT;
2061         else
2062                 render_irqs =
2063                         GT_USER_INTERRUPT |
2064                         GT_PIPE_NOTIFY |
2065                         GT_BSD_USER_INTERRUPT;
2066         I915_WRITE(GTIER, render_irqs);
2067         POSTING_READ(GTIER);
2068
2069         ibx_irq_postinstall(dev);
2070
2071         if (IS_IRONLAKE_M(dev)) {
2072                 /* Clear & enable PCU event interrupts */
2073                 I915_WRITE(DEIIR, DE_PCU_EVENT);
2074                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2075                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2076         }
2077
2078         return 0;
2079 }
2080
2081 static int ivybridge_irq_postinstall(struct drm_device *dev)
2082 {
2083         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2084         /* enable kind of interrupts always enabled */
2085         u32 display_mask =
2086                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2087                 DE_PLANEC_FLIP_DONE_IVB |
2088                 DE_PLANEB_FLIP_DONE_IVB |
2089                 DE_PLANEA_FLIP_DONE_IVB |
2090                 DE_AUX_CHANNEL_A_IVB;
2091         u32 render_irqs;
2092
2093         dev_priv->irq_mask = ~display_mask;
2094
2095         /* should always can generate irq */
2096         I915_WRITE(DEIIR, I915_READ(DEIIR));
2097         I915_WRITE(DEIMR, dev_priv->irq_mask);
2098         I915_WRITE(DEIER,
2099                    display_mask |
2100                    DE_PIPEC_VBLANK_IVB |
2101                    DE_PIPEB_VBLANK_IVB |
2102                    DE_PIPEA_VBLANK_IVB);
2103         POSTING_READ(DEIER);
2104
2105         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2106
2107         I915_WRITE(GTIIR, I915_READ(GTIIR));
2108         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2109
2110         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2111                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2112         I915_WRITE(GTIER, render_irqs);
2113         POSTING_READ(GTIER);
2114
2115         ibx_irq_postinstall(dev);
2116
2117         return 0;
2118 }
2119
2120 static int valleyview_irq_postinstall(struct drm_device *dev)
2121 {
2122         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2123         u32 enable_mask;
2124         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2125         u32 render_irqs;
2126         u16 msid;
2127
2128         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2129         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2130                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2131                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2132                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2133
2134         /*
2135          *Leave vblank interrupts masked initially.  enable/disable will
2136          * toggle them based on usage.
2137          */
2138         dev_priv->irq_mask = (~enable_mask) |
2139                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2140                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2141
2142         /* Hack for broken MSIs on VLV */
2143         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2144         pci_read_config_word(dev->pdev, 0x98, &msid);
2145         msid &= 0xff; /* mask out delivery bits */
2146         msid |= (1<<14);
2147         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2148
2149         I915_WRITE(PORT_HOTPLUG_EN, 0);
2150         POSTING_READ(PORT_HOTPLUG_EN);
2151
2152         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2153         I915_WRITE(VLV_IER, enable_mask);
2154         I915_WRITE(VLV_IIR, 0xffffffff);
2155         I915_WRITE(PIPESTAT(0), 0xffff);
2156         I915_WRITE(PIPESTAT(1), 0xffff);
2157         POSTING_READ(VLV_IER);
2158
2159         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2160         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2161         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2162
2163         I915_WRITE(VLV_IIR, 0xffffffff);
2164         I915_WRITE(VLV_IIR, 0xffffffff);
2165
2166         I915_WRITE(GTIIR, I915_READ(GTIIR));
2167         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2168
2169         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2170                 GEN6_BLITTER_USER_INTERRUPT;
2171         I915_WRITE(GTIER, render_irqs);
2172         POSTING_READ(GTIER);
2173
2174         /* ack & enable invalid PTE error interrupts */
2175 #if 0 /* FIXME: add support to irq handler for checking these bits */
2176         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2177         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2178 #endif
2179
2180         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2181
2182         return 0;
2183 }
2184
2185 static void valleyview_hpd_irq_setup(struct drm_device *dev)
2186 {
2187         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2188         u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2189
2190         /* Note HDMI and DP share bits */
2191         if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2192                 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2193         if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2194                 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2195         if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2196                 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2197         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2198                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2199         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2200                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2201         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2202                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2203                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2204         }
2205
2206         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2207 }
2208
2209 static void valleyview_irq_uninstall(struct drm_device *dev)
2210 {
2211         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2212         int pipe;
2213
2214         if (!dev_priv)
2215                 return;
2216
2217         for_each_pipe(pipe)
2218                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2219
2220         I915_WRITE(HWSTAM, 0xffffffff);
2221         I915_WRITE(PORT_HOTPLUG_EN, 0);
2222         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2223         for_each_pipe(pipe)
2224                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2225         I915_WRITE(VLV_IIR, 0xffffffff);
2226         I915_WRITE(VLV_IMR, 0xffffffff);
2227         I915_WRITE(VLV_IER, 0x0);
2228         POSTING_READ(VLV_IER);
2229 }
2230
2231 static void ironlake_irq_uninstall(struct drm_device *dev)
2232 {
2233         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2234
2235         if (!dev_priv)
2236                 return;
2237
2238         I915_WRITE(HWSTAM, 0xffffffff);
2239
2240         I915_WRITE(DEIMR, 0xffffffff);
2241         I915_WRITE(DEIER, 0x0);
2242         I915_WRITE(DEIIR, I915_READ(DEIIR));
2243
2244         I915_WRITE(GTIMR, 0xffffffff);
2245         I915_WRITE(GTIER, 0x0);
2246         I915_WRITE(GTIIR, I915_READ(GTIIR));
2247
2248         I915_WRITE(SDEIMR, 0xffffffff);
2249         I915_WRITE(SDEIER, 0x0);
2250         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2251 }
2252
2253 static void i8xx_irq_preinstall(struct drm_device * dev)
2254 {
2255         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2256         int pipe;
2257
2258         atomic_set(&dev_priv->irq_received, 0);
2259
2260         for_each_pipe(pipe)
2261                 I915_WRITE(PIPESTAT(pipe), 0);
2262         I915_WRITE16(IMR, 0xffff);
2263         I915_WRITE16(IER, 0x0);
2264         POSTING_READ16(IER);
2265 }
2266
2267 static int i8xx_irq_postinstall(struct drm_device *dev)
2268 {
2269         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2270
2271         I915_WRITE16(EMR,
2272                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2273
2274         /* Unmask the interrupts that we always want on. */
2275         dev_priv->irq_mask =
2276                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2277                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2278                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2279                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2280                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2281         I915_WRITE16(IMR, dev_priv->irq_mask);
2282
2283         I915_WRITE16(IER,
2284                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2285                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2286                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2287                      I915_USER_INTERRUPT);
2288         POSTING_READ16(IER);
2289
2290         return 0;
2291 }
2292
2293 /*
2294  * Returns true when a page flip has completed.
2295  */
2296 static bool i8xx_handle_vblank(struct drm_device *dev,
2297                                int pipe, u16 iir)
2298 {
2299         drm_i915_private_t *dev_priv = dev->dev_private;
2300         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2301
2302         if (!drm_handle_vblank(dev, pipe))
2303                 return false;
2304
2305         if ((iir & flip_pending) == 0)
2306                 return false;
2307
2308         intel_prepare_page_flip(dev, pipe);
2309
2310         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2311          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2312          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2313          * the flip is completed (no longer pending). Since this doesn't raise
2314          * an interrupt per se, we watch for the change at vblank.
2315          */
2316         if (I915_READ16(ISR) & flip_pending)
2317                 return false;
2318
2319         intel_finish_page_flip(dev, pipe);
2320
2321         return true;
2322 }
2323
2324 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2325 {
2326         struct drm_device *dev = (struct drm_device *) arg;
2327         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2328         u16 iir, new_iir;
2329         u32 pipe_stats[2];
2330         unsigned long irqflags;
2331         int irq_received;
2332         int pipe;
2333         u16 flip_mask =
2334                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2335                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2336
2337         atomic_inc(&dev_priv->irq_received);
2338
2339         iir = I915_READ16(IIR);
2340         if (iir == 0)
2341                 return IRQ_NONE;
2342
2343         while (iir & ~flip_mask) {
2344                 /* Can't rely on pipestat interrupt bit in iir as it might
2345                  * have been cleared after the pipestat interrupt was received.
2346                  * It doesn't set the bit in iir again, but it still produces
2347                  * interrupts (for non-MSI).
2348                  */
2349                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2350                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2351                         i915_handle_error(dev, false);
2352
2353                 for_each_pipe(pipe) {
2354                         int reg = PIPESTAT(pipe);
2355                         pipe_stats[pipe] = I915_READ(reg);
2356
2357                         /*
2358                          * Clear the PIPE*STAT regs before the IIR
2359                          */
2360                         if (pipe_stats[pipe] & 0x8000ffff) {
2361                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2362                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2363                                                          pipe_name(pipe));
2364                                 I915_WRITE(reg, pipe_stats[pipe]);
2365                                 irq_received = 1;
2366                         }
2367                 }
2368                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2369
2370                 I915_WRITE16(IIR, iir & ~flip_mask);
2371                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2372
2373                 i915_update_dri1_breadcrumb(dev);
2374
2375                 if (iir & I915_USER_INTERRUPT)
2376                         notify_ring(dev, &dev_priv->ring[RCS]);
2377
2378                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2379                     i8xx_handle_vblank(dev, 0, iir))
2380                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2381
2382                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2383                     i8xx_handle_vblank(dev, 1, iir))
2384                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2385
2386                 iir = new_iir;
2387         }
2388
2389         return IRQ_HANDLED;
2390 }
2391
2392 static void i8xx_irq_uninstall(struct drm_device * dev)
2393 {
2394         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2395         int pipe;
2396
2397         for_each_pipe(pipe) {
2398                 /* Clear enable bits; then clear status bits */
2399                 I915_WRITE(PIPESTAT(pipe), 0);
2400                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2401         }
2402         I915_WRITE16(IMR, 0xffff);
2403         I915_WRITE16(IER, 0x0);
2404         I915_WRITE16(IIR, I915_READ16(IIR));
2405 }
2406
2407 static void i915_irq_preinstall(struct drm_device * dev)
2408 {
2409         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2410         int pipe;
2411
2412         atomic_set(&dev_priv->irq_received, 0);
2413
2414         if (I915_HAS_HOTPLUG(dev)) {
2415                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2416                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2417         }
2418
2419         I915_WRITE16(HWSTAM, 0xeffe);
2420         for_each_pipe(pipe)
2421                 I915_WRITE(PIPESTAT(pipe), 0);
2422         I915_WRITE(IMR, 0xffffffff);
2423         I915_WRITE(IER, 0x0);
2424         POSTING_READ(IER);
2425 }
2426
2427 static int i915_irq_postinstall(struct drm_device *dev)
2428 {
2429         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2430         u32 enable_mask;
2431
2432         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2433
2434         /* Unmask the interrupts that we always want on. */
2435         dev_priv->irq_mask =
2436                 ~(I915_ASLE_INTERRUPT |
2437                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2438                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2439                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2440                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2441                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2442
2443         enable_mask =
2444                 I915_ASLE_INTERRUPT |
2445                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2446                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2447                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2448                 I915_USER_INTERRUPT;
2449
2450         if (I915_HAS_HOTPLUG(dev)) {
2451                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2452                 POSTING_READ(PORT_HOTPLUG_EN);
2453
2454                 /* Enable in IER... */
2455                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2456                 /* and unmask in IMR */
2457                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2458         }
2459
2460         I915_WRITE(IMR, dev_priv->irq_mask);
2461         I915_WRITE(IER, enable_mask);
2462         POSTING_READ(IER);
2463
2464         intel_opregion_enable_asle(dev);
2465
2466         return 0;
2467 }
2468
2469 static void i915_hpd_irq_setup(struct drm_device *dev)
2470 {
2471         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2472         u32 hotplug_en;
2473
2474         if (I915_HAS_HOTPLUG(dev)) {
2475                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2476
2477                 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2478                         hotplug_en |= PORTB_HOTPLUG_INT_EN;
2479                 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2480                         hotplug_en |= PORTC_HOTPLUG_INT_EN;
2481                 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2482                         hotplug_en |= PORTD_HOTPLUG_INT_EN;
2483                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2484                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2485                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2486                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2487                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2488                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2489                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2490                 }
2491
2492                 /* Ignore TV since it's buggy */
2493
2494                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2495         }
2496 }
2497
2498 /*
2499  * Returns true when a page flip has completed.
2500  */
2501 static bool i915_handle_vblank(struct drm_device *dev,
2502                                int plane, int pipe, u32 iir)
2503 {
2504         drm_i915_private_t *dev_priv = dev->dev_private;
2505         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2506
2507         if (!drm_handle_vblank(dev, pipe))
2508                 return false;
2509
2510         if ((iir & flip_pending) == 0)
2511                 return false;
2512
2513         intel_prepare_page_flip(dev, plane);
2514
2515         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2516          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2517          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2518          * the flip is completed (no longer pending). Since this doesn't raise
2519          * an interrupt per se, we watch for the change at vblank.
2520          */
2521         if (I915_READ(ISR) & flip_pending)
2522                 return false;
2523
2524         intel_finish_page_flip(dev, pipe);
2525
2526         return true;
2527 }
2528
2529 static irqreturn_t i915_irq_handler(int irq, void *arg)
2530 {
2531         struct drm_device *dev = (struct drm_device *) arg;
2532         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2533         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2534         unsigned long irqflags;
2535         u32 flip_mask =
2536                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2537                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2538         int pipe, ret = IRQ_NONE;
2539
2540         atomic_inc(&dev_priv->irq_received);
2541
2542         iir = I915_READ(IIR);
2543         do {
2544                 bool irq_received = (iir & ~flip_mask) != 0;
2545                 bool blc_event = false;
2546
2547                 /* Can't rely on pipestat interrupt bit in iir as it might
2548                  * have been cleared after the pipestat interrupt was received.
2549                  * It doesn't set the bit in iir again, but it still produces
2550                  * interrupts (for non-MSI).
2551                  */
2552                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2553                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2554                         i915_handle_error(dev, false);
2555
2556                 for_each_pipe(pipe) {
2557                         int reg = PIPESTAT(pipe);
2558                         pipe_stats[pipe] = I915_READ(reg);
2559
2560                         /* Clear the PIPE*STAT regs before the IIR */
2561                         if (pipe_stats[pipe] & 0x8000ffff) {
2562                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2563                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2564                                                          pipe_name(pipe));
2565                                 I915_WRITE(reg, pipe_stats[pipe]);
2566                                 irq_received = true;
2567                         }
2568                 }
2569                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2570
2571                 if (!irq_received)
2572                         break;
2573
2574                 /* Consume port.  Then clear IIR or we'll miss events */
2575                 if ((I915_HAS_HOTPLUG(dev)) &&
2576                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2577                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2578
2579                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2580                                   hotplug_status);
2581                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2582                                 queue_work(dev_priv->wq,
2583                                            &dev_priv->hotplug_work);
2584
2585                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2586                         POSTING_READ(PORT_HOTPLUG_STAT);
2587                 }
2588
2589                 I915_WRITE(IIR, iir & ~flip_mask);
2590                 new_iir = I915_READ(IIR); /* Flush posted writes */
2591
2592                 if (iir & I915_USER_INTERRUPT)
2593                         notify_ring(dev, &dev_priv->ring[RCS]);
2594
2595                 for_each_pipe(pipe) {
2596                         int plane = pipe;
2597                         if (IS_MOBILE(dev))
2598                                 plane = !plane;
2599
2600                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2601                             i915_handle_vblank(dev, plane, pipe, iir))
2602                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2603
2604                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2605                                 blc_event = true;
2606                 }
2607
2608                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2609                         intel_opregion_asle_intr(dev);
2610
2611                 /* With MSI, interrupts are only generated when iir
2612                  * transitions from zero to nonzero.  If another bit got
2613                  * set while we were handling the existing iir bits, then
2614                  * we would never get another interrupt.
2615                  *
2616                  * This is fine on non-MSI as well, as if we hit this path
2617                  * we avoid exiting the interrupt handler only to generate
2618                  * another one.
2619                  *
2620                  * Note that for MSI this could cause a stray interrupt report
2621                  * if an interrupt landed in the time between writing IIR and
2622                  * the posting read.  This should be rare enough to never
2623                  * trigger the 99% of 100,000 interrupts test for disabling
2624                  * stray interrupts.
2625                  */
2626                 ret = IRQ_HANDLED;
2627                 iir = new_iir;
2628         } while (iir & ~flip_mask);
2629
2630         i915_update_dri1_breadcrumb(dev);
2631
2632         return ret;
2633 }
2634
2635 static void i915_irq_uninstall(struct drm_device * dev)
2636 {
2637         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2638         int pipe;
2639
2640         if (I915_HAS_HOTPLUG(dev)) {
2641                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2642                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2643         }
2644
2645         I915_WRITE16(HWSTAM, 0xffff);
2646         for_each_pipe(pipe) {
2647                 /* Clear enable bits; then clear status bits */
2648                 I915_WRITE(PIPESTAT(pipe), 0);
2649                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2650         }
2651         I915_WRITE(IMR, 0xffffffff);
2652         I915_WRITE(IER, 0x0);
2653
2654         I915_WRITE(IIR, I915_READ(IIR));
2655 }
2656
2657 static void i965_irq_preinstall(struct drm_device * dev)
2658 {
2659         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2660         int pipe;
2661
2662         atomic_set(&dev_priv->irq_received, 0);
2663
2664         I915_WRITE(PORT_HOTPLUG_EN, 0);
2665         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2666
2667         I915_WRITE(HWSTAM, 0xeffe);
2668         for_each_pipe(pipe)
2669                 I915_WRITE(PIPESTAT(pipe), 0);
2670         I915_WRITE(IMR, 0xffffffff);
2671         I915_WRITE(IER, 0x0);
2672         POSTING_READ(IER);
2673 }
2674
2675 static int i965_irq_postinstall(struct drm_device *dev)
2676 {
2677         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2678         u32 enable_mask;
2679         u32 error_mask;
2680
2681         /* Unmask the interrupts that we always want on. */
2682         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2683                                I915_DISPLAY_PORT_INTERRUPT |
2684                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2685                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2686                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2687                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2688                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2689
2690         enable_mask = ~dev_priv->irq_mask;
2691         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2692                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2693         enable_mask |= I915_USER_INTERRUPT;
2694
2695         if (IS_G4X(dev))
2696                 enable_mask |= I915_BSD_USER_INTERRUPT;
2697
2698         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2699
2700         /*
2701          * Enable some error detection, note the instruction error mask
2702          * bit is reserved, so we leave it masked.
2703          */
2704         if (IS_G4X(dev)) {
2705                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2706                                GM45_ERROR_MEM_PRIV |
2707                                GM45_ERROR_CP_PRIV |
2708                                I915_ERROR_MEMORY_REFRESH);
2709         } else {
2710                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2711                                I915_ERROR_MEMORY_REFRESH);
2712         }
2713         I915_WRITE(EMR, error_mask);
2714
2715         I915_WRITE(IMR, dev_priv->irq_mask);
2716         I915_WRITE(IER, enable_mask);
2717         POSTING_READ(IER);
2718
2719         I915_WRITE(PORT_HOTPLUG_EN, 0);
2720         POSTING_READ(PORT_HOTPLUG_EN);
2721
2722         intel_opregion_enable_asle(dev);
2723
2724         return 0;
2725 }
2726
2727 static void i965_hpd_irq_setup(struct drm_device *dev)
2728 {
2729         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2730         u32 hotplug_en;
2731
2732         /* Note HDMI and DP share hotplug bits */
2733         hotplug_en = 0;
2734         if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2735                 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2736         if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2737                 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2738         if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2739                 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2740         if (IS_G4X(dev)) {
2741                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2742                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2743                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2744                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2745         } else {
2746                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2747                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2748                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2749                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2750         }
2751         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2752                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2753
2754                 /* Programming the CRT detection parameters tends
2755                    to generate a spurious hotplug event about three
2756                    seconds later.  So just do it once.
2757                    */
2758                 if (IS_G4X(dev))
2759                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2760                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2761         }
2762
2763         /* Ignore TV since it's buggy */
2764
2765         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2766 }
2767
2768 static irqreturn_t i965_irq_handler(int irq, void *arg)
2769 {
2770         struct drm_device *dev = (struct drm_device *) arg;
2771         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2772         u32 iir, new_iir;
2773         u32 pipe_stats[I915_MAX_PIPES];
2774         unsigned long irqflags;
2775         int irq_received;
2776         int ret = IRQ_NONE, pipe;
2777         u32 flip_mask =
2778                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2779                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2780
2781         atomic_inc(&dev_priv->irq_received);
2782
2783         iir = I915_READ(IIR);
2784
2785         for (;;) {
2786                 bool blc_event = false;
2787
2788                 irq_received = (iir & ~flip_mask) != 0;
2789
2790                 /* Can't rely on pipestat interrupt bit in iir as it might
2791                  * have been cleared after the pipestat interrupt was received.
2792                  * It doesn't set the bit in iir again, but it still produces
2793                  * interrupts (for non-MSI).
2794                  */
2795                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2796                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2797                         i915_handle_error(dev, false);
2798
2799                 for_each_pipe(pipe) {
2800                         int reg = PIPESTAT(pipe);
2801                         pipe_stats[pipe] = I915_READ(reg);
2802
2803                         /*
2804                          * Clear the PIPE*STAT regs before the IIR
2805                          */
2806                         if (pipe_stats[pipe] & 0x8000ffff) {
2807                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2808                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2809                                                          pipe_name(pipe));
2810                                 I915_WRITE(reg, pipe_stats[pipe]);
2811                                 irq_received = 1;
2812                         }
2813                 }
2814                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2815
2816                 if (!irq_received)
2817                         break;
2818
2819                 ret = IRQ_HANDLED;
2820
2821                 /* Consume port.  Then clear IIR or we'll miss events */
2822                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2823                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2824
2825                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2826                                   hotplug_status);
2827                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2828                                 queue_work(dev_priv->wq,
2829                                            &dev_priv->hotplug_work);
2830
2831                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2832                         I915_READ(PORT_HOTPLUG_STAT);
2833                 }
2834
2835                 I915_WRITE(IIR, iir & ~flip_mask);
2836                 new_iir = I915_READ(IIR); /* Flush posted writes */
2837
2838                 if (iir & I915_USER_INTERRUPT)
2839                         notify_ring(dev, &dev_priv->ring[RCS]);
2840                 if (iir & I915_BSD_USER_INTERRUPT)
2841                         notify_ring(dev, &dev_priv->ring[VCS]);
2842
2843                 for_each_pipe(pipe) {
2844                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2845                             i915_handle_vblank(dev, pipe, pipe, iir))
2846                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
2847
2848                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2849                                 blc_event = true;
2850                 }
2851
2852
2853                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2854                         intel_opregion_asle_intr(dev);
2855
2856                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2857                         gmbus_irq_handler(dev);
2858
2859                 /* With MSI, interrupts are only generated when iir
2860                  * transitions from zero to nonzero.  If another bit got
2861                  * set while we were handling the existing iir bits, then
2862                  * we would never get another interrupt.
2863                  *
2864                  * This is fine on non-MSI as well, as if we hit this path
2865                  * we avoid exiting the interrupt handler only to generate
2866                  * another one.
2867                  *
2868                  * Note that for MSI this could cause a stray interrupt report
2869                  * if an interrupt landed in the time between writing IIR and
2870                  * the posting read.  This should be rare enough to never
2871                  * trigger the 99% of 100,000 interrupts test for disabling
2872                  * stray interrupts.
2873                  */
2874                 iir = new_iir;
2875         }
2876
2877         i915_update_dri1_breadcrumb(dev);
2878
2879         return ret;
2880 }
2881
2882 static void i965_irq_uninstall(struct drm_device * dev)
2883 {
2884         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2885         int pipe;
2886
2887         if (!dev_priv)
2888                 return;
2889
2890         I915_WRITE(PORT_HOTPLUG_EN, 0);
2891         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2892
2893         I915_WRITE(HWSTAM, 0xffffffff);
2894         for_each_pipe(pipe)
2895                 I915_WRITE(PIPESTAT(pipe), 0);
2896         I915_WRITE(IMR, 0xffffffff);
2897         I915_WRITE(IER, 0x0);
2898
2899         for_each_pipe(pipe)
2900                 I915_WRITE(PIPESTAT(pipe),
2901                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2902         I915_WRITE(IIR, I915_READ(IIR));
2903 }
2904
2905 void intel_irq_init(struct drm_device *dev)
2906 {
2907         struct drm_i915_private *dev_priv = dev->dev_private;
2908
2909         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2910         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
2911         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2912         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
2913
2914         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2915                     i915_hangcheck_elapsed,
2916                     (unsigned long) dev);
2917
2918         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
2919
2920         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2921         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2922         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2923                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2924                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2925         }
2926
2927         if (drm_core_check_feature(dev, DRIVER_MODESET))
2928                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2929         else
2930                 dev->driver->get_vblank_timestamp = NULL;
2931         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2932
2933         if (IS_VALLEYVIEW(dev)) {
2934                 dev->driver->irq_handler = valleyview_irq_handler;
2935                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2936                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2937                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2938                 dev->driver->enable_vblank = valleyview_enable_vblank;
2939                 dev->driver->disable_vblank = valleyview_disable_vblank;
2940                 dev_priv->display.hpd_irq_setup = valleyview_hpd_irq_setup;
2941         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2942                 /* Share pre & uninstall handlers with ILK/SNB */
2943                 dev->driver->irq_handler = ivybridge_irq_handler;
2944                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2945                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2946                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2947                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2948                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2949         } else if (HAS_PCH_SPLIT(dev)) {
2950                 dev->driver->irq_handler = ironlake_irq_handler;
2951                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2952                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2953                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2954                 dev->driver->enable_vblank = ironlake_enable_vblank;
2955                 dev->driver->disable_vblank = ironlake_disable_vblank;
2956         } else {
2957                 if (INTEL_INFO(dev)->gen == 2) {
2958                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2959                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2960                         dev->driver->irq_handler = i8xx_irq_handler;
2961                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2962                 } else if (INTEL_INFO(dev)->gen == 3) {
2963                         dev->driver->irq_preinstall = i915_irq_preinstall;
2964                         dev->driver->irq_postinstall = i915_irq_postinstall;
2965                         dev->driver->irq_uninstall = i915_irq_uninstall;
2966                         dev->driver->irq_handler = i915_irq_handler;
2967                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2968                 } else {
2969                         dev->driver->irq_preinstall = i965_irq_preinstall;
2970                         dev->driver->irq_postinstall = i965_irq_postinstall;
2971                         dev->driver->irq_uninstall = i965_irq_uninstall;
2972                         dev->driver->irq_handler = i965_irq_handler;
2973                         dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup;
2974                 }
2975                 dev->driver->enable_vblank = i915_enable_vblank;
2976                 dev->driver->disable_vblank = i915_disable_vblank;
2977         }
2978 }
2979
2980 void intel_hpd_init(struct drm_device *dev)
2981 {
2982         struct drm_i915_private *dev_priv = dev->dev_private;
2983
2984         if (dev_priv->display.hpd_irq_setup)
2985                 dev_priv->display.hpd_irq_setup(dev);
2986 }