drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "intel_drv.h"
  38
  39 /* For display hotplug interrupt */
  40 static void
  41 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  42 {
  43         if ((dev_priv->irq_mask & mask) != 0) {
  44                 dev_priv->irq_mask &= ~mask;
  45                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  46                 POSTING_READ(DEIMR);
  47         }
  48 }
  49
  50 static inline void
  51 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  52 {
  53         if ((dev_priv->irq_mask & mask) != mask) {
  54                 dev_priv->irq_mask |= mask;
  55                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  56                 POSTING_READ(DEIMR);
  57         }
  58 }
  59
  60 void
  61 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  62 {
  63         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  64                 u32 reg = PIPESTAT(pipe);
  65
  66                 dev_priv->pipestat[pipe] |= mask;
  67                 /* Enable the interrupt, clear any pending status */
  68                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  69                 POSTING_READ(reg);
  70         }
  71 }
  72
  73 void
  74 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  75 {
  76         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  77                 u32 reg = PIPESTAT(pipe);
  78
  79                 dev_priv->pipestat[pipe] &= ~mask;
  80                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
  81                 POSTING_READ(reg);
  82         }
  83 }
  84
  85 /**
  86  * intel_enable_asle - enable ASLE interrupt for OpRegion
  87  */
  88 void intel_enable_asle(struct drm_device *dev)
  89 {
  90         drm_i915_private_t *dev_priv = dev->dev_private;
  91         unsigned long irqflags;
  92
  93         /* FIXME: opregion/asle for VLV */
  94         if (IS_VALLEYVIEW(dev))
  95                 return;
  96
  97         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  98
  99         if (HAS_PCH_SPLIT(dev))
 100                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 101         else {
 102                 i915_enable_pipestat(dev_priv, 1,
 103                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 104                 if (INTEL_INFO(dev)->gen >= 4)
 105                         i915_enable_pipestat(dev_priv, 0,
 106                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 107         }
 108
 109         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 110 }
 111
 112 /**
 113  * i915_pipe_enabled - check if a pipe is enabled
 114  * @dev: DRM device
 115  * @pipe: pipe to check
 116  *
 117  * Reading certain registers when the pipe is disabled can hang the chip.
 118  * Use this routine to make sure the PLL is running and the pipe is active
 119  * before reading such registers if unsure.
 120  */
 121 static int
 122 i915_pipe_enabled(struct drm_device *dev, int pipe)
 123 {
 124         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 125         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 126                                                                       pipe);
 127
 128         return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
 129 }
 130
 131 /* Called from drm generic code, passed a 'crtc', which
 132  * we use as a pipe index
 133  */
 134 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 135 {
 136         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 137         unsigned long high_frame;
 138         unsigned long low_frame;
 139         u32 high1, high2, low;
 140
 141         if (!i915_pipe_enabled(dev, pipe)) {
 142                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 143                                 "pipe %c\n", pipe_name(pipe));
 144                 return 0;
 145         }
 146
 147         high_frame = PIPEFRAME(pipe);
 148         low_frame = PIPEFRAMEPIXEL(pipe);
 149
 150         /*
 151          * High & low register fields aren't synchronized, so make sure
 152          * we get a low value that's stable across two reads of the high
 153          * register.
 154          */
 155         do {
 156                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 157                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 158                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 159         } while (high1 != high2);
 160
 161         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 162         low >>= PIPE_FRAME_LOW_SHIFT;
 163         return (high1 << 8) | low;
 164 }
 165
 166 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169         int reg = PIPE_FRMCOUNT_GM45(pipe);
 170
 171         if (!i915_pipe_enabled(dev, pipe)) {
 172                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 173                                  "pipe %c\n", pipe_name(pipe));
 174                 return 0;
 175         }
 176
 177         return I915_READ(reg);
 178 }
 179
 180 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 181                              int *vpos, int *hpos)
 182 {
 183         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 184         u32 vbl = 0, position = 0;
 185         int vbl_start, vbl_end, htotal, vtotal;
 186         bool in_vbl = true;
 187         int ret = 0;
 188         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 189                                                                       pipe);
 190
 191         if (!i915_pipe_enabled(dev, pipe)) {
 192                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 193                                  "pipe %c\n", pipe_name(pipe));
 194                 return 0;
 195         }
 196
 197         /* Get vtotal. */
 198         vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 199
 200         if (INTEL_INFO(dev)->gen >= 4) {
 201                 /* No obvious pixelcount register. Only query vertical
 202                  * scanout position from Display scan line register.
 203                  */
 204                 position = I915_READ(PIPEDSL(pipe));
 205
 206                 /* Decode into vertical scanout position. Don't have
 207                  * horizontal scanout position.
 208                  */
 209                 *vpos = position & 0x1fff;
 210                 *hpos = 0;
 211         } else {
 212                 /* Have access to pixelcount since start of frame.
 213                  * We can split this into vertical and horizontal
 214                  * scanout position.
 215                  */
 216                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 217
 218                 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 219                 *vpos = position / htotal;
 220                 *hpos = position - (*vpos * htotal);
 221         }
 222
 223         /* Query vblank area. */
 224         vbl = I915_READ(VBLANK(cpu_transcoder));
 225
 226         /* Test position against vblank region. */
 227         vbl_start = vbl & 0x1fff;
 228         vbl_end = (vbl >> 16) & 0x1fff;
 229
 230         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 231                 in_vbl = false;
 232
 233         /* Inside "upper part" of vblank area? Apply corrective offset: */
 234         if (in_vbl && (*vpos >= vbl_start))
 235                 *vpos = *vpos - vtotal;
 236
 237         /* Readouts valid? */
 238         if (vbl > 0)
 239                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 240
 241         /* In vblank? */
 242         if (in_vbl)
 243                 ret |= DRM_SCANOUTPOS_INVBL;
 244
 245         return ret;
 246 }
 247
 248 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 249                               int *max_error,
 250                               struct timeval *vblank_time,
 251                               unsigned flags)
 252 {
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         struct drm_crtc *crtc;
 255
 256         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 257                 DRM_ERROR("Invalid crtc %d\n", pipe);
 258                 return -EINVAL;
 259         }
 260
 261         /* Get drm_crtc to timestamp: */
 262         crtc = intel_get_crtc_for_pipe(dev, pipe);
 263         if (crtc == NULL) {
 264                 DRM_ERROR("Invalid crtc %d\n", pipe);
 265                 return -EINVAL;
 266         }
 267
 268         if (!crtc->enabled) {
 269                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 270                 return -EBUSY;
 271         }
 272
 273         /* Helper routine in DRM core does all the work: */
 274         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 275                                                      vblank_time, flags,
 276                                                      crtc);
 277 }
 278
 279 /*
 280  * Handle hotplug events outside the interrupt handler proper.
 281  */
 282 static void i915_hotplug_work_func(struct work_struct *work)
 283 {
 284         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 285                                                     hotplug_work);
 286         struct drm_device *dev = dev_priv->dev;
 287         struct drm_mode_config *mode_config = &dev->mode_config;
 288         struct intel_encoder *encoder;
 289
 290         /* HPD irq before everything is fully set up. */
 291         if (!dev_priv->enable_hotplug_processing)
 292                 return;
 293
 294         mutex_lock(&mode_config->mutex);
 295         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 296
 297         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 298                 if (encoder->hot_plug)
 299                         encoder->hot_plug(encoder);
 300
 301         mutex_unlock(&mode_config->mutex);
 302
 303         /* Just fire off a uevent and let userspace tell us what to do */
 304         drm_helper_hpd_irq_event(dev);
 305 }
 306
 307 static void ironlake_handle_rps_change(struct drm_device *dev)
 308 {
 309         drm_i915_private_t *dev_priv = dev->dev_private;
 310         u32 busy_up, busy_down, max_avg, min_avg;
 311         u8 new_delay;
 312         unsigned long flags;
 313
 314         spin_lock_irqsave(&mchdev_lock, flags);
 315
 316         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 317
 318         new_delay = dev_priv->ips.cur_delay;
 319
 320         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 321         busy_up = I915_READ(RCPREVBSYTUPAVG);
 322         busy_down = I915_READ(RCPREVBSYTDNAVG);
 323         max_avg = I915_READ(RCBMAXAVG);
 324         min_avg = I915_READ(RCBMINAVG);
 325
 326         /* Handle RCS change request from hw */
 327         if (busy_up > max_avg) {
 328                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 329                         new_delay = dev_priv->ips.cur_delay - 1;
 330                 if (new_delay < dev_priv->ips.max_delay)
 331                         new_delay = dev_priv->ips.max_delay;
 332         } else if (busy_down < min_avg) {
 333                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 334                         new_delay = dev_priv->ips.cur_delay + 1;
 335                 if (new_delay > dev_priv->ips.min_delay)
 336                         new_delay = dev_priv->ips.min_delay;
 337         }
 338
 339         if (ironlake_set_drps(dev, new_delay))
 340                 dev_priv->ips.cur_delay = new_delay;
 341
 342         spin_unlock_irqrestore(&mchdev_lock, flags);
 343
 344         return;
 345 }
 346
 347 static void notify_ring(struct drm_device *dev,
 348                         struct intel_ring_buffer *ring)
 349 {
 350         struct drm_i915_private *dev_priv = dev->dev_private;
 351
 352         if (ring->obj == NULL)
 353                 return;
 354
 355         trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 356
 357         wake_up_all(&ring->irq_queue);
 358         if (i915_enable_hangcheck) {
 359                 dev_priv->gpu_error.hangcheck_count = 0;
 360                 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
 361                           round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
 362         }
 363 }
 364
 365 static void gen6_pm_rps_work(struct work_struct *work)
 366 {
 367         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 368                                                     rps.work);
 369         u32 pm_iir, pm_imr;
 370         u8 new_delay;
 371
 372         spin_lock_irq(&dev_priv->rps.lock);
 373         pm_iir = dev_priv->rps.pm_iir;
 374         dev_priv->rps.pm_iir = 0;
 375         pm_imr = I915_READ(GEN6_PMIMR);
 376         I915_WRITE(GEN6_PMIMR, 0);
 377         spin_unlock_irq(&dev_priv->rps.lock);
 378
 379         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 380                 return;
 381
 382         mutex_lock(&dev_priv->rps.hw_lock);
 383
 384         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 385                 new_delay = dev_priv->rps.cur_delay + 1;
 386         else
 387                 new_delay = dev_priv->rps.cur_delay - 1;
 388
 389         /* sysfs frequency interfaces may have snuck in while servicing the
 390          * interrupt
 391          */
 392         if (!(new_delay > dev_priv->rps.max_delay ||
 393               new_delay < dev_priv->rps.min_delay)) {
 394                 gen6_set_rps(dev_priv->dev, new_delay);
 395         }
 396
 397         mutex_unlock(&dev_priv->rps.hw_lock);
 398 }
 399
 400
 401 /**
 402  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 403  * occurred.
 404  * @work: workqueue struct
 405  *
 406  * Doesn't actually do anything except notify userspace. As a consequence of
 407  * this event, userspace should try to remap the bad rows since statistically
 408  * it is likely the same row is more likely to go bad again.
 409  */
 410 static void ivybridge_parity_work(struct work_struct *work)
 411 {
 412         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 413                                                     l3_parity.error_work);
 414         u32 error_status, row, bank, subbank;
 415         char *parity_event[5];
 416         uint32_t misccpctl;
 417         unsigned long flags;
 418
 419         /* We must turn off DOP level clock gating to access the L3 registers.
 420          * In order to prevent a get/put style interface, acquire struct mutex
 421          * any time we access those registers.
 422          */
 423         mutex_lock(&dev_priv->dev->struct_mutex);
 424
 425         misccpctl = I915_READ(GEN7_MISCCPCTL);
 426         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 427         POSTING_READ(GEN7_MISCCPCTL);
 428
 429         error_status = I915_READ(GEN7_L3CDERRST1);
 430         row = GEN7_PARITY_ERROR_ROW(error_status);
 431         bank = GEN7_PARITY_ERROR_BANK(error_status);
 432         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 433
 434         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 435                                     GEN7_L3CDERRST1_ENABLE);
 436         POSTING_READ(GEN7_L3CDERRST1);
 437
 438         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 439
 440         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 441         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 442         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 443         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 444
 445         mutex_unlock(&dev_priv->dev->struct_mutex);
 446
 447         parity_event[0] = "L3_PARITY_ERROR=1";
 448         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 449         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 450         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 451         parity_event[4] = NULL;
 452
 453         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 454                            KOBJ_CHANGE, parity_event);
 455
 456         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 457                   row, bank, subbank);
 458
 459         kfree(parity_event[3]);
 460         kfree(parity_event[2]);
 461         kfree(parity_event[1]);
 462 }
 463
 464 static void ivybridge_handle_parity_error(struct drm_device *dev)
 465 {
 466         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 467         unsigned long flags;
 468
 469         if (!HAS_L3_GPU_CACHE(dev))
 470                 return;
 471
 472         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 473         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 474         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 475         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 476
 477         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 478 }
 479
 480 static void snb_gt_irq_handler(struct drm_device *dev,
 481                                struct drm_i915_private *dev_priv,
 482                                u32 gt_iir)
 483 {
 484
 485         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 486                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 487                 notify_ring(dev, &dev_priv->ring[RCS]);
 488         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 489                 notify_ring(dev, &dev_priv->ring[VCS]);
 490         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 491                 notify_ring(dev, &dev_priv->ring[BCS]);
 492
 493         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 494                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 495                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 496                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 497                 i915_handle_error(dev, false);
 498         }
 499
 500         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 501                 ivybridge_handle_parity_error(dev);
 502 }
 503
 504 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 505                                 u32 pm_iir)
 506 {
 507         unsigned long flags;
 508
 509         /*
 510          * IIR bits should never already be set because IMR should
 511          * prevent an interrupt from being shown in IIR. The warning
 512          * displays a case where we've unsafely cleared
 513          * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 514          * type is not a problem, it displays a problem in the logic.
 515          *
 516          * The mask bit in IMR is cleared by dev_priv->rps.work.
 517          */
 518
 519         spin_lock_irqsave(&dev_priv->rps.lock, flags);
 520         dev_priv->rps.pm_iir |= pm_iir;
 521         I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 522         POSTING_READ(GEN6_PMIMR);
 523         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 524
 525         queue_work(dev_priv->wq, &dev_priv->rps.work);
 526 }
 527
 528 static void gmbus_irq_handler(struct drm_device *dev)
 529 {
 530         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 531
 532         wake_up_all(&dev_priv->gmbus_wait_queue);
 533 }
 534
 535 static void dp_aux_irq_handler(struct drm_device *dev)
 536 {
 537         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 538
 539         wake_up_all(&dev_priv->gmbus_wait_queue);
 540 }
 541
 542 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 543 {
 544         struct drm_device *dev = (struct drm_device *) arg;
 545         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 546         u32 iir, gt_iir, pm_iir;
 547         irqreturn_t ret = IRQ_NONE;
 548         unsigned long irqflags;
 549         int pipe;
 550         u32 pipe_stats[I915_MAX_PIPES];
 551
 552         atomic_inc(&dev_priv->irq_received);
 553
 554         while (true) {
 555                 iir = I915_READ(VLV_IIR);
 556                 gt_iir = I915_READ(GTIIR);
 557                 pm_iir = I915_READ(GEN6_PMIIR);
 558
 559                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 560                         goto out;
 561
 562                 ret = IRQ_HANDLED;
 563
 564                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 565
 566                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 567                 for_each_pipe(pipe) {
 568                         int reg = PIPESTAT(pipe);
 569                         pipe_stats[pipe] = I915_READ(reg);
 570
 571                         /*
 572                          * Clear the PIPE*STAT regs before the IIR
 573                          */
 574                         if (pipe_stats[pipe] & 0x8000ffff) {
 575                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 576                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 577                                                          pipe_name(pipe));
 578                                 I915_WRITE(reg, pipe_stats[pipe]);
 579                         }
 580                 }
 581                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 582
 583                 for_each_pipe(pipe) {
 584                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 585                                 drm_handle_vblank(dev, pipe);
 586
 587                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 588                                 intel_prepare_page_flip(dev, pipe);
 589                                 intel_finish_page_flip(dev, pipe);
 590                         }
 591                 }
 592
 593                 /* Consume port.  Then clear IIR or we'll miss events */
 594                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 595                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 596
 597                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 598                                          hotplug_status);
 599                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 600                                 queue_work(dev_priv->wq,
 601                                            &dev_priv->hotplug_work);
 602
 603                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 604                         I915_READ(PORT_HOTPLUG_STAT);
 605                 }
 606
 607                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
 608                         gmbus_irq_handler(dev);
 609
 610                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 611                         gen6_queue_rps_work(dev_priv, pm_iir);
 612
 613                 I915_WRITE(GTIIR, gt_iir);
 614                 I915_WRITE(GEN6_PMIIR, pm_iir);
 615                 I915_WRITE(VLV_IIR, iir);
 616         }
 617
 618 out:
 619         return ret;
 620 }
 621
 622 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 623 {
 624         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 625         int pipe;
 626
 627         if (pch_iir & SDE_HOTPLUG_MASK)
 628                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 629
 630         if (pch_iir & SDE_AUDIO_POWER_MASK)
 631                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 632                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 633                                  SDE_AUDIO_POWER_SHIFT);
 634
 635         if (pch_iir & SDE_AUX_MASK)
 636                 dp_aux_irq_handler(dev);
 637
 638         if (pch_iir & SDE_GMBUS)
 639                 gmbus_irq_handler(dev);
 640
 641         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 642                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 643
 644         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 645                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 646
 647         if (pch_iir & SDE_POISON)
 648                 DRM_ERROR("PCH poison interrupt\n");
 649
 650         if (pch_iir & SDE_FDI_MASK)
 651                 for_each_pipe(pipe)
 652                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 653                                          pipe_name(pipe),
 654                                          I915_READ(FDI_RX_IIR(pipe)));
 655
 656         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 657                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 658
 659         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 660                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 661
 662         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 663                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 664         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 665                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 666 }
 667
 668 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 669 {
 670         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 671         int pipe;
 672
 673         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 674                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 675
 676         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 677                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 678                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 679                                  SDE_AUDIO_POWER_SHIFT_CPT);
 680
 681         if (pch_iir & SDE_AUX_MASK_CPT)
 682                 dp_aux_irq_handler(dev);
 683
 684         if (pch_iir & SDE_GMBUS_CPT)
 685                 gmbus_irq_handler(dev);
 686
 687         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 688                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 689
 690         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 691                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 692
 693         if (pch_iir & SDE_FDI_MASK_CPT)
 694                 for_each_pipe(pipe)
 695                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 696                                          pipe_name(pipe),
 697                                          I915_READ(FDI_RX_IIR(pipe)));
 698 }
 699
 700 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 701 {
 702         struct drm_device *dev = (struct drm_device *) arg;
 703         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 704         u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
 705         irqreturn_t ret = IRQ_NONE;
 706         int i;
 707
 708         atomic_inc(&dev_priv->irq_received);
 709
 710         /* disable master interrupt before clearing iir  */
 711         de_ier = I915_READ(DEIER);
 712         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 713
 714         /* Disable south interrupts. We'll only write to SDEIIR once, so further
 715          * interrupts will will be stored on its back queue, and then we'll be
 716          * able to process them after we restore SDEIER (as soon as we restore
 717          * it, we'll get an interrupt if SDEIIR still has something to process
 718          * due to its back queue). */
 719         sde_ier = I915_READ(SDEIER);
 720         I915_WRITE(SDEIER, 0);
 721         POSTING_READ(SDEIER);
 722
 723         gt_iir = I915_READ(GTIIR);
 724         if (gt_iir) {
 725                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 726                 I915_WRITE(GTIIR, gt_iir);
 727                 ret = IRQ_HANDLED;
 728         }
 729
 730         de_iir = I915_READ(DEIIR);
 731         if (de_iir) {
 732                 if (de_iir & DE_AUX_CHANNEL_A_IVB)
 733                         dp_aux_irq_handler(dev);
 734
 735                 if (de_iir & DE_GSE_IVB)
 736                         intel_opregion_gse_intr(dev);
 737
 738                 for (i = 0; i < 3; i++) {
 739                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 740                                 drm_handle_vblank(dev, i);
 741                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 742                                 intel_prepare_page_flip(dev, i);
 743                                 intel_finish_page_flip_plane(dev, i);
 744                         }
 745                 }
 746
 747                 /* check event from PCH */
 748                 if (de_iir & DE_PCH_EVENT_IVB) {
 749                         u32 pch_iir = I915_READ(SDEIIR);
 750
 751                         cpt_irq_handler(dev, pch_iir);
 752
 753                         /* clear PCH hotplug event before clear CPU irq */
 754                         I915_WRITE(SDEIIR, pch_iir);
 755                 }
 756
 757                 I915_WRITE(DEIIR, de_iir);
 758                 ret = IRQ_HANDLED;
 759         }
 760
 761         pm_iir = I915_READ(GEN6_PMIIR);
 762         if (pm_iir) {
 763                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 764                         gen6_queue_rps_work(dev_priv, pm_iir);
 765                 I915_WRITE(GEN6_PMIIR, pm_iir);
 766                 ret = IRQ_HANDLED;
 767         }
 768
 769         I915_WRITE(DEIER, de_ier);
 770         POSTING_READ(DEIER);
 771         I915_WRITE(SDEIER, sde_ier);
 772         POSTING_READ(SDEIER);
 773
 774         return ret;
 775 }
 776
 777 static void ilk_gt_irq_handler(struct drm_device *dev,
 778                                struct drm_i915_private *dev_priv,
 779                                u32 gt_iir)
 780 {
 781         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 782                 notify_ring(dev, &dev_priv->ring[RCS]);
 783         if (gt_iir & GT_BSD_USER_INTERRUPT)
 784                 notify_ring(dev, &dev_priv->ring[VCS]);
 785 }
 786
 787 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 788 {
 789         struct drm_device *dev = (struct drm_device *) arg;
 790         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 791         int ret = IRQ_NONE;
 792         u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
 793
 794         atomic_inc(&dev_priv->irq_received);
 795
 796         /* disable master interrupt before clearing iir  */
 797         de_ier = I915_READ(DEIER);
 798         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 799         POSTING_READ(DEIER);
 800
 801         /* Disable south interrupts. We'll only write to SDEIIR once, so further
 802          * interrupts will will be stored on its back queue, and then we'll be
 803          * able to process them after we restore SDEIER (as soon as we restore
 804          * it, we'll get an interrupt if SDEIIR still has something to process
 805          * due to its back queue). */
 806         sde_ier = I915_READ(SDEIER);
 807         I915_WRITE(SDEIER, 0);
 808         POSTING_READ(SDEIER);
 809
 810         de_iir = I915_READ(DEIIR);
 811         gt_iir = I915_READ(GTIIR);
 812         pm_iir = I915_READ(GEN6_PMIIR);
 813
 814         if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
 815                 goto done;
 816
 817         ret = IRQ_HANDLED;
 818
 819         if (IS_GEN5(dev))
 820                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 821         else
 822                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 823
 824         if (de_iir & DE_AUX_CHANNEL_A)
 825                 dp_aux_irq_handler(dev);
 826
 827         if (de_iir & DE_GSE)
 828                 intel_opregion_gse_intr(dev);
 829
 830         if (de_iir & DE_PIPEA_VBLANK)
 831                 drm_handle_vblank(dev, 0);
 832
 833         if (de_iir & DE_PIPEB_VBLANK)
 834                 drm_handle_vblank(dev, 1);
 835
 836         if (de_iir & DE_PLANEA_FLIP_DONE) {
 837                 intel_prepare_page_flip(dev, 0);
 838                 intel_finish_page_flip_plane(dev, 0);
 839         }
 840
 841         if (de_iir & DE_PLANEB_FLIP_DONE) {
 842                 intel_prepare_page_flip(dev, 1);
 843                 intel_finish_page_flip_plane(dev, 1);
 844         }
 845
 846         /* check event from PCH */
 847         if (de_iir & DE_PCH_EVENT) {
 848                 u32 pch_iir = I915_READ(SDEIIR);
 849
 850                 if (HAS_PCH_CPT(dev))
 851                         cpt_irq_handler(dev, pch_iir);
 852                 else
 853                         ibx_irq_handler(dev, pch_iir);
 854
 855                 /* should clear PCH hotplug event before clear CPU irq */
 856                 I915_WRITE(SDEIIR, pch_iir);
 857         }
 858
 859         if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
 860                 ironlake_handle_rps_change(dev);
 861
 862         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 863                 gen6_queue_rps_work(dev_priv, pm_iir);
 864
 865         I915_WRITE(GTIIR, gt_iir);
 866         I915_WRITE(DEIIR, de_iir);
 867         I915_WRITE(GEN6_PMIIR, pm_iir);
 868
 869 done:
 870         I915_WRITE(DEIER, de_ier);
 871         POSTING_READ(DEIER);
 872         I915_WRITE(SDEIER, sde_ier);
 873         POSTING_READ(SDEIER);
 874
 875         return ret;
 876 }
 877
 878 /**
 879  * i915_error_work_func - do process context error handling work
 880  * @work: work struct
 881  *
 882  * Fire an error uevent so userspace can see that a hang or error
 883  * was detected.
 884  */
 885 static void i915_error_work_func(struct work_struct *work)
 886 {
 887         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
 888                                                     work);
 889         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
 890                                                     gpu_error);
 891         struct drm_device *dev = dev_priv->dev;
 892         struct intel_ring_buffer *ring;
 893         char *error_event[] = { "ERROR=1", NULL };
 894         char *reset_event[] = { "RESET=1", NULL };
 895         char *reset_done_event[] = { "ERROR=0", NULL };
 896         int i, ret;
 897
 898         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 899
 900         /*
 901          * Note that there's only one work item which does gpu resets, so we
 902          * need not worry about concurrent gpu resets potentially incrementing
 903          * error->reset_counter twice. We only need to take care of another
 904          * racing irq/hangcheck declaring the gpu dead for a second time. A
 905          * quick check for that is good enough: schedule_work ensures the
 906          * correct ordering between hang detection and this work item, and since
 907          * the reset in-progress bit is only ever set by code outside of this
 908          * work we don't need to worry about any other races.
 909          */
 910         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
 911                 DRM_DEBUG_DRIVER("resetting chip\n");
 912                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
 913                                    reset_event);
 914
 915                 ret = i915_reset(dev);
 916
 917                 if (ret == 0) {
 918                         /*
 919                          * After all the gem state is reset, increment the reset
 920                          * counter and wake up everyone waiting for the reset to
 921                          * complete.
 922                          *
 923                          * Since unlock operations are a one-sided barrier only,
 924                          * we need to insert a barrier here to order any seqno
 925                          * updates before
 926                          * the counter increment.
 927                          */
 928                         smp_mb__before_atomic_inc();
 929                         atomic_inc(&dev_priv->gpu_error.reset_counter);
 930
 931                         kobject_uevent_env(&dev->primary->kdev.kobj,
 932                                            KOBJ_CHANGE, reset_done_event);
 933                 } else {
 934                         atomic_set(&error->reset_counter, I915_WEDGED);
 935                 }
 936
 937                 for_each_ring(ring, dev_priv, i)
 938                         wake_up_all(&ring->irq_queue);
 939
 940                 wake_up_all(&dev_priv->gpu_error.reset_queue);
 941         }
 942 }
 943
 944 /* NB: please notice the memset */
 945 static void i915_get_extra_instdone(struct drm_device *dev,
 946                                     uint32_t *instdone)
 947 {
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
 950
 951         switch(INTEL_INFO(dev)->gen) {
 952         case 2:
 953         case 3:
 954                 instdone[0] = I915_READ(INSTDONE);
 955                 break;
 956         case 4:
 957         case 5:
 958         case 6:
 959                 instdone[0] = I915_READ(INSTDONE_I965);
 960                 instdone[1] = I915_READ(INSTDONE1);
 961                 break;
 962         default:
 963                 WARN_ONCE(1, "Unsupported platform\n");
 964         case 7:
 965                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
 966                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
 967                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
 968                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
 969                 break;
 970         }
 971 }
 972
 973 #ifdef CONFIG_DEBUG_FS
 974 static struct drm_i915_error_object *
 975 i915_error_object_create(struct drm_i915_private *dev_priv,
 976                          struct drm_i915_gem_object *src)
 977 {
 978         struct drm_i915_error_object *dst;
 979         int i, count;
 980         u32 reloc_offset;
 981
 982         if (src == NULL || src->pages == NULL)
 983                 return NULL;
 984
 985         count = src->base.size / PAGE_SIZE;
 986
 987         dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
 988         if (dst == NULL)
 989                 return NULL;
 990
 991         reloc_offset = src->gtt_offset;
 992         for (i = 0; i < count; i++) {
 993                 unsigned long flags;
 994                 void *d;
 995
 996                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 997                 if (d == NULL)
 998                         goto unwind;
 999
1000                 local_irq_save(flags);
1001                 if (reloc_offset < dev_priv->gtt.mappable_end &&
1002                     src->has_global_gtt_mapping) {
1003                         void __iomem *s;
1004
1005                         /* Simply ignore tiling or any overlapping fence.
1006                          * It's part of the error state, and this hopefully
1007                          * captures what the GPU read.
1008                          */
1009
1010                         s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1011                                                      reloc_offset);
1012                         memcpy_fromio(d, s, PAGE_SIZE);
1013                         io_mapping_unmap_atomic(s);
1014                 } else if (src->stolen) {
1015                         unsigned long offset;
1016
1017                         offset = dev_priv->mm.stolen_base;
1018                         offset += src->stolen->start;
1019                         offset += i << PAGE_SHIFT;
1020
1021                         memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1022                 } else {
1023                         struct page *page;
1024                         void *s;
1025
1026                         page = i915_gem_object_get_page(src, i);
1027
1028                         drm_clflush_pages(&page, 1);
1029
1030                         s = kmap_atomic(page);
1031                         memcpy(d, s, PAGE_SIZE);
1032                         kunmap_atomic(s);
1033
1034                         drm_clflush_pages(&page, 1);
1035                 }
1036                 local_irq_restore(flags);
1037
1038                 dst->pages[i] = d;
1039
1040                 reloc_offset += PAGE_SIZE;
1041         }
1042         dst->page_count = count;
1043         dst->gtt_offset = src->gtt_offset;
1044
1045         return dst;
1046
1047 unwind:
1048         while (i--)
1049                 kfree(dst->pages[i]);
1050         kfree(dst);
1051         return NULL;
1052 }
1053
1054 static void
1055 i915_error_object_free(struct drm_i915_error_object *obj)
1056 {
1057         int page;
1058
1059         if (obj == NULL)
1060                 return;
1061
1062         for (page = 0; page < obj->page_count; page++)
1063                 kfree(obj->pages[page]);
1064
1065         kfree(obj);
1066 }
1067
1068 void
1069 i915_error_state_free(struct kref *error_ref)
1070 {
1071         struct drm_i915_error_state *error = container_of(error_ref,
1072                                                           typeof(*error), ref);
1073         int i;
1074
1075         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1076                 i915_error_object_free(error->ring[i].batchbuffer);
1077                 i915_error_object_free(error->ring[i].ringbuffer);
1078                 kfree(error->ring[i].requests);
1079         }
1080
1081         kfree(error->active_bo);
1082         kfree(error->overlay);
1083         kfree(error);
1084 }
1085 static void capture_bo(struct drm_i915_error_buffer *err,
1086                        struct drm_i915_gem_object *obj)
1087 {
1088         err->size = obj->base.size;
1089         err->name = obj->base.name;
1090         err->rseqno = obj->last_read_seqno;
1091         err->wseqno = obj->last_write_seqno;
1092         err->gtt_offset = obj->gtt_offset;
1093         err->read_domains = obj->base.read_domains;
1094         err->write_domain = obj->base.write_domain;
1095         err->fence_reg = obj->fence_reg;
1096         err->pinned = 0;
1097         if (obj->pin_count > 0)
1098                 err->pinned = 1;
1099         if (obj->user_pin_count > 0)
1100                 err->pinned = -1;
1101         err->tiling = obj->tiling_mode;
1102         err->dirty = obj->dirty;
1103         err->purgeable = obj->madv != I915_MADV_WILLNEED;
1104         err->ring = obj->ring ? obj->ring->id : -1;
1105         err->cache_level = obj->cache_level;
1106 }
1107
1108 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1109                              int count, struct list_head *head)
1110 {
1111         struct drm_i915_gem_object *obj;
1112         int i = 0;
1113
1114         list_for_each_entry(obj, head, mm_list) {
1115                 capture_bo(err++, obj);
1116                 if (++i == count)
1117                         break;
1118         }
1119
1120         return i;
1121 }
1122
1123 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1124                              int count, struct list_head *head)
1125 {
1126         struct drm_i915_gem_object *obj;
1127         int i = 0;
1128
1129         list_for_each_entry(obj, head, gtt_list) {
1130                 if (obj->pin_count == 0)
1131                         continue;
1132
1133                 capture_bo(err++, obj);
1134                 if (++i == count)
1135                         break;
1136         }
1137
1138         return i;
1139 }
1140
1141 static void i915_gem_record_fences(struct drm_device *dev,
1142                                    struct drm_i915_error_state *error)
1143 {
1144         struct drm_i915_private *dev_priv = dev->dev_private;
1145         int i;
1146
1147         /* Fences */
1148         switch (INTEL_INFO(dev)->gen) {
1149         case 7:
1150         case 6:
1151                 for (i = 0; i < 16; i++)
1152                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1153                 break;
1154         case 5:
1155         case 4:
1156                 for (i = 0; i < 16; i++)
1157                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1158                 break;
1159         case 3:
1160                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1161                         for (i = 0; i < 8; i++)
1162                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1163         case 2:
1164                 for (i = 0; i < 8; i++)
1165                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1166                 break;
1167
1168         default:
1169                 BUG();
1170         }
1171 }
1172
1173 static struct drm_i915_error_object *
1174 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1175                              struct intel_ring_buffer *ring)
1176 {
1177         struct drm_i915_gem_object *obj;
1178         u32 seqno;
1179
1180         if (!ring->get_seqno)
1181                 return NULL;
1182
1183         if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1184                 u32 acthd = I915_READ(ACTHD);
1185
1186                 if (WARN_ON(ring->id != RCS))
1187                         return NULL;
1188
1189                 obj = ring->private;
1190                 if (acthd >= obj->gtt_offset &&
1191                     acthd < obj->gtt_offset + obj->base.size)
1192                         return i915_error_object_create(dev_priv, obj);
1193         }
1194
1195         seqno = ring->get_seqno(ring, false);
1196         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1197                 if (obj->ring != ring)
1198                         continue;
1199
1200                 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1201                         continue;
1202
1203                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1204                         continue;
1205
1206                 /* We need to copy these to an anonymous buffer as the simplest
1207                  * method to avoid being overwritten by userspace.
1208                  */
1209                 return i915_error_object_create(dev_priv, obj);
1210         }
1211
1212         return NULL;
1213 }
1214
1215 static void i915_record_ring_state(struct drm_device *dev,
1216                                    struct drm_i915_error_state *error,
1217                                    struct intel_ring_buffer *ring)
1218 {
1219         struct drm_i915_private *dev_priv = dev->dev_private;
1220
1221         if (INTEL_INFO(dev)->gen >= 6) {
1222                 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1223                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1224                 error->semaphore_mboxes[ring->id][0]
1225                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1226                 error->semaphore_mboxes[ring->id][1]
1227                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1228                 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1229                 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1230         }
1231
1232         if (INTEL_INFO(dev)->gen >= 4) {
1233                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1234                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1235                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1236                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1237                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1238                 if (ring->id == RCS)
1239                         error->bbaddr = I915_READ64(BB_ADDR);
1240         } else {
1241                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1242                 error->ipeir[ring->id] = I915_READ(IPEIR);
1243                 error->ipehr[ring->id] = I915_READ(IPEHR);
1244                 error->instdone[ring->id] = I915_READ(INSTDONE);
1245         }
1246
1247         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1248         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1249         error->seqno[ring->id] = ring->get_seqno(ring, false);
1250         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1251         error->head[ring->id] = I915_READ_HEAD(ring);
1252         error->tail[ring->id] = I915_READ_TAIL(ring);
1253         error->ctl[ring->id] = I915_READ_CTL(ring);
1254
1255         error->cpu_ring_head[ring->id] = ring->head;
1256         error->cpu_ring_tail[ring->id] = ring->tail;
1257 }
1258
1259 static void i915_gem_record_rings(struct drm_device *dev,
1260                                   struct drm_i915_error_state *error)
1261 {
1262         struct drm_i915_private *dev_priv = dev->dev_private;
1263         struct intel_ring_buffer *ring;
1264         struct drm_i915_gem_request *request;
1265         int i, count;
1266
1267         for_each_ring(ring, dev_priv, i) {
1268                 i915_record_ring_state(dev, error, ring);
1269
1270                 error->ring[i].batchbuffer =
1271                         i915_error_first_batchbuffer(dev_priv, ring);
1272
1273                 error->ring[i].ringbuffer =
1274                         i915_error_object_create(dev_priv, ring->obj);
1275
1276                 count = 0;
1277                 list_for_each_entry(request, &ring->request_list, list)
1278                         count++;
1279
1280                 error->ring[i].num_requests = count;
1281                 error->ring[i].requests =
1282                         kmalloc(count*sizeof(struct drm_i915_error_request),
1283                                 GFP_ATOMIC);
1284                 if (error->ring[i].requests == NULL) {
1285                         error->ring[i].num_requests = 0;
1286                         continue;
1287                 }
1288
1289                 count = 0;
1290                 list_for_each_entry(request, &ring->request_list, list) {
1291                         struct drm_i915_error_request *erq;
1292
1293                         erq = &error->ring[i].requests[count++];
1294                         erq->seqno = request->seqno;
1295                         erq->jiffies = request->emitted_jiffies;
1296                         erq->tail = request->tail;
1297                 }
1298         }
1299 }
1300
1301 /**
1302  * i915_capture_error_state - capture an error record for later analysis
1303  * @dev: drm device
1304  *
1305  * Should be called when an error is detected (either a hang or an error
1306  * interrupt) to capture error state from the time of the error.  Fills
1307  * out a structure which becomes available in debugfs for user level tools
1308  * to pick up.
1309  */
1310 static void i915_capture_error_state(struct drm_device *dev)
1311 {
1312         struct drm_i915_private *dev_priv = dev->dev_private;
1313         struct drm_i915_gem_object *obj;
1314         struct drm_i915_error_state *error;
1315         unsigned long flags;
1316         int i, pipe;
1317
1318         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1319         error = dev_priv->gpu_error.first_error;
1320         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1321         if (error)
1322                 return;
1323
1324         /* Account for pipe specific data like PIPE*STAT */
1325         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1326         if (!error) {
1327                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1328                 return;
1329         }
1330
1331         DRM_INFO("capturing error event; look for more information in"
1332                  "/sys/kernel/debug/dri/%d/i915_error_state\n",
1333                  dev->primary->index);
1334
1335         kref_init(&error->ref);
1336         error->eir = I915_READ(EIR);
1337         error->pgtbl_er = I915_READ(PGTBL_ER);
1338         error->ccid = I915_READ(CCID);
1339
1340         if (HAS_PCH_SPLIT(dev))
1341                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1342         else if (IS_VALLEYVIEW(dev))
1343                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1344         else if (IS_GEN2(dev))
1345                 error->ier = I915_READ16(IER);
1346         else
1347                 error->ier = I915_READ(IER);
1348
1349         if (INTEL_INFO(dev)->gen >= 6)
1350                 error->derrmr = I915_READ(DERRMR);
1351
1352         if (IS_VALLEYVIEW(dev))
1353                 error->forcewake = I915_READ(FORCEWAKE_VLV);
1354         else if (INTEL_INFO(dev)->gen >= 7)
1355                 error->forcewake = I915_READ(FORCEWAKE_MT);
1356         else if (INTEL_INFO(dev)->gen == 6)
1357                 error->forcewake = I915_READ(FORCEWAKE);
1358
1359         for_each_pipe(pipe)
1360                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1361
1362         if (INTEL_INFO(dev)->gen >= 6) {
1363                 error->error = I915_READ(ERROR_GEN6);
1364                 error->done_reg = I915_READ(DONE_REG);
1365         }
1366
1367         if (INTEL_INFO(dev)->gen == 7)
1368                 error->err_int = I915_READ(GEN7_ERR_INT);
1369
1370         i915_get_extra_instdone(dev, error->extra_instdone);
1371
1372         i915_gem_record_fences(dev, error);
1373         i915_gem_record_rings(dev, error);
1374
1375         /* Record buffers on the active and pinned lists. */
1376         error->active_bo = NULL;
1377         error->pinned_bo = NULL;
1378
1379         i = 0;
1380         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1381                 i++;
1382         error->active_bo_count = i;
1383         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1384                 if (obj->pin_count)
1385                         i++;
1386         error->pinned_bo_count = i - error->active_bo_count;
1387
1388         error->active_bo = NULL;
1389         error->pinned_bo = NULL;
1390         if (i) {
1391                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1392                                            GFP_ATOMIC);
1393                 if (error->active_bo)
1394                         error->pinned_bo =
1395                                 error->active_bo + error->active_bo_count;
1396         }
1397
1398         if (error->active_bo)
1399                 error->active_bo_count =
1400                         capture_active_bo(error->active_bo,
1401                                           error->active_bo_count,
1402                                           &dev_priv->mm.active_list);
1403
1404         if (error->pinned_bo)
1405                 error->pinned_bo_count =
1406                         capture_pinned_bo(error->pinned_bo,
1407                                           error->pinned_bo_count,
1408                                           &dev_priv->mm.bound_list);
1409
1410         do_gettimeofday(&error->time);
1411
1412         error->overlay = intel_overlay_capture_error_state(dev);
1413         error->display = intel_display_capture_error_state(dev);
1414
1415         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1416         if (dev_priv->gpu_error.first_error == NULL) {
1417                 dev_priv->gpu_error.first_error = error;
1418                 error = NULL;
1419         }
1420         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1421
1422         if (error)
1423                 i915_error_state_free(&error->ref);
1424 }
1425
1426 void i915_destroy_error_state(struct drm_device *dev)
1427 {
1428         struct drm_i915_private *dev_priv = dev->dev_private;
1429         struct drm_i915_error_state *error;
1430         unsigned long flags;
1431
1432         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1433         error = dev_priv->gpu_error.first_error;
1434         dev_priv->gpu_error.first_error = NULL;
1435         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1436
1437         if (error)
1438                 kref_put(&error->ref, i915_error_state_free);
1439 }
1440 #else
1441 #define i915_capture_error_state(x)
1442 #endif
1443
1444 static void i915_report_and_clear_eir(struct drm_device *dev)
1445 {
1446         struct drm_i915_private *dev_priv = dev->dev_private;
1447         uint32_t instdone[I915_NUM_INSTDONE_REG];
1448         u32 eir = I915_READ(EIR);
1449         int pipe, i;
1450
1451         if (!eir)
1452                 return;
1453
1454         pr_err("render error detected, EIR: 0x%08x\n", eir);
1455
1456         i915_get_extra_instdone(dev, instdone);
1457
1458         if (IS_G4X(dev)) {
1459                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1460                         u32 ipeir = I915_READ(IPEIR_I965);
1461
1462                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1463                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1464                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1465                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1466                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1467                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1468                         I915_WRITE(IPEIR_I965, ipeir);
1469                         POSTING_READ(IPEIR_I965);
1470                 }
1471                 if (eir & GM45_ERROR_PAGE_TABLE) {
1472                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1473                         pr_err("page table error\n");
1474                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1475                         I915_WRITE(PGTBL_ER, pgtbl_err);
1476                         POSTING_READ(PGTBL_ER);
1477                 }
1478         }
1479
1480         if (!IS_GEN2(dev)) {
1481                 if (eir & I915_ERROR_PAGE_TABLE) {
1482                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1483                         pr_err("page table error\n");
1484                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1485                         I915_WRITE(PGTBL_ER, pgtbl_err);
1486                         POSTING_READ(PGTBL_ER);
1487                 }
1488         }
1489
1490         if (eir & I915_ERROR_MEMORY_REFRESH) {
1491                 pr_err("memory refresh error:\n");
1492                 for_each_pipe(pipe)
1493                         pr_err("pipe %c stat: 0x%08x\n",
1494                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1495                 /* pipestat has already been acked */
1496         }
1497         if (eir & I915_ERROR_INSTRUCTION) {
1498                 pr_err("instruction error\n");
1499                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1500                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1501                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1502                 if (INTEL_INFO(dev)->gen < 4) {
1503                         u32 ipeir = I915_READ(IPEIR);
1504
1505                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1506                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1507                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1508                         I915_WRITE(IPEIR, ipeir);
1509                         POSTING_READ(IPEIR);
1510                 } else {
1511                         u32 ipeir = I915_READ(IPEIR_I965);
1512
1513                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1514                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1515                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1516                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1517                         I915_WRITE(IPEIR_I965, ipeir);
1518                         POSTING_READ(IPEIR_I965);
1519                 }
1520         }
1521
1522         I915_WRITE(EIR, eir);
1523         POSTING_READ(EIR);
1524         eir = I915_READ(EIR);
1525         if (eir) {
1526                 /*
1527                  * some errors might have become stuck,
1528                  * mask them.
1529                  */
1530                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1531                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1532                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1533         }
1534 }
1535
1536 /**
1537  * i915_handle_error - handle an error interrupt
1538  * @dev: drm device
1539  *
1540  * Do some basic checking of regsiter state at error interrupt time and
1541  * dump it to the syslog.  Also call i915_capture_error_state() to make
1542  * sure we get a record and make it available in debugfs.  Fire a uevent
1543  * so userspace knows something bad happened (should trigger collection
1544  * of a ring dump etc.).
1545  */
1546 void i915_handle_error(struct drm_device *dev, bool wedged)
1547 {
1548         struct drm_i915_private *dev_priv = dev->dev_private;
1549         struct intel_ring_buffer *ring;
1550         int i;
1551
1552         i915_capture_error_state(dev);
1553         i915_report_and_clear_eir(dev);
1554
1555         if (wedged) {
1556                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1557                                 &dev_priv->gpu_error.reset_counter);
1558
1559                 /*
1560                  * Wakeup waiting processes so that the reset work item
1561                  * doesn't deadlock trying to grab various locks.
1562                  */
1563                 for_each_ring(ring, dev_priv, i)
1564                         wake_up_all(&ring->irq_queue);
1565         }
1566
1567         queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
1568 }
1569
1570 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1571 {
1572         drm_i915_private_t *dev_priv = dev->dev_private;
1573         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1575         struct drm_i915_gem_object *obj;
1576         struct intel_unpin_work *work;
1577         unsigned long flags;
1578         bool stall_detected;
1579
1580         /* Ignore early vblank irqs */
1581         if (intel_crtc == NULL)
1582                 return;
1583
1584         spin_lock_irqsave(&dev->event_lock, flags);
1585         work = intel_crtc->unpin_work;
1586
1587         if (work == NULL ||
1588             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1589             !work->enable_stall_check) {
1590                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1591                 spin_unlock_irqrestore(&dev->event_lock, flags);
1592                 return;
1593         }
1594
1595         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1596         obj = work->pending_flip_obj;
1597         if (INTEL_INFO(dev)->gen >= 4) {
1598                 int dspsurf = DSPSURF(intel_crtc->plane);
1599                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1600                                         obj->gtt_offset;
1601         } else {
1602                 int dspaddr = DSPADDR(intel_crtc->plane);
1603                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1604                                                         crtc->y * crtc->fb->pitches[0] +
1605                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1606         }
1607
1608         spin_unlock_irqrestore(&dev->event_lock, flags);
1609
1610         if (stall_detected) {
1611                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1612                 intel_prepare_page_flip(dev, intel_crtc->plane);
1613         }
1614 }
1615
1616 /* Called from drm generic code, passed 'crtc' which
1617  * we use as a pipe index
1618  */
1619 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1620 {
1621         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1622         unsigned long irqflags;
1623
1624         if (!i915_pipe_enabled(dev, pipe))
1625                 return -EINVAL;
1626
1627         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1628         if (INTEL_INFO(dev)->gen >= 4)
1629                 i915_enable_pipestat(dev_priv, pipe,
1630                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1631         else
1632                 i915_enable_pipestat(dev_priv, pipe,
1633                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1634
1635         /* maintain vblank delivery even in deep C-states */
1636         if (dev_priv->info->gen == 3)
1637                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1638         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1639
1640         return 0;
1641 }
1642
1643 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1644 {
1645         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1646         unsigned long irqflags;
1647
1648         if (!i915_pipe_enabled(dev, pipe))
1649                 return -EINVAL;
1650
1651         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1652         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1653                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1654         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1655
1656         return 0;
1657 }
1658
1659 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1660 {
1661         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1662         unsigned long irqflags;
1663
1664         if (!i915_pipe_enabled(dev, pipe))
1665                 return -EINVAL;
1666
1667         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1668         ironlake_enable_display_irq(dev_priv,
1669                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1670         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1671
1672         return 0;
1673 }
1674
1675 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1676 {
1677         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1678         unsigned long irqflags;
1679         u32 imr;
1680
1681         if (!i915_pipe_enabled(dev, pipe))
1682                 return -EINVAL;
1683
1684         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1685         imr = I915_READ(VLV_IMR);
1686         if (pipe == 0)
1687                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1688         else
1689                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1690         I915_WRITE(VLV_IMR, imr);
1691         i915_enable_pipestat(dev_priv, pipe,
1692                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1693         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1694
1695         return 0;
1696 }
1697
1698 /* Called from drm generic code, passed 'crtc' which
1699  * we use as a pipe index
1700  */
1701 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1702 {
1703         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1704         unsigned long irqflags;
1705
1706         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1707         if (dev_priv->info->gen == 3)
1708                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1709
1710         i915_disable_pipestat(dev_priv, pipe,
1711                               PIPE_VBLANK_INTERRUPT_ENABLE |
1712                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1713         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1714 }
1715
1716 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1717 {
1718         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1719         unsigned long irqflags;
1720
1721         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1722         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1723                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1724         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1725 }
1726
1727 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1728 {
1729         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1730         unsigned long irqflags;
1731
1732         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1733         ironlake_disable_display_irq(dev_priv,
1734                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1735         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1736 }
1737
1738 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1739 {
1740         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1741         unsigned long irqflags;
1742         u32 imr;
1743
1744         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1745         i915_disable_pipestat(dev_priv, pipe,
1746                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1747         imr = I915_READ(VLV_IMR);
1748         if (pipe == 0)
1749                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1750         else
1751                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1752         I915_WRITE(VLV_IMR, imr);
1753         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1754 }
1755
1756 static u32
1757 ring_last_seqno(struct intel_ring_buffer *ring)
1758 {
1759         return list_entry(ring->request_list.prev,
1760                           struct drm_i915_gem_request, list)->seqno;
1761 }
1762
1763 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1764 {
1765         if (list_empty(&ring->request_list) ||
1766             i915_seqno_passed(ring->get_seqno(ring, false),
1767                               ring_last_seqno(ring))) {
1768                 /* Issue a wake-up to catch stuck h/w. */
1769                 if (waitqueue_active(&ring->irq_queue)) {
1770                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1771                                   ring->name);
1772                         wake_up_all(&ring->irq_queue);
1773                         *err = true;
1774                 }
1775                 return true;
1776         }
1777         return false;
1778 }
1779
1780 static bool kick_ring(struct intel_ring_buffer *ring)
1781 {
1782         struct drm_device *dev = ring->dev;
1783         struct drm_i915_private *dev_priv = dev->dev_private;
1784         u32 tmp = I915_READ_CTL(ring);
1785         if (tmp & RING_WAIT) {
1786                 DRM_ERROR("Kicking stuck wait on %s\n",
1787                           ring->name);
1788                 I915_WRITE_CTL(ring, tmp);
1789                 return true;
1790         }
1791         return false;
1792 }
1793
1794 static bool i915_hangcheck_hung(struct drm_device *dev)
1795 {
1796         drm_i915_private_t *dev_priv = dev->dev_private;
1797
1798         if (dev_priv->gpu_error.hangcheck_count++ > 1) {
1799                 bool hung = true;
1800
1801                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1802                 i915_handle_error(dev, true);
1803
1804                 if (!IS_GEN2(dev)) {
1805                         struct intel_ring_buffer *ring;
1806                         int i;
1807
1808                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1809                          * If so we can simply poke the RB_WAIT bit
1810                          * and break the hang. This should work on
1811                          * all but the second generation chipsets.
1812                          */
1813                         for_each_ring(ring, dev_priv, i)
1814                                 hung &= !kick_ring(ring);
1815                 }
1816
1817                 return hung;
1818         }
1819
1820         return false;
1821 }
1822
1823 /**
1824  * This is called when the chip hasn't reported back with completed
1825  * batchbuffers in a long time. The first time this is called we simply record
1826  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1827  * again, we assume the chip is wedged and try to fix it.
1828  */
1829 void i915_hangcheck_elapsed(unsigned long data)
1830 {
1831         struct drm_device *dev = (struct drm_device *)data;
1832         drm_i915_private_t *dev_priv = dev->dev_private;
1833         uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
1834         struct intel_ring_buffer *ring;
1835         bool err = false, idle;
1836         int i;
1837
1838         if (!i915_enable_hangcheck)
1839                 return;
1840
1841         memset(acthd, 0, sizeof(acthd));
1842         idle = true;
1843         for_each_ring(ring, dev_priv, i) {
1844             idle &= i915_hangcheck_ring_idle(ring, &err);
1845             acthd[i] = intel_ring_get_active_head(ring);
1846         }
1847
1848         /* If all work is done then ACTHD clearly hasn't advanced. */
1849         if (idle) {
1850                 if (err) {
1851                         if (i915_hangcheck_hung(dev))
1852                                 return;
1853
1854                         goto repeat;
1855                 }
1856
1857                 dev_priv->gpu_error.hangcheck_count = 0;
1858                 return;
1859         }
1860
1861         i915_get_extra_instdone(dev, instdone);
1862         if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1863                    sizeof(acthd)) == 0 &&
1864             memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1865                    sizeof(instdone)) == 0) {
1866                 if (i915_hangcheck_hung(dev))
1867                         return;
1868         } else {
1869                 dev_priv->gpu_error.hangcheck_count = 0;
1870
1871                 memcpy(dev_priv->gpu_error.last_acthd, acthd,
1872                        sizeof(acthd));
1873                 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
1874                        sizeof(instdone));
1875         }
1876
1877 repeat:
1878         /* Reset timer case chip hangs without another request being added */
1879         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
1880                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1881 }
1882
1883 /* drm_dma.h hooks
1884 */
1885 static void ironlake_irq_preinstall(struct drm_device *dev)
1886 {
1887         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1888
1889         atomic_set(&dev_priv->irq_received, 0);
1890
1891         I915_WRITE(HWSTAM, 0xeffe);
1892
1893         /* XXX hotplug from PCH */
1894
1895         I915_WRITE(DEIMR, 0xffffffff);
1896         I915_WRITE(DEIER, 0x0);
1897         POSTING_READ(DEIER);
1898
1899         /* and GT */
1900         I915_WRITE(GTIMR, 0xffffffff);
1901         I915_WRITE(GTIER, 0x0);
1902         POSTING_READ(GTIER);
1903
1904         /* south display irq */
1905         I915_WRITE(SDEIMR, 0xffffffff);
1906         I915_WRITE(SDEIER, 0x0);
1907         POSTING_READ(SDEIER);
1908 }
1909
1910 static void valleyview_irq_preinstall(struct drm_device *dev)
1911 {
1912         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1913         int pipe;
1914
1915         atomic_set(&dev_priv->irq_received, 0);
1916
1917         /* VLV magic */
1918         I915_WRITE(VLV_IMR, 0);
1919         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1920         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1921         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1922
1923         /* and GT */
1924         I915_WRITE(GTIIR, I915_READ(GTIIR));
1925         I915_WRITE(GTIIR, I915_READ(GTIIR));
1926         I915_WRITE(GTIMR, 0xffffffff);
1927         I915_WRITE(GTIER, 0x0);
1928         POSTING_READ(GTIER);
1929
1930         I915_WRITE(DPINVGTT, 0xff);
1931
1932         I915_WRITE(PORT_HOTPLUG_EN, 0);
1933         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1934         for_each_pipe(pipe)
1935                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1936         I915_WRITE(VLV_IIR, 0xffffffff);
1937         I915_WRITE(VLV_IMR, 0xffffffff);
1938         I915_WRITE(VLV_IER, 0x0);
1939         POSTING_READ(VLV_IER);
1940 }
1941
1942 /*
1943  * Enable digital hotplug on the PCH, and configure the DP short pulse
1944  * duration to 2ms (which is the minimum in the Display Port spec)
1945  *
1946  * This register is the same on all known PCH chips.
1947  */
1948
1949 static void ibx_enable_hotplug(struct drm_device *dev)
1950 {
1951         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1952         u32     hotplug;
1953
1954         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1955         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1956         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1957         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1958         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1959         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1960 }
1961
1962 static void ibx_irq_postinstall(struct drm_device *dev)
1963 {
1964         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1965         u32 mask;
1966
1967         if (HAS_PCH_IBX(dev))
1968                 mask = SDE_HOTPLUG_MASK |
1969                        SDE_GMBUS |
1970                        SDE_AUX_MASK;
1971         else
1972                 mask = SDE_HOTPLUG_MASK_CPT |
1973                        SDE_GMBUS_CPT |
1974                        SDE_AUX_MASK_CPT;
1975
1976         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1977         I915_WRITE(SDEIMR, ~mask);
1978         I915_WRITE(SDEIER, mask);
1979         POSTING_READ(SDEIER);
1980
1981         ibx_enable_hotplug(dev);
1982 }
1983
1984 static int ironlake_irq_postinstall(struct drm_device *dev)
1985 {
1986         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1987         /* enable kind of interrupts always enabled */
1988         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1989                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
1990                            DE_AUX_CHANNEL_A;
1991         u32 render_irqs;
1992
1993         dev_priv->irq_mask = ~display_mask;
1994
1995         /* should always can generate irq */
1996         I915_WRITE(DEIIR, I915_READ(DEIIR));
1997         I915_WRITE(DEIMR, dev_priv->irq_mask);
1998         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1999         POSTING_READ(DEIER);
2000
2001         dev_priv->gt_irq_mask = ~0;
2002
2003         I915_WRITE(GTIIR, I915_READ(GTIIR));
2004         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2005
2006         if (IS_GEN6(dev))
2007                 render_irqs =
2008                         GT_USER_INTERRUPT |
2009                         GEN6_BSD_USER_INTERRUPT |
2010                         GEN6_BLITTER_USER_INTERRUPT;
2011         else
2012                 render_irqs =
2013                         GT_USER_INTERRUPT |
2014                         GT_PIPE_NOTIFY |
2015                         GT_BSD_USER_INTERRUPT;
2016         I915_WRITE(GTIER, render_irqs);
2017         POSTING_READ(GTIER);
2018
2019         ibx_irq_postinstall(dev);
2020
2021         if (IS_IRONLAKE_M(dev)) {
2022                 /* Clear & enable PCU event interrupts */
2023                 I915_WRITE(DEIIR, DE_PCU_EVENT);
2024                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2025                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2026         }
2027
2028         return 0;
2029 }
2030
2031 static int ivybridge_irq_postinstall(struct drm_device *dev)
2032 {
2033         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2034         /* enable kind of interrupts always enabled */
2035         u32 display_mask =
2036                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2037                 DE_PLANEC_FLIP_DONE_IVB |
2038                 DE_PLANEB_FLIP_DONE_IVB |
2039                 DE_PLANEA_FLIP_DONE_IVB |
2040                 DE_AUX_CHANNEL_A_IVB;
2041         u32 render_irqs;
2042
2043         dev_priv->irq_mask = ~display_mask;
2044
2045         /* should always can generate irq */
2046         I915_WRITE(DEIIR, I915_READ(DEIIR));
2047         I915_WRITE(DEIMR, dev_priv->irq_mask);
2048         I915_WRITE(DEIER,
2049                    display_mask |
2050                    DE_PIPEC_VBLANK_IVB |
2051                    DE_PIPEB_VBLANK_IVB |
2052                    DE_PIPEA_VBLANK_IVB);
2053         POSTING_READ(DEIER);
2054
2055         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2056
2057         I915_WRITE(GTIIR, I915_READ(GTIIR));
2058         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2059
2060         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2061                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2062         I915_WRITE(GTIER, render_irqs);
2063         POSTING_READ(GTIER);
2064
2065         ibx_irq_postinstall(dev);
2066
2067         return 0;
2068 }
2069
2070 static int valleyview_irq_postinstall(struct drm_device *dev)
2071 {
2072         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2073         u32 enable_mask;
2074         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2075         u32 render_irqs;
2076         u16 msid;
2077
2078         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2079         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2080                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2081                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2082                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2083
2084         /*
2085          *Leave vblank interrupts masked initially.  enable/disable will
2086          * toggle them based on usage.
2087          */
2088         dev_priv->irq_mask = (~enable_mask) |
2089                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2090                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2091
2092         dev_priv->pipestat[0] = 0;
2093         dev_priv->pipestat[1] = 0;
2094
2095         /* Hack for broken MSIs on VLV */
2096         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2097         pci_read_config_word(dev->pdev, 0x98, &msid);
2098         msid &= 0xff; /* mask out delivery bits */
2099         msid |= (1<<14);
2100         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2101
2102         I915_WRITE(PORT_HOTPLUG_EN, 0);
2103         POSTING_READ(PORT_HOTPLUG_EN);
2104
2105         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2106         I915_WRITE(VLV_IER, enable_mask);
2107         I915_WRITE(VLV_IIR, 0xffffffff);
2108         I915_WRITE(PIPESTAT(0), 0xffff);
2109         I915_WRITE(PIPESTAT(1), 0xffff);
2110         POSTING_READ(VLV_IER);
2111
2112         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2113         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2114         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2115
2116         I915_WRITE(VLV_IIR, 0xffffffff);
2117         I915_WRITE(VLV_IIR, 0xffffffff);
2118
2119         I915_WRITE(GTIIR, I915_READ(GTIIR));
2120         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2121
2122         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2123                 GEN6_BLITTER_USER_INTERRUPT;
2124         I915_WRITE(GTIER, render_irqs);
2125         POSTING_READ(GTIER);
2126
2127         /* ack & enable invalid PTE error interrupts */
2128 #if 0 /* FIXME: add support to irq handler for checking these bits */
2129         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2130         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2131 #endif
2132
2133         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2134
2135         return 0;
2136 }
2137
2138 static void valleyview_hpd_irq_setup(struct drm_device *dev)
2139 {
2140         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2141         u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2142
2143         /* Note HDMI and DP share bits */
2144         if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2145                 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2146         if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2147                 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2148         if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2149                 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2150         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2151                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2152         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2153                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2154         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2155                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2156                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2157         }
2158
2159         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2160 }
2161
2162 static void valleyview_irq_uninstall(struct drm_device *dev)
2163 {
2164         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2165         int pipe;
2166
2167         if (!dev_priv)
2168                 return;
2169
2170         for_each_pipe(pipe)
2171                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2172
2173         I915_WRITE(HWSTAM, 0xffffffff);
2174         I915_WRITE(PORT_HOTPLUG_EN, 0);
2175         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2176         for_each_pipe(pipe)
2177                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2178         I915_WRITE(VLV_IIR, 0xffffffff);
2179         I915_WRITE(VLV_IMR, 0xffffffff);
2180         I915_WRITE(VLV_IER, 0x0);
2181         POSTING_READ(VLV_IER);
2182 }
2183
2184 static void ironlake_irq_uninstall(struct drm_device *dev)
2185 {
2186         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2187
2188         if (!dev_priv)
2189                 return;
2190
2191         I915_WRITE(HWSTAM, 0xffffffff);
2192
2193         I915_WRITE(DEIMR, 0xffffffff);
2194         I915_WRITE(DEIER, 0x0);
2195         I915_WRITE(DEIIR, I915_READ(DEIIR));
2196
2197         I915_WRITE(GTIMR, 0xffffffff);
2198         I915_WRITE(GTIER, 0x0);
2199         I915_WRITE(GTIIR, I915_READ(GTIIR));
2200
2201         I915_WRITE(SDEIMR, 0xffffffff);
2202         I915_WRITE(SDEIER, 0x0);
2203         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2204 }
2205
2206 static void i8xx_irq_preinstall(struct drm_device * dev)
2207 {
2208         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2209         int pipe;
2210
2211         atomic_set(&dev_priv->irq_received, 0);
2212
2213         for_each_pipe(pipe)
2214                 I915_WRITE(PIPESTAT(pipe), 0);
2215         I915_WRITE16(IMR, 0xffff);
2216         I915_WRITE16(IER, 0x0);
2217         POSTING_READ16(IER);
2218 }
2219
2220 static int i8xx_irq_postinstall(struct drm_device *dev)
2221 {
2222         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2223
2224         dev_priv->pipestat[0] = 0;
2225         dev_priv->pipestat[1] = 0;
2226
2227         I915_WRITE16(EMR,
2228                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2229
2230         /* Unmask the interrupts that we always want on. */
2231         dev_priv->irq_mask =
2232                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2233                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2234                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2235                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2236                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2237         I915_WRITE16(IMR, dev_priv->irq_mask);
2238
2239         I915_WRITE16(IER,
2240                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2241                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2242                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2243                      I915_USER_INTERRUPT);
2244         POSTING_READ16(IER);
2245
2246         return 0;
2247 }
2248
2249 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2250 {
2251         struct drm_device *dev = (struct drm_device *) arg;
2252         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2253         u16 iir, new_iir;
2254         u32 pipe_stats[2];
2255         unsigned long irqflags;
2256         int irq_received;
2257         int pipe;
2258         u16 flip_mask =
2259                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2260                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2261
2262         atomic_inc(&dev_priv->irq_received);
2263
2264         iir = I915_READ16(IIR);
2265         if (iir == 0)
2266                 return IRQ_NONE;
2267
2268         while (iir & ~flip_mask) {
2269                 /* Can't rely on pipestat interrupt bit in iir as it might
2270                  * have been cleared after the pipestat interrupt was received.
2271                  * It doesn't set the bit in iir again, but it still produces
2272                  * interrupts (for non-MSI).
2273                  */
2274                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2275                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2276                         i915_handle_error(dev, false);
2277
2278                 for_each_pipe(pipe) {
2279                         int reg = PIPESTAT(pipe);
2280                         pipe_stats[pipe] = I915_READ(reg);
2281
2282                         /*
2283                          * Clear the PIPE*STAT regs before the IIR
2284                          */
2285                         if (pipe_stats[pipe] & 0x8000ffff) {
2286                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2287                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2288                                                          pipe_name(pipe));
2289                                 I915_WRITE(reg, pipe_stats[pipe]);
2290                                 irq_received = 1;
2291                         }
2292                 }
2293                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2294
2295                 I915_WRITE16(IIR, iir & ~flip_mask);
2296                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2297
2298                 i915_update_dri1_breadcrumb(dev);
2299
2300                 if (iir & I915_USER_INTERRUPT)
2301                         notify_ring(dev, &dev_priv->ring[RCS]);
2302
2303                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2304                     drm_handle_vblank(dev, 0)) {
2305                         if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2306                                 intel_prepare_page_flip(dev, 0);
2307                                 intel_finish_page_flip(dev, 0);
2308                                 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2309                         }
2310                 }
2311
2312                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2313                     drm_handle_vblank(dev, 1)) {
2314                         if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2315                                 intel_prepare_page_flip(dev, 1);
2316                                 intel_finish_page_flip(dev, 1);
2317                                 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2318                         }
2319                 }
2320
2321                 iir = new_iir;
2322         }
2323
2324         return IRQ_HANDLED;
2325 }
2326
2327 static void i8xx_irq_uninstall(struct drm_device * dev)
2328 {
2329         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2330         int pipe;
2331
2332         for_each_pipe(pipe) {
2333                 /* Clear enable bits; then clear status bits */
2334                 I915_WRITE(PIPESTAT(pipe), 0);
2335                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2336         }
2337         I915_WRITE16(IMR, 0xffff);
2338         I915_WRITE16(IER, 0x0);
2339         I915_WRITE16(IIR, I915_READ16(IIR));
2340 }
2341
2342 static void i915_irq_preinstall(struct drm_device * dev)
2343 {
2344         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2345         int pipe;
2346
2347         atomic_set(&dev_priv->irq_received, 0);
2348
2349         if (I915_HAS_HOTPLUG(dev)) {
2350                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2351                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2352         }
2353
2354         I915_WRITE16(HWSTAM, 0xeffe);
2355         for_each_pipe(pipe)
2356                 I915_WRITE(PIPESTAT(pipe), 0);
2357         I915_WRITE(IMR, 0xffffffff);
2358         I915_WRITE(IER, 0x0);
2359         POSTING_READ(IER);
2360 }
2361
2362 static int i915_irq_postinstall(struct drm_device *dev)
2363 {
2364         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2365         u32 enable_mask;
2366
2367         dev_priv->pipestat[0] = 0;
2368         dev_priv->pipestat[1] = 0;
2369
2370         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2371
2372         /* Unmask the interrupts that we always want on. */
2373         dev_priv->irq_mask =
2374                 ~(I915_ASLE_INTERRUPT |
2375                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2376                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2377                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2378                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2379                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2380
2381         enable_mask =
2382                 I915_ASLE_INTERRUPT |
2383                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2384                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2385                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2386                 I915_USER_INTERRUPT;
2387
2388         if (I915_HAS_HOTPLUG(dev)) {
2389                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2390                 POSTING_READ(PORT_HOTPLUG_EN);
2391
2392                 /* Enable in IER... */
2393                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2394                 /* and unmask in IMR */
2395                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2396         }
2397
2398         I915_WRITE(IMR, dev_priv->irq_mask);
2399         I915_WRITE(IER, enable_mask);
2400         POSTING_READ(IER);
2401
2402         intel_opregion_enable_asle(dev);
2403
2404         return 0;
2405 }
2406
2407 static void i915_hpd_irq_setup(struct drm_device *dev)
2408 {
2409         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2410         u32 hotplug_en;
2411
2412         if (I915_HAS_HOTPLUG(dev)) {
2413                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2414
2415                 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2416                         hotplug_en |= PORTB_HOTPLUG_INT_EN;
2417                 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2418                         hotplug_en |= PORTC_HOTPLUG_INT_EN;
2419                 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2420                         hotplug_en |= PORTD_HOTPLUG_INT_EN;
2421                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2422                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2423                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2424                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2425                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2426                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2427                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2428                 }
2429
2430                 /* Ignore TV since it's buggy */
2431
2432                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2433         }
2434 }
2435
2436 static irqreturn_t i915_irq_handler(int irq, void *arg)
2437 {
2438         struct drm_device *dev = (struct drm_device *) arg;
2439         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2440         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2441         unsigned long irqflags;
2442         u32 flip_mask =
2443                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2444                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2445         u32 flip[2] = {
2446                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2447                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2448         };
2449         int pipe, ret = IRQ_NONE;
2450
2451         atomic_inc(&dev_priv->irq_received);
2452
2453         iir = I915_READ(IIR);
2454         do {
2455                 bool irq_received = (iir & ~flip_mask) != 0;
2456                 bool blc_event = false;
2457
2458                 /* Can't rely on pipestat interrupt bit in iir as it might
2459                  * have been cleared after the pipestat interrupt was received.
2460                  * It doesn't set the bit in iir again, but it still produces
2461                  * interrupts (for non-MSI).
2462                  */
2463                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2464                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2465                         i915_handle_error(dev, false);
2466
2467                 for_each_pipe(pipe) {
2468                         int reg = PIPESTAT(pipe);
2469                         pipe_stats[pipe] = I915_READ(reg);
2470
2471                         /* Clear the PIPE*STAT regs before the IIR */
2472                         if (pipe_stats[pipe] & 0x8000ffff) {
2473                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2474                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2475                                                          pipe_name(pipe));
2476                                 I915_WRITE(reg, pipe_stats[pipe]);
2477                                 irq_received = true;
2478                         }
2479                 }
2480                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2481
2482                 if (!irq_received)
2483                         break;
2484
2485                 /* Consume port.  Then clear IIR or we'll miss events */
2486                 if ((I915_HAS_HOTPLUG(dev)) &&
2487                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2488                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2489
2490                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2491                                   hotplug_status);
2492                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2493                                 queue_work(dev_priv->wq,
2494                                            &dev_priv->hotplug_work);
2495
2496                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2497                         POSTING_READ(PORT_HOTPLUG_STAT);
2498                 }
2499
2500                 I915_WRITE(IIR, iir & ~flip_mask);
2501                 new_iir = I915_READ(IIR); /* Flush posted writes */
2502
2503                 if (iir & I915_USER_INTERRUPT)
2504                         notify_ring(dev, &dev_priv->ring[RCS]);
2505
2506                 for_each_pipe(pipe) {
2507                         int plane = pipe;
2508                         if (IS_MOBILE(dev))
2509                                 plane = !plane;
2510                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2511                             drm_handle_vblank(dev, pipe)) {
2512                                 if (iir & flip[plane]) {
2513                                         intel_prepare_page_flip(dev, plane);
2514                                         intel_finish_page_flip(dev, pipe);
2515                                         flip_mask &= ~flip[plane];
2516                                 }
2517                         }
2518
2519                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2520                                 blc_event = true;
2521                 }
2522
2523                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2524                         intel_opregion_asle_intr(dev);
2525
2526                 /* With MSI, interrupts are only generated when iir
2527                  * transitions from zero to nonzero.  If another bit got
2528                  * set while we were handling the existing iir bits, then
2529                  * we would never get another interrupt.
2530                  *
2531                  * This is fine on non-MSI as well, as if we hit this path
2532                  * we avoid exiting the interrupt handler only to generate
2533                  * another one.
2534                  *
2535                  * Note that for MSI this could cause a stray interrupt report
2536                  * if an interrupt landed in the time between writing IIR and
2537                  * the posting read.  This should be rare enough to never
2538                  * trigger the 99% of 100,000 interrupts test for disabling
2539                  * stray interrupts.
2540                  */
2541                 ret = IRQ_HANDLED;
2542                 iir = new_iir;
2543         } while (iir & ~flip_mask);
2544
2545         i915_update_dri1_breadcrumb(dev);
2546
2547         return ret;
2548 }
2549
2550 static void i915_irq_uninstall(struct drm_device * dev)
2551 {
2552         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2553         int pipe;
2554
2555         if (I915_HAS_HOTPLUG(dev)) {
2556                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2557                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2558         }
2559
2560         I915_WRITE16(HWSTAM, 0xffff);
2561         for_each_pipe(pipe) {
2562                 /* Clear enable bits; then clear status bits */
2563                 I915_WRITE(PIPESTAT(pipe), 0);
2564                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2565         }
2566         I915_WRITE(IMR, 0xffffffff);
2567         I915_WRITE(IER, 0x0);
2568
2569         I915_WRITE(IIR, I915_READ(IIR));
2570 }
2571
2572 static void i965_irq_preinstall(struct drm_device * dev)
2573 {
2574         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2575         int pipe;
2576
2577         atomic_set(&dev_priv->irq_received, 0);
2578
2579         I915_WRITE(PORT_HOTPLUG_EN, 0);
2580         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2581
2582         I915_WRITE(HWSTAM, 0xeffe);
2583         for_each_pipe(pipe)
2584                 I915_WRITE(PIPESTAT(pipe), 0);
2585         I915_WRITE(IMR, 0xffffffff);
2586         I915_WRITE(IER, 0x0);
2587         POSTING_READ(IER);
2588 }
2589
2590 static int i965_irq_postinstall(struct drm_device *dev)
2591 {
2592         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2593         u32 enable_mask;
2594         u32 error_mask;
2595
2596         /* Unmask the interrupts that we always want on. */
2597         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2598                                I915_DISPLAY_PORT_INTERRUPT |
2599                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2600                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2601                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2602                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2603                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2604
2605         enable_mask = ~dev_priv->irq_mask;
2606         enable_mask |= I915_USER_INTERRUPT;
2607
2608         if (IS_G4X(dev))
2609                 enable_mask |= I915_BSD_USER_INTERRUPT;
2610
2611         dev_priv->pipestat[0] = 0;
2612         dev_priv->pipestat[1] = 0;
2613         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2614
2615         /*
2616          * Enable some error detection, note the instruction error mask
2617          * bit is reserved, so we leave it masked.
2618          */
2619         if (IS_G4X(dev)) {
2620                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2621                                GM45_ERROR_MEM_PRIV |
2622                                GM45_ERROR_CP_PRIV |
2623                                I915_ERROR_MEMORY_REFRESH);
2624         } else {
2625                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2626                                I915_ERROR_MEMORY_REFRESH);
2627         }
2628         I915_WRITE(EMR, error_mask);
2629
2630         I915_WRITE(IMR, dev_priv->irq_mask);
2631         I915_WRITE(IER, enable_mask);
2632         POSTING_READ(IER);
2633
2634         I915_WRITE(PORT_HOTPLUG_EN, 0);
2635         POSTING_READ(PORT_HOTPLUG_EN);
2636
2637         intel_opregion_enable_asle(dev);
2638
2639         return 0;
2640 }
2641
2642 static void i965_hpd_irq_setup(struct drm_device *dev)
2643 {
2644         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2645         u32 hotplug_en;
2646
2647         /* Note HDMI and DP share hotplug bits */
2648         hotplug_en = 0;
2649         if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2650                 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2651         if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2652                 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2653         if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2654                 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2655         if (IS_G4X(dev)) {
2656                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2657                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2658                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2659                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2660         } else {
2661                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2662                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2663                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2664                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2665         }
2666         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2667                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2668
2669                 /* Programming the CRT detection parameters tends
2670                    to generate a spurious hotplug event about three
2671                    seconds later.  So just do it once.
2672                    */
2673                 if (IS_G4X(dev))
2674                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2675                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2676         }
2677
2678         /* Ignore TV since it's buggy */
2679
2680         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2681 }
2682
2683 static irqreturn_t i965_irq_handler(int irq, void *arg)
2684 {
2685         struct drm_device *dev = (struct drm_device *) arg;
2686         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2687         u32 iir, new_iir;
2688         u32 pipe_stats[I915_MAX_PIPES];
2689         unsigned long irqflags;
2690         int irq_received;
2691         int ret = IRQ_NONE, pipe;
2692
2693         atomic_inc(&dev_priv->irq_received);
2694
2695         iir = I915_READ(IIR);
2696
2697         for (;;) {
2698                 bool blc_event = false;
2699
2700                 irq_received = iir != 0;
2701
2702                 /* Can't rely on pipestat interrupt bit in iir as it might
2703                  * have been cleared after the pipestat interrupt was received.
2704                  * It doesn't set the bit in iir again, but it still produces
2705                  * interrupts (for non-MSI).
2706                  */
2707                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2708                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2709                         i915_handle_error(dev, false);
2710
2711                 for_each_pipe(pipe) {
2712                         int reg = PIPESTAT(pipe);
2713                         pipe_stats[pipe] = I915_READ(reg);
2714
2715                         /*
2716                          * Clear the PIPE*STAT regs before the IIR
2717                          */
2718                         if (pipe_stats[pipe] & 0x8000ffff) {
2719                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2720                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2721                                                          pipe_name(pipe));
2722                                 I915_WRITE(reg, pipe_stats[pipe]);
2723                                 irq_received = 1;
2724                         }
2725                 }
2726                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2727
2728                 if (!irq_received)
2729                         break;
2730
2731                 ret = IRQ_HANDLED;
2732
2733                 /* Consume port.  Then clear IIR or we'll miss events */
2734                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2735                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2736
2737                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2738                                   hotplug_status);
2739                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2740                                 queue_work(dev_priv->wq,
2741                                            &dev_priv->hotplug_work);
2742
2743                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2744                         I915_READ(PORT_HOTPLUG_STAT);
2745                 }
2746
2747                 I915_WRITE(IIR, iir);
2748                 new_iir = I915_READ(IIR); /* Flush posted writes */
2749
2750                 if (iir & I915_USER_INTERRUPT)
2751                         notify_ring(dev, &dev_priv->ring[RCS]);
2752                 if (iir & I915_BSD_USER_INTERRUPT)
2753                         notify_ring(dev, &dev_priv->ring[VCS]);
2754
2755                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2756                         intel_prepare_page_flip(dev, 0);
2757
2758                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2759                         intel_prepare_page_flip(dev, 1);
2760
2761                 for_each_pipe(pipe) {
2762                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2763                             drm_handle_vblank(dev, pipe)) {
2764                                 i915_pageflip_stall_check(dev, pipe);
2765                                 intel_finish_page_flip(dev, pipe);
2766                         }
2767
2768                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2769                                 blc_event = true;
2770                 }
2771
2772
2773                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2774                         intel_opregion_asle_intr(dev);
2775
2776                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2777                         gmbus_irq_handler(dev);
2778
2779                 /* With MSI, interrupts are only generated when iir
2780                  * transitions from zero to nonzero.  If another bit got
2781                  * set while we were handling the existing iir bits, then
2782                  * we would never get another interrupt.
2783                  *
2784                  * This is fine on non-MSI as well, as if we hit this path
2785                  * we avoid exiting the interrupt handler only to generate
2786                  * another one.
2787                  *
2788                  * Note that for MSI this could cause a stray interrupt report
2789                  * if an interrupt landed in the time between writing IIR and
2790                  * the posting read.  This should be rare enough to never
2791                  * trigger the 99% of 100,000 interrupts test for disabling
2792                  * stray interrupts.
2793                  */
2794                 iir = new_iir;
2795         }
2796
2797         i915_update_dri1_breadcrumb(dev);
2798
2799         return ret;
2800 }
2801
2802 static void i965_irq_uninstall(struct drm_device * dev)
2803 {
2804         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2805         int pipe;
2806
2807         if (!dev_priv)
2808                 return;
2809
2810         I915_WRITE(PORT_HOTPLUG_EN, 0);
2811         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2812
2813         I915_WRITE(HWSTAM, 0xffffffff);
2814         for_each_pipe(pipe)
2815                 I915_WRITE(PIPESTAT(pipe), 0);
2816         I915_WRITE(IMR, 0xffffffff);
2817         I915_WRITE(IER, 0x0);
2818
2819         for_each_pipe(pipe)
2820                 I915_WRITE(PIPESTAT(pipe),
2821                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2822         I915_WRITE(IIR, I915_READ(IIR));
2823 }
2824
2825 void intel_irq_init(struct drm_device *dev)
2826 {
2827         struct drm_i915_private *dev_priv = dev->dev_private;
2828
2829         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2830         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
2831         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2832         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
2833
2834         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2835                     i915_hangcheck_elapsed,
2836                     (unsigned long) dev);
2837
2838         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
2839
2840         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2841         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2842         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2843                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2844                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2845         }
2846
2847         if (drm_core_check_feature(dev, DRIVER_MODESET))
2848                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2849         else
2850                 dev->driver->get_vblank_timestamp = NULL;
2851         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2852
2853         if (IS_VALLEYVIEW(dev)) {
2854                 dev->driver->irq_handler = valleyview_irq_handler;
2855                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2856                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2857                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2858                 dev->driver->enable_vblank = valleyview_enable_vblank;
2859                 dev->driver->disable_vblank = valleyview_disable_vblank;
2860                 dev_priv->display.hpd_irq_setup = valleyview_hpd_irq_setup;
2861         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2862                 /* Share pre & uninstall handlers with ILK/SNB */
2863                 dev->driver->irq_handler = ivybridge_irq_handler;
2864                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2865                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2866                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2867                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2868                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2869         } else if (HAS_PCH_SPLIT(dev)) {
2870                 dev->driver->irq_handler = ironlake_irq_handler;
2871                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2872                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2873                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2874                 dev->driver->enable_vblank = ironlake_enable_vblank;
2875                 dev->driver->disable_vblank = ironlake_disable_vblank;
2876         } else {
2877                 if (INTEL_INFO(dev)->gen == 2) {
2878                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2879                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2880                         dev->driver->irq_handler = i8xx_irq_handler;
2881                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2882                 } else if (INTEL_INFO(dev)->gen == 3) {
2883                         dev->driver->irq_preinstall = i915_irq_preinstall;
2884                         dev->driver->irq_postinstall = i915_irq_postinstall;
2885                         dev->driver->irq_uninstall = i915_irq_uninstall;
2886                         dev->driver->irq_handler = i915_irq_handler;
2887                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2888                 } else {
2889                         dev->driver->irq_preinstall = i965_irq_preinstall;
2890                         dev->driver->irq_postinstall = i965_irq_postinstall;
2891                         dev->driver->irq_uninstall = i965_irq_uninstall;
2892                         dev->driver->irq_handler = i965_irq_handler;
2893                         dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup;
2894                 }
2895                 dev->driver->enable_vblank = i915_enable_vblank;
2896                 dev->driver->disable_vblank = i915_disable_vblank;
2897         }
2898 }
2899
2900 void intel_hpd_init(struct drm_device *dev)
2901 {
2902         struct drm_i915_private *dev_priv = dev->dev_private;
2903
2904         if (dev_priv->display.hpd_irq_setup)
2905                 dev_priv->display.hpd_irq_setup(dev);
2906 }