drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /* For display hotplug interrupt */
  41 static void
  42 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  43 {
  44         if ((dev_priv->irq_mask & mask) != 0) {
  45                 dev_priv->irq_mask &= ~mask;
  46                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  47                 POSTING_READ(DEIMR);
  48         }
  49 }
  50
  51 static inline void
  52 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  53 {
  54         if ((dev_priv->irq_mask & mask) != mask) {
  55                 dev_priv->irq_mask |= mask;
  56                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  57                 POSTING_READ(DEIMR);
  58         }
  59 }
  60
  61 void
  62 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  63 {
  64         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  65                 u32 reg = PIPESTAT(pipe);
  66
  67                 dev_priv->pipestat[pipe] |= mask;
  68                 /* Enable the interrupt, clear any pending status */
  69                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  70                 POSTING_READ(reg);
  71         }
  72 }
  73
  74 void
  75 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  76 {
  77         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  78                 u32 reg = PIPESTAT(pipe);
  79
  80                 dev_priv->pipestat[pipe] &= ~mask;
  81                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
  82                 POSTING_READ(reg);
  83         }
  84 }
  85
  86 /**
  87  * intel_enable_asle - enable ASLE interrupt for OpRegion
  88  */
  89 void intel_enable_asle(struct drm_device *dev)
  90 {
  91         drm_i915_private_t *dev_priv = dev->dev_private;
  92         unsigned long irqflags;
  93
  94         /* FIXME: opregion/asle for VLV */
  95         if (IS_VALLEYVIEW(dev))
  96                 return;
  97
  98         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  99
 100         if (HAS_PCH_SPLIT(dev))
 101                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 102         else {
 103                 i915_enable_pipestat(dev_priv, 1,
 104                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 105                 if (INTEL_INFO(dev)->gen >= 4)
 106                         i915_enable_pipestat(dev_priv, 0,
 107                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 108         }
 109
 110         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 111 }
 112
 113 /**
 114  * i915_pipe_enabled - check if a pipe is enabled
 115  * @dev: DRM device
 116  * @pipe: pipe to check
 117  *
 118  * Reading certain registers when the pipe is disabled can hang the chip.
 119  * Use this routine to make sure the PLL is running and the pipe is active
 120  * before reading such registers if unsure.
 121  */
 122 static int
 123 i915_pipe_enabled(struct drm_device *dev, int pipe)
 124 {
 125         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 126         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 127 }
 128
 129 /* Called from drm generic code, passed a 'crtc', which
 130  * we use as a pipe index
 131  */
 132 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 133 {
 134         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 135         unsigned long high_frame;
 136         unsigned long low_frame;
 137         u32 high1, high2, low;
 138
 139         if (!i915_pipe_enabled(dev, pipe)) {
 140                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 141                                 "pipe %c\n", pipe_name(pipe));
 142                 return 0;
 143         }
 144
 145         high_frame = PIPEFRAME(pipe);
 146         low_frame = PIPEFRAMEPIXEL(pipe);
 147
 148         /*
 149          * High & low register fields aren't synchronized, so make sure
 150          * we get a low value that's stable across two reads of the high
 151          * register.
 152          */
 153         do {
 154                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 155                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 156                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 157         } while (high1 != high2);
 158
 159         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 160         low >>= PIPE_FRAME_LOW_SHIFT;
 161         return (high1 << 8) | low;
 162 }
 163
 164 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 165 {
 166         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 167         int reg = PIPE_FRMCOUNT_GM45(pipe);
 168
 169         if (!i915_pipe_enabled(dev, pipe)) {
 170                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 171                                  "pipe %c\n", pipe_name(pipe));
 172                 return 0;
 173         }
 174
 175         return I915_READ(reg);
 176 }
 177
 178 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 179                              int *vpos, int *hpos)
 180 {
 181         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 182         u32 vbl = 0, position = 0;
 183         int vbl_start, vbl_end, htotal, vtotal;
 184         bool in_vbl = true;
 185         int ret = 0;
 186
 187         if (!i915_pipe_enabled(dev, pipe)) {
 188                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 189                                  "pipe %c\n", pipe_name(pipe));
 190                 return 0;
 191         }
 192
 193         /* Get vtotal. */
 194         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 195
 196         if (INTEL_INFO(dev)->gen >= 4) {
 197                 /* No obvious pixelcount register. Only query vertical
 198                  * scanout position from Display scan line register.
 199                  */
 200                 position = I915_READ(PIPEDSL(pipe));
 201
 202                 /* Decode into vertical scanout position. Don't have
 203                  * horizontal scanout position.
 204                  */
 205                 *vpos = position & 0x1fff;
 206                 *hpos = 0;
 207         } else {
 208                 /* Have access to pixelcount since start of frame.
 209                  * We can split this into vertical and horizontal
 210                  * scanout position.
 211                  */
 212                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 213
 214                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 215                 *vpos = position / htotal;
 216                 *hpos = position - (*vpos * htotal);
 217         }
 218
 219         /* Query vblank area. */
 220         vbl = I915_READ(VBLANK(pipe));
 221
 222         /* Test position against vblank region. */
 223         vbl_start = vbl & 0x1fff;
 224         vbl_end = (vbl >> 16) & 0x1fff;
 225
 226         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 227                 in_vbl = false;
 228
 229         /* Inside "upper part" of vblank area? Apply corrective offset: */
 230         if (in_vbl && (*vpos >= vbl_start))
 231                 *vpos = *vpos - vtotal;
 232
 233         /* Readouts valid? */
 234         if (vbl > 0)
 235                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 236
 237         /* In vblank? */
 238         if (in_vbl)
 239                 ret |= DRM_SCANOUTPOS_INVBL;
 240
 241         return ret;
 242 }
 243
 244 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 245                               int *max_error,
 246                               struct timeval *vblank_time,
 247                               unsigned flags)
 248 {
 249         struct drm_i915_private *dev_priv = dev->dev_private;
 250         struct drm_crtc *crtc;
 251
 252         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 253                 DRM_ERROR("Invalid crtc %d\n", pipe);
 254                 return -EINVAL;
 255         }
 256
 257         /* Get drm_crtc to timestamp: */
 258         crtc = intel_get_crtc_for_pipe(dev, pipe);
 259         if (crtc == NULL) {
 260                 DRM_ERROR("Invalid crtc %d\n", pipe);
 261                 return -EINVAL;
 262         }
 263
 264         if (!crtc->enabled) {
 265                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 266                 return -EBUSY;
 267         }
 268
 269         /* Helper routine in DRM core does all the work: */
 270         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 271                                                      vblank_time, flags,
 272                                                      crtc);
 273 }
 274
 275 /*
 276  * Handle hotplug events outside the interrupt handler proper.
 277  */
 278 static void i915_hotplug_work_func(struct work_struct *work)
 279 {
 280         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 281                                                     hotplug_work);
 282         struct drm_device *dev = dev_priv->dev;
 283         struct drm_mode_config *mode_config = &dev->mode_config;
 284         struct intel_encoder *encoder;
 285
 286         mutex_lock(&mode_config->mutex);
 287         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 288
 289         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 290                 if (encoder->hot_plug)
 291                         encoder->hot_plug(encoder);
 292
 293         mutex_unlock(&mode_config->mutex);
 294
 295         /* Just fire off a uevent and let userspace tell us what to do */
 296         drm_helper_hpd_irq_event(dev);
 297 }
 298
 299 static void i915_handle_rps_change(struct drm_device *dev)
 300 {
 301         drm_i915_private_t *dev_priv = dev->dev_private;
 302         u32 busy_up, busy_down, max_avg, min_avg;
 303         u8 new_delay = dev_priv->cur_delay;
 304
 305         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 306         busy_up = I915_READ(RCPREVBSYTUPAVG);
 307         busy_down = I915_READ(RCPREVBSYTDNAVG);
 308         max_avg = I915_READ(RCBMAXAVG);
 309         min_avg = I915_READ(RCBMINAVG);
 310
 311         /* Handle RCS change request from hw */
 312         if (busy_up > max_avg) {
 313                 if (dev_priv->cur_delay != dev_priv->max_delay)
 314                         new_delay = dev_priv->cur_delay - 1;
 315                 if (new_delay < dev_priv->max_delay)
 316                         new_delay = dev_priv->max_delay;
 317         } else if (busy_down < min_avg) {
 318                 if (dev_priv->cur_delay != dev_priv->min_delay)
 319                         new_delay = dev_priv->cur_delay + 1;
 320                 if (new_delay > dev_priv->min_delay)
 321                         new_delay = dev_priv->min_delay;
 322         }
 323
 324         if (ironlake_set_drps(dev, new_delay))
 325                 dev_priv->cur_delay = new_delay;
 326
 327         return;
 328 }
 329
 330 static void notify_ring(struct drm_device *dev,
 331                         struct intel_ring_buffer *ring)
 332 {
 333         struct drm_i915_private *dev_priv = dev->dev_private;
 334
 335         if (ring->obj == NULL)
 336                 return;
 337
 338         trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
 339
 340         wake_up_all(&ring->irq_queue);
 341         if (i915_enable_hangcheck) {
 342                 dev_priv->hangcheck_count = 0;
 343                 mod_timer(&dev_priv->hangcheck_timer,
 344                           jiffies +
 345                           msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 346         }
 347 }
 348
 349 static void gen6_pm_rps_work(struct work_struct *work)
 350 {
 351         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 352                                                     rps_work);
 353         u32 pm_iir, pm_imr;
 354         u8 new_delay;
 355
 356         spin_lock_irq(&dev_priv->rps_lock);
 357         pm_iir = dev_priv->pm_iir;
 358         dev_priv->pm_iir = 0;
 359         pm_imr = I915_READ(GEN6_PMIMR);
 360         I915_WRITE(GEN6_PMIMR, 0);
 361         spin_unlock_irq(&dev_priv->rps_lock);
 362
 363         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 364                 return;
 365
 366         mutex_lock(&dev_priv->dev->struct_mutex);
 367
 368         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 369                 new_delay = dev_priv->cur_delay + 1;
 370         else
 371                 new_delay = dev_priv->cur_delay - 1;
 372
 373         gen6_set_rps(dev_priv->dev, new_delay);
 374
 375         mutex_unlock(&dev_priv->dev->struct_mutex);
 376 }
 377
 378 static void snb_gt_irq_handler(struct drm_device *dev,
 379                                struct drm_i915_private *dev_priv,
 380                                u32 gt_iir)
 381 {
 382
 383         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 384                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 385                 notify_ring(dev, &dev_priv->ring[RCS]);
 386         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 387                 notify_ring(dev, &dev_priv->ring[VCS]);
 388         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 389                 notify_ring(dev, &dev_priv->ring[BCS]);
 390
 391         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 392                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 393                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 394                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 395                 i915_handle_error(dev, false);
 396         }
 397 }
 398
 399 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 400                                 u32 pm_iir)
 401 {
 402         unsigned long flags;
 403
 404         /*
 405          * IIR bits should never already be set because IMR should
 406          * prevent an interrupt from being shown in IIR. The warning
 407          * displays a case where we've unsafely cleared
 408          * dev_priv->pm_iir. Although missing an interrupt of the same
 409          * type is not a problem, it displays a problem in the logic.
 410          *
 411          * The mask bit in IMR is cleared by rps_work.
 412          */
 413
 414         spin_lock_irqsave(&dev_priv->rps_lock, flags);
 415         WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 416         dev_priv->pm_iir |= pm_iir;
 417         I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 418         POSTING_READ(GEN6_PMIMR);
 419         spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 420
 421         queue_work(dev_priv->wq, &dev_priv->rps_work);
 422 }
 423
 424 static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
 425 {
 426         struct drm_device *dev = (struct drm_device *) arg;
 427         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 428         u32 iir, gt_iir, pm_iir;
 429         irqreturn_t ret = IRQ_NONE;
 430         unsigned long irqflags;
 431         int pipe;
 432         u32 pipe_stats[I915_MAX_PIPES];
 433         u32 vblank_status;
 434         int vblank = 0;
 435         bool blc_event;
 436
 437         atomic_inc(&dev_priv->irq_received);
 438
 439         vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
 440                 PIPE_VBLANK_INTERRUPT_STATUS;
 441
 442         while (true) {
 443                 iir = I915_READ(VLV_IIR);
 444                 gt_iir = I915_READ(GTIIR);
 445                 pm_iir = I915_READ(GEN6_PMIIR);
 446
 447                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 448                         goto out;
 449
 450                 ret = IRQ_HANDLED;
 451
 452                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 453
 454                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 455                 for_each_pipe(pipe) {
 456                         int reg = PIPESTAT(pipe);
 457                         pipe_stats[pipe] = I915_READ(reg);
 458
 459                         /*
 460                          * Clear the PIPE*STAT regs before the IIR
 461                          */
 462                         if (pipe_stats[pipe] & 0x8000ffff) {
 463                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 464                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 465                                                          pipe_name(pipe));
 466                                 I915_WRITE(reg, pipe_stats[pipe]);
 467                         }
 468                 }
 469                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 470
 471                 /* Consume port.  Then clear IIR or we'll miss events */
 472                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 473                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 474
 475                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 476                                          hotplug_status);
 477                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 478                                 queue_work(dev_priv->wq,
 479                                            &dev_priv->hotplug_work);
 480
 481                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 482                         I915_READ(PORT_HOTPLUG_STAT);
 483                 }
 484
 485
 486                 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
 487                         drm_handle_vblank(dev, 0);
 488                         vblank++;
 489                         intel_finish_page_flip(dev, 0);
 490                 }
 491
 492                 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
 493                         drm_handle_vblank(dev, 1);
 494                         vblank++;
 495                         intel_finish_page_flip(dev, 0);
 496                 }
 497
 498                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 499                         blc_event = true;
 500
 501                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 502                         gen6_queue_rps_work(dev_priv, pm_iir);
 503
 504                 I915_WRITE(GTIIR, gt_iir);
 505                 I915_WRITE(GEN6_PMIIR, pm_iir);
 506                 I915_WRITE(VLV_IIR, iir);
 507         }
 508
 509 out:
 510         return ret;
 511 }
 512
 513 static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
 514 {
 515         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 516         int pipe;
 517
 518         if (pch_iir & SDE_AUDIO_POWER_MASK)
 519                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 520                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 521                                  SDE_AUDIO_POWER_SHIFT);
 522
 523         if (pch_iir & SDE_GMBUS)
 524                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 525
 526         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 527                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 528
 529         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 530                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 531
 532         if (pch_iir & SDE_POISON)
 533                 DRM_ERROR("PCH poison interrupt\n");
 534
 535         if (pch_iir & SDE_FDI_MASK)
 536                 for_each_pipe(pipe)
 537                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 538                                          pipe_name(pipe),
 539                                          I915_READ(FDI_RX_IIR(pipe)));
 540
 541         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 542                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 543
 544         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 545                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 546
 547         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 548                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 549         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 550                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 551 }
 552
 553 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 554 {
 555         struct drm_device *dev = (struct drm_device *) arg;
 556         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 557         u32 de_iir, gt_iir, de_ier, pm_iir;
 558         irqreturn_t ret = IRQ_NONE;
 559         int i;
 560
 561         atomic_inc(&dev_priv->irq_received);
 562
 563         /* disable master interrupt before clearing iir  */
 564         de_ier = I915_READ(DEIER);
 565         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 566
 567         gt_iir = I915_READ(GTIIR);
 568         if (gt_iir) {
 569                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 570                 I915_WRITE(GTIIR, gt_iir);
 571                 ret = IRQ_HANDLED;
 572         }
 573
 574         de_iir = I915_READ(DEIIR);
 575         if (de_iir) {
 576                 if (de_iir & DE_GSE_IVB)
 577                         intel_opregion_gse_intr(dev);
 578
 579                 for (i = 0; i < 3; i++) {
 580                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 581                                 intel_prepare_page_flip(dev, i);
 582                                 intel_finish_page_flip_plane(dev, i);
 583                         }
 584                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 585                                 drm_handle_vblank(dev, i);
 586                 }
 587
 588                 /* check event from PCH */
 589                 if (de_iir & DE_PCH_EVENT_IVB) {
 590                         u32 pch_iir = I915_READ(SDEIIR);
 591
 592                         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 593                                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 594                         pch_irq_handler(dev, pch_iir);
 595
 596                         /* clear PCH hotplug event before clear CPU irq */
 597                         I915_WRITE(SDEIIR, pch_iir);
 598                 }
 599
 600                 I915_WRITE(DEIIR, de_iir);
 601                 ret = IRQ_HANDLED;
 602         }
 603
 604         pm_iir = I915_READ(GEN6_PMIIR);
 605         if (pm_iir) {
 606                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 607                         gen6_queue_rps_work(dev_priv, pm_iir);
 608                 I915_WRITE(GEN6_PMIIR, pm_iir);
 609                 ret = IRQ_HANDLED;
 610         }
 611
 612         I915_WRITE(DEIER, de_ier);
 613         POSTING_READ(DEIER);
 614
 615         return ret;
 616 }
 617
 618 static void ilk_gt_irq_handler(struct drm_device *dev,
 619                                struct drm_i915_private *dev_priv,
 620                                u32 gt_iir)
 621 {
 622         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 623                 notify_ring(dev, &dev_priv->ring[RCS]);
 624         if (gt_iir & GT_BSD_USER_INTERRUPT)
 625                 notify_ring(dev, &dev_priv->ring[VCS]);
 626 }
 627
 628 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 629 {
 630         struct drm_device *dev = (struct drm_device *) arg;
 631         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 632         int ret = IRQ_NONE;
 633         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 634         u32 hotplug_mask;
 635
 636         atomic_inc(&dev_priv->irq_received);
 637
 638         /* disable master interrupt before clearing iir  */
 639         de_ier = I915_READ(DEIER);
 640         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 641         POSTING_READ(DEIER);
 642
 643         de_iir = I915_READ(DEIIR);
 644         gt_iir = I915_READ(GTIIR);
 645         pch_iir = I915_READ(SDEIIR);
 646         pm_iir = I915_READ(GEN6_PMIIR);
 647
 648         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 649             (!IS_GEN6(dev) || pm_iir == 0))
 650                 goto done;
 651
 652         if (HAS_PCH_CPT(dev))
 653                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 654         else
 655                 hotplug_mask = SDE_HOTPLUG_MASK;
 656
 657         ret = IRQ_HANDLED;
 658
 659         if (IS_GEN5(dev))
 660                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 661         else
 662                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 663
 664         if (de_iir & DE_GSE)
 665                 intel_opregion_gse_intr(dev);
 666
 667         if (de_iir & DE_PLANEA_FLIP_DONE) {
 668                 intel_prepare_page_flip(dev, 0);
 669                 intel_finish_page_flip_plane(dev, 0);
 670         }
 671
 672         if (de_iir & DE_PLANEB_FLIP_DONE) {
 673                 intel_prepare_page_flip(dev, 1);
 674                 intel_finish_page_flip_plane(dev, 1);
 675         }
 676
 677         if (de_iir & DE_PIPEA_VBLANK)
 678                 drm_handle_vblank(dev, 0);
 679
 680         if (de_iir & DE_PIPEB_VBLANK)
 681                 drm_handle_vblank(dev, 1);
 682
 683         /* check event from PCH */
 684         if (de_iir & DE_PCH_EVENT) {
 685                 if (pch_iir & hotplug_mask)
 686                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 687                 pch_irq_handler(dev, pch_iir);
 688         }
 689
 690         if (de_iir & DE_PCU_EVENT) {
 691                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 692                 i915_handle_rps_change(dev);
 693         }
 694
 695         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 696                 gen6_queue_rps_work(dev_priv, pm_iir);
 697
 698         /* should clear PCH hotplug event before clear CPU irq */
 699         I915_WRITE(SDEIIR, pch_iir);
 700         I915_WRITE(GTIIR, gt_iir);
 701         I915_WRITE(DEIIR, de_iir);
 702         I915_WRITE(GEN6_PMIIR, pm_iir);
 703
 704 done:
 705         I915_WRITE(DEIER, de_ier);
 706         POSTING_READ(DEIER);
 707
 708         return ret;
 709 }
 710
 711 /**
 712  * i915_error_work_func - do process context error handling work
 713  * @work: work struct
 714  *
 715  * Fire an error uevent so userspace can see that a hang or error
 716  * was detected.
 717  */
 718 static void i915_error_work_func(struct work_struct *work)
 719 {
 720         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 721                                                     error_work);
 722         struct drm_device *dev = dev_priv->dev;
 723         char *error_event[] = { "ERROR=1", NULL };
 724         char *reset_event[] = { "RESET=1", NULL };
 725         char *reset_done_event[] = { "ERROR=0", NULL };
 726
 727         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 728
 729         if (atomic_read(&dev_priv->mm.wedged)) {
 730                 DRM_DEBUG_DRIVER("resetting chip\n");
 731                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 732                 if (!i915_reset(dev)) {
 733                         atomic_set(&dev_priv->mm.wedged, 0);
 734                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 735                 }
 736                 complete_all(&dev_priv->error_completion);
 737         }
 738 }
 739
 740 #ifdef CONFIG_DEBUG_FS
 741 static struct drm_i915_error_object *
 742 i915_error_object_create(struct drm_i915_private *dev_priv,
 743                          struct drm_i915_gem_object *src)
 744 {
 745         struct drm_i915_error_object *dst;
 746         int page, page_count;
 747         u32 reloc_offset;
 748
 749         if (src == NULL || src->pages == NULL)
 750                 return NULL;
 751
 752         page_count = src->base.size / PAGE_SIZE;
 753
 754         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
 755         if (dst == NULL)
 756                 return NULL;
 757
 758         reloc_offset = src->gtt_offset;
 759         for (page = 0; page < page_count; page++) {
 760                 unsigned long flags;
 761                 void *d;
 762
 763                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 764                 if (d == NULL)
 765                         goto unwind;
 766
 767                 local_irq_save(flags);
 768                 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
 769                     src->has_global_gtt_mapping) {
 770                         void __iomem *s;
 771
 772                         /* Simply ignore tiling or any overlapping fence.
 773                          * It's part of the error state, and this hopefully
 774                          * captures what the GPU read.
 775                          */
 776
 777                         s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 778                                                      reloc_offset);
 779                         memcpy_fromio(d, s, PAGE_SIZE);
 780                         io_mapping_unmap_atomic(s);
 781                 } else {
 782                         void *s;
 783
 784                         drm_clflush_pages(&src->pages[page], 1);
 785
 786                         s = kmap_atomic(src->pages[page]);
 787                         memcpy(d, s, PAGE_SIZE);
 788                         kunmap_atomic(s);
 789
 790                         drm_clflush_pages(&src->pages[page], 1);
 791                 }
 792                 local_irq_restore(flags);
 793
 794                 dst->pages[page] = d;
 795
 796                 reloc_offset += PAGE_SIZE;
 797         }
 798         dst->page_count = page_count;
 799         dst->gtt_offset = src->gtt_offset;
 800
 801         return dst;
 802
 803 unwind:
 804         while (page--)
 805                 kfree(dst->pages[page]);
 806         kfree(dst);
 807         return NULL;
 808 }
 809
 810 static void
 811 i915_error_object_free(struct drm_i915_error_object *obj)
 812 {
 813         int page;
 814
 815         if (obj == NULL)
 816                 return;
 817
 818         for (page = 0; page < obj->page_count; page++)
 819                 kfree(obj->pages[page]);
 820
 821         kfree(obj);
 822 }
 823
 824 void
 825 i915_error_state_free(struct kref *error_ref)
 826 {
 827         struct drm_i915_error_state *error = container_of(error_ref,
 828                                                           typeof(*error), ref);
 829         int i;
 830
 831         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 832                 i915_error_object_free(error->ring[i].batchbuffer);
 833                 i915_error_object_free(error->ring[i].ringbuffer);
 834                 kfree(error->ring[i].requests);
 835         }
 836
 837         kfree(error->active_bo);
 838         kfree(error->overlay);
 839         kfree(error);
 840 }
 841 static void capture_bo(struct drm_i915_error_buffer *err,
 842                        struct drm_i915_gem_object *obj)
 843 {
 844         err->size = obj->base.size;
 845         err->name = obj->base.name;
 846         err->seqno = obj->last_rendering_seqno;
 847         err->gtt_offset = obj->gtt_offset;
 848         err->read_domains = obj->base.read_domains;
 849         err->write_domain = obj->base.write_domain;
 850         err->fence_reg = obj->fence_reg;
 851         err->pinned = 0;
 852         if (obj->pin_count > 0)
 853                 err->pinned = 1;
 854         if (obj->user_pin_count > 0)
 855                 err->pinned = -1;
 856         err->tiling = obj->tiling_mode;
 857         err->dirty = obj->dirty;
 858         err->purgeable = obj->madv != I915_MADV_WILLNEED;
 859         err->ring = obj->ring ? obj->ring->id : -1;
 860         err->cache_level = obj->cache_level;
 861 }
 862
 863 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
 864                              int count, struct list_head *head)
 865 {
 866         struct drm_i915_gem_object *obj;
 867         int i = 0;
 868
 869         list_for_each_entry(obj, head, mm_list) {
 870                 capture_bo(err++, obj);
 871                 if (++i == count)
 872                         break;
 873         }
 874
 875         return i;
 876 }
 877
 878 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
 879                              int count, struct list_head *head)
 880 {
 881         struct drm_i915_gem_object *obj;
 882         int i = 0;
 883
 884         list_for_each_entry(obj, head, gtt_list) {
 885                 if (obj->pin_count == 0)
 886                         continue;
 887
 888                 capture_bo(err++, obj);
 889                 if (++i == count)
 890                         break;
 891         }
 892
 893         return i;
 894 }
 895
 896 static void i915_gem_record_fences(struct drm_device *dev,
 897                                    struct drm_i915_error_state *error)
 898 {
 899         struct drm_i915_private *dev_priv = dev->dev_private;
 900         int i;
 901
 902         /* Fences */
 903         switch (INTEL_INFO(dev)->gen) {
 904         case 7:
 905         case 6:
 906                 for (i = 0; i < 16; i++)
 907                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 908                 break;
 909         case 5:
 910         case 4:
 911                 for (i = 0; i < 16; i++)
 912                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 913                 break;
 914         case 3:
 915                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 916                         for (i = 0; i < 8; i++)
 917                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 918         case 2:
 919                 for (i = 0; i < 8; i++)
 920                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 921                 break;
 922
 923         }
 924 }
 925
 926 static struct drm_i915_error_object *
 927 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 928                              struct intel_ring_buffer *ring)
 929 {
 930         struct drm_i915_gem_object *obj;
 931         u32 seqno;
 932
 933         if (!ring->get_seqno)
 934                 return NULL;
 935
 936         seqno = ring->get_seqno(ring);
 937         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 938                 if (obj->ring != ring)
 939                         continue;
 940
 941                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
 942                         continue;
 943
 944                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 945                         continue;
 946
 947                 /* We need to copy these to an anonymous buffer as the simplest
 948                  * method to avoid being overwritten by userspace.
 949                  */
 950                 return i915_error_object_create(dev_priv, obj);
 951         }
 952
 953         return NULL;
 954 }
 955
 956 static void i915_record_ring_state(struct drm_device *dev,
 957                                    struct drm_i915_error_state *error,
 958                                    struct intel_ring_buffer *ring)
 959 {
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961
 962         if (INTEL_INFO(dev)->gen >= 6) {
 963                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
 964                 error->semaphore_mboxes[ring->id][0]
 965                         = I915_READ(RING_SYNC_0(ring->mmio_base));
 966                 error->semaphore_mboxes[ring->id][1]
 967                         = I915_READ(RING_SYNC_1(ring->mmio_base));
 968         }
 969
 970         if (INTEL_INFO(dev)->gen >= 4) {
 971                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
 972                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
 973                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
 974                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
 975                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
 976                 if (ring->id == RCS) {
 977                         error->instdone1 = I915_READ(INSTDONE1);
 978                         error->bbaddr = I915_READ64(BB_ADDR);
 979                 }
 980         } else {
 981                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
 982                 error->ipeir[ring->id] = I915_READ(IPEIR);
 983                 error->ipehr[ring->id] = I915_READ(IPEHR);
 984                 error->instdone[ring->id] = I915_READ(INSTDONE);
 985         }
 986
 987         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
 988         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
 989         error->seqno[ring->id] = ring->get_seqno(ring);
 990         error->acthd[ring->id] = intel_ring_get_active_head(ring);
 991         error->head[ring->id] = I915_READ_HEAD(ring);
 992         error->tail[ring->id] = I915_READ_TAIL(ring);
 993
 994         error->cpu_ring_head[ring->id] = ring->head;
 995         error->cpu_ring_tail[ring->id] = ring->tail;
 996 }
 997
 998 static void i915_gem_record_rings(struct drm_device *dev,
 999                                   struct drm_i915_error_state *error)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002         struct intel_ring_buffer *ring;
1003         struct drm_i915_gem_request *request;
1004         int i, count;
1005
1006         for_each_ring(ring, dev_priv, i) {
1007                 i915_record_ring_state(dev, error, ring);
1008
1009                 error->ring[i].batchbuffer =
1010                         i915_error_first_batchbuffer(dev_priv, ring);
1011
1012                 error->ring[i].ringbuffer =
1013                         i915_error_object_create(dev_priv, ring->obj);
1014
1015                 count = 0;
1016                 list_for_each_entry(request, &ring->request_list, list)
1017                         count++;
1018
1019                 error->ring[i].num_requests = count;
1020                 error->ring[i].requests =
1021                         kmalloc(count*sizeof(struct drm_i915_error_request),
1022                                 GFP_ATOMIC);
1023                 if (error->ring[i].requests == NULL) {
1024                         error->ring[i].num_requests = 0;
1025                         continue;
1026                 }
1027
1028                 count = 0;
1029                 list_for_each_entry(request, &ring->request_list, list) {
1030                         struct drm_i915_error_request *erq;
1031
1032                         erq = &error->ring[i].requests[count++];
1033                         erq->seqno = request->seqno;
1034                         erq->jiffies = request->emitted_jiffies;
1035                         erq->tail = request->tail;
1036                 }
1037         }
1038 }
1039
1040 /**
1041  * i915_capture_error_state - capture an error record for later analysis
1042  * @dev: drm device
1043  *
1044  * Should be called when an error is detected (either a hang or an error
1045  * interrupt) to capture error state from the time of the error.  Fills
1046  * out a structure which becomes available in debugfs for user level tools
1047  * to pick up.
1048  */
1049 static void i915_capture_error_state(struct drm_device *dev)
1050 {
1051         struct drm_i915_private *dev_priv = dev->dev_private;
1052         struct drm_i915_gem_object *obj;
1053         struct drm_i915_error_state *error;
1054         unsigned long flags;
1055         int i, pipe;
1056
1057         spin_lock_irqsave(&dev_priv->error_lock, flags);
1058         error = dev_priv->first_error;
1059         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1060         if (error)
1061                 return;
1062
1063         /* Account for pipe specific data like PIPE*STAT */
1064         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1065         if (!error) {
1066                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1067                 return;
1068         }
1069
1070         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1071                  dev->primary->index);
1072
1073         kref_init(&error->ref);
1074         error->eir = I915_READ(EIR);
1075         error->pgtbl_er = I915_READ(PGTBL_ER);
1076
1077         if (HAS_PCH_SPLIT(dev))
1078                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1079         else if (IS_VALLEYVIEW(dev))
1080                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1081         else if (IS_GEN2(dev))
1082                 error->ier = I915_READ16(IER);
1083         else
1084                 error->ier = I915_READ(IER);
1085
1086         for_each_pipe(pipe)
1087                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1088
1089         if (INTEL_INFO(dev)->gen >= 6) {
1090                 error->error = I915_READ(ERROR_GEN6);
1091                 error->done_reg = I915_READ(DONE_REG);
1092         }
1093
1094         i915_gem_record_fences(dev, error);
1095         i915_gem_record_rings(dev, error);
1096
1097         /* Record buffers on the active and pinned lists. */
1098         error->active_bo = NULL;
1099         error->pinned_bo = NULL;
1100
1101         i = 0;
1102         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1103                 i++;
1104         error->active_bo_count = i;
1105         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1106                 if (obj->pin_count)
1107                         i++;
1108         error->pinned_bo_count = i - error->active_bo_count;
1109
1110         error->active_bo = NULL;
1111         error->pinned_bo = NULL;
1112         if (i) {
1113                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1114                                            GFP_ATOMIC);
1115                 if (error->active_bo)
1116                         error->pinned_bo =
1117                                 error->active_bo + error->active_bo_count;
1118         }
1119
1120         if (error->active_bo)
1121                 error->active_bo_count =
1122                         capture_active_bo(error->active_bo,
1123                                           error->active_bo_count,
1124                                           &dev_priv->mm.active_list);
1125
1126         if (error->pinned_bo)
1127                 error->pinned_bo_count =
1128                         capture_pinned_bo(error->pinned_bo,
1129                                           error->pinned_bo_count,
1130                                           &dev_priv->mm.gtt_list);
1131
1132         do_gettimeofday(&error->time);
1133
1134         error->overlay = intel_overlay_capture_error_state(dev);
1135         error->display = intel_display_capture_error_state(dev);
1136
1137         spin_lock_irqsave(&dev_priv->error_lock, flags);
1138         if (dev_priv->first_error == NULL) {
1139                 dev_priv->first_error = error;
1140                 error = NULL;
1141         }
1142         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1143
1144         if (error)
1145                 i915_error_state_free(&error->ref);
1146 }
1147
1148 void i915_destroy_error_state(struct drm_device *dev)
1149 {
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         struct drm_i915_error_state *error;
1152         unsigned long flags;
1153
1154         spin_lock_irqsave(&dev_priv->error_lock, flags);
1155         error = dev_priv->first_error;
1156         dev_priv->first_error = NULL;
1157         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1158
1159         if (error)
1160                 kref_put(&error->ref, i915_error_state_free);
1161 }
1162 #else
1163 #define i915_capture_error_state(x)
1164 #endif
1165
1166 static void i915_report_and_clear_eir(struct drm_device *dev)
1167 {
1168         struct drm_i915_private *dev_priv = dev->dev_private;
1169         u32 eir = I915_READ(EIR);
1170         int pipe;
1171
1172         if (!eir)
1173                 return;
1174
1175         pr_err("render error detected, EIR: 0x%08x\n", eir);
1176
1177         if (IS_G4X(dev)) {
1178                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1179                         u32 ipeir = I915_READ(IPEIR_I965);
1180
1181                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1182                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1183                         pr_err("  INSTDONE: 0x%08x\n",
1184                                I915_READ(INSTDONE_I965));
1185                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1186                         pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1187                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1188                         I915_WRITE(IPEIR_I965, ipeir);
1189                         POSTING_READ(IPEIR_I965);
1190                 }
1191                 if (eir & GM45_ERROR_PAGE_TABLE) {
1192                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1193                         pr_err("page table error\n");
1194                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1195                         I915_WRITE(PGTBL_ER, pgtbl_err);
1196                         POSTING_READ(PGTBL_ER);
1197                 }
1198         }
1199
1200         if (!IS_GEN2(dev)) {
1201                 if (eir & I915_ERROR_PAGE_TABLE) {
1202                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1203                         pr_err("page table error\n");
1204                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1205                         I915_WRITE(PGTBL_ER, pgtbl_err);
1206                         POSTING_READ(PGTBL_ER);
1207                 }
1208         }
1209
1210         if (eir & I915_ERROR_MEMORY_REFRESH) {
1211                 pr_err("memory refresh error:\n");
1212                 for_each_pipe(pipe)
1213                         pr_err("pipe %c stat: 0x%08x\n",
1214                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1215                 /* pipestat has already been acked */
1216         }
1217         if (eir & I915_ERROR_INSTRUCTION) {
1218                 pr_err("instruction error\n");
1219                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1220                 if (INTEL_INFO(dev)->gen < 4) {
1221                         u32 ipeir = I915_READ(IPEIR);
1222
1223                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1224                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1225                         pr_err("  INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1226                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1227                         I915_WRITE(IPEIR, ipeir);
1228                         POSTING_READ(IPEIR);
1229                 } else {
1230                         u32 ipeir = I915_READ(IPEIR_I965);
1231
1232                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1233                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1234                         pr_err("  INSTDONE: 0x%08x\n",
1235                                I915_READ(INSTDONE_I965));
1236                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1237                         pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1238                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1239                         I915_WRITE(IPEIR_I965, ipeir);
1240                         POSTING_READ(IPEIR_I965);
1241                 }
1242         }
1243
1244         I915_WRITE(EIR, eir);
1245         POSTING_READ(EIR);
1246         eir = I915_READ(EIR);
1247         if (eir) {
1248                 /*
1249                  * some errors might have become stuck,
1250                  * mask them.
1251                  */
1252                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1253                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1254                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1255         }
1256 }
1257
1258 /**
1259  * i915_handle_error - handle an error interrupt
1260  * @dev: drm device
1261  *
1262  * Do some basic checking of regsiter state at error interrupt time and
1263  * dump it to the syslog.  Also call i915_capture_error_state() to make
1264  * sure we get a record and make it available in debugfs.  Fire a uevent
1265  * so userspace knows something bad happened (should trigger collection
1266  * of a ring dump etc.).
1267  */
1268 void i915_handle_error(struct drm_device *dev, bool wedged)
1269 {
1270         struct drm_i915_private *dev_priv = dev->dev_private;
1271         struct intel_ring_buffer *ring;
1272         int i;
1273
1274         i915_capture_error_state(dev);
1275         i915_report_and_clear_eir(dev);
1276
1277         if (wedged) {
1278                 INIT_COMPLETION(dev_priv->error_completion);
1279                 atomic_set(&dev_priv->mm.wedged, 1);
1280
1281                 /*
1282                  * Wakeup waiting processes so they don't hang
1283                  */
1284                 for_each_ring(ring, dev_priv, i)
1285                         wake_up_all(&ring->irq_queue);
1286         }
1287
1288         queue_work(dev_priv->wq, &dev_priv->error_work);
1289 }
1290
1291 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1292 {
1293         drm_i915_private_t *dev_priv = dev->dev_private;
1294         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1296         struct drm_i915_gem_object *obj;
1297         struct intel_unpin_work *work;
1298         unsigned long flags;
1299         bool stall_detected;
1300
1301         /* Ignore early vblank irqs */
1302         if (intel_crtc == NULL)
1303                 return;
1304
1305         spin_lock_irqsave(&dev->event_lock, flags);
1306         work = intel_crtc->unpin_work;
1307
1308         if (work == NULL || work->pending || !work->enable_stall_check) {
1309                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1310                 spin_unlock_irqrestore(&dev->event_lock, flags);
1311                 return;
1312         }
1313
1314         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1315         obj = work->pending_flip_obj;
1316         if (INTEL_INFO(dev)->gen >= 4) {
1317                 int dspsurf = DSPSURF(intel_crtc->plane);
1318                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1319                                         obj->gtt_offset;
1320         } else {
1321                 int dspaddr = DSPADDR(intel_crtc->plane);
1322                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1323                                                         crtc->y * crtc->fb->pitches[0] +
1324                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1325         }
1326
1327         spin_unlock_irqrestore(&dev->event_lock, flags);
1328
1329         if (stall_detected) {
1330                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1331                 intel_prepare_page_flip(dev, intel_crtc->plane);
1332         }
1333 }
1334
1335 /* Called from drm generic code, passed 'crtc' which
1336  * we use as a pipe index
1337  */
1338 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1339 {
1340         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1341         unsigned long irqflags;
1342
1343         if (!i915_pipe_enabled(dev, pipe))
1344                 return -EINVAL;
1345
1346         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1347         if (INTEL_INFO(dev)->gen >= 4)
1348                 i915_enable_pipestat(dev_priv, pipe,
1349                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1350         else
1351                 i915_enable_pipestat(dev_priv, pipe,
1352                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1353
1354         /* maintain vblank delivery even in deep C-states */
1355         if (dev_priv->info->gen == 3)
1356                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1357         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1358
1359         return 0;
1360 }
1361
1362 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1363 {
1364         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1365         unsigned long irqflags;
1366
1367         if (!i915_pipe_enabled(dev, pipe))
1368                 return -EINVAL;
1369
1370         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1371         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1372                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1373         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1374
1375         return 0;
1376 }
1377
1378 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1379 {
1380         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1381         unsigned long irqflags;
1382
1383         if (!i915_pipe_enabled(dev, pipe))
1384                 return -EINVAL;
1385
1386         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1387         ironlake_enable_display_irq(dev_priv,
1388                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1389         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1390
1391         return 0;
1392 }
1393
1394 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1395 {
1396         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1397         unsigned long irqflags;
1398         u32 dpfl, imr;
1399
1400         if (!i915_pipe_enabled(dev, pipe))
1401                 return -EINVAL;
1402
1403         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1404         dpfl = I915_READ(VLV_DPFLIPSTAT);
1405         imr = I915_READ(VLV_IMR);
1406         if (pipe == 0) {
1407                 dpfl |= PIPEA_VBLANK_INT_EN;
1408                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1409         } else {
1410                 dpfl |= PIPEA_VBLANK_INT_EN;
1411                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1412         }
1413         I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1414         I915_WRITE(VLV_IMR, imr);
1415         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1416
1417         return 0;
1418 }
1419
1420 /* Called from drm generic code, passed 'crtc' which
1421  * we use as a pipe index
1422  */
1423 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1424 {
1425         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1426         unsigned long irqflags;
1427
1428         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1429         if (dev_priv->info->gen == 3)
1430                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1431
1432         i915_disable_pipestat(dev_priv, pipe,
1433                               PIPE_VBLANK_INTERRUPT_ENABLE |
1434                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1435         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1436 }
1437
1438 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1439 {
1440         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1441         unsigned long irqflags;
1442
1443         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1444         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1445                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1446         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1447 }
1448
1449 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1450 {
1451         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1452         unsigned long irqflags;
1453
1454         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1455         ironlake_disable_display_irq(dev_priv,
1456                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1457         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1458 }
1459
1460 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1461 {
1462         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1463         unsigned long irqflags;
1464         u32 dpfl, imr;
1465
1466         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1467         dpfl = I915_READ(VLV_DPFLIPSTAT);
1468         imr = I915_READ(VLV_IMR);
1469         if (pipe == 0) {
1470                 dpfl &= ~PIPEA_VBLANK_INT_EN;
1471                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1472         } else {
1473                 dpfl &= ~PIPEB_VBLANK_INT_EN;
1474                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1475         }
1476         I915_WRITE(VLV_IMR, imr);
1477         I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1478         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1479 }
1480
1481 static u32
1482 ring_last_seqno(struct intel_ring_buffer *ring)
1483 {
1484         return list_entry(ring->request_list.prev,
1485                           struct drm_i915_gem_request, list)->seqno;
1486 }
1487
1488 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1489 {
1490         if (list_empty(&ring->request_list) ||
1491             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1492                 /* Issue a wake-up to catch stuck h/w. */
1493                 if (waitqueue_active(&ring->irq_queue)) {
1494                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1495                                   ring->name);
1496                         wake_up_all(&ring->irq_queue);
1497                         *err = true;
1498                 }
1499                 return true;
1500         }
1501         return false;
1502 }
1503
1504 static bool kick_ring(struct intel_ring_buffer *ring)
1505 {
1506         struct drm_device *dev = ring->dev;
1507         struct drm_i915_private *dev_priv = dev->dev_private;
1508         u32 tmp = I915_READ_CTL(ring);
1509         if (tmp & RING_WAIT) {
1510                 DRM_ERROR("Kicking stuck wait on %s\n",
1511                           ring->name);
1512                 I915_WRITE_CTL(ring, tmp);
1513                 return true;
1514         }
1515         return false;
1516 }
1517
1518 static bool i915_hangcheck_hung(struct drm_device *dev)
1519 {
1520         drm_i915_private_t *dev_priv = dev->dev_private;
1521
1522         if (dev_priv->hangcheck_count++ > 1) {
1523                 bool hung = true;
1524
1525                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1526                 i915_handle_error(dev, true);
1527
1528                 if (!IS_GEN2(dev)) {
1529                         struct intel_ring_buffer *ring;
1530                         int i;
1531
1532                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1533                          * If so we can simply poke the RB_WAIT bit
1534                          * and break the hang. This should work on
1535                          * all but the second generation chipsets.
1536                          */
1537                         for_each_ring(ring, dev_priv, i)
1538                                 hung &= !kick_ring(ring);
1539                 }
1540
1541                 return hung;
1542         }
1543
1544         return false;
1545 }
1546
1547 /**
1548  * This is called when the chip hasn't reported back with completed
1549  * batchbuffers in a long time. The first time this is called we simply record
1550  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1551  * again, we assume the chip is wedged and try to fix it.
1552  */
1553 void i915_hangcheck_elapsed(unsigned long data)
1554 {
1555         struct drm_device *dev = (struct drm_device *)data;
1556         drm_i915_private_t *dev_priv = dev->dev_private;
1557         uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1558         struct intel_ring_buffer *ring;
1559         bool err = false, idle;
1560         int i;
1561
1562         if (!i915_enable_hangcheck)
1563                 return;
1564
1565         memset(acthd, 0, sizeof(acthd));
1566         idle = true;
1567         for_each_ring(ring, dev_priv, i) {
1568             idle &= i915_hangcheck_ring_idle(ring, &err);
1569             acthd[i] = intel_ring_get_active_head(ring);
1570         }
1571
1572         /* If all work is done then ACTHD clearly hasn't advanced. */
1573         if (idle) {
1574                 if (err) {
1575                         if (i915_hangcheck_hung(dev))
1576                                 return;
1577
1578                         goto repeat;
1579                 }
1580
1581                 dev_priv->hangcheck_count = 0;
1582                 return;
1583         }
1584
1585         if (INTEL_INFO(dev)->gen < 4) {
1586                 instdone = I915_READ(INSTDONE);
1587                 instdone1 = 0;
1588         } else {
1589                 instdone = I915_READ(INSTDONE_I965);
1590                 instdone1 = I915_READ(INSTDONE1);
1591         }
1592
1593         if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1594             dev_priv->last_instdone == instdone &&
1595             dev_priv->last_instdone1 == instdone1) {
1596                 if (i915_hangcheck_hung(dev))
1597                         return;
1598         } else {
1599                 dev_priv->hangcheck_count = 0;
1600
1601                 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1602                 dev_priv->last_instdone = instdone;
1603                 dev_priv->last_instdone1 = instdone1;
1604         }
1605
1606 repeat:
1607         /* Reset timer case chip hangs without another request being added */
1608         mod_timer(&dev_priv->hangcheck_timer,
1609                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1610 }
1611
1612 /* drm_dma.h hooks
1613 */
1614 static void ironlake_irq_preinstall(struct drm_device *dev)
1615 {
1616         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1617
1618         atomic_set(&dev_priv->irq_received, 0);
1619
1620
1621         I915_WRITE(HWSTAM, 0xeffe);
1622
1623         /* XXX hotplug from PCH */
1624
1625         I915_WRITE(DEIMR, 0xffffffff);
1626         I915_WRITE(DEIER, 0x0);
1627         POSTING_READ(DEIER);
1628
1629         /* and GT */
1630         I915_WRITE(GTIMR, 0xffffffff);
1631         I915_WRITE(GTIER, 0x0);
1632         POSTING_READ(GTIER);
1633
1634         /* south display irq */
1635         I915_WRITE(SDEIMR, 0xffffffff);
1636         I915_WRITE(SDEIER, 0x0);
1637         POSTING_READ(SDEIER);
1638 }
1639
1640 static void valleyview_irq_preinstall(struct drm_device *dev)
1641 {
1642         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1643         int pipe;
1644
1645         atomic_set(&dev_priv->irq_received, 0);
1646
1647         /* VLV magic */
1648         I915_WRITE(VLV_IMR, 0);
1649         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1650         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1651         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1652
1653         /* and GT */
1654         I915_WRITE(GTIIR, I915_READ(GTIIR));
1655         I915_WRITE(GTIIR, I915_READ(GTIIR));
1656         I915_WRITE(GTIMR, 0xffffffff);
1657         I915_WRITE(GTIER, 0x0);
1658         POSTING_READ(GTIER);
1659
1660         I915_WRITE(DPINVGTT, 0xff);
1661
1662         I915_WRITE(PORT_HOTPLUG_EN, 0);
1663         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1664         for_each_pipe(pipe)
1665                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1666         I915_WRITE(VLV_IIR, 0xffffffff);
1667         I915_WRITE(VLV_IMR, 0xffffffff);
1668         I915_WRITE(VLV_IER, 0x0);
1669         POSTING_READ(VLV_IER);
1670 }
1671
1672 /*
1673  * Enable digital hotplug on the PCH, and configure the DP short pulse
1674  * duration to 2ms (which is the minimum in the Display Port spec)
1675  *
1676  * This register is the same on all known PCH chips.
1677  */
1678
1679 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1680 {
1681         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1682         u32     hotplug;
1683
1684         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1685         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1686         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1687         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1688         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1689         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1690 }
1691
1692 static int ironlake_irq_postinstall(struct drm_device *dev)
1693 {
1694         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1695         /* enable kind of interrupts always enabled */
1696         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1697                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1698         u32 render_irqs;
1699         u32 hotplug_mask;
1700
1701         dev_priv->irq_mask = ~display_mask;
1702
1703         /* should always can generate irq */
1704         I915_WRITE(DEIIR, I915_READ(DEIIR));
1705         I915_WRITE(DEIMR, dev_priv->irq_mask);
1706         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1707         POSTING_READ(DEIER);
1708
1709         dev_priv->gt_irq_mask = ~0;
1710
1711         I915_WRITE(GTIIR, I915_READ(GTIIR));
1712         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1713
1714         if (IS_GEN6(dev))
1715                 render_irqs =
1716                         GT_USER_INTERRUPT |
1717                         GEN6_BSD_USER_INTERRUPT |
1718                         GEN6_BLITTER_USER_INTERRUPT;
1719         else
1720                 render_irqs =
1721                         GT_USER_INTERRUPT |
1722                         GT_PIPE_NOTIFY |
1723                         GT_BSD_USER_INTERRUPT;
1724         I915_WRITE(GTIER, render_irqs);
1725         POSTING_READ(GTIER);
1726
1727         if (HAS_PCH_CPT(dev)) {
1728                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1729                                 SDE_PORTB_HOTPLUG_CPT |
1730                                 SDE_PORTC_HOTPLUG_CPT |
1731                                 SDE_PORTD_HOTPLUG_CPT);
1732         } else {
1733                 hotplug_mask = (SDE_CRT_HOTPLUG |
1734                                 SDE_PORTB_HOTPLUG |
1735                                 SDE_PORTC_HOTPLUG |
1736                                 SDE_PORTD_HOTPLUG |
1737                                 SDE_AUX_MASK);
1738         }
1739
1740         dev_priv->pch_irq_mask = ~hotplug_mask;
1741
1742         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1743         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1744         I915_WRITE(SDEIER, hotplug_mask);
1745         POSTING_READ(SDEIER);
1746
1747         ironlake_enable_pch_hotplug(dev);
1748
1749         if (IS_IRONLAKE_M(dev)) {
1750                 /* Clear & enable PCU event interrupts */
1751                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1752                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1753                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1754         }
1755
1756         return 0;
1757 }
1758
1759 static int ivybridge_irq_postinstall(struct drm_device *dev)
1760 {
1761         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1762         /* enable kind of interrupts always enabled */
1763         u32 display_mask =
1764                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1765                 DE_PLANEC_FLIP_DONE_IVB |
1766                 DE_PLANEB_FLIP_DONE_IVB |
1767                 DE_PLANEA_FLIP_DONE_IVB;
1768         u32 render_irqs;
1769         u32 hotplug_mask;
1770
1771         dev_priv->irq_mask = ~display_mask;
1772
1773         /* should always can generate irq */
1774         I915_WRITE(DEIIR, I915_READ(DEIIR));
1775         I915_WRITE(DEIMR, dev_priv->irq_mask);
1776         I915_WRITE(DEIER,
1777                    display_mask |
1778                    DE_PIPEC_VBLANK_IVB |
1779                    DE_PIPEB_VBLANK_IVB |
1780                    DE_PIPEA_VBLANK_IVB);
1781         POSTING_READ(DEIER);
1782
1783         dev_priv->gt_irq_mask = ~0;
1784
1785         I915_WRITE(GTIIR, I915_READ(GTIIR));
1786         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1787
1788         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1789                 GEN6_BLITTER_USER_INTERRUPT;
1790         I915_WRITE(GTIER, render_irqs);
1791         POSTING_READ(GTIER);
1792
1793         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1794                         SDE_PORTB_HOTPLUG_CPT |
1795                         SDE_PORTC_HOTPLUG_CPT |
1796                         SDE_PORTD_HOTPLUG_CPT);
1797         dev_priv->pch_irq_mask = ~hotplug_mask;
1798
1799         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1800         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1801         I915_WRITE(SDEIER, hotplug_mask);
1802         POSTING_READ(SDEIER);
1803
1804         ironlake_enable_pch_hotplug(dev);
1805
1806         return 0;
1807 }
1808
1809 static int valleyview_irq_postinstall(struct drm_device *dev)
1810 {
1811         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1812         u32 render_irqs;
1813         u32 enable_mask;
1814         u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1815         u16 msid;
1816
1817         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1818         enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1819                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1820
1821         dev_priv->irq_mask = ~enable_mask;
1822
1823         dev_priv->pipestat[0] = 0;
1824         dev_priv->pipestat[1] = 0;
1825
1826         /* Hack for broken MSIs on VLV */
1827         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1828         pci_read_config_word(dev->pdev, 0x98, &msid);
1829         msid &= 0xff; /* mask out delivery bits */
1830         msid |= (1<<14);
1831         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1832
1833         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1834         I915_WRITE(VLV_IER, enable_mask);
1835         I915_WRITE(VLV_IIR, 0xffffffff);
1836         I915_WRITE(PIPESTAT(0), 0xffff);
1837         I915_WRITE(PIPESTAT(1), 0xffff);
1838         POSTING_READ(VLV_IER);
1839
1840         I915_WRITE(VLV_IIR, 0xffffffff);
1841         I915_WRITE(VLV_IIR, 0xffffffff);
1842
1843         render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1844                 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1845                 GT_GEN6_BLT_USER_INTERRUPT |
1846                 GT_GEN6_BSD_USER_INTERRUPT |
1847                 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1848                 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1849                 GT_PIPE_NOTIFY |
1850                 GT_RENDER_CS_ERROR_INTERRUPT |
1851                 GT_SYNC_STATUS |
1852                 GT_USER_INTERRUPT;
1853
1854         dev_priv->gt_irq_mask = ~render_irqs;
1855
1856         I915_WRITE(GTIIR, I915_READ(GTIIR));
1857         I915_WRITE(GTIIR, I915_READ(GTIIR));
1858         I915_WRITE(GTIMR, 0);
1859         I915_WRITE(GTIER, render_irqs);
1860         POSTING_READ(GTIER);
1861
1862         /* ack & enable invalid PTE error interrupts */
1863 #if 0 /* FIXME: add support to irq handler for checking these bits */
1864         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1865         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1866 #endif
1867
1868         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1869 #if 0 /* FIXME: check register definitions; some have moved */
1870         /* Note HDMI and DP share bits */
1871         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1872                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1873         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1874                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1875         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1876                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1877         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1878                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1879         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1880                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1881         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1882                 hotplug_en |= CRT_HOTPLUG_INT_EN;
1883                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1884         }
1885 #endif
1886
1887         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1888
1889         return 0;
1890 }
1891
1892 static void valleyview_irq_uninstall(struct drm_device *dev)
1893 {
1894         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1895         int pipe;
1896
1897         if (!dev_priv)
1898                 return;
1899
1900         for_each_pipe(pipe)
1901                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1902
1903         I915_WRITE(HWSTAM, 0xffffffff);
1904         I915_WRITE(PORT_HOTPLUG_EN, 0);
1905         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1906         for_each_pipe(pipe)
1907                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1908         I915_WRITE(VLV_IIR, 0xffffffff);
1909         I915_WRITE(VLV_IMR, 0xffffffff);
1910         I915_WRITE(VLV_IER, 0x0);
1911         POSTING_READ(VLV_IER);
1912 }
1913
1914 static void ironlake_irq_uninstall(struct drm_device *dev)
1915 {
1916         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1917
1918         if (!dev_priv)
1919                 return;
1920
1921         I915_WRITE(HWSTAM, 0xffffffff);
1922
1923         I915_WRITE(DEIMR, 0xffffffff);
1924         I915_WRITE(DEIER, 0x0);
1925         I915_WRITE(DEIIR, I915_READ(DEIIR));
1926
1927         I915_WRITE(GTIMR, 0xffffffff);
1928         I915_WRITE(GTIER, 0x0);
1929         I915_WRITE(GTIIR, I915_READ(GTIIR));
1930
1931         I915_WRITE(SDEIMR, 0xffffffff);
1932         I915_WRITE(SDEIER, 0x0);
1933         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1934 }
1935
1936 static void i8xx_irq_preinstall(struct drm_device * dev)
1937 {
1938         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1939         int pipe;
1940
1941         atomic_set(&dev_priv->irq_received, 0);
1942
1943         for_each_pipe(pipe)
1944                 I915_WRITE(PIPESTAT(pipe), 0);
1945         I915_WRITE16(IMR, 0xffff);
1946         I915_WRITE16(IER, 0x0);
1947         POSTING_READ16(IER);
1948 }
1949
1950 static int i8xx_irq_postinstall(struct drm_device *dev)
1951 {
1952         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1953
1954         dev_priv->pipestat[0] = 0;
1955         dev_priv->pipestat[1] = 0;
1956
1957         I915_WRITE16(EMR,
1958                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
1959
1960         /* Unmask the interrupts that we always want on. */
1961         dev_priv->irq_mask =
1962                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1963                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1964                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
1965                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
1966                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1967         I915_WRITE16(IMR, dev_priv->irq_mask);
1968
1969         I915_WRITE16(IER,
1970                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1971                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1972                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
1973                      I915_USER_INTERRUPT);
1974         POSTING_READ16(IER);
1975
1976         return 0;
1977 }
1978
1979 static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
1980 {
1981         struct drm_device *dev = (struct drm_device *) arg;
1982         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1983         u16 iir, new_iir;
1984         u32 pipe_stats[2];
1985         unsigned long irqflags;
1986         int irq_received;
1987         int pipe;
1988         u16 flip_mask =
1989                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
1990                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
1991
1992         atomic_inc(&dev_priv->irq_received);
1993
1994         iir = I915_READ16(IIR);
1995         if (iir == 0)
1996                 return IRQ_NONE;
1997
1998         while (iir & ~flip_mask) {
1999                 /* Can't rely on pipestat interrupt bit in iir as it might
2000                  * have been cleared after the pipestat interrupt was received.
2001                  * It doesn't set the bit in iir again, but it still produces
2002                  * interrupts (for non-MSI).
2003                  */
2004                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2005                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2006                         i915_handle_error(dev, false);
2007
2008                 for_each_pipe(pipe) {
2009                         int reg = PIPESTAT(pipe);
2010                         pipe_stats[pipe] = I915_READ(reg);
2011
2012                         /*
2013                          * Clear the PIPE*STAT regs before the IIR
2014                          */
2015                         if (pipe_stats[pipe] & 0x8000ffff) {
2016                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2017                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2018                                                          pipe_name(pipe));
2019                                 I915_WRITE(reg, pipe_stats[pipe]);
2020                                 irq_received = 1;
2021                         }
2022                 }
2023                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2024
2025                 I915_WRITE16(IIR, iir & ~flip_mask);
2026                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2027
2028                 i915_update_dri1_breadcrumb(dev);
2029
2030                 if (iir & I915_USER_INTERRUPT)
2031                         notify_ring(dev, &dev_priv->ring[RCS]);
2032
2033                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2034                     drm_handle_vblank(dev, 0)) {
2035                         if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2036                                 intel_prepare_page_flip(dev, 0);
2037                                 intel_finish_page_flip(dev, 0);
2038                                 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2039                         }
2040                 }
2041
2042                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2043                     drm_handle_vblank(dev, 1)) {
2044                         if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2045                                 intel_prepare_page_flip(dev, 1);
2046                                 intel_finish_page_flip(dev, 1);
2047                                 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2048                         }
2049                 }
2050
2051                 iir = new_iir;
2052         }
2053
2054         return IRQ_HANDLED;
2055 }
2056
2057 static void i8xx_irq_uninstall(struct drm_device * dev)
2058 {
2059         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2060         int pipe;
2061
2062         for_each_pipe(pipe) {
2063                 /* Clear enable bits; then clear status bits */
2064                 I915_WRITE(PIPESTAT(pipe), 0);
2065                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2066         }
2067         I915_WRITE16(IMR, 0xffff);
2068         I915_WRITE16(IER, 0x0);
2069         I915_WRITE16(IIR, I915_READ16(IIR));
2070 }
2071
2072 static void i915_irq_preinstall(struct drm_device * dev)
2073 {
2074         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2075         int pipe;
2076
2077         atomic_set(&dev_priv->irq_received, 0);
2078
2079         if (I915_HAS_HOTPLUG(dev)) {
2080                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2081                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2082         }
2083
2084         I915_WRITE16(HWSTAM, 0xeffe);
2085         for_each_pipe(pipe)
2086                 I915_WRITE(PIPESTAT(pipe), 0);
2087         I915_WRITE(IMR, 0xffffffff);
2088         I915_WRITE(IER, 0x0);
2089         POSTING_READ(IER);
2090 }
2091
2092 static int i915_irq_postinstall(struct drm_device *dev)
2093 {
2094         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2095         u32 enable_mask;
2096
2097         dev_priv->pipestat[0] = 0;
2098         dev_priv->pipestat[1] = 0;
2099
2100         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2101
2102         /* Unmask the interrupts that we always want on. */
2103         dev_priv->irq_mask =
2104                 ~(I915_ASLE_INTERRUPT |
2105                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2106                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2107                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2108                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2109                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2110
2111         enable_mask =
2112                 I915_ASLE_INTERRUPT |
2113                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2114                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2115                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2116                 I915_USER_INTERRUPT;
2117
2118         if (I915_HAS_HOTPLUG(dev)) {
2119                 /* Enable in IER... */
2120                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2121                 /* and unmask in IMR */
2122                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2123         }
2124
2125         I915_WRITE(IMR, dev_priv->irq_mask);
2126         I915_WRITE(IER, enable_mask);
2127         POSTING_READ(IER);
2128
2129         if (I915_HAS_HOTPLUG(dev)) {
2130                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2131
2132                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2133                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2134                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2135                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2136                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2137                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2138                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2139                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2140                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2141                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2142                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2143                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2144                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2145                 }
2146
2147                 /* Ignore TV since it's buggy */
2148
2149                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2150         }
2151
2152         intel_opregion_enable_asle(dev);
2153
2154         return 0;
2155 }
2156
2157 static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2158 {
2159         struct drm_device *dev = (struct drm_device *) arg;
2160         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2161         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2162         unsigned long irqflags;
2163         u32 flip_mask =
2164                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2165                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2166         u32 flip[2] = {
2167                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2168                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2169         };
2170         int pipe, ret = IRQ_NONE;
2171
2172         atomic_inc(&dev_priv->irq_received);
2173
2174         iir = I915_READ(IIR);
2175         do {
2176                 bool irq_received = (iir & ~flip_mask) != 0;
2177                 bool blc_event = false;
2178
2179                 /* Can't rely on pipestat interrupt bit in iir as it might
2180                  * have been cleared after the pipestat interrupt was received.
2181                  * It doesn't set the bit in iir again, but it still produces
2182                  * interrupts (for non-MSI).
2183                  */
2184                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2185                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2186                         i915_handle_error(dev, false);
2187
2188                 for_each_pipe(pipe) {
2189                         int reg = PIPESTAT(pipe);
2190                         pipe_stats[pipe] = I915_READ(reg);
2191
2192                         /* Clear the PIPE*STAT regs before the IIR */
2193                         if (pipe_stats[pipe] & 0x8000ffff) {
2194                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2195                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2196                                                          pipe_name(pipe));
2197                                 I915_WRITE(reg, pipe_stats[pipe]);
2198                                 irq_received = true;
2199                         }
2200                 }
2201                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2202
2203                 if (!irq_received)
2204                         break;
2205
2206                 /* Consume port.  Then clear IIR or we'll miss events */
2207                 if ((I915_HAS_HOTPLUG(dev)) &&
2208                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2209                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2210
2211                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2212                                   hotplug_status);
2213                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2214                                 queue_work(dev_priv->wq,
2215                                            &dev_priv->hotplug_work);
2216
2217                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2218                         POSTING_READ(PORT_HOTPLUG_STAT);
2219                 }
2220
2221                 I915_WRITE(IIR, iir & ~flip_mask);
2222                 new_iir = I915_READ(IIR); /* Flush posted writes */
2223
2224                 if (iir & I915_USER_INTERRUPT)
2225                         notify_ring(dev, &dev_priv->ring[RCS]);
2226
2227                 for_each_pipe(pipe) {
2228                         int plane = pipe;
2229                         if (IS_MOBILE(dev))
2230                                 plane = !plane;
2231                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2232                             drm_handle_vblank(dev, pipe)) {
2233                                 if (iir & flip[plane]) {
2234                                         intel_prepare_page_flip(dev, plane);
2235                                         intel_finish_page_flip(dev, pipe);
2236                                         flip_mask &= ~flip[plane];
2237                                 }
2238                         }
2239
2240                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2241                                 blc_event = true;
2242                 }
2243
2244                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2245                         intel_opregion_asle_intr(dev);
2246
2247                 /* With MSI, interrupts are only generated when iir
2248                  * transitions from zero to nonzero.  If another bit got
2249                  * set while we were handling the existing iir bits, then
2250                  * we would never get another interrupt.
2251                  *
2252                  * This is fine on non-MSI as well, as if we hit this path
2253                  * we avoid exiting the interrupt handler only to generate
2254                  * another one.
2255                  *
2256                  * Note that for MSI this could cause a stray interrupt report
2257                  * if an interrupt landed in the time between writing IIR and
2258                  * the posting read.  This should be rare enough to never
2259                  * trigger the 99% of 100,000 interrupts test for disabling
2260                  * stray interrupts.
2261                  */
2262                 ret = IRQ_HANDLED;
2263                 iir = new_iir;
2264         } while (iir & ~flip_mask);
2265
2266         i915_update_dri1_breadcrumb(dev);
2267
2268         return ret;
2269 }
2270
2271 static void i915_irq_uninstall(struct drm_device * dev)
2272 {
2273         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2274         int pipe;
2275
2276         if (I915_HAS_HOTPLUG(dev)) {
2277                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2278                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2279         }
2280
2281         I915_WRITE16(HWSTAM, 0xffff);
2282         for_each_pipe(pipe) {
2283                 /* Clear enable bits; then clear status bits */
2284                 I915_WRITE(PIPESTAT(pipe), 0);
2285                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2286         }
2287         I915_WRITE(IMR, 0xffffffff);
2288         I915_WRITE(IER, 0x0);
2289
2290         I915_WRITE(IIR, I915_READ(IIR));
2291 }
2292
2293 static void i965_irq_preinstall(struct drm_device * dev)
2294 {
2295         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2296         int pipe;
2297
2298         atomic_set(&dev_priv->irq_received, 0);
2299
2300         if (I915_HAS_HOTPLUG(dev)) {
2301                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2302                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2303         }
2304
2305         I915_WRITE(HWSTAM, 0xeffe);
2306         for_each_pipe(pipe)
2307                 I915_WRITE(PIPESTAT(pipe), 0);
2308         I915_WRITE(IMR, 0xffffffff);
2309         I915_WRITE(IER, 0x0);
2310         POSTING_READ(IER);
2311 }
2312
2313 static int i965_irq_postinstall(struct drm_device *dev)
2314 {
2315         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2316         u32 enable_mask;
2317         u32 error_mask;
2318
2319         /* Unmask the interrupts that we always want on. */
2320         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2321                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2322                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2323                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2324                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2325                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2326
2327         enable_mask = ~dev_priv->irq_mask;
2328         enable_mask |= I915_USER_INTERRUPT;
2329
2330         if (IS_G4X(dev))
2331                 enable_mask |= I915_BSD_USER_INTERRUPT;
2332
2333         dev_priv->pipestat[0] = 0;
2334         dev_priv->pipestat[1] = 0;
2335
2336         if (I915_HAS_HOTPLUG(dev)) {
2337                 /* Enable in IER... */
2338                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2339                 /* and unmask in IMR */
2340                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2341         }
2342
2343         /*
2344          * Enable some error detection, note the instruction error mask
2345          * bit is reserved, so we leave it masked.
2346          */
2347         if (IS_G4X(dev)) {
2348                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2349                                GM45_ERROR_MEM_PRIV |
2350                                GM45_ERROR_CP_PRIV |
2351                                I915_ERROR_MEMORY_REFRESH);
2352         } else {
2353                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2354                                I915_ERROR_MEMORY_REFRESH);
2355         }
2356         I915_WRITE(EMR, error_mask);
2357
2358         I915_WRITE(IMR, dev_priv->irq_mask);
2359         I915_WRITE(IER, enable_mask);
2360         POSTING_READ(IER);
2361
2362         if (I915_HAS_HOTPLUG(dev)) {
2363                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2364
2365                 /* Note HDMI and DP share bits */
2366                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2367                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2368                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2369                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2370                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2371                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2372                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2373                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2374                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2375                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2376                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2377                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2378
2379                         /* Programming the CRT detection parameters tends
2380                            to generate a spurious hotplug event about three
2381                            seconds later.  So just do it once.
2382                         */
2383                         if (IS_G4X(dev))
2384                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2385                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2386                 }
2387
2388                 /* Ignore TV since it's buggy */
2389
2390                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2391         }
2392
2393         intel_opregion_enable_asle(dev);
2394
2395         return 0;
2396 }
2397
2398 static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2399 {
2400         struct drm_device *dev = (struct drm_device *) arg;
2401         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2402         u32 iir, new_iir;
2403         u32 pipe_stats[I915_MAX_PIPES];
2404         unsigned long irqflags;
2405         int irq_received;
2406         int ret = IRQ_NONE, pipe;
2407
2408         atomic_inc(&dev_priv->irq_received);
2409
2410         iir = I915_READ(IIR);
2411
2412         for (;;) {
2413                 bool blc_event = false;
2414
2415                 irq_received = iir != 0;
2416
2417                 /* Can't rely on pipestat interrupt bit in iir as it might
2418                  * have been cleared after the pipestat interrupt was received.
2419                  * It doesn't set the bit in iir again, but it still produces
2420                  * interrupts (for non-MSI).
2421                  */
2422                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2423                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2424                         i915_handle_error(dev, false);
2425
2426                 for_each_pipe(pipe) {
2427                         int reg = PIPESTAT(pipe);
2428                         pipe_stats[pipe] = I915_READ(reg);
2429
2430                         /*
2431                          * Clear the PIPE*STAT regs before the IIR
2432                          */
2433                         if (pipe_stats[pipe] & 0x8000ffff) {
2434                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2435                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2436                                                          pipe_name(pipe));
2437                                 I915_WRITE(reg, pipe_stats[pipe]);
2438                                 irq_received = 1;
2439                         }
2440                 }
2441                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2442
2443                 if (!irq_received)
2444                         break;
2445
2446                 ret = IRQ_HANDLED;
2447
2448                 /* Consume port.  Then clear IIR or we'll miss events */
2449                 if ((I915_HAS_HOTPLUG(dev)) &&
2450                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2451                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2452
2453                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2454                                   hotplug_status);
2455                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2456                                 queue_work(dev_priv->wq,
2457                                            &dev_priv->hotplug_work);
2458
2459                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2460                         I915_READ(PORT_HOTPLUG_STAT);
2461                 }
2462
2463                 I915_WRITE(IIR, iir);
2464                 new_iir = I915_READ(IIR); /* Flush posted writes */
2465
2466                 if (iir & I915_USER_INTERRUPT)
2467                         notify_ring(dev, &dev_priv->ring[RCS]);
2468                 if (iir & I915_BSD_USER_INTERRUPT)
2469                         notify_ring(dev, &dev_priv->ring[VCS]);
2470
2471                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2472                         intel_prepare_page_flip(dev, 0);
2473
2474                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2475                         intel_prepare_page_flip(dev, 1);
2476
2477                 for_each_pipe(pipe) {
2478                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2479                             drm_handle_vblank(dev, pipe)) {
2480                                 i915_pageflip_stall_check(dev, pipe);
2481                                 intel_finish_page_flip(dev, pipe);
2482                         }
2483
2484                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2485                                 blc_event = true;
2486                 }
2487
2488
2489                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2490                         intel_opregion_asle_intr(dev);
2491
2492                 /* With MSI, interrupts are only generated when iir
2493                  * transitions from zero to nonzero.  If another bit got
2494                  * set while we were handling the existing iir bits, then
2495                  * we would never get another interrupt.
2496                  *
2497                  * This is fine on non-MSI as well, as if we hit this path
2498                  * we avoid exiting the interrupt handler only to generate
2499                  * another one.
2500                  *
2501                  * Note that for MSI this could cause a stray interrupt report
2502                  * if an interrupt landed in the time between writing IIR and
2503                  * the posting read.  This should be rare enough to never
2504                  * trigger the 99% of 100,000 interrupts test for disabling
2505                  * stray interrupts.
2506                  */
2507                 iir = new_iir;
2508         }
2509
2510         i915_update_dri1_breadcrumb(dev);
2511
2512         return ret;
2513 }
2514
2515 static void i965_irq_uninstall(struct drm_device * dev)
2516 {
2517         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2518         int pipe;
2519
2520         if (!dev_priv)
2521                 return;
2522
2523         if (I915_HAS_HOTPLUG(dev)) {
2524                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2525                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2526         }
2527
2528         I915_WRITE(HWSTAM, 0xffffffff);
2529         for_each_pipe(pipe)
2530                 I915_WRITE(PIPESTAT(pipe), 0);
2531         I915_WRITE(IMR, 0xffffffff);
2532         I915_WRITE(IER, 0x0);
2533
2534         for_each_pipe(pipe)
2535                 I915_WRITE(PIPESTAT(pipe),
2536                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2537         I915_WRITE(IIR, I915_READ(IIR));
2538 }
2539
2540 void intel_irq_init(struct drm_device *dev)
2541 {
2542         struct drm_i915_private *dev_priv = dev->dev_private;
2543
2544         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2545         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2546         INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2547
2548         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2549         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2550         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2551                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2552                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2553         }
2554
2555         if (drm_core_check_feature(dev, DRIVER_MODESET))
2556                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2557         else
2558                 dev->driver->get_vblank_timestamp = NULL;
2559         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2560
2561         if (IS_VALLEYVIEW(dev)) {
2562                 dev->driver->irq_handler = valleyview_irq_handler;
2563                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2564                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2565                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2566                 dev->driver->enable_vblank = valleyview_enable_vblank;
2567                 dev->driver->disable_vblank = valleyview_disable_vblank;
2568         } else if (IS_IVYBRIDGE(dev)) {
2569                 /* Share pre & uninstall handlers with ILK/SNB */
2570                 dev->driver->irq_handler = ivybridge_irq_handler;
2571                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2572                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2573                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2574                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2575                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2576         } else if (IS_HASWELL(dev)) {
2577                 /* Share interrupts handling with IVB */
2578                 dev->driver->irq_handler = ivybridge_irq_handler;
2579                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2580                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2581                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2582                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2583                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2584         } else if (HAS_PCH_SPLIT(dev)) {
2585                 dev->driver->irq_handler = ironlake_irq_handler;
2586                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2587                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2588                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2589                 dev->driver->enable_vblank = ironlake_enable_vblank;
2590                 dev->driver->disable_vblank = ironlake_disable_vblank;
2591         } else {
2592                 if (INTEL_INFO(dev)->gen == 2) {
2593                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2594                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2595                         dev->driver->irq_handler = i8xx_irq_handler;
2596                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2597                 } else if (INTEL_INFO(dev)->gen == 3) {
2598                         /* IIR "flip pending" means done if this bit is set */
2599                         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2600
2601                         dev->driver->irq_preinstall = i915_irq_preinstall;
2602                         dev->driver->irq_postinstall = i915_irq_postinstall;
2603                         dev->driver->irq_uninstall = i915_irq_uninstall;
2604                         dev->driver->irq_handler = i915_irq_handler;
2605                 } else {
2606                         dev->driver->irq_preinstall = i965_irq_preinstall;
2607                         dev->driver->irq_postinstall = i965_irq_postinstall;
2608                         dev->driver->irq_uninstall = i965_irq_uninstall;
2609                         dev->driver->irq_handler = i965_irq_handler;
2610                 }
2611                 dev->driver->enable_vblank = i915_enable_vblank;
2612                 dev->driver->disable_vblank = i915_disable_vblank;
2613         }
2614 }