2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include <linux/string.h>
29 #include <linux/bitops.h>
31 #include <drm/i915_drm.h>
34 /** @file i915_gem_tiling.c
36 * Support for managing tiling state of buffer objects.
38 * The idea behind tiling is to increase cache hit rates by rearranging
39 * pixel data so that a group of pixel accesses are in the same cacheline.
40 * Performance improvement from doing this on the back/depth buffer are on
43 * Intel architectures make this somewhat more complicated, though, by
44 * adjustments made to addressing of data when the memory is in interleaved
45 * mode (matched pairs of DIMMS) to improve memory bandwidth.
46 * For interleaved memory, the CPU sends every sequential 64 bytes
47 * to an alternate memory channel so it can get the bandwidth from both.
49 * The GPU also rearranges its accesses for increased bandwidth to interleaved
50 * memory, and it matches what the CPU does for non-tiled. However, when tiled
51 * it does it a little differently, since one walks addresses not just in the
52 * X direction but also Y. So, along with alternating channels when bit
53 * 6 of the address flips, it also alternates when other bits flip -- Bits 9
54 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
55 * are common to both the 915 and 965-class hardware.
57 * The CPU also sometimes XORs in higher bits as well, to improve
58 * bandwidth doing strided access like we do so frequently in graphics. This
59 * is called "Channel XOR Randomization" in the MCH documentation. The result
60 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
63 * All of this bit 6 XORing has an effect on our memory management,
64 * as we need to make sure that the 3d driver can correctly address object
67 * If we don't have interleaved memory, all tiling is safe and no swizzling is
70 * When bit 17 is XORed in, we simply refuse to tile at all. Bit
71 * 17 is not just a page offset, so as we page an objet out and back in,
72 * individual pages in it will have different bit 17 addresses, resulting in
73 * each 64 bytes being swapped with its neighbor!
75 * Otherwise, if interleaved, we have to tell the 3d driver what the address
76 * swizzling it needs to do is, since it's writing with the CPU to the pages
77 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
78 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
79 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
80 * to match what the GPU expects.
84 * Detects bit 6 swizzling of address lookup between IGD access and CPU
85 * access through main memory.
88 i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
90 struct drm_i915_private *dev_priv = dev->dev_private;
91 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
92 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
94 if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
96 * On BDW+, swizzling is not used. We leave the CPU memory
97 * controller in charge of optimizing memory accesses without
98 * the extra address manipulation GPU side.
100 * VLV and CHV don't have GPU swizzling.
102 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
103 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
104 } else if (INTEL_INFO(dev)->gen >= 6) {
105 if (dev_priv->preserve_bios_swizzle) {
106 if (I915_READ(DISP_ARB_CTL) &
107 DISP_TILE_SURFACE_SWIZZLING) {
108 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
109 swizzle_y = I915_BIT_6_SWIZZLE_9;
111 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
112 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
115 uint32_t dimm_c0, dimm_c1;
116 dimm_c0 = I915_READ(MAD_DIMM_C0);
117 dimm_c1 = I915_READ(MAD_DIMM_C1);
118 dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
119 dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
120 /* Enable swizzling when the channels are populated
121 * with identically sized dimms. We don't need to check
122 * the 3rd channel because no cpu with gpu attached
123 * ships in that configuration. Also, swizzling only
124 * makes sense for 2 channels anyway. */
125 if (dimm_c0 == dimm_c1) {
126 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
127 swizzle_y = I915_BIT_6_SWIZZLE_9;
129 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
130 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
133 } else if (IS_GEN5(dev)) {
134 /* On Ironlake whatever DRAM config, GPU always do
135 * same swizzling setup.
137 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
138 swizzle_y = I915_BIT_6_SWIZZLE_9;
139 } else if (IS_GEN2(dev)) {
140 /* As far as we know, the 865 doesn't have these bit 6
143 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
144 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
145 } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
148 /* On 9xx chipsets, channel interleave by the CPU is
149 * determined by DCC. For single-channel, neither the CPU
150 * nor the GPU do swizzling. For dual channel interleaved,
151 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
152 * 9 for Y tiled. The CPU's interleave is independent, and
153 * can be based on either bit 11 (haven't seen this yet) or
156 dcc = I915_READ(DCC);
157 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
158 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
159 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
160 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
161 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
163 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
164 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
165 /* This is the base swizzling by the GPU for
168 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
169 swizzle_y = I915_BIT_6_SWIZZLE_9;
170 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
171 /* Bit 11 swizzling by the CPU in addition. */
172 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
173 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
175 /* Bit 17 swizzling by the CPU in addition. */
176 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
177 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
182 /* check for L-shaped memory aka modified enhanced addressing */
184 uint32_t ddc2 = I915_READ(DCC2);
186 if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE)) {
187 /* Since the swizzling may vary within an
188 * object, we have no idea what the swizzling
189 * is for any page in particular. Thus we
190 * cannot migrate tiled pages using the GPU,
191 * nor can we tell userspace what the exact
192 * swizzling is for any object.
194 dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
195 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
196 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
200 if (dcc == 0xffffffff) {
201 DRM_ERROR("Couldn't read from MCHBAR. "
202 "Disabling tiling.\n");
203 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
204 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
207 /* The 965, G33, and newer, have a very flexible memory
208 * configuration. It will enable dual-channel mode
209 * (interleaving) on as much memory as it can, and the GPU
210 * will additionally sometimes enable different bit 6
211 * swizzling for tiled objects from the CPU.
213 * Here's what I found on the G965:
214 * slot fill memory size swizzling
215 * 0A 0B 1A 1B 1-ch 2-ch
217 * 512 0 512 0 16 1008 X
218 * 512 0 0 512 16 1008 X
219 * 0 512 0 512 16 1008 X
220 * 1024 1024 1024 0 2048 1024 O
222 * We could probably detect this based on either the DRB
223 * matching, which was the case for the swizzling required in
224 * the table above, or from the 1-ch value being less than
225 * the minimum size of a rank.
227 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
228 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
229 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
231 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
232 swizzle_y = I915_BIT_6_SWIZZLE_9;
236 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
237 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
240 /* Check pitch constriants for all chips & tiling formats */
242 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
246 /* Linear is always fine */
247 if (tiling_mode == I915_TILING_NONE)
251 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
256 /* check maximum stride & object size */
257 /* i965+ stores the end address of the gtt mapping in the fence
258 * reg, so dont bother to check the size */
259 if (INTEL_INFO(dev)->gen >= 7) {
260 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
262 } else if (INTEL_INFO(dev)->gen >= 4) {
263 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
270 if (size > I830_FENCE_MAX_SIZE_VAL << 20)
273 if (size > I830_FENCE_MAX_SIZE_VAL << 19)
278 if (stride < tile_width)
281 /* 965+ just needs multiples of tile width */
282 if (INTEL_INFO(dev)->gen >= 4) {
283 if (stride & (tile_width - 1))
288 /* Pre-965 needs power of two tile widths */
289 if (stride & (stride - 1))
295 /* Is the current GTT allocation valid for the change in tiling? */
297 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
301 if (tiling_mode == I915_TILING_NONE)
304 if (INTEL_INFO(obj->base.dev)->gen >= 4)
307 if (INTEL_INFO(obj->base.dev)->gen == 3) {
308 if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
311 if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
315 size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
316 if (i915_gem_obj_ggtt_size(obj) != size)
319 if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
326 * Sets the tiling mode of an object, returning the required swizzling of
327 * bit 6 of addresses in the object.
330 i915_gem_set_tiling(struct drm_device *dev, void *data,
331 struct drm_file *file)
333 struct drm_i915_gem_set_tiling *args = data;
334 struct drm_i915_private *dev_priv = dev->dev_private;
335 struct drm_i915_gem_object *obj;
338 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
339 if (&obj->base == NULL)
342 if (!i915_tiling_ok(dev,
343 args->stride, obj->base.size, args->tiling_mode)) {
344 drm_gem_object_unreference_unlocked(&obj->base);
348 mutex_lock(&dev->struct_mutex);
349 if (obj->pin_display || obj->framebuffer_references) {
354 if (args->tiling_mode == I915_TILING_NONE) {
355 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
358 if (args->tiling_mode == I915_TILING_X)
359 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
361 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
363 /* Hide bit 17 swizzling from the user. This prevents old Mesa
364 * from aborting the application on sw fallbacks to bit 17,
365 * and we use the pread/pwrite bit17 paths to swizzle for it.
366 * If there was a user that was relying on the swizzle
367 * information for drm_intel_bo_map()ed reads/writes this would
368 * break it, but we don't have any of those.
370 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
371 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
372 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
373 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
375 /* If we can't handle the swizzling, make it untiled. */
376 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
377 args->tiling_mode = I915_TILING_NONE;
378 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
383 if (args->tiling_mode != obj->tiling_mode ||
384 args->stride != obj->stride) {
385 /* We need to rebind the object if its current allocation
386 * no longer meets the alignment restrictions for its new
387 * tiling mode. Otherwise we can just leave it alone, but
388 * need to ensure that any fence register is updated before
389 * the next fenced (either through the GTT or by the BLT unit
390 * on older GPUs) access.
392 * After updating the tiling parameters, we then flag whether
393 * we need to update an associated fence register. Note this
394 * has to also include the unfenced register the GPU uses
395 * whilst executing a fenced command for an untiled object.
397 if (obj->map_and_fenceable &&
398 !i915_gem_object_fence_ok(obj, args->tiling_mode))
399 ret = i915_gem_object_ggtt_unbind(obj);
403 obj->madv == I915_MADV_WILLNEED &&
404 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
405 if (args->tiling_mode == I915_TILING_NONE)
406 i915_gem_object_unpin_pages(obj);
407 if (obj->tiling_mode == I915_TILING_NONE)
408 i915_gem_object_pin_pages(obj);
412 obj->last_fenced_req ||
413 obj->fence_reg != I915_FENCE_REG_NONE;
415 obj->tiling_mode = args->tiling_mode;
416 obj->stride = args->stride;
418 /* Force the fence to be reacquired for GTT access */
419 i915_gem_release_mmap(obj);
422 /* we have to maintain this existing ABI... */
423 args->stride = obj->stride;
424 args->tiling_mode = obj->tiling_mode;
426 /* Try to preallocate memory required to save swizzling on put-pages */
427 if (i915_gem_object_needs_bit17_swizzle(obj)) {
428 if (obj->bit_17 == NULL) {
429 obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
430 sizeof(long), GFP_KERNEL);
438 drm_gem_object_unreference(&obj->base);
439 mutex_unlock(&dev->struct_mutex);
445 * Returns the current tiling mode and required bit 6 swizzling for the object.
448 i915_gem_get_tiling(struct drm_device *dev, void *data,
449 struct drm_file *file)
451 struct drm_i915_gem_get_tiling *args = data;
452 struct drm_i915_private *dev_priv = dev->dev_private;
453 struct drm_i915_gem_object *obj;
455 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
456 if (&obj->base == NULL)
459 mutex_lock(&dev->struct_mutex);
461 args->tiling_mode = obj->tiling_mode;
462 switch (obj->tiling_mode) {
464 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
467 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
469 case I915_TILING_NONE:
470 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
473 DRM_ERROR("unknown tiling mode\n");
476 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
477 args->phys_swizzle_mode = args->swizzle_mode;
478 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
479 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
480 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
481 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
483 drm_gem_object_unreference(&obj->base);
484 mutex_unlock(&dev->struct_mutex);
490 * Swap every 64 bytes of this page around, to account for it having a new
491 * bit 17 of its physical address and therefore being interpreted differently
495 i915_gem_swizzle_page(struct page *page)
503 for (i = 0; i < PAGE_SIZE; i += 128) {
504 memcpy(temp, &vaddr[i], 64);
505 memcpy(&vaddr[i], &vaddr[i + 64], 64);
506 memcpy(&vaddr[i + 64], temp, 64);
513 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
515 struct sg_page_iter sg_iter;
518 if (obj->bit_17 == NULL)
522 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
523 struct page *page = sg_page_iter_page(&sg_iter);
524 char new_bit_17 = page_to_phys(page) >> 17;
525 if ((new_bit_17 & 0x1) !=
526 (test_bit(i, obj->bit_17) != 0)) {
527 i915_gem_swizzle_page(page);
528 set_page_dirty(page);
535 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
537 struct sg_page_iter sg_iter;
538 int page_count = obj->base.size >> PAGE_SHIFT;
541 if (obj->bit_17 == NULL) {
542 obj->bit_17 = kcalloc(BITS_TO_LONGS(page_count),
543 sizeof(long), GFP_KERNEL);
544 if (obj->bit_17 == NULL) {
545 DRM_ERROR("Failed to allocate memory for bit 17 "
552 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
553 if (page_to_phys(sg_page_iter_page(&sg_iter)) & (1 << 17))
554 __set_bit(i, obj->bit_17);
556 __clear_bit(i, obj->bit_17);