2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
37 struct list_head objects;
40 struct drm_i915_gem_object *lut[0];
41 struct hlist_head buckets[0];
45 static struct eb_objects *
46 eb_create(struct drm_i915_gem_execbuffer2 *args)
48 struct eb_objects *eb = NULL;
50 if (args->flags & I915_EXEC_HANDLE_LUT) {
51 int size = args->buffer_count;
52 size *= sizeof(struct drm_i915_gem_object *);
53 size += sizeof(struct eb_objects);
54 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
58 int size = args->buffer_count;
59 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
60 BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head)));
61 while (count > 2*size)
63 eb = kzalloc(count*sizeof(struct hlist_head) +
64 sizeof(struct eb_objects),
71 eb->and = -args->buffer_count;
73 INIT_LIST_HEAD(&eb->objects);
78 eb_reset(struct eb_objects *eb)
81 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
85 eb_lookup_objects(struct eb_objects *eb,
86 struct drm_i915_gem_exec_object2 *exec,
87 const struct drm_i915_gem_execbuffer2 *args,
88 struct drm_file *file)
92 spin_lock(&file->table_lock);
93 for (i = 0; i < args->buffer_count; i++) {
94 struct drm_i915_gem_object *obj;
96 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
98 spin_unlock(&file->table_lock);
99 DRM_DEBUG("Invalid object handle %d at index %d\n",
104 if (!list_empty(&obj->exec_list)) {
105 spin_unlock(&file->table_lock);
106 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
107 obj, exec[i].handle, i);
111 drm_gem_object_reference(&obj->base);
112 list_add_tail(&obj->exec_list, &eb->objects);
114 obj->exec_entry = &exec[i];
118 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
119 obj->exec_handle = handle;
120 hlist_add_head(&obj->exec_node,
121 &eb->buckets[handle & eb->and]);
124 spin_unlock(&file->table_lock);
129 static struct drm_i915_gem_object *
130 eb_get_object(struct eb_objects *eb, unsigned long handle)
133 if (handle >= -eb->and)
135 return eb->lut[handle];
137 struct hlist_head *head;
138 struct hlist_node *node;
140 head = &eb->buckets[handle & eb->and];
141 hlist_for_each(node, head) {
142 struct drm_i915_gem_object *obj;
144 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
145 if (obj->exec_handle == handle)
153 eb_destroy(struct eb_objects *eb)
155 while (!list_empty(&eb->objects)) {
156 struct drm_i915_gem_object *obj;
158 obj = list_first_entry(&eb->objects,
159 struct drm_i915_gem_object,
161 list_del_init(&obj->exec_list);
162 drm_gem_object_unreference(&obj->base);
167 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
169 return (obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
170 !obj->map_and_fenceable ||
171 obj->cache_level != I915_CACHE_NONE);
175 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
176 struct eb_objects *eb,
177 struct drm_i915_gem_relocation_entry *reloc)
179 struct drm_device *dev = obj->base.dev;
180 struct drm_gem_object *target_obj;
181 struct drm_i915_gem_object *target_i915_obj;
182 uint32_t target_offset;
185 /* we've already hold a reference to all valid objects */
186 target_obj = &eb_get_object(eb, reloc->target_handle)->base;
187 if (unlikely(target_obj == NULL))
190 target_i915_obj = to_intel_bo(target_obj);
191 target_offset = target_i915_obj->gtt_offset;
193 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
194 * pipe_control writes because the gpu doesn't properly redirect them
195 * through the ppgtt for non_secure batchbuffers. */
196 if (unlikely(IS_GEN6(dev) &&
197 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
198 !target_i915_obj->has_global_gtt_mapping)) {
199 i915_gem_gtt_bind_object(target_i915_obj,
200 target_i915_obj->cache_level);
203 /* Validate that the target is in a valid r/w GPU domain */
204 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
205 DRM_DEBUG("reloc with multiple write domains: "
206 "obj %p target %d offset %d "
207 "read %08x write %08x",
208 obj, reloc->target_handle,
211 reloc->write_domain);
214 if (unlikely((reloc->write_domain | reloc->read_domains)
215 & ~I915_GEM_GPU_DOMAINS)) {
216 DRM_DEBUG("reloc with read/write non-GPU domains: "
217 "obj %p target %d offset %d "
218 "read %08x write %08x",
219 obj, reloc->target_handle,
222 reloc->write_domain);
226 target_obj->pending_read_domains |= reloc->read_domains;
227 target_obj->pending_write_domain |= reloc->write_domain;
229 /* If the relocation already has the right value in it, no
230 * more work needs to be done.
232 if (target_offset == reloc->presumed_offset)
235 /* Check that the relocation address is valid... */
236 if (unlikely(reloc->offset > obj->base.size - 4)) {
237 DRM_DEBUG("Relocation beyond object bounds: "
238 "obj %p target %d offset %d size %d.\n",
239 obj, reloc->target_handle,
241 (int) obj->base.size);
244 if (unlikely(reloc->offset & 3)) {
245 DRM_DEBUG("Relocation not 4-byte aligned: "
246 "obj %p target %d offset %d.\n",
247 obj, reloc->target_handle,
248 (int) reloc->offset);
252 /* We can't wait for rendering with pagefaults disabled */
253 if (obj->active && in_atomic())
256 reloc->delta += target_offset;
257 if (use_cpu_reloc(obj)) {
258 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
261 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
265 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
266 reloc->offset >> PAGE_SHIFT));
267 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
268 kunmap_atomic(vaddr);
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 uint32_t __iomem *reloc_entry;
272 void __iomem *reloc_page;
274 ret = i915_gem_object_set_to_gtt_domain(obj, true);
278 ret = i915_gem_object_put_fence(obj);
282 /* Map the page containing the relocation we're going to perform. */
283 reloc->offset += obj->gtt_offset;
284 reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
285 reloc->offset & PAGE_MASK);
286 reloc_entry = (uint32_t __iomem *)
287 (reloc_page + (reloc->offset & ~PAGE_MASK));
288 iowrite32(reloc->delta, reloc_entry);
289 io_mapping_unmap_atomic(reloc_page);
292 /* and update the user's relocation entry */
293 reloc->presumed_offset = target_offset;
299 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
300 struct eb_objects *eb)
302 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
303 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
304 struct drm_i915_gem_relocation_entry __user *user_relocs;
305 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
308 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
310 remain = entry->relocation_count;
312 struct drm_i915_gem_relocation_entry *r = stack_reloc;
314 if (count > ARRAY_SIZE(stack_reloc))
315 count = ARRAY_SIZE(stack_reloc);
318 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
322 u64 offset = r->presumed_offset;
324 ret = i915_gem_execbuffer_relocate_entry(obj, eb, r);
328 if (r->presumed_offset != offset &&
329 __copy_to_user_inatomic(&user_relocs->presumed_offset,
331 sizeof(r->presumed_offset))) {
345 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
346 struct eb_objects *eb,
347 struct drm_i915_gem_relocation_entry *relocs)
349 const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
352 for (i = 0; i < entry->relocation_count; i++) {
353 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
362 i915_gem_execbuffer_relocate(struct drm_device *dev,
363 struct eb_objects *eb)
365 struct drm_i915_gem_object *obj;
368 /* This is the fast path and we cannot handle a pagefault whilst
369 * holding the struct mutex lest the user pass in the relocations
370 * contained within a mmaped bo. For in such a case we, the page
371 * fault handler would call i915_gem_fault() and we would try to
372 * acquire the struct mutex again. Obviously this is bad and so
373 * lockdep complains vehemently.
376 list_for_each_entry(obj, &eb->objects, exec_list) {
377 ret = i915_gem_execbuffer_relocate_object(obj, eb);
386 #define __EXEC_OBJECT_HAS_PIN (1<<31)
387 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
390 need_reloc_mappable(struct drm_i915_gem_object *obj)
392 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
393 return entry->relocation_count && !use_cpu_reloc(obj);
397 i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
398 struct intel_ring_buffer *ring,
401 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
402 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
403 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
404 bool need_fence, need_mappable;
408 has_fenced_gpu_access &&
409 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
410 obj->tiling_mode != I915_TILING_NONE;
411 need_mappable = need_fence || need_reloc_mappable(obj);
413 ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false);
417 entry->flags |= __EXEC_OBJECT_HAS_PIN;
419 if (has_fenced_gpu_access) {
420 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
421 ret = i915_gem_object_get_fence(obj);
425 if (i915_gem_object_pin_fence(obj))
426 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
428 obj->pending_fenced_gpu_access = true;
432 /* Ensure ppgtt mapping exists if needed */
433 if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
434 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
435 obj, obj->cache_level);
437 obj->has_aliasing_ppgtt_mapping = 1;
440 if (entry->offset != obj->gtt_offset) {
441 entry->offset = obj->gtt_offset;
445 if (entry->flags & EXEC_OBJECT_WRITE) {
446 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
447 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
450 if (entry->flags & EXEC_OBJECT_NEEDS_GTT &&
451 !obj->has_global_gtt_mapping)
452 i915_gem_gtt_bind_object(obj, obj->cache_level);
458 i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj)
460 struct drm_i915_gem_exec_object2 *entry;
465 entry = obj->exec_entry;
467 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
468 i915_gem_object_unpin_fence(obj);
470 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
471 i915_gem_object_unpin(obj);
473 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
477 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
478 struct drm_file *file,
479 struct list_head *objects,
482 struct drm_i915_gem_object *obj;
483 struct list_head ordered_objects;
484 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
487 INIT_LIST_HEAD(&ordered_objects);
488 while (!list_empty(objects)) {
489 struct drm_i915_gem_exec_object2 *entry;
490 bool need_fence, need_mappable;
492 obj = list_first_entry(objects,
493 struct drm_i915_gem_object,
495 entry = obj->exec_entry;
498 has_fenced_gpu_access &&
499 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
500 obj->tiling_mode != I915_TILING_NONE;
501 need_mappable = need_fence || need_reloc_mappable(obj);
504 list_move(&obj->exec_list, &ordered_objects);
506 list_move_tail(&obj->exec_list, &ordered_objects);
508 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
509 obj->base.pending_write_domain = 0;
510 obj->pending_fenced_gpu_access = false;
512 list_splice(&ordered_objects, objects);
514 /* Attempt to pin all of the buffers into the GTT.
515 * This is done in 3 phases:
517 * 1a. Unbind all objects that do not match the GTT constraints for
518 * the execbuffer (fenceable, mappable, alignment etc).
519 * 1b. Increment pin count for already bound objects.
520 * 2. Bind new objects.
521 * 3. Decrement pin count.
523 * This avoid unnecessary unbinding of later objects in order to make
524 * room for the earlier objects *unless* we need to defragment.
530 /* Unbind any ill-fitting objects or pin. */
531 list_for_each_entry(obj, objects, exec_list) {
532 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
533 bool need_fence, need_mappable;
539 has_fenced_gpu_access &&
540 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
541 obj->tiling_mode != I915_TILING_NONE;
542 need_mappable = need_fence || need_reloc_mappable(obj);
544 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
545 (need_mappable && !obj->map_and_fenceable))
546 ret = i915_gem_object_unbind(obj);
548 ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
553 /* Bind fresh objects */
554 list_for_each_entry(obj, objects, exec_list) {
558 ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
563 err: /* Decrement pin count for bound objects */
564 list_for_each_entry(obj, objects, exec_list)
565 i915_gem_execbuffer_unreserve_object(obj);
567 if (ret != -ENOSPC || retry++)
570 ret = i915_gem_evict_everything(ring->dev);
577 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
578 struct drm_i915_gem_execbuffer2 *args,
579 struct drm_file *file,
580 struct intel_ring_buffer *ring,
581 struct eb_objects *eb,
582 struct drm_i915_gem_exec_object2 *exec)
584 struct drm_i915_gem_relocation_entry *reloc;
585 struct drm_i915_gem_object *obj;
589 int count = args->buffer_count;
591 /* We may process another execbuffer during the unlock... */
592 while (!list_empty(&eb->objects)) {
593 obj = list_first_entry(&eb->objects,
594 struct drm_i915_gem_object,
596 list_del_init(&obj->exec_list);
597 drm_gem_object_unreference(&obj->base);
600 mutex_unlock(&dev->struct_mutex);
603 for (i = 0; i < count; i++)
604 total += exec[i].relocation_count;
606 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
607 reloc = drm_malloc_ab(total, sizeof(*reloc));
608 if (reloc == NULL || reloc_offset == NULL) {
609 drm_free_large(reloc);
610 drm_free_large(reloc_offset);
611 mutex_lock(&dev->struct_mutex);
616 for (i = 0; i < count; i++) {
617 struct drm_i915_gem_relocation_entry __user *user_relocs;
618 u64 invalid_offset = (u64)-1;
621 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
623 if (copy_from_user(reloc+total, user_relocs,
624 exec[i].relocation_count * sizeof(*reloc))) {
626 mutex_lock(&dev->struct_mutex);
630 /* As we do not update the known relocation offsets after
631 * relocating (due to the complexities in lock handling),
632 * we need to mark them as invalid now so that we force the
633 * relocation processing next time. Just in case the target
634 * object is evicted and then rebound into its old
635 * presumed_offset before the next execbuffer - if that
636 * happened we would make the mistake of assuming that the
637 * relocations were valid.
639 for (j = 0; j < exec[i].relocation_count; j++) {
640 if (copy_to_user(&user_relocs[j].presumed_offset,
642 sizeof(invalid_offset))) {
644 mutex_lock(&dev->struct_mutex);
649 reloc_offset[i] = total;
650 total += exec[i].relocation_count;
653 ret = i915_mutex_lock_interruptible(dev);
655 mutex_lock(&dev->struct_mutex);
659 /* reacquire the objects */
661 ret = eb_lookup_objects(eb, exec, args, file);
665 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
666 ret = i915_gem_execbuffer_reserve(ring, file, &eb->objects, &need_relocs);
670 list_for_each_entry(obj, &eb->objects, exec_list) {
671 int offset = obj->exec_entry - exec;
672 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
673 reloc + reloc_offset[offset]);
678 /* Leave the user relocations as are, this is the painfully slow path,
679 * and we want to avoid the complication of dropping the lock whilst
680 * having buffers reserved in the aperture and so causing spurious
681 * ENOSPC for random operations.
685 drm_free_large(reloc);
686 drm_free_large(reloc_offset);
691 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
692 struct list_head *objects)
694 struct drm_i915_gem_object *obj;
695 uint32_t flush_domains = 0;
698 list_for_each_entry(obj, objects, exec_list) {
699 ret = i915_gem_object_sync(obj, ring);
703 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
704 i915_gem_clflush_object(obj);
706 flush_domains |= obj->base.write_domain;
709 if (flush_domains & I915_GEM_DOMAIN_CPU)
710 i915_gem_chipset_flush(ring->dev);
712 if (flush_domains & I915_GEM_DOMAIN_GTT)
715 /* Unconditionally invalidate gpu caches and ensure that we do flush
716 * any residual writes from the previous batch.
718 return intel_ring_invalidate_all_caches(ring);
722 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
724 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
727 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
731 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
736 for (i = 0; i < count; i++) {
737 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
738 int length; /* limited by fault_in_pages_readable() */
740 if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS)
743 /* First check for malicious input causing overflow */
744 if (exec[i].relocation_count >
745 INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
748 length = exec[i].relocation_count *
749 sizeof(struct drm_i915_gem_relocation_entry);
750 /* we may also need to update the presumed offsets */
751 if (!access_ok(VERIFY_WRITE, ptr, length))
754 if (fault_in_multipages_readable(ptr, length))
762 i915_gem_execbuffer_move_to_active(struct list_head *objects,
763 struct intel_ring_buffer *ring)
765 struct drm_i915_gem_object *obj;
767 list_for_each_entry(obj, objects, exec_list) {
768 u32 old_read = obj->base.read_domains;
769 u32 old_write = obj->base.write_domain;
771 obj->base.write_domain = obj->base.pending_write_domain;
772 if (obj->base.write_domain == 0)
773 obj->base.pending_read_domains |= obj->base.read_domains;
774 obj->base.read_domains = obj->base.pending_read_domains;
775 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
777 i915_gem_object_move_to_active(obj, ring);
778 if (obj->base.write_domain) {
780 obj->last_write_seqno = intel_ring_get_seqno(ring);
781 if (obj->pin_count) /* check for potential scanout */
782 intel_mark_fb_busy(obj);
785 trace_i915_gem_object_change_domain(obj, old_read, old_write);
790 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
791 struct drm_file *file,
792 struct intel_ring_buffer *ring)
794 /* Unconditionally force add_request to emit a full flush. */
795 ring->gpu_caches_dirty = true;
797 /* Add a breadcrumb for the completion of the batch buffer */
798 (void)i915_add_request(ring, file, NULL);
802 i915_reset_gen7_sol_offsets(struct drm_device *dev,
803 struct intel_ring_buffer *ring)
805 drm_i915_private_t *dev_priv = dev->dev_private;
808 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
811 ret = intel_ring_begin(ring, 4 * 3);
815 for (i = 0; i < 4; i++) {
816 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
817 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
818 intel_ring_emit(ring, 0);
821 intel_ring_advance(ring);
827 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
828 struct drm_file *file,
829 struct drm_i915_gem_execbuffer2 *args,
830 struct drm_i915_gem_exec_object2 *exec)
832 drm_i915_private_t *dev_priv = dev->dev_private;
833 struct eb_objects *eb;
834 struct drm_i915_gem_object *batch_obj;
835 struct drm_clip_rect *cliprects = NULL;
836 struct intel_ring_buffer *ring;
837 u32 ctx_id = i915_execbuffer2_get_context_id(*args);
838 u32 exec_start, exec_len;
843 if (!i915_gem_check_execbuffer(args))
846 ret = validate_exec_list(exec, args->buffer_count);
851 if (args->flags & I915_EXEC_SECURE) {
852 if (!file->is_master || !capable(CAP_SYS_ADMIN))
855 flags |= I915_DISPATCH_SECURE;
857 if (args->flags & I915_EXEC_IS_PINNED)
858 flags |= I915_DISPATCH_PINNED;
860 switch (args->flags & I915_EXEC_RING_MASK) {
861 case I915_EXEC_DEFAULT:
862 case I915_EXEC_RENDER:
863 ring = &dev_priv->ring[RCS];
866 ring = &dev_priv->ring[VCS];
868 DRM_DEBUG("Ring %s doesn't support contexts\n",
874 ring = &dev_priv->ring[BCS];
876 DRM_DEBUG("Ring %s doesn't support contexts\n",
882 DRM_DEBUG("execbuf with unknown ring: %d\n",
883 (int)(args->flags & I915_EXEC_RING_MASK));
886 if (!intel_ring_initialized(ring)) {
887 DRM_DEBUG("execbuf with invalid ring: %d\n",
888 (int)(args->flags & I915_EXEC_RING_MASK));
892 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
893 mask = I915_EXEC_CONSTANTS_MASK;
895 case I915_EXEC_CONSTANTS_REL_GENERAL:
896 case I915_EXEC_CONSTANTS_ABSOLUTE:
897 case I915_EXEC_CONSTANTS_REL_SURFACE:
898 if (ring == &dev_priv->ring[RCS] &&
899 mode != dev_priv->relative_constants_mode) {
900 if (INTEL_INFO(dev)->gen < 4)
903 if (INTEL_INFO(dev)->gen > 5 &&
904 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
907 /* The HW changed the meaning on this bit on gen6 */
908 if (INTEL_INFO(dev)->gen >= 6)
909 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
913 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
917 if (args->buffer_count < 1) {
918 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
922 if (args->num_cliprects != 0) {
923 if (ring != &dev_priv->ring[RCS]) {
924 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
928 if (INTEL_INFO(dev)->gen >= 5) {
929 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
933 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
934 DRM_DEBUG("execbuf with %u cliprects\n",
935 args->num_cliprects);
939 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
941 if (cliprects == NULL) {
946 if (copy_from_user(cliprects,
947 (struct drm_clip_rect __user *)(uintptr_t)
949 sizeof(*cliprects)*args->num_cliprects)) {
955 ret = i915_mutex_lock_interruptible(dev);
959 if (dev_priv->mm.suspended) {
960 mutex_unlock(&dev->struct_mutex);
965 eb = eb_create(args);
967 mutex_unlock(&dev->struct_mutex);
972 /* Look up object handles */
973 ret = eb_lookup_objects(eb, exec, args, file);
977 /* take note of the batch buffer before we might reorder the lists */
978 batch_obj = list_entry(eb->objects.prev,
979 struct drm_i915_gem_object,
982 /* Move the objects en-masse into the GTT, evicting if necessary. */
983 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
984 ret = i915_gem_execbuffer_reserve(ring, file, &eb->objects, &need_relocs);
988 /* The objects are in their final locations, apply the relocations. */
990 ret = i915_gem_execbuffer_relocate(dev, eb);
992 if (ret == -EFAULT) {
993 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
995 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1001 /* Set the pending read domains for the batch buffer to COMMAND */
1002 if (batch_obj->base.pending_write_domain) {
1003 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1007 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1009 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1010 * batch" bit. Hence we need to pin secure batches into the global gtt.
1011 * hsw should have this fixed, but let's be paranoid and do it
1012 * unconditionally for now. */
1013 if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
1014 i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
1016 ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->objects);
1020 ret = i915_switch_context(ring, file, ctx_id);
1024 if (ring == &dev_priv->ring[RCS] &&
1025 mode != dev_priv->relative_constants_mode) {
1026 ret = intel_ring_begin(ring, 4);
1030 intel_ring_emit(ring, MI_NOOP);
1031 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1032 intel_ring_emit(ring, INSTPM);
1033 intel_ring_emit(ring, mask << 16 | mode);
1034 intel_ring_advance(ring);
1036 dev_priv->relative_constants_mode = mode;
1039 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1040 ret = i915_reset_gen7_sol_offsets(dev, ring);
1045 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1046 exec_len = args->batch_len;
1048 for (i = 0; i < args->num_cliprects; i++) {
1049 ret = i915_emit_box(dev, &cliprects[i],
1050 args->DR1, args->DR4);
1054 ret = ring->dispatch_execbuffer(ring,
1055 exec_start, exec_len,
1061 ret = ring->dispatch_execbuffer(ring,
1062 exec_start, exec_len,
1068 trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
1070 i915_gem_execbuffer_move_to_active(&eb->objects, ring);
1071 i915_gem_execbuffer_retire_commands(dev, file, ring);
1076 mutex_unlock(&dev->struct_mutex);
1084 * Legacy execbuffer just creates an exec2 list from the original exec object
1085 * list array and passes it to the real function.
1088 i915_gem_execbuffer(struct drm_device *dev, void *data,
1089 struct drm_file *file)
1091 struct drm_i915_gem_execbuffer *args = data;
1092 struct drm_i915_gem_execbuffer2 exec2;
1093 struct drm_i915_gem_exec_object *exec_list = NULL;
1094 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1097 if (args->buffer_count < 1) {
1098 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1102 /* Copy in the exec list from userland */
1103 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1104 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1105 if (exec_list == NULL || exec2_list == NULL) {
1106 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1107 args->buffer_count);
1108 drm_free_large(exec_list);
1109 drm_free_large(exec2_list);
1112 ret = copy_from_user(exec_list,
1113 (void __user *)(uintptr_t)args->buffers_ptr,
1114 sizeof(*exec_list) * args->buffer_count);
1116 DRM_DEBUG("copy %d exec entries failed %d\n",
1117 args->buffer_count, ret);
1118 drm_free_large(exec_list);
1119 drm_free_large(exec2_list);
1123 for (i = 0; i < args->buffer_count; i++) {
1124 exec2_list[i].handle = exec_list[i].handle;
1125 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1126 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1127 exec2_list[i].alignment = exec_list[i].alignment;
1128 exec2_list[i].offset = exec_list[i].offset;
1129 if (INTEL_INFO(dev)->gen < 4)
1130 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1132 exec2_list[i].flags = 0;
1135 exec2.buffers_ptr = args->buffers_ptr;
1136 exec2.buffer_count = args->buffer_count;
1137 exec2.batch_start_offset = args->batch_start_offset;
1138 exec2.batch_len = args->batch_len;
1139 exec2.DR1 = args->DR1;
1140 exec2.DR4 = args->DR4;
1141 exec2.num_cliprects = args->num_cliprects;
1142 exec2.cliprects_ptr = args->cliprects_ptr;
1143 exec2.flags = I915_EXEC_RENDER;
1144 i915_execbuffer2_set_context_id(exec2, 0);
1146 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1148 /* Copy the new buffer offsets back to the user's exec list. */
1149 for (i = 0; i < args->buffer_count; i++)
1150 exec_list[i].offset = exec2_list[i].offset;
1151 /* ... and back out to userspace */
1152 ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr,
1154 sizeof(*exec_list) * args->buffer_count);
1157 DRM_DEBUG("failed to copy %d exec entries "
1158 "back to user (%d)\n",
1159 args->buffer_count, ret);
1163 drm_free_large(exec_list);
1164 drm_free_large(exec2_list);
1169 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1170 struct drm_file *file)
1172 struct drm_i915_gem_execbuffer2 *args = data;
1173 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1176 if (args->buffer_count < 1 ||
1177 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1178 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1182 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1183 GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
1184 if (exec2_list == NULL)
1185 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1186 args->buffer_count);
1187 if (exec2_list == NULL) {
1188 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1189 args->buffer_count);
1192 ret = copy_from_user(exec2_list,
1193 (struct drm_i915_relocation_entry __user *)
1194 (uintptr_t) args->buffers_ptr,
1195 sizeof(*exec2_list) * args->buffer_count);
1197 DRM_DEBUG("copy %d exec entries failed %d\n",
1198 args->buffer_count, ret);
1199 drm_free_large(exec2_list);
1203 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1205 /* Copy the new buffer offsets back to the user's exec list. */
1206 ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr,
1208 sizeof(*exec2_list) * args->buffer_count);
1211 DRM_DEBUG("failed to copy %d exec entries "
1212 "back to user (%d)\n",
1213 args->buffer_count, ret);
1217 drm_free_large(exec2_list);