2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
43 static __must_check int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
46 static __must_check int
47 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
48 struct i915_address_space *vm,
50 bool map_and_fenceable,
52 static int i915_gem_phys_pwrite(struct drm_device *dev,
53 struct drm_i915_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file);
57 static void i915_gem_write_fence(struct drm_device *dev, int reg,
58 struct drm_i915_gem_object *obj);
59 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
60 struct drm_i915_fence_reg *fence,
63 static unsigned long i915_gem_inactive_count(struct shrinker *shrinker,
64 struct shrink_control *sc);
65 static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker,
66 struct shrink_control *sc);
67 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
68 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
69 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
71 static bool cpu_cache_is_coherent(struct drm_device *dev,
72 enum i915_cache_level level)
74 return HAS_LLC(dev) || level != I915_CACHE_NONE;
77 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
79 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
82 return obj->pin_display;
85 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
88 i915_gem_release_mmap(obj);
90 /* As we do not have an associated fence register, we will force
91 * a tiling change if we ever need to acquire one.
93 obj->fence_dirty = false;
94 obj->fence_reg = I915_FENCE_REG_NONE;
97 /* some bookkeeping */
98 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
101 spin_lock(&dev_priv->mm.object_stat_lock);
102 dev_priv->mm.object_count++;
103 dev_priv->mm.object_memory += size;
104 spin_unlock(&dev_priv->mm.object_stat_lock);
107 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
110 spin_lock(&dev_priv->mm.object_stat_lock);
111 dev_priv->mm.object_count--;
112 dev_priv->mm.object_memory -= size;
113 spin_unlock(&dev_priv->mm.object_stat_lock);
117 i915_gem_wait_for_error(struct i915_gpu_error *error)
121 #define EXIT_COND (!i915_reset_in_progress(error) || \
122 i915_terminally_wedged(error))
127 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
128 * userspace. If it takes that long something really bad is going on and
129 * we should simply try to bail out and fail as gracefully as possible.
131 ret = wait_event_interruptible_timeout(error->reset_queue,
135 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
137 } else if (ret < 0) {
145 int i915_mutex_lock_interruptible(struct drm_device *dev)
147 struct drm_i915_private *dev_priv = dev->dev_private;
150 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
154 ret = mutex_lock_interruptible(&dev->struct_mutex);
158 WARN_ON(i915_verify_lists(dev));
163 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
165 return i915_gem_obj_bound_any(obj) && !obj->active;
169 i915_gem_init_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_init *args = data;
175 if (drm_core_check_feature(dev, DRIVER_MODESET))
178 if (args->gtt_start >= args->gtt_end ||
179 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
182 /* GEM with user mode setting was never supported on ilk and later. */
183 if (INTEL_INFO(dev)->gen >= 5)
186 mutex_lock(&dev->struct_mutex);
187 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
189 dev_priv->gtt.mappable_end = args->gtt_end;
190 mutex_unlock(&dev->struct_mutex);
196 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
197 struct drm_file *file)
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_i915_gem_get_aperture *args = data;
201 struct drm_i915_gem_object *obj;
205 mutex_lock(&dev->struct_mutex);
206 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
207 if (i915_gem_obj_is_pinned(obj))
208 pinned += i915_gem_obj_ggtt_size(obj);
209 mutex_unlock(&dev->struct_mutex);
211 args->aper_size = dev_priv->gtt.base.total;
212 args->aper_available_size = args->aper_size - pinned;
217 void *i915_gem_object_alloc(struct drm_device *dev)
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
223 void i915_gem_object_free(struct drm_i915_gem_object *obj)
225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
226 kmem_cache_free(dev_priv->slab, obj);
230 i915_gem_create(struct drm_file *file,
231 struct drm_device *dev,
235 struct drm_i915_gem_object *obj;
239 size = roundup(size, PAGE_SIZE);
243 /* Allocate the new object */
244 obj = i915_gem_alloc_object(dev, size);
248 ret = drm_gem_handle_create(file, &obj->base, &handle);
249 /* drop reference from allocate - handle holds it now */
250 drm_gem_object_unreference_unlocked(&obj->base);
259 i915_gem_dumb_create(struct drm_file *file,
260 struct drm_device *dev,
261 struct drm_mode_create_dumb *args)
263 /* have to work out size/pitch and return them */
264 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
265 args->size = args->pitch * args->height;
266 return i915_gem_create(file, dev,
267 args->size, &args->handle);
271 * Creates a new mm object and returns a handle to it.
274 i915_gem_create_ioctl(struct drm_device *dev, void *data,
275 struct drm_file *file)
277 struct drm_i915_gem_create *args = data;
279 return i915_gem_create(file, dev,
280 args->size, &args->handle);
284 __copy_to_user_swizzled(char __user *cpu_vaddr,
285 const char *gpu_vaddr, int gpu_offset,
288 int ret, cpu_offset = 0;
291 int cacheline_end = ALIGN(gpu_offset + 1, 64);
292 int this_length = min(cacheline_end - gpu_offset, length);
293 int swizzled_gpu_offset = gpu_offset ^ 64;
295 ret = __copy_to_user(cpu_vaddr + cpu_offset,
296 gpu_vaddr + swizzled_gpu_offset,
301 cpu_offset += this_length;
302 gpu_offset += this_length;
303 length -= this_length;
310 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
311 const char __user *cpu_vaddr,
314 int ret, cpu_offset = 0;
317 int cacheline_end = ALIGN(gpu_offset + 1, 64);
318 int this_length = min(cacheline_end - gpu_offset, length);
319 int swizzled_gpu_offset = gpu_offset ^ 64;
321 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
322 cpu_vaddr + cpu_offset,
327 cpu_offset += this_length;
328 gpu_offset += this_length;
329 length -= this_length;
335 /* Per-page copy function for the shmem pread fastpath.
336 * Flushes invalid cachelines before reading the target if
337 * needs_clflush is set. */
339 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
340 char __user *user_data,
341 bool page_do_bit17_swizzling, bool needs_clflush)
346 if (unlikely(page_do_bit17_swizzling))
349 vaddr = kmap_atomic(page);
351 drm_clflush_virt_range(vaddr + shmem_page_offset,
353 ret = __copy_to_user_inatomic(user_data,
354 vaddr + shmem_page_offset,
356 kunmap_atomic(vaddr);
358 return ret ? -EFAULT : 0;
362 shmem_clflush_swizzled_range(char *addr, unsigned long length,
365 if (unlikely(swizzled)) {
366 unsigned long start = (unsigned long) addr;
367 unsigned long end = (unsigned long) addr + length;
369 /* For swizzling simply ensure that we always flush both
370 * channels. Lame, but simple and it works. Swizzled
371 * pwrite/pread is far from a hotpath - current userspace
372 * doesn't use it at all. */
373 start = round_down(start, 128);
374 end = round_up(end, 128);
376 drm_clflush_virt_range((void *)start, end - start);
378 drm_clflush_virt_range(addr, length);
383 /* Only difference to the fast-path function is that this can handle bit17
384 * and uses non-atomic copy and kmap functions. */
386 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
387 char __user *user_data,
388 bool page_do_bit17_swizzling, bool needs_clflush)
395 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
397 page_do_bit17_swizzling);
399 if (page_do_bit17_swizzling)
400 ret = __copy_to_user_swizzled(user_data,
401 vaddr, shmem_page_offset,
404 ret = __copy_to_user(user_data,
405 vaddr + shmem_page_offset,
409 return ret ? - EFAULT : 0;
413 i915_gem_shmem_pread(struct drm_device *dev,
414 struct drm_i915_gem_object *obj,
415 struct drm_i915_gem_pread *args,
416 struct drm_file *file)
418 char __user *user_data;
421 int shmem_page_offset, page_length, ret = 0;
422 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
424 int needs_clflush = 0;
425 struct sg_page_iter sg_iter;
427 user_data = to_user_ptr(args->data_ptr);
430 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
432 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
433 /* If we're not in the cpu read domain, set ourself into the gtt
434 * read domain and manually flush cachelines (if required). This
435 * optimizes for the case when the gpu will dirty the data
436 * anyway again before the next pread happens. */
437 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
438 ret = i915_gem_object_wait_rendering(obj, true);
443 ret = i915_gem_object_get_pages(obj);
447 i915_gem_object_pin_pages(obj);
449 offset = args->offset;
451 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
452 offset >> PAGE_SHIFT) {
453 struct page *page = sg_page_iter_page(&sg_iter);
458 /* Operation in this page
460 * shmem_page_offset = offset within page in shmem file
461 * page_length = bytes to copy for this page
463 shmem_page_offset = offset_in_page(offset);
464 page_length = remain;
465 if ((shmem_page_offset + page_length) > PAGE_SIZE)
466 page_length = PAGE_SIZE - shmem_page_offset;
468 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
469 (page_to_phys(page) & (1 << 17)) != 0;
471 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
472 user_data, page_do_bit17_swizzling,
477 mutex_unlock(&dev->struct_mutex);
479 if (likely(!i915.prefault_disable) && !prefaulted) {
480 ret = fault_in_multipages_writeable(user_data, remain);
481 /* Userspace is tricking us, but we've already clobbered
482 * its pages with the prefault and promised to write the
483 * data up to the first fault. Hence ignore any errors
484 * and just continue. */
489 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
490 user_data, page_do_bit17_swizzling,
493 mutex_lock(&dev->struct_mutex);
496 mark_page_accessed(page);
501 remain -= page_length;
502 user_data += page_length;
503 offset += page_length;
507 i915_gem_object_unpin_pages(obj);
513 * Reads data from the object referenced by handle.
515 * On error, the contents of *data are undefined.
518 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
519 struct drm_file *file)
521 struct drm_i915_gem_pread *args = data;
522 struct drm_i915_gem_object *obj;
528 if (!access_ok(VERIFY_WRITE,
529 to_user_ptr(args->data_ptr),
533 ret = i915_mutex_lock_interruptible(dev);
537 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
538 if (&obj->base == NULL) {
543 /* Bounds check source. */
544 if (args->offset > obj->base.size ||
545 args->size > obj->base.size - args->offset) {
550 /* prime objects have no backing filp to GEM pread/pwrite
553 if (!obj->base.filp) {
558 trace_i915_gem_object_pread(obj, args->offset, args->size);
560 ret = i915_gem_shmem_pread(dev, obj, args, file);
563 drm_gem_object_unreference(&obj->base);
565 mutex_unlock(&dev->struct_mutex);
569 /* This is the fast write path which cannot handle
570 * page faults in the source data
574 fast_user_write(struct io_mapping *mapping,
575 loff_t page_base, int page_offset,
576 char __user *user_data,
579 void __iomem *vaddr_atomic;
581 unsigned long unwritten;
583 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
584 /* We can use the cpu mem copy function because this is X86. */
585 vaddr = (void __force*)vaddr_atomic + page_offset;
586 unwritten = __copy_from_user_inatomic_nocache(vaddr,
588 io_mapping_unmap_atomic(vaddr_atomic);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
598 struct drm_i915_gem_object *obj,
599 struct drm_i915_gem_pwrite *args,
600 struct drm_file *file)
602 drm_i915_private_t *dev_priv = dev->dev_private;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length, ret;
608 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
612 ret = i915_gem_object_set_to_gtt_domain(obj, true);
616 ret = i915_gem_object_put_fence(obj);
620 user_data = to_user_ptr(args->data_ptr);
623 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
626 /* Operation in this page
628 * page_base = page offset within aperture
629 * page_offset = offset within page
630 * page_length = bytes to copy for this page
632 page_base = offset & PAGE_MASK;
633 page_offset = offset_in_page(offset);
634 page_length = remain;
635 if ((page_offset + remain) > PAGE_SIZE)
636 page_length = PAGE_SIZE - page_offset;
638 /* If we get a fault while copying data, then (presumably) our
639 * source page isn't available. Return the error and we'll
640 * retry in the slow path.
642 if (fast_user_write(dev_priv->gtt.mappable, page_base,
643 page_offset, user_data, page_length)) {
648 remain -= page_length;
649 user_data += page_length;
650 offset += page_length;
654 i915_gem_object_ggtt_unpin(obj);
659 /* Per-page copy function for the shmem pwrite fastpath.
660 * Flushes invalid cachelines before writing to the target if
661 * needs_clflush_before is set and flushes out any written cachelines after
662 * writing if needs_clflush is set. */
664 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
665 char __user *user_data,
666 bool page_do_bit17_swizzling,
667 bool needs_clflush_before,
668 bool needs_clflush_after)
673 if (unlikely(page_do_bit17_swizzling))
676 vaddr = kmap_atomic(page);
677 if (needs_clflush_before)
678 drm_clflush_virt_range(vaddr + shmem_page_offset,
680 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
683 if (needs_clflush_after)
684 drm_clflush_virt_range(vaddr + shmem_page_offset,
686 kunmap_atomic(vaddr);
688 return ret ? -EFAULT : 0;
691 /* Only difference to the fast-path function is that this can handle bit17
692 * and uses non-atomic copy and kmap functions. */
694 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
695 char __user *user_data,
696 bool page_do_bit17_swizzling,
697 bool needs_clflush_before,
698 bool needs_clflush_after)
704 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
705 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
707 page_do_bit17_swizzling);
708 if (page_do_bit17_swizzling)
709 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
713 ret = __copy_from_user(vaddr + shmem_page_offset,
716 if (needs_clflush_after)
717 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
719 page_do_bit17_swizzling);
722 return ret ? -EFAULT : 0;
726 i915_gem_shmem_pwrite(struct drm_device *dev,
727 struct drm_i915_gem_object *obj,
728 struct drm_i915_gem_pwrite *args,
729 struct drm_file *file)
733 char __user *user_data;
734 int shmem_page_offset, page_length, ret = 0;
735 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
736 int hit_slowpath = 0;
737 int needs_clflush_after = 0;
738 int needs_clflush_before = 0;
739 struct sg_page_iter sg_iter;
741 user_data = to_user_ptr(args->data_ptr);
744 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
746 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
747 /* If we're not in the cpu write domain, set ourself into the gtt
748 * write domain and manually flush cachelines (if required). This
749 * optimizes for the case when the gpu will use the data
750 * right away and we therefore have to clflush anyway. */
751 needs_clflush_after = cpu_write_needs_clflush(obj);
752 ret = i915_gem_object_wait_rendering(obj, false);
756 /* Same trick applies to invalidate partially written cachelines read
758 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
759 needs_clflush_before =
760 !cpu_cache_is_coherent(dev, obj->cache_level);
762 ret = i915_gem_object_get_pages(obj);
766 i915_gem_object_pin_pages(obj);
768 offset = args->offset;
771 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
772 offset >> PAGE_SHIFT) {
773 struct page *page = sg_page_iter_page(&sg_iter);
774 int partial_cacheline_write;
779 /* Operation in this page
781 * shmem_page_offset = offset within page in shmem file
782 * page_length = bytes to copy for this page
784 shmem_page_offset = offset_in_page(offset);
786 page_length = remain;
787 if ((shmem_page_offset + page_length) > PAGE_SIZE)
788 page_length = PAGE_SIZE - shmem_page_offset;
790 /* If we don't overwrite a cacheline completely we need to be
791 * careful to have up-to-date data by first clflushing. Don't
792 * overcomplicate things and flush the entire patch. */
793 partial_cacheline_write = needs_clflush_before &&
794 ((shmem_page_offset | page_length)
795 & (boot_cpu_data.x86_clflush_size - 1));
797 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
798 (page_to_phys(page) & (1 << 17)) != 0;
800 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
801 user_data, page_do_bit17_swizzling,
802 partial_cacheline_write,
803 needs_clflush_after);
808 mutex_unlock(&dev->struct_mutex);
809 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
810 user_data, page_do_bit17_swizzling,
811 partial_cacheline_write,
812 needs_clflush_after);
814 mutex_lock(&dev->struct_mutex);
817 set_page_dirty(page);
818 mark_page_accessed(page);
823 remain -= page_length;
824 user_data += page_length;
825 offset += page_length;
829 i915_gem_object_unpin_pages(obj);
833 * Fixup: Flush cpu caches in case we didn't flush the dirty
834 * cachelines in-line while writing and the object moved
835 * out of the cpu write domain while we've dropped the lock.
837 if (!needs_clflush_after &&
838 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
839 if (i915_gem_clflush_object(obj, obj->pin_display))
840 i915_gem_chipset_flush(dev);
844 if (needs_clflush_after)
845 i915_gem_chipset_flush(dev);
851 * Writes data to the object referenced by handle.
853 * On error, the contents of the buffer that were to be modified are undefined.
856 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
857 struct drm_file *file)
859 struct drm_i915_gem_pwrite *args = data;
860 struct drm_i915_gem_object *obj;
866 if (!access_ok(VERIFY_READ,
867 to_user_ptr(args->data_ptr),
871 if (likely(!i915.prefault_disable)) {
872 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
878 ret = i915_mutex_lock_interruptible(dev);
882 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
883 if (&obj->base == NULL) {
888 /* Bounds check destination. */
889 if (args->offset > obj->base.size ||
890 args->size > obj->base.size - args->offset) {
895 /* prime objects have no backing filp to GEM pread/pwrite
898 if (!obj->base.filp) {
903 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
906 /* We can only do the GTT pwrite on untiled buffers, as otherwise
907 * it would end up going through the fenced access, and we'll get
908 * different detiling behavior between reading and writing.
909 * pread/pwrite currently are reading and writing from the CPU
910 * perspective, requiring manual detiling by the client.
913 ret = i915_gem_phys_pwrite(dev, obj, args, file);
917 if (obj->tiling_mode == I915_TILING_NONE &&
918 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
919 cpu_write_needs_clflush(obj)) {
920 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
921 /* Note that the gtt paths might fail with non-page-backed user
922 * pointers (e.g. gtt mappings when moving data between
923 * textures). Fallback to the shmem path in that case. */
926 if (ret == -EFAULT || ret == -ENOSPC)
927 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
930 drm_gem_object_unreference(&obj->base);
932 mutex_unlock(&dev->struct_mutex);
937 i915_gem_check_wedge(struct i915_gpu_error *error,
940 if (i915_reset_in_progress(error)) {
941 /* Non-interruptible callers can't handle -EAGAIN, hence return
942 * -EIO unconditionally for these. */
946 /* Recovery complete, but the reset failed ... */
947 if (i915_terminally_wedged(error))
957 * Compare seqno against outstanding lazy request. Emit a request if they are
961 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
965 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
968 if (seqno == ring->outstanding_lazy_seqno)
969 ret = i915_add_request(ring, NULL);
974 static void fake_irq(unsigned long data)
976 wake_up_process((struct task_struct *)data);
979 static bool missed_irq(struct drm_i915_private *dev_priv,
980 struct intel_ring_buffer *ring)
982 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
985 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
987 if (file_priv == NULL)
990 return !atomic_xchg(&file_priv->rps_wait_boost, true);
994 * __wait_seqno - wait until execution of seqno has finished
995 * @ring: the ring expected to report seqno
997 * @reset_counter: reset sequence associated with the given seqno
998 * @interruptible: do an interruptible wait (normally yes)
999 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1001 * Note: It is of utmost importance that the passed in seqno and reset_counter
1002 * values have been read by the caller in an smp safe manner. Where read-side
1003 * locks are involved, it is sufficient to read the reset_counter before
1004 * unlocking the lock that protects the seqno. For lockless tricks, the
1005 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1008 * Returns 0 if the seqno was found within the alloted time. Else returns the
1009 * errno with remaining time filled in timeout argument.
1011 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1012 unsigned reset_counter,
1014 struct timespec *timeout,
1015 struct drm_i915_file_private *file_priv)
1017 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1018 const bool irq_test_in_progress =
1019 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1020 struct timespec before, now;
1022 unsigned long timeout_expire;
1025 WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
1027 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1030 timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
1032 if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) {
1033 gen6_rps_boost(dev_priv);
1035 mod_delayed_work(dev_priv->wq,
1036 &file_priv->mm.idle_work,
1037 msecs_to_jiffies(100));
1040 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1043 /* Record current time in case interrupted by signal, or wedged */
1044 trace_i915_gem_request_wait_begin(ring, seqno);
1045 getrawmonotonic(&before);
1047 struct timer_list timer;
1049 prepare_to_wait(&ring->irq_queue, &wait,
1050 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1052 /* We need to check whether any gpu reset happened in between
1053 * the caller grabbing the seqno and now ... */
1054 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1055 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1056 * is truely gone. */
1057 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1063 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1068 if (interruptible && signal_pending(current)) {
1073 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1078 timer.function = NULL;
1079 if (timeout || missed_irq(dev_priv, ring)) {
1080 unsigned long expire;
1082 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1083 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1084 mod_timer(&timer, expire);
1089 if (timer.function) {
1090 del_singleshot_timer_sync(&timer);
1091 destroy_timer_on_stack(&timer);
1094 getrawmonotonic(&now);
1095 trace_i915_gem_request_wait_end(ring, seqno);
1097 if (!irq_test_in_progress)
1098 ring->irq_put(ring);
1100 finish_wait(&ring->irq_queue, &wait);
1103 struct timespec sleep_time = timespec_sub(now, before);
1104 *timeout = timespec_sub(*timeout, sleep_time);
1105 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1106 set_normalized_timespec(timeout, 0, 0);
1113 * Waits for a sequence number to be signaled, and cleans up the
1114 * request and object lists appropriately for that event.
1117 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1119 struct drm_device *dev = ring->dev;
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121 bool interruptible = dev_priv->mm.interruptible;
1124 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1127 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1131 ret = i915_gem_check_olr(ring, seqno);
1135 return __wait_seqno(ring, seqno,
1136 atomic_read(&dev_priv->gpu_error.reset_counter),
1137 interruptible, NULL, NULL);
1141 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1142 struct intel_ring_buffer *ring)
1144 i915_gem_retire_requests_ring(ring);
1146 /* Manually manage the write flush as we may have not yet
1147 * retired the buffer.
1149 * Note that the last_write_seqno is always the earlier of
1150 * the two (read/write) seqno, so if we haved successfully waited,
1151 * we know we have passed the last write.
1153 obj->last_write_seqno = 0;
1154 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1160 * Ensures that all rendering to the object has completed and the object is
1161 * safe to unbind from the GTT or access from the CPU.
1163 static __must_check int
1164 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1167 struct intel_ring_buffer *ring = obj->ring;
1171 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1175 ret = i915_wait_seqno(ring, seqno);
1179 return i915_gem_object_wait_rendering__tail(obj, ring);
1182 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1183 * as the object state may change during this call.
1185 static __must_check int
1186 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1187 struct drm_file *file,
1190 struct drm_device *dev = obj->base.dev;
1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 struct intel_ring_buffer *ring = obj->ring;
1193 unsigned reset_counter;
1197 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1198 BUG_ON(!dev_priv->mm.interruptible);
1200 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1204 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1208 ret = i915_gem_check_olr(ring, seqno);
1212 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1213 mutex_unlock(&dev->struct_mutex);
1214 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file->driver_priv);
1215 mutex_lock(&dev->struct_mutex);
1219 return i915_gem_object_wait_rendering__tail(obj, ring);
1223 * Called when user space prepares to use an object with the CPU, either
1224 * through the mmap ioctl's mapping or a GTT mapping.
1227 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1228 struct drm_file *file)
1230 struct drm_i915_gem_set_domain *args = data;
1231 struct drm_i915_gem_object *obj;
1232 uint32_t read_domains = args->read_domains;
1233 uint32_t write_domain = args->write_domain;
1236 /* Only handle setting domains to types used by the CPU. */
1237 if (write_domain & I915_GEM_GPU_DOMAINS)
1240 if (read_domains & I915_GEM_GPU_DOMAINS)
1243 /* Having something in the write domain implies it's in the read
1244 * domain, and only that read domain. Enforce that in the request.
1246 if (write_domain != 0 && read_domains != write_domain)
1249 ret = i915_mutex_lock_interruptible(dev);
1253 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1254 if (&obj->base == NULL) {
1259 /* Try to flush the object off the GPU without holding the lock.
1260 * We will repeat the flush holding the lock in the normal manner
1261 * to catch cases where we are gazumped.
1263 ret = i915_gem_object_wait_rendering__nonblocking(obj, file, !write_domain);
1267 if (read_domains & I915_GEM_DOMAIN_GTT) {
1268 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1270 /* Silently promote "you're not bound, there was nothing to do"
1271 * to success, since the client was just asking us to
1272 * make sure everything was done.
1277 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1281 drm_gem_object_unreference(&obj->base);
1283 mutex_unlock(&dev->struct_mutex);
1288 * Called when user space has done writes to this buffer
1291 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1292 struct drm_file *file)
1294 struct drm_i915_gem_sw_finish *args = data;
1295 struct drm_i915_gem_object *obj;
1298 ret = i915_mutex_lock_interruptible(dev);
1302 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1303 if (&obj->base == NULL) {
1308 /* Pinned buffers may be scanout, so flush the cache */
1309 if (obj->pin_display)
1310 i915_gem_object_flush_cpu_write_domain(obj, true);
1312 drm_gem_object_unreference(&obj->base);
1314 mutex_unlock(&dev->struct_mutex);
1319 * Maps the contents of an object, returning the address it is mapped
1322 * While the mapping holds a reference on the contents of the object, it doesn't
1323 * imply a ref on the object itself.
1326 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1327 struct drm_file *file)
1329 struct drm_i915_gem_mmap *args = data;
1330 struct drm_gem_object *obj;
1333 obj = drm_gem_object_lookup(dev, file, args->handle);
1337 /* prime objects have no backing filp to GEM mmap
1341 drm_gem_object_unreference_unlocked(obj);
1345 addr = vm_mmap(obj->filp, 0, args->size,
1346 PROT_READ | PROT_WRITE, MAP_SHARED,
1348 drm_gem_object_unreference_unlocked(obj);
1349 if (IS_ERR((void *)addr))
1352 args->addr_ptr = (uint64_t) addr;
1358 * i915_gem_fault - fault a page into the GTT
1359 * vma: VMA in question
1362 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1363 * from userspace. The fault handler takes care of binding the object to
1364 * the GTT (if needed), allocating and programming a fence register (again,
1365 * only if needed based on whether the old reg is still valid or the object
1366 * is tiled) and inserting a new PTE into the faulting process.
1368 * Note that the faulting process may involve evicting existing objects
1369 * from the GTT and/or fence registers to make room. So performance may
1370 * suffer if the GTT working set is large or there are few fence registers
1373 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1375 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1376 struct drm_device *dev = obj->base.dev;
1377 drm_i915_private_t *dev_priv = dev->dev_private;
1378 pgoff_t page_offset;
1381 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1383 intel_runtime_pm_get(dev_priv);
1385 /* We don't use vmf->pgoff since that has the fake offset */
1386 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1389 ret = i915_mutex_lock_interruptible(dev);
1393 trace_i915_gem_object_fault(obj, page_offset, true, write);
1395 /* Access to snoopable pages through the GTT is incoherent. */
1396 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1401 /* Now bind it into the GTT if needed */
1402 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1406 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1410 ret = i915_gem_object_get_fence(obj);
1414 obj->fault_mappable = true;
1416 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1420 /* Finally, remap it using the new GTT offset */
1421 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1423 i915_gem_object_ggtt_unpin(obj);
1425 mutex_unlock(&dev->struct_mutex);
1429 /* If this -EIO is due to a gpu hang, give the reset code a
1430 * chance to clean up the mess. Otherwise return the proper
1432 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
1433 ret = VM_FAULT_SIGBUS;
1438 * EAGAIN means the gpu is hung and we'll wait for the error
1439 * handler to reset everything when re-faulting in
1440 * i915_mutex_lock_interruptible.
1447 * EBUSY is ok: this just means that another thread
1448 * already did the job.
1450 ret = VM_FAULT_NOPAGE;
1456 ret = VM_FAULT_SIGBUS;
1459 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1460 ret = VM_FAULT_SIGBUS;
1464 intel_runtime_pm_put(dev_priv);
1468 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1470 struct i915_vma *vma;
1473 * Only the global gtt is relevant for gtt memory mappings, so restrict
1474 * list traversal to objects bound into the global address space. Note
1475 * that the active list should be empty, but better safe than sorry.
1477 WARN_ON(!list_empty(&dev_priv->gtt.base.active_list));
1478 list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
1479 i915_gem_release_mmap(vma->obj);
1480 list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
1481 i915_gem_release_mmap(vma->obj);
1485 * i915_gem_release_mmap - remove physical page mappings
1486 * @obj: obj in question
1488 * Preserve the reservation of the mmapping with the DRM core code, but
1489 * relinquish ownership of the pages back to the system.
1491 * It is vital that we remove the page mapping if we have mapped a tiled
1492 * object through the GTT and then lose the fence register due to
1493 * resource pressure. Similarly if the object has been moved out of the
1494 * aperture, than pages mapped into userspace must be revoked. Removing the
1495 * mapping will then trigger a page fault on the next user access, allowing
1496 * fixup by i915_gem_fault().
1499 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1501 if (!obj->fault_mappable)
1504 drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
1505 obj->fault_mappable = false;
1509 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1513 if (INTEL_INFO(dev)->gen >= 4 ||
1514 tiling_mode == I915_TILING_NONE)
1517 /* Previous chips need a power-of-two fence region when tiling */
1518 if (INTEL_INFO(dev)->gen == 3)
1519 gtt_size = 1024*1024;
1521 gtt_size = 512*1024;
1523 while (gtt_size < size)
1530 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1531 * @obj: object to check
1533 * Return the required GTT alignment for an object, taking into account
1534 * potential fence register mapping.
1537 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1538 int tiling_mode, bool fenced)
1541 * Minimum alignment is 4k (GTT page size), but might be greater
1542 * if a fence register is needed for the object.
1544 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1545 tiling_mode == I915_TILING_NONE)
1549 * Previous chips need to be aligned to the size of the smallest
1550 * fence register that can contain the object.
1552 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1555 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1557 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1560 if (drm_vma_node_has_offset(&obj->base.vma_node))
1563 dev_priv->mm.shrinker_no_lock_stealing = true;
1565 ret = drm_gem_create_mmap_offset(&obj->base);
1569 /* Badly fragmented mmap space? The only way we can recover
1570 * space is by destroying unwanted objects. We can't randomly release
1571 * mmap_offsets as userspace expects them to be persistent for the
1572 * lifetime of the objects. The closest we can is to release the
1573 * offsets on purgeable objects by truncating it and marking it purged,
1574 * which prevents userspace from ever using that object again.
1576 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1577 ret = drm_gem_create_mmap_offset(&obj->base);
1581 i915_gem_shrink_all(dev_priv);
1582 ret = drm_gem_create_mmap_offset(&obj->base);
1584 dev_priv->mm.shrinker_no_lock_stealing = false;
1589 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1591 drm_gem_free_mmap_offset(&obj->base);
1595 i915_gem_mmap_gtt(struct drm_file *file,
1596 struct drm_device *dev,
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 struct drm_i915_gem_object *obj;
1604 ret = i915_mutex_lock_interruptible(dev);
1608 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1609 if (&obj->base == NULL) {
1614 if (obj->base.size > dev_priv->gtt.mappable_end) {
1619 if (obj->madv != I915_MADV_WILLNEED) {
1620 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1625 ret = i915_gem_object_create_mmap_offset(obj);
1629 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1632 drm_gem_object_unreference(&obj->base);
1634 mutex_unlock(&dev->struct_mutex);
1639 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1641 * @data: GTT mapping ioctl data
1642 * @file: GEM object info
1644 * Simply returns the fake offset to userspace so it can mmap it.
1645 * The mmap call will end up in drm_gem_mmap(), which will set things
1646 * up so we can get faults in the handler above.
1648 * The fault handler will take care of binding the object into the GTT
1649 * (since it may have been evicted to make room for something), allocating
1650 * a fence register, and mapping the appropriate aperture address into
1654 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1655 struct drm_file *file)
1657 struct drm_i915_gem_mmap_gtt *args = data;
1659 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1662 /* Immediately discard the backing storage */
1664 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1666 struct inode *inode;
1668 i915_gem_object_free_mmap_offset(obj);
1670 if (obj->base.filp == NULL)
1673 /* Our goal here is to return as much of the memory as
1674 * is possible back to the system as we are called from OOM.
1675 * To do this we must instruct the shmfs to drop all of its
1676 * backing pages, *now*.
1678 inode = file_inode(obj->base.filp);
1679 shmem_truncate_range(inode, 0, (loff_t)-1);
1681 obj->madv = __I915_MADV_PURGED;
1685 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1687 return obj->madv == I915_MADV_DONTNEED;
1691 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1693 struct sg_page_iter sg_iter;
1696 BUG_ON(obj->madv == __I915_MADV_PURGED);
1698 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1700 /* In the event of a disaster, abandon all caches and
1701 * hope for the best.
1703 WARN_ON(ret != -EIO);
1704 i915_gem_clflush_object(obj, true);
1705 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1708 if (i915_gem_object_needs_bit17_swizzle(obj))
1709 i915_gem_object_save_bit_17_swizzle(obj);
1711 if (obj->madv == I915_MADV_DONTNEED)
1714 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1715 struct page *page = sg_page_iter_page(&sg_iter);
1718 set_page_dirty(page);
1720 if (obj->madv == I915_MADV_WILLNEED)
1721 mark_page_accessed(page);
1723 page_cache_release(page);
1727 sg_free_table(obj->pages);
1732 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1734 const struct drm_i915_gem_object_ops *ops = obj->ops;
1736 if (obj->pages == NULL)
1739 if (obj->pages_pin_count)
1742 BUG_ON(i915_gem_obj_bound_any(obj));
1744 /* ->put_pages might need to allocate memory for the bit17 swizzle
1745 * array, hence protect them from being reaped by removing them from gtt
1747 list_del(&obj->global_list);
1749 ops->put_pages(obj);
1752 if (i915_gem_object_is_purgeable(obj))
1753 i915_gem_object_truncate(obj);
1758 static unsigned long
1759 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1760 bool purgeable_only)
1762 struct list_head still_bound_list;
1763 struct drm_i915_gem_object *obj, *next;
1764 unsigned long count = 0;
1766 list_for_each_entry_safe(obj, next,
1767 &dev_priv->mm.unbound_list,
1769 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1770 i915_gem_object_put_pages(obj) == 0) {
1771 count += obj->base.size >> PAGE_SHIFT;
1772 if (count >= target)
1778 * As we may completely rewrite the bound list whilst unbinding
1779 * (due to retiring requests) we have to strictly process only
1780 * one element of the list at the time, and recheck the list
1781 * on every iteration.
1783 INIT_LIST_HEAD(&still_bound_list);
1784 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1785 struct i915_vma *vma, *v;
1787 obj = list_first_entry(&dev_priv->mm.bound_list,
1788 typeof(*obj), global_list);
1789 list_move_tail(&obj->global_list, &still_bound_list);
1791 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1795 * Hold a reference whilst we unbind this object, as we may
1796 * end up waiting for and retiring requests. This might
1797 * release the final reference (held by the active list)
1798 * and result in the object being freed from under us.
1799 * in this object being freed.
1801 * Note 1: Shrinking the bound list is special since only active
1802 * (and hence bound objects) can contain such limbo objects, so
1803 * we don't need special tricks for shrinking the unbound list.
1804 * The only other place where we have to be careful with active
1805 * objects suddenly disappearing due to retiring requests is the
1808 * Note 2: Even though the bound list doesn't hold a reference
1809 * to the object we can safely grab one here: The final object
1810 * unreferencing and the bound_list are both protected by the
1811 * dev->struct_mutex and so we won't ever be able to observe an
1812 * object on the bound_list with a reference count equals 0.
1814 drm_gem_object_reference(&obj->base);
1816 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1817 if (i915_vma_unbind(vma))
1820 if (i915_gem_object_put_pages(obj) == 0)
1821 count += obj->base.size >> PAGE_SHIFT;
1823 drm_gem_object_unreference(&obj->base);
1825 list_splice(&still_bound_list, &dev_priv->mm.bound_list);
1830 static unsigned long
1831 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1833 return __i915_gem_shrink(dev_priv, target, true);
1836 static unsigned long
1837 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1839 struct drm_i915_gem_object *obj, *next;
1842 i915_gem_evict_everything(dev_priv->dev);
1844 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1846 if (i915_gem_object_put_pages(obj) == 0)
1847 freed += obj->base.size >> PAGE_SHIFT;
1853 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1855 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1857 struct address_space *mapping;
1858 struct sg_table *st;
1859 struct scatterlist *sg;
1860 struct sg_page_iter sg_iter;
1862 unsigned long last_pfn = 0; /* suppress gcc warning */
1865 /* Assert that the object is not currently in any GPU domain. As it
1866 * wasn't in the GTT, there shouldn't be any way it could have been in
1869 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1870 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1872 st = kmalloc(sizeof(*st), GFP_KERNEL);
1876 page_count = obj->base.size / PAGE_SIZE;
1877 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1882 /* Get the list of pages out of our struct file. They'll be pinned
1883 * at this point until we release them.
1885 * Fail silently without starting the shrinker
1887 mapping = file_inode(obj->base.filp)->i_mapping;
1888 gfp = mapping_gfp_mask(mapping);
1889 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1890 gfp &= ~(__GFP_IO | __GFP_WAIT);
1893 for (i = 0; i < page_count; i++) {
1894 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1896 i915_gem_purge(dev_priv, page_count);
1897 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1900 /* We've tried hard to allocate the memory by reaping
1901 * our own buffer, now let the real VM do its job and
1902 * go down in flames if truly OOM.
1904 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1905 gfp |= __GFP_IO | __GFP_WAIT;
1907 i915_gem_shrink_all(dev_priv);
1908 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1912 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1913 gfp &= ~(__GFP_IO | __GFP_WAIT);
1915 #ifdef CONFIG_SWIOTLB
1916 if (swiotlb_nr_tbl()) {
1918 sg_set_page(sg, page, PAGE_SIZE, 0);
1923 if (!i || page_to_pfn(page) != last_pfn + 1) {
1927 sg_set_page(sg, page, PAGE_SIZE, 0);
1929 sg->length += PAGE_SIZE;
1931 last_pfn = page_to_pfn(page);
1933 /* Check that the i965g/gm workaround works. */
1934 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
1936 #ifdef CONFIG_SWIOTLB
1937 if (!swiotlb_nr_tbl())
1942 if (i915_gem_object_needs_bit17_swizzle(obj))
1943 i915_gem_object_do_bit_17_swizzle(obj);
1949 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1950 page_cache_release(sg_page_iter_page(&sg_iter));
1953 return PTR_ERR(page);
1956 /* Ensure that the associated pages are gathered from the backing storage
1957 * and pinned into our object. i915_gem_object_get_pages() may be called
1958 * multiple times before they are released by a single call to
1959 * i915_gem_object_put_pages() - once the pages are no longer referenced
1960 * either as a result of memory pressure (reaping pages under the shrinker)
1961 * or as the object is itself released.
1964 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1966 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1967 const struct drm_i915_gem_object_ops *ops = obj->ops;
1973 if (obj->madv != I915_MADV_WILLNEED) {
1974 DRM_ERROR("Attempting to obtain a purgeable object\n");
1978 BUG_ON(obj->pages_pin_count);
1980 ret = ops->get_pages(obj);
1984 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1989 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1990 struct intel_ring_buffer *ring)
1992 struct drm_device *dev = obj->base.dev;
1993 struct drm_i915_private *dev_priv = dev->dev_private;
1994 u32 seqno = intel_ring_get_seqno(ring);
1996 BUG_ON(ring == NULL);
1997 if (obj->ring != ring && obj->last_write_seqno) {
1998 /* Keep the seqno relative to the current ring */
1999 obj->last_write_seqno = seqno;
2003 /* Add a reference if we're newly entering the active list. */
2005 drm_gem_object_reference(&obj->base);
2009 list_move_tail(&obj->ring_list, &ring->active_list);
2011 obj->last_read_seqno = seqno;
2013 if (obj->fenced_gpu_access) {
2014 obj->last_fenced_seqno = seqno;
2016 /* Bump MRU to take account of the delayed flush */
2017 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2018 struct drm_i915_fence_reg *reg;
2020 reg = &dev_priv->fence_regs[obj->fence_reg];
2021 list_move_tail(®->lru_list,
2022 &dev_priv->mm.fence_list);
2027 void i915_vma_move_to_active(struct i915_vma *vma,
2028 struct intel_ring_buffer *ring)
2030 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2031 return i915_gem_object_move_to_active(vma->obj, ring);
2035 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2037 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2038 struct i915_address_space *vm;
2039 struct i915_vma *vma;
2041 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2042 BUG_ON(!obj->active);
2044 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2045 vma = i915_gem_obj_to_vma(obj, vm);
2046 if (vma && !list_empty(&vma->mm_list))
2047 list_move_tail(&vma->mm_list, &vm->inactive_list);
2050 list_del_init(&obj->ring_list);
2053 obj->last_read_seqno = 0;
2054 obj->last_write_seqno = 0;
2055 obj->base.write_domain = 0;
2057 obj->last_fenced_seqno = 0;
2058 obj->fenced_gpu_access = false;
2061 drm_gem_object_unreference(&obj->base);
2063 WARN_ON(i915_verify_lists(dev));
2067 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070 struct intel_ring_buffer *ring;
2073 /* Carefully retire all requests without writing to the rings */
2074 for_each_ring(ring, dev_priv, i) {
2075 ret = intel_ring_idle(ring);
2079 i915_gem_retire_requests(dev);
2081 /* Finally reset hw state */
2082 for_each_ring(ring, dev_priv, i) {
2083 intel_ring_init_seqno(ring, seqno);
2085 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2086 ring->sync_seqno[j] = 0;
2092 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2094 struct drm_i915_private *dev_priv = dev->dev_private;
2100 /* HWS page needs to be set less than what we
2101 * will inject to ring
2103 ret = i915_gem_init_seqno(dev, seqno - 1);
2107 /* Carefully set the last_seqno value so that wrap
2108 * detection still works
2110 dev_priv->next_seqno = seqno;
2111 dev_priv->last_seqno = seqno - 1;
2112 if (dev_priv->last_seqno == 0)
2113 dev_priv->last_seqno--;
2119 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2123 /* reserve 0 for non-seqno */
2124 if (dev_priv->next_seqno == 0) {
2125 int ret = i915_gem_init_seqno(dev, 0);
2129 dev_priv->next_seqno = 1;
2132 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2136 int __i915_add_request(struct intel_ring_buffer *ring,
2137 struct drm_file *file,
2138 struct drm_i915_gem_object *obj,
2141 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2142 struct drm_i915_gem_request *request;
2143 u32 request_ring_position, request_start;
2147 request_start = intel_ring_get_tail(ring);
2149 * Emit any outstanding flushes - execbuf can fail to emit the flush
2150 * after having emitted the batchbuffer command. Hence we need to fix
2151 * things up similar to emitting the lazy request. The difference here
2152 * is that the flush _must_ happen before the next request, no matter
2155 ret = intel_ring_flush_all_caches(ring);
2159 request = ring->preallocated_lazy_request;
2160 if (WARN_ON(request == NULL))
2163 /* Record the position of the start of the request so that
2164 * should we detect the updated seqno part-way through the
2165 * GPU processing the request, we never over-estimate the
2166 * position of the head.
2168 request_ring_position = intel_ring_get_tail(ring);
2170 ret = ring->add_request(ring);
2174 request->seqno = intel_ring_get_seqno(ring);
2175 request->ring = ring;
2176 request->head = request_start;
2177 request->tail = request_ring_position;
2179 /* Whilst this request exists, batch_obj will be on the
2180 * active_list, and so will hold the active reference. Only when this
2181 * request is retired will the the batch_obj be moved onto the
2182 * inactive_list and lose its active reference. Hence we do not need
2183 * to explicitly hold another reference here.
2185 request->batch_obj = obj;
2187 /* Hold a reference to the current context so that we can inspect
2188 * it later in case a hangcheck error event fires.
2190 request->ctx = ring->last_context;
2192 i915_gem_context_reference(request->ctx);
2194 request->emitted_jiffies = jiffies;
2195 was_empty = list_empty(&ring->request_list);
2196 list_add_tail(&request->list, &ring->request_list);
2197 request->file_priv = NULL;
2200 struct drm_i915_file_private *file_priv = file->driver_priv;
2202 spin_lock(&file_priv->mm.lock);
2203 request->file_priv = file_priv;
2204 list_add_tail(&request->client_list,
2205 &file_priv->mm.request_list);
2206 spin_unlock(&file_priv->mm.lock);
2209 trace_i915_gem_request_add(ring, request->seqno);
2210 ring->outstanding_lazy_seqno = 0;
2211 ring->preallocated_lazy_request = NULL;
2213 if (!dev_priv->ums.mm_suspended) {
2214 i915_queue_hangcheck(ring->dev);
2217 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2218 queue_delayed_work(dev_priv->wq,
2219 &dev_priv->mm.retire_work,
2220 round_jiffies_up_relative(HZ));
2221 intel_mark_busy(dev_priv->dev);
2226 *out_seqno = request->seqno;
2231 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2233 struct drm_i915_file_private *file_priv = request->file_priv;
2238 spin_lock(&file_priv->mm.lock);
2239 list_del(&request->client_list);
2240 request->file_priv = NULL;
2241 spin_unlock(&file_priv->mm.lock);
2244 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2245 const struct i915_hw_context *ctx)
2247 unsigned long elapsed;
2249 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2251 if (ctx->hang_stats.banned)
2254 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2255 if (dev_priv->gpu_error.stop_rings == 0 &&
2256 i915_gem_context_is_default(ctx)) {
2257 DRM_ERROR("gpu hanging too fast, banning!\n");
2259 DRM_DEBUG("context hanging too fast, banning!\n");
2268 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2269 struct i915_hw_context *ctx,
2272 struct i915_ctx_hang_stats *hs;
2277 hs = &ctx->hang_stats;
2280 hs->banned = i915_context_is_banned(dev_priv, ctx);
2282 hs->guilty_ts = get_seconds();
2284 hs->batch_pending++;
2288 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2290 list_del(&request->list);
2291 i915_gem_request_remove_from_client(request);
2294 i915_gem_context_unreference(request->ctx);
2299 static struct drm_i915_gem_request *
2300 i915_gem_find_first_non_complete(struct intel_ring_buffer *ring)
2302 struct drm_i915_gem_request *request;
2303 const u32 completed_seqno = ring->get_seqno(ring, false);
2305 list_for_each_entry(request, &ring->request_list, list) {
2306 if (i915_seqno_passed(completed_seqno, request->seqno))
2315 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2316 struct intel_ring_buffer *ring)
2318 struct drm_i915_gem_request *request;
2321 request = i915_gem_find_first_non_complete(ring);
2323 if (request == NULL)
2326 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2328 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2330 list_for_each_entry_continue(request, &ring->request_list, list)
2331 i915_set_reset_status(dev_priv, request->ctx, false);
2334 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2335 struct intel_ring_buffer *ring)
2337 while (!list_empty(&ring->active_list)) {
2338 struct drm_i915_gem_object *obj;
2340 obj = list_first_entry(&ring->active_list,
2341 struct drm_i915_gem_object,
2344 i915_gem_object_move_to_inactive(obj);
2348 * We must free the requests after all the corresponding objects have
2349 * been moved off active lists. Which is the same order as the normal
2350 * retire_requests function does. This is important if object hold
2351 * implicit references on things like e.g. ppgtt address spaces through
2354 while (!list_empty(&ring->request_list)) {
2355 struct drm_i915_gem_request *request;
2357 request = list_first_entry(&ring->request_list,
2358 struct drm_i915_gem_request,
2361 i915_gem_free_request(request);
2365 void i915_gem_restore_fences(struct drm_device *dev)
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2370 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2371 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2374 * Commit delayed tiling changes if we have an object still
2375 * attached to the fence, otherwise just clear the fence.
2378 i915_gem_object_update_fence(reg->obj, reg,
2379 reg->obj->tiling_mode);
2381 i915_gem_write_fence(dev, i, NULL);
2386 void i915_gem_reset(struct drm_device *dev)
2388 struct drm_i915_private *dev_priv = dev->dev_private;
2389 struct intel_ring_buffer *ring;
2393 * Before we free the objects from the requests, we need to inspect
2394 * them for finding the guilty party. As the requests only borrow
2395 * their reference to the objects, the inspection must be done first.
2397 for_each_ring(ring, dev_priv, i)
2398 i915_gem_reset_ring_status(dev_priv, ring);
2400 for_each_ring(ring, dev_priv, i)
2401 i915_gem_reset_ring_cleanup(dev_priv, ring);
2403 i915_gem_cleanup_ringbuffer(dev);
2405 i915_gem_context_reset(dev);
2407 i915_gem_restore_fences(dev);
2411 * This function clears the request list as sequence numbers are passed.
2414 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2418 if (list_empty(&ring->request_list))
2421 WARN_ON(i915_verify_lists(ring->dev));
2423 seqno = ring->get_seqno(ring, true);
2425 /* Move any buffers on the active list that are no longer referenced
2426 * by the ringbuffer to the flushing/inactive lists as appropriate,
2427 * before we free the context associated with the requests.
2429 while (!list_empty(&ring->active_list)) {
2430 struct drm_i915_gem_object *obj;
2432 obj = list_first_entry(&ring->active_list,
2433 struct drm_i915_gem_object,
2436 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2439 i915_gem_object_move_to_inactive(obj);
2443 while (!list_empty(&ring->request_list)) {
2444 struct drm_i915_gem_request *request;
2446 request = list_first_entry(&ring->request_list,
2447 struct drm_i915_gem_request,
2450 if (!i915_seqno_passed(seqno, request->seqno))
2453 trace_i915_gem_request_retire(ring, request->seqno);
2454 /* We know the GPU must have read the request to have
2455 * sent us the seqno + interrupt, so use the position
2456 * of tail of the request to update the last known position
2459 ring->last_retired_head = request->tail;
2461 i915_gem_free_request(request);
2464 if (unlikely(ring->trace_irq_seqno &&
2465 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2466 ring->irq_put(ring);
2467 ring->trace_irq_seqno = 0;
2470 WARN_ON(i915_verify_lists(ring->dev));
2474 i915_gem_retire_requests(struct drm_device *dev)
2476 drm_i915_private_t *dev_priv = dev->dev_private;
2477 struct intel_ring_buffer *ring;
2481 for_each_ring(ring, dev_priv, i) {
2482 i915_gem_retire_requests_ring(ring);
2483 idle &= list_empty(&ring->request_list);
2487 mod_delayed_work(dev_priv->wq,
2488 &dev_priv->mm.idle_work,
2489 msecs_to_jiffies(100));
2495 i915_gem_retire_work_handler(struct work_struct *work)
2497 struct drm_i915_private *dev_priv =
2498 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2499 struct drm_device *dev = dev_priv->dev;
2502 /* Come back later if the device is busy... */
2504 if (mutex_trylock(&dev->struct_mutex)) {
2505 idle = i915_gem_retire_requests(dev);
2506 mutex_unlock(&dev->struct_mutex);
2509 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2510 round_jiffies_up_relative(HZ));
2514 i915_gem_idle_work_handler(struct work_struct *work)
2516 struct drm_i915_private *dev_priv =
2517 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2519 intel_mark_idle(dev_priv->dev);
2523 * Ensures that an object will eventually get non-busy by flushing any required
2524 * write domains, emitting any outstanding lazy request and retiring and
2525 * completed requests.
2528 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2533 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2537 i915_gem_retire_requests_ring(obj->ring);
2544 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2545 * @DRM_IOCTL_ARGS: standard ioctl arguments
2547 * Returns 0 if successful, else an error is returned with the remaining time in
2548 * the timeout parameter.
2549 * -ETIME: object is still busy after timeout
2550 * -ERESTARTSYS: signal interrupted the wait
2551 * -ENONENT: object doesn't exist
2552 * Also possible, but rare:
2553 * -EAGAIN: GPU wedged
2555 * -ENODEV: Internal IRQ fail
2556 * -E?: The add request failed
2558 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2559 * non-zero timeout parameter the wait ioctl will wait for the given number of
2560 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2561 * without holding struct_mutex the object may become re-busied before this
2562 * function completes. A similar but shorter * race condition exists in the busy
2566 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2568 drm_i915_private_t *dev_priv = dev->dev_private;
2569 struct drm_i915_gem_wait *args = data;
2570 struct drm_i915_gem_object *obj;
2571 struct intel_ring_buffer *ring = NULL;
2572 struct timespec timeout_stack, *timeout = NULL;
2573 unsigned reset_counter;
2577 if (args->timeout_ns >= 0) {
2578 timeout_stack = ns_to_timespec(args->timeout_ns);
2579 timeout = &timeout_stack;
2582 ret = i915_mutex_lock_interruptible(dev);
2586 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2587 if (&obj->base == NULL) {
2588 mutex_unlock(&dev->struct_mutex);
2592 /* Need to make sure the object gets inactive eventually. */
2593 ret = i915_gem_object_flush_active(obj);
2598 seqno = obj->last_read_seqno;
2605 /* Do this after OLR check to make sure we make forward progress polling
2606 * on this IOCTL with a 0 timeout (like busy ioctl)
2608 if (!args->timeout_ns) {
2613 drm_gem_object_unreference(&obj->base);
2614 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2615 mutex_unlock(&dev->struct_mutex);
2617 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
2619 args->timeout_ns = timespec_to_ns(timeout);
2623 drm_gem_object_unreference(&obj->base);
2624 mutex_unlock(&dev->struct_mutex);
2629 * i915_gem_object_sync - sync an object to a ring.
2631 * @obj: object which may be in use on another ring.
2632 * @to: ring we wish to use the object on. May be NULL.
2634 * This code is meant to abstract object synchronization with the GPU.
2635 * Calling with NULL implies synchronizing the object with the CPU
2636 * rather than a particular GPU ring.
2638 * Returns 0 if successful, else propagates up the lower layer error.
2641 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2642 struct intel_ring_buffer *to)
2644 struct intel_ring_buffer *from = obj->ring;
2648 if (from == NULL || to == from)
2651 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2652 return i915_gem_object_wait_rendering(obj, false);
2654 idx = intel_ring_sync_index(from, to);
2656 seqno = obj->last_read_seqno;
2657 if (seqno <= from->sync_seqno[idx])
2660 ret = i915_gem_check_olr(obj->ring, seqno);
2664 trace_i915_gem_ring_sync_to(from, to, seqno);
2665 ret = to->sync_to(to, from, seqno);
2667 /* We use last_read_seqno because sync_to()
2668 * might have just caused seqno wrap under
2671 from->sync_seqno[idx] = obj->last_read_seqno;
2676 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2678 u32 old_write_domain, old_read_domains;
2680 /* Force a pagefault for domain tracking on next user access */
2681 i915_gem_release_mmap(obj);
2683 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2686 /* Wait for any direct GTT access to complete */
2689 old_read_domains = obj->base.read_domains;
2690 old_write_domain = obj->base.write_domain;
2692 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2693 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2695 trace_i915_gem_object_change_domain(obj,
2700 int i915_vma_unbind(struct i915_vma *vma)
2702 struct drm_i915_gem_object *obj = vma->obj;
2703 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2706 if (list_empty(&vma->vma_link))
2709 if (!drm_mm_node_allocated(&vma->node)) {
2710 i915_gem_vma_destroy(vma);
2718 BUG_ON(obj->pages == NULL);
2720 ret = i915_gem_object_finish_gpu(obj);
2723 /* Continue on if we fail due to EIO, the GPU is hung so we
2724 * should be safe and we need to cleanup or else we might
2725 * cause memory corruption through use-after-free.
2728 i915_gem_object_finish_gtt(obj);
2730 /* release the fence reg _after_ flushing */
2731 ret = i915_gem_object_put_fence(obj);
2735 trace_i915_vma_unbind(vma);
2737 vma->unbind_vma(vma);
2739 i915_gem_gtt_finish_object(obj);
2741 list_del(&vma->mm_list);
2742 /* Avoid an unnecessary call to unbind on rebind. */
2743 if (i915_is_ggtt(vma->vm))
2744 obj->map_and_fenceable = true;
2746 drm_mm_remove_node(&vma->node);
2747 i915_gem_vma_destroy(vma);
2749 /* Since the unbound list is global, only move to that list if
2750 * no more VMAs exist. */
2751 if (list_empty(&obj->vma_list))
2752 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2754 /* And finally now the object is completely decoupled from this vma,
2755 * we can drop its hold on the backing storage and allow it to be
2756 * reaped by the shrinker.
2758 i915_gem_object_unpin_pages(obj);
2764 * Unbinds an object from the global GTT aperture.
2767 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2769 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2770 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2772 if (!i915_gem_obj_ggtt_bound(obj))
2775 if (i915_gem_obj_to_ggtt(obj)->pin_count)
2778 BUG_ON(obj->pages == NULL);
2780 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2783 int i915_gpu_idle(struct drm_device *dev)
2785 drm_i915_private_t *dev_priv = dev->dev_private;
2786 struct intel_ring_buffer *ring;
2789 /* Flush everything onto the inactive list. */
2790 for_each_ring(ring, dev_priv, i) {
2791 ret = i915_switch_context(ring, NULL, ring->default_context);
2795 ret = intel_ring_idle(ring);
2803 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2804 struct drm_i915_gem_object *obj)
2806 drm_i915_private_t *dev_priv = dev->dev_private;
2808 int fence_pitch_shift;
2810 if (INTEL_INFO(dev)->gen >= 6) {
2811 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2812 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2814 fence_reg = FENCE_REG_965_0;
2815 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2818 fence_reg += reg * 8;
2820 /* To w/a incoherency with non-atomic 64-bit register updates,
2821 * we split the 64-bit update into two 32-bit writes. In order
2822 * for a partial fence not to be evaluated between writes, we
2823 * precede the update with write to turn off the fence register,
2824 * and only enable the fence as the last step.
2826 * For extra levels of paranoia, we make sure each step lands
2827 * before applying the next step.
2829 I915_WRITE(fence_reg, 0);
2830 POSTING_READ(fence_reg);
2833 u32 size = i915_gem_obj_ggtt_size(obj);
2836 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2838 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2839 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2840 if (obj->tiling_mode == I915_TILING_Y)
2841 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2842 val |= I965_FENCE_REG_VALID;
2844 I915_WRITE(fence_reg + 4, val >> 32);
2845 POSTING_READ(fence_reg + 4);
2847 I915_WRITE(fence_reg + 0, val);
2848 POSTING_READ(fence_reg);
2850 I915_WRITE(fence_reg + 4, 0);
2851 POSTING_READ(fence_reg + 4);
2855 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2856 struct drm_i915_gem_object *obj)
2858 drm_i915_private_t *dev_priv = dev->dev_private;
2862 u32 size = i915_gem_obj_ggtt_size(obj);
2866 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2867 (size & -size) != size ||
2868 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2869 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2870 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2872 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2877 /* Note: pitch better be a power of two tile widths */
2878 pitch_val = obj->stride / tile_width;
2879 pitch_val = ffs(pitch_val) - 1;
2881 val = i915_gem_obj_ggtt_offset(obj);
2882 if (obj->tiling_mode == I915_TILING_Y)
2883 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2884 val |= I915_FENCE_SIZE_BITS(size);
2885 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2886 val |= I830_FENCE_REG_VALID;
2891 reg = FENCE_REG_830_0 + reg * 4;
2893 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2895 I915_WRITE(reg, val);
2899 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2900 struct drm_i915_gem_object *obj)
2902 drm_i915_private_t *dev_priv = dev->dev_private;
2906 u32 size = i915_gem_obj_ggtt_size(obj);
2909 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2910 (size & -size) != size ||
2911 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2912 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2913 i915_gem_obj_ggtt_offset(obj), size);
2915 pitch_val = obj->stride / 128;
2916 pitch_val = ffs(pitch_val) - 1;
2918 val = i915_gem_obj_ggtt_offset(obj);
2919 if (obj->tiling_mode == I915_TILING_Y)
2920 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2921 val |= I830_FENCE_SIZE_BITS(size);
2922 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2923 val |= I830_FENCE_REG_VALID;
2927 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2928 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2931 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2933 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2936 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2937 struct drm_i915_gem_object *obj)
2939 struct drm_i915_private *dev_priv = dev->dev_private;
2941 /* Ensure that all CPU reads are completed before installing a fence
2942 * and all writes before removing the fence.
2944 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2947 WARN(obj && (!obj->stride || !obj->tiling_mode),
2948 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2949 obj->stride, obj->tiling_mode);
2951 switch (INTEL_INFO(dev)->gen) {
2956 case 4: i965_write_fence_reg(dev, reg, obj); break;
2957 case 3: i915_write_fence_reg(dev, reg, obj); break;
2958 case 2: i830_write_fence_reg(dev, reg, obj); break;
2962 /* And similarly be paranoid that no direct access to this region
2963 * is reordered to before the fence is installed.
2965 if (i915_gem_object_needs_mb(obj))
2969 static inline int fence_number(struct drm_i915_private *dev_priv,
2970 struct drm_i915_fence_reg *fence)
2972 return fence - dev_priv->fence_regs;
2975 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2976 struct drm_i915_fence_reg *fence,
2979 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2980 int reg = fence_number(dev_priv, fence);
2982 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2985 obj->fence_reg = reg;
2987 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2989 obj->fence_reg = I915_FENCE_REG_NONE;
2991 list_del_init(&fence->lru_list);
2993 obj->fence_dirty = false;
2997 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2999 if (obj->last_fenced_seqno) {
3000 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3004 obj->last_fenced_seqno = 0;
3007 obj->fenced_gpu_access = false;
3012 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3014 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3015 struct drm_i915_fence_reg *fence;
3018 ret = i915_gem_object_wait_fence(obj);
3022 if (obj->fence_reg == I915_FENCE_REG_NONE)
3025 fence = &dev_priv->fence_regs[obj->fence_reg];
3027 i915_gem_object_fence_lost(obj);
3028 i915_gem_object_update_fence(obj, fence, false);
3033 static struct drm_i915_fence_reg *
3034 i915_find_fence_reg(struct drm_device *dev)
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct drm_i915_fence_reg *reg, *avail;
3040 /* First try to find a free reg */
3042 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3043 reg = &dev_priv->fence_regs[i];
3047 if (!reg->pin_count)
3054 /* None available, try to steal one or wait for a user to finish */
3055 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3063 /* Wait for completion of pending flips which consume fences */
3064 if (intel_has_pending_fb_unpin(dev))
3065 return ERR_PTR(-EAGAIN);
3067 return ERR_PTR(-EDEADLK);
3071 * i915_gem_object_get_fence - set up fencing for an object
3072 * @obj: object to map through a fence reg
3074 * When mapping objects through the GTT, userspace wants to be able to write
3075 * to them without having to worry about swizzling if the object is tiled.
3076 * This function walks the fence regs looking for a free one for @obj,
3077 * stealing one if it can't find any.
3079 * It then sets up the reg based on the object's properties: address, pitch
3080 * and tiling format.
3082 * For an untiled surface, this removes any existing fence.
3085 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3087 struct drm_device *dev = obj->base.dev;
3088 struct drm_i915_private *dev_priv = dev->dev_private;
3089 bool enable = obj->tiling_mode != I915_TILING_NONE;
3090 struct drm_i915_fence_reg *reg;
3093 /* Have we updated the tiling parameters upon the object and so
3094 * will need to serialise the write to the associated fence register?
3096 if (obj->fence_dirty) {
3097 ret = i915_gem_object_wait_fence(obj);
3102 /* Just update our place in the LRU if our fence is getting reused. */
3103 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3104 reg = &dev_priv->fence_regs[obj->fence_reg];
3105 if (!obj->fence_dirty) {
3106 list_move_tail(®->lru_list,
3107 &dev_priv->mm.fence_list);
3110 } else if (enable) {
3111 reg = i915_find_fence_reg(dev);
3113 return PTR_ERR(reg);
3116 struct drm_i915_gem_object *old = reg->obj;
3118 ret = i915_gem_object_wait_fence(old);
3122 i915_gem_object_fence_lost(old);
3127 i915_gem_object_update_fence(obj, reg, enable);
3132 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3133 struct drm_mm_node *gtt_space,
3134 unsigned long cache_level)
3136 struct drm_mm_node *other;
3138 /* On non-LLC machines we have to be careful when putting differing
3139 * types of snoopable memory together to avoid the prefetcher
3140 * crossing memory domains and dying.
3145 if (!drm_mm_node_allocated(gtt_space))
3148 if (list_empty(>t_space->node_list))
3151 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3152 if (other->allocated && !other->hole_follows && other->color != cache_level)
3155 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3156 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3162 static void i915_gem_verify_gtt(struct drm_device *dev)
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 struct drm_i915_gem_object *obj;
3169 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3170 if (obj->gtt_space == NULL) {
3171 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3176 if (obj->cache_level != obj->gtt_space->color) {
3177 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3178 i915_gem_obj_ggtt_offset(obj),
3179 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3181 obj->gtt_space->color);
3186 if (!i915_gem_valid_gtt_space(dev,
3188 obj->cache_level)) {
3189 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3190 i915_gem_obj_ggtt_offset(obj),
3191 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3203 * Finds free space in the GTT aperture and binds the object there.
3206 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3207 struct i915_address_space *vm,
3209 bool map_and_fenceable,
3212 struct drm_device *dev = obj->base.dev;
3213 drm_i915_private_t *dev_priv = dev->dev_private;
3214 u32 size, fence_size, fence_alignment, unfenced_alignment;
3216 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3217 struct i915_vma *vma;
3220 fence_size = i915_gem_get_gtt_size(dev,
3223 fence_alignment = i915_gem_get_gtt_alignment(dev,
3225 obj->tiling_mode, true);
3226 unfenced_alignment =
3227 i915_gem_get_gtt_alignment(dev,
3229 obj->tiling_mode, false);
3232 alignment = map_and_fenceable ? fence_alignment :
3234 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3235 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3239 size = map_and_fenceable ? fence_size : obj->base.size;
3241 /* If the object is bigger than the entire aperture, reject it early
3242 * before evicting everything in a vain attempt to find space.
3244 if (obj->base.size > gtt_max) {
3245 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3247 map_and_fenceable ? "mappable" : "total",
3252 ret = i915_gem_object_get_pages(obj);
3256 i915_gem_object_pin_pages(obj);
3258 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3265 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3267 obj->cache_level, 0, gtt_max,
3268 DRM_MM_SEARCH_DEFAULT);
3270 ret = i915_gem_evict_something(dev, vm, size, alignment,
3279 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3280 obj->cache_level))) {
3282 goto err_remove_node;
3285 ret = i915_gem_gtt_prepare_object(obj);
3287 goto err_remove_node;
3289 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3290 list_add_tail(&vma->mm_list, &vm->inactive_list);
3292 if (i915_is_ggtt(vm)) {
3293 bool mappable, fenceable;
3295 fenceable = (vma->node.size == fence_size &&
3296 (vma->node.start & (fence_alignment - 1)) == 0);
3298 mappable = (vma->node.start + obj->base.size <=
3299 dev_priv->gtt.mappable_end);
3301 obj->map_and_fenceable = mappable && fenceable;
3304 WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3306 trace_i915_vma_bind(vma, map_and_fenceable);
3307 i915_gem_verify_gtt(dev);
3311 drm_mm_remove_node(&vma->node);
3313 i915_gem_vma_destroy(vma);
3315 i915_gem_object_unpin_pages(obj);
3320 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3323 /* If we don't have a page list set up, then we're not pinned
3324 * to GPU, and we can ignore the cache flush because it'll happen
3325 * again at bind time.
3327 if (obj->pages == NULL)
3331 * Stolen memory is always coherent with the GPU as it is explicitly
3332 * marked as wc by the system, or the system is cache-coherent.
3337 /* If the GPU is snooping the contents of the CPU cache,
3338 * we do not need to manually clear the CPU cache lines. However,
3339 * the caches are only snooped when the render cache is
3340 * flushed/invalidated. As we always have to emit invalidations
3341 * and flushes when moving into and out of the RENDER domain, correct
3342 * snooping behaviour occurs naturally as the result of our domain
3345 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3348 trace_i915_gem_object_clflush(obj);
3349 drm_clflush_sg(obj->pages);
3354 /** Flushes the GTT write domain for the object if it's dirty. */
3356 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3358 uint32_t old_write_domain;
3360 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3363 /* No actual flushing is required for the GTT write domain. Writes
3364 * to it immediately go to main memory as far as we know, so there's
3365 * no chipset flush. It also doesn't land in render cache.
3367 * However, we do have to enforce the order so that all writes through
3368 * the GTT land before any writes to the device, such as updates to
3373 old_write_domain = obj->base.write_domain;
3374 obj->base.write_domain = 0;
3376 trace_i915_gem_object_change_domain(obj,
3377 obj->base.read_domains,
3381 /** Flushes the CPU write domain for the object if it's dirty. */
3383 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3386 uint32_t old_write_domain;
3388 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3391 if (i915_gem_clflush_object(obj, force))
3392 i915_gem_chipset_flush(obj->base.dev);
3394 old_write_domain = obj->base.write_domain;
3395 obj->base.write_domain = 0;
3397 trace_i915_gem_object_change_domain(obj,
3398 obj->base.read_domains,
3403 * Moves a single object to the GTT read, and possibly write domain.
3405 * This function returns when the move is complete, including waiting on
3409 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3411 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3412 uint32_t old_write_domain, old_read_domains;
3415 /* Not valid to be called on unbound objects. */
3416 if (!i915_gem_obj_bound_any(obj))
3419 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3422 ret = i915_gem_object_wait_rendering(obj, !write);
3426 i915_gem_object_flush_cpu_write_domain(obj, false);
3428 /* Serialise direct access to this object with the barriers for
3429 * coherent writes from the GPU, by effectively invalidating the
3430 * GTT domain upon first access.
3432 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3435 old_write_domain = obj->base.write_domain;
3436 old_read_domains = obj->base.read_domains;
3438 /* It should now be out of any other write domains, and we can update
3439 * the domain values for our changes.
3441 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3442 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3444 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3445 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3449 trace_i915_gem_object_change_domain(obj,
3453 /* And bump the LRU for this access */
3454 if (i915_gem_object_is_inactive(obj)) {
3455 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3457 list_move_tail(&vma->mm_list,
3458 &dev_priv->gtt.base.inactive_list);
3465 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3466 enum i915_cache_level cache_level)
3468 struct drm_device *dev = obj->base.dev;
3469 struct i915_vma *vma;
3472 if (obj->cache_level == cache_level)
3475 if (i915_gem_obj_is_pinned(obj)) {
3476 DRM_DEBUG("can not change the cache level of pinned objects\n");
3480 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3481 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3482 ret = i915_vma_unbind(vma);
3490 if (i915_gem_obj_bound_any(obj)) {
3491 ret = i915_gem_object_finish_gpu(obj);
3495 i915_gem_object_finish_gtt(obj);
3497 /* Before SandyBridge, you could not use tiling or fence
3498 * registers with snooped memory, so relinquish any fences
3499 * currently pointing to our region in the aperture.
3501 if (INTEL_INFO(dev)->gen < 6) {
3502 ret = i915_gem_object_put_fence(obj);
3507 list_for_each_entry(vma, &obj->vma_list, vma_link)
3508 vma->bind_vma(vma, cache_level, 0);
3511 list_for_each_entry(vma, &obj->vma_list, vma_link)
3512 vma->node.color = cache_level;
3513 obj->cache_level = cache_level;
3515 if (cpu_write_needs_clflush(obj)) {
3516 u32 old_read_domains, old_write_domain;
3518 /* If we're coming from LLC cached, then we haven't
3519 * actually been tracking whether the data is in the
3520 * CPU cache or not, since we only allow one bit set
3521 * in obj->write_domain and have been skipping the clflushes.
3522 * Just set it to the CPU cache for now.
3524 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3526 old_read_domains = obj->base.read_domains;
3527 old_write_domain = obj->base.write_domain;
3529 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3530 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3532 trace_i915_gem_object_change_domain(obj,
3537 i915_gem_verify_gtt(dev);
3541 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3542 struct drm_file *file)
3544 struct drm_i915_gem_caching *args = data;
3545 struct drm_i915_gem_object *obj;
3548 ret = i915_mutex_lock_interruptible(dev);
3552 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3553 if (&obj->base == NULL) {
3558 switch (obj->cache_level) {
3559 case I915_CACHE_LLC:
3560 case I915_CACHE_L3_LLC:
3561 args->caching = I915_CACHING_CACHED;
3565 args->caching = I915_CACHING_DISPLAY;
3569 args->caching = I915_CACHING_NONE;
3573 drm_gem_object_unreference(&obj->base);
3575 mutex_unlock(&dev->struct_mutex);
3579 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3580 struct drm_file *file)
3582 struct drm_i915_gem_caching *args = data;
3583 struct drm_i915_gem_object *obj;
3584 enum i915_cache_level level;
3587 switch (args->caching) {
3588 case I915_CACHING_NONE:
3589 level = I915_CACHE_NONE;
3591 case I915_CACHING_CACHED:
3592 level = I915_CACHE_LLC;
3594 case I915_CACHING_DISPLAY:
3595 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3601 ret = i915_mutex_lock_interruptible(dev);
3605 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3606 if (&obj->base == NULL) {
3611 ret = i915_gem_object_set_cache_level(obj, level);
3613 drm_gem_object_unreference(&obj->base);
3615 mutex_unlock(&dev->struct_mutex);
3619 static bool is_pin_display(struct drm_i915_gem_object *obj)
3621 /* There are 3 sources that pin objects:
3622 * 1. The display engine (scanouts, sprites, cursors);
3623 * 2. Reservations for execbuffer;
3626 * We can ignore reservations as we hold the struct_mutex and
3627 * are only called outside of the reservation path. The user
3628 * can only increment pin_count once, and so if after
3629 * subtracting the potential reference by the user, any pin_count
3630 * remains, it must be due to another use by the display engine.
3632 return i915_gem_obj_to_ggtt(obj)->pin_count - !!obj->user_pin_count;
3636 * Prepare buffer for display plane (scanout, cursors, etc).
3637 * Can be called from an uninterruptible phase (modesetting) and allows
3638 * any flushes to be pipelined (for pageflips).
3641 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3643 struct intel_ring_buffer *pipelined)
3645 u32 old_read_domains, old_write_domain;
3648 if (pipelined != obj->ring) {
3649 ret = i915_gem_object_sync(obj, pipelined);
3654 /* Mark the pin_display early so that we account for the
3655 * display coherency whilst setting up the cache domains.
3657 obj->pin_display = true;
3659 /* The display engine is not coherent with the LLC cache on gen6. As
3660 * a result, we make sure that the pinning that is about to occur is
3661 * done with uncached PTEs. This is lowest common denominator for all
3664 * However for gen6+, we could do better by using the GFDT bit instead
3665 * of uncaching, which would allow us to flush all the LLC-cached data
3666 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3668 ret = i915_gem_object_set_cache_level(obj,
3669 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3671 goto err_unpin_display;
3673 /* As the user may map the buffer once pinned in the display plane
3674 * (e.g. libkms for the bootup splash), we have to ensure that we
3675 * always use map_and_fenceable for all scanout buffers.
3677 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3679 goto err_unpin_display;
3681 i915_gem_object_flush_cpu_write_domain(obj, true);
3683 old_write_domain = obj->base.write_domain;
3684 old_read_domains = obj->base.read_domains;
3686 /* It should now be out of any other write domains, and we can update
3687 * the domain values for our changes.
3689 obj->base.write_domain = 0;
3690 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3692 trace_i915_gem_object_change_domain(obj,
3699 obj->pin_display = is_pin_display(obj);
3704 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3706 i915_gem_object_ggtt_unpin(obj);
3707 obj->pin_display = is_pin_display(obj);
3711 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3715 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3718 ret = i915_gem_object_wait_rendering(obj, false);
3722 /* Ensure that we invalidate the GPU's caches and TLBs. */
3723 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3728 * Moves a single object to the CPU read, and possibly write domain.
3730 * This function returns when the move is complete, including waiting on
3734 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3736 uint32_t old_write_domain, old_read_domains;
3739 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3742 ret = i915_gem_object_wait_rendering(obj, !write);
3746 i915_gem_object_flush_gtt_write_domain(obj);
3748 old_write_domain = obj->base.write_domain;
3749 old_read_domains = obj->base.read_domains;
3751 /* Flush the CPU cache if it's still invalid. */
3752 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3753 i915_gem_clflush_object(obj, false);
3755 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3758 /* It should now be out of any other write domains, and we can update
3759 * the domain values for our changes.
3761 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3763 /* If we're writing through the CPU, then the GPU read domains will
3764 * need to be invalidated at next use.
3767 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3768 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3771 trace_i915_gem_object_change_domain(obj,
3778 /* Throttle our rendering by waiting until the ring has completed our requests
3779 * emitted over 20 msec ago.
3781 * Note that if we were to use the current jiffies each time around the loop,
3782 * we wouldn't escape the function with any frames outstanding if the time to
3783 * render a frame was over 20ms.
3785 * This should get us reasonable parallelism between CPU and GPU but also
3786 * relatively low latency when blocking on a particular request to finish.
3789 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792 struct drm_i915_file_private *file_priv = file->driver_priv;
3793 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3794 struct drm_i915_gem_request *request;
3795 struct intel_ring_buffer *ring = NULL;
3796 unsigned reset_counter;
3800 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3804 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3808 spin_lock(&file_priv->mm.lock);
3809 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3810 if (time_after_eq(request->emitted_jiffies, recent_enough))
3813 ring = request->ring;
3814 seqno = request->seqno;
3816 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3817 spin_unlock(&file_priv->mm.lock);
3822 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
3824 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3830 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3831 struct i915_address_space *vm,
3833 bool map_and_fenceable,
3836 const u32 flags = map_and_fenceable ? GLOBAL_BIND : 0;
3837 struct i915_vma *vma;
3840 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3842 vma = i915_gem_obj_to_vma(obj, vm);
3845 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3849 vma->node.start & (alignment - 1)) ||
3850 (map_and_fenceable && !obj->map_and_fenceable)) {
3851 WARN(vma->pin_count,
3852 "bo is already pinned with incorrect alignment:"
3853 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3854 " obj->map_and_fenceable=%d\n",
3855 i915_gem_obj_offset(obj, vm), alignment,
3857 obj->map_and_fenceable);
3858 ret = i915_vma_unbind(vma);
3864 if (!i915_gem_obj_bound(obj, vm)) {
3865 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3873 vma = i915_gem_obj_to_vma(obj, vm);
3875 vma->bind_vma(vma, obj->cache_level, flags);
3877 i915_gem_obj_to_vma(obj, vm)->pin_count++;
3878 obj->pin_mappable |= map_and_fenceable;
3884 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3886 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3889 BUG_ON(vma->pin_count == 0);
3890 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
3892 if (--vma->pin_count == 0)
3893 obj->pin_mappable = false;
3897 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3898 struct drm_file *file)
3900 struct drm_i915_gem_pin *args = data;
3901 struct drm_i915_gem_object *obj;
3904 if (INTEL_INFO(dev)->gen >= 6)
3907 ret = i915_mutex_lock_interruptible(dev);
3911 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3912 if (&obj->base == NULL) {
3917 if (obj->madv != I915_MADV_WILLNEED) {
3918 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3923 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3924 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3930 if (obj->user_pin_count == ULONG_MAX) {
3935 if (obj->user_pin_count == 0) {
3936 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3941 obj->user_pin_count++;
3942 obj->pin_filp = file;
3944 args->offset = i915_gem_obj_ggtt_offset(obj);
3946 drm_gem_object_unreference(&obj->base);
3948 mutex_unlock(&dev->struct_mutex);
3953 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3954 struct drm_file *file)
3956 struct drm_i915_gem_pin *args = data;
3957 struct drm_i915_gem_object *obj;
3960 ret = i915_mutex_lock_interruptible(dev);
3964 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3965 if (&obj->base == NULL) {
3970 if (obj->pin_filp != file) {
3971 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3976 obj->user_pin_count--;
3977 if (obj->user_pin_count == 0) {
3978 obj->pin_filp = NULL;
3979 i915_gem_object_ggtt_unpin(obj);
3983 drm_gem_object_unreference(&obj->base);
3985 mutex_unlock(&dev->struct_mutex);
3990 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3991 struct drm_file *file)
3993 struct drm_i915_gem_busy *args = data;
3994 struct drm_i915_gem_object *obj;
3997 ret = i915_mutex_lock_interruptible(dev);
4001 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4002 if (&obj->base == NULL) {
4007 /* Count all active objects as busy, even if they are currently not used
4008 * by the gpu. Users of this interface expect objects to eventually
4009 * become non-busy without any further actions, therefore emit any
4010 * necessary flushes here.
4012 ret = i915_gem_object_flush_active(obj);
4014 args->busy = obj->active;
4016 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4017 args->busy |= intel_ring_flag(obj->ring) << 16;
4020 drm_gem_object_unreference(&obj->base);
4022 mutex_unlock(&dev->struct_mutex);
4027 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4028 struct drm_file *file_priv)
4030 return i915_gem_ring_throttle(dev, file_priv);
4034 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4035 struct drm_file *file_priv)
4037 struct drm_i915_gem_madvise *args = data;
4038 struct drm_i915_gem_object *obj;
4041 switch (args->madv) {
4042 case I915_MADV_DONTNEED:
4043 case I915_MADV_WILLNEED:
4049 ret = i915_mutex_lock_interruptible(dev);
4053 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4054 if (&obj->base == NULL) {
4059 if (i915_gem_obj_is_pinned(obj)) {
4064 if (obj->madv != __I915_MADV_PURGED)
4065 obj->madv = args->madv;
4067 /* if the object is no longer attached, discard its backing storage */
4068 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4069 i915_gem_object_truncate(obj);
4071 args->retained = obj->madv != __I915_MADV_PURGED;
4074 drm_gem_object_unreference(&obj->base);
4076 mutex_unlock(&dev->struct_mutex);
4080 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4081 const struct drm_i915_gem_object_ops *ops)
4083 INIT_LIST_HEAD(&obj->global_list);
4084 INIT_LIST_HEAD(&obj->ring_list);
4085 INIT_LIST_HEAD(&obj->obj_exec_link);
4086 INIT_LIST_HEAD(&obj->vma_list);
4090 obj->fence_reg = I915_FENCE_REG_NONE;
4091 obj->madv = I915_MADV_WILLNEED;
4092 /* Avoid an unnecessary call to unbind on the first bind. */
4093 obj->map_and_fenceable = true;
4095 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4098 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4099 .get_pages = i915_gem_object_get_pages_gtt,
4100 .put_pages = i915_gem_object_put_pages_gtt,
4103 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4106 struct drm_i915_gem_object *obj;
4107 struct address_space *mapping;
4110 obj = i915_gem_object_alloc(dev);
4114 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4115 i915_gem_object_free(obj);
4119 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4120 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4121 /* 965gm cannot relocate objects above 4GiB. */
4122 mask &= ~__GFP_HIGHMEM;
4123 mask |= __GFP_DMA32;
4126 mapping = file_inode(obj->base.filp)->i_mapping;
4127 mapping_set_gfp_mask(mapping, mask);
4129 i915_gem_object_init(obj, &i915_gem_object_ops);
4131 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4132 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4135 /* On some devices, we can have the GPU use the LLC (the CPU
4136 * cache) for about a 10% performance improvement
4137 * compared to uncached. Graphics requests other than
4138 * display scanout are coherent with the CPU in
4139 * accessing this cache. This means in this mode we
4140 * don't need to clflush on the CPU side, and on the
4141 * GPU side we only need to flush internal caches to
4142 * get data visible to the CPU.
4144 * However, we maintain the display planes as UC, and so
4145 * need to rebind when first used as such.
4147 obj->cache_level = I915_CACHE_LLC;
4149 obj->cache_level = I915_CACHE_NONE;
4151 trace_i915_gem_object_create(obj);
4156 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4158 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4159 struct drm_device *dev = obj->base.dev;
4160 drm_i915_private_t *dev_priv = dev->dev_private;
4161 struct i915_vma *vma, *next;
4163 intel_runtime_pm_get(dev_priv);
4165 trace_i915_gem_object_destroy(obj);
4168 i915_gem_detach_phys_object(dev, obj);
4170 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4174 ret = i915_vma_unbind(vma);
4175 if (WARN_ON(ret == -ERESTARTSYS)) {
4176 bool was_interruptible;
4178 was_interruptible = dev_priv->mm.interruptible;
4179 dev_priv->mm.interruptible = false;
4181 WARN_ON(i915_vma_unbind(vma));
4183 dev_priv->mm.interruptible = was_interruptible;
4187 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4188 * before progressing. */
4190 i915_gem_object_unpin_pages(obj);
4192 if (WARN_ON(obj->pages_pin_count))
4193 obj->pages_pin_count = 0;
4194 i915_gem_object_put_pages(obj);
4195 i915_gem_object_free_mmap_offset(obj);
4196 i915_gem_object_release_stolen(obj);
4200 if (obj->base.import_attach)
4201 drm_prime_gem_destroy(&obj->base, NULL);
4203 drm_gem_object_release(&obj->base);
4204 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4207 i915_gem_object_free(obj);
4209 intel_runtime_pm_put(dev_priv);
4212 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4213 struct i915_address_space *vm)
4215 struct i915_vma *vma;
4216 list_for_each_entry(vma, &obj->vma_list, vma_link)
4223 void i915_gem_vma_destroy(struct i915_vma *vma)
4225 WARN_ON(vma->node.allocated);
4227 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4228 if (!list_empty(&vma->exec_list))
4231 list_del(&vma->vma_link);
4237 i915_gem_suspend(struct drm_device *dev)
4239 drm_i915_private_t *dev_priv = dev->dev_private;
4242 mutex_lock(&dev->struct_mutex);
4243 if (dev_priv->ums.mm_suspended)
4246 ret = i915_gpu_idle(dev);
4250 i915_gem_retire_requests(dev);
4252 /* Under UMS, be paranoid and evict. */
4253 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4254 i915_gem_evict_everything(dev);
4256 i915_kernel_lost_context(dev);
4257 i915_gem_cleanup_ringbuffer(dev);
4259 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4260 * We need to replace this with a semaphore, or something.
4261 * And not confound ums.mm_suspended!
4263 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4265 mutex_unlock(&dev->struct_mutex);
4267 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4268 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4269 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4274 mutex_unlock(&dev->struct_mutex);
4278 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
4280 struct drm_device *dev = ring->dev;
4281 drm_i915_private_t *dev_priv = dev->dev_private;
4282 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4283 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4286 if (!HAS_L3_DPF(dev) || !remap_info)
4289 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4294 * Note: We do not worry about the concurrent register cacheline hang
4295 * here because no other code should access these registers other than
4296 * at initialization time.
4298 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4299 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4300 intel_ring_emit(ring, reg_base + i);
4301 intel_ring_emit(ring, remap_info[i/4]);
4304 intel_ring_advance(ring);
4309 void i915_gem_init_swizzling(struct drm_device *dev)
4311 drm_i915_private_t *dev_priv = dev->dev_private;
4313 if (INTEL_INFO(dev)->gen < 5 ||
4314 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4317 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4318 DISP_TILE_SURFACE_SWIZZLING);
4323 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4325 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4326 else if (IS_GEN7(dev))
4327 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4328 else if (IS_GEN8(dev))
4329 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4335 intel_enable_blt(struct drm_device *dev)
4340 /* The blitter was dysfunctional on early prototypes */
4341 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4342 DRM_INFO("BLT not supported on this pre-production hardware;"
4343 " graphics performance will be degraded.\n");
4350 static int i915_gem_init_rings(struct drm_device *dev)
4352 struct drm_i915_private *dev_priv = dev->dev_private;
4355 ret = intel_init_render_ring_buffer(dev);
4360 ret = intel_init_bsd_ring_buffer(dev);
4362 goto cleanup_render_ring;
4365 if (intel_enable_blt(dev)) {
4366 ret = intel_init_blt_ring_buffer(dev);
4368 goto cleanup_bsd_ring;
4371 if (HAS_VEBOX(dev)) {
4372 ret = intel_init_vebox_ring_buffer(dev);
4374 goto cleanup_blt_ring;
4378 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4380 goto cleanup_vebox_ring;
4385 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4387 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4389 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4390 cleanup_render_ring:
4391 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4397 i915_gem_init_hw(struct drm_device *dev)
4399 drm_i915_private_t *dev_priv = dev->dev_private;
4402 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4405 if (dev_priv->ellc_size)
4406 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4408 if (IS_HASWELL(dev))
4409 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4410 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4412 if (HAS_PCH_NOP(dev)) {
4413 if (IS_IVYBRIDGE(dev)) {
4414 u32 temp = I915_READ(GEN7_MSG_CTL);
4415 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4416 I915_WRITE(GEN7_MSG_CTL, temp);
4417 } else if (INTEL_INFO(dev)->gen >= 7) {
4418 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4419 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4420 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4424 i915_gem_init_swizzling(dev);
4426 ret = i915_gem_init_rings(dev);
4430 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4431 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4434 * XXX: Contexts should only be initialized once. Doing a switch to the
4435 * default context switch however is something we'd like to do after
4436 * reset or thaw (the latter may not actually be necessary for HW, but
4437 * goes with our code better). Context switching requires rings (for
4438 * the do_switch), but before enabling PPGTT. So don't move this.
4440 ret = i915_gem_context_enable(dev_priv);
4442 DRM_ERROR("Context enable failed %d\n", ret);
4449 i915_gem_cleanup_ringbuffer(dev);
4453 int i915_gem_init(struct drm_device *dev)
4455 struct drm_i915_private *dev_priv = dev->dev_private;
4458 mutex_lock(&dev->struct_mutex);
4460 if (IS_VALLEYVIEW(dev)) {
4461 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4462 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4463 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4464 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4467 i915_gem_init_global_gtt(dev);
4469 ret = i915_gem_context_init(dev);
4473 ret = i915_gem_init_hw(dev);
4474 mutex_unlock(&dev->struct_mutex);
4476 WARN_ON(dev_priv->mm.aliasing_ppgtt);
4477 i915_gem_context_fini(dev);
4478 drm_mm_takedown(&dev_priv->gtt.base.mm);
4482 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4483 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4484 dev_priv->dri1.allow_batchbuffer = 1;
4489 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4491 drm_i915_private_t *dev_priv = dev->dev_private;
4492 struct intel_ring_buffer *ring;
4495 for_each_ring(ring, dev_priv, i)
4496 intel_cleanup_ring_buffer(ring);
4500 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4501 struct drm_file *file_priv)
4503 struct drm_i915_private *dev_priv = dev->dev_private;
4506 if (drm_core_check_feature(dev, DRIVER_MODESET))
4509 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4510 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4511 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4514 mutex_lock(&dev->struct_mutex);
4515 dev_priv->ums.mm_suspended = 0;
4517 ret = i915_gem_init_hw(dev);
4519 mutex_unlock(&dev->struct_mutex);
4523 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4524 mutex_unlock(&dev->struct_mutex);
4526 ret = drm_irq_install(dev);
4528 goto cleanup_ringbuffer;
4533 mutex_lock(&dev->struct_mutex);
4534 i915_gem_cleanup_ringbuffer(dev);
4535 dev_priv->ums.mm_suspended = 1;
4536 mutex_unlock(&dev->struct_mutex);
4542 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4543 struct drm_file *file_priv)
4545 if (drm_core_check_feature(dev, DRIVER_MODESET))
4548 drm_irq_uninstall(dev);
4550 return i915_gem_suspend(dev);
4554 i915_gem_lastclose(struct drm_device *dev)
4558 if (drm_core_check_feature(dev, DRIVER_MODESET))
4561 ret = i915_gem_suspend(dev);
4563 DRM_ERROR("failed to idle hardware: %d\n", ret);
4567 init_ring_lists(struct intel_ring_buffer *ring)
4569 INIT_LIST_HEAD(&ring->active_list);
4570 INIT_LIST_HEAD(&ring->request_list);
4573 void i915_init_vm(struct drm_i915_private *dev_priv,
4574 struct i915_address_space *vm)
4576 if (!i915_is_ggtt(vm))
4577 drm_mm_init(&vm->mm, vm->start, vm->total);
4578 vm->dev = dev_priv->dev;
4579 INIT_LIST_HEAD(&vm->active_list);
4580 INIT_LIST_HEAD(&vm->inactive_list);
4581 INIT_LIST_HEAD(&vm->global_link);
4582 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4586 i915_gem_load(struct drm_device *dev)
4588 drm_i915_private_t *dev_priv = dev->dev_private;
4592 kmem_cache_create("i915_gem_object",
4593 sizeof(struct drm_i915_gem_object), 0,
4597 INIT_LIST_HEAD(&dev_priv->vm_list);
4598 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4600 INIT_LIST_HEAD(&dev_priv->context_list);
4601 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4602 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4603 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4604 for (i = 0; i < I915_NUM_RINGS; i++)
4605 init_ring_lists(&dev_priv->ring[i]);
4606 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4607 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4608 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4609 i915_gem_retire_work_handler);
4610 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4611 i915_gem_idle_work_handler);
4612 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4614 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4616 I915_WRITE(MI_ARB_STATE,
4617 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4620 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4622 /* Old X drivers will take 0-2 for front, back, depth buffers */
4623 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4624 dev_priv->fence_reg_start = 3;
4626 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4627 dev_priv->num_fence_regs = 32;
4628 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4629 dev_priv->num_fence_regs = 16;
4631 dev_priv->num_fence_regs = 8;
4633 /* Initialize fence registers to zero */
4634 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4635 i915_gem_restore_fences(dev);
4637 i915_gem_detect_bit_6_swizzle(dev);
4638 init_waitqueue_head(&dev_priv->pending_flip_queue);
4640 dev_priv->mm.interruptible = true;
4642 dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan;
4643 dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count;
4644 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4645 register_shrinker(&dev_priv->mm.inactive_shrinker);
4649 * Create a physically contiguous memory object for this object
4650 * e.g. for cursor + overlay regs
4652 static int i915_gem_init_phys_object(struct drm_device *dev,
4653 int id, int size, int align)
4655 drm_i915_private_t *dev_priv = dev->dev_private;
4656 struct drm_i915_gem_phys_object *phys_obj;
4659 if (dev_priv->mm.phys_objs[id - 1] || !size)
4662 phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL);
4668 phys_obj->handle = drm_pci_alloc(dev, size, align);
4669 if (!phys_obj->handle) {
4674 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4677 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4685 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4687 drm_i915_private_t *dev_priv = dev->dev_private;
4688 struct drm_i915_gem_phys_object *phys_obj;
4690 if (!dev_priv->mm.phys_objs[id - 1])
4693 phys_obj = dev_priv->mm.phys_objs[id - 1];
4694 if (phys_obj->cur_obj) {
4695 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4699 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4701 drm_pci_free(dev, phys_obj->handle);
4703 dev_priv->mm.phys_objs[id - 1] = NULL;
4706 void i915_gem_free_all_phys_object(struct drm_device *dev)
4710 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4711 i915_gem_free_phys_object(dev, i);
4714 void i915_gem_detach_phys_object(struct drm_device *dev,
4715 struct drm_i915_gem_object *obj)
4717 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4724 vaddr = obj->phys_obj->handle->vaddr;
4726 page_count = obj->base.size / PAGE_SIZE;
4727 for (i = 0; i < page_count; i++) {
4728 struct page *page = shmem_read_mapping_page(mapping, i);
4729 if (!IS_ERR(page)) {
4730 char *dst = kmap_atomic(page);
4731 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4734 drm_clflush_pages(&page, 1);
4736 set_page_dirty(page);
4737 mark_page_accessed(page);
4738 page_cache_release(page);
4741 i915_gem_chipset_flush(dev);
4743 obj->phys_obj->cur_obj = NULL;
4744 obj->phys_obj = NULL;
4748 i915_gem_attach_phys_object(struct drm_device *dev,
4749 struct drm_i915_gem_object *obj,
4753 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4754 drm_i915_private_t *dev_priv = dev->dev_private;
4759 if (id > I915_MAX_PHYS_OBJECT)
4762 if (obj->phys_obj) {
4763 if (obj->phys_obj->id == id)
4765 i915_gem_detach_phys_object(dev, obj);
4768 /* create a new object */
4769 if (!dev_priv->mm.phys_objs[id - 1]) {
4770 ret = i915_gem_init_phys_object(dev, id,
4771 obj->base.size, align);
4773 DRM_ERROR("failed to init phys object %d size: %zu\n",
4774 id, obj->base.size);
4779 /* bind to the object */
4780 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4781 obj->phys_obj->cur_obj = obj;
4783 page_count = obj->base.size / PAGE_SIZE;
4785 for (i = 0; i < page_count; i++) {
4789 page = shmem_read_mapping_page(mapping, i);
4791 return PTR_ERR(page);
4793 src = kmap_atomic(page);
4794 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4795 memcpy(dst, src, PAGE_SIZE);
4798 mark_page_accessed(page);
4799 page_cache_release(page);
4806 i915_gem_phys_pwrite(struct drm_device *dev,
4807 struct drm_i915_gem_object *obj,
4808 struct drm_i915_gem_pwrite *args,
4809 struct drm_file *file_priv)
4811 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4812 char __user *user_data = to_user_ptr(args->data_ptr);
4814 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4815 unsigned long unwritten;
4817 /* The physical object once assigned is fixed for the lifetime
4818 * of the obj, so we can safely drop the lock and continue
4821 mutex_unlock(&dev->struct_mutex);
4822 unwritten = copy_from_user(vaddr, user_data, args->size);
4823 mutex_lock(&dev->struct_mutex);
4828 i915_gem_chipset_flush(dev);
4832 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4834 struct drm_i915_file_private *file_priv = file->driver_priv;
4836 cancel_delayed_work_sync(&file_priv->mm.idle_work);
4838 /* Clean up our request list when the client is going away, so that
4839 * later retire_requests won't dereference our soon-to-be-gone
4842 spin_lock(&file_priv->mm.lock);
4843 while (!list_empty(&file_priv->mm.request_list)) {
4844 struct drm_i915_gem_request *request;
4846 request = list_first_entry(&file_priv->mm.request_list,
4847 struct drm_i915_gem_request,
4849 list_del(&request->client_list);
4850 request->file_priv = NULL;
4852 spin_unlock(&file_priv->mm.lock);
4856 i915_gem_file_idle_work_handler(struct work_struct *work)
4858 struct drm_i915_file_private *file_priv =
4859 container_of(work, typeof(*file_priv), mm.idle_work.work);
4861 atomic_set(&file_priv->rps_wait_boost, false);
4864 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4866 struct drm_i915_file_private *file_priv;
4869 DRM_DEBUG_DRIVER("\n");
4871 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4875 file->driver_priv = file_priv;
4876 file_priv->dev_priv = dev->dev_private;
4878 spin_lock_init(&file_priv->mm.lock);
4879 INIT_LIST_HEAD(&file_priv->mm.request_list);
4880 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4881 i915_gem_file_idle_work_handler);
4883 ret = i915_gem_context_open(dev, file);
4890 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4892 if (!mutex_is_locked(mutex))
4895 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4896 return mutex->owner == task;
4898 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4903 static unsigned long
4904 i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc)
4906 struct drm_i915_private *dev_priv =
4907 container_of(shrinker,
4908 struct drm_i915_private,
4909 mm.inactive_shrinker);
4910 struct drm_device *dev = dev_priv->dev;
4911 struct drm_i915_gem_object *obj;
4913 unsigned long count;
4915 if (!mutex_trylock(&dev->struct_mutex)) {
4916 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4919 if (dev_priv->mm.shrinker_no_lock_stealing)
4926 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4927 if (obj->pages_pin_count == 0)
4928 count += obj->base.size >> PAGE_SHIFT;
4930 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4934 if (!i915_gem_obj_is_pinned(obj) && obj->pages_pin_count == 0)
4935 count += obj->base.size >> PAGE_SHIFT;
4939 mutex_unlock(&dev->struct_mutex);
4944 /* All the new VM stuff */
4945 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4946 struct i915_address_space *vm)
4948 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4949 struct i915_vma *vma;
4951 if (!dev_priv->mm.aliasing_ppgtt ||
4952 vm == &dev_priv->mm.aliasing_ppgtt->base)
4953 vm = &dev_priv->gtt.base;
4955 BUG_ON(list_empty(&o->vma_list));
4956 list_for_each_entry(vma, &o->vma_list, vma_link) {
4958 return vma->node.start;
4964 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
4965 struct i915_address_space *vm)
4967 struct i915_vma *vma;
4969 list_for_each_entry(vma, &o->vma_list, vma_link)
4970 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
4976 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
4978 struct i915_vma *vma;
4980 list_for_each_entry(vma, &o->vma_list, vma_link)
4981 if (drm_mm_node_allocated(&vma->node))
4987 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
4988 struct i915_address_space *vm)
4990 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4991 struct i915_vma *vma;
4993 if (!dev_priv->mm.aliasing_ppgtt ||
4994 vm == &dev_priv->mm.aliasing_ppgtt->base)
4995 vm = &dev_priv->gtt.base;
4997 BUG_ON(list_empty(&o->vma_list));
4999 list_for_each_entry(vma, &o->vma_list, vma_link)
5001 return vma->node.size;
5006 static unsigned long
5007 i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc)
5009 struct drm_i915_private *dev_priv =
5010 container_of(shrinker,
5011 struct drm_i915_private,
5012 mm.inactive_shrinker);
5013 struct drm_device *dev = dev_priv->dev;
5014 unsigned long freed;
5017 if (!mutex_trylock(&dev->struct_mutex)) {
5018 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5021 if (dev_priv->mm.shrinker_no_lock_stealing)
5027 freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5028 if (freed < sc->nr_to_scan)
5029 freed += __i915_gem_shrink(dev_priv,
5030 sc->nr_to_scan - freed,
5032 if (freed < sc->nr_to_scan)
5033 freed += i915_gem_shrink_all(dev_priv);
5036 mutex_unlock(&dev->struct_mutex);
5041 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5043 struct i915_vma *vma;
5045 if (WARN_ON(list_empty(&obj->vma_list)))
5048 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5049 if (vma->vm != obj_to_ggtt(obj))