2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
44 static __must_check int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
59 struct shrink_control *sc);
60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
63 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
64 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
66 static bool cpu_cache_is_coherent(struct drm_device *dev,
67 enum i915_cache_level level)
69 return HAS_LLC(dev) || level != I915_CACHE_NONE;
72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
74 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
77 return obj->pin_display;
80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
83 i915_gem_release_mmap(obj);
85 /* As we do not have an associated fence register, we will force
86 * a tiling change if we ever need to acquire one.
88 obj->fence_dirty = false;
89 obj->fence_reg = I915_FENCE_REG_NONE;
92 /* some bookkeeping */
93 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
96 spin_lock(&dev_priv->mm.object_stat_lock);
97 dev_priv->mm.object_count++;
98 dev_priv->mm.object_memory += size;
99 spin_unlock(&dev_priv->mm.object_stat_lock);
102 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
105 spin_lock(&dev_priv->mm.object_stat_lock);
106 dev_priv->mm.object_count--;
107 dev_priv->mm.object_memory -= size;
108 spin_unlock(&dev_priv->mm.object_stat_lock);
112 i915_gem_wait_for_error(struct i915_gpu_error *error)
116 #define EXIT_COND (!i915_reset_in_progress(error) || \
117 i915_terminally_wedged(error))
122 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
123 * userspace. If it takes that long something really bad is going on and
124 * we should simply try to bail out and fail as gracefully as possible.
126 ret = wait_event_interruptible_timeout(error->reset_queue,
130 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
132 } else if (ret < 0) {
140 int i915_mutex_lock_interruptible(struct drm_device *dev)
142 struct drm_i915_private *dev_priv = dev->dev_private;
145 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
149 ret = mutex_lock_interruptible(&dev->struct_mutex);
153 WARN_ON(i915_verify_lists(dev));
158 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
160 return i915_gem_obj_bound_any(obj) && !obj->active;
164 i915_gem_init_ioctl(struct drm_device *dev, void *data,
165 struct drm_file *file)
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 struct drm_i915_gem_init *args = data;
170 if (drm_core_check_feature(dev, DRIVER_MODESET))
173 if (args->gtt_start >= args->gtt_end ||
174 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
177 /* GEM with user mode setting was never supported on ilk and later. */
178 if (INTEL_INFO(dev)->gen >= 5)
181 mutex_lock(&dev->struct_mutex);
182 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
184 dev_priv->gtt.mappable_end = args->gtt_end;
185 mutex_unlock(&dev->struct_mutex);
191 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
192 struct drm_file *file)
194 struct drm_i915_private *dev_priv = dev->dev_private;
195 struct drm_i915_gem_get_aperture *args = data;
196 struct drm_i915_gem_object *obj;
200 mutex_lock(&dev->struct_mutex);
201 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
202 if (i915_gem_obj_is_pinned(obj))
203 pinned += i915_gem_obj_ggtt_size(obj);
204 mutex_unlock(&dev->struct_mutex);
206 args->aper_size = dev_priv->gtt.base.total;
207 args->aper_available_size = args->aper_size - pinned;
212 static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
214 drm_dma_handle_t *phys = obj->phys_handle;
219 if (obj->madv == I915_MADV_WILLNEED) {
220 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
221 char *vaddr = phys->vaddr;
224 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
225 struct page *page = shmem_read_mapping_page(mapping, i);
227 char *dst = kmap_atomic(page);
228 memcpy(dst, vaddr, PAGE_SIZE);
229 drm_clflush_virt_range(dst, PAGE_SIZE);
232 set_page_dirty(page);
233 mark_page_accessed(page);
234 page_cache_release(page);
238 i915_gem_chipset_flush(obj->base.dev);
242 set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
244 drm_pci_free(obj->base.dev, phys);
245 obj->phys_handle = NULL;
249 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
252 drm_dma_handle_t *phys;
253 struct address_space *mapping;
257 if (obj->phys_handle) {
258 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
264 if (obj->madv != I915_MADV_WILLNEED)
267 if (obj->base.filp == NULL)
270 /* create a new object */
271 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
277 set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
279 mapping = file_inode(obj->base.filp)->i_mapping;
280 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
284 page = shmem_read_mapping_page(mapping, i);
287 set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
289 drm_pci_free(obj->base.dev, phys);
290 return PTR_ERR(page);
293 src = kmap_atomic(page);
294 memcpy(vaddr, src, PAGE_SIZE);
297 mark_page_accessed(page);
298 page_cache_release(page);
303 obj->phys_handle = phys;
308 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
309 struct drm_i915_gem_pwrite *args,
310 struct drm_file *file_priv)
312 struct drm_device *dev = obj->base.dev;
313 void *vaddr = obj->phys_handle->vaddr + args->offset;
314 char __user *user_data = to_user_ptr(args->data_ptr);
316 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
317 unsigned long unwritten;
319 /* The physical object once assigned is fixed for the lifetime
320 * of the obj, so we can safely drop the lock and continue
323 mutex_unlock(&dev->struct_mutex);
324 unwritten = copy_from_user(vaddr, user_data, args->size);
325 mutex_lock(&dev->struct_mutex);
330 i915_gem_chipset_flush(dev);
334 void *i915_gem_object_alloc(struct drm_device *dev)
336 struct drm_i915_private *dev_priv = dev->dev_private;
337 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
340 void i915_gem_object_free(struct drm_i915_gem_object *obj)
342 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
343 kmem_cache_free(dev_priv->slab, obj);
347 i915_gem_create(struct drm_file *file,
348 struct drm_device *dev,
352 struct drm_i915_gem_object *obj;
356 size = roundup(size, PAGE_SIZE);
360 /* Allocate the new object */
361 obj = i915_gem_alloc_object(dev, size);
365 ret = drm_gem_handle_create(file, &obj->base, &handle);
366 /* drop reference from allocate - handle holds it now */
367 drm_gem_object_unreference_unlocked(&obj->base);
376 i915_gem_dumb_create(struct drm_file *file,
377 struct drm_device *dev,
378 struct drm_mode_create_dumb *args)
380 /* have to work out size/pitch and return them */
381 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
382 args->size = args->pitch * args->height;
383 return i915_gem_create(file, dev,
384 args->size, &args->handle);
388 * Creates a new mm object and returns a handle to it.
391 i915_gem_create_ioctl(struct drm_device *dev, void *data,
392 struct drm_file *file)
394 struct drm_i915_gem_create *args = data;
396 return i915_gem_create(file, dev,
397 args->size, &args->handle);
401 __copy_to_user_swizzled(char __user *cpu_vaddr,
402 const char *gpu_vaddr, int gpu_offset,
405 int ret, cpu_offset = 0;
408 int cacheline_end = ALIGN(gpu_offset + 1, 64);
409 int this_length = min(cacheline_end - gpu_offset, length);
410 int swizzled_gpu_offset = gpu_offset ^ 64;
412 ret = __copy_to_user(cpu_vaddr + cpu_offset,
413 gpu_vaddr + swizzled_gpu_offset,
418 cpu_offset += this_length;
419 gpu_offset += this_length;
420 length -= this_length;
427 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
428 const char __user *cpu_vaddr,
431 int ret, cpu_offset = 0;
434 int cacheline_end = ALIGN(gpu_offset + 1, 64);
435 int this_length = min(cacheline_end - gpu_offset, length);
436 int swizzled_gpu_offset = gpu_offset ^ 64;
438 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
439 cpu_vaddr + cpu_offset,
444 cpu_offset += this_length;
445 gpu_offset += this_length;
446 length -= this_length;
453 * Pins the specified object's pages and synchronizes the object with
454 * GPU accesses. Sets needs_clflush to non-zero if the caller should
455 * flush the object from the CPU cache.
457 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
467 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
468 /* If we're not in the cpu read domain, set ourself into the gtt
469 * read domain and manually flush cachelines (if required). This
470 * optimizes for the case when the gpu will dirty the data
471 * anyway again before the next pread happens. */
472 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
474 ret = i915_gem_object_wait_rendering(obj, true);
478 i915_gem_object_retire(obj);
481 ret = i915_gem_object_get_pages(obj);
485 i915_gem_object_pin_pages(obj);
490 /* Per-page copy function for the shmem pread fastpath.
491 * Flushes invalid cachelines before reading the target if
492 * needs_clflush is set. */
494 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
495 char __user *user_data,
496 bool page_do_bit17_swizzling, bool needs_clflush)
501 if (unlikely(page_do_bit17_swizzling))
504 vaddr = kmap_atomic(page);
506 drm_clflush_virt_range(vaddr + shmem_page_offset,
508 ret = __copy_to_user_inatomic(user_data,
509 vaddr + shmem_page_offset,
511 kunmap_atomic(vaddr);
513 return ret ? -EFAULT : 0;
517 shmem_clflush_swizzled_range(char *addr, unsigned long length,
520 if (unlikely(swizzled)) {
521 unsigned long start = (unsigned long) addr;
522 unsigned long end = (unsigned long) addr + length;
524 /* For swizzling simply ensure that we always flush both
525 * channels. Lame, but simple and it works. Swizzled
526 * pwrite/pread is far from a hotpath - current userspace
527 * doesn't use it at all. */
528 start = round_down(start, 128);
529 end = round_up(end, 128);
531 drm_clflush_virt_range((void *)start, end - start);
533 drm_clflush_virt_range(addr, length);
538 /* Only difference to the fast-path function is that this can handle bit17
539 * and uses non-atomic copy and kmap functions. */
541 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
542 char __user *user_data,
543 bool page_do_bit17_swizzling, bool needs_clflush)
550 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
552 page_do_bit17_swizzling);
554 if (page_do_bit17_swizzling)
555 ret = __copy_to_user_swizzled(user_data,
556 vaddr, shmem_page_offset,
559 ret = __copy_to_user(user_data,
560 vaddr + shmem_page_offset,
564 return ret ? - EFAULT : 0;
568 i915_gem_shmem_pread(struct drm_device *dev,
569 struct drm_i915_gem_object *obj,
570 struct drm_i915_gem_pread *args,
571 struct drm_file *file)
573 char __user *user_data;
576 int shmem_page_offset, page_length, ret = 0;
577 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
579 int needs_clflush = 0;
580 struct sg_page_iter sg_iter;
582 user_data = to_user_ptr(args->data_ptr);
585 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
587 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
591 offset = args->offset;
593 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
594 offset >> PAGE_SHIFT) {
595 struct page *page = sg_page_iter_page(&sg_iter);
600 /* Operation in this page
602 * shmem_page_offset = offset within page in shmem file
603 * page_length = bytes to copy for this page
605 shmem_page_offset = offset_in_page(offset);
606 page_length = remain;
607 if ((shmem_page_offset + page_length) > PAGE_SIZE)
608 page_length = PAGE_SIZE - shmem_page_offset;
610 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
611 (page_to_phys(page) & (1 << 17)) != 0;
613 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
614 user_data, page_do_bit17_swizzling,
619 mutex_unlock(&dev->struct_mutex);
621 if (likely(!i915.prefault_disable) && !prefaulted) {
622 ret = fault_in_multipages_writeable(user_data, remain);
623 /* Userspace is tricking us, but we've already clobbered
624 * its pages with the prefault and promised to write the
625 * data up to the first fault. Hence ignore any errors
626 * and just continue. */
631 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
632 user_data, page_do_bit17_swizzling,
635 mutex_lock(&dev->struct_mutex);
641 remain -= page_length;
642 user_data += page_length;
643 offset += page_length;
647 i915_gem_object_unpin_pages(obj);
653 * Reads data from the object referenced by handle.
655 * On error, the contents of *data are undefined.
658 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
659 struct drm_file *file)
661 struct drm_i915_gem_pread *args = data;
662 struct drm_i915_gem_object *obj;
668 if (!access_ok(VERIFY_WRITE,
669 to_user_ptr(args->data_ptr),
673 ret = i915_mutex_lock_interruptible(dev);
677 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
678 if (&obj->base == NULL) {
683 /* Bounds check source. */
684 if (args->offset > obj->base.size ||
685 args->size > obj->base.size - args->offset) {
690 /* prime objects have no backing filp to GEM pread/pwrite
693 if (!obj->base.filp) {
698 trace_i915_gem_object_pread(obj, args->offset, args->size);
700 ret = i915_gem_shmem_pread(dev, obj, args, file);
703 drm_gem_object_unreference(&obj->base);
705 mutex_unlock(&dev->struct_mutex);
709 /* This is the fast write path which cannot handle
710 * page faults in the source data
714 fast_user_write(struct io_mapping *mapping,
715 loff_t page_base, int page_offset,
716 char __user *user_data,
719 void __iomem *vaddr_atomic;
721 unsigned long unwritten;
723 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
724 /* We can use the cpu mem copy function because this is X86. */
725 vaddr = (void __force*)vaddr_atomic + page_offset;
726 unwritten = __copy_from_user_inatomic_nocache(vaddr,
728 io_mapping_unmap_atomic(vaddr_atomic);
733 * This is the fast pwrite path, where we copy the data directly from the
734 * user into the GTT, uncached.
737 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
738 struct drm_i915_gem_object *obj,
739 struct drm_i915_gem_pwrite *args,
740 struct drm_file *file)
742 struct drm_i915_private *dev_priv = dev->dev_private;
744 loff_t offset, page_base;
745 char __user *user_data;
746 int page_offset, page_length, ret;
748 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
752 ret = i915_gem_object_set_to_gtt_domain(obj, true);
756 ret = i915_gem_object_put_fence(obj);
760 user_data = to_user_ptr(args->data_ptr);
763 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
766 /* Operation in this page
768 * page_base = page offset within aperture
769 * page_offset = offset within page
770 * page_length = bytes to copy for this page
772 page_base = offset & PAGE_MASK;
773 page_offset = offset_in_page(offset);
774 page_length = remain;
775 if ((page_offset + remain) > PAGE_SIZE)
776 page_length = PAGE_SIZE - page_offset;
778 /* If we get a fault while copying data, then (presumably) our
779 * source page isn't available. Return the error and we'll
780 * retry in the slow path.
782 if (fast_user_write(dev_priv->gtt.mappable, page_base,
783 page_offset, user_data, page_length)) {
788 remain -= page_length;
789 user_data += page_length;
790 offset += page_length;
794 i915_gem_object_ggtt_unpin(obj);
799 /* Per-page copy function for the shmem pwrite fastpath.
800 * Flushes invalid cachelines before writing to the target if
801 * needs_clflush_before is set and flushes out any written cachelines after
802 * writing if needs_clflush is set. */
804 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
805 char __user *user_data,
806 bool page_do_bit17_swizzling,
807 bool needs_clflush_before,
808 bool needs_clflush_after)
813 if (unlikely(page_do_bit17_swizzling))
816 vaddr = kmap_atomic(page);
817 if (needs_clflush_before)
818 drm_clflush_virt_range(vaddr + shmem_page_offset,
820 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
821 user_data, page_length);
822 if (needs_clflush_after)
823 drm_clflush_virt_range(vaddr + shmem_page_offset,
825 kunmap_atomic(vaddr);
827 return ret ? -EFAULT : 0;
830 /* Only difference to the fast-path function is that this can handle bit17
831 * and uses non-atomic copy and kmap functions. */
833 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
834 char __user *user_data,
835 bool page_do_bit17_swizzling,
836 bool needs_clflush_before,
837 bool needs_clflush_after)
843 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
844 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
846 page_do_bit17_swizzling);
847 if (page_do_bit17_swizzling)
848 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
852 ret = __copy_from_user(vaddr + shmem_page_offset,
855 if (needs_clflush_after)
856 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
858 page_do_bit17_swizzling);
861 return ret ? -EFAULT : 0;
865 i915_gem_shmem_pwrite(struct drm_device *dev,
866 struct drm_i915_gem_object *obj,
867 struct drm_i915_gem_pwrite *args,
868 struct drm_file *file)
872 char __user *user_data;
873 int shmem_page_offset, page_length, ret = 0;
874 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
875 int hit_slowpath = 0;
876 int needs_clflush_after = 0;
877 int needs_clflush_before = 0;
878 struct sg_page_iter sg_iter;
880 user_data = to_user_ptr(args->data_ptr);
883 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
885 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
886 /* If we're not in the cpu write domain, set ourself into the gtt
887 * write domain and manually flush cachelines (if required). This
888 * optimizes for the case when the gpu will use the data
889 * right away and we therefore have to clflush anyway. */
890 needs_clflush_after = cpu_write_needs_clflush(obj);
891 ret = i915_gem_object_wait_rendering(obj, false);
895 i915_gem_object_retire(obj);
897 /* Same trick applies to invalidate partially written cachelines read
899 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
900 needs_clflush_before =
901 !cpu_cache_is_coherent(dev, obj->cache_level);
903 ret = i915_gem_object_get_pages(obj);
907 i915_gem_object_pin_pages(obj);
909 offset = args->offset;
912 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
913 offset >> PAGE_SHIFT) {
914 struct page *page = sg_page_iter_page(&sg_iter);
915 int partial_cacheline_write;
920 /* Operation in this page
922 * shmem_page_offset = offset within page in shmem file
923 * page_length = bytes to copy for this page
925 shmem_page_offset = offset_in_page(offset);
927 page_length = remain;
928 if ((shmem_page_offset + page_length) > PAGE_SIZE)
929 page_length = PAGE_SIZE - shmem_page_offset;
931 /* If we don't overwrite a cacheline completely we need to be
932 * careful to have up-to-date data by first clflushing. Don't
933 * overcomplicate things and flush the entire patch. */
934 partial_cacheline_write = needs_clflush_before &&
935 ((shmem_page_offset | page_length)
936 & (boot_cpu_data.x86_clflush_size - 1));
938 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
939 (page_to_phys(page) & (1 << 17)) != 0;
941 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
942 user_data, page_do_bit17_swizzling,
943 partial_cacheline_write,
944 needs_clflush_after);
949 mutex_unlock(&dev->struct_mutex);
950 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
951 user_data, page_do_bit17_swizzling,
952 partial_cacheline_write,
953 needs_clflush_after);
955 mutex_lock(&dev->struct_mutex);
961 remain -= page_length;
962 user_data += page_length;
963 offset += page_length;
967 i915_gem_object_unpin_pages(obj);
971 * Fixup: Flush cpu caches in case we didn't flush the dirty
972 * cachelines in-line while writing and the object moved
973 * out of the cpu write domain while we've dropped the lock.
975 if (!needs_clflush_after &&
976 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
977 if (i915_gem_clflush_object(obj, obj->pin_display))
978 i915_gem_chipset_flush(dev);
982 if (needs_clflush_after)
983 i915_gem_chipset_flush(dev);
989 * Writes data to the object referenced by handle.
991 * On error, the contents of the buffer that were to be modified are undefined.
994 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
995 struct drm_file *file)
997 struct drm_i915_gem_pwrite *args = data;
998 struct drm_i915_gem_object *obj;
1001 if (args->size == 0)
1004 if (!access_ok(VERIFY_READ,
1005 to_user_ptr(args->data_ptr),
1009 if (likely(!i915.prefault_disable)) {
1010 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1016 ret = i915_mutex_lock_interruptible(dev);
1020 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1021 if (&obj->base == NULL) {
1026 /* Bounds check destination. */
1027 if (args->offset > obj->base.size ||
1028 args->size > obj->base.size - args->offset) {
1033 /* prime objects have no backing filp to GEM pread/pwrite
1036 if (!obj->base.filp) {
1041 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1044 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1045 * it would end up going through the fenced access, and we'll get
1046 * different detiling behavior between reading and writing.
1047 * pread/pwrite currently are reading and writing from the CPU
1048 * perspective, requiring manual detiling by the client.
1050 if (obj->phys_handle) {
1051 ret = i915_gem_phys_pwrite(obj, args, file);
1055 if (obj->tiling_mode == I915_TILING_NONE &&
1056 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1057 cpu_write_needs_clflush(obj)) {
1058 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1059 /* Note that the gtt paths might fail with non-page-backed user
1060 * pointers (e.g. gtt mappings when moving data between
1061 * textures). Fallback to the shmem path in that case. */
1064 if (ret == -EFAULT || ret == -ENOSPC)
1065 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1068 drm_gem_object_unreference(&obj->base);
1070 mutex_unlock(&dev->struct_mutex);
1075 i915_gem_check_wedge(struct i915_gpu_error *error,
1078 if (i915_reset_in_progress(error)) {
1079 /* Non-interruptible callers can't handle -EAGAIN, hence return
1080 * -EIO unconditionally for these. */
1084 /* Recovery complete, but the reset failed ... */
1085 if (i915_terminally_wedged(error))
1095 * Compare seqno against outstanding lazy request. Emit a request if they are
1099 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1103 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1106 if (seqno == ring->outstanding_lazy_seqno)
1107 ret = i915_add_request(ring, NULL);
1112 static void fake_irq(unsigned long data)
1114 wake_up_process((struct task_struct *)data);
1117 static bool missed_irq(struct drm_i915_private *dev_priv,
1118 struct intel_engine_cs *ring)
1120 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1123 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1125 if (file_priv == NULL)
1128 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1132 * __wait_seqno - wait until execution of seqno has finished
1133 * @ring: the ring expected to report seqno
1135 * @reset_counter: reset sequence associated with the given seqno
1136 * @interruptible: do an interruptible wait (normally yes)
1137 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1139 * Note: It is of utmost importance that the passed in seqno and reset_counter
1140 * values have been read by the caller in an smp safe manner. Where read-side
1141 * locks are involved, it is sufficient to read the reset_counter before
1142 * unlocking the lock that protects the seqno. For lockless tricks, the
1143 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1146 * Returns 0 if the seqno was found within the alloted time. Else returns the
1147 * errno with remaining time filled in timeout argument.
1149 static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1150 unsigned reset_counter,
1153 struct drm_i915_file_private *file_priv)
1155 struct drm_device *dev = ring->dev;
1156 struct drm_i915_private *dev_priv = dev->dev_private;
1157 const bool irq_test_in_progress =
1158 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1160 unsigned long timeout_expire;
1164 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1166 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1169 timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1171 if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1172 gen6_rps_boost(dev_priv);
1174 mod_delayed_work(dev_priv->wq,
1175 &file_priv->mm.idle_work,
1176 msecs_to_jiffies(100));
1179 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1182 /* Record current time in case interrupted by signal, or wedged */
1183 trace_i915_gem_request_wait_begin(ring, seqno);
1184 before = ktime_get_raw_ns();
1186 struct timer_list timer;
1188 prepare_to_wait(&ring->irq_queue, &wait,
1189 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1191 /* We need to check whether any gpu reset happened in between
1192 * the caller grabbing the seqno and now ... */
1193 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1194 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1195 * is truely gone. */
1196 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1202 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1207 if (interruptible && signal_pending(current)) {
1212 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1217 timer.function = NULL;
1218 if (timeout || missed_irq(dev_priv, ring)) {
1219 unsigned long expire;
1221 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1222 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1223 mod_timer(&timer, expire);
1228 if (timer.function) {
1229 del_singleshot_timer_sync(&timer);
1230 destroy_timer_on_stack(&timer);
1233 now = ktime_get_raw_ns();
1234 trace_i915_gem_request_wait_end(ring, seqno);
1236 if (!irq_test_in_progress)
1237 ring->irq_put(ring);
1239 finish_wait(&ring->irq_queue, &wait);
1242 s64 tres = *timeout - (now - before);
1244 *timeout = tres < 0 ? 0 : tres;
1251 * Waits for a sequence number to be signaled, and cleans up the
1252 * request and object lists appropriately for that event.
1255 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1257 struct drm_device *dev = ring->dev;
1258 struct drm_i915_private *dev_priv = dev->dev_private;
1259 bool interruptible = dev_priv->mm.interruptible;
1262 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1265 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1269 ret = i915_gem_check_olr(ring, seqno);
1273 return __wait_seqno(ring, seqno,
1274 atomic_read(&dev_priv->gpu_error.reset_counter),
1275 interruptible, NULL, NULL);
1279 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1280 struct intel_engine_cs *ring)
1285 /* Manually manage the write flush as we may have not yet
1286 * retired the buffer.
1288 * Note that the last_write_seqno is always the earlier of
1289 * the two (read/write) seqno, so if we haved successfully waited,
1290 * we know we have passed the last write.
1292 obj->last_write_seqno = 0;
1298 * Ensures that all rendering to the object has completed and the object is
1299 * safe to unbind from the GTT or access from the CPU.
1301 static __must_check int
1302 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1305 struct intel_engine_cs *ring = obj->ring;
1309 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1313 ret = i915_wait_seqno(ring, seqno);
1317 return i915_gem_object_wait_rendering__tail(obj, ring);
1320 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1321 * as the object state may change during this call.
1323 static __must_check int
1324 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1325 struct drm_i915_file_private *file_priv,
1328 struct drm_device *dev = obj->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 struct intel_engine_cs *ring = obj->ring;
1331 unsigned reset_counter;
1335 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1336 BUG_ON(!dev_priv->mm.interruptible);
1338 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1342 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1346 ret = i915_gem_check_olr(ring, seqno);
1350 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1351 mutex_unlock(&dev->struct_mutex);
1352 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1353 mutex_lock(&dev->struct_mutex);
1357 return i915_gem_object_wait_rendering__tail(obj, ring);
1361 * Called when user space prepares to use an object with the CPU, either
1362 * through the mmap ioctl's mapping or a GTT mapping.
1365 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1366 struct drm_file *file)
1368 struct drm_i915_gem_set_domain *args = data;
1369 struct drm_i915_gem_object *obj;
1370 uint32_t read_domains = args->read_domains;
1371 uint32_t write_domain = args->write_domain;
1374 /* Only handle setting domains to types used by the CPU. */
1375 if (write_domain & I915_GEM_GPU_DOMAINS)
1378 if (read_domains & I915_GEM_GPU_DOMAINS)
1381 /* Having something in the write domain implies it's in the read
1382 * domain, and only that read domain. Enforce that in the request.
1384 if (write_domain != 0 && read_domains != write_domain)
1387 ret = i915_mutex_lock_interruptible(dev);
1391 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1392 if (&obj->base == NULL) {
1397 /* Try to flush the object off the GPU without holding the lock.
1398 * We will repeat the flush holding the lock in the normal manner
1399 * to catch cases where we are gazumped.
1401 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1407 if (read_domains & I915_GEM_DOMAIN_GTT) {
1408 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1410 /* Silently promote "you're not bound, there was nothing to do"
1411 * to success, since the client was just asking us to
1412 * make sure everything was done.
1417 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1421 drm_gem_object_unreference(&obj->base);
1423 mutex_unlock(&dev->struct_mutex);
1428 * Called when user space has done writes to this buffer
1431 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1432 struct drm_file *file)
1434 struct drm_i915_gem_sw_finish *args = data;
1435 struct drm_i915_gem_object *obj;
1438 ret = i915_mutex_lock_interruptible(dev);
1442 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1443 if (&obj->base == NULL) {
1448 /* Pinned buffers may be scanout, so flush the cache */
1449 if (obj->pin_display)
1450 i915_gem_object_flush_cpu_write_domain(obj, true);
1452 drm_gem_object_unreference(&obj->base);
1454 mutex_unlock(&dev->struct_mutex);
1459 * Maps the contents of an object, returning the address it is mapped
1462 * While the mapping holds a reference on the contents of the object, it doesn't
1463 * imply a ref on the object itself.
1466 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1467 struct drm_file *file)
1469 struct drm_i915_gem_mmap *args = data;
1470 struct drm_gem_object *obj;
1473 obj = drm_gem_object_lookup(dev, file, args->handle);
1477 /* prime objects have no backing filp to GEM mmap
1481 drm_gem_object_unreference_unlocked(obj);
1485 addr = vm_mmap(obj->filp, 0, args->size,
1486 PROT_READ | PROT_WRITE, MAP_SHARED,
1488 drm_gem_object_unreference_unlocked(obj);
1489 if (IS_ERR((void *)addr))
1492 args->addr_ptr = (uint64_t) addr;
1498 * i915_gem_fault - fault a page into the GTT
1499 * vma: VMA in question
1502 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1503 * from userspace. The fault handler takes care of binding the object to
1504 * the GTT (if needed), allocating and programming a fence register (again,
1505 * only if needed based on whether the old reg is still valid or the object
1506 * is tiled) and inserting a new PTE into the faulting process.
1508 * Note that the faulting process may involve evicting existing objects
1509 * from the GTT and/or fence registers to make room. So performance may
1510 * suffer if the GTT working set is large or there are few fence registers
1513 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1515 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1516 struct drm_device *dev = obj->base.dev;
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518 pgoff_t page_offset;
1521 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1523 intel_runtime_pm_get(dev_priv);
1525 /* We don't use vmf->pgoff since that has the fake offset */
1526 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1529 ret = i915_mutex_lock_interruptible(dev);
1533 trace_i915_gem_object_fault(obj, page_offset, true, write);
1535 /* Try to flush the object off the GPU first without holding the lock.
1536 * Upon reacquiring the lock, we will perform our sanity checks and then
1537 * repeat the flush holding the lock in the normal manner to catch cases
1538 * where we are gazumped.
1540 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1544 /* Access to snoopable pages through the GTT is incoherent. */
1545 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1550 /* Now bind it into the GTT if needed */
1551 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1555 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1559 ret = i915_gem_object_get_fence(obj);
1563 /* Finally, remap it using the new GTT offset */
1564 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1567 if (!obj->fault_mappable) {
1568 unsigned long size = min_t(unsigned long,
1569 vma->vm_end - vma->vm_start,
1573 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1574 ret = vm_insert_pfn(vma,
1575 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1581 obj->fault_mappable = true;
1583 ret = vm_insert_pfn(vma,
1584 (unsigned long)vmf->virtual_address,
1587 i915_gem_object_ggtt_unpin(obj);
1589 mutex_unlock(&dev->struct_mutex);
1594 * We eat errors when the gpu is terminally wedged to avoid
1595 * userspace unduly crashing (gl has no provisions for mmaps to
1596 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1597 * and so needs to be reported.
1599 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1600 ret = VM_FAULT_SIGBUS;
1605 * EAGAIN means the gpu is hung and we'll wait for the error
1606 * handler to reset everything when re-faulting in
1607 * i915_mutex_lock_interruptible.
1614 * EBUSY is ok: this just means that another thread
1615 * already did the job.
1617 ret = VM_FAULT_NOPAGE;
1624 ret = VM_FAULT_SIGBUS;
1627 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1628 ret = VM_FAULT_SIGBUS;
1632 intel_runtime_pm_put(dev_priv);
1637 * i915_gem_release_mmap - remove physical page mappings
1638 * @obj: obj in question
1640 * Preserve the reservation of the mmapping with the DRM core code, but
1641 * relinquish ownership of the pages back to the system.
1643 * It is vital that we remove the page mapping if we have mapped a tiled
1644 * object through the GTT and then lose the fence register due to
1645 * resource pressure. Similarly if the object has been moved out of the
1646 * aperture, than pages mapped into userspace must be revoked. Removing the
1647 * mapping will then trigger a page fault on the next user access, allowing
1648 * fixup by i915_gem_fault().
1651 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1653 if (!obj->fault_mappable)
1656 drm_vma_node_unmap(&obj->base.vma_node,
1657 obj->base.dev->anon_inode->i_mapping);
1658 obj->fault_mappable = false;
1662 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1664 struct drm_i915_gem_object *obj;
1666 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1667 i915_gem_release_mmap(obj);
1671 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1675 if (INTEL_INFO(dev)->gen >= 4 ||
1676 tiling_mode == I915_TILING_NONE)
1679 /* Previous chips need a power-of-two fence region when tiling */
1680 if (INTEL_INFO(dev)->gen == 3)
1681 gtt_size = 1024*1024;
1683 gtt_size = 512*1024;
1685 while (gtt_size < size)
1692 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1693 * @obj: object to check
1695 * Return the required GTT alignment for an object, taking into account
1696 * potential fence register mapping.
1699 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1700 int tiling_mode, bool fenced)
1703 * Minimum alignment is 4k (GTT page size), but might be greater
1704 * if a fence register is needed for the object.
1706 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1707 tiling_mode == I915_TILING_NONE)
1711 * Previous chips need to be aligned to the size of the smallest
1712 * fence register that can contain the object.
1714 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1717 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1719 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1722 if (drm_vma_node_has_offset(&obj->base.vma_node))
1725 dev_priv->mm.shrinker_no_lock_stealing = true;
1727 ret = drm_gem_create_mmap_offset(&obj->base);
1731 /* Badly fragmented mmap space? The only way we can recover
1732 * space is by destroying unwanted objects. We can't randomly release
1733 * mmap_offsets as userspace expects them to be persistent for the
1734 * lifetime of the objects. The closest we can is to release the
1735 * offsets on purgeable objects by truncating it and marking it purged,
1736 * which prevents userspace from ever using that object again.
1738 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1739 ret = drm_gem_create_mmap_offset(&obj->base);
1743 i915_gem_shrink_all(dev_priv);
1744 ret = drm_gem_create_mmap_offset(&obj->base);
1746 dev_priv->mm.shrinker_no_lock_stealing = false;
1751 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1753 drm_gem_free_mmap_offset(&obj->base);
1757 i915_gem_mmap_gtt(struct drm_file *file,
1758 struct drm_device *dev,
1762 struct drm_i915_private *dev_priv = dev->dev_private;
1763 struct drm_i915_gem_object *obj;
1766 ret = i915_mutex_lock_interruptible(dev);
1770 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1771 if (&obj->base == NULL) {
1776 if (obj->base.size > dev_priv->gtt.mappable_end) {
1781 if (obj->madv != I915_MADV_WILLNEED) {
1782 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1787 ret = i915_gem_object_create_mmap_offset(obj);
1791 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1794 drm_gem_object_unreference(&obj->base);
1796 mutex_unlock(&dev->struct_mutex);
1801 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1803 * @data: GTT mapping ioctl data
1804 * @file: GEM object info
1806 * Simply returns the fake offset to userspace so it can mmap it.
1807 * The mmap call will end up in drm_gem_mmap(), which will set things
1808 * up so we can get faults in the handler above.
1810 * The fault handler will take care of binding the object into the GTT
1811 * (since it may have been evicted to make room for something), allocating
1812 * a fence register, and mapping the appropriate aperture address into
1816 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1817 struct drm_file *file)
1819 struct drm_i915_gem_mmap_gtt *args = data;
1821 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1825 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1827 return obj->madv == I915_MADV_DONTNEED;
1830 /* Immediately discard the backing storage */
1832 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1834 i915_gem_object_free_mmap_offset(obj);
1836 if (obj->base.filp == NULL)
1839 /* Our goal here is to return as much of the memory as
1840 * is possible back to the system as we are called from OOM.
1841 * To do this we must instruct the shmfs to drop all of its
1842 * backing pages, *now*.
1844 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1845 obj->madv = __I915_MADV_PURGED;
1848 /* Try to discard unwanted pages */
1850 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1852 struct address_space *mapping;
1854 switch (obj->madv) {
1855 case I915_MADV_DONTNEED:
1856 i915_gem_object_truncate(obj);
1857 case __I915_MADV_PURGED:
1861 if (obj->base.filp == NULL)
1864 mapping = file_inode(obj->base.filp)->i_mapping,
1865 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1869 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1871 struct sg_page_iter sg_iter;
1874 BUG_ON(obj->madv == __I915_MADV_PURGED);
1876 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1878 /* In the event of a disaster, abandon all caches and
1879 * hope for the best.
1881 WARN_ON(ret != -EIO);
1882 i915_gem_clflush_object(obj, true);
1883 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1886 if (i915_gem_object_needs_bit17_swizzle(obj))
1887 i915_gem_object_save_bit_17_swizzle(obj);
1889 if (obj->madv == I915_MADV_DONTNEED)
1892 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1893 struct page *page = sg_page_iter_page(&sg_iter);
1896 set_page_dirty(page);
1898 if (obj->madv == I915_MADV_WILLNEED)
1899 mark_page_accessed(page);
1901 page_cache_release(page);
1905 sg_free_table(obj->pages);
1910 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1912 const struct drm_i915_gem_object_ops *ops = obj->ops;
1914 if (obj->pages == NULL)
1917 if (obj->pages_pin_count)
1920 BUG_ON(i915_gem_obj_bound_any(obj));
1922 /* ->put_pages might need to allocate memory for the bit17 swizzle
1923 * array, hence protect them from being reaped by removing them from gtt
1925 list_del(&obj->global_list);
1927 ops->put_pages(obj);
1930 i915_gem_object_invalidate(obj);
1935 static unsigned long
1936 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1937 bool purgeable_only)
1939 struct list_head still_in_list;
1940 struct drm_i915_gem_object *obj;
1941 unsigned long count = 0;
1944 * As we may completely rewrite the (un)bound list whilst unbinding
1945 * (due to retiring requests) we have to strictly process only
1946 * one element of the list at the time, and recheck the list
1947 * on every iteration.
1949 * In particular, we must hold a reference whilst removing the
1950 * object as we may end up waiting for and/or retiring the objects.
1951 * This might release the final reference (held by the active list)
1952 * and result in the object being freed from under us. This is
1953 * similar to the precautions the eviction code must take whilst
1956 * Also note that although these lists do not hold a reference to
1957 * the object we can safely grab one here: The final object
1958 * unreferencing and the bound_list are both protected by the
1959 * dev->struct_mutex and so we won't ever be able to observe an
1960 * object on the bound_list with a reference count equals 0.
1962 INIT_LIST_HEAD(&still_in_list);
1963 while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
1964 obj = list_first_entry(&dev_priv->mm.unbound_list,
1965 typeof(*obj), global_list);
1966 list_move_tail(&obj->global_list, &still_in_list);
1968 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1971 drm_gem_object_reference(&obj->base);
1973 if (i915_gem_object_put_pages(obj) == 0)
1974 count += obj->base.size >> PAGE_SHIFT;
1976 drm_gem_object_unreference(&obj->base);
1978 list_splice(&still_in_list, &dev_priv->mm.unbound_list);
1980 INIT_LIST_HEAD(&still_in_list);
1981 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1982 struct i915_vma *vma, *v;
1984 obj = list_first_entry(&dev_priv->mm.bound_list,
1985 typeof(*obj), global_list);
1986 list_move_tail(&obj->global_list, &still_in_list);
1988 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1991 drm_gem_object_reference(&obj->base);
1993 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1994 if (i915_vma_unbind(vma))
1997 if (i915_gem_object_put_pages(obj) == 0)
1998 count += obj->base.size >> PAGE_SHIFT;
2000 drm_gem_object_unreference(&obj->base);
2002 list_splice(&still_in_list, &dev_priv->mm.bound_list);
2007 static unsigned long
2008 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
2010 return __i915_gem_shrink(dev_priv, target, true);
2013 static unsigned long
2014 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2016 i915_gem_evict_everything(dev_priv->dev);
2017 return __i915_gem_shrink(dev_priv, LONG_MAX, false);
2021 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2023 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2025 struct address_space *mapping;
2026 struct sg_table *st;
2027 struct scatterlist *sg;
2028 struct sg_page_iter sg_iter;
2030 unsigned long last_pfn = 0; /* suppress gcc warning */
2033 /* Assert that the object is not currently in any GPU domain. As it
2034 * wasn't in the GTT, there shouldn't be any way it could have been in
2037 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2038 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2040 st = kmalloc(sizeof(*st), GFP_KERNEL);
2044 page_count = obj->base.size / PAGE_SIZE;
2045 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2050 /* Get the list of pages out of our struct file. They'll be pinned
2051 * at this point until we release them.
2053 * Fail silently without starting the shrinker
2055 mapping = file_inode(obj->base.filp)->i_mapping;
2056 gfp = mapping_gfp_mask(mapping);
2057 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2058 gfp &= ~(__GFP_IO | __GFP_WAIT);
2061 for (i = 0; i < page_count; i++) {
2062 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2064 i915_gem_purge(dev_priv, page_count);
2065 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2068 /* We've tried hard to allocate the memory by reaping
2069 * our own buffer, now let the real VM do its job and
2070 * go down in flames if truly OOM.
2072 i915_gem_shrink_all(dev_priv);
2073 page = shmem_read_mapping_page(mapping, i);
2077 #ifdef CONFIG_SWIOTLB
2078 if (swiotlb_nr_tbl()) {
2080 sg_set_page(sg, page, PAGE_SIZE, 0);
2085 if (!i || page_to_pfn(page) != last_pfn + 1) {
2089 sg_set_page(sg, page, PAGE_SIZE, 0);
2091 sg->length += PAGE_SIZE;
2093 last_pfn = page_to_pfn(page);
2095 /* Check that the i965g/gm workaround works. */
2096 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2098 #ifdef CONFIG_SWIOTLB
2099 if (!swiotlb_nr_tbl())
2104 if (i915_gem_object_needs_bit17_swizzle(obj))
2105 i915_gem_object_do_bit_17_swizzle(obj);
2111 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2112 page_cache_release(sg_page_iter_page(&sg_iter));
2116 /* shmemfs first checks if there is enough memory to allocate the page
2117 * and reports ENOSPC should there be insufficient, along with the usual
2118 * ENOMEM for a genuine allocation failure.
2120 * We use ENOSPC in our driver to mean that we have run out of aperture
2121 * space and so want to translate the error from shmemfs back to our
2122 * usual understanding of ENOMEM.
2124 if (PTR_ERR(page) == -ENOSPC)
2127 return PTR_ERR(page);
2130 /* Ensure that the associated pages are gathered from the backing storage
2131 * and pinned into our object. i915_gem_object_get_pages() may be called
2132 * multiple times before they are released by a single call to
2133 * i915_gem_object_put_pages() - once the pages are no longer referenced
2134 * either as a result of memory pressure (reaping pages under the shrinker)
2135 * or as the object is itself released.
2138 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2140 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2141 const struct drm_i915_gem_object_ops *ops = obj->ops;
2147 if (obj->madv != I915_MADV_WILLNEED) {
2148 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2152 BUG_ON(obj->pages_pin_count);
2154 ret = ops->get_pages(obj);
2158 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2163 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2164 struct intel_engine_cs *ring)
2166 struct drm_device *dev = obj->base.dev;
2167 struct drm_i915_private *dev_priv = dev->dev_private;
2168 u32 seqno = intel_ring_get_seqno(ring);
2170 BUG_ON(ring == NULL);
2171 if (obj->ring != ring && obj->last_write_seqno) {
2172 /* Keep the seqno relative to the current ring */
2173 obj->last_write_seqno = seqno;
2177 /* Add a reference if we're newly entering the active list. */
2179 drm_gem_object_reference(&obj->base);
2183 list_move_tail(&obj->ring_list, &ring->active_list);
2185 obj->last_read_seqno = seqno;
2187 if (obj->fenced_gpu_access) {
2188 obj->last_fenced_seqno = seqno;
2190 /* Bump MRU to take account of the delayed flush */
2191 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2192 struct drm_i915_fence_reg *reg;
2194 reg = &dev_priv->fence_regs[obj->fence_reg];
2195 list_move_tail(®->lru_list,
2196 &dev_priv->mm.fence_list);
2201 void i915_vma_move_to_active(struct i915_vma *vma,
2202 struct intel_engine_cs *ring)
2204 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2205 return i915_gem_object_move_to_active(vma->obj, ring);
2209 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2211 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2212 struct i915_address_space *vm;
2213 struct i915_vma *vma;
2215 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2216 BUG_ON(!obj->active);
2218 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2219 vma = i915_gem_obj_to_vma(obj, vm);
2220 if (vma && !list_empty(&vma->mm_list))
2221 list_move_tail(&vma->mm_list, &vm->inactive_list);
2224 intel_fb_obj_flush(obj, true);
2226 list_del_init(&obj->ring_list);
2229 obj->last_read_seqno = 0;
2230 obj->last_write_seqno = 0;
2231 obj->base.write_domain = 0;
2233 obj->last_fenced_seqno = 0;
2234 obj->fenced_gpu_access = false;
2237 drm_gem_object_unreference(&obj->base);
2239 WARN_ON(i915_verify_lists(dev));
2243 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2245 struct intel_engine_cs *ring = obj->ring;
2250 if (i915_seqno_passed(ring->get_seqno(ring, true),
2251 obj->last_read_seqno))
2252 i915_gem_object_move_to_inactive(obj);
2256 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2258 struct drm_i915_private *dev_priv = dev->dev_private;
2259 struct intel_engine_cs *ring;
2262 /* Carefully retire all requests without writing to the rings */
2263 for_each_ring(ring, dev_priv, i) {
2264 ret = intel_ring_idle(ring);
2268 i915_gem_retire_requests(dev);
2270 /* Finally reset hw state */
2271 for_each_ring(ring, dev_priv, i) {
2272 intel_ring_init_seqno(ring, seqno);
2274 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2275 ring->semaphore.sync_seqno[j] = 0;
2281 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2283 struct drm_i915_private *dev_priv = dev->dev_private;
2289 /* HWS page needs to be set less than what we
2290 * will inject to ring
2292 ret = i915_gem_init_seqno(dev, seqno - 1);
2296 /* Carefully set the last_seqno value so that wrap
2297 * detection still works
2299 dev_priv->next_seqno = seqno;
2300 dev_priv->last_seqno = seqno - 1;
2301 if (dev_priv->last_seqno == 0)
2302 dev_priv->last_seqno--;
2308 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2312 /* reserve 0 for non-seqno */
2313 if (dev_priv->next_seqno == 0) {
2314 int ret = i915_gem_init_seqno(dev, 0);
2318 dev_priv->next_seqno = 1;
2321 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2325 int __i915_add_request(struct intel_engine_cs *ring,
2326 struct drm_file *file,
2327 struct drm_i915_gem_object *obj,
2330 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2331 struct drm_i915_gem_request *request;
2332 u32 request_ring_position, request_start;
2335 request_start = intel_ring_get_tail(ring->buffer);
2337 * Emit any outstanding flushes - execbuf can fail to emit the flush
2338 * after having emitted the batchbuffer command. Hence we need to fix
2339 * things up similar to emitting the lazy request. The difference here
2340 * is that the flush _must_ happen before the next request, no matter
2343 ret = intel_ring_flush_all_caches(ring);
2347 request = ring->preallocated_lazy_request;
2348 if (WARN_ON(request == NULL))
2351 /* Record the position of the start of the request so that
2352 * should we detect the updated seqno part-way through the
2353 * GPU processing the request, we never over-estimate the
2354 * position of the head.
2356 request_ring_position = intel_ring_get_tail(ring->buffer);
2358 ret = ring->add_request(ring);
2362 request->seqno = intel_ring_get_seqno(ring);
2363 request->ring = ring;
2364 request->head = request_start;
2365 request->tail = request_ring_position;
2367 /* Whilst this request exists, batch_obj will be on the
2368 * active_list, and so will hold the active reference. Only when this
2369 * request is retired will the the batch_obj be moved onto the
2370 * inactive_list and lose its active reference. Hence we do not need
2371 * to explicitly hold another reference here.
2373 request->batch_obj = obj;
2375 /* Hold a reference to the current context so that we can inspect
2376 * it later in case a hangcheck error event fires.
2378 request->ctx = ring->last_context;
2380 i915_gem_context_reference(request->ctx);
2382 request->emitted_jiffies = jiffies;
2383 list_add_tail(&request->list, &ring->request_list);
2384 request->file_priv = NULL;
2387 struct drm_i915_file_private *file_priv = file->driver_priv;
2389 spin_lock(&file_priv->mm.lock);
2390 request->file_priv = file_priv;
2391 list_add_tail(&request->client_list,
2392 &file_priv->mm.request_list);
2393 spin_unlock(&file_priv->mm.lock);
2396 trace_i915_gem_request_add(ring, request->seqno);
2397 ring->outstanding_lazy_seqno = 0;
2398 ring->preallocated_lazy_request = NULL;
2400 if (!dev_priv->ums.mm_suspended) {
2401 i915_queue_hangcheck(ring->dev);
2403 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2404 queue_delayed_work(dev_priv->wq,
2405 &dev_priv->mm.retire_work,
2406 round_jiffies_up_relative(HZ));
2407 intel_mark_busy(dev_priv->dev);
2411 *out_seqno = request->seqno;
2416 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2418 struct drm_i915_file_private *file_priv = request->file_priv;
2423 spin_lock(&file_priv->mm.lock);
2424 list_del(&request->client_list);
2425 request->file_priv = NULL;
2426 spin_unlock(&file_priv->mm.lock);
2429 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2430 const struct intel_context *ctx)
2432 unsigned long elapsed;
2434 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2436 if (ctx->hang_stats.banned)
2439 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2440 if (!i915_gem_context_is_default(ctx)) {
2441 DRM_DEBUG("context hanging too fast, banning!\n");
2443 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2444 if (i915_stop_ring_allow_warn(dev_priv))
2445 DRM_ERROR("gpu hanging too fast, banning!\n");
2453 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2454 struct intel_context *ctx,
2457 struct i915_ctx_hang_stats *hs;
2462 hs = &ctx->hang_stats;
2465 hs->banned = i915_context_is_banned(dev_priv, ctx);
2467 hs->guilty_ts = get_seconds();
2469 hs->batch_pending++;
2473 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2475 list_del(&request->list);
2476 i915_gem_request_remove_from_client(request);
2479 i915_gem_context_unreference(request->ctx);
2484 struct drm_i915_gem_request *
2485 i915_gem_find_active_request(struct intel_engine_cs *ring)
2487 struct drm_i915_gem_request *request;
2488 u32 completed_seqno;
2490 completed_seqno = ring->get_seqno(ring, false);
2492 list_for_each_entry(request, &ring->request_list, list) {
2493 if (i915_seqno_passed(completed_seqno, request->seqno))
2502 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2503 struct intel_engine_cs *ring)
2505 struct drm_i915_gem_request *request;
2508 request = i915_gem_find_active_request(ring);
2510 if (request == NULL)
2513 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2515 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2517 list_for_each_entry_continue(request, &ring->request_list, list)
2518 i915_set_reset_status(dev_priv, request->ctx, false);
2521 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2522 struct intel_engine_cs *ring)
2524 while (!list_empty(&ring->active_list)) {
2525 struct drm_i915_gem_object *obj;
2527 obj = list_first_entry(&ring->active_list,
2528 struct drm_i915_gem_object,
2531 i915_gem_object_move_to_inactive(obj);
2535 * We must free the requests after all the corresponding objects have
2536 * been moved off active lists. Which is the same order as the normal
2537 * retire_requests function does. This is important if object hold
2538 * implicit references on things like e.g. ppgtt address spaces through
2541 while (!list_empty(&ring->request_list)) {
2542 struct drm_i915_gem_request *request;
2544 request = list_first_entry(&ring->request_list,
2545 struct drm_i915_gem_request,
2548 i915_gem_free_request(request);
2551 /* These may not have been flush before the reset, do so now */
2552 kfree(ring->preallocated_lazy_request);
2553 ring->preallocated_lazy_request = NULL;
2554 ring->outstanding_lazy_seqno = 0;
2557 void i915_gem_restore_fences(struct drm_device *dev)
2559 struct drm_i915_private *dev_priv = dev->dev_private;
2562 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2563 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2566 * Commit delayed tiling changes if we have an object still
2567 * attached to the fence, otherwise just clear the fence.
2570 i915_gem_object_update_fence(reg->obj, reg,
2571 reg->obj->tiling_mode);
2573 i915_gem_write_fence(dev, i, NULL);
2578 void i915_gem_reset(struct drm_device *dev)
2580 struct drm_i915_private *dev_priv = dev->dev_private;
2581 struct intel_engine_cs *ring;
2585 * Before we free the objects from the requests, we need to inspect
2586 * them for finding the guilty party. As the requests only borrow
2587 * their reference to the objects, the inspection must be done first.
2589 for_each_ring(ring, dev_priv, i)
2590 i915_gem_reset_ring_status(dev_priv, ring);
2592 for_each_ring(ring, dev_priv, i)
2593 i915_gem_reset_ring_cleanup(dev_priv, ring);
2595 i915_gem_context_reset(dev);
2597 i915_gem_restore_fences(dev);
2601 * This function clears the request list as sequence numbers are passed.
2604 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2608 if (list_empty(&ring->request_list))
2611 WARN_ON(i915_verify_lists(ring->dev));
2613 seqno = ring->get_seqno(ring, true);
2615 /* Move any buffers on the active list that are no longer referenced
2616 * by the ringbuffer to the flushing/inactive lists as appropriate,
2617 * before we free the context associated with the requests.
2619 while (!list_empty(&ring->active_list)) {
2620 struct drm_i915_gem_object *obj;
2622 obj = list_first_entry(&ring->active_list,
2623 struct drm_i915_gem_object,
2626 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2629 i915_gem_object_move_to_inactive(obj);
2633 while (!list_empty(&ring->request_list)) {
2634 struct drm_i915_gem_request *request;
2636 request = list_first_entry(&ring->request_list,
2637 struct drm_i915_gem_request,
2640 if (!i915_seqno_passed(seqno, request->seqno))
2643 trace_i915_gem_request_retire(ring, request->seqno);
2644 /* We know the GPU must have read the request to have
2645 * sent us the seqno + interrupt, so use the position
2646 * of tail of the request to update the last known position
2649 ring->buffer->last_retired_head = request->tail;
2651 i915_gem_free_request(request);
2654 if (unlikely(ring->trace_irq_seqno &&
2655 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2656 ring->irq_put(ring);
2657 ring->trace_irq_seqno = 0;
2660 WARN_ON(i915_verify_lists(ring->dev));
2664 i915_gem_retire_requests(struct drm_device *dev)
2666 struct drm_i915_private *dev_priv = dev->dev_private;
2667 struct intel_engine_cs *ring;
2671 for_each_ring(ring, dev_priv, i) {
2672 i915_gem_retire_requests_ring(ring);
2673 idle &= list_empty(&ring->request_list);
2677 mod_delayed_work(dev_priv->wq,
2678 &dev_priv->mm.idle_work,
2679 msecs_to_jiffies(100));
2685 i915_gem_retire_work_handler(struct work_struct *work)
2687 struct drm_i915_private *dev_priv =
2688 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2689 struct drm_device *dev = dev_priv->dev;
2692 /* Come back later if the device is busy... */
2694 if (mutex_trylock(&dev->struct_mutex)) {
2695 idle = i915_gem_retire_requests(dev);
2696 mutex_unlock(&dev->struct_mutex);
2699 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2700 round_jiffies_up_relative(HZ));
2704 i915_gem_idle_work_handler(struct work_struct *work)
2706 struct drm_i915_private *dev_priv =
2707 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2709 intel_mark_idle(dev_priv->dev);
2713 * Ensures that an object will eventually get non-busy by flushing any required
2714 * write domains, emitting any outstanding lazy request and retiring and
2715 * completed requests.
2718 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2723 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2727 i915_gem_retire_requests_ring(obj->ring);
2734 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2735 * @DRM_IOCTL_ARGS: standard ioctl arguments
2737 * Returns 0 if successful, else an error is returned with the remaining time in
2738 * the timeout parameter.
2739 * -ETIME: object is still busy after timeout
2740 * -ERESTARTSYS: signal interrupted the wait
2741 * -ENONENT: object doesn't exist
2742 * Also possible, but rare:
2743 * -EAGAIN: GPU wedged
2745 * -ENODEV: Internal IRQ fail
2746 * -E?: The add request failed
2748 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2749 * non-zero timeout parameter the wait ioctl will wait for the given number of
2750 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2751 * without holding struct_mutex the object may become re-busied before this
2752 * function completes. A similar but shorter * race condition exists in the busy
2756 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2759 struct drm_i915_gem_wait *args = data;
2760 struct drm_i915_gem_object *obj;
2761 struct intel_engine_cs *ring = NULL;
2762 unsigned reset_counter;
2766 ret = i915_mutex_lock_interruptible(dev);
2770 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2771 if (&obj->base == NULL) {
2772 mutex_unlock(&dev->struct_mutex);
2776 /* Need to make sure the object gets inactive eventually. */
2777 ret = i915_gem_object_flush_active(obj);
2782 seqno = obj->last_read_seqno;
2789 /* Do this after OLR check to make sure we make forward progress polling
2790 * on this IOCTL with a timeout <=0 (like busy ioctl)
2792 if (args->timeout_ns <= 0) {
2797 drm_gem_object_unreference(&obj->base);
2798 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2799 mutex_unlock(&dev->struct_mutex);
2801 return __wait_seqno(ring, seqno, reset_counter, true, &args->timeout_ns,
2805 drm_gem_object_unreference(&obj->base);
2806 mutex_unlock(&dev->struct_mutex);
2811 * i915_gem_object_sync - sync an object to a ring.
2813 * @obj: object which may be in use on another ring.
2814 * @to: ring we wish to use the object on. May be NULL.
2816 * This code is meant to abstract object synchronization with the GPU.
2817 * Calling with NULL implies synchronizing the object with the CPU
2818 * rather than a particular GPU ring.
2820 * Returns 0 if successful, else propagates up the lower layer error.
2823 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2824 struct intel_engine_cs *to)
2826 struct intel_engine_cs *from = obj->ring;
2830 if (from == NULL || to == from)
2833 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2834 return i915_gem_object_wait_rendering(obj, false);
2836 idx = intel_ring_sync_index(from, to);
2838 seqno = obj->last_read_seqno;
2839 /* Optimization: Avoid semaphore sync when we are sure we already
2840 * waited for an object with higher seqno */
2841 if (seqno <= from->semaphore.sync_seqno[idx])
2844 ret = i915_gem_check_olr(obj->ring, seqno);
2848 trace_i915_gem_ring_sync_to(from, to, seqno);
2849 ret = to->semaphore.sync_to(to, from, seqno);
2851 /* We use last_read_seqno because sync_to()
2852 * might have just caused seqno wrap under
2855 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2860 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2862 u32 old_write_domain, old_read_domains;
2864 /* Force a pagefault for domain tracking on next user access */
2865 i915_gem_release_mmap(obj);
2867 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2870 /* Wait for any direct GTT access to complete */
2873 old_read_domains = obj->base.read_domains;
2874 old_write_domain = obj->base.write_domain;
2876 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2877 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2879 trace_i915_gem_object_change_domain(obj,
2884 int i915_vma_unbind(struct i915_vma *vma)
2886 struct drm_i915_gem_object *obj = vma->obj;
2887 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2890 if (list_empty(&vma->vma_link))
2893 if (!drm_mm_node_allocated(&vma->node)) {
2894 i915_gem_vma_destroy(vma);
2901 BUG_ON(obj->pages == NULL);
2903 ret = i915_gem_object_finish_gpu(obj);
2906 /* Continue on if we fail due to EIO, the GPU is hung so we
2907 * should be safe and we need to cleanup or else we might
2908 * cause memory corruption through use-after-free.
2911 if (i915_is_ggtt(vma->vm)) {
2912 i915_gem_object_finish_gtt(obj);
2914 /* release the fence reg _after_ flushing */
2915 ret = i915_gem_object_put_fence(obj);
2920 trace_i915_vma_unbind(vma);
2922 vma->unbind_vma(vma);
2924 list_del_init(&vma->mm_list);
2925 /* Avoid an unnecessary call to unbind on rebind. */
2926 if (i915_is_ggtt(vma->vm))
2927 obj->map_and_fenceable = true;
2929 drm_mm_remove_node(&vma->node);
2930 i915_gem_vma_destroy(vma);
2932 /* Since the unbound list is global, only move to that list if
2933 * no more VMAs exist. */
2934 if (list_empty(&obj->vma_list)) {
2935 i915_gem_gtt_finish_object(obj);
2936 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2939 /* And finally now the object is completely decoupled from this vma,
2940 * we can drop its hold on the backing storage and allow it to be
2941 * reaped by the shrinker.
2943 i915_gem_object_unpin_pages(obj);
2948 int i915_gpu_idle(struct drm_device *dev)
2950 struct drm_i915_private *dev_priv = dev->dev_private;
2951 struct intel_engine_cs *ring;
2954 /* Flush everything onto the inactive list. */
2955 for_each_ring(ring, dev_priv, i) {
2956 ret = i915_switch_context(ring, ring->default_context);
2960 ret = intel_ring_idle(ring);
2968 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2969 struct drm_i915_gem_object *obj)
2971 struct drm_i915_private *dev_priv = dev->dev_private;
2973 int fence_pitch_shift;
2975 if (INTEL_INFO(dev)->gen >= 6) {
2976 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2977 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2979 fence_reg = FENCE_REG_965_0;
2980 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2983 fence_reg += reg * 8;
2985 /* To w/a incoherency with non-atomic 64-bit register updates,
2986 * we split the 64-bit update into two 32-bit writes. In order
2987 * for a partial fence not to be evaluated between writes, we
2988 * precede the update with write to turn off the fence register,
2989 * and only enable the fence as the last step.
2991 * For extra levels of paranoia, we make sure each step lands
2992 * before applying the next step.
2994 I915_WRITE(fence_reg, 0);
2995 POSTING_READ(fence_reg);
2998 u32 size = i915_gem_obj_ggtt_size(obj);
3001 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3003 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3004 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3005 if (obj->tiling_mode == I915_TILING_Y)
3006 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3007 val |= I965_FENCE_REG_VALID;
3009 I915_WRITE(fence_reg + 4, val >> 32);
3010 POSTING_READ(fence_reg + 4);
3012 I915_WRITE(fence_reg + 0, val);
3013 POSTING_READ(fence_reg);
3015 I915_WRITE(fence_reg + 4, 0);
3016 POSTING_READ(fence_reg + 4);
3020 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3021 struct drm_i915_gem_object *obj)
3023 struct drm_i915_private *dev_priv = dev->dev_private;
3027 u32 size = i915_gem_obj_ggtt_size(obj);
3031 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3032 (size & -size) != size ||
3033 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3034 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3035 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3037 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3042 /* Note: pitch better be a power of two tile widths */
3043 pitch_val = obj->stride / tile_width;
3044 pitch_val = ffs(pitch_val) - 1;
3046 val = i915_gem_obj_ggtt_offset(obj);
3047 if (obj->tiling_mode == I915_TILING_Y)
3048 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3049 val |= I915_FENCE_SIZE_BITS(size);
3050 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3051 val |= I830_FENCE_REG_VALID;
3056 reg = FENCE_REG_830_0 + reg * 4;
3058 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3060 I915_WRITE(reg, val);
3064 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3065 struct drm_i915_gem_object *obj)
3067 struct drm_i915_private *dev_priv = dev->dev_private;
3071 u32 size = i915_gem_obj_ggtt_size(obj);
3074 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3075 (size & -size) != size ||
3076 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3077 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3078 i915_gem_obj_ggtt_offset(obj), size);
3080 pitch_val = obj->stride / 128;
3081 pitch_val = ffs(pitch_val) - 1;
3083 val = i915_gem_obj_ggtt_offset(obj);
3084 if (obj->tiling_mode == I915_TILING_Y)
3085 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3086 val |= I830_FENCE_SIZE_BITS(size);
3087 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3088 val |= I830_FENCE_REG_VALID;
3092 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3093 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3096 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3098 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3101 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3102 struct drm_i915_gem_object *obj)
3104 struct drm_i915_private *dev_priv = dev->dev_private;
3106 /* Ensure that all CPU reads are completed before installing a fence
3107 * and all writes before removing the fence.
3109 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3112 WARN(obj && (!obj->stride || !obj->tiling_mode),
3113 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3114 obj->stride, obj->tiling_mode);
3116 switch (INTEL_INFO(dev)->gen) {
3121 case 4: i965_write_fence_reg(dev, reg, obj); break;
3122 case 3: i915_write_fence_reg(dev, reg, obj); break;
3123 case 2: i830_write_fence_reg(dev, reg, obj); break;
3127 /* And similarly be paranoid that no direct access to this region
3128 * is reordered to before the fence is installed.
3130 if (i915_gem_object_needs_mb(obj))
3134 static inline int fence_number(struct drm_i915_private *dev_priv,
3135 struct drm_i915_fence_reg *fence)
3137 return fence - dev_priv->fence_regs;
3140 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3141 struct drm_i915_fence_reg *fence,
3144 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3145 int reg = fence_number(dev_priv, fence);
3147 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3150 obj->fence_reg = reg;
3152 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3154 obj->fence_reg = I915_FENCE_REG_NONE;
3156 list_del_init(&fence->lru_list);
3158 obj->fence_dirty = false;
3162 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3164 if (obj->last_fenced_seqno) {
3165 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3169 obj->last_fenced_seqno = 0;
3172 obj->fenced_gpu_access = false;
3177 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3180 struct drm_i915_fence_reg *fence;
3183 ret = i915_gem_object_wait_fence(obj);
3187 if (obj->fence_reg == I915_FENCE_REG_NONE)
3190 fence = &dev_priv->fence_regs[obj->fence_reg];
3192 if (WARN_ON(fence->pin_count))
3195 i915_gem_object_fence_lost(obj);
3196 i915_gem_object_update_fence(obj, fence, false);
3201 static struct drm_i915_fence_reg *
3202 i915_find_fence_reg(struct drm_device *dev)
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 struct drm_i915_fence_reg *reg, *avail;
3208 /* First try to find a free reg */
3210 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3211 reg = &dev_priv->fence_regs[i];
3215 if (!reg->pin_count)
3222 /* None available, try to steal one or wait for a user to finish */
3223 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3231 /* Wait for completion of pending flips which consume fences */
3232 if (intel_has_pending_fb_unpin(dev))
3233 return ERR_PTR(-EAGAIN);
3235 return ERR_PTR(-EDEADLK);
3239 * i915_gem_object_get_fence - set up fencing for an object
3240 * @obj: object to map through a fence reg
3242 * When mapping objects through the GTT, userspace wants to be able to write
3243 * to them without having to worry about swizzling if the object is tiled.
3244 * This function walks the fence regs looking for a free one for @obj,
3245 * stealing one if it can't find any.
3247 * It then sets up the reg based on the object's properties: address, pitch
3248 * and tiling format.
3250 * For an untiled surface, this removes any existing fence.
3253 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3255 struct drm_device *dev = obj->base.dev;
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257 bool enable = obj->tiling_mode != I915_TILING_NONE;
3258 struct drm_i915_fence_reg *reg;
3261 /* Have we updated the tiling parameters upon the object and so
3262 * will need to serialise the write to the associated fence register?
3264 if (obj->fence_dirty) {
3265 ret = i915_gem_object_wait_fence(obj);
3270 /* Just update our place in the LRU if our fence is getting reused. */
3271 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3272 reg = &dev_priv->fence_regs[obj->fence_reg];
3273 if (!obj->fence_dirty) {
3274 list_move_tail(®->lru_list,
3275 &dev_priv->mm.fence_list);
3278 } else if (enable) {
3279 reg = i915_find_fence_reg(dev);
3281 return PTR_ERR(reg);
3284 struct drm_i915_gem_object *old = reg->obj;
3286 ret = i915_gem_object_wait_fence(old);
3290 i915_gem_object_fence_lost(old);
3295 i915_gem_object_update_fence(obj, reg, enable);
3300 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3301 struct drm_mm_node *gtt_space,
3302 unsigned long cache_level)
3304 struct drm_mm_node *other;
3306 /* On non-LLC machines we have to be careful when putting differing
3307 * types of snoopable memory together to avoid the prefetcher
3308 * crossing memory domains and dying.
3313 if (!drm_mm_node_allocated(gtt_space))
3316 if (list_empty(>t_space->node_list))
3319 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3320 if (other->allocated && !other->hole_follows && other->color != cache_level)
3323 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3324 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3330 static void i915_gem_verify_gtt(struct drm_device *dev)
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334 struct drm_i915_gem_object *obj;
3337 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3338 if (obj->gtt_space == NULL) {
3339 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3344 if (obj->cache_level != obj->gtt_space->color) {
3345 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3346 i915_gem_obj_ggtt_offset(obj),
3347 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3349 obj->gtt_space->color);
3354 if (!i915_gem_valid_gtt_space(dev,
3356 obj->cache_level)) {
3357 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3358 i915_gem_obj_ggtt_offset(obj),
3359 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3371 * Finds free space in the GTT aperture and binds the object there.
3373 static struct i915_vma *
3374 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3375 struct i915_address_space *vm,
3379 struct drm_device *dev = obj->base.dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 u32 size, fence_size, fence_alignment, unfenced_alignment;
3382 unsigned long start =
3383 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3385 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3386 struct i915_vma *vma;
3389 fence_size = i915_gem_get_gtt_size(dev,
3392 fence_alignment = i915_gem_get_gtt_alignment(dev,
3394 obj->tiling_mode, true);
3395 unfenced_alignment =
3396 i915_gem_get_gtt_alignment(dev,
3398 obj->tiling_mode, false);
3401 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3403 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3404 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3405 return ERR_PTR(-EINVAL);
3408 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3410 /* If the object is bigger than the entire aperture, reject it early
3411 * before evicting everything in a vain attempt to find space.
3413 if (obj->base.size > end) {
3414 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3416 flags & PIN_MAPPABLE ? "mappable" : "total",
3418 return ERR_PTR(-E2BIG);
3421 ret = i915_gem_object_get_pages(obj);
3423 return ERR_PTR(ret);
3425 i915_gem_object_pin_pages(obj);
3427 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3432 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3436 DRM_MM_SEARCH_DEFAULT,
3437 DRM_MM_CREATE_DEFAULT);
3439 ret = i915_gem_evict_something(dev, vm, size, alignment,
3448 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3449 obj->cache_level))) {
3451 goto err_remove_node;
3454 ret = i915_gem_gtt_prepare_object(obj);
3456 goto err_remove_node;
3458 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3459 list_add_tail(&vma->mm_list, &vm->inactive_list);
3461 if (i915_is_ggtt(vm)) {
3462 bool mappable, fenceable;
3464 fenceable = (vma->node.size == fence_size &&
3465 (vma->node.start & (fence_alignment - 1)) == 0);
3467 mappable = (vma->node.start + obj->base.size <=
3468 dev_priv->gtt.mappable_end);
3470 obj->map_and_fenceable = mappable && fenceable;
3473 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3475 trace_i915_vma_bind(vma, flags);
3476 vma->bind_vma(vma, obj->cache_level,
3477 flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3479 i915_gem_verify_gtt(dev);
3483 drm_mm_remove_node(&vma->node);
3485 i915_gem_vma_destroy(vma);
3488 i915_gem_object_unpin_pages(obj);
3493 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3496 /* If we don't have a page list set up, then we're not pinned
3497 * to GPU, and we can ignore the cache flush because it'll happen
3498 * again at bind time.
3500 if (obj->pages == NULL)
3504 * Stolen memory is always coherent with the GPU as it is explicitly
3505 * marked as wc by the system, or the system is cache-coherent.
3510 /* If the GPU is snooping the contents of the CPU cache,
3511 * we do not need to manually clear the CPU cache lines. However,
3512 * the caches are only snooped when the render cache is
3513 * flushed/invalidated. As we always have to emit invalidations
3514 * and flushes when moving into and out of the RENDER domain, correct
3515 * snooping behaviour occurs naturally as the result of our domain
3518 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3521 trace_i915_gem_object_clflush(obj);
3522 drm_clflush_sg(obj->pages);
3527 /** Flushes the GTT write domain for the object if it's dirty. */
3529 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3531 uint32_t old_write_domain;
3533 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3536 /* No actual flushing is required for the GTT write domain. Writes
3537 * to it immediately go to main memory as far as we know, so there's
3538 * no chipset flush. It also doesn't land in render cache.
3540 * However, we do have to enforce the order so that all writes through
3541 * the GTT land before any writes to the device, such as updates to
3546 old_write_domain = obj->base.write_domain;
3547 obj->base.write_domain = 0;
3549 intel_fb_obj_flush(obj, false);
3551 trace_i915_gem_object_change_domain(obj,
3552 obj->base.read_domains,
3556 /** Flushes the CPU write domain for the object if it's dirty. */
3558 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3561 uint32_t old_write_domain;
3563 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3566 if (i915_gem_clflush_object(obj, force))
3567 i915_gem_chipset_flush(obj->base.dev);
3569 old_write_domain = obj->base.write_domain;
3570 obj->base.write_domain = 0;
3572 intel_fb_obj_flush(obj, false);
3574 trace_i915_gem_object_change_domain(obj,
3575 obj->base.read_domains,
3580 * Moves a single object to the GTT read, and possibly write domain.
3582 * This function returns when the move is complete, including waiting on
3586 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3588 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3589 uint32_t old_write_domain, old_read_domains;
3592 /* Not valid to be called on unbound objects. */
3593 if (!i915_gem_obj_bound_any(obj))
3596 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3599 ret = i915_gem_object_wait_rendering(obj, !write);
3603 i915_gem_object_retire(obj);
3604 i915_gem_object_flush_cpu_write_domain(obj, false);
3606 /* Serialise direct access to this object with the barriers for
3607 * coherent writes from the GPU, by effectively invalidating the
3608 * GTT domain upon first access.
3610 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3613 old_write_domain = obj->base.write_domain;
3614 old_read_domains = obj->base.read_domains;
3616 /* It should now be out of any other write domains, and we can update
3617 * the domain values for our changes.
3619 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3620 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3622 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3623 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3628 intel_fb_obj_invalidate(obj, NULL);
3630 trace_i915_gem_object_change_domain(obj,
3634 /* And bump the LRU for this access */
3635 if (i915_gem_object_is_inactive(obj)) {
3636 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3638 list_move_tail(&vma->mm_list,
3639 &dev_priv->gtt.base.inactive_list);
3646 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3647 enum i915_cache_level cache_level)
3649 struct drm_device *dev = obj->base.dev;
3650 struct i915_vma *vma, *next;
3653 if (obj->cache_level == cache_level)
3656 if (i915_gem_obj_is_pinned(obj)) {
3657 DRM_DEBUG("can not change the cache level of pinned objects\n");
3661 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3662 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3663 ret = i915_vma_unbind(vma);
3669 if (i915_gem_obj_bound_any(obj)) {
3670 ret = i915_gem_object_finish_gpu(obj);
3674 i915_gem_object_finish_gtt(obj);
3676 /* Before SandyBridge, you could not use tiling or fence
3677 * registers with snooped memory, so relinquish any fences
3678 * currently pointing to our region in the aperture.
3680 if (INTEL_INFO(dev)->gen < 6) {
3681 ret = i915_gem_object_put_fence(obj);
3686 list_for_each_entry(vma, &obj->vma_list, vma_link)
3687 if (drm_mm_node_allocated(&vma->node))
3688 vma->bind_vma(vma, cache_level,
3689 obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3692 list_for_each_entry(vma, &obj->vma_list, vma_link)
3693 vma->node.color = cache_level;
3694 obj->cache_level = cache_level;
3696 if (cpu_write_needs_clflush(obj)) {
3697 u32 old_read_domains, old_write_domain;
3699 /* If we're coming from LLC cached, then we haven't
3700 * actually been tracking whether the data is in the
3701 * CPU cache or not, since we only allow one bit set
3702 * in obj->write_domain and have been skipping the clflushes.
3703 * Just set it to the CPU cache for now.
3705 i915_gem_object_retire(obj);
3706 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3708 old_read_domains = obj->base.read_domains;
3709 old_write_domain = obj->base.write_domain;
3711 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3712 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3714 trace_i915_gem_object_change_domain(obj,
3719 i915_gem_verify_gtt(dev);
3723 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3724 struct drm_file *file)
3726 struct drm_i915_gem_caching *args = data;
3727 struct drm_i915_gem_object *obj;
3730 ret = i915_mutex_lock_interruptible(dev);
3734 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3735 if (&obj->base == NULL) {
3740 switch (obj->cache_level) {
3741 case I915_CACHE_LLC:
3742 case I915_CACHE_L3_LLC:
3743 args->caching = I915_CACHING_CACHED;
3747 args->caching = I915_CACHING_DISPLAY;
3751 args->caching = I915_CACHING_NONE;
3755 drm_gem_object_unreference(&obj->base);
3757 mutex_unlock(&dev->struct_mutex);
3761 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3762 struct drm_file *file)
3764 struct drm_i915_gem_caching *args = data;
3765 struct drm_i915_gem_object *obj;
3766 enum i915_cache_level level;
3769 switch (args->caching) {
3770 case I915_CACHING_NONE:
3771 level = I915_CACHE_NONE;
3773 case I915_CACHING_CACHED:
3774 level = I915_CACHE_LLC;
3776 case I915_CACHING_DISPLAY:
3777 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3783 ret = i915_mutex_lock_interruptible(dev);
3787 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3788 if (&obj->base == NULL) {
3793 ret = i915_gem_object_set_cache_level(obj, level);
3795 drm_gem_object_unreference(&obj->base);
3797 mutex_unlock(&dev->struct_mutex);
3801 static bool is_pin_display(struct drm_i915_gem_object *obj)
3803 struct i915_vma *vma;
3805 if (list_empty(&obj->vma_list))
3808 vma = i915_gem_obj_to_ggtt(obj);
3812 /* There are 3 sources that pin objects:
3813 * 1. The display engine (scanouts, sprites, cursors);
3814 * 2. Reservations for execbuffer;
3817 * We can ignore reservations as we hold the struct_mutex and
3818 * are only called outside of the reservation path. The user
3819 * can only increment pin_count once, and so if after
3820 * subtracting the potential reference by the user, any pin_count
3821 * remains, it must be due to another use by the display engine.
3823 return vma->pin_count - !!obj->user_pin_count;
3827 * Prepare buffer for display plane (scanout, cursors, etc).
3828 * Can be called from an uninterruptible phase (modesetting) and allows
3829 * any flushes to be pipelined (for pageflips).
3832 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3834 struct intel_engine_cs *pipelined)
3836 u32 old_read_domains, old_write_domain;
3837 bool was_pin_display;
3840 if (pipelined != obj->ring) {
3841 ret = i915_gem_object_sync(obj, pipelined);
3846 /* Mark the pin_display early so that we account for the
3847 * display coherency whilst setting up the cache domains.
3849 was_pin_display = obj->pin_display;
3850 obj->pin_display = true;
3852 /* The display engine is not coherent with the LLC cache on gen6. As
3853 * a result, we make sure that the pinning that is about to occur is
3854 * done with uncached PTEs. This is lowest common denominator for all
3857 * However for gen6+, we could do better by using the GFDT bit instead
3858 * of uncaching, which would allow us to flush all the LLC-cached data
3859 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3861 ret = i915_gem_object_set_cache_level(obj,
3862 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3864 goto err_unpin_display;
3866 /* As the user may map the buffer once pinned in the display plane
3867 * (e.g. libkms for the bootup splash), we have to ensure that we
3868 * always use map_and_fenceable for all scanout buffers.
3870 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3872 goto err_unpin_display;
3874 i915_gem_object_flush_cpu_write_domain(obj, true);
3876 old_write_domain = obj->base.write_domain;
3877 old_read_domains = obj->base.read_domains;
3879 /* It should now be out of any other write domains, and we can update
3880 * the domain values for our changes.
3882 obj->base.write_domain = 0;
3883 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3885 trace_i915_gem_object_change_domain(obj,
3892 WARN_ON(was_pin_display != is_pin_display(obj));
3893 obj->pin_display = was_pin_display;
3898 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3900 i915_gem_object_ggtt_unpin(obj);
3901 obj->pin_display = is_pin_display(obj);
3905 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3909 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3912 ret = i915_gem_object_wait_rendering(obj, false);
3916 /* Ensure that we invalidate the GPU's caches and TLBs. */
3917 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3922 * Moves a single object to the CPU read, and possibly write domain.
3924 * This function returns when the move is complete, including waiting on
3928 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3930 uint32_t old_write_domain, old_read_domains;
3933 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3936 ret = i915_gem_object_wait_rendering(obj, !write);
3940 i915_gem_object_retire(obj);
3941 i915_gem_object_flush_gtt_write_domain(obj);
3943 old_write_domain = obj->base.write_domain;
3944 old_read_domains = obj->base.read_domains;
3946 /* Flush the CPU cache if it's still invalid. */
3947 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3948 i915_gem_clflush_object(obj, false);
3950 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3953 /* It should now be out of any other write domains, and we can update
3954 * the domain values for our changes.
3956 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3958 /* If we're writing through the CPU, then the GPU read domains will
3959 * need to be invalidated at next use.
3962 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3963 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3967 intel_fb_obj_invalidate(obj, NULL);
3969 trace_i915_gem_object_change_domain(obj,
3976 /* Throttle our rendering by waiting until the ring has completed our requests
3977 * emitted over 20 msec ago.
3979 * Note that if we were to use the current jiffies each time around the loop,
3980 * we wouldn't escape the function with any frames outstanding if the time to
3981 * render a frame was over 20ms.
3983 * This should get us reasonable parallelism between CPU and GPU but also
3984 * relatively low latency when blocking on a particular request to finish.
3987 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3989 struct drm_i915_private *dev_priv = dev->dev_private;
3990 struct drm_i915_file_private *file_priv = file->driver_priv;
3991 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3992 struct drm_i915_gem_request *request;
3993 struct intel_engine_cs *ring = NULL;
3994 unsigned reset_counter;
3998 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4002 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4006 spin_lock(&file_priv->mm.lock);
4007 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4008 if (time_after_eq(request->emitted_jiffies, recent_enough))
4011 ring = request->ring;
4012 seqno = request->seqno;
4014 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4015 spin_unlock(&file_priv->mm.lock);
4020 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4022 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4028 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4030 struct drm_i915_gem_object *obj = vma->obj;
4033 vma->node.start & (alignment - 1))
4036 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4039 if (flags & PIN_OFFSET_BIAS &&
4040 vma->node.start < (flags & PIN_OFFSET_MASK))
4047 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4048 struct i915_address_space *vm,
4052 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4053 struct i915_vma *vma;
4056 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4059 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4062 vma = i915_gem_obj_to_vma(obj, vm);
4064 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4067 if (i915_vma_misplaced(vma, alignment, flags)) {
4068 WARN(vma->pin_count,
4069 "bo is already pinned with incorrect alignment:"
4070 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4071 " obj->map_and_fenceable=%d\n",
4072 i915_gem_obj_offset(obj, vm), alignment,
4073 !!(flags & PIN_MAPPABLE),
4074 obj->map_and_fenceable);
4075 ret = i915_vma_unbind(vma);
4083 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4084 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4086 return PTR_ERR(vma);
4089 if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
4090 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4093 if (flags & PIN_MAPPABLE)
4094 obj->pin_mappable |= true;
4100 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4102 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4105 BUG_ON(vma->pin_count == 0);
4106 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4108 if (--vma->pin_count == 0)
4109 obj->pin_mappable = false;
4113 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4115 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4116 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4117 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4119 WARN_ON(!ggtt_vma ||
4120 dev_priv->fence_regs[obj->fence_reg].pin_count >
4121 ggtt_vma->pin_count);
4122 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4129 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4131 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4132 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4133 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4134 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4139 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4140 struct drm_file *file)
4142 struct drm_i915_gem_pin *args = data;
4143 struct drm_i915_gem_object *obj;
4146 if (INTEL_INFO(dev)->gen >= 6)
4149 ret = i915_mutex_lock_interruptible(dev);
4153 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4154 if (&obj->base == NULL) {
4159 if (obj->madv != I915_MADV_WILLNEED) {
4160 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4165 if (obj->pin_filp != NULL && obj->pin_filp != file) {
4166 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4172 if (obj->user_pin_count == ULONG_MAX) {
4177 if (obj->user_pin_count == 0) {
4178 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4183 obj->user_pin_count++;
4184 obj->pin_filp = file;
4186 args->offset = i915_gem_obj_ggtt_offset(obj);
4188 drm_gem_object_unreference(&obj->base);
4190 mutex_unlock(&dev->struct_mutex);
4195 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4196 struct drm_file *file)
4198 struct drm_i915_gem_pin *args = data;
4199 struct drm_i915_gem_object *obj;
4202 ret = i915_mutex_lock_interruptible(dev);
4206 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4207 if (&obj->base == NULL) {
4212 if (obj->pin_filp != file) {
4213 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4218 obj->user_pin_count--;
4219 if (obj->user_pin_count == 0) {
4220 obj->pin_filp = NULL;
4221 i915_gem_object_ggtt_unpin(obj);
4225 drm_gem_object_unreference(&obj->base);
4227 mutex_unlock(&dev->struct_mutex);
4232 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4233 struct drm_file *file)
4235 struct drm_i915_gem_busy *args = data;
4236 struct drm_i915_gem_object *obj;
4239 ret = i915_mutex_lock_interruptible(dev);
4243 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4244 if (&obj->base == NULL) {
4249 /* Count all active objects as busy, even if they are currently not used
4250 * by the gpu. Users of this interface expect objects to eventually
4251 * become non-busy without any further actions, therefore emit any
4252 * necessary flushes here.
4254 ret = i915_gem_object_flush_active(obj);
4256 args->busy = obj->active;
4258 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4259 args->busy |= intel_ring_flag(obj->ring) << 16;
4262 drm_gem_object_unreference(&obj->base);
4264 mutex_unlock(&dev->struct_mutex);
4269 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4270 struct drm_file *file_priv)
4272 return i915_gem_ring_throttle(dev, file_priv);
4276 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4277 struct drm_file *file_priv)
4279 struct drm_i915_gem_madvise *args = data;
4280 struct drm_i915_gem_object *obj;
4283 switch (args->madv) {
4284 case I915_MADV_DONTNEED:
4285 case I915_MADV_WILLNEED:
4291 ret = i915_mutex_lock_interruptible(dev);
4295 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4296 if (&obj->base == NULL) {
4301 if (i915_gem_obj_is_pinned(obj)) {
4306 if (obj->madv != __I915_MADV_PURGED)
4307 obj->madv = args->madv;
4309 /* if the object is no longer attached, discard its backing storage */
4310 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4311 i915_gem_object_truncate(obj);
4313 args->retained = obj->madv != __I915_MADV_PURGED;
4316 drm_gem_object_unreference(&obj->base);
4318 mutex_unlock(&dev->struct_mutex);
4322 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4323 const struct drm_i915_gem_object_ops *ops)
4325 INIT_LIST_HEAD(&obj->global_list);
4326 INIT_LIST_HEAD(&obj->ring_list);
4327 INIT_LIST_HEAD(&obj->obj_exec_link);
4328 INIT_LIST_HEAD(&obj->vma_list);
4332 obj->fence_reg = I915_FENCE_REG_NONE;
4333 obj->madv = I915_MADV_WILLNEED;
4334 /* Avoid an unnecessary call to unbind on the first bind. */
4335 obj->map_and_fenceable = true;
4337 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4340 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4341 .get_pages = i915_gem_object_get_pages_gtt,
4342 .put_pages = i915_gem_object_put_pages_gtt,
4345 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4348 struct drm_i915_gem_object *obj;
4349 struct address_space *mapping;
4352 obj = i915_gem_object_alloc(dev);
4356 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4357 i915_gem_object_free(obj);
4361 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4362 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4363 /* 965gm cannot relocate objects above 4GiB. */
4364 mask &= ~__GFP_HIGHMEM;
4365 mask |= __GFP_DMA32;
4368 mapping = file_inode(obj->base.filp)->i_mapping;
4369 mapping_set_gfp_mask(mapping, mask);
4371 i915_gem_object_init(obj, &i915_gem_object_ops);
4373 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4374 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4377 /* On some devices, we can have the GPU use the LLC (the CPU
4378 * cache) for about a 10% performance improvement
4379 * compared to uncached. Graphics requests other than
4380 * display scanout are coherent with the CPU in
4381 * accessing this cache. This means in this mode we
4382 * don't need to clflush on the CPU side, and on the
4383 * GPU side we only need to flush internal caches to
4384 * get data visible to the CPU.
4386 * However, we maintain the display planes as UC, and so
4387 * need to rebind when first used as such.
4389 obj->cache_level = I915_CACHE_LLC;
4391 obj->cache_level = I915_CACHE_NONE;
4393 trace_i915_gem_object_create(obj);
4398 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4400 /* If we are the last user of the backing storage (be it shmemfs
4401 * pages or stolen etc), we know that the pages are going to be
4402 * immediately released. In this case, we can then skip copying
4403 * back the contents from the GPU.
4406 if (obj->madv != I915_MADV_WILLNEED)
4409 if (obj->base.filp == NULL)
4412 /* At first glance, this looks racy, but then again so would be
4413 * userspace racing mmap against close. However, the first external
4414 * reference to the filp can only be obtained through the
4415 * i915_gem_mmap_ioctl() which safeguards us against the user
4416 * acquiring such a reference whilst we are in the middle of
4417 * freeing the object.
4419 return atomic_long_read(&obj->base.filp->f_count) == 1;
4422 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4424 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4425 struct drm_device *dev = obj->base.dev;
4426 struct drm_i915_private *dev_priv = dev->dev_private;
4427 struct i915_vma *vma, *next;
4429 intel_runtime_pm_get(dev_priv);
4431 trace_i915_gem_object_destroy(obj);
4433 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4437 ret = i915_vma_unbind(vma);
4438 if (WARN_ON(ret == -ERESTARTSYS)) {
4439 bool was_interruptible;
4441 was_interruptible = dev_priv->mm.interruptible;
4442 dev_priv->mm.interruptible = false;
4444 WARN_ON(i915_vma_unbind(vma));
4446 dev_priv->mm.interruptible = was_interruptible;
4450 i915_gem_object_detach_phys(obj);
4452 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4453 * before progressing. */
4455 i915_gem_object_unpin_pages(obj);
4457 WARN_ON(obj->frontbuffer_bits);
4459 if (WARN_ON(obj->pages_pin_count))
4460 obj->pages_pin_count = 0;
4461 if (discard_backing_storage(obj))
4462 obj->madv = I915_MADV_DONTNEED;
4463 i915_gem_object_put_pages(obj);
4464 i915_gem_object_free_mmap_offset(obj);
4468 if (obj->base.import_attach)
4469 drm_prime_gem_destroy(&obj->base, NULL);
4471 if (obj->ops->release)
4472 obj->ops->release(obj);
4474 drm_gem_object_release(&obj->base);
4475 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4478 i915_gem_object_free(obj);
4480 intel_runtime_pm_put(dev_priv);
4483 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4484 struct i915_address_space *vm)
4486 struct i915_vma *vma;
4487 list_for_each_entry(vma, &obj->vma_list, vma_link)
4494 void i915_gem_vma_destroy(struct i915_vma *vma)
4496 WARN_ON(vma->node.allocated);
4498 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4499 if (!list_empty(&vma->exec_list))
4502 list_del(&vma->vma_link);
4508 i915_gem_stop_ringbuffers(struct drm_device *dev)
4510 struct drm_i915_private *dev_priv = dev->dev_private;
4511 struct intel_engine_cs *ring;
4514 for_each_ring(ring, dev_priv, i)
4515 intel_stop_ring_buffer(ring);
4519 i915_gem_suspend(struct drm_device *dev)
4521 struct drm_i915_private *dev_priv = dev->dev_private;
4524 mutex_lock(&dev->struct_mutex);
4525 if (dev_priv->ums.mm_suspended)
4528 ret = i915_gpu_idle(dev);
4532 i915_gem_retire_requests(dev);
4534 /* Under UMS, be paranoid and evict. */
4535 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4536 i915_gem_evict_everything(dev);
4538 i915_kernel_lost_context(dev);
4539 i915_gem_stop_ringbuffers(dev);
4541 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4542 * We need to replace this with a semaphore, or something.
4543 * And not confound ums.mm_suspended!
4545 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4547 mutex_unlock(&dev->struct_mutex);
4549 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4550 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4551 flush_delayed_work(&dev_priv->mm.idle_work);
4556 mutex_unlock(&dev->struct_mutex);
4560 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4562 struct drm_device *dev = ring->dev;
4563 struct drm_i915_private *dev_priv = dev->dev_private;
4564 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4565 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4568 if (!HAS_L3_DPF(dev) || !remap_info)
4571 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4576 * Note: We do not worry about the concurrent register cacheline hang
4577 * here because no other code should access these registers other than
4578 * at initialization time.
4580 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4581 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4582 intel_ring_emit(ring, reg_base + i);
4583 intel_ring_emit(ring, remap_info[i/4]);
4586 intel_ring_advance(ring);
4591 void i915_gem_init_swizzling(struct drm_device *dev)
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4595 if (INTEL_INFO(dev)->gen < 5 ||
4596 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4599 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4600 DISP_TILE_SURFACE_SWIZZLING);
4605 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4607 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4608 else if (IS_GEN7(dev))
4609 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4610 else if (IS_GEN8(dev))
4611 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4617 intel_enable_blt(struct drm_device *dev)
4622 /* The blitter was dysfunctional on early prototypes */
4623 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4624 DRM_INFO("BLT not supported on this pre-production hardware;"
4625 " graphics performance will be degraded.\n");
4632 static int i915_gem_init_rings(struct drm_device *dev)
4634 struct drm_i915_private *dev_priv = dev->dev_private;
4637 ret = intel_init_render_ring_buffer(dev);
4642 ret = intel_init_bsd_ring_buffer(dev);
4644 goto cleanup_render_ring;
4647 if (intel_enable_blt(dev)) {
4648 ret = intel_init_blt_ring_buffer(dev);
4650 goto cleanup_bsd_ring;
4653 if (HAS_VEBOX(dev)) {
4654 ret = intel_init_vebox_ring_buffer(dev);
4656 goto cleanup_blt_ring;
4659 if (HAS_BSD2(dev)) {
4660 ret = intel_init_bsd2_ring_buffer(dev);
4662 goto cleanup_vebox_ring;
4665 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4667 goto cleanup_bsd2_ring;
4672 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4674 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4676 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4678 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4679 cleanup_render_ring:
4680 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4686 i915_gem_init_hw(struct drm_device *dev)
4688 struct drm_i915_private *dev_priv = dev->dev_private;
4691 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4694 if (dev_priv->ellc_size)
4695 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4697 if (IS_HASWELL(dev))
4698 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4699 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4701 if (HAS_PCH_NOP(dev)) {
4702 if (IS_IVYBRIDGE(dev)) {
4703 u32 temp = I915_READ(GEN7_MSG_CTL);
4704 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4705 I915_WRITE(GEN7_MSG_CTL, temp);
4706 } else if (INTEL_INFO(dev)->gen >= 7) {
4707 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4708 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4709 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4713 i915_gem_init_swizzling(dev);
4715 ret = i915_gem_init_rings(dev);
4719 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4720 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4723 * XXX: Contexts should only be initialized once. Doing a switch to the
4724 * default context switch however is something we'd like to do after
4725 * reset or thaw (the latter may not actually be necessary for HW, but
4726 * goes with our code better). Context switching requires rings (for
4727 * the do_switch), but before enabling PPGTT. So don't move this.
4729 ret = i915_gem_context_enable(dev_priv);
4730 if (ret && ret != -EIO) {
4731 DRM_ERROR("Context enable failed %d\n", ret);
4732 i915_gem_cleanup_ringbuffer(dev);
4738 int i915_gem_init(struct drm_device *dev)
4740 struct drm_i915_private *dev_priv = dev->dev_private;
4743 mutex_lock(&dev->struct_mutex);
4745 if (IS_VALLEYVIEW(dev)) {
4746 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4747 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4748 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4749 VLV_GTLC_ALLOWWAKEACK), 10))
4750 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4753 i915_gem_init_userptr(dev);
4754 i915_gem_init_global_gtt(dev);
4756 ret = i915_gem_context_init(dev);
4758 mutex_unlock(&dev->struct_mutex);
4762 ret = i915_gem_init_hw(dev);
4764 /* Allow ring initialisation to fail by marking the GPU as
4765 * wedged. But we only want to do this where the GPU is angry,
4766 * for all other failure, such as an allocation failure, bail.
4768 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4769 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4772 mutex_unlock(&dev->struct_mutex);
4774 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4775 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4776 dev_priv->dri1.allow_batchbuffer = 1;
4781 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4783 struct drm_i915_private *dev_priv = dev->dev_private;
4784 struct intel_engine_cs *ring;
4787 for_each_ring(ring, dev_priv, i)
4788 intel_cleanup_ring_buffer(ring);
4792 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4793 struct drm_file *file_priv)
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4798 if (drm_core_check_feature(dev, DRIVER_MODESET))
4801 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4802 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4803 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4806 mutex_lock(&dev->struct_mutex);
4807 dev_priv->ums.mm_suspended = 0;
4809 ret = i915_gem_init_hw(dev);
4811 mutex_unlock(&dev->struct_mutex);
4815 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4817 ret = drm_irq_install(dev, dev->pdev->irq);
4819 goto cleanup_ringbuffer;
4820 mutex_unlock(&dev->struct_mutex);
4825 i915_gem_cleanup_ringbuffer(dev);
4826 dev_priv->ums.mm_suspended = 1;
4827 mutex_unlock(&dev->struct_mutex);
4833 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4834 struct drm_file *file_priv)
4836 if (drm_core_check_feature(dev, DRIVER_MODESET))
4839 mutex_lock(&dev->struct_mutex);
4840 drm_irq_uninstall(dev);
4841 mutex_unlock(&dev->struct_mutex);
4843 return i915_gem_suspend(dev);
4847 i915_gem_lastclose(struct drm_device *dev)
4851 if (drm_core_check_feature(dev, DRIVER_MODESET))
4854 ret = i915_gem_suspend(dev);
4856 DRM_ERROR("failed to idle hardware: %d\n", ret);
4860 init_ring_lists(struct intel_engine_cs *ring)
4862 INIT_LIST_HEAD(&ring->active_list);
4863 INIT_LIST_HEAD(&ring->request_list);
4866 void i915_init_vm(struct drm_i915_private *dev_priv,
4867 struct i915_address_space *vm)
4869 if (!i915_is_ggtt(vm))
4870 drm_mm_init(&vm->mm, vm->start, vm->total);
4871 vm->dev = dev_priv->dev;
4872 INIT_LIST_HEAD(&vm->active_list);
4873 INIT_LIST_HEAD(&vm->inactive_list);
4874 INIT_LIST_HEAD(&vm->global_link);
4875 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4879 i915_gem_load(struct drm_device *dev)
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4885 kmem_cache_create("i915_gem_object",
4886 sizeof(struct drm_i915_gem_object), 0,
4890 INIT_LIST_HEAD(&dev_priv->vm_list);
4891 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4893 INIT_LIST_HEAD(&dev_priv->context_list);
4894 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4895 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4896 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4897 for (i = 0; i < I915_NUM_RINGS; i++)
4898 init_ring_lists(&dev_priv->ring[i]);
4899 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4900 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4901 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4902 i915_gem_retire_work_handler);
4903 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4904 i915_gem_idle_work_handler);
4905 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4907 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4908 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4909 I915_WRITE(MI_ARB_STATE,
4910 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4913 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4915 /* Old X drivers will take 0-2 for front, back, depth buffers */
4916 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4917 dev_priv->fence_reg_start = 3;
4919 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4920 dev_priv->num_fence_regs = 32;
4921 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4922 dev_priv->num_fence_regs = 16;
4924 dev_priv->num_fence_regs = 8;
4926 /* Initialize fence registers to zero */
4927 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4928 i915_gem_restore_fences(dev);
4930 i915_gem_detect_bit_6_swizzle(dev);
4931 init_waitqueue_head(&dev_priv->pending_flip_queue);
4933 dev_priv->mm.interruptible = true;
4935 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4936 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4937 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4938 register_shrinker(&dev_priv->mm.shrinker);
4940 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4941 register_oom_notifier(&dev_priv->mm.oom_notifier);
4943 mutex_init(&dev_priv->fb_tracking.lock);
4946 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4948 struct drm_i915_file_private *file_priv = file->driver_priv;
4950 cancel_delayed_work_sync(&file_priv->mm.idle_work);
4952 /* Clean up our request list when the client is going away, so that
4953 * later retire_requests won't dereference our soon-to-be-gone
4956 spin_lock(&file_priv->mm.lock);
4957 while (!list_empty(&file_priv->mm.request_list)) {
4958 struct drm_i915_gem_request *request;
4960 request = list_first_entry(&file_priv->mm.request_list,
4961 struct drm_i915_gem_request,
4963 list_del(&request->client_list);
4964 request->file_priv = NULL;
4966 spin_unlock(&file_priv->mm.lock);
4970 i915_gem_file_idle_work_handler(struct work_struct *work)
4972 struct drm_i915_file_private *file_priv =
4973 container_of(work, typeof(*file_priv), mm.idle_work.work);
4975 atomic_set(&file_priv->rps_wait_boost, false);
4978 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4980 struct drm_i915_file_private *file_priv;
4983 DRM_DEBUG_DRIVER("\n");
4985 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4989 file->driver_priv = file_priv;
4990 file_priv->dev_priv = dev->dev_private;
4991 file_priv->file = file;
4993 spin_lock_init(&file_priv->mm.lock);
4994 INIT_LIST_HEAD(&file_priv->mm.request_list);
4995 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4996 i915_gem_file_idle_work_handler);
4998 ret = i915_gem_context_open(dev, file);
5005 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5006 struct drm_i915_gem_object *new,
5007 unsigned frontbuffer_bits)
5010 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5011 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5012 old->frontbuffer_bits &= ~frontbuffer_bits;
5016 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5017 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5018 new->frontbuffer_bits |= frontbuffer_bits;
5022 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5024 if (!mutex_is_locked(mutex))
5027 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5028 return mutex->owner == task;
5030 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5035 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5037 if (!mutex_trylock(&dev->struct_mutex)) {
5038 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5041 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5051 static int num_vma_bound(struct drm_i915_gem_object *obj)
5053 struct i915_vma *vma;
5056 list_for_each_entry(vma, &obj->vma_list, vma_link)
5057 if (drm_mm_node_allocated(&vma->node))
5063 static unsigned long
5064 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5066 struct drm_i915_private *dev_priv =
5067 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5068 struct drm_device *dev = dev_priv->dev;
5069 struct drm_i915_gem_object *obj;
5070 unsigned long count;
5073 if (!i915_gem_shrinker_lock(dev, &unlock))
5077 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5078 if (obj->pages_pin_count == 0)
5079 count += obj->base.size >> PAGE_SHIFT;
5081 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5082 if (!i915_gem_obj_is_pinned(obj) &&
5083 obj->pages_pin_count == num_vma_bound(obj))
5084 count += obj->base.size >> PAGE_SHIFT;
5088 mutex_unlock(&dev->struct_mutex);
5093 /* All the new VM stuff */
5094 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5095 struct i915_address_space *vm)
5097 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5098 struct i915_vma *vma;
5100 if (!dev_priv->mm.aliasing_ppgtt ||
5101 vm == &dev_priv->mm.aliasing_ppgtt->base)
5102 vm = &dev_priv->gtt.base;
5104 list_for_each_entry(vma, &o->vma_list, vma_link) {
5106 return vma->node.start;
5109 WARN(1, "%s vma for this object not found.\n",
5110 i915_is_ggtt(vm) ? "global" : "ppgtt");
5114 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5115 struct i915_address_space *vm)
5117 struct i915_vma *vma;
5119 list_for_each_entry(vma, &o->vma_list, vma_link)
5120 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5126 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5128 struct i915_vma *vma;
5130 list_for_each_entry(vma, &o->vma_list, vma_link)
5131 if (drm_mm_node_allocated(&vma->node))
5137 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5138 struct i915_address_space *vm)
5140 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5141 struct i915_vma *vma;
5143 if (!dev_priv->mm.aliasing_ppgtt ||
5144 vm == &dev_priv->mm.aliasing_ppgtt->base)
5145 vm = &dev_priv->gtt.base;
5147 BUG_ON(list_empty(&o->vma_list));
5149 list_for_each_entry(vma, &o->vma_list, vma_link)
5151 return vma->node.size;
5156 static unsigned long
5157 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5159 struct drm_i915_private *dev_priv =
5160 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5161 struct drm_device *dev = dev_priv->dev;
5162 unsigned long freed;
5165 if (!i915_gem_shrinker_lock(dev, &unlock))
5168 freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5169 if (freed < sc->nr_to_scan)
5170 freed += __i915_gem_shrink(dev_priv,
5171 sc->nr_to_scan - freed,
5174 mutex_unlock(&dev->struct_mutex);
5180 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5182 struct drm_i915_private *dev_priv =
5183 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5184 struct drm_device *dev = dev_priv->dev;
5185 struct drm_i915_gem_object *obj;
5186 unsigned long timeout = msecs_to_jiffies(5000) + 1;
5187 unsigned long pinned, bound, unbound, freed;
5188 bool was_interruptible;
5191 while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5192 schedule_timeout_killable(1);
5193 if (fatal_signal_pending(current))
5197 pr_err("Unable to purge GPU memory due lock contention.\n");
5201 was_interruptible = dev_priv->mm.interruptible;
5202 dev_priv->mm.interruptible = false;
5204 freed = i915_gem_shrink_all(dev_priv);
5206 dev_priv->mm.interruptible = was_interruptible;
5208 /* Because we may be allocating inside our own driver, we cannot
5209 * assert that there are no objects with pinned pages that are not
5210 * being pointed to by hardware.
5212 unbound = bound = pinned = 0;
5213 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5214 if (!obj->base.filp) /* not backed by a freeable object */
5217 if (obj->pages_pin_count)
5218 pinned += obj->base.size;
5220 unbound += obj->base.size;
5222 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5223 if (!obj->base.filp)
5226 if (obj->pages_pin_count)
5227 pinned += obj->base.size;
5229 bound += obj->base.size;
5233 mutex_unlock(&dev->struct_mutex);
5235 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5237 if (unbound || bound)
5238 pr_err("%lu and %lu bytes still available in the "
5239 "bound and unbound GPU page lists.\n",
5242 *(unsigned long *)ptr += freed;
5246 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5248 struct i915_vma *vma;
5250 /* This WARN has probably outlived its usefulness (callers already
5251 * WARN if they don't find the GGTT vma they expect). When removing,
5252 * remember to remove the pre-check in is_pin_display() as well */
5253 if (WARN_ON(list_empty(&obj->vma_list)))
5256 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5257 if (vma->vm != obj_to_ggtt(obj))