2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
43 static __must_check int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
46 static __must_check int
47 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
48 struct i915_address_space *vm,
50 bool map_and_fenceable,
52 static int i915_gem_phys_pwrite(struct drm_device *dev,
53 struct drm_i915_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file);
57 static void i915_gem_write_fence(struct drm_device *dev, int reg,
58 struct drm_i915_gem_object *obj);
59 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
60 struct drm_i915_fence_reg *fence,
63 static unsigned long i915_gem_inactive_count(struct shrinker *shrinker,
64 struct shrink_control *sc);
65 static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker,
66 struct shrink_control *sc);
67 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
68 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
69 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
71 static bool cpu_cache_is_coherent(struct drm_device *dev,
72 enum i915_cache_level level)
74 return HAS_LLC(dev) || level != I915_CACHE_NONE;
77 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
79 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
82 return obj->pin_display;
85 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
88 i915_gem_release_mmap(obj);
90 /* As we do not have an associated fence register, we will force
91 * a tiling change if we ever need to acquire one.
93 obj->fence_dirty = false;
94 obj->fence_reg = I915_FENCE_REG_NONE;
97 /* some bookkeeping */
98 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
101 spin_lock(&dev_priv->mm.object_stat_lock);
102 dev_priv->mm.object_count++;
103 dev_priv->mm.object_memory += size;
104 spin_unlock(&dev_priv->mm.object_stat_lock);
107 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
110 spin_lock(&dev_priv->mm.object_stat_lock);
111 dev_priv->mm.object_count--;
112 dev_priv->mm.object_memory -= size;
113 spin_unlock(&dev_priv->mm.object_stat_lock);
117 i915_gem_wait_for_error(struct i915_gpu_error *error)
121 #define EXIT_COND (!i915_reset_in_progress(error) || \
122 i915_terminally_wedged(error))
127 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
128 * userspace. If it takes that long something really bad is going on and
129 * we should simply try to bail out and fail as gracefully as possible.
131 ret = wait_event_interruptible_timeout(error->reset_queue,
135 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
137 } else if (ret < 0) {
145 int i915_mutex_lock_interruptible(struct drm_device *dev)
147 struct drm_i915_private *dev_priv = dev->dev_private;
150 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
154 ret = mutex_lock_interruptible(&dev->struct_mutex);
158 WARN_ON(i915_verify_lists(dev));
163 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
165 return i915_gem_obj_bound_any(obj) && !obj->active;
169 i915_gem_init_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_init *args = data;
175 if (drm_core_check_feature(dev, DRIVER_MODESET))
178 if (args->gtt_start >= args->gtt_end ||
179 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
182 /* GEM with user mode setting was never supported on ilk and later. */
183 if (INTEL_INFO(dev)->gen >= 5)
186 mutex_lock(&dev->struct_mutex);
187 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
189 dev_priv->gtt.mappable_end = args->gtt_end;
190 mutex_unlock(&dev->struct_mutex);
196 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
197 struct drm_file *file)
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_i915_gem_get_aperture *args = data;
201 struct drm_i915_gem_object *obj;
205 mutex_lock(&dev->struct_mutex);
206 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
207 if (i915_gem_obj_is_pinned(obj))
208 pinned += i915_gem_obj_ggtt_size(obj);
209 mutex_unlock(&dev->struct_mutex);
211 args->aper_size = dev_priv->gtt.base.total;
212 args->aper_available_size = args->aper_size - pinned;
217 void *i915_gem_object_alloc(struct drm_device *dev)
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
223 void i915_gem_object_free(struct drm_i915_gem_object *obj)
225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
226 kmem_cache_free(dev_priv->slab, obj);
230 i915_gem_create(struct drm_file *file,
231 struct drm_device *dev,
235 struct drm_i915_gem_object *obj;
239 size = roundup(size, PAGE_SIZE);
243 /* Allocate the new object */
244 obj = i915_gem_alloc_object(dev, size);
248 ret = drm_gem_handle_create(file, &obj->base, &handle);
249 /* drop reference from allocate - handle holds it now */
250 drm_gem_object_unreference_unlocked(&obj->base);
259 i915_gem_dumb_create(struct drm_file *file,
260 struct drm_device *dev,
261 struct drm_mode_create_dumb *args)
263 /* have to work out size/pitch and return them */
264 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
265 args->size = args->pitch * args->height;
266 return i915_gem_create(file, dev,
267 args->size, &args->handle);
271 * Creates a new mm object and returns a handle to it.
274 i915_gem_create_ioctl(struct drm_device *dev, void *data,
275 struct drm_file *file)
277 struct drm_i915_gem_create *args = data;
279 return i915_gem_create(file, dev,
280 args->size, &args->handle);
284 __copy_to_user_swizzled(char __user *cpu_vaddr,
285 const char *gpu_vaddr, int gpu_offset,
288 int ret, cpu_offset = 0;
291 int cacheline_end = ALIGN(gpu_offset + 1, 64);
292 int this_length = min(cacheline_end - gpu_offset, length);
293 int swizzled_gpu_offset = gpu_offset ^ 64;
295 ret = __copy_to_user(cpu_vaddr + cpu_offset,
296 gpu_vaddr + swizzled_gpu_offset,
301 cpu_offset += this_length;
302 gpu_offset += this_length;
303 length -= this_length;
310 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
311 const char __user *cpu_vaddr,
314 int ret, cpu_offset = 0;
317 int cacheline_end = ALIGN(gpu_offset + 1, 64);
318 int this_length = min(cacheline_end - gpu_offset, length);
319 int swizzled_gpu_offset = gpu_offset ^ 64;
321 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
322 cpu_vaddr + cpu_offset,
327 cpu_offset += this_length;
328 gpu_offset += this_length;
329 length -= this_length;
335 /* Per-page copy function for the shmem pread fastpath.
336 * Flushes invalid cachelines before reading the target if
337 * needs_clflush is set. */
339 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
340 char __user *user_data,
341 bool page_do_bit17_swizzling, bool needs_clflush)
346 if (unlikely(page_do_bit17_swizzling))
349 vaddr = kmap_atomic(page);
351 drm_clflush_virt_range(vaddr + shmem_page_offset,
353 ret = __copy_to_user_inatomic(user_data,
354 vaddr + shmem_page_offset,
356 kunmap_atomic(vaddr);
358 return ret ? -EFAULT : 0;
362 shmem_clflush_swizzled_range(char *addr, unsigned long length,
365 if (unlikely(swizzled)) {
366 unsigned long start = (unsigned long) addr;
367 unsigned long end = (unsigned long) addr + length;
369 /* For swizzling simply ensure that we always flush both
370 * channels. Lame, but simple and it works. Swizzled
371 * pwrite/pread is far from a hotpath - current userspace
372 * doesn't use it at all. */
373 start = round_down(start, 128);
374 end = round_up(end, 128);
376 drm_clflush_virt_range((void *)start, end - start);
378 drm_clflush_virt_range(addr, length);
383 /* Only difference to the fast-path function is that this can handle bit17
384 * and uses non-atomic copy and kmap functions. */
386 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
387 char __user *user_data,
388 bool page_do_bit17_swizzling, bool needs_clflush)
395 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
397 page_do_bit17_swizzling);
399 if (page_do_bit17_swizzling)
400 ret = __copy_to_user_swizzled(user_data,
401 vaddr, shmem_page_offset,
404 ret = __copy_to_user(user_data,
405 vaddr + shmem_page_offset,
409 return ret ? - EFAULT : 0;
413 i915_gem_shmem_pread(struct drm_device *dev,
414 struct drm_i915_gem_object *obj,
415 struct drm_i915_gem_pread *args,
416 struct drm_file *file)
418 char __user *user_data;
421 int shmem_page_offset, page_length, ret = 0;
422 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
424 int needs_clflush = 0;
425 struct sg_page_iter sg_iter;
427 user_data = to_user_ptr(args->data_ptr);
430 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
432 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
433 /* If we're not in the cpu read domain, set ourself into the gtt
434 * read domain and manually flush cachelines (if required). This
435 * optimizes for the case when the gpu will dirty the data
436 * anyway again before the next pread happens. */
437 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
438 ret = i915_gem_object_wait_rendering(obj, true);
443 ret = i915_gem_object_get_pages(obj);
447 i915_gem_object_pin_pages(obj);
449 offset = args->offset;
451 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
452 offset >> PAGE_SHIFT) {
453 struct page *page = sg_page_iter_page(&sg_iter);
458 /* Operation in this page
460 * shmem_page_offset = offset within page in shmem file
461 * page_length = bytes to copy for this page
463 shmem_page_offset = offset_in_page(offset);
464 page_length = remain;
465 if ((shmem_page_offset + page_length) > PAGE_SIZE)
466 page_length = PAGE_SIZE - shmem_page_offset;
468 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
469 (page_to_phys(page) & (1 << 17)) != 0;
471 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
472 user_data, page_do_bit17_swizzling,
477 mutex_unlock(&dev->struct_mutex);
479 if (likely(!i915.prefault_disable) && !prefaulted) {
480 ret = fault_in_multipages_writeable(user_data, remain);
481 /* Userspace is tricking us, but we've already clobbered
482 * its pages with the prefault and promised to write the
483 * data up to the first fault. Hence ignore any errors
484 * and just continue. */
489 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
490 user_data, page_do_bit17_swizzling,
493 mutex_lock(&dev->struct_mutex);
496 mark_page_accessed(page);
501 remain -= page_length;
502 user_data += page_length;
503 offset += page_length;
507 i915_gem_object_unpin_pages(obj);
513 * Reads data from the object referenced by handle.
515 * On error, the contents of *data are undefined.
518 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
519 struct drm_file *file)
521 struct drm_i915_gem_pread *args = data;
522 struct drm_i915_gem_object *obj;
528 if (!access_ok(VERIFY_WRITE,
529 to_user_ptr(args->data_ptr),
533 ret = i915_mutex_lock_interruptible(dev);
537 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
538 if (&obj->base == NULL) {
543 /* Bounds check source. */
544 if (args->offset > obj->base.size ||
545 args->size > obj->base.size - args->offset) {
550 /* prime objects have no backing filp to GEM pread/pwrite
553 if (!obj->base.filp) {
558 trace_i915_gem_object_pread(obj, args->offset, args->size);
560 ret = i915_gem_shmem_pread(dev, obj, args, file);
563 drm_gem_object_unreference(&obj->base);
565 mutex_unlock(&dev->struct_mutex);
569 /* This is the fast write path which cannot handle
570 * page faults in the source data
574 fast_user_write(struct io_mapping *mapping,
575 loff_t page_base, int page_offset,
576 char __user *user_data,
579 void __iomem *vaddr_atomic;
581 unsigned long unwritten;
583 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
584 /* We can use the cpu mem copy function because this is X86. */
585 vaddr = (void __force*)vaddr_atomic + page_offset;
586 unwritten = __copy_from_user_inatomic_nocache(vaddr,
588 io_mapping_unmap_atomic(vaddr_atomic);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
598 struct drm_i915_gem_object *obj,
599 struct drm_i915_gem_pwrite *args,
600 struct drm_file *file)
602 drm_i915_private_t *dev_priv = dev->dev_private;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length, ret;
608 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
612 ret = i915_gem_object_set_to_gtt_domain(obj, true);
616 ret = i915_gem_object_put_fence(obj);
620 user_data = to_user_ptr(args->data_ptr);
623 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
626 /* Operation in this page
628 * page_base = page offset within aperture
629 * page_offset = offset within page
630 * page_length = bytes to copy for this page
632 page_base = offset & PAGE_MASK;
633 page_offset = offset_in_page(offset);
634 page_length = remain;
635 if ((page_offset + remain) > PAGE_SIZE)
636 page_length = PAGE_SIZE - page_offset;
638 /* If we get a fault while copying data, then (presumably) our
639 * source page isn't available. Return the error and we'll
640 * retry in the slow path.
642 if (fast_user_write(dev_priv->gtt.mappable, page_base,
643 page_offset, user_data, page_length)) {
648 remain -= page_length;
649 user_data += page_length;
650 offset += page_length;
654 i915_gem_object_ggtt_unpin(obj);
659 /* Per-page copy function for the shmem pwrite fastpath.
660 * Flushes invalid cachelines before writing to the target if
661 * needs_clflush_before is set and flushes out any written cachelines after
662 * writing if needs_clflush is set. */
664 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
665 char __user *user_data,
666 bool page_do_bit17_swizzling,
667 bool needs_clflush_before,
668 bool needs_clflush_after)
673 if (unlikely(page_do_bit17_swizzling))
676 vaddr = kmap_atomic(page);
677 if (needs_clflush_before)
678 drm_clflush_virt_range(vaddr + shmem_page_offset,
680 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
683 if (needs_clflush_after)
684 drm_clflush_virt_range(vaddr + shmem_page_offset,
686 kunmap_atomic(vaddr);
688 return ret ? -EFAULT : 0;
691 /* Only difference to the fast-path function is that this can handle bit17
692 * and uses non-atomic copy and kmap functions. */
694 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
695 char __user *user_data,
696 bool page_do_bit17_swizzling,
697 bool needs_clflush_before,
698 bool needs_clflush_after)
704 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
705 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
707 page_do_bit17_swizzling);
708 if (page_do_bit17_swizzling)
709 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
713 ret = __copy_from_user(vaddr + shmem_page_offset,
716 if (needs_clflush_after)
717 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
719 page_do_bit17_swizzling);
722 return ret ? -EFAULT : 0;
726 i915_gem_shmem_pwrite(struct drm_device *dev,
727 struct drm_i915_gem_object *obj,
728 struct drm_i915_gem_pwrite *args,
729 struct drm_file *file)
733 char __user *user_data;
734 int shmem_page_offset, page_length, ret = 0;
735 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
736 int hit_slowpath = 0;
737 int needs_clflush_after = 0;
738 int needs_clflush_before = 0;
739 struct sg_page_iter sg_iter;
741 user_data = to_user_ptr(args->data_ptr);
744 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
746 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
747 /* If we're not in the cpu write domain, set ourself into the gtt
748 * write domain and manually flush cachelines (if required). This
749 * optimizes for the case when the gpu will use the data
750 * right away and we therefore have to clflush anyway. */
751 needs_clflush_after = cpu_write_needs_clflush(obj);
752 ret = i915_gem_object_wait_rendering(obj, false);
756 /* Same trick applies to invalidate partially written cachelines read
758 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
759 needs_clflush_before =
760 !cpu_cache_is_coherent(dev, obj->cache_level);
762 ret = i915_gem_object_get_pages(obj);
766 i915_gem_object_pin_pages(obj);
768 offset = args->offset;
771 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
772 offset >> PAGE_SHIFT) {
773 struct page *page = sg_page_iter_page(&sg_iter);
774 int partial_cacheline_write;
779 /* Operation in this page
781 * shmem_page_offset = offset within page in shmem file
782 * page_length = bytes to copy for this page
784 shmem_page_offset = offset_in_page(offset);
786 page_length = remain;
787 if ((shmem_page_offset + page_length) > PAGE_SIZE)
788 page_length = PAGE_SIZE - shmem_page_offset;
790 /* If we don't overwrite a cacheline completely we need to be
791 * careful to have up-to-date data by first clflushing. Don't
792 * overcomplicate things and flush the entire patch. */
793 partial_cacheline_write = needs_clflush_before &&
794 ((shmem_page_offset | page_length)
795 & (boot_cpu_data.x86_clflush_size - 1));
797 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
798 (page_to_phys(page) & (1 << 17)) != 0;
800 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
801 user_data, page_do_bit17_swizzling,
802 partial_cacheline_write,
803 needs_clflush_after);
808 mutex_unlock(&dev->struct_mutex);
809 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
810 user_data, page_do_bit17_swizzling,
811 partial_cacheline_write,
812 needs_clflush_after);
814 mutex_lock(&dev->struct_mutex);
817 set_page_dirty(page);
818 mark_page_accessed(page);
823 remain -= page_length;
824 user_data += page_length;
825 offset += page_length;
829 i915_gem_object_unpin_pages(obj);
833 * Fixup: Flush cpu caches in case we didn't flush the dirty
834 * cachelines in-line while writing and the object moved
835 * out of the cpu write domain while we've dropped the lock.
837 if (!needs_clflush_after &&
838 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
839 if (i915_gem_clflush_object(obj, obj->pin_display))
840 i915_gem_chipset_flush(dev);
844 if (needs_clflush_after)
845 i915_gem_chipset_flush(dev);
851 * Writes data to the object referenced by handle.
853 * On error, the contents of the buffer that were to be modified are undefined.
856 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
857 struct drm_file *file)
859 struct drm_i915_gem_pwrite *args = data;
860 struct drm_i915_gem_object *obj;
866 if (!access_ok(VERIFY_READ,
867 to_user_ptr(args->data_ptr),
871 if (likely(!i915.prefault_disable)) {
872 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
878 ret = i915_mutex_lock_interruptible(dev);
882 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
883 if (&obj->base == NULL) {
888 /* Bounds check destination. */
889 if (args->offset > obj->base.size ||
890 args->size > obj->base.size - args->offset) {
895 /* prime objects have no backing filp to GEM pread/pwrite
898 if (!obj->base.filp) {
903 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
906 /* We can only do the GTT pwrite on untiled buffers, as otherwise
907 * it would end up going through the fenced access, and we'll get
908 * different detiling behavior between reading and writing.
909 * pread/pwrite currently are reading and writing from the CPU
910 * perspective, requiring manual detiling by the client.
913 ret = i915_gem_phys_pwrite(dev, obj, args, file);
917 if (obj->tiling_mode == I915_TILING_NONE &&
918 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
919 cpu_write_needs_clflush(obj)) {
920 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
921 /* Note that the gtt paths might fail with non-page-backed user
922 * pointers (e.g. gtt mappings when moving data between
923 * textures). Fallback to the shmem path in that case. */
926 if (ret == -EFAULT || ret == -ENOSPC)
927 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
930 drm_gem_object_unreference(&obj->base);
932 mutex_unlock(&dev->struct_mutex);
937 i915_gem_check_wedge(struct i915_gpu_error *error,
940 if (i915_reset_in_progress(error)) {
941 /* Non-interruptible callers can't handle -EAGAIN, hence return
942 * -EIO unconditionally for these. */
946 /* Recovery complete, but the reset failed ... */
947 if (i915_terminally_wedged(error))
957 * Compare seqno against outstanding lazy request. Emit a request if they are
961 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
965 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
968 if (seqno == ring->outstanding_lazy_seqno)
969 ret = i915_add_request(ring, NULL);
974 static void fake_irq(unsigned long data)
976 wake_up_process((struct task_struct *)data);
979 static bool missed_irq(struct drm_i915_private *dev_priv,
980 struct intel_ring_buffer *ring)
982 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
985 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
987 if (file_priv == NULL)
990 return !atomic_xchg(&file_priv->rps_wait_boost, true);
994 * __wait_seqno - wait until execution of seqno has finished
995 * @ring: the ring expected to report seqno
997 * @reset_counter: reset sequence associated with the given seqno
998 * @interruptible: do an interruptible wait (normally yes)
999 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1001 * Note: It is of utmost importance that the passed in seqno and reset_counter
1002 * values have been read by the caller in an smp safe manner. Where read-side
1003 * locks are involved, it is sufficient to read the reset_counter before
1004 * unlocking the lock that protects the seqno. For lockless tricks, the
1005 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1008 * Returns 0 if the seqno was found within the alloted time. Else returns the
1009 * errno with remaining time filled in timeout argument.
1011 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1012 unsigned reset_counter,
1014 struct timespec *timeout,
1015 struct drm_i915_file_private *file_priv)
1017 struct drm_device *dev = ring->dev;
1018 drm_i915_private_t *dev_priv = dev->dev_private;
1019 const bool irq_test_in_progress =
1020 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1021 struct timespec before, now;
1023 unsigned long timeout_expire;
1026 WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
1028 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1031 timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
1033 if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
1034 gen6_rps_boost(dev_priv);
1036 mod_delayed_work(dev_priv->wq,
1037 &file_priv->mm.idle_work,
1038 msecs_to_jiffies(100));
1041 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1044 /* Record current time in case interrupted by signal, or wedged */
1045 trace_i915_gem_request_wait_begin(ring, seqno);
1046 getrawmonotonic(&before);
1048 struct timer_list timer;
1050 prepare_to_wait(&ring->irq_queue, &wait,
1051 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1053 /* We need to check whether any gpu reset happened in between
1054 * the caller grabbing the seqno and now ... */
1055 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1056 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1057 * is truely gone. */
1058 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1064 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1069 if (interruptible && signal_pending(current)) {
1074 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1079 timer.function = NULL;
1080 if (timeout || missed_irq(dev_priv, ring)) {
1081 unsigned long expire;
1083 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1084 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1085 mod_timer(&timer, expire);
1090 if (timer.function) {
1091 del_singleshot_timer_sync(&timer);
1092 destroy_timer_on_stack(&timer);
1095 getrawmonotonic(&now);
1096 trace_i915_gem_request_wait_end(ring, seqno);
1098 if (!irq_test_in_progress)
1099 ring->irq_put(ring);
1101 finish_wait(&ring->irq_queue, &wait);
1104 struct timespec sleep_time = timespec_sub(now, before);
1105 *timeout = timespec_sub(*timeout, sleep_time);
1106 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1107 set_normalized_timespec(timeout, 0, 0);
1114 * Waits for a sequence number to be signaled, and cleans up the
1115 * request and object lists appropriately for that event.
1118 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1120 struct drm_device *dev = ring->dev;
1121 struct drm_i915_private *dev_priv = dev->dev_private;
1122 bool interruptible = dev_priv->mm.interruptible;
1125 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1128 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1132 ret = i915_gem_check_olr(ring, seqno);
1136 return __wait_seqno(ring, seqno,
1137 atomic_read(&dev_priv->gpu_error.reset_counter),
1138 interruptible, NULL, NULL);
1142 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1143 struct intel_ring_buffer *ring)
1145 i915_gem_retire_requests_ring(ring);
1147 /* Manually manage the write flush as we may have not yet
1148 * retired the buffer.
1150 * Note that the last_write_seqno is always the earlier of
1151 * the two (read/write) seqno, so if we haved successfully waited,
1152 * we know we have passed the last write.
1154 obj->last_write_seqno = 0;
1155 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1161 * Ensures that all rendering to the object has completed and the object is
1162 * safe to unbind from the GTT or access from the CPU.
1164 static __must_check int
1165 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1168 struct intel_ring_buffer *ring = obj->ring;
1172 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1176 ret = i915_wait_seqno(ring, seqno);
1180 return i915_gem_object_wait_rendering__tail(obj, ring);
1183 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1184 * as the object state may change during this call.
1186 static __must_check int
1187 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1188 struct drm_file *file,
1191 struct drm_device *dev = obj->base.dev;
1192 struct drm_i915_private *dev_priv = dev->dev_private;
1193 struct intel_ring_buffer *ring = obj->ring;
1194 unsigned reset_counter;
1198 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1199 BUG_ON(!dev_priv->mm.interruptible);
1201 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1205 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1209 ret = i915_gem_check_olr(ring, seqno);
1213 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1214 mutex_unlock(&dev->struct_mutex);
1215 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file->driver_priv);
1216 mutex_lock(&dev->struct_mutex);
1220 return i915_gem_object_wait_rendering__tail(obj, ring);
1224 * Called when user space prepares to use an object with the CPU, either
1225 * through the mmap ioctl's mapping or a GTT mapping.
1228 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1229 struct drm_file *file)
1231 struct drm_i915_gem_set_domain *args = data;
1232 struct drm_i915_gem_object *obj;
1233 uint32_t read_domains = args->read_domains;
1234 uint32_t write_domain = args->write_domain;
1237 /* Only handle setting domains to types used by the CPU. */
1238 if (write_domain & I915_GEM_GPU_DOMAINS)
1241 if (read_domains & I915_GEM_GPU_DOMAINS)
1244 /* Having something in the write domain implies it's in the read
1245 * domain, and only that read domain. Enforce that in the request.
1247 if (write_domain != 0 && read_domains != write_domain)
1250 ret = i915_mutex_lock_interruptible(dev);
1254 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1255 if (&obj->base == NULL) {
1260 /* Try to flush the object off the GPU without holding the lock.
1261 * We will repeat the flush holding the lock in the normal manner
1262 * to catch cases where we are gazumped.
1264 ret = i915_gem_object_wait_rendering__nonblocking(obj, file, !write_domain);
1268 if (read_domains & I915_GEM_DOMAIN_GTT) {
1269 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1271 /* Silently promote "you're not bound, there was nothing to do"
1272 * to success, since the client was just asking us to
1273 * make sure everything was done.
1278 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1282 drm_gem_object_unreference(&obj->base);
1284 mutex_unlock(&dev->struct_mutex);
1289 * Called when user space has done writes to this buffer
1292 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1293 struct drm_file *file)
1295 struct drm_i915_gem_sw_finish *args = data;
1296 struct drm_i915_gem_object *obj;
1299 ret = i915_mutex_lock_interruptible(dev);
1303 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1304 if (&obj->base == NULL) {
1309 /* Pinned buffers may be scanout, so flush the cache */
1310 if (obj->pin_display)
1311 i915_gem_object_flush_cpu_write_domain(obj, true);
1313 drm_gem_object_unreference(&obj->base);
1315 mutex_unlock(&dev->struct_mutex);
1320 * Maps the contents of an object, returning the address it is mapped
1323 * While the mapping holds a reference on the contents of the object, it doesn't
1324 * imply a ref on the object itself.
1327 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1328 struct drm_file *file)
1330 struct drm_i915_gem_mmap *args = data;
1331 struct drm_gem_object *obj;
1334 obj = drm_gem_object_lookup(dev, file, args->handle);
1338 /* prime objects have no backing filp to GEM mmap
1342 drm_gem_object_unreference_unlocked(obj);
1346 addr = vm_mmap(obj->filp, 0, args->size,
1347 PROT_READ | PROT_WRITE, MAP_SHARED,
1349 drm_gem_object_unreference_unlocked(obj);
1350 if (IS_ERR((void *)addr))
1353 args->addr_ptr = (uint64_t) addr;
1359 * i915_gem_fault - fault a page into the GTT
1360 * vma: VMA in question
1363 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1364 * from userspace. The fault handler takes care of binding the object to
1365 * the GTT (if needed), allocating and programming a fence register (again,
1366 * only if needed based on whether the old reg is still valid or the object
1367 * is tiled) and inserting a new PTE into the faulting process.
1369 * Note that the faulting process may involve evicting existing objects
1370 * from the GTT and/or fence registers to make room. So performance may
1371 * suffer if the GTT working set is large or there are few fence registers
1374 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1376 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1377 struct drm_device *dev = obj->base.dev;
1378 drm_i915_private_t *dev_priv = dev->dev_private;
1379 pgoff_t page_offset;
1382 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1384 intel_runtime_pm_get(dev_priv);
1386 /* We don't use vmf->pgoff since that has the fake offset */
1387 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1390 ret = i915_mutex_lock_interruptible(dev);
1394 trace_i915_gem_object_fault(obj, page_offset, true, write);
1396 /* Access to snoopable pages through the GTT is incoherent. */
1397 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1402 /* Now bind it into the GTT if needed */
1403 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1407 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1411 ret = i915_gem_object_get_fence(obj);
1415 obj->fault_mappable = true;
1417 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1421 /* Finally, remap it using the new GTT offset */
1422 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1424 i915_gem_object_ggtt_unpin(obj);
1426 mutex_unlock(&dev->struct_mutex);
1430 /* If this -EIO is due to a gpu hang, give the reset code a
1431 * chance to clean up the mess. Otherwise return the proper
1433 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
1434 ret = VM_FAULT_SIGBUS;
1439 * EAGAIN means the gpu is hung and we'll wait for the error
1440 * handler to reset everything when re-faulting in
1441 * i915_mutex_lock_interruptible.
1448 * EBUSY is ok: this just means that another thread
1449 * already did the job.
1451 ret = VM_FAULT_NOPAGE;
1458 ret = VM_FAULT_SIGBUS;
1461 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1462 ret = VM_FAULT_SIGBUS;
1466 intel_runtime_pm_put(dev_priv);
1470 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1472 struct i915_vma *vma;
1475 * Only the global gtt is relevant for gtt memory mappings, so restrict
1476 * list traversal to objects bound into the global address space. Note
1477 * that the active list should be empty, but better safe than sorry.
1479 WARN_ON(!list_empty(&dev_priv->gtt.base.active_list));
1480 list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
1481 i915_gem_release_mmap(vma->obj);
1482 list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
1483 i915_gem_release_mmap(vma->obj);
1487 * i915_gem_release_mmap - remove physical page mappings
1488 * @obj: obj in question
1490 * Preserve the reservation of the mmapping with the DRM core code, but
1491 * relinquish ownership of the pages back to the system.
1493 * It is vital that we remove the page mapping if we have mapped a tiled
1494 * object through the GTT and then lose the fence register due to
1495 * resource pressure. Similarly if the object has been moved out of the
1496 * aperture, than pages mapped into userspace must be revoked. Removing the
1497 * mapping will then trigger a page fault on the next user access, allowing
1498 * fixup by i915_gem_fault().
1501 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1503 if (!obj->fault_mappable)
1506 drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
1507 obj->fault_mappable = false;
1511 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1515 if (INTEL_INFO(dev)->gen >= 4 ||
1516 tiling_mode == I915_TILING_NONE)
1519 /* Previous chips need a power-of-two fence region when tiling */
1520 if (INTEL_INFO(dev)->gen == 3)
1521 gtt_size = 1024*1024;
1523 gtt_size = 512*1024;
1525 while (gtt_size < size)
1532 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1533 * @obj: object to check
1535 * Return the required GTT alignment for an object, taking into account
1536 * potential fence register mapping.
1539 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1540 int tiling_mode, bool fenced)
1543 * Minimum alignment is 4k (GTT page size), but might be greater
1544 * if a fence register is needed for the object.
1546 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1547 tiling_mode == I915_TILING_NONE)
1551 * Previous chips need to be aligned to the size of the smallest
1552 * fence register that can contain the object.
1554 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1557 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1559 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1562 if (drm_vma_node_has_offset(&obj->base.vma_node))
1565 dev_priv->mm.shrinker_no_lock_stealing = true;
1567 ret = drm_gem_create_mmap_offset(&obj->base);
1571 /* Badly fragmented mmap space? The only way we can recover
1572 * space is by destroying unwanted objects. We can't randomly release
1573 * mmap_offsets as userspace expects them to be persistent for the
1574 * lifetime of the objects. The closest we can is to release the
1575 * offsets on purgeable objects by truncating it and marking it purged,
1576 * which prevents userspace from ever using that object again.
1578 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1579 ret = drm_gem_create_mmap_offset(&obj->base);
1583 i915_gem_shrink_all(dev_priv);
1584 ret = drm_gem_create_mmap_offset(&obj->base);
1586 dev_priv->mm.shrinker_no_lock_stealing = false;
1591 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1593 drm_gem_free_mmap_offset(&obj->base);
1597 i915_gem_mmap_gtt(struct drm_file *file,
1598 struct drm_device *dev,
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 struct drm_i915_gem_object *obj;
1606 ret = i915_mutex_lock_interruptible(dev);
1610 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1611 if (&obj->base == NULL) {
1616 if (obj->base.size > dev_priv->gtt.mappable_end) {
1621 if (obj->madv != I915_MADV_WILLNEED) {
1622 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1627 ret = i915_gem_object_create_mmap_offset(obj);
1631 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1634 drm_gem_object_unreference(&obj->base);
1636 mutex_unlock(&dev->struct_mutex);
1641 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1643 * @data: GTT mapping ioctl data
1644 * @file: GEM object info
1646 * Simply returns the fake offset to userspace so it can mmap it.
1647 * The mmap call will end up in drm_gem_mmap(), which will set things
1648 * up so we can get faults in the handler above.
1650 * The fault handler will take care of binding the object into the GTT
1651 * (since it may have been evicted to make room for something), allocating
1652 * a fence register, and mapping the appropriate aperture address into
1656 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1657 struct drm_file *file)
1659 struct drm_i915_gem_mmap_gtt *args = data;
1661 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1664 /* Immediately discard the backing storage */
1666 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1668 struct inode *inode;
1670 i915_gem_object_free_mmap_offset(obj);
1672 if (obj->base.filp == NULL)
1675 /* Our goal here is to return as much of the memory as
1676 * is possible back to the system as we are called from OOM.
1677 * To do this we must instruct the shmfs to drop all of its
1678 * backing pages, *now*.
1680 inode = file_inode(obj->base.filp);
1681 shmem_truncate_range(inode, 0, (loff_t)-1);
1683 obj->madv = __I915_MADV_PURGED;
1687 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1689 return obj->madv == I915_MADV_DONTNEED;
1693 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1695 struct sg_page_iter sg_iter;
1698 BUG_ON(obj->madv == __I915_MADV_PURGED);
1700 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1702 /* In the event of a disaster, abandon all caches and
1703 * hope for the best.
1705 WARN_ON(ret != -EIO);
1706 i915_gem_clflush_object(obj, true);
1707 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1710 if (i915_gem_object_needs_bit17_swizzle(obj))
1711 i915_gem_object_save_bit_17_swizzle(obj);
1713 if (obj->madv == I915_MADV_DONTNEED)
1716 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1717 struct page *page = sg_page_iter_page(&sg_iter);
1720 set_page_dirty(page);
1722 if (obj->madv == I915_MADV_WILLNEED)
1723 mark_page_accessed(page);
1725 page_cache_release(page);
1729 sg_free_table(obj->pages);
1734 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1736 const struct drm_i915_gem_object_ops *ops = obj->ops;
1738 if (obj->pages == NULL)
1741 if (obj->pages_pin_count)
1744 BUG_ON(i915_gem_obj_bound_any(obj));
1746 /* ->put_pages might need to allocate memory for the bit17 swizzle
1747 * array, hence protect them from being reaped by removing them from gtt
1749 list_del(&obj->global_list);
1751 ops->put_pages(obj);
1754 if (i915_gem_object_is_purgeable(obj))
1755 i915_gem_object_truncate(obj);
1760 static unsigned long
1761 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1762 bool purgeable_only)
1764 struct list_head still_bound_list;
1765 struct drm_i915_gem_object *obj, *next;
1766 unsigned long count = 0;
1768 list_for_each_entry_safe(obj, next,
1769 &dev_priv->mm.unbound_list,
1771 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1772 i915_gem_object_put_pages(obj) == 0) {
1773 count += obj->base.size >> PAGE_SHIFT;
1774 if (count >= target)
1780 * As we may completely rewrite the bound list whilst unbinding
1781 * (due to retiring requests) we have to strictly process only
1782 * one element of the list at the time, and recheck the list
1783 * on every iteration.
1785 INIT_LIST_HEAD(&still_bound_list);
1786 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1787 struct i915_vma *vma, *v;
1789 obj = list_first_entry(&dev_priv->mm.bound_list,
1790 typeof(*obj), global_list);
1791 list_move_tail(&obj->global_list, &still_bound_list);
1793 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1797 * Hold a reference whilst we unbind this object, as we may
1798 * end up waiting for and retiring requests. This might
1799 * release the final reference (held by the active list)
1800 * and result in the object being freed from under us.
1801 * in this object being freed.
1803 * Note 1: Shrinking the bound list is special since only active
1804 * (and hence bound objects) can contain such limbo objects, so
1805 * we don't need special tricks for shrinking the unbound list.
1806 * The only other place where we have to be careful with active
1807 * objects suddenly disappearing due to retiring requests is the
1810 * Note 2: Even though the bound list doesn't hold a reference
1811 * to the object we can safely grab one here: The final object
1812 * unreferencing and the bound_list are both protected by the
1813 * dev->struct_mutex and so we won't ever be able to observe an
1814 * object on the bound_list with a reference count equals 0.
1816 drm_gem_object_reference(&obj->base);
1818 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1819 if (i915_vma_unbind(vma))
1822 if (i915_gem_object_put_pages(obj) == 0)
1823 count += obj->base.size >> PAGE_SHIFT;
1825 drm_gem_object_unreference(&obj->base);
1827 list_splice(&still_bound_list, &dev_priv->mm.bound_list);
1832 static unsigned long
1833 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1835 return __i915_gem_shrink(dev_priv, target, true);
1838 static unsigned long
1839 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1841 struct drm_i915_gem_object *obj, *next;
1844 i915_gem_evict_everything(dev_priv->dev);
1846 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1848 if (i915_gem_object_put_pages(obj) == 0)
1849 freed += obj->base.size >> PAGE_SHIFT;
1855 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1857 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1859 struct address_space *mapping;
1860 struct sg_table *st;
1861 struct scatterlist *sg;
1862 struct sg_page_iter sg_iter;
1864 unsigned long last_pfn = 0; /* suppress gcc warning */
1867 /* Assert that the object is not currently in any GPU domain. As it
1868 * wasn't in the GTT, there shouldn't be any way it could have been in
1871 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1872 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1874 st = kmalloc(sizeof(*st), GFP_KERNEL);
1878 page_count = obj->base.size / PAGE_SIZE;
1879 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1884 /* Get the list of pages out of our struct file. They'll be pinned
1885 * at this point until we release them.
1887 * Fail silently without starting the shrinker
1889 mapping = file_inode(obj->base.filp)->i_mapping;
1890 gfp = mapping_gfp_mask(mapping);
1891 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1892 gfp &= ~(__GFP_IO | __GFP_WAIT);
1895 for (i = 0; i < page_count; i++) {
1896 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1898 i915_gem_purge(dev_priv, page_count);
1899 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1902 /* We've tried hard to allocate the memory by reaping
1903 * our own buffer, now let the real VM do its job and
1904 * go down in flames if truly OOM.
1906 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1907 gfp |= __GFP_IO | __GFP_WAIT;
1909 i915_gem_shrink_all(dev_priv);
1910 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1914 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1915 gfp &= ~(__GFP_IO | __GFP_WAIT);
1917 #ifdef CONFIG_SWIOTLB
1918 if (swiotlb_nr_tbl()) {
1920 sg_set_page(sg, page, PAGE_SIZE, 0);
1925 if (!i || page_to_pfn(page) != last_pfn + 1) {
1929 sg_set_page(sg, page, PAGE_SIZE, 0);
1931 sg->length += PAGE_SIZE;
1933 last_pfn = page_to_pfn(page);
1935 /* Check that the i965g/gm workaround works. */
1936 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
1938 #ifdef CONFIG_SWIOTLB
1939 if (!swiotlb_nr_tbl())
1944 if (i915_gem_object_needs_bit17_swizzle(obj))
1945 i915_gem_object_do_bit_17_swizzle(obj);
1951 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1952 page_cache_release(sg_page_iter_page(&sg_iter));
1955 return PTR_ERR(page);
1958 /* Ensure that the associated pages are gathered from the backing storage
1959 * and pinned into our object. i915_gem_object_get_pages() may be called
1960 * multiple times before they are released by a single call to
1961 * i915_gem_object_put_pages() - once the pages are no longer referenced
1962 * either as a result of memory pressure (reaping pages under the shrinker)
1963 * or as the object is itself released.
1966 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1968 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1969 const struct drm_i915_gem_object_ops *ops = obj->ops;
1975 if (obj->madv != I915_MADV_WILLNEED) {
1976 DRM_ERROR("Attempting to obtain a purgeable object\n");
1980 BUG_ON(obj->pages_pin_count);
1982 ret = ops->get_pages(obj);
1986 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1991 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1992 struct intel_ring_buffer *ring)
1994 struct drm_device *dev = obj->base.dev;
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996 u32 seqno = intel_ring_get_seqno(ring);
1998 BUG_ON(ring == NULL);
1999 if (obj->ring != ring && obj->last_write_seqno) {
2000 /* Keep the seqno relative to the current ring */
2001 obj->last_write_seqno = seqno;
2005 /* Add a reference if we're newly entering the active list. */
2007 drm_gem_object_reference(&obj->base);
2011 list_move_tail(&obj->ring_list, &ring->active_list);
2013 obj->last_read_seqno = seqno;
2015 if (obj->fenced_gpu_access) {
2016 obj->last_fenced_seqno = seqno;
2018 /* Bump MRU to take account of the delayed flush */
2019 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2020 struct drm_i915_fence_reg *reg;
2022 reg = &dev_priv->fence_regs[obj->fence_reg];
2023 list_move_tail(®->lru_list,
2024 &dev_priv->mm.fence_list);
2029 void i915_vma_move_to_active(struct i915_vma *vma,
2030 struct intel_ring_buffer *ring)
2032 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2033 return i915_gem_object_move_to_active(vma->obj, ring);
2037 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2039 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2040 struct i915_address_space *vm;
2041 struct i915_vma *vma;
2043 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2044 BUG_ON(!obj->active);
2046 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2047 vma = i915_gem_obj_to_vma(obj, vm);
2048 if (vma && !list_empty(&vma->mm_list))
2049 list_move_tail(&vma->mm_list, &vm->inactive_list);
2052 list_del_init(&obj->ring_list);
2055 obj->last_read_seqno = 0;
2056 obj->last_write_seqno = 0;
2057 obj->base.write_domain = 0;
2059 obj->last_fenced_seqno = 0;
2060 obj->fenced_gpu_access = false;
2063 drm_gem_object_unreference(&obj->base);
2065 WARN_ON(i915_verify_lists(dev));
2069 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2071 struct drm_i915_private *dev_priv = dev->dev_private;
2072 struct intel_ring_buffer *ring;
2075 /* Carefully retire all requests without writing to the rings */
2076 for_each_ring(ring, dev_priv, i) {
2077 ret = intel_ring_idle(ring);
2081 i915_gem_retire_requests(dev);
2083 /* Finally reset hw state */
2084 for_each_ring(ring, dev_priv, i) {
2085 intel_ring_init_seqno(ring, seqno);
2087 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2088 ring->sync_seqno[j] = 0;
2094 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2102 /* HWS page needs to be set less than what we
2103 * will inject to ring
2105 ret = i915_gem_init_seqno(dev, seqno - 1);
2109 /* Carefully set the last_seqno value so that wrap
2110 * detection still works
2112 dev_priv->next_seqno = seqno;
2113 dev_priv->last_seqno = seqno - 1;
2114 if (dev_priv->last_seqno == 0)
2115 dev_priv->last_seqno--;
2121 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2125 /* reserve 0 for non-seqno */
2126 if (dev_priv->next_seqno == 0) {
2127 int ret = i915_gem_init_seqno(dev, 0);
2131 dev_priv->next_seqno = 1;
2134 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2138 int __i915_add_request(struct intel_ring_buffer *ring,
2139 struct drm_file *file,
2140 struct drm_i915_gem_object *obj,
2143 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2144 struct drm_i915_gem_request *request;
2145 u32 request_ring_position, request_start;
2149 request_start = intel_ring_get_tail(ring);
2151 * Emit any outstanding flushes - execbuf can fail to emit the flush
2152 * after having emitted the batchbuffer command. Hence we need to fix
2153 * things up similar to emitting the lazy request. The difference here
2154 * is that the flush _must_ happen before the next request, no matter
2157 ret = intel_ring_flush_all_caches(ring);
2161 request = ring->preallocated_lazy_request;
2162 if (WARN_ON(request == NULL))
2165 /* Record the position of the start of the request so that
2166 * should we detect the updated seqno part-way through the
2167 * GPU processing the request, we never over-estimate the
2168 * position of the head.
2170 request_ring_position = intel_ring_get_tail(ring);
2172 ret = ring->add_request(ring);
2176 request->seqno = intel_ring_get_seqno(ring);
2177 request->ring = ring;
2178 request->head = request_start;
2179 request->tail = request_ring_position;
2181 /* Whilst this request exists, batch_obj will be on the
2182 * active_list, and so will hold the active reference. Only when this
2183 * request is retired will the the batch_obj be moved onto the
2184 * inactive_list and lose its active reference. Hence we do not need
2185 * to explicitly hold another reference here.
2187 request->batch_obj = obj;
2189 /* Hold a reference to the current context so that we can inspect
2190 * it later in case a hangcheck error event fires.
2192 request->ctx = ring->last_context;
2194 i915_gem_context_reference(request->ctx);
2196 request->emitted_jiffies = jiffies;
2197 was_empty = list_empty(&ring->request_list);
2198 list_add_tail(&request->list, &ring->request_list);
2199 request->file_priv = NULL;
2202 struct drm_i915_file_private *file_priv = file->driver_priv;
2204 spin_lock(&file_priv->mm.lock);
2205 request->file_priv = file_priv;
2206 list_add_tail(&request->client_list,
2207 &file_priv->mm.request_list);
2208 spin_unlock(&file_priv->mm.lock);
2211 trace_i915_gem_request_add(ring, request->seqno);
2212 ring->outstanding_lazy_seqno = 0;
2213 ring->preallocated_lazy_request = NULL;
2215 if (!dev_priv->ums.mm_suspended) {
2216 i915_queue_hangcheck(ring->dev);
2219 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2220 queue_delayed_work(dev_priv->wq,
2221 &dev_priv->mm.retire_work,
2222 round_jiffies_up_relative(HZ));
2223 intel_mark_busy(dev_priv->dev);
2228 *out_seqno = request->seqno;
2233 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2235 struct drm_i915_file_private *file_priv = request->file_priv;
2240 spin_lock(&file_priv->mm.lock);
2241 list_del(&request->client_list);
2242 request->file_priv = NULL;
2243 spin_unlock(&file_priv->mm.lock);
2246 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2247 const struct i915_hw_context *ctx)
2249 unsigned long elapsed;
2251 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2253 if (ctx->hang_stats.banned)
2256 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2257 if (dev_priv->gpu_error.stop_rings == 0 &&
2258 i915_gem_context_is_default(ctx)) {
2259 DRM_ERROR("gpu hanging too fast, banning!\n");
2261 DRM_DEBUG("context hanging too fast, banning!\n");
2270 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2271 struct i915_hw_context *ctx,
2274 struct i915_ctx_hang_stats *hs;
2279 hs = &ctx->hang_stats;
2282 hs->banned = i915_context_is_banned(dev_priv, ctx);
2284 hs->guilty_ts = get_seconds();
2286 hs->batch_pending++;
2290 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2292 list_del(&request->list);
2293 i915_gem_request_remove_from_client(request);
2296 i915_gem_context_unreference(request->ctx);
2301 static struct drm_i915_gem_request *
2302 i915_gem_find_first_non_complete(struct intel_ring_buffer *ring)
2304 struct drm_i915_gem_request *request;
2305 const u32 completed_seqno = ring->get_seqno(ring, false);
2307 list_for_each_entry(request, &ring->request_list, list) {
2308 if (i915_seqno_passed(completed_seqno, request->seqno))
2317 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2318 struct intel_ring_buffer *ring)
2320 struct drm_i915_gem_request *request;
2323 request = i915_gem_find_first_non_complete(ring);
2325 if (request == NULL)
2328 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2330 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2332 list_for_each_entry_continue(request, &ring->request_list, list)
2333 i915_set_reset_status(dev_priv, request->ctx, false);
2336 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2337 struct intel_ring_buffer *ring)
2339 while (!list_empty(&ring->active_list)) {
2340 struct drm_i915_gem_object *obj;
2342 obj = list_first_entry(&ring->active_list,
2343 struct drm_i915_gem_object,
2346 i915_gem_object_move_to_inactive(obj);
2350 * We must free the requests after all the corresponding objects have
2351 * been moved off active lists. Which is the same order as the normal
2352 * retire_requests function does. This is important if object hold
2353 * implicit references on things like e.g. ppgtt address spaces through
2356 while (!list_empty(&ring->request_list)) {
2357 struct drm_i915_gem_request *request;
2359 request = list_first_entry(&ring->request_list,
2360 struct drm_i915_gem_request,
2363 i915_gem_free_request(request);
2367 void i915_gem_restore_fences(struct drm_device *dev)
2369 struct drm_i915_private *dev_priv = dev->dev_private;
2372 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2373 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2376 * Commit delayed tiling changes if we have an object still
2377 * attached to the fence, otherwise just clear the fence.
2380 i915_gem_object_update_fence(reg->obj, reg,
2381 reg->obj->tiling_mode);
2383 i915_gem_write_fence(dev, i, NULL);
2388 void i915_gem_reset(struct drm_device *dev)
2390 struct drm_i915_private *dev_priv = dev->dev_private;
2391 struct intel_ring_buffer *ring;
2395 * Before we free the objects from the requests, we need to inspect
2396 * them for finding the guilty party. As the requests only borrow
2397 * their reference to the objects, the inspection must be done first.
2399 for_each_ring(ring, dev_priv, i)
2400 i915_gem_reset_ring_status(dev_priv, ring);
2402 for_each_ring(ring, dev_priv, i)
2403 i915_gem_reset_ring_cleanup(dev_priv, ring);
2405 i915_gem_cleanup_ringbuffer(dev);
2407 i915_gem_context_reset(dev);
2409 i915_gem_restore_fences(dev);
2413 * This function clears the request list as sequence numbers are passed.
2416 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2420 if (list_empty(&ring->request_list))
2423 WARN_ON(i915_verify_lists(ring->dev));
2425 seqno = ring->get_seqno(ring, true);
2427 /* Move any buffers on the active list that are no longer referenced
2428 * by the ringbuffer to the flushing/inactive lists as appropriate,
2429 * before we free the context associated with the requests.
2431 while (!list_empty(&ring->active_list)) {
2432 struct drm_i915_gem_object *obj;
2434 obj = list_first_entry(&ring->active_list,
2435 struct drm_i915_gem_object,
2438 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2441 i915_gem_object_move_to_inactive(obj);
2445 while (!list_empty(&ring->request_list)) {
2446 struct drm_i915_gem_request *request;
2448 request = list_first_entry(&ring->request_list,
2449 struct drm_i915_gem_request,
2452 if (!i915_seqno_passed(seqno, request->seqno))
2455 trace_i915_gem_request_retire(ring, request->seqno);
2456 /* We know the GPU must have read the request to have
2457 * sent us the seqno + interrupt, so use the position
2458 * of tail of the request to update the last known position
2461 ring->last_retired_head = request->tail;
2463 i915_gem_free_request(request);
2466 if (unlikely(ring->trace_irq_seqno &&
2467 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2468 ring->irq_put(ring);
2469 ring->trace_irq_seqno = 0;
2472 WARN_ON(i915_verify_lists(ring->dev));
2476 i915_gem_retire_requests(struct drm_device *dev)
2478 drm_i915_private_t *dev_priv = dev->dev_private;
2479 struct intel_ring_buffer *ring;
2483 for_each_ring(ring, dev_priv, i) {
2484 i915_gem_retire_requests_ring(ring);
2485 idle &= list_empty(&ring->request_list);
2489 mod_delayed_work(dev_priv->wq,
2490 &dev_priv->mm.idle_work,
2491 msecs_to_jiffies(100));
2497 i915_gem_retire_work_handler(struct work_struct *work)
2499 struct drm_i915_private *dev_priv =
2500 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2501 struct drm_device *dev = dev_priv->dev;
2504 /* Come back later if the device is busy... */
2506 if (mutex_trylock(&dev->struct_mutex)) {
2507 idle = i915_gem_retire_requests(dev);
2508 mutex_unlock(&dev->struct_mutex);
2511 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2512 round_jiffies_up_relative(HZ));
2516 i915_gem_idle_work_handler(struct work_struct *work)
2518 struct drm_i915_private *dev_priv =
2519 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2521 intel_mark_idle(dev_priv->dev);
2525 * Ensures that an object will eventually get non-busy by flushing any required
2526 * write domains, emitting any outstanding lazy request and retiring and
2527 * completed requests.
2530 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2535 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2539 i915_gem_retire_requests_ring(obj->ring);
2546 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2547 * @DRM_IOCTL_ARGS: standard ioctl arguments
2549 * Returns 0 if successful, else an error is returned with the remaining time in
2550 * the timeout parameter.
2551 * -ETIME: object is still busy after timeout
2552 * -ERESTARTSYS: signal interrupted the wait
2553 * -ENONENT: object doesn't exist
2554 * Also possible, but rare:
2555 * -EAGAIN: GPU wedged
2557 * -ENODEV: Internal IRQ fail
2558 * -E?: The add request failed
2560 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2561 * non-zero timeout parameter the wait ioctl will wait for the given number of
2562 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2563 * without holding struct_mutex the object may become re-busied before this
2564 * function completes. A similar but shorter * race condition exists in the busy
2568 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2570 drm_i915_private_t *dev_priv = dev->dev_private;
2571 struct drm_i915_gem_wait *args = data;
2572 struct drm_i915_gem_object *obj;
2573 struct intel_ring_buffer *ring = NULL;
2574 struct timespec timeout_stack, *timeout = NULL;
2575 unsigned reset_counter;
2579 if (args->timeout_ns >= 0) {
2580 timeout_stack = ns_to_timespec(args->timeout_ns);
2581 timeout = &timeout_stack;
2584 ret = i915_mutex_lock_interruptible(dev);
2588 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2589 if (&obj->base == NULL) {
2590 mutex_unlock(&dev->struct_mutex);
2594 /* Need to make sure the object gets inactive eventually. */
2595 ret = i915_gem_object_flush_active(obj);
2600 seqno = obj->last_read_seqno;
2607 /* Do this after OLR check to make sure we make forward progress polling
2608 * on this IOCTL with a 0 timeout (like busy ioctl)
2610 if (!args->timeout_ns) {
2615 drm_gem_object_unreference(&obj->base);
2616 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2617 mutex_unlock(&dev->struct_mutex);
2619 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
2621 args->timeout_ns = timespec_to_ns(timeout);
2625 drm_gem_object_unreference(&obj->base);
2626 mutex_unlock(&dev->struct_mutex);
2631 * i915_gem_object_sync - sync an object to a ring.
2633 * @obj: object which may be in use on another ring.
2634 * @to: ring we wish to use the object on. May be NULL.
2636 * This code is meant to abstract object synchronization with the GPU.
2637 * Calling with NULL implies synchronizing the object with the CPU
2638 * rather than a particular GPU ring.
2640 * Returns 0 if successful, else propagates up the lower layer error.
2643 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2644 struct intel_ring_buffer *to)
2646 struct intel_ring_buffer *from = obj->ring;
2650 if (from == NULL || to == from)
2653 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2654 return i915_gem_object_wait_rendering(obj, false);
2656 idx = intel_ring_sync_index(from, to);
2658 seqno = obj->last_read_seqno;
2659 if (seqno <= from->sync_seqno[idx])
2662 ret = i915_gem_check_olr(obj->ring, seqno);
2666 trace_i915_gem_ring_sync_to(from, to, seqno);
2667 ret = to->sync_to(to, from, seqno);
2669 /* We use last_read_seqno because sync_to()
2670 * might have just caused seqno wrap under
2673 from->sync_seqno[idx] = obj->last_read_seqno;
2678 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2680 u32 old_write_domain, old_read_domains;
2682 /* Force a pagefault for domain tracking on next user access */
2683 i915_gem_release_mmap(obj);
2685 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2688 /* Wait for any direct GTT access to complete */
2691 old_read_domains = obj->base.read_domains;
2692 old_write_domain = obj->base.write_domain;
2694 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2695 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2697 trace_i915_gem_object_change_domain(obj,
2702 int i915_vma_unbind(struct i915_vma *vma)
2704 struct drm_i915_gem_object *obj = vma->obj;
2705 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2708 if (list_empty(&vma->vma_link))
2711 if (!drm_mm_node_allocated(&vma->node)) {
2712 i915_gem_vma_destroy(vma);
2720 BUG_ON(obj->pages == NULL);
2722 ret = i915_gem_object_finish_gpu(obj);
2725 /* Continue on if we fail due to EIO, the GPU is hung so we
2726 * should be safe and we need to cleanup or else we might
2727 * cause memory corruption through use-after-free.
2730 i915_gem_object_finish_gtt(obj);
2732 /* release the fence reg _after_ flushing */
2733 ret = i915_gem_object_put_fence(obj);
2737 trace_i915_vma_unbind(vma);
2739 vma->unbind_vma(vma);
2741 i915_gem_gtt_finish_object(obj);
2743 list_del(&vma->mm_list);
2744 /* Avoid an unnecessary call to unbind on rebind. */
2745 if (i915_is_ggtt(vma->vm))
2746 obj->map_and_fenceable = true;
2748 drm_mm_remove_node(&vma->node);
2749 i915_gem_vma_destroy(vma);
2751 /* Since the unbound list is global, only move to that list if
2752 * no more VMAs exist. */
2753 if (list_empty(&obj->vma_list))
2754 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2756 /* And finally now the object is completely decoupled from this vma,
2757 * we can drop its hold on the backing storage and allow it to be
2758 * reaped by the shrinker.
2760 i915_gem_object_unpin_pages(obj);
2766 * Unbinds an object from the global GTT aperture.
2769 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2771 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2772 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2774 if (!i915_gem_obj_ggtt_bound(obj))
2777 if (i915_gem_obj_to_ggtt(obj)->pin_count)
2780 BUG_ON(obj->pages == NULL);
2782 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2785 int i915_gpu_idle(struct drm_device *dev)
2787 drm_i915_private_t *dev_priv = dev->dev_private;
2788 struct intel_ring_buffer *ring;
2791 /* Flush everything onto the inactive list. */
2792 for_each_ring(ring, dev_priv, i) {
2793 ret = i915_switch_context(ring, NULL, ring->default_context);
2797 ret = intel_ring_idle(ring);
2805 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2806 struct drm_i915_gem_object *obj)
2808 drm_i915_private_t *dev_priv = dev->dev_private;
2810 int fence_pitch_shift;
2812 if (INTEL_INFO(dev)->gen >= 6) {
2813 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2814 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2816 fence_reg = FENCE_REG_965_0;
2817 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2820 fence_reg += reg * 8;
2822 /* To w/a incoherency with non-atomic 64-bit register updates,
2823 * we split the 64-bit update into two 32-bit writes. In order
2824 * for a partial fence not to be evaluated between writes, we
2825 * precede the update with write to turn off the fence register,
2826 * and only enable the fence as the last step.
2828 * For extra levels of paranoia, we make sure each step lands
2829 * before applying the next step.
2831 I915_WRITE(fence_reg, 0);
2832 POSTING_READ(fence_reg);
2835 u32 size = i915_gem_obj_ggtt_size(obj);
2838 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2840 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2841 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2842 if (obj->tiling_mode == I915_TILING_Y)
2843 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2844 val |= I965_FENCE_REG_VALID;
2846 I915_WRITE(fence_reg + 4, val >> 32);
2847 POSTING_READ(fence_reg + 4);
2849 I915_WRITE(fence_reg + 0, val);
2850 POSTING_READ(fence_reg);
2852 I915_WRITE(fence_reg + 4, 0);
2853 POSTING_READ(fence_reg + 4);
2857 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2858 struct drm_i915_gem_object *obj)
2860 drm_i915_private_t *dev_priv = dev->dev_private;
2864 u32 size = i915_gem_obj_ggtt_size(obj);
2868 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2869 (size & -size) != size ||
2870 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2871 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2872 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2874 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2879 /* Note: pitch better be a power of two tile widths */
2880 pitch_val = obj->stride / tile_width;
2881 pitch_val = ffs(pitch_val) - 1;
2883 val = i915_gem_obj_ggtt_offset(obj);
2884 if (obj->tiling_mode == I915_TILING_Y)
2885 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2886 val |= I915_FENCE_SIZE_BITS(size);
2887 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2888 val |= I830_FENCE_REG_VALID;
2893 reg = FENCE_REG_830_0 + reg * 4;
2895 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2897 I915_WRITE(reg, val);
2901 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2902 struct drm_i915_gem_object *obj)
2904 drm_i915_private_t *dev_priv = dev->dev_private;
2908 u32 size = i915_gem_obj_ggtt_size(obj);
2911 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2912 (size & -size) != size ||
2913 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2914 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2915 i915_gem_obj_ggtt_offset(obj), size);
2917 pitch_val = obj->stride / 128;
2918 pitch_val = ffs(pitch_val) - 1;
2920 val = i915_gem_obj_ggtt_offset(obj);
2921 if (obj->tiling_mode == I915_TILING_Y)
2922 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2923 val |= I830_FENCE_SIZE_BITS(size);
2924 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2925 val |= I830_FENCE_REG_VALID;
2929 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2930 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2933 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2935 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2938 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2939 struct drm_i915_gem_object *obj)
2941 struct drm_i915_private *dev_priv = dev->dev_private;
2943 /* Ensure that all CPU reads are completed before installing a fence
2944 * and all writes before removing the fence.
2946 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2949 WARN(obj && (!obj->stride || !obj->tiling_mode),
2950 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2951 obj->stride, obj->tiling_mode);
2953 switch (INTEL_INFO(dev)->gen) {
2958 case 4: i965_write_fence_reg(dev, reg, obj); break;
2959 case 3: i915_write_fence_reg(dev, reg, obj); break;
2960 case 2: i830_write_fence_reg(dev, reg, obj); break;
2964 /* And similarly be paranoid that no direct access to this region
2965 * is reordered to before the fence is installed.
2967 if (i915_gem_object_needs_mb(obj))
2971 static inline int fence_number(struct drm_i915_private *dev_priv,
2972 struct drm_i915_fence_reg *fence)
2974 return fence - dev_priv->fence_regs;
2977 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2978 struct drm_i915_fence_reg *fence,
2981 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2982 int reg = fence_number(dev_priv, fence);
2984 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2987 obj->fence_reg = reg;
2989 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2991 obj->fence_reg = I915_FENCE_REG_NONE;
2993 list_del_init(&fence->lru_list);
2995 obj->fence_dirty = false;
2999 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3001 if (obj->last_fenced_seqno) {
3002 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3006 obj->last_fenced_seqno = 0;
3009 obj->fenced_gpu_access = false;
3014 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3016 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3017 struct drm_i915_fence_reg *fence;
3020 ret = i915_gem_object_wait_fence(obj);
3024 if (obj->fence_reg == I915_FENCE_REG_NONE)
3027 fence = &dev_priv->fence_regs[obj->fence_reg];
3029 i915_gem_object_fence_lost(obj);
3030 i915_gem_object_update_fence(obj, fence, false);
3035 static struct drm_i915_fence_reg *
3036 i915_find_fence_reg(struct drm_device *dev)
3038 struct drm_i915_private *dev_priv = dev->dev_private;
3039 struct drm_i915_fence_reg *reg, *avail;
3042 /* First try to find a free reg */
3044 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3045 reg = &dev_priv->fence_regs[i];
3049 if (!reg->pin_count)
3056 /* None available, try to steal one or wait for a user to finish */
3057 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3065 /* Wait for completion of pending flips which consume fences */
3066 if (intel_has_pending_fb_unpin(dev))
3067 return ERR_PTR(-EAGAIN);
3069 return ERR_PTR(-EDEADLK);
3073 * i915_gem_object_get_fence - set up fencing for an object
3074 * @obj: object to map through a fence reg
3076 * When mapping objects through the GTT, userspace wants to be able to write
3077 * to them without having to worry about swizzling if the object is tiled.
3078 * This function walks the fence regs looking for a free one for @obj,
3079 * stealing one if it can't find any.
3081 * It then sets up the reg based on the object's properties: address, pitch
3082 * and tiling format.
3084 * For an untiled surface, this removes any existing fence.
3087 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3089 struct drm_device *dev = obj->base.dev;
3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091 bool enable = obj->tiling_mode != I915_TILING_NONE;
3092 struct drm_i915_fence_reg *reg;
3095 /* Have we updated the tiling parameters upon the object and so
3096 * will need to serialise the write to the associated fence register?
3098 if (obj->fence_dirty) {
3099 ret = i915_gem_object_wait_fence(obj);
3104 /* Just update our place in the LRU if our fence is getting reused. */
3105 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3106 reg = &dev_priv->fence_regs[obj->fence_reg];
3107 if (!obj->fence_dirty) {
3108 list_move_tail(®->lru_list,
3109 &dev_priv->mm.fence_list);
3112 } else if (enable) {
3113 reg = i915_find_fence_reg(dev);
3115 return PTR_ERR(reg);
3118 struct drm_i915_gem_object *old = reg->obj;
3120 ret = i915_gem_object_wait_fence(old);
3124 i915_gem_object_fence_lost(old);
3129 i915_gem_object_update_fence(obj, reg, enable);
3134 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3135 struct drm_mm_node *gtt_space,
3136 unsigned long cache_level)
3138 struct drm_mm_node *other;
3140 /* On non-LLC machines we have to be careful when putting differing
3141 * types of snoopable memory together to avoid the prefetcher
3142 * crossing memory domains and dying.
3147 if (!drm_mm_node_allocated(gtt_space))
3150 if (list_empty(>t_space->node_list))
3153 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3154 if (other->allocated && !other->hole_follows && other->color != cache_level)
3157 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3158 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3164 static void i915_gem_verify_gtt(struct drm_device *dev)
3167 struct drm_i915_private *dev_priv = dev->dev_private;
3168 struct drm_i915_gem_object *obj;
3171 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3172 if (obj->gtt_space == NULL) {
3173 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3178 if (obj->cache_level != obj->gtt_space->color) {
3179 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3180 i915_gem_obj_ggtt_offset(obj),
3181 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3183 obj->gtt_space->color);
3188 if (!i915_gem_valid_gtt_space(dev,
3190 obj->cache_level)) {
3191 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3192 i915_gem_obj_ggtt_offset(obj),
3193 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3205 * Finds free space in the GTT aperture and binds the object there.
3208 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3209 struct i915_address_space *vm,
3211 bool map_and_fenceable,
3214 struct drm_device *dev = obj->base.dev;
3215 drm_i915_private_t *dev_priv = dev->dev_private;
3216 u32 size, fence_size, fence_alignment, unfenced_alignment;
3218 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3219 struct i915_vma *vma;
3222 fence_size = i915_gem_get_gtt_size(dev,
3225 fence_alignment = i915_gem_get_gtt_alignment(dev,
3227 obj->tiling_mode, true);
3228 unfenced_alignment =
3229 i915_gem_get_gtt_alignment(dev,
3231 obj->tiling_mode, false);
3234 alignment = map_and_fenceable ? fence_alignment :
3236 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3237 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3241 size = map_and_fenceable ? fence_size : obj->base.size;
3243 /* If the object is bigger than the entire aperture, reject it early
3244 * before evicting everything in a vain attempt to find space.
3246 if (obj->base.size > gtt_max) {
3247 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3249 map_and_fenceable ? "mappable" : "total",
3254 ret = i915_gem_object_get_pages(obj);
3258 i915_gem_object_pin_pages(obj);
3260 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3267 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3269 obj->cache_level, 0, gtt_max,
3270 DRM_MM_SEARCH_DEFAULT);
3272 ret = i915_gem_evict_something(dev, vm, size, alignment,
3281 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3282 obj->cache_level))) {
3284 goto err_remove_node;
3287 ret = i915_gem_gtt_prepare_object(obj);
3289 goto err_remove_node;
3291 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3292 list_add_tail(&vma->mm_list, &vm->inactive_list);
3294 if (i915_is_ggtt(vm)) {
3295 bool mappable, fenceable;
3297 fenceable = (vma->node.size == fence_size &&
3298 (vma->node.start & (fence_alignment - 1)) == 0);
3300 mappable = (vma->node.start + obj->base.size <=
3301 dev_priv->gtt.mappable_end);
3303 obj->map_and_fenceable = mappable && fenceable;
3306 WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3308 trace_i915_vma_bind(vma, map_and_fenceable);
3309 i915_gem_verify_gtt(dev);
3313 drm_mm_remove_node(&vma->node);
3315 i915_gem_vma_destroy(vma);
3317 i915_gem_object_unpin_pages(obj);
3322 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3325 /* If we don't have a page list set up, then we're not pinned
3326 * to GPU, and we can ignore the cache flush because it'll happen
3327 * again at bind time.
3329 if (obj->pages == NULL)
3333 * Stolen memory is always coherent with the GPU as it is explicitly
3334 * marked as wc by the system, or the system is cache-coherent.
3339 /* If the GPU is snooping the contents of the CPU cache,
3340 * we do not need to manually clear the CPU cache lines. However,
3341 * the caches are only snooped when the render cache is
3342 * flushed/invalidated. As we always have to emit invalidations
3343 * and flushes when moving into and out of the RENDER domain, correct
3344 * snooping behaviour occurs naturally as the result of our domain
3347 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3350 trace_i915_gem_object_clflush(obj);
3351 drm_clflush_sg(obj->pages);
3356 /** Flushes the GTT write domain for the object if it's dirty. */
3358 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3360 uint32_t old_write_domain;
3362 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3365 /* No actual flushing is required for the GTT write domain. Writes
3366 * to it immediately go to main memory as far as we know, so there's
3367 * no chipset flush. It also doesn't land in render cache.
3369 * However, we do have to enforce the order so that all writes through
3370 * the GTT land before any writes to the device, such as updates to
3375 old_write_domain = obj->base.write_domain;
3376 obj->base.write_domain = 0;
3378 trace_i915_gem_object_change_domain(obj,
3379 obj->base.read_domains,
3383 /** Flushes the CPU write domain for the object if it's dirty. */
3385 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3388 uint32_t old_write_domain;
3390 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3393 if (i915_gem_clflush_object(obj, force))
3394 i915_gem_chipset_flush(obj->base.dev);
3396 old_write_domain = obj->base.write_domain;
3397 obj->base.write_domain = 0;
3399 trace_i915_gem_object_change_domain(obj,
3400 obj->base.read_domains,
3405 * Moves a single object to the GTT read, and possibly write domain.
3407 * This function returns when the move is complete, including waiting on
3411 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3413 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3414 uint32_t old_write_domain, old_read_domains;
3417 /* Not valid to be called on unbound objects. */
3418 if (!i915_gem_obj_bound_any(obj))
3421 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3424 ret = i915_gem_object_wait_rendering(obj, !write);
3428 i915_gem_object_flush_cpu_write_domain(obj, false);
3430 /* Serialise direct access to this object with the barriers for
3431 * coherent writes from the GPU, by effectively invalidating the
3432 * GTT domain upon first access.
3434 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3437 old_write_domain = obj->base.write_domain;
3438 old_read_domains = obj->base.read_domains;
3440 /* It should now be out of any other write domains, and we can update
3441 * the domain values for our changes.
3443 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3444 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3446 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3447 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3451 trace_i915_gem_object_change_domain(obj,
3455 /* And bump the LRU for this access */
3456 if (i915_gem_object_is_inactive(obj)) {
3457 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3459 list_move_tail(&vma->mm_list,
3460 &dev_priv->gtt.base.inactive_list);
3467 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3468 enum i915_cache_level cache_level)
3470 struct drm_device *dev = obj->base.dev;
3471 struct i915_vma *vma;
3474 if (obj->cache_level == cache_level)
3477 if (i915_gem_obj_is_pinned(obj)) {
3478 DRM_DEBUG("can not change the cache level of pinned objects\n");
3482 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3483 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3484 ret = i915_vma_unbind(vma);
3492 if (i915_gem_obj_bound_any(obj)) {
3493 ret = i915_gem_object_finish_gpu(obj);
3497 i915_gem_object_finish_gtt(obj);
3499 /* Before SandyBridge, you could not use tiling or fence
3500 * registers with snooped memory, so relinquish any fences
3501 * currently pointing to our region in the aperture.
3503 if (INTEL_INFO(dev)->gen < 6) {
3504 ret = i915_gem_object_put_fence(obj);
3509 list_for_each_entry(vma, &obj->vma_list, vma_link)
3510 vma->bind_vma(vma, cache_level, 0);
3513 list_for_each_entry(vma, &obj->vma_list, vma_link)
3514 vma->node.color = cache_level;
3515 obj->cache_level = cache_level;
3517 if (cpu_write_needs_clflush(obj)) {
3518 u32 old_read_domains, old_write_domain;
3520 /* If we're coming from LLC cached, then we haven't
3521 * actually been tracking whether the data is in the
3522 * CPU cache or not, since we only allow one bit set
3523 * in obj->write_domain and have been skipping the clflushes.
3524 * Just set it to the CPU cache for now.
3526 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3528 old_read_domains = obj->base.read_domains;
3529 old_write_domain = obj->base.write_domain;
3531 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3532 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3534 trace_i915_gem_object_change_domain(obj,
3539 i915_gem_verify_gtt(dev);
3543 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3544 struct drm_file *file)
3546 struct drm_i915_gem_caching *args = data;
3547 struct drm_i915_gem_object *obj;
3550 ret = i915_mutex_lock_interruptible(dev);
3554 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3555 if (&obj->base == NULL) {
3560 switch (obj->cache_level) {
3561 case I915_CACHE_LLC:
3562 case I915_CACHE_L3_LLC:
3563 args->caching = I915_CACHING_CACHED;
3567 args->caching = I915_CACHING_DISPLAY;
3571 args->caching = I915_CACHING_NONE;
3575 drm_gem_object_unreference(&obj->base);
3577 mutex_unlock(&dev->struct_mutex);
3581 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3582 struct drm_file *file)
3584 struct drm_i915_gem_caching *args = data;
3585 struct drm_i915_gem_object *obj;
3586 enum i915_cache_level level;
3589 switch (args->caching) {
3590 case I915_CACHING_NONE:
3591 level = I915_CACHE_NONE;
3593 case I915_CACHING_CACHED:
3594 level = I915_CACHE_LLC;
3596 case I915_CACHING_DISPLAY:
3597 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3603 ret = i915_mutex_lock_interruptible(dev);
3607 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3608 if (&obj->base == NULL) {
3613 ret = i915_gem_object_set_cache_level(obj, level);
3615 drm_gem_object_unreference(&obj->base);
3617 mutex_unlock(&dev->struct_mutex);
3621 static bool is_pin_display(struct drm_i915_gem_object *obj)
3623 /* There are 3 sources that pin objects:
3624 * 1. The display engine (scanouts, sprites, cursors);
3625 * 2. Reservations for execbuffer;
3628 * We can ignore reservations as we hold the struct_mutex and
3629 * are only called outside of the reservation path. The user
3630 * can only increment pin_count once, and so if after
3631 * subtracting the potential reference by the user, any pin_count
3632 * remains, it must be due to another use by the display engine.
3634 return i915_gem_obj_to_ggtt(obj)->pin_count - !!obj->user_pin_count;
3638 * Prepare buffer for display plane (scanout, cursors, etc).
3639 * Can be called from an uninterruptible phase (modesetting) and allows
3640 * any flushes to be pipelined (for pageflips).
3643 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3645 struct intel_ring_buffer *pipelined)
3647 u32 old_read_domains, old_write_domain;
3650 if (pipelined != obj->ring) {
3651 ret = i915_gem_object_sync(obj, pipelined);
3656 /* Mark the pin_display early so that we account for the
3657 * display coherency whilst setting up the cache domains.
3659 obj->pin_display = true;
3661 /* The display engine is not coherent with the LLC cache on gen6. As
3662 * a result, we make sure that the pinning that is about to occur is
3663 * done with uncached PTEs. This is lowest common denominator for all
3666 * However for gen6+, we could do better by using the GFDT bit instead
3667 * of uncaching, which would allow us to flush all the LLC-cached data
3668 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3670 ret = i915_gem_object_set_cache_level(obj,
3671 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3673 goto err_unpin_display;
3675 /* As the user may map the buffer once pinned in the display plane
3676 * (e.g. libkms for the bootup splash), we have to ensure that we
3677 * always use map_and_fenceable for all scanout buffers.
3679 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3681 goto err_unpin_display;
3683 i915_gem_object_flush_cpu_write_domain(obj, true);
3685 old_write_domain = obj->base.write_domain;
3686 old_read_domains = obj->base.read_domains;
3688 /* It should now be out of any other write domains, and we can update
3689 * the domain values for our changes.
3691 obj->base.write_domain = 0;
3692 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3694 trace_i915_gem_object_change_domain(obj,
3701 obj->pin_display = is_pin_display(obj);
3706 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3708 i915_gem_object_ggtt_unpin(obj);
3709 obj->pin_display = is_pin_display(obj);
3713 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3717 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3720 ret = i915_gem_object_wait_rendering(obj, false);
3724 /* Ensure that we invalidate the GPU's caches and TLBs. */
3725 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3730 * Moves a single object to the CPU read, and possibly write domain.
3732 * This function returns when the move is complete, including waiting on
3736 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3738 uint32_t old_write_domain, old_read_domains;
3741 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3744 ret = i915_gem_object_wait_rendering(obj, !write);
3748 i915_gem_object_flush_gtt_write_domain(obj);
3750 old_write_domain = obj->base.write_domain;
3751 old_read_domains = obj->base.read_domains;
3753 /* Flush the CPU cache if it's still invalid. */
3754 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3755 i915_gem_clflush_object(obj, false);
3757 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3760 /* It should now be out of any other write domains, and we can update
3761 * the domain values for our changes.
3763 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3765 /* If we're writing through the CPU, then the GPU read domains will
3766 * need to be invalidated at next use.
3769 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3770 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3773 trace_i915_gem_object_change_domain(obj,
3780 /* Throttle our rendering by waiting until the ring has completed our requests
3781 * emitted over 20 msec ago.
3783 * Note that if we were to use the current jiffies each time around the loop,
3784 * we wouldn't escape the function with any frames outstanding if the time to
3785 * render a frame was over 20ms.
3787 * This should get us reasonable parallelism between CPU and GPU but also
3788 * relatively low latency when blocking on a particular request to finish.
3791 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3793 struct drm_i915_private *dev_priv = dev->dev_private;
3794 struct drm_i915_file_private *file_priv = file->driver_priv;
3795 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3796 struct drm_i915_gem_request *request;
3797 struct intel_ring_buffer *ring = NULL;
3798 unsigned reset_counter;
3802 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3806 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3810 spin_lock(&file_priv->mm.lock);
3811 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3812 if (time_after_eq(request->emitted_jiffies, recent_enough))
3815 ring = request->ring;
3816 seqno = request->seqno;
3818 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3819 spin_unlock(&file_priv->mm.lock);
3824 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
3826 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3832 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3833 struct i915_address_space *vm,
3835 bool map_and_fenceable,
3838 const u32 flags = map_and_fenceable ? GLOBAL_BIND : 0;
3839 struct i915_vma *vma;
3842 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3844 vma = i915_gem_obj_to_vma(obj, vm);
3847 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3851 vma->node.start & (alignment - 1)) ||
3852 (map_and_fenceable && !obj->map_and_fenceable)) {
3853 WARN(vma->pin_count,
3854 "bo is already pinned with incorrect alignment:"
3855 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3856 " obj->map_and_fenceable=%d\n",
3857 i915_gem_obj_offset(obj, vm), alignment,
3859 obj->map_and_fenceable);
3860 ret = i915_vma_unbind(vma);
3866 if (!i915_gem_obj_bound(obj, vm)) {
3867 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3875 vma = i915_gem_obj_to_vma(obj, vm);
3877 vma->bind_vma(vma, obj->cache_level, flags);
3879 i915_gem_obj_to_vma(obj, vm)->pin_count++;
3880 obj->pin_mappable |= map_and_fenceable;
3886 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3888 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3891 BUG_ON(vma->pin_count == 0);
3892 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
3894 if (--vma->pin_count == 0)
3895 obj->pin_mappable = false;
3899 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3900 struct drm_file *file)
3902 struct drm_i915_gem_pin *args = data;
3903 struct drm_i915_gem_object *obj;
3906 if (INTEL_INFO(dev)->gen >= 6)
3909 ret = i915_mutex_lock_interruptible(dev);
3913 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3914 if (&obj->base == NULL) {
3919 if (obj->madv != I915_MADV_WILLNEED) {
3920 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3925 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3926 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3932 if (obj->user_pin_count == ULONG_MAX) {
3937 if (obj->user_pin_count == 0) {
3938 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3943 obj->user_pin_count++;
3944 obj->pin_filp = file;
3946 args->offset = i915_gem_obj_ggtt_offset(obj);
3948 drm_gem_object_unreference(&obj->base);
3950 mutex_unlock(&dev->struct_mutex);
3955 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3956 struct drm_file *file)
3958 struct drm_i915_gem_pin *args = data;
3959 struct drm_i915_gem_object *obj;
3962 ret = i915_mutex_lock_interruptible(dev);
3966 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3967 if (&obj->base == NULL) {
3972 if (obj->pin_filp != file) {
3973 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3978 obj->user_pin_count--;
3979 if (obj->user_pin_count == 0) {
3980 obj->pin_filp = NULL;
3981 i915_gem_object_ggtt_unpin(obj);
3985 drm_gem_object_unreference(&obj->base);
3987 mutex_unlock(&dev->struct_mutex);
3992 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3993 struct drm_file *file)
3995 struct drm_i915_gem_busy *args = data;
3996 struct drm_i915_gem_object *obj;
3999 ret = i915_mutex_lock_interruptible(dev);
4003 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4004 if (&obj->base == NULL) {
4009 /* Count all active objects as busy, even if they are currently not used
4010 * by the gpu. Users of this interface expect objects to eventually
4011 * become non-busy without any further actions, therefore emit any
4012 * necessary flushes here.
4014 ret = i915_gem_object_flush_active(obj);
4016 args->busy = obj->active;
4018 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4019 args->busy |= intel_ring_flag(obj->ring) << 16;
4022 drm_gem_object_unreference(&obj->base);
4024 mutex_unlock(&dev->struct_mutex);
4029 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4030 struct drm_file *file_priv)
4032 return i915_gem_ring_throttle(dev, file_priv);
4036 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4037 struct drm_file *file_priv)
4039 struct drm_i915_gem_madvise *args = data;
4040 struct drm_i915_gem_object *obj;
4043 switch (args->madv) {
4044 case I915_MADV_DONTNEED:
4045 case I915_MADV_WILLNEED:
4051 ret = i915_mutex_lock_interruptible(dev);
4055 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4056 if (&obj->base == NULL) {
4061 if (i915_gem_obj_is_pinned(obj)) {
4066 if (obj->madv != __I915_MADV_PURGED)
4067 obj->madv = args->madv;
4069 /* if the object is no longer attached, discard its backing storage */
4070 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4071 i915_gem_object_truncate(obj);
4073 args->retained = obj->madv != __I915_MADV_PURGED;
4076 drm_gem_object_unreference(&obj->base);
4078 mutex_unlock(&dev->struct_mutex);
4082 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4083 const struct drm_i915_gem_object_ops *ops)
4085 INIT_LIST_HEAD(&obj->global_list);
4086 INIT_LIST_HEAD(&obj->ring_list);
4087 INIT_LIST_HEAD(&obj->obj_exec_link);
4088 INIT_LIST_HEAD(&obj->vma_list);
4092 obj->fence_reg = I915_FENCE_REG_NONE;
4093 obj->madv = I915_MADV_WILLNEED;
4094 /* Avoid an unnecessary call to unbind on the first bind. */
4095 obj->map_and_fenceable = true;
4097 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4100 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4101 .get_pages = i915_gem_object_get_pages_gtt,
4102 .put_pages = i915_gem_object_put_pages_gtt,
4105 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4108 struct drm_i915_gem_object *obj;
4109 struct address_space *mapping;
4112 obj = i915_gem_object_alloc(dev);
4116 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4117 i915_gem_object_free(obj);
4121 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4122 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4123 /* 965gm cannot relocate objects above 4GiB. */
4124 mask &= ~__GFP_HIGHMEM;
4125 mask |= __GFP_DMA32;
4128 mapping = file_inode(obj->base.filp)->i_mapping;
4129 mapping_set_gfp_mask(mapping, mask);
4131 i915_gem_object_init(obj, &i915_gem_object_ops);
4133 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4134 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4137 /* On some devices, we can have the GPU use the LLC (the CPU
4138 * cache) for about a 10% performance improvement
4139 * compared to uncached. Graphics requests other than
4140 * display scanout are coherent with the CPU in
4141 * accessing this cache. This means in this mode we
4142 * don't need to clflush on the CPU side, and on the
4143 * GPU side we only need to flush internal caches to
4144 * get data visible to the CPU.
4146 * However, we maintain the display planes as UC, and so
4147 * need to rebind when first used as such.
4149 obj->cache_level = I915_CACHE_LLC;
4151 obj->cache_level = I915_CACHE_NONE;
4153 trace_i915_gem_object_create(obj);
4158 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4160 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4161 struct drm_device *dev = obj->base.dev;
4162 drm_i915_private_t *dev_priv = dev->dev_private;
4163 struct i915_vma *vma, *next;
4165 intel_runtime_pm_get(dev_priv);
4167 trace_i915_gem_object_destroy(obj);
4170 i915_gem_detach_phys_object(dev, obj);
4172 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4176 ret = i915_vma_unbind(vma);
4177 if (WARN_ON(ret == -ERESTARTSYS)) {
4178 bool was_interruptible;
4180 was_interruptible = dev_priv->mm.interruptible;
4181 dev_priv->mm.interruptible = false;
4183 WARN_ON(i915_vma_unbind(vma));
4185 dev_priv->mm.interruptible = was_interruptible;
4189 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4190 * before progressing. */
4192 i915_gem_object_unpin_pages(obj);
4194 if (WARN_ON(obj->pages_pin_count))
4195 obj->pages_pin_count = 0;
4196 i915_gem_object_put_pages(obj);
4197 i915_gem_object_free_mmap_offset(obj);
4198 i915_gem_object_release_stolen(obj);
4202 if (obj->base.import_attach)
4203 drm_prime_gem_destroy(&obj->base, NULL);
4205 drm_gem_object_release(&obj->base);
4206 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4209 i915_gem_object_free(obj);
4211 intel_runtime_pm_put(dev_priv);
4214 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4215 struct i915_address_space *vm)
4217 struct i915_vma *vma;
4218 list_for_each_entry(vma, &obj->vma_list, vma_link)
4225 void i915_gem_vma_destroy(struct i915_vma *vma)
4227 WARN_ON(vma->node.allocated);
4229 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4230 if (!list_empty(&vma->exec_list))
4233 list_del(&vma->vma_link);
4239 i915_gem_suspend(struct drm_device *dev)
4241 drm_i915_private_t *dev_priv = dev->dev_private;
4244 mutex_lock(&dev->struct_mutex);
4245 if (dev_priv->ums.mm_suspended)
4248 ret = i915_gpu_idle(dev);
4252 i915_gem_retire_requests(dev);
4254 /* Under UMS, be paranoid and evict. */
4255 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4256 i915_gem_evict_everything(dev);
4258 i915_kernel_lost_context(dev);
4259 i915_gem_cleanup_ringbuffer(dev);
4261 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4262 * We need to replace this with a semaphore, or something.
4263 * And not confound ums.mm_suspended!
4265 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4267 mutex_unlock(&dev->struct_mutex);
4269 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4270 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4271 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4276 mutex_unlock(&dev->struct_mutex);
4280 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
4282 struct drm_device *dev = ring->dev;
4283 drm_i915_private_t *dev_priv = dev->dev_private;
4284 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4285 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4288 if (!HAS_L3_DPF(dev) || !remap_info)
4291 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4296 * Note: We do not worry about the concurrent register cacheline hang
4297 * here because no other code should access these registers other than
4298 * at initialization time.
4300 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4301 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4302 intel_ring_emit(ring, reg_base + i);
4303 intel_ring_emit(ring, remap_info[i/4]);
4306 intel_ring_advance(ring);
4311 void i915_gem_init_swizzling(struct drm_device *dev)
4313 drm_i915_private_t *dev_priv = dev->dev_private;
4315 if (INTEL_INFO(dev)->gen < 5 ||
4316 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4319 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4320 DISP_TILE_SURFACE_SWIZZLING);
4325 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4327 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4328 else if (IS_GEN7(dev))
4329 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4330 else if (IS_GEN8(dev))
4331 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4337 intel_enable_blt(struct drm_device *dev)
4342 /* The blitter was dysfunctional on early prototypes */
4343 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4344 DRM_INFO("BLT not supported on this pre-production hardware;"
4345 " graphics performance will be degraded.\n");
4352 static int i915_gem_init_rings(struct drm_device *dev)
4354 struct drm_i915_private *dev_priv = dev->dev_private;
4357 ret = intel_init_render_ring_buffer(dev);
4362 ret = intel_init_bsd_ring_buffer(dev);
4364 goto cleanup_render_ring;
4367 if (intel_enable_blt(dev)) {
4368 ret = intel_init_blt_ring_buffer(dev);
4370 goto cleanup_bsd_ring;
4373 if (HAS_VEBOX(dev)) {
4374 ret = intel_init_vebox_ring_buffer(dev);
4376 goto cleanup_blt_ring;
4380 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4382 goto cleanup_vebox_ring;
4387 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4389 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4391 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4392 cleanup_render_ring:
4393 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4399 i915_gem_init_hw(struct drm_device *dev)
4401 drm_i915_private_t *dev_priv = dev->dev_private;
4404 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4407 if (dev_priv->ellc_size)
4408 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4410 if (IS_HASWELL(dev))
4411 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4412 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4414 if (HAS_PCH_NOP(dev)) {
4415 if (IS_IVYBRIDGE(dev)) {
4416 u32 temp = I915_READ(GEN7_MSG_CTL);
4417 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4418 I915_WRITE(GEN7_MSG_CTL, temp);
4419 } else if (INTEL_INFO(dev)->gen >= 7) {
4420 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4421 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4422 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4426 i915_gem_init_swizzling(dev);
4428 ret = i915_gem_init_rings(dev);
4432 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4433 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4436 * XXX: Contexts should only be initialized once. Doing a switch to the
4437 * default context switch however is something we'd like to do after
4438 * reset or thaw (the latter may not actually be necessary for HW, but
4439 * goes with our code better). Context switching requires rings (for
4440 * the do_switch), but before enabling PPGTT. So don't move this.
4442 ret = i915_gem_context_enable(dev_priv);
4444 DRM_ERROR("Context enable failed %d\n", ret);
4451 i915_gem_cleanup_ringbuffer(dev);
4455 int i915_gem_init(struct drm_device *dev)
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4460 mutex_lock(&dev->struct_mutex);
4462 if (IS_VALLEYVIEW(dev)) {
4463 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4464 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4465 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4466 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4469 i915_gem_init_global_gtt(dev);
4471 ret = i915_gem_context_init(dev);
4473 mutex_unlock(&dev->struct_mutex);
4477 ret = i915_gem_init_hw(dev);
4478 mutex_unlock(&dev->struct_mutex);
4480 WARN_ON(dev_priv->mm.aliasing_ppgtt);
4481 i915_gem_context_fini(dev);
4482 drm_mm_takedown(&dev_priv->gtt.base.mm);
4486 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4487 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4488 dev_priv->dri1.allow_batchbuffer = 1;
4493 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4495 drm_i915_private_t *dev_priv = dev->dev_private;
4496 struct intel_ring_buffer *ring;
4499 for_each_ring(ring, dev_priv, i)
4500 intel_cleanup_ring_buffer(ring);
4504 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4505 struct drm_file *file_priv)
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4510 if (drm_core_check_feature(dev, DRIVER_MODESET))
4513 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4514 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4515 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4518 mutex_lock(&dev->struct_mutex);
4519 dev_priv->ums.mm_suspended = 0;
4521 ret = i915_gem_init_hw(dev);
4523 mutex_unlock(&dev->struct_mutex);
4527 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4528 mutex_unlock(&dev->struct_mutex);
4530 ret = drm_irq_install(dev);
4532 goto cleanup_ringbuffer;
4537 mutex_lock(&dev->struct_mutex);
4538 i915_gem_cleanup_ringbuffer(dev);
4539 dev_priv->ums.mm_suspended = 1;
4540 mutex_unlock(&dev->struct_mutex);
4546 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4547 struct drm_file *file_priv)
4549 if (drm_core_check_feature(dev, DRIVER_MODESET))
4552 drm_irq_uninstall(dev);
4554 return i915_gem_suspend(dev);
4558 i915_gem_lastclose(struct drm_device *dev)
4562 if (drm_core_check_feature(dev, DRIVER_MODESET))
4565 ret = i915_gem_suspend(dev);
4567 DRM_ERROR("failed to idle hardware: %d\n", ret);
4571 init_ring_lists(struct intel_ring_buffer *ring)
4573 INIT_LIST_HEAD(&ring->active_list);
4574 INIT_LIST_HEAD(&ring->request_list);
4577 void i915_init_vm(struct drm_i915_private *dev_priv,
4578 struct i915_address_space *vm)
4580 if (!i915_is_ggtt(vm))
4581 drm_mm_init(&vm->mm, vm->start, vm->total);
4582 vm->dev = dev_priv->dev;
4583 INIT_LIST_HEAD(&vm->active_list);
4584 INIT_LIST_HEAD(&vm->inactive_list);
4585 INIT_LIST_HEAD(&vm->global_link);
4586 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4590 i915_gem_load(struct drm_device *dev)
4592 drm_i915_private_t *dev_priv = dev->dev_private;
4596 kmem_cache_create("i915_gem_object",
4597 sizeof(struct drm_i915_gem_object), 0,
4601 INIT_LIST_HEAD(&dev_priv->vm_list);
4602 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4604 INIT_LIST_HEAD(&dev_priv->context_list);
4605 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4606 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4607 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4608 for (i = 0; i < I915_NUM_RINGS; i++)
4609 init_ring_lists(&dev_priv->ring[i]);
4610 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4611 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4612 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4613 i915_gem_retire_work_handler);
4614 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4615 i915_gem_idle_work_handler);
4616 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4618 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4620 I915_WRITE(MI_ARB_STATE,
4621 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4624 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4626 /* Old X drivers will take 0-2 for front, back, depth buffers */
4627 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4628 dev_priv->fence_reg_start = 3;
4630 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4631 dev_priv->num_fence_regs = 32;
4632 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4633 dev_priv->num_fence_regs = 16;
4635 dev_priv->num_fence_regs = 8;
4637 /* Initialize fence registers to zero */
4638 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4639 i915_gem_restore_fences(dev);
4641 i915_gem_detect_bit_6_swizzle(dev);
4642 init_waitqueue_head(&dev_priv->pending_flip_queue);
4644 dev_priv->mm.interruptible = true;
4646 dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan;
4647 dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count;
4648 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4649 register_shrinker(&dev_priv->mm.inactive_shrinker);
4653 * Create a physically contiguous memory object for this object
4654 * e.g. for cursor + overlay regs
4656 static int i915_gem_init_phys_object(struct drm_device *dev,
4657 int id, int size, int align)
4659 drm_i915_private_t *dev_priv = dev->dev_private;
4660 struct drm_i915_gem_phys_object *phys_obj;
4663 if (dev_priv->mm.phys_objs[id - 1] || !size)
4666 phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL);
4672 phys_obj->handle = drm_pci_alloc(dev, size, align);
4673 if (!phys_obj->handle) {
4678 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4681 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4689 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4691 drm_i915_private_t *dev_priv = dev->dev_private;
4692 struct drm_i915_gem_phys_object *phys_obj;
4694 if (!dev_priv->mm.phys_objs[id - 1])
4697 phys_obj = dev_priv->mm.phys_objs[id - 1];
4698 if (phys_obj->cur_obj) {
4699 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4703 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4705 drm_pci_free(dev, phys_obj->handle);
4707 dev_priv->mm.phys_objs[id - 1] = NULL;
4710 void i915_gem_free_all_phys_object(struct drm_device *dev)
4714 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4715 i915_gem_free_phys_object(dev, i);
4718 void i915_gem_detach_phys_object(struct drm_device *dev,
4719 struct drm_i915_gem_object *obj)
4721 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4728 vaddr = obj->phys_obj->handle->vaddr;
4730 page_count = obj->base.size / PAGE_SIZE;
4731 for (i = 0; i < page_count; i++) {
4732 struct page *page = shmem_read_mapping_page(mapping, i);
4733 if (!IS_ERR(page)) {
4734 char *dst = kmap_atomic(page);
4735 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4738 drm_clflush_pages(&page, 1);
4740 set_page_dirty(page);
4741 mark_page_accessed(page);
4742 page_cache_release(page);
4745 i915_gem_chipset_flush(dev);
4747 obj->phys_obj->cur_obj = NULL;
4748 obj->phys_obj = NULL;
4752 i915_gem_attach_phys_object(struct drm_device *dev,
4753 struct drm_i915_gem_object *obj,
4757 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4758 drm_i915_private_t *dev_priv = dev->dev_private;
4763 if (id > I915_MAX_PHYS_OBJECT)
4766 if (obj->phys_obj) {
4767 if (obj->phys_obj->id == id)
4769 i915_gem_detach_phys_object(dev, obj);
4772 /* create a new object */
4773 if (!dev_priv->mm.phys_objs[id - 1]) {
4774 ret = i915_gem_init_phys_object(dev, id,
4775 obj->base.size, align);
4777 DRM_ERROR("failed to init phys object %d size: %zu\n",
4778 id, obj->base.size);
4783 /* bind to the object */
4784 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4785 obj->phys_obj->cur_obj = obj;
4787 page_count = obj->base.size / PAGE_SIZE;
4789 for (i = 0; i < page_count; i++) {
4793 page = shmem_read_mapping_page(mapping, i);
4795 return PTR_ERR(page);
4797 src = kmap_atomic(page);
4798 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4799 memcpy(dst, src, PAGE_SIZE);
4802 mark_page_accessed(page);
4803 page_cache_release(page);
4810 i915_gem_phys_pwrite(struct drm_device *dev,
4811 struct drm_i915_gem_object *obj,
4812 struct drm_i915_gem_pwrite *args,
4813 struct drm_file *file_priv)
4815 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4816 char __user *user_data = to_user_ptr(args->data_ptr);
4818 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4819 unsigned long unwritten;
4821 /* The physical object once assigned is fixed for the lifetime
4822 * of the obj, so we can safely drop the lock and continue
4825 mutex_unlock(&dev->struct_mutex);
4826 unwritten = copy_from_user(vaddr, user_data, args->size);
4827 mutex_lock(&dev->struct_mutex);
4832 i915_gem_chipset_flush(dev);
4836 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4838 struct drm_i915_file_private *file_priv = file->driver_priv;
4840 cancel_delayed_work_sync(&file_priv->mm.idle_work);
4842 /* Clean up our request list when the client is going away, so that
4843 * later retire_requests won't dereference our soon-to-be-gone
4846 spin_lock(&file_priv->mm.lock);
4847 while (!list_empty(&file_priv->mm.request_list)) {
4848 struct drm_i915_gem_request *request;
4850 request = list_first_entry(&file_priv->mm.request_list,
4851 struct drm_i915_gem_request,
4853 list_del(&request->client_list);
4854 request->file_priv = NULL;
4856 spin_unlock(&file_priv->mm.lock);
4860 i915_gem_file_idle_work_handler(struct work_struct *work)
4862 struct drm_i915_file_private *file_priv =
4863 container_of(work, typeof(*file_priv), mm.idle_work.work);
4865 atomic_set(&file_priv->rps_wait_boost, false);
4868 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4870 struct drm_i915_file_private *file_priv;
4873 DRM_DEBUG_DRIVER("\n");
4875 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4879 file->driver_priv = file_priv;
4880 file_priv->dev_priv = dev->dev_private;
4882 spin_lock_init(&file_priv->mm.lock);
4883 INIT_LIST_HEAD(&file_priv->mm.request_list);
4884 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4885 i915_gem_file_idle_work_handler);
4887 ret = i915_gem_context_open(dev, file);
4894 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4896 if (!mutex_is_locked(mutex))
4899 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4900 return mutex->owner == task;
4902 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4907 static unsigned long
4908 i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc)
4910 struct drm_i915_private *dev_priv =
4911 container_of(shrinker,
4912 struct drm_i915_private,
4913 mm.inactive_shrinker);
4914 struct drm_device *dev = dev_priv->dev;
4915 struct drm_i915_gem_object *obj;
4917 unsigned long count;
4919 if (!mutex_trylock(&dev->struct_mutex)) {
4920 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4923 if (dev_priv->mm.shrinker_no_lock_stealing)
4930 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4931 if (obj->pages_pin_count == 0)
4932 count += obj->base.size >> PAGE_SHIFT;
4934 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4938 if (!i915_gem_obj_is_pinned(obj) && obj->pages_pin_count == 0)
4939 count += obj->base.size >> PAGE_SHIFT;
4943 mutex_unlock(&dev->struct_mutex);
4948 /* All the new VM stuff */
4949 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4950 struct i915_address_space *vm)
4952 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4953 struct i915_vma *vma;
4955 if (!dev_priv->mm.aliasing_ppgtt ||
4956 vm == &dev_priv->mm.aliasing_ppgtt->base)
4957 vm = &dev_priv->gtt.base;
4959 BUG_ON(list_empty(&o->vma_list));
4960 list_for_each_entry(vma, &o->vma_list, vma_link) {
4962 return vma->node.start;
4968 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
4969 struct i915_address_space *vm)
4971 struct i915_vma *vma;
4973 list_for_each_entry(vma, &o->vma_list, vma_link)
4974 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
4980 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
4982 struct i915_vma *vma;
4984 list_for_each_entry(vma, &o->vma_list, vma_link)
4985 if (drm_mm_node_allocated(&vma->node))
4991 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
4992 struct i915_address_space *vm)
4994 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4995 struct i915_vma *vma;
4997 if (!dev_priv->mm.aliasing_ppgtt ||
4998 vm == &dev_priv->mm.aliasing_ppgtt->base)
4999 vm = &dev_priv->gtt.base;
5001 BUG_ON(list_empty(&o->vma_list));
5003 list_for_each_entry(vma, &o->vma_list, vma_link)
5005 return vma->node.size;
5010 static unsigned long
5011 i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc)
5013 struct drm_i915_private *dev_priv =
5014 container_of(shrinker,
5015 struct drm_i915_private,
5016 mm.inactive_shrinker);
5017 struct drm_device *dev = dev_priv->dev;
5018 unsigned long freed;
5021 if (!mutex_trylock(&dev->struct_mutex)) {
5022 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5025 if (dev_priv->mm.shrinker_no_lock_stealing)
5031 freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5032 if (freed < sc->nr_to_scan)
5033 freed += __i915_gem_shrink(dev_priv,
5034 sc->nr_to_scan - freed,
5036 if (freed < sc->nr_to_scan)
5037 freed += i915_gem_shrink_all(dev_priv);
5040 mutex_unlock(&dev->struct_mutex);
5045 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5047 struct i915_vma *vma;
5049 if (WARN_ON(list_empty(&obj->vma_list)))
5052 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5053 if (vma->vm != obj_to_ggtt(obj))