2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
44 static __must_check int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
59 struct shrink_control *sc);
60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
63 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
65 static bool cpu_cache_is_coherent(struct drm_device *dev,
66 enum i915_cache_level level)
68 return HAS_LLC(dev) || level != I915_CACHE_NONE;
71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
73 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
76 return obj->pin_display;
79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
82 i915_gem_release_mmap(obj);
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
87 obj->fence_dirty = false;
88 obj->fence_reg = I915_FENCE_REG_NONE;
91 /* some bookkeeping */
92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
95 spin_lock(&dev_priv->mm.object_stat_lock);
96 dev_priv->mm.object_count++;
97 dev_priv->mm.object_memory += size;
98 spin_unlock(&dev_priv->mm.object_stat_lock);
101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
104 spin_lock(&dev_priv->mm.object_stat_lock);
105 dev_priv->mm.object_count--;
106 dev_priv->mm.object_memory -= size;
107 spin_unlock(&dev_priv->mm.object_stat_lock);
111 i915_gem_wait_for_error(struct i915_gpu_error *error)
115 #define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
125 ret = wait_event_interruptible_timeout(error->reset_queue,
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
131 } else if (ret < 0) {
139 int i915_mutex_lock_interruptible(struct drm_device *dev)
141 struct drm_i915_private *dev_priv = dev->dev_private;
144 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
148 ret = mutex_lock_interruptible(&dev->struct_mutex);
152 WARN_ON(i915_verify_lists(dev));
157 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
159 return i915_gem_obj_bound_any(obj) && !obj->active;
163 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
164 struct drm_file *file)
166 struct drm_i915_private *dev_priv = dev->dev_private;
167 struct drm_i915_gem_get_aperture *args = data;
168 struct drm_i915_gem_object *obj;
172 mutex_lock(&dev->struct_mutex);
173 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
174 if (i915_gem_obj_is_pinned(obj))
175 pinned += i915_gem_obj_ggtt_size(obj);
176 mutex_unlock(&dev->struct_mutex);
178 args->aper_size = dev_priv->gtt.base.total;
179 args->aper_available_size = args->aper_size - pinned;
185 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
187 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
188 char *vaddr = obj->phys_handle->vaddr;
190 struct scatterlist *sg;
193 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
196 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
200 page = shmem_read_mapping_page(mapping, i);
202 return PTR_ERR(page);
204 src = kmap_atomic(page);
205 memcpy(vaddr, src, PAGE_SIZE);
206 drm_clflush_virt_range(vaddr, PAGE_SIZE);
209 page_cache_release(page);
213 i915_gem_chipset_flush(obj->base.dev);
215 st = kmalloc(sizeof(*st), GFP_KERNEL);
219 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
226 sg->length = obj->base.size;
228 sg_dma_address(sg) = obj->phys_handle->busaddr;
229 sg_dma_len(sg) = obj->base.size;
232 obj->has_dma_mapping = true;
237 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
241 BUG_ON(obj->madv == __I915_MADV_PURGED);
243 ret = i915_gem_object_set_to_cpu_domain(obj, true);
245 /* In the event of a disaster, abandon all caches and
248 WARN_ON(ret != -EIO);
249 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
252 if (obj->madv == I915_MADV_DONTNEED)
256 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
257 char *vaddr = obj->phys_handle->vaddr;
260 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
264 page = shmem_read_mapping_page(mapping, i);
268 dst = kmap_atomic(page);
269 drm_clflush_virt_range(vaddr, PAGE_SIZE);
270 memcpy(dst, vaddr, PAGE_SIZE);
273 set_page_dirty(page);
274 if (obj->madv == I915_MADV_WILLNEED)
275 mark_page_accessed(page);
276 page_cache_release(page);
282 sg_free_table(obj->pages);
285 obj->has_dma_mapping = false;
289 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
291 drm_pci_free(obj->base.dev, obj->phys_handle);
294 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
295 .get_pages = i915_gem_object_get_pages_phys,
296 .put_pages = i915_gem_object_put_pages_phys,
297 .release = i915_gem_object_release_phys,
301 drop_pages(struct drm_i915_gem_object *obj)
303 struct i915_vma *vma, *next;
306 drm_gem_object_reference(&obj->base);
307 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
308 if (i915_vma_unbind(vma))
311 ret = i915_gem_object_put_pages(obj);
312 drm_gem_object_unreference(&obj->base);
318 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
321 drm_dma_handle_t *phys;
324 if (obj->phys_handle) {
325 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
331 if (obj->madv != I915_MADV_WILLNEED)
334 if (obj->base.filp == NULL)
337 ret = drop_pages(obj);
341 /* create a new object */
342 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
346 obj->phys_handle = phys;
347 obj->ops = &i915_gem_phys_ops;
349 return i915_gem_object_get_pages(obj);
353 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
354 struct drm_i915_gem_pwrite *args,
355 struct drm_file *file_priv)
357 struct drm_device *dev = obj->base.dev;
358 void *vaddr = obj->phys_handle->vaddr + args->offset;
359 char __user *user_data = to_user_ptr(args->data_ptr);
362 /* We manually control the domain here and pretend that it
363 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
365 ret = i915_gem_object_wait_rendering(obj, false);
369 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
370 unsigned long unwritten;
372 /* The physical object once assigned is fixed for the lifetime
373 * of the obj, so we can safely drop the lock and continue
376 mutex_unlock(&dev->struct_mutex);
377 unwritten = copy_from_user(vaddr, user_data, args->size);
378 mutex_lock(&dev->struct_mutex);
383 drm_clflush_virt_range(vaddr, args->size);
384 i915_gem_chipset_flush(dev);
388 void *i915_gem_object_alloc(struct drm_device *dev)
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
394 void i915_gem_object_free(struct drm_i915_gem_object *obj)
396 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
397 kmem_cache_free(dev_priv->slab, obj);
401 i915_gem_create(struct drm_file *file,
402 struct drm_device *dev,
407 struct drm_i915_gem_object *obj;
411 size = roundup(size, PAGE_SIZE);
415 /* Allocate the new object */
416 obj = i915_gem_alloc_object(dev, size);
420 obj->base.dumb = dumb;
421 ret = drm_gem_handle_create(file, &obj->base, &handle);
422 /* drop reference from allocate - handle holds it now */
423 drm_gem_object_unreference_unlocked(&obj->base);
432 i915_gem_dumb_create(struct drm_file *file,
433 struct drm_device *dev,
434 struct drm_mode_create_dumb *args)
436 /* have to work out size/pitch and return them */
437 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
438 args->size = args->pitch * args->height;
439 return i915_gem_create(file, dev,
440 args->size, true, &args->handle);
444 * Creates a new mm object and returns a handle to it.
447 i915_gem_create_ioctl(struct drm_device *dev, void *data,
448 struct drm_file *file)
450 struct drm_i915_gem_create *args = data;
452 return i915_gem_create(file, dev,
453 args->size, false, &args->handle);
457 __copy_to_user_swizzled(char __user *cpu_vaddr,
458 const char *gpu_vaddr, int gpu_offset,
461 int ret, cpu_offset = 0;
464 int cacheline_end = ALIGN(gpu_offset + 1, 64);
465 int this_length = min(cacheline_end - gpu_offset, length);
466 int swizzled_gpu_offset = gpu_offset ^ 64;
468 ret = __copy_to_user(cpu_vaddr + cpu_offset,
469 gpu_vaddr + swizzled_gpu_offset,
474 cpu_offset += this_length;
475 gpu_offset += this_length;
476 length -= this_length;
483 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
484 const char __user *cpu_vaddr,
487 int ret, cpu_offset = 0;
490 int cacheline_end = ALIGN(gpu_offset + 1, 64);
491 int this_length = min(cacheline_end - gpu_offset, length);
492 int swizzled_gpu_offset = gpu_offset ^ 64;
494 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
495 cpu_vaddr + cpu_offset,
500 cpu_offset += this_length;
501 gpu_offset += this_length;
502 length -= this_length;
509 * Pins the specified object's pages and synchronizes the object with
510 * GPU accesses. Sets needs_clflush to non-zero if the caller should
511 * flush the object from the CPU cache.
513 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
523 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
524 /* If we're not in the cpu read domain, set ourself into the gtt
525 * read domain and manually flush cachelines (if required). This
526 * optimizes for the case when the gpu will dirty the data
527 * anyway again before the next pread happens. */
528 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
530 ret = i915_gem_object_wait_rendering(obj, true);
534 i915_gem_object_retire(obj);
537 ret = i915_gem_object_get_pages(obj);
541 i915_gem_object_pin_pages(obj);
546 /* Per-page copy function for the shmem pread fastpath.
547 * Flushes invalid cachelines before reading the target if
548 * needs_clflush is set. */
550 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
551 char __user *user_data,
552 bool page_do_bit17_swizzling, bool needs_clflush)
557 if (unlikely(page_do_bit17_swizzling))
560 vaddr = kmap_atomic(page);
562 drm_clflush_virt_range(vaddr + shmem_page_offset,
564 ret = __copy_to_user_inatomic(user_data,
565 vaddr + shmem_page_offset,
567 kunmap_atomic(vaddr);
569 return ret ? -EFAULT : 0;
573 shmem_clflush_swizzled_range(char *addr, unsigned long length,
576 if (unlikely(swizzled)) {
577 unsigned long start = (unsigned long) addr;
578 unsigned long end = (unsigned long) addr + length;
580 /* For swizzling simply ensure that we always flush both
581 * channels. Lame, but simple and it works. Swizzled
582 * pwrite/pread is far from a hotpath - current userspace
583 * doesn't use it at all. */
584 start = round_down(start, 128);
585 end = round_up(end, 128);
587 drm_clflush_virt_range((void *)start, end - start);
589 drm_clflush_virt_range(addr, length);
594 /* Only difference to the fast-path function is that this can handle bit17
595 * and uses non-atomic copy and kmap functions. */
597 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
598 char __user *user_data,
599 bool page_do_bit17_swizzling, bool needs_clflush)
606 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
608 page_do_bit17_swizzling);
610 if (page_do_bit17_swizzling)
611 ret = __copy_to_user_swizzled(user_data,
612 vaddr, shmem_page_offset,
615 ret = __copy_to_user(user_data,
616 vaddr + shmem_page_offset,
620 return ret ? - EFAULT : 0;
624 i915_gem_shmem_pread(struct drm_device *dev,
625 struct drm_i915_gem_object *obj,
626 struct drm_i915_gem_pread *args,
627 struct drm_file *file)
629 char __user *user_data;
632 int shmem_page_offset, page_length, ret = 0;
633 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
635 int needs_clflush = 0;
636 struct sg_page_iter sg_iter;
638 user_data = to_user_ptr(args->data_ptr);
641 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
643 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
647 offset = args->offset;
649 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
650 offset >> PAGE_SHIFT) {
651 struct page *page = sg_page_iter_page(&sg_iter);
656 /* Operation in this page
658 * shmem_page_offset = offset within page in shmem file
659 * page_length = bytes to copy for this page
661 shmem_page_offset = offset_in_page(offset);
662 page_length = remain;
663 if ((shmem_page_offset + page_length) > PAGE_SIZE)
664 page_length = PAGE_SIZE - shmem_page_offset;
666 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
667 (page_to_phys(page) & (1 << 17)) != 0;
669 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
670 user_data, page_do_bit17_swizzling,
675 mutex_unlock(&dev->struct_mutex);
677 if (likely(!i915.prefault_disable) && !prefaulted) {
678 ret = fault_in_multipages_writeable(user_data, remain);
679 /* Userspace is tricking us, but we've already clobbered
680 * its pages with the prefault and promised to write the
681 * data up to the first fault. Hence ignore any errors
682 * and just continue. */
687 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
688 user_data, page_do_bit17_swizzling,
691 mutex_lock(&dev->struct_mutex);
697 remain -= page_length;
698 user_data += page_length;
699 offset += page_length;
703 i915_gem_object_unpin_pages(obj);
709 * Reads data from the object referenced by handle.
711 * On error, the contents of *data are undefined.
714 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
715 struct drm_file *file)
717 struct drm_i915_gem_pread *args = data;
718 struct drm_i915_gem_object *obj;
724 if (!access_ok(VERIFY_WRITE,
725 to_user_ptr(args->data_ptr),
729 ret = i915_mutex_lock_interruptible(dev);
733 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
734 if (&obj->base == NULL) {
739 /* Bounds check source. */
740 if (args->offset > obj->base.size ||
741 args->size > obj->base.size - args->offset) {
746 /* prime objects have no backing filp to GEM pread/pwrite
749 if (!obj->base.filp) {
754 trace_i915_gem_object_pread(obj, args->offset, args->size);
756 ret = i915_gem_shmem_pread(dev, obj, args, file);
759 drm_gem_object_unreference(&obj->base);
761 mutex_unlock(&dev->struct_mutex);
765 /* This is the fast write path which cannot handle
766 * page faults in the source data
770 fast_user_write(struct io_mapping *mapping,
771 loff_t page_base, int page_offset,
772 char __user *user_data,
775 void __iomem *vaddr_atomic;
777 unsigned long unwritten;
779 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
780 /* We can use the cpu mem copy function because this is X86. */
781 vaddr = (void __force*)vaddr_atomic + page_offset;
782 unwritten = __copy_from_user_inatomic_nocache(vaddr,
784 io_mapping_unmap_atomic(vaddr_atomic);
789 * This is the fast pwrite path, where we copy the data directly from the
790 * user into the GTT, uncached.
793 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
794 struct drm_i915_gem_object *obj,
795 struct drm_i915_gem_pwrite *args,
796 struct drm_file *file)
798 struct drm_i915_private *dev_priv = dev->dev_private;
800 loff_t offset, page_base;
801 char __user *user_data;
802 int page_offset, page_length, ret;
804 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
808 ret = i915_gem_object_set_to_gtt_domain(obj, true);
812 ret = i915_gem_object_put_fence(obj);
816 user_data = to_user_ptr(args->data_ptr);
819 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
822 /* Operation in this page
824 * page_base = page offset within aperture
825 * page_offset = offset within page
826 * page_length = bytes to copy for this page
828 page_base = offset & PAGE_MASK;
829 page_offset = offset_in_page(offset);
830 page_length = remain;
831 if ((page_offset + remain) > PAGE_SIZE)
832 page_length = PAGE_SIZE - page_offset;
834 /* If we get a fault while copying data, then (presumably) our
835 * source page isn't available. Return the error and we'll
836 * retry in the slow path.
838 if (fast_user_write(dev_priv->gtt.mappable, page_base,
839 page_offset, user_data, page_length)) {
844 remain -= page_length;
845 user_data += page_length;
846 offset += page_length;
850 i915_gem_object_ggtt_unpin(obj);
855 /* Per-page copy function for the shmem pwrite fastpath.
856 * Flushes invalid cachelines before writing to the target if
857 * needs_clflush_before is set and flushes out any written cachelines after
858 * writing if needs_clflush is set. */
860 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
861 char __user *user_data,
862 bool page_do_bit17_swizzling,
863 bool needs_clflush_before,
864 bool needs_clflush_after)
869 if (unlikely(page_do_bit17_swizzling))
872 vaddr = kmap_atomic(page);
873 if (needs_clflush_before)
874 drm_clflush_virt_range(vaddr + shmem_page_offset,
876 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
877 user_data, page_length);
878 if (needs_clflush_after)
879 drm_clflush_virt_range(vaddr + shmem_page_offset,
881 kunmap_atomic(vaddr);
883 return ret ? -EFAULT : 0;
886 /* Only difference to the fast-path function is that this can handle bit17
887 * and uses non-atomic copy and kmap functions. */
889 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
890 char __user *user_data,
891 bool page_do_bit17_swizzling,
892 bool needs_clflush_before,
893 bool needs_clflush_after)
899 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
900 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
902 page_do_bit17_swizzling);
903 if (page_do_bit17_swizzling)
904 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
908 ret = __copy_from_user(vaddr + shmem_page_offset,
911 if (needs_clflush_after)
912 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
914 page_do_bit17_swizzling);
917 return ret ? -EFAULT : 0;
921 i915_gem_shmem_pwrite(struct drm_device *dev,
922 struct drm_i915_gem_object *obj,
923 struct drm_i915_gem_pwrite *args,
924 struct drm_file *file)
928 char __user *user_data;
929 int shmem_page_offset, page_length, ret = 0;
930 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
931 int hit_slowpath = 0;
932 int needs_clflush_after = 0;
933 int needs_clflush_before = 0;
934 struct sg_page_iter sg_iter;
936 user_data = to_user_ptr(args->data_ptr);
939 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
941 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
942 /* If we're not in the cpu write domain, set ourself into the gtt
943 * write domain and manually flush cachelines (if required). This
944 * optimizes for the case when the gpu will use the data
945 * right away and we therefore have to clflush anyway. */
946 needs_clflush_after = cpu_write_needs_clflush(obj);
947 ret = i915_gem_object_wait_rendering(obj, false);
951 i915_gem_object_retire(obj);
953 /* Same trick applies to invalidate partially written cachelines read
955 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
956 needs_clflush_before =
957 !cpu_cache_is_coherent(dev, obj->cache_level);
959 ret = i915_gem_object_get_pages(obj);
963 i915_gem_object_pin_pages(obj);
965 offset = args->offset;
968 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
969 offset >> PAGE_SHIFT) {
970 struct page *page = sg_page_iter_page(&sg_iter);
971 int partial_cacheline_write;
976 /* Operation in this page
978 * shmem_page_offset = offset within page in shmem file
979 * page_length = bytes to copy for this page
981 shmem_page_offset = offset_in_page(offset);
983 page_length = remain;
984 if ((shmem_page_offset + page_length) > PAGE_SIZE)
985 page_length = PAGE_SIZE - shmem_page_offset;
987 /* If we don't overwrite a cacheline completely we need to be
988 * careful to have up-to-date data by first clflushing. Don't
989 * overcomplicate things and flush the entire patch. */
990 partial_cacheline_write = needs_clflush_before &&
991 ((shmem_page_offset | page_length)
992 & (boot_cpu_data.x86_clflush_size - 1));
994 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
995 (page_to_phys(page) & (1 << 17)) != 0;
997 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
998 user_data, page_do_bit17_swizzling,
999 partial_cacheline_write,
1000 needs_clflush_after);
1005 mutex_unlock(&dev->struct_mutex);
1006 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1007 user_data, page_do_bit17_swizzling,
1008 partial_cacheline_write,
1009 needs_clflush_after);
1011 mutex_lock(&dev->struct_mutex);
1017 remain -= page_length;
1018 user_data += page_length;
1019 offset += page_length;
1023 i915_gem_object_unpin_pages(obj);
1027 * Fixup: Flush cpu caches in case we didn't flush the dirty
1028 * cachelines in-line while writing and the object moved
1029 * out of the cpu write domain while we've dropped the lock.
1031 if (!needs_clflush_after &&
1032 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1033 if (i915_gem_clflush_object(obj, obj->pin_display))
1034 i915_gem_chipset_flush(dev);
1038 if (needs_clflush_after)
1039 i915_gem_chipset_flush(dev);
1045 * Writes data to the object referenced by handle.
1047 * On error, the contents of the buffer that were to be modified are undefined.
1050 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1051 struct drm_file *file)
1053 struct drm_i915_gem_pwrite *args = data;
1054 struct drm_i915_gem_object *obj;
1057 if (args->size == 0)
1060 if (!access_ok(VERIFY_READ,
1061 to_user_ptr(args->data_ptr),
1065 if (likely(!i915.prefault_disable)) {
1066 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1072 ret = i915_mutex_lock_interruptible(dev);
1076 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1077 if (&obj->base == NULL) {
1082 /* Bounds check destination. */
1083 if (args->offset > obj->base.size ||
1084 args->size > obj->base.size - args->offset) {
1089 /* prime objects have no backing filp to GEM pread/pwrite
1092 if (!obj->base.filp) {
1097 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1100 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1101 * it would end up going through the fenced access, and we'll get
1102 * different detiling behavior between reading and writing.
1103 * pread/pwrite currently are reading and writing from the CPU
1104 * perspective, requiring manual detiling by the client.
1106 if (obj->tiling_mode == I915_TILING_NONE &&
1107 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1108 cpu_write_needs_clflush(obj)) {
1109 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1110 /* Note that the gtt paths might fail with non-page-backed user
1111 * pointers (e.g. gtt mappings when moving data between
1112 * textures). Fallback to the shmem path in that case. */
1115 if (ret == -EFAULT || ret == -ENOSPC) {
1116 if (obj->phys_handle)
1117 ret = i915_gem_phys_pwrite(obj, args, file);
1119 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1123 drm_gem_object_unreference(&obj->base);
1125 mutex_unlock(&dev->struct_mutex);
1130 i915_gem_check_wedge(struct i915_gpu_error *error,
1133 if (i915_reset_in_progress(error)) {
1134 /* Non-interruptible callers can't handle -EAGAIN, hence return
1135 * -EIO unconditionally for these. */
1139 /* Recovery complete, but the reset failed ... */
1140 if (i915_terminally_wedged(error))
1144 * Check if GPU Reset is in progress - we need intel_ring_begin
1145 * to work properly to reinit the hw state while the gpu is
1146 * still marked as reset-in-progress. Handle this with a flag.
1148 if (!error->reload_in_reset)
1156 * Compare arbitrary request against outstanding lazy request. Emit on match.
1159 i915_gem_check_olr(struct drm_i915_gem_request *req)
1163 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1166 if (req == req->ring->outstanding_lazy_request)
1167 ret = i915_add_request(req->ring);
1172 static void fake_irq(unsigned long data)
1174 wake_up_process((struct task_struct *)data);
1177 static bool missed_irq(struct drm_i915_private *dev_priv,
1178 struct intel_engine_cs *ring)
1180 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1183 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1185 if (file_priv == NULL)
1188 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1192 * __i915_wait_request - wait until execution of request has finished
1194 * @reset_counter: reset sequence associated with the given request
1195 * @interruptible: do an interruptible wait (normally yes)
1196 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1198 * Note: It is of utmost importance that the passed in seqno and reset_counter
1199 * values have been read by the caller in an smp safe manner. Where read-side
1200 * locks are involved, it is sufficient to read the reset_counter before
1201 * unlocking the lock that protects the seqno. For lockless tricks, the
1202 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1205 * Returns 0 if the request was found within the alloted time. Else returns the
1206 * errno with remaining time filled in timeout argument.
1208 int __i915_wait_request(struct drm_i915_gem_request *req,
1209 unsigned reset_counter,
1212 struct drm_i915_file_private *file_priv)
1214 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1215 struct drm_device *dev = ring->dev;
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217 const bool irq_test_in_progress =
1218 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1220 unsigned long timeout_expire;
1224 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1226 if (i915_gem_request_completed(req, true))
1229 timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1231 if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1232 gen6_rps_boost(dev_priv);
1234 mod_delayed_work(dev_priv->wq,
1235 &file_priv->mm.idle_work,
1236 msecs_to_jiffies(100));
1239 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1242 /* Record current time in case interrupted by signal, or wedged */
1243 trace_i915_gem_request_wait_begin(req);
1244 before = ktime_get_raw_ns();
1246 struct timer_list timer;
1248 prepare_to_wait(&ring->irq_queue, &wait,
1249 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1251 /* We need to check whether any gpu reset happened in between
1252 * the caller grabbing the seqno and now ... */
1253 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1254 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1255 * is truely gone. */
1256 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1262 if (i915_gem_request_completed(req, false)) {
1267 if (interruptible && signal_pending(current)) {
1272 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1277 timer.function = NULL;
1278 if (timeout || missed_irq(dev_priv, ring)) {
1279 unsigned long expire;
1281 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1282 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1283 mod_timer(&timer, expire);
1288 if (timer.function) {
1289 del_singleshot_timer_sync(&timer);
1290 destroy_timer_on_stack(&timer);
1293 now = ktime_get_raw_ns();
1294 trace_i915_gem_request_wait_end(req);
1296 if (!irq_test_in_progress)
1297 ring->irq_put(ring);
1299 finish_wait(&ring->irq_queue, &wait);
1302 s64 tres = *timeout - (now - before);
1304 *timeout = tres < 0 ? 0 : tres;
1311 * Waits for a request to be signaled, and cleans up the
1312 * request and object lists appropriately for that event.
1315 i915_wait_request(struct drm_i915_gem_request *req)
1317 struct drm_device *dev;
1318 struct drm_i915_private *dev_priv;
1320 unsigned reset_counter;
1323 BUG_ON(req == NULL);
1325 dev = req->ring->dev;
1326 dev_priv = dev->dev_private;
1327 interruptible = dev_priv->mm.interruptible;
1329 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1331 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1335 ret = i915_gem_check_olr(req);
1339 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1340 i915_gem_request_reference(req);
1341 ret = __i915_wait_request(req, reset_counter,
1342 interruptible, NULL, NULL);
1343 i915_gem_request_unreference(req);
1348 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1353 /* Manually manage the write flush as we may have not yet
1354 * retired the buffer.
1356 * Note that the last_write_req is always the earlier of
1357 * the two (read/write) requests, so if we haved successfully waited,
1358 * we know we have passed the last write.
1360 i915_gem_request_assign(&obj->last_write_req, NULL);
1366 * Ensures that all rendering to the object has completed and the object is
1367 * safe to unbind from the GTT or access from the CPU.
1369 static __must_check int
1370 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1373 struct drm_i915_gem_request *req;
1376 req = readonly ? obj->last_write_req : obj->last_read_req;
1380 ret = i915_wait_request(req);
1384 return i915_gem_object_wait_rendering__tail(obj);
1387 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1388 * as the object state may change during this call.
1390 static __must_check int
1391 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1392 struct drm_i915_file_private *file_priv,
1395 struct drm_i915_gem_request *req;
1396 struct drm_device *dev = obj->base.dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private;
1398 unsigned reset_counter;
1401 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1402 BUG_ON(!dev_priv->mm.interruptible);
1404 req = readonly ? obj->last_write_req : obj->last_read_req;
1408 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1412 ret = i915_gem_check_olr(req);
1416 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1417 i915_gem_request_reference(req);
1418 mutex_unlock(&dev->struct_mutex);
1419 ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv);
1420 mutex_lock(&dev->struct_mutex);
1421 i915_gem_request_unreference(req);
1425 return i915_gem_object_wait_rendering__tail(obj);
1429 * Called when user space prepares to use an object with the CPU, either
1430 * through the mmap ioctl's mapping or a GTT mapping.
1433 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1434 struct drm_file *file)
1436 struct drm_i915_gem_set_domain *args = data;
1437 struct drm_i915_gem_object *obj;
1438 uint32_t read_domains = args->read_domains;
1439 uint32_t write_domain = args->write_domain;
1442 /* Only handle setting domains to types used by the CPU. */
1443 if (write_domain & I915_GEM_GPU_DOMAINS)
1446 if (read_domains & I915_GEM_GPU_DOMAINS)
1449 /* Having something in the write domain implies it's in the read
1450 * domain, and only that read domain. Enforce that in the request.
1452 if (write_domain != 0 && read_domains != write_domain)
1455 ret = i915_mutex_lock_interruptible(dev);
1459 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1460 if (&obj->base == NULL) {
1465 /* Try to flush the object off the GPU without holding the lock.
1466 * We will repeat the flush holding the lock in the normal manner
1467 * to catch cases where we are gazumped.
1469 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1475 if (read_domains & I915_GEM_DOMAIN_GTT) {
1476 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1478 /* Silently promote "you're not bound, there was nothing to do"
1479 * to success, since the client was just asking us to
1480 * make sure everything was done.
1485 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1489 drm_gem_object_unreference(&obj->base);
1491 mutex_unlock(&dev->struct_mutex);
1496 * Called when user space has done writes to this buffer
1499 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1500 struct drm_file *file)
1502 struct drm_i915_gem_sw_finish *args = data;
1503 struct drm_i915_gem_object *obj;
1506 ret = i915_mutex_lock_interruptible(dev);
1510 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1511 if (&obj->base == NULL) {
1516 /* Pinned buffers may be scanout, so flush the cache */
1517 if (obj->pin_display)
1518 i915_gem_object_flush_cpu_write_domain(obj, true);
1520 drm_gem_object_unreference(&obj->base);
1522 mutex_unlock(&dev->struct_mutex);
1527 * Maps the contents of an object, returning the address it is mapped
1530 * While the mapping holds a reference on the contents of the object, it doesn't
1531 * imply a ref on the object itself.
1535 * DRM driver writers who look a this function as an example for how to do GEM
1536 * mmap support, please don't implement mmap support like here. The modern way
1537 * to implement DRM mmap support is with an mmap offset ioctl (like
1538 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1539 * That way debug tooling like valgrind will understand what's going on, hiding
1540 * the mmap call in a driver private ioctl will break that. The i915 driver only
1541 * does cpu mmaps this way because we didn't know better.
1544 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1545 struct drm_file *file)
1547 struct drm_i915_gem_mmap *args = data;
1548 struct drm_gem_object *obj;
1551 obj = drm_gem_object_lookup(dev, file, args->handle);
1555 /* prime objects have no backing filp to GEM mmap
1559 drm_gem_object_unreference_unlocked(obj);
1563 addr = vm_mmap(obj->filp, 0, args->size,
1564 PROT_READ | PROT_WRITE, MAP_SHARED,
1566 drm_gem_object_unreference_unlocked(obj);
1567 if (IS_ERR((void *)addr))
1570 args->addr_ptr = (uint64_t) addr;
1576 * i915_gem_fault - fault a page into the GTT
1577 * vma: VMA in question
1580 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1581 * from userspace. The fault handler takes care of binding the object to
1582 * the GTT (if needed), allocating and programming a fence register (again,
1583 * only if needed based on whether the old reg is still valid or the object
1584 * is tiled) and inserting a new PTE into the faulting process.
1586 * Note that the faulting process may involve evicting existing objects
1587 * from the GTT and/or fence registers to make room. So performance may
1588 * suffer if the GTT working set is large or there are few fence registers
1591 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1593 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1594 struct drm_device *dev = obj->base.dev;
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596 pgoff_t page_offset;
1599 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1601 intel_runtime_pm_get(dev_priv);
1603 /* We don't use vmf->pgoff since that has the fake offset */
1604 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1607 ret = i915_mutex_lock_interruptible(dev);
1611 trace_i915_gem_object_fault(obj, page_offset, true, write);
1613 /* Try to flush the object off the GPU first without holding the lock.
1614 * Upon reacquiring the lock, we will perform our sanity checks and then
1615 * repeat the flush holding the lock in the normal manner to catch cases
1616 * where we are gazumped.
1618 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1622 /* Access to snoopable pages through the GTT is incoherent. */
1623 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1628 /* Now bind it into the GTT if needed */
1629 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1633 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1637 ret = i915_gem_object_get_fence(obj);
1641 /* Finally, remap it using the new GTT offset */
1642 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1645 if (!obj->fault_mappable) {
1646 unsigned long size = min_t(unsigned long,
1647 vma->vm_end - vma->vm_start,
1651 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1652 ret = vm_insert_pfn(vma,
1653 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1659 obj->fault_mappable = true;
1661 ret = vm_insert_pfn(vma,
1662 (unsigned long)vmf->virtual_address,
1665 i915_gem_object_ggtt_unpin(obj);
1667 mutex_unlock(&dev->struct_mutex);
1672 * We eat errors when the gpu is terminally wedged to avoid
1673 * userspace unduly crashing (gl has no provisions for mmaps to
1674 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1675 * and so needs to be reported.
1677 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1678 ret = VM_FAULT_SIGBUS;
1683 * EAGAIN means the gpu is hung and we'll wait for the error
1684 * handler to reset everything when re-faulting in
1685 * i915_mutex_lock_interruptible.
1692 * EBUSY is ok: this just means that another thread
1693 * already did the job.
1695 ret = VM_FAULT_NOPAGE;
1702 ret = VM_FAULT_SIGBUS;
1705 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1706 ret = VM_FAULT_SIGBUS;
1710 intel_runtime_pm_put(dev_priv);
1715 * i915_gem_release_mmap - remove physical page mappings
1716 * @obj: obj in question
1718 * Preserve the reservation of the mmapping with the DRM core code, but
1719 * relinquish ownership of the pages back to the system.
1721 * It is vital that we remove the page mapping if we have mapped a tiled
1722 * object through the GTT and then lose the fence register due to
1723 * resource pressure. Similarly if the object has been moved out of the
1724 * aperture, than pages mapped into userspace must be revoked. Removing the
1725 * mapping will then trigger a page fault on the next user access, allowing
1726 * fixup by i915_gem_fault().
1729 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1731 if (!obj->fault_mappable)
1734 drm_vma_node_unmap(&obj->base.vma_node,
1735 obj->base.dev->anon_inode->i_mapping);
1736 obj->fault_mappable = false;
1740 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1742 struct drm_i915_gem_object *obj;
1744 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1745 i915_gem_release_mmap(obj);
1749 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1753 if (INTEL_INFO(dev)->gen >= 4 ||
1754 tiling_mode == I915_TILING_NONE)
1757 /* Previous chips need a power-of-two fence region when tiling */
1758 if (INTEL_INFO(dev)->gen == 3)
1759 gtt_size = 1024*1024;
1761 gtt_size = 512*1024;
1763 while (gtt_size < size)
1770 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1771 * @obj: object to check
1773 * Return the required GTT alignment for an object, taking into account
1774 * potential fence register mapping.
1777 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1778 int tiling_mode, bool fenced)
1781 * Minimum alignment is 4k (GTT page size), but might be greater
1782 * if a fence register is needed for the object.
1784 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1785 tiling_mode == I915_TILING_NONE)
1789 * Previous chips need to be aligned to the size of the smallest
1790 * fence register that can contain the object.
1792 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1795 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1797 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1800 if (drm_vma_node_has_offset(&obj->base.vma_node))
1803 dev_priv->mm.shrinker_no_lock_stealing = true;
1805 ret = drm_gem_create_mmap_offset(&obj->base);
1809 /* Badly fragmented mmap space? The only way we can recover
1810 * space is by destroying unwanted objects. We can't randomly release
1811 * mmap_offsets as userspace expects them to be persistent for the
1812 * lifetime of the objects. The closest we can is to release the
1813 * offsets on purgeable objects by truncating it and marking it purged,
1814 * which prevents userspace from ever using that object again.
1816 i915_gem_shrink(dev_priv,
1817 obj->base.size >> PAGE_SHIFT,
1819 I915_SHRINK_UNBOUND |
1820 I915_SHRINK_PURGEABLE);
1821 ret = drm_gem_create_mmap_offset(&obj->base);
1825 i915_gem_shrink_all(dev_priv);
1826 ret = drm_gem_create_mmap_offset(&obj->base);
1828 dev_priv->mm.shrinker_no_lock_stealing = false;
1833 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1835 drm_gem_free_mmap_offset(&obj->base);
1839 i915_gem_mmap_gtt(struct drm_file *file,
1840 struct drm_device *dev,
1841 uint32_t handle, bool dumb,
1844 struct drm_i915_private *dev_priv = dev->dev_private;
1845 struct drm_i915_gem_object *obj;
1848 ret = i915_mutex_lock_interruptible(dev);
1852 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1853 if (&obj->base == NULL) {
1859 * We don't allow dumb mmaps on objects created using another
1862 WARN_ONCE(dumb && !(obj->base.dumb || obj->base.import_attach),
1863 "Illegal dumb map of accelerated buffer.\n");
1865 if (obj->base.size > dev_priv->gtt.mappable_end) {
1870 if (obj->madv != I915_MADV_WILLNEED) {
1871 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1876 ret = i915_gem_object_create_mmap_offset(obj);
1880 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1883 drm_gem_object_unreference(&obj->base);
1885 mutex_unlock(&dev->struct_mutex);
1890 i915_gem_dumb_map_offset(struct drm_file *file,
1891 struct drm_device *dev,
1895 return i915_gem_mmap_gtt(file, dev, handle, true, offset);
1899 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1901 * @data: GTT mapping ioctl data
1902 * @file: GEM object info
1904 * Simply returns the fake offset to userspace so it can mmap it.
1905 * The mmap call will end up in drm_gem_mmap(), which will set things
1906 * up so we can get faults in the handler above.
1908 * The fault handler will take care of binding the object into the GTT
1909 * (since it may have been evicted to make room for something), allocating
1910 * a fence register, and mapping the appropriate aperture address into
1914 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1915 struct drm_file *file)
1917 struct drm_i915_gem_mmap_gtt *args = data;
1919 return i915_gem_mmap_gtt(file, dev, args->handle, false, &args->offset);
1923 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1925 return obj->madv == I915_MADV_DONTNEED;
1928 /* Immediately discard the backing storage */
1930 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1932 i915_gem_object_free_mmap_offset(obj);
1934 if (obj->base.filp == NULL)
1937 /* Our goal here is to return as much of the memory as
1938 * is possible back to the system as we are called from OOM.
1939 * To do this we must instruct the shmfs to drop all of its
1940 * backing pages, *now*.
1942 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1943 obj->madv = __I915_MADV_PURGED;
1946 /* Try to discard unwanted pages */
1948 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1950 struct address_space *mapping;
1952 switch (obj->madv) {
1953 case I915_MADV_DONTNEED:
1954 i915_gem_object_truncate(obj);
1955 case __I915_MADV_PURGED:
1959 if (obj->base.filp == NULL)
1962 mapping = file_inode(obj->base.filp)->i_mapping,
1963 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1967 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1969 struct sg_page_iter sg_iter;
1972 BUG_ON(obj->madv == __I915_MADV_PURGED);
1974 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1976 /* In the event of a disaster, abandon all caches and
1977 * hope for the best.
1979 WARN_ON(ret != -EIO);
1980 i915_gem_clflush_object(obj, true);
1981 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1984 if (i915_gem_object_needs_bit17_swizzle(obj))
1985 i915_gem_object_save_bit_17_swizzle(obj);
1987 if (obj->madv == I915_MADV_DONTNEED)
1990 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1991 struct page *page = sg_page_iter_page(&sg_iter);
1994 set_page_dirty(page);
1996 if (obj->madv == I915_MADV_WILLNEED)
1997 mark_page_accessed(page);
1999 page_cache_release(page);
2003 sg_free_table(obj->pages);
2008 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2010 const struct drm_i915_gem_object_ops *ops = obj->ops;
2012 if (obj->pages == NULL)
2015 if (obj->pages_pin_count)
2018 BUG_ON(i915_gem_obj_bound_any(obj));
2020 /* ->put_pages might need to allocate memory for the bit17 swizzle
2021 * array, hence protect them from being reaped by removing them from gtt
2023 list_del(&obj->global_list);
2025 ops->put_pages(obj);
2028 i915_gem_object_invalidate(obj);
2034 i915_gem_shrink(struct drm_i915_private *dev_priv,
2035 long target, unsigned flags)
2038 struct list_head *list;
2041 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2042 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2045 unsigned long count = 0;
2048 * As we may completely rewrite the (un)bound list whilst unbinding
2049 * (due to retiring requests) we have to strictly process only
2050 * one element of the list at the time, and recheck the list
2051 * on every iteration.
2053 * In particular, we must hold a reference whilst removing the
2054 * object as we may end up waiting for and/or retiring the objects.
2055 * This might release the final reference (held by the active list)
2056 * and result in the object being freed from under us. This is
2057 * similar to the precautions the eviction code must take whilst
2060 * Also note that although these lists do not hold a reference to
2061 * the object we can safely grab one here: The final object
2062 * unreferencing and the bound_list are both protected by the
2063 * dev->struct_mutex and so we won't ever be able to observe an
2064 * object on the bound_list with a reference count equals 0.
2066 for (phase = phases; phase->list; phase++) {
2067 struct list_head still_in_list;
2069 if ((flags & phase->bit) == 0)
2072 INIT_LIST_HEAD(&still_in_list);
2073 while (count < target && !list_empty(phase->list)) {
2074 struct drm_i915_gem_object *obj;
2075 struct i915_vma *vma, *v;
2077 obj = list_first_entry(phase->list,
2078 typeof(*obj), global_list);
2079 list_move_tail(&obj->global_list, &still_in_list);
2081 if (flags & I915_SHRINK_PURGEABLE &&
2082 !i915_gem_object_is_purgeable(obj))
2085 drm_gem_object_reference(&obj->base);
2087 /* For the unbound phase, this should be a no-op! */
2088 list_for_each_entry_safe(vma, v,
2089 &obj->vma_list, vma_link)
2090 if (i915_vma_unbind(vma))
2093 if (i915_gem_object_put_pages(obj) == 0)
2094 count += obj->base.size >> PAGE_SHIFT;
2096 drm_gem_object_unreference(&obj->base);
2098 list_splice(&still_in_list, phase->list);
2104 static unsigned long
2105 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2107 i915_gem_evict_everything(dev_priv->dev);
2108 return i915_gem_shrink(dev_priv, LONG_MAX,
2109 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2113 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2115 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2117 struct address_space *mapping;
2118 struct sg_table *st;
2119 struct scatterlist *sg;
2120 struct sg_page_iter sg_iter;
2122 unsigned long last_pfn = 0; /* suppress gcc warning */
2125 /* Assert that the object is not currently in any GPU domain. As it
2126 * wasn't in the GTT, there shouldn't be any way it could have been in
2129 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2130 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2132 st = kmalloc(sizeof(*st), GFP_KERNEL);
2136 page_count = obj->base.size / PAGE_SIZE;
2137 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2142 /* Get the list of pages out of our struct file. They'll be pinned
2143 * at this point until we release them.
2145 * Fail silently without starting the shrinker
2147 mapping = file_inode(obj->base.filp)->i_mapping;
2148 gfp = mapping_gfp_mask(mapping);
2149 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2150 gfp &= ~(__GFP_IO | __GFP_WAIT);
2153 for (i = 0; i < page_count; i++) {
2154 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2156 i915_gem_shrink(dev_priv,
2159 I915_SHRINK_UNBOUND |
2160 I915_SHRINK_PURGEABLE);
2161 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2164 /* We've tried hard to allocate the memory by reaping
2165 * our own buffer, now let the real VM do its job and
2166 * go down in flames if truly OOM.
2168 i915_gem_shrink_all(dev_priv);
2169 page = shmem_read_mapping_page(mapping, i);
2173 #ifdef CONFIG_SWIOTLB
2174 if (swiotlb_nr_tbl()) {
2176 sg_set_page(sg, page, PAGE_SIZE, 0);
2181 if (!i || page_to_pfn(page) != last_pfn + 1) {
2185 sg_set_page(sg, page, PAGE_SIZE, 0);
2187 sg->length += PAGE_SIZE;
2189 last_pfn = page_to_pfn(page);
2191 /* Check that the i965g/gm workaround works. */
2192 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2194 #ifdef CONFIG_SWIOTLB
2195 if (!swiotlb_nr_tbl())
2200 if (i915_gem_object_needs_bit17_swizzle(obj))
2201 i915_gem_object_do_bit_17_swizzle(obj);
2203 if (obj->tiling_mode != I915_TILING_NONE &&
2204 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2205 i915_gem_object_pin_pages(obj);
2211 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2212 page_cache_release(sg_page_iter_page(&sg_iter));
2216 /* shmemfs first checks if there is enough memory to allocate the page
2217 * and reports ENOSPC should there be insufficient, along with the usual
2218 * ENOMEM for a genuine allocation failure.
2220 * We use ENOSPC in our driver to mean that we have run out of aperture
2221 * space and so want to translate the error from shmemfs back to our
2222 * usual understanding of ENOMEM.
2224 if (PTR_ERR(page) == -ENOSPC)
2227 return PTR_ERR(page);
2230 /* Ensure that the associated pages are gathered from the backing storage
2231 * and pinned into our object. i915_gem_object_get_pages() may be called
2232 * multiple times before they are released by a single call to
2233 * i915_gem_object_put_pages() - once the pages are no longer referenced
2234 * either as a result of memory pressure (reaping pages under the shrinker)
2235 * or as the object is itself released.
2238 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2240 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2241 const struct drm_i915_gem_object_ops *ops = obj->ops;
2247 if (obj->madv != I915_MADV_WILLNEED) {
2248 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2252 BUG_ON(obj->pages_pin_count);
2254 ret = ops->get_pages(obj);
2258 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2263 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2264 struct intel_engine_cs *ring)
2266 struct drm_i915_gem_request *req = intel_ring_get_request(ring);
2268 BUG_ON(ring == NULL);
2269 if (obj->ring != ring && obj->last_write_req) {
2270 /* Keep the request relative to the current ring */
2271 i915_gem_request_assign(&obj->last_write_req, req);
2275 /* Add a reference if we're newly entering the active list. */
2277 drm_gem_object_reference(&obj->base);
2281 list_move_tail(&obj->ring_list, &ring->active_list);
2283 i915_gem_request_assign(&obj->last_read_req, req);
2286 void i915_vma_move_to_active(struct i915_vma *vma,
2287 struct intel_engine_cs *ring)
2289 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2290 return i915_gem_object_move_to_active(vma->obj, ring);
2294 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2296 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2297 struct i915_address_space *vm;
2298 struct i915_vma *vma;
2300 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2301 BUG_ON(!obj->active);
2303 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2304 vma = i915_gem_obj_to_vma(obj, vm);
2305 if (vma && !list_empty(&vma->mm_list))
2306 list_move_tail(&vma->mm_list, &vm->inactive_list);
2309 intel_fb_obj_flush(obj, true);
2311 list_del_init(&obj->ring_list);
2314 i915_gem_request_assign(&obj->last_read_req, NULL);
2315 i915_gem_request_assign(&obj->last_write_req, NULL);
2316 obj->base.write_domain = 0;
2318 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2321 drm_gem_object_unreference(&obj->base);
2323 WARN_ON(i915_verify_lists(dev));
2327 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2329 struct intel_engine_cs *ring = obj->ring;
2334 if (i915_gem_request_completed(obj->last_read_req, true))
2335 i915_gem_object_move_to_inactive(obj);
2339 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2341 struct drm_i915_private *dev_priv = dev->dev_private;
2342 struct intel_engine_cs *ring;
2345 /* Carefully retire all requests without writing to the rings */
2346 for_each_ring(ring, dev_priv, i) {
2347 ret = intel_ring_idle(ring);
2351 i915_gem_retire_requests(dev);
2353 /* Finally reset hw state */
2354 for_each_ring(ring, dev_priv, i) {
2355 intel_ring_init_seqno(ring, seqno);
2357 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2358 ring->semaphore.sync_seqno[j] = 0;
2364 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2372 /* HWS page needs to be set less than what we
2373 * will inject to ring
2375 ret = i915_gem_init_seqno(dev, seqno - 1);
2379 /* Carefully set the last_seqno value so that wrap
2380 * detection still works
2382 dev_priv->next_seqno = seqno;
2383 dev_priv->last_seqno = seqno - 1;
2384 if (dev_priv->last_seqno == 0)
2385 dev_priv->last_seqno--;
2391 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2395 /* reserve 0 for non-seqno */
2396 if (dev_priv->next_seqno == 0) {
2397 int ret = i915_gem_init_seqno(dev, 0);
2401 dev_priv->next_seqno = 1;
2404 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2408 int __i915_add_request(struct intel_engine_cs *ring,
2409 struct drm_file *file,
2410 struct drm_i915_gem_object *obj)
2412 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2413 struct drm_i915_gem_request *request;
2414 struct intel_ringbuffer *ringbuf;
2415 u32 request_ring_position, request_start;
2418 request = ring->outstanding_lazy_request;
2419 if (WARN_ON(request == NULL))
2422 if (i915.enable_execlists) {
2423 struct intel_context *ctx = request->ctx;
2424 ringbuf = ctx->engine[ring->id].ringbuf;
2426 ringbuf = ring->buffer;
2428 request_start = intel_ring_get_tail(ringbuf);
2430 * Emit any outstanding flushes - execbuf can fail to emit the flush
2431 * after having emitted the batchbuffer command. Hence we need to fix
2432 * things up similar to emitting the lazy request. The difference here
2433 * is that the flush _must_ happen before the next request, no matter
2436 if (i915.enable_execlists) {
2437 ret = logical_ring_flush_all_caches(ringbuf);
2441 ret = intel_ring_flush_all_caches(ring);
2446 /* Record the position of the start of the request so that
2447 * should we detect the updated seqno part-way through the
2448 * GPU processing the request, we never over-estimate the
2449 * position of the head.
2451 request_ring_position = intel_ring_get_tail(ringbuf);
2453 if (i915.enable_execlists) {
2454 ret = ring->emit_request(ringbuf);
2458 ret = ring->add_request(ring);
2463 request->head = request_start;
2464 request->tail = request_ring_position;
2466 /* Whilst this request exists, batch_obj will be on the
2467 * active_list, and so will hold the active reference. Only when this
2468 * request is retired will the the batch_obj be moved onto the
2469 * inactive_list and lose its active reference. Hence we do not need
2470 * to explicitly hold another reference here.
2472 request->batch_obj = obj;
2474 if (!i915.enable_execlists) {
2475 /* Hold a reference to the current context so that we can inspect
2476 * it later in case a hangcheck error event fires.
2478 request->ctx = ring->last_context;
2480 i915_gem_context_reference(request->ctx);
2483 request->emitted_jiffies = jiffies;
2484 list_add_tail(&request->list, &ring->request_list);
2485 request->file_priv = NULL;
2488 struct drm_i915_file_private *file_priv = file->driver_priv;
2490 spin_lock(&file_priv->mm.lock);
2491 request->file_priv = file_priv;
2492 list_add_tail(&request->client_list,
2493 &file_priv->mm.request_list);
2494 spin_unlock(&file_priv->mm.lock);
2497 trace_i915_gem_request_add(request);
2498 ring->outstanding_lazy_request = NULL;
2500 i915_queue_hangcheck(ring->dev);
2502 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2503 queue_delayed_work(dev_priv->wq,
2504 &dev_priv->mm.retire_work,
2505 round_jiffies_up_relative(HZ));
2506 intel_mark_busy(dev_priv->dev);
2512 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2514 struct drm_i915_file_private *file_priv = request->file_priv;
2519 spin_lock(&file_priv->mm.lock);
2520 list_del(&request->client_list);
2521 request->file_priv = NULL;
2522 spin_unlock(&file_priv->mm.lock);
2525 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2526 const struct intel_context *ctx)
2528 unsigned long elapsed;
2530 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2532 if (ctx->hang_stats.banned)
2535 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2536 if (!i915_gem_context_is_default(ctx)) {
2537 DRM_DEBUG("context hanging too fast, banning!\n");
2539 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2540 if (i915_stop_ring_allow_warn(dev_priv))
2541 DRM_ERROR("gpu hanging too fast, banning!\n");
2549 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2550 struct intel_context *ctx,
2553 struct i915_ctx_hang_stats *hs;
2558 hs = &ctx->hang_stats;
2561 hs->banned = i915_context_is_banned(dev_priv, ctx);
2563 hs->guilty_ts = get_seconds();
2565 hs->batch_pending++;
2569 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2571 list_del(&request->list);
2572 i915_gem_request_remove_from_client(request);
2574 i915_gem_request_unreference(request);
2577 void i915_gem_request_free(struct kref *req_ref)
2579 struct drm_i915_gem_request *req = container_of(req_ref,
2581 struct intel_context *ctx = req->ctx;
2584 if (i915.enable_execlists) {
2585 struct intel_engine_cs *ring = req->ring;
2587 if (ctx != ring->default_context)
2588 intel_lr_context_unpin(ring, ctx);
2591 i915_gem_context_unreference(ctx);
2597 struct drm_i915_gem_request *
2598 i915_gem_find_active_request(struct intel_engine_cs *ring)
2600 struct drm_i915_gem_request *request;
2602 list_for_each_entry(request, &ring->request_list, list) {
2603 if (i915_gem_request_completed(request, false))
2612 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2613 struct intel_engine_cs *ring)
2615 struct drm_i915_gem_request *request;
2618 request = i915_gem_find_active_request(ring);
2620 if (request == NULL)
2623 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2625 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2627 list_for_each_entry_continue(request, &ring->request_list, list)
2628 i915_set_reset_status(dev_priv, request->ctx, false);
2631 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2632 struct intel_engine_cs *ring)
2634 while (!list_empty(&ring->active_list)) {
2635 struct drm_i915_gem_object *obj;
2637 obj = list_first_entry(&ring->active_list,
2638 struct drm_i915_gem_object,
2641 i915_gem_object_move_to_inactive(obj);
2645 * Clear the execlists queue up before freeing the requests, as those
2646 * are the ones that keep the context and ringbuffer backing objects
2649 while (!list_empty(&ring->execlist_queue)) {
2650 struct intel_ctx_submit_request *submit_req;
2652 submit_req = list_first_entry(&ring->execlist_queue,
2653 struct intel_ctx_submit_request,
2655 list_del(&submit_req->execlist_link);
2656 intel_runtime_pm_put(dev_priv);
2657 i915_gem_context_unreference(submit_req->ctx);
2662 * We must free the requests after all the corresponding objects have
2663 * been moved off active lists. Which is the same order as the normal
2664 * retire_requests function does. This is important if object hold
2665 * implicit references on things like e.g. ppgtt address spaces through
2668 while (!list_empty(&ring->request_list)) {
2669 struct drm_i915_gem_request *request;
2671 request = list_first_entry(&ring->request_list,
2672 struct drm_i915_gem_request,
2675 i915_gem_free_request(request);
2678 /* This may not have been flushed before the reset, so clean it now */
2679 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2682 void i915_gem_restore_fences(struct drm_device *dev)
2684 struct drm_i915_private *dev_priv = dev->dev_private;
2687 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2688 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2691 * Commit delayed tiling changes if we have an object still
2692 * attached to the fence, otherwise just clear the fence.
2695 i915_gem_object_update_fence(reg->obj, reg,
2696 reg->obj->tiling_mode);
2698 i915_gem_write_fence(dev, i, NULL);
2703 void i915_gem_reset(struct drm_device *dev)
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_engine_cs *ring;
2710 * Before we free the objects from the requests, we need to inspect
2711 * them for finding the guilty party. As the requests only borrow
2712 * their reference to the objects, the inspection must be done first.
2714 for_each_ring(ring, dev_priv, i)
2715 i915_gem_reset_ring_status(dev_priv, ring);
2717 for_each_ring(ring, dev_priv, i)
2718 i915_gem_reset_ring_cleanup(dev_priv, ring);
2720 i915_gem_context_reset(dev);
2722 i915_gem_restore_fences(dev);
2726 * This function clears the request list as sequence numbers are passed.
2729 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2731 if (list_empty(&ring->request_list))
2734 WARN_ON(i915_verify_lists(ring->dev));
2736 /* Move any buffers on the active list that are no longer referenced
2737 * by the ringbuffer to the flushing/inactive lists as appropriate,
2738 * before we free the context associated with the requests.
2740 while (!list_empty(&ring->active_list)) {
2741 struct drm_i915_gem_object *obj;
2743 obj = list_first_entry(&ring->active_list,
2744 struct drm_i915_gem_object,
2747 if (!i915_gem_request_completed(obj->last_read_req, true))
2750 i915_gem_object_move_to_inactive(obj);
2754 while (!list_empty(&ring->request_list)) {
2755 struct drm_i915_gem_request *request;
2756 struct intel_ringbuffer *ringbuf;
2758 request = list_first_entry(&ring->request_list,
2759 struct drm_i915_gem_request,
2762 if (!i915_gem_request_completed(request, true))
2765 trace_i915_gem_request_retire(request);
2767 /* This is one of the few common intersection points
2768 * between legacy ringbuffer submission and execlists:
2769 * we need to tell them apart in order to find the correct
2770 * ringbuffer to which the request belongs to.
2772 if (i915.enable_execlists) {
2773 struct intel_context *ctx = request->ctx;
2774 ringbuf = ctx->engine[ring->id].ringbuf;
2776 ringbuf = ring->buffer;
2778 /* We know the GPU must have read the request to have
2779 * sent us the seqno + interrupt, so use the position
2780 * of tail of the request to update the last known position
2783 ringbuf->last_retired_head = request->tail;
2785 i915_gem_free_request(request);
2788 if (unlikely(ring->trace_irq_seqno &&
2789 i915_seqno_passed(ring->get_seqno(ring, true),
2790 ring->trace_irq_seqno))) {
2791 ring->irq_put(ring);
2792 ring->trace_irq_seqno = 0;
2795 WARN_ON(i915_verify_lists(ring->dev));
2799 i915_gem_retire_requests(struct drm_device *dev)
2801 struct drm_i915_private *dev_priv = dev->dev_private;
2802 struct intel_engine_cs *ring;
2806 for_each_ring(ring, dev_priv, i) {
2807 i915_gem_retire_requests_ring(ring);
2808 idle &= list_empty(&ring->request_list);
2809 if (i915.enable_execlists) {
2810 unsigned long flags;
2812 spin_lock_irqsave(&ring->execlist_lock, flags);
2813 idle &= list_empty(&ring->execlist_queue);
2814 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2816 intel_execlists_retire_requests(ring);
2821 mod_delayed_work(dev_priv->wq,
2822 &dev_priv->mm.idle_work,
2823 msecs_to_jiffies(100));
2829 i915_gem_retire_work_handler(struct work_struct *work)
2831 struct drm_i915_private *dev_priv =
2832 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2833 struct drm_device *dev = dev_priv->dev;
2836 /* Come back later if the device is busy... */
2838 if (mutex_trylock(&dev->struct_mutex)) {
2839 idle = i915_gem_retire_requests(dev);
2840 mutex_unlock(&dev->struct_mutex);
2843 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2844 round_jiffies_up_relative(HZ));
2848 i915_gem_idle_work_handler(struct work_struct *work)
2850 struct drm_i915_private *dev_priv =
2851 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2853 intel_mark_idle(dev_priv->dev);
2857 * Ensures that an object will eventually get non-busy by flushing any required
2858 * write domains, emitting any outstanding lazy request and retiring and
2859 * completed requests.
2862 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2867 ret = i915_gem_check_olr(obj->last_read_req);
2871 i915_gem_retire_requests_ring(obj->ring);
2878 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2879 * @DRM_IOCTL_ARGS: standard ioctl arguments
2881 * Returns 0 if successful, else an error is returned with the remaining time in
2882 * the timeout parameter.
2883 * -ETIME: object is still busy after timeout
2884 * -ERESTARTSYS: signal interrupted the wait
2885 * -ENONENT: object doesn't exist
2886 * Also possible, but rare:
2887 * -EAGAIN: GPU wedged
2889 * -ENODEV: Internal IRQ fail
2890 * -E?: The add request failed
2892 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2893 * non-zero timeout parameter the wait ioctl will wait for the given number of
2894 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2895 * without holding struct_mutex the object may become re-busied before this
2896 * function completes. A similar but shorter * race condition exists in the busy
2900 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903 struct drm_i915_gem_wait *args = data;
2904 struct drm_i915_gem_object *obj;
2905 struct drm_i915_gem_request *req;
2906 unsigned reset_counter;
2909 if (args->flags != 0)
2912 ret = i915_mutex_lock_interruptible(dev);
2916 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2917 if (&obj->base == NULL) {
2918 mutex_unlock(&dev->struct_mutex);
2922 /* Need to make sure the object gets inactive eventually. */
2923 ret = i915_gem_object_flush_active(obj);
2927 if (!obj->active || !obj->last_read_req)
2930 req = obj->last_read_req;
2932 /* Do this after OLR check to make sure we make forward progress polling
2933 * on this IOCTL with a timeout <=0 (like busy ioctl)
2935 if (args->timeout_ns <= 0) {
2940 drm_gem_object_unreference(&obj->base);
2941 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2942 i915_gem_request_reference(req);
2943 mutex_unlock(&dev->struct_mutex);
2945 ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns,
2947 mutex_lock(&dev->struct_mutex);
2948 i915_gem_request_unreference(req);
2949 mutex_unlock(&dev->struct_mutex);
2953 drm_gem_object_unreference(&obj->base);
2954 mutex_unlock(&dev->struct_mutex);
2959 * i915_gem_object_sync - sync an object to a ring.
2961 * @obj: object which may be in use on another ring.
2962 * @to: ring we wish to use the object on. May be NULL.
2964 * This code is meant to abstract object synchronization with the GPU.
2965 * Calling with NULL implies synchronizing the object with the CPU
2966 * rather than a particular GPU ring.
2968 * Returns 0 if successful, else propagates up the lower layer error.
2971 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2972 struct intel_engine_cs *to)
2974 struct intel_engine_cs *from = obj->ring;
2978 if (from == NULL || to == from)
2981 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2982 return i915_gem_object_wait_rendering(obj, false);
2984 idx = intel_ring_sync_index(from, to);
2986 seqno = i915_gem_request_get_seqno(obj->last_read_req);
2987 /* Optimization: Avoid semaphore sync when we are sure we already
2988 * waited for an object with higher seqno */
2989 if (seqno <= from->semaphore.sync_seqno[idx])
2992 ret = i915_gem_check_olr(obj->last_read_req);
2996 trace_i915_gem_ring_sync_to(from, to, obj->last_read_req);
2997 ret = to->semaphore.sync_to(to, from, seqno);
2999 /* We use last_read_req because sync_to()
3000 * might have just caused seqno wrap under
3003 from->semaphore.sync_seqno[idx] =
3004 i915_gem_request_get_seqno(obj->last_read_req);
3009 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3011 u32 old_write_domain, old_read_domains;
3013 /* Force a pagefault for domain tracking on next user access */
3014 i915_gem_release_mmap(obj);
3016 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3019 /* Wait for any direct GTT access to complete */
3022 old_read_domains = obj->base.read_domains;
3023 old_write_domain = obj->base.write_domain;
3025 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3026 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3028 trace_i915_gem_object_change_domain(obj,
3033 int i915_vma_unbind(struct i915_vma *vma)
3035 struct drm_i915_gem_object *obj = vma->obj;
3036 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3039 if (list_empty(&vma->vma_link))
3042 if (!drm_mm_node_allocated(&vma->node)) {
3043 i915_gem_vma_destroy(vma);
3050 BUG_ON(obj->pages == NULL);
3052 ret = i915_gem_object_finish_gpu(obj);
3055 /* Continue on if we fail due to EIO, the GPU is hung so we
3056 * should be safe and we need to cleanup or else we might
3057 * cause memory corruption through use-after-free.
3060 /* Throw away the active reference before moving to the unbound list */
3061 i915_gem_object_retire(obj);
3063 if (i915_is_ggtt(vma->vm)) {
3064 i915_gem_object_finish_gtt(obj);
3066 /* release the fence reg _after_ flushing */
3067 ret = i915_gem_object_put_fence(obj);
3072 trace_i915_vma_unbind(vma);
3074 vma->unbind_vma(vma);
3076 list_del_init(&vma->mm_list);
3077 if (i915_is_ggtt(vma->vm))
3078 obj->map_and_fenceable = false;
3080 drm_mm_remove_node(&vma->node);
3081 i915_gem_vma_destroy(vma);
3083 /* Since the unbound list is global, only move to that list if
3084 * no more VMAs exist. */
3085 if (list_empty(&obj->vma_list)) {
3086 i915_gem_gtt_finish_object(obj);
3087 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3090 /* And finally now the object is completely decoupled from this vma,
3091 * we can drop its hold on the backing storage and allow it to be
3092 * reaped by the shrinker.
3094 i915_gem_object_unpin_pages(obj);
3099 int i915_gpu_idle(struct drm_device *dev)
3101 struct drm_i915_private *dev_priv = dev->dev_private;
3102 struct intel_engine_cs *ring;
3105 /* Flush everything onto the inactive list. */
3106 for_each_ring(ring, dev_priv, i) {
3107 if (!i915.enable_execlists) {
3108 ret = i915_switch_context(ring, ring->default_context);
3113 ret = intel_ring_idle(ring);
3121 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3122 struct drm_i915_gem_object *obj)
3124 struct drm_i915_private *dev_priv = dev->dev_private;
3126 int fence_pitch_shift;
3128 if (INTEL_INFO(dev)->gen >= 6) {
3129 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3130 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3132 fence_reg = FENCE_REG_965_0;
3133 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3136 fence_reg += reg * 8;
3138 /* To w/a incoherency with non-atomic 64-bit register updates,
3139 * we split the 64-bit update into two 32-bit writes. In order
3140 * for a partial fence not to be evaluated between writes, we
3141 * precede the update with write to turn off the fence register,
3142 * and only enable the fence as the last step.
3144 * For extra levels of paranoia, we make sure each step lands
3145 * before applying the next step.
3147 I915_WRITE(fence_reg, 0);
3148 POSTING_READ(fence_reg);
3151 u32 size = i915_gem_obj_ggtt_size(obj);
3154 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3156 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3157 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3158 if (obj->tiling_mode == I915_TILING_Y)
3159 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3160 val |= I965_FENCE_REG_VALID;
3162 I915_WRITE(fence_reg + 4, val >> 32);
3163 POSTING_READ(fence_reg + 4);
3165 I915_WRITE(fence_reg + 0, val);
3166 POSTING_READ(fence_reg);
3168 I915_WRITE(fence_reg + 4, 0);
3169 POSTING_READ(fence_reg + 4);
3173 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3174 struct drm_i915_gem_object *obj)
3176 struct drm_i915_private *dev_priv = dev->dev_private;
3180 u32 size = i915_gem_obj_ggtt_size(obj);
3184 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3185 (size & -size) != size ||
3186 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3187 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3188 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3190 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3195 /* Note: pitch better be a power of two tile widths */
3196 pitch_val = obj->stride / tile_width;
3197 pitch_val = ffs(pitch_val) - 1;
3199 val = i915_gem_obj_ggtt_offset(obj);
3200 if (obj->tiling_mode == I915_TILING_Y)
3201 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3202 val |= I915_FENCE_SIZE_BITS(size);
3203 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3204 val |= I830_FENCE_REG_VALID;
3209 reg = FENCE_REG_830_0 + reg * 4;
3211 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3213 I915_WRITE(reg, val);
3217 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3218 struct drm_i915_gem_object *obj)
3220 struct drm_i915_private *dev_priv = dev->dev_private;
3224 u32 size = i915_gem_obj_ggtt_size(obj);
3227 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3228 (size & -size) != size ||
3229 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3230 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3231 i915_gem_obj_ggtt_offset(obj), size);
3233 pitch_val = obj->stride / 128;
3234 pitch_val = ffs(pitch_val) - 1;
3236 val = i915_gem_obj_ggtt_offset(obj);
3237 if (obj->tiling_mode == I915_TILING_Y)
3238 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3239 val |= I830_FENCE_SIZE_BITS(size);
3240 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3241 val |= I830_FENCE_REG_VALID;
3245 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3246 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3249 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3251 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3254 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3255 struct drm_i915_gem_object *obj)
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3259 /* Ensure that all CPU reads are completed before installing a fence
3260 * and all writes before removing the fence.
3262 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3265 WARN(obj && (!obj->stride || !obj->tiling_mode),
3266 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3267 obj->stride, obj->tiling_mode);
3269 switch (INTEL_INFO(dev)->gen) {
3275 case 4: i965_write_fence_reg(dev, reg, obj); break;
3276 case 3: i915_write_fence_reg(dev, reg, obj); break;
3277 case 2: i830_write_fence_reg(dev, reg, obj); break;
3281 /* And similarly be paranoid that no direct access to this region
3282 * is reordered to before the fence is installed.
3284 if (i915_gem_object_needs_mb(obj))
3288 static inline int fence_number(struct drm_i915_private *dev_priv,
3289 struct drm_i915_fence_reg *fence)
3291 return fence - dev_priv->fence_regs;
3294 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3295 struct drm_i915_fence_reg *fence,
3298 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3299 int reg = fence_number(dev_priv, fence);
3301 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3304 obj->fence_reg = reg;
3306 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3308 obj->fence_reg = I915_FENCE_REG_NONE;
3310 list_del_init(&fence->lru_list);
3312 obj->fence_dirty = false;
3316 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3318 if (obj->last_fenced_req) {
3319 int ret = i915_wait_request(obj->last_fenced_req);
3323 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3330 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3332 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3333 struct drm_i915_fence_reg *fence;
3336 ret = i915_gem_object_wait_fence(obj);
3340 if (obj->fence_reg == I915_FENCE_REG_NONE)
3343 fence = &dev_priv->fence_regs[obj->fence_reg];
3345 if (WARN_ON(fence->pin_count))
3348 i915_gem_object_fence_lost(obj);
3349 i915_gem_object_update_fence(obj, fence, false);
3354 static struct drm_i915_fence_reg *
3355 i915_find_fence_reg(struct drm_device *dev)
3357 struct drm_i915_private *dev_priv = dev->dev_private;
3358 struct drm_i915_fence_reg *reg, *avail;
3361 /* First try to find a free reg */
3363 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3364 reg = &dev_priv->fence_regs[i];
3368 if (!reg->pin_count)
3375 /* None available, try to steal one or wait for a user to finish */
3376 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3384 /* Wait for completion of pending flips which consume fences */
3385 if (intel_has_pending_fb_unpin(dev))
3386 return ERR_PTR(-EAGAIN);
3388 return ERR_PTR(-EDEADLK);
3392 * i915_gem_object_get_fence - set up fencing for an object
3393 * @obj: object to map through a fence reg
3395 * When mapping objects through the GTT, userspace wants to be able to write
3396 * to them without having to worry about swizzling if the object is tiled.
3397 * This function walks the fence regs looking for a free one for @obj,
3398 * stealing one if it can't find any.
3400 * It then sets up the reg based on the object's properties: address, pitch
3401 * and tiling format.
3403 * For an untiled surface, this removes any existing fence.
3406 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3408 struct drm_device *dev = obj->base.dev;
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 bool enable = obj->tiling_mode != I915_TILING_NONE;
3411 struct drm_i915_fence_reg *reg;
3414 /* Have we updated the tiling parameters upon the object and so
3415 * will need to serialise the write to the associated fence register?
3417 if (obj->fence_dirty) {
3418 ret = i915_gem_object_wait_fence(obj);
3423 /* Just update our place in the LRU if our fence is getting reused. */
3424 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3425 reg = &dev_priv->fence_regs[obj->fence_reg];
3426 if (!obj->fence_dirty) {
3427 list_move_tail(®->lru_list,
3428 &dev_priv->mm.fence_list);
3431 } else if (enable) {
3432 if (WARN_ON(!obj->map_and_fenceable))
3435 reg = i915_find_fence_reg(dev);
3437 return PTR_ERR(reg);
3440 struct drm_i915_gem_object *old = reg->obj;
3442 ret = i915_gem_object_wait_fence(old);
3446 i915_gem_object_fence_lost(old);
3451 i915_gem_object_update_fence(obj, reg, enable);
3456 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3457 unsigned long cache_level)
3459 struct drm_mm_node *gtt_space = &vma->node;
3460 struct drm_mm_node *other;
3463 * On some machines we have to be careful when putting differing types
3464 * of snoopable memory together to avoid the prefetcher crossing memory
3465 * domains and dying. During vm initialisation, we decide whether or not
3466 * these constraints apply and set the drm_mm.color_adjust
3469 if (vma->vm->mm.color_adjust == NULL)
3472 if (!drm_mm_node_allocated(gtt_space))
3475 if (list_empty(>t_space->node_list))
3478 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3479 if (other->allocated && !other->hole_follows && other->color != cache_level)
3482 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3483 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3490 * Finds free space in the GTT aperture and binds the object there.
3492 static struct i915_vma *
3493 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3494 struct i915_address_space *vm,
3498 struct drm_device *dev = obj->base.dev;
3499 struct drm_i915_private *dev_priv = dev->dev_private;
3500 u32 size, fence_size, fence_alignment, unfenced_alignment;
3501 unsigned long start =
3502 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3504 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3505 struct i915_vma *vma;
3508 fence_size = i915_gem_get_gtt_size(dev,
3511 fence_alignment = i915_gem_get_gtt_alignment(dev,
3513 obj->tiling_mode, true);
3514 unfenced_alignment =
3515 i915_gem_get_gtt_alignment(dev,
3517 obj->tiling_mode, false);
3520 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3522 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3523 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3524 return ERR_PTR(-EINVAL);
3527 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3529 /* If the object is bigger than the entire aperture, reject it early
3530 * before evicting everything in a vain attempt to find space.
3532 if (obj->base.size > end) {
3533 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3535 flags & PIN_MAPPABLE ? "mappable" : "total",
3537 return ERR_PTR(-E2BIG);
3540 ret = i915_gem_object_get_pages(obj);
3542 return ERR_PTR(ret);
3544 i915_gem_object_pin_pages(obj);
3546 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3551 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3555 DRM_MM_SEARCH_DEFAULT,
3556 DRM_MM_CREATE_DEFAULT);
3558 ret = i915_gem_evict_something(dev, vm, size, alignment,
3567 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3569 goto err_remove_node;
3572 ret = i915_gem_gtt_prepare_object(obj);
3574 goto err_remove_node;
3576 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3577 list_add_tail(&vma->mm_list, &vm->inactive_list);
3579 trace_i915_vma_bind(vma, flags);
3580 vma->bind_vma(vma, obj->cache_level,
3581 flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3586 drm_mm_remove_node(&vma->node);
3588 i915_gem_vma_destroy(vma);
3591 i915_gem_object_unpin_pages(obj);
3596 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3599 /* If we don't have a page list set up, then we're not pinned
3600 * to GPU, and we can ignore the cache flush because it'll happen
3601 * again at bind time.
3603 if (obj->pages == NULL)
3607 * Stolen memory is always coherent with the GPU as it is explicitly
3608 * marked as wc by the system, or the system is cache-coherent.
3610 if (obj->stolen || obj->phys_handle)
3613 /* If the GPU is snooping the contents of the CPU cache,
3614 * we do not need to manually clear the CPU cache lines. However,
3615 * the caches are only snooped when the render cache is
3616 * flushed/invalidated. As we always have to emit invalidations
3617 * and flushes when moving into and out of the RENDER domain, correct
3618 * snooping behaviour occurs naturally as the result of our domain
3621 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3624 trace_i915_gem_object_clflush(obj);
3625 drm_clflush_sg(obj->pages);
3630 /** Flushes the GTT write domain for the object if it's dirty. */
3632 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3634 uint32_t old_write_domain;
3636 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3639 /* No actual flushing is required for the GTT write domain. Writes
3640 * to it immediately go to main memory as far as we know, so there's
3641 * no chipset flush. It also doesn't land in render cache.
3643 * However, we do have to enforce the order so that all writes through
3644 * the GTT land before any writes to the device, such as updates to
3649 old_write_domain = obj->base.write_domain;
3650 obj->base.write_domain = 0;
3652 intel_fb_obj_flush(obj, false);
3654 trace_i915_gem_object_change_domain(obj,
3655 obj->base.read_domains,
3659 /** Flushes the CPU write domain for the object if it's dirty. */
3661 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3664 uint32_t old_write_domain;
3666 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3669 if (i915_gem_clflush_object(obj, force))
3670 i915_gem_chipset_flush(obj->base.dev);
3672 old_write_domain = obj->base.write_domain;
3673 obj->base.write_domain = 0;
3675 intel_fb_obj_flush(obj, false);
3677 trace_i915_gem_object_change_domain(obj,
3678 obj->base.read_domains,
3683 * Moves a single object to the GTT read, and possibly write domain.
3685 * This function returns when the move is complete, including waiting on
3689 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3691 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3692 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3693 uint32_t old_write_domain, old_read_domains;
3696 /* Not valid to be called on unbound objects. */
3700 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3703 ret = i915_gem_object_wait_rendering(obj, !write);
3707 i915_gem_object_retire(obj);
3708 i915_gem_object_flush_cpu_write_domain(obj, false);
3710 /* Serialise direct access to this object with the barriers for
3711 * coherent writes from the GPU, by effectively invalidating the
3712 * GTT domain upon first access.
3714 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3717 old_write_domain = obj->base.write_domain;
3718 old_read_domains = obj->base.read_domains;
3720 /* It should now be out of any other write domains, and we can update
3721 * the domain values for our changes.
3723 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3724 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3726 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3727 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3732 intel_fb_obj_invalidate(obj, NULL);
3734 trace_i915_gem_object_change_domain(obj,
3738 /* And bump the LRU for this access */
3739 if (i915_gem_object_is_inactive(obj))
3740 list_move_tail(&vma->mm_list,
3741 &dev_priv->gtt.base.inactive_list);
3746 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3747 enum i915_cache_level cache_level)
3749 struct drm_device *dev = obj->base.dev;
3750 struct i915_vma *vma, *next;
3753 if (obj->cache_level == cache_level)
3756 if (i915_gem_obj_is_pinned(obj)) {
3757 DRM_DEBUG("can not change the cache level of pinned objects\n");
3761 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3762 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3763 ret = i915_vma_unbind(vma);
3769 if (i915_gem_obj_bound_any(obj)) {
3770 ret = i915_gem_object_finish_gpu(obj);
3774 i915_gem_object_finish_gtt(obj);
3776 /* Before SandyBridge, you could not use tiling or fence
3777 * registers with snooped memory, so relinquish any fences
3778 * currently pointing to our region in the aperture.
3780 if (INTEL_INFO(dev)->gen < 6) {
3781 ret = i915_gem_object_put_fence(obj);
3786 list_for_each_entry(vma, &obj->vma_list, vma_link)
3787 if (drm_mm_node_allocated(&vma->node))
3788 vma->bind_vma(vma, cache_level,
3789 vma->bound & GLOBAL_BIND);
3792 list_for_each_entry(vma, &obj->vma_list, vma_link)
3793 vma->node.color = cache_level;
3794 obj->cache_level = cache_level;
3796 if (cpu_write_needs_clflush(obj)) {
3797 u32 old_read_domains, old_write_domain;
3799 /* If we're coming from LLC cached, then we haven't
3800 * actually been tracking whether the data is in the
3801 * CPU cache or not, since we only allow one bit set
3802 * in obj->write_domain and have been skipping the clflushes.
3803 * Just set it to the CPU cache for now.
3805 i915_gem_object_retire(obj);
3806 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3808 old_read_domains = obj->base.read_domains;
3809 old_write_domain = obj->base.write_domain;
3811 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3812 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3814 trace_i915_gem_object_change_domain(obj,
3822 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3823 struct drm_file *file)
3825 struct drm_i915_gem_caching *args = data;
3826 struct drm_i915_gem_object *obj;
3829 ret = i915_mutex_lock_interruptible(dev);
3833 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3834 if (&obj->base == NULL) {
3839 switch (obj->cache_level) {
3840 case I915_CACHE_LLC:
3841 case I915_CACHE_L3_LLC:
3842 args->caching = I915_CACHING_CACHED;
3846 args->caching = I915_CACHING_DISPLAY;
3850 args->caching = I915_CACHING_NONE;
3854 drm_gem_object_unreference(&obj->base);
3856 mutex_unlock(&dev->struct_mutex);
3860 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3861 struct drm_file *file)
3863 struct drm_i915_gem_caching *args = data;
3864 struct drm_i915_gem_object *obj;
3865 enum i915_cache_level level;
3868 switch (args->caching) {
3869 case I915_CACHING_NONE:
3870 level = I915_CACHE_NONE;
3872 case I915_CACHING_CACHED:
3873 level = I915_CACHE_LLC;
3875 case I915_CACHING_DISPLAY:
3876 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3882 ret = i915_mutex_lock_interruptible(dev);
3886 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3887 if (&obj->base == NULL) {
3892 ret = i915_gem_object_set_cache_level(obj, level);
3894 drm_gem_object_unreference(&obj->base);
3896 mutex_unlock(&dev->struct_mutex);
3900 static bool is_pin_display(struct drm_i915_gem_object *obj)
3902 struct i915_vma *vma;
3904 vma = i915_gem_obj_to_ggtt(obj);
3908 /* There are 2 sources that pin objects:
3909 * 1. The display engine (scanouts, sprites, cursors);
3910 * 2. Reservations for execbuffer;
3912 * We can ignore reservations as we hold the struct_mutex and
3913 * are only called outside of the reservation path.
3915 return vma->pin_count;
3919 * Prepare buffer for display plane (scanout, cursors, etc).
3920 * Can be called from an uninterruptible phase (modesetting) and allows
3921 * any flushes to be pipelined (for pageflips).
3924 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3926 struct intel_engine_cs *pipelined)
3928 u32 old_read_domains, old_write_domain;
3929 bool was_pin_display;
3932 if (pipelined != obj->ring) {
3933 ret = i915_gem_object_sync(obj, pipelined);
3938 /* Mark the pin_display early so that we account for the
3939 * display coherency whilst setting up the cache domains.
3941 was_pin_display = obj->pin_display;
3942 obj->pin_display = true;
3944 /* The display engine is not coherent with the LLC cache on gen6. As
3945 * a result, we make sure that the pinning that is about to occur is
3946 * done with uncached PTEs. This is lowest common denominator for all
3949 * However for gen6+, we could do better by using the GFDT bit instead
3950 * of uncaching, which would allow us to flush all the LLC-cached data
3951 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3953 ret = i915_gem_object_set_cache_level(obj,
3954 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3956 goto err_unpin_display;
3958 /* As the user may map the buffer once pinned in the display plane
3959 * (e.g. libkms for the bootup splash), we have to ensure that we
3960 * always use map_and_fenceable for all scanout buffers.
3962 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3964 goto err_unpin_display;
3966 i915_gem_object_flush_cpu_write_domain(obj, true);
3968 old_write_domain = obj->base.write_domain;
3969 old_read_domains = obj->base.read_domains;
3971 /* It should now be out of any other write domains, and we can update
3972 * the domain values for our changes.
3974 obj->base.write_domain = 0;
3975 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3977 trace_i915_gem_object_change_domain(obj,
3984 WARN_ON(was_pin_display != is_pin_display(obj));
3985 obj->pin_display = was_pin_display;
3990 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3992 i915_gem_object_ggtt_unpin(obj);
3993 obj->pin_display = is_pin_display(obj);
3997 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4001 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4004 ret = i915_gem_object_wait_rendering(obj, false);
4008 /* Ensure that we invalidate the GPU's caches and TLBs. */
4009 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4014 * Moves a single object to the CPU read, and possibly write domain.
4016 * This function returns when the move is complete, including waiting on
4020 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4022 uint32_t old_write_domain, old_read_domains;
4025 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4028 ret = i915_gem_object_wait_rendering(obj, !write);
4032 i915_gem_object_retire(obj);
4033 i915_gem_object_flush_gtt_write_domain(obj);
4035 old_write_domain = obj->base.write_domain;
4036 old_read_domains = obj->base.read_domains;
4038 /* Flush the CPU cache if it's still invalid. */
4039 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4040 i915_gem_clflush_object(obj, false);
4042 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4045 /* It should now be out of any other write domains, and we can update
4046 * the domain values for our changes.
4048 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4050 /* If we're writing through the CPU, then the GPU read domains will
4051 * need to be invalidated at next use.
4054 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4055 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4059 intel_fb_obj_invalidate(obj, NULL);
4061 trace_i915_gem_object_change_domain(obj,
4068 /* Throttle our rendering by waiting until the ring has completed our requests
4069 * emitted over 20 msec ago.
4071 * Note that if we were to use the current jiffies each time around the loop,
4072 * we wouldn't escape the function with any frames outstanding if the time to
4073 * render a frame was over 20ms.
4075 * This should get us reasonable parallelism between CPU and GPU but also
4076 * relatively low latency when blocking on a particular request to finish.
4079 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4081 struct drm_i915_private *dev_priv = dev->dev_private;
4082 struct drm_i915_file_private *file_priv = file->driver_priv;
4083 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4084 struct drm_i915_gem_request *request, *target = NULL;
4085 unsigned reset_counter;
4088 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4092 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4096 spin_lock(&file_priv->mm.lock);
4097 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4098 if (time_after_eq(request->emitted_jiffies, recent_enough))
4103 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4105 i915_gem_request_reference(target);
4106 spin_unlock(&file_priv->mm.lock);
4111 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4113 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4115 mutex_lock(&dev->struct_mutex);
4116 i915_gem_request_unreference(target);
4117 mutex_unlock(&dev->struct_mutex);
4123 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4125 struct drm_i915_gem_object *obj = vma->obj;
4128 vma->node.start & (alignment - 1))
4131 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4134 if (flags & PIN_OFFSET_BIAS &&
4135 vma->node.start < (flags & PIN_OFFSET_MASK))
4142 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4143 struct i915_address_space *vm,
4147 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4148 struct i915_vma *vma;
4152 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4155 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4158 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4161 vma = i915_gem_obj_to_vma(obj, vm);
4163 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4166 if (i915_vma_misplaced(vma, alignment, flags)) {
4167 WARN(vma->pin_count,
4168 "bo is already pinned with incorrect alignment:"
4169 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4170 " obj->map_and_fenceable=%d\n",
4171 i915_gem_obj_offset(obj, vm), alignment,
4172 !!(flags & PIN_MAPPABLE),
4173 obj->map_and_fenceable);
4174 ret = i915_vma_unbind(vma);
4182 bound = vma ? vma->bound : 0;
4183 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4184 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4186 return PTR_ERR(vma);
4189 if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND))
4190 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4192 if ((bound ^ vma->bound) & GLOBAL_BIND) {
4193 bool mappable, fenceable;
4194 u32 fence_size, fence_alignment;
4196 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4199 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4204 fenceable = (vma->node.size == fence_size &&
4205 (vma->node.start & (fence_alignment - 1)) == 0);
4207 mappable = (vma->node.start + obj->base.size <=
4208 dev_priv->gtt.mappable_end);
4210 obj->map_and_fenceable = mappable && fenceable;
4213 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4216 if (flags & PIN_MAPPABLE)
4217 obj->pin_mappable |= true;
4223 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4225 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4228 BUG_ON(vma->pin_count == 0);
4229 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4231 if (--vma->pin_count == 0)
4232 obj->pin_mappable = false;
4236 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4238 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4239 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4240 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4242 WARN_ON(!ggtt_vma ||
4243 dev_priv->fence_regs[obj->fence_reg].pin_count >
4244 ggtt_vma->pin_count);
4245 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4252 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4254 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4255 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4256 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4257 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4262 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4263 struct drm_file *file)
4265 struct drm_i915_gem_busy *args = data;
4266 struct drm_i915_gem_object *obj;
4269 ret = i915_mutex_lock_interruptible(dev);
4273 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4274 if (&obj->base == NULL) {
4279 /* Count all active objects as busy, even if they are currently not used
4280 * by the gpu. Users of this interface expect objects to eventually
4281 * become non-busy without any further actions, therefore emit any
4282 * necessary flushes here.
4284 ret = i915_gem_object_flush_active(obj);
4286 args->busy = obj->active;
4288 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4289 args->busy |= intel_ring_flag(obj->ring) << 16;
4292 drm_gem_object_unreference(&obj->base);
4294 mutex_unlock(&dev->struct_mutex);
4299 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4300 struct drm_file *file_priv)
4302 return i915_gem_ring_throttle(dev, file_priv);
4306 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4307 struct drm_file *file_priv)
4309 struct drm_i915_private *dev_priv = dev->dev_private;
4310 struct drm_i915_gem_madvise *args = data;
4311 struct drm_i915_gem_object *obj;
4314 switch (args->madv) {
4315 case I915_MADV_DONTNEED:
4316 case I915_MADV_WILLNEED:
4322 ret = i915_mutex_lock_interruptible(dev);
4326 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4327 if (&obj->base == NULL) {
4332 if (i915_gem_obj_is_pinned(obj)) {
4338 obj->tiling_mode != I915_TILING_NONE &&
4339 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4340 if (obj->madv == I915_MADV_WILLNEED)
4341 i915_gem_object_unpin_pages(obj);
4342 if (args->madv == I915_MADV_WILLNEED)
4343 i915_gem_object_pin_pages(obj);
4346 if (obj->madv != __I915_MADV_PURGED)
4347 obj->madv = args->madv;
4349 /* if the object is no longer attached, discard its backing storage */
4350 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4351 i915_gem_object_truncate(obj);
4353 args->retained = obj->madv != __I915_MADV_PURGED;
4356 drm_gem_object_unreference(&obj->base);
4358 mutex_unlock(&dev->struct_mutex);
4362 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4363 const struct drm_i915_gem_object_ops *ops)
4365 INIT_LIST_HEAD(&obj->global_list);
4366 INIT_LIST_HEAD(&obj->ring_list);
4367 INIT_LIST_HEAD(&obj->obj_exec_link);
4368 INIT_LIST_HEAD(&obj->vma_list);
4372 obj->fence_reg = I915_FENCE_REG_NONE;
4373 obj->madv = I915_MADV_WILLNEED;
4375 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4378 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4379 .get_pages = i915_gem_object_get_pages_gtt,
4380 .put_pages = i915_gem_object_put_pages_gtt,
4383 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4386 struct drm_i915_gem_object *obj;
4387 struct address_space *mapping;
4390 obj = i915_gem_object_alloc(dev);
4394 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4395 i915_gem_object_free(obj);
4399 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4400 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4401 /* 965gm cannot relocate objects above 4GiB. */
4402 mask &= ~__GFP_HIGHMEM;
4403 mask |= __GFP_DMA32;
4406 mapping = file_inode(obj->base.filp)->i_mapping;
4407 mapping_set_gfp_mask(mapping, mask);
4409 i915_gem_object_init(obj, &i915_gem_object_ops);
4411 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4412 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4415 /* On some devices, we can have the GPU use the LLC (the CPU
4416 * cache) for about a 10% performance improvement
4417 * compared to uncached. Graphics requests other than
4418 * display scanout are coherent with the CPU in
4419 * accessing this cache. This means in this mode we
4420 * don't need to clflush on the CPU side, and on the
4421 * GPU side we only need to flush internal caches to
4422 * get data visible to the CPU.
4424 * However, we maintain the display planes as UC, and so
4425 * need to rebind when first used as such.
4427 obj->cache_level = I915_CACHE_LLC;
4429 obj->cache_level = I915_CACHE_NONE;
4431 trace_i915_gem_object_create(obj);
4436 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4438 /* If we are the last user of the backing storage (be it shmemfs
4439 * pages or stolen etc), we know that the pages are going to be
4440 * immediately released. In this case, we can then skip copying
4441 * back the contents from the GPU.
4444 if (obj->madv != I915_MADV_WILLNEED)
4447 if (obj->base.filp == NULL)
4450 /* At first glance, this looks racy, but then again so would be
4451 * userspace racing mmap against close. However, the first external
4452 * reference to the filp can only be obtained through the
4453 * i915_gem_mmap_ioctl() which safeguards us against the user
4454 * acquiring such a reference whilst we are in the middle of
4455 * freeing the object.
4457 return atomic_long_read(&obj->base.filp->f_count) == 1;
4460 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4462 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4463 struct drm_device *dev = obj->base.dev;
4464 struct drm_i915_private *dev_priv = dev->dev_private;
4465 struct i915_vma *vma, *next;
4467 intel_runtime_pm_get(dev_priv);
4469 trace_i915_gem_object_destroy(obj);
4471 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4475 ret = i915_vma_unbind(vma);
4476 if (WARN_ON(ret == -ERESTARTSYS)) {
4477 bool was_interruptible;
4479 was_interruptible = dev_priv->mm.interruptible;
4480 dev_priv->mm.interruptible = false;
4482 WARN_ON(i915_vma_unbind(vma));
4484 dev_priv->mm.interruptible = was_interruptible;
4488 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4489 * before progressing. */
4491 i915_gem_object_unpin_pages(obj);
4493 WARN_ON(obj->frontbuffer_bits);
4495 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4496 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4497 obj->tiling_mode != I915_TILING_NONE)
4498 i915_gem_object_unpin_pages(obj);
4500 if (WARN_ON(obj->pages_pin_count))
4501 obj->pages_pin_count = 0;
4502 if (discard_backing_storage(obj))
4503 obj->madv = I915_MADV_DONTNEED;
4504 i915_gem_object_put_pages(obj);
4505 i915_gem_object_free_mmap_offset(obj);
4509 if (obj->base.import_attach)
4510 drm_prime_gem_destroy(&obj->base, NULL);
4512 if (obj->ops->release)
4513 obj->ops->release(obj);
4515 drm_gem_object_release(&obj->base);
4516 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4519 i915_gem_object_free(obj);
4521 intel_runtime_pm_put(dev_priv);
4524 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4525 struct i915_address_space *vm)
4527 struct i915_vma *vma;
4528 list_for_each_entry(vma, &obj->vma_list, vma_link)
4535 void i915_gem_vma_destroy(struct i915_vma *vma)
4537 struct i915_address_space *vm = NULL;
4538 WARN_ON(vma->node.allocated);
4540 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4541 if (!list_empty(&vma->exec_list))
4546 if (!i915_is_ggtt(vm))
4547 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4549 list_del(&vma->vma_link);
4555 i915_gem_stop_ringbuffers(struct drm_device *dev)
4557 struct drm_i915_private *dev_priv = dev->dev_private;
4558 struct intel_engine_cs *ring;
4561 for_each_ring(ring, dev_priv, i)
4562 dev_priv->gt.stop_ring(ring);
4566 i915_gem_suspend(struct drm_device *dev)
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4571 mutex_lock(&dev->struct_mutex);
4572 ret = i915_gpu_idle(dev);
4576 i915_gem_retire_requests(dev);
4578 /* Under UMS, be paranoid and evict. */
4579 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4580 i915_gem_evict_everything(dev);
4582 i915_gem_stop_ringbuffers(dev);
4583 mutex_unlock(&dev->struct_mutex);
4585 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4586 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4587 flush_delayed_work(&dev_priv->mm.idle_work);
4589 /* Assert that we sucessfully flushed all the work and
4590 * reset the GPU back to its idle, low power state.
4592 WARN_ON(dev_priv->mm.busy);
4597 mutex_unlock(&dev->struct_mutex);
4601 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4603 struct drm_device *dev = ring->dev;
4604 struct drm_i915_private *dev_priv = dev->dev_private;
4605 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4606 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4609 if (!HAS_L3_DPF(dev) || !remap_info)
4612 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4617 * Note: We do not worry about the concurrent register cacheline hang
4618 * here because no other code should access these registers other than
4619 * at initialization time.
4621 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4622 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4623 intel_ring_emit(ring, reg_base + i);
4624 intel_ring_emit(ring, remap_info[i/4]);
4627 intel_ring_advance(ring);
4632 void i915_gem_init_swizzling(struct drm_device *dev)
4634 struct drm_i915_private *dev_priv = dev->dev_private;
4636 if (INTEL_INFO(dev)->gen < 5 ||
4637 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4640 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4641 DISP_TILE_SURFACE_SWIZZLING);
4646 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4648 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4649 else if (IS_GEN7(dev))
4650 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4651 else if (IS_GEN8(dev))
4652 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4658 intel_enable_blt(struct drm_device *dev)
4663 /* The blitter was dysfunctional on early prototypes */
4664 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4665 DRM_INFO("BLT not supported on this pre-production hardware;"
4666 " graphics performance will be degraded.\n");
4673 static void init_unused_ring(struct drm_device *dev, u32 base)
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4677 I915_WRITE(RING_CTL(base), 0);
4678 I915_WRITE(RING_HEAD(base), 0);
4679 I915_WRITE(RING_TAIL(base), 0);
4680 I915_WRITE(RING_START(base), 0);
4683 static void init_unused_rings(struct drm_device *dev)
4686 init_unused_ring(dev, PRB1_BASE);
4687 init_unused_ring(dev, SRB0_BASE);
4688 init_unused_ring(dev, SRB1_BASE);
4689 init_unused_ring(dev, SRB2_BASE);
4690 init_unused_ring(dev, SRB3_BASE);
4691 } else if (IS_GEN2(dev)) {
4692 init_unused_ring(dev, SRB0_BASE);
4693 init_unused_ring(dev, SRB1_BASE);
4694 } else if (IS_GEN3(dev)) {
4695 init_unused_ring(dev, PRB1_BASE);
4696 init_unused_ring(dev, PRB2_BASE);
4700 int i915_gem_init_rings(struct drm_device *dev)
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4706 * At least 830 can leave some of the unused rings
4707 * "active" (ie. head != tail) after resume which
4708 * will prevent c3 entry. Makes sure all unused rings
4711 init_unused_rings(dev);
4713 ret = intel_init_render_ring_buffer(dev);
4718 ret = intel_init_bsd_ring_buffer(dev);
4720 goto cleanup_render_ring;
4723 if (intel_enable_blt(dev)) {
4724 ret = intel_init_blt_ring_buffer(dev);
4726 goto cleanup_bsd_ring;
4729 if (HAS_VEBOX(dev)) {
4730 ret = intel_init_vebox_ring_buffer(dev);
4732 goto cleanup_blt_ring;
4735 if (HAS_BSD2(dev)) {
4736 ret = intel_init_bsd2_ring_buffer(dev);
4738 goto cleanup_vebox_ring;
4741 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4743 goto cleanup_bsd2_ring;
4748 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4750 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4752 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4754 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4755 cleanup_render_ring:
4756 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4762 i915_gem_init_hw(struct drm_device *dev)
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4767 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4770 if (dev_priv->ellc_size)
4771 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4773 if (IS_HASWELL(dev))
4774 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4775 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4777 if (HAS_PCH_NOP(dev)) {
4778 if (IS_IVYBRIDGE(dev)) {
4779 u32 temp = I915_READ(GEN7_MSG_CTL);
4780 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4781 I915_WRITE(GEN7_MSG_CTL, temp);
4782 } else if (INTEL_INFO(dev)->gen >= 7) {
4783 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4784 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4785 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4789 i915_gem_init_swizzling(dev);
4791 ret = dev_priv->gt.init_rings(dev);
4795 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4796 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4799 * XXX: Contexts should only be initialized once. Doing a switch to the
4800 * default context switch however is something we'd like to do after
4801 * reset or thaw (the latter may not actually be necessary for HW, but
4802 * goes with our code better). Context switching requires rings (for
4803 * the do_switch), but before enabling PPGTT. So don't move this.
4805 ret = i915_gem_context_enable(dev_priv);
4806 if (ret && ret != -EIO) {
4807 DRM_ERROR("Context enable failed %d\n", ret);
4808 i915_gem_cleanup_ringbuffer(dev);
4813 ret = i915_ppgtt_init_hw(dev);
4814 if (ret && ret != -EIO) {
4815 DRM_ERROR("PPGTT enable failed %d\n", ret);
4816 i915_gem_cleanup_ringbuffer(dev);
4822 int i915_gem_init(struct drm_device *dev)
4824 struct drm_i915_private *dev_priv = dev->dev_private;
4827 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4828 i915.enable_execlists);
4830 mutex_lock(&dev->struct_mutex);
4832 if (IS_VALLEYVIEW(dev)) {
4833 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4834 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4835 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4836 VLV_GTLC_ALLOWWAKEACK), 10))
4837 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4840 if (!i915.enable_execlists) {
4841 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4842 dev_priv->gt.init_rings = i915_gem_init_rings;
4843 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4844 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4846 dev_priv->gt.do_execbuf = intel_execlists_submission;
4847 dev_priv->gt.init_rings = intel_logical_rings_init;
4848 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4849 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4852 ret = i915_gem_init_userptr(dev);
4854 mutex_unlock(&dev->struct_mutex);
4858 i915_gem_init_global_gtt(dev);
4860 ret = i915_gem_context_init(dev);
4862 mutex_unlock(&dev->struct_mutex);
4866 ret = i915_gem_init_hw(dev);
4868 /* Allow ring initialisation to fail by marking the GPU as
4869 * wedged. But we only want to do this where the GPU is angry,
4870 * for all other failure, such as an allocation failure, bail.
4872 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4873 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4876 mutex_unlock(&dev->struct_mutex);
4882 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4884 struct drm_i915_private *dev_priv = dev->dev_private;
4885 struct intel_engine_cs *ring;
4888 for_each_ring(ring, dev_priv, i)
4889 dev_priv->gt.cleanup_ring(ring);
4893 init_ring_lists(struct intel_engine_cs *ring)
4895 INIT_LIST_HEAD(&ring->active_list);
4896 INIT_LIST_HEAD(&ring->request_list);
4899 void i915_init_vm(struct drm_i915_private *dev_priv,
4900 struct i915_address_space *vm)
4902 if (!i915_is_ggtt(vm))
4903 drm_mm_init(&vm->mm, vm->start, vm->total);
4904 vm->dev = dev_priv->dev;
4905 INIT_LIST_HEAD(&vm->active_list);
4906 INIT_LIST_HEAD(&vm->inactive_list);
4907 INIT_LIST_HEAD(&vm->global_link);
4908 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4912 i915_gem_load(struct drm_device *dev)
4914 struct drm_i915_private *dev_priv = dev->dev_private;
4918 kmem_cache_create("i915_gem_object",
4919 sizeof(struct drm_i915_gem_object), 0,
4923 INIT_LIST_HEAD(&dev_priv->vm_list);
4924 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4926 INIT_LIST_HEAD(&dev_priv->context_list);
4927 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4928 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4929 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4930 for (i = 0; i < I915_NUM_RINGS; i++)
4931 init_ring_lists(&dev_priv->ring[i]);
4932 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4933 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4934 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4935 i915_gem_retire_work_handler);
4936 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4937 i915_gem_idle_work_handler);
4938 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4940 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4941 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4942 I915_WRITE(MI_ARB_STATE,
4943 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4946 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4948 /* Old X drivers will take 0-2 for front, back, depth buffers */
4949 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4950 dev_priv->fence_reg_start = 3;
4952 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4953 dev_priv->num_fence_regs = 32;
4954 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4955 dev_priv->num_fence_regs = 16;
4957 dev_priv->num_fence_regs = 8;
4959 /* Initialize fence registers to zero */
4960 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4961 i915_gem_restore_fences(dev);
4963 i915_gem_detect_bit_6_swizzle(dev);
4964 init_waitqueue_head(&dev_priv->pending_flip_queue);
4966 dev_priv->mm.interruptible = true;
4968 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4969 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4970 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4971 register_shrinker(&dev_priv->mm.shrinker);
4973 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4974 register_oom_notifier(&dev_priv->mm.oom_notifier);
4976 mutex_init(&dev_priv->fb_tracking.lock);
4979 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4981 struct drm_i915_file_private *file_priv = file->driver_priv;
4983 cancel_delayed_work_sync(&file_priv->mm.idle_work);
4985 /* Clean up our request list when the client is going away, so that
4986 * later retire_requests won't dereference our soon-to-be-gone
4989 spin_lock(&file_priv->mm.lock);
4990 while (!list_empty(&file_priv->mm.request_list)) {
4991 struct drm_i915_gem_request *request;
4993 request = list_first_entry(&file_priv->mm.request_list,
4994 struct drm_i915_gem_request,
4996 list_del(&request->client_list);
4997 request->file_priv = NULL;
4999 spin_unlock(&file_priv->mm.lock);
5003 i915_gem_file_idle_work_handler(struct work_struct *work)
5005 struct drm_i915_file_private *file_priv =
5006 container_of(work, typeof(*file_priv), mm.idle_work.work);
5008 atomic_set(&file_priv->rps_wait_boost, false);
5011 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5013 struct drm_i915_file_private *file_priv;
5016 DRM_DEBUG_DRIVER("\n");
5018 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5022 file->driver_priv = file_priv;
5023 file_priv->dev_priv = dev->dev_private;
5024 file_priv->file = file;
5026 spin_lock_init(&file_priv->mm.lock);
5027 INIT_LIST_HEAD(&file_priv->mm.request_list);
5028 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5029 i915_gem_file_idle_work_handler);
5031 ret = i915_gem_context_open(dev, file);
5039 * i915_gem_track_fb - update frontbuffer tracking
5040 * old: current GEM buffer for the frontbuffer slots
5041 * new: new GEM buffer for the frontbuffer slots
5042 * frontbuffer_bits: bitmask of frontbuffer slots
5044 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5045 * from @old and setting them in @new. Both @old and @new can be NULL.
5047 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5048 struct drm_i915_gem_object *new,
5049 unsigned frontbuffer_bits)
5052 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5053 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5054 old->frontbuffer_bits &= ~frontbuffer_bits;
5058 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5059 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5060 new->frontbuffer_bits |= frontbuffer_bits;
5064 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5066 if (!mutex_is_locked(mutex))
5069 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5070 return mutex->owner == task;
5072 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5077 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5079 if (!mutex_trylock(&dev->struct_mutex)) {
5080 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5083 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5093 static int num_vma_bound(struct drm_i915_gem_object *obj)
5095 struct i915_vma *vma;
5098 list_for_each_entry(vma, &obj->vma_list, vma_link)
5099 if (drm_mm_node_allocated(&vma->node))
5105 static unsigned long
5106 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5108 struct drm_i915_private *dev_priv =
5109 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5110 struct drm_device *dev = dev_priv->dev;
5111 struct drm_i915_gem_object *obj;
5112 unsigned long count;
5115 if (!i915_gem_shrinker_lock(dev, &unlock))
5119 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5120 if (obj->pages_pin_count == 0)
5121 count += obj->base.size >> PAGE_SHIFT;
5123 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5124 if (!i915_gem_obj_is_pinned(obj) &&
5125 obj->pages_pin_count == num_vma_bound(obj))
5126 count += obj->base.size >> PAGE_SHIFT;
5130 mutex_unlock(&dev->struct_mutex);
5135 /* All the new VM stuff */
5136 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5137 struct i915_address_space *vm)
5139 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5140 struct i915_vma *vma;
5142 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5144 list_for_each_entry(vma, &o->vma_list, vma_link) {
5146 return vma->node.start;
5149 WARN(1, "%s vma for this object not found.\n",
5150 i915_is_ggtt(vm) ? "global" : "ppgtt");
5154 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5155 struct i915_address_space *vm)
5157 struct i915_vma *vma;
5159 list_for_each_entry(vma, &o->vma_list, vma_link)
5160 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5166 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5168 struct i915_vma *vma;
5170 list_for_each_entry(vma, &o->vma_list, vma_link)
5171 if (drm_mm_node_allocated(&vma->node))
5177 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5178 struct i915_address_space *vm)
5180 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5181 struct i915_vma *vma;
5183 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5185 BUG_ON(list_empty(&o->vma_list));
5187 list_for_each_entry(vma, &o->vma_list, vma_link)
5189 return vma->node.size;
5194 static unsigned long
5195 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5197 struct drm_i915_private *dev_priv =
5198 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5199 struct drm_device *dev = dev_priv->dev;
5200 unsigned long freed;
5203 if (!i915_gem_shrinker_lock(dev, &unlock))
5206 freed = i915_gem_shrink(dev_priv,
5209 I915_SHRINK_UNBOUND |
5210 I915_SHRINK_PURGEABLE);
5211 if (freed < sc->nr_to_scan)
5212 freed += i915_gem_shrink(dev_priv,
5213 sc->nr_to_scan - freed,
5215 I915_SHRINK_UNBOUND);
5217 mutex_unlock(&dev->struct_mutex);
5223 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5225 struct drm_i915_private *dev_priv =
5226 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5227 struct drm_device *dev = dev_priv->dev;
5228 struct drm_i915_gem_object *obj;
5229 unsigned long timeout = msecs_to_jiffies(5000) + 1;
5230 unsigned long pinned, bound, unbound, freed_pages;
5231 bool was_interruptible;
5234 while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5235 schedule_timeout_killable(1);
5236 if (fatal_signal_pending(current))
5240 pr_err("Unable to purge GPU memory due lock contention.\n");
5244 was_interruptible = dev_priv->mm.interruptible;
5245 dev_priv->mm.interruptible = false;
5247 freed_pages = i915_gem_shrink_all(dev_priv);
5249 dev_priv->mm.interruptible = was_interruptible;
5251 /* Because we may be allocating inside our own driver, we cannot
5252 * assert that there are no objects with pinned pages that are not
5253 * being pointed to by hardware.
5255 unbound = bound = pinned = 0;
5256 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5257 if (!obj->base.filp) /* not backed by a freeable object */
5260 if (obj->pages_pin_count)
5261 pinned += obj->base.size;
5263 unbound += obj->base.size;
5265 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5266 if (!obj->base.filp)
5269 if (obj->pages_pin_count)
5270 pinned += obj->base.size;
5272 bound += obj->base.size;
5276 mutex_unlock(&dev->struct_mutex);
5278 if (freed_pages || unbound || bound)
5279 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5280 freed_pages << PAGE_SHIFT, pinned);
5281 if (unbound || bound)
5282 pr_err("%lu and %lu bytes still available in the "
5283 "bound and unbound GPU page lists.\n",
5286 *(unsigned long *)ptr += freed_pages;
5290 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5292 struct i915_vma *vma;
5294 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5295 if (vma->vm != i915_obj_to_ggtt(obj))