2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43 bool map_and_fenceable,
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
65 i915_gem_release_mmap(obj);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj->fence_dirty = false;
71 obj->fence_reg = I915_FENCE_REG_NONE;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
78 dev_priv->mm.object_count++;
79 dev_priv->mm.object_memory += size;
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
85 dev_priv->mm.object_count--;
86 dev_priv->mm.object_memory -= size;
90 i915_gem_wait_for_error(struct i915_gpu_error *error)
94 #define EXIT_COND (!i915_reset_in_progress(error) || \
95 i915_terminally_wedged(error))
100 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
101 * userspace. If it takes that long something really bad is going on and
102 * we should simply try to bail out and fail as gracefully as possible.
104 ret = wait_event_interruptible_timeout(error->reset_queue,
108 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
110 } else if (ret < 0) {
118 int i915_mutex_lock_interruptible(struct drm_device *dev)
120 struct drm_i915_private *dev_priv = dev->dev_private;
123 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
127 ret = mutex_lock_interruptible(&dev->struct_mutex);
131 WARN_ON(i915_verify_lists(dev));
136 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
138 return obj->gtt_space && !obj->active;
142 i915_gem_init_ioctl(struct drm_device *dev, void *data,
143 struct drm_file *file)
145 struct drm_i915_private *dev_priv = dev->dev_private;
146 struct drm_i915_gem_init *args = data;
148 if (drm_core_check_feature(dev, DRIVER_MODESET))
151 if (args->gtt_start >= args->gtt_end ||
152 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
155 /* GEM with user mode setting was never supported on ilk and later. */
156 if (INTEL_INFO(dev)->gen >= 5)
159 mutex_lock(&dev->struct_mutex);
160 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
162 dev_priv->gtt.mappable_end = args->gtt_end;
163 mutex_unlock(&dev->struct_mutex);
169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_get_aperture *args = data;
174 struct drm_i915_gem_object *obj;
178 mutex_lock(&dev->struct_mutex);
179 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
181 pinned += obj->gtt_space->size;
182 mutex_unlock(&dev->struct_mutex);
184 args->aper_size = dev_priv->gtt.total;
185 args->aper_available_size = args->aper_size - pinned;
190 void *i915_gem_object_alloc(struct drm_device *dev)
192 struct drm_i915_private *dev_priv = dev->dev_private;
193 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
196 void i915_gem_object_free(struct drm_i915_gem_object *obj)
198 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
199 kmem_cache_free(dev_priv->slab, obj);
203 i915_gem_create(struct drm_file *file,
204 struct drm_device *dev,
208 struct drm_i915_gem_object *obj;
212 size = roundup(size, PAGE_SIZE);
216 /* Allocate the new object */
217 obj = i915_gem_alloc_object(dev, size);
221 ret = drm_gem_handle_create(file, &obj->base, &handle);
223 drm_gem_object_release(&obj->base);
224 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
225 i915_gem_object_free(obj);
229 /* drop reference from allocate - handle holds it now */
230 drm_gem_object_unreference(&obj->base);
231 trace_i915_gem_object_create(obj);
238 i915_gem_dumb_create(struct drm_file *file,
239 struct drm_device *dev,
240 struct drm_mode_create_dumb *args)
242 /* have to work out size/pitch and return them */
243 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
244 args->size = args->pitch * args->height;
245 return i915_gem_create(file, dev,
246 args->size, &args->handle);
249 int i915_gem_dumb_destroy(struct drm_file *file,
250 struct drm_device *dev,
253 return drm_gem_handle_delete(file, handle);
257 * Creates a new mm object and returns a handle to it.
260 i915_gem_create_ioctl(struct drm_device *dev, void *data,
261 struct drm_file *file)
263 struct drm_i915_gem_create *args = data;
265 return i915_gem_create(file, dev,
266 args->size, &args->handle);
270 __copy_to_user_swizzled(char __user *cpu_vaddr,
271 const char *gpu_vaddr, int gpu_offset,
274 int ret, cpu_offset = 0;
277 int cacheline_end = ALIGN(gpu_offset + 1, 64);
278 int this_length = min(cacheline_end - gpu_offset, length);
279 int swizzled_gpu_offset = gpu_offset ^ 64;
281 ret = __copy_to_user(cpu_vaddr + cpu_offset,
282 gpu_vaddr + swizzled_gpu_offset,
287 cpu_offset += this_length;
288 gpu_offset += this_length;
289 length -= this_length;
296 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
297 const char __user *cpu_vaddr,
300 int ret, cpu_offset = 0;
303 int cacheline_end = ALIGN(gpu_offset + 1, 64);
304 int this_length = min(cacheline_end - gpu_offset, length);
305 int swizzled_gpu_offset = gpu_offset ^ 64;
307 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
308 cpu_vaddr + cpu_offset,
313 cpu_offset += this_length;
314 gpu_offset += this_length;
315 length -= this_length;
321 /* Per-page copy function for the shmem pread fastpath.
322 * Flushes invalid cachelines before reading the target if
323 * needs_clflush is set. */
325 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
326 char __user *user_data,
327 bool page_do_bit17_swizzling, bool needs_clflush)
332 if (unlikely(page_do_bit17_swizzling))
335 vaddr = kmap_atomic(page);
337 drm_clflush_virt_range(vaddr + shmem_page_offset,
339 ret = __copy_to_user_inatomic(user_data,
340 vaddr + shmem_page_offset,
342 kunmap_atomic(vaddr);
344 return ret ? -EFAULT : 0;
348 shmem_clflush_swizzled_range(char *addr, unsigned long length,
351 if (unlikely(swizzled)) {
352 unsigned long start = (unsigned long) addr;
353 unsigned long end = (unsigned long) addr + length;
355 /* For swizzling simply ensure that we always flush both
356 * channels. Lame, but simple and it works. Swizzled
357 * pwrite/pread is far from a hotpath - current userspace
358 * doesn't use it at all. */
359 start = round_down(start, 128);
360 end = round_up(end, 128);
362 drm_clflush_virt_range((void *)start, end - start);
364 drm_clflush_virt_range(addr, length);
369 /* Only difference to the fast-path function is that this can handle bit17
370 * and uses non-atomic copy and kmap functions. */
372 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
373 char __user *user_data,
374 bool page_do_bit17_swizzling, bool needs_clflush)
381 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
383 page_do_bit17_swizzling);
385 if (page_do_bit17_swizzling)
386 ret = __copy_to_user_swizzled(user_data,
387 vaddr, shmem_page_offset,
390 ret = __copy_to_user(user_data,
391 vaddr + shmem_page_offset,
395 return ret ? - EFAULT : 0;
399 i915_gem_shmem_pread(struct drm_device *dev,
400 struct drm_i915_gem_object *obj,
401 struct drm_i915_gem_pread *args,
402 struct drm_file *file)
404 char __user *user_data;
407 int shmem_page_offset, page_length, ret = 0;
408 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
410 int needs_clflush = 0;
411 struct sg_page_iter sg_iter;
413 user_data = to_user_ptr(args->data_ptr);
416 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
418 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
419 /* If we're not in the cpu read domain, set ourself into the gtt
420 * read domain and manually flush cachelines (if required). This
421 * optimizes for the case when the gpu will dirty the data
422 * anyway again before the next pread happens. */
423 if (obj->cache_level == I915_CACHE_NONE)
425 if (obj->gtt_space) {
426 ret = i915_gem_object_set_to_gtt_domain(obj, false);
432 ret = i915_gem_object_get_pages(obj);
436 i915_gem_object_pin_pages(obj);
438 offset = args->offset;
440 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
441 offset >> PAGE_SHIFT) {
442 struct page *page = sg_page_iter_page(&sg_iter);
447 /* Operation in this page
449 * shmem_page_offset = offset within page in shmem file
450 * page_length = bytes to copy for this page
452 shmem_page_offset = offset_in_page(offset);
453 page_length = remain;
454 if ((shmem_page_offset + page_length) > PAGE_SIZE)
455 page_length = PAGE_SIZE - shmem_page_offset;
457 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
458 (page_to_phys(page) & (1 << 17)) != 0;
460 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
461 user_data, page_do_bit17_swizzling,
466 mutex_unlock(&dev->struct_mutex);
469 ret = fault_in_multipages_writeable(user_data, remain);
470 /* Userspace is tricking us, but we've already clobbered
471 * its pages with the prefault and promised to write the
472 * data up to the first fault. Hence ignore any errors
473 * and just continue. */
478 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
479 user_data, page_do_bit17_swizzling,
482 mutex_lock(&dev->struct_mutex);
485 mark_page_accessed(page);
490 remain -= page_length;
491 user_data += page_length;
492 offset += page_length;
496 i915_gem_object_unpin_pages(obj);
502 * Reads data from the object referenced by handle.
504 * On error, the contents of *data are undefined.
507 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
508 struct drm_file *file)
510 struct drm_i915_gem_pread *args = data;
511 struct drm_i915_gem_object *obj;
517 if (!access_ok(VERIFY_WRITE,
518 to_user_ptr(args->data_ptr),
522 ret = i915_mutex_lock_interruptible(dev);
526 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
527 if (&obj->base == NULL) {
532 /* Bounds check source. */
533 if (args->offset > obj->base.size ||
534 args->size > obj->base.size - args->offset) {
539 /* prime objects have no backing filp to GEM pread/pwrite
542 if (!obj->base.filp) {
547 trace_i915_gem_object_pread(obj, args->offset, args->size);
549 ret = i915_gem_shmem_pread(dev, obj, args, file);
552 drm_gem_object_unreference(&obj->base);
554 mutex_unlock(&dev->struct_mutex);
558 /* This is the fast write path which cannot handle
559 * page faults in the source data
563 fast_user_write(struct io_mapping *mapping,
564 loff_t page_base, int page_offset,
565 char __user *user_data,
568 void __iomem *vaddr_atomic;
570 unsigned long unwritten;
572 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
573 /* We can use the cpu mem copy function because this is X86. */
574 vaddr = (void __force*)vaddr_atomic + page_offset;
575 unwritten = __copy_from_user_inatomic_nocache(vaddr,
577 io_mapping_unmap_atomic(vaddr_atomic);
582 * This is the fast pwrite path, where we copy the data directly from the
583 * user into the GTT, uncached.
586 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
587 struct drm_i915_gem_object *obj,
588 struct drm_i915_gem_pwrite *args,
589 struct drm_file *file)
591 drm_i915_private_t *dev_priv = dev->dev_private;
593 loff_t offset, page_base;
594 char __user *user_data;
595 int page_offset, page_length, ret;
597 ret = i915_gem_object_pin(obj, 0, true, true);
601 ret = i915_gem_object_set_to_gtt_domain(obj, true);
605 ret = i915_gem_object_put_fence(obj);
609 user_data = to_user_ptr(args->data_ptr);
612 offset = obj->gtt_offset + args->offset;
615 /* Operation in this page
617 * page_base = page offset within aperture
618 * page_offset = offset within page
619 * page_length = bytes to copy for this page
621 page_base = offset & PAGE_MASK;
622 page_offset = offset_in_page(offset);
623 page_length = remain;
624 if ((page_offset + remain) > PAGE_SIZE)
625 page_length = PAGE_SIZE - page_offset;
627 /* If we get a fault while copying data, then (presumably) our
628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
631 if (fast_user_write(dev_priv->gtt.mappable, page_base,
632 page_offset, user_data, page_length)) {
637 remain -= page_length;
638 user_data += page_length;
639 offset += page_length;
643 i915_gem_object_unpin(obj);
648 /* Per-page copy function for the shmem pwrite fastpath.
649 * Flushes invalid cachelines before writing to the target if
650 * needs_clflush_before is set and flushes out any written cachelines after
651 * writing if needs_clflush is set. */
653 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
654 char __user *user_data,
655 bool page_do_bit17_swizzling,
656 bool needs_clflush_before,
657 bool needs_clflush_after)
662 if (unlikely(page_do_bit17_swizzling))
665 vaddr = kmap_atomic(page);
666 if (needs_clflush_before)
667 drm_clflush_virt_range(vaddr + shmem_page_offset,
669 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
672 if (needs_clflush_after)
673 drm_clflush_virt_range(vaddr + shmem_page_offset,
675 kunmap_atomic(vaddr);
677 return ret ? -EFAULT : 0;
680 /* Only difference to the fast-path function is that this can handle bit17
681 * and uses non-atomic copy and kmap functions. */
683 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
684 char __user *user_data,
685 bool page_do_bit17_swizzling,
686 bool needs_clflush_before,
687 bool needs_clflush_after)
693 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
694 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
696 page_do_bit17_swizzling);
697 if (page_do_bit17_swizzling)
698 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
702 ret = __copy_from_user(vaddr + shmem_page_offset,
705 if (needs_clflush_after)
706 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
708 page_do_bit17_swizzling);
711 return ret ? -EFAULT : 0;
715 i915_gem_shmem_pwrite(struct drm_device *dev,
716 struct drm_i915_gem_object *obj,
717 struct drm_i915_gem_pwrite *args,
718 struct drm_file *file)
722 char __user *user_data;
723 int shmem_page_offset, page_length, ret = 0;
724 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
725 int hit_slowpath = 0;
726 int needs_clflush_after = 0;
727 int needs_clflush_before = 0;
728 struct sg_page_iter sg_iter;
730 user_data = to_user_ptr(args->data_ptr);
733 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
735 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
736 /* If we're not in the cpu write domain, set ourself into the gtt
737 * write domain and manually flush cachelines (if required). This
738 * optimizes for the case when the gpu will use the data
739 * right away and we therefore have to clflush anyway. */
740 if (obj->cache_level == I915_CACHE_NONE)
741 needs_clflush_after = 1;
742 if (obj->gtt_space) {
743 ret = i915_gem_object_set_to_gtt_domain(obj, true);
748 /* Same trick applies for invalidate partially written cachelines before
750 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
751 && obj->cache_level == I915_CACHE_NONE)
752 needs_clflush_before = 1;
754 ret = i915_gem_object_get_pages(obj);
758 i915_gem_object_pin_pages(obj);
760 offset = args->offset;
763 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
764 offset >> PAGE_SHIFT) {
765 struct page *page = sg_page_iter_page(&sg_iter);
766 int partial_cacheline_write;
771 /* Operation in this page
773 * shmem_page_offset = offset within page in shmem file
774 * page_length = bytes to copy for this page
776 shmem_page_offset = offset_in_page(offset);
778 page_length = remain;
779 if ((shmem_page_offset + page_length) > PAGE_SIZE)
780 page_length = PAGE_SIZE - shmem_page_offset;
782 /* If we don't overwrite a cacheline completely we need to be
783 * careful to have up-to-date data by first clflushing. Don't
784 * overcomplicate things and flush the entire patch. */
785 partial_cacheline_write = needs_clflush_before &&
786 ((shmem_page_offset | page_length)
787 & (boot_cpu_data.x86_clflush_size - 1));
789 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
790 (page_to_phys(page) & (1 << 17)) != 0;
792 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
793 user_data, page_do_bit17_swizzling,
794 partial_cacheline_write,
795 needs_clflush_after);
800 mutex_unlock(&dev->struct_mutex);
801 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
802 user_data, page_do_bit17_swizzling,
803 partial_cacheline_write,
804 needs_clflush_after);
806 mutex_lock(&dev->struct_mutex);
809 set_page_dirty(page);
810 mark_page_accessed(page);
815 remain -= page_length;
816 user_data += page_length;
817 offset += page_length;
821 i915_gem_object_unpin_pages(obj);
825 * Fixup: Flush cpu caches in case we didn't flush the dirty
826 * cachelines in-line while writing and the object moved
827 * out of the cpu write domain while we've dropped the lock.
829 if (!needs_clflush_after &&
830 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
831 i915_gem_clflush_object(obj);
832 i915_gem_chipset_flush(dev);
836 if (needs_clflush_after)
837 i915_gem_chipset_flush(dev);
843 * Writes data to the object referenced by handle.
845 * On error, the contents of the buffer that were to be modified are undefined.
848 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
849 struct drm_file *file)
851 struct drm_i915_gem_pwrite *args = data;
852 struct drm_i915_gem_object *obj;
858 if (!access_ok(VERIFY_READ,
859 to_user_ptr(args->data_ptr),
863 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
868 ret = i915_mutex_lock_interruptible(dev);
872 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
873 if (&obj->base == NULL) {
878 /* Bounds check destination. */
879 if (args->offset > obj->base.size ||
880 args->size > obj->base.size - args->offset) {
885 /* prime objects have no backing filp to GEM pread/pwrite
888 if (!obj->base.filp) {
893 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
896 /* We can only do the GTT pwrite on untiled buffers, as otherwise
897 * it would end up going through the fenced access, and we'll get
898 * different detiling behavior between reading and writing.
899 * pread/pwrite currently are reading and writing from the CPU
900 * perspective, requiring manual detiling by the client.
903 ret = i915_gem_phys_pwrite(dev, obj, args, file);
907 if (obj->cache_level == I915_CACHE_NONE &&
908 obj->tiling_mode == I915_TILING_NONE &&
909 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
910 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
911 /* Note that the gtt paths might fail with non-page-backed user
912 * pointers (e.g. gtt mappings when moving data between
913 * textures). Fallback to the shmem path in that case. */
916 if (ret == -EFAULT || ret == -ENOSPC)
917 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
920 drm_gem_object_unreference(&obj->base);
922 mutex_unlock(&dev->struct_mutex);
927 i915_gem_check_wedge(struct i915_gpu_error *error,
930 if (i915_reset_in_progress(error)) {
931 /* Non-interruptible callers can't handle -EAGAIN, hence return
932 * -EIO unconditionally for these. */
936 /* Recovery complete, but the reset failed ... */
937 if (i915_terminally_wedged(error))
947 * Compare seqno against outstanding lazy request. Emit a request if they are
951 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
955 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
958 if (seqno == ring->outstanding_lazy_request)
959 ret = i915_add_request(ring, NULL, NULL);
965 * __wait_seqno - wait until execution of seqno has finished
966 * @ring: the ring expected to report seqno
968 * @reset_counter: reset sequence associated with the given seqno
969 * @interruptible: do an interruptible wait (normally yes)
970 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
972 * Note: It is of utmost importance that the passed in seqno and reset_counter
973 * values have been read by the caller in an smp safe manner. Where read-side
974 * locks are involved, it is sufficient to read the reset_counter before
975 * unlocking the lock that protects the seqno. For lockless tricks, the
976 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
979 * Returns 0 if the seqno was found within the alloted time. Else returns the
980 * errno with remaining time filled in timeout argument.
982 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
983 unsigned reset_counter,
984 bool interruptible, struct timespec *timeout)
986 drm_i915_private_t *dev_priv = ring->dev->dev_private;
987 struct timespec before, now, wait_time={1,0};
988 unsigned long timeout_jiffies;
990 bool wait_forever = true;
993 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
996 trace_i915_gem_request_wait_begin(ring, seqno);
998 if (timeout != NULL) {
999 wait_time = *timeout;
1000 wait_forever = false;
1003 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1005 if (WARN_ON(!ring->irq_get(ring)))
1008 /* Record current time in case interrupted by signal, or wedged * */
1009 getrawmonotonic(&before);
1012 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1013 i915_reset_in_progress(&dev_priv->gpu_error) || \
1014 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1017 end = wait_event_interruptible_timeout(ring->irq_queue,
1021 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1024 /* We need to check whether any gpu reset happened in between
1025 * the caller grabbing the seqno and now ... */
1026 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1029 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1031 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1034 } while (end == 0 && wait_forever);
1036 getrawmonotonic(&now);
1038 ring->irq_put(ring);
1039 trace_i915_gem_request_wait_end(ring, seqno);
1043 struct timespec sleep_time = timespec_sub(now, before);
1044 *timeout = timespec_sub(*timeout, sleep_time);
1045 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1046 set_normalized_timespec(timeout, 0, 0);
1051 case -EAGAIN: /* Wedged */
1052 case -ERESTARTSYS: /* Signal */
1054 case 0: /* Timeout */
1056 default: /* Completed */
1057 WARN_ON(end < 0); /* We're not aware of other errors */
1063 * Waits for a sequence number to be signaled, and cleans up the
1064 * request and object lists appropriately for that event.
1067 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1069 struct drm_device *dev = ring->dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 bool interruptible = dev_priv->mm.interruptible;
1074 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1077 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1081 ret = i915_gem_check_olr(ring, seqno);
1085 return __wait_seqno(ring, seqno,
1086 atomic_read(&dev_priv->gpu_error.reset_counter),
1087 interruptible, NULL);
1091 * Ensures that all rendering to the object has completed and the object is
1092 * safe to unbind from the GTT or access from the CPU.
1094 static __must_check int
1095 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1098 struct intel_ring_buffer *ring = obj->ring;
1102 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1106 ret = i915_wait_seqno(ring, seqno);
1110 i915_gem_retire_requests_ring(ring);
1112 /* Manually manage the write flush as we may have not yet
1113 * retired the buffer.
1115 if (obj->last_write_seqno &&
1116 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1117 obj->last_write_seqno = 0;
1118 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1124 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1125 * as the object state may change during this call.
1127 static __must_check int
1128 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1131 struct drm_device *dev = obj->base.dev;
1132 struct drm_i915_private *dev_priv = dev->dev_private;
1133 struct intel_ring_buffer *ring = obj->ring;
1134 unsigned reset_counter;
1138 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1139 BUG_ON(!dev_priv->mm.interruptible);
1141 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1145 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1149 ret = i915_gem_check_olr(ring, seqno);
1153 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1154 mutex_unlock(&dev->struct_mutex);
1155 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1156 mutex_lock(&dev->struct_mutex);
1158 i915_gem_retire_requests_ring(ring);
1160 /* Manually manage the write flush as we may have not yet
1161 * retired the buffer.
1164 obj->last_write_seqno &&
1165 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1166 obj->last_write_seqno = 0;
1167 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1174 * Called when user space prepares to use an object with the CPU, either
1175 * through the mmap ioctl's mapping or a GTT mapping.
1178 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1179 struct drm_file *file)
1181 struct drm_i915_gem_set_domain *args = data;
1182 struct drm_i915_gem_object *obj;
1183 uint32_t read_domains = args->read_domains;
1184 uint32_t write_domain = args->write_domain;
1187 /* Only handle setting domains to types used by the CPU. */
1188 if (write_domain & I915_GEM_GPU_DOMAINS)
1191 if (read_domains & I915_GEM_GPU_DOMAINS)
1194 /* Having something in the write domain implies it's in the read
1195 * domain, and only that read domain. Enforce that in the request.
1197 if (write_domain != 0 && read_domains != write_domain)
1200 ret = i915_mutex_lock_interruptible(dev);
1204 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1205 if (&obj->base == NULL) {
1210 /* Try to flush the object off the GPU without holding the lock.
1211 * We will repeat the flush holding the lock in the normal manner
1212 * to catch cases where we are gazumped.
1214 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1218 if (read_domains & I915_GEM_DOMAIN_GTT) {
1219 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1221 /* Silently promote "you're not bound, there was nothing to do"
1222 * to success, since the client was just asking us to
1223 * make sure everything was done.
1228 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1232 drm_gem_object_unreference(&obj->base);
1234 mutex_unlock(&dev->struct_mutex);
1239 * Called when user space has done writes to this buffer
1242 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1243 struct drm_file *file)
1245 struct drm_i915_gem_sw_finish *args = data;
1246 struct drm_i915_gem_object *obj;
1249 ret = i915_mutex_lock_interruptible(dev);
1253 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1254 if (&obj->base == NULL) {
1259 /* Pinned buffers may be scanout, so flush the cache */
1261 i915_gem_object_flush_cpu_write_domain(obj);
1263 drm_gem_object_unreference(&obj->base);
1265 mutex_unlock(&dev->struct_mutex);
1270 * Maps the contents of an object, returning the address it is mapped
1273 * While the mapping holds a reference on the contents of the object, it doesn't
1274 * imply a ref on the object itself.
1277 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1278 struct drm_file *file)
1280 struct drm_i915_gem_mmap *args = data;
1281 struct drm_gem_object *obj;
1284 obj = drm_gem_object_lookup(dev, file, args->handle);
1288 /* prime objects have no backing filp to GEM mmap
1292 drm_gem_object_unreference_unlocked(obj);
1296 addr = vm_mmap(obj->filp, 0, args->size,
1297 PROT_READ | PROT_WRITE, MAP_SHARED,
1299 drm_gem_object_unreference_unlocked(obj);
1300 if (IS_ERR((void *)addr))
1303 args->addr_ptr = (uint64_t) addr;
1309 * i915_gem_fault - fault a page into the GTT
1310 * vma: VMA in question
1313 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1314 * from userspace. The fault handler takes care of binding the object to
1315 * the GTT (if needed), allocating and programming a fence register (again,
1316 * only if needed based on whether the old reg is still valid or the object
1317 * is tiled) and inserting a new PTE into the faulting process.
1319 * Note that the faulting process may involve evicting existing objects
1320 * from the GTT and/or fence registers to make room. So performance may
1321 * suffer if the GTT working set is large or there are few fence registers
1324 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1326 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1327 struct drm_device *dev = obj->base.dev;
1328 drm_i915_private_t *dev_priv = dev->dev_private;
1329 pgoff_t page_offset;
1332 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1334 /* We don't use vmf->pgoff since that has the fake offset */
1335 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1338 ret = i915_mutex_lock_interruptible(dev);
1342 trace_i915_gem_object_fault(obj, page_offset, true, write);
1344 /* Access to snoopable pages through the GTT is incoherent. */
1345 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1350 /* Now bind it into the GTT if needed */
1351 ret = i915_gem_object_pin(obj, 0, true, false);
1355 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1359 ret = i915_gem_object_get_fence(obj);
1363 obj->fault_mappable = true;
1365 pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) +
1368 /* Finally, remap it using the new GTT offset */
1369 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1371 i915_gem_object_unpin(obj);
1373 mutex_unlock(&dev->struct_mutex);
1377 /* If this -EIO is due to a gpu hang, give the reset code a
1378 * chance to clean up the mess. Otherwise return the proper
1380 if (i915_terminally_wedged(&dev_priv->gpu_error))
1381 return VM_FAULT_SIGBUS;
1383 /* Give the error handler a chance to run and move the
1384 * objects off the GPU active list. Next time we service the
1385 * fault, we should be able to transition the page into the
1386 * GTT without touching the GPU (and so avoid further
1387 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1388 * with coherency, just lost writes.
1396 * EBUSY is ok: this just means that another thread
1397 * already did the job.
1399 return VM_FAULT_NOPAGE;
1401 return VM_FAULT_OOM;
1403 return VM_FAULT_SIGBUS;
1405 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1406 return VM_FAULT_SIGBUS;
1411 * i915_gem_release_mmap - remove physical page mappings
1412 * @obj: obj in question
1414 * Preserve the reservation of the mmapping with the DRM core code, but
1415 * relinquish ownership of the pages back to the system.
1417 * It is vital that we remove the page mapping if we have mapped a tiled
1418 * object through the GTT and then lose the fence register due to
1419 * resource pressure. Similarly if the object has been moved out of the
1420 * aperture, than pages mapped into userspace must be revoked. Removing the
1421 * mapping will then trigger a page fault on the next user access, allowing
1422 * fixup by i915_gem_fault().
1425 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1427 if (!obj->fault_mappable)
1430 if (obj->base.dev->dev_mapping)
1431 unmap_mapping_range(obj->base.dev->dev_mapping,
1432 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1435 obj->fault_mappable = false;
1439 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1443 if (INTEL_INFO(dev)->gen >= 4 ||
1444 tiling_mode == I915_TILING_NONE)
1447 /* Previous chips need a power-of-two fence region when tiling */
1448 if (INTEL_INFO(dev)->gen == 3)
1449 gtt_size = 1024*1024;
1451 gtt_size = 512*1024;
1453 while (gtt_size < size)
1460 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1461 * @obj: object to check
1463 * Return the required GTT alignment for an object, taking into account
1464 * potential fence register mapping.
1467 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1468 int tiling_mode, bool fenced)
1471 * Minimum alignment is 4k (GTT page size), but might be greater
1472 * if a fence register is needed for the object.
1474 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1475 tiling_mode == I915_TILING_NONE)
1479 * Previous chips need to be aligned to the size of the smallest
1480 * fence register that can contain the object.
1482 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1485 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1487 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1490 if (obj->base.map_list.map)
1493 dev_priv->mm.shrinker_no_lock_stealing = true;
1495 ret = drm_gem_create_mmap_offset(&obj->base);
1499 /* Badly fragmented mmap space? The only way we can recover
1500 * space is by destroying unwanted objects. We can't randomly release
1501 * mmap_offsets as userspace expects them to be persistent for the
1502 * lifetime of the objects. The closest we can is to release the
1503 * offsets on purgeable objects by truncating it and marking it purged,
1504 * which prevents userspace from ever using that object again.
1506 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1507 ret = drm_gem_create_mmap_offset(&obj->base);
1511 i915_gem_shrink_all(dev_priv);
1512 ret = drm_gem_create_mmap_offset(&obj->base);
1514 dev_priv->mm.shrinker_no_lock_stealing = false;
1519 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1521 if (!obj->base.map_list.map)
1524 drm_gem_free_mmap_offset(&obj->base);
1528 i915_gem_mmap_gtt(struct drm_file *file,
1529 struct drm_device *dev,
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 struct drm_i915_gem_object *obj;
1537 ret = i915_mutex_lock_interruptible(dev);
1541 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1542 if (&obj->base == NULL) {
1547 if (obj->base.size > dev_priv->gtt.mappable_end) {
1552 if (obj->madv != I915_MADV_WILLNEED) {
1553 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1558 ret = i915_gem_object_create_mmap_offset(obj);
1562 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1565 drm_gem_object_unreference(&obj->base);
1567 mutex_unlock(&dev->struct_mutex);
1572 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1574 * @data: GTT mapping ioctl data
1575 * @file: GEM object info
1577 * Simply returns the fake offset to userspace so it can mmap it.
1578 * The mmap call will end up in drm_gem_mmap(), which will set things
1579 * up so we can get faults in the handler above.
1581 * The fault handler will take care of binding the object into the GTT
1582 * (since it may have been evicted to make room for something), allocating
1583 * a fence register, and mapping the appropriate aperture address into
1587 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1588 struct drm_file *file)
1590 struct drm_i915_gem_mmap_gtt *args = data;
1592 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1595 /* Immediately discard the backing storage */
1597 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1599 struct inode *inode;
1601 i915_gem_object_free_mmap_offset(obj);
1603 if (obj->base.filp == NULL)
1606 /* Our goal here is to return as much of the memory as
1607 * is possible back to the system as we are called from OOM.
1608 * To do this we must instruct the shmfs to drop all of its
1609 * backing pages, *now*.
1611 inode = file_inode(obj->base.filp);
1612 shmem_truncate_range(inode, 0, (loff_t)-1);
1614 obj->madv = __I915_MADV_PURGED;
1618 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1620 return obj->madv == I915_MADV_DONTNEED;
1624 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1626 struct sg_page_iter sg_iter;
1629 BUG_ON(obj->madv == __I915_MADV_PURGED);
1631 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1633 /* In the event of a disaster, abandon all caches and
1634 * hope for the best.
1636 WARN_ON(ret != -EIO);
1637 i915_gem_clflush_object(obj);
1638 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1641 if (i915_gem_object_needs_bit17_swizzle(obj))
1642 i915_gem_object_save_bit_17_swizzle(obj);
1644 if (obj->madv == I915_MADV_DONTNEED)
1647 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1648 struct page *page = sg_page_iter_page(&sg_iter);
1651 set_page_dirty(page);
1653 if (obj->madv == I915_MADV_WILLNEED)
1654 mark_page_accessed(page);
1656 page_cache_release(page);
1660 sg_free_table(obj->pages);
1665 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1667 const struct drm_i915_gem_object_ops *ops = obj->ops;
1669 if (obj->pages == NULL)
1672 BUG_ON(obj->gtt_space);
1674 if (obj->pages_pin_count)
1677 /* ->put_pages might need to allocate memory for the bit17 swizzle
1678 * array, hence protect them from being reaped by removing them from gtt
1680 list_del(&obj->gtt_list);
1682 ops->put_pages(obj);
1685 if (i915_gem_object_is_purgeable(obj))
1686 i915_gem_object_truncate(obj);
1692 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1693 bool purgeable_only)
1695 struct drm_i915_gem_object *obj, *next;
1698 list_for_each_entry_safe(obj, next,
1699 &dev_priv->mm.unbound_list,
1701 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1702 i915_gem_object_put_pages(obj) == 0) {
1703 count += obj->base.size >> PAGE_SHIFT;
1704 if (count >= target)
1709 list_for_each_entry_safe(obj, next,
1710 &dev_priv->mm.inactive_list,
1712 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1713 i915_gem_object_unbind(obj) == 0 &&
1714 i915_gem_object_put_pages(obj) == 0) {
1715 count += obj->base.size >> PAGE_SHIFT;
1716 if (count >= target)
1725 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1727 return __i915_gem_shrink(dev_priv, target, true);
1731 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1733 struct drm_i915_gem_object *obj, *next;
1735 i915_gem_evict_everything(dev_priv->dev);
1737 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1738 i915_gem_object_put_pages(obj);
1742 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1744 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1746 struct address_space *mapping;
1747 struct sg_table *st;
1748 struct scatterlist *sg;
1749 struct sg_page_iter sg_iter;
1751 unsigned long last_pfn = 0; /* suppress gcc warning */
1754 /* Assert that the object is not currently in any GPU domain. As it
1755 * wasn't in the GTT, there shouldn't be any way it could have been in
1758 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1759 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1761 st = kmalloc(sizeof(*st), GFP_KERNEL);
1765 page_count = obj->base.size / PAGE_SIZE;
1766 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1772 /* Get the list of pages out of our struct file. They'll be pinned
1773 * at this point until we release them.
1775 * Fail silently without starting the shrinker
1777 mapping = file_inode(obj->base.filp)->i_mapping;
1778 gfp = mapping_gfp_mask(mapping);
1779 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1780 gfp &= ~(__GFP_IO | __GFP_WAIT);
1783 for (i = 0; i < page_count; i++) {
1784 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1786 i915_gem_purge(dev_priv, page_count);
1787 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1790 /* We've tried hard to allocate the memory by reaping
1791 * our own buffer, now let the real VM do its job and
1792 * go down in flames if truly OOM.
1794 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1795 gfp |= __GFP_IO | __GFP_WAIT;
1797 i915_gem_shrink_all(dev_priv);
1798 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1802 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1803 gfp &= ~(__GFP_IO | __GFP_WAIT);
1805 #ifdef CONFIG_SWIOTLB
1806 if (swiotlb_nr_tbl()) {
1808 sg_set_page(sg, page, PAGE_SIZE, 0);
1813 if (!i || page_to_pfn(page) != last_pfn + 1) {
1817 sg_set_page(sg, page, PAGE_SIZE, 0);
1819 sg->length += PAGE_SIZE;
1821 last_pfn = page_to_pfn(page);
1823 #ifdef CONFIG_SWIOTLB
1824 if (!swiotlb_nr_tbl())
1829 if (i915_gem_object_needs_bit17_swizzle(obj))
1830 i915_gem_object_do_bit_17_swizzle(obj);
1836 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1837 page_cache_release(sg_page_iter_page(&sg_iter));
1840 return PTR_ERR(page);
1843 /* Ensure that the associated pages are gathered from the backing storage
1844 * and pinned into our object. i915_gem_object_get_pages() may be called
1845 * multiple times before they are released by a single call to
1846 * i915_gem_object_put_pages() - once the pages are no longer referenced
1847 * either as a result of memory pressure (reaping pages under the shrinker)
1848 * or as the object is itself released.
1851 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1853 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1854 const struct drm_i915_gem_object_ops *ops = obj->ops;
1860 if (obj->madv != I915_MADV_WILLNEED) {
1861 DRM_ERROR("Attempting to obtain a purgeable object\n");
1865 BUG_ON(obj->pages_pin_count);
1867 ret = ops->get_pages(obj);
1871 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1876 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1877 struct intel_ring_buffer *ring)
1879 struct drm_device *dev = obj->base.dev;
1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881 u32 seqno = intel_ring_get_seqno(ring);
1883 BUG_ON(ring == NULL);
1884 if (obj->ring != ring && obj->last_write_seqno) {
1885 /* Keep the seqno relative to the current ring */
1886 obj->last_write_seqno = seqno;
1890 /* Add a reference if we're newly entering the active list. */
1892 drm_gem_object_reference(&obj->base);
1896 /* Move from whatever list we were on to the tail of execution. */
1897 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1898 list_move_tail(&obj->ring_list, &ring->active_list);
1900 obj->last_read_seqno = seqno;
1902 if (obj->fenced_gpu_access) {
1903 obj->last_fenced_seqno = seqno;
1905 /* Bump MRU to take account of the delayed flush */
1906 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1907 struct drm_i915_fence_reg *reg;
1909 reg = &dev_priv->fence_regs[obj->fence_reg];
1910 list_move_tail(®->lru_list,
1911 &dev_priv->mm.fence_list);
1917 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1919 struct drm_device *dev = obj->base.dev;
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1922 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1923 BUG_ON(!obj->active);
1925 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1927 list_del_init(&obj->ring_list);
1930 obj->last_read_seqno = 0;
1931 obj->last_write_seqno = 0;
1932 obj->base.write_domain = 0;
1934 obj->last_fenced_seqno = 0;
1935 obj->fenced_gpu_access = false;
1938 drm_gem_object_unreference(&obj->base);
1940 WARN_ON(i915_verify_lists(dev));
1944 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1946 struct drm_i915_private *dev_priv = dev->dev_private;
1947 struct intel_ring_buffer *ring;
1950 /* Carefully retire all requests without writing to the rings */
1951 for_each_ring(ring, dev_priv, i) {
1952 ret = intel_ring_idle(ring);
1956 i915_gem_retire_requests(dev);
1958 /* Finally reset hw state */
1959 for_each_ring(ring, dev_priv, i) {
1960 intel_ring_init_seqno(ring, seqno);
1962 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1963 ring->sync_seqno[j] = 0;
1969 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1971 struct drm_i915_private *dev_priv = dev->dev_private;
1977 /* HWS page needs to be set less than what we
1978 * will inject to ring
1980 ret = i915_gem_init_seqno(dev, seqno - 1);
1984 /* Carefully set the last_seqno value so that wrap
1985 * detection still works
1987 dev_priv->next_seqno = seqno;
1988 dev_priv->last_seqno = seqno - 1;
1989 if (dev_priv->last_seqno == 0)
1990 dev_priv->last_seqno--;
1996 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1998 struct drm_i915_private *dev_priv = dev->dev_private;
2000 /* reserve 0 for non-seqno */
2001 if (dev_priv->next_seqno == 0) {
2002 int ret = i915_gem_init_seqno(dev, 0);
2006 dev_priv->next_seqno = 1;
2009 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2014 i915_add_request(struct intel_ring_buffer *ring,
2015 struct drm_file *file,
2018 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2019 struct drm_i915_gem_request *request;
2020 u32 request_ring_position;
2025 * Emit any outstanding flushes - execbuf can fail to emit the flush
2026 * after having emitted the batchbuffer command. Hence we need to fix
2027 * things up similar to emitting the lazy request. The difference here
2028 * is that the flush _must_ happen before the next request, no matter
2031 ret = intel_ring_flush_all_caches(ring);
2035 request = kmalloc(sizeof(*request), GFP_KERNEL);
2036 if (request == NULL)
2040 /* Record the position of the start of the request so that
2041 * should we detect the updated seqno part-way through the
2042 * GPU processing the request, we never over-estimate the
2043 * position of the head.
2045 request_ring_position = intel_ring_get_tail(ring);
2047 ret = ring->add_request(ring);
2053 request->seqno = intel_ring_get_seqno(ring);
2054 request->ring = ring;
2055 request->tail = request_ring_position;
2056 request->emitted_jiffies = jiffies;
2057 was_empty = list_empty(&ring->request_list);
2058 list_add_tail(&request->list, &ring->request_list);
2059 request->file_priv = NULL;
2062 struct drm_i915_file_private *file_priv = file->driver_priv;
2064 spin_lock(&file_priv->mm.lock);
2065 request->file_priv = file_priv;
2066 list_add_tail(&request->client_list,
2067 &file_priv->mm.request_list);
2068 spin_unlock(&file_priv->mm.lock);
2071 trace_i915_gem_request_add(ring, request->seqno);
2072 ring->outstanding_lazy_request = 0;
2074 if (!dev_priv->mm.suspended) {
2075 if (i915_enable_hangcheck) {
2076 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2077 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2080 queue_delayed_work(dev_priv->wq,
2081 &dev_priv->mm.retire_work,
2082 round_jiffies_up_relative(HZ));
2083 intel_mark_busy(dev_priv->dev);
2088 *out_seqno = request->seqno;
2093 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2095 struct drm_i915_file_private *file_priv = request->file_priv;
2100 spin_lock(&file_priv->mm.lock);
2101 if (request->file_priv) {
2102 list_del(&request->client_list);
2103 request->file_priv = NULL;
2105 spin_unlock(&file_priv->mm.lock);
2108 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2109 struct intel_ring_buffer *ring)
2111 while (!list_empty(&ring->request_list)) {
2112 struct drm_i915_gem_request *request;
2114 request = list_first_entry(&ring->request_list,
2115 struct drm_i915_gem_request,
2118 list_del(&request->list);
2119 i915_gem_request_remove_from_client(request);
2123 while (!list_empty(&ring->active_list)) {
2124 struct drm_i915_gem_object *obj;
2126 obj = list_first_entry(&ring->active_list,
2127 struct drm_i915_gem_object,
2130 i915_gem_object_move_to_inactive(obj);
2134 void i915_gem_restore_fences(struct drm_device *dev)
2136 struct drm_i915_private *dev_priv = dev->dev_private;
2139 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2140 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2143 * Commit delayed tiling changes if we have an object still
2144 * attached to the fence, otherwise just clear the fence.
2147 i915_gem_object_update_fence(reg->obj, reg,
2148 reg->obj->tiling_mode);
2150 i915_gem_write_fence(dev, i, NULL);
2155 void i915_gem_reset(struct drm_device *dev)
2157 struct drm_i915_private *dev_priv = dev->dev_private;
2158 struct drm_i915_gem_object *obj;
2159 struct intel_ring_buffer *ring;
2162 for_each_ring(ring, dev_priv, i)
2163 i915_gem_reset_ring_lists(dev_priv, ring);
2165 /* Move everything out of the GPU domains to ensure we do any
2166 * necessary invalidation upon reuse.
2168 list_for_each_entry(obj,
2169 &dev_priv->mm.inactive_list,
2172 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2175 i915_gem_restore_fences(dev);
2179 * This function clears the request list as sequence numbers are passed.
2182 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2186 if (list_empty(&ring->request_list))
2189 WARN_ON(i915_verify_lists(ring->dev));
2191 seqno = ring->get_seqno(ring, true);
2193 while (!list_empty(&ring->request_list)) {
2194 struct drm_i915_gem_request *request;
2196 request = list_first_entry(&ring->request_list,
2197 struct drm_i915_gem_request,
2200 if (!i915_seqno_passed(seqno, request->seqno))
2203 trace_i915_gem_request_retire(ring, request->seqno);
2204 /* We know the GPU must have read the request to have
2205 * sent us the seqno + interrupt, so use the position
2206 * of tail of the request to update the last known position
2209 ring->last_retired_head = request->tail;
2211 list_del(&request->list);
2212 i915_gem_request_remove_from_client(request);
2216 /* Move any buffers on the active list that are no longer referenced
2217 * by the ringbuffer to the flushing/inactive lists as appropriate.
2219 while (!list_empty(&ring->active_list)) {
2220 struct drm_i915_gem_object *obj;
2222 obj = list_first_entry(&ring->active_list,
2223 struct drm_i915_gem_object,
2226 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2229 i915_gem_object_move_to_inactive(obj);
2232 if (unlikely(ring->trace_irq_seqno &&
2233 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2234 ring->irq_put(ring);
2235 ring->trace_irq_seqno = 0;
2238 WARN_ON(i915_verify_lists(ring->dev));
2242 i915_gem_retire_requests(struct drm_device *dev)
2244 drm_i915_private_t *dev_priv = dev->dev_private;
2245 struct intel_ring_buffer *ring;
2248 for_each_ring(ring, dev_priv, i)
2249 i915_gem_retire_requests_ring(ring);
2253 i915_gem_retire_work_handler(struct work_struct *work)
2255 drm_i915_private_t *dev_priv;
2256 struct drm_device *dev;
2257 struct intel_ring_buffer *ring;
2261 dev_priv = container_of(work, drm_i915_private_t,
2262 mm.retire_work.work);
2263 dev = dev_priv->dev;
2265 /* Come back later if the device is busy... */
2266 if (!mutex_trylock(&dev->struct_mutex)) {
2267 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2268 round_jiffies_up_relative(HZ));
2272 i915_gem_retire_requests(dev);
2274 /* Send a periodic flush down the ring so we don't hold onto GEM
2275 * objects indefinitely.
2278 for_each_ring(ring, dev_priv, i) {
2279 if (ring->gpu_caches_dirty)
2280 i915_add_request(ring, NULL, NULL);
2282 idle &= list_empty(&ring->request_list);
2285 if (!dev_priv->mm.suspended && !idle)
2286 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2287 round_jiffies_up_relative(HZ));
2289 intel_mark_idle(dev);
2291 mutex_unlock(&dev->struct_mutex);
2295 * Ensures that an object will eventually get non-busy by flushing any required
2296 * write domains, emitting any outstanding lazy request and retiring and
2297 * completed requests.
2300 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2305 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2309 i915_gem_retire_requests_ring(obj->ring);
2316 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2317 * @DRM_IOCTL_ARGS: standard ioctl arguments
2319 * Returns 0 if successful, else an error is returned with the remaining time in
2320 * the timeout parameter.
2321 * -ETIME: object is still busy after timeout
2322 * -ERESTARTSYS: signal interrupted the wait
2323 * -ENONENT: object doesn't exist
2324 * Also possible, but rare:
2325 * -EAGAIN: GPU wedged
2327 * -ENODEV: Internal IRQ fail
2328 * -E?: The add request failed
2330 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2331 * non-zero timeout parameter the wait ioctl will wait for the given number of
2332 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2333 * without holding struct_mutex the object may become re-busied before this
2334 * function completes. A similar but shorter * race condition exists in the busy
2338 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2340 drm_i915_private_t *dev_priv = dev->dev_private;
2341 struct drm_i915_gem_wait *args = data;
2342 struct drm_i915_gem_object *obj;
2343 struct intel_ring_buffer *ring = NULL;
2344 struct timespec timeout_stack, *timeout = NULL;
2345 unsigned reset_counter;
2349 if (args->timeout_ns >= 0) {
2350 timeout_stack = ns_to_timespec(args->timeout_ns);
2351 timeout = &timeout_stack;
2354 ret = i915_mutex_lock_interruptible(dev);
2358 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2359 if (&obj->base == NULL) {
2360 mutex_unlock(&dev->struct_mutex);
2364 /* Need to make sure the object gets inactive eventually. */
2365 ret = i915_gem_object_flush_active(obj);
2370 seqno = obj->last_read_seqno;
2377 /* Do this after OLR check to make sure we make forward progress polling
2378 * on this IOCTL with a 0 timeout (like busy ioctl)
2380 if (!args->timeout_ns) {
2385 drm_gem_object_unreference(&obj->base);
2386 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2387 mutex_unlock(&dev->struct_mutex);
2389 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2391 args->timeout_ns = timespec_to_ns(timeout);
2395 drm_gem_object_unreference(&obj->base);
2396 mutex_unlock(&dev->struct_mutex);
2401 * i915_gem_object_sync - sync an object to a ring.
2403 * @obj: object which may be in use on another ring.
2404 * @to: ring we wish to use the object on. May be NULL.
2406 * This code is meant to abstract object synchronization with the GPU.
2407 * Calling with NULL implies synchronizing the object with the CPU
2408 * rather than a particular GPU ring.
2410 * Returns 0 if successful, else propagates up the lower layer error.
2413 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2414 struct intel_ring_buffer *to)
2416 struct intel_ring_buffer *from = obj->ring;
2420 if (from == NULL || to == from)
2423 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2424 return i915_gem_object_wait_rendering(obj, false);
2426 idx = intel_ring_sync_index(from, to);
2428 seqno = obj->last_read_seqno;
2429 if (seqno <= from->sync_seqno[idx])
2432 ret = i915_gem_check_olr(obj->ring, seqno);
2436 ret = to->sync_to(to, from, seqno);
2438 /* We use last_read_seqno because sync_to()
2439 * might have just caused seqno wrap under
2442 from->sync_seqno[idx] = obj->last_read_seqno;
2447 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2449 u32 old_write_domain, old_read_domains;
2451 /* Force a pagefault for domain tracking on next user access */
2452 i915_gem_release_mmap(obj);
2454 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2457 /* Wait for any direct GTT access to complete */
2460 old_read_domains = obj->base.read_domains;
2461 old_write_domain = obj->base.write_domain;
2463 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2464 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2466 trace_i915_gem_object_change_domain(obj,
2472 * Unbinds an object from the GTT aperture.
2475 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2477 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2480 if (obj->gtt_space == NULL)
2486 BUG_ON(obj->pages == NULL);
2488 ret = i915_gem_object_finish_gpu(obj);
2491 /* Continue on if we fail due to EIO, the GPU is hung so we
2492 * should be safe and we need to cleanup or else we might
2493 * cause memory corruption through use-after-free.
2496 i915_gem_object_finish_gtt(obj);
2498 /* release the fence reg _after_ flushing */
2499 ret = i915_gem_object_put_fence(obj);
2503 trace_i915_gem_object_unbind(obj);
2505 if (obj->has_global_gtt_mapping)
2506 i915_gem_gtt_unbind_object(obj);
2507 if (obj->has_aliasing_ppgtt_mapping) {
2508 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2509 obj->has_aliasing_ppgtt_mapping = 0;
2511 i915_gem_gtt_finish_object(obj);
2513 list_del(&obj->mm_list);
2514 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2515 /* Avoid an unnecessary call to unbind on rebind. */
2516 obj->map_and_fenceable = true;
2518 drm_mm_put_block(obj->gtt_space);
2519 obj->gtt_space = NULL;
2520 obj->gtt_offset = 0;
2525 int i915_gpu_idle(struct drm_device *dev)
2527 drm_i915_private_t *dev_priv = dev->dev_private;
2528 struct intel_ring_buffer *ring;
2531 /* Flush everything onto the inactive list. */
2532 for_each_ring(ring, dev_priv, i) {
2533 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2537 ret = intel_ring_idle(ring);
2545 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2546 struct drm_i915_gem_object *obj)
2548 drm_i915_private_t *dev_priv = dev->dev_private;
2550 int fence_pitch_shift;
2552 if (INTEL_INFO(dev)->gen >= 6) {
2553 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2554 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2556 fence_reg = FENCE_REG_965_0;
2557 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2560 fence_reg += reg * 8;
2562 /* To w/a incoherency with non-atomic 64-bit register updates,
2563 * we split the 64-bit update into two 32-bit writes. In order
2564 * for a partial fence not to be evaluated between writes, we
2565 * precede the update with write to turn off the fence register,
2566 * and only enable the fence as the last step.
2568 * For extra levels of paranoia, we make sure each step lands
2569 * before applying the next step.
2571 I915_WRITE(fence_reg, 0);
2572 POSTING_READ(fence_reg);
2575 u32 size = obj->gtt_space->size;
2578 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2580 val |= obj->gtt_offset & 0xfffff000;
2581 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2582 if (obj->tiling_mode == I915_TILING_Y)
2583 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2584 val |= I965_FENCE_REG_VALID;
2586 I915_WRITE(fence_reg + 4, val >> 32);
2587 POSTING_READ(fence_reg + 4);
2589 I915_WRITE(fence_reg + 0, val);
2590 POSTING_READ(fence_reg);
2592 I915_WRITE(fence_reg + 4, 0);
2593 POSTING_READ(fence_reg + 4);
2597 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2598 struct drm_i915_gem_object *obj)
2600 drm_i915_private_t *dev_priv = dev->dev_private;
2604 u32 size = obj->gtt_space->size;
2608 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2609 (size & -size) != size ||
2610 (obj->gtt_offset & (size - 1)),
2611 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2612 obj->gtt_offset, obj->map_and_fenceable, size);
2614 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2619 /* Note: pitch better be a power of two tile widths */
2620 pitch_val = obj->stride / tile_width;
2621 pitch_val = ffs(pitch_val) - 1;
2623 val = obj->gtt_offset;
2624 if (obj->tiling_mode == I915_TILING_Y)
2625 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2626 val |= I915_FENCE_SIZE_BITS(size);
2627 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2628 val |= I830_FENCE_REG_VALID;
2633 reg = FENCE_REG_830_0 + reg * 4;
2635 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2637 I915_WRITE(reg, val);
2641 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2642 struct drm_i915_gem_object *obj)
2644 drm_i915_private_t *dev_priv = dev->dev_private;
2648 u32 size = obj->gtt_space->size;
2651 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2652 (size & -size) != size ||
2653 (obj->gtt_offset & (size - 1)),
2654 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2655 obj->gtt_offset, size);
2657 pitch_val = obj->stride / 128;
2658 pitch_val = ffs(pitch_val) - 1;
2660 val = obj->gtt_offset;
2661 if (obj->tiling_mode == I915_TILING_Y)
2662 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2663 val |= I830_FENCE_SIZE_BITS(size);
2664 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2665 val |= I830_FENCE_REG_VALID;
2669 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2670 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2673 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2675 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2678 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2679 struct drm_i915_gem_object *obj)
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2683 /* Ensure that all CPU reads are completed before installing a fence
2684 * and all writes before removing the fence.
2686 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2689 WARN(obj && (!obj->stride || !obj->tiling_mode),
2690 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2691 obj->stride, obj->tiling_mode);
2693 switch (INTEL_INFO(dev)->gen) {
2697 case 4: i965_write_fence_reg(dev, reg, obj); break;
2698 case 3: i915_write_fence_reg(dev, reg, obj); break;
2699 case 2: i830_write_fence_reg(dev, reg, obj); break;
2703 /* And similarly be paranoid that no direct access to this region
2704 * is reordered to before the fence is installed.
2706 if (i915_gem_object_needs_mb(obj))
2710 static inline int fence_number(struct drm_i915_private *dev_priv,
2711 struct drm_i915_fence_reg *fence)
2713 return fence - dev_priv->fence_regs;
2716 static void i915_gem_write_fence__ipi(void *data)
2721 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2722 struct drm_i915_fence_reg *fence,
2725 struct drm_device *dev = obj->base.dev;
2726 struct drm_i915_private *dev_priv = dev->dev_private;
2727 int fence_reg = fence_number(dev_priv, fence);
2729 /* In order to fully serialize access to the fenced region and
2730 * the update to the fence register we need to take extreme
2731 * measures on SNB+. In theory, the write to the fence register
2732 * flushes all memory transactions before, and coupled with the
2733 * mb() placed around the register write we serialise all memory
2734 * operations with respect to the changes in the tiler. Yet, on
2735 * SNB+ we need to take a step further and emit an explicit wbinvd()
2736 * on each processor in order to manually flush all memory
2737 * transactions before updating the fence register.
2739 if (HAS_LLC(obj->base.dev))
2740 on_each_cpu(i915_gem_write_fence__ipi, NULL, 1);
2741 i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL);
2744 obj->fence_reg = fence_reg;
2746 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2748 obj->fence_reg = I915_FENCE_REG_NONE;
2750 list_del_init(&fence->lru_list);
2752 obj->fence_dirty = false;
2756 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2758 if (obj->last_fenced_seqno) {
2759 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2763 obj->last_fenced_seqno = 0;
2766 obj->fenced_gpu_access = false;
2771 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2773 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2774 struct drm_i915_fence_reg *fence;
2777 ret = i915_gem_object_wait_fence(obj);
2781 if (obj->fence_reg == I915_FENCE_REG_NONE)
2784 fence = &dev_priv->fence_regs[obj->fence_reg];
2786 i915_gem_object_fence_lost(obj);
2787 i915_gem_object_update_fence(obj, fence, false);
2792 static struct drm_i915_fence_reg *
2793 i915_find_fence_reg(struct drm_device *dev)
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2796 struct drm_i915_fence_reg *reg, *avail;
2799 /* First try to find a free reg */
2801 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2802 reg = &dev_priv->fence_regs[i];
2806 if (!reg->pin_count)
2813 /* None available, try to steal one or wait for a user to finish */
2814 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2825 * i915_gem_object_get_fence - set up fencing for an object
2826 * @obj: object to map through a fence reg
2828 * When mapping objects through the GTT, userspace wants to be able to write
2829 * to them without having to worry about swizzling if the object is tiled.
2830 * This function walks the fence regs looking for a free one for @obj,
2831 * stealing one if it can't find any.
2833 * It then sets up the reg based on the object's properties: address, pitch
2834 * and tiling format.
2836 * For an untiled surface, this removes any existing fence.
2839 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2841 struct drm_device *dev = obj->base.dev;
2842 struct drm_i915_private *dev_priv = dev->dev_private;
2843 bool enable = obj->tiling_mode != I915_TILING_NONE;
2844 struct drm_i915_fence_reg *reg;
2847 /* Have we updated the tiling parameters upon the object and so
2848 * will need to serialise the write to the associated fence register?
2850 if (obj->fence_dirty) {
2851 ret = i915_gem_object_wait_fence(obj);
2856 /* Just update our place in the LRU if our fence is getting reused. */
2857 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2858 reg = &dev_priv->fence_regs[obj->fence_reg];
2859 if (!obj->fence_dirty) {
2860 list_move_tail(®->lru_list,
2861 &dev_priv->mm.fence_list);
2864 } else if (enable) {
2865 reg = i915_find_fence_reg(dev);
2870 struct drm_i915_gem_object *old = reg->obj;
2872 ret = i915_gem_object_wait_fence(old);
2876 i915_gem_object_fence_lost(old);
2881 i915_gem_object_update_fence(obj, reg, enable);
2886 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2887 struct drm_mm_node *gtt_space,
2888 unsigned long cache_level)
2890 struct drm_mm_node *other;
2892 /* On non-LLC machines we have to be careful when putting differing
2893 * types of snoopable memory together to avoid the prefetcher
2894 * crossing memory domains and dying.
2899 if (gtt_space == NULL)
2902 if (list_empty(>t_space->node_list))
2905 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2906 if (other->allocated && !other->hole_follows && other->color != cache_level)
2909 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2910 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2916 static void i915_gem_verify_gtt(struct drm_device *dev)
2919 struct drm_i915_private *dev_priv = dev->dev_private;
2920 struct drm_i915_gem_object *obj;
2923 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2924 if (obj->gtt_space == NULL) {
2925 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2930 if (obj->cache_level != obj->gtt_space->color) {
2931 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2932 obj->gtt_space->start,
2933 obj->gtt_space->start + obj->gtt_space->size,
2935 obj->gtt_space->color);
2940 if (!i915_gem_valid_gtt_space(dev,
2942 obj->cache_level)) {
2943 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2944 obj->gtt_space->start,
2945 obj->gtt_space->start + obj->gtt_space->size,
2957 * Finds free space in the GTT aperture and binds the object there.
2960 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2962 bool map_and_fenceable,
2965 struct drm_device *dev = obj->base.dev;
2966 drm_i915_private_t *dev_priv = dev->dev_private;
2967 struct drm_mm_node *node;
2968 u32 size, fence_size, fence_alignment, unfenced_alignment;
2969 bool mappable, fenceable;
2972 fence_size = i915_gem_get_gtt_size(dev,
2975 fence_alignment = i915_gem_get_gtt_alignment(dev,
2977 obj->tiling_mode, true);
2978 unfenced_alignment =
2979 i915_gem_get_gtt_alignment(dev,
2981 obj->tiling_mode, false);
2984 alignment = map_and_fenceable ? fence_alignment :
2986 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2987 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2991 size = map_and_fenceable ? fence_size : obj->base.size;
2993 /* If the object is bigger than the entire aperture, reject it early
2994 * before evicting everything in a vain attempt to find space.
2996 if (obj->base.size >
2997 (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) {
2998 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
3002 ret = i915_gem_object_get_pages(obj);
3006 i915_gem_object_pin_pages(obj);
3008 node = kzalloc(sizeof(*node), GFP_KERNEL);
3010 i915_gem_object_unpin_pages(obj);
3015 if (map_and_fenceable)
3016 ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
3017 size, alignment, obj->cache_level,
3018 0, dev_priv->gtt.mappable_end);
3020 ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node,
3021 size, alignment, obj->cache_level);
3023 ret = i915_gem_evict_something(dev, size, alignment,
3030 i915_gem_object_unpin_pages(obj);
3034 if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
3035 i915_gem_object_unpin_pages(obj);
3036 drm_mm_put_block(node);
3040 ret = i915_gem_gtt_prepare_object(obj);
3042 i915_gem_object_unpin_pages(obj);
3043 drm_mm_put_block(node);
3047 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
3048 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3050 obj->gtt_space = node;
3051 obj->gtt_offset = node->start;
3054 node->size == fence_size &&
3055 (node->start & (fence_alignment - 1)) == 0;
3058 obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
3060 obj->map_and_fenceable = mappable && fenceable;
3062 i915_gem_object_unpin_pages(obj);
3063 trace_i915_gem_object_bind(obj, map_and_fenceable);
3064 i915_gem_verify_gtt(dev);
3069 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3071 /* If we don't have a page list set up, then we're not pinned
3072 * to GPU, and we can ignore the cache flush because it'll happen
3073 * again at bind time.
3075 if (obj->pages == NULL)
3079 * Stolen memory is always coherent with the GPU as it is explicitly
3080 * marked as wc by the system, or the system is cache-coherent.
3085 /* If the GPU is snooping the contents of the CPU cache,
3086 * we do not need to manually clear the CPU cache lines. However,
3087 * the caches are only snooped when the render cache is
3088 * flushed/invalidated. As we always have to emit invalidations
3089 * and flushes when moving into and out of the RENDER domain, correct
3090 * snooping behaviour occurs naturally as the result of our domain
3093 if (obj->cache_level != I915_CACHE_NONE)
3096 trace_i915_gem_object_clflush(obj);
3098 drm_clflush_sg(obj->pages);
3101 /** Flushes the GTT write domain for the object if it's dirty. */
3103 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3105 uint32_t old_write_domain;
3107 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3110 /* No actual flushing is required for the GTT write domain. Writes
3111 * to it immediately go to main memory as far as we know, so there's
3112 * no chipset flush. It also doesn't land in render cache.
3114 * However, we do have to enforce the order so that all writes through
3115 * the GTT land before any writes to the device, such as updates to
3120 old_write_domain = obj->base.write_domain;
3121 obj->base.write_domain = 0;
3123 trace_i915_gem_object_change_domain(obj,
3124 obj->base.read_domains,
3128 /** Flushes the CPU write domain for the object if it's dirty. */
3130 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3132 uint32_t old_write_domain;
3134 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3137 i915_gem_clflush_object(obj);
3138 i915_gem_chipset_flush(obj->base.dev);
3139 old_write_domain = obj->base.write_domain;
3140 obj->base.write_domain = 0;
3142 trace_i915_gem_object_change_domain(obj,
3143 obj->base.read_domains,
3148 * Moves a single object to the GTT read, and possibly write domain.
3150 * This function returns when the move is complete, including waiting on
3154 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3156 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3157 uint32_t old_write_domain, old_read_domains;
3160 /* Not valid to be called on unbound objects. */
3161 if (obj->gtt_space == NULL)
3164 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3167 ret = i915_gem_object_wait_rendering(obj, !write);
3171 i915_gem_object_flush_cpu_write_domain(obj);
3173 /* Serialise direct access to this object with the barriers for
3174 * coherent writes from the GPU, by effectively invalidating the
3175 * GTT domain upon first access.
3177 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3180 old_write_domain = obj->base.write_domain;
3181 old_read_domains = obj->base.read_domains;
3183 /* It should now be out of any other write domains, and we can update
3184 * the domain values for our changes.
3186 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3187 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3189 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3190 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3194 trace_i915_gem_object_change_domain(obj,
3198 /* And bump the LRU for this access */
3199 if (i915_gem_object_is_inactive(obj))
3200 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3205 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3206 enum i915_cache_level cache_level)
3208 struct drm_device *dev = obj->base.dev;
3209 drm_i915_private_t *dev_priv = dev->dev_private;
3212 if (obj->cache_level == cache_level)
3215 if (obj->pin_count) {
3216 DRM_DEBUG("can not change the cache level of pinned objects\n");
3220 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3221 ret = i915_gem_object_unbind(obj);
3226 if (obj->gtt_space) {
3227 ret = i915_gem_object_finish_gpu(obj);
3231 i915_gem_object_finish_gtt(obj);
3233 /* Before SandyBridge, you could not use tiling or fence
3234 * registers with snooped memory, so relinquish any fences
3235 * currently pointing to our region in the aperture.
3237 if (INTEL_INFO(dev)->gen < 6) {
3238 ret = i915_gem_object_put_fence(obj);
3243 if (obj->has_global_gtt_mapping)
3244 i915_gem_gtt_bind_object(obj, cache_level);
3245 if (obj->has_aliasing_ppgtt_mapping)
3246 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3249 obj->gtt_space->color = cache_level;
3252 if (cache_level == I915_CACHE_NONE) {
3253 u32 old_read_domains, old_write_domain;
3255 /* If we're coming from LLC cached, then we haven't
3256 * actually been tracking whether the data is in the
3257 * CPU cache or not, since we only allow one bit set
3258 * in obj->write_domain and have been skipping the clflushes.
3259 * Just set it to the CPU cache for now.
3261 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3262 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3264 old_read_domains = obj->base.read_domains;
3265 old_write_domain = obj->base.write_domain;
3267 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3268 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3270 trace_i915_gem_object_change_domain(obj,
3275 obj->cache_level = cache_level;
3276 i915_gem_verify_gtt(dev);
3280 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3281 struct drm_file *file)
3283 struct drm_i915_gem_caching *args = data;
3284 struct drm_i915_gem_object *obj;
3287 ret = i915_mutex_lock_interruptible(dev);
3291 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3292 if (&obj->base == NULL) {
3297 args->caching = obj->cache_level != I915_CACHE_NONE;
3299 drm_gem_object_unreference(&obj->base);
3301 mutex_unlock(&dev->struct_mutex);
3305 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3306 struct drm_file *file)
3308 struct drm_i915_gem_caching *args = data;
3309 struct drm_i915_gem_object *obj;
3310 enum i915_cache_level level;
3313 switch (args->caching) {
3314 case I915_CACHING_NONE:
3315 level = I915_CACHE_NONE;
3317 case I915_CACHING_CACHED:
3318 level = I915_CACHE_LLC;
3324 ret = i915_mutex_lock_interruptible(dev);
3328 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3329 if (&obj->base == NULL) {
3334 ret = i915_gem_object_set_cache_level(obj, level);
3336 drm_gem_object_unreference(&obj->base);
3338 mutex_unlock(&dev->struct_mutex);
3343 * Prepare buffer for display plane (scanout, cursors, etc).
3344 * Can be called from an uninterruptible phase (modesetting) and allows
3345 * any flushes to be pipelined (for pageflips).
3348 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3350 struct intel_ring_buffer *pipelined)
3352 u32 old_read_domains, old_write_domain;
3355 if (pipelined != obj->ring) {
3356 ret = i915_gem_object_sync(obj, pipelined);
3361 /* The display engine is not coherent with the LLC cache on gen6. As
3362 * a result, we make sure that the pinning that is about to occur is
3363 * done with uncached PTEs. This is lowest common denominator for all
3366 * However for gen6+, we could do better by using the GFDT bit instead
3367 * of uncaching, which would allow us to flush all the LLC-cached data
3368 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3370 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3374 /* As the user may map the buffer once pinned in the display plane
3375 * (e.g. libkms for the bootup splash), we have to ensure that we
3376 * always use map_and_fenceable for all scanout buffers.
3378 ret = i915_gem_object_pin(obj, alignment, true, false);
3382 i915_gem_object_flush_cpu_write_domain(obj);
3384 old_write_domain = obj->base.write_domain;
3385 old_read_domains = obj->base.read_domains;
3387 /* It should now be out of any other write domains, and we can update
3388 * the domain values for our changes.
3390 obj->base.write_domain = 0;
3391 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3393 trace_i915_gem_object_change_domain(obj,
3401 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3405 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3408 ret = i915_gem_object_wait_rendering(obj, false);
3412 /* Ensure that we invalidate the GPU's caches and TLBs. */
3413 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3418 * Moves a single object to the CPU read, and possibly write domain.
3420 * This function returns when the move is complete, including waiting on
3424 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3426 uint32_t old_write_domain, old_read_domains;
3429 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3432 ret = i915_gem_object_wait_rendering(obj, !write);
3436 i915_gem_object_flush_gtt_write_domain(obj);
3438 old_write_domain = obj->base.write_domain;
3439 old_read_domains = obj->base.read_domains;
3441 /* Flush the CPU cache if it's still invalid. */
3442 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3443 i915_gem_clflush_object(obj);
3445 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3448 /* It should now be out of any other write domains, and we can update
3449 * the domain values for our changes.
3451 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3453 /* If we're writing through the CPU, then the GPU read domains will
3454 * need to be invalidated at next use.
3457 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3458 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3461 trace_i915_gem_object_change_domain(obj,
3468 /* Throttle our rendering by waiting until the ring has completed our requests
3469 * emitted over 20 msec ago.
3471 * Note that if we were to use the current jiffies each time around the loop,
3472 * we wouldn't escape the function with any frames outstanding if the time to
3473 * render a frame was over 20ms.
3475 * This should get us reasonable parallelism between CPU and GPU but also
3476 * relatively low latency when blocking on a particular request to finish.
3479 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 struct drm_i915_file_private *file_priv = file->driver_priv;
3483 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3484 struct drm_i915_gem_request *request;
3485 struct intel_ring_buffer *ring = NULL;
3486 unsigned reset_counter;
3490 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3494 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3498 spin_lock(&file_priv->mm.lock);
3499 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3500 if (time_after_eq(request->emitted_jiffies, recent_enough))
3503 ring = request->ring;
3504 seqno = request->seqno;
3506 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3507 spin_unlock(&file_priv->mm.lock);
3512 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3514 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3520 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3522 bool map_and_fenceable,
3527 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3530 if (obj->gtt_space != NULL) {
3531 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3532 (map_and_fenceable && !obj->map_and_fenceable)) {
3533 WARN(obj->pin_count,
3534 "bo is already pinned with incorrect alignment:"
3535 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3536 " obj->map_and_fenceable=%d\n",
3537 obj->gtt_offset, alignment,
3539 obj->map_and_fenceable);
3540 ret = i915_gem_object_unbind(obj);
3546 if (obj->gtt_space == NULL) {
3547 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3549 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3555 if (!dev_priv->mm.aliasing_ppgtt)
3556 i915_gem_gtt_bind_object(obj, obj->cache_level);
3559 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3560 i915_gem_gtt_bind_object(obj, obj->cache_level);
3563 obj->pin_mappable |= map_and_fenceable;
3569 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3571 BUG_ON(obj->pin_count == 0);
3572 BUG_ON(obj->gtt_space == NULL);
3574 if (--obj->pin_count == 0)
3575 obj->pin_mappable = false;
3579 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3580 struct drm_file *file)
3582 struct drm_i915_gem_pin *args = data;
3583 struct drm_i915_gem_object *obj;
3586 ret = i915_mutex_lock_interruptible(dev);
3590 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3591 if (&obj->base == NULL) {
3596 if (obj->madv != I915_MADV_WILLNEED) {
3597 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3602 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3603 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3609 if (obj->user_pin_count == 0) {
3610 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3615 obj->user_pin_count++;
3616 obj->pin_filp = file;
3618 /* XXX - flush the CPU caches for pinned objects
3619 * as the X server doesn't manage domains yet
3621 i915_gem_object_flush_cpu_write_domain(obj);
3622 args->offset = obj->gtt_offset;
3624 drm_gem_object_unreference(&obj->base);
3626 mutex_unlock(&dev->struct_mutex);
3631 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3632 struct drm_file *file)
3634 struct drm_i915_gem_pin *args = data;
3635 struct drm_i915_gem_object *obj;
3638 ret = i915_mutex_lock_interruptible(dev);
3642 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3643 if (&obj->base == NULL) {
3648 if (obj->pin_filp != file) {
3649 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3654 obj->user_pin_count--;
3655 if (obj->user_pin_count == 0) {
3656 obj->pin_filp = NULL;
3657 i915_gem_object_unpin(obj);
3661 drm_gem_object_unreference(&obj->base);
3663 mutex_unlock(&dev->struct_mutex);
3668 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3669 struct drm_file *file)
3671 struct drm_i915_gem_busy *args = data;
3672 struct drm_i915_gem_object *obj;
3675 ret = i915_mutex_lock_interruptible(dev);
3679 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3680 if (&obj->base == NULL) {
3685 /* Count all active objects as busy, even if they are currently not used
3686 * by the gpu. Users of this interface expect objects to eventually
3687 * become non-busy without any further actions, therefore emit any
3688 * necessary flushes here.
3690 ret = i915_gem_object_flush_active(obj);
3692 args->busy = obj->active;
3694 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3695 args->busy |= intel_ring_flag(obj->ring) << 16;
3698 drm_gem_object_unreference(&obj->base);
3700 mutex_unlock(&dev->struct_mutex);
3705 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3706 struct drm_file *file_priv)
3708 return i915_gem_ring_throttle(dev, file_priv);
3712 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3713 struct drm_file *file_priv)
3715 struct drm_i915_gem_madvise *args = data;
3716 struct drm_i915_gem_object *obj;
3719 switch (args->madv) {
3720 case I915_MADV_DONTNEED:
3721 case I915_MADV_WILLNEED:
3727 ret = i915_mutex_lock_interruptible(dev);
3731 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3732 if (&obj->base == NULL) {
3737 if (obj->pin_count) {
3742 if (obj->madv != __I915_MADV_PURGED)
3743 obj->madv = args->madv;
3745 /* if the object is no longer attached, discard its backing storage */
3746 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3747 i915_gem_object_truncate(obj);
3749 args->retained = obj->madv != __I915_MADV_PURGED;
3752 drm_gem_object_unreference(&obj->base);
3754 mutex_unlock(&dev->struct_mutex);
3758 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3759 const struct drm_i915_gem_object_ops *ops)
3761 INIT_LIST_HEAD(&obj->mm_list);
3762 INIT_LIST_HEAD(&obj->gtt_list);
3763 INIT_LIST_HEAD(&obj->ring_list);
3764 INIT_LIST_HEAD(&obj->exec_list);
3768 obj->fence_reg = I915_FENCE_REG_NONE;
3769 obj->madv = I915_MADV_WILLNEED;
3770 /* Avoid an unnecessary call to unbind on the first bind. */
3771 obj->map_and_fenceable = true;
3773 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3776 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3777 .get_pages = i915_gem_object_get_pages_gtt,
3778 .put_pages = i915_gem_object_put_pages_gtt,
3781 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3784 struct drm_i915_gem_object *obj;
3785 struct address_space *mapping;
3788 obj = i915_gem_object_alloc(dev);
3792 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3793 i915_gem_object_free(obj);
3797 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3798 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3799 /* 965gm cannot relocate objects above 4GiB. */
3800 mask &= ~__GFP_HIGHMEM;
3801 mask |= __GFP_DMA32;
3804 mapping = file_inode(obj->base.filp)->i_mapping;
3805 mapping_set_gfp_mask(mapping, mask);
3807 i915_gem_object_init(obj, &i915_gem_object_ops);
3809 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3810 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3813 /* On some devices, we can have the GPU use the LLC (the CPU
3814 * cache) for about a 10% performance improvement
3815 * compared to uncached. Graphics requests other than
3816 * display scanout are coherent with the CPU in
3817 * accessing this cache. This means in this mode we
3818 * don't need to clflush on the CPU side, and on the
3819 * GPU side we only need to flush internal caches to
3820 * get data visible to the CPU.
3822 * However, we maintain the display planes as UC, and so
3823 * need to rebind when first used as such.
3825 obj->cache_level = I915_CACHE_LLC;
3827 obj->cache_level = I915_CACHE_NONE;
3832 int i915_gem_init_object(struct drm_gem_object *obj)
3839 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3841 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3842 struct drm_device *dev = obj->base.dev;
3843 drm_i915_private_t *dev_priv = dev->dev_private;
3845 trace_i915_gem_object_destroy(obj);
3848 i915_gem_detach_phys_object(dev, obj);
3851 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3852 bool was_interruptible;
3854 was_interruptible = dev_priv->mm.interruptible;
3855 dev_priv->mm.interruptible = false;
3857 WARN_ON(i915_gem_object_unbind(obj));
3859 dev_priv->mm.interruptible = was_interruptible;
3862 obj->pages_pin_count = 0;
3863 i915_gem_object_put_pages(obj);
3864 i915_gem_object_free_mmap_offset(obj);
3865 i915_gem_object_release_stolen(obj);
3869 if (obj->base.import_attach)
3870 drm_prime_gem_destroy(&obj->base, NULL);
3872 drm_gem_object_release(&obj->base);
3873 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3876 i915_gem_object_free(obj);
3880 i915_gem_idle(struct drm_device *dev)
3882 drm_i915_private_t *dev_priv = dev->dev_private;
3885 mutex_lock(&dev->struct_mutex);
3887 if (dev_priv->mm.suspended) {
3888 mutex_unlock(&dev->struct_mutex);
3892 ret = i915_gpu_idle(dev);
3894 mutex_unlock(&dev->struct_mutex);
3897 i915_gem_retire_requests(dev);
3899 /* Under UMS, be paranoid and evict. */
3900 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3901 i915_gem_evict_everything(dev);
3903 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3904 * We need to replace this with a semaphore, or something.
3905 * And not confound mm.suspended!
3907 dev_priv->mm.suspended = 1;
3908 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
3910 i915_kernel_lost_context(dev);
3911 i915_gem_cleanup_ringbuffer(dev);
3913 mutex_unlock(&dev->struct_mutex);
3915 /* Cancel the retire work handler, which should be idle now. */
3916 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3921 void i915_gem_l3_remap(struct drm_device *dev)
3923 drm_i915_private_t *dev_priv = dev->dev_private;
3927 if (!HAS_L3_GPU_CACHE(dev))
3930 if (!dev_priv->l3_parity.remap_info)
3933 misccpctl = I915_READ(GEN7_MISCCPCTL);
3934 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3935 POSTING_READ(GEN7_MISCCPCTL);
3937 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3938 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3939 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3940 DRM_DEBUG("0x%x was already programmed to %x\n",
3941 GEN7_L3LOG_BASE + i, remap);
3942 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3943 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3944 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3947 /* Make sure all the writes land before disabling dop clock gating */
3948 POSTING_READ(GEN7_L3LOG_BASE);
3950 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3953 void i915_gem_init_swizzling(struct drm_device *dev)
3955 drm_i915_private_t *dev_priv = dev->dev_private;
3957 if (INTEL_INFO(dev)->gen < 5 ||
3958 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3961 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3962 DISP_TILE_SURFACE_SWIZZLING);
3967 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3969 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3970 else if (IS_GEN7(dev))
3971 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3977 intel_enable_blt(struct drm_device *dev)
3982 /* The blitter was dysfunctional on early prototypes */
3983 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3984 DRM_INFO("BLT not supported on this pre-production hardware;"
3985 " graphics performance will be degraded.\n");
3992 static int i915_gem_init_rings(struct drm_device *dev)
3994 struct drm_i915_private *dev_priv = dev->dev_private;
3997 ret = intel_init_render_ring_buffer(dev);
4002 ret = intel_init_bsd_ring_buffer(dev);
4004 goto cleanup_render_ring;
4007 if (intel_enable_blt(dev)) {
4008 ret = intel_init_blt_ring_buffer(dev);
4010 goto cleanup_bsd_ring;
4013 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4015 goto cleanup_blt_ring;
4020 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4022 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4023 cleanup_render_ring:
4024 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4030 i915_gem_init_hw(struct drm_device *dev)
4032 drm_i915_private_t *dev_priv = dev->dev_private;
4035 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4038 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4039 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4041 if (HAS_PCH_NOP(dev)) {
4042 u32 temp = I915_READ(GEN7_MSG_CTL);
4043 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4044 I915_WRITE(GEN7_MSG_CTL, temp);
4047 i915_gem_l3_remap(dev);
4049 i915_gem_init_swizzling(dev);
4051 ret = i915_gem_init_rings(dev);
4056 * XXX: There was some w/a described somewhere suggesting loading
4057 * contexts before PPGTT.
4059 i915_gem_context_init(dev);
4060 if (dev_priv->mm.aliasing_ppgtt) {
4061 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4063 i915_gem_cleanup_aliasing_ppgtt(dev);
4064 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4071 int i915_gem_init(struct drm_device *dev)
4073 struct drm_i915_private *dev_priv = dev->dev_private;
4076 mutex_lock(&dev->struct_mutex);
4078 if (IS_VALLEYVIEW(dev)) {
4079 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4080 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4081 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4082 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4085 i915_gem_init_global_gtt(dev);
4087 ret = i915_gem_init_hw(dev);
4088 mutex_unlock(&dev->struct_mutex);
4090 i915_gem_cleanup_aliasing_ppgtt(dev);
4094 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4095 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4096 dev_priv->dri1.allow_batchbuffer = 1;
4101 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4103 drm_i915_private_t *dev_priv = dev->dev_private;
4104 struct intel_ring_buffer *ring;
4107 for_each_ring(ring, dev_priv, i)
4108 intel_cleanup_ring_buffer(ring);
4112 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4113 struct drm_file *file_priv)
4115 drm_i915_private_t *dev_priv = dev->dev_private;
4118 if (drm_core_check_feature(dev, DRIVER_MODESET))
4121 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4122 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4123 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4126 mutex_lock(&dev->struct_mutex);
4127 dev_priv->mm.suspended = 0;
4129 ret = i915_gem_init_hw(dev);
4131 mutex_unlock(&dev->struct_mutex);
4135 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4136 mutex_unlock(&dev->struct_mutex);
4138 ret = drm_irq_install(dev);
4140 goto cleanup_ringbuffer;
4145 mutex_lock(&dev->struct_mutex);
4146 i915_gem_cleanup_ringbuffer(dev);
4147 dev_priv->mm.suspended = 1;
4148 mutex_unlock(&dev->struct_mutex);
4154 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4155 struct drm_file *file_priv)
4157 if (drm_core_check_feature(dev, DRIVER_MODESET))
4160 drm_irq_uninstall(dev);
4161 return i915_gem_idle(dev);
4165 i915_gem_lastclose(struct drm_device *dev)
4169 if (drm_core_check_feature(dev, DRIVER_MODESET))
4172 ret = i915_gem_idle(dev);
4174 DRM_ERROR("failed to idle hardware: %d\n", ret);
4178 init_ring_lists(struct intel_ring_buffer *ring)
4180 INIT_LIST_HEAD(&ring->active_list);
4181 INIT_LIST_HEAD(&ring->request_list);
4185 i915_gem_load(struct drm_device *dev)
4187 drm_i915_private_t *dev_priv = dev->dev_private;
4191 kmem_cache_create("i915_gem_object",
4192 sizeof(struct drm_i915_gem_object), 0,
4196 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4197 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4198 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4199 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4200 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4201 for (i = 0; i < I915_NUM_RINGS; i++)
4202 init_ring_lists(&dev_priv->ring[i]);
4203 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4204 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4205 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4206 i915_gem_retire_work_handler);
4207 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4209 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4211 I915_WRITE(MI_ARB_STATE,
4212 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4215 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4217 /* Old X drivers will take 0-2 for front, back, depth buffers */
4218 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4219 dev_priv->fence_reg_start = 3;
4221 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4222 dev_priv->num_fence_regs = 32;
4223 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4224 dev_priv->num_fence_regs = 16;
4226 dev_priv->num_fence_regs = 8;
4228 /* Initialize fence registers to zero */
4229 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4230 i915_gem_restore_fences(dev);
4232 i915_gem_detect_bit_6_swizzle(dev);
4233 init_waitqueue_head(&dev_priv->pending_flip_queue);
4235 dev_priv->mm.interruptible = true;
4237 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4238 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4239 register_shrinker(&dev_priv->mm.inactive_shrinker);
4243 * Create a physically contiguous memory object for this object
4244 * e.g. for cursor + overlay regs
4246 static int i915_gem_init_phys_object(struct drm_device *dev,
4247 int id, int size, int align)
4249 drm_i915_private_t *dev_priv = dev->dev_private;
4250 struct drm_i915_gem_phys_object *phys_obj;
4253 if (dev_priv->mm.phys_objs[id - 1] || !size)
4256 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4262 phys_obj->handle = drm_pci_alloc(dev, size, align);
4263 if (!phys_obj->handle) {
4268 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4271 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4279 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4281 drm_i915_private_t *dev_priv = dev->dev_private;
4282 struct drm_i915_gem_phys_object *phys_obj;
4284 if (!dev_priv->mm.phys_objs[id - 1])
4287 phys_obj = dev_priv->mm.phys_objs[id - 1];
4288 if (phys_obj->cur_obj) {
4289 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4293 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4295 drm_pci_free(dev, phys_obj->handle);
4297 dev_priv->mm.phys_objs[id - 1] = NULL;
4300 void i915_gem_free_all_phys_object(struct drm_device *dev)
4304 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4305 i915_gem_free_phys_object(dev, i);
4308 void i915_gem_detach_phys_object(struct drm_device *dev,
4309 struct drm_i915_gem_object *obj)
4311 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4318 vaddr = obj->phys_obj->handle->vaddr;
4320 page_count = obj->base.size / PAGE_SIZE;
4321 for (i = 0; i < page_count; i++) {
4322 struct page *page = shmem_read_mapping_page(mapping, i);
4323 if (!IS_ERR(page)) {
4324 char *dst = kmap_atomic(page);
4325 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4328 drm_clflush_pages(&page, 1);
4330 set_page_dirty(page);
4331 mark_page_accessed(page);
4332 page_cache_release(page);
4335 i915_gem_chipset_flush(dev);
4337 obj->phys_obj->cur_obj = NULL;
4338 obj->phys_obj = NULL;
4342 i915_gem_attach_phys_object(struct drm_device *dev,
4343 struct drm_i915_gem_object *obj,
4347 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4348 drm_i915_private_t *dev_priv = dev->dev_private;
4353 if (id > I915_MAX_PHYS_OBJECT)
4356 if (obj->phys_obj) {
4357 if (obj->phys_obj->id == id)
4359 i915_gem_detach_phys_object(dev, obj);
4362 /* create a new object */
4363 if (!dev_priv->mm.phys_objs[id - 1]) {
4364 ret = i915_gem_init_phys_object(dev, id,
4365 obj->base.size, align);
4367 DRM_ERROR("failed to init phys object %d size: %zu\n",
4368 id, obj->base.size);
4373 /* bind to the object */
4374 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4375 obj->phys_obj->cur_obj = obj;
4377 page_count = obj->base.size / PAGE_SIZE;
4379 for (i = 0; i < page_count; i++) {
4383 page = shmem_read_mapping_page(mapping, i);
4385 return PTR_ERR(page);
4387 src = kmap_atomic(page);
4388 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4389 memcpy(dst, src, PAGE_SIZE);
4392 mark_page_accessed(page);
4393 page_cache_release(page);
4400 i915_gem_phys_pwrite(struct drm_device *dev,
4401 struct drm_i915_gem_object *obj,
4402 struct drm_i915_gem_pwrite *args,
4403 struct drm_file *file_priv)
4405 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4406 char __user *user_data = to_user_ptr(args->data_ptr);
4408 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4409 unsigned long unwritten;
4411 /* The physical object once assigned is fixed for the lifetime
4412 * of the obj, so we can safely drop the lock and continue
4415 mutex_unlock(&dev->struct_mutex);
4416 unwritten = copy_from_user(vaddr, user_data, args->size);
4417 mutex_lock(&dev->struct_mutex);
4422 i915_gem_chipset_flush(dev);
4426 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4428 struct drm_i915_file_private *file_priv = file->driver_priv;
4430 /* Clean up our request list when the client is going away, so that
4431 * later retire_requests won't dereference our soon-to-be-gone
4434 spin_lock(&file_priv->mm.lock);
4435 while (!list_empty(&file_priv->mm.request_list)) {
4436 struct drm_i915_gem_request *request;
4438 request = list_first_entry(&file_priv->mm.request_list,
4439 struct drm_i915_gem_request,
4441 list_del(&request->client_list);
4442 request->file_priv = NULL;
4444 spin_unlock(&file_priv->mm.lock);
4447 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4449 if (!mutex_is_locked(mutex))
4452 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4453 return mutex->owner == task;
4455 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4461 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4463 struct drm_i915_private *dev_priv =
4464 container_of(shrinker,
4465 struct drm_i915_private,
4466 mm.inactive_shrinker);
4467 struct drm_device *dev = dev_priv->dev;
4468 struct drm_i915_gem_object *obj;
4469 int nr_to_scan = sc->nr_to_scan;
4473 if (!mutex_trylock(&dev->struct_mutex)) {
4474 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4477 if (dev_priv->mm.shrinker_no_lock_stealing)
4484 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4486 nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4489 i915_gem_shrink_all(dev_priv);
4493 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4494 if (obj->pages_pin_count == 0)
4495 cnt += obj->base.size >> PAGE_SHIFT;
4496 list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list)
4497 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4498 cnt += obj->base.size >> PAGE_SHIFT;
4501 mutex_unlock(&dev->struct_mutex);