1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
40 /* General customization:
43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45 #define DRIVER_NAME "i915"
46 #define DRIVER_DESC "Intel Graphics"
47 #define DRIVER_DATE "20080730"
59 #define I915_NUM_PIPE 2
61 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66 * 1.2: Add Power Management
67 * 1.3: Add vblank support
68 * 1.4: Fix cmdbuffer path, add heap destroy
69 * 1.5: Add vblank pipe configuration
70 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
71 * - Support vertical blank on secondary display pipe
73 #define DRIVER_MAJOR 1
74 #define DRIVER_MINOR 6
75 #define DRIVER_PATCHLEVEL 0
77 #define WATCH_COHERENCY 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object {
90 struct page **page_list;
91 drm_dma_handle_t *handle;
92 struct drm_i915_gem_object *cur_obj;
96 struct mem_block *next;
97 struct mem_block *prev;
100 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
103 struct opregion_header;
104 struct opregion_acpi;
105 struct opregion_swsci;
106 struct opregion_asle;
108 struct intel_opregion {
109 struct opregion_header *header;
110 struct opregion_acpi *acpi;
111 struct opregion_swsci *swsci;
112 struct opregion_asle *asle;
115 #define OPREGION_SIZE (8*1024)
117 struct intel_overlay;
118 struct intel_overlay_error_state;
120 struct drm_i915_master_private {
121 drm_local_map_t *sarea;
122 struct _drm_i915_sarea *sarea_priv;
124 #define I915_FENCE_REG_NONE -1
126 struct drm_i915_fence_reg {
127 struct list_head lru_list;
128 struct drm_i915_gem_object *obj;
129 uint32_t setup_seqno;
132 struct sdvo_device_mapping {
142 struct intel_display_error_state;
144 struct drm_i915_error_state {
153 u32 error; /* gen6+ */
154 u32 bcs_acthd; /* gen6+ blt engine */
159 u32 vcs_acthd; /* gen6+ bsd engine */
171 struct drm_i915_error_object {
175 } *ringbuffer, *batchbuffer[I915_NUM_RINGS];
176 struct drm_i915_error_buffer {
190 } *active_bo, *pinned_bo;
191 u32 active_bo_count, pinned_bo_count;
192 struct intel_overlay_error_state *overlay;
193 struct intel_display_error_state *display;
196 struct drm_i915_display_funcs {
197 void (*dpms)(struct drm_crtc *crtc, int mode);
198 bool (*fbc_enabled)(struct drm_device *dev);
199 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
200 void (*disable_fbc)(struct drm_device *dev);
201 int (*get_display_clock_speed)(struct drm_device *dev);
202 int (*get_fifo_size)(struct drm_device *dev, int plane);
203 void (*update_wm)(struct drm_device *dev, int planea_clock,
204 int planeb_clock, int sr_hdisplay, int sr_htotal,
206 /* clock updates for mode set */
208 /* render clock increase/decrease */
209 /* display clock increase/decrease */
210 /* pll clock increase/decrease */
211 /* clock gating init */
214 struct intel_device_info {
224 u8 is_broadwater : 1;
227 u8 has_pipe_cxsr : 1;
229 u8 cursor_needs_physical : 1;
231 u8 overlay_needs_physical : 1;
238 FBC_NO_OUTPUT, /* no outputs enabled to compress */
239 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
240 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
241 FBC_MODE_TOO_LARGE, /* mode too large for compression */
242 FBC_BAD_PLANE, /* fbc not supported on plane */
243 FBC_NOT_TILED, /* buffer not tiled */
244 FBC_MULTIPLE_PIPES, /* more than one pipe active */
248 PCH_IBX, /* Ibexpeak PCH */
249 PCH_CPT, /* Cougarpoint PCH */
252 #define QUIRK_PIPEA_FORCE (1<<0)
256 typedef struct drm_i915_private {
257 struct drm_device *dev;
259 const struct intel_device_info *info;
262 int relative_constants_mode;
267 struct i2c_adapter adapter;
268 struct i2c_adapter *force_bit;
272 struct pci_dev *bridge_dev;
273 struct intel_ring_buffer ring[I915_NUM_RINGS];
276 drm_dma_handle_t *status_page_dmah;
277 dma_addr_t dma_status_page;
279 drm_local_map_t hws_map;
280 struct drm_i915_gem_object *pwrctx;
281 struct drm_i915_gem_object *renderctx;
283 struct resource mch_res;
291 atomic_t irq_received;
294 /* protects the irq masks */
296 /** Cached value of IMR to avoid reads in updating the bitfield */
302 u32 hotplug_supported_mask;
303 struct work_struct hotplug_work;
305 int tex_lru_log_granularity;
306 int allow_batchbuffer;
307 struct mem_block *agp_heap;
308 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
312 /* For hangcheck timer */
313 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
314 struct timer_list hangcheck_timer;
317 uint32_t last_instdone;
318 uint32_t last_instdone1;
320 unsigned long cfb_size;
321 unsigned long cfb_pitch;
322 unsigned long cfb_offset;
329 struct intel_opregion opregion;
332 struct intel_overlay *overlay;
335 int backlight_level; /* restore backlight to this value */
336 bool backlight_enabled;
337 struct drm_display_mode *panel_fixed_mode;
338 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
339 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
341 /* Feature bits from the VBIOS */
342 unsigned int int_tv_support:1;
343 unsigned int lvds_dither:1;
344 unsigned int lvds_vbt:1;
345 unsigned int int_crt_support:1;
346 unsigned int lvds_use_ssc:1;
357 struct edp_power_seq pps;
359 bool no_aux_handshake;
361 struct notifier_block lid_notifier;
364 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
365 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
366 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
368 unsigned int fsb_freq, mem_freq, is_ddr3;
370 spinlock_t error_lock;
371 struct drm_i915_error_state *first_error;
372 struct work_struct error_work;
373 struct completion error_completion;
374 struct workqueue_struct *wq;
376 /* Display functions */
377 struct drm_i915_display_funcs display;
379 /* PCH chipset type */
380 enum intel_pch pch_type;
382 unsigned long quirks;
407 u32 saveTRANS_HTOTAL_A;
408 u32 saveTRANS_HBLANK_A;
409 u32 saveTRANS_HSYNC_A;
410 u32 saveTRANS_VTOTAL_A;
411 u32 saveTRANS_VBLANK_A;
412 u32 saveTRANS_VSYNC_A;
420 u32 savePFIT_PGM_RATIOS;
421 u32 saveBLC_HIST_CTL;
423 u32 saveBLC_PWM_CTL2;
424 u32 saveBLC_CPU_PWM_CTL;
425 u32 saveBLC_CPU_PWM_CTL2;
438 u32 saveTRANS_HTOTAL_B;
439 u32 saveTRANS_HBLANK_B;
440 u32 saveTRANS_HSYNC_B;
441 u32 saveTRANS_VTOTAL_B;
442 u32 saveTRANS_VBLANK_B;
443 u32 saveTRANS_VSYNC_B;
457 u32 savePP_ON_DELAYS;
458 u32 savePP_OFF_DELAYS;
466 u32 savePFIT_CONTROL;
467 u32 save_palette_a[256];
468 u32 save_palette_b[256];
469 u32 saveDPFC_CB_BASE;
470 u32 saveFBC_CFB_BASE;
473 u32 saveFBC_CONTROL2;
483 u32 saveCACHE_MODE_0;
484 u32 saveMI_ARB_STATE;
495 uint64_t saveFENCE[16];
506 u32 savePIPEA_GMCH_DATA_M;
507 u32 savePIPEB_GMCH_DATA_M;
508 u32 savePIPEA_GMCH_DATA_N;
509 u32 savePIPEB_GMCH_DATA_N;
510 u32 savePIPEA_DP_LINK_M;
511 u32 savePIPEB_DP_LINK_M;
512 u32 savePIPEA_DP_LINK_N;
513 u32 savePIPEB_DP_LINK_N;
524 u32 savePCH_DREF_CONTROL;
525 u32 saveDISP_ARB_CTL;
526 u32 savePIPEA_DATA_M1;
527 u32 savePIPEA_DATA_N1;
528 u32 savePIPEA_LINK_M1;
529 u32 savePIPEA_LINK_N1;
530 u32 savePIPEB_DATA_M1;
531 u32 savePIPEB_DATA_N1;
532 u32 savePIPEB_LINK_M1;
533 u32 savePIPEB_LINK_N1;
534 u32 saveMCHBAR_RENDER_STANDBY;
537 /** Bridge to intel-gtt-ko */
538 const struct intel_gtt *gtt;
539 /** Memory allocator for GTT stolen memory */
540 struct drm_mm stolen;
541 /** Memory allocator for GTT */
542 struct drm_mm gtt_space;
543 /** List of all objects in gtt_space. Used to restore gtt
544 * mappings on resume */
545 struct list_head gtt_list;
547 /** Usable portion of the GTT for GEM */
548 unsigned long gtt_start;
549 unsigned long gtt_mappable_end;
550 unsigned long gtt_end;
552 struct io_mapping *gtt_mapping;
555 struct shrinker inactive_shrinker;
558 * List of objects currently involved in rendering.
560 * Includes buffers having the contents of their GPU caches
561 * flushed, not necessarily primitives. last_rendering_seqno
562 * represents when the rendering involved will be completed.
564 * A reference is held on the buffer while on this list.
566 struct list_head active_list;
569 * List of objects which are not in the ringbuffer but which
570 * still have a write_domain which needs to be flushed before
573 * last_rendering_seqno is 0 while an object is in this list.
575 * A reference is held on the buffer while on this list.
577 struct list_head flushing_list;
580 * LRU list of objects which are not in the ringbuffer and
581 * are ready to unbind, but are still in the GTT.
583 * last_rendering_seqno is 0 while an object is in this list.
585 * A reference is not held on the buffer while on this list,
586 * as merely being GTT-bound shouldn't prevent its being
587 * freed, and we'll pull it off the list in the free path.
589 struct list_head inactive_list;
592 * LRU list of objects which are not in the ringbuffer but
593 * are still pinned in the GTT.
595 struct list_head pinned_list;
597 /** LRU list of objects with fence regs on them. */
598 struct list_head fence_list;
601 * List of objects currently pending being freed.
603 * These objects are no longer in use, but due to a signal
604 * we were prevented from freeing them at the appointed time.
606 struct list_head deferred_free_list;
609 * We leave the user IRQ off as much as possible,
610 * but this means that requests will finish and never
611 * be retired once the system goes idle. Set a timer to
612 * fire periodically while the ring is running. When it
613 * fires, go retire requests.
615 struct delayed_work retire_work;
618 * Flag if the X Server, and thus DRM, is not currently in
619 * control of the device.
621 * This is set between LeaveVT and EnterVT. It needs to be
622 * replaced with a semaphore. It also needs to be
623 * transitioned away from for kernel modesetting.
628 * Flag if the hardware appears to be wedged.
630 * This is set when attempts to idle the device timeout.
631 * It prevents command submission from occuring and makes
632 * every pending request fail
636 /** Bit 6 swizzling required for X tiling */
637 uint32_t bit_6_swizzle_x;
638 /** Bit 6 swizzling required for Y tiling */
639 uint32_t bit_6_swizzle_y;
641 /* storage for physical objects */
642 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
644 /* accounting, useful for userland debugging */
646 size_t mappable_gtt_total;
647 size_t object_memory;
650 struct sdvo_device_mapping sdvo_mappings[2];
651 /* indicate whether the LVDS_BORDER should be enabled or not */
652 unsigned int lvds_border_bits;
653 /* Panel fitter placement and size for Ironlake+ */
654 u32 pch_pf_pos, pch_pf_size;
656 struct drm_crtc *plane_to_crtc_mapping[2];
657 struct drm_crtc *pipe_to_crtc_mapping[2];
658 wait_queue_head_t pending_flip_queue;
659 bool flip_pending_is_done;
661 /* Reclocking support */
662 bool render_reclock_avail;
663 bool lvds_downclock_avail;
664 /* indicates the reduced downclock for LVDS*/
666 struct work_struct idle_work;
667 struct timer_list idle_timer;
671 struct child_device_config *child_dev;
672 struct drm_connector *int_lvds_connector;
674 bool mchbar_need_disable;
683 unsigned long last_time1;
685 struct timespec last_time2;
686 unsigned long gfx_power;
690 spinlock_t *mchdev_lock;
692 enum no_fbc_reason no_fbc_reason;
694 struct drm_mm_node *compressed_fb;
695 struct drm_mm_node *compressed_llb;
697 unsigned long last_gpu_reset;
699 /* list of fbdev register on this device */
700 struct intel_fbdev *fbdev;
701 } drm_i915_private_t;
703 struct drm_i915_gem_object {
704 struct drm_gem_object base;
706 /** Current space allocated to this object in the GTT, if any. */
707 struct drm_mm_node *gtt_space;
708 struct list_head gtt_list;
710 /** This object's place on the active/flushing/inactive lists */
711 struct list_head ring_list;
712 struct list_head mm_list;
713 /** This object's place on GPU write list */
714 struct list_head gpu_write_list;
715 /** This object's place in the batchbuffer or on the eviction list */
716 struct list_head exec_list;
719 * This is set if the object is on the active or flushing lists
720 * (has pending rendering), and is not set if it's on inactive (ready
723 unsigned int active : 1;
726 * This is set if the object has been written to since last bound
729 unsigned int dirty : 1;
732 * This is set if the object has been written to since the last
735 unsigned int pending_gpu_write : 1;
738 * Fence register bits (if any) for this object. Will be set
739 * as needed when mapped into the GTT.
740 * Protected by dev->struct_mutex.
742 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
744 signed int fence_reg : 5;
747 * Advice: are the backing pages purgeable?
749 unsigned int madv : 2;
752 * Current tiling mode for the object.
754 unsigned int tiling_mode : 2;
755 unsigned int tiling_changed : 1;
757 /** How many users have pinned this object in GTT space. The following
758 * users can each hold at most one reference: pwrite/pread, pin_ioctl
759 * (via user_pin_count), execbuffer (objects are not allowed multiple
760 * times for the same batchbuffer), and the framebuffer code. When
761 * switching/pageflipping, the framebuffer code has at most two buffers
764 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
765 * bits with absolutely no headroom. So use 4 bits. */
766 unsigned int pin_count : 4;
767 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
770 * Is the object at the current location in the gtt mappable and
771 * fenceable? Used to avoid costly recalculations.
773 unsigned int map_and_fenceable : 1;
776 * Whether the current gtt mapping needs to be mappable (and isn't just
777 * mappable by accident). Track pin and fault separate for a more
778 * accurate mappable working set.
780 unsigned int fault_mappable : 1;
781 unsigned int pin_mappable : 1;
784 * Is the GPU currently using a fence to access this buffer,
786 unsigned int pending_fenced_gpu_access:1;
787 unsigned int fenced_gpu_access:1;
794 struct scatterlist *sg_list;
798 * Used for performing relocations during execbuffer insertion.
800 struct hlist_node exec_node;
801 unsigned long exec_handle;
802 struct drm_i915_gem_exec_object2 *exec_entry;
805 * Current offset of the object in GTT space.
807 * This is the same as gtt_space->start
811 /** Breadcrumb of last rendering to the buffer. */
812 uint32_t last_rendering_seqno;
813 struct intel_ring_buffer *ring;
815 /** Breadcrumb of last fenced GPU access to the buffer. */
816 uint32_t last_fenced_seqno;
817 struct intel_ring_buffer *last_fenced_ring;
819 /** Current tiling stride for the object, if it's tiled. */
822 /** Record of address bit 17 of each page at last unbind. */
823 unsigned long *bit_17;
825 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
829 * If present, while GEM_DOMAIN_CPU is in the read domain this array
830 * flags which individual pages are valid.
832 uint8_t *page_cpu_valid;
834 /** User space pin count and filp owning the pin */
835 uint32_t user_pin_count;
836 struct drm_file *pin_filp;
838 /** for phy allocated objects */
839 struct drm_i915_gem_phys_object *phys_obj;
842 * Number of crtcs where this object is currently the fb, but
843 * will be page flipped away on the next vblank. When it
844 * reaches 0, dev_priv->pending_flip_queue will be woken up.
846 atomic_t pending_flip;
849 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
852 * Request queue structure.
854 * The request queue allows us to note sequence numbers that have been emitted
855 * and may be associated with active buffers to be retired.
857 * By keeping this list, we can avoid having to do questionable
858 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
859 * an emission time with seqnos for tracking how far ahead of the GPU we are.
861 struct drm_i915_gem_request {
862 /** On Which ring this request was generated */
863 struct intel_ring_buffer *ring;
865 /** GEM sequence number associated with this request. */
868 /** Time at which this request was emitted, in jiffies. */
869 unsigned long emitted_jiffies;
871 /** global list entry for this request */
872 struct list_head list;
874 struct drm_i915_file_private *file_priv;
875 /** file_priv list entry for this request */
876 struct list_head client_list;
879 struct drm_i915_file_private {
881 struct spinlock lock;
882 struct list_head request_list;
886 enum intel_chip_family {
893 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
895 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
896 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
897 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
898 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
899 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
900 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
901 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
902 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
903 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
904 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
905 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
906 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
907 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
908 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
909 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
910 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
911 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
912 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
913 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
915 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
916 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
917 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
918 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
919 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
921 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
922 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
923 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
925 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
926 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
928 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
929 * rows, which changed the alignment requirements and fence programming.
931 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
933 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
934 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
935 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
936 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
937 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
938 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
939 /* dsparb controlled by hw only */
940 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
942 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
943 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
944 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
946 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
947 #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
949 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
950 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
951 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
953 #include "i915_trace.h"
955 extern struct drm_ioctl_desc i915_ioctls[];
956 extern int i915_max_ioctl;
957 extern unsigned int i915_fbpercrtc;
958 extern unsigned int i915_powersave;
959 extern unsigned int i915_lvds_downclock;
960 extern unsigned int i915_panel_use_ssc;
961 extern unsigned int i915_enable_rc6;
963 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
964 extern int i915_resume(struct drm_device *dev);
965 extern void i915_save_display(struct drm_device *dev);
966 extern void i915_restore_display(struct drm_device *dev);
967 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
968 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
971 extern void i915_kernel_lost_context(struct drm_device * dev);
972 extern int i915_driver_load(struct drm_device *, unsigned long flags);
973 extern int i915_driver_unload(struct drm_device *);
974 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
975 extern void i915_driver_lastclose(struct drm_device * dev);
976 extern void i915_driver_preclose(struct drm_device *dev,
977 struct drm_file *file_priv);
978 extern void i915_driver_postclose(struct drm_device *dev,
979 struct drm_file *file_priv);
980 extern int i915_driver_device_is_agp(struct drm_device * dev);
981 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
983 extern int i915_emit_box(struct drm_device *dev,
984 struct drm_clip_rect *box,
986 extern int i915_reset(struct drm_device *dev, u8 flags);
987 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
988 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
989 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
990 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
994 void i915_hangcheck_elapsed(unsigned long data);
995 void i915_handle_error(struct drm_device *dev, bool wedged);
996 extern int i915_irq_emit(struct drm_device *dev, void *data,
997 struct drm_file *file_priv);
998 extern int i915_irq_wait(struct drm_device *dev, void *data,
999 struct drm_file *file_priv);
1000 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
1001 extern void i915_enable_interrupt (struct drm_device *dev);
1003 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
1004 extern void i915_driver_irq_preinstall(struct drm_device * dev);
1005 extern int i915_driver_irq_postinstall(struct drm_device *dev);
1006 extern void i915_driver_irq_uninstall(struct drm_device * dev);
1007 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1008 struct drm_file *file_priv);
1009 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1010 struct drm_file *file_priv);
1011 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
1012 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
1013 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1014 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1015 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1016 struct drm_file *file_priv);
1019 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1022 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1024 void intel_enable_asle (struct drm_device *dev);
1025 int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
1027 struct timeval *vblank_time,
1030 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
1031 int *vpos, int *hpos);
1033 #ifdef CONFIG_DEBUG_FS
1034 extern void i915_destroy_error_state(struct drm_device *dev);
1036 #define i915_destroy_error_state(x)
1041 extern int i915_mem_alloc(struct drm_device *dev, void *data,
1042 struct drm_file *file_priv);
1043 extern int i915_mem_free(struct drm_device *dev, void *data,
1044 struct drm_file *file_priv);
1045 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1046 struct drm_file *file_priv);
1047 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1048 struct drm_file *file_priv);
1049 extern void i915_mem_takedown(struct mem_block **heap);
1050 extern void i915_mem_release(struct drm_device * dev,
1051 struct drm_file *file_priv, struct mem_block *heap);
1053 int i915_gem_check_is_wedged(struct drm_device *dev);
1054 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1055 struct drm_file *file_priv);
1056 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1057 struct drm_file *file_priv);
1058 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1059 struct drm_file *file_priv);
1060 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1061 struct drm_file *file_priv);
1062 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1063 struct drm_file *file_priv);
1064 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1065 struct drm_file *file_priv);
1066 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1067 struct drm_file *file_priv);
1068 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1069 struct drm_file *file_priv);
1070 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1071 struct drm_file *file_priv);
1072 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1073 struct drm_file *file_priv);
1074 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1075 struct drm_file *file_priv);
1076 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1077 struct drm_file *file_priv);
1078 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1079 struct drm_file *file_priv);
1080 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1081 struct drm_file *file_priv);
1082 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1083 struct drm_file *file_priv);
1084 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1085 struct drm_file *file_priv);
1086 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1087 struct drm_file *file_priv);
1088 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1089 struct drm_file *file_priv);
1090 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1091 struct drm_file *file_priv);
1092 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1093 struct drm_file *file_priv);
1094 void i915_gem_load(struct drm_device *dev);
1095 int i915_gem_init_object(struct drm_gem_object *obj);
1096 int __must_check i915_gem_flush_ring(struct drm_device *dev,
1097 struct intel_ring_buffer *ring,
1098 uint32_t invalidate_domains,
1099 uint32_t flush_domains);
1100 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1102 void i915_gem_free_object(struct drm_gem_object *obj);
1103 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1105 bool map_and_fenceable);
1106 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1107 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1108 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1109 void i915_gem_lastclose(struct drm_device *dev);
1111 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1112 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1113 bool interruptible);
1114 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1115 struct intel_ring_buffer *ring,
1119 * Returns true if seq1 is later than seq2.
1122 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1124 return (int32_t)(seq1 - seq2) >= 0;
1128 i915_gem_next_request_seqno(struct drm_device *dev,
1129 struct intel_ring_buffer *ring)
1131 drm_i915_private_t *dev_priv = dev->dev_private;
1132 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1135 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1136 struct intel_ring_buffer *pipelined,
1137 bool interruptible);
1138 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1140 void i915_gem_retire_requests(struct drm_device *dev);
1141 void i915_gem_reset(struct drm_device *dev);
1142 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1143 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1144 uint32_t read_domains,
1145 uint32_t write_domain);
1146 int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
1147 bool interruptible);
1148 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1149 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1150 void i915_gem_do_init(struct drm_device *dev,
1151 unsigned long start,
1152 unsigned long mappable_end,
1154 int __must_check i915_gpu_idle(struct drm_device *dev);
1155 int __must_check i915_gem_idle(struct drm_device *dev);
1156 int __must_check i915_add_request(struct drm_device *dev,
1157 struct drm_file *file_priv,
1158 struct drm_i915_gem_request *request,
1159 struct intel_ring_buffer *ring);
1160 int __must_check i915_do_wait_request(struct drm_device *dev,
1163 struct intel_ring_buffer *ring);
1164 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1166 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1169 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
1170 struct intel_ring_buffer *pipelined);
1171 int i915_gem_attach_phys_object(struct drm_device *dev,
1172 struct drm_i915_gem_object *obj,
1175 void i915_gem_detach_phys_object(struct drm_device *dev,
1176 struct drm_i915_gem_object *obj);
1177 void i915_gem_free_all_phys_object(struct drm_device *dev);
1178 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1180 /* i915_gem_gtt.c */
1181 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1182 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1183 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1185 /* i915_gem_evict.c */
1186 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1187 unsigned alignment, bool mappable);
1188 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1189 bool purgeable_only);
1190 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1191 bool purgeable_only);
1193 /* i915_gem_tiling.c */
1194 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1195 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1196 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1198 /* i915_gem_debug.c */
1199 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1200 const char *where, uint32_t mark);
1202 int i915_verify_lists(struct drm_device *dev);
1204 #define i915_verify_lists(dev) 0
1206 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1208 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1209 const char *where, uint32_t mark);
1211 /* i915_debugfs.c */
1212 int i915_debugfs_init(struct drm_minor *minor);
1213 void i915_debugfs_cleanup(struct drm_minor *minor);
1215 /* i915_suspend.c */
1216 extern int i915_save_state(struct drm_device *dev);
1217 extern int i915_restore_state(struct drm_device *dev);
1219 /* i915_suspend.c */
1220 extern int i915_save_state(struct drm_device *dev);
1221 extern int i915_restore_state(struct drm_device *dev);
1224 extern int intel_setup_gmbus(struct drm_device *dev);
1225 extern void intel_teardown_gmbus(struct drm_device *dev);
1226 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1227 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1228 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1230 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1232 extern void intel_i2c_reset(struct drm_device *dev);
1234 /* intel_opregion.c */
1235 extern int intel_opregion_setup(struct drm_device *dev);
1237 extern void intel_opregion_init(struct drm_device *dev);
1238 extern void intel_opregion_fini(struct drm_device *dev);
1239 extern void intel_opregion_asle_intr(struct drm_device *dev);
1240 extern void intel_opregion_gse_intr(struct drm_device *dev);
1241 extern void intel_opregion_enable_asle(struct drm_device *dev);
1243 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1244 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1245 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1246 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1247 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1252 extern void intel_register_dsm_handler(void);
1253 extern void intel_unregister_dsm_handler(void);
1255 static inline void intel_register_dsm_handler(void) { return; }
1256 static inline void intel_unregister_dsm_handler(void) { return; }
1257 #endif /* CONFIG_ACPI */
1260 extern void intel_modeset_init(struct drm_device *dev);
1261 extern void intel_modeset_cleanup(struct drm_device *dev);
1262 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1263 extern void i8xx_disable_fbc(struct drm_device *dev);
1264 extern void g4x_disable_fbc(struct drm_device *dev);
1265 extern void ironlake_disable_fbc(struct drm_device *dev);
1266 extern void intel_disable_fbc(struct drm_device *dev);
1267 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1268 extern bool intel_fbc_enabled(struct drm_device *dev);
1269 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1270 extern void ironlake_enable_rc6(struct drm_device *dev);
1271 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1272 extern void intel_detect_pch (struct drm_device *dev);
1273 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1276 #ifdef CONFIG_DEBUG_FS
1277 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1278 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1280 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1281 extern void intel_display_print_error_state(struct seq_file *m,
1282 struct drm_device *dev,
1283 struct intel_display_error_state *error);
1286 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1288 #define BEGIN_LP_RING(n) \
1289 intel_ring_begin(LP_RING(dev_priv), (n))
1291 #define OUT_RING(x) \
1292 intel_ring_emit(LP_RING(dev_priv), x)
1294 #define ADVANCE_LP_RING() \
1295 intel_ring_advance(LP_RING(dev_priv))
1298 * Lock test for when it's just for synchronization of ring access.
1300 * In that case, we don't need to do it when GEM is initialized as nobody else
1301 * has access to the ring.
1303 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1304 if (LP_RING(dev->dev_private)->obj == NULL) \
1305 LOCK_TEST_WITH_RETURN(dev, file); \
1309 #define __i915_read(x, y) \
1310 static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1311 u##x val = read##y(dev_priv->regs + reg); \
1312 trace_i915_reg_rw('R', reg, val, sizeof(val)); \
1321 #define __i915_write(x, y) \
1322 static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1323 trace_i915_reg_rw('W', reg, val, sizeof(val)); \
1324 write##y(val, dev_priv->regs + reg); \
1332 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1333 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1335 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1336 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1337 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1338 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1340 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1341 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1342 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1343 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1345 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1346 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1348 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1349 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1352 /* On SNB platform, before reading ring registers forcewake bit
1353 * must be set to prevent GT core from power down and stale values being
1356 void __gen6_force_wake_get(struct drm_i915_private *dev_priv);
1357 void __gen6_force_wake_put (struct drm_i915_private *dev_priv);
1358 static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
1362 if (dev_priv->info->gen >= 6) {
1363 __gen6_force_wake_get(dev_priv);
1364 val = I915_READ(reg);
1365 __gen6_force_wake_put(dev_priv);
1367 val = I915_READ(reg);
1373 i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
1375 /* Trace down the write operation before the real write */
1376 trace_i915_reg_rw('W', reg, val, len);
1379 writeq(val, dev_priv->regs + reg);
1382 writel(val, dev_priv->regs + reg);
1385 writew(val, dev_priv->regs + reg);
1388 writeb(val, dev_priv->regs + reg);
1394 * Reads a dword out of the status page, which is written to from the command
1395 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1396 * MI_STORE_DATA_IMM.
1398 * The following dwords have a reserved meaning:
1399 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1400 * 0x04: ring 0 head pointer
1401 * 0x05: ring 1 head pointer (915-class)
1402 * 0x06: ring 2 head pointer (915-class)
1403 * 0x10-0x1b: Context status DWords (GM45)
1404 * 0x1f: Last written status offset. (GM45)
1406 * The area from dword 0x20 to 0x3ff is available for driver usage.
1408 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1409 (LP_RING(dev_priv)->status_page.page_addr))[reg])
1410 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1411 #define I915_GEM_HWS_INDEX 0x20
1412 #define I915_BREADCRUMB_INDEX 0x21