1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <drm/intel-gtt.h>
40 #include <linux/backlight.h>
42 /* General customization:
45 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
47 #define DRIVER_NAME "i915"
48 #define DRIVER_DESC "Intel Graphics"
49 #define DRIVER_DATE "20080730"
57 #define pipe_name(p) ((p) + 'A')
64 #define plane_name(p) ((p) + 'A')
66 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
68 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
73 * 1.2: Add Power Management
74 * 1.3: Add vblank support
75 * 1.4: Fix cmdbuffer path, add heap destroy
76 * 1.5: Add vblank pipe configuration
77 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
78 * - Support vertical blank on secondary display pipe
80 #define DRIVER_MAJOR 1
81 #define DRIVER_MINOR 6
82 #define DRIVER_PATCHLEVEL 0
84 #define WATCH_COHERENCY 0
87 #define I915_GEM_PHYS_CURSOR_0 1
88 #define I915_GEM_PHYS_CURSOR_1 2
89 #define I915_GEM_PHYS_OVERLAY_REGS 3
90 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
92 struct drm_i915_gem_phys_object {
94 struct page **page_list;
95 drm_dma_handle_t *handle;
96 struct drm_i915_gem_object *cur_obj;
100 struct mem_block *next;
101 struct mem_block *prev;
104 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
107 struct opregion_header;
108 struct opregion_acpi;
109 struct opregion_swsci;
110 struct opregion_asle;
111 struct drm_i915_private;
113 struct intel_opregion {
114 struct opregion_header *header;
115 struct opregion_acpi *acpi;
116 struct opregion_swsci *swsci;
117 struct opregion_asle *asle;
119 u32 __iomem *lid_state;
121 #define OPREGION_SIZE (8*1024)
123 struct intel_overlay;
124 struct intel_overlay_error_state;
126 struct drm_i915_master_private {
127 drm_local_map_t *sarea;
128 struct _drm_i915_sarea *sarea_priv;
130 #define I915_FENCE_REG_NONE -1
131 #define I915_MAX_NUM_FENCES 16
132 /* 16 fences + sign bit for FENCE_REG_NONE */
133 #define I915_MAX_NUM_FENCE_BITS 5
135 struct drm_i915_fence_reg {
136 struct list_head lru_list;
137 struct drm_i915_gem_object *obj;
138 uint32_t setup_seqno;
142 struct sdvo_device_mapping {
151 struct intel_display_error_state;
153 struct drm_i915_error_state {
156 u32 pipestat[I915_MAX_PIPES];
157 u32 tail[I915_NUM_RINGS];
158 u32 head[I915_NUM_RINGS];
159 u32 ipeir[I915_NUM_RINGS];
160 u32 ipehr[I915_NUM_RINGS];
161 u32 instdone[I915_NUM_RINGS];
162 u32 acthd[I915_NUM_RINGS];
163 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
164 /* our own tracking of ring head and tail */
165 u32 cpu_ring_head[I915_NUM_RINGS];
166 u32 cpu_ring_tail[I915_NUM_RINGS];
167 u32 error; /* gen6+ */
168 u32 instpm[I915_NUM_RINGS];
169 u32 instps[I915_NUM_RINGS];
171 u32 seqno[I915_NUM_RINGS];
173 u32 fault_reg[I915_NUM_RINGS];
175 u32 faddr[I915_NUM_RINGS];
176 u64 fence[I915_MAX_NUM_FENCES];
178 struct drm_i915_error_ring {
179 struct drm_i915_error_object {
183 } *ringbuffer, *batchbuffer;
184 struct drm_i915_error_request {
190 } ring[I915_NUM_RINGS];
191 struct drm_i915_error_buffer {
198 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
205 } *active_bo, *pinned_bo;
206 u32 active_bo_count, pinned_bo_count;
207 struct intel_overlay_error_state *overlay;
208 struct intel_display_error_state *display;
211 struct drm_i915_display_funcs {
212 void (*dpms)(struct drm_crtc *crtc, int mode);
213 bool (*fbc_enabled)(struct drm_device *dev);
214 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
215 void (*disable_fbc)(struct drm_device *dev);
216 int (*get_display_clock_speed)(struct drm_device *dev);
217 int (*get_fifo_size)(struct drm_device *dev, int plane);
218 void (*update_wm)(struct drm_device *dev);
219 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
220 uint32_t sprite_width, int pixel_size);
221 int (*crtc_mode_set)(struct drm_crtc *crtc,
222 struct drm_display_mode *mode,
223 struct drm_display_mode *adjusted_mode,
225 struct drm_framebuffer *old_fb);
226 void (*write_eld)(struct drm_connector *connector,
227 struct drm_crtc *crtc);
228 void (*fdi_link_train)(struct drm_crtc *crtc);
229 void (*init_clock_gating)(struct drm_device *dev);
230 void (*init_pch_clock_gating)(struct drm_device *dev);
231 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
232 struct drm_framebuffer *fb,
233 struct drm_i915_gem_object *obj);
234 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
236 void (*force_wake_get)(struct drm_i915_private *dev_priv);
237 void (*force_wake_put)(struct drm_i915_private *dev_priv);
238 /* clock updates for mode set */
240 /* render clock increase/decrease */
241 /* display clock increase/decrease */
242 /* pll clock increase/decrease */
245 struct intel_device_info {
264 u8 cursor_needs_physical:1;
266 u8 overlay_needs_physical:1;
273 #define I915_PPGTT_PD_ENTRIES 512
274 #define I915_PPGTT_PT_ENTRIES 1024
275 struct i915_hw_ppgtt {
276 unsigned num_pd_entries;
277 struct page **pt_pages;
279 dma_addr_t *pt_dma_addr;
280 dma_addr_t scratch_page_dma_addr;
284 FBC_NO_OUTPUT, /* no outputs enabled to compress */
285 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
286 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
287 FBC_MODE_TOO_LARGE, /* mode too large for compression */
288 FBC_BAD_PLANE, /* fbc not supported on plane */
289 FBC_NOT_TILED, /* buffer not tiled */
290 FBC_MULTIPLE_PIPES, /* more than one pipe active */
295 PCH_IBX, /* Ibexpeak PCH */
296 PCH_CPT, /* Cougarpoint PCH */
299 #define QUIRK_PIPEA_FORCE (1<<0)
300 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
301 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
304 struct intel_fbc_work;
307 struct i2c_adapter adapter;
311 struct i2c_algo_bit_data bit_algo;
312 struct drm_i915_private *dev_priv;
315 typedef struct drm_i915_private {
316 struct drm_device *dev;
318 const struct intel_device_info *info;
321 int relative_constants_mode;
324 /** gt_fifo_count and the subsequent register write are synchronized
325 * with dev->struct_mutex. */
326 unsigned gt_fifo_count;
327 /** forcewake_count is protected by gt_lock */
328 unsigned forcewake_count;
329 /** gt_lock is also taken in irq contexts. */
330 struct spinlock gt_lock;
332 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
334 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
335 * controller on different i2c buses. */
336 struct mutex gmbus_mutex;
339 * Base address of the gmbus and gpio block.
341 uint32_t gpio_mmio_base;
343 struct pci_dev *bridge_dev;
344 struct intel_ring_buffer ring[I915_NUM_RINGS];
347 drm_dma_handle_t *status_page_dmah;
349 drm_local_map_t hws_map;
350 struct drm_i915_gem_object *pwrctx;
351 struct drm_i915_gem_object *renderctx;
353 struct resource mch_res;
361 atomic_t irq_received;
363 /* protects the irq masks */
366 /* DPIO indirect register protection */
367 spinlock_t dpio_lock;
369 /** Cached value of IMR to avoid reads in updating the bitfield */
375 u32 hotplug_supported_mask;
376 struct work_struct hotplug_work;
378 int tex_lru_log_granularity;
379 int allow_batchbuffer;
380 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
384 /* For hangcheck timer */
385 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
386 struct timer_list hangcheck_timer;
389 uint32_t last_acthd_bsd;
390 uint32_t last_acthd_blt;
391 uint32_t last_instdone;
392 uint32_t last_instdone1;
394 unsigned long cfb_size;
396 enum plane cfb_plane;
398 struct intel_fbc_work *fbc_work;
400 struct intel_opregion opregion;
403 struct intel_overlay *overlay;
404 bool sprite_scaling_enabled;
407 int backlight_level; /* restore backlight to this value */
408 bool backlight_enabled;
409 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
410 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
412 /* Feature bits from the VBIOS */
413 unsigned int int_tv_support:1;
414 unsigned int lvds_dither:1;
415 unsigned int lvds_vbt:1;
416 unsigned int int_crt_support:1;
417 unsigned int lvds_use_ssc:1;
418 unsigned int display_clock_mode:1;
420 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
421 unsigned int lvds_val; /* used for checking LVDS channel mode */
431 struct edp_power_seq pps;
433 bool no_aux_handshake;
435 struct notifier_block lid_notifier;
438 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
439 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
440 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
442 unsigned int fsb_freq, mem_freq, is_ddr3;
444 spinlock_t error_lock;
445 struct drm_i915_error_state *first_error;
446 struct work_struct error_work;
447 struct completion error_completion;
448 struct workqueue_struct *wq;
450 /* Display functions */
451 struct drm_i915_display_funcs display;
453 /* PCH chipset type */
454 enum intel_pch pch_type;
456 unsigned long quirks;
481 u32 saveTRANS_HTOTAL_A;
482 u32 saveTRANS_HBLANK_A;
483 u32 saveTRANS_HSYNC_A;
484 u32 saveTRANS_VTOTAL_A;
485 u32 saveTRANS_VBLANK_A;
486 u32 saveTRANS_VSYNC_A;
494 u32 savePFIT_PGM_RATIOS;
495 u32 saveBLC_HIST_CTL;
497 u32 saveBLC_PWM_CTL2;
498 u32 saveBLC_CPU_PWM_CTL;
499 u32 saveBLC_CPU_PWM_CTL2;
512 u32 saveTRANS_HTOTAL_B;
513 u32 saveTRANS_HBLANK_B;
514 u32 saveTRANS_HSYNC_B;
515 u32 saveTRANS_VTOTAL_B;
516 u32 saveTRANS_VBLANK_B;
517 u32 saveTRANS_VSYNC_B;
531 u32 savePP_ON_DELAYS;
532 u32 savePP_OFF_DELAYS;
540 u32 savePFIT_CONTROL;
541 u32 save_palette_a[256];
542 u32 save_palette_b[256];
543 u32 saveDPFC_CB_BASE;
544 u32 saveFBC_CFB_BASE;
547 u32 saveFBC_CONTROL2;
557 u32 saveCACHE_MODE_0;
558 u32 saveMI_ARB_STATE;
569 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
580 u32 savePIPEA_GMCH_DATA_M;
581 u32 savePIPEB_GMCH_DATA_M;
582 u32 savePIPEA_GMCH_DATA_N;
583 u32 savePIPEB_GMCH_DATA_N;
584 u32 savePIPEA_DP_LINK_M;
585 u32 savePIPEB_DP_LINK_M;
586 u32 savePIPEA_DP_LINK_N;
587 u32 savePIPEB_DP_LINK_N;
598 u32 savePCH_DREF_CONTROL;
599 u32 saveDISP_ARB_CTL;
600 u32 savePIPEA_DATA_M1;
601 u32 savePIPEA_DATA_N1;
602 u32 savePIPEA_LINK_M1;
603 u32 savePIPEA_LINK_N1;
604 u32 savePIPEB_DATA_M1;
605 u32 savePIPEB_DATA_N1;
606 u32 savePIPEB_LINK_M1;
607 u32 savePIPEB_LINK_N1;
608 u32 saveMCHBAR_RENDER_STANDBY;
609 u32 savePCH_PORT_HOTPLUG;
612 /** Bridge to intel-gtt-ko */
613 const struct intel_gtt *gtt;
614 /** Memory allocator for GTT stolen memory */
615 struct drm_mm stolen;
616 /** Memory allocator for GTT */
617 struct drm_mm gtt_space;
618 /** List of all objects in gtt_space. Used to restore gtt
619 * mappings on resume */
620 struct list_head gtt_list;
622 /** Usable portion of the GTT for GEM */
623 unsigned long gtt_start;
624 unsigned long gtt_mappable_end;
625 unsigned long gtt_end;
627 struct io_mapping *gtt_mapping;
630 /** PPGTT used for aliasing the PPGTT with the GTT */
631 struct i915_hw_ppgtt *aliasing_ppgtt;
633 struct shrinker inactive_shrinker;
636 * List of objects currently involved in rendering.
638 * Includes buffers having the contents of their GPU caches
639 * flushed, not necessarily primitives. last_rendering_seqno
640 * represents when the rendering involved will be completed.
642 * A reference is held on the buffer while on this list.
644 struct list_head active_list;
647 * List of objects which are not in the ringbuffer but which
648 * still have a write_domain which needs to be flushed before
651 * last_rendering_seqno is 0 while an object is in this list.
653 * A reference is held on the buffer while on this list.
655 struct list_head flushing_list;
658 * LRU list of objects which are not in the ringbuffer and
659 * are ready to unbind, but are still in the GTT.
661 * last_rendering_seqno is 0 while an object is in this list.
663 * A reference is not held on the buffer while on this list,
664 * as merely being GTT-bound shouldn't prevent its being
665 * freed, and we'll pull it off the list in the free path.
667 struct list_head inactive_list;
670 * LRU list of objects which are not in the ringbuffer but
671 * are still pinned in the GTT.
673 struct list_head pinned_list;
675 /** LRU list of objects with fence regs on them. */
676 struct list_head fence_list;
679 * List of objects currently pending being freed.
681 * These objects are no longer in use, but due to a signal
682 * we were prevented from freeing them at the appointed time.
684 struct list_head deferred_free_list;
687 * We leave the user IRQ off as much as possible,
688 * but this means that requests will finish and never
689 * be retired once the system goes idle. Set a timer to
690 * fire periodically while the ring is running. When it
691 * fires, go retire requests.
693 struct delayed_work retire_work;
696 * Are we in a non-interruptible section of code like
702 * Flag if the X Server, and thus DRM, is not currently in
703 * control of the device.
705 * This is set between LeaveVT and EnterVT. It needs to be
706 * replaced with a semaphore. It also needs to be
707 * transitioned away from for kernel modesetting.
712 * Flag if the hardware appears to be wedged.
714 * This is set when attempts to idle the device timeout.
715 * It prevents command submission from occurring and makes
716 * every pending request fail
720 /** Bit 6 swizzling required for X tiling */
721 uint32_t bit_6_swizzle_x;
722 /** Bit 6 swizzling required for Y tiling */
723 uint32_t bit_6_swizzle_y;
725 /* storage for physical objects */
726 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
728 /* accounting, useful for userland debugging */
730 size_t mappable_gtt_total;
731 size_t object_memory;
734 struct sdvo_device_mapping sdvo_mappings[2];
735 /* indicate whether the LVDS_BORDER should be enabled or not */
736 unsigned int lvds_border_bits;
737 /* Panel fitter placement and size for Ironlake+ */
738 u32 pch_pf_pos, pch_pf_size;
740 struct drm_crtc *plane_to_crtc_mapping[3];
741 struct drm_crtc *pipe_to_crtc_mapping[3];
742 wait_queue_head_t pending_flip_queue;
743 bool flip_pending_is_done;
745 /* Reclocking support */
746 bool render_reclock_avail;
747 bool lvds_downclock_avail;
748 /* indicates the reduced downclock for LVDS*/
750 struct work_struct idle_work;
751 struct timer_list idle_timer;
755 struct child_device_config *child_dev;
756 struct drm_connector *int_lvds_connector;
757 struct drm_connector *int_edp_connector;
759 bool mchbar_need_disable;
761 struct work_struct rps_work;
772 unsigned long last_time1;
773 unsigned long chipset_power;
775 struct timespec last_time2;
776 unsigned long gfx_power;
780 spinlock_t *mchdev_lock;
782 enum no_fbc_reason no_fbc_reason;
784 struct drm_mm_node *compressed_fb;
785 struct drm_mm_node *compressed_llb;
787 unsigned long last_gpu_reset;
789 /* list of fbdev register on this device */
790 struct intel_fbdev *fbdev;
792 struct backlight_device *backlight;
794 struct drm_property *broadcast_rgb_property;
795 struct drm_property *force_audio_property;
796 } drm_i915_private_t;
798 enum hdmi_force_audio {
799 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
800 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
801 HDMI_AUDIO_AUTO, /* trust EDID */
802 HDMI_AUDIO_ON, /* force turn on HDMI audio */
805 enum i915_cache_level {
808 I915_CACHE_LLC_MLC, /* gen6+ */
811 struct drm_i915_gem_object {
812 struct drm_gem_object base;
814 /** Current space allocated to this object in the GTT, if any. */
815 struct drm_mm_node *gtt_space;
816 struct list_head gtt_list;
818 /** This object's place on the active/flushing/inactive lists */
819 struct list_head ring_list;
820 struct list_head mm_list;
821 /** This object's place on GPU write list */
822 struct list_head gpu_write_list;
823 /** This object's place in the batchbuffer or on the eviction list */
824 struct list_head exec_list;
827 * This is set if the object is on the active or flushing lists
828 * (has pending rendering), and is not set if it's on inactive (ready
831 unsigned int active:1;
834 * This is set if the object has been written to since last bound
837 unsigned int dirty:1;
840 * This is set if the object has been written to since the last
843 unsigned int pending_gpu_write:1;
846 * Fence register bits (if any) for this object. Will be set
847 * as needed when mapped into the GTT.
848 * Protected by dev->struct_mutex.
850 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
853 * Advice: are the backing pages purgeable?
858 * Current tiling mode for the object.
860 unsigned int tiling_mode:2;
861 unsigned int tiling_changed:1;
863 /** How many users have pinned this object in GTT space. The following
864 * users can each hold at most one reference: pwrite/pread, pin_ioctl
865 * (via user_pin_count), execbuffer (objects are not allowed multiple
866 * times for the same batchbuffer), and the framebuffer code. When
867 * switching/pageflipping, the framebuffer code has at most two buffers
870 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
871 * bits with absolutely no headroom. So use 4 bits. */
872 unsigned int pin_count:4;
873 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
876 * Is the object at the current location in the gtt mappable and
877 * fenceable? Used to avoid costly recalculations.
879 unsigned int map_and_fenceable:1;
882 * Whether the current gtt mapping needs to be mappable (and isn't just
883 * mappable by accident). Track pin and fault separate for a more
884 * accurate mappable working set.
886 unsigned int fault_mappable:1;
887 unsigned int pin_mappable:1;
890 * Is the GPU currently using a fence to access this buffer,
892 unsigned int pending_fenced_gpu_access:1;
893 unsigned int fenced_gpu_access:1;
895 unsigned int cache_level:2;
897 unsigned int has_aliasing_ppgtt_mapping:1;
898 unsigned int has_global_gtt_mapping:1;
905 struct scatterlist *sg_list;
909 * Used for performing relocations during execbuffer insertion.
911 struct hlist_node exec_node;
912 unsigned long exec_handle;
913 struct drm_i915_gem_exec_object2 *exec_entry;
916 * Current offset of the object in GTT space.
918 * This is the same as gtt_space->start
922 /** Breadcrumb of last rendering to the buffer. */
923 uint32_t last_rendering_seqno;
924 struct intel_ring_buffer *ring;
926 /** Breadcrumb of last fenced GPU access to the buffer. */
927 uint32_t last_fenced_seqno;
928 struct intel_ring_buffer *last_fenced_ring;
930 /** Current tiling stride for the object, if it's tiled. */
933 /** Record of address bit 17 of each page at last unbind. */
934 unsigned long *bit_17;
936 /** User space pin count and filp owning the pin */
937 uint32_t user_pin_count;
938 struct drm_file *pin_filp;
940 /** for phy allocated objects */
941 struct drm_i915_gem_phys_object *phys_obj;
944 * Number of crtcs where this object is currently the fb, but
945 * will be page flipped away on the next vblank. When it
946 * reaches 0, dev_priv->pending_flip_queue will be woken up.
948 atomic_t pending_flip;
951 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
954 * Request queue structure.
956 * The request queue allows us to note sequence numbers that have been emitted
957 * and may be associated with active buffers to be retired.
959 * By keeping this list, we can avoid having to do questionable
960 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
961 * an emission time with seqnos for tracking how far ahead of the GPU we are.
963 struct drm_i915_gem_request {
964 /** On Which ring this request was generated */
965 struct intel_ring_buffer *ring;
967 /** GEM sequence number associated with this request. */
970 /** Postion in the ringbuffer of the end of the request */
973 /** Time at which this request was emitted, in jiffies. */
974 unsigned long emitted_jiffies;
976 /** global list entry for this request */
977 struct list_head list;
979 struct drm_i915_file_private *file_priv;
980 /** file_priv list entry for this request */
981 struct list_head client_list;
984 struct drm_i915_file_private {
986 struct spinlock lock;
987 struct list_head request_list;
991 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
993 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
994 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
995 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
996 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
997 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
998 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
999 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1000 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1001 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1002 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1003 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1004 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1005 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1006 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1007 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1008 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1009 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1010 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1011 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1012 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1013 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1014 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1017 * The genX designation typically refers to the render engine, so render
1018 * capability related checks should use IS_GEN, while display and other checks
1019 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1022 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1023 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1024 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1025 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1026 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1027 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1029 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1030 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1031 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1032 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1034 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
1036 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1037 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1039 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1040 * rows, which changed the alignment requirements and fence programming.
1042 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1044 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1045 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1046 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1047 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1048 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1049 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1050 /* dsparb controlled by hw only */
1051 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1053 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1054 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1055 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1057 #define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split)
1058 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1060 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1061 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1062 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1064 #include "i915_trace.h"
1066 extern struct drm_ioctl_desc i915_ioctls[];
1067 extern int i915_max_ioctl;
1068 extern unsigned int i915_fbpercrtc __always_unused;
1069 extern int i915_panel_ignore_lid __read_mostly;
1070 extern unsigned int i915_powersave __read_mostly;
1071 extern int i915_semaphores __read_mostly;
1072 extern unsigned int i915_lvds_downclock __read_mostly;
1073 extern int i915_lvds_channel_mode __read_mostly;
1074 extern int i915_panel_use_ssc __read_mostly;
1075 extern int i915_vbt_sdvo_panel_type __read_mostly;
1076 extern int i915_enable_rc6 __read_mostly;
1077 extern int i915_enable_fbc __read_mostly;
1078 extern bool i915_enable_hangcheck __read_mostly;
1079 extern bool i915_enable_ppgtt __read_mostly;
1081 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1082 extern int i915_resume(struct drm_device *dev);
1083 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1084 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1087 extern void i915_kernel_lost_context(struct drm_device * dev);
1088 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1089 extern int i915_driver_unload(struct drm_device *);
1090 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1091 extern void i915_driver_lastclose(struct drm_device * dev);
1092 extern void i915_driver_preclose(struct drm_device *dev,
1093 struct drm_file *file_priv);
1094 extern void i915_driver_postclose(struct drm_device *dev,
1095 struct drm_file *file_priv);
1096 extern int i915_driver_device_is_agp(struct drm_device * dev);
1097 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1099 extern int i915_emit_box(struct drm_device *dev,
1100 struct drm_clip_rect *box,
1102 extern int i915_reset(struct drm_device *dev, u8 flags);
1103 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1104 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1105 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1106 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1110 void i915_hangcheck_elapsed(unsigned long data);
1111 void i915_handle_error(struct drm_device *dev, bool wedged);
1112 extern int i915_irq_emit(struct drm_device *dev, void *data,
1113 struct drm_file *file_priv);
1114 extern int i915_irq_wait(struct drm_device *dev, void *data,
1115 struct drm_file *file_priv);
1117 extern void intel_irq_init(struct drm_device *dev);
1119 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1120 struct drm_file *file_priv);
1121 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1122 struct drm_file *file_priv);
1123 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1124 struct drm_file *file_priv);
1127 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1130 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1132 void intel_enable_asle(struct drm_device *dev);
1134 #ifdef CONFIG_DEBUG_FS
1135 extern void i915_destroy_error_state(struct drm_device *dev);
1137 #define i915_destroy_error_state(x)
1142 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1143 struct drm_file *file_priv);
1144 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1145 struct drm_file *file_priv);
1146 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1147 struct drm_file *file_priv);
1148 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1149 struct drm_file *file_priv);
1150 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1151 struct drm_file *file_priv);
1152 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1153 struct drm_file *file_priv);
1154 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1155 struct drm_file *file_priv);
1156 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1157 struct drm_file *file_priv);
1158 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1159 struct drm_file *file_priv);
1160 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1161 struct drm_file *file_priv);
1162 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1163 struct drm_file *file_priv);
1164 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1165 struct drm_file *file_priv);
1166 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1167 struct drm_file *file_priv);
1168 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1169 struct drm_file *file_priv);
1170 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1171 struct drm_file *file_priv);
1172 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1173 struct drm_file *file_priv);
1174 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1175 struct drm_file *file_priv);
1176 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1177 struct drm_file *file_priv);
1178 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1179 struct drm_file *file_priv);
1180 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1181 struct drm_file *file_priv);
1182 void i915_gem_load(struct drm_device *dev);
1183 int i915_gem_init_object(struct drm_gem_object *obj);
1184 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1185 uint32_t invalidate_domains,
1186 uint32_t flush_domains);
1187 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1189 void i915_gem_free_object(struct drm_gem_object *obj);
1190 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1192 bool map_and_fenceable);
1193 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1194 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1195 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1196 void i915_gem_lastclose(struct drm_device *dev);
1198 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1199 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1200 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1201 struct intel_ring_buffer *ring,
1204 int i915_gem_dumb_create(struct drm_file *file_priv,
1205 struct drm_device *dev,
1206 struct drm_mode_create_dumb *args);
1207 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1208 uint32_t handle, uint64_t *offset);
1209 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1212 * Returns true if seq1 is later than seq2.
1215 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1217 return (int32_t)(seq1 - seq2) >= 0;
1220 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1222 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1223 struct intel_ring_buffer *pipelined);
1224 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1227 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1229 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1230 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1231 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1236 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1238 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1239 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1240 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1244 void i915_gem_retire_requests(struct drm_device *dev);
1245 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1247 void i915_gem_reset(struct drm_device *dev);
1248 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1249 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1250 uint32_t read_domains,
1251 uint32_t write_domain);
1252 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1253 int __must_check i915_gem_init_hw(struct drm_device *dev);
1254 void i915_gem_init_swizzling(struct drm_device *dev);
1255 void i915_gem_init_ppgtt(struct drm_device *dev);
1256 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1257 int __must_check i915_gpu_idle(struct drm_device *dev, bool do_retire);
1258 int __must_check i915_gem_idle(struct drm_device *dev);
1259 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1260 struct drm_file *file,
1261 struct drm_i915_gem_request *request);
1262 int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1265 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1267 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1270 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1272 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1274 struct intel_ring_buffer *pipelined);
1275 int i915_gem_attach_phys_object(struct drm_device *dev,
1276 struct drm_i915_gem_object *obj,
1279 void i915_gem_detach_phys_object(struct drm_device *dev,
1280 struct drm_i915_gem_object *obj);
1281 void i915_gem_free_all_phys_object(struct drm_device *dev);
1282 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1285 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1289 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1290 enum i915_cache_level cache_level);
1292 /* i915_gem_gtt.c */
1293 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1294 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1295 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1296 struct drm_i915_gem_object *obj,
1297 enum i915_cache_level cache_level);
1298 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1299 struct drm_i915_gem_object *obj);
1301 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1302 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1303 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1304 enum i915_cache_level cache_level);
1305 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1306 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1307 void i915_gem_init_global_gtt(struct drm_device *dev,
1308 unsigned long start,
1309 unsigned long mappable_end,
1312 /* i915_gem_evict.c */
1313 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1314 unsigned alignment, bool mappable);
1315 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1316 bool purgeable_only);
1317 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1318 bool purgeable_only);
1320 /* i915_gem_tiling.c */
1321 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1322 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1323 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1325 /* i915_gem_debug.c */
1326 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1327 const char *where, uint32_t mark);
1329 int i915_verify_lists(struct drm_device *dev);
1331 #define i915_verify_lists(dev) 0
1333 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1335 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1336 const char *where, uint32_t mark);
1338 /* i915_debugfs.c */
1339 int i915_debugfs_init(struct drm_minor *minor);
1340 void i915_debugfs_cleanup(struct drm_minor *minor);
1342 /* i915_suspend.c */
1343 extern int i915_save_state(struct drm_device *dev);
1344 extern int i915_restore_state(struct drm_device *dev);
1346 /* i915_suspend.c */
1347 extern int i915_save_state(struct drm_device *dev);
1348 extern int i915_restore_state(struct drm_device *dev);
1351 extern int intel_setup_gmbus(struct drm_device *dev);
1352 extern void intel_teardown_gmbus(struct drm_device *dev);
1353 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1355 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1358 extern struct i2c_adapter *intel_gmbus_get_adapter(
1359 struct drm_i915_private *dev_priv, unsigned port);
1360 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1361 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1362 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1364 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1366 extern void intel_i2c_reset(struct drm_device *dev);
1368 /* intel_opregion.c */
1369 extern int intel_opregion_setup(struct drm_device *dev);
1371 extern void intel_opregion_init(struct drm_device *dev);
1372 extern void intel_opregion_fini(struct drm_device *dev);
1373 extern void intel_opregion_asle_intr(struct drm_device *dev);
1374 extern void intel_opregion_gse_intr(struct drm_device *dev);
1375 extern void intel_opregion_enable_asle(struct drm_device *dev);
1377 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1378 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1379 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1380 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1381 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1386 extern void intel_register_dsm_handler(void);
1387 extern void intel_unregister_dsm_handler(void);
1389 static inline void intel_register_dsm_handler(void) { return; }
1390 static inline void intel_unregister_dsm_handler(void) { return; }
1391 #endif /* CONFIG_ACPI */
1394 extern void intel_modeset_init(struct drm_device *dev);
1395 extern void intel_modeset_gem_init(struct drm_device *dev);
1396 extern void intel_modeset_cleanup(struct drm_device *dev);
1397 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1398 extern bool intel_fbc_enabled(struct drm_device *dev);
1399 extern void intel_disable_fbc(struct drm_device *dev);
1400 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1401 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1402 extern void ironlake_enable_rc6(struct drm_device *dev);
1403 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1404 extern void intel_detect_pch(struct drm_device *dev);
1405 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1407 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1408 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1409 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1410 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1412 extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
1413 extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
1416 #ifdef CONFIG_DEBUG_FS
1417 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1418 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1420 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1421 extern void intel_display_print_error_state(struct seq_file *m,
1422 struct drm_device *dev,
1423 struct intel_display_error_state *error);
1426 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1428 #define BEGIN_LP_RING(n) \
1429 intel_ring_begin(LP_RING(dev_priv), (n))
1431 #define OUT_RING(x) \
1432 intel_ring_emit(LP_RING(dev_priv), x)
1434 #define ADVANCE_LP_RING() \
1435 intel_ring_advance(LP_RING(dev_priv))
1438 * Lock test for when it's just for synchronization of ring access.
1440 * In that case, we don't need to do it when GEM is initialized as nobody else
1441 * has access to the ring.
1443 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1444 if (LP_RING(dev->dev_private)->obj == NULL) \
1445 LOCK_TEST_WITH_RETURN(dev, file); \
1448 /* On SNB platform, before reading ring registers forcewake bit
1449 * must be set to prevent GT core from power down and stale values being
1452 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1453 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1454 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1456 #define __i915_read(x, y) \
1457 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1465 #define __i915_write(x, y) \
1466 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1474 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1475 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1477 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1478 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1479 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1480 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1482 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1483 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1484 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1485 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1487 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1488 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1490 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1491 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)