1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150508"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
86 #define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 unlikely(__ret_warn_on); \
114 I915_MAX_PIPES = _PIPE_EDP
116 #define pipe_name(p) ((p) + 'A')
125 #define transcoder_name(t) ((t) + 'A')
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
131 * This value doesn't count the cursor plane.
133 #define I915_MAX_PLANES 4
140 #define plane_name(p) ((p) + 'A')
142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
152 #define port_name(p) ((p) + 'A')
154 #define I915_NUM_PHYS_VLV 2
166 enum intel_display_power_domain {
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
173 POWER_DOMAIN_TRANSCODER_A,
174 POWER_DOMAIN_TRANSCODER_B,
175 POWER_DOMAIN_TRANSCODER_C,
176 POWER_DOMAIN_TRANSCODER_EDP,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES,
185 POWER_DOMAIN_PORT_DSI,
186 POWER_DOMAIN_PORT_CRT,
187 POWER_DOMAIN_PORT_OTHER,
200 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
201 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
203 #define POWER_DOMAIN_TRANSCODER(tran) \
204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
205 (tran) + POWER_DOMAIN_TRANSCODER_A)
209 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
220 #define I915_GEM_GPU_DOMAINS \
221 (I915_GEM_DOMAIN_RENDER | \
222 I915_GEM_DOMAIN_SAMPLER | \
223 I915_GEM_DOMAIN_COMMAND | \
224 I915_GEM_DOMAIN_INSTRUCTION | \
225 I915_GEM_DOMAIN_VERTEX)
227 #define for_each_pipe(__dev_priv, __p) \
228 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
229 #define for_each_plane(__dev_priv, __pipe, __p) \
231 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
233 #define for_each_sprite(__dev_priv, __p, __s) \
235 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
238 #define for_each_crtc(dev, crtc) \
239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
241 #define for_each_intel_plane(dev, intel_plane) \
242 list_for_each_entry(intel_plane, \
243 &dev->mode_config.plane_list, \
246 #define for_each_intel_crtc(dev, intel_crtc) \
247 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
249 #define for_each_intel_encoder(dev, intel_encoder) \
250 list_for_each_entry(intel_encoder, \
251 &(dev)->mode_config.encoder_list, \
254 #define for_each_intel_connector(dev, intel_connector) \
255 list_for_each_entry(intel_connector, \
256 &dev->mode_config.connector_list, \
259 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
260 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
261 if ((intel_encoder)->base.crtc == (__crtc))
263 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
264 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
265 if ((intel_connector)->base.encoder == (__encoder))
267 #define for_each_power_domain(domain, mask) \
268 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
269 if ((1 << (domain)) & (mask))
271 struct drm_i915_private;
272 struct i915_mm_struct;
273 struct i915_mmu_object;
275 struct drm_i915_file_private {
276 struct drm_i915_private *dev_priv;
277 struct drm_file *file;
281 struct list_head request_list;
283 struct idr context_idr;
285 struct intel_rps_client {
286 struct list_head link;
290 struct intel_engine_cs *bsd_ring;
294 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
295 /* real shared dpll ids must be >= 0 */
296 DPLL_ID_PCH_PLL_A = 0,
297 DPLL_ID_PCH_PLL_B = 1,
302 DPLL_ID_SKL_DPLL1 = 0,
303 DPLL_ID_SKL_DPLL2 = 1,
304 DPLL_ID_SKL_DPLL3 = 2,
306 #define I915_NUM_PLLS 3
308 struct intel_dpll_hw_state {
320 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
321 * lower part of ctrl1 and they get shifted into position when writing
322 * the register. This allows us to easily compare the state to share
326 /* HDMI only, 0 when used for DP */
327 uint32_t cfgcr1, cfgcr2;
330 uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12;
333 struct intel_shared_dpll_config {
334 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
335 struct intel_dpll_hw_state hw_state;
338 struct intel_shared_dpll {
339 struct intel_shared_dpll_config config;
340 struct intel_shared_dpll_config *new_config;
342 int active; /* count of number of active CRTCs (i.e. DPMS on) */
343 bool on; /* is the PLL actually active? Disabled during modeset */
345 /* should match the index in the dev_priv->shared_dplls array */
346 enum intel_dpll_id id;
347 /* The mode_set hook is optional and should be used together with the
348 * intel_prepare_shared_dpll function. */
349 void (*mode_set)(struct drm_i915_private *dev_priv,
350 struct intel_shared_dpll *pll);
351 void (*enable)(struct drm_i915_private *dev_priv,
352 struct intel_shared_dpll *pll);
353 void (*disable)(struct drm_i915_private *dev_priv,
354 struct intel_shared_dpll *pll);
355 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
356 struct intel_shared_dpll *pll,
357 struct intel_dpll_hw_state *hw_state);
365 /* Used by dp and fdi links */
366 struct intel_link_m_n {
374 void intel_link_compute_m_n(int bpp, int nlanes,
375 int pixel_clock, int link_clock,
376 struct intel_link_m_n *m_n);
378 /* Interface history:
381 * 1.2: Add Power Management
382 * 1.3: Add vblank support
383 * 1.4: Fix cmdbuffer path, add heap destroy
384 * 1.5: Add vblank pipe configuration
385 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
386 * - Support vertical blank on secondary display pipe
388 #define DRIVER_MAJOR 1
389 #define DRIVER_MINOR 6
390 #define DRIVER_PATCHLEVEL 0
392 #define WATCH_LISTS 0
394 struct opregion_header;
395 struct opregion_acpi;
396 struct opregion_swsci;
397 struct opregion_asle;
399 struct intel_opregion {
400 struct opregion_header __iomem *header;
401 struct opregion_acpi __iomem *acpi;
402 struct opregion_swsci __iomem *swsci;
403 u32 swsci_gbda_sub_functions;
404 u32 swsci_sbcb_sub_functions;
405 struct opregion_asle __iomem *asle;
407 u32 __iomem *lid_state;
408 struct work_struct asle_work;
410 #define OPREGION_SIZE (8*1024)
412 struct intel_overlay;
413 struct intel_overlay_error_state;
415 #define I915_FENCE_REG_NONE -1
416 #define I915_MAX_NUM_FENCES 32
417 /* 32 fences + sign bit for FENCE_REG_NONE */
418 #define I915_MAX_NUM_FENCE_BITS 6
420 struct drm_i915_fence_reg {
421 struct list_head lru_list;
422 struct drm_i915_gem_object *obj;
426 struct sdvo_device_mapping {
435 struct intel_display_error_state;
437 struct drm_i915_error_state {
445 /* Generic register state */
453 u32 error; /* gen6+ */
454 u32 err_int; /* gen7 */
455 u32 fault_data0; /* gen8, gen9 */
456 u32 fault_data1; /* gen8, gen9 */
462 u32 extra_instdone[I915_NUM_INSTDONE_REG];
463 u64 fence[I915_MAX_NUM_FENCES];
464 struct intel_overlay_error_state *overlay;
465 struct intel_display_error_state *display;
466 struct drm_i915_error_object *semaphore_obj;
468 struct drm_i915_error_ring {
470 /* Software tracked state */
473 enum intel_ring_hangcheck_action hangcheck_action;
476 /* our own tracking of ring head and tail */
480 u32 semaphore_seqno[I915_NUM_RINGS - 1];
499 u32 rc_psmi; /* sleep state */
500 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
502 struct drm_i915_error_object {
506 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
508 struct drm_i915_error_request {
523 char comm[TASK_COMM_LEN];
524 } ring[I915_NUM_RINGS];
526 struct drm_i915_error_buffer {
529 u32 rseqno[I915_NUM_RINGS], wseqno;
533 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
541 } **active_bo, **pinned_bo;
543 u32 *active_bo_count, *pinned_bo_count;
547 struct intel_connector;
548 struct intel_encoder;
549 struct intel_crtc_state;
550 struct intel_initial_plane_config;
555 struct drm_i915_display_funcs {
556 bool (*fbc_enabled)(struct drm_device *dev);
557 void (*enable_fbc)(struct drm_crtc *crtc);
558 void (*disable_fbc)(struct drm_device *dev);
559 int (*get_display_clock_speed)(struct drm_device *dev);
560 int (*get_fifo_size)(struct drm_device *dev, int plane);
562 * find_dpll() - Find the best values for the PLL
563 * @limit: limits for the PLL
564 * @crtc: current CRTC
565 * @target: target frequency in kHz
566 * @refclk: reference clock frequency in kHz
567 * @match_clock: if provided, @best_clock P divider must
568 * match the P divider from @match_clock
569 * used for LVDS downclocking
570 * @best_clock: best PLL values found
572 * Returns true on success, false on failure.
574 bool (*find_dpll)(const struct intel_limit *limit,
575 struct intel_crtc_state *crtc_state,
576 int target, int refclk,
577 struct dpll *match_clock,
578 struct dpll *best_clock);
579 void (*update_wm)(struct drm_crtc *crtc);
580 void (*update_sprite_wm)(struct drm_plane *plane,
581 struct drm_crtc *crtc,
582 uint32_t sprite_width, uint32_t sprite_height,
583 int pixel_size, bool enable, bool scaled);
584 void (*modeset_global_resources)(struct drm_atomic_state *state);
585 /* Returns the active state of the crtc, and if the crtc is active,
586 * fills out the pipe-config with the hw state. */
587 bool (*get_pipe_config)(struct intel_crtc *,
588 struct intel_crtc_state *);
589 void (*get_initial_plane_config)(struct intel_crtc *,
590 struct intel_initial_plane_config *);
591 int (*crtc_compute_clock)(struct intel_crtc *crtc,
592 struct intel_crtc_state *crtc_state);
593 void (*crtc_enable)(struct drm_crtc *crtc);
594 void (*crtc_disable)(struct drm_crtc *crtc);
595 void (*off)(struct drm_crtc *crtc);
596 void (*audio_codec_enable)(struct drm_connector *connector,
597 struct intel_encoder *encoder,
598 struct drm_display_mode *mode);
599 void (*audio_codec_disable)(struct intel_encoder *encoder);
600 void (*fdi_link_train)(struct drm_crtc *crtc);
601 void (*init_clock_gating)(struct drm_device *dev);
602 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
603 struct drm_framebuffer *fb,
604 struct drm_i915_gem_object *obj,
605 struct intel_engine_cs *ring,
607 void (*update_primary_plane)(struct drm_crtc *crtc,
608 struct drm_framebuffer *fb,
610 void (*hpd_irq_setup)(struct drm_device *dev);
611 /* clock updates for mode set */
613 /* render clock increase/decrease */
614 /* display clock increase/decrease */
615 /* pll clock increase/decrease */
617 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
618 uint32_t (*get_backlight)(struct intel_connector *connector);
619 void (*set_backlight)(struct intel_connector *connector,
621 void (*disable_backlight)(struct intel_connector *connector);
622 void (*enable_backlight)(struct intel_connector *connector);
625 enum forcewake_domain_id {
626 FW_DOMAIN_ID_RENDER = 0,
627 FW_DOMAIN_ID_BLITTER,
633 enum forcewake_domains {
634 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
635 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
636 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
637 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
642 struct intel_uncore_funcs {
643 void (*force_wake_get)(struct drm_i915_private *dev_priv,
644 enum forcewake_domains domains);
645 void (*force_wake_put)(struct drm_i915_private *dev_priv,
646 enum forcewake_domains domains);
648 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
649 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
650 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
651 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
653 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
654 uint8_t val, bool trace);
655 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
656 uint16_t val, bool trace);
657 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
658 uint32_t val, bool trace);
659 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
660 uint64_t val, bool trace);
663 struct intel_uncore {
664 spinlock_t lock; /** lock is also taken in irq contexts. */
666 struct intel_uncore_funcs funcs;
669 enum forcewake_domains fw_domains;
671 struct intel_uncore_forcewake_domain {
672 struct drm_i915_private *i915;
673 enum forcewake_domain_id id;
675 struct timer_list timer;
682 } fw_domain[FW_DOMAIN_ID_COUNT];
685 /* Iterate over initialised fw domains */
686 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
687 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
688 (i__) < FW_DOMAIN_ID_COUNT; \
689 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
690 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
692 #define for_each_fw_domain(domain__, dev_priv__, i__) \
693 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
696 FW_UNINITIALIZED = 0,
704 uint32_t dmc_fw_size;
706 uint32_t mmioaddr[8];
707 uint32_t mmiodata[8];
708 enum csr_state state;
711 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
712 func(is_mobile) sep \
715 func(is_i945gm) sep \
717 func(need_gfx_hws) sep \
719 func(is_pineview) sep \
720 func(is_broadwater) sep \
721 func(is_crestline) sep \
722 func(is_ivybridge) sep \
723 func(is_valleyview) sep \
724 func(is_haswell) sep \
725 func(is_skylake) sep \
726 func(is_preliminary) sep \
728 func(has_pipe_cxsr) sep \
729 func(has_hotplug) sep \
730 func(cursor_needs_physical) sep \
731 func(has_overlay) sep \
732 func(overlay_needs_physical) sep \
733 func(supports_tv) sep \
738 #define DEFINE_FLAG(name) u8 name:1
739 #define SEP_SEMICOLON ;
741 struct intel_device_info {
742 u32 display_mmio_offset;
745 u8 num_sprites[I915_MAX_PIPES];
747 u8 ring_mask; /* Rings supported by the HW */
748 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
749 /* Register offsets for the various display pipes and transcoders */
750 int pipe_offsets[I915_MAX_TRANSCODERS];
751 int trans_offsets[I915_MAX_TRANSCODERS];
752 int palette_offsets[I915_MAX_PIPES];
753 int cursor_offsets[I915_MAX_PIPES];
755 /* Slice/subslice/EU info */
758 u8 subslice_per_slice;
761 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
764 u8 has_subslice_pg:1;
771 enum i915_cache_level {
773 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
774 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
775 caches, eg sampler/render caches, and the
776 large Last-Level-Cache. LLC is coherent with
777 the CPU, but L3 is only visible to the GPU. */
778 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
781 struct i915_ctx_hang_stats {
782 /* This context had batch pending when hang was declared */
783 unsigned batch_pending;
785 /* This context had batch active when hang was declared */
786 unsigned batch_active;
788 /* Time when this context was last blamed for a GPU reset */
789 unsigned long guilty_ts;
791 /* If the contexts causes a second GPU hang within this time,
792 * it is permanently banned from submitting any more work.
794 unsigned long ban_period_seconds;
796 /* This context is banned to submit more work */
800 /* This must match up with the value previously used for execbuf2.rsvd1. */
801 #define DEFAULT_CONTEXT_HANDLE 0
803 * struct intel_context - as the name implies, represents a context.
804 * @ref: reference count.
805 * @user_handle: userspace tracking identity for this context.
806 * @remap_slice: l3 row remapping information.
807 * @file_priv: filp associated with this context (NULL for global default
809 * @hang_stats: information about the role of this context in possible GPU
811 * @ppgtt: virtual memory space used by this context.
812 * @legacy_hw_ctx: render context backing object and whether it is correctly
813 * initialized (legacy ring submission mechanism only).
814 * @link: link in the global list of contexts.
816 * Contexts are memory images used by the hardware to store copies of their
819 struct intel_context {
823 struct drm_i915_file_private *file_priv;
824 struct i915_ctx_hang_stats hang_stats;
825 struct i915_hw_ppgtt *ppgtt;
827 /* Legacy ring buffer submission */
829 struct drm_i915_gem_object *rcs_state;
834 bool rcs_initialized;
836 struct drm_i915_gem_object *state;
837 struct intel_ringbuffer *ringbuf;
839 } engine[I915_NUM_RINGS];
841 struct list_head link;
852 unsigned long uncompressed_size;
855 unsigned int possible_framebuffer_bits;
856 unsigned int busy_bits;
857 struct intel_crtc *crtc;
860 struct drm_mm_node compressed_fb;
861 struct drm_mm_node *compressed_llb;
865 /* Tracks whether the HW is actually enabled, not whether the feature is
869 struct intel_fbc_work {
870 struct delayed_work work;
871 struct drm_crtc *crtc;
872 struct drm_framebuffer *fb;
876 FBC_OK, /* FBC is enabled */
877 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
878 FBC_NO_OUTPUT, /* no outputs enabled to compress */
879 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
880 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
881 FBC_MODE_TOO_LARGE, /* mode too large for compression */
882 FBC_BAD_PLANE, /* fbc not supported on plane */
883 FBC_NOT_TILED, /* buffer not tiled */
884 FBC_MULTIPLE_PIPES, /* more than one pipe active */
886 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
891 * HIGH_RR is the highest eDP panel refresh rate read from EDID
892 * LOW_RR is the lowest eDP panel refresh rate found from EDID
893 * parsing for same resolution.
895 enum drrs_refresh_rate_type {
898 DRRS_MAX_RR, /* RR count */
901 enum drrs_support_type {
902 DRRS_NOT_SUPPORTED = 0,
903 STATIC_DRRS_SUPPORT = 1,
904 SEAMLESS_DRRS_SUPPORT = 2
910 struct delayed_work work;
912 unsigned busy_frontbuffer_bits;
913 enum drrs_refresh_rate_type refresh_rate_type;
914 enum drrs_support_type type;
921 struct intel_dp *enabled;
923 struct delayed_work work;
924 unsigned busy_frontbuffer_bits;
930 PCH_NONE = 0, /* No PCH present */
931 PCH_IBX, /* Ibexpeak PCH */
932 PCH_CPT, /* Cougarpoint PCH */
933 PCH_LPT, /* Lynxpoint PCH */
934 PCH_SPT, /* Sunrisepoint PCH */
938 enum intel_sbi_destination {
943 #define QUIRK_PIPEA_FORCE (1<<0)
944 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
945 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
946 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
947 #define QUIRK_PIPEB_FORCE (1<<4)
948 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
951 struct intel_fbc_work;
954 struct i2c_adapter adapter;
958 struct i2c_algo_bit_data bit_algo;
959 struct drm_i915_private *dev_priv;
962 struct i915_suspend_saved_registers {
965 u32 savePP_ON_DELAYS;
966 u32 savePP_OFF_DELAYS;
972 u32 saveCACHE_MODE_0;
973 u32 saveMI_ARB_STATE;
977 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
978 u32 savePCH_PORT_HOTPLUG;
982 struct vlv_s0ix_state {
989 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
990 u32 media_max_req_count;
991 u32 gfx_max_req_count;
1017 u32 rp_down_timeout;
1023 /* Display 1 CZ domain */
1028 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1030 /* GT SA CZ domain */
1037 /* Display 2 CZ domain */
1041 u32 clock_gate_dis2;
1044 struct intel_rps_ei {
1050 struct intel_gen6_power_mgmt {
1052 * work, interrupts_enabled and pm_iir are protected by
1053 * dev_priv->irq_lock
1055 struct work_struct work;
1056 bool interrupts_enabled;
1059 /* Frequencies are stored in potentially platform dependent multiples.
1060 * In other words, *_freq needs to be multiplied by X to be interesting.
1061 * Soft limits are those which are used for the dynamic reclocking done
1062 * by the driver (raise frequencies under heavy loads, and lower for
1063 * lighter loads). Hard limits are those imposed by the hardware.
1065 * A distinction is made for overclocking, which is never enabled by
1066 * default, and is considered to be above the hard limit if it's
1069 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1070 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1071 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1072 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1073 u8 min_freq; /* AKA RPn. Minimum frequency */
1074 u8 idle_freq; /* Frequency to request when we are idle */
1075 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1076 u8 rp1_freq; /* "less than" RP0 power/freqency */
1077 u8 rp0_freq; /* Non-overclocked max frequency. */
1080 u8 up_threshold; /* Current %busy required to uplock */
1081 u8 down_threshold; /* Current %busy required to downclock */
1084 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1087 struct delayed_work delayed_resume_work;
1088 struct list_head clients;
1091 struct intel_rps_client semaphores, mmioflips;
1093 /* manual wa residency calculations */
1094 struct intel_rps_ei up_ei, down_ei;
1097 * Protects RPS/RC6 register access and PCU communication.
1098 * Must be taken after struct_mutex if nested.
1100 struct mutex hw_lock;
1103 /* defined intel_pm.c */
1104 extern spinlock_t mchdev_lock;
1106 struct intel_ilk_power_mgmt {
1114 unsigned long last_time1;
1115 unsigned long chipset_power;
1118 unsigned long gfx_power;
1125 struct drm_i915_private;
1126 struct i915_power_well;
1128 struct i915_power_well_ops {
1130 * Synchronize the well's hw state to match the current sw state, for
1131 * example enable/disable it based on the current refcount. Called
1132 * during driver init and resume time, possibly after first calling
1133 * the enable/disable handlers.
1135 void (*sync_hw)(struct drm_i915_private *dev_priv,
1136 struct i915_power_well *power_well);
1138 * Enable the well and resources that depend on it (for example
1139 * interrupts located on the well). Called after the 0->1 refcount
1142 void (*enable)(struct drm_i915_private *dev_priv,
1143 struct i915_power_well *power_well);
1145 * Disable the well and resources that depend on it. Called after
1146 * the 1->0 refcount transition.
1148 void (*disable)(struct drm_i915_private *dev_priv,
1149 struct i915_power_well *power_well);
1150 /* Returns the hw enabled state. */
1151 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1152 struct i915_power_well *power_well);
1155 /* Power well structure for haswell */
1156 struct i915_power_well {
1159 /* power well enable/disable usage count */
1161 /* cached hw enabled state */
1163 unsigned long domains;
1165 const struct i915_power_well_ops *ops;
1168 struct i915_power_domains {
1170 * Power wells needed for initialization at driver init and suspend
1171 * time are on. They are kept on until after the first modeset.
1175 int power_well_count;
1178 int domain_use_count[POWER_DOMAIN_NUM];
1179 struct i915_power_well *power_wells;
1182 #define MAX_L3_SLICES 2
1183 struct intel_l3_parity {
1184 u32 *remap_info[MAX_L3_SLICES];
1185 struct work_struct error_work;
1189 struct i915_gem_mm {
1190 /** Memory allocator for GTT stolen memory */
1191 struct drm_mm stolen;
1192 /** List of all objects in gtt_space. Used to restore gtt
1193 * mappings on resume */
1194 struct list_head bound_list;
1196 * List of objects which are not bound to the GTT (thus
1197 * are idle and not used by the GPU) but still have
1198 * (presumably uncached) pages still attached.
1200 struct list_head unbound_list;
1202 /** Usable portion of the GTT for GEM */
1203 unsigned long stolen_base; /* limited to low memory (32-bit) */
1205 /** PPGTT used for aliasing the PPGTT with the GTT */
1206 struct i915_hw_ppgtt *aliasing_ppgtt;
1208 struct notifier_block oom_notifier;
1209 struct shrinker shrinker;
1210 bool shrinker_no_lock_stealing;
1212 /** LRU list of objects with fence regs on them. */
1213 struct list_head fence_list;
1216 * We leave the user IRQ off as much as possible,
1217 * but this means that requests will finish and never
1218 * be retired once the system goes idle. Set a timer to
1219 * fire periodically while the ring is running. When it
1220 * fires, go retire requests.
1222 struct delayed_work retire_work;
1225 * When we detect an idle GPU, we want to turn on
1226 * powersaving features. So once we see that there
1227 * are no more requests outstanding and no more
1228 * arrive within a small period of time, we fire
1229 * off the idle_work.
1231 struct delayed_work idle_work;
1234 * Are we in a non-interruptible section of code like
1240 * Is the GPU currently considered idle, or busy executing userspace
1241 * requests? Whilst idle, we attempt to power down the hardware and
1242 * display clocks. In order to reduce the effect on performance, there
1243 * is a slight delay before we do so.
1247 /* the indicator for dispatch video commands on two BSD rings */
1248 int bsd_ring_dispatch_index;
1250 /** Bit 6 swizzling required for X tiling */
1251 uint32_t bit_6_swizzle_x;
1252 /** Bit 6 swizzling required for Y tiling */
1253 uint32_t bit_6_swizzle_y;
1255 /* accounting, useful for userland debugging */
1256 spinlock_t object_stat_lock;
1257 size_t object_memory;
1261 struct drm_i915_error_state_buf {
1262 struct drm_i915_private *i915;
1271 struct i915_error_state_file_priv {
1272 struct drm_device *dev;
1273 struct drm_i915_error_state *error;
1276 struct i915_gpu_error {
1277 /* For hangcheck timer */
1278 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1279 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1280 /* Hang gpu twice in this window and your context gets banned */
1281 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1283 struct workqueue_struct *hangcheck_wq;
1284 struct delayed_work hangcheck_work;
1286 /* For reset and error_state handling. */
1288 /* Protected by the above dev->gpu_error.lock. */
1289 struct drm_i915_error_state *first_error;
1291 unsigned long missed_irq_rings;
1294 * State variable controlling the reset flow and count
1296 * This is a counter which gets incremented when reset is triggered,
1297 * and again when reset has been handled. So odd values (lowest bit set)
1298 * means that reset is in progress and even values that
1299 * (reset_counter >> 1):th reset was successfully completed.
1301 * If reset is not completed succesfully, the I915_WEDGE bit is
1302 * set meaning that hardware is terminally sour and there is no
1303 * recovery. All waiters on the reset_queue will be woken when
1306 * This counter is used by the wait_seqno code to notice that reset
1307 * event happened and it needs to restart the entire ioctl (since most
1308 * likely the seqno it waited for won't ever signal anytime soon).
1310 * This is important for lock-free wait paths, where no contended lock
1311 * naturally enforces the correct ordering between the bail-out of the
1312 * waiter and the gpu reset work code.
1314 atomic_t reset_counter;
1316 #define I915_RESET_IN_PROGRESS_FLAG 1
1317 #define I915_WEDGED (1 << 31)
1320 * Waitqueue to signal when the reset has completed. Used by clients
1321 * that wait for dev_priv->mm.wedged to settle.
1323 wait_queue_head_t reset_queue;
1325 /* Userspace knobs for gpu hang simulation;
1326 * combines both a ring mask, and extra flags
1329 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1330 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1332 /* For missed irq/seqno simulation. */
1333 unsigned int test_irq_rings;
1335 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1336 bool reload_in_reset;
1339 enum modeset_restore {
1340 MODESET_ON_LID_OPEN,
1345 struct ddi_vbt_port_info {
1347 * This is an index in the HDMI/DVI DDI buffer translation table.
1348 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1349 * populate this field.
1351 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1352 uint8_t hdmi_level_shift;
1354 uint8_t supports_dvi:1;
1355 uint8_t supports_hdmi:1;
1356 uint8_t supports_dp:1;
1359 enum psr_lines_to_wait {
1360 PSR_0_LINES_TO_WAIT = 0,
1362 PSR_4_LINES_TO_WAIT,
1366 struct intel_vbt_data {
1367 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1368 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1371 unsigned int int_tv_support:1;
1372 unsigned int lvds_dither:1;
1373 unsigned int lvds_vbt:1;
1374 unsigned int int_crt_support:1;
1375 unsigned int lvds_use_ssc:1;
1376 unsigned int display_clock_mode:1;
1377 unsigned int fdi_rx_polarity_inverted:1;
1378 unsigned int has_mipi:1;
1380 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1382 enum drrs_support_type drrs_type;
1387 int edp_preemphasis;
1389 bool edp_initialized;
1392 struct edp_power_seq edp_pps;
1396 bool require_aux_wakeup;
1398 enum psr_lines_to_wait lines_to_wait;
1399 int tp1_wakeup_time;
1400 int tp2_tp3_wakeup_time;
1406 bool active_low_pwm;
1407 u8 min_brightness; /* min_brightness/255 of max */
1414 struct mipi_config *config;
1415 struct mipi_pps_data *pps;
1419 u8 *sequence[MIPI_SEQ_MAX];
1425 union child_device_config *child_dev;
1427 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1430 enum intel_ddb_partitioning {
1432 INTEL_DDB_PART_5_6, /* IVB+ */
1435 struct intel_wm_level {
1443 struct ilk_wm_values {
1444 uint32_t wm_pipe[3];
1446 uint32_t wm_lp_spr[3];
1447 uint32_t wm_linetime[3];
1449 enum intel_ddb_partitioning partitioning;
1452 struct vlv_wm_values {
1471 struct skl_ddb_entry {
1472 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1475 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1477 return entry->end - entry->start;
1480 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1481 const struct skl_ddb_entry *e2)
1483 if (e1->start == e2->start && e1->end == e2->end)
1489 struct skl_ddb_allocation {
1490 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1491 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1492 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */
1493 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1496 struct skl_wm_values {
1497 bool dirty[I915_MAX_PIPES];
1498 struct skl_ddb_allocation ddb;
1499 uint32_t wm_linetime[I915_MAX_PIPES];
1500 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1501 uint32_t cursor[I915_MAX_PIPES][8];
1502 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1503 uint32_t cursor_trans[I915_MAX_PIPES];
1506 struct skl_wm_level {
1507 bool plane_en[I915_MAX_PLANES];
1509 uint16_t plane_res_b[I915_MAX_PLANES];
1510 uint8_t plane_res_l[I915_MAX_PLANES];
1511 uint16_t cursor_res_b;
1512 uint8_t cursor_res_l;
1516 * This struct helps tracking the state needed for runtime PM, which puts the
1517 * device in PCI D3 state. Notice that when this happens, nothing on the
1518 * graphics device works, even register access, so we don't get interrupts nor
1521 * Every piece of our code that needs to actually touch the hardware needs to
1522 * either call intel_runtime_pm_get or call intel_display_power_get with the
1523 * appropriate power domain.
1525 * Our driver uses the autosuspend delay feature, which means we'll only really
1526 * suspend if we stay with zero refcount for a certain amount of time. The
1527 * default value is currently very conservative (see intel_runtime_pm_enable), but
1528 * it can be changed with the standard runtime PM files from sysfs.
1530 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1531 * goes back to false exactly before we reenable the IRQs. We use this variable
1532 * to check if someone is trying to enable/disable IRQs while they're supposed
1533 * to be disabled. This shouldn't happen and we'll print some error messages in
1536 * For more, read the Documentation/power/runtime_pm.txt.
1538 struct i915_runtime_pm {
1543 enum intel_pipe_crc_source {
1544 INTEL_PIPE_CRC_SOURCE_NONE,
1545 INTEL_PIPE_CRC_SOURCE_PLANE1,
1546 INTEL_PIPE_CRC_SOURCE_PLANE2,
1547 INTEL_PIPE_CRC_SOURCE_PF,
1548 INTEL_PIPE_CRC_SOURCE_PIPE,
1549 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1550 INTEL_PIPE_CRC_SOURCE_TV,
1551 INTEL_PIPE_CRC_SOURCE_DP_B,
1552 INTEL_PIPE_CRC_SOURCE_DP_C,
1553 INTEL_PIPE_CRC_SOURCE_DP_D,
1554 INTEL_PIPE_CRC_SOURCE_AUTO,
1555 INTEL_PIPE_CRC_SOURCE_MAX,
1558 struct intel_pipe_crc_entry {
1563 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1564 struct intel_pipe_crc {
1566 bool opened; /* exclusive access to the result file */
1567 struct intel_pipe_crc_entry *entries;
1568 enum intel_pipe_crc_source source;
1570 wait_queue_head_t wq;
1573 struct i915_frontbuffer_tracking {
1577 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1584 struct i915_wa_reg {
1587 /* bitmask representing WA bits */
1591 #define I915_MAX_WA_REGS 16
1593 struct i915_workarounds {
1594 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1598 struct i915_virtual_gpu {
1602 struct drm_i915_private {
1603 struct drm_device *dev;
1604 struct kmem_cache *objects;
1605 struct kmem_cache *vmas;
1606 struct kmem_cache *requests;
1608 const struct intel_device_info info;
1610 int relative_constants_mode;
1614 struct intel_uncore uncore;
1616 struct i915_virtual_gpu vgpu;
1618 struct intel_csr csr;
1620 /* Display CSR-related protection */
1621 struct mutex csr_lock;
1623 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1625 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1626 * controller on different i2c buses. */
1627 struct mutex gmbus_mutex;
1630 * Base address of the gmbus and gpio block.
1632 uint32_t gpio_mmio_base;
1634 /* MMIO base address for MIPI regs */
1635 uint32_t mipi_mmio_base;
1637 wait_queue_head_t gmbus_wait_queue;
1639 struct pci_dev *bridge_dev;
1640 struct intel_engine_cs ring[I915_NUM_RINGS];
1641 struct drm_i915_gem_object *semaphore_obj;
1642 uint32_t last_seqno, next_seqno;
1644 struct drm_dma_handle *status_page_dmah;
1645 struct resource mch_res;
1647 /* protects the irq masks */
1648 spinlock_t irq_lock;
1650 /* protects the mmio flip data */
1651 spinlock_t mmio_flip_lock;
1653 bool display_irqs_enabled;
1655 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1656 struct pm_qos_request pm_qos;
1658 /* DPIO indirect register protection */
1659 struct mutex dpio_lock;
1661 /** Cached value of IMR to avoid reads in updating the bitfield */
1664 u32 de_irq_mask[I915_MAX_PIPES];
1669 u32 pipestat_irq_mask[I915_MAX_PIPES];
1671 struct work_struct hotplug_work;
1673 unsigned long hpd_last_jiffies;
1678 HPD_MARK_DISABLED = 2
1680 } hpd_stats[HPD_NUM_PINS];
1682 struct delayed_work hotplug_reenable_work;
1684 struct i915_fbc fbc;
1685 struct i915_drrs drrs;
1686 struct intel_opregion opregion;
1687 struct intel_vbt_data vbt;
1689 bool preserve_bios_swizzle;
1692 struct intel_overlay *overlay;
1694 /* backlight registers and fields in struct intel_panel */
1695 struct mutex backlight_lock;
1698 bool no_aux_handshake;
1700 /* protects panel power sequencer state */
1701 struct mutex pps_mutex;
1703 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1704 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1705 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1707 unsigned int fsb_freq, mem_freq, is_ddr3;
1708 unsigned int cdclk_freq;
1709 unsigned int hpll_freq;
1712 * wq - Driver workqueue for GEM.
1714 * NOTE: Work items scheduled here are not allowed to grab any modeset
1715 * locks, for otherwise the flushing done in the pageflip code will
1716 * result in deadlocks.
1718 struct workqueue_struct *wq;
1720 /* Display functions */
1721 struct drm_i915_display_funcs display;
1723 /* PCH chipset type */
1724 enum intel_pch pch_type;
1725 unsigned short pch_id;
1727 unsigned long quirks;
1729 enum modeset_restore modeset_restore;
1730 struct mutex modeset_restore_lock;
1732 struct list_head vm_list; /* Global list of all address spaces */
1733 struct i915_gtt gtt; /* VM representing the global address space */
1735 struct i915_gem_mm mm;
1736 DECLARE_HASHTABLE(mm_structs, 7);
1737 struct mutex mm_lock;
1739 /* Kernel Modesetting */
1741 struct sdvo_device_mapping sdvo_mappings[2];
1743 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1744 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1745 wait_queue_head_t pending_flip_queue;
1747 #ifdef CONFIG_DEBUG_FS
1748 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1751 int num_shared_dpll;
1752 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1753 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1755 struct i915_workarounds workarounds;
1757 /* Reclocking support */
1758 bool render_reclock_avail;
1759 bool lvds_downclock_avail;
1760 /* indicates the reduced downclock for LVDS*/
1763 struct i915_frontbuffer_tracking fb_tracking;
1767 bool mchbar_need_disable;
1769 struct intel_l3_parity l3_parity;
1771 /* Cannot be determined by PCIID. You must always read a register. */
1774 /* gen6+ rps state */
1775 struct intel_gen6_power_mgmt rps;
1777 /* ilk-only ips/rps state. Everything in here is protected by the global
1778 * mchdev_lock in intel_pm.c */
1779 struct intel_ilk_power_mgmt ips;
1781 struct i915_power_domains power_domains;
1783 struct i915_psr psr;
1785 struct i915_gpu_error gpu_error;
1787 struct drm_i915_gem_object *vlv_pctx;
1789 #ifdef CONFIG_DRM_I915_FBDEV
1790 /* list of fbdev register on this device */
1791 struct intel_fbdev *fbdev;
1792 struct work_struct fbdev_suspend_work;
1795 struct drm_property *broadcast_rgb_property;
1796 struct drm_property *force_audio_property;
1798 /* hda/i915 audio component */
1799 bool audio_component_registered;
1801 uint32_t hw_context_size;
1802 struct list_head context_list;
1806 u32 chv_phy_control;
1809 struct i915_suspend_saved_registers regfile;
1810 struct vlv_s0ix_state vlv_s0ix_state;
1814 * Raw watermark latency values:
1815 * in 0.1us units for WM0,
1816 * in 0.5us units for WM1+.
1819 uint16_t pri_latency[5];
1821 uint16_t spr_latency[5];
1823 uint16_t cur_latency[5];
1825 * Raw watermark memory latency values
1826 * for SKL for all 8 levels
1829 uint16_t skl_latency[8];
1832 * The skl_wm_values structure is a bit too big for stack
1833 * allocation, so we keep the staging struct where we store
1834 * intermediate results here instead.
1836 struct skl_wm_values skl_results;
1838 /* current hardware state */
1840 struct ilk_wm_values hw;
1841 struct skl_wm_values skl_hw;
1842 struct vlv_wm_values vlv;
1846 struct i915_runtime_pm pm;
1848 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1849 u32 long_hpd_port_mask;
1850 u32 short_hpd_port_mask;
1851 struct work_struct dig_port_work;
1854 * if we get a HPD irq from DP and a HPD irq from non-DP
1855 * the non-DP HPD could block the workqueue on a mode config
1856 * mutex getting, that userspace may have taken. However
1857 * userspace is waiting on the DP workqueue to run which is
1858 * blocked behind the non-DP one.
1860 struct workqueue_struct *dp_wq;
1862 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1864 int (*execbuf_submit)(struct drm_device *dev, struct drm_file *file,
1865 struct intel_engine_cs *ring,
1866 struct intel_context *ctx,
1867 struct drm_i915_gem_execbuffer2 *args,
1868 struct list_head *vmas,
1869 struct drm_i915_gem_object *batch_obj,
1870 u64 exec_start, u32 flags);
1871 int (*init_rings)(struct drm_device *dev);
1872 void (*cleanup_ring)(struct intel_engine_cs *ring);
1873 void (*stop_ring)(struct intel_engine_cs *ring);
1876 bool edp_low_vswing;
1879 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1880 * will be rejected. Instead look for a better place.
1884 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1886 return dev->dev_private;
1889 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1891 return to_i915(dev_get_drvdata(dev));
1894 /* Iterate over initialised rings */
1895 #define for_each_ring(ring__, dev_priv__, i__) \
1896 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1897 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1899 enum hdmi_force_audio {
1900 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1901 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1902 HDMI_AUDIO_AUTO, /* trust EDID */
1903 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1906 #define I915_GTT_OFFSET_NONE ((u32)-1)
1908 struct drm_i915_gem_object_ops {
1909 /* Interface between the GEM object and its backing storage.
1910 * get_pages() is called once prior to the use of the associated set
1911 * of pages before to binding them into the GTT, and put_pages() is
1912 * called after we no longer need them. As we expect there to be
1913 * associated cost with migrating pages between the backing storage
1914 * and making them available for the GPU (e.g. clflush), we may hold
1915 * onto the pages after they are no longer referenced by the GPU
1916 * in case they may be used again shortly (for example migrating the
1917 * pages to a different memory domain within the GTT). put_pages()
1918 * will therefore most likely be called when the object itself is
1919 * being released or under memory pressure (where we attempt to
1920 * reap pages for the shrinker).
1922 int (*get_pages)(struct drm_i915_gem_object *);
1923 void (*put_pages)(struct drm_i915_gem_object *);
1924 int (*dmabuf_export)(struct drm_i915_gem_object *);
1925 void (*release)(struct drm_i915_gem_object *);
1929 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1930 * considered to be the frontbuffer for the given plane interface-vise. This
1931 * doesn't mean that the hw necessarily already scans it out, but that any
1932 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1934 * We have one bit per pipe and per scanout plane type.
1936 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1937 #define INTEL_FRONTBUFFER_BITS \
1938 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1939 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1940 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1941 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1942 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1943 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1944 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1945 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1946 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1947 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1948 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1950 struct drm_i915_gem_object {
1951 struct drm_gem_object base;
1953 const struct drm_i915_gem_object_ops *ops;
1955 /** List of VMAs backed by this object */
1956 struct list_head vma_list;
1958 /** Stolen memory for this object, instead of being backed by shmem. */
1959 struct drm_mm_node *stolen;
1960 struct list_head global_list;
1962 struct list_head ring_list[I915_NUM_RINGS];
1963 /** Used in execbuf to temporarily hold a ref */
1964 struct list_head obj_exec_link;
1966 struct list_head batch_pool_link;
1969 * This is set if the object is on the active lists (has pending
1970 * rendering and so a non-zero seqno), and is not set if it i s on
1971 * inactive (ready to be unbound) list.
1973 unsigned int active:I915_NUM_RINGS;
1976 * This is set if the object has been written to since last bound
1979 unsigned int dirty:1;
1982 * Fence register bits (if any) for this object. Will be set
1983 * as needed when mapped into the GTT.
1984 * Protected by dev->struct_mutex.
1986 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1989 * Advice: are the backing pages purgeable?
1991 unsigned int madv:2;
1994 * Current tiling mode for the object.
1996 unsigned int tiling_mode:2;
1998 * Whether the tiling parameters for the currently associated fence
1999 * register have changed. Note that for the purposes of tracking
2000 * tiling changes we also treat the unfenced register, the register
2001 * slot that the object occupies whilst it executes a fenced
2002 * command (such as BLT on gen2/3), as a "fence".
2004 unsigned int fence_dirty:1;
2007 * Is the object at the current location in the gtt mappable and
2008 * fenceable? Used to avoid costly recalculations.
2010 unsigned int map_and_fenceable:1;
2013 * Whether the current gtt mapping needs to be mappable (and isn't just
2014 * mappable by accident). Track pin and fault separate for a more
2015 * accurate mappable working set.
2017 unsigned int fault_mappable:1;
2020 * Is the object to be mapped as read-only to the GPU
2021 * Only honoured if hardware has relevant pte bit
2023 unsigned long gt_ro:1;
2024 unsigned int cache_level:3;
2025 unsigned int cache_dirty:1;
2027 unsigned int has_dma_mapping:1;
2029 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2031 unsigned int pin_display;
2033 struct sg_table *pages;
2034 int pages_pin_count;
2036 struct scatterlist *sg;
2040 /* prime dma-buf support */
2041 void *dma_buf_vmapping;
2044 /** Breadcrumb of last rendering to the buffer.
2045 * There can only be one writer, but we allow for multiple readers.
2046 * If there is a writer that necessarily implies that all other
2047 * read requests are complete - but we may only be lazily clearing
2048 * the read requests. A read request is naturally the most recent
2049 * request on a ring, so we may have two different write and read
2050 * requests on one ring where the write request is older than the
2051 * read request. This allows for the CPU to read from an active
2052 * buffer by only waiting for the write to complete.
2054 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2055 struct drm_i915_gem_request *last_write_req;
2056 /** Breadcrumb of last fenced GPU access to the buffer. */
2057 struct drm_i915_gem_request *last_fenced_req;
2059 /** Current tiling stride for the object, if it's tiled. */
2062 /** References from framebuffers, locks out tiling changes. */
2063 unsigned long framebuffer_references;
2065 /** Record of address bit 17 of each page at last unbind. */
2066 unsigned long *bit_17;
2069 /** for phy allocated objects */
2070 struct drm_dma_handle *phys_handle;
2072 struct i915_gem_userptr {
2074 unsigned read_only :1;
2075 unsigned workers :4;
2076 #define I915_GEM_USERPTR_MAX_WORKERS 15
2078 struct i915_mm_struct *mm;
2079 struct i915_mmu_object *mmu_object;
2080 struct work_struct *work;
2084 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2086 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2087 struct drm_i915_gem_object *new,
2088 unsigned frontbuffer_bits);
2091 * Request queue structure.
2093 * The request queue allows us to note sequence numbers that have been emitted
2094 * and may be associated with active buffers to be retired.
2096 * By keeping this list, we can avoid having to do questionable sequence
2097 * number comparisons on buffer last_read|write_seqno. It also allows an
2098 * emission time to be associated with the request for tracking how far ahead
2099 * of the GPU the submission is.
2101 * The requests are reference counted, so upon creation they should have an
2102 * initial reference taken using kref_init
2104 struct drm_i915_gem_request {
2107 /** On Which ring this request was generated */
2108 struct drm_i915_private *i915;
2109 struct intel_engine_cs *ring;
2111 /** GEM sequence number associated with this request. */
2114 /** Position in the ringbuffer of the start of the request */
2118 * Position in the ringbuffer of the start of the postfix.
2119 * This is required to calculate the maximum available ringbuffer
2120 * space without overwriting the postfix.
2124 /** Position in the ringbuffer of the end of the whole request */
2128 * Context and ring buffer related to this request
2129 * Contexts are refcounted, so when this request is associated with a
2130 * context, we must increment the context's refcount, to guarantee that
2131 * it persists while any request is linked to it. Requests themselves
2132 * are also refcounted, so the request will only be freed when the last
2133 * reference to it is dismissed, and the code in
2134 * i915_gem_request_free() will then decrement the refcount on the
2137 struct intel_context *ctx;
2138 struct intel_ringbuffer *ringbuf;
2140 /** Batch buffer related to this request if any */
2141 struct drm_i915_gem_object *batch_obj;
2143 /** Time at which this request was emitted, in jiffies. */
2144 unsigned long emitted_jiffies;
2146 /** global list entry for this request */
2147 struct list_head list;
2149 struct drm_i915_file_private *file_priv;
2150 /** file_priv list entry for this request */
2151 struct list_head client_list;
2153 /** process identifier submitting this request */
2157 * The ELSP only accepts two elements at a time, so we queue
2158 * context/tail pairs on a given queue (ring->execlist_queue) until the
2159 * hardware is available. The queue serves a double purpose: we also use
2160 * it to keep track of the up to 2 contexts currently in the hardware
2161 * (usually one in execution and the other queued up by the GPU): We
2162 * only remove elements from the head of the queue when the hardware
2163 * informs us that an element has been completed.
2165 * All accesses to the queue are mediated by a spinlock
2166 * (ring->execlist_lock).
2169 /** Execlist link in the submission queue.*/
2170 struct list_head execlist_link;
2172 /** Execlists no. of times this request has been sent to the ELSP */
2177 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2178 struct intel_context *ctx);
2179 void i915_gem_request_free(struct kref *req_ref);
2181 static inline uint32_t
2182 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2184 return req ? req->seqno : 0;
2187 static inline struct intel_engine_cs *
2188 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2190 return req ? req->ring : NULL;
2193 static inline struct drm_i915_gem_request *
2194 i915_gem_request_reference(struct drm_i915_gem_request *req)
2197 kref_get(&req->ref);
2202 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2204 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2205 kref_put(&req->ref, i915_gem_request_free);
2209 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2211 struct drm_device *dev;
2216 dev = req->ring->dev;
2217 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2218 mutex_unlock(&dev->struct_mutex);
2221 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2222 struct drm_i915_gem_request *src)
2225 i915_gem_request_reference(src);
2228 i915_gem_request_unreference(*pdst);
2234 * XXX: i915_gem_request_completed should be here but currently needs the
2235 * definition of i915_seqno_passed() which is below. It will be moved in
2236 * a later patch when the call to i915_seqno_passed() is obsoleted...
2240 * A command that requires special handling by the command parser.
2242 struct drm_i915_cmd_descriptor {
2244 * Flags describing how the command parser processes the command.
2246 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2247 * a length mask if not set
2248 * CMD_DESC_SKIP: The command is allowed but does not follow the
2249 * standard length encoding for the opcode range in
2251 * CMD_DESC_REJECT: The command is never allowed
2252 * CMD_DESC_REGISTER: The command should be checked against the
2253 * register whitelist for the appropriate ring
2254 * CMD_DESC_MASTER: The command is allowed if the submitting process
2258 #define CMD_DESC_FIXED (1<<0)
2259 #define CMD_DESC_SKIP (1<<1)
2260 #define CMD_DESC_REJECT (1<<2)
2261 #define CMD_DESC_REGISTER (1<<3)
2262 #define CMD_DESC_BITMASK (1<<4)
2263 #define CMD_DESC_MASTER (1<<5)
2266 * The command's unique identification bits and the bitmask to get them.
2267 * This isn't strictly the opcode field as defined in the spec and may
2268 * also include type, subtype, and/or subop fields.
2276 * The command's length. The command is either fixed length (i.e. does
2277 * not include a length field) or has a length field mask. The flag
2278 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2279 * a length mask. All command entries in a command table must include
2280 * length information.
2288 * Describes where to find a register address in the command to check
2289 * against the ring's register whitelist. Only valid if flags has the
2290 * CMD_DESC_REGISTER bit set.
2297 #define MAX_CMD_DESC_BITMASKS 3
2299 * Describes command checks where a particular dword is masked and
2300 * compared against an expected value. If the command does not match
2301 * the expected value, the parser rejects it. Only valid if flags has
2302 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2305 * If the check specifies a non-zero condition_mask then the parser
2306 * only performs the check when the bits specified by condition_mask
2313 u32 condition_offset;
2315 } bits[MAX_CMD_DESC_BITMASKS];
2319 * A table of commands requiring special handling by the command parser.
2321 * Each ring has an array of tables. Each table consists of an array of command
2322 * descriptors, which must be sorted with command opcodes in ascending order.
2324 struct drm_i915_cmd_table {
2325 const struct drm_i915_cmd_descriptor *table;
2329 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2330 #define __I915__(p) ({ \
2331 struct drm_i915_private *__p; \
2332 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2333 __p = (struct drm_i915_private *)p; \
2334 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2335 __p = to_i915((struct drm_device *)p); \
2340 #define INTEL_INFO(p) (&__I915__(p)->info)
2341 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2342 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2344 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2345 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2346 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2347 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2348 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2349 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2350 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2351 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2352 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2353 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2354 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2355 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2356 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2357 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2358 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2359 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2360 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2361 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2362 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2363 INTEL_DEVID(dev) == 0x0152 || \
2364 INTEL_DEVID(dev) == 0x015a)
2365 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2366 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2367 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2368 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2369 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2370 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2371 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2372 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2373 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2374 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2375 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2376 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2377 (INTEL_DEVID(dev) & 0xf) == 0xe))
2378 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2379 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2380 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2381 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2382 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2383 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2384 /* ULX machines are also considered ULT. */
2385 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2386 INTEL_DEVID(dev) == 0x0A1E)
2387 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2389 #define SKL_REVID_A0 (0x0)
2390 #define SKL_REVID_B0 (0x1)
2391 #define SKL_REVID_C0 (0x2)
2392 #define SKL_REVID_D0 (0x3)
2393 #define SKL_REVID_E0 (0x4)
2394 #define SKL_REVID_F0 (0x5)
2396 #define BXT_REVID_A0 (0x0)
2397 #define BXT_REVID_B0 (0x3)
2398 #define BXT_REVID_C0 (0x6)
2401 * The genX designation typically refers to the render engine, so render
2402 * capability related checks should use IS_GEN, while display and other checks
2403 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2406 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2407 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2408 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2409 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2410 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2411 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2412 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2413 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2415 #define RENDER_RING (1<<RCS)
2416 #define BSD_RING (1<<VCS)
2417 #define BLT_RING (1<<BCS)
2418 #define VEBOX_RING (1<<VECS)
2419 #define BSD2_RING (1<<VCS2)
2420 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2421 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2422 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2423 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2424 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2425 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2426 __I915__(dev)->ellc_size)
2427 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2429 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2430 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2431 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2432 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2434 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2435 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2437 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2438 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2440 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2441 * even when in MSI mode. This results in spurious interrupt warnings if the
2442 * legacy irq no. is shared with another device. The kernel then disables that
2443 * interrupt source and so prevents the other device from working properly.
2445 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2446 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2448 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2449 * rows, which changed the alignment requirements and fence programming.
2451 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2453 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2454 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2455 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2456 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2457 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2459 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2460 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2461 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2463 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2465 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2466 INTEL_INFO(dev)->gen >= 9)
2468 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2469 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2470 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2471 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2473 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2474 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2476 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2477 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2479 #define HAS_CSR(dev) (IS_SKYLAKE(dev))
2481 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2482 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2483 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2484 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2485 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2486 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2487 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2488 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2490 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2491 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2492 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2493 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2494 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2495 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2496 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2498 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2500 /* DPF == dynamic parity feature */
2501 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2502 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2504 #define GT_FREQUENCY_MULTIPLIER 50
2505 #define GEN9_FREQ_SCALER 3
2507 #include "i915_trace.h"
2509 extern const struct drm_ioctl_desc i915_ioctls[];
2510 extern int i915_max_ioctl;
2512 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2513 extern int i915_resume_legacy(struct drm_device *dev);
2516 struct i915_params {
2518 int panel_ignore_lid;
2520 unsigned int lvds_downclock;
2521 int lvds_channel_mode;
2523 int vbt_sdvo_panel_type;
2527 int enable_execlists;
2529 unsigned int preliminary_hw_support;
2530 int disable_power_well;
2532 int invert_brightness;
2533 int enable_cmd_parser;
2534 /* leave bools at the end to not create holes */
2535 bool enable_hangcheck;
2537 bool prefault_disable;
2538 bool load_detect_test;
2540 bool disable_display;
2541 bool disable_vtd_wa;
2544 bool verbose_state_checks;
2545 bool nuclear_pageflip;
2548 extern struct i915_params i915 __read_mostly;
2551 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2552 extern int i915_driver_unload(struct drm_device *);
2553 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2554 extern void i915_driver_lastclose(struct drm_device * dev);
2555 extern void i915_driver_preclose(struct drm_device *dev,
2556 struct drm_file *file);
2557 extern void i915_driver_postclose(struct drm_device *dev,
2558 struct drm_file *file);
2559 extern int i915_driver_device_is_agp(struct drm_device * dev);
2560 #ifdef CONFIG_COMPAT
2561 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2564 extern int intel_gpu_reset(struct drm_device *dev);
2565 extern int i915_reset(struct drm_device *dev);
2566 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2567 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2568 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2569 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2570 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2571 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2572 void i915_firmware_load_error_print(const char *fw_path, int err);
2575 void i915_queue_hangcheck(struct drm_device *dev);
2577 void i915_handle_error(struct drm_device *dev, bool wedged,
2578 const char *fmt, ...);
2580 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2581 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2582 int intel_irq_install(struct drm_i915_private *dev_priv);
2583 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2585 extern void intel_uncore_sanitize(struct drm_device *dev);
2586 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2587 bool restore_forcewake);
2588 extern void intel_uncore_init(struct drm_device *dev);
2589 extern void intel_uncore_check_errors(struct drm_device *dev);
2590 extern void intel_uncore_fini(struct drm_device *dev);
2591 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2592 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2593 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2594 enum forcewake_domains domains);
2595 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2596 enum forcewake_domains domains);
2597 /* Like above but the caller must manage the uncore.lock itself.
2598 * Must be used with I915_READ_FW and friends.
2600 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2601 enum forcewake_domains domains);
2602 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2603 enum forcewake_domains domains);
2604 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2605 static inline bool intel_vgpu_active(struct drm_device *dev)
2607 return to_i915(dev)->vgpu.active;
2611 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2615 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2618 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2619 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2621 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2623 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2624 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2625 uint32_t interrupt_mask,
2626 uint32_t enabled_irq_mask);
2627 #define ibx_enable_display_interrupt(dev_priv, bits) \
2628 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2629 #define ibx_disable_display_interrupt(dev_priv, bits) \
2630 ibx_display_interrupt_update((dev_priv), (bits), 0)
2633 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2634 struct drm_file *file_priv);
2635 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2636 struct drm_file *file_priv);
2637 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2638 struct drm_file *file_priv);
2639 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2640 struct drm_file *file_priv);
2641 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2642 struct drm_file *file_priv);
2643 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2644 struct drm_file *file_priv);
2645 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2646 struct drm_file *file_priv);
2647 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2648 struct intel_engine_cs *ring);
2649 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2650 struct drm_file *file,
2651 struct intel_engine_cs *ring,
2652 struct drm_i915_gem_object *obj);
2653 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2654 struct drm_file *file,
2655 struct intel_engine_cs *ring,
2656 struct intel_context *ctx,
2657 struct drm_i915_gem_execbuffer2 *args,
2658 struct list_head *vmas,
2659 struct drm_i915_gem_object *batch_obj,
2660 u64 exec_start, u32 flags);
2661 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2662 struct drm_file *file_priv);
2663 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2664 struct drm_file *file_priv);
2665 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2666 struct drm_file *file_priv);
2667 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2668 struct drm_file *file);
2669 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2670 struct drm_file *file);
2671 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2672 struct drm_file *file_priv);
2673 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2674 struct drm_file *file_priv);
2675 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2676 struct drm_file *file_priv);
2677 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2678 struct drm_file *file_priv);
2679 int i915_gem_init_userptr(struct drm_device *dev);
2680 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2681 struct drm_file *file);
2682 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2683 struct drm_file *file_priv);
2684 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2685 struct drm_file *file_priv);
2686 void i915_gem_load(struct drm_device *dev);
2687 void *i915_gem_object_alloc(struct drm_device *dev);
2688 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2689 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2690 const struct drm_i915_gem_object_ops *ops);
2691 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2693 void i915_init_vm(struct drm_i915_private *dev_priv,
2694 struct i915_address_space *vm);
2695 void i915_gem_free_object(struct drm_gem_object *obj);
2696 void i915_gem_vma_destroy(struct i915_vma *vma);
2698 /* Flags used by pin/bind&friends. */
2699 #define PIN_MAPPABLE (1<<0)
2700 #define PIN_NONBLOCK (1<<1)
2701 #define PIN_GLOBAL (1<<2)
2702 #define PIN_OFFSET_BIAS (1<<3)
2703 #define PIN_USER (1<<4)
2704 #define PIN_UPDATE (1<<5)
2705 #define PIN_OFFSET_MASK (~4095)
2707 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2708 struct i915_address_space *vm,
2712 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2713 const struct i915_ggtt_view *view,
2717 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2719 int __must_check i915_vma_unbind(struct i915_vma *vma);
2720 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2721 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2722 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2724 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2725 int *needs_clflush);
2727 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2729 static inline int __sg_page_count(struct scatterlist *sg)
2731 return sg->length >> PAGE_SHIFT;
2734 static inline struct page *
2735 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2737 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2740 if (n < obj->get_page.last) {
2741 obj->get_page.sg = obj->pages->sgl;
2742 obj->get_page.last = 0;
2745 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2746 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2747 if (unlikely(sg_is_chain(obj->get_page.sg)))
2748 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2751 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2754 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2756 BUG_ON(obj->pages == NULL);
2757 obj->pages_pin_count++;
2759 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2761 BUG_ON(obj->pages_pin_count == 0);
2762 obj->pages_pin_count--;
2765 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2766 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2767 struct intel_engine_cs *to);
2768 void i915_vma_move_to_active(struct i915_vma *vma,
2769 struct intel_engine_cs *ring);
2770 int i915_gem_dumb_create(struct drm_file *file_priv,
2771 struct drm_device *dev,
2772 struct drm_mode_create_dumb *args);
2773 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2774 uint32_t handle, uint64_t *offset);
2776 * Returns true if seq1 is later than seq2.
2779 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2781 return (int32_t)(seq1 - seq2) >= 0;
2784 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2785 bool lazy_coherency)
2789 BUG_ON(req == NULL);
2791 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2793 return i915_seqno_passed(seqno, req->seqno);
2796 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2797 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2798 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2799 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2801 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2802 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2804 struct drm_i915_gem_request *
2805 i915_gem_find_active_request(struct intel_engine_cs *ring);
2807 bool i915_gem_retire_requests(struct drm_device *dev);
2808 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2809 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2810 bool interruptible);
2811 int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
2813 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2815 return unlikely(atomic_read(&error->reset_counter)
2816 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2819 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2821 return atomic_read(&error->reset_counter) & I915_WEDGED;
2824 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2826 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2829 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2831 return dev_priv->gpu_error.stop_rings == 0 ||
2832 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2835 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2837 return dev_priv->gpu_error.stop_rings == 0 ||
2838 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2841 void i915_gem_reset(struct drm_device *dev);
2842 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2843 int __must_check i915_gem_init(struct drm_device *dev);
2844 int i915_gem_init_rings(struct drm_device *dev);
2845 int __must_check i915_gem_init_hw(struct drm_device *dev);
2846 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2847 void i915_gem_init_swizzling(struct drm_device *dev);
2848 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2849 int __must_check i915_gpu_idle(struct drm_device *dev);
2850 int __must_check i915_gem_suspend(struct drm_device *dev);
2851 int __i915_add_request(struct intel_engine_cs *ring,
2852 struct drm_file *file,
2853 struct drm_i915_gem_object *batch_obj);
2854 #define i915_add_request(ring) \
2855 __i915_add_request(ring, NULL, NULL)
2856 int __i915_wait_request(struct drm_i915_gem_request *req,
2857 unsigned reset_counter,
2860 struct intel_rps_client *rps);
2861 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2862 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2864 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2867 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2870 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2872 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2874 struct intel_engine_cs *pipelined,
2875 const struct i915_ggtt_view *view);
2876 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2877 const struct i915_ggtt_view *view);
2878 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2880 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2881 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2884 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2886 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2887 int tiling_mode, bool fenced);
2889 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2890 enum i915_cache_level cache_level);
2892 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2893 struct dma_buf *dma_buf);
2895 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2896 struct drm_gem_object *gem_obj, int flags);
2898 void i915_gem_restore_fences(struct drm_device *dev);
2901 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
2902 const struct i915_ggtt_view *view);
2904 i915_gem_obj_offset(struct drm_i915_gem_object *o,
2905 struct i915_address_space *vm);
2906 static inline unsigned long
2907 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
2909 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
2912 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2913 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
2914 const struct i915_ggtt_view *view);
2915 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2916 struct i915_address_space *vm);
2918 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2919 struct i915_address_space *vm);
2921 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2922 struct i915_address_space *vm);
2924 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
2925 const struct i915_ggtt_view *view);
2928 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2929 struct i915_address_space *vm);
2931 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2932 const struct i915_ggtt_view *view);
2934 static inline struct i915_vma *
2935 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
2937 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
2939 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
2941 /* Some GGTT VM helpers */
2942 #define i915_obj_to_ggtt(obj) \
2943 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2944 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2946 struct i915_address_space *ggtt =
2947 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2951 static inline struct i915_hw_ppgtt *
2952 i915_vm_to_ppgtt(struct i915_address_space *vm)
2954 WARN_ON(i915_is_ggtt(vm));
2956 return container_of(vm, struct i915_hw_ppgtt, base);
2960 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2962 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
2965 static inline unsigned long
2966 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2968 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2971 static inline int __must_check
2972 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2976 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2977 alignment, flags | PIN_GLOBAL);
2981 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2983 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2986 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
2987 const struct i915_ggtt_view *view);
2989 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
2991 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
2994 /* i915_gem_context.c */
2995 int __must_check i915_gem_context_init(struct drm_device *dev);
2996 void i915_gem_context_fini(struct drm_device *dev);
2997 void i915_gem_context_reset(struct drm_device *dev);
2998 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2999 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
3000 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3001 int i915_switch_context(struct intel_engine_cs *ring,
3002 struct intel_context *to);
3003 struct intel_context *
3004 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3005 void i915_gem_context_free(struct kref *ctx_ref);
3006 struct drm_i915_gem_object *
3007 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3008 static inline void i915_gem_context_reference(struct intel_context *ctx)
3010 kref_get(&ctx->ref);
3013 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3015 kref_put(&ctx->ref, i915_gem_context_free);
3018 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3020 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3023 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3024 struct drm_file *file);
3025 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3026 struct drm_file *file);
3027 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3028 struct drm_file *file_priv);
3029 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3030 struct drm_file *file_priv);
3032 /* i915_gem_evict.c */
3033 int __must_check i915_gem_evict_something(struct drm_device *dev,
3034 struct i915_address_space *vm,
3037 unsigned cache_level,
3038 unsigned long start,
3041 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3042 int i915_gem_evict_everything(struct drm_device *dev);
3044 /* belongs in i915_gem_gtt.h */
3045 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3047 if (INTEL_INFO(dev)->gen < 6)
3048 intel_gtt_chipset_flush();
3051 /* i915_gem_stolen.c */
3052 int i915_gem_init_stolen(struct drm_device *dev);
3053 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
3054 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
3055 void i915_gem_cleanup_stolen(struct drm_device *dev);
3056 struct drm_i915_gem_object *
3057 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3058 struct drm_i915_gem_object *
3059 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3064 /* i915_gem_shrinker.c */
3065 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3068 #define I915_SHRINK_PURGEABLE 0x1
3069 #define I915_SHRINK_UNBOUND 0x2
3070 #define I915_SHRINK_BOUND 0x4
3071 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3072 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3075 /* i915_gem_tiling.c */
3076 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3078 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3080 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3081 obj->tiling_mode != I915_TILING_NONE;
3084 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3085 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3086 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3088 /* i915_gem_debug.c */
3090 int i915_verify_lists(struct drm_device *dev);
3092 #define i915_verify_lists(dev) 0
3095 /* i915_debugfs.c */
3096 int i915_debugfs_init(struct drm_minor *minor);
3097 void i915_debugfs_cleanup(struct drm_minor *minor);
3098 #ifdef CONFIG_DEBUG_FS
3099 int i915_debugfs_connector_add(struct drm_connector *connector);
3100 void intel_display_crc_init(struct drm_device *dev);
3102 static inline int i915_debugfs_connector_add(struct drm_connector *connector) {}
3103 static inline void intel_display_crc_init(struct drm_device *dev) {}
3106 /* i915_gpu_error.c */
3108 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3109 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3110 const struct i915_error_state_file_priv *error);
3111 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3112 struct drm_i915_private *i915,
3113 size_t count, loff_t pos);
3114 static inline void i915_error_state_buf_release(
3115 struct drm_i915_error_state_buf *eb)
3119 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3120 const char *error_msg);
3121 void i915_error_state_get(struct drm_device *dev,
3122 struct i915_error_state_file_priv *error_priv);
3123 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3124 void i915_destroy_error_state(struct drm_device *dev);
3126 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3127 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3129 /* i915_cmd_parser.c */
3130 int i915_cmd_parser_get_version(void);
3131 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3132 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3133 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3134 int i915_parse_cmds(struct intel_engine_cs *ring,
3135 struct drm_i915_gem_object *batch_obj,
3136 struct drm_i915_gem_object *shadow_batch_obj,
3137 u32 batch_start_offset,
3141 /* i915_suspend.c */
3142 extern int i915_save_state(struct drm_device *dev);
3143 extern int i915_restore_state(struct drm_device *dev);
3146 void i915_setup_sysfs(struct drm_device *dev_priv);
3147 void i915_teardown_sysfs(struct drm_device *dev_priv);
3150 extern int intel_setup_gmbus(struct drm_device *dev);
3151 extern void intel_teardown_gmbus(struct drm_device *dev);
3152 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3155 extern struct i2c_adapter *
3156 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3157 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3158 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3159 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3161 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3163 extern void intel_i2c_reset(struct drm_device *dev);
3165 /* intel_opregion.c */
3167 extern int intel_opregion_setup(struct drm_device *dev);
3168 extern void intel_opregion_init(struct drm_device *dev);
3169 extern void intel_opregion_fini(struct drm_device *dev);
3170 extern void intel_opregion_asle_intr(struct drm_device *dev);
3171 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3173 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3176 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3177 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3178 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3179 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3181 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3186 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3194 extern void intel_register_dsm_handler(void);
3195 extern void intel_unregister_dsm_handler(void);
3197 static inline void intel_register_dsm_handler(void) { return; }
3198 static inline void intel_unregister_dsm_handler(void) { return; }
3199 #endif /* CONFIG_ACPI */
3202 extern void intel_modeset_init_hw(struct drm_device *dev);
3203 extern void intel_modeset_init(struct drm_device *dev);
3204 extern void intel_modeset_gem_init(struct drm_device *dev);
3205 extern void intel_modeset_cleanup(struct drm_device *dev);
3206 extern void intel_connector_unregister(struct intel_connector *);
3207 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3208 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3209 bool force_restore);
3210 extern void i915_redisable_vga(struct drm_device *dev);
3211 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3212 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3213 extern void intel_init_pch_refclk(struct drm_device *dev);
3214 extern void intel_set_rps(struct drm_device *dev, u8 val);
3215 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3217 extern void intel_detect_pch(struct drm_device *dev);
3218 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3219 extern int intel_enable_rc6(const struct drm_device *dev);
3221 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3222 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3223 struct drm_file *file);
3224 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3225 struct drm_file *file);
3228 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3229 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3230 struct intel_overlay_error_state *error);
3232 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3233 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3234 struct drm_device *dev,
3235 struct intel_display_error_state *error);
3237 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3238 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3240 /* intel_sideband.c */
3241 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3242 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3243 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3244 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3245 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3246 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3247 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3248 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3249 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3250 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3251 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3252 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3253 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3254 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3255 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3256 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3257 enum intel_sbi_destination destination);
3258 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3259 enum intel_sbi_destination destination);
3260 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3261 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3263 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3264 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3266 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3267 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3269 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3270 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3271 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3272 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3274 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3275 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3276 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3277 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3279 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3280 * will be implemented using 2 32-bit writes in an arbitrary order with
3281 * an arbitrary delay between them. This can cause the hardware to
3282 * act upon the intermediate value, possibly leading to corruption and
3283 * machine death. You have been warned.
3285 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3286 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3288 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3289 u32 upper = I915_READ(upper_reg); \
3290 u32 lower = I915_READ(lower_reg); \
3291 u32 tmp = I915_READ(upper_reg); \
3292 if (upper != tmp) { \
3294 lower = I915_READ(lower_reg); \
3295 WARN_ON(I915_READ(upper_reg) != upper); \
3297 (u64)upper << 32 | lower; })
3299 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3300 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3302 /* These are untraced mmio-accessors that are only valid to be used inside
3303 * criticial sections inside IRQ handlers where forcewake is explicitly
3305 * Think twice, and think again, before using these.
3306 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3307 * intel_uncore_forcewake_irqunlock().
3309 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3310 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3311 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3313 /* "Broadcast RGB" property */
3314 #define INTEL_BROADCAST_RGB_AUTO 0
3315 #define INTEL_BROADCAST_RGB_FULL 1
3316 #define INTEL_BROADCAST_RGB_LIMITED 2
3318 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3320 if (IS_VALLEYVIEW(dev))
3321 return VLV_VGACNTRL;
3322 else if (INTEL_INFO(dev)->gen >= 5)
3323 return CPU_VGACNTRL;
3328 static inline void __user *to_user_ptr(u64 address)
3330 return (void __user *)(uintptr_t)address;
3333 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3335 unsigned long j = msecs_to_jiffies(m);
3337 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3340 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3342 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3345 static inline unsigned long
3346 timespec_to_jiffies_timeout(const struct timespec *value)
3348 unsigned long j = timespec_to_jiffies(value);
3350 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3354 * If you need to wait X milliseconds between events A and B, but event B
3355 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3356 * when event A happened, then just before event B you call this function and
3357 * pass the timestamp as the first argument, and X as the second argument.
3360 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3362 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3365 * Don't re-read the value of "jiffies" every time since it may change
3366 * behind our back and break the math.
3368 tmp_jiffies = jiffies;
3369 target_jiffies = timestamp_jiffies +
3370 msecs_to_jiffies_timeout(to_wait_ms);
3372 if (time_after(target_jiffies, tmp_jiffies)) {
3373 remaining_jiffies = target_jiffies - tmp_jiffies;
3374 while (remaining_jiffies)
3376 schedule_timeout_uninterruptible(remaining_jiffies);
3380 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3381 struct drm_i915_gem_request *req)
3383 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3384 i915_gem_request_assign(&ring->trace_irq_req, req);