1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
53 #include "intel_guc.h"
55 /* General customization:
58 #define DRIVER_NAME "i915"
59 #define DRIVER_DESC "Intel Graphics"
60 #define DRIVER_DATE "20151010"
63 /* Many gcc seem to no see through this and fall over :( */
65 #define WARN_ON(x) ({ \
66 bool __i915_warn_cond = (x); \
67 if (__builtin_constant_p(__i915_warn_cond)) \
68 BUILD_BUG_ON(__i915_warn_cond); \
69 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
71 #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
75 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
77 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
78 (long) (x), __func__);
80 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
81 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
82 * which may not necessarily be a user visible problem. This will either
83 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
84 * enable distros and users to tailor their preferred amount of i915 abrt
87 #define I915_STATE_WARN(condition, format...) ({ \
88 int __ret_warn_on = !!(condition); \
89 if (unlikely(__ret_warn_on)) { \
90 if (i915.verbose_state_checks) \
95 unlikely(__ret_warn_on); \
98 #define I915_STATE_WARN_ON(condition) ({ \
99 int __ret_warn_on = !!(condition); \
100 if (unlikely(__ret_warn_on)) { \
101 if (i915.verbose_state_checks) \
102 WARN(1, "WARN_ON(" #condition ")\n"); \
104 DRM_ERROR("WARN_ON(" #condition ")\n"); \
106 unlikely(__ret_warn_on); \
109 static inline const char *yesno(bool v)
111 return v ? "yes" : "no";
120 I915_MAX_PIPES = _PIPE_EDP
122 #define pipe_name(p) ((p) + 'A')
131 #define transcoder_name(t) ((t) + 'A')
134 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
135 * number of planes per CRTC. Not all platforms really have this many planes,
136 * which means some arrays of size I915_MAX_PLANES may have unused entries
137 * between the topmost sprite plane and the cursor plane.
146 #define plane_name(p) ((p) + 'A')
148 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
158 #define port_name(p) ((p) + 'A')
160 #define I915_NUM_PHYS_VLV 2
172 enum intel_display_power_domain {
176 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
177 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
178 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
179 POWER_DOMAIN_TRANSCODER_A,
180 POWER_DOMAIN_TRANSCODER_B,
181 POWER_DOMAIN_TRANSCODER_C,
182 POWER_DOMAIN_TRANSCODER_EDP,
183 POWER_DOMAIN_PORT_DDI_A_2_LANES,
184 POWER_DOMAIN_PORT_DDI_A_4_LANES,
185 POWER_DOMAIN_PORT_DDI_B_2_LANES,
186 POWER_DOMAIN_PORT_DDI_B_4_LANES,
187 POWER_DOMAIN_PORT_DDI_C_2_LANES,
188 POWER_DOMAIN_PORT_DDI_C_4_LANES,
189 POWER_DOMAIN_PORT_DDI_D_2_LANES,
190 POWER_DOMAIN_PORT_DDI_D_4_LANES,
191 POWER_DOMAIN_PORT_DDI_E_2_LANES,
192 POWER_DOMAIN_PORT_DSI,
193 POWER_DOMAIN_PORT_CRT,
194 POWER_DOMAIN_PORT_OTHER,
207 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
208 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
209 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
210 #define POWER_DOMAIN_TRANSCODER(tran) \
211 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
212 (tran) + POWER_DOMAIN_TRANSCODER_A)
216 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
228 #define for_each_hpd_pin(__pin) \
229 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
231 struct i915_hotplug {
232 struct work_struct hotplug_work;
235 unsigned long last_jiffies;
240 HPD_MARK_DISABLED = 2
242 } stats[HPD_NUM_PINS];
244 struct delayed_work reenable_work;
246 struct intel_digital_port *irq_port[I915_MAX_PORTS];
249 struct work_struct dig_port_work;
252 * if we get a HPD irq from DP and a HPD irq from non-DP
253 * the non-DP HPD could block the workqueue on a mode config
254 * mutex getting, that userspace may have taken. However
255 * userspace is waiting on the DP workqueue to run which is
256 * blocked behind the non-DP one.
258 struct workqueue_struct *dp_wq;
261 #define I915_GEM_GPU_DOMAINS \
262 (I915_GEM_DOMAIN_RENDER | \
263 I915_GEM_DOMAIN_SAMPLER | \
264 I915_GEM_DOMAIN_COMMAND | \
265 I915_GEM_DOMAIN_INSTRUCTION | \
266 I915_GEM_DOMAIN_VERTEX)
268 #define for_each_pipe(__dev_priv, __p) \
269 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
270 #define for_each_plane(__dev_priv, __pipe, __p) \
272 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
274 #define for_each_sprite(__dev_priv, __p, __s) \
276 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
279 #define for_each_crtc(dev, crtc) \
280 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
282 #define for_each_intel_plane(dev, intel_plane) \
283 list_for_each_entry(intel_plane, \
284 &dev->mode_config.plane_list, \
287 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
288 list_for_each_entry(intel_plane, \
289 &(dev)->mode_config.plane_list, \
291 if ((intel_plane)->pipe == (intel_crtc)->pipe)
293 #define for_each_intel_crtc(dev, intel_crtc) \
294 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
296 #define for_each_intel_encoder(dev, intel_encoder) \
297 list_for_each_entry(intel_encoder, \
298 &(dev)->mode_config.encoder_list, \
301 #define for_each_intel_connector(dev, intel_connector) \
302 list_for_each_entry(intel_connector, \
303 &dev->mode_config.connector_list, \
306 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
307 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
308 if ((intel_encoder)->base.crtc == (__crtc))
310 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
311 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
312 if ((intel_connector)->base.encoder == (__encoder))
314 #define for_each_power_domain(domain, mask) \
315 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
316 if ((1 << (domain)) & (mask))
318 struct drm_i915_private;
319 struct i915_mm_struct;
320 struct i915_mmu_object;
322 struct drm_i915_file_private {
323 struct drm_i915_private *dev_priv;
324 struct drm_file *file;
328 struct list_head request_list;
329 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
330 * chosen to prevent the CPU getting more than a frame ahead of the GPU
331 * (when using lax throttling for the frontbuffer). We also use it to
332 * offer free GPU waitboosts for severely congested workloads.
334 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
336 struct idr context_idr;
338 struct intel_rps_client {
339 struct list_head link;
343 struct intel_engine_cs *bsd_ring;
347 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
348 /* real shared dpll ids must be >= 0 */
349 DPLL_ID_PCH_PLL_A = 0,
350 DPLL_ID_PCH_PLL_B = 1,
357 DPLL_ID_SKL_DPLL1 = 0,
358 DPLL_ID_SKL_DPLL2 = 1,
359 DPLL_ID_SKL_DPLL3 = 2,
361 #define I915_NUM_PLLS 3
363 struct intel_dpll_hw_state {
376 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
377 * lower part of ctrl1 and they get shifted into position when writing
378 * the register. This allows us to easily compare the state to share
382 /* HDMI only, 0 when used for DP */
383 uint32_t cfgcr1, cfgcr2;
386 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
390 struct intel_shared_dpll_config {
391 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
392 struct intel_dpll_hw_state hw_state;
395 struct intel_shared_dpll {
396 struct intel_shared_dpll_config config;
398 int active; /* count of number of active CRTCs (i.e. DPMS on) */
399 bool on; /* is the PLL actually active? Disabled during modeset */
401 /* should match the index in the dev_priv->shared_dplls array */
402 enum intel_dpll_id id;
403 /* The mode_set hook is optional and should be used together with the
404 * intel_prepare_shared_dpll function. */
405 void (*mode_set)(struct drm_i915_private *dev_priv,
406 struct intel_shared_dpll *pll);
407 void (*enable)(struct drm_i915_private *dev_priv,
408 struct intel_shared_dpll *pll);
409 void (*disable)(struct drm_i915_private *dev_priv,
410 struct intel_shared_dpll *pll);
411 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
412 struct intel_shared_dpll *pll,
413 struct intel_dpll_hw_state *hw_state);
421 /* Used by dp and fdi links */
422 struct intel_link_m_n {
430 void intel_link_compute_m_n(int bpp, int nlanes,
431 int pixel_clock, int link_clock,
432 struct intel_link_m_n *m_n);
434 /* Interface history:
437 * 1.2: Add Power Management
438 * 1.3: Add vblank support
439 * 1.4: Fix cmdbuffer path, add heap destroy
440 * 1.5: Add vblank pipe configuration
441 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
442 * - Support vertical blank on secondary display pipe
444 #define DRIVER_MAJOR 1
445 #define DRIVER_MINOR 6
446 #define DRIVER_PATCHLEVEL 0
448 #define WATCH_LISTS 0
450 struct opregion_header;
451 struct opregion_acpi;
452 struct opregion_swsci;
453 struct opregion_asle;
455 struct intel_opregion {
456 struct opregion_header *header;
457 struct opregion_acpi *acpi;
458 struct opregion_swsci *swsci;
459 u32 swsci_gbda_sub_functions;
460 u32 swsci_sbcb_sub_functions;
461 struct opregion_asle *asle;
464 struct work_struct asle_work;
466 #define OPREGION_SIZE (8*1024)
468 struct intel_overlay;
469 struct intel_overlay_error_state;
471 #define I915_FENCE_REG_NONE -1
472 #define I915_MAX_NUM_FENCES 32
473 /* 32 fences + sign bit for FENCE_REG_NONE */
474 #define I915_MAX_NUM_FENCE_BITS 6
476 struct drm_i915_fence_reg {
477 struct list_head lru_list;
478 struct drm_i915_gem_object *obj;
482 struct sdvo_device_mapping {
491 struct intel_display_error_state;
493 struct drm_i915_error_state {
502 /* Generic register state */
510 u32 error; /* gen6+ */
511 u32 err_int; /* gen7 */
512 u32 fault_data0; /* gen8, gen9 */
513 u32 fault_data1; /* gen8, gen9 */
519 u32 extra_instdone[I915_NUM_INSTDONE_REG];
520 u64 fence[I915_MAX_NUM_FENCES];
521 struct intel_overlay_error_state *overlay;
522 struct intel_display_error_state *display;
523 struct drm_i915_error_object *semaphore_obj;
525 struct drm_i915_error_ring {
527 /* Software tracked state */
530 enum intel_ring_hangcheck_action hangcheck_action;
533 /* our own tracking of ring head and tail */
537 u32 semaphore_seqno[I915_NUM_RINGS - 1];
556 u32 rc_psmi; /* sleep state */
557 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
559 struct drm_i915_error_object {
563 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
565 struct drm_i915_error_request {
580 char comm[TASK_COMM_LEN];
581 } ring[I915_NUM_RINGS];
583 struct drm_i915_error_buffer {
586 u32 rseqno[I915_NUM_RINGS], wseqno;
590 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
598 } **active_bo, **pinned_bo;
600 u32 *active_bo_count, *pinned_bo_count;
604 struct intel_connector;
605 struct intel_encoder;
606 struct intel_crtc_state;
607 struct intel_initial_plane_config;
612 struct drm_i915_display_funcs {
613 int (*get_display_clock_speed)(struct drm_device *dev);
614 int (*get_fifo_size)(struct drm_device *dev, int plane);
616 * find_dpll() - Find the best values for the PLL
617 * @limit: limits for the PLL
618 * @crtc: current CRTC
619 * @target: target frequency in kHz
620 * @refclk: reference clock frequency in kHz
621 * @match_clock: if provided, @best_clock P divider must
622 * match the P divider from @match_clock
623 * used for LVDS downclocking
624 * @best_clock: best PLL values found
626 * Returns true on success, false on failure.
628 bool (*find_dpll)(const struct intel_limit *limit,
629 struct intel_crtc_state *crtc_state,
630 int target, int refclk,
631 struct dpll *match_clock,
632 struct dpll *best_clock);
633 void (*update_wm)(struct drm_crtc *crtc);
634 void (*update_sprite_wm)(struct drm_plane *plane,
635 struct drm_crtc *crtc,
636 uint32_t sprite_width, uint32_t sprite_height,
637 int pixel_size, bool enable, bool scaled);
638 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
639 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
640 /* Returns the active state of the crtc, and if the crtc is active,
641 * fills out the pipe-config with the hw state. */
642 bool (*get_pipe_config)(struct intel_crtc *,
643 struct intel_crtc_state *);
644 void (*get_initial_plane_config)(struct intel_crtc *,
645 struct intel_initial_plane_config *);
646 int (*crtc_compute_clock)(struct intel_crtc *crtc,
647 struct intel_crtc_state *crtc_state);
648 void (*crtc_enable)(struct drm_crtc *crtc);
649 void (*crtc_disable)(struct drm_crtc *crtc);
650 void (*audio_codec_enable)(struct drm_connector *connector,
651 struct intel_encoder *encoder,
652 const struct drm_display_mode *adjusted_mode);
653 void (*audio_codec_disable)(struct intel_encoder *encoder);
654 void (*fdi_link_train)(struct drm_crtc *crtc);
655 void (*init_clock_gating)(struct drm_device *dev);
656 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
657 struct drm_framebuffer *fb,
658 struct drm_i915_gem_object *obj,
659 struct drm_i915_gem_request *req,
661 void (*update_primary_plane)(struct drm_crtc *crtc,
662 struct drm_framebuffer *fb,
664 void (*hpd_irq_setup)(struct drm_device *dev);
665 /* clock updates for mode set */
667 /* render clock increase/decrease */
668 /* display clock increase/decrease */
669 /* pll clock increase/decrease */
672 enum forcewake_domain_id {
673 FW_DOMAIN_ID_RENDER = 0,
674 FW_DOMAIN_ID_BLITTER,
680 enum forcewake_domains {
681 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
682 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
683 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
684 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
689 struct intel_uncore_funcs {
690 void (*force_wake_get)(struct drm_i915_private *dev_priv,
691 enum forcewake_domains domains);
692 void (*force_wake_put)(struct drm_i915_private *dev_priv,
693 enum forcewake_domains domains);
695 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
696 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
697 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
698 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
700 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
701 uint8_t val, bool trace);
702 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
703 uint16_t val, bool trace);
704 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
705 uint32_t val, bool trace);
706 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
707 uint64_t val, bool trace);
710 struct intel_uncore {
711 spinlock_t lock; /** lock is also taken in irq contexts. */
713 struct intel_uncore_funcs funcs;
716 enum forcewake_domains fw_domains;
718 struct intel_uncore_forcewake_domain {
719 struct drm_i915_private *i915;
720 enum forcewake_domain_id id;
722 struct timer_list timer;
729 } fw_domain[FW_DOMAIN_ID_COUNT];
732 /* Iterate over initialised fw domains */
733 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
734 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
735 (i__) < FW_DOMAIN_ID_COUNT; \
736 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
737 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
739 #define for_each_fw_domain(domain__, dev_priv__, i__) \
740 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
743 FW_UNINITIALIZED = 0,
750 uint32_t *dmc_payload;
751 uint32_t dmc_fw_size;
753 uint32_t mmioaddr[8];
754 uint32_t mmiodata[8];
755 enum csr_state state;
758 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
759 func(is_mobile) sep \
762 func(is_i945gm) sep \
764 func(need_gfx_hws) sep \
766 func(is_pineview) sep \
767 func(is_broadwater) sep \
768 func(is_crestline) sep \
769 func(is_ivybridge) sep \
770 func(is_valleyview) sep \
771 func(is_haswell) sep \
772 func(is_skylake) sep \
773 func(is_preliminary) sep \
775 func(has_pipe_cxsr) sep \
776 func(has_hotplug) sep \
777 func(cursor_needs_physical) sep \
778 func(has_overlay) sep \
779 func(overlay_needs_physical) sep \
780 func(supports_tv) sep \
785 #define DEFINE_FLAG(name) u8 name:1
786 #define SEP_SEMICOLON ;
788 struct intel_device_info {
789 u32 display_mmio_offset;
792 u8 num_sprites[I915_MAX_PIPES];
794 u8 ring_mask; /* Rings supported by the HW */
795 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
796 /* Register offsets for the various display pipes and transcoders */
797 int pipe_offsets[I915_MAX_TRANSCODERS];
798 int trans_offsets[I915_MAX_TRANSCODERS];
799 int palette_offsets[I915_MAX_PIPES];
800 int cursor_offsets[I915_MAX_PIPES];
802 /* Slice/subslice/EU info */
805 u8 subslice_per_slice;
808 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
811 u8 has_subslice_pg:1;
818 enum i915_cache_level {
820 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
821 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
822 caches, eg sampler/render caches, and the
823 large Last-Level-Cache. LLC is coherent with
824 the CPU, but L3 is only visible to the GPU. */
825 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
828 struct i915_ctx_hang_stats {
829 /* This context had batch pending when hang was declared */
830 unsigned batch_pending;
832 /* This context had batch active when hang was declared */
833 unsigned batch_active;
835 /* Time when this context was last blamed for a GPU reset */
836 unsigned long guilty_ts;
838 /* If the contexts causes a second GPU hang within this time,
839 * it is permanently banned from submitting any more work.
841 unsigned long ban_period_seconds;
843 /* This context is banned to submit more work */
847 /* This must match up with the value previously used for execbuf2.rsvd1. */
848 #define DEFAULT_CONTEXT_HANDLE 0
850 #define CONTEXT_NO_ZEROMAP (1<<0)
852 * struct intel_context - as the name implies, represents a context.
853 * @ref: reference count.
854 * @user_handle: userspace tracking identity for this context.
855 * @remap_slice: l3 row remapping information.
856 * @flags: context specific flags:
857 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
858 * @file_priv: filp associated with this context (NULL for global default
860 * @hang_stats: information about the role of this context in possible GPU
862 * @ppgtt: virtual memory space used by this context.
863 * @legacy_hw_ctx: render context backing object and whether it is correctly
864 * initialized (legacy ring submission mechanism only).
865 * @link: link in the global list of contexts.
867 * Contexts are memory images used by the hardware to store copies of their
870 struct intel_context {
874 struct drm_i915_private *i915;
876 struct drm_i915_file_private *file_priv;
877 struct i915_ctx_hang_stats hang_stats;
878 struct i915_hw_ppgtt *ppgtt;
880 /* Legacy ring buffer submission */
882 struct drm_i915_gem_object *rcs_state;
888 struct drm_i915_gem_object *state;
889 struct intel_ringbuffer *ringbuf;
891 } engine[I915_NUM_RINGS];
893 struct list_head link;
905 /* This is always the inner lock when overlapping with struct_mutex and
906 * it's the outer lock when overlapping with stolen_lock. */
908 unsigned long uncompressed_size;
911 unsigned int possible_framebuffer_bits;
912 unsigned int busy_bits;
913 struct intel_crtc *crtc;
916 struct drm_mm_node compressed_fb;
917 struct drm_mm_node *compressed_llb;
921 /* Tracks whether the HW is actually enabled, not whether the feature is
925 struct intel_fbc_work {
926 struct delayed_work work;
927 struct intel_crtc *crtc;
928 struct drm_framebuffer *fb;
932 FBC_OK, /* FBC is enabled */
933 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
934 FBC_NO_OUTPUT, /* no outputs enabled to compress */
935 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
936 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
937 FBC_MODE_TOO_LARGE, /* mode too large for compression */
938 FBC_BAD_PLANE, /* fbc not supported on plane */
939 FBC_NOT_TILED, /* buffer not tiled */
940 FBC_MULTIPLE_PIPES, /* more than one pipe active */
942 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
943 FBC_ROTATION, /* rotation is not supported */
944 FBC_IN_DBG_MASTER, /* kernel debugger is active */
945 FBC_BAD_STRIDE, /* stride is not supported */
946 FBC_PIXEL_RATE, /* pixel rate is too big */
947 FBC_PIXEL_FORMAT /* pixel format is invalid */
950 bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
951 void (*enable_fbc)(struct intel_crtc *crtc);
952 void (*disable_fbc)(struct drm_i915_private *dev_priv);
956 * HIGH_RR is the highest eDP panel refresh rate read from EDID
957 * LOW_RR is the lowest eDP panel refresh rate found from EDID
958 * parsing for same resolution.
960 enum drrs_refresh_rate_type {
963 DRRS_MAX_RR, /* RR count */
966 enum drrs_support_type {
967 DRRS_NOT_SUPPORTED = 0,
968 STATIC_DRRS_SUPPORT = 1,
969 SEAMLESS_DRRS_SUPPORT = 2
975 struct delayed_work work;
977 unsigned busy_frontbuffer_bits;
978 enum drrs_refresh_rate_type refresh_rate_type;
979 enum drrs_support_type type;
986 struct intel_dp *enabled;
988 struct delayed_work work;
989 unsigned busy_frontbuffer_bits;
995 PCH_NONE = 0, /* No PCH present */
996 PCH_IBX, /* Ibexpeak PCH */
997 PCH_CPT, /* Cougarpoint PCH */
998 PCH_LPT, /* Lynxpoint PCH */
999 PCH_SPT, /* Sunrisepoint PCH */
1003 enum intel_sbi_destination {
1008 #define QUIRK_PIPEA_FORCE (1<<0)
1009 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1010 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1011 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1012 #define QUIRK_PIPEB_FORCE (1<<4)
1013 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1016 struct intel_fbc_work;
1018 struct intel_gmbus {
1019 struct i2c_adapter adapter;
1023 struct i2c_algo_bit_data bit_algo;
1024 struct drm_i915_private *dev_priv;
1027 struct i915_suspend_saved_registers {
1030 u32 savePP_ON_DELAYS;
1031 u32 savePP_OFF_DELAYS;
1036 u32 saveFBC_CONTROL;
1037 u32 saveCACHE_MODE_0;
1038 u32 saveMI_ARB_STATE;
1042 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1043 u32 savePCH_PORT_HOTPLUG;
1047 struct vlv_s0ix_state {
1054 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1055 u32 media_max_req_count;
1056 u32 gfx_max_req_count;
1082 u32 rp_down_timeout;
1088 /* Display 1 CZ domain */
1093 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1095 /* GT SA CZ domain */
1102 /* Display 2 CZ domain */
1106 u32 clock_gate_dis2;
1109 struct intel_rps_ei {
1115 struct intel_gen6_power_mgmt {
1117 * work, interrupts_enabled and pm_iir are protected by
1118 * dev_priv->irq_lock
1120 struct work_struct work;
1121 bool interrupts_enabled;
1124 /* Frequencies are stored in potentially platform dependent multiples.
1125 * In other words, *_freq needs to be multiplied by X to be interesting.
1126 * Soft limits are those which are used for the dynamic reclocking done
1127 * by the driver (raise frequencies under heavy loads, and lower for
1128 * lighter loads). Hard limits are those imposed by the hardware.
1130 * A distinction is made for overclocking, which is never enabled by
1131 * default, and is considered to be above the hard limit if it's
1134 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1135 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1136 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1137 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1138 u8 min_freq; /* AKA RPn. Minimum frequency */
1139 u8 idle_freq; /* Frequency to request when we are idle */
1140 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1141 u8 rp1_freq; /* "less than" RP0 power/freqency */
1142 u8 rp0_freq; /* Non-overclocked max frequency. */
1144 u8 up_threshold; /* Current %busy required to uplock */
1145 u8 down_threshold; /* Current %busy required to downclock */
1148 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1150 spinlock_t client_lock;
1151 struct list_head clients;
1155 struct delayed_work delayed_resume_work;
1158 struct intel_rps_client semaphores, mmioflips;
1160 /* manual wa residency calculations */
1161 struct intel_rps_ei up_ei, down_ei;
1164 * Protects RPS/RC6 register access and PCU communication.
1165 * Must be taken after struct_mutex if nested. Note that
1166 * this lock may be held for long periods of time when
1167 * talking to hw - so only take it when talking to hw!
1169 struct mutex hw_lock;
1172 /* defined intel_pm.c */
1173 extern spinlock_t mchdev_lock;
1175 struct intel_ilk_power_mgmt {
1183 unsigned long last_time1;
1184 unsigned long chipset_power;
1187 unsigned long gfx_power;
1194 struct drm_i915_private;
1195 struct i915_power_well;
1197 struct i915_power_well_ops {
1199 * Synchronize the well's hw state to match the current sw state, for
1200 * example enable/disable it based on the current refcount. Called
1201 * during driver init and resume time, possibly after first calling
1202 * the enable/disable handlers.
1204 void (*sync_hw)(struct drm_i915_private *dev_priv,
1205 struct i915_power_well *power_well);
1207 * Enable the well and resources that depend on it (for example
1208 * interrupts located on the well). Called after the 0->1 refcount
1211 void (*enable)(struct drm_i915_private *dev_priv,
1212 struct i915_power_well *power_well);
1214 * Disable the well and resources that depend on it. Called after
1215 * the 1->0 refcount transition.
1217 void (*disable)(struct drm_i915_private *dev_priv,
1218 struct i915_power_well *power_well);
1219 /* Returns the hw enabled state. */
1220 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1221 struct i915_power_well *power_well);
1224 /* Power well structure for haswell */
1225 struct i915_power_well {
1228 /* power well enable/disable usage count */
1230 /* cached hw enabled state */
1232 unsigned long domains;
1234 const struct i915_power_well_ops *ops;
1237 struct i915_power_domains {
1239 * Power wells needed for initialization at driver init and suspend
1240 * time are on. They are kept on until after the first modeset.
1244 int power_well_count;
1247 int domain_use_count[POWER_DOMAIN_NUM];
1248 struct i915_power_well *power_wells;
1251 #define MAX_L3_SLICES 2
1252 struct intel_l3_parity {
1253 u32 *remap_info[MAX_L3_SLICES];
1254 struct work_struct error_work;
1258 struct i915_gem_mm {
1259 /** Memory allocator for GTT stolen memory */
1260 struct drm_mm stolen;
1261 /** Protects the usage of the GTT stolen memory allocator. This is
1262 * always the inner lock when overlapping with struct_mutex. */
1263 struct mutex stolen_lock;
1265 /** List of all objects in gtt_space. Used to restore gtt
1266 * mappings on resume */
1267 struct list_head bound_list;
1269 * List of objects which are not bound to the GTT (thus
1270 * are idle and not used by the GPU) but still have
1271 * (presumably uncached) pages still attached.
1273 struct list_head unbound_list;
1275 /** Usable portion of the GTT for GEM */
1276 unsigned long stolen_base; /* limited to low memory (32-bit) */
1278 /** PPGTT used for aliasing the PPGTT with the GTT */
1279 struct i915_hw_ppgtt *aliasing_ppgtt;
1281 struct notifier_block oom_notifier;
1282 struct shrinker shrinker;
1283 bool shrinker_no_lock_stealing;
1285 /** LRU list of objects with fence regs on them. */
1286 struct list_head fence_list;
1289 * We leave the user IRQ off as much as possible,
1290 * but this means that requests will finish and never
1291 * be retired once the system goes idle. Set a timer to
1292 * fire periodically while the ring is running. When it
1293 * fires, go retire requests.
1295 struct delayed_work retire_work;
1298 * When we detect an idle GPU, we want to turn on
1299 * powersaving features. So once we see that there
1300 * are no more requests outstanding and no more
1301 * arrive within a small period of time, we fire
1302 * off the idle_work.
1304 struct delayed_work idle_work;
1307 * Are we in a non-interruptible section of code like
1313 * Is the GPU currently considered idle, or busy executing userspace
1314 * requests? Whilst idle, we attempt to power down the hardware and
1315 * display clocks. In order to reduce the effect on performance, there
1316 * is a slight delay before we do so.
1320 /* the indicator for dispatch video commands on two BSD rings */
1321 int bsd_ring_dispatch_index;
1323 /** Bit 6 swizzling required for X tiling */
1324 uint32_t bit_6_swizzle_x;
1325 /** Bit 6 swizzling required for Y tiling */
1326 uint32_t bit_6_swizzle_y;
1328 /* accounting, useful for userland debugging */
1329 spinlock_t object_stat_lock;
1330 size_t object_memory;
1334 struct drm_i915_error_state_buf {
1335 struct drm_i915_private *i915;
1344 struct i915_error_state_file_priv {
1345 struct drm_device *dev;
1346 struct drm_i915_error_state *error;
1349 struct i915_gpu_error {
1350 /* For hangcheck timer */
1351 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1352 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1353 /* Hang gpu twice in this window and your context gets banned */
1354 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1356 struct workqueue_struct *hangcheck_wq;
1357 struct delayed_work hangcheck_work;
1359 /* For reset and error_state handling. */
1361 /* Protected by the above dev->gpu_error.lock. */
1362 struct drm_i915_error_state *first_error;
1364 unsigned long missed_irq_rings;
1367 * State variable controlling the reset flow and count
1369 * This is a counter which gets incremented when reset is triggered,
1370 * and again when reset has been handled. So odd values (lowest bit set)
1371 * means that reset is in progress and even values that
1372 * (reset_counter >> 1):th reset was successfully completed.
1374 * If reset is not completed succesfully, the I915_WEDGE bit is
1375 * set meaning that hardware is terminally sour and there is no
1376 * recovery. All waiters on the reset_queue will be woken when
1379 * This counter is used by the wait_seqno code to notice that reset
1380 * event happened and it needs to restart the entire ioctl (since most
1381 * likely the seqno it waited for won't ever signal anytime soon).
1383 * This is important for lock-free wait paths, where no contended lock
1384 * naturally enforces the correct ordering between the bail-out of the
1385 * waiter and the gpu reset work code.
1387 atomic_t reset_counter;
1389 #define I915_RESET_IN_PROGRESS_FLAG 1
1390 #define I915_WEDGED (1 << 31)
1393 * Waitqueue to signal when the reset has completed. Used by clients
1394 * that wait for dev_priv->mm.wedged to settle.
1396 wait_queue_head_t reset_queue;
1398 /* Userspace knobs for gpu hang simulation;
1399 * combines both a ring mask, and extra flags
1402 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1403 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1405 /* For missed irq/seqno simulation. */
1406 unsigned int test_irq_rings;
1408 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1409 bool reload_in_reset;
1412 enum modeset_restore {
1413 MODESET_ON_LID_OPEN,
1418 #define DP_AUX_A 0x40
1419 #define DP_AUX_B 0x10
1420 #define DP_AUX_C 0x20
1421 #define DP_AUX_D 0x30
1423 #define DDC_PIN_B 0x05
1424 #define DDC_PIN_C 0x04
1425 #define DDC_PIN_D 0x06
1427 struct ddi_vbt_port_info {
1429 * This is an index in the HDMI/DVI DDI buffer translation table.
1430 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1431 * populate this field.
1433 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1434 uint8_t hdmi_level_shift;
1436 uint8_t supports_dvi:1;
1437 uint8_t supports_hdmi:1;
1438 uint8_t supports_dp:1;
1440 uint8_t alternate_aux_channel;
1441 uint8_t alternate_ddc_pin;
1443 uint8_t dp_boost_level;
1444 uint8_t hdmi_boost_level;
1447 enum psr_lines_to_wait {
1448 PSR_0_LINES_TO_WAIT = 0,
1450 PSR_4_LINES_TO_WAIT,
1454 struct intel_vbt_data {
1455 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1456 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1459 unsigned int int_tv_support:1;
1460 unsigned int lvds_dither:1;
1461 unsigned int lvds_vbt:1;
1462 unsigned int int_crt_support:1;
1463 unsigned int lvds_use_ssc:1;
1464 unsigned int display_clock_mode:1;
1465 unsigned int fdi_rx_polarity_inverted:1;
1466 unsigned int has_mipi:1;
1468 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1470 enum drrs_support_type drrs_type;
1475 int edp_preemphasis;
1477 bool edp_initialized;
1480 struct edp_power_seq edp_pps;
1484 bool require_aux_wakeup;
1486 enum psr_lines_to_wait lines_to_wait;
1487 int tp1_wakeup_time;
1488 int tp2_tp3_wakeup_time;
1494 bool active_low_pwm;
1495 u8 min_brightness; /* min_brightness/255 of max */
1502 struct mipi_config *config;
1503 struct mipi_pps_data *pps;
1507 u8 *sequence[MIPI_SEQ_MAX];
1513 union child_device_config *child_dev;
1515 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1518 enum intel_ddb_partitioning {
1520 INTEL_DDB_PART_5_6, /* IVB+ */
1523 struct intel_wm_level {
1531 struct ilk_wm_values {
1532 uint32_t wm_pipe[3];
1534 uint32_t wm_lp_spr[3];
1535 uint32_t wm_linetime[3];
1537 enum intel_ddb_partitioning partitioning;
1540 struct vlv_pipe_wm {
1551 struct vlv_wm_values {
1552 struct vlv_pipe_wm pipe[3];
1553 struct vlv_sr_wm sr;
1563 struct skl_ddb_entry {
1564 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1567 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1569 return entry->end - entry->start;
1572 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1573 const struct skl_ddb_entry *e2)
1575 if (e1->start == e2->start && e1->end == e2->end)
1581 struct skl_ddb_allocation {
1582 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1583 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1584 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1587 struct skl_wm_values {
1588 bool dirty[I915_MAX_PIPES];
1589 struct skl_ddb_allocation ddb;
1590 uint32_t wm_linetime[I915_MAX_PIPES];
1591 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1592 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1595 struct skl_wm_level {
1596 bool plane_en[I915_MAX_PLANES];
1597 uint16_t plane_res_b[I915_MAX_PLANES];
1598 uint8_t plane_res_l[I915_MAX_PLANES];
1602 * This struct helps tracking the state needed for runtime PM, which puts the
1603 * device in PCI D3 state. Notice that when this happens, nothing on the
1604 * graphics device works, even register access, so we don't get interrupts nor
1607 * Every piece of our code that needs to actually touch the hardware needs to
1608 * either call intel_runtime_pm_get or call intel_display_power_get with the
1609 * appropriate power domain.
1611 * Our driver uses the autosuspend delay feature, which means we'll only really
1612 * suspend if we stay with zero refcount for a certain amount of time. The
1613 * default value is currently very conservative (see intel_runtime_pm_enable), but
1614 * it can be changed with the standard runtime PM files from sysfs.
1616 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1617 * goes back to false exactly before we reenable the IRQs. We use this variable
1618 * to check if someone is trying to enable/disable IRQs while they're supposed
1619 * to be disabled. This shouldn't happen and we'll print some error messages in
1622 * For more, read the Documentation/power/runtime_pm.txt.
1624 struct i915_runtime_pm {
1629 enum intel_pipe_crc_source {
1630 INTEL_PIPE_CRC_SOURCE_NONE,
1631 INTEL_PIPE_CRC_SOURCE_PLANE1,
1632 INTEL_PIPE_CRC_SOURCE_PLANE2,
1633 INTEL_PIPE_CRC_SOURCE_PF,
1634 INTEL_PIPE_CRC_SOURCE_PIPE,
1635 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1636 INTEL_PIPE_CRC_SOURCE_TV,
1637 INTEL_PIPE_CRC_SOURCE_DP_B,
1638 INTEL_PIPE_CRC_SOURCE_DP_C,
1639 INTEL_PIPE_CRC_SOURCE_DP_D,
1640 INTEL_PIPE_CRC_SOURCE_AUTO,
1641 INTEL_PIPE_CRC_SOURCE_MAX,
1644 struct intel_pipe_crc_entry {
1649 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1650 struct intel_pipe_crc {
1652 bool opened; /* exclusive access to the result file */
1653 struct intel_pipe_crc_entry *entries;
1654 enum intel_pipe_crc_source source;
1656 wait_queue_head_t wq;
1659 struct i915_frontbuffer_tracking {
1663 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1670 struct i915_wa_reg {
1673 /* bitmask representing WA bits */
1677 #define I915_MAX_WA_REGS 16
1679 struct i915_workarounds {
1680 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1684 struct i915_virtual_gpu {
1688 struct i915_execbuffer_params {
1689 struct drm_device *dev;
1690 struct drm_file *file;
1691 uint32_t dispatch_flags;
1692 uint32_t args_batch_start_offset;
1693 uint64_t batch_obj_vm_offset;
1694 struct intel_engine_cs *ring;
1695 struct drm_i915_gem_object *batch_obj;
1696 struct intel_context *ctx;
1697 struct drm_i915_gem_request *request;
1700 struct drm_i915_private {
1701 struct drm_device *dev;
1702 struct kmem_cache *objects;
1703 struct kmem_cache *vmas;
1704 struct kmem_cache *requests;
1706 const struct intel_device_info info;
1708 int relative_constants_mode;
1712 struct intel_uncore uncore;
1714 struct i915_virtual_gpu vgpu;
1716 struct intel_guc guc;
1718 struct intel_csr csr;
1720 /* Display CSR-related protection */
1721 struct mutex csr_lock;
1723 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1725 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1726 * controller on different i2c buses. */
1727 struct mutex gmbus_mutex;
1730 * Base address of the gmbus and gpio block.
1732 uint32_t gpio_mmio_base;
1734 /* MMIO base address for MIPI regs */
1735 uint32_t mipi_mmio_base;
1737 wait_queue_head_t gmbus_wait_queue;
1739 struct pci_dev *bridge_dev;
1740 struct intel_engine_cs ring[I915_NUM_RINGS];
1741 struct drm_i915_gem_object *semaphore_obj;
1742 uint32_t last_seqno, next_seqno;
1744 struct drm_dma_handle *status_page_dmah;
1745 struct resource mch_res;
1747 /* protects the irq masks */
1748 spinlock_t irq_lock;
1750 /* protects the mmio flip data */
1751 spinlock_t mmio_flip_lock;
1753 bool display_irqs_enabled;
1755 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1756 struct pm_qos_request pm_qos;
1758 /* Sideband mailbox protection */
1759 struct mutex sb_lock;
1761 /** Cached value of IMR to avoid reads in updating the bitfield */
1764 u32 de_irq_mask[I915_MAX_PIPES];
1769 u32 pipestat_irq_mask[I915_MAX_PIPES];
1771 struct i915_hotplug hotplug;
1772 struct i915_fbc fbc;
1773 struct i915_drrs drrs;
1774 struct intel_opregion opregion;
1775 struct intel_vbt_data vbt;
1777 bool preserve_bios_swizzle;
1780 struct intel_overlay *overlay;
1782 /* backlight registers and fields in struct intel_panel */
1783 struct mutex backlight_lock;
1786 bool no_aux_handshake;
1788 /* protects panel power sequencer state */
1789 struct mutex pps_mutex;
1791 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1792 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1794 unsigned int fsb_freq, mem_freq, is_ddr3;
1795 unsigned int skl_boot_cdclk;
1796 unsigned int cdclk_freq, max_cdclk_freq;
1797 unsigned int max_dotclk_freq;
1798 unsigned int hpll_freq;
1799 unsigned int czclk_freq;
1802 * wq - Driver workqueue for GEM.
1804 * NOTE: Work items scheduled here are not allowed to grab any modeset
1805 * locks, for otherwise the flushing done in the pageflip code will
1806 * result in deadlocks.
1808 struct workqueue_struct *wq;
1810 /* Display functions */
1811 struct drm_i915_display_funcs display;
1813 /* PCH chipset type */
1814 enum intel_pch pch_type;
1815 unsigned short pch_id;
1817 unsigned long quirks;
1819 enum modeset_restore modeset_restore;
1820 struct mutex modeset_restore_lock;
1822 struct list_head vm_list; /* Global list of all address spaces */
1823 struct i915_gtt gtt; /* VM representing the global address space */
1825 struct i915_gem_mm mm;
1826 DECLARE_HASHTABLE(mm_structs, 7);
1827 struct mutex mm_lock;
1829 /* Kernel Modesetting */
1831 struct sdvo_device_mapping sdvo_mappings[2];
1833 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1834 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1835 wait_queue_head_t pending_flip_queue;
1837 #ifdef CONFIG_DEBUG_FS
1838 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1841 int num_shared_dpll;
1842 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1843 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1845 struct i915_workarounds workarounds;
1847 /* Reclocking support */
1848 bool render_reclock_avail;
1850 struct i915_frontbuffer_tracking fb_tracking;
1854 bool mchbar_need_disable;
1856 struct intel_l3_parity l3_parity;
1858 /* Cannot be determined by PCIID. You must always read a register. */
1861 /* gen6+ rps state */
1862 struct intel_gen6_power_mgmt rps;
1864 /* ilk-only ips/rps state. Everything in here is protected by the global
1865 * mchdev_lock in intel_pm.c */
1866 struct intel_ilk_power_mgmt ips;
1868 struct i915_power_domains power_domains;
1870 struct i915_psr psr;
1872 struct i915_gpu_error gpu_error;
1874 struct drm_i915_gem_object *vlv_pctx;
1876 #ifdef CONFIG_DRM_FBDEV_EMULATION
1877 /* list of fbdev register on this device */
1878 struct intel_fbdev *fbdev;
1879 struct work_struct fbdev_suspend_work;
1882 struct drm_property *broadcast_rgb_property;
1883 struct drm_property *force_audio_property;
1885 /* hda/i915 audio component */
1886 struct i915_audio_component *audio_component;
1887 bool audio_component_registered;
1889 * av_mutex - mutex for audio/video sync
1892 struct mutex av_mutex;
1894 uint32_t hw_context_size;
1895 struct list_head context_list;
1899 u32 chv_phy_control;
1902 struct i915_suspend_saved_registers regfile;
1903 struct vlv_s0ix_state vlv_s0ix_state;
1907 * Raw watermark latency values:
1908 * in 0.1us units for WM0,
1909 * in 0.5us units for WM1+.
1912 uint16_t pri_latency[5];
1914 uint16_t spr_latency[5];
1916 uint16_t cur_latency[5];
1918 * Raw watermark memory latency values
1919 * for SKL for all 8 levels
1922 uint16_t skl_latency[8];
1925 * The skl_wm_values structure is a bit too big for stack
1926 * allocation, so we keep the staging struct where we store
1927 * intermediate results here instead.
1929 struct skl_wm_values skl_results;
1931 /* current hardware state */
1933 struct ilk_wm_values hw;
1934 struct skl_wm_values skl_hw;
1935 struct vlv_wm_values vlv;
1941 struct i915_runtime_pm pm;
1943 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1945 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1946 struct drm_i915_gem_execbuffer2 *args,
1947 struct list_head *vmas);
1948 int (*init_rings)(struct drm_device *dev);
1949 void (*cleanup_ring)(struct intel_engine_cs *ring);
1950 void (*stop_ring)(struct intel_engine_cs *ring);
1953 bool edp_low_vswing;
1955 /* perform PHY state sanity checks? */
1956 bool chv_phy_assert[2];
1959 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1960 * will be rejected. Instead look for a better place.
1964 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1966 return dev->dev_private;
1969 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1971 return to_i915(dev_get_drvdata(dev));
1974 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1976 return container_of(guc, struct drm_i915_private, guc);
1979 /* Iterate over initialised rings */
1980 #define for_each_ring(ring__, dev_priv__, i__) \
1981 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1982 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1984 enum hdmi_force_audio {
1985 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1986 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1987 HDMI_AUDIO_AUTO, /* trust EDID */
1988 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1991 #define I915_GTT_OFFSET_NONE ((u32)-1)
1993 struct drm_i915_gem_object_ops {
1994 /* Interface between the GEM object and its backing storage.
1995 * get_pages() is called once prior to the use of the associated set
1996 * of pages before to binding them into the GTT, and put_pages() is
1997 * called after we no longer need them. As we expect there to be
1998 * associated cost with migrating pages between the backing storage
1999 * and making them available for the GPU (e.g. clflush), we may hold
2000 * onto the pages after they are no longer referenced by the GPU
2001 * in case they may be used again shortly (for example migrating the
2002 * pages to a different memory domain within the GTT). put_pages()
2003 * will therefore most likely be called when the object itself is
2004 * being released or under memory pressure (where we attempt to
2005 * reap pages for the shrinker).
2007 int (*get_pages)(struct drm_i915_gem_object *);
2008 void (*put_pages)(struct drm_i915_gem_object *);
2009 int (*dmabuf_export)(struct drm_i915_gem_object *);
2010 void (*release)(struct drm_i915_gem_object *);
2014 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2015 * considered to be the frontbuffer for the given plane interface-wise. This
2016 * doesn't mean that the hw necessarily already scans it out, but that any
2017 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2019 * We have one bit per pipe and per scanout plane type.
2021 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2022 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2023 #define INTEL_FRONTBUFFER_BITS \
2024 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2025 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2026 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2027 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2028 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2029 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2030 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2031 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2032 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2033 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2034 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2036 struct drm_i915_gem_object {
2037 struct drm_gem_object base;
2039 const struct drm_i915_gem_object_ops *ops;
2041 /** List of VMAs backed by this object */
2042 struct list_head vma_list;
2044 /** Stolen memory for this object, instead of being backed by shmem. */
2045 struct drm_mm_node *stolen;
2046 struct list_head global_list;
2048 struct list_head ring_list[I915_NUM_RINGS];
2049 /** Used in execbuf to temporarily hold a ref */
2050 struct list_head obj_exec_link;
2052 struct list_head batch_pool_link;
2055 * This is set if the object is on the active lists (has pending
2056 * rendering and so a non-zero seqno), and is not set if it i s on
2057 * inactive (ready to be unbound) list.
2059 unsigned int active:I915_NUM_RINGS;
2062 * This is set if the object has been written to since last bound
2065 unsigned int dirty:1;
2068 * Fence register bits (if any) for this object. Will be set
2069 * as needed when mapped into the GTT.
2070 * Protected by dev->struct_mutex.
2072 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2075 * Advice: are the backing pages purgeable?
2077 unsigned int madv:2;
2080 * Current tiling mode for the object.
2082 unsigned int tiling_mode:2;
2084 * Whether the tiling parameters for the currently associated fence
2085 * register have changed. Note that for the purposes of tracking
2086 * tiling changes we also treat the unfenced register, the register
2087 * slot that the object occupies whilst it executes a fenced
2088 * command (such as BLT on gen2/3), as a "fence".
2090 unsigned int fence_dirty:1;
2093 * Is the object at the current location in the gtt mappable and
2094 * fenceable? Used to avoid costly recalculations.
2096 unsigned int map_and_fenceable:1;
2099 * Whether the current gtt mapping needs to be mappable (and isn't just
2100 * mappable by accident). Track pin and fault separate for a more
2101 * accurate mappable working set.
2103 unsigned int fault_mappable:1;
2106 * Is the object to be mapped as read-only to the GPU
2107 * Only honoured if hardware has relevant pte bit
2109 unsigned long gt_ro:1;
2110 unsigned int cache_level:3;
2111 unsigned int cache_dirty:1;
2113 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2115 unsigned int pin_display;
2117 struct sg_table *pages;
2118 int pages_pin_count;
2120 struct scatterlist *sg;
2124 /* prime dma-buf support */
2125 void *dma_buf_vmapping;
2128 /** Breadcrumb of last rendering to the buffer.
2129 * There can only be one writer, but we allow for multiple readers.
2130 * If there is a writer that necessarily implies that all other
2131 * read requests are complete - but we may only be lazily clearing
2132 * the read requests. A read request is naturally the most recent
2133 * request on a ring, so we may have two different write and read
2134 * requests on one ring where the write request is older than the
2135 * read request. This allows for the CPU to read from an active
2136 * buffer by only waiting for the write to complete.
2138 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2139 struct drm_i915_gem_request *last_write_req;
2140 /** Breadcrumb of last fenced GPU access to the buffer. */
2141 struct drm_i915_gem_request *last_fenced_req;
2143 /** Current tiling stride for the object, if it's tiled. */
2146 /** References from framebuffers, locks out tiling changes. */
2147 unsigned long framebuffer_references;
2149 /** Record of address bit 17 of each page at last unbind. */
2150 unsigned long *bit_17;
2153 /** for phy allocated objects */
2154 struct drm_dma_handle *phys_handle;
2156 struct i915_gem_userptr {
2158 unsigned read_only :1;
2159 unsigned workers :4;
2160 #define I915_GEM_USERPTR_MAX_WORKERS 15
2162 struct i915_mm_struct *mm;
2163 struct i915_mmu_object *mmu_object;
2164 struct work_struct *work;
2168 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2170 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2171 struct drm_i915_gem_object *new,
2172 unsigned frontbuffer_bits);
2175 * Request queue structure.
2177 * The request queue allows us to note sequence numbers that have been emitted
2178 * and may be associated with active buffers to be retired.
2180 * By keeping this list, we can avoid having to do questionable sequence
2181 * number comparisons on buffer last_read|write_seqno. It also allows an
2182 * emission time to be associated with the request for tracking how far ahead
2183 * of the GPU the submission is.
2185 * The requests are reference counted, so upon creation they should have an
2186 * initial reference taken using kref_init
2188 struct drm_i915_gem_request {
2191 /** On Which ring this request was generated */
2192 struct drm_i915_private *i915;
2193 struct intel_engine_cs *ring;
2195 /** GEM sequence number associated with this request. */
2198 /** Position in the ringbuffer of the start of the request */
2202 * Position in the ringbuffer of the start of the postfix.
2203 * This is required to calculate the maximum available ringbuffer
2204 * space without overwriting the postfix.
2208 /** Position in the ringbuffer of the end of the whole request */
2212 * Context and ring buffer related to this request
2213 * Contexts are refcounted, so when this request is associated with a
2214 * context, we must increment the context's refcount, to guarantee that
2215 * it persists while any request is linked to it. Requests themselves
2216 * are also refcounted, so the request will only be freed when the last
2217 * reference to it is dismissed, and the code in
2218 * i915_gem_request_free() will then decrement the refcount on the
2221 struct intel_context *ctx;
2222 struct intel_ringbuffer *ringbuf;
2224 /** Batch buffer related to this request if any (used for
2225 error state dump only) */
2226 struct drm_i915_gem_object *batch_obj;
2228 /** Time at which this request was emitted, in jiffies. */
2229 unsigned long emitted_jiffies;
2231 /** global list entry for this request */
2232 struct list_head list;
2234 struct drm_i915_file_private *file_priv;
2235 /** file_priv list entry for this request */
2236 struct list_head client_list;
2238 /** process identifier submitting this request */
2242 * The ELSP only accepts two elements at a time, so we queue
2243 * context/tail pairs on a given queue (ring->execlist_queue) until the
2244 * hardware is available. The queue serves a double purpose: we also use
2245 * it to keep track of the up to 2 contexts currently in the hardware
2246 * (usually one in execution and the other queued up by the GPU): We
2247 * only remove elements from the head of the queue when the hardware
2248 * informs us that an element has been completed.
2250 * All accesses to the queue are mediated by a spinlock
2251 * (ring->execlist_lock).
2254 /** Execlist link in the submission queue.*/
2255 struct list_head execlist_link;
2257 /** Execlists no. of times this request has been sent to the ELSP */
2262 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2263 struct intel_context *ctx,
2264 struct drm_i915_gem_request **req_out);
2265 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2266 void i915_gem_request_free(struct kref *req_ref);
2267 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2268 struct drm_file *file);
2270 static inline uint32_t
2271 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2273 return req ? req->seqno : 0;
2276 static inline struct intel_engine_cs *
2277 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2279 return req ? req->ring : NULL;
2282 static inline struct drm_i915_gem_request *
2283 i915_gem_request_reference(struct drm_i915_gem_request *req)
2286 kref_get(&req->ref);
2291 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2293 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2294 kref_put(&req->ref, i915_gem_request_free);
2298 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2300 struct drm_device *dev;
2305 dev = req->ring->dev;
2306 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2307 mutex_unlock(&dev->struct_mutex);
2310 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2311 struct drm_i915_gem_request *src)
2314 i915_gem_request_reference(src);
2317 i915_gem_request_unreference(*pdst);
2323 * XXX: i915_gem_request_completed should be here but currently needs the
2324 * definition of i915_seqno_passed() which is below. It will be moved in
2325 * a later patch when the call to i915_seqno_passed() is obsoleted...
2329 * A command that requires special handling by the command parser.
2331 struct drm_i915_cmd_descriptor {
2333 * Flags describing how the command parser processes the command.
2335 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2336 * a length mask if not set
2337 * CMD_DESC_SKIP: The command is allowed but does not follow the
2338 * standard length encoding for the opcode range in
2340 * CMD_DESC_REJECT: The command is never allowed
2341 * CMD_DESC_REGISTER: The command should be checked against the
2342 * register whitelist for the appropriate ring
2343 * CMD_DESC_MASTER: The command is allowed if the submitting process
2347 #define CMD_DESC_FIXED (1<<0)
2348 #define CMD_DESC_SKIP (1<<1)
2349 #define CMD_DESC_REJECT (1<<2)
2350 #define CMD_DESC_REGISTER (1<<3)
2351 #define CMD_DESC_BITMASK (1<<4)
2352 #define CMD_DESC_MASTER (1<<5)
2355 * The command's unique identification bits and the bitmask to get them.
2356 * This isn't strictly the opcode field as defined in the spec and may
2357 * also include type, subtype, and/or subop fields.
2365 * The command's length. The command is either fixed length (i.e. does
2366 * not include a length field) or has a length field mask. The flag
2367 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2368 * a length mask. All command entries in a command table must include
2369 * length information.
2377 * Describes where to find a register address in the command to check
2378 * against the ring's register whitelist. Only valid if flags has the
2379 * CMD_DESC_REGISTER bit set.
2381 * A non-zero step value implies that the command may access multiple
2382 * registers in sequence (e.g. LRI), in that case step gives the
2383 * distance in dwords between individual offset fields.
2391 #define MAX_CMD_DESC_BITMASKS 3
2393 * Describes command checks where a particular dword is masked and
2394 * compared against an expected value. If the command does not match
2395 * the expected value, the parser rejects it. Only valid if flags has
2396 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2399 * If the check specifies a non-zero condition_mask then the parser
2400 * only performs the check when the bits specified by condition_mask
2407 u32 condition_offset;
2409 } bits[MAX_CMD_DESC_BITMASKS];
2413 * A table of commands requiring special handling by the command parser.
2415 * Each ring has an array of tables. Each table consists of an array of command
2416 * descriptors, which must be sorted with command opcodes in ascending order.
2418 struct drm_i915_cmd_table {
2419 const struct drm_i915_cmd_descriptor *table;
2423 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2424 #define __I915__(p) ({ \
2425 struct drm_i915_private *__p; \
2426 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2427 __p = (struct drm_i915_private *)p; \
2428 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2429 __p = to_i915((struct drm_device *)p); \
2434 #define INTEL_INFO(p) (&__I915__(p)->info)
2435 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2436 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2438 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2439 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2440 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2441 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2442 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2443 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2444 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2445 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2446 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2447 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2448 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2449 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2450 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2451 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2452 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2453 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2454 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2455 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2456 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2457 INTEL_DEVID(dev) == 0x0152 || \
2458 INTEL_DEVID(dev) == 0x015a)
2459 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2460 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2461 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2462 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2463 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2464 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2465 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2466 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2467 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2468 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2469 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2470 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2471 (INTEL_DEVID(dev) & 0xf) == 0xe))
2472 /* ULX machines are also considered ULT. */
2473 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2474 (INTEL_DEVID(dev) & 0xf) == 0xe)
2475 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2476 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2477 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2478 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2479 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2480 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2481 /* ULX machines are also considered ULT. */
2482 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2483 INTEL_DEVID(dev) == 0x0A1E)
2484 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2485 INTEL_DEVID(dev) == 0x1913 || \
2486 INTEL_DEVID(dev) == 0x1916 || \
2487 INTEL_DEVID(dev) == 0x1921 || \
2488 INTEL_DEVID(dev) == 0x1926)
2489 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2490 INTEL_DEVID(dev) == 0x1915 || \
2491 INTEL_DEVID(dev) == 0x191E)
2492 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2493 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2494 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2495 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2497 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2499 #define SKL_REVID_A0 (0x0)
2500 #define SKL_REVID_B0 (0x1)
2501 #define SKL_REVID_C0 (0x2)
2502 #define SKL_REVID_D0 (0x3)
2503 #define SKL_REVID_E0 (0x4)
2504 #define SKL_REVID_F0 (0x5)
2506 #define BXT_REVID_A0 (0x0)
2507 #define BXT_REVID_B0 (0x3)
2508 #define BXT_REVID_C0 (0x9)
2511 * The genX designation typically refers to the render engine, so render
2512 * capability related checks should use IS_GEN, while display and other checks
2513 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2516 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2517 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2518 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2519 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2520 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2521 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2522 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2523 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2525 #define RENDER_RING (1<<RCS)
2526 #define BSD_RING (1<<VCS)
2527 #define BLT_RING (1<<BCS)
2528 #define VEBOX_RING (1<<VECS)
2529 #define BSD2_RING (1<<VCS2)
2530 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2531 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2532 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2533 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2534 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2535 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2536 __I915__(dev)->ellc_size)
2537 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2539 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2540 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2541 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2542 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2543 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2545 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2546 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2548 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2549 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2551 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2552 * even when in MSI mode. This results in spurious interrupt warnings if the
2553 * legacy irq no. is shared with another device. The kernel then disables that
2554 * interrupt source and so prevents the other device from working properly.
2556 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2557 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2559 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2560 * rows, which changed the alignment requirements and fence programming.
2562 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2564 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2565 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2567 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2568 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2569 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2571 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2573 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2574 INTEL_INFO(dev)->gen >= 9)
2576 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2577 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2578 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2579 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2581 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2582 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2584 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2585 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2587 #define HAS_CSR(dev) (IS_GEN9(dev))
2589 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev))
2590 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev))
2592 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2593 INTEL_INFO(dev)->gen >= 8)
2595 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2596 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
2598 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2599 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2600 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2601 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2602 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2603 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2604 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2605 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2606 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2608 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2609 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2610 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2611 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2612 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2613 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2614 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2615 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2617 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2619 /* DPF == dynamic parity feature */
2620 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2621 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2623 #define GT_FREQUENCY_MULTIPLIER 50
2624 #define GEN9_FREQ_SCALER 3
2626 #include "i915_trace.h"
2628 extern const struct drm_ioctl_desc i915_ioctls[];
2629 extern int i915_max_ioctl;
2631 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2632 extern int i915_resume_switcheroo(struct drm_device *dev);
2635 struct i915_params {
2637 int panel_ignore_lid;
2639 int lvds_channel_mode;
2641 int vbt_sdvo_panel_type;
2645 int enable_execlists;
2647 unsigned int preliminary_hw_support;
2648 int disable_power_well;
2650 int invert_brightness;
2651 int enable_cmd_parser;
2652 /* leave bools at the end to not create holes */
2653 bool enable_hangcheck;
2655 bool prefault_disable;
2656 bool load_detect_test;
2658 bool disable_display;
2659 bool disable_vtd_wa;
2660 bool enable_guc_submission;
2664 bool verbose_state_checks;
2665 bool nuclear_pageflip;
2668 extern struct i915_params i915 __read_mostly;
2671 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2672 extern int i915_driver_unload(struct drm_device *);
2673 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2674 extern void i915_driver_lastclose(struct drm_device * dev);
2675 extern void i915_driver_preclose(struct drm_device *dev,
2676 struct drm_file *file);
2677 extern void i915_driver_postclose(struct drm_device *dev,
2678 struct drm_file *file);
2679 #ifdef CONFIG_COMPAT
2680 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2683 extern int intel_gpu_reset(struct drm_device *dev);
2684 extern bool intel_has_gpu_reset(struct drm_device *dev);
2685 extern int i915_reset(struct drm_device *dev);
2686 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2687 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2688 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2689 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2690 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2691 void i915_firmware_load_error_print(const char *fw_path, int err);
2693 /* intel_hotplug.c */
2694 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2695 void intel_hpd_init(struct drm_i915_private *dev_priv);
2696 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2697 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2698 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2701 void i915_queue_hangcheck(struct drm_device *dev);
2703 void i915_handle_error(struct drm_device *dev, bool wedged,
2704 const char *fmt, ...);
2706 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2707 int intel_irq_install(struct drm_i915_private *dev_priv);
2708 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2710 extern void intel_uncore_sanitize(struct drm_device *dev);
2711 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2712 bool restore_forcewake);
2713 extern void intel_uncore_init(struct drm_device *dev);
2714 extern void intel_uncore_check_errors(struct drm_device *dev);
2715 extern void intel_uncore_fini(struct drm_device *dev);
2716 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2717 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2718 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2719 enum forcewake_domains domains);
2720 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2721 enum forcewake_domains domains);
2722 /* Like above but the caller must manage the uncore.lock itself.
2723 * Must be used with I915_READ_FW and friends.
2725 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2726 enum forcewake_domains domains);
2727 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2728 enum forcewake_domains domains);
2729 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2730 static inline bool intel_vgpu_active(struct drm_device *dev)
2732 return to_i915(dev)->vgpu.active;
2736 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2740 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2743 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2744 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2745 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2749 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2751 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2752 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2753 uint32_t interrupt_mask,
2754 uint32_t enabled_irq_mask);
2755 #define ibx_enable_display_interrupt(dev_priv, bits) \
2756 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2757 #define ibx_disable_display_interrupt(dev_priv, bits) \
2758 ibx_display_interrupt_update((dev_priv), (bits), 0)
2761 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2762 struct drm_file *file_priv);
2763 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2764 struct drm_file *file_priv);
2765 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2766 struct drm_file *file_priv);
2767 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2768 struct drm_file *file_priv);
2769 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2770 struct drm_file *file_priv);
2771 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2772 struct drm_file *file_priv);
2773 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2774 struct drm_file *file_priv);
2775 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2776 struct drm_i915_gem_request *req);
2777 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2778 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2779 struct drm_i915_gem_execbuffer2 *args,
2780 struct list_head *vmas);
2781 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2782 struct drm_file *file_priv);
2783 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2784 struct drm_file *file_priv);
2785 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2786 struct drm_file *file_priv);
2787 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2788 struct drm_file *file);
2789 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2790 struct drm_file *file);
2791 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2792 struct drm_file *file_priv);
2793 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2794 struct drm_file *file_priv);
2795 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2796 struct drm_file *file_priv);
2797 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2798 struct drm_file *file_priv);
2799 int i915_gem_init_userptr(struct drm_device *dev);
2800 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2801 struct drm_file *file);
2802 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2803 struct drm_file *file_priv);
2804 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2805 struct drm_file *file_priv);
2806 void i915_gem_load(struct drm_device *dev);
2807 void *i915_gem_object_alloc(struct drm_device *dev);
2808 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2809 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2810 const struct drm_i915_gem_object_ops *ops);
2811 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2813 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2814 struct drm_device *dev, const void *data, size_t size);
2815 void i915_gem_free_object(struct drm_gem_object *obj);
2816 void i915_gem_vma_destroy(struct i915_vma *vma);
2818 /* Flags used by pin/bind&friends. */
2819 #define PIN_MAPPABLE (1<<0)
2820 #define PIN_NONBLOCK (1<<1)
2821 #define PIN_GLOBAL (1<<2)
2822 #define PIN_OFFSET_BIAS (1<<3)
2823 #define PIN_USER (1<<4)
2824 #define PIN_UPDATE (1<<5)
2825 #define PIN_ZONE_4G (1<<6)
2826 #define PIN_HIGH (1<<7)
2827 #define PIN_OFFSET_MASK (~4095)
2829 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2830 struct i915_address_space *vm,
2834 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2835 const struct i915_ggtt_view *view,
2839 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2841 int __must_check i915_vma_unbind(struct i915_vma *vma);
2843 * BEWARE: Do not use the function below unless you can _absolutely_
2844 * _guarantee_ VMA in question is _not in use_ anywhere.
2846 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2847 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2848 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2849 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2851 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2852 int *needs_clflush);
2854 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2856 static inline int __sg_page_count(struct scatterlist *sg)
2858 return sg->length >> PAGE_SHIFT;
2861 static inline struct page *
2862 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2864 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2867 if (n < obj->get_page.last) {
2868 obj->get_page.sg = obj->pages->sgl;
2869 obj->get_page.last = 0;
2872 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2873 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2874 if (unlikely(sg_is_chain(obj->get_page.sg)))
2875 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2878 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2881 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2883 BUG_ON(obj->pages == NULL);
2884 obj->pages_pin_count++;
2886 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2888 BUG_ON(obj->pages_pin_count == 0);
2889 obj->pages_pin_count--;
2892 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2893 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2894 struct intel_engine_cs *to,
2895 struct drm_i915_gem_request **to_req);
2896 void i915_vma_move_to_active(struct i915_vma *vma,
2897 struct drm_i915_gem_request *req);
2898 int i915_gem_dumb_create(struct drm_file *file_priv,
2899 struct drm_device *dev,
2900 struct drm_mode_create_dumb *args);
2901 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2902 uint32_t handle, uint64_t *offset);
2904 * Returns true if seq1 is later than seq2.
2907 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2909 return (int32_t)(seq1 - seq2) >= 0;
2912 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2913 bool lazy_coherency)
2917 BUG_ON(req == NULL);
2919 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2921 return i915_seqno_passed(seqno, req->seqno);
2924 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2925 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2927 struct drm_i915_gem_request *
2928 i915_gem_find_active_request(struct intel_engine_cs *ring);
2930 bool i915_gem_retire_requests(struct drm_device *dev);
2931 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2932 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2933 bool interruptible);
2935 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2937 return unlikely(atomic_read(&error->reset_counter)
2938 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2941 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2943 return atomic_read(&error->reset_counter) & I915_WEDGED;
2946 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2948 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2951 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2953 return dev_priv->gpu_error.stop_rings == 0 ||
2954 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2957 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2959 return dev_priv->gpu_error.stop_rings == 0 ||
2960 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2963 void i915_gem_reset(struct drm_device *dev);
2964 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2965 int __must_check i915_gem_init(struct drm_device *dev);
2966 int i915_gem_init_rings(struct drm_device *dev);
2967 int __must_check i915_gem_init_hw(struct drm_device *dev);
2968 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
2969 void i915_gem_init_swizzling(struct drm_device *dev);
2970 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2971 int __must_check i915_gpu_idle(struct drm_device *dev);
2972 int __must_check i915_gem_suspend(struct drm_device *dev);
2973 void __i915_add_request(struct drm_i915_gem_request *req,
2974 struct drm_i915_gem_object *batch_obj,
2976 #define i915_add_request(req) \
2977 __i915_add_request(req, NULL, true)
2978 #define i915_add_request_no_flush(req) \
2979 __i915_add_request(req, NULL, false)
2980 int __i915_wait_request(struct drm_i915_gem_request *req,
2981 unsigned reset_counter,
2984 struct intel_rps_client *rps);
2985 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2986 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2988 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2991 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2994 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2996 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2998 struct intel_engine_cs *pipelined,
2999 struct drm_i915_gem_request **pipelined_request,
3000 const struct i915_ggtt_view *view);
3001 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3002 const struct i915_ggtt_view *view);
3003 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3005 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3006 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3009 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3011 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3012 int tiling_mode, bool fenced);
3014 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3015 enum i915_cache_level cache_level);
3017 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3018 struct dma_buf *dma_buf);
3020 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3021 struct drm_gem_object *gem_obj, int flags);
3023 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3024 const struct i915_ggtt_view *view);
3025 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3026 struct i915_address_space *vm);
3028 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3030 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3033 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3034 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3035 const struct i915_ggtt_view *view);
3036 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3037 struct i915_address_space *vm);
3039 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3040 struct i915_address_space *vm);
3042 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3043 struct i915_address_space *vm);
3045 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3046 const struct i915_ggtt_view *view);
3049 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3050 struct i915_address_space *vm);
3052 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3053 const struct i915_ggtt_view *view);
3055 static inline struct i915_vma *
3056 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3058 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3060 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3062 /* Some GGTT VM helpers */
3063 #define i915_obj_to_ggtt(obj) \
3064 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3065 static inline bool i915_is_ggtt(struct i915_address_space *vm)
3067 struct i915_address_space *ggtt =
3068 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3072 static inline struct i915_hw_ppgtt *
3073 i915_vm_to_ppgtt(struct i915_address_space *vm)
3075 WARN_ON(i915_is_ggtt(vm));
3077 return container_of(vm, struct i915_hw_ppgtt, base);
3081 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3083 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3086 static inline unsigned long
3087 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3089 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3092 static inline int __must_check
3093 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3097 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3098 alignment, flags | PIN_GLOBAL);
3102 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3104 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3107 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3108 const struct i915_ggtt_view *view);
3110 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3112 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3115 /* i915_gem_fence.c */
3116 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3117 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3119 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3120 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3122 void i915_gem_restore_fences(struct drm_device *dev);
3124 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3125 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3126 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3128 /* i915_gem_context.c */
3129 int __must_check i915_gem_context_init(struct drm_device *dev);
3130 void i915_gem_context_fini(struct drm_device *dev);
3131 void i915_gem_context_reset(struct drm_device *dev);
3132 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3133 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3134 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3135 int i915_switch_context(struct drm_i915_gem_request *req);
3136 struct intel_context *
3137 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3138 void i915_gem_context_free(struct kref *ctx_ref);
3139 struct drm_i915_gem_object *
3140 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3141 static inline void i915_gem_context_reference(struct intel_context *ctx)
3143 kref_get(&ctx->ref);
3146 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3148 kref_put(&ctx->ref, i915_gem_context_free);
3151 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3153 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3156 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3157 struct drm_file *file);
3158 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3159 struct drm_file *file);
3160 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3161 struct drm_file *file_priv);
3162 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3163 struct drm_file *file_priv);
3165 /* i915_gem_evict.c */
3166 int __must_check i915_gem_evict_something(struct drm_device *dev,
3167 struct i915_address_space *vm,
3170 unsigned cache_level,
3171 unsigned long start,
3174 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3176 /* belongs in i915_gem_gtt.h */
3177 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3179 if (INTEL_INFO(dev)->gen < 6)
3180 intel_gtt_chipset_flush();
3183 /* i915_gem_stolen.c */
3184 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3185 struct drm_mm_node *node, u64 size,
3186 unsigned alignment);
3187 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3188 struct drm_mm_node *node, u64 size,
3189 unsigned alignment, u64 start,
3191 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3192 struct drm_mm_node *node);
3193 int i915_gem_init_stolen(struct drm_device *dev);
3194 void i915_gem_cleanup_stolen(struct drm_device *dev);
3195 struct drm_i915_gem_object *
3196 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3197 struct drm_i915_gem_object *
3198 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3203 /* i915_gem_shrinker.c */
3204 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3205 unsigned long target,
3207 #define I915_SHRINK_PURGEABLE 0x1
3208 #define I915_SHRINK_UNBOUND 0x2
3209 #define I915_SHRINK_BOUND 0x4
3210 #define I915_SHRINK_ACTIVE 0x8
3211 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3212 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3215 /* i915_gem_tiling.c */
3216 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3218 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3220 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3221 obj->tiling_mode != I915_TILING_NONE;
3224 /* i915_gem_debug.c */
3226 int i915_verify_lists(struct drm_device *dev);
3228 #define i915_verify_lists(dev) 0
3231 /* i915_debugfs.c */
3232 int i915_debugfs_init(struct drm_minor *minor);
3233 void i915_debugfs_cleanup(struct drm_minor *minor);
3234 #ifdef CONFIG_DEBUG_FS
3235 int i915_debugfs_connector_add(struct drm_connector *connector);
3236 void intel_display_crc_init(struct drm_device *dev);
3238 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3240 static inline void intel_display_crc_init(struct drm_device *dev) {}
3243 /* i915_gpu_error.c */
3245 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3246 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3247 const struct i915_error_state_file_priv *error);
3248 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3249 struct drm_i915_private *i915,
3250 size_t count, loff_t pos);
3251 static inline void i915_error_state_buf_release(
3252 struct drm_i915_error_state_buf *eb)
3256 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3257 const char *error_msg);
3258 void i915_error_state_get(struct drm_device *dev,
3259 struct i915_error_state_file_priv *error_priv);
3260 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3261 void i915_destroy_error_state(struct drm_device *dev);
3263 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3264 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3266 /* i915_cmd_parser.c */
3267 int i915_cmd_parser_get_version(void);
3268 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3269 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3270 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3271 int i915_parse_cmds(struct intel_engine_cs *ring,
3272 struct drm_i915_gem_object *batch_obj,
3273 struct drm_i915_gem_object *shadow_batch_obj,
3274 u32 batch_start_offset,
3278 /* i915_suspend.c */
3279 extern int i915_save_state(struct drm_device *dev);
3280 extern int i915_restore_state(struct drm_device *dev);
3283 void i915_setup_sysfs(struct drm_device *dev_priv);
3284 void i915_teardown_sysfs(struct drm_device *dev_priv);
3287 extern int intel_setup_gmbus(struct drm_device *dev);
3288 extern void intel_teardown_gmbus(struct drm_device *dev);
3289 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3292 extern struct i2c_adapter *
3293 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3294 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3295 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3296 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3298 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3300 extern void intel_i2c_reset(struct drm_device *dev);
3302 /* intel_opregion.c */
3304 extern int intel_opregion_setup(struct drm_device *dev);
3305 extern void intel_opregion_init(struct drm_device *dev);
3306 extern void intel_opregion_fini(struct drm_device *dev);
3307 extern void intel_opregion_asle_intr(struct drm_device *dev);
3308 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3310 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3313 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3314 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3315 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3316 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3318 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3323 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3331 extern void intel_register_dsm_handler(void);
3332 extern void intel_unregister_dsm_handler(void);
3334 static inline void intel_register_dsm_handler(void) { return; }
3335 static inline void intel_unregister_dsm_handler(void) { return; }
3336 #endif /* CONFIG_ACPI */
3339 extern void intel_modeset_init_hw(struct drm_device *dev);
3340 extern void intel_modeset_init(struct drm_device *dev);
3341 extern void intel_modeset_gem_init(struct drm_device *dev);
3342 extern void intel_modeset_cleanup(struct drm_device *dev);
3343 extern void intel_connector_unregister(struct intel_connector *);
3344 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3345 extern void intel_display_resume(struct drm_device *dev);
3346 extern void i915_redisable_vga(struct drm_device *dev);
3347 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3348 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3349 extern void intel_init_pch_refclk(struct drm_device *dev);
3350 extern void intel_set_rps(struct drm_device *dev, u8 val);
3351 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3353 extern void intel_detect_pch(struct drm_device *dev);
3354 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3355 extern int intel_enable_rc6(const struct drm_device *dev);
3357 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3358 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3359 struct drm_file *file);
3360 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3361 struct drm_file *file);
3364 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3365 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3366 struct intel_overlay_error_state *error);
3368 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3369 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3370 struct drm_device *dev,
3371 struct intel_display_error_state *error);
3373 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3374 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3376 /* intel_sideband.c */
3377 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3378 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3379 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3380 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3381 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3382 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3383 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3384 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3385 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3386 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3387 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3388 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3389 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3390 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3391 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3392 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3393 enum intel_sbi_destination destination);
3394 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3395 enum intel_sbi_destination destination);
3396 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3397 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3399 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3400 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3402 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3403 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3405 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3406 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3407 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3408 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3410 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3411 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3412 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3413 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3415 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3416 * will be implemented using 2 32-bit writes in an arbitrary order with
3417 * an arbitrary delay between them. This can cause the hardware to
3418 * act upon the intermediate value, possibly leading to corruption and
3419 * machine death. You have been warned.
3421 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3422 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3424 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3425 u32 upper, lower, old_upper, loop = 0; \
3426 upper = I915_READ(upper_reg); \
3428 old_upper = upper; \
3429 lower = I915_READ(lower_reg); \
3430 upper = I915_READ(upper_reg); \
3431 } while (upper != old_upper && loop++ < 2); \
3432 (u64)upper << 32 | lower; })
3434 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3435 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3437 /* These are untraced mmio-accessors that are only valid to be used inside
3438 * criticial sections inside IRQ handlers where forcewake is explicitly
3440 * Think twice, and think again, before using these.
3441 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3442 * intel_uncore_forcewake_irqunlock().
3444 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3445 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3446 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3448 /* "Broadcast RGB" property */
3449 #define INTEL_BROADCAST_RGB_AUTO 0
3450 #define INTEL_BROADCAST_RGB_FULL 1
3451 #define INTEL_BROADCAST_RGB_LIMITED 2
3453 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3455 if (IS_VALLEYVIEW(dev))
3456 return VLV_VGACNTRL;
3457 else if (INTEL_INFO(dev)->gen >= 5)
3458 return CPU_VGACNTRL;
3463 static inline void __user *to_user_ptr(u64 address)
3465 return (void __user *)(uintptr_t)address;
3468 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3470 unsigned long j = msecs_to_jiffies(m);
3472 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3475 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3477 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3480 static inline unsigned long
3481 timespec_to_jiffies_timeout(const struct timespec *value)
3483 unsigned long j = timespec_to_jiffies(value);
3485 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3489 * If you need to wait X milliseconds between events A and B, but event B
3490 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3491 * when event A happened, then just before event B you call this function and
3492 * pass the timestamp as the first argument, and X as the second argument.
3495 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3497 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3500 * Don't re-read the value of "jiffies" every time since it may change
3501 * behind our back and break the math.
3503 tmp_jiffies = jiffies;
3504 target_jiffies = timestamp_jiffies +
3505 msecs_to_jiffies_timeout(to_wait_ms);
3507 if (time_after(target_jiffies, tmp_jiffies)) {
3508 remaining_jiffies = target_jiffies - tmp_jiffies;
3509 while (remaining_jiffies)
3511 schedule_timeout_uninterruptible(remaining_jiffies);
3515 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3516 struct drm_i915_gem_request *req)
3518 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3519 i915_gem_request_assign(&ring->trace_irq_req, req);