1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <drm/intel-gtt.h>
40 #include <linux/backlight.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
44 /* General customization:
47 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
49 #define DRIVER_NAME "i915"
50 #define DRIVER_DESC "Intel Graphics"
51 #define DRIVER_DATE "20080730"
59 #define pipe_name(p) ((p) + 'A')
66 #define plane_name(p) ((p) + 'A')
76 #define port_name(p) ((p) + 'A')
78 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
80 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
82 struct intel_pch_pll {
83 int refcount; /* count of number of CRTCs sharing this PLL */
84 int active; /* count of number of active CRTCs (i.e. DPMS on) */
85 bool on; /* is the PLL actually active? Disabled during modeset */
90 #define I915_NUM_PLLS 2
95 * 1.2: Add Power Management
96 * 1.3: Add vblank support
97 * 1.4: Fix cmdbuffer path, add heap destroy
98 * 1.5: Add vblank pipe configuration
99 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
100 * - Support vertical blank on secondary display pipe
102 #define DRIVER_MAJOR 1
103 #define DRIVER_MINOR 6
104 #define DRIVER_PATCHLEVEL 0
106 #define WATCH_COHERENCY 0
107 #define WATCH_LISTS 0
109 #define I915_GEM_PHYS_CURSOR_0 1
110 #define I915_GEM_PHYS_CURSOR_1 2
111 #define I915_GEM_PHYS_OVERLAY_REGS 3
112 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
114 struct drm_i915_gem_phys_object {
116 struct page **page_list;
117 drm_dma_handle_t *handle;
118 struct drm_i915_gem_object *cur_obj;
122 struct mem_block *next;
123 struct mem_block *prev;
126 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
129 struct opregion_header;
130 struct opregion_acpi;
131 struct opregion_swsci;
132 struct opregion_asle;
133 struct drm_i915_private;
135 struct intel_opregion {
136 struct opregion_header __iomem *header;
137 struct opregion_acpi __iomem *acpi;
138 struct opregion_swsci __iomem *swsci;
139 struct opregion_asle __iomem *asle;
141 u32 __iomem *lid_state;
143 #define OPREGION_SIZE (8*1024)
145 struct intel_overlay;
146 struct intel_overlay_error_state;
148 struct drm_i915_master_private {
149 drm_local_map_t *sarea;
150 struct _drm_i915_sarea *sarea_priv;
152 #define I915_FENCE_REG_NONE -1
153 #define I915_MAX_NUM_FENCES 16
154 /* 16 fences + sign bit for FENCE_REG_NONE */
155 #define I915_MAX_NUM_FENCE_BITS 5
157 struct drm_i915_fence_reg {
158 struct list_head lru_list;
159 struct drm_i915_gem_object *obj;
163 struct sdvo_device_mapping {
172 struct intel_display_error_state;
174 struct drm_i915_error_state {
179 bool waiting[I915_NUM_RINGS];
180 u32 pipestat[I915_MAX_PIPES];
181 u32 tail[I915_NUM_RINGS];
182 u32 head[I915_NUM_RINGS];
183 u32 ipeir[I915_NUM_RINGS];
184 u32 ipehr[I915_NUM_RINGS];
185 u32 instdone[I915_NUM_RINGS];
186 u32 acthd[I915_NUM_RINGS];
187 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
188 /* our own tracking of ring head and tail */
189 u32 cpu_ring_head[I915_NUM_RINGS];
190 u32 cpu_ring_tail[I915_NUM_RINGS];
191 u32 error; /* gen6+ */
192 u32 instpm[I915_NUM_RINGS];
193 u32 instps[I915_NUM_RINGS];
195 u32 seqno[I915_NUM_RINGS];
197 u32 fault_reg[I915_NUM_RINGS];
199 u32 faddr[I915_NUM_RINGS];
200 u64 fence[I915_MAX_NUM_FENCES];
202 struct drm_i915_error_ring {
203 struct drm_i915_error_object {
207 } *ringbuffer, *batchbuffer;
208 struct drm_i915_error_request {
214 } ring[I915_NUM_RINGS];
215 struct drm_i915_error_buffer {
222 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
229 } *active_bo, *pinned_bo;
230 u32 active_bo_count, pinned_bo_count;
231 struct intel_overlay_error_state *overlay;
232 struct intel_display_error_state *display;
235 struct drm_i915_display_funcs {
236 void (*dpms)(struct drm_crtc *crtc, int mode);
237 bool (*fbc_enabled)(struct drm_device *dev);
238 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
239 void (*disable_fbc)(struct drm_device *dev);
240 int (*get_display_clock_speed)(struct drm_device *dev);
241 int (*get_fifo_size)(struct drm_device *dev, int plane);
242 void (*update_wm)(struct drm_device *dev);
243 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
244 uint32_t sprite_width, int pixel_size);
245 void (*sanitize_pm)(struct drm_device *dev);
246 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
247 struct drm_display_mode *mode);
248 int (*crtc_mode_set)(struct drm_crtc *crtc,
249 struct drm_display_mode *mode,
250 struct drm_display_mode *adjusted_mode,
252 struct drm_framebuffer *old_fb);
253 void (*off)(struct drm_crtc *crtc);
254 void (*write_eld)(struct drm_connector *connector,
255 struct drm_crtc *crtc);
256 void (*fdi_link_train)(struct drm_crtc *crtc);
257 void (*init_clock_gating)(struct drm_device *dev);
258 void (*init_pch_clock_gating)(struct drm_device *dev);
259 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
260 struct drm_framebuffer *fb,
261 struct drm_i915_gem_object *obj);
262 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
264 void (*force_wake_get)(struct drm_i915_private *dev_priv);
265 void (*force_wake_put)(struct drm_i915_private *dev_priv);
266 /* clock updates for mode set */
268 /* render clock increase/decrease */
269 /* display clock increase/decrease */
270 /* pll clock increase/decrease */
273 struct intel_device_info {
293 u8 cursor_needs_physical:1;
295 u8 overlay_needs_physical:1;
302 #define I915_PPGTT_PD_ENTRIES 512
303 #define I915_PPGTT_PT_ENTRIES 1024
304 struct i915_hw_ppgtt {
305 unsigned num_pd_entries;
306 struct page **pt_pages;
308 dma_addr_t *pt_dma_addr;
309 dma_addr_t scratch_page_dma_addr;
313 FBC_NO_OUTPUT, /* no outputs enabled to compress */
314 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
315 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
316 FBC_MODE_TOO_LARGE, /* mode too large for compression */
317 FBC_BAD_PLANE, /* fbc not supported on plane */
318 FBC_NOT_TILED, /* buffer not tiled */
319 FBC_MULTIPLE_PIPES, /* more than one pipe active */
324 PCH_IBX, /* Ibexpeak PCH */
325 PCH_CPT, /* Cougarpoint PCH */
326 PCH_LPT, /* Lynxpoint PCH */
329 #define QUIRK_PIPEA_FORCE (1<<0)
330 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
331 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
334 struct intel_fbc_work;
337 struct i2c_adapter adapter;
341 struct i2c_algo_bit_data bit_algo;
342 struct drm_i915_private *dev_priv;
345 typedef struct drm_i915_private {
346 struct drm_device *dev;
348 const struct intel_device_info *info;
350 int relative_constants_mode;
353 /** gt_fifo_count and the subsequent register write are synchronized
354 * with dev->struct_mutex. */
355 unsigned gt_fifo_count;
356 /** forcewake_count is protected by gt_lock */
357 unsigned forcewake_count;
358 /** gt_lock is also taken in irq contexts. */
359 struct spinlock gt_lock;
361 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
363 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
364 * controller on different i2c buses. */
365 struct mutex gmbus_mutex;
368 * Base address of the gmbus and gpio block.
370 uint32_t gpio_mmio_base;
372 struct pci_dev *bridge_dev;
373 struct intel_ring_buffer ring[I915_NUM_RINGS];
376 drm_dma_handle_t *status_page_dmah;
378 struct drm_i915_gem_object *pwrctx;
379 struct drm_i915_gem_object *renderctx;
381 struct resource mch_res;
389 atomic_t irq_received;
391 /* protects the irq masks */
394 /* DPIO indirect register protection */
395 spinlock_t dpio_lock;
397 /** Cached value of IMR to avoid reads in updating the bitfield */
403 u32 hotplug_supported_mask;
404 struct work_struct hotplug_work;
406 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
410 /* For hangcheck timer */
411 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
412 struct timer_list hangcheck_timer;
414 uint32_t last_acthd[I915_NUM_RINGS];
415 uint32_t last_instdone;
416 uint32_t last_instdone1;
418 unsigned int stop_rings;
420 unsigned long cfb_size;
422 enum plane cfb_plane;
424 struct intel_fbc_work *fbc_work;
426 struct intel_opregion opregion;
429 struct intel_overlay *overlay;
430 bool sprite_scaling_enabled;
433 int backlight_level; /* restore backlight to this value */
434 bool backlight_enabled;
435 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
436 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
438 /* Feature bits from the VBIOS */
439 unsigned int int_tv_support:1;
440 unsigned int lvds_dither:1;
441 unsigned int lvds_vbt:1;
442 unsigned int int_crt_support:1;
443 unsigned int lvds_use_ssc:1;
444 unsigned int display_clock_mode:1;
446 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
447 unsigned int lvds_val; /* used for checking LVDS channel mode */
457 struct edp_power_seq pps;
459 bool no_aux_handshake;
461 struct notifier_block lid_notifier;
464 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
465 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
466 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
468 unsigned int fsb_freq, mem_freq, is_ddr3;
470 spinlock_t error_lock;
471 /* Protected by dev->error_lock. */
472 struct drm_i915_error_state *first_error;
473 struct work_struct error_work;
474 struct completion error_completion;
475 struct workqueue_struct *wq;
477 /* Display functions */
478 struct drm_i915_display_funcs display;
480 /* PCH chipset type */
481 enum intel_pch pch_type;
483 unsigned long quirks;
508 u32 saveTRANS_HTOTAL_A;
509 u32 saveTRANS_HBLANK_A;
510 u32 saveTRANS_HSYNC_A;
511 u32 saveTRANS_VTOTAL_A;
512 u32 saveTRANS_VBLANK_A;
513 u32 saveTRANS_VSYNC_A;
521 u32 savePFIT_PGM_RATIOS;
522 u32 saveBLC_HIST_CTL;
524 u32 saveBLC_PWM_CTL2;
525 u32 saveBLC_CPU_PWM_CTL;
526 u32 saveBLC_CPU_PWM_CTL2;
539 u32 saveTRANS_HTOTAL_B;
540 u32 saveTRANS_HBLANK_B;
541 u32 saveTRANS_HSYNC_B;
542 u32 saveTRANS_VTOTAL_B;
543 u32 saveTRANS_VBLANK_B;
544 u32 saveTRANS_VSYNC_B;
558 u32 savePP_ON_DELAYS;
559 u32 savePP_OFF_DELAYS;
567 u32 savePFIT_CONTROL;
568 u32 save_palette_a[256];
569 u32 save_palette_b[256];
570 u32 saveDPFC_CB_BASE;
571 u32 saveFBC_CFB_BASE;
574 u32 saveFBC_CONTROL2;
584 u32 saveCACHE_MODE_0;
585 u32 saveMI_ARB_STATE;
596 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
607 u32 savePIPEA_GMCH_DATA_M;
608 u32 savePIPEB_GMCH_DATA_M;
609 u32 savePIPEA_GMCH_DATA_N;
610 u32 savePIPEB_GMCH_DATA_N;
611 u32 savePIPEA_DP_LINK_M;
612 u32 savePIPEB_DP_LINK_M;
613 u32 savePIPEA_DP_LINK_N;
614 u32 savePIPEB_DP_LINK_N;
625 u32 savePCH_DREF_CONTROL;
626 u32 saveDISP_ARB_CTL;
627 u32 savePIPEA_DATA_M1;
628 u32 savePIPEA_DATA_N1;
629 u32 savePIPEA_LINK_M1;
630 u32 savePIPEA_LINK_N1;
631 u32 savePIPEB_DATA_M1;
632 u32 savePIPEB_DATA_N1;
633 u32 savePIPEB_LINK_M1;
634 u32 savePIPEB_LINK_N1;
635 u32 saveMCHBAR_RENDER_STANDBY;
636 u32 savePCH_PORT_HOTPLUG;
639 /** Bridge to intel-gtt-ko */
640 const struct intel_gtt *gtt;
641 /** Memory allocator for GTT stolen memory */
642 struct drm_mm stolen;
643 /** Memory allocator for GTT */
644 struct drm_mm gtt_space;
645 /** List of all objects in gtt_space. Used to restore gtt
646 * mappings on resume */
647 struct list_head gtt_list;
649 /** Usable portion of the GTT for GEM */
650 unsigned long gtt_start;
651 unsigned long gtt_mappable_end;
652 unsigned long gtt_end;
654 struct io_mapping *gtt_mapping;
657 /** PPGTT used for aliasing the PPGTT with the GTT */
658 struct i915_hw_ppgtt *aliasing_ppgtt;
662 struct shrinker inactive_shrinker;
665 * List of objects currently involved in rendering.
667 * Includes buffers having the contents of their GPU caches
668 * flushed, not necessarily primitives. last_rendering_seqno
669 * represents when the rendering involved will be completed.
671 * A reference is held on the buffer while on this list.
673 struct list_head active_list;
676 * List of objects which are not in the ringbuffer but which
677 * still have a write_domain which needs to be flushed before
680 * last_rendering_seqno is 0 while an object is in this list.
682 * A reference is held on the buffer while on this list.
684 struct list_head flushing_list;
687 * LRU list of objects which are not in the ringbuffer and
688 * are ready to unbind, but are still in the GTT.
690 * last_rendering_seqno is 0 while an object is in this list.
692 * A reference is not held on the buffer while on this list,
693 * as merely being GTT-bound shouldn't prevent its being
694 * freed, and we'll pull it off the list in the free path.
696 struct list_head inactive_list;
698 /** LRU list of objects with fence regs on them. */
699 struct list_head fence_list;
702 * We leave the user IRQ off as much as possible,
703 * but this means that requests will finish and never
704 * be retired once the system goes idle. Set a timer to
705 * fire periodically while the ring is running. When it
706 * fires, go retire requests.
708 struct delayed_work retire_work;
711 * Are we in a non-interruptible section of code like
717 * Flag if the X Server, and thus DRM, is not currently in
718 * control of the device.
720 * This is set between LeaveVT and EnterVT. It needs to be
721 * replaced with a semaphore. It also needs to be
722 * transitioned away from for kernel modesetting.
727 * Flag if the hardware appears to be wedged.
729 * This is set when attempts to idle the device timeout.
730 * It prevents command submission from occurring and makes
731 * every pending request fail
735 /** Bit 6 swizzling required for X tiling */
736 uint32_t bit_6_swizzle_x;
737 /** Bit 6 swizzling required for Y tiling */
738 uint32_t bit_6_swizzle_y;
740 /* storage for physical objects */
741 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
743 /* accounting, useful for userland debugging */
745 size_t mappable_gtt_total;
746 size_t object_memory;
750 /* Old dri1 support infrastructure, beware the dragons ya fools entering
753 unsigned allow_batchbuffer : 1;
754 u32 __iomem *gfx_hws_cpu_addr;
757 /* Kernel Modesetting */
759 struct sdvo_device_mapping sdvo_mappings[2];
760 /* indicate whether the LVDS_BORDER should be enabled or not */
761 unsigned int lvds_border_bits;
762 /* Panel fitter placement and size for Ironlake+ */
763 u32 pch_pf_pos, pch_pf_size;
765 struct drm_crtc *plane_to_crtc_mapping[3];
766 struct drm_crtc *pipe_to_crtc_mapping[3];
767 wait_queue_head_t pending_flip_queue;
769 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
771 /* Reclocking support */
772 bool render_reclock_avail;
773 bool lvds_downclock_avail;
774 /* indicates the reduced downclock for LVDS*/
776 struct work_struct idle_work;
777 struct timer_list idle_timer;
781 struct child_device_config *child_dev;
782 struct drm_connector *int_lvds_connector;
783 struct drm_connector *int_edp_connector;
785 bool mchbar_need_disable;
787 struct work_struct rps_work;
798 unsigned long last_time1;
799 unsigned long chipset_power;
801 struct timespec last_time2;
802 unsigned long gfx_power;
806 spinlock_t *mchdev_lock;
808 enum no_fbc_reason no_fbc_reason;
810 struct drm_mm_node *compressed_fb;
811 struct drm_mm_node *compressed_llb;
813 unsigned long last_gpu_reset;
815 /* list of fbdev register on this device */
816 struct intel_fbdev *fbdev;
818 struct backlight_device *backlight;
820 struct drm_property *broadcast_rgb_property;
821 struct drm_property *force_audio_property;
823 struct work_struct parity_error_work;
824 } drm_i915_private_t;
826 /* Iterate over initialised rings */
827 #define for_each_ring(ring__, dev_priv__, i__) \
828 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
829 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
831 enum hdmi_force_audio {
832 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
833 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
834 HDMI_AUDIO_AUTO, /* trust EDID */
835 HDMI_AUDIO_ON, /* force turn on HDMI audio */
838 enum i915_cache_level {
841 I915_CACHE_LLC_MLC, /* gen6+ */
844 struct drm_i915_gem_object {
845 struct drm_gem_object base;
847 /** Current space allocated to this object in the GTT, if any. */
848 struct drm_mm_node *gtt_space;
849 struct list_head gtt_list;
851 /** This object's place on the active/flushing/inactive lists */
852 struct list_head ring_list;
853 struct list_head mm_list;
854 /** This object's place on GPU write list */
855 struct list_head gpu_write_list;
856 /** This object's place in the batchbuffer or on the eviction list */
857 struct list_head exec_list;
860 * This is set if the object is on the active or flushing lists
861 * (has pending rendering), and is not set if it's on inactive (ready
864 unsigned int active:1;
867 * This is set if the object has been written to since last bound
870 unsigned int dirty:1;
873 * This is set if the object has been written to since the last
876 unsigned int pending_gpu_write:1;
879 * Fence register bits (if any) for this object. Will be set
880 * as needed when mapped into the GTT.
881 * Protected by dev->struct_mutex.
883 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
886 * Advice: are the backing pages purgeable?
891 * Current tiling mode for the object.
893 unsigned int tiling_mode:2;
895 * Whether the tiling parameters for the currently associated fence
896 * register have changed. Note that for the purposes of tracking
897 * tiling changes we also treat the unfenced register, the register
898 * slot that the object occupies whilst it executes a fenced
899 * command (such as BLT on gen2/3), as a "fence".
901 unsigned int fence_dirty:1;
903 /** How many users have pinned this object in GTT space. The following
904 * users can each hold at most one reference: pwrite/pread, pin_ioctl
905 * (via user_pin_count), execbuffer (objects are not allowed multiple
906 * times for the same batchbuffer), and the framebuffer code. When
907 * switching/pageflipping, the framebuffer code has at most two buffers
910 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
911 * bits with absolutely no headroom. So use 4 bits. */
912 unsigned int pin_count:4;
913 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
916 * Is the object at the current location in the gtt mappable and
917 * fenceable? Used to avoid costly recalculations.
919 unsigned int map_and_fenceable:1;
922 * Whether the current gtt mapping needs to be mappable (and isn't just
923 * mappable by accident). Track pin and fault separate for a more
924 * accurate mappable working set.
926 unsigned int fault_mappable:1;
927 unsigned int pin_mappable:1;
930 * Is the GPU currently using a fence to access this buffer,
932 unsigned int pending_fenced_gpu_access:1;
933 unsigned int fenced_gpu_access:1;
935 unsigned int cache_level:2;
937 unsigned int has_aliasing_ppgtt_mapping:1;
938 unsigned int has_global_gtt_mapping:1;
945 struct scatterlist *sg_list;
948 /* prime dma-buf support */
949 struct sg_table *sg_table;
950 void *dma_buf_vmapping;
954 * Used for performing relocations during execbuffer insertion.
956 struct hlist_node exec_node;
957 unsigned long exec_handle;
958 struct drm_i915_gem_exec_object2 *exec_entry;
961 * Current offset of the object in GTT space.
963 * This is the same as gtt_space->start
967 struct intel_ring_buffer *ring;
969 /** Breadcrumb of last rendering to the buffer. */
970 uint32_t last_rendering_seqno;
971 /** Breadcrumb of last fenced GPU access to the buffer. */
972 uint32_t last_fenced_seqno;
974 /** Current tiling stride for the object, if it's tiled. */
977 /** Record of address bit 17 of each page at last unbind. */
978 unsigned long *bit_17;
980 /** User space pin count and filp owning the pin */
981 uint32_t user_pin_count;
982 struct drm_file *pin_filp;
984 /** for phy allocated objects */
985 struct drm_i915_gem_phys_object *phys_obj;
988 * Number of crtcs where this object is currently the fb, but
989 * will be page flipped away on the next vblank. When it
990 * reaches 0, dev_priv->pending_flip_queue will be woken up.
992 atomic_t pending_flip;
995 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
998 * Request queue structure.
1000 * The request queue allows us to note sequence numbers that have been emitted
1001 * and may be associated with active buffers to be retired.
1003 * By keeping this list, we can avoid having to do questionable
1004 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1005 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1007 struct drm_i915_gem_request {
1008 /** On Which ring this request was generated */
1009 struct intel_ring_buffer *ring;
1011 /** GEM sequence number associated with this request. */
1014 /** Postion in the ringbuffer of the end of the request */
1017 /** Time at which this request was emitted, in jiffies. */
1018 unsigned long emitted_jiffies;
1020 /** global list entry for this request */
1021 struct list_head list;
1023 struct drm_i915_file_private *file_priv;
1024 /** file_priv list entry for this request */
1025 struct list_head client_list;
1028 struct drm_i915_file_private {
1030 struct spinlock lock;
1031 struct list_head request_list;
1035 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1037 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1038 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1039 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1040 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1041 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1042 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1043 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1044 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1045 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1046 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1047 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1048 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1049 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1050 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1051 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1052 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1053 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1054 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1055 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1056 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1057 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1058 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1061 * The genX designation typically refers to the render engine, so render
1062 * capability related checks should use IS_GEN, while display and other checks
1063 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1066 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1067 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1068 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1069 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1070 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1071 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1073 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1074 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1075 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1076 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1078 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
1080 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1081 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1083 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1084 * rows, which changed the alignment requirements and fence programming.
1086 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1088 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1089 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1090 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1091 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1092 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1093 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1094 /* dsparb controlled by hw only */
1095 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1097 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1098 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1099 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1101 #define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split)
1102 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1104 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1105 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1106 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1107 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1109 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1111 #include "i915_trace.h"
1114 * RC6 is a special power stage which allows the GPU to enter an very
1115 * low-voltage mode when idle, using down to 0V while at this stage. This
1116 * stage is entered automatically when the GPU is idle when RC6 support is
1117 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1119 * There are different RC6 modes available in Intel GPU, which differentiate
1120 * among each other with the latency required to enter and leave RC6 and
1121 * voltage consumed by the GPU in different states.
1123 * The combination of the following flags define which states GPU is allowed
1124 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1125 * RC6pp is deepest RC6. Their support by hardware varies according to the
1126 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1127 * which brings the most power savings; deeper states save more power, but
1128 * require higher latency to switch to and wake up.
1130 #define INTEL_RC6_ENABLE (1<<0)
1131 #define INTEL_RC6p_ENABLE (1<<1)
1132 #define INTEL_RC6pp_ENABLE (1<<2)
1134 extern struct drm_ioctl_desc i915_ioctls[];
1135 extern int i915_max_ioctl;
1136 extern unsigned int i915_fbpercrtc __always_unused;
1137 extern int i915_panel_ignore_lid __read_mostly;
1138 extern unsigned int i915_powersave __read_mostly;
1139 extern int i915_semaphores __read_mostly;
1140 extern unsigned int i915_lvds_downclock __read_mostly;
1141 extern int i915_lvds_channel_mode __read_mostly;
1142 extern int i915_panel_use_ssc __read_mostly;
1143 extern int i915_vbt_sdvo_panel_type __read_mostly;
1144 extern int i915_enable_rc6 __read_mostly;
1145 extern int i915_enable_fbc __read_mostly;
1146 extern bool i915_enable_hangcheck __read_mostly;
1147 extern int i915_enable_ppgtt __read_mostly;
1149 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1150 extern int i915_resume(struct drm_device *dev);
1151 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1152 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1155 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1156 extern void i915_kernel_lost_context(struct drm_device * dev);
1157 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1158 extern int i915_driver_unload(struct drm_device *);
1159 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1160 extern void i915_driver_lastclose(struct drm_device * dev);
1161 extern void i915_driver_preclose(struct drm_device *dev,
1162 struct drm_file *file_priv);
1163 extern void i915_driver_postclose(struct drm_device *dev,
1164 struct drm_file *file_priv);
1165 extern int i915_driver_device_is_agp(struct drm_device * dev);
1166 #ifdef CONFIG_COMPAT
1167 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1170 extern int i915_emit_box(struct drm_device *dev,
1171 struct drm_clip_rect *box,
1173 extern int i915_reset(struct drm_device *dev);
1174 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1175 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1176 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1177 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1181 void i915_hangcheck_elapsed(unsigned long data);
1182 void i915_handle_error(struct drm_device *dev, bool wedged);
1184 extern void intel_irq_init(struct drm_device *dev);
1186 void i915_error_state_free(struct kref *error_ref);
1189 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1192 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1194 void intel_enable_asle(struct drm_device *dev);
1196 #ifdef CONFIG_DEBUG_FS
1197 extern void i915_destroy_error_state(struct drm_device *dev);
1199 #define i915_destroy_error_state(x)
1204 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1205 struct drm_file *file_priv);
1206 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1207 struct drm_file *file_priv);
1208 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1209 struct drm_file *file_priv);
1210 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1211 struct drm_file *file_priv);
1212 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1213 struct drm_file *file_priv);
1214 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1215 struct drm_file *file_priv);
1216 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1217 struct drm_file *file_priv);
1218 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1219 struct drm_file *file_priv);
1220 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1221 struct drm_file *file_priv);
1222 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1223 struct drm_file *file_priv);
1224 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1225 struct drm_file *file_priv);
1226 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1227 struct drm_file *file_priv);
1228 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1229 struct drm_file *file_priv);
1230 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1231 struct drm_file *file_priv);
1232 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1233 struct drm_file *file_priv);
1234 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1235 struct drm_file *file_priv);
1236 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1237 struct drm_file *file_priv);
1238 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1239 struct drm_file *file_priv);
1240 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1241 struct drm_file *file_priv);
1242 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1243 struct drm_file *file_priv);
1244 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1245 struct drm_file *file_priv);
1246 void i915_gem_load(struct drm_device *dev);
1247 int i915_gem_init_object(struct drm_gem_object *obj);
1248 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1249 uint32_t invalidate_domains,
1250 uint32_t flush_domains);
1251 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1253 void i915_gem_free_object(struct drm_gem_object *obj);
1254 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1256 bool map_and_fenceable);
1257 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1258 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1259 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1260 void i915_gem_lastclose(struct drm_device *dev);
1262 int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1264 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1265 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1266 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1267 struct intel_ring_buffer *to);
1268 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1269 struct intel_ring_buffer *ring,
1272 int i915_gem_dumb_create(struct drm_file *file_priv,
1273 struct drm_device *dev,
1274 struct drm_mode_create_dumb *args);
1275 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1276 uint32_t handle, uint64_t *offset);
1277 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1280 * Returns true if seq1 is later than seq2.
1283 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1285 return (int32_t)(seq1 - seq2) >= 0;
1288 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1290 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1291 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1294 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1296 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1297 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1298 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1305 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1307 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1308 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1309 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1313 void i915_gem_retire_requests(struct drm_device *dev);
1314 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1316 void i915_gem_reset(struct drm_device *dev);
1317 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1318 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1319 uint32_t read_domains,
1320 uint32_t write_domain);
1321 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1322 int __must_check i915_gem_init(struct drm_device *dev);
1323 int __must_check i915_gem_init_hw(struct drm_device *dev);
1324 void i915_gem_l3_remap(struct drm_device *dev);
1325 void i915_gem_init_swizzling(struct drm_device *dev);
1326 void i915_gem_init_ppgtt(struct drm_device *dev);
1327 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1328 int __must_check i915_gpu_idle(struct drm_device *dev);
1329 int __must_check i915_gem_idle(struct drm_device *dev);
1330 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1331 struct drm_file *file,
1332 struct drm_i915_gem_request *request);
1333 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1335 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1337 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1340 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1342 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1344 struct intel_ring_buffer *pipelined);
1345 int i915_gem_attach_phys_object(struct drm_device *dev,
1346 struct drm_i915_gem_object *obj,
1349 void i915_gem_detach_phys_object(struct drm_device *dev,
1350 struct drm_i915_gem_object *obj);
1351 void i915_gem_free_all_phys_object(struct drm_device *dev);
1352 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1355 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1359 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1360 enum i915_cache_level cache_level);
1362 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1363 struct dma_buf *dma_buf);
1365 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1366 struct drm_gem_object *gem_obj, int flags);
1369 /* i915_gem_gtt.c */
1370 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1371 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1372 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1373 struct drm_i915_gem_object *obj,
1374 enum i915_cache_level cache_level);
1375 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1376 struct drm_i915_gem_object *obj);
1378 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1379 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1380 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1381 enum i915_cache_level cache_level);
1382 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1383 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1384 void i915_gem_init_global_gtt(struct drm_device *dev,
1385 unsigned long start,
1386 unsigned long mappable_end,
1389 /* i915_gem_evict.c */
1390 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1391 unsigned alignment, bool mappable);
1392 int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only);
1394 /* i915_gem_stolen.c */
1395 int i915_gem_init_stolen(struct drm_device *dev);
1396 void i915_gem_cleanup_stolen(struct drm_device *dev);
1398 /* i915_gem_tiling.c */
1399 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1400 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1401 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1403 /* i915_gem_debug.c */
1404 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1405 const char *where, uint32_t mark);
1407 int i915_verify_lists(struct drm_device *dev);
1409 #define i915_verify_lists(dev) 0
1411 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1413 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1414 const char *where, uint32_t mark);
1416 /* i915_debugfs.c */
1417 int i915_debugfs_init(struct drm_minor *minor);
1418 void i915_debugfs_cleanup(struct drm_minor *minor);
1420 /* i915_suspend.c */
1421 extern int i915_save_state(struct drm_device *dev);
1422 extern int i915_restore_state(struct drm_device *dev);
1424 /* i915_suspend.c */
1425 extern int i915_save_state(struct drm_device *dev);
1426 extern int i915_restore_state(struct drm_device *dev);
1429 void i915_setup_sysfs(struct drm_device *dev_priv);
1430 void i915_teardown_sysfs(struct drm_device *dev_priv);
1433 extern int intel_setup_gmbus(struct drm_device *dev);
1434 extern void intel_teardown_gmbus(struct drm_device *dev);
1435 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1437 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1440 extern struct i2c_adapter *intel_gmbus_get_adapter(
1441 struct drm_i915_private *dev_priv, unsigned port);
1442 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1443 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1444 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1446 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1448 extern void intel_i2c_reset(struct drm_device *dev);
1450 /* intel_opregion.c */
1451 extern int intel_opregion_setup(struct drm_device *dev);
1453 extern void intel_opregion_init(struct drm_device *dev);
1454 extern void intel_opregion_fini(struct drm_device *dev);
1455 extern void intel_opregion_asle_intr(struct drm_device *dev);
1456 extern void intel_opregion_gse_intr(struct drm_device *dev);
1457 extern void intel_opregion_enable_asle(struct drm_device *dev);
1459 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1460 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1461 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1462 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1463 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1468 extern void intel_register_dsm_handler(void);
1469 extern void intel_unregister_dsm_handler(void);
1471 static inline void intel_register_dsm_handler(void) { return; }
1472 static inline void intel_unregister_dsm_handler(void) { return; }
1473 #endif /* CONFIG_ACPI */
1476 extern void intel_modeset_init_hw(struct drm_device *dev);
1477 extern void intel_modeset_init(struct drm_device *dev);
1478 extern void intel_modeset_gem_init(struct drm_device *dev);
1479 extern void intel_modeset_cleanup(struct drm_device *dev);
1480 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1481 extern bool intel_fbc_enabled(struct drm_device *dev);
1482 extern void intel_disable_fbc(struct drm_device *dev);
1483 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1484 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1485 extern void ironlake_enable_rc6(struct drm_device *dev);
1486 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1487 extern void intel_detect_pch(struct drm_device *dev);
1488 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1489 extern int intel_enable_rc6(const struct drm_device *dev);
1491 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1492 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1493 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1494 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1495 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1497 extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
1498 extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
1501 #ifdef CONFIG_DEBUG_FS
1502 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1503 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1505 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1506 extern void intel_display_print_error_state(struct seq_file *m,
1507 struct drm_device *dev,
1508 struct intel_display_error_state *error);
1511 /* On SNB platform, before reading ring registers forcewake bit
1512 * must be set to prevent GT core from power down and stale values being
1515 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1516 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1517 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1519 #define __i915_read(x, y) \
1520 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1528 #define __i915_write(x, y) \
1529 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1537 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1538 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1540 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1541 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1542 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1543 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1545 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1546 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1547 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1548 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1550 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1551 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1553 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1554 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)