1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
63 #define pipe_name(p) ((p) + 'A')
71 #define transcoder_name(t) ((t) + 'A')
78 #define plane_name(p) ((p) + 'A')
80 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
90 #define port_name(p) ((p) + 'A')
92 #define I915_NUM_PHYS_VLV 1
104 enum intel_display_power_domain {
108 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
109 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
110 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
111 POWER_DOMAIN_TRANSCODER_A,
112 POWER_DOMAIN_TRANSCODER_B,
113 POWER_DOMAIN_TRANSCODER_C,
114 POWER_DOMAIN_TRANSCODER_EDP,
122 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
124 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
125 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
126 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
127 #define POWER_DOMAIN_TRANSCODER(tran) \
128 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
129 (tran) + POWER_DOMAIN_TRANSCODER_A)
131 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
132 BIT(POWER_DOMAIN_PIPE_A) | \
133 BIT(POWER_DOMAIN_TRANSCODER_EDP))
134 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
135 BIT(POWER_DOMAIN_PIPE_A) | \
136 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
137 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
141 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
142 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
152 #define I915_GEM_GPU_DOMAINS \
153 (I915_GEM_DOMAIN_RENDER | \
154 I915_GEM_DOMAIN_SAMPLER | \
155 I915_GEM_DOMAIN_COMMAND | \
156 I915_GEM_DOMAIN_INSTRUCTION | \
157 I915_GEM_DOMAIN_VERTEX)
159 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
161 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
162 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
163 if ((intel_encoder)->base.crtc == (__crtc))
165 struct drm_i915_private;
168 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
169 /* real shared dpll ids must be >= 0 */
173 #define I915_NUM_PLLS 2
175 struct intel_dpll_hw_state {
182 struct intel_shared_dpll {
183 int refcount; /* count of number of CRTCs sharing this PLL */
184 int active; /* count of number of active CRTCs (i.e. DPMS on) */
185 bool on; /* is the PLL actually active? Disabled during modeset */
187 /* should match the index in the dev_priv->shared_dplls array */
188 enum intel_dpll_id id;
189 struct intel_dpll_hw_state hw_state;
190 void (*mode_set)(struct drm_i915_private *dev_priv,
191 struct intel_shared_dpll *pll);
192 void (*enable)(struct drm_i915_private *dev_priv,
193 struct intel_shared_dpll *pll);
194 void (*disable)(struct drm_i915_private *dev_priv,
195 struct intel_shared_dpll *pll);
196 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
197 struct intel_shared_dpll *pll,
198 struct intel_dpll_hw_state *hw_state);
201 /* Used by dp and fdi links */
202 struct intel_link_m_n {
210 void intel_link_compute_m_n(int bpp, int nlanes,
211 int pixel_clock, int link_clock,
212 struct intel_link_m_n *m_n);
214 struct intel_ddi_plls {
220 /* Interface history:
223 * 1.2: Add Power Management
224 * 1.3: Add vblank support
225 * 1.4: Fix cmdbuffer path, add heap destroy
226 * 1.5: Add vblank pipe configuration
227 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
228 * - Support vertical blank on secondary display pipe
230 #define DRIVER_MAJOR 1
231 #define DRIVER_MINOR 6
232 #define DRIVER_PATCHLEVEL 0
234 #define WATCH_LISTS 0
237 #define I915_GEM_PHYS_CURSOR_0 1
238 #define I915_GEM_PHYS_CURSOR_1 2
239 #define I915_GEM_PHYS_OVERLAY_REGS 3
240 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
242 struct drm_i915_gem_phys_object {
244 struct page **page_list;
245 drm_dma_handle_t *handle;
246 struct drm_i915_gem_object *cur_obj;
249 struct opregion_header;
250 struct opregion_acpi;
251 struct opregion_swsci;
252 struct opregion_asle;
254 struct intel_opregion {
255 struct opregion_header __iomem *header;
256 struct opregion_acpi __iomem *acpi;
257 struct opregion_swsci __iomem *swsci;
258 u32 swsci_gbda_sub_functions;
259 u32 swsci_sbcb_sub_functions;
260 struct opregion_asle __iomem *asle;
262 u32 __iomem *lid_state;
263 struct work_struct asle_work;
265 #define OPREGION_SIZE (8*1024)
267 struct intel_overlay;
268 struct intel_overlay_error_state;
270 struct drm_i915_master_private {
271 drm_local_map_t *sarea;
272 struct _drm_i915_sarea *sarea_priv;
274 #define I915_FENCE_REG_NONE -1
275 #define I915_MAX_NUM_FENCES 32
276 /* 32 fences + sign bit for FENCE_REG_NONE */
277 #define I915_MAX_NUM_FENCE_BITS 6
279 struct drm_i915_fence_reg {
280 struct list_head lru_list;
281 struct drm_i915_gem_object *obj;
285 struct sdvo_device_mapping {
294 struct intel_display_error_state;
296 struct drm_i915_error_state {
304 bool waiting[I915_NUM_RINGS];
305 u32 pipestat[I915_MAX_PIPES];
306 u32 tail[I915_NUM_RINGS];
307 u32 head[I915_NUM_RINGS];
308 u32 ctl[I915_NUM_RINGS];
309 u32 ipeir[I915_NUM_RINGS];
310 u32 ipehr[I915_NUM_RINGS];
311 u32 instdone[I915_NUM_RINGS];
312 u32 acthd[I915_NUM_RINGS];
313 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
314 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
315 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
316 /* our own tracking of ring head and tail */
317 u32 cpu_ring_head[I915_NUM_RINGS];
318 u32 cpu_ring_tail[I915_NUM_RINGS];
319 u32 error; /* gen6+ */
320 u32 err_int; /* gen7 */
321 u32 bbstate[I915_NUM_RINGS];
322 u32 instpm[I915_NUM_RINGS];
323 u32 instps[I915_NUM_RINGS];
324 u32 extra_instdone[I915_NUM_INSTDONE_REG];
325 u32 seqno[I915_NUM_RINGS];
327 u32 fault_reg[I915_NUM_RINGS];
329 u32 faddr[I915_NUM_RINGS];
330 u64 fence[I915_MAX_NUM_FENCES];
332 struct drm_i915_error_ring {
333 struct drm_i915_error_object {
337 } *ringbuffer, *batchbuffer, *ctx;
338 struct drm_i915_error_request {
344 } ring[I915_NUM_RINGS];
345 struct drm_i915_error_buffer {
352 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
359 } **active_bo, **pinned_bo;
360 u32 *active_bo_count, *pinned_bo_count;
361 struct intel_overlay_error_state *overlay;
362 struct intel_display_error_state *display;
363 int hangcheck_score[I915_NUM_RINGS];
364 enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS];
367 struct intel_connector;
368 struct intel_crtc_config;
373 struct drm_i915_display_funcs {
374 bool (*fbc_enabled)(struct drm_device *dev);
375 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
376 void (*disable_fbc)(struct drm_device *dev);
377 int (*get_display_clock_speed)(struct drm_device *dev);
378 int (*get_fifo_size)(struct drm_device *dev, int plane);
380 * find_dpll() - Find the best values for the PLL
381 * @limit: limits for the PLL
382 * @crtc: current CRTC
383 * @target: target frequency in kHz
384 * @refclk: reference clock frequency in kHz
385 * @match_clock: if provided, @best_clock P divider must
386 * match the P divider from @match_clock
387 * used for LVDS downclocking
388 * @best_clock: best PLL values found
390 * Returns true on success, false on failure.
392 bool (*find_dpll)(const struct intel_limit *limit,
393 struct drm_crtc *crtc,
394 int target, int refclk,
395 struct dpll *match_clock,
396 struct dpll *best_clock);
397 void (*update_wm)(struct drm_crtc *crtc);
398 void (*update_sprite_wm)(struct drm_plane *plane,
399 struct drm_crtc *crtc,
400 uint32_t sprite_width, int pixel_size,
401 bool enable, bool scaled);
402 void (*modeset_global_resources)(struct drm_device *dev);
403 /* Returns the active state of the crtc, and if the crtc is active,
404 * fills out the pipe-config with the hw state. */
405 bool (*get_pipe_config)(struct intel_crtc *,
406 struct intel_crtc_config *);
407 int (*crtc_mode_set)(struct drm_crtc *crtc,
409 struct drm_framebuffer *old_fb);
410 void (*crtc_enable)(struct drm_crtc *crtc);
411 void (*crtc_disable)(struct drm_crtc *crtc);
412 void (*off)(struct drm_crtc *crtc);
413 void (*write_eld)(struct drm_connector *connector,
414 struct drm_crtc *crtc,
415 struct drm_display_mode *mode);
416 void (*fdi_link_train)(struct drm_crtc *crtc);
417 void (*init_clock_gating)(struct drm_device *dev);
418 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
419 struct drm_framebuffer *fb,
420 struct drm_i915_gem_object *obj,
422 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
424 void (*hpd_irq_setup)(struct drm_device *dev);
425 /* clock updates for mode set */
427 /* render clock increase/decrease */
428 /* display clock increase/decrease */
429 /* pll clock increase/decrease */
431 int (*setup_backlight)(struct intel_connector *connector);
432 uint32_t (*get_backlight)(struct intel_connector *connector);
433 void (*set_backlight)(struct intel_connector *connector,
435 void (*disable_backlight)(struct intel_connector *connector);
436 void (*enable_backlight)(struct intel_connector *connector);
439 struct intel_uncore_funcs {
440 void (*force_wake_get)(struct drm_i915_private *dev_priv,
442 void (*force_wake_put)(struct drm_i915_private *dev_priv,
445 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
446 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
447 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
448 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
450 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
451 uint8_t val, bool trace);
452 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
453 uint16_t val, bool trace);
454 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
455 uint32_t val, bool trace);
456 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
457 uint64_t val, bool trace);
460 struct intel_uncore {
461 spinlock_t lock; /** lock is also taken in irq contexts. */
463 struct intel_uncore_funcs funcs;
466 unsigned forcewake_count;
468 unsigned fw_rendercount;
469 unsigned fw_mediacount;
471 struct delayed_work force_wake_work;
474 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
475 func(is_mobile) sep \
478 func(is_i945gm) sep \
480 func(need_gfx_hws) sep \
482 func(is_pineview) sep \
483 func(is_broadwater) sep \
484 func(is_crestline) sep \
485 func(is_ivybridge) sep \
486 func(is_valleyview) sep \
487 func(is_haswell) sep \
488 func(is_preliminary) sep \
490 func(has_pipe_cxsr) sep \
491 func(has_hotplug) sep \
492 func(cursor_needs_physical) sep \
493 func(has_overlay) sep \
494 func(overlay_needs_physical) sep \
495 func(supports_tv) sep \
500 #define DEFINE_FLAG(name) u8 name:1
501 #define SEP_SEMICOLON ;
503 struct intel_device_info {
504 u32 display_mmio_offset;
507 u8 ring_mask; /* Rings supported by the HW */
508 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
514 enum i915_cache_level {
516 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
517 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
518 caches, eg sampler/render caches, and the
519 large Last-Level-Cache. LLC is coherent with
520 the CPU, but L3 is only visible to the GPU. */
521 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
524 typedef uint32_t gen6_gtt_pte_t;
526 struct i915_address_space {
528 struct drm_device *dev;
529 struct list_head global_link;
530 unsigned long start; /* Start offset always 0 for dri2 */
531 size_t total; /* size addr space maps (ex. 2GB for ggtt) */
539 * List of objects currently involved in rendering.
541 * Includes buffers having the contents of their GPU caches
542 * flushed, not necessarily primitives. last_rendering_seqno
543 * represents when the rendering involved will be completed.
545 * A reference is held on the buffer while on this list.
547 struct list_head active_list;
550 * LRU list of objects which are not in the ringbuffer and
551 * are ready to unbind, but are still in the GTT.
553 * last_rendering_seqno is 0 while an object is in this list.
555 * A reference is not held on the buffer while on this list,
556 * as merely being GTT-bound shouldn't prevent its being
557 * freed, and we'll pull it off the list in the free path.
559 struct list_head inactive_list;
561 /* FIXME: Need a more generic return type */
562 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
563 enum i915_cache_level level,
564 bool valid); /* Create a valid PTE */
565 void (*clear_range)(struct i915_address_space *vm,
566 unsigned int first_entry,
567 unsigned int num_entries,
569 void (*insert_entries)(struct i915_address_space *vm,
571 unsigned int first_entry,
572 enum i915_cache_level cache_level);
573 void (*cleanup)(struct i915_address_space *vm);
576 /* The Graphics Translation Table is the way in which GEN hardware translates a
577 * Graphics Virtual Address into a Physical Address. In addition to the normal
578 * collateral associated with any va->pa translations GEN hardware also has a
579 * portion of the GTT which can be mapped by the CPU and remain both coherent
580 * and correct (in cases like swizzling). That region is referred to as GMADR in
584 struct i915_address_space base;
585 size_t stolen_size; /* Total size of stolen memory */
587 unsigned long mappable_end; /* End offset that we can CPU map */
588 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
589 phys_addr_t mappable_base; /* PA of our GMADR */
591 /** "Graphics Stolen Memory" holds the global PTEs */
599 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
600 size_t *stolen, phys_addr_t *mappable_base,
601 unsigned long *mappable_end);
603 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
605 struct i915_hw_ppgtt {
606 struct i915_address_space base;
607 unsigned num_pd_entries;
609 struct page **pt_pages;
610 struct page *gen8_pt_pages;
612 struct page *pd_pages;
617 dma_addr_t pd_dma_addr[4];
620 dma_addr_t *pt_dma_addr;
621 dma_addr_t *gen8_pt_dma_addr[4];
623 int (*enable)(struct drm_device *dev);
627 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
628 * VMA's presence cannot be guaranteed before binding, or after unbinding the
629 * object into/from the address space.
631 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
632 * will always be <= an objects lifetime. So object refcounting should cover us.
635 struct drm_mm_node node;
636 struct drm_i915_gem_object *obj;
637 struct i915_address_space *vm;
639 /** This object's place on the active/inactive lists */
640 struct list_head mm_list;
642 struct list_head vma_link; /* Link in the object's VMA list */
644 /** This vma's place in the batchbuffer or on the eviction list */
645 struct list_head exec_list;
648 * Used for performing relocations during execbuffer insertion.
650 struct hlist_node exec_node;
651 unsigned long exec_handle;
652 struct drm_i915_gem_exec_object2 *exec_entry;
656 struct i915_ctx_hang_stats {
657 /* This context had batch pending when hang was declared */
658 unsigned batch_pending;
660 /* This context had batch active when hang was declared */
661 unsigned batch_active;
663 /* Time when this context was last blamed for a GPU reset */
664 unsigned long guilty_ts;
666 /* This context is banned to submit more work */
670 /* This must match up with the value previously used for execbuf2.rsvd1. */
671 #define DEFAULT_CONTEXT_ID 0
672 struct i915_hw_context {
677 struct drm_i915_file_private *file_priv;
678 struct intel_ring_buffer *ring;
679 struct drm_i915_gem_object *obj;
680 struct i915_ctx_hang_stats hang_stats;
682 struct list_head link;
691 struct drm_mm_node *compressed_fb;
692 struct drm_mm_node *compressed_llb;
694 struct intel_fbc_work {
695 struct delayed_work work;
696 struct drm_crtc *crtc;
697 struct drm_framebuffer *fb;
702 FBC_OK, /* FBC is enabled */
703 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
704 FBC_NO_OUTPUT, /* no outputs enabled to compress */
705 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
706 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
707 FBC_MODE_TOO_LARGE, /* mode too large for compression */
708 FBC_BAD_PLANE, /* fbc not supported on plane */
709 FBC_NOT_TILED, /* buffer not tiled */
710 FBC_MULTIPLE_PIPES, /* more than one pipe active */
712 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
722 PCH_NONE = 0, /* No PCH present */
723 PCH_IBX, /* Ibexpeak PCH */
724 PCH_CPT, /* Cougarpoint PCH */
725 PCH_LPT, /* Lynxpoint PCH */
729 enum intel_sbi_destination {
734 #define QUIRK_PIPEA_FORCE (1<<0)
735 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
736 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
739 struct intel_fbc_work;
742 struct i2c_adapter adapter;
746 struct i2c_algo_bit_data bit_algo;
747 struct drm_i915_private *dev_priv;
750 struct i915_suspend_saved_registers {
771 u32 saveTRANS_HTOTAL_A;
772 u32 saveTRANS_HBLANK_A;
773 u32 saveTRANS_HSYNC_A;
774 u32 saveTRANS_VTOTAL_A;
775 u32 saveTRANS_VBLANK_A;
776 u32 saveTRANS_VSYNC_A;
784 u32 savePFIT_PGM_RATIOS;
785 u32 saveBLC_HIST_CTL;
787 u32 saveBLC_PWM_CTL2;
788 u32 saveBLC_HIST_CTL_B;
789 u32 saveBLC_CPU_PWM_CTL;
790 u32 saveBLC_CPU_PWM_CTL2;
803 u32 saveTRANS_HTOTAL_B;
804 u32 saveTRANS_HBLANK_B;
805 u32 saveTRANS_HSYNC_B;
806 u32 saveTRANS_VTOTAL_B;
807 u32 saveTRANS_VBLANK_B;
808 u32 saveTRANS_VSYNC_B;
822 u32 savePP_ON_DELAYS;
823 u32 savePP_OFF_DELAYS;
831 u32 savePFIT_CONTROL;
832 u32 save_palette_a[256];
833 u32 save_palette_b[256];
834 u32 saveDPFC_CB_BASE;
835 u32 saveFBC_CFB_BASE;
838 u32 saveFBC_CONTROL2;
848 u32 saveCACHE_MODE_0;
849 u32 saveMI_ARB_STATE;
860 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
871 u32 savePIPEA_GMCH_DATA_M;
872 u32 savePIPEB_GMCH_DATA_M;
873 u32 savePIPEA_GMCH_DATA_N;
874 u32 savePIPEB_GMCH_DATA_N;
875 u32 savePIPEA_DP_LINK_M;
876 u32 savePIPEB_DP_LINK_M;
877 u32 savePIPEA_DP_LINK_N;
878 u32 savePIPEB_DP_LINK_N;
889 u32 savePCH_DREF_CONTROL;
890 u32 saveDISP_ARB_CTL;
891 u32 savePIPEA_DATA_M1;
892 u32 savePIPEA_DATA_N1;
893 u32 savePIPEA_LINK_M1;
894 u32 savePIPEA_LINK_N1;
895 u32 savePIPEB_DATA_M1;
896 u32 savePIPEB_DATA_N1;
897 u32 savePIPEB_LINK_M1;
898 u32 savePIPEB_LINK_N1;
899 u32 saveMCHBAR_RENDER_STANDBY;
900 u32 savePCH_PORT_HOTPLUG;
903 struct intel_gen6_power_mgmt {
904 /* work and pm_iir are protected by dev_priv->irq_lock */
905 struct work_struct work;
908 /* The below variables an all the rps hw state are protected by
909 * dev->struct mutext. */
919 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
922 struct delayed_work delayed_resume_work;
925 * Protects RPS/RC6 register access and PCU communication.
926 * Must be taken after struct_mutex if nested.
928 struct mutex hw_lock;
931 /* defined intel_pm.c */
932 extern spinlock_t mchdev_lock;
934 struct intel_ilk_power_mgmt {
942 unsigned long last_time1;
943 unsigned long chipset_power;
945 struct timespec last_time2;
946 unsigned long gfx_power;
952 struct drm_i915_gem_object *pwrctx;
953 struct drm_i915_gem_object *renderctx;
956 /* Power well structure for haswell */
957 struct i915_power_well {
960 /* power well enable/disable usage count */
962 unsigned long domains;
964 void (*set)(struct drm_device *dev, struct i915_power_well *power_well,
966 bool (*is_enabled)(struct drm_device *dev,
967 struct i915_power_well *power_well);
970 struct i915_power_domains {
972 * Power wells needed for initialization at driver init and suspend
973 * time are on. They are kept on until after the first modeset.
976 int power_well_count;
979 int domain_use_count[POWER_DOMAIN_NUM];
980 struct i915_power_well *power_wells;
983 struct i915_dri1_state {
984 unsigned allow_batchbuffer : 1;
985 u32 __iomem *gfx_hws_cpu_addr;
996 struct i915_ums_state {
998 * Flag if the X Server, and thus DRM, is not currently in
999 * control of the device.
1001 * This is set between LeaveVT and EnterVT. It needs to be
1002 * replaced with a semaphore. It also needs to be
1003 * transitioned away from for kernel modesetting.
1008 #define MAX_L3_SLICES 2
1009 struct intel_l3_parity {
1010 u32 *remap_info[MAX_L3_SLICES];
1011 struct work_struct error_work;
1015 struct i915_gem_mm {
1016 /** Memory allocator for GTT stolen memory */
1017 struct drm_mm stolen;
1018 /** List of all objects in gtt_space. Used to restore gtt
1019 * mappings on resume */
1020 struct list_head bound_list;
1022 * List of objects which are not bound to the GTT (thus
1023 * are idle and not used by the GPU) but still have
1024 * (presumably uncached) pages still attached.
1026 struct list_head unbound_list;
1028 /** Usable portion of the GTT for GEM */
1029 unsigned long stolen_base; /* limited to low memory (32-bit) */
1031 /** PPGTT used for aliasing the PPGTT with the GTT */
1032 struct i915_hw_ppgtt *aliasing_ppgtt;
1034 struct shrinker inactive_shrinker;
1035 bool shrinker_no_lock_stealing;
1037 /** LRU list of objects with fence regs on them. */
1038 struct list_head fence_list;
1041 * We leave the user IRQ off as much as possible,
1042 * but this means that requests will finish and never
1043 * be retired once the system goes idle. Set a timer to
1044 * fire periodically while the ring is running. When it
1045 * fires, go retire requests.
1047 struct delayed_work retire_work;
1050 * When we detect an idle GPU, we want to turn on
1051 * powersaving features. So once we see that there
1052 * are no more requests outstanding and no more
1053 * arrive within a small period of time, we fire
1054 * off the idle_work.
1056 struct delayed_work idle_work;
1059 * Are we in a non-interruptible section of code like
1064 /** Bit 6 swizzling required for X tiling */
1065 uint32_t bit_6_swizzle_x;
1066 /** Bit 6 swizzling required for Y tiling */
1067 uint32_t bit_6_swizzle_y;
1069 /* storage for physical objects */
1070 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1072 /* accounting, useful for userland debugging */
1073 spinlock_t object_stat_lock;
1074 size_t object_memory;
1078 struct drm_i915_error_state_buf {
1087 struct i915_error_state_file_priv {
1088 struct drm_device *dev;
1089 struct drm_i915_error_state *error;
1092 struct i915_gpu_error {
1093 /* For hangcheck timer */
1094 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1095 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1096 /* Hang gpu twice in this window and your context gets banned */
1097 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1099 struct timer_list hangcheck_timer;
1101 /* For reset and error_state handling. */
1103 /* Protected by the above dev->gpu_error.lock. */
1104 struct drm_i915_error_state *first_error;
1105 struct work_struct work;
1108 unsigned long missed_irq_rings;
1111 * State variable controlling the reset flow and count
1113 * This is a counter which gets incremented when reset is triggered,
1114 * and again when reset has been handled. So odd values (lowest bit set)
1115 * means that reset is in progress and even values that
1116 * (reset_counter >> 1):th reset was successfully completed.
1118 * If reset is not completed succesfully, the I915_WEDGE bit is
1119 * set meaning that hardware is terminally sour and there is no
1120 * recovery. All waiters on the reset_queue will be woken when
1123 * This counter is used by the wait_seqno code to notice that reset
1124 * event happened and it needs to restart the entire ioctl (since most
1125 * likely the seqno it waited for won't ever signal anytime soon).
1127 * This is important for lock-free wait paths, where no contended lock
1128 * naturally enforces the correct ordering between the bail-out of the
1129 * waiter and the gpu reset work code.
1131 atomic_t reset_counter;
1133 #define I915_RESET_IN_PROGRESS_FLAG 1
1134 #define I915_WEDGED (1 << 31)
1137 * Waitqueue to signal when the reset has completed. Used by clients
1138 * that wait for dev_priv->mm.wedged to settle.
1140 wait_queue_head_t reset_queue;
1142 /* For gpu hang simulation. */
1143 unsigned int stop_rings;
1145 /* For missed irq/seqno simulation. */
1146 unsigned int test_irq_rings;
1149 enum modeset_restore {
1150 MODESET_ON_LID_OPEN,
1155 struct ddi_vbt_port_info {
1156 uint8_t hdmi_level_shift;
1158 uint8_t supports_dvi:1;
1159 uint8_t supports_hdmi:1;
1160 uint8_t supports_dp:1;
1163 struct intel_vbt_data {
1164 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1165 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1168 unsigned int int_tv_support:1;
1169 unsigned int lvds_dither:1;
1170 unsigned int lvds_vbt:1;
1171 unsigned int int_crt_support:1;
1172 unsigned int lvds_use_ssc:1;
1173 unsigned int display_clock_mode:1;
1174 unsigned int fdi_rx_polarity_inverted:1;
1176 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1181 int edp_preemphasis;
1183 bool edp_initialized;
1186 struct edp_power_seq edp_pps;
1196 union child_device_config *child_dev;
1198 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1201 enum intel_ddb_partitioning {
1203 INTEL_DDB_PART_5_6, /* IVB+ */
1206 struct intel_wm_level {
1214 struct hsw_wm_values {
1215 uint32_t wm_pipe[3];
1217 uint32_t wm_lp_spr[3];
1218 uint32_t wm_linetime[3];
1220 enum intel_ddb_partitioning partitioning;
1224 * This struct tracks the state needed for the Package C8+ feature.
1226 * Package states C8 and deeper are really deep PC states that can only be
1227 * reached when all the devices on the system allow it, so even if the graphics
1228 * device allows PC8+, it doesn't mean the system will actually get to these
1231 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1232 * is disabled and the GPU is idle. When these conditions are met, we manually
1233 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1236 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1237 * the state of some registers, so when we come back from PC8+ we need to
1238 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1239 * need to take care of the registers kept by RC6.
1241 * The interrupt disabling is part of the requirements. We can only leave the
1242 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1243 * can lock the machine.
1245 * Ideally every piece of our code that needs PC8+ disabled would call
1246 * hsw_disable_package_c8, which would increment disable_count and prevent the
1247 * system from reaching PC8+. But we don't have a symmetric way to do this for
1248 * everything, so we have the requirements_met and gpu_idle variables. When we
1249 * switch requirements_met or gpu_idle to true we decrease disable_count, and
1250 * increase it in the opposite case. The requirements_met variable is true when
1251 * all the CRTCs, encoders and the power well are disabled. The gpu_idle
1252 * variable is true when the GPU is idle.
1254 * In addition to everything, we only actually enable PC8+ if disable_count
1255 * stays at zero for at least some seconds. This is implemented with the
1256 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1257 * consecutive times when all screens are disabled and some background app
1258 * queries the state of our connectors, or we have some application constantly
1259 * waking up to use the GPU. Only after the enable_work function actually
1260 * enables PC8+ the "enable" variable will become true, which means that it can
1261 * be false even if disable_count is 0.
1263 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1264 * goes back to false exactly before we reenable the IRQs. We use this variable
1265 * to check if someone is trying to enable/disable IRQs while they're supposed
1266 * to be disabled. This shouldn't happen and we'll print some error messages in
1267 * case it happens, but if it actually happens we'll also update the variables
1268 * inside struct regsave so when we restore the IRQs they will contain the
1269 * latest expected values.
1271 * For more, read "Display Sequences for Package C8" on our documentation.
1273 struct i915_package_c8 {
1274 bool requirements_met;
1277 /* Only true after the delayed work task actually enables it. */
1281 struct delayed_work enable_work;
1288 uint32_t gen6_pmimr;
1292 enum intel_pipe_crc_source {
1293 INTEL_PIPE_CRC_SOURCE_NONE,
1294 INTEL_PIPE_CRC_SOURCE_PLANE1,
1295 INTEL_PIPE_CRC_SOURCE_PLANE2,
1296 INTEL_PIPE_CRC_SOURCE_PF,
1297 INTEL_PIPE_CRC_SOURCE_PIPE,
1298 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1299 INTEL_PIPE_CRC_SOURCE_TV,
1300 INTEL_PIPE_CRC_SOURCE_DP_B,
1301 INTEL_PIPE_CRC_SOURCE_DP_C,
1302 INTEL_PIPE_CRC_SOURCE_DP_D,
1303 INTEL_PIPE_CRC_SOURCE_AUTO,
1304 INTEL_PIPE_CRC_SOURCE_MAX,
1307 struct intel_pipe_crc_entry {
1312 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1313 struct intel_pipe_crc {
1315 bool opened; /* exclusive access to the result file */
1316 struct intel_pipe_crc_entry *entries;
1317 enum intel_pipe_crc_source source;
1319 wait_queue_head_t wq;
1322 typedef struct drm_i915_private {
1323 struct drm_device *dev;
1324 struct kmem_cache *slab;
1326 const struct intel_device_info *info;
1328 int relative_constants_mode;
1332 struct intel_uncore uncore;
1334 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1337 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1338 * controller on different i2c buses. */
1339 struct mutex gmbus_mutex;
1342 * Base address of the gmbus and gpio block.
1344 uint32_t gpio_mmio_base;
1346 wait_queue_head_t gmbus_wait_queue;
1348 struct pci_dev *bridge_dev;
1349 struct intel_ring_buffer ring[I915_NUM_RINGS];
1350 uint32_t last_seqno, next_seqno;
1352 drm_dma_handle_t *status_page_dmah;
1353 struct resource mch_res;
1355 atomic_t irq_received;
1357 /* protects the irq masks */
1358 spinlock_t irq_lock;
1360 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1361 struct pm_qos_request pm_qos;
1363 /* DPIO indirect register protection */
1364 struct mutex dpio_lock;
1366 /** Cached value of IMR to avoid reads in updating the bitfield */
1369 u32 de_irq_mask[I915_MAX_PIPES];
1374 struct work_struct hotplug_work;
1375 bool enable_hotplug_processing;
1377 unsigned long hpd_last_jiffies;
1382 HPD_MARK_DISABLED = 2
1384 } hpd_stats[HPD_NUM_PINS];
1386 struct timer_list hotplug_reenable_timer;
1390 struct i915_fbc fbc;
1391 struct intel_opregion opregion;
1392 struct intel_vbt_data vbt;
1395 struct intel_overlay *overlay;
1396 unsigned int sprite_scaling_enabled;
1398 /* backlight registers and fields in struct intel_panel */
1399 spinlock_t backlight_lock;
1402 bool no_aux_handshake;
1404 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1405 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1406 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1408 unsigned int fsb_freq, mem_freq, is_ddr3;
1411 * wq - Driver workqueue for GEM.
1413 * NOTE: Work items scheduled here are not allowed to grab any modeset
1414 * locks, for otherwise the flushing done in the pageflip code will
1415 * result in deadlocks.
1417 struct workqueue_struct *wq;
1419 /* Display functions */
1420 struct drm_i915_display_funcs display;
1422 /* PCH chipset type */
1423 enum intel_pch pch_type;
1424 unsigned short pch_id;
1426 unsigned long quirks;
1428 enum modeset_restore modeset_restore;
1429 struct mutex modeset_restore_lock;
1431 struct list_head vm_list; /* Global list of all address spaces */
1432 struct i915_gtt gtt; /* VMA representing the global address space */
1434 struct i915_gem_mm mm;
1436 /* Kernel Modesetting */
1438 struct sdvo_device_mapping sdvo_mappings[2];
1440 struct drm_crtc *plane_to_crtc_mapping[3];
1441 struct drm_crtc *pipe_to_crtc_mapping[3];
1442 wait_queue_head_t pending_flip_queue;
1444 #ifdef CONFIG_DEBUG_FS
1445 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1448 int num_shared_dpll;
1449 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1450 struct intel_ddi_plls ddi_plls;
1451 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1453 /* Reclocking support */
1454 bool render_reclock_avail;
1455 bool lvds_downclock_avail;
1456 /* indicates the reduced downclock for LVDS*/
1460 bool mchbar_need_disable;
1462 struct intel_l3_parity l3_parity;
1464 /* Cannot be determined by PCIID. You must always read a register. */
1467 /* gen6+ rps state */
1468 struct intel_gen6_power_mgmt rps;
1470 /* ilk-only ips/rps state. Everything in here is protected by the global
1471 * mchdev_lock in intel_pm.c */
1472 struct intel_ilk_power_mgmt ips;
1474 struct i915_power_domains power_domains;
1476 struct i915_psr psr;
1478 struct i915_gpu_error gpu_error;
1480 struct drm_i915_gem_object *vlv_pctx;
1482 #ifdef CONFIG_DRM_I915_FBDEV
1483 /* list of fbdev register on this device */
1484 struct intel_fbdev *fbdev;
1488 * The console may be contended at resume, but we don't
1489 * want it to block on it.
1491 struct work_struct console_resume_work;
1493 struct drm_property *broadcast_rgb_property;
1494 struct drm_property *force_audio_property;
1496 uint32_t hw_context_size;
1497 struct list_head context_list;
1501 struct i915_suspend_saved_registers regfile;
1505 * Raw watermark latency values:
1506 * in 0.1us units for WM0,
1507 * in 0.5us units for WM1+.
1510 uint16_t pri_latency[5];
1512 uint16_t spr_latency[5];
1514 uint16_t cur_latency[5];
1516 /* current hardware state */
1517 struct hsw_wm_values hw;
1520 struct i915_package_c8 pc8;
1522 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1524 struct i915_dri1_state dri1;
1525 /* Old ums support infrastructure, same warning applies. */
1526 struct i915_ums_state ums;
1527 } drm_i915_private_t;
1529 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1531 return dev->dev_private;
1534 /* Iterate over initialised rings */
1535 #define for_each_ring(ring__, dev_priv__, i__) \
1536 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1537 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1539 enum hdmi_force_audio {
1540 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1541 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1542 HDMI_AUDIO_AUTO, /* trust EDID */
1543 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1546 #define I915_GTT_OFFSET_NONE ((u32)-1)
1548 struct drm_i915_gem_object_ops {
1549 /* Interface between the GEM object and its backing storage.
1550 * get_pages() is called once prior to the use of the associated set
1551 * of pages before to binding them into the GTT, and put_pages() is
1552 * called after we no longer need them. As we expect there to be
1553 * associated cost with migrating pages between the backing storage
1554 * and making them available for the GPU (e.g. clflush), we may hold
1555 * onto the pages after they are no longer referenced by the GPU
1556 * in case they may be used again shortly (for example migrating the
1557 * pages to a different memory domain within the GTT). put_pages()
1558 * will therefore most likely be called when the object itself is
1559 * being released or under memory pressure (where we attempt to
1560 * reap pages for the shrinker).
1562 int (*get_pages)(struct drm_i915_gem_object *);
1563 void (*put_pages)(struct drm_i915_gem_object *);
1566 struct drm_i915_gem_object {
1567 struct drm_gem_object base;
1569 const struct drm_i915_gem_object_ops *ops;
1571 /** List of VMAs backed by this object */
1572 struct list_head vma_list;
1574 /** Stolen memory for this object, instead of being backed by shmem. */
1575 struct drm_mm_node *stolen;
1576 struct list_head global_list;
1578 struct list_head ring_list;
1579 /** Used in execbuf to temporarily hold a ref */
1580 struct list_head obj_exec_link;
1583 * This is set if the object is on the active lists (has pending
1584 * rendering and so a non-zero seqno), and is not set if it i s on
1585 * inactive (ready to be unbound) list.
1587 unsigned int active:1;
1590 * This is set if the object has been written to since last bound
1593 unsigned int dirty:1;
1596 * Fence register bits (if any) for this object. Will be set
1597 * as needed when mapped into the GTT.
1598 * Protected by dev->struct_mutex.
1600 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1603 * Advice: are the backing pages purgeable?
1605 unsigned int madv:2;
1608 * Current tiling mode for the object.
1610 unsigned int tiling_mode:2;
1612 * Whether the tiling parameters for the currently associated fence
1613 * register have changed. Note that for the purposes of tracking
1614 * tiling changes we also treat the unfenced register, the register
1615 * slot that the object occupies whilst it executes a fenced
1616 * command (such as BLT on gen2/3), as a "fence".
1618 unsigned int fence_dirty:1;
1620 /** How many users have pinned this object in GTT space. The following
1621 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1622 * (via user_pin_count), execbuffer (objects are not allowed multiple
1623 * times for the same batchbuffer), and the framebuffer code. When
1624 * switching/pageflipping, the framebuffer code has at most two buffers
1627 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1628 * bits with absolutely no headroom. So use 4 bits. */
1629 unsigned int pin_count:4;
1630 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1633 * Is the object at the current location in the gtt mappable and
1634 * fenceable? Used to avoid costly recalculations.
1636 unsigned int map_and_fenceable:1;
1639 * Whether the current gtt mapping needs to be mappable (and isn't just
1640 * mappable by accident). Track pin and fault separate for a more
1641 * accurate mappable working set.
1643 unsigned int fault_mappable:1;
1644 unsigned int pin_mappable:1;
1645 unsigned int pin_display:1;
1648 * Is the GPU currently using a fence to access this buffer,
1650 unsigned int pending_fenced_gpu_access:1;
1651 unsigned int fenced_gpu_access:1;
1653 unsigned int cache_level:3;
1655 unsigned int has_aliasing_ppgtt_mapping:1;
1656 unsigned int has_global_gtt_mapping:1;
1657 unsigned int has_dma_mapping:1;
1659 struct sg_table *pages;
1660 int pages_pin_count;
1662 /* prime dma-buf support */
1663 void *dma_buf_vmapping;
1666 struct intel_ring_buffer *ring;
1668 /** Breadcrumb of last rendering to the buffer. */
1669 uint32_t last_read_seqno;
1670 uint32_t last_write_seqno;
1671 /** Breadcrumb of last fenced GPU access to the buffer. */
1672 uint32_t last_fenced_seqno;
1674 /** Current tiling stride for the object, if it's tiled. */
1677 /** References from framebuffers, locks out tiling changes. */
1678 unsigned long framebuffer_references;
1680 /** Record of address bit 17 of each page at last unbind. */
1681 unsigned long *bit_17;
1683 /** User space pin count and filp owning the pin */
1684 unsigned long user_pin_count;
1685 struct drm_file *pin_filp;
1687 /** for phy allocated objects */
1688 struct drm_i915_gem_phys_object *phys_obj;
1690 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1692 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1695 * Request queue structure.
1697 * The request queue allows us to note sequence numbers that have been emitted
1698 * and may be associated with active buffers to be retired.
1700 * By keeping this list, we can avoid having to do questionable
1701 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1702 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1704 struct drm_i915_gem_request {
1705 /** On Which ring this request was generated */
1706 struct intel_ring_buffer *ring;
1708 /** GEM sequence number associated with this request. */
1711 /** Position in the ringbuffer of the start of the request */
1714 /** Position in the ringbuffer of the end of the request */
1717 /** Context related to this request */
1718 struct i915_hw_context *ctx;
1720 /** Batch buffer related to this request if any */
1721 struct drm_i915_gem_object *batch_obj;
1723 /** Time at which this request was emitted, in jiffies. */
1724 unsigned long emitted_jiffies;
1726 /** global list entry for this request */
1727 struct list_head list;
1729 struct drm_i915_file_private *file_priv;
1730 /** file_priv list entry for this request */
1731 struct list_head client_list;
1734 struct drm_i915_file_private {
1735 struct drm_i915_private *dev_priv;
1739 struct list_head request_list;
1740 struct delayed_work idle_work;
1742 struct idr context_idr;
1744 struct i915_ctx_hang_stats hang_stats;
1745 atomic_t rps_wait_boost;
1748 #define INTEL_INFO(dev) (to_i915(dev)->info)
1750 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1751 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1752 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1753 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1754 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1755 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1756 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1757 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1758 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1759 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1760 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1761 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1762 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1763 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1764 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1765 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1766 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1767 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1768 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1769 (dev)->pdev->device == 0x0152 || \
1770 (dev)->pdev->device == 0x015a)
1771 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1772 (dev)->pdev->device == 0x0106 || \
1773 (dev)->pdev->device == 0x010A)
1774 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1775 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1776 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
1777 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1778 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1779 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1780 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1781 (((dev)->pdev->device & 0xf) == 0x2 || \
1782 ((dev)->pdev->device & 0xf) == 0x6 || \
1783 ((dev)->pdev->device & 0xf) == 0xe))
1784 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1785 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1786 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1787 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1788 ((dev)->pdev->device & 0x00F0) == 0x0020)
1789 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1792 * The genX designation typically refers to the render engine, so render
1793 * capability related checks should use IS_GEN, while display and other checks
1794 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1797 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1798 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1799 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1800 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1801 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1802 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1803 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1805 #define RENDER_RING (1<<RCS)
1806 #define BSD_RING (1<<VCS)
1807 #define BLT_RING (1<<BCS)
1808 #define VEBOX_RING (1<<VECS)
1809 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1810 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1811 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1812 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1813 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1814 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1816 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1817 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1819 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1820 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1822 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1823 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1825 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1826 * rows, which changed the alignment requirements and fence programming.
1828 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1830 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1831 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1832 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1833 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1834 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1836 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1837 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1838 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1840 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
1842 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1843 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1844 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1845 #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
1847 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1848 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1849 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1850 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1851 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1852 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1854 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1855 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1856 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1857 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1858 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1859 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1861 /* DPF == dynamic parity feature */
1862 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1863 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1865 #define GT_FREQUENCY_MULTIPLIER 50
1867 #include "i915_trace.h"
1869 extern const struct drm_ioctl_desc i915_ioctls[];
1870 extern int i915_max_ioctl;
1871 extern unsigned int i915_fbpercrtc __always_unused;
1872 extern int i915_panel_ignore_lid __read_mostly;
1873 extern unsigned int i915_powersave __read_mostly;
1874 extern int i915_semaphores __read_mostly;
1875 extern unsigned int i915_lvds_downclock __read_mostly;
1876 extern int i915_lvds_channel_mode __read_mostly;
1877 extern int i915_panel_use_ssc __read_mostly;
1878 extern int i915_vbt_sdvo_panel_type __read_mostly;
1879 extern int i915_enable_rc6 __read_mostly;
1880 extern int i915_enable_fbc __read_mostly;
1881 extern bool i915_enable_hangcheck __read_mostly;
1882 extern int i915_enable_ppgtt __read_mostly;
1883 extern int i915_enable_psr __read_mostly;
1884 extern unsigned int i915_preliminary_hw_support __read_mostly;
1885 extern int i915_disable_power_well __read_mostly;
1886 extern int i915_enable_ips __read_mostly;
1887 extern bool i915_fastboot __read_mostly;
1888 extern int i915_enable_pc8 __read_mostly;
1889 extern int i915_pc8_timeout __read_mostly;
1890 extern bool i915_prefault_disable __read_mostly;
1892 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1893 extern int i915_resume(struct drm_device *dev);
1894 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1895 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1898 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1899 extern void i915_kernel_lost_context(struct drm_device * dev);
1900 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1901 extern int i915_driver_unload(struct drm_device *);
1902 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1903 extern void i915_driver_lastclose(struct drm_device * dev);
1904 extern void i915_driver_preclose(struct drm_device *dev,
1905 struct drm_file *file_priv);
1906 extern void i915_driver_postclose(struct drm_device *dev,
1907 struct drm_file *file_priv);
1908 extern int i915_driver_device_is_agp(struct drm_device * dev);
1909 #ifdef CONFIG_COMPAT
1910 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1913 extern int i915_emit_box(struct drm_device *dev,
1914 struct drm_clip_rect *box,
1916 extern int intel_gpu_reset(struct drm_device *dev);
1917 extern int i915_reset(struct drm_device *dev);
1918 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1919 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1920 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1921 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1923 extern void intel_console_resume(struct work_struct *work);
1926 void i915_queue_hangcheck(struct drm_device *dev);
1927 void i915_handle_error(struct drm_device *dev, bool wedged);
1929 extern void intel_irq_init(struct drm_device *dev);
1930 extern void intel_pm_init(struct drm_device *dev);
1931 extern void intel_hpd_init(struct drm_device *dev);
1932 extern void intel_pm_init(struct drm_device *dev);
1934 extern void intel_uncore_sanitize(struct drm_device *dev);
1935 extern void intel_uncore_early_sanitize(struct drm_device *dev);
1936 extern void intel_uncore_init(struct drm_device *dev);
1937 extern void intel_uncore_check_errors(struct drm_device *dev);
1938 extern void intel_uncore_fini(struct drm_device *dev);
1941 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
1944 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
1947 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1948 struct drm_file *file_priv);
1949 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1950 struct drm_file *file_priv);
1951 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1952 struct drm_file *file_priv);
1953 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1954 struct drm_file *file_priv);
1955 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1956 struct drm_file *file_priv);
1957 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1958 struct drm_file *file_priv);
1959 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1960 struct drm_file *file_priv);
1961 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1962 struct drm_file *file_priv);
1963 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1964 struct drm_file *file_priv);
1965 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1966 struct drm_file *file_priv);
1967 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1968 struct drm_file *file_priv);
1969 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1970 struct drm_file *file_priv);
1971 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1972 struct drm_file *file_priv);
1973 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1974 struct drm_file *file);
1975 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1976 struct drm_file *file);
1977 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1978 struct drm_file *file_priv);
1979 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1980 struct drm_file *file_priv);
1981 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1982 struct drm_file *file_priv);
1983 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1984 struct drm_file *file_priv);
1985 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1986 struct drm_file *file_priv);
1987 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1988 struct drm_file *file_priv);
1989 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1990 struct drm_file *file_priv);
1991 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1992 struct drm_file *file_priv);
1993 void i915_gem_load(struct drm_device *dev);
1994 void *i915_gem_object_alloc(struct drm_device *dev);
1995 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1996 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1997 const struct drm_i915_gem_object_ops *ops);
1998 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2000 void i915_gem_free_object(struct drm_gem_object *obj);
2001 void i915_gem_vma_destroy(struct i915_vma *vma);
2003 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2004 struct i915_address_space *vm,
2006 bool map_and_fenceable,
2008 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
2009 int __must_check i915_vma_unbind(struct i915_vma *vma);
2010 int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
2011 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2012 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2013 void i915_gem_lastclose(struct drm_device *dev);
2015 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2016 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2018 struct sg_page_iter sg_iter;
2020 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2021 return sg_page_iter_page(&sg_iter);
2025 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2027 BUG_ON(obj->pages == NULL);
2028 obj->pages_pin_count++;
2030 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2032 BUG_ON(obj->pages_pin_count == 0);
2033 obj->pages_pin_count--;
2036 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2037 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2038 struct intel_ring_buffer *to);
2039 void i915_vma_move_to_active(struct i915_vma *vma,
2040 struct intel_ring_buffer *ring);
2041 int i915_gem_dumb_create(struct drm_file *file_priv,
2042 struct drm_device *dev,
2043 struct drm_mode_create_dumb *args);
2044 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2045 uint32_t handle, uint64_t *offset);
2047 * Returns true if seq1 is later than seq2.
2050 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2052 return (int32_t)(seq1 - seq2) >= 0;
2055 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2056 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2057 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2058 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2061 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2063 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2064 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2065 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2072 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2074 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2075 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2076 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2077 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2081 bool i915_gem_retire_requests(struct drm_device *dev);
2082 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
2083 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2084 bool interruptible);
2085 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2087 return unlikely(atomic_read(&error->reset_counter)
2088 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2091 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2093 return atomic_read(&error->reset_counter) & I915_WEDGED;
2096 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2098 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2101 void i915_gem_reset(struct drm_device *dev);
2102 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2103 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2104 int __must_check i915_gem_init(struct drm_device *dev);
2105 int __must_check i915_gem_init_hw(struct drm_device *dev);
2106 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2107 void i915_gem_init_swizzling(struct drm_device *dev);
2108 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2109 int __must_check i915_gpu_idle(struct drm_device *dev);
2110 int __must_check i915_gem_suspend(struct drm_device *dev);
2111 int __i915_add_request(struct intel_ring_buffer *ring,
2112 struct drm_file *file,
2113 struct drm_i915_gem_object *batch_obj,
2115 #define i915_add_request(ring, seqno) \
2116 __i915_add_request(ring, NULL, NULL, seqno)
2117 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2119 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2121 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2124 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2126 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2128 struct intel_ring_buffer *pipelined);
2129 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2130 int i915_gem_attach_phys_object(struct drm_device *dev,
2131 struct drm_i915_gem_object *obj,
2134 void i915_gem_detach_phys_object(struct drm_device *dev,
2135 struct drm_i915_gem_object *obj);
2136 void i915_gem_free_all_phys_object(struct drm_device *dev);
2137 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2138 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2141 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2143 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2144 int tiling_mode, bool fenced);
2146 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2147 enum i915_cache_level cache_level);
2149 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2150 struct dma_buf *dma_buf);
2152 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2153 struct drm_gem_object *gem_obj, int flags);
2155 void i915_gem_restore_fences(struct drm_device *dev);
2157 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2158 struct i915_address_space *vm);
2159 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2160 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2161 struct i915_address_space *vm);
2162 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2163 struct i915_address_space *vm);
2164 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2165 struct i915_address_space *vm);
2167 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2168 struct i915_address_space *vm);
2170 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2172 /* Some GGTT VM helpers */
2173 #define obj_to_ggtt(obj) \
2174 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2175 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2177 struct i915_address_space *ggtt =
2178 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2182 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2184 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2187 static inline unsigned long
2188 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2190 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2193 static inline unsigned long
2194 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2196 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2199 static inline int __must_check
2200 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2202 bool map_and_fenceable,
2205 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment,
2206 map_and_fenceable, nonblocking);
2209 /* i915_gem_context.c */
2210 int __must_check i915_gem_context_init(struct drm_device *dev);
2211 void i915_gem_context_fini(struct drm_device *dev);
2212 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2213 int i915_switch_context(struct intel_ring_buffer *ring,
2214 struct drm_file *file, int to_id);
2215 void i915_gem_context_free(struct kref *ctx_ref);
2216 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2218 kref_get(&ctx->ref);
2221 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2223 kref_put(&ctx->ref, i915_gem_context_free);
2226 struct i915_ctx_hang_stats * __must_check
2227 i915_gem_context_get_hang_stats(struct drm_device *dev,
2228 struct drm_file *file,
2230 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2231 struct drm_file *file);
2232 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2233 struct drm_file *file);
2235 /* i915_gem_gtt.c */
2236 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
2237 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
2238 struct drm_i915_gem_object *obj,
2239 enum i915_cache_level cache_level);
2240 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
2241 struct drm_i915_gem_object *obj);
2243 void i915_check_and_clear_faults(struct drm_device *dev);
2244 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
2245 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
2246 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2247 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
2248 enum i915_cache_level cache_level);
2249 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
2250 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
2251 void i915_gem_init_global_gtt(struct drm_device *dev);
2252 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
2253 unsigned long mappable_end, unsigned long end);
2254 int i915_gem_gtt_init(struct drm_device *dev);
2255 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2257 if (INTEL_INFO(dev)->gen < 6)
2258 intel_gtt_chipset_flush();
2262 /* i915_gem_evict.c */
2263 int __must_check i915_gem_evict_something(struct drm_device *dev,
2264 struct i915_address_space *vm,
2267 unsigned cache_level,
2270 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2271 int i915_gem_evict_everything(struct drm_device *dev);
2273 /* i915_gem_stolen.c */
2274 int i915_gem_init_stolen(struct drm_device *dev);
2275 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2276 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2277 void i915_gem_cleanup_stolen(struct drm_device *dev);
2278 struct drm_i915_gem_object *
2279 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2280 struct drm_i915_gem_object *
2281 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2285 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2287 /* i915_gem_tiling.c */
2288 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2290 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2292 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2293 obj->tiling_mode != I915_TILING_NONE;
2296 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2297 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2298 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2300 /* i915_gem_debug.c */
2302 int i915_verify_lists(struct drm_device *dev);
2304 #define i915_verify_lists(dev) 0
2307 /* i915_debugfs.c */
2308 int i915_debugfs_init(struct drm_minor *minor);
2309 void i915_debugfs_cleanup(struct drm_minor *minor);
2310 #ifdef CONFIG_DEBUG_FS
2311 void intel_display_crc_init(struct drm_device *dev);
2313 static inline void intel_display_crc_init(struct drm_device *dev) {}
2316 /* i915_gpu_error.c */
2318 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2319 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2320 const struct i915_error_state_file_priv *error);
2321 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2322 size_t count, loff_t pos);
2323 static inline void i915_error_state_buf_release(
2324 struct drm_i915_error_state_buf *eb)
2328 void i915_capture_error_state(struct drm_device *dev);
2329 void i915_error_state_get(struct drm_device *dev,
2330 struct i915_error_state_file_priv *error_priv);
2331 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2332 void i915_destroy_error_state(struct drm_device *dev);
2334 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2335 const char *i915_cache_level_str(int type);
2337 /* i915_suspend.c */
2338 extern int i915_save_state(struct drm_device *dev);
2339 extern int i915_restore_state(struct drm_device *dev);
2342 void i915_save_display_reg(struct drm_device *dev);
2343 void i915_restore_display_reg(struct drm_device *dev);
2346 void i915_setup_sysfs(struct drm_device *dev_priv);
2347 void i915_teardown_sysfs(struct drm_device *dev_priv);
2350 extern int intel_setup_gmbus(struct drm_device *dev);
2351 extern void intel_teardown_gmbus(struct drm_device *dev);
2352 static inline bool intel_gmbus_is_port_valid(unsigned port)
2354 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2357 extern struct i2c_adapter *intel_gmbus_get_adapter(
2358 struct drm_i915_private *dev_priv, unsigned port);
2359 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2360 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2361 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2363 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2365 extern void intel_i2c_reset(struct drm_device *dev);
2367 /* intel_opregion.c */
2368 struct intel_encoder;
2369 extern int intel_opregion_setup(struct drm_device *dev);
2371 extern void intel_opregion_init(struct drm_device *dev);
2372 extern void intel_opregion_fini(struct drm_device *dev);
2373 extern void intel_opregion_asle_intr(struct drm_device *dev);
2374 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2376 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2379 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2380 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2381 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2383 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2388 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2396 extern void intel_register_dsm_handler(void);
2397 extern void intel_unregister_dsm_handler(void);
2399 static inline void intel_register_dsm_handler(void) { return; }
2400 static inline void intel_unregister_dsm_handler(void) { return; }
2401 #endif /* CONFIG_ACPI */
2404 extern void intel_modeset_init_hw(struct drm_device *dev);
2405 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2406 extern void intel_modeset_init(struct drm_device *dev);
2407 extern void intel_modeset_gem_init(struct drm_device *dev);
2408 extern void intel_modeset_cleanup(struct drm_device *dev);
2409 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2410 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2411 bool force_restore);
2412 extern void i915_redisable_vga(struct drm_device *dev);
2413 extern bool intel_fbc_enabled(struct drm_device *dev);
2414 extern void intel_disable_fbc(struct drm_device *dev);
2415 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2416 extern void intel_init_pch_refclk(struct drm_device *dev);
2417 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2418 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2419 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2420 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2421 extern void intel_detect_pch(struct drm_device *dev);
2422 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2423 extern int intel_enable_rc6(const struct drm_device *dev);
2425 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2426 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2427 struct drm_file *file);
2428 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2429 struct drm_file *file);
2432 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2433 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2434 struct intel_overlay_error_state *error);
2436 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2437 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2438 struct drm_device *dev,
2439 struct intel_display_error_state *error);
2441 /* On SNB platform, before reading ring registers forcewake bit
2442 * must be set to prevent GT core from power down and stale values being
2445 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2446 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2448 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2449 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2451 /* intel_sideband.c */
2452 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2453 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2454 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2455 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2456 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2457 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2458 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2459 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2460 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2461 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2462 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2463 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2464 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2465 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2466 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2467 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2468 enum intel_sbi_destination destination);
2469 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2470 enum intel_sbi_destination destination);
2472 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2473 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2475 void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2476 void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2478 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
2479 (((reg) >= 0x2000 && (reg) < 0x4000) ||\
2480 ((reg) >= 0x5000 && (reg) < 0x8000) ||\
2481 ((reg) >= 0xB000 && (reg) < 0x12000) ||\
2482 ((reg) >= 0x2E000 && (reg) < 0x30000))
2484 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
2485 (((reg) >= 0x12000 && (reg) < 0x14000) ||\
2486 ((reg) >= 0x22000 && (reg) < 0x24000) ||\
2487 ((reg) >= 0x30000 && (reg) < 0x40000))
2489 #define FORCEWAKE_RENDER (1 << 0)
2490 #define FORCEWAKE_MEDIA (1 << 1)
2491 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2494 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2495 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2497 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2498 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2499 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2500 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2502 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2503 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2504 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2505 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2507 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2508 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2510 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2511 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2513 /* "Broadcast RGB" property */
2514 #define INTEL_BROADCAST_RGB_AUTO 0
2515 #define INTEL_BROADCAST_RGB_FULL 1
2516 #define INTEL_BROADCAST_RGB_LIMITED 2
2518 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2520 if (HAS_PCH_SPLIT(dev))
2521 return CPU_VGACNTRL;
2522 else if (IS_VALLEYVIEW(dev))
2523 return VLV_VGACNTRL;
2528 static inline void __user *to_user_ptr(u64 address)
2530 return (void __user *)(uintptr_t)address;
2533 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2535 unsigned long j = msecs_to_jiffies(m);
2537 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2540 static inline unsigned long
2541 timespec_to_jiffies_timeout(const struct timespec *value)
2543 unsigned long j = timespec_to_jiffies(value);
2545 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);